code: def _translate_src_register_oprnd(self, operand):
          
          reg_info = self._arch_alias_mapper.get(operand.name, None)
  
          if reg_info:
              var_base_name, offset = reg_info
  
              var_size = self._arch_regs_size[var_base_name]
          else:
              var_base_name = operand.name
              var_size = operand.size
  
          var_name = self._get_var_name(var_base_name)
          ret_val = self.make_bitvec(var_size, var_name)
  
          if reg_info:
              ret_val = smtfunction.extract(ret_val, offset, operand.size)
  
          return ret_val
docs: Translate source register operand to SMT expr.