docs: def renderContent(self):
          """
          Walk from outputs to inputs
          for each public signal register port of wrap node if required
          lazy load all operator and statement nodes for signals
          """
          stm = self.stm
          portCtx = self.portCtx
          # for each inputs and outputs render expression trees
  
          # walk statements and render muxs and memories
          for o in stm._outputs:
              if not self.isVirtual:
                  portCtx.register(o, PortType.OUTPUT)
  
          canHaveRamPorts = isinstance(stm, IfContainer) and arr_any(
              chain(stm._inputs, stm._outputs),
              lambda s: isinstance(s._dtype, HArray))
          # render RAM ports
          consumedOutputs = set()
          if canHaveRamPorts:
              for pType, memSig, addrSig, enSig, io in detectRamPorts(stm, stm.cond):
                  if pType == RAM_READ:
                      self.createRamReadNode(memSig, enSig, addrSig,
                                             io, True)
                      consumedOutputs.add(io)
  
                  elif pType == RAM_WRITE:
                      self.createRamWriteNode(memSig, enSig, addrSig,
                                              io, True)
                      consumedOutputs.add(memSig)
  
                  else:
                      raise TypeError()
  
          for o in stm._outputs:
              if o not in consumedOutputs:
                  self.renderForSignal(stm, o, True)
  
          if not self.isVirtual:
              self.netCtxs.applyConnections(self.node)