docs: def detectRamPorts(stm: IfContainer, current_en: RtlSignalBase):
      """
      Detect RAM ports in If statement
  
      :param stm: statement to detect the ram ports in
      :param current_en: curent en/clk signal
      """
      if stm.ifFalse or stm.elIfs:
          return
      for _stm in stm.ifTrue:
          if isinstance(_stm, IfContainer):
              yield from detectRamPorts(_stm, _stm.cond & current_en)
          elif isinstance(_stm, Assignment):
              if isinstance(_stm.dst._dtype, HArray):
                  assert len(_stm.indexes) == 1, "one address per RAM port"
                  w_addr = _stm.indexes[0]
                  mem = _stm.dst
                  yield (RAM_WRITE, mem, w_addr, current_en, _stm.src)
              elif _stm.src.hidden and len(_stm.src.drivers) == 1:
                  op = _stm.src.drivers[0]
                  mem = op.operands[0]
                  if isinstance(mem._dtype, HArray) and op.operator == AllOps.INDEX:
                      r_addr = op.operands[1]
                      if _stm.indexes:
                          raise NotImplementedError()
                      yield (RAM_READ, mem, r_addr, current_en, _stm.dst)