docs: def update_reg(self, addr, mask, new_val):
          """ Update register at 'addr', replace the bits masked out by 'mask'
          with new_val. new_val is shifted left to match the LSB of 'mask'
  
          Returns just-written value of register.
          """
          shift = _mask_to_shift(mask)
          val = self.read_reg(addr)
          val &= ~mask
          val |= (new_val << shift) & mask
          self.write_reg(addr, val)
  
          return val