docs: def load(self, addr, size=None, condition=None, fallback=None, add_constraints=None, action=None, endness=None,
               inspect=True, disable_actions=False, ret_on_segv=False):
          """
          Loads size bytes from dst.
  
          :param dst:             The address to load from.
          :param size:            The size (in bytes) of the load.
          :param condition:       A claripy expression representing a condition for a conditional load.
          :param fallback:        A fallback value if the condition ends up being False.
          :param add_constraints: Add constraints resulting from the merge (default: True).
          :param action:          A SimActionData to fill out with the constraints.
          :param endness:         The endness to load with.
          :param bool inspect:    Whether this store should trigger SimInspect breakpoints or not.
          :param bool disable_actions: Whether this store should avoid creating SimActions or not. When set to False,
                                       state options are respected.
          :param bool ret_on_segv: Whether returns the memory that is already loaded before a segmentation fault is triggered. The default is False.
  
          There are a few possible return values. If no condition or fallback are passed in,
          then the return is the bytes at the address, in the form of a claripy expression.
          For example:
  
              <A BVV(0x41, 32)>
  
          On the other hand, if a condition and fallback are provided, the value is conditional:
  
              <A If(condition, BVV(0x41, 32), fallback)>
          """
  
          _inspect = inspect and self.state.supports_inspect
  
          add_constraints = True if add_constraints is None else add_constraints
  
          addr_e = _raw_ast(addr)
          size_e = _raw_ast(size)
          condition_e = _raw_ast(condition)
          fallback_e = _raw_ast(fallback)
  
          if isinstance(addr, str):
              named_addr, named_size = self._resolve_location_name(addr)
              addr = named_addr
              addr_e = addr
              if size is None:
                  size = named_size
                  size_e = size
  
          if size is None:
              size = self.state.arch.bits // self.state.arch.byte_width
              size_e = size
  
          if _inspect:
              if self.category == 'reg':
                  self.state._inspect('reg_read', BP_BEFORE, reg_read_offset=addr_e, reg_read_length=size_e,
                                      reg_read_condition=condition_e
                                      )
                  addr_e = self.state._inspect_getattr("reg_read_offset", addr_e)
                  size_e = self.state._inspect_getattr("reg_read_length", size_e)
                  condition_e = self.state._inspect_getattr("reg_read_condition", condition_e)
  
              elif self.category == 'mem':
                  self.state._inspect('mem_read', BP_BEFORE, mem_read_address=addr_e, mem_read_length=size_e,
                                      mem_read_condition=condition_e
                                      )
                  addr_e = self.state._inspect_getattr("mem_read_address", addr_e)
                  size_e = self.state._inspect_getattr("mem_read_length", size_e)
                  condition_e = self.state._inspect_getattr("mem_read_condition", condition_e)
  
          if (
              o.UNDER_CONSTRAINED_SYMEXEC in self.state.options and
              isinstance(addr_e, claripy.ast.Base) and
              addr_e.uninitialized
          ):
              self._constrain_underconstrained_index(addr_e)
  
          try:
              a,r,c = self._load(addr_e, size_e, condition=condition_e, fallback=fallback_e, inspect=_inspect,
                                 events=not disable_actions, ret_on_segv=ret_on_segv)
          except SimSegfaultError as e:
              e.original_addr = addr_e
              raise
          if _inspect:
              # tracer uses address_concretization_add_constraints to overwrite the add_constraints value
              # TODO: Make this logic less arbitrary
              add_constraints = self.state._inspect_getattr('address_concretization_add_constraints', add_constraints)
          if add_constraints and c:
              self.state.add_constraints(*c)
  
          if (self.category == 'mem' and o.SIMPLIFY_MEMORY_READS in self.state.options) or \
             (self.category == 'reg' and o.SIMPLIFY_REGISTER_READS in self.state.options):  # pylint:disable=too-many-boolean-expressions
              l.debug("simplifying %s read...", self.category)
              r = self.state.simplify(r)
  
          if not self._abstract_backer and \
                  o.UNINITIALIZED_ACCESS_AWARENESS in self.state.options and \
                  self.state.uninitialized_access_handler is not None and \
                  (r.op == 'Reverse' or r.op == 'BVV') and \
                  getattr(r._model_vsa, 'uninitialized', False):
              normalized_addresses = self.normalize_address(addr)
              if len(normalized_addresses) > 0 and type(normalized_addresses[0]) is AddressWrapper:
                  normalized_addresses = [ (aw.region, aw.address) for aw in normalized_addresses ]
              self.state.uninitialized_access_handler(self.category, normalized_addresses, size, r, self.state.scratch.bbl_addr, self.state.scratch.stmt_idx)
  
          # the endianess
          endness = self.endness if endness is None else endness
          if endness == "Iend_LE":
              r = r.reversed
  
          if _inspect:
              if self.category == 'mem':
                  self.state._inspect('mem_read', BP_AFTER, mem_read_expr=r)
                  r = self.state._inspect_getattr("mem_read_expr", r)
  
              elif self.category == 'reg':
                  self.state._inspect('reg_read', BP_AFTER, reg_read_expr=r)
                  r = self.state._inspect_getattr("reg_read_expr", r)
  
          if not disable_actions:
              if o.AST_DEPS in self.state.options and self.category == 'reg':
                  r = SimActionObject(r, reg_deps=frozenset((addr,)))
  
              if o.AUTO_REFS in self.state.options and action is None:
                  ref_size = size * self.state.arch.byte_width if size is not None else r.size()
                  region_type = self.category
                  if region_type == 'file':
                      # Special handling for files to keep compatibility
                      # We may use some refactoring later
                      region_type = self.id
                  action = SimActionData(self.state, region_type, 'read', addr=addr, data=r, size=ref_size,
                                         condition=condition, fallback=fallback)
                  self.state.history.add_action(action)
  
              if action is not None:
                  action.actual_addrs = a
                  action.added_constraints = action._make_object(self.state.solver.And(*c)
                                                                 if len(c) > 0 else self.state.solver.true)
  
          return r