A modern application specific integrated circuit (ASIC) requires a significant amount of random access memory (RAM) to operate satisfactorily. In an example, for networking applications, the memory needs to be accessed at a high rate with low latency. Often, a single ASIC chip needs to read and write independently to multiple memory elements. One present solution to the need for ASIC memory access is to use dynamic RAM (DRAM) embedded in a logic process, so-called embedded DRAM or eDRAM, to locate memory near the logic that accesses it and to connect the memory to the logic using a wide bus. eDRAM memory is dense and, being on the same die with the ASIC logic, allows dense, high-speed interconnections between the memory and the logic. eDRAM also avoids the slow, narrow, power-hungry interface entailed in connecting a logic die to separate DRAM dice through either packages and a printed circuit board (PCB) or in a side-by-side multi-chip module (MCM).
Embedded DRAM however presents a number of challenges. The additional processing steps to embed the memory with the logic both increases manufacturing costs and reduces yield. The embedded DRAM is not as dense as it is in a dedicated DRAM. Lastly, embedded DRAM technology is not widely available.
In integrated circuit (IC) technology, a circuit almost always performs better and costs less when it is constructed using a semiconductor manufacturing process that is optimal for the particular function performed by the circuit, so partitioning the system into separate logic and DRAM integrated circuits is attractive. The high parasitics of the connection between separate dice on a PCB or even an MCM substrate might be alleviated by stacking one die on the other. However, until recently, stacked dice have almost always been connected by wire bonds along their respective perimeters, which greatly limit the number and the quality of the connections. For many communication system and networking applications, multiple wide logic to memory buses with low parasitics are desired.
Recently, interconnect technologies known as fine pitch through-silicon via (TSV) and metal-to-metal bonds have been developed to enable the fabrication of stacked dice having an area array interconnect in a “through-silicon stacking” (TSS) architecture. An area array interconnect using TSVs and metal-to-metal bonds provide physically short, relatively low parasitic connections, to provide what can be referred to as, “I/O-less on-circuit access to off-circuit technology.” Such through-silicon stacking allows the consideration of partitioning an IC device into separate logic and DRAM dice.
In general, it is often the situation that an application specific integrated circuit (ASIC) device will use more area than a DRAM circuit. As a result, stacking the smaller DRAM on a larger ASIC and arranging a heat sink on top of the stack is inefficient for transferring heat generated in the ASIC through the DRAM to the heat sink. While thermally conductive materials are known for filling imperfections in mating surfaces of integrated circuits and heat sinks, these thermally conductive materials are not nearly as efficient at transferring heat as semiconductor materials and metals over the thickness or height of an integrated circuit.
Moreover, data processing speed and efficiency of many ASICs and ASIC-based assemblies, depend in large part, on how internally generated heat is controlled and removed from the circuits. Existing heat sinks and heat exchangers do not, in all instances, effectively control and remove internally generated heat, especially in the context of stacked dies that produce gaps between an active surface of an ASIC and a heat sink.
USPTO Backgrounds
USPTO Backgrounds