The present invention relates to a BiCMOS logic circuit, and more particularly to a full-swing BiCMOS driver which has fast switching characteristics with low power consumption.
FIG. 1 shows an inverter of conventional BiCMOS logic circuits. In FIG. 1, a pull-up controlling part 1 pulls an output up to high level when an input signals is in a low level state and includes each PMOS and NMOS transistor P1 and N1 of which drains are connected with each other. Also, a pull-down controlling part 2 pulls the output down to low level when the output signal is in high level state and includes each NMOS transistor N2 and N3, in which the gate of the NMOS transistor N2 is connected to an input terminal VIN and the drain of the NMOS transistor N2 is connected to an output terminal VOUT.
In the pull-down controlling part 2, the NMOS transistor N3 is connected to the source of the NMOS transistor N2 and the gate of the NMOS transistor N3 is connected to the base of a transistor Q1 in an output driving part 3, so that when a low level signal is applied to the input terminal VIN, the NMOS transistor N3 is turned on by a high level potential applied to the base of the transistor Q1 in the output driving part 3.
The output driving part 3 for providing an output signal according to signals of the pull-up and pull-down controlling parts 1 and 2 includes the transistor Q1 and another transistor Q2 which are interconnected, being turned on respectively by driving the PMOS transistor P1 in the full-up controlling part 1 and the NMOS transistor N2 in the pull-down controlling part 2.
In this conventional BiCMOS inverter, when a high level signal is applied to the input terminal VIN, the PMOS transistor P1 in the pull-up controlling part 1 is turned off and the NMOS transistor N1 is turned on. Thus, charge stored in the base of transistor Q1 is discharged toward the output terminal VOUT. Also, if the PMOS transistor P1 is turned off, the drain of the PMOS transistor P1 becomes a low level state and the transistor Q1 is turned off, so a low level signal is provided from the output terminal VOUT.
On the other hand, the NMOS transistor N2 in the pull-down controlling part 2 is turned on by the high level signal applied to the input terminal VIN and then the transistor Q2 is turned on. Thus, the output terminal VOUT provides the low level signal corresponding to a collector-to-emitter saturation voltage VCE of the transistor Q2.
By contrast, if a low level signal is applied to the input terminal VIN, the PMOS transistor P1 in the pull-up controlling part 1 is turned on, while the NMOS transistor N1 is turned off. Thus, the drain of the PMOS transistor P1 becomes a high level state thereby turning on the transistor Q1 in the output driving part 3.
On the other hand, the NMOS transistor N2 is turned off since the input signal is low and then the transistor Q2 in the output driving part 3 is turned off. Also, the charge stored in the base of the transistor Q2 is discharged toward the ground since the NMOS transistor N3 is turned on by the high level the drain in the PMOS transistor P1. Thus, the output terminal VOUT provides a high level signal but this high level signal corresponds to the level diminished by a base-to-emitter voltage VBE from a supply voltage VDD.
In this conventional BiCMOS inverter, the high level output corresponds to that lowered by the base-to-emitter voltage VBE from the supply voltage VDD while the low level output corresponds to the collect-emitter voltage VCE. Thus, this inverter can't provide the full-swing signal. In order to solve this problem, a CMOS inverter was added to the conventional BiCMOS inverter to achieve the full-swing of the output voltage.
FIG. 2 shows the conventional full-swing invert. in FIG. 2, the inverter I1 replaces pull-up controlling part 1 of a conventional BiCMOS inverter and another inverter I2 is located between the input and output terminals VIN and VOUT in order to provide the full-swing signal of the output voltage.
Accordingly, if a low level signal is applied to the input terminal VIN, the low level signal is inverted to a high level by the inverter I2 and such a high level signal is provided to the output terminal VOUT. By contrast, if a high level signal is applied to the input terminal VIN, a low level signal inverted by the inverter I2 is provided. This circuit provides the full-swing signal but additional power consumption is also required since current flows from the supply voltage VDD to ground during the switching time of the inverter I2.
USPTO Backgrounds
USPTO Backgrounds