My invention relates to a phase locked loop circuit, and particularly to a phase locked loop circuit that synchronizes a voltage controlled oscillator with a reference oscillator relatively quickly.
Voltage controlled and reference oscillators are used with phase locked loop circuits for various applications, such as a frequency synthesizer for radio and electronic equipment. In such equipment, particularly multichannel radio equipment, it is desirable or necessary that the frequency or channel of the radio be changed by programming information. Such programming information may and frequently does cause prior art phase locked loops to lose synchronization, with the result that a voltage controlled oscillator may wander over a wide frequency range for a long time before synchronization is restored.
Prior art phase locked loops use a phase detector that samples a ramp voltage produced by a ramp generator and started by each pulse from the reference oscillator. This sample is taken in response to each pulse produced by the voltage controlled oscillator. (The ramp voltage is then reset to await the next start.) The samples are used in a feedback arrangement to correct the frequency of the voltage controlled oscillator. The phase locked loop is locked when the voltage of the ramp at the sample time coincides with the voltage required to keep the voltage controlled oscillator frequency synchronized with the reference oscillator frequency. Because of the negative feedback arrangement of the loop, the loop is self-correcting so that it maintains the time or phase of the voltage controlled oscillator signals or pulses synchronized with the reference oscillator signals or pulses.
Such a prior art sample and hold phase detector is versatile, in that the loop gain and hence the bandwidth and frequency switching speed can be controlled by adjusting the slope of the ramp voltage. This slope effectively sets the gain of the phase detector. If relatively high gain is needed, the ramp voltage can be made steep. However, such a steep ramp reaches the maximum supply voltage available, and then becomes constant. In many cases, a higher voltage is desired or needed to correct the frequency of the voltage controlled oscillator. This is an undesired condition that causes loss of synchronization, as will be explained. This limitation on the maximum voltage available results in a relatively long time to achieve synchronization where programmed inputs create a large difference between the phase of voltage controlled and reference oscillator signals or pulses. In some applications, such a relatively long time may not be acceptable or permissible.
USPTO Backgrounds
USPTO Backgrounds