Japanese Patent Application Laid-Open Publication (Translation of PCT Application) No. 2000-506313 (Patent Document 1) describes technology for providing a switching element which achieves both a low on-resistance and a high withstand voltage. Specifically, Patent Document 1 describes a structure for cascode connection between a junction FET (Junction Field Effect Transistor) formed of silicon carbide (SiC) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed of silicon (Si).
Japanese Patent Application Laid-Open Publication No. 2008-198735 (Patent Document 2) describes a structure for serial connection between an FET formed of SiC and a diode formed of Si in order to provide an element with a low on-voltage and a high withstand voltage.
Japanese Patent Application Laid-Open Publication No. 2002-208673 (Patent Document 3) describes structure in which a switching element and a diode are stacked interposing a flat-plate connection terminal in order to reduce the area of a power module.
Japanese Patent Application Laid-Open Publication No. 2010-206100 (Patent Document 4) describes a technology in which erroneous breakthrough is prevented by increasing a threshold voltage of a normally-off-type junction FET formed of SiC. Specifically, a junction FET and a MOSFET are disposed on a SiC substrate, and the MOSFET is diode-connected to the gate electrode of the junction FET.
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USPTO Backgrounds