Integrated circuit array sensors are difficult to test in production. The desired result is that each sensing site (pixel) should be responsive to the anticipated radiation and should be capable of storing an analogue charge packet for a suitable integration period. This charge packet should then be readable by activating word-lines to enable a row of pixels to be sensed via bit-lines which connect the pixels to sense amplifiers or to other readout mechanisms at the edge of the sensing array. A typical architecture has horizontal scan-circuit, which controls the read-out of analogue switches or sensors, connected to an output amplifier and buffer.
A complete optical test is awkward to perform when the integrated circuits are in wafer form. It is more convenient to perform this test once the circuits have been separated and packaged. However, it is economically desirable only to package good circuits or those circuits which are most likely to pass the final test. It is possible to assess circuits in the wafer by a preliminary electrical test of the array. This test may include writing charge packets into pixel locations and then executing sensing procedures to determine whether each pixel has successfully stored a packet and whether the word and bit-line mechanisms can successfully access each location. Unfortunately, this can be a long procedure and it is made more difficult if the test includes the analog characteristics of each pixel.
Both the final optical test and the on-wafer electrical test can require specialized test equipment and occupy test times longer than those associated with conventional digital integrated circuit production.
USPTO Backgrounds
USPTO Backgrounds