1. Field of the Invention
The present invention relates to an etching gas composition for etching silicon oxide and to a method of etching silicon oxide using the same, and more particularly, to an improved etching gas composition including novel combinations of components enabling the manufacture of a contact hole of a semiconductor device, said hole having a high aspect ratio and a good vertical profile, and to a method of etching silicon oxide using said improved etching gas composition.
2. Description of the Related Art
Recently, as information media such as computers have become widely spread, semiconductor devices for such specialized applications have also rapidly progressed. From a viewpoint of the function of the semiconductor device, a rapid operating velocity and a large capacity are required. In order to satisfy these requirements, manufacturing methods for semiconductor devices have been developed to improve such characteristics as integration degree, reliability, response time, etc. In order to increase the integration degree, a cell size should be reduced, and the size and margin of all of the patterns formed on a substrate also should be reduced. On the other hand, with conventional etching techniques, the aspect ratio of each member of the device (vertical size of the device with respect to the horizontal size thereof) is increased.
Accordingly, the formation of a contact hole having a high aspect ratio using conventional etching becomes gradually diverse and more difficult. Some methods and characteristics for the formation of the contact hole using conventional approaches have been reported as follows.
Japanese Patent Laid-Open No. Hei 11-330057 discloses a method of etching an oxide layer by utilizing an etching gas of C4F8 or C5F8 while adding CH2F2 and CO gas for promoting an etching reaction. According to this method, the flow rate of C4F8 or C5F8 gas is limited to a small amount in order to effectively etch a contact hole having a low ILD step and a contact hole having a high ILD step simultaneously.
U.S. Pat. No. 6,010,968 (issued to Yang et al.) discloses a method of etching a multi-layered contact hole by utilizing Ar/CO/C4F8/CH2F2 in a ratio of 3:4:12:80 as a plasma etching gas. Silicon nitride and silicon oxide are selectively etched by utilizing the etching gas, however, silicon or silicide is not etched.
Japanese Patent Laid-open No. Hei 11-340207 discloses a method of etching a contact hole of a nitride layer by flowing Ar/C4F8/CH2F2 gas within a treating bath. Through this method, a carbon film is formed at the shoulder portion of an exposed SiNx layer within the contact hole, and a deposition of carbon at the bottom portion of the contact hole is prevented. Accordingly, the damage on the SiNx film can be prevented and a contact hole having a high aspect ratio can be formed.
U.S. Pat. No. 5,429,710 discloses a method of etching a contact hole by utilizing C4F8/CH2F2 gas. According to this method, re-sputtering or re-deposition onto a sidewall of a contact hole of aluminum from an underlying aluminum-based material layer can be prevented during an etching of an insulating layer made of silicon compound.
Besides the above-described methods, various other etching methods for the formation of a contact hole have been reported. Research and development toward overcoming a resolution limit in order to reduce the size of CD (critical dimension) as a design rule decreases also are continuously progressing. Recently, photoresist wherein solubility with respect to an aqueous solution changes by a light having a DUV (deep ultraviolet) wavelength is becoming widely used instead of photoresist wherein solubility changes by a light having an i-line wavelength. When employing the photoresist which reacts by the light having the DUV wavelength, the resolution can be improved. However, the thickness of the photoresist should be reduced. Owing to the thin photoresist mask, a selectivity margin with respect to the photoresist is insufficient during an etching of a contact hole, resulting in a problem of a wide top CD of the contact hole occurring. This wide top CD induces an insufficient ILD margin between the contact holes or an insufficient separation between the contact holes.
FIGS. 1A & 1B are cross-sectional views of a photoresist pattern and an etched oxide layer after implementing an etching of an underlying silicon oxide layer by utilizing the photoresist pattern as a mask according to the conventional method.
Referring to FIG. 1A, a silicon oxide layer 110 is formed by depositing an oxide compound to a thickness of about 20,000-30,000 Å on a silicon substrate 100. Then, photoresist is deposited on the silicon oxide layer 110, and a common photolithography is implemented to form a photoresist pattern 122 having a CD of about 250 nm and a thickness of about 6500 Å.
Referring to FIG. 1B. a plasma enhanced dry etching is implemented by utilizing the photoresist pattern 122 as an etching mask to form an oxide layer pattern 112 having a contact hole 125 wherein the aspect ratio is about 8:1 to 12:1.
The thickness of the remaining photoresist pattern is 1000 Å or less. At the top portion of the contact hole 125, the photoresist has been lost and the CD is enlarged. It is found that the top CD of an underlying oxide layer also is enlarged as well as the photoresist pattern 122.
Owing to the phenomena of the enlargement of the top CD, a sufficient separation between adjacent contact holes cannot be accomplished, and this induces an insufficient ILD margin and defects.
In order to solve the above-described problems, a process utilizing a selectivity of a hard mask such as polysilicon, TiN, SiN, etc. has been developed. This method is designed for reducing the loss of the photoresist through forming a hard mask under the photoresist layer, the hard mask having a high etching selectivity with respect to a silicon oxide layer. Through the application of the hard mask, the loss of the photoresist can be somewhat reduced; however, additional deposition and etching steps for the hard mask complicate the manufacturing process of a semiconductor device. In addition, the improvement on the selectivity of the photoresist has a limit and so a remarkably large improvement could not be accomplished using this approach. Ultimately, an application of this method for mass production is not recommended when considering the minimal beneficial effect obtainable as compared with the additional problems of increases of particles and the number of process steps.
Another method recently developed is a polymer enhanced advance contact etching (PEACE) process. By this method, an underlying layer is etched to some degree by utilizing a photoresist pattern and, then, a polymer is deposited to form a thin polymer layer. The etching is implemented again to some degree and, then, the polymer is deposited again. This etching and deposition process is repeated to complete the etching process. After implementing the deposition of the polymer, the polymer layer formed at the bottom portion of the underlying layer is thinner than that formed at the side portion thereof. Through this characteristic, the etching characteristic of the vertical direction can be improved. However, this process must be implemented within a specific equipment. In addition, the process stability is still questionable due to an implementation of the multi-step process.
In still another method, a polymer rich process is utilized to increase the selectivity of photoresist with respect to a silicon oxide layer. This method is applicable during implementing an etching process for forming a self aligned contact (SAC) structure to prevent damage onto a shoulder portion of a spacer. By this method, polymer remains during implementing an etching process to form a contact hole in order to form a slope at the side wall of the contact hole. With this approach, too, however, some problems are generated as follows. Through this method, undesirable slope is greatly generated to induce a reactive ion etching lag (RIE-lag) phenomenon. Also, an etch stopping phenomenon also occurs through a plugging of the hole by the polymer before completing the etching to a desired depth. The RIE-lag means that an etching difference results between contact holes having different sizes when implementing the formation process of the contact hole within a wafer.\
These and other problems with and limitations of the prior art etching processes are overcome in whole or in part by the etching gas compositions and methods of the present invention.
USPTO Backgrounds
USPTO Backgrounds