FIGS. 1-4 (Prior Art) illustrate various examples of prior art clock input filter circuits. The circuit of FIG. 1 (see U.S. Pat. No. 5,650,739 for further details) involves analog circuitry including a pair of comparators. This circuit is fairly large when realized in integrated circuit form, consumes a substantial amount of static power, and involves an external threshold voltage generator. The circuit of FIG. 2 (see U.S. Pat. No. 6,507,221 for further details) involves a pair of delay circuits and digital Schmitt triggers rather than the delay circuits and analog comparators of FIG. 1, but the circuit of FIG. 2 involves an intercoupling between the outputs of the Schmitt triggers and the delay circuit supplying the other Schmitt trigger. The circuit of figure (see U.S. Pat. No. 6,535,057 for further details) has only a single programmable delay line that supplies the input signals to the AND and BAND gates. Similarly, the circuit of FIG. 4 (see U.S. Pat. No. 6,535,057 for further details) involves only a single delay circuit DELBUF. None of the circuits of FIGS. 1-4 is readily programmable to adjust the duty cycle of the output signal. A more versatile and processor-configurable clock input filter circuit having low static power consumption and having a duty cycle adjust capability is desired.
USPTO Backgrounds
USPTO Backgrounds