There is a constant demand to improve the performance of a Metal-oxide-semiconductor field effect transistor (MOSFET) which typically involves faster speeds and higher reliability. The speed of the device is usually governed by the width of the gate electrode that is also referred to as the gate length and which is typically one of the smallest dimensions in the device. The critical dimension (CD) or gate length is being reduced in each successive technology generation. The 130 nm technology node has gate lengths from about 100 nm to about 130 nm. For the 100 nm node that is currently being implemented in manufacturing, gate lengths as small as 60 or 70 nm are being produced. One shortcoming in state of the art lithography processes is that they are incapable of controllably printing features in photoresist smaller than about 100 nm. Many semiconductor manufacturers have overcome this problem using a trimming process which laterally shrinks the photoresist line with an etch step.
MOSFETs are typically made by first defining active areas in a substrate 10 by forming isolation regions 12 consisting of insulating material like silicon dioxide as shown in FIG. 1a. Isolation regions can be generated by local oxidation of silicon (LOCOS) or by a shallow trench isolation (STI) technique that was used to form isolation regions 12 depicted in the drawing. A thin gate oxide layer 14 is grown over the substrate between the isolation regions 12 and then a gate electrode material 15 such as polysilicon is deposited on the gate oxide. Next a hardmask 16 is deposited on gate electrode layer 15. Optionally, an anti-reflective coating (ARC) 17 is coated on the hardmask 16 in order to improve process latitude during a subsequent photoresist patterning step. A photoresist is spin coated to provide a photoresist layer 18 and is patterned using conventional methods to form a line having a width L1 in FIG. 1a. Photoresist 18 then serves as an etch mask for etching the pattern through ARC 17.
Frequently, L1 is not narrow enough to meet the requirements for a fast transistor speed. Therefore, prior art methods usually include a resist trimming step in which a plasma etch is used to laterally shrink dimension L1 to a smaller size L2 shown in FIG. 1b. The height H1 of photoresist layer 18 decreases to a thickness H2 in the etched photoresist film 18b. Linewidth L2 is transferred into hardmask 16 to give an etched hardmask layer 16a shown in FIG. 1c. 
Referring to FIG. 1d, photoresist 18b and ARC 17a are stripped and linewidth L2 in hardmask 16a is etch transferred through polysilicon 15 and oxide layer 14 to form layers 14a, 15a. Additional processing to fabricate the MOSFET includes forming spacers 24 on the sides of etched polysilicon layer 15a, forming source/drain regions 22 and source/drain extensions 28 to define a channel 30, and forming silicide contact regions 32 as illustrated in FIG. 1e. 
One problem associated with trimming photoresist 18 is that shortening occurs at line ends which can degrade device performance. A cross sectional view in FIG. 2a is of a line end from an angle perpendicular to a long side of the line. Because of imperfections in the lithography process to form photoresist line 18, the line is tapered near the end represented by 18a. There is a region with length S1 near line end 18a where the thickness is less than H1. During the photoresist trimming step that shrinks L1 to L2 and H1 to H2 in FIG. 1b, the region having length S1 near line end 18a does not offer as much resistance to the etch as the remainder of line 18 and therefore the line 18 is shortened by a distance S2 as depicted in FIG. 2b. Although the specification is for line end shortening (LES) to be less than three times the distance (L1–L2/2) trimmed from one long side of the line 18b, LES or S2 is often as large as 7 times the trimmed amount, especially for linewidths L1 that are sub-200 nm in size.
Furthermore, the height H2 in FIG. 1b is considerably shorter than the original thickness H1 in line 18 and may not be a good etch mask for pattern transfer into hardmask 16. In some cases as shown in FIG. 2c, only 10 nm or less of photoresist height H3 remains after the hardmask 16 etch. As a result, rough edges at the top of line 18b in FIG. 2b can easily generate grooves in the sidewalls of line 18 that are transferred through ARC 17a into hardmask 16a which is detrimental to device performance. Generally, a 50 to 100 nm thickness H3 in photoresist 18b is desirable in FIG. 1c but for prior art methods this might require coating a thicker photoresist 18 that could dramatically reduce process latitude for forming line 18 in FIGS. 1a and 2a. Therefore, an improved method is needed that enables a larger H2 and H3 and simultaneously reduces the amount of LES (S2).
The top down view in FIG. 3a shows another problem associated with LES. The design in this example which might occur in an SRAM cell calls for a pattern in photoresist line 40 having a width W1 and a line end 40a to be transferred into an underlying polysilicon layer (not shown) that overlaps a contact 42. Because of line end shortening during an etch to trim photoresist line 40 to line 40b having a width W2 and a line end 40c as illustrated in FIG. 3b, line 40b does not overlap contact 42 and an “open” circuit defect is produced after a subsequent etch transfer into the polysilicon layer. Note that the LES distance W3 which is the difference between line end 40a and line end 40c is significantly longer than the dimension (W1–W2/2) that was trimmed from one side of the line 40 to form line 40b. In some cases, mask designers might be able to intentionally add extensions to the line on the mask that will print a longer photoresist line 40. However, in most instances, this correction is not possible because there is not enough room in the mask design to compensate for LES.
Prior art patents offer improvements for trimming photoresist patterns to provide a smaller gate length than can be generated by lithography methods. U.S. Pat. No. 6,121,155 describes a trim etch process whereby a critical dimension (CD) loss saturation point is reached that limits further lateral loss in a photoresist line.
In. U.S. Pat. No. 6,197,687, a photoactive layer is coated above a photoresist layer and both are patterned to provide a gate length that is reduced by a trim etch involving HBr, oxygen, and argon. Since the photoactive layer has an etch rate equal to or less than the photoresist layer, the entire height of the photoresist is retained during the trim etch.
In U.S. Pat. No. 6,283,131, a trim etch, a hardmask etch, a photoresist strip, a cleaning operation, and a gate etch are all performed in the same etch chamber to reduce wafer handling and decrease cycle time. In this case, when a photoresist trimming is required, the trim occurs before etching the hardmask layer. The trim etch employs a gas mixture including HBr, O2, and Ar while the etch through the oxynitride hardmask uses CF4 and Ar.
U.S. Pat. No. 6,204,133 describes a reduced gate length in which spacers are formed on the walls of an opening in a phosphosilicate glass (PPG) layer that has been deposited on a substrate. The spacers are formed by an anisotropic etch of a conformal dielectric layer. A heat treatment diffuses ions from the PPG into the substrate to form lightly doped source/drain regions. Oxide and polysilicon layers are then deposited and patterned by conventional means to form a gate electrode.
Although LES is an important issue in fabricating integrated circuits, there is no prior art that mentions how to minimize the problem through a controllable etch process. A workable method should be readily implemented in manufacturing and should be versatile so that it can be applied to the manufacture of a variety of features including trenches, lines, islands and elongated holes.
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