As miniaturization of elements of integrated circuit semiconductor devices drives the industry, the width and the pitch of an active region have become smaller, thus rendering the use of traditional LOCOS (local oxidation of silicon) isolation techniques problematic. STI is considered a more viable isolation technique than LOCOS because, by its nature, STI creates hardly any bird's beak characteristic of LOCOS, thereby achieving better control of active width at sub-micron feature sizes.
Conventional STI fabrication techniques include forming a pad oxide on an upper surface of a semiconductor substrate, forming a nitride, e.g., silicon nitride, polish stop layer thereon, typically having a thickness of greater than 1,000 Å, forming an opening in the nitride polish stop layer, anisotropically etching to form a trench in the semiconductor substrate, and forming a thermal oxide liner in the trench with insulating material, such as silicon oxide, forming an overburden on the nitride polish stop layer. Planarization is then implemented, as by conducting chemical mechanical polishing (CMP). During subsequent processing, the nitride layer is removed along with the pad oxide followed by formation of active areas, which typically involve masking, ion implantation, and cleaning steps. During such cleaning steps, the top corners of the field oxide are isotropically removed leaving a void or “divot” in the oxide fill.
For example, a conventional STI fabrication technique is illustrated in FIGS. 1 through 4, wherein similar features are denoted by similar reference characters. Adverting to FIG. 1, a pad oxide 11 is formed over an upper surface of a semiconductor substrate 10, and a silicon nitride polish stop layer 12 is formed thereon, typically at a thickness in excess of 1,000 Å. A photomask (not shown) is then used to form an opening through the nitride polish stop layer 12, pad oxide 11, and a trench is formed in the semiconductor substrate 10.
Subsequently, a thermal oxide liner (not shown) is formed in the trench, an insulating material is deposited and planarization implemented, as by CMP, resulting in the intermediate structure illustrated in FIG. 2, the reference character 20 denoting the oxide fill. Similarly, the nitride polish stop layer 12 and pad oxide layer 11 are removed and cleaning steps, which include oxide-consuming HF-based wet steps, are performed on the active regions during the process of doping and gate/sacrificial oxide formation. In current ULSI integration schemes, two and even three different gate oxides are integrated onto a single chip to facilitate different types of transistors. This requires an enhanced oxide etch budget and can exacerbate the divot formation. Such cleaning steps result in the formation of divots 30 as illustrated in FIG. 3.
The STI divots are problematic in various respects. For example, STI divots are responsible for high field edge leakage, particularly with shallow source/drain junctions. As shown in FIG. 4, silicide regions 41 formed on shallow source/drain regions 40 grow steeply downwards, as illustrated by reference character 42, below the junction depth formed at a latter stage resulting in high leakage and shorting. Segregation of dopants, notably boron, at STI field edges reduces the junction depth. Accordingly, after the junctions are silicided, the silicide 42 penetrating into the substrate causes shorting routes and, hence, large leakage occurrence from the source/drain junctions to a well or substrate.
In strained silicon applications, in which a thin silicon (Si) layer is provided on a silicon germanium (SiGe) layer, the potential for formation of STI divots during the STI process exposes the underlying SiGe layer during the process flow. This is highly undesirable as it leads to poor silicide formation, among other issues.
USPTO Backgrounds
USPTO Backgrounds