The present invention generally relates to a dynamic random access memory device and a method for producing the same, and more particularly, to improvements in the layer structure of a dynamic random access memory device and a method for producing such an improved dynamic random access memory device.
A dynamic random access memory (hereinafter simply referred to as a DRAM device) has a number of memory cells. Each memory cell is composed of a memory cell capacitor and a transfer gate transistor. Currently, there has been considerable activity in reduction of the size of a DRAM device. It is required particularly to reduce the size of a memory cell capacitor in order to reduce the size of DRAM devices. It is noted that the area of memory cell capacitors which occupies a semiconductor substrate decreases, capacitance of each memory cell capacitor decreases. The capacitance of the memory cell capacitor depends greatly on the size of a storage electrode of the memory cell, which is paired with an opposed electrode thereof. As the area of the storage capacitor which occupies the semiconductor substrate decreases, the capacitance of the memory cell capacitor decreases considerably. The reduction of the size of the memory cell capacitor, particularly the reduction of the size of the storage electrode causes the following problems in addition to the decrease in capacitance of the memory cell capacitor. First, soft errors due to irradiation of .alpha.-particles increase with a decrease of the capacitance of the memory cell capacitor Secondly, although it is known to make the storage electrode thick so as to increase the side wall area thereof and thereby increase the entire surface area of the storage electrode, it is difficult to obtain a fine pattern because the aspect ratio with respect to bit lines and contact holes increases. Thirdly, neighboring bit lines are located closer, or in other words, a separation distance between the neighboring bit lines decreases. The closer the neighboring bit lines are arranged, the greater the coupling capacitance therebetween.
USPTO Backgrounds
USPTO Backgrounds