1. Field of the Invention
The present invention relates to a semiconductor apparatus, in particular, to a semiconductor apparatus with a plurality of semiconductor devices being built.
2. Description of the Related Art
Recently, as a packaging technology in which miniaturization and high performance of semiconductor apparatuses used in electronic equipment can be realized, a multi stack structure (a multi chip package structure) has been known, in which a plurality of semiconductor devices (e.g. semiconductor chips) are mounted by lamination.
FIG. 4 is a schematic section showing a semiconductor apparatus having a conventional stack structure. In this semiconductor apparatus, a first semiconductor chip 1110 having a relatively large area is fixed onto a wiring board (inter-poser) 1140 by a die bond material 1112, and a second semiconductor chip 1120 is fixed onto the first semiconductor chip 1110 by a die bond material 1122 not so as to interfere with an electrode pad 1113 of the first semiconductor chip 1110.
The electrode pad 1113 formed on the upper surface of the first semiconductor chip 1110 is electrically connected with a pad electrode 1143 formed on the wiring board 1140 by a bonding wire 1114 made of gold wiring or the like. And a pad electrode 1123 on the upper surface of the second semiconductor chip 1120 is electrically connected with the pad electrode 1143 by a bonding wire 1124.
The first semiconductor chip 1110 stacked on the wiring board 1140 and the second semiconductor chip 1120 are sealed by a sealing resin layer 1150. An external connection terminal 1145 electrically connected with the pad electrode 1143 is formed on the underside (undersurface) of the semiconductor chip mounting surface of the wiring board 1140.
A semiconductor apparatus having a stack structure described above, when mounted on a print wiring board and used, can reduce an area for mounting in a planar direction as compared with the case where a plurality of semiconductor devices (semiconductor chips) are arranged on a plane, therefore the semiconductor apparatus can meet the demand for miniaturization and high integration of electronic equipment.
However, in a semiconductor apparatus which adopts a stack structure to achieve such miniaturization and high integration thereof, and in particular, in the case of a semiconductor apparatus which adopts a semiconductor device having a circuit area which consumes more power (heat generating circuit area), there is a concern that a wrong operation might occur or the apparatus be destroyed, if heat release to the outside is insufficient when the temperature of the circuit area abruptly rises.
USPTO Backgrounds
USPTO Backgrounds