1. Field of the Invention
Aspect's of the present invention relate to a non-volatile memory device and a fabrication method. More specifically, aspects of the present invention relates to a non-volatile memory device formed on a glass substrate, and a method for fabricating a non-volatile memory device, and a memory apparatus including a non-volatile memory device.
2. Description of the Related Art
Generally, non-volatile memory devices may be classified into floating-gate memory devices and charge-trapping memory devices. A floating-gate memory device is a device that maintains a memory by using a potential well. A charge-trapping memory device is a device that maintains a memory by trapping charges in a trap region inside a nitride film or a trap region present in an interface between a nitride film and an insulator.
A representative form of the charge-trapping memory device is a device having a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) configuration. A typical SONOS configuration may include a sequential stack of a semiconductor substrate, an ONO configuration, and a gate electrode. The ONO configuration may include a sequential stack of a tunneling oxide film, a nitride film and a blocking oxide film. The tunneling oxide film tunnels electrons into a trap region inside the nitride film or a trap region at an interface of the nitride film. The blocking oxide film blocks charges from moving between the nitride film and the gate electrode. The trap region stores charges. Source/drain regions may be provided in the semiconductor substrate on either side of this stack.
Recently, the creation of a non-volatile memory device on a glass substrate has been investigated. Such a configuration may include a sequential stack of the glass substrate, the ONO configuration, and the gate electrode. The glass substrate may include a protective layer, e.g., a buffer oxide film, thereon to protect the glass substrate. A polysilicon layer may be provided on the protective layer. Source/drain regions may be provided in the polysilicon layer on either side of this stack.
Creation of the polysilicon layer may include crystallizing an amorphous polysilicon layer, e.g., by irradiating the amorphous polysilicon layer with a laser. Thus, surfaces of the polysilicon layers may be rough and non-uniform, which may result in a large leakage current being generated. In other words, a leakage current may be significantly increased due to the non-uniformity and roughness of the surfaces of the polysilicon layer. Therefore, such a non-volatile memory may function abnormally during programming/erasing operations.
USPTO Backgrounds
USPTO Backgrounds