1. Technical Field
Example embodiments relate to a bonding pad structure and a method of fabricating the same. Other example embodiments relate to an electronic device having a bonding pad structure and a method of fabricating the same.
2. Discussion of the Related Art
In recent years, electronic products and communication devices have been scaled-down and/or manufactured to operate with a higher performance. Due to this trend, researchers are looking for various ways to develop higher-performing electronic devices (e.g., a semiconductor chip including the electronic products and the communication devices) and/or decrease the size of the electronic products and the communication devices. In order to decrease the size of the electronic devices (e.g., the semiconductor chip), semiconductor manufacturing techniques have been developed with regard to fine line widths, multi-layered metal interconnection lines and the like.
Semiconductor manufacturing techniques, which use multi-layered metal interconnection lines, have been widely researched and used. The multi-layered metal interconnection lines may be formed of copper (Cu) interconnects having a damascene interconnect structure with low resistivity and/or high reliability in order to increase the performance of the semiconductor chip.
There are limits to decreasing the size of the electronic device using the conventional semiconductor manufacturing techniques for forming fine line widths and the multi-layered metal interconnection lines. In order to decrease the size of the electronic device, the bonding pad pitch may be reduced. The bonding pad may contact a bonding wire that electrically connects the semiconductor chip and a printed circuit board.
A bonding pad structure of the semiconductor device using Cu interconnects has been acknowledged in the art. A bonding pad structure formed of an aluminum layer may be formed on a substrate having the Cu interconnects. According to the conventional art, the Cu interconnects may be used to increase the performance of the electronic device. A plurality of bonding pad structures may be formed at a same level. Because there are limits to reducing the distance between the bonding pads positioned at a same level, there are also limits to reducing the bonding pad pitch. As such, it may be difficult to decrease the two-dimensional area occupied by the bonding pads in the semiconductor chip.
USPTO Backgrounds
USPTO Backgrounds