(a) Field of the Invention
The present invention relates to a synchronous semiconductor memory device having a desired-speed test mode.
(b) Description of the Related Art
A synchronous semiconductor memory device, such as a synchronous DRAM (SDRAM) device, performs a high-speed read/write operation based on a read/write command which is supplied in synchrony with an external clock signal. FIG. 3 shows a conventional SDRAM device in a block diagram. The SDRAM device includes internal clock generator 11, command decoder 12, internal address generator 13, memory cell array 14, row-decoder controller 15, row address decoder 16, column address decoder 17, sense amplifier block 18, data amplifier 19, column-decoder controller 20 and input/output (I/O) block 21.
The internal clock generator 11 receives an external clock signal CLK, to generate an internal clock signal in synchrony with the external clock signal CLK. The command decoder 12 receives external control signals including /RAS (row address strobe), /CAS (column address strobe), /WE (write enable) and /CS (chip select) signals through the control input terminals thereof, to decode the command supplied to the SDRAM, controlling the row-decoder controller 15 and the column-decoder controller 20 based on the decoded command. The symbol “/” disposed before a signal name in this text means that the corresponding signal has an active low level.
The internal address generator 13 generates internal addresses including row address (X) and column address (Y) based on the address signal ADD input through the address terminal, delivering the row address and the column address to the row address decoder 16 and the column address decoder 17, respectively. The memory cell array 14 includes an array of memory cells each storing therein data, a plurality of bit line pairs 24 each extending along the column direction of the memory cell array 14 and connected to the sense amplifier block 18, and a plurality of word lines each extending along the row direction of the memory cell array 14 and connected to the row address decoder 16.
The row-decoder controller 15 controls the row address decoder 16, and activates/inactivates the sense amplifier block 18. The row address decoder 16 selects one of word lines 25 based on the control signal supplied from the row-decoder controller 15 and the row address supplied from the internal address generator 13. The column-decoder controller 20 controls the column address decoder 17, and activates/inactivates the data amplifier 19. The column address decoder 17 selects one of the sense amplifiers in the sense amplifier block 18 based on the control signal supplied from the column-decoder controller 20 and the column address supplied from the internal address generator 13, wherein the selected sense amplifier delivers the output thereof to the data amplifier 19.
Each sense amplifier in the sense amplifier block 18 amplifies a small potential difference between a corresponding bit line pair 24 in the memory cell array 14 up to a specified level. The I/O block 11 is connected to the data amplifier 19 via a bus RWBUS, and delivers/receives read/write data DQ through data terminals.
FIG. 4 shows a timing chart of the SDRAM device of FIG. 3 in a normal operation mode. In a clock cycle C1 of the external clock signal CLK, the command decoder 12 decodes the external control signals including /RAS, /CAS, /WE and CS. It is assumed here that the decoded command is an activating command AC, which indicates selection of one of the word lines specified by the input row address.
In the SDRAM device, the activating command AC allows a signal IRASB delivered from the row-decoder controller 15 to assume a low level. The low level of signal IRASB permits the row address decoder 16 to select one of the word lines 25 corresponding to the row address (X) delivered from the internal address generator 13. The selection of the word line 25 allows the selected memory cells to deliver the own data to the sense amplifiers in the sense amplifier block 18 through the corresponding bit line pairs 24. The sense amplifiers in the sense amplifier block 18 amplify the potential differences between the respective bit line pairs 24 up to a specified level.
In a clock cycle C3, a write command WC is input to the SDRAM device, whereby signal ICASB delivered from the command decoder 12 to the column-decoder controller 20 assumes a low level. The low level of signal ICASB activates the column-decoder controller 20, which controls the column address decoder 17 to select one of the column selection lines 23 corresponding to the column address (Y) delivered from the internal address generator 13. The column selection line thus selected allows the write data DQ input through the data terminal to be stored in the selected memory cell through the I/O block 11, data amplifier 19 and sense amplifier block 18.
In a clock cycle C4, a precharge command PrC is input to the SDRAM device, whereby each of signals IRASB and ICASB assumes a high level. The high level of signal IRASB allows the selected word line 25 to be released from the selection and all the bit line pairs 24 to be equalized. In a clock cycle C6, an activating command AC is again input, the data of memory cells are read out to the bit line pairs 24, and the potential differences are amplified similarly to clock cycle C1.
In a clock cycle C8, a read command RC is input to the SDRAM, whereby signal ICASB assumes a low level. The low level of signal ICASB allows one of the column selection lines 23 to be selected. The selection of the column selection line 23 allows the data read out from the selected memory cell and amplified by the sense amplifier to be delivered to the data amplifier 19, whereby the read data DQ is output through the bus RWBUS, I/O block 21 and data terminals.
The time interval between the input of write command WC and input of precharge command PrC is defined by tDPL which is prescribed in the specification. Similarly, the time interval between the input of precharge command PrC and input of activating command AC is defined by tRP, and the time interval between the input of activating command AC and the input of read command RC is defined by tRCD, which are prescribed in the specification. A SDRAM having a higher operational speed should have smaller values for these time lengths tDPL, tRP and tRCD, and so prescribed in the specification of the SDRAM.
It is generally known that the time interval between the input of write command, read command or precharge command and the completion of the actual write-in, read-out or precharge varies from memory to memory. Thus, the products of SDRAM are subjected to a final product test by using a memory tester as to whether or not the products have a specified performance.
For example, after the precharge command PrC is input to the SDRAM device in clock cycle C4, and if the precharge itself is not completed within the time length tRP, i.e., before clock cycle C6 at which the activating command AC is input whereby the bit line pair are not equalized, then the bit line pair cannot read out the correct data from the selected memory cell. In this respect, the memory tester supplies the precharge command at clock cycle C4 and read command at clock cycle C6, and judges pass or fail of the product based on the fact whether or not the read data coincides with the expected value.
It is to be noted that a read/write command is fed to a SDRAM device in synchrony with the external clock signal CLK and thus a high-speed memory tester generating a high-frequency external clock signal should be used for testing a high-speed SDRAM. For example, if a time length of 15 nanoseconds is prescribed for tPDL, a memory tester having a clock cycle of around 15 nanoseconds should be used for the memory test.
However, a low-speed memory tester generating a long-cycle external clock signal is also used for testing a high-speed SDRAM in some step of the fabrication process thereof. In such a memory test using the low-speed memory tester, the interval of the inputs of commands cannot be set shorter than the clock cycle of the external clock signal, wherein the low-speed memory tester cannot test the high-speed memory device based on specifications of tDPL, tRP and tRCD required for the memory device.
Patent Publication JP-A-11-144497 describes a technique for testing a high-speed memory device by using a low-speed memory tester. In the described technique, the commands such as activating command and precharge command are delayed by the internal circuit to reduce the time interval between these commands and the succeeding read/write command. By controlling the delays of these commands, the memory tester can test the high-speed memory device based on the specification required. In this technique, however, the total test time cannot be reduced because these commands are supplied in synchrony with the low-frequency clock signal and a specified number of commands must be supplied to the memory device for the test.
JP-A-11-306797 describes another technique for testing a high-speed memory device by using a low-speed memory tester. In this technique, an internal clock signal is obtained by doubling the frequency of the external clock signal. When a read/write command is supplied in synchrony with the rise time of the external clock signal, a specified command is generated within the memory device in synchrony with the fall time of the external clock signal, whereby the specified command is supplied in synchrony with the internal clock signal. However, in this technique, the time interval between inputs of the commands cannot be controlled, as a result of which the test cannot be performed according to the desired specification.
USPTO Backgrounds
USPTO Backgrounds