Many of today's dynamic random access MOS memories require potential levels which are more positive or more negative in potential than those of the power supplies used with the memories. One frequently used circuit which provides such a potential consists of two serially connected MOS transistors with a capacitor connected between the common terminal of both and the gate terminal of the first. The source of a third MOS transistor is connected to an output terminal and to the gate of the first transistor. The drain of the third transistor is connected to an input terminal and to an input of a delay gate whose output is connected to the gate of the second transistor. One problem with this circuitry is that the capacitor is completely discharged during a cycle of operation and must be fully recharged within the delay time of the delay gate at the beginning of each cycle. In addition, any load capacitance connected to the output terminal must also be charged through the third transistor and then by the capacitor of the circuit. This requires the third transistor and the circuit capacitor both be relatively large.
USPTO Backgrounds
USPTO Backgrounds