The present disclosure relates to a semiconductor device and an integrated semiconductor device. More particularly, the disclosure relates to a semiconductor device and an integrated semiconductor device having a circuit structure for supporting tests at the time of manufacture.
The integrated semiconductor device such as a multilayer semiconductor device formed by stacking semiconductor chips in multiple layers has a plurality of chip selection terminals for individually controlling the semiconductor chips configured. In many cases, a suitable number of these chip selection terminals are provided to address the layered semiconductor chips. It may thus be necessary to increase the number of chip selection terminals in proportion to a growing number of semiconductor chips in layers.
Techniques have been known to determine which of the multiple chip selection terminals to use on the semiconductor device. On such technique involves providing each of the chips with a unique chip ID and using fuse trimming so as to control the chips individually (e.g., see Japanese Patent Laid-Open No. 2005-122823 (FIG. 3)).
USPTO Backgrounds
USPTO Backgrounds