A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal Oxide Semiconductor Field Effect Transistor (MOSFET) memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages can be applied to program and erase each cell. Programming occurs by using hot electron injection to trap electrons on the floating gate, thereby raising the threshold voltage of the cell. Erasing employs the Fowler-Nordheim tunneling effect to decrease the number of electrons on the floating gate, thereby lowering the threshold voltage of the cell. Upon reading, each programmed cell reads as a binary 0, and each erased level within a cell reads as a binary 1. Flash memory cells provide for nonvolatile data storage.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. One example of this kind of arrangement is a NOR memory configuration.
FIG. 1 illustrates a planar view of a typical configuration of a section of a memory array 100 in a NOR memory configuration. FIG. 1 is not drawn to scale. As shown in FIG. 1, the array 100 is comprised of rows 110 and columns 120 of memory cells. Each of the memory cells is isolated from other memory cells by insulating layers (e.g., a plurality of shallow trench isolation regions (STI) 150.
The control gates of each of the memory cells are coupled together in each of the plurality of rows 110 of memory cells, and form a plurality of word lines 130 that extend along the row direction.
Bit lines extend in the column direction and are coupled to drain regions via drain contacts 160 in an associated column of memory cells 120. The bit lines are coupled to drain regions of memory cells in associated columns of memory cells 120.
A plurality of source lines 140 extend in the row direction and are coupled to the source regions of each of the memory cells in the array of memory cells 100. One source line is coupled to source regions in adjoining rows of memory cells, and as a result, one source region is shared between two memory cells. Similarly, drain regions are shared amongst adjoining rows of memory cells, and as a result, one drain region is shared between two memory cells.
Each of a plurality of source contacts is coupled to the plurality of common source lines 140. Each of the plurality of source contacts 145 is formed in line with the associated common source line to which it is coupled. The source contacts are formed in a column 147, and may be connected with each other. The column 147 is isolated between two STI regions and forms a dead zone in which no memory cells are present.
As shown in FIG. 1, due to current photolithography limitations in forming contact vias, the space required for each of the plurality of source contacts 145 is larger than their associated common source lines 140. As a result, the common source lines 140 need to be widened in the region surrounding their associated source contacts 145. This is to accommodate the wider source contacts 145. As such, word lines on either side of the common source line 140 are bent to accommodate for the increased area for the common source line surrounding an associated source contact 145.
However, as the size of each memory cell and correspondingly, the array 100 itself is reduced, the bending of the word lines to accommodate for the size of the source contacts is limited by current photolithography and chemical vaporization deposition (CVD) techniques. For example, as the size shrinks, it becomes more difficult to form a pronounced bend in each of the plurality of word lines 130 at current pitches achievable by current photolithography techniques. As a result, the size of the overall array 100 is limited by the ability to bend the word lines 130.
Furthermore, the inability to form straight word lines in the region surrounding the source contacts 145 effects the uniformity of cells throughout the array 100. Specifically, the memory cells bordering the column 147 of source contacts that includes the source contacts 145 may have electrical characteristics (erase and program) that are different than those memory cells that do not border a column of source contacts. Threshold voltage and current leakage are specific problems. In particular, a change in the erasing characteristics of a memory cell bordering the column 147 of source contacts can alter the threshold voltage of the cell into the negative region. This causes cell current to always flow (leakage) irrespective of the associated word line potential. As such, memory cells lying on the same bit line as the defective cell will have an erroneous state being read.
USPTO Backgrounds
USPTO Backgrounds