1. Field of the Invention
The present invention relates to a memory cell structure of semiconductor memory device, and particularly to a memory cell structure of semiconductor memory device and fabricating method thereof suitable to a highly integrated memory device by using a line patterning method to overcome a resolution limitation.
2. Description of the Conventional Art
There have been proposed many kinds of cell arrays and structures for a highly integrated semiconductor dynamic random access memory (DRAM) device.
The conventional semiconductor memory device as shown in FIG. 1A and 1B adopts a capacitor under bit line (CUB) structure in which a capacitor is formed in a rectangular active region a on a silicon substrate, and then a bit line is formed. In the figure, the capacitor consists of a node electrode 1a and a plate electrode 1b. The reference signal WL designates word lines. In a memory cell of the CUB structure, the capacitor being below the bit lines, is restricted in its area. In order to obtain the same capacitance in a highly integrated memory device as in an existing one, it is required to increase the topology of the capacitor. However, this results in an increase of the aspect ratio of the bit line contact hole, which is accompanied by a technical difficulty in filling up the contact hole with a conductive layer and in line patterning. therefore, such a memory cell structure is not suitable for a highly integrated memory device.
For 16M or 64M DRAM semiconductor elements, a new cell array and a structure thereof are required. FIGS. 2A and 2B show a semiconductor memory element of a capacitor over bit line (COB) structure as disclosed in U.S. Pat. No. 5,140,389 which designed to increase the capacitance by first forming the bit lines and securing the area for the capacitor above the upper part of the bit lines (BL). The capacitor consists of a node electrode 1a and a plate electrode 1b. In such structure, it is inevitably to design the active region a in a diagonal form so as to make the bit lines (BL) and word lines (WL) cross after the capacitor is formed on the bit line BL. Consequently, there have arisen the problems that the phenomena of a significant reduction or distortion of the pattern can occur upon forming the active region a in a diagonal form, it is difficult to secure space for the active regions and to form an exact pattern, and the packing density is reduced. For this reason, a new memory cell array and structure is required for a very highly integrated memory device (256M or more DRAM).
As shown in FIGS. 3A to 3I, the memory cells for semiconductor memory devices adopting the COB structure as shown in FIG. 2 are fabricating through the following steps:
(a) implanting boron ions B.sup.+ into the substrate 1. forming an oxide film 2 of SiO2 on the substrate 1 in a thickness of about 100 .ANG., and then depositing a nitride film 3 of Si3N4 in a thickness of about 1400 .ANG. by means of a low-pressure chemical vapor deposition (LPCVD); PA1 (c) patterning the active regions a by forming a photoresist layer 4 on the nitride film 3, and then forming a field channel stop layer by implanting boron into the substrate; PA1 (d) removing the patterned photoresist layer 4, removing the nitride film 3 after forming a field oxide film 5, and then growing a gate oxide film 6 in a thickness of about 100 .ANG.; PA1 (e) depositing a doped polysilicon on the substrate 1, forming gate electrodes 7 on the active regions by patterning the polysilicon, and then forming lightly doped source/drain regions which are lightly doped drain (LDD) regions, by means of ion-implantation of phosphorous ions P+; PA1 (f) depositing an insulation film on the surface of the substrate 1, forming side wall spacers on the gate electrode 7, and then forming doped n+ source/drain regions by implanting arsenic ions As+ into the substrate 1; PA1 (g) coating an insulation film 10 on the surface of the semiconductor substrate 1, forming contact holes for bit line contact by exposing a part of each active region of the substrate 1, forming sequentially a polysilicon film 11, a tungsten silicide WSi2 film and an insulation film 13 so as to fill up the contact hole, and forming, after patterning the insulation film 13, the bit lines in the polysilicon film 11 and then the tungsten silicide film 12 using the insulation film 13 as mask; PA1 (h) forming contact holes by exposing a part of the substrate 1 on which the bit lines are formed, depositing and patterning a polysilicon film 14 on the substrate 1 so as to fill up the contact holes and to form the capacitor node electrodes; and PA1 (i) depositing a dielectric film 15 on the node electrodes, forming a plate electrode of the capacitors, and depositing a polysilicon film 16 on the dielectric film 15.
The semiconductor memory device adopting the conventional COB structure as described above, has problems in that because the active pattern is in a diagonal form and has so many corners, a considerable reduction or distortion of pattern can occur, the photolithography process is difficult, and the packing density to be formed in the same area is so los that it is disadvantageous to a high integration device.
USPTO Backgrounds
USPTO Backgrounds