This invention relates, in general, to semiconductor devices, and more particularly, to field effect transistors that are arranged in an array configuration for high power applications.
During operation, power FETs generate a significant amount of heat due to the relatively high current densities that flow through the FETs. The amount of heat that is generated can be enough to damage structures within the array, or at the very least, affect the mean time to failure of the device in a customer's application.
One technique to address this problem is shown in U.S. Pat. No. 5,003,370, which issued to Shunji Kashwagi on Mar. 26, 1992. The solution shown is directed to applications that operate at high frequencies (e.g., 900 MHz), and thus, applications with relatively short "on" times (approximately 1-50 nanoseconds). Simply stated, the solution involves increasing the effective distance between individual cells by configuring the cells in a zigzag pattern so that there is an inactive heatsink between each cell. However, the solution is only practical for devices that have short "on" times (less than 50 nanoseconds) because the heatsinks between each cell can only dissipate a relatively small amount of energy.
Accordingly, a need exists to provide a semiconductor device that has improved energy dissipation capability when the device is operated for a long period of time. It would also be advantageous if the device could be formed without increasing its size so as not to increase its manufacturing complexity or cost.
USPTO Backgrounds
USPTO Backgrounds