The present disclosure relates to semiconductor devices and methods of forming the same.
As the degree of integration of integrated circuit devices increases, wiring structures may be downsized and/or become more dense. In addition, as the critical dimension (CD) of semiconductor devices decreases, the gap distance between neighboring wiring structures may also decrease.
Some semiconductor devices have included stacked structures so as to increase the degree of integration. Conductive structures, such as a transistor, are formed on a semiconductor device, such as a wafer, and an insulation interlayer is formed on the substrate to a sufficient thickness to cover the conductive structures. Wiring structures are formed on the insulation interlayer and are electrically connected to the conductive structures underlying the insulation interlayer. Thus, the wiring structures may include a conductive interconnection penetrating through the insulation interlayer and making contact with the conductive structures, and a metal wiring making contact with the conductive interconnection and transferring external signals to the conductive structures.
The wiring structure may be formed through a photolithography process for forming an opening in an insulation layer and a deposition process for forming the interconnection and the metal wiring in the opening. Recently, wiring structures have been downsized as the reduction of critical dimension and the aspect ratio of the opening has rapidly increased. Thus, void and seam defects have been frequently detected in the photolithography process, and neighboring wirings have been easily brought into contact with each other to thereby generate bridge defects and electric shorts.
For the above reasons, some interconnections have been firstly formed in the opening and an additional insulation layer has been formed on the interconnection in such a way that the interconnection is exposed through a trench. Thereafter, a conductive metal is deposited onto the insulation layer to fill up the trench, thereby forming the metal wiring making contact with the interconnection in the trench.
In such a case, a planarization process has been used in an attempt to improve the reliability of the wiring structure. For example, an insulation interlayer may be formed on an underlying structure in such a way that the underlying structure is exposed through the via-hole. Then, a conductive layer may be formed on the insulation interlayer to a sufficient thickness to fill up the via-hole, and an upper portion of the conductive layer is removed by a planarization process until a top surface of the insulation interlayer is exposed. Therefore, the conductive layer remains in the via-hole of the insulation interlayer to thereby form the interconnection.
In the above process for forming the interconnection, residuals of the conductive layer on the insulation interlayer due to insufficient planarization may have various process defects. For example, a barrier layer and the conductive metal layer filling up the via-hole may have a different polishing resistance. Accordingly, the conductive layer and the barrier layer may be removed from the insulation interlayer at different rates in the planarization process, and thus the barrier layer may locally remain on the insulation interlayer.
Moreover, as the gap distance between wirings gradually decreases with the increased of degree of integration in semiconductor devices, residuals of the barrier layer have frequently caused electric connections between the interconnection and a neighboring wiring, as well as the wiring respective to the interconnection, to thereby generate bridge failures between neighboring wirings.
In addition, an upper surface of the interconnection may be non-uniform due to hydrogen peroxide (H2O2) in polishing slurry. When the conductive layer and the barrier layer are removed by a chemical mechanical polishing (CMP) process, the conductive layer is locally melted by the hydrogen peroxide (H2O2) in the polishing slurry, and thus the upper surface of the interconnection is partially melted after the CMP process. Non-uniformity of the surface of the interconnection may deteriorate the contact quality of the interconnection and the wiring, thereby decreasing the reliability of the wiring structure. Also, sufficient removal of the residuals of the barrier layer from the insulation interlayer can take a significant amount of the polishing time and the increase in the polishing time may cause a larger melted area of the upper surface of the interconnection due to the hydrogen peroxide (H2O2), thereby deteriorating the contact stability between the interconnection and the wiring.
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USPTO Backgrounds