1. Field
The described embodiments relate to caches in electronic devices. More specifically, the described embodiments relate to a technique for predicting the outcomes of memory requests in a cache memory.
2. Related Art
Many modern computing devices (e.g., laptop/desktop computers, smart phones, set-top boxes, appliances, etc.) include a processing subsystem with one or more caches. Caches are generally smaller, fast-access memory circuits located in or near the processing subsystem that can be used to store data that is retrieved from lower levels of a memory hierarchy in the computing device (i.e., other, larger caches and/or memories) to enable faster access to the stored data.
During operation in such computing devices, memory requests are sent to a cache in an attempt to quickly resolve the memory requests. When attempts to resolve memory requests in the cache fail (i.e., when the memory requests “miss” in the cache), the memory requests are forwarded to a lower level of the memory hierarchy to be resolved. Because determining that the memory request has missed in the cache takes time and fruitlessly consumes resources (e.g., bandwidth on signal busses, processing time in the cache, etc.), misses in caches are undesirable.
USPTO Backgrounds
USPTO Backgrounds