1. Field of the Invention
The present invention relates to passive electrical elements or devices and, more particularly, to such devices formed as part of integrated circuits.
2. Description of the Related Art
Present passive elements, such as inductors, which are integrated on chip typically suffer from high series resistance and capacitive coupling effects which reduce their Q factor. For example, spiral inductors fabricated using a thick last metal layer suffer from having underpass (from center of coil to outer connection) resistance much higher than the rest of the coil. This is due to the prior metal level, which is usually much thinner, being utilized for the underpass. Additionally, inductance density (inductance per unit area) is lower than desired when creating inductors from a single thick last metal layer, causing use of excessive chip area that cannot be used for active functions.
In prior art implementations, the stacking of inductors in series to increase the inductance density has had only limited success due to the high resistivity of the second to last metal level that is utilized to create the second spiral. In prior art implementations, the last two metal levels are also typically separated by a relatively thin dielectric, causing them to be highly capacitively coupled. Creating stacked inductors in this manner causes excessive series resistance and low self-resonance (due to the high capacitive coupling); both factors tending to limit the achievable Q for a spiral inductor.
Another application that has been difficult to achieve due to the limitations of prior art approaches is the realization of coupled inductor structures (e.g., transformers, couplers, baluns, etc.). Excessive capacitive coupling and resistance asymmetry have sometimes precluded the use of coupled inductors that are stacked on top of each other. The most common approach to realizing coupled inductors in prior art implementations, is to create interdigitated spirals on the final level of metal. This approach suffers from excessive use of chip area and from low coupling coefficients (0.7 to 0.85).
For certain prior art approaches, see, for example, U.S. Pat. No. 6,114,937, Integrated Circuit Spiral Inductor, Sep. 5, 2000, by Burghartz, et al., which is hereby incorporated in its entirety by reference.
The present inventors believe that these drawbacks in the prior art can be overcome.
USPTO Backgrounds
USPTO Backgrounds