Silicon carbide (SiC) possesses unique electronic and physical properties such as wide band gap, high breakdown field, high thermal conductivity, and low thermal expansion coefficient. These unique electronic and physical properties make it the material of choice for power electronics that withstand higher breakdown voltage and operate at higher temperatures, far exceeding the performance of their Si counterparts.
SiC exists in a variety of polymorphic crystalline structures called polytypes, e.g., 3C—SiC, 6H—SiC, 4H—SiC, etc., where “C” indicates cubic phases, and “H” hexagonal. The different polytypes can be described by the different ordering, or stacking sequence, of the Si—C bilayers along the c-axis, and can have a wide range of different electronic and physical properties. Out of the more than 200 polytypes, the 3C (cubic zinc blende), 4H and 6H hexagonal structures have the lowest formation energies.
The 3C—SiC is the only cubic phase, and is advantageous for metal-oxide-semiconductor (MOS) device architecture due to its higher channel mobility because near interface traps are not active in the SiO2/3C—SiC system. In addition, its cubic structure in principle enables it to be realized as a thin film on Si(001) and thereby readily integrated with current Si MOS technology, a key criterion for future technological application. Conversely, the hexagonal structure of the 4H and 6H phases are incompatible with growth on Si(001). Integration as a thin film on Si also has significant economic implications, because SiC bulk crystals are very costly to produce, and at present only the 4H— and 6H—SiC bulk wafers are available commercially—no bulk 3C—SiC single crystal substrate wafers are available, and thus it must be grown on a different substrate.
Therefore there has been significant interest to produce low-cost, large area 3C—SiC films on a low cost substrate which serves as a surrogate substrate for subsequent epitaxial growth of 3C—SiC single crystal thin film device heterostructures.
In recent years, considerable efforts have been spent on the growth of SiC on Si substrates, typically by molecular beam epitaxy (MBE) and chemical vapor deposition (CVD) techniques. However, due to the large lattice mismatch (20%), the resulting SiC films are not of high enough quality required for high-power electronic devices. The use of a buffer layer has been shown to seed the growth of higher quality SiC films. Previous buffer layers have been created through the chemical reaction of the Si substrate and carbon-containing gases such as C2H4 and CO at elevated temperatures.
When the buffer is porous, as is in the case of CO due to the formation of volatile Si—O species, the significant relaxation of the elastic stresses between the SiC film and Si substrate leads to films with far less defects.
However, this process with CO gas has only been done during high pressure CVD.
Here, an alternate method of producing a porous SiC buffer layer on a Si substrate is demonstrated, through solid state reaction with a pre-deposited amorphous C film at about 950° C. in ultrahigh vacuum (UHV).
This new method has several advantages over current processes. First, the resulting 3C—SiC buffer layer is much thinner (1-2 nm), with a thickness directly controlled by the thickness of the C film. Second, it works at a much lower temperature (about 950° C.) than those with gaseous species (1100-1400° C.), reducing the thermal budget and the excess energy available for formation of undesirable defects. Third, it is compatible with both CVD and MBE, the two major techniques used to grow device quality 3C—SiC heterostructures.
USPTO Backgrounds
USPTO Backgrounds