The present invention relates to manufacturing techniques of semiconductor devices, and more specifically, to a technique effectively applied to a semiconductor device with a semiconductor chip mounted over another semiconductor chip.
Japanese Unexamined Patent Publication No. 2001-217387 (Patent Document 1) discloses a method for stacking semiconductor chips which involves respectively forming alignment marks on the surface of a parent chip (fixed device) and on the surface of a child chip (semiconductor chip), and stacking the child chip over the parent chip based on the result of detection of the alignment marks such that the respective alignment marks on both chips face each other.
Japanese Unexamined Patent Publication No. 2011-187574 (Patent Document 2) discloses a semiconductor device including a semiconductor chip with a penetrating electrode between a wiring substrate and a laminated body of a plurality of memory chips.
USPTO Backgrounds
USPTO Backgrounds