This invention relates generally to integrated circuits and manufacturing methods and more particularly to structures and methods having improved planarity and alkali ion gettering properties.
As is known in the art, in forming small line width geometries in a semiconductor process using photolithography, it is necessary to provide a highly planar surface for various photolithographic masks used in such process. Further, in the fabrication of dynamic random access memories (DRAMs) a plurality of gate electrodes are formed adjacent one another with relative small separation, i.e., gaps, between each adjacent pair thereof. Thus, it is necessary to fill these gaps width a suitable material, preferably a material with a low dielectric constant to prevent coupling between the adjacent electrodes as well as to provide a planar surface for subsequent photolithography.
With one process, after the gate electrodes are formed, a dielectric layer of silicon nitride is chemically vapor deposited (CVD) over the surface. The CVD silicon nitride is a conformal deposition and therefore gaps remain between adjacent gate electrode structures. The gap width between gate electrode structures after the layer of silicon nitride is deposited is in the order of 1200 xc3x85. Next, a layer of boron phosphorous doped glass (BPSG) is chemically vapor deposited over the structure to fill in the gaps. The CVD BPSG is thick enough to not only fill the gaps but also extends over the tops of the CVD silicon nitride layer and over the filled gaps to a thickness in the order of 4000 xc3x85-5000 xc3x85.
As is also known in the art, contaminants, such as sodium ions, or other alkali ions may come into contact with the outer BPSG layer. However, the phosphorous in the BPSG layer acts as a gettering material to counteract the effect of the alkali ion contaminant. The structure is then heated to form a more planar surface. However, because of high degree of planarity required for the subsequent photolithographic processing, e.g. metal layer patterning into electrically conductive wires, relatively expensive chemical mechanical polishing (CMP) may be required to form a surface with the requisite degree of planarity.
The invention relates to the filling of gaps such as those between adjacent gate electrodes of a semiconductor structure. In one embodiment, a self-planarizing material is deposited over the structure. A first portion of such material flows between the gate electrodes to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A dopant, here phosphorous, is formed in the second portion of the self-planarizing material.
In accordance with the invention, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. Further, the phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. Still further, the dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes.
In accordance with one feature of the invention, the self-planarizing material is a flowable material. The phosphorous dopant may be provided by, for example: implanting phosphorous ions into the second portion of the self-planarizing layer and heating the material to both cure such material and activate the phosphorous ions; depositing a phosphorous doped layer over the layer of self-planarizing material, heating the structure to out-diffuse the phosphorous dopant into the second portion of the self-planarizing material and then selectively removing the deposited layer; or by curing the spun-on self-planarizing material in a phosphine environment.
USPTO Backgrounds
USPTO Backgrounds