It is known that the performance of a transistor may depend on an operation current of the transistor. Therefore, efforts have been made to provide high operation currents for transistors. In particular, strained silicon channel (SSC) techniques have been studied wherein stress is applied to a channel region.
SSC techniques may provide a strained channel layer on an upper part of a metal oxide silicon field effect transistor (MOSFET) by forming a stress inducing layer. SSC techniques have been disclosed in the article by T. Ghani et al. entitled “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS Transistor” (IEEE in 2003).
However, even if a stress inducing layer covers a bulk type MOSFET, stress provided by the stress inducing layer may be distributed in a substrate since the body area (or thickness of the substrate) of a MOSFET is relatively large compared to the thickness of the stress inducing layer. Accordingly, it may be difficult to obtain a high mobility of carriers and there may be a limit in obtaining a high operating current of the MOSFET.
USPTO Backgrounds
USPTO Backgrounds