Conventional digital integrated circuits comprise complex combinational networks for performing logical operations on data and memory elements interconnected with the combinational networks to provide memory functions essential to the operation of the combinational networks. Such integrated circuits are difficult to test due to the complexity of their operation.
Modern digital integrated circuit designers incorporate test features in digital integrated circuits at the design stage to ensure that such circuits are testable. In one design technique known as Level Sensitive Scan Design (LSSD) designers partition circuits into combinational networks and scannable memory elements usually flip flops. The flip flops are made reconfigurable from their operating configuration in which they are connected to the combinational networks of the circuits as required to support normal operation of the circuit to a scan configuration in which they are decoupled from the combinational networks and connected in series to form one or more shift registers known as scan chains.
The scan configuration is used during testing of the circuit to shift a known test stimulus pattern into the scan chains. The flip flops are then put into the operation configuration for at least one clock cycle so that the combinational networks performing logical operations on some of the data making up the test stimulus pattern and alter the data stored in some of the flip flops. The flip flops are then returned to the scan configuration to shift the altered data out of the scan chains as a test response pattern. The test response pattern is compared with a calculated test response pattern or with a test response pattern obtained from a circuit which is known to be functioning properly to determine whether the circuit under test if functioning properly.
Previously proposed scan testing techniques for circuits operating at multiple clock speeds used a single slowless speed clock as in U.S. Pat. No. 4,503,537 or multiple clocks for the scannable elements grouped for clocking by appropriate clocks as taught in U.S. Pat. No. 5,349,587. Both of these known techniques were applied to circuits having multiple clocks for normal operation.
Recently, digital circuit designs have been developed that eliminate the use of multiple clocks. This has been done to obviate timing problems associated with timing edges for multiple clocks being out of synchronization on arrival at the clock input of memory elements. In place of multiple clocks, these new digital circuit designs using a single master clock signal at a highest desired operating frequency. Lower clock rate sections of the digital circuit are implemented using specially designed flip flops that have clock enable signals derived from multiple clocks but synchronized with the master clock signal.
While this design technique solves the operational problems faced by the circuit designers, it creates new problems for circuit testing. The technique of U.S. Pat. No. 4,503,537 could be used with the same short comings of not testing at all frequencies used in operation. The technique of U.S. Pat. No. 5,349,587 could be used for scan testing but may introduce into the testing environment those same problems that circuit designers were trying to eliminate in the operation environment by not using multiple clocks.
Clearly, there is a need in the prior art for a scan testing technique for the digital circuit design described above.
USPTO Backgrounds
USPTO Backgrounds