The present invention relates in general to methods of fabricating electrical circuit components and in particular to methods of fabricating devices comprising both standard voltage threshold transistors and low voltage threshold transistors.
Standard voltage threshold (Vt) metal oxide semiconductor field effect transistor (MOSFET) devices can function to limit current when their gate voltage is not biased with respect to the voltage threshold. Accordingly, standard Vt MOSFET devices are suitable for complimentary metal oxide semiconductor (CMOS) circuit applications where power dissipation is of concern to the circuit designer. Lowering the voltage threshold of the MOSFET device however, generally increases the device switching performance. Accordingly, low Vt MOSFET devices are suitable for CMOS applications where fast switching is of concern to the designer. A low Vt MOSFET device is more likely to experience leakage current as compared to a standard Vt MOSFET device however. Likewise, a standard Vt MOSFET device may switch slower than a relatively lower Vt MOSFET device.
Accordingly, it is advantageous to incorporate MOSFET devices that operate at multiple voltage thresholds into CMOS circuits. For example, standard Vt MOSFET devices can be used to reduce power dissipation when a circuit is operating in standby mode. Low Vt MOSFET devices are often capable of driving relatively high current and can potentially increase the maximum overall speed of an electrical circuit because relatively lower Vt MOSFET devices typically exhibit faster switching characteristics than a corresponding relatively higher Vt MOSFET device.
The combination of standard Vt and low Vt MOSFET devices in a single substrate complicates the manufacture of CMOS circuits. For example, multiple masking, implanting, and other processing steps are typically necessary to create standard and low Vt PMOS as well as the standard and low Vt NMOS devices. Each processing step increases the complexity of the fabrication process and potentially reduces yield due to the increased potential for possibility defects. As the packing density of complex circuit arrays increases, the potential for reduced yield further increases.
USPTO Backgrounds
USPTO Backgrounds