1. Field of the Invention
The present invention relates, in general, to the testing of integrated circuits and, more specifically, to verification of the exact timing of a memory interface with surrounding logic when performing an at-speed scan test of an integrated circuit (IC).
2. Description of Related Art
The main challenges which face semiconductor manufacturers and integrated circuit designers revolve around achieving the highest yield in the shortest amount of time. This is especially true as the industry continues to move to smaller process geometries and beyond and as circuit operating speeds continue to increase. There is a need therefore for products and test solutions that enable circuit designers to improve product quality, gain information on the source of product failures and field returns, and use that information to create higher yielding integrated circuits (ICs) faster. To that end, it is well known to test ICs by scan test techniques in which test data is scanned into an IC to stimulate the IC and IC response data is scanned out for analysis. One problem which has yet to be satisfactorily resolved is testing of memory test interfaces and surrounding test logic which generate memory inputs and receive memory outputs.
FIGS. 1a and 1b illustrate a memory 12, surrounded by input and output logic circuitry 14, and 16, respectively. The memory includes memory cells, address decoder, precharge logic, etc., which are not shown for simplicity. Input scannable memory elements 18, which form a test input scan chain, are provided for scanning test data into the circuit and output scannable memory elements 20, which form a test response output scan chain, are provided for capturing and scanning test responses from the circuit. The input memory elements apply test patterns to the logic which, in turn, apply inputs to the write enable control, address and data inputs of the memory 12. The data outputs of the memory are applied to the output logic on the output side of the memory. The output of the logic is applied to the output scannable memory elements 20. The memory elements are arranged into scan chains by applying an active scan enable signal, SE, to respective inputs. An inactive scan enable signal is applied to the memory elements to launch test data or capture response data. As is well known in the art, the scannable memory elements include flip-flops for storing test and response data.
The bold lines in the figures represent a plurality of lines or connectors and corresponding scannable memory elements, the number of which depends on the number of memory write enable inputs, address inputs and data inputs and memory outputs of the circuit design.
For the purpose of simplifying the description, it is assumed herein that all flip-flops, and the memory are positive edge-triggered. In FIG. 1a, the memory is in phase with the surrounding logic so that it captures its input and updates its output on the rising edge of the clock. In FIG. 1b, the memory is out of phase with the surrounding logic because of clock inversion caused by inverter 22. The memory output is latched by transparent latch 24 so that the memory output appears to update its output on the positive edge before it is used by the surrounding logic 16. The memory input is captured on the falling edge of the clock. The test method of the present invention addresses both circuit configurations.
FIG. 2 illustrates a known memory circuit 12 which includes a memory test interface or BIST collar 32 which surrounds memory 12, a memory BIST (Built-In Self-Test) circuit 34 and circuit modifications, described below, to the memory circuits of FIGS. 1a and 1b for performing at-speed scan testing of the memory interface 32. The circuit logic includes logic 14a which outputs a write enable data, logic 14b which outputs an address and input data to be applied to the memory and output logic 16 which receives data output by the memory. The test interface is indicated by the dotted line and includes test interface input multiplexers (muxes) 36, controlled by a BistOn select signal for selecting between functional inputs and BIST inputs. The input muxes include a write enable mux 38, a plurality of address input muxes 40 and a plurality of data input muxes 42.
A bypass mechanism 44 connects data inputs and corresponding data outputs through respective scannable flip-flops 46. Flip-flops 46 are clocked on the same edge of the clock, CK, which clocks the memory. The test interface also includes an output muxes 48, controlled by a test mode signal, tm, which is active high during scan and BIST testing to select between a memory output and the output of a corresponding bypass flip-flops 46.
Scannable observation logic 50 and 52 are provided for the control (e.g. write enable) and address inputs, respectively, of the memory. This logic is in the form of scannable flip-flops that are clocked on the same edge as the memory. The bypass mechanism and the observation logic complement other features, such as memory BIST circuit 34, to test the memory independently of a scan test.
A scan test is performed by deselecting the memory, setting BistOn low and tm high. Test data is scanned into the input scan chain 18 and applied to input logic 14a and 14b whose outputs are applied to the test interface input muxes 36. The outputs of input muxes 38 and 40 are captured in observation logic 50 and 52 and the outputs of data input muxes 42 are captured in bypass flip-flops 46. The outputs of bypass flip-flops 42 are applied to inputs of output muxes 48, the outputs of which are applied to output logic 16 whose outputs are captured by the output scan chain. The captured data is scanned out for analysis.
An interface input timing test is performed by launching test data from the input scan chain and capturing data in the observation memory elements 50 and 52 and bypass flip-flops 46. The captured data is scanned out for analysis. An output timing test involves launching data from bypass flip-flops 46 and capturing the resulting data in output scan chain 20. The captured data is scanned out and analyzed. As explained below, there are drawbacks to this method and circuitry.
The observation and bypass mechanisms allow for testing the timing of the input relatively accurately because the setup time for a synchronous configuration is similar to that of a flip-flop. However, the test of the output side of the memory is less accurate because the bypass flip-flops update their output significantly faster than the memory. As a result, subtle delay faults can escape detection by a combination of a scan test and a memory BIST test even though both tests are performed at-speed. Another limitation is that the bypass mechanism can be relatively expensive in terms of silicon area for wide data buses. Further, because of their potential impact on timing, it would also be desirable to eliminate the set of output muxes 48 at the output of the memory. It will be seen therefore that there is a need for a method and circuitry that address these limitations.
USPTO Backgrounds
USPTO Backgrounds