1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, for example, having a package structure called a CSP (chip scale package) structure and in particular to a miniaturized and slimmed semiconductor integrated circuit device.
2. Description of the Related Art
In recent years, strict requirements for miniaturization and slimming down of semiconductor integrated circuit devices have been made increasingly with miniaturization and slimming down of electronic machines. To meet the requirements, a package structure called a CSP structure is proposed as one of new miniaturized and slim package structures replacing flat packages of conventional semiconductor integrated circuit device package structures.
The CSP structure, which is a package structure where a reliability guarantee test such as a burn-in test of a semiconductor integrated circuit device can be executed, is suppressed in size almost to a semiconductor chip size; basically it is a structure wherein a semiconductor chip is directly connected to a carrier substrate of almost a chip size instead of connecting a semiconductor chip and a lead frame by conventional wiring bonding.
An example of the structure is described on pages 35-38 of November number 1995 of "Hyoumen jissou gijyutu." FIG. 12 is a sectional view of a semiconductor integrated circuit device shown in the prior art. FIG. 13 shows a carrier substrate. The semiconductor integrated circuit device uses a polyimide film as a base material 18 for a carrier substrate and a circuitry conductive layer consisting of external connection parts 4 and a chip connection part 5 is formed on the surface of the film as a carrier substrate. Further, a conductive pad 8 formed on a semiconductor chip 1 is connected to the chip connection part 5 and the space between the surfaces of the semiconductor chip 1 and the carrier substrate is filled with an elastomer 2 of a rubber material as a thermal expansion coefficient relief material. External connection terminals 7 are placed on the rear face at the position of the external connection parts 4 of the base material 18. The entire dimensions of the semiconductor integrated circuit device are thus set almost to a chip size.
Another example of the structure is described on pages 22-25 of November number 1995 of "Hyoumen jissou gijyutu." FIG. 14 is a sectional view of a semiconductor integrated circuit device shown in the prior art. FIG. 15 shows a carrier substrate. The semiconductor integrated circuit device comprises external connection parts 4 disposed on the rear face and chip connection parts 5 disposed on the surface and uses a ceramic substrate 10 formed with through holes 9 for connecting the external connection parts 4 and the chip connection parts 5 as a carrier substrate. The chip connection part 5 and a conductive pad 8 of the semiconductor chip 1 are connected by a chip connection terminal 14. Each external connection part 4 is provided with an external connection terminal 7. The space between the surfaces of the carrier substrate and the semiconductor chip 1 is filled with a seal resin 12 made of normal thermosetting resin. The entire dimensions of the semiconductor integrated circuit device are thus set almost to a chip size.
However, the semiconductor integrated circuit device shown in FIG. 12 uses a polyimide film as the base material 18 for the carrier substrate. The polyimide film has a thermal expansion coefficient of 60.times.10.sup.-6 .degree. C..sup.-1, which differs largely from the thermal expansion coefficient of the silicon semiconductor chip 1, 4.times.10.sup.-6 .degree. C..sup.-1. The semiconductor integrated circuit device shown in FIG. 12 uses the elastomer 2 to relieve the stress produced due to the thermal expansion coefficient difference. Use of the elastomer 2 involves problems of lowering humidity resistance for the semiconductor chip 1, cost increase because of installation of new facilities, cost increase of seal resin, etc. Further, to relieve the heat stress, the conductive pad 8 of the connection part to the carrier substrate needs to be placed at the center of the semiconductor chip 1, for example.
The semiconductor integrated circuit device shown in FIG. 14 comprises the carrier substrate 10 made of alumina of ceramic (thermal expansion coefficient=8.times.10.sup.-6 .degree. C..sup.-1); the thermal expansion coefficient difference between the carrier substrate 10 and the semiconductor chip 1 is comparatively small. Therefore, a special heat stress relief material is not required, the space between the semiconductor chip 1 and the carrier substrate 10 may be filled with the seal resin 12 made of normal thermosetting resin, etc., and the conductive pad 8 of the semiconductor chip 1 corresponding to the chip connection terminal 14 may be placed in the surrounding of the semiconductor 1. However, the through holes 9 need to be made in the carrier substrate 10 made of ceramic and conduction treatment such as plating of the inner walls of the through holes 9 or filling the through holes with a conductive material is required. Moreover, the ceramic material is hard and brittle as compared with the film material, etc., thus a reasonable thickness is required for ensuring reliability; the ceramic material is also disadvantageous from the viewpoint of the entire thickness of the package.
USPTO Backgrounds
USPTO Backgrounds