The present invention relates to a method for making an electrical circuit board and more particularly, to a method for making a multi-layer electrical circuit board having apertures and/or cavities which are formed within the circuit board and/or through various portions of the circuit board, and which provide for improved and/or more reliable solder interconnections between portions or layers of the circuit board.
Multi-layer circuit boards contain and/or include electrical components and interconnecting conductive traces or routing lines which selectively and operatively populate opposed first and second surfaces (i.e., top and bottom surfaces) of each board (or other respective interior portions of each of the boards), thereby desirably allowing each of the electrical circuit boards to contain and/or include a relatively large amount of electrical components and conductive traces which efficiently and densely populate the respective boards.
It is desirable to allow for communication by and between and/or interconnection of the component containing conductive surfaces and/or portions of an electrical circuit board, thereby allowing the contained electrical components and traces on each side of the board (or within certain interior portions of the board) to cooperatively and selectively interconnect to form one or more desired electrical circuits. This communication and interconnection may require the use of shared electrical ground planes, the transmittal of electrical power and/or control type signals between each of the component containing surfaces and/or the component containing board portions, and/or the selective and physical connection of various contained components.
This desired interconnection typically requires one or more holes or cavities to be drilled and/or formed through the core of the circuit board substrate, thereby selectively creating one or more xe2x80x9cthrough-holexe2x80x9d, type vias or apertures (i.e., holes which pass through and/or traverse the entire circuit board or all of the opposed component containing surfaces), and one or more xe2x80x9cblindxe2x80x9d type vias or apertures (i.e., holes which do not pass through and/or traverse the entire circuit board and all of the opposed component containing surfaces). The vias are then typically filled with solder (e.g., a pin or component connector is soldered into the hole). In this manner, electrical connections are made or formed which connect electrical components and/or circuitry to the core of the circuit board substrate, or to other components and/or circuitry located on the opposing side or surface of the board.
One drawback associated with these conventional vias and with this circuit board design is that layers of relatively non-solderable material (i.e., insulating material and/or material which does not substantially bind or metallurgically bond with solder) are typically present within these vias, and thus, the solder does not consistently and reliably electrically connect the desired layers of circuitry and/or components together. For example and without limitation, portions or layers of non-solderable material often xe2x80x9coverhangxe2x80x9d or project beyond conductive layers or portions of the circuit board, which are typically xe2x80x9cetched backxe2x80x9d or recessed within the insulating portions or layers. This arrangement often results in a void which is not filled by the relatively high-tension solder material, thereby substantially preventing or reducing the likelihood of the solder material xe2x80x9cwettingxe2x80x9d or metallurgically bonding to the conducting portions or layers of the circuit board. Hence, these types of arrangements often result in a defective portion or region of the circuit board where all layers of the circuit board are not desirably interconnected.
There is therefore a need for a method for producing a multi-layer electrical circuit board which overcomes some or all of the previously delineated drawbacks of prior circuit boards and which includes vias or cavities which provide for improved solder interconnections between one or more layers of electrical circuitry.
It is a first object of the present invention to provide a method for producing a multi-layer electrical circuit board which overcomes some or all of the previously delineated drawbacks of, prior multi-layer electrical circuit board forming methodologies and techniques.
It is a second object of the present invention to provide a method for making a multi-layer electrical circuit board which includes one or more vias, apertures or cavities which provide for highly reliable and solderable interconnections between conductive layers or portions of the circuit board.
It is a third object of the invention to provide a method for producing a multi-layer electrical circuit, board which overcomes some or all of the previously delineated drawbacks of prior multi-layer electrical circuit board forming methodologies and techniques and which allows for the selective, efficient, and reliable formation of apertures or cavities, which allows for communication by and between some or all of the various component containing surfaces and portions of the formed multi-layer electrical circuit board, which selectively allows components contained within and/or upon these portions and surfaces to be interconnected, and which is further adapted to selectively and communicatively receive an electrical component and/or an electrical component connector portion.
According to a first aspect of the present invention a method is provided for forming a solder connection within a multi-layer circuit board having a first conductive layer, and a first and a second insulating layer, the first conductive layer being disposed between the first and the second insulating layer. The method includes the steps of: forming a first aperture through the first conductive layer, the first insulating layer and the second insulating layer; forming a second aperture through the first conductive layer, the first insulating layer and the second insulating layer, the second aperture being formed in relative close proximity to the first aperture, effective to cause at least a first portion of the first layer and at least a second portion of the second layer to separate from a third portion of the first conductive layer, thereby exposing the third portion of the first conductive layer; and wetting the third portion with a solder material, thereby metallurgically bonding the solder material to the first conductive layer.
USPTO Backgrounds
USPTO Backgrounds