Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials, or alloys. Such a Si alloy may be, for instance, silicon-germanium (SiGe). The devices in the embodiments of the present disclosure are typically part of the art of single crystal, Si based material device technology. Or, more specifically, of the silicon-on-insulator (SOI) technology, where a layer of silicon based material for building devices sits on top of an insulating material.
There is a great difficulty in maintaining performance improvements in devices of deeply submicron generations. A useful scheme known in the art is to build devices in a semiconducting layer which is isolated from the semiconducting substrate by a buried insulating layer. Most commonly the semiconducting layer is Si, hence the terminology silicon-on-insulator (SOI) technology is in general use. The buried insulator usually is SiO2, to yield the customary name of BOX (buried oxide).
Within SOI technology there exist a class of devices characterized as floating body devices. The term “floating” refers to the potential of the device body, as it is not tied to any particular controlled voltage source. The floating body in an SOI transistor leads to several undesirable effects. The circuit switching speed depends on the body potential, which may be a function of the previous switching history. The floating body is an additional source of variation that makes precise transistor-to-transistor matching more difficult than for bulk transistors. Therefore for many applications it would be desirable to have means to control the body potential. Such control, for instance, may be to tie the body potential to the source potential. This may usually be accomplished by changing the transistor layout to include a body contact region at the surface, which electrically connects to the body through the device width direction. There are several drawbacks of this solution. First, there is a layout area penalty, and secondly, the body contact resistance may be very large in wide-width devices. It also has been proposed (U.S. Pat. No. 6,635,542, by Sleight et al) to use a leakage, or damage, implant on the source side to introduce defects and to raise junction leakage between body and source to achieve an effective body-to-source tie. This approach is not fully satisfactory, and a solution to eliminate the problem, which in the art is often named the floating body, or memory problem, has still not been found.
USPTO Backgrounds
USPTO Backgrounds