Generally, a MOS field effect transistor (MOSFET) includes a gate insulating film which is formed on a semiconductor substrate, a gate electrode on the gate insulting film, and source/drain regions are formed at both sides of the gate electrode. In a typical MOSFET, a channel is formed in a channel region underlying the gate electrode as a bias voltage is applied.
As semiconductor devices have become highly integrated, channels have decreased in length. Therefore, methods have been developed in an effort to improve transistor performance.
Some techniques involve increasing the mobility of electrons or holes in the channel region. Specifically, if the mobility of the carriers increases, switching characteristics of a transistor may be improved, which may make it possible to manufacture a device having higher speed.
Some techniques involve changing the energy band structure of a channel region by applying physical stress. For example, when the semiconductor has a crystallographic orientation <100>, and the channel of an NMOS transistor has a crystallographic orientation <110>, if a tensile stress is applied in a channel direction, performance of an NMOS transistor may be improved. If a compressive stress is applied in the channel direction, performance of a PMOS transistor may be improved.
In contrast, if a tensile stress is applied in a transverse direction, that is, in a direction perpendicular to the channels of an NMOS or PMOS transistor, the mobility of a number of carriers may be increased, which may improve performance of the transistors.
Typically, an isolation region is formed around an NMOS or PMOS transistor. If the isolation region is formed of an HDP (High Density Plasma) oxide film, for example, it may be possible to decrease the mobility of a number of carriers of the NMOS and PMOS by applying a compressive stress in the transverse direction.
USPTO Backgrounds
USPTO Backgrounds