1. Field of the Invention
The present invention is directed to methods of manufacturing integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of optimizing die yield in a silicon wafer.
2. Description of the Prior Art
In the manufacture of integrated circuit devices, a silicon wafer is typically partitioned into die or dice each having an identical arrangement of semiconductor structures. The die are formed on the silicon wafer by a photolithography tool, called a stepper. The stepper prints the die in groups, called shots, on the surface of the silicon wafer. The wafer yield is the number of die formed on the silicon wafer that perform satisfactorily to the design specifications of the integrated circuit device.
USPTO Backgrounds
USPTO Backgrounds