1. Field of the Invention
The present invention relates to logic elements for use with programmable logic devices or other similar devices.
2. Description of the Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements (LEs) sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). As used herein, the term logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) indicates a logic circuit that includes at least one look-up table (LUT). An LE may also include a carry-out chain, register, and other elements.
Logic elements typically include configurable elements holding configuration data that determines the particular function or functions carried out by the logic element. A typical LUT circuit may include ram bits that hold data (a “1” or “0”). However, other types of configurable elements may be used. Some examples may include static or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. For purposes herein, the generic term “memory element” will be used to refer to any programmable element that may be configured to determine functions implemented by other PLDs.
A typical LUT circuit used as a logic element provides an output signal that is a function of multiple input signals. The particular logic function may be determined by programming the LUT's memory elements. A typical LUT circuit may be represented as a plurality of memory elements coupled to a “tree” of 2:1 MUXes. The LUT MUX tree includes a first level comprising a single 2:1 MUX providing the LUT output and also includes successive additional levels of MUXes, each level including twice as many MUXes as the previous level and the number of memory elements being twice as many as the number of 2:1 MUXes in a last MUX level coupled to the memory elements. Each 2:1 MUX level provides a logic input to the LUT circuit coupled to control inputs of the MUXes at that MUX level. Thus, to obtain an n-input LUT (or “nLUT”) typically requires 2n memory elements and 2n MUXes. Adding an input to an nLUT circuit to provide an n+1 input LUT (“(n+1)LUT”) therefore typically requires providing a total of 2n+1 memory elements and (2n+1-1) MUXes, i.e., approximately a doubling of resources relative to that required by an nLUT.
The expressive power of an LE is a quantification of the amount of generic logic that the LE can support. For example, if a given hardware circuit can be implemented using either 20 LEs of type A or 10 LEs of type B, type B has greater expressive power than type A.
Greater expressive power normally comes at a cost in that an LE of type B will typically consume greater silicon area than an LE of type A. Additionally, depending on the logic to be implemented, the expressive power of an LE of type B may not be necessary. Thus, if a LAB is made up of LEs of type B, and the logic to be implemented by the LAB does not require the expressive power of an LE of type B, but could be as efficiently implemented in an LE of type A having less expressive power, inefficiencies may result.
One way to address this problem is discussed in A. Kaviani, Novel Architectures and Synthesis methods for High Capacity Field Programmable Devices, Doctoral Thesis, University of Toronto, January, 1999. Kaviani discloses a PLD architecture combining both FPGAs based on LUTs and Complex Programmable Logic Devices (CPLDs) based on product terms and not using LUTs. CPLDs however, generally have a lower logic capacity, measured in terms of equivalent logic gates, than LUT based FPGAs. Thus, the PLD architecture of Kaviani may not provide adequate power for efficient implementation of a number of logic configurations.
USPTO Backgrounds
USPTO Backgrounds