1. Field of the Invention
The present invention relates to a heat treatment method for a silicon wafer, and more particularly to a heat treatment method which can reduce the density of crystal originated particles (COPs) and micro-defects which serve as nuclei of oxidation induced stacking faults at the surface of a silicon wafer, as well as to a silicon wafer heat-treated by the method.
2. Description of the Related Art
In order to improve electric characteristics of a silicon wafer such as oxide-film dielectric breakdown voltage and leakage current, the surface layer portion of the waferxe2x80x94on which semiconductor devices are fabricatedxe2x80x94must be made defect free. Various methods for heat-treating silicon wafers in various ways have been proposed in order to form a defect-free layer at the surface of the silicon wafer to thereby obtain a so-called intrinsic gettering effect. Among them, there has been generally employed a method in which a silicon wafer is subjected to low-temperature heat treatment at a temperature of 650xc2x0 C.-700xc2x0 C. for a few hours and then subjected to high-temperature heat treatment at a temperature of 1150xc2x0 C.-1200xc2x0 C. for four hours in a reducing atmosphere such as a 100%-hydrogen atmosphere.
In such a conventional method, although a defect-free layer can be formed at the surface of a silicon wafer, the high-temperature heat treatment requires over 1 hour, resulting in low productivity. Also, oxide precipitate is generated in the wafer, and the oxide precipitate causes warp and slip dislocation in a subsequent device-fabricating process.
Moreover, in the conventional method, since heat treatment is performed in batch through use of a so-called vertical type furnace, a large amount of hydrogen must be caused to flow through the furnace, resulting in an increased level of danger.
In order to solve the above-described problems, there have been proposed inventions as shown in, for example, Japanese Patent Application Laid-Open (kokai) No. 7-161707. In the invention disclosed in this publication, an apparatus capable of rapid heating and rapid cooling (hereinafter referred to as a xe2x80x9crapid heating/rapid cooling apparatusxe2x80x9d) is used in order to improve the oxide-film dielectric breakdown voltage of a wafer through heat treatment that is performed for a short period of time; for example, 1-60 seconds, within a relatively low temperature range of 950xc2x0 C.-1200xc2x0 C.
In this method, since wafers are treated in so-called single wafer processing, the heat treatment can be completed within a short period of time to thereby improve productivity, and problems stemming from generation of oxide precipitate do not occur. Further, since the volume of the chamber is small, the amount of hydrogen gas to be used can be reduced to thereby enhance safety and eliminate necessity for a special apparatus.
Meanwhile, micro-defects which are generated due to precipitation of oxygen or the like and which serve as nuclei of oxidation induced stacking faults and COPs (Crystal Originated Particles) have recently been cited as a cause of decreasing the yield of a device-fabricating process.
Oxidation induced stacking faults are originated from micro-defects introduced during crystal growth and serving as nuclei and appear in an oxidation step or the like of a device fabricating process, becoming a cause of failures such as an increased leakage current of fabricated devices. COP is one type of crystal defect that is introduced in a crystal during the growth thereof and is known to be a defect having a regular octahedron structure.
When a silicon wafer subjected to mirror-polishing is cleaned through use of a mixture solution of ammonia and hydrogen peroxide, pits are formed in the wafer surface. When the number of particles on the wafer is measured through use of a particle counter, pits are also detected and counted as particles together with real particles. The thus-detected pits are called xe2x80x9cCOPsxe2x80x9d in order to distinguish them from the actual particles.
Although there are many opinions in relation to the effects of COPs, COPs existing at the surface of a wafer are known to deteriorate the electric characteristics of the wafer.
For example, a time dependent dielectric breakdown (TDDB) of oxide film, one important electric characteristic of a semiconductor device determined through a reliability test, is known to be related to COPs, and therefore reduction of COPs is required in order to improve the time dependent dielectric breakdown.
Also, COPs are said to affect an ordinary time zero dielectric breakdown (TZDB) of oxide film.
Moreover, COPs are said to adversely affect the device-fabricating process. That is, if a COP exists at the surface of a wafer, a step is formed during a wiring process, and the thus-formed step causes breakage of wiring, resulting in a decrease in yield.
Since wafers are subjected to many heat treatment processes during the manufacture of semiconductor devices, COPs may be generated after any one of the heat treatments. Especially, it has been known that when a wafer is subjected to wet oxidization at 1050xc2x0 C. for 30 to 240 minutes, COPs are likely to be generated.
As described above, reduction of COPs and micro-defects which serve as nuclei of oxidation induced stacking faults has recently become necessary in order to improve electric characteristics of silicon wafers.
In the conventional technique disclosed in Japanese Patent Application Laid-Open No. 7-161707, heat treatment conditions are determined in consideration of oxide-film dielectric breakdown voltage and no investigation is conducted as to COPs and micro-defects which serve as nuclei of oxidation induced stacking faults at the surface of a wafer, which directly affect the electric characteristics of a resultant device. Although in the embodiment of the invention disclosed in this publication the BMD density of a wafer is taken into consideration, COPs at the wafer surface are not considered.
The results of an experiment conducted by the present inventors reveal that under the conventional heat treatment method disclosed in Japanese Patent Application Laid-Open No. 7-161707, oxide-film dielectric breakdown voltage can be improved to some extent, but COPs cannot be reduced to a sufficient level, so that sufficient improvement is not achieved for electric characteristics other than oxide-film dielectric breakdown voltage.
That is, when a silicon wafer was subjected to hydrogen heat treatment for 30 seconds at 1050xc2x0 C., which is within the temperature range of the conventional technique, the number of COPs did not decrease, and haze that represents the roughness of the wafer surface sometimes deteriorated due to etching of silicon by hydrogen. Further, even when heat treatment was conducted at 1100xc2x0 C., a sufficient result was not obtained in terms of elimination of COPs, like in the above-described case. From the above, it was found that under the heat treatment conditions employed in the conventional technique, COPs cannot be reduced sufficiently.
The present invention has been accomplished to solve the above-mentioned problems, and an object of the present invention is to provide a heat treatment method for a silicon wafer in which a silicon wafer is subjected to heat treatment in a reducing atmosphere through use of a rapid heating/rapid cooling apparatus and which can reduce the density of COPs and micro-defects which serve as nuclei of oxidation induced stacking faults at the surface of a silicon wafer.
The heat treatment method can improve not only oxide-film dielectric breakdown voltage but also other electric characteristics such as electrical reliability and leakage current, and also can make the best use of advantages peculiar to the rapid heating/rapid cooling apparatus; i.e., enhancement of productivity and reduction in the amount of hydrogen gas to be used.
To achieve the above object, the present invention provides a heat treatment method for a silicon wafer in which a silicon wafer is heat treated in a reducing atmosphere through use of a rapid heating/rapid cooling apparatus. The method is characterized in that the silicon wafer is heat treated for a period of 1 to 60 seconds at a temperature in the range of 1200xc2x0 C. to the melting temperature of silicon.
In the heat treatment method for heat treating a silicon wafer in a reducing atmosphere through use of a rapid heating/rapid cooling apparatus, when the silicon wafer is heat treated at a temperature in the range of 1200xc2x0 C. to the melting temperature of silicon, which is higher than the temperature range used in the conventional method, COPs and micro-defects which serve as nuclei of oxidation induced stacking faults can be reduced, and thus not only oxide-film dielectric breakdown voltage but also other electric characteristics such as electrical reliability and leakage current can be improved.
In this case, the reducing atmosphere is preferably a 100%-hydrogen atmosphere or a mixed atmosphere of hydrogen and argon, because COPs can be reduced effectively through use of such a reducing atmosphere.
In the present invention, the time duration for heat treatment can be shortened to a period of 1 to 30 seconds, which is shorter than that in the conventional method. Since heat treatment is performed at a high temperature, COPs and micro-defects which serve as nuclei of oxidation induced stacking faults can be reduced sufficiently through heat treatment for a period as long as 30 seconds.
In a silicon wafer subjected to the heat treatment according to the present invention, the density of COPs can be reduced to a sufficient level. For example, when the number of COPs in each 8-inch wafer is considered, the number of COPs decreases to 50 or less. Therefore, characteristics of a resultant device are improved, and yield of the device is increased.
As described above, in the present invention, since a silicon wafer can be subjected to high-temperature heat treatment in a reducing atmosphere through use of a rapid heating/rapid cooling apparatus to thereby reduce COPs and micro-defects which serve as nuclei of oxidation induced stacking faults in the surface layer of the silicon wafer, wafers having excellent electric characteristics can be obtained. That is, even when COPs and micro-defects which serve as nuclei of oxidation induced stacking faults are introduced into a silicon monocrystal during growth thereof and/or into a wafer during heat treatment subsequent to the growth of the silicon monocrystal, the COPs and micro-defects which serve as nuclei of oxidation induced stacking faults can be eliminated by the heat treatment of the present invention.
Since a silicon wafer subjected to the heat treatment according to the present invention has a reduced number of defects at the surface thereof, such a silicon wafer can also be used for the purpose of particle monitoring.
Moreover, since a rapid heating/rapid cooling apparatus for single-wafer processing is used, oxygen precipitation occurs to a lesser extent compared to the case of batch type heat treatment such as a conventional intrinsic gettering heat treatment. Therefore, warping of wafers, generation of slip dislocation, and other related problems can be solved. In addition, the heat treatment processing can be completed within a shortened period of time, so that productivity is improved.
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