The present invention relates to a transistor circuit for a semiconductor device with hysteresis operation, which is insensitive to noises and suitable to a semiconductor LSI.
With a current trend toward higher integration of semiconductor LSI circuits, the power consumption in an LSI chip is increasing. This results in inviting various noises in the LSI circuit and causes erroneous operation.
FIG. 1 shows an address transition detector circuit for detecting the transition of an address signal. The reference symbol Ar denotes an address signal. The reference symbol CE denotes a chip enable signal set at "L" level in a standby mode in which the internal circuit operation is inhibited. The reference symbol CE denotes an inverted chip enable signal. The reference numeral 1 denotes a NOR gate consisting of MOS transistor 11 to 14. The reference numeral 2 denotes an inverter consisting of MOS transistors 15 and 16. The reference numeral 3 denotes a pulse generator (internal circuit) being formed with MOS transistors 20 to 49, which detects a change in the potential of an inputted voltage (at node a2) and generates an output pulse (at node a11) upon detecting such a change. The reference numeral 50 denotes a power supply terminal. In a normal operation mode, signal CE is at "H" level and signal CE is at "L" level.
FIG. 2 shows the waveform of respective signals appearing in the circuit of FIG. 1. At the time when the level of address signal Ar changes from "L" to "H", node a1 is at "H", node a2 is at "L", node a3 is at "H", node a4 is at "L", and node a7 is at "H". Since node a8 is pulled up by p-channel transistor 20, the level of node a8 is "H" so that node a9 is at "L" and node a10 is at "H". Then, a clocked gate 60 is closed and a clocked gate 61 is opened, thereby establishing a positive feedback loop between nodes a5 and a6 so as to stably hold the logical state.
When address signal Ar goes to "H", node a4 goes to "H" and n-channel transistor 22 is turned on. Since node a7 is initially set at "H" and transistor 24 is turned on with the "H" of node a7, the circuit of transistors 22, 24 and 25 is activated and node a8 goes to "L". Node a9 then goes to "H", node a10 goes to "L", and clocked gate 60 is opened. In this manner, the information of changed signal Ar is transmitted through the circuit path of FIG. 1, and node a7 goes to "L" so that transistor 24 is turned off. A discharge path of transistors 22, 24 and 25 is then cut off, and node a8 is pulled up to "H" again. Along with this, node a9 goes to "L", node a10 goes to "H", and clocked gate 60 is closed to complete the series of circuit operations. During this process, node all produces a pulse PX with a certain width.
When address signal Ar goes to "L", node all similarly generates another pulse PX.
The circuit of FIG. 1 detects the transition of address signal Ar (from "L" to "H" or vice versa) and generates at node all a pluse signal PX having a certain width. This circuit may be applied to a memory circuit of internally synchronized type or the like. In such a synchronous memory circuit, the change in an address signal is generally asynchronous. For this reason, every time the address signal changes, an inner pulse is generated to initialize the internal logical state of the circuit or generated to control the circuit operation.
The circuit of FIG. 1 is generally employed in an address input section of a memory circuit, and it controls the operation of the memory circuit by pulse PX obtained at node all. Thus, to achieve an accurate operation, the pulse width and generation timing of pulses PX obtained at node all must be properly controlled, so that an accurate and stable operation of the circuit is guaranteed.
As described above, according to the FIG. 1 configuration, a change or transition in the input signal Ar is transmitted to the internal circuit 3 so that the address transition detector circuit is activated.
Assume that the potential of address signal Ar is substantially fixed at a prescribed constant level but it involves a slight potential change due to noises, etc. Such a slight potential change is not generally detected by input gate 1 and will not be transmitted to the internal circuit 3. However, if the level of signal Ar reaches a potential at which the gain or amplification factor of input gate 1 is high, said slight potential change in signal Ar is largely amplified by input gate 1, and the amplified potential change causes an erroneous detection. Namely, the pulse width, timing, etc. of pulses PX obtained by the erroneous detection are inaccurate, and the circuit cannot be operated in a normal manner.
The above description is made with reference to a case wherein signal Ar is subjected to noises. However, a similar situation may also arise when noises on a power supply line fluctuate the power supply potential for input gate 1. This is because, since the potential of an input signal is defined with respect to a power supply potential, a fluctuation in the power supply potential equivalently induces noises in the input signal. Especially, in a semiconductor LSI, a power or current consumption within the LSI chip becomes large in proportion to an increase in integration density. From this, a fluctuation in the potential of a power supply line cannot be disregarded in such an LSI. It is likely that such a situation will continue. In this manner, a conventional circuit as shown in FIG. 1 is liable to an erroneous operation due to noises or the like and a countermeasure to this problem to guarantee a stable operation has been desired.
USPTO Backgrounds
USPTO Backgrounds