1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to context aware sub-circuit layout modification.
2. Background Art
In hierarchical IC chip designs, a set of commonly used sub-circuits, such as library cells, are designed in order to maximize the design re-use and productivity. The sub-circuit layout can be used by many different circuits (macros) and IP blocks of the IC chips. In some customized IC chip designs, there are strict methodology requirements imposed on the placement and routing between the sub-circuits and the environments thereof. For example, application specific IC (ASIC) chip design methodology requires that sub-circuits must be placed in a non-overlapping fashion and design shapes must be half of a ground rule value away from the bounding box of the sub-circuits. However, in other customized designs, there is no such restriction and the interaction between the sub-circuits and their environments can be different from one circuit to another.
A circuit layout may be modified for a number of reasons, for example, to meet the ground rule constraints, to improve the performance, to migrate it from one technology to another, to fix the ground rule violations due to an engineering change order in the design flow, etc. In order to maintain the hierarchy, when a sub-circuit layout is used by multiple macros, the modified layout of the sub-circuit must be identical among all the modified macros. Therefore, usually the sub-circuit is modified first, and then maintained unchanged (frozen) when the macros are modified. Changing the layout of a sub-circuit presents a challenge because it requires the consideration of all the environment of the sub-circuit in order to get the best modified layout. For example, suppose a sub-circuit A is used by three macros M1, M2 and M3. There is no strict design methodology requirement on where and how sub-circuit A must be placed and routed in the macros, i.e., as long as it does not introduce ground rule violation, shapes from the macros can be placed at any spot with respect to sub-circuit A. In order to maintain the hierarchy, when one or more macros of M1, M2 and M3 need to be modified for layout migration from one technology to another, sub-circuit A is modified first and maintained frozen when the macros are modified. If, as shown in FIG. 1, sub-circuit A is modified independently (from A to A′ in FIG. 1) without the consideration of its interaction with all of the circuits (e.g., M1 in FIG. 1), then it is possible that some ground rule violations 10 may occur between sub-circuit A and the macros (e.g., M1 in FIG. 1) that cannot be fixed by modifying the macros due to the fact that the content of sub-circuit A is already frozen. Currently, there is no adequate technique to address this situation.
USPTO Backgrounds
USPTO Backgrounds