1. Field of the Invention
This invention relates generally to electronic driver circuits, and more particularly to a novel circuit and method for driving a display by multiplexing predetermined voltages to achieve modulation between saturation and threshold voltages of pixel electrodes in a liquid crystal display.
2. Description of the Background Art
FIG. 1 shows a single pixel cell 100 of a typical liquid crystal display. Pixel cell 100 includes a liquid crystal layer 102, contained between a transparent common electrode 104 and a pixel storage electrode 106, and a storage element 108. Storage element 108 includes complementary data input terminals 110 and 112, data output terminal 114, and a control terminal 116. Responsive to a write signal on control terminal 116, storage element 108 reads complementary data signals asserted on a pair of bit lines (B+ and B-) 118 and 120, and latches the signal on output terminal 114 and coupled pixel electrode 106.
Liquid crystal layer 102 rotates the polarization of light passing through it, the degree of rotation depending on the root-mean-square (RMS) voltage across liquid crystal layer 102. The ability to rotate the polarization is exploited to modulate the intensity of reflected light as follows. An incident light beam 122 is polarized by polarizer 124. The polarized beam then passes through liquid crystal layer 102, is reflected off of pixel electrode 106, and passes again through liquid crystal layer 102. During this double pass through liquid crystal layer 102, the beam's polarization is rotated by an amount which depends on the data signal being asserted on pixel storage electrode 106. The beam then passes through polarizer 126, which passes only that portion of the beam having a specified polarity. Thus, the intensity of the reflected beam passing through polarizer 126 depends on the amount of polarization rotation induced by liquid crystal layer 102, which in turn depends on the data signal being asserted on pixel storage electrode 106.
Storage clement 108 can be either an analog storage element (e.g. capacitative) or a digital storage element (e.g., SRAM latch). In the case of a digital storage element, a common way to drive pixel storage electrode 106 is via pulse-width-modulation (PWM). In PWM, different gray scale levels are represented by multi-bit words (i.e., binary numbers). The multi-bit words are converted to a series of pulses, whose time-averaged root-mean-square (RMS) voltage corresponds to the analog voltage necessary to attain the desired gray scale value.
For example, in a 4-bit PWM scheme, the frame time (time in which a gray scale value is written to every pixel) is divided into 15 time intervals. During each interval, a signal (high, e.g., 5V or low, e.g., 0V) is asserted on the pixel storage electrode 106. There are, therefore, 16 (0-15) different gray scale values possible, depending on the number of "high" pulses asserted during the frame time. The assertion of 0 high pulses corresponds to a gray scale value of 0 (RMS 0V), whereas the assertion of 15 high pulses corresponds to a gray scale value of 15 (RMS 5V). Intermediate numbers of high pulses correspond to intermediate gray scale levels.
FIG. 2 shows a series of pulses corresponding to the 4-bit gray scale value (1010), where the most significant bit is the far left bit. In this example of binary-weighted pulse-width modulation, the pulses are grouped to correspond to the bits of the binary gray scale value. Specifically, the first group B3 includes 8 intervals (2.sup.3), and corresponds to the most significant bit of the value (1010). Similarly, group B2 includes 4 intervals (2.sup.2) corresponding to the next most significant bit, group B1 includes 2 intervals (2.sup.1) corresponding to the next most significant bit, and group B0 includes 1 interval (2.sup.0) corresponding to the least significant bit. This grouping reduces the number of pulses required from 15 to 4, one for each bit of the binary gray scale value, with the width of each pulse corresponding to the significance of its associated bit. Thus, for the value (1010), the first pulse B3 (8 intervals wide) is high, the second pulse B2 (4 intervals wide) is low), the third pulse B1 (2 intervals wide) is high, and the last pulse B0 (1 interval wide) is low. This series of pulses results in an RMS voltage that is approximately .sqroot.2/3 (10 of 15 intervals) of the full value (5V), or approximately 4.1V.
The resolution of the gray scale can be improved by adding additional bits to the binary gray scale value. For example, if 8 bits are used, the frame time is divided into 255 intervals, providing 256 possible gray scale values. In general, for (n) bits, the frame time is divided into (2.sup.n -1) intervals, yielding (2.sup.n) possible gray scale values.
Because the liquid crystal cells are susceptible to deterioration due to ionic migration resulting from a DC voltage being applied across them, the above described PWM scheme is modified as shown in FIG. 3. The frame time is divided in half. During the first half, the PWM data is asserted on the pixel storage electrode, while the common electrode is held low. During the second half of the frame time, the complement of the PWM data is asserted on the pixel storage electrode, while the common electrode is held high. This results in a net DC component of 0V, avoiding deterioration of the liquid crystal cell, without changing the RMS voltage across the cell, as is well known to those skilled in the art.
FIG. 4 shows a response curve of an electrically controlled, birefringent liquid crystal cell. The vertical axis 402 indicates the percent of full brightness (i.e., maximum light reflection) of the cell, and the horizontal axis 404 indicates the RMS voltage across the cell. As shown, the minimum brightness (a dark pixel) is achieved at an RMS voltage Vtt. For some wavelengths of light, an RMS voltage less than Vtt results in a pixel that is not completely dark, as shown in FIG. 4. For other wavelengths all RMS voltages less than Vtt result in a dark pixel. In the portion of the curve between Vtt and Vsat, the percent brightness increases as the RMS voltage increases, until 100% full brightness is reached at Vsat. Once the RMS voltage exceeds Vsat, however, the percent brightness decreases as the RMS voltage increases.
FIG. 5 shows an RMS voltage versus gray scale value curve, for an 8-bit (256 gray scale values) gray scale system. The RMS voltage for each gray scale value ("Gray Value") is given by the following formula, where Von is the digital "on" value, typically Vdd: ##EQU1##
Gray scale value (x) corresponds to an RMS voltage equal to Vtt and, referring back to FIG. 4, to 0% brightness (i.e., minimum brightness which may not achieve exactly 0 brightness). Thus, the gray scale values less than value (x) are unusable, because for some wavelengths of light, they result in a brighter rather than a darker pixel, and for other wavelengths, the values result in 0% brightness and are, therefore, redundant. Similarly, value (y) corresponds to an RMS voltage equal to Vsat and, referring back to FIG. 4, to 100% full brightness. Thus, the gray scale values greater than value (y) are also unusable, because they result in a darker rather than a brighter pixel. The result of these wasted values is that true 8-bit gray scale resolution is not obtained.
In order to avoid gray scale distortions, all gray scale values must be confined to the useful portion of the liquid crystal response curve (FIG. 4) between Vtt and Vsat. One way to accomplish this is to add an additional bit to the gray scale code (e.g., use a 9-bit gray scale system) and then map the 8-bit values to the values of the 9-bit system corresponding to the useful portion of the response curve. The addition of a single bit, however, increases the bandwidth requirements of the data interface by 100%, and is, therefore, undesirable. What is needed is a system and method for confining all of the available gray scale values to the useful portion of the liquid crystal response curve.
In addition to the problem of confining all of the grayscale values to the useful portion of the liquid crystal response curve, it is also difficult to implement the debiasing (i.e., maintaining a net D.C. bias of 0V across the pixel cells). For example, the voltage being asserted on the common electrode cannot be changed while data is being asserted on the pixel electrodes. To do so, would change the data being asserted on the display (converting high signals to low signals and vice versa) and distort the displayed image. Further, because of the substantial amount of time required to write data to the display, it is difficult to rapidly write an "on" state or an "off" state to the entire display. Additionally, in order to invert the data in the display, the complement of the data must be written to each pixel of the display.
What is needed is a display capable of rapidly inverting the stored data, rapidly implementing on and off states, and providing write time flexibility.
USPTO Backgrounds
USPTO Backgrounds