A) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a dummy structure which does not function as part of an electronic circuit. The dummy structure is made of an active region dummy, a gate electrode dummy, a local interconnect dummy or the like.
B) Description of the Related Art
Since the recent integration degree of semiconductor integrated circuit devices is high, shallow trench isolation (STI) excellent in planarization has been adopted as isolation techniques in place of local oxidation of silicon (LOCOS). Since the gate length is becoming shorter than ever, a high patterning precision is required to form a gate electrode. Local interconnects are often used for electrically connecting electronic elements such as MOS transistors and capacitors in a local area.
For example, a buffer silicon oxide film and a silicon nitride film are formed on a silicon substrate, and an opening is formed through the silicon nitride film and the buffer silicon oxide film, the opening having a shape corresponding to an isolation region which defines active regions. By using the silicon nitride film as a mask, the silicon substrate is etched to form an isolation trench.
An insulating layer such as a silicon oxide film is deposited to bury or embed the insulating layer in the isolation trench. An unnecessary insulating film deposited on the silicon nitride film is removed by chemical mechanical polishing (CMP). With the above processes, a silicon substrate can be obtained which has a trench isolation region and a flat surface.
The silicon nitride film used as the mask is removed and necessary ion implantation is performed. Thereafter, a gate oxide film and a polysilicon film are formed on the surface of the active region. The gate oxide film and polysilicon film are patterned to form an insulated gate electrode (and word line) through anisotropic etching using a photoresist pattern. The gate electrode having a short gate length can be formed through high precision patterning.
After ions are implanted into the regions on both sides of the gate electrode to form extension regions, an insulating film such as a silicon oxide film is deposited and anisotropic etching is performed to form side wall spacers. By using the gate electrode and side wall spacers as a mask, ion implantation is performed to form high impurity concentration or deep source/drain regions. Annealing is performed to activate implanted impurity ions.
If the resistances of the gate electrode and source/drain regions are to be reduced, metal capable of silicidation such as Co is deposited on the surface of the silicon substrate and a silicide layer is formed on the silicon surface through silicidation reaction.
Thereafter, an interlevel insulating film is deposited burying or embedding the gate electrode. An irregular surface due to the gate electrode and the like is planarized by CMP. Via holes for deriving electrodes and grooves for local interconnects are formed through the interlevel insulating film by anisotropic etching. A local interconnect groove has, for example, a constant width. A metal layer such as Ti, TiN and W is deposited to bury the metal layer in the via holes and local interconnect grooves. An unnecessary metal layer deposited on the surface of the interlevel insulating film is removed by CMP or the like. Thereafter, necessary upper level wirings and an interlevel insulating film or films are formed.
Gate electrodes and local interconnects on the surface of a silicon substrate have a high integration density and require a highest precision. High precision photolithography requires a flat surface of an underlying layer. If the surface is irregular, an image transfer precision of photolithography lowers. If the distribution of the areas for gate electrodes and local interconnects (including via holes) to be etched have a variation, etch rate changes with this variation.
If the distribution of areas of an isolation region has a large variation in an STI process, the central area of the silicon oxide film buried in a trench having a large width is polished faster than other areas, resulting in dishing. In an active region having a small width sandwiched between trench portions having a large width or in a region where active regions having a small width are dense, CMP does not stop at the silicon nitride film and the active regions are polished, resulting in erosion. If the flatness of the substrate surface is lost because of such phenomena, a later lithography process for an upper layer is adversely affected.
If the distribution of via conductors and local interconnects has a variation, similar phenomena occur during CMP which is performed after a conductive layer is buried in via holes and local interconnect grooves formed through the interlevel insulating film.
In order to guarantee the surface flatness, it is desired to distribute active region dummies in addition to active regions defined by an isolation region. Similarly, it is desired to distribute local interconnect dummies when via holes and local interconnect grooves are disposed. When gate electrodes are formed, it is desired to form gate electrode dummies in order to make uniform the distribution of gate electrodes. Such dummy regions are often designed by automatic calculations. However, forming dummy regions may pose other problems.
FIGS. 7A and 7B illustrate a problem posed by forming an active region dummy. An active region AR has an exposed silicon surface defied by an isolation region. An insulated gate electrode G is formed traversing the active region AR. An n-type well NW is formed under the active region. A p-type well PW surrounds the n-type well NW. In this layout, a problem occurs if an active region dummy ARD is formed lying across the boundary between the n-type well NW and p-type well PW, as shown in FIG. 7A.
As shown in FIG. 7B, as the active region dummy ARD is formed lying across the boundary between the n-type well NW and p-type well PW and a silicide layer SIL is formed on the surface of the active region dummy, the n-type well NW and p-type well PW are electrically short-circuited by the silicide layer SIL.
FIG. 7C shows the structure of a gate electrode dummy GD formed on the surface of an isolation region STI. A similar cross sectional structure is obtained if a gate electrode extends on an isolation region. A polysilicon layer pattern is formed and a silicide layer SIL is formed on the surface of the polysilicon layer pattern.
After the active region dummy ARD and gate electrode dummy GD are formed, a local interconnect dummy LID is formed through an interlevel insulating film formed over the active region dummy ARD and gate electrode dummy GD. Since the active region dummy ARD and gate electrode dummy GD are positioned under the local interconnect dummy, these dummies ARD and GD are collectively called a lower level dummy LD.
FIG. 7D illustrates a problem posed by the active region dummy ARD and local interconnect dummy LID. In the structure similar to that shown in FIG. 7A, an active region dummy ARD1 is formed in the n-type well NW, and an active region dummy ARD2 is formed in the p-type well PW. The local interconnect dummy LID is formed at the same time when local interconnects LI1 and LI2 of an actual device are formed.
Since the local interconnect dummy LID electrically connects the active regions ARD1 and ARD2, the n-type well NW and p-type well PW are electrically short-circuited by the local interconnect dummy LID. This problem occurs when the active region dummy and local interconnect dummy are designed independently.
FIG. 7E illustratively shows another problem posed by forming dummies. A local interconnect dummy LID is disposed above lower level dummies LD and electrically connected to the lower level dummies LD. If a wiring layer is formed above the local interconnect dummy LID, parasitic capacitance is formed between the wiring layer and the local interconnect dummy LID. The parasitic capacitance is large because the local interconnect dummy LID is connected to a plurality of lower level dummies. If the distribution of parasitic capacitances is irregular, the electric characteristics of wiring layers have a variation.
There is a proposal that dummy patterns should be disposed obliquely relative to a reference axis of semiconductor elements in a semiconductor device in order to make uniform parasitic capacitances (Japanese Patent No. 3247600).
USPTO Backgrounds
USPTO Backgrounds