1. Field of the Invention
The present invention is generally directed to the field of integrated circuit devices, and, more particularly, to a transistor with an asymmetric silicon germanium source region, and various methods of making same.
2. Description of the Related Art
The manufacturing of semiconductor devices may involve many process steps. For example, semiconductor fabrication typically involves processes such as deposition processes, etching processes, thermal growth processes, various heat treatment processes, ion implantation, photolithography, etc. Such processes may be performed in any of a variety of different combinations to produce semiconductor devices that are useful in a wide variety of applications.
In general, there is a constant drive within the semiconductor industry to increase the operating speed and efficiency of various integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds and efficiency. This demand for increased speed and efficiency has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors, as well as the packing density of such devices on an integrated circuit device. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor or the thinner the gate insulation layer, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Modern field effect transistors comprise a gate electrode, a gate insulation layer, a source region and a drain region. When an appropriate voltage is applied to the gate electrode, a channel region is formed between the source region and the drain region and electrons (or holes) flow between the source region and drain region. The source and drain regions of such transistors are normally the same. For example, for an NMOS transistor, both the source and drain regions are formed by introducing an N-type dopant material, e.g., arsenic, into the semiconductor material. For a PMOS transistor, the source and drain regions are formed by introducing a P-type dopant material, e.g., boron, into the semiconductor material. In some cases, there may be a difference in the dopant concentration of the source and drain regions.
Such transistors with symmetric source and drain regions are sufficient for many applications, as evidenced by their widespread use within the industry. However, in some applications, it may be desirable to make transistors that depart from this traditional structure to enhance the performance of the device.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.
USPTO Backgrounds
USPTO Backgrounds