1. Field of the Invention
The present invention relates to a semiconductor device, more particularly a semiconductor device including an insulated gate transistor, and a manufacture method for such a semiconductor device.
2. Related Background Art
In recent years, semiconductor devices have become key devices for increasing performance of imaging devices such as image sensors and image displays.
As one example of semiconductor devices effective in improving a performance level, there is a transistor of the type that a semiconductor thin film on an insulating layer is used as an active region.
Forming single crystal Si as a semiconductor thin film on an insulating layer is widely known as a Silicon-On-Insulator (SOI) technique. A lot of studies have been focused on the SOI technique because devices utilizing it have many superior points which cannot be attained by bulk Si substrates used to manufacture ordinary Si integrated circuits. The SOI technique is practiced by, for instance, a method of condensing and irradiating an energy beam, such as an electron ray and a laser beam, onto an amorphous or polycrystal Si layer and growing a single crystal layer on SiO.sub.2 by recrystallization through melt, or a method of forming an SiO.sub.2 layer in a single crystal Si substrate by ion implantation of oxygen (called a SIMOX (Separation by Ion Implanted Oxygen) process).
Such a structure that a semiconductor thin film is formed on an insulating layer by using the SOI technique to suppress a short channel effect is proposed in, for instance, "Manufacture of very thin-film MOSFET/SIMOX with gate length of 0.15 .mu.m and its characteristics", 1991 Autumn Congress of Japanese Electron Information Communication Society, SC-9-3. This paper describes that thinning the Si layer is effective in suppression of a short channel region effect and thinning a buried oxide film below the channel region is effective in suppression of a short channel effect upon the threshold voltage. It is also described that thinning the buried oxide film raises a problem of increasing parasitic capacity associated with source and drain regions.
Furthermore, a double gate MOS has recently been also developed which includes a second gate on the side opposite to a semiconductor layer, where source and drain regions are formed, and a usual gate with insulating layer therebetween. FIG. 1 shows one example of such a double gate MOS. Denoted by reference numeral 61 is a substrate, 62 to 62" are insulating layers, 63 is a second gate, 64 is a source region, and 65 is a drain region. A source electrode 67 and a drain electrode 68 are connected to the source region 64 and the drain region 65, respectively. A portion 66 sandwiched between the source region 64 and the drain region 65 is a channel portion, and 69 denotes a first gate for controlling the channel portion. It is known that the double gate MOS have advantages of improving a short channel effect and increasing a current driving force.
USPTO Backgrounds
USPTO Backgrounds