1. Field of the Invention
This invention relates to self-aligned bipolar transistor (BT) for which the extrinsic base implant, extrinsic base silicide, and the emitter are self-aligned to one another.
2. Description of the Related Art
It has been shown that introducing a SiGe epitaxial layer to serve as the base of a bipolar transistor allows the bipolar transistor to achieve high switching speeds. By reducing the parasitic base resistance and capacitance, one can take advantage of the speed increase to further increase in the maximum oscillation frequency (fmax). One easy approach to accomplish this goal is to reduce the lateral dimensions of the transistor. Aligning one part of the transistor to another is traditionally done by lithography. In designing such a structure one must consider the alignment and critical dimension tolerance associated with the lithography processes. Integration schemes that make use of self-alignment instead of lithography, where of one part of the transistor is used to align another feature of the transistor, have proven to be efficient in reducing the lateral dimensions and increasing transistor performance.
For a conventional bipolar transistor, the extrinsic base layer is implanted after the patterning of the emitter polysilicon layer. These conventional patterning processes still rely on lithography to align the emitter polysilicon layer pattern to the emitter opening and the subsequent contact. The emitter polysilicon layer pattern is typically large enough to allow for tolerance in the lithographic processes for the emitter contact. Therefore, for this type of integration scheme, the extrinsic base implant and silicide are non-self aligned and are spaced far away from the emitter base junction, which results in high base resistance. The maximum oscillation frequency of such a non-self aligned transistor is limited by a base resistance (Rb) caused by such spacing.
The below-referenced U.S. patents disclose embodiments that were satisfactory for the purposes for which they were intended. The disclosures of the below-referenced prior U.S. patents, in their entireties, are hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art.
For example, in U.S. Pat. No. 6,534,372, the extrinsic base is delimitated by a permanent spacer formed around a temporary emitter pedestal or by the temporary emitter pedestal itself. The temporary pedestal is later removed by lithography and etching to be replaced by a polysilicon emitter. The permanent spacer must then be of sufficient width for the second lithographic pattern edge with its associated critical dimensions (CD) and alignment tolerance to be formed on top of the spacer. In addition, the spacer width has to be sufficient to provide emitter-base isolation. This adds a structural constraint on the emitter dimension and minimum distance between the heavy doped extrinsic base area and the emitter-base junction. Also, the emitter polysilicon layer and the extrinsic base silicide are defined by lithography which adds to the lateral dimension and base resistance.
In U.S. Pat. No. 6,531,720, the lateral profile of the extrinsic base doping is determined by a dual spacer formed around a temporary emitter pedestal. The emitter polysilicon layer and the extrinsic base silicide are defined by lithography which adds to the lateral dimension and the base resistance. Another drawback of this integration scheme is that the temporary pedestal lays on top of a thick stack of oxide nitride and polysilicon layers. In this case, the stack is needed to later form the emitter-base isolation and, consequently, the dopant implantation through such a thick stack have to be of high energy to achieve low base resistance in the extrinsic base region. This results in less control over the doping profile and loss of intrinsic base region due to dopant diffusion.
USPTO Backgrounds
USPTO Backgrounds