Priority is claimed to Japanese Patent Application Number JP2004-150362 filed on May 20, 2004, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a circuit device, a manufacturing method thereof, and a sheet-like board member. More specifically, the present invention relates to a circuit device having a conductive pattern isolated by isolation trenches, a manufacturing method thereof, and a sheet-like board member.
2. Related art
Conventionally, circuit devices to be set on electronic devices are expected to satisfy demands for smaller sizes, thinner profiles, and lighter weights for application to mobile telephones, portable computers, and the like.
For example, a wafer scale chip size package (referred to as CSP) having a size equivalent to a chip has been recently released.
FIG. 12 shows CSP 66 having a slightly larger size than a chip size, which adopts glass epoxy substrate 65 as a supporting substrate. Description will be made herein on an assumption that a transistor chip T is mounted on the glass epoxy substrate 65.
First electrode 67, second electrode 68, and die pad 69 are formed on a surface of this glass epoxy substrate 65, and first rear surface electrode 70 and second rear surface electrode 71 are formed on a rear surface thereof. Moreover, the first electrode 67 is electrically connected to the first rear surface electrode 70 via a through hole TH and the second electrode 68 is electrically connected to the second rear surface electrode 71 via another through hole TH. Meanwhile, the bare transistor chip T is fixed to the die pad 69, an emitter electrode of the transistor is connected to the first electrode 67 through metal thin wire 72, and a base electrode of the transistor is electrically connected to the second electrode 68 through the metal thin wire 72. In addition, the glass epoxy substrate 65 is provided with resin layer 73 so as to cover the transistor chip T.
Although the CSP 66 adopts the glass epoxy substrate 65, the CSP 66 has a simple extension structure from the chip T to the rear surface electrodes 70 and 71 for external connection in contrast to a wafer scale CSP. Accordingly, the CSP 66 has an advantage of productivity at lower costs.
However, the CSP 66 uses the glass epoxy substrate 65 as an interposer. Accordingly, the CSP 66 has limitations for achieving a smaller size and a thinner profile. For this reason, circuit device 80 which does not require an interposer has been developed. This technology is described for instance in Japanese Patent Publication No. 2002-076246 (p. 7, FIG. 1).
Referring to FIG. 13A, the circuit device 80 includes conductive pattern 81, circuit element 82 fixed onto the conductive pattern 81, metal thin wire 84 for electrically connecting the circuit element 82 to the conductive pattern 81, and sealing resin 83 for covering the circuit element 82 and the conductive pattern 81 while exposing a rear surface of the conductive pattern 81. Therefore, the circuit device 80 does not require a mounting substrate, and is formed in a thinner profile and a smaller size as compared to the CSP 66. Moreover, the above-described circuit device 80 is formed by providing isolation trenches 87 on a surface of a sheet of a conductive foil, performing fixation of the circuit element 82 and formation of the sealing resin 83, and then etching back the conductive foil until the sealing resin 83 filled in the isolation trenches 87 are exposed.
FIG. 13B shows an example of the etch-back step carried out as an experiment. Specifically, respective conductive patterns 81 are formed by etching after forming resist 90 on a rear surface of the conductive foil so as to cover regions targeted for forming the conductive patterns 81. Side surfaces of the conductive patterns 81 formed in the above-described steps have curved shapes.
In the above-described method of forming the circuit device 80, the respective conductive patterns 81 are electrically isolated from one another by use of the isolation trenches 87. But this method causes problems as described below.
Referring to FIG. 13B, side etching progresses on an interface of the resist 90, and thus an area of a rear surface of the electrode that remains after isolation becomes extremely small. Moreover, when solder resist covers the rear surface and points of solder mounting are opened, it is not possible to perform solder mounting at flat portions.
Meanwhile, due to an uneven progress of etching, the conductive foil may remain at portions of the isolation trenches 87. In such a case, the conductive patterns 81 may be electrically short circuited.
Furthermore, over-etching may be often performed to suppress the above-described problems, and the individual conductive patterns 81 may become excessively thin.
USPTO Backgrounds
USPTO Backgrounds