1. Field of the Invention
The present invention relates to an apparatus for controlling a memory device and a related method, and more particularly, to a memory controlling system for writing pixel data of pixels in a display screen into a memory device and a method thereof.
2. Description of the Prior Art
An interlacing method is always used in a memory controlling system to increase the accessing rate of a memory block. Conventionally, in an interlace system, the memory block is divided into a predetermined number of sub-memory units, and a memory controller sequentially stores the pixel data of pixels in a panel to the predetermined number of sub-memory units to increase the performance. In some applications, however, such as a mobile phone memory controller, the storing vector of the panel may not be limited to one direction, i.e., the memory controller may store the pixel data of pixels in the panel in various directions, such as from left to right, right to left, top to bottom, bottom to top, etc. Therefore, a shortcoming may emerge in the conventional interlace system when the storing procedure reaches the end of a line and the pixel data of a next line is going to be stored to the sub-memory units. More specifically, the pixel data of the first pixel in a next line may be stored into the same sub-memory unit as the pixel data of the last pixel in the previous line. When this happens, the performance will decrease.
A similar problem will occur when an active window is set to the panel. More specifically, when the pixel data of the last pixel in the active window is stored to one sub-memory unit and the pixel data of the first pixel in the active window is the next pixel data being stored to the sub-memory units, the pixel data of the first pixel in the active window may be stored to the same sub-memory unit of the pixel data of the last pixel in the active window. When this happens, the performance of storing the pixel data in the active window into the memory block will be decreased. Therefore, providing an efficient way for interlacing the memory block to solve the above-mentioned problems is a significant concern in the memory controller field.
USPTO Backgrounds
USPTO Backgrounds