Relatively high speed interfaces that use push-pull drivers such as double data rate (DDR) and DDR II memory controllers require impedance control of the I/O buffers to meet the signal integrity requirements of the interface. These interfaces generally use a reference voltage (Vref) that is centered at a mid-point of the voltage swing of the driver generating the signal.
There are two important requirements for the driver impedance control. The first requirement is that the drivers maintain tight matching of the pull-up and pull-down impedance so that the center of the voltage swing of the driver is close to the reference voltage point to maximize the voltage margin. This can be critical when dealing with signal integrity problems such as ring back.
The second important requirement for impedance control of the buffer is to maintain overall target impedance for the driver. For example, the driver may need to have an impedance of 18 Ohms +/−10%. This tolerance is looser than the requirement for pull-up/pull-down impedance matching.
Generally, a smaller die area lowers the manufacturing cost of the memory controller. As such, to drive down costs, the amount of area available to support a driver may be limited. This can be at odds with the requirement for impedance control as seen in the prior art.
One current approach to solve this problem is to use digitally controlled legs that are switched in as needed to match the target impedance. In such a solution, the control lines for the pull-up and pull-down are generally separate because the impedance characteristics for the pull-up are often times different than that of the pull-down for all process, voltage, and temperature (PVT) cases.
Digital leg selection provides relatively smaller driver sizes. The pure digital method, however, requires fine granularity to enable the pull-up and pull-down to be matched closely. The required number of independent lines for pull-down and pull-up leg selection can also cause problems with routing.
Another approach is to use a pure analog method. In this case, analog biases are adjusted to give the desired pull-up and pull-down impedance. This method provides relatively lower number of control lines with fine granularity. However, this method potentially requires a larger size driver size, in part, because the pull-up and pull-down transistors need to be increased to reach the desired impedance.
USPTO Backgrounds
USPTO Backgrounds