A Kanerva memory system is random access memory system which uses long addresses, typically in the range of 100 to 10000 bits, to store and retrieve information. Most importantly, Kanerva memories are associative such that storage locations do not have to be precisely addressed. The address space is partitioned into a number of key addresses. A set of addresses within a Hamming distance of the key address (the Hamming distance being the number of bit positions in which two N-bit binary vectors differ) "activate" that key address allowing access to a storage element associated with that key address. The Hamming distance (or radius of capture) may vary from key address to key address. Each storage element includes a series of multibit counters or registers, each storing data as a signed integer typcially represented by 2-8 binary bits. One counter or register is provided in each element for each bit position in the data words being stored/retrieved.
When an actual address is received by the Kanerva memory requesting access, a test is performed to determine which key address or addresses are activated. During a read operation a number of key addresses may be activated and a best-average value is determined for the data retrieved from the corresponding storage elements accessed. During a write to an accessed storage element, a logic 1 at a given bit position of a data word being written to the element increments the corresponding counter while a logic 0 at a given bit position decrements the corresponding counter.
Kanerva memory systems are useful many data processing applications requiring associative memory, such as pattern recognition and pattern classification. Thus, the need has arisen for a fast, simple and inexpensive implementations of Kanerva memories.
USPTO Backgrounds
USPTO Backgrounds