1. Field of the Invention
The present invention relates to a multiple-channel picture display circuit capable of displaying, on a television screen, the received pictures of a plurality of channels in the form of separate pictures.
2. Related Art Statement
A multiple-channel picture display circuit has recently been provided in order to functionally supplement channel search operations of television receivers. As shown in FIG. 1, the picture information obtained by receiving the signals of a plurality of channels are simultaneously displayed in the form of separate pictures, whereby it is possible to identify a channel with a particular signal and corresponding picture information. FIG. 1 shows an example in which multiple-channel pictures which differ from a main picture are displayed on a portion of a main picture area as sub-picture information. Japanese Patent Application No. 113612/1984 filed by Sharp Corporation (Japanese Patent Laid Open No. 257681/1985) discloses that the whole picture area of a television receiver is divided into equal parts to display multiple-channel pictures.
FIG. 2 is a block diagram showing the above-described mutiple-channel picture display circuit.
In FIG. 2, a desired channel signal is selected by means of a Tv tuner 52 to convert a high frequency signal induced in an antenna 51 into an intermediate frequency (IF) signal, and the IF signal is supplied to a video detector circuit 53. The output of the video detector circuit 53 is supplied to a main picture signal processing circuit 54 which serves to separately process a chroma signal and a luminance signal, and the supplied signal is separated into an R-Y signal, a B-Y signal, and a -Y signal. These R-Y, B-Y and -Y signals are supplied to a cathode ray tube (CRT) 56 through a picture switching circuit 55, and are reproduced on the CRT 56 as main picture information.
Reference numeral 57 denotes a time division switching circuit for converting the R-Y, B-Y, and luminance signals -Y output from the main picture signal processing circuit 54 into a time-division multiplexed signal by way of the switching operation of a multiplexer. The output of the time division switching circuit 57 is converted into a digital signal by an analog/digital converter (hereinafter referred to as the "A/D converter") 58 and is then supplied to a digital signal processing circuit 59. The digital signal processing circuit 59 generates an address signal and writes the digitized picture signal into a picture memory 60 which is provided for storing a picture to be displayed and into which picture information for multiple channels can be written. Also, the digital signal processing circuit 59 effects reading from the picture memory 60 in a controlled manner, and supplies the time division multiplexed picture signal written into the picture memory 60 to a picture switching circuit 55 through a digital/analog converter (hereinafter referred to as the "D/A converter") 61. In response to a switching control signal from the digital signal processing circuit 59, the picture switching circuit 55 selectively outputs the main picture signal and the multiple-channel picture signal by a switching operation to display a picture such as that shown in FIG. 1. During the above operation, the digital signal processing circuit 59 is supplying predetermined switching control signals to the time division switching circuit 57.
Reference numeral 62 denotes a tuning microcomputer including CPU A microcomputer 62 provides control over the receiving operation of the TV tuner 52 through a phase-locked loop (PLL) circuit 63. Also, the microcomputer 62 supplies a write enable signal to the aforesaid digital processing circuit 59. The digital signal processing circuit 59 effects writing into the picture memory 60 while the write enable signal is present.
Reference numeral 64 denotes a synchronizing separator circuit for separating a synchronizing signal from the output from the video detector circuit 53. Horizontal and vertical synchronizing signal components HD and VD, which have been output from the synchronizing separator circuit 64, are supplied to the digital signal processing circuit 59. The digital signal processing circuit 59 utilizes the synchronizing signal components HD and VD as a synchronizing signal which constitutes a reference signal for generating the write address signal mentioned above.
FIG. 3 is a timing chart which diagrammatically shows the operation of displaying four-channel multiple pictures such as those shown in FIG. 1. In FIG. 3, part A shows a receiving operation through which the received signals supplied from the PLL circuit 63 are sequentially switched from one channel to another to allow individual channels to be received in the order of, for example, channel 1, channel 2, . . . , at predetermined time intervals Part B represents the write enable signal from the microcomputer 62, and the write enable signal is generated each time one channel is received. As shown in Part C, the write operation is effected in synchronization with the period of generation of the write enable signal, and the received signal of channels 1 to 4 can be written into the picture memory 60.
FIG. 4 shows an address map used for writing the received picture information for four pictures of the channels 1 to 4.
Parts a, b, c and d correspond to channels 1, 2, 3 and 4, respectively. As can be seen from FIG. 4, the number of addresses assigned to the received signal of each channel is fifty six per horizontal trace period.
First, when the picture information of channel 1 is to be written, the digital signal processing circuit 59 processes the vertical synchronizing signal of channel 1 and resets the value of its vertical address counter to address "0". Each time the horizontal synchronizing signal component HD of channel 1 is processed in the digital signal processing circuit 59, the vertical address counter increments its count by (+) 168 and effects writing of picture information for one horizontal trace period. When such horizontal writing is repeated and a picture for one field is written, the vertical address counter increments the write address by (-) 24920 and resets the value of the write address to "0". Thus, writing of picture information for the next field is again carried out. When the microcomputer 62 stops generating the write enable signal, the digital signal processing circuit 59 processes the next vertical synchronizing signal component VD after having completely written the one-field picture information of channel 1, and increments the value of the write address counter by (-) 24864. Thus, the write address counter is set to "56" which is a write start address for channel 2.
When the writing operation proceeds from channel 1 to channel 2, channel 2 is received through the PLL circuit 63 under the control of the microcomputer 62. When channel 2 is received, the microcomputer 62 outputs a write enable signal and the vertical address counter writes the received signal of channel 2 from write address 56 into the picture memory 60. Writing of channels 3 and 4 is also effected in a similar manner.
The resultant address allocation in the picture memory 60 is as follows: The addresses assigned to the right-hand end of the picture area of channel 1 coincide with those assigned to the left-hand end of the picture area of channel 2, the addresses assigned to the right-hand end of the picture area of channel 2 coincide with those of the left-hand end of the picture area of channel 3, the addresses assigned to the right-hand end of the picture area of channel 3 coincide with those of those assigned to the left-hand end of the picture area of channel 4, and the addresses assigned to the right-hand end of the picture area of channel 4 coincide with those assigned to the left-hand end of the picture area of channel 1. Accordingly, the multiple-channel picture display area is divided into four segments. This address allocation makes it easy to count, during readout operation, readout addresses by utilizing, as triggers, the horizontal synchronizing signal components contained in the main picture signal.
An address counting operation for one horizontal retrace period will now be explained with reference to FIG. 5. In FIG. 5, part (a) represents a horizontal synchronizing signal output, and part (b) represents the period of write operation corresponding to part (a). The digital signal processing circuit 59 utilizes the horizontal synchronizing signal component HD as a trigger to cause the write address counter to execute a counting operation. During the period of the horizontal synchronizing signal component HD, no clock for address counting is generated. When the process proceeds to the succeeding horizontal trace period after the aforesaid period has passed, a clock for address counting is generated. In general, the length of a horizontal retrace period is 16% of one horizontal trace period of duration 63.5 .mu.sec. Accordingly the period of the signal component HD is approximately 10.2 .mu.sec and an available picture area period is therefore approximately 53.3 .mu.sec. The length of a write period TW is determined by an overscanning ratio. In this example, if the horizontal overscanning ratio is assumed to be 10%, the write period TW of the received signal is ##EQU1##
From (53.3-48.0)/2, a write stop period Ts within the available picture area period is EQU Ts=2.67 .mu.sec (2)
In other words, in order to accommodate the overscanning ratio, the digital signal processing circuit 59 writes, into the picture memory 60, one-horizontal-trace signal which excludes its leading portion of duration of approximately 2.67 .mu.sec which follows the leading signal component HD and its trailing portion of duration of approximately 2.67 .mu.sec which is followed by the trailing signal component HD.
It is assumed here that a channel with no signal has been received. In this case, the synchronizing separator circuit 64 outputs noise as its synchronizing signal output, but noise pulses each having duration close to one horizontal trace period appear because of the nature of a time-constant circuit for use as the synchronizing separator. Although depending upon the performance of the synchronizing separator circuit 64, the period of such a noise pulse commonly deviates from a normal period by an amount of .+-.2 .mu.sec to .+-.4 .mu.sec.
Accordingly, if the period of the noise pulse becomes shorter than the normal period by Ts (2.67 .mu.sec) or more (for example, by 4 .mu.sec) as shown by the dashed line of FIG. 5(a), the digital signal processing circuit 59 will increment the write address by (+) 168 due to the generation of the noise pulse before the number of addresses (fifty six) required for one horizontal trace period has been counted. This leads to the phenomenon in which no picture data for the next horizontal trace period is written to predetermined addresses; for example, picture data of a channel with no signal is written to addresses to which picture data of a channel with a particular signal is to be written. As a result, in a multiple-channel display mode, a number of malfunctions may take place; for example, a picture pattern is offset from a corresponding display frame, and a picture of a channel with no signal may be displayed at a display position allocated for a channel with a particular signal.
In order to prevent such malfunctions from occurring when a channel with no signal is received, it is possible to utilize a method in which the write stop period Ts is set to a period longer than the aforesaid period 2.67 .mu.sec, for example, about 4.5 .mu.sec to about 5 .mu.sec so that the counting of the required number (fifty six) of write addresses can be completed even if the amount of dispersion of the period of the synchronizing signal component HD becomes small by a maximum of 4 .mu.sec. However, the fact that the write stop period Ts is set to a somewhat long period means that the write period TW is shortened, causing the picture information to be lost by an amount equivalent to not less than the overscanning ratio of 16%. As a result, the amount of information will be insufficient.
As described above, television receivers of the type having the conventional multiple-channel picture display function have the problem that malfunctions in writing are caused by the dispersion of the horizontal synchronizing component HD due to noise pulses during the reception of a channel with no signal. Moreover, if the write stop period is extended and the write period TW is shortened, it is necessary to eliminate the portion of a picture which exceeds the overscanning ratio. The result is a lack of the amount of information.
USPTO Backgrounds
USPTO Backgrounds