1. Field of the Invention
The present invention relates to a clock synchronous serial information transfer apparatus comprising, a transmit unit (hereinafter, referred to as a transmit unit of a clocked Serial I/O) and a receiving unit (hereinafter referred to as a receiving unit of a clocked serial I/O, or when designating a clock synchronous serial information transfer apparatus referred to as a clocked serial I/O), and particularly to a clocked serial I/O in the case, where noises occur in a communication reference signal (hereinafter, referred to as a communication clock) for synchronism.
2. Description of the Related Art
In a microcomputer, when communicating information with peripherals and other microcomputers, there are a method of transmitting and receiving data in parallel and a method of transmitting and receiving data in series. In the parallel and serial transmissions and receptions, more data can be transferred per unit time in the case of using the parallel transmitting and receiving. However, when considering a communication cost, more wirings are required in the parallel transmitting and receiving, thus the cost increases. So there is a field accepting the serial transmitting and receiving in which less wirings is required even though a transfer rate is low.
However, also in the serial transmitting and receiving, there are the clocked serial I/O which uses a communication clock and transmits and receives data in synchronism with the communication clock, and an asynchronous serial information transmitting and receiving which transmits and receives data without using the communication clock. Also in this case, the transfer rate and the number of wirings are related to each other; the higher transfer rate is the clocked serial I/O and the less wirings is the asynchronous serial information transmitting and receiving. And hence, in the field where the wirings are few and the transfer rate is high, the clocked serial I/O is frequently used.
Next, the operation of the above-mentioned clocked serial I/O is briefly described.
FIG. 1 is a schematic view showing connection between the transmit unit and the receiving unit of the clocked serial I/O.
In FIG. 1, numeral 1 designates the transmit unit of the clocked serial I/O, numeral 2 designates the receiving unit of the clocked serial I/O, numeral 3 designates the communication clock outputted from the receiving unit 2 of the clocked serial I/O and inputted to the transmit unit 1 of the clocked serial I/O, numeral 4 designates a communication enable outputted from the transmit unit 1 of the clocked serial I/O and inputted to the receiving unit 2 of the clocked serial I/O, and numeral 5 designates communication data outputted from the transmit unit 1 of the clocked serial I/O and inputted to the receiving unit 2 of the clocked serial I/O.
The operation is described with reference to a timing chart shown in FIG. 2. In the timing chart shown in FIG. 2, a signal flow is shown as a time lapse from left to right.
When the transmit unit 1 of the clocked serial I/O transmits data "b00110110" (b indicates that following numerals are binary), at first, the communication enable 4 is changed to a low level from a high level. The receiving unit 2 of the clocked serial I/O starts the communication clock 3 when recognizing that the communication enable 4 is at the low level. Responding to the low level of the communication clock 3, the transmit unit 1 of the clocked serial I/O brings the communication enable 4 to the high level, and outputs the low level as the communication data 5. The receiving unit 2 of the clocked serial I/O brings the communication clock 3 to the high level, and receives information of the communication data 5 at the timing thereof. Since it is at the low level in this case, "0" is recognized.
Next, in order to have the next data being transferred, the receiving unit 2 of the clocked serial I/O brings the communication clock 3 to the low level. Since the transmit unit 1 of the clocked serial I/O transmits the next data "0" responding to the low level of the communication clock 3, the communication data 5 is kept at the low level. Next, the receiving unit 2 of the clocked serial I/O brings the communication clock 3 to the high level, and receives information of the communication data 5 at the timing thereof. Since it is at the low level in this case, "0" is recognized.
Next, the receiving unit 2 of the clocked serial I/O brings the communication clock 3 to the low level to have the third data being transferred. Responding to the low level of the communication clock 3, the transmit unit 1 of the clocked serial I/O brings the communication data 5 to the high level to transmit the next data "1". The receiving unit 2 of the clocked serial I/O brings the communication clock 3 to the high level, and receives information of the communication data 5 at the timing thereof. Since it is at the high level in this case, "1" is recognized. As such, the receiving unit 2 of the clocked serial I/O receives fourth to eighth data, thereby the data "b00110110" is transferred.
Next, a circuit configuration in the transmit unit 1 of the clocked serial I/O, and the operation to output data responsive to the communication clock 3 are described with reference to FIG. 3 and FIG. 4.
In FIG. 3, numeral 6 designates a control signal circuit, which receives an input signal and outputs two control signals. The control signal circuit 6 is constituted by a NAND element 7 which obtains a NAND logic of the communication clock 3 and an enable signal, which decides to operate the transmit unit 1 of the clocked serial I/O or not, and an inverter element 8 which inverts an output of the NAND element 7.
Numerals 9a to 16a and 9b to 16b designate latch circuits which change outputs thereof responsive to the control signals outputted from the control signal circuit 6. Where, the control signal outputted from the inverter element 8 of the control signal circuit 6 controls the latch circuits 9a to 16a, and the control signal outputted from the NAND element 7 of the control signal circuit 6 controls the latch circuits 9b to 16b.
These latch circuits are interconnected as follows; an output of the latch circuit 16a is inputted to the latch circuit 16b, an output of which is inputted to the latch circuit 15a, an output of which is inputted to the latch circuit 15b, an output of which is inputted to the latch circuit 14a, an output of which is inputted to the latch circuit 14b, an output of which is inputted to the latch circuit 13a, an output of which is inputted to the latch circuit 13b, an output of which is inputted to the latch circuit 12a, an output of which is inputted to the latch circuit 12b, an output of which is inputted to the latch circuit 11a, an output of which is inputted to the latch circuit 11b, an output of which is inputted to the latch circuit 10a, an output of which is inputted to the latch circuit 10b, an output of which is inputted to the latch circuit 9a, and an output of which is inputted to the latch circuit 9b. An output Dout of the latch circuit 9b is outputted as the communication data 5.
For the convenience' sake of description, the signals are coded so that FIG. 3 and FIG. 4 correspond with each other. An output of the inverter element 8 is designated CLKa, and an output of the NAND element 7 is designated CLKb, the output of the latch circuit 9a is designated a, the output of the latch circuit 10b is designated b, the output of the latch circuit 10a is designated c, and output of the latch circuit 11b is designated d, the output of the latch circuit 11a is designated e, the output of the latch circuit 12b is designated f, the output of the latch circuit 12a is designated g, the output of the latch circuit 13b is designated h, the output of the latch circuit 13a is designated i, the output of the latch circuit 14b is designated j, the output of the latch circuit 14a is designated k, the output of the latch 15b is designated l, the output of the latch circuit 15a is designated m, the output of the latch circuit 16b is designated n and the output of the latch circuit 16a is designated o.
Since occurrence of noises in the communication clock 3 is different at the time point outputted from the receiving unit 2 of the clocked serial I/O and at the time point inputted to the transmit unit 1 of the clocked serial I/O, the communication clock 3 seen at the transmit unit 1 of the clocked serial I/O is designated CLKin to distinguish the difference.
FIG. 5 shows an example of configuration of the latch circuit 9a to 16a and 9b to 16b.
In this example, the latch circuits are that, when an input signal to a control terminal CT is at the high level, a data value inputted to an input terminal IT is outputted intact to an output terminal OT, and when the input signal to the control terminal CT is at the low level, a value being outputted at that time point is continuously outputted from the output terminal OT independently of the state of input data to the input terminal IT.
Next, the operation of the configuration shown in FIG. 3 is described using the same data "b00110110" as the case of the description of FIG. 1.
At first, data are latched in the latch circuits as follows; "0" is latched in the latch circuit 10b, "0" is latched in the latch circuit 11b, "1" is latched in the latch circuit 12b, "1" is latched in the latch circuit 13b, "0" is latched in the latch circuit 14b, "1" is latched in the latch circuit 15b, "1" is latched in the latch circuit 16b and "0" is latched in the latch circuit 16a.
Since the CLKa is valid and the CLKb is invalid, outputs from the latch circuits are that; a is "0", b is "0", c is "0", d is "0", e is "1", f is "1", g is "1", h is "1, i is "0", j is "0", k is "1", l is "1", m is "1", n is "1" and o is "0".
This state is a state shown in a leftmost first cycle in FIG. 4. Hereupon, though the output Dout is designated "X", it means that the output Dout may be either "1" or "0".
Next, when the communication clock 3 changes to the low level from the high level, the CLKin transits to the low level from the high level, responding thereto the CLKa changes to invalid from valid and the CLKb changes to valid from invalid. Thereby, the latch circuits 9a to 16a latch the inputs respectively and the latch circuits 9b to 16b transmit the inputs to the outputs respectively.
This state is a state shown in a second cycle in FIG. 4. The outputs are that, Dout is "0", a is "0", b is "0", c is "0", d is "1", e is "1", f is "1", g is "1", h is "0", i is "0", j is "1", k is "1", l is "1", m is "1", n is "0" and o is "0". Data are shifted between the latch circuits in such a manner.
The case where the noises occur in the communication clock 3 is described. This state is shown in a sixth cycle and a ninth cycle in FIG. 4.
In the case of sixth cycle, the noise occurs at the low level of the communication clock 3, and the CLKin instantaneously becomes high level, the CLKa becomes high level instantaneously and the CLKb becomes low level instantaneously. In this case, as is shown in FIG. 4, data proceeds by one. In such case, data received by the receiving unit 2 of the clocked serial I/O is finally "b001010XX", and the data is not transmitted and received correctly.
As such, in the conventional apparatus, such a problem was encountered that, when the noise occurs in the communication clock 3, erroneous data is transmitted and received.
USPTO Backgrounds
USPTO Backgrounds