1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device capable of speeding up a determination of a reading voltage, thereby making operations of reading stored information faster.
2. Description of the Related Art
In semiconductor memory devices, acceleration of access time required for reading and writing stored information is a significant challenge in order to improve their performance. It is needless to say that a same goes for non-volatile semiconductor memory devices such as a flash memory or a like.
In recent years, there is a tendency that a structure of the non-volatile semiconductor device is scaled down to increase a storage capacity, which presents a problem of drain disturbance.
For example, in a case of the flash memory, since application of a high voltage to a drain of a scaled-down floating gate-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) constituting a memory cell becomes difficult, it is necessary to discriminate the memory cell (hereinafter may be also referred to as an "OFF-cell") in a state where an electric charge has been injected into a floating gate by using a low voltage of, for example, about 0.5 V as a bias voltage to be applied to the memory cell causing a current not to flow from a memory cell (hereinafter may be also referred to as an "ON-cell") in a state where the electric charge has been drawn from the floating gate, allowing the current to flow. It is, therefore, required that a small difference in voltages for reading stored information from the memory cell be reliably detected and time required for determination of an outputting state be shortened as much as possible in order to enable a high speed reading.
Circuit configurations and one example of operations of a conventional non-volatile semiconductor memory device will be hereinafter described.
FIG. 8 is a schematic circuit diagram showing an example of configurations of a reading circuit in the conventional non-volatile semiconductor memory device. FIG. 9 is a graph for explaining operations of a feedback-type bias circuit. FIG. 10 is a schematic block diagram of a reading timing generating circuit used for the conventional non-volatile semiconductor memory device. FIG. 11 is a timing chart showing reading operations in the conventional non-volatile semiconductor memory device. FIGS. 12A, 12B are diagrams explaining determination of an outputting state for reading in the conventional non-volatile semiconductor memory device.
As shown in FIG. 8, the reading circuit in the conventional non-volatile semiconductor memory device is chiefly composed of a memory cell M.sub.mn shown as a representative one selected from a memory cell array (not shown) by a bit line BL.sub.m and a word line WL.sub.n, a bit line decoder BDE.sub.m shown as a representative one used to select the bit line BL.sub.m, a feedback-type bias circuit 1, a load circuit 2, a pre-charging circuit 3, a sense circuit (SA) 4 and a latch circuit 5.
Also, as depicted in FIG. 8, the feedback-type bias circuit 1 has N-channel transistors 11, 12, 13 and 14 and P-channel transistors 15 and 16. A drain of the N-channel transistor 11 is connected to the load circuit 2 and a connecting point between the N-channel transistor and the load circuit 2 is hereinafter called "node C". A source of the N-channel transistor 11 is connected to the bit line decoder BDE.sub.m and a connecting point between them is hereafter called "node B". A gate of the N-channel 11 is connected to a drain of the N-channel transistor 14 and a connecting point between them is hereafter called "node A". A source of the P-channel transistor 15 is connected to a power source V.sub.DD, its drain is connected to a node A and its gate is connected to a line of a sense amplifier activating signal SAE. A source of the P-channel transistor 16 is connected to the power source V.sub.DD, its drain is connected to a drain of the N-channel transistor 12 and its gate is connected to a line of the sense amplifier activating signal SAE. A gate of the N-channel transistor 12 is connected to its drain and its source is connected to the node A. A drain of the N-channel transistor 13 is connected to the node A, its source is connected to a ground and its gate is connected to a line of the sense amplifier activating signal SAE. A drain of the N-channel transistor 14 is connected to the node A, its source is connected to the ground and its gate is connected to the node B.
The load circuit 2 has a P-channel transistor 21 and an N-channel transistor 22. A source of the P-channel transistor 21 is connected to the power source V.sub.DD, its drain is connected to a drain of the N-channel transistor 22 and its gate is connected to a line of the sense amplifier activating signal SAE. A gate of the N-channel transistor 22 is connected to its drain and its source is connected to the node C. The pre-charging circuit 3 has a P-channel transistor 31 and an N-channel transistor 32. A source of the P-channel transistor 31 is connected to the power source V.sub.DD, its drain is connected to a drain of the N-channel transistor 32 and its gate is connected to a line of a bit line pre-charging signal ATDP. A source of the N-channel transistor 32 is connected to the node B and its gate is connected to the node A.
The sense circuit 4 is composed of a comparison circuit used to compare a reference voltage V.sub.REF from a reference circuit (not shown) with an output voltage V.sub.A at the node C connected to the drain of the N-channel transistor 11 of the feedback-type bias circuit 1 and to produce a signal showing a result of comparison. The latch circuit 5 is composed of a circuit used to latch an output of the sense circuit 4 in response to a sense amplifier output latching signal LAT.
The feedback-type bias circuit 1 has a function to supply a predetermined bias voltage V.sub.B to the memory cell M.sub.mn. The load circuit 2 functions as a load by acting as a source of a constant current provided by the power source V.sub.DD to the feedback-type bias circuit 1. The pre-charging circuit 3 is used to supply a pre-charging current to the bit line BL.sub.m when the bit line BL.sub.m is selected. The sense circuit 4 is adapted to judge whether the memory cell M.sub.mn is in the ON-cell state or in the OFF-cell state by comparing the reading output voltage V.sub.A from the feedback-type bias circuit 1 with the reference voltage V.sub.REF from the reference circuit (not shown). The latch circuit 5 is adapted to latch a signal showing a judging result from the sense circuit 4 and to generate output data. In the feedback-type bias circuit 1, while reading is not performed, since the sense amplifier activating signal SAE is high and the P-channel transistors 15 and 16 are turned OFF and the N-channel transistor 13 is turned ON, a voltage V.sub.F at the node A is almost 0 (zero) volts and, since the N-channel transistor 11 is in an OFF state, the voltage V.sub.B of the feedback-type bias circuit is 0 (zero) volts. On the other hand, while the reading is being performed, since the sense amplifier activating signal SAE is low, the P-channel transistors 15 and 16 are turned ON and the N-channel transistor 13 is turned OFF and, since a current flowing from the power source V.sub.DD through a switch composed of the P-channel transistor 15 and a current flowing from the power source V.sub.DD through a switch composed of the P-channel transistor 16 and through a constant current source load composed of the N-channel transistor 12 flows into the N-channel transistor 14, the voltage V.sub.F generated at the node A is supplied to the gate of the N-channel transistor 11. Though this causes a current to flow through the N-channel transistor 11 and the predetermined bias voltage V.sub.B to be generated at the node B, since a line for the predetermined bias voltage V.sub.B is connected to the gate of the N-channel transistor 14, a current flowing through the N-channel transistor changes depending upon the predetermined bias voltage V.sub.B and therefore the voltage V.sub.F at the node A to be supplied to the gate of the N-channel transistor 11 changes. Since such feedback control as above is exercised, the predetermined bias voltage V.sub.B at the node B becomes almost constant in a steady state.
FIG. 9 is a praph explaining a distribution of a current at each of components, shown in FIG. 8, contained in the feedback-type bias circuit 1 during operations. In FIG. 9, "I.sub.a " represents currents corresponding to a voltage V.sub.DS between the drain and source of the N-channel transistor 14, and "I.sub.a1 " to "I.sub.a6 " represent characteristics of currents flowing through the N-channel transistor 14 which changes depending upon different voltages (V.sub.G1 to V.sub.G6) of the gate, while "I.sub.b " represents currents corresponding to a voltage V.sub.DS between the drain and source of the P-channel transistor 15, and "I.sub.c " represents characteristics of currents flowing through the circuit composed of the P-channel transistor 16 and the N-channel transistor 12. "I.sub.b +I.sub.c " represents a sum of currents flowing through the P-channel transistor 15, a current flowing through the P-channel transistor 16 and a current flowing through the N-channel transistor 12. At this point, the predetermined bias voltage V.sub.B at the node B is determined as a gate voltage (V.sub.G) of the N-channel transistor 14 at a point P where the current I.sub.a and the current I.sub.b +I.sub.c reach an equilibrium.
In the load circuit 2, while reading is performed, since the sense amplifier activating signal SAE goes high and the P-channel transistor 21 is turned ON, a current I.sub.1 is supplied from the power source V.sub.DD through the N-channel transistor 22 constituting the constant current source load to the N-channel transistor 11 of the feedback-type bias circuit 1.
The pre-charging circuit 3 has a function to speed up a rise in the predetermined bias voltage V.sub.B at the node B at the time of reading operation by supplying a current I.sub.2, which flows when the P-channel transistor 31 is turned ON after the bit line pre-charging signal ATDP goes low in an early stage of a read-out cycle, to the bit line through the N-channel transistor 32 operating in tandem with the N-channel transistor 11 of the feedback-type bias circuit 1.
A pre-charging circuit being similar to that described above is disclosed in, for example, Japanese Laid-open Patent Application No. Hei2-285593.
The sense circuit 4 is used to produce an output signal having a logical level being changed depending upon a level of the voltage V.sub.A relative to the reference voltage V.sub.REF by comparing the voltage V.sub.A at the node C with the reference voltage V.sub.REF from the reference circuit (not shown).
The latch circuit 5, by latching an output signal from the sense circuit 4 in response to the sense amplifier output latching signal LAT, is operated to output data "1" when the memory cell is in the ON-cell state and data "0" when the memory cell is in the OFF-cell state.
Next, operations of the reading circuit in the conventional non-volatile semiconductor device by referring to FIG. 8 will be described below.
In the bit line decoder BDE.sub.m, when the bit line BL.sub.m is selected, the bit line selection signals a1 and a2 are high, the bit line selection transistors Tm1 and Tm2 are turned ON and the memory cell M.sub.mn is connected to the bit line BL.sub.m. Moreover, by selecting the word line WL.sub.n, the memory cell M.sub.mn is in a state allowing reading-out of either an ON-state or OFF-state.
In the early stage of the read-out cycle when the sense amplifier activating signal SAE goes high, the predetermined bias voltage V.sub.B of the node B becomes 0 (zero) volts. At this point, since the N-channel transistor 14 in the feedback-type bias circuit 1 is turned OFF and the voltage V.sub.F of the node A is maximum, the N-channel transistor 11 is turned ON and the current I.sub.1 becomes maximum.
This causes an additional capacitor (having wiring capacitance, drain capacitance of the memory cell M.sub.mn or a like) of the bit line BL.sub.m to be pre-charged, resulting in a gradual increase in the voltage V.sub.B at the node B. When the predetermined bias voltage V.sub.B increases, a current flows through the N-channel transistor 14 and the voltage V.sub.F at the node A decreases, causing the current I.sub.I of the N-channel transistor 11 to decrease. Also, when feedback operations of the feedback-type bias circuit 1 converge on termination and the predetermined bias voltage V.sub.B at the node B reaches a predetermined memory cell drain voltage (for example, 0.5V), the memory cell M.sub.mn is in a state where a current can flow and, if it is in the ON-cell state, a memory cell current flows through the N-channel transistor 11, while, if it is in the OFF-cell state, the memory cell current does not flow. Therefore, since the voltage V.sub.A at the node C increases if the memory cell M.sub.mn is in the OFF-cell state (in an OFF-voltage state) and the voltage decreases if the memory cell M.sub.mn is in the ON-cell state (in an ON-voltage state), when an intermediate voltage between the ON voltage and the OFF voltage is produced as a reference voltage V.sub.REF from the reference circuit (not shown), the sense circuit 4 is adapted to compare the voltage V.sub.A with the voltage V.sub.REF and to produce an output showing the discrimination between the OFF-cell state and ON-cell state.
The latch circuit 5 is operated to latch an output signal of the sense circuit 4 in response to the sense amplifier output latching signal LAT and to output data "0" when the memory cell is in the OFF-cell state and data "1" when the memory cell is in the ON-cell state. In a pre-charging circuit 3 shown in FIG. 8, during a short time in the early stage of the read-out cycle when the sense amplifier activating signal SAE is active, the bit line pre-charging signal ATDP is low and the P-channel transistor 31 is turned ON causing the current I.sub.2 to be supplied from the power source V.sub.DD to the bit line for pre-charging through the N-channel transistor 32 controlled in tandem with the N-channel transistor 11, which causes the rise of the predetermined bias voltage V.sub.B at the node B to be speeded up and the speed for the determination of the voltage V.sub.A at the node C to be improved.
FIG. 10 is a schematic block diagram of a reading timing generating circuit in the reading circuit shown in FIG. 8. The reading timing generating circuit is chiefly composed of an address change detecting signal generating circuit 101 and a pulse generating circuit 102. The address change detecting signal generating circuit 101 has an address change detecting circuit 103 adapted to detect a change point of address data contained in an external address inputting signal AO and to produce an address change detecting signal OS. The pulse generating circuit 102 is operated to produce, by internal pulse generating circuits (not shown) embedded therein and in response to the address change detecting signal OS, the sense amplifier activating signal SAE used to activate the reading circuit, the bit line pre-charging signal ATDP used to activate the pre-charging circuit 3 in the early stage of the read-out cycle when the sense amplifier activating signal SAE remains active and the sense amplifier output latching signal LAT used to latch an output from the sense circuit 4 at the latch circuit 5.
Next, reading operations in the conventional non-volatile semiconductor memory device will be described by referring to FIG. 11. A signal of each of components of the reading circuit in the conventional non-volatile semiconductor memory device shown in FIG. 8 are shown in FIG. 11. In response to external address inputting signals AO to Ai, from the address change detecting signal generating circuit 101 (FIG. 10) is outputted the address change detecting signal OS, which causes the sense amplifier activating signal SAE from the pulse generating circuit 102* (FIG. 10) (in the drawings, a symbol "*" represents an inverted signal), the bit line pre-charging signal ATDP* and the sense amplifier output latching signal LAT to be produced. In the reading circuit shown in FIG. 8, the sense amplifier activating signal SAE* and the bit line pre-charging signal ATDP* are inputted as notinverted signals and an inactive state is changed to an active state.
In the feedback-type bias circuit 1, when the sense amplifier activating signal SAE* is generated, the P-channel transistors 15 and 16 are turned ON and the N-channel transistor 13 is turned OFF, which causes the current I.sub.1 to be supplied to the bit line through the load circuit 2 and then the N-channel 11. When the bit line pre-charging signal ATDP* is produced in the early stage of the period when the sense amplifier activating signal SAE* is active, the current I.sub.2 flows from the pre-charging circuit 3 through the bit line. Therefore, a current I.sub.M (=I.sub.1 +I.sub.2) flows through the bit line and the pre-charging is done. When the feedback operation in the feedback-type bias circuit 1 is complete and the pre-charging by the pre-charging circuit 3 is then complete, the voltage V.sub.A at the node C is determined to be an OFF-bit potential V.sub.A (OFF) or an ON-bit potential V.sub.A (ON) depending upon the OFF-state or ON-state of the memory cell. The latch circuit 5 is operated to latch an output of a sense circuit 4 in response to the sense amplifier output latching signal LAT. However, though the conventional non-volatile semiconductor memory device shown in FIG. 8 is provided with the pre-charging circuit 3 to shorten time required for pre-charging the bit line, since much time is required before the reading of data becomes enabled after the bit line is pre-charged, the speed-up of operations in the non-volatile semiconductor memory device is interfered with.
FIGS. 12A and 12B are enlarged views showing changes in voltages and currents occurring when a reading output is generated in the reading circuit of the conventional non-volatile semiconductor memory device shown in FIG. 8 and also explaining the determination of outputted states, in which FIG. 12A shows changes in voltages and FIG. 12B shows changes in currents. In the conventional reading circuit shown in FIG. 8, read-out data is determined after a certain period of time elapses since the bit line pre-charging signal ATDP becomes inactive. As reasons for such delays in the determination of the read-out data in the conventional reading circuit, following two points can be considered.
(1) In the pre-charging circuit 3, when the bit line pre-charging signal ATDP has become inactive and the P-channel transistor 31 has been turned OFF, a potential on the outputting side (i.e., at the drain) of the P-channel transistor 31 rises to the power source voltage V.sub.DD. Since there is the additional capacitor having the wiring capacitance, drain capacitance or a like on the outputting side of the P-channel transistor 31, the current I.sub.2 flows, after the bit line pre-charging signal ATDP becomes inactive, by an electrical charge occurring during charging of the capacitor so that its potential rises to the power source voltage V.sub.DD. However, since a current I.sub.M flowing through the bit line is constant, time is required before a cell current I.sub.1 (it is a memory cell current at this point) flowing through the N-channel transistor 11 decreases and the ON-bit potential V.sub.A (ON), which is a reading voltage used when the memory cell is in the ON-cell state, is determined. In FIG. 12B, "t" represents time causing a decrease in data reading speed, based on the current I.sub.2, appearing after the bit line pre-charging signal ATDP becomes inactive. PA1 (2) When the output of the feedback-type bias circuit 1 is turned OFF, the bit line is pre-charged until the predetermined bias voltage V.sub.B at the node B is changed to its OFF level and, in this state, the voltage V.sub.A at the node C is determined. The same operations as above are carried out in the reference circuit (not shown) generating the reference voltage V.sub.REF. In the sense circuit 4, a comparison between the voltage V.sub.A and the voltage V.sub.REF is made, however, at this point, since the voltage V.sub.A at the node C rises to a level (i.e., a differential operation point) exceeding that allowing the comparison operations of the sense circuit 4, much time is required before the voltage V.sub.A reaches a value at a differential operation point, thus causing the decrease in the reading speed. In order to decrease a difference between the ON-bit potential and OFF-bit potential in the voltage V.sub.A at the node C, a load used to flow a leak current is connected to the bit line, however, if the current I.sub.1 flowing through the feedback-type bias circuit 1 is 0 (zero), the voltage V.sub.A at the node C rises nearly to the power source voltage V.sub.DD. This is because it takes time for the voltage V.sub.A at the node C that is raised by over-charging to drop to the differential operation point value due to flowing of a current through the N-channel transistor 11 and due to drawing of electrical charges from the node C having the voltage V.sub.A. In contrast, in the reference circuit, since the memory cell being in the ON-cell state is always connected, no rise occurs in the voltage V.sub.REF. PA1 a bias voltage supplying circuit for supplying a predetermined bias voltage to a bit line by letting a current flow from a load circuit, in response to a first timing signal produced when an address of a memory cell is selected, to the memory cell to be connected to the bit line by a bit line selecting circuit in accordance with selection of the address and for generating a reading voltage at a point of connection with the load circuit by letting a current flow in accordance with an ON-state or OFF-state of the memory cell, PA1 a pre-charging circuit for letting a current flow to the bit line in response to a second timing signal produced in an early stage when the second timing signal is active; and PA1 whereby the pre-charging circuit is operated to interrupt a current in a last stage when the second timing signal is active.
USPTO Backgrounds
USPTO Backgrounds