1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device intended to suppress a leak current from insulated gate field effect transistors so as to save the power consumption.
2. Description of the Related Art
In a semiconductor integrated circuit, a large number of insulated gate field effect transistors (hereinafter abbreviated to “MOSFETs”) are provided. Further, the channel length is shortened by a micro-fabrication process, and the gate oxide film thickness is reduced, so as to increase the integration or improve the operating speed. However, a threshold is lowered, or the ratio of a leak current to the power consumption increases. Thus, a solution to those problems is requested.
It is a well-known fact that the threshold or the leak current can be controlled to some extent by adjusting a source-substrate voltage or a source-drain voltage. Researches in recent years have suggested that when such a voltage is made not higher than a certain voltage, the leak current increases unexpectedly due to GIDL (Gate Induced Drain Leakage), BTBT (Band To Band Tunneling) or the like (see A. Keshavasrzi and seven others, “Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs”, ISLP ED'01 pp. 207–211).
Therefore, a technique in which a fixed limit value is set for the source-substrate voltage and the voltage is prevented from exceeding the limit value so as to suppress a leak current has been proposed (see Japanese Patent Application No. 2003-358891).
However, with the advance of the micro-fabrication process, it has been difficult to suppress a variation in process with sufficient accuracy. Thus, as in Patent Document 1, due to a variation in the source-substrate voltage perfect for suppressing the leak current, the leak current may increase unexpectedly in the configuration where a fixed limit value is provided to set the source-substrate voltage. Further, any leak current has dependency on temperature. Accordingly, when the source-substrate voltage or the source-drain voltage is set independently of the device temperature, there is a problem that the leak current cannot be suppressed satisfactorily.
There is a problem that the source-substrate voltage or the source-drain voltage perfect for reducing the current leakage depends not only on such a variation in process but also on a temperature condition or a power supply voltage.
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