1. Field of the Invention
The present invention relates to a method of manufacturing a substrate of a liquid crystal display device on which a switching element and a pixel electrode are provided. In particular, the present invention relates to a method of manufacturing a substrate using a light developable organic protection layer in order to simplify the manufacturing steps and to prevent defective patterning of the pixel electrode.
2. Description of the Related Art
In general, a substrate of a conventional LCD on which a switching element and a pixel electrode are provided is formed as shown in FIGS. 1 and 2. FIG. 2 is a cross-sectional view which is cut along line II--II of FIG. 1.
As illustrated in FIG. 1, a gate bus line 60 is formed to extend horizontally and a data bus line 70 is formed to extend vertically on a transparent substrate 10. A TFT, which includes a gate electrode 60a, a source electrode 70a, a drain electrode 70b and a semiconductor layer 90, is formed at the intersection area where the gate bus line 60 and the data bus line 70 cross each other. A pixel electrode 40 which is in contact with the drain electrode 70b is formed at the above mentioned intersection area. A storage capacitance electrode 35 is formed at an area where the pixel electrode 40 and the gate bus line 60 overlap. A gate pad 60b which is arranged to be in contact with a driving IC terminal is formed at each end of the gate bus line 60. A data pad 70c is formed at each end of the data bus line 70. A pinhole type of defectively patterned part is formed at the pixel electrode 40 due to a jagged protruding portion 80a which is formed during patterning of a protection layer.
A defectively patterned part formed by the jagged protruding portion 80a is shown in more detail in FIG. 2. The jagged protruding portion 80a is formed if photoresist is not completely eliminated or if the photoresist is not applied evenly during the formation of contact holes 30a, 30b, 30c and 30d in an organic protection layer 55 which includes a TFT having a gate electrode 60a, a semiconductor layer 90, a source electrode 70a and a drain electrode 70b. If an ITO layer is coated in order to form a pixel electrode 40 in the above mentioned condition, a pinhole type of defectively patterned part occurs on the surface of the ITO layer. The defectively patterned part of the pixel electrode causes a poor quality pixel and also causes the pixel to have a low aperture ratio.
When the organic protection layer, in other words, the benzocyclobuten (hereinafter referred to as "BCB") protection layer 55, having a non-dielectric constant of about 2.7, is applied, the surface of the BCB protection layer maintains evenness and especially there is an advantage in that the pixel can be designed to have an enlarged aperture ratio by overlapping the pixel electrode 40 and the data bus line 70 because the BCB protection layer has a low non-dielectric constant compared to an inorganic protection layer, having a non-dielectric constant which is equal to or greater than 5, such as SiNx and SiOx. In spite of this advantage, the aperture ratio of the pixel is decreased and does not satisfy the desired ratio due to the defective pattern of the pixel electrode.
Further problems not described with respect to FIG. 2 will be illustrated hereafter in detail with reference to various manufacturing steps shown in FIGS. 3a to 3i.
As seen in FIG. 3a, a metal layer 6 which includes aluminum, aluminum alloy, Cr and Mo is formed via coating on a transparent substrate 10 and a photoresist 80 is formed on the metal layer 6 so as to have a certain pattern as shown in FIG. 3a.
A gate bus line 60, a gate electrode 60a and a gate pad 60b are formed by wet etching the exposed metal layer along the pattern of the photoresist 80. The portion of the photoresist 80 which remains on the metal layer 6 after forming each pattern is removed as shown in FIG. 3b.
A gate insulating layer 50 which includes an inorganic insulating layer like SiNx and SiOx, a semiconductor layer 90 which includes a-Si and an ohmic contact layer 92 which includes n+type a-Si are formed by sequentially coating on the substrate at a location where the gate electrode 60a and other elements are formed. The photoresist 80 is formed so as to have a certain pattern on the ohmic contact layer 92 of the gate electrode part as shown in FIG. 3c.
The exposed ohmic contact layer 92 is etched via a dry or wet etching method along the pattern of the photoresist and the exposed semiconductor layer 90 is etched at the same time. The photoresist which remains on the pattern is removed after the pattern of the ohmic contact layer 92 and the semiconductor layer 90 are formed so as to have an island shape via the above-described etching method on the gate insulating layer 50 of the gate electrode part as shown in FIG. 3d.
A metal layer 7 which includes aluminum, aluminum alloy, Cr and Mo is formed by coating on the substrate where the pattern of the ohmic contact layer 92 and the semiconductor layer 90 is formed and the photoresist 80 is formed to have a certain pattern on the metal layer as shown in FIG. 3e.
A data bus line 70, a source electrode 70a which contacts the ohmic contact layer 92 and a drain electrode 70b are formed via wet etching of the exposed metal layer 7 along the pattern of photoresist. A metal layer 70d which includes a storage capacitance electrode is formed on the gate insulating layer 50 at a location where the portion of the gate bus line 60 and the data pad 70c are formed on the gate insulating layer 50. After forming each pattern element, etching of the exposed ohmic contact layer 92 using the source and drain electrodes as masks and forming of an ohmic contact layer 92a and 92b so that it is separated into two separate portions located on both sides of the semiconductor layer 90, is performed. The photoresist which remains on the pattern is removed after etching is finished so as to produce the above mentioned structure and through the above steps, the TFT which acts as a switching element is formed on the transparent substrate as shown in FIG. 3f.
The protection layer 55 which includes an organic insulating layer like BCB is coated on the entire substrate where the TFT and other elements are formed. The organic insulating layer with BCB is very advantageous for improving the aperture ratio because it has a low non-dielectric constant and has a characteristic of making the surface of substrate even when applied on the surface. In other words, even if the pixel electrode overlaps a data bus line and the like in order to maximize the aperture ratio of the pixel, the voltage of the pixel is not distorted because current voltage in the data bus line does not effect the pixel due to the high insulation of the BCB protection layer. Also, because the surface is even, when the substrate is closely adhered, a desired cell gap is maintained evenly and insufficient rubbing of an orientation film which is formed on the pixel electrode is decreased. The photoresist 80 is formed to have a certain pattern on the protection layer 55 with such characteristics. The photoresist pattern layer 80 is formed so as to partially expose the gate pad 60b, the drain electrode 70b, the data pad 70c and the metal layer forming the storage capacitance electrode 70d as shown in FIG. 3g.
Contact holes 30a, 30b and 30c are formed by dry etching the protection layer 55, which is exposed along the pattern of the photo resist, by using CF.sub.4 /O.sub.2 or SF.sub.6 /O.sub.2 gas and a contact hole 30d is formed by etching the gate insulating layer 50 until the surface of the gate pad 60b is exposed after the surface of the drain electrode 70b, the data pad 70c and the metal layer forming the storage capacitance electrode 70d is exposed. The photoresist which remains on the protection layer 55 is removed by ashing with plasma O.sub.2 after forming the contact hole. However, during the ashing, the photoresist is not removed easily because it has a carbonizing reaction and if the photo resist is not applied evenly, a jagged protruding portion 80a occurs on the surface of the protection layer 55 as shown in FIG. 3h.
An ITO layer 4 is coated on the protection layer where the contact hole is formed and photoresist 80 is formed on the ITO layer so as to have a certain pattern. During the coating process of the ITO layer, the ITO layer is not coated on the jagged protruding portion 80a which is formed on the surface of the protection layer 55 and therefore, pinholes are formed as shown in FIG. 3i.
A pixel electrode 40, storage capacitance electrode 35, a data pad 70c' and a gate pad 60b' which are in contact with the drain electrode 70b are formed by wet etching the ITO layer 4 which is exposed along the pattern of the photoresist. The pixel electrode 40 is formed so as to overlap the data bus line 70 in order to maximize the aperture ratio. The photoresist remaining on the pattern is removed when the pattern is formed by the etching method.
A substrate of an LCD formed in manner described above results in a pinhole being formed inside the pixel electrode 40 and a defective pattern in which the edge of the pixel electrode is not formed smoothly occurs as shown in FIG. 2.
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