1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to the semiconductor memory device being provided with an error correcting code (ECC) circuit.
The present application claims priority of Japanese Patent Application No. 2002-203334 filed on Jul. 11, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) is employed in a storage section of various information devices such as personal computers and, as an amount of information increases, to process (that is, to write and read) information made up of multiple bits also increases. However, as such information consisting of multiple bits to be processed increases, an error occurs inevitably in part of bits of the information when being transmitted. To solve this problem, that is, to improve reliability in the transmission of the information, a DRAM with an ECC circuit having a function of detecting and correcting error bits is provided. The ECC (Error Correcting Code) circuit is configured by using a known Hamming Code. It is known that the Hamming Code is a self-correcting code that can detect and corrects one bit error out of multiple bits.
On the other hand, an SDRAM (Synchronous DRAM) is becoming widespread which enables a high-speed access and is configured so as to operate in synchronization with a clock signal fed from an outside. In such the above SDRAM, an operation speed can be improved several times compared with the conventional DRAM configured so as to operate in a mode being asynchronous to an external signal.
However, such the SDRAM as described above has a problem of a Pause Refresh Tail distribution of information to be stored in a memory cell, that is, a problem of a Pause Refresh failure. Here, time during which a memory cell was left without any process being performed after data had been written thereon is called Pause time. A Pause Refresh test (also called “Pause test”) is carried out to check whether data can be read normally from the memory cell after a lapse of a set Pause time. If nothing is done, since data having been written is corrupted by a leakage current, rewriting (refresh) operation is required before data is corrupted.
A Pause Refresh distribution being produced as a result from a Pause Refresh test, which represents Pause Refresh real power occurring until the data is corrupted by the leakage current after each bit has been written, is given as two Gaussian distributions including a Pause Refresh normal distribution being a good distribution which accounts for about 99.9% of the total distribution and a Pause Refresh Tail distribution being a poor distribution which accounts for remaining error of about 0.1% of the total distribution. In the SDRAM, in order to greatly reduce a data holding current, it is necessary to lengthen a refresh period so that the refresh period exceeds a period for the Pause Refresh real power to efficiently improve and correct the Pause Refresh Tail distribution (error rate≈0.01% of random bits), Thus, by greatly reducing a data holding current, reduction in power consumption of the SDRAM can be achieved.
Such the DRAM with the ECC circuit described above is disclosed in, for example, Japanese Patent No. 2539950 (Japanese Patent Application Laid-open No. Hei 6-89595). The disclosed DRAM has a 128+9 bit SRAM (Static Random Access Memory) internally and is configured so that access to an outside device can obtained through the SRAM. Moreover, the DRAM with the ECC circuit as described above is disclosed in, for example, Japanese Patent Application Laid-open No. Hei 10-326497. The disclosed DRAM has a configuration with specifications that can comply with packet input/output specifications as employed in a RDRAM (Rambus DRAM).
There is a problem in that, since such the conventional semiconductor memory devices as described above cannot be applied to an SDRAM, when the Pause Refresh Tail distribution is to be improved and corrected, if bits have a low error rate, the Pause Refresh Tail distribution cannot be efficiently improved and corrected and therefore even by lengthening a refresh period so that the refresh period exceeds a period for the Pause Refresh real power, it is impossible to greatly reduce a data holding current.
In the case of the DRAM disclosed in the Japanese Patent No. 2539950, since access to the outside device is obtained through an SRAM made up of 128+9 bits, when a writing operation is performed, after data has been read once to the SRAM (that is, a pre-fetching operation has been performed), writing to a memory cell is performed and therefore redundant time has to be provided during writing operations of the SDRAM. That is, writing of the SDRAM is completed by simultaneously setting a writing command, data and a Y address (address of a device to which the writing is done) and time required for the above pre-fetching operation is not needed and is completed only by one setting. When the ECC circuit is mounted internally as in the case of the DRAM disclosed as above, since data has to be set after a two-cycle delay or a three-cycle delay from a writing command, three cycles or four cycles are needed before an operation is completed. Therefore, since the above pre-fetching operation is required, specifications for the SDRAM cannot be met.
Next, in the case of the DRAM disclosed in the Japanese Patent Application No. Hei 10-326497, since the DRAM has a configuration with specifications that can comply with packet input/output specifications, packet data has to be prepared and since configurations of the DRAM are basically different from those of the SDRAM, the disclosed DRAM cannot be applied to the SDRAM as in the case of the DRAM disclosed in Japanese Patent No. 2539950.
USPTO Backgrounds
USPTO Backgrounds