Integrated circuits typically employ latches to store data. Some latches are able to retain data when the integrated circuit enters a low-power mode. When the integrated circuit changes to a normal or active mode, the retained data is provided at the latch output in response to an isolation signal indicating the mode change. However, errors can result from imprecision in the timing of the isolation signal. For example, if a latch provides an asynchronous reset control signal to downstream elements, a delay in the isolation signal can cause an undesirable reset of the downstream elements. The likelihood of such errors can be reduced by individually controlling the timing of isolation signals for each latch in the integrated circuit. However, this can require an undesirable number of individually controlled isolation signals, and can also require undesirably complex circuitry to control each isolation signal. Accordingly, there is a need for an improved latch device.
USPTO Backgrounds
USPTO Backgrounds