1. Technical Field
Example embodiments of the inventive concept relate to non-volatile semiconductor devices and to methods of manufacturing non-volatile semiconductor devices. More particularly, example embodiments of the inventive concept relate to flash memory devices having a required breakdown voltage while reducing a leakage current, and to a method of manufacturing the flash memory devices.
2. Description of the Related Art
Various data can typically be stored permanently or temporarily in semiconductor memory devices. In the semiconductor memory devices, the data may be stored in a memory cell thereof as logics of “0” or “1”. The semiconductor devices are usually divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices may lose the stored data when an applied power is off. However, the non-volatile semiconductor memory devices may keep the stored data even though an applied power is off.
A flash memory device, one of the non-volatile semiconductor memory devices, has been developed for various electronic apparatuses such as, for example, computers, digital cameras, portable multimedia players, cellular phones, MP3 players, games, memory sticks, etc. As for the conventional flash memory devices, data may be stored into the flash memory device or may be read from the flash memory device through the Fowler-Nordheim tunneling mechanism or through the hot electron injection mechanism.
The flash memory device may have a floating gate type or a charge trap type. The floating gate type flash memory device may not be properly employed in a current semiconductor device because the floating gate type flash memory device may not be highly integrated to a desired degree for the current extremely highly integrated semiconductor device. Hence, the charge trapping type flash memory device has been widely used because of the high integration degree thereof.
FIG. 1 is a cross sectional view showing the conventional charge trapping type flash memory device.
As shown in FIG. 1, the conventional charge trapping type flash memory device includes a tunnel oxide layer 15, a charge trapping layer pattern 20, a blocking layer pattern 25, a metal electrode 30, a mask 35 and a spacer 40.
The tunnel oxide layer 15 is formed on a substrate 10. The charge trapping layer pattern 20 and the blocking layer pattern 25 are sequentially formed on the tunnel oxide layer 15. The metal electrode 30 and the mask 35 are formed on the blocking layer pattern 25. The metal electrode 30 has a width smaller than the width of the blocking layer pattern 25. Thus, an offset is formed between the metal electrode 30 and the blocking layer pattern 25. The spacer 35 is located on sidewalls of the metal electrode 30.
The charge trapping type flash memory device may have an integration degree larger than the integration degree of the floating gate type flash memory device. The charge trapping layer pattern 20 is generally formed using a nitride for ensuring charge trap sites therein. The blocking layer pattern 25 includes a high-k material for preventing charges from moving toward the metal electrode 30.
However, etched damages such as defects may be generated at sidewalls of the blocking layer pattern 25 while etching a blocking layer to form the blocking layer pattern 25. Such defects of the blocking layer pattern 25 may serve as undesired charge trap sites to cause the movements of the charges thereto, so that the conventional charge trapping type flash memory device may have reduced breakdown voltage and increased leakage current. To resolve these difficulties, at least one spacer 40 is formed on the sidewall of the metal electrode 30 to maintain the offset between the metal electrode 30 and the blocking layer pattern 25.
FIG. 2A is a graph showing breakdown voltages relative to thicknesses of spacers in conventional charge trapping type flash memory devices. In FIG. 2A, a line A1 indicates a breakdown voltage variation of a first conventional charge trapping type flash memory device having double spacers of middle temperature oxide (MTO) and silicon nitride. Here, the double spacers have thicknesses of about 100 Å and about 130 Å, respectively. A line B1 denotes a breakdown voltage variation of a second conventional charge trapping type flash memory device including double spacers of MTO and silicon nitride, which have thicknesses of about 80 Å and about 105 Å. Further, a line C1 represents a breakdown voltage variation of a third conventional charge trapping type flash memory device including double spacers of MTO and silicon nitride, which have thicknesses of about 50 Å and about 70 Å.
FIG. 2B is a graph showing the breakdown voltages relative to leakage currents in the conventional charge trapping type flash memory devices. In FIG. 2B, a line A2 represents the breakdown voltage variation of the first conventional charge trapping type flash memory device, and a line B2 denotes the breakdown voltage variation of the second conventional charge trapping type flash memory device. Additionally, a line C2 means the breakdown voltage variation of the third conventional charge trapping type flash memory device, and a line D indicates a breakdown voltage variation of a fourth conventional charge trapping type flash memory device including double spacers of MTO and silicon nitride, which have thicknesses of about 100 Å and about 100 Å.
Referring to FIGS. 2A and 2B, the conventional charge trapping type flash memory device includes the double spacers of which thicknesses above about 50 Å and about 70 Å in an attempt to provide the desired breakdown voltage and leakage current when the conventional charge trapping type flash memory device has the double spacers for maintaining the offset.
FIG. 3 is an electron microscopic picture showing a conventional charge trapping type flash memory device having a spacer.
As shown in FIG. 3, gate structures having a metal gate (e.g., the light portion) and a spacer may be too closely arranged when the spacer is provided on a sidewall of the metal gate. That is, the adjacent gate structures may be connected to each other as the conventional charge trapping type flash memory device is highly integrated. Further, a charge trapping layer pattern and a blocking layer pattern may not be properly formed because a charge trapping layer and a blocking layer may not be etched when the adjacent gate structures having the spacers are closely arranged in a cell area of the conventional charge trapping type flash memory device.
USPTO Backgrounds
USPTO Backgrounds