The present invention relates generally to verification environments, and more particularly to verification environments utilizing hardware description languages.
VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems, such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design.
VHDL has constructs to handle the parallelism inherent in hardware designs, in order to directly represent operations which are common in hardware, such as an extended set of Boolean operators including NAND and NOR. VHDL also allows arrays to be indexed in either ascending or descending direction; both conventions are used in hardware.
USPTO Backgrounds
USPTO Backgrounds