Resin-impregnated fiberglass sheets are commonly used in the formation of printed circuit boards. The fiberglass cloth is typically impregnated with the selected thermoset resin which is then partially cured and the impregnated cloth sheared to form what are known as sticker or prepreg sheets. In order to enhance the adhesion of the resin to the fiberglass, often a coupling agent, such as a silane, is coated onto the surface of the fiberglass prior to impregnation. The prepreg sheets are then laid up with sheets of metal such as copper or copper-invar-copper (CIC) and laminated with heat and pressure to fully cure the laid-up laminate with the metal sheets defining ground, power and signal planes. One of the desirable characteristics of the resin-impregnated fiberglass sheets is that the resin-impregnation must cover the fibers of the fiberglass and must be able to be partially cured to a non-tacky state wherein the sheets can be handled for the lamination process. This is often referred to as a B-stage, a cure state which allows the sheets to be sufficiently self-supporting to be laid up as a laminate, but not advanced enough in the state of cure that they are rigid or non-flowable when heated, and they can be further cured to a final cure with heat and pressure to form a laminate structure as is well known in the art. As indicated above, this lamination process normally includes the lamination of one or more sheets of metal, such as copper, CIC or other metal, to provide necessary ground planes, power planes and signal planes buried within the laminated circuit board. Also in conventional practice, openings are formed, either by drilling or other means, through the fully cured laminates which form the openings for vias or plated through holes where the connections can be made from one surface of the circuit board to the other and to the various internal planes within the laminate as required.
A conventional technique of forming the resin-impregnated fiberglass sheets is to provide a coil of the fiberglass material and unwind the fiberglass material from the coil and continuously pass it through a tank containing the solution of the desired resin in a solvent, and then pass the coated or impregnated material through a treater tower wherein heat is applied to drive off the solvent and to partially cure the resin material by initiating cross-linking and then coiling the partially-cured or B staged material into a coil. Thereafter, the partially-cured material is uncoiled and cut into sheets of the desired length. These sheets, known as prepreg sheets, are then used in the lamination process described above.
This prepreg material has long been used for manufacturing circuit boards, however, more recently, the same prepreg material and same laminating techniques that have been used to form a circuit board have been used to form chip carriers. A chip carrier is basically a small-size version of a circuit board where the metallurgy and the lay out can be much finer than on a circuit board. Printed circuit board reliability tests are defined, e.g., in IPC specifications, whereas chip carrier tests are defined by JEDEC specifications which are derived for ceramic carriers and are more severe tests. In addition, because of the finer geometry of the metallurgy and the lay-out, chip carriers are more prone to failure from various failure mechanisms.
A particular defect that can occur is the formation of pin holes. A pin hole is an opening in the resin which impregnates the fiberglass. Most pin holes will fill in during lamination. However, a small number of pin holes may remain and become the source of defects. With pin holes, shorts can develop between adjacent power planes or power and ground planes, or whatever planes happen to be adjacent to each other. Potentially, these pin holes provide shorting paths that can be established and revealed under leakage tests and other high potential tests.
The cloth styles of intermediate thickness seem to be the most susceptible to pinholing, while very light weight and heavy weight cloths have a lower defect density. Thus, according to conventional prior art techniques, in order to reduce pin hole density in any given cloth, thinner, finer weave clothes are used. However, this has several drawbacks. First, thinner, finer weave clothes are more expensive than thicker, coarser weave clothes per unit area, and secondly, the thinner clothes in many instances may not provide the necessary thickness or dielectric separation between two adjacent planes, thus necessitating the use of two laminated superimposed clothes. The use of two clothes significantly reduces the possibility of pin hole defects establishing shorting paths since it is highly unlikely that two pin holes would be exactly aligned or closely enough aligned to provide such a path. Thus, if only one cloth of the pair has a pin hole, the strong probability is that this in itself will not be enough to cause the shortage since it is highly improbable that a pin hole in the other cloth will be aligned with the pin hole in the first cloth. When thicker clothes are used with a higher pin hole density, two clothes can also be used, but this significantly increases the thickness of the circuit board or chip carrier being formed which often is undesirable. Alternatively, to maintain the thickness, two sheets of thinner cloths have to be used to attain the required reliability.
Hence, it is an object of the present invention to provide a resin-impregnated cloth and a method of forming said cloth wherein the pin hole density is significantly reduced over cloths produced by prior art techniques.
USPTO Backgrounds
USPTO Backgrounds