1. Field of the Invention
The present invention relates to a semiconductor device in which element regions are isolated by trenches formed in a semiconductor substrate and a method of fabricating this semiconductor device. More particularly, the invention relates to a semiconductor device in which a transistor operating at a high voltage and a transistor operating at a low voltage are formed on the same semiconductor substrate and a method of fabricating this semiconductor device.
2. Description of the Prior Art
In recent years, collective erasing type flash memories such as EEPROMs (electrically erasable programmable read only memories) have begun to be used in IC cards etc. A memory cell of an EEPROM has two gate electrodes of a floating gate and a control gate and performs the writing/erasure of data by controlling the supply and receipt of electric charges to and from the floating gate.
A flash memory is provided with a driving circuit to drive the memory cell. Furthermore, in recent years, there has also been developed a system LSI in which a memory cell and a CPU or other logic circuits are formed on the same semiconductor substrate. Hereinafter, both a driving circuit and a logic circuit formed on the same semiconductor substrate as the memory cell are respectively referred to as a peripheral circuit.
FIGS. 1A to 1G are sectional views showing a conventional method of fabricating a semiconductor device (a flash memory) in the order of fabrication steps. Incidentally, in FIGS. 1A to 1G, the cross-section of a memory-cell formation section is shown in the left-hand part of each view, and the cross-section of a peripheral-circuit formation section is shown in the right-hand part.
First, as shown in FIG. 1A, a pad oxide film 101 is formed on a semiconductor substrate 100, and a silicon nitride film 102 is formed on the pad oxide film by the CVD (chemical vapor deposition) process. Incidentally, a film of laminated structure of a silicon oxide layer and a silicon nitride layer may sometimes be formed in place of the silicon nitride film 102.
Next, as shown in FIG. 1B, the silicon nitride film 102 is patterned to a prescribed shape by the photolithography process. Then, the pad oxide film 101 and the semiconductor substrate 100 are etched by use of this silicon nitride film 102 as a mask, thereby forming shallow trenches 103a and 103b respectively in the memory-cell formation section and peripheral-circuit formation section.
Next, as shown in FIG. 1C, a silicon oxide film 105 is formed by depositing silicon oxide on the whole surface of the top side of the semiconductor substrate 100 and the trenches 103a and 103b are embedded with the silicon oxide. After that, the silicon oxide film 105 and the silicon nitride film 102 are polished by the CMP (chemical mechanical polishing) process, for example, thereby making the surfaces of these films flat. In this step, however, it is necessary only that the silicon oxide within each of the trenches 103a and 103b be mutually isolated, and the polishing is completed before the silicon nitride film 102 is completely removed.
After that, as shown in FIG. 1D, the silicon nitride film 102 is removed by etching. Hereinafter, a film formed of the silicon oxide within the trench 103a of the memory-cell formation section is referred to as an element-isolating film 106a, and a film formed of the silicon oxide within the trench 103b of the peripheral-circuit formation section is referred to as an element-isolating film 106b. 
Next, as shown in FIG. 1E, after the removal of the pad oxide film 101 by etching, a tunnel oxide film 107a and a gate oxide film 107b, each having a prescribed thickness, are formed respectively in the memory-cell formation section and the peripheral-circuit formation section by oxidizing an exposed substrate surface.
Next, as shown in FIG. 1F, a floating gate 108a, an intermediate insulating film 109 and a control gate 110a are formed in the memory-cell formation section, and a gate electrode 110b is formed on a gate oxide film 107b of the peripheral-circuit formation section. The floating gate 108a is formed on the tunnel oxide film 107a of each memory cell region, with one floating gate per tunnel oxide film, and the control gate 110a is formed so as to pass above the plurality of floating gates 108a formed in a line.
After that, a source/drain layer (not shown) is formed by doping impurities on the surface of the semiconductor substrate 100 by use of the control gate 110a and the gate electrode 110b as masks. Furthermore, an interlayer-insulating film 111 is formed on the whole surface of the top side of the semiconductor substrate 100, and the control gate 110a and the gate electrode 110b are covered with this interlayer-insulating film 111.
Subsequently, a contact hole (not shown) is formed in a prescribed position of the interlayer-insulating film 111 by the photolithography process. Then, a metal film is formed on the whole surface of the top side of the semiconductor substrate 100, and by patterning this metal film, as shown in FIG. 1G, a bit line 112a is formed in the memory-cell formation section, and an interconnection 112b is formed in the peripheral-circuit formation section. The flash memory is completed in this manner.
However, the present inventors consider that the above-described conventional method of fabricating semiconductor devices has the following problems.
FIG. 2 is an enlarged view of the shape of a top edge portion of the element-isolating film. As shown in this FIG. 2, in the conventional method the curvature of an interface between the top edge portion of the element-isolating film 106 and the semiconductor substrate 100 is small and, therefore, thinning (the phenomenon that an insulating film becomes thin in the vicinity of a corner portion) occurs. For this reason, a parasitic transistor occurs parallel to the memory cell, with the result that humps occur in the current-voltage characteristics of the memory cell, causing an increase in leakage current.
Furthermore, a high voltage of about 20 V is applied to the memory cell in contrast to the operating of the transistor in the peripheral circuit at a low voltage of 3.3 V or less. Therefore, when the curvature of the interface between the top edge portion of the element-isolating film 106 and the semiconductor substrate 100 is small, strong electric fields concentrate on this part, thereby posing the problems that the controllability of the supply and receipt of electric charges to and from the floating gate 108a decreases and that the tunnel oxide film 107a is broken.
On the other hand, it is conceivable to increase the curvature of the interface between the top edge portion of the element-isolating film 106 and the semiconductor substrate 100. In this case, however, the area of the element region inevitably becomes small, with the result that the current-driving capacity of the transistor constituting the peripheral circuit decreases, causing a decrease in the operating speed. When the curvature of the interface between the top edge portion of the element-isolating film 106 and the semiconductor substrate 100 is increased and, at the same time, the area of the element region of the peripheral-circuit formation section is increased, the problem that the high integration of the semiconductor device is impaired.
Incidentally, in Patent Application Publication (KOKAI) 2000-269450, it is proposed to increase the curvature of an end portion of the element region of the peripheral-circuit formation section to a value larger than the curvature of an end portion of the element region of the memory-cell formation section. In this case, however, it is impossible to prevent a decrease in the controllability of the supply and receipt of electric charges to and from the floating gate by the memory cell and the breakage of the tunnel oxide film. Furthermore, it is impossible to prevent a decrease in the driving capacity of the peripheral circuit and a decrease in integration density.
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