1. Technical Field
This disclosure relates to the fabrication of semiconductor devices, and more particularly, to methods of fabricating a semiconductor device by exposing the upper sidewalls of a contact plug to form a charge storage electrode.
2. Description of the Related Art
As design rules for semiconductor devices continue to be reduced, a capacitor formation process becomes increasingly important to achieving high integration densities. For this reason, constant efforts have been made to fabricate a capacitor that provides a desired capacitance within a steadily smaller area.
The capacitance of a capacitor is determined by the area of a capacitor and the permittivity of a dielectric layer. The area of the capacitor means an effective area of a dielectric layer between a storage electrode and a plate electrode. The capacitance of the capacitor is proportional to the effective area of the dielectric layer. Furthermore, high-k dielectric layers such as Ta2O5, Al2O3, BST ((Ba, Sr)TiO3) have been used to replace conventional nitride-oxide (NO) dielectric layers, which further increases the capacitance of the capacitor. However, such a high-k dielectric layer must be accompanied by a metal electrode, and the use of a metal electrode also poses many difficulties.
Therefore, research is underway to develop a method of increasing an effective area of a dielectric layer through a structural modification of a charge storage electrode.
A three-dimensionally structured electrode has been disclosed in U.S. Pat. No. 5,597,756 to Fazan et al. (“Fazan”) entitled “PROCESS FOR FABRICATING A CUP-SHAPED DRAM CAPACITOR USING A MULTI-LAYER PARTLY-SACRIFICIAL STACK.”
FIGS. 1A and 1B are cross-sectional diagrams illustrating a conventional method of fabricating a semiconductor device having a three-dimensional electrode.
Referring to FIG. 1A, an interlayer insulating layer 16 is formed to cover a semiconductor substrate 10 on which a lower structure including capacitor contact plugs 15 is formed, and an etch stop pattern 17 and a molding pattern 18 are formed on the interlayer insulating layer 16, so as to expose the capacitor contact plug 15 and the portion of the interlayer insulating layer 16 around the capacitor contact plug 15. The etch stop pattern 17 is formed to prevent the interlayer insulating layer 16 from being damaged during an etch process for removing the molding pattern 18.
The lower structure includes landing plugs 14, gate electrodes 11, and mask insulating layers 12. The capacitor contact plugs 15 are connected with the semiconductor substrate 10 through the landing plugs 14. The landing plugs 14 are connected to the semiconductor substrate 10, which is exposed between spacer insulating layers 13 covering the sidewalls of the gate electrode 11 and the mask insulating layer 12.
The interlayer insulating layer 16 is formed of a material having good flow characteristics for planarization, and covers the semiconductor substrate 10 having the lower structure described above. Since the interlayer insulating layer 16 has good flow characteristics, it will normally also have a relatively high wet etch rate. For example, the etch rate of the material of the interlayer insulating layer 16 is higher than the etch rate of the material of the molding pattern 18. Thus, in a cleaning process performed after the formation of the molding pattern 18, the interlayer insulating layer 16 exposed around the capacitor contact plug 15 is wet-etched relatively more rapidly, so as to generate a undercut U under the etch stop pattern 17. When the undercuts U are overly formed inside the interlayer insulating layer 16 between the adjacent capacitor contact plugs 15, adjacent charge storage electrodes may be connected.
As shown in FIG. 1B, cylindrical-shaped charge storage electrodes 19 are achieved by forming a conductive layer pattern covering the inner walls of the molding pattern 18 and the capacitor contact plug 15, and removing the molding pattern 18. As described above, in the case that the undercut U is formed, the inner walls of the undercut U are covered with a conductive layer during a deposition process of the conductive layer to form the charge storage electrodes 19. Thus, the adjacent charge storage electrodes 19 are connected as shown in the circled portion A of FIG. 1B, thereby deteriorating the reliability of devices.
Embodiments of the invention address these and other disadvantages of the conventional art.
USPTO Backgrounds
USPTO Backgrounds