This application claims the benefit of Korean Patent Application No. 1999-21033, filed on Jun. 7, 1999, under 35 U.S.C. xc2xa7 119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a Liquid Crystal Display (LCD), and more particularly, to a Thin Film Transistor (TFT) array substrate and to a method of fabricating the same.
2. Description of Related Art
Generally, a liquid crystal display (LCD) comprises opposed upper and lower substrates and an interposed liquid crystal. On the lower substrate, a plurality of gate lines extending in one direction and a plurality of data lines extending in a perpendicular direction are formed. Within this matrix arrangement is a plurality of thin film transistors (TFTs) disposed near the crossings of the data and gate lines. The TFTs are used as switches that selectively apply voltages across the liquid crystal.
Nowadays, the liquid crystal display (LCD) is frequently used in computers, such as laptop computers. While liquid crystal displays started out as relatively simple display devices, they have become large and relatively complex displays. A large-sized LCD employs an active matrix array substrate that includes numerous pixel regions, data and gate lines that cross each other to define the pixel regions, and TFTs (switching device) positioned near the crossings of the data and gate lines.
With such active matrix type liquid crystal displays, high picture quality and high definition are important. To help achieve such features, storage capacitors in parallel with pixel electrodes have been used.
In general, without a storage capacitor, the electric charge of a first signal applied through the TFT will leak away after a short time. In contrast, with a storage capacitor the first electric charge is maintained until the application of a second signal.
In general, for the storage capacitor the gate line acts as one capacitor electrode and the pixel electrode acts as the other capacitor electrode.
FIG. 1 is an enlarged plan view illustrating the array substrate of a conventional active matrix type LCD having a pixel region xe2x80x9cPxe2x80x9d, a storage capacitor xe2x80x9cCxe2x80x9d, a TFT xe2x80x9cAxe2x80x9d and gate and data lines 36 and 49. A drain electrode 47 of the TFT xe2x80x9cAxe2x80x9d is connected to a pixel electrode 40 of the pixel region xe2x80x9cPxe2x80x9d via a contact hole 57.
A semiconductor channel region 53 is formed between source and drain electrodes 45 and 47 by exposing a portion of the intrinsic semiconductor layer 39. Ohmic contact regions are formed between the intrinsic semiconductor layer 39 and the source and drain electrodes 45 and 47. Gate and data pads (not shown) are formed at one end of the gate and data lines 36 and 49.
FIGS. 2a to 2f are cross-sectional views taken along line I-I of FIG. 1, and are used to illustrate process steps of fabricating a TFT array substrate using a conventional four-mask process.
Referring to FIG. 2a, a first metallic layer is formed on a substrate 31 and is then patterned using a first mask process to form a gate pad (not shown), a gate electrode 33 and a gate line 36. The first metallic layer is beneficially made of a metallic material having a low resistance, such as Aluminum (Al) or Al-alloy. When the gate line 36 is used as a capacitor electrode, the time constant of the gate line increases. Thus, a material having the low resistance, such as Aluminum, is preferably used for the gate line. Aluminum can decrease the time constant compared with a material having a higher resistance, such as Tantalum (Ta) or Chrome (Cr).
The gate electrode 33 is extended from the gate line 36 and is formed at the comer of the pixel region. Referring back to FIG. 1, a portion of the gate line 36 is used as a capacitor electrode of the storage capacitor xe2x80x9cCxe2x80x9d.
As shown in FIG. 2b, a first insulation layer 37 is formed by depositing an inorganic substance, such as Silicon Nitride (SiNx) or Silicon Oxide (SiO2), or an organic substance, such as BCB (Benzocyclobutene) or acryl, on the substrate 31 while covering the gate electrode 33 and the gate line 36 (and thus the capacitor electrode). Then, an intrinsic semiconductor layer 39, such as pure amorphous silicon, is formed on the first insulation layer 37. Then, an extrinsic semiconductor layer 41, such as impurity (n+ or p+) doped amorphous silicon, is sequentially formed on the intrinsic semiconductor layer 39. Then, a second metallic layer 43 made of a material such as Molybdenum (Mo), Tantalum (Ta), Tungsten (W), Antimony (Sb) or the like is formed on the extrinsic semiconductor layer 41.
Referring to FIG. 2c, the source and drain electrodes 45 and 47, data line 49 (see FIG. 1), data pad (not shown) and second capacitor electrode 51 having an island shape are formed by patterning the second metallic layer 43 and the extrinsic semiconductor layer 41 using a second mask process. The source and drain electrodes 45 and 47 are spaced apart from each other to expose the semiconductor channel region 53. At this time, the extrinsic semiconductor layer 41 is removed using the source and drain electrodes 45 and 47 as a mask. Moreover, careful is required in this step, so as not to pattern the intrinsic semiconductor layer 39.
The portions of the extrinsic semiconductor layer 41 between the intrinsic semiconductor layer 39 and the source and drain electrodes 45 and 47 act as ohmic contact layers 43a and 43b, respectively.
As shown in FIG. 2d, a second insulation layer or protection layer 53 is formed on the metallic layers 45, 47 and 51, and on the intrinsic semiconductor layer 39.
Referring to FIG. 2e, contact holes 55 and 57 are formed by patterning the protection layer 53. Simultaneously, the pixel region xe2x80x9cPxe2x80x9d is formed by patterning the protection layer 53, the intrinsic semiconductor layer 39, and the first insulation layer 37 using a third mask process, except for the region for the storage capacitor and the data line.
Referring to FIG. 2f, a transparent conductive substance such as ITO (indium-tin-oxide) is deposited and patterned using a fourth mask process to form a pixel electrode 40. Thus, the pixel electrode 40, which electrically connects to the second capacitor electrode 51 and to the drain electrode 47 via contact holes 55 and 57, is formed.
FIG. 3a is an enlarged view illustrating the portion xe2x80x9cCxe2x80x9d of FIG. 2f, while FIG. 3b is an equivalent circuit of FIG. 3a. 
As shown in FIGS. 3a and 3b, the storage capacitor xe2x80x9cCxe2x80x9d includes the first capacitor electrode/gate line 36. It also includes the second capacitor electrode 51 (having a contact with the pixel electrode 40), the first insulation layer 37 (which stores the electric charge as a dielectric layer), and the semiconductor layer 42 (the intrinsic and extrinsic semiconductor layers 39 and 41 that act as a dielectric layer).
According to the conventional method for manufacturing a TFT array substrate using a four-mask process, the process steps are reduced over a five-mask process. However, the storage capacitance is also decreased compared to the five-mask process. For a better understanding, the storage capacitance is represented by the following equation:                               C          st                =                              ϵ            ·            A                    d                                    (        1        )            
In the above equation (1), xe2x80x9cCstxe2x80x9d denotes capacity, xe2x80x9c∈xe2x80x9d denotes a dielectric constant of the dielectric layer, xe2x80x9cdxe2x80x9d represents the thickness of the dielectric layer and xe2x80x9cAxe2x80x9d represents the area of the capacitor electrode. As described by Equation (1), the storage capacitance xe2x80x9cCstxe2x80x9d is in proportion to the area xe2x80x9cAxe2x80x9d and is in inverse proportion to the thickness xe2x80x9cdxe2x80x9d of the dielectric layer.
Therefore, due to the fact that the dielectric layer includes two layers (the first insulation layer 37 and the semiconductor layer 42) between the two capacitor electrodes 36 and 51, in the conventional four-mask process the capacitance is less than it could be.
In order to overcome the problems described above, a preferred embodiment of the present invention provides a method of fabricating a TFT array substrate having a large storage capacitance using a four-mask process, beneficially for use in an LCD device that has high picture quality and high definition.
In order to achieve the above objects, in one aspect, the preferred embodiment of the present invention provides for a thin film transistor (TFT) array substrate, including: a substrate; a plurality of a gate lines on the substrate; a plurality of data lines crossing the gate lines and formed over the substrate; a pixel electrode in a pixel region that is defined by the crossing data and gate lines; a TFT connecting to the pixel electrode; and a storage capacitor connecting to the pixel electrode, said storage capacitor including: the gate line; a first insulation layer on the gate line; intrinsic and extrinsic semiconductor layers formed sequentially on the first insulation layer; a first capacitor electrode on the semiconductor layer; a second insulation layer over the first capacitor electrode and semiconductor layer; and a second capacitor electrode on the second insulation layer in a position corresponding to the first capacitor electrode.
The TFT array substrate has a gate contact hole exposing a portion of the gate line and positioned at one side of the first capacitor electrode. The TFT array substrate has at least one gate contact hole, and the contact hole penetrates the central part of the first capacitor electrode. The TFT array substrate further includes the gate line and first capacitor electrode having electrical connections to each other using a transparent conductive electrode.
In order to achieve the above object, in another aspect, the present invention provides a method of fabricating a thin film transistor (TFT) array substrate, including: providing a substrate; depositing a first metallic layer on the substrate; forming a gate electrode and gate line on the substrate by patterning the first metallic layer using a first mask process; forming a first insulation layer over the gate electrode, gate line and substrate; forming an intrinsic semiconductor layer on the first insulation layer; forming an extrinsic semiconductor layer on the intrinsic semiconductor layer; depositing a second metallic layer on the extrinsic semiconductor layer; forming a data line, source and drain electrodes, and a first capacitor electrode having an island shape over the gate line by patterning the second metallic layer and extrinsic semiconductor layer using a second mask process; forming a second insulation layer over the data line, source and drain electrodes, and first capacitor electrode; forming a drain contact hole by patterning the second insulation layer using a third mask process, simultaneously, forming a pixel region and gate contact hole by patterning the first and second insulation layers and intrinsic semiconductor layer, simultaneously, exposing the portion of the first capacitor electrode by patterning the second insulation layer; depositing a transparent conductive electrode over the entire surface; and patterning the transparent conductive electrode by using a fourth mask process to form an electrode connecting layer connecting the first capacitor electrode with the gate line, to form a pixel electrode connected to the drain electrode via the drain contact hole, and to form a second capacitor electrode extended from the pixel electrode, overlapping the first capacitor electrode, and spaced apart from the electrode connecting layer.
In the method of fabricating the TFT array substrate, the gate electrode is beneficially made of Aluminum (Al) or of an Al-alloy. The method of fabricating the TFT array substrate further comprises the step of forming the gate contact hole exposing the portion of gate line and positioned at the one side of the first capacitor electrode by patterning the intrinsic semiconductor layer and first insulation layer. The method fabricates at least one gate contact hole. The contact hole penetrates the central part of the first capacitor electrode and is formed over the gate electrode. The method further comprises the steps of fabricating a storage capacitor, wherein the second capacitor electrode formed on the second insulation layer is over the first capacitor electrode.
USPTO Backgrounds
USPTO Backgrounds