This invention relates to computer systems of the type wherein a peripheral device makes requests to memory for data, and more particularly to systems wherein multiple memory modules are communicated with by means of a bus and in which several peripheral devices are likewise interconnected by a bus.
In some computer systems, peripheral devices such as magnetic disc memory units make requests to memory for data. Conventionally, in the performance of a number of such requests, each data request is handled separately. The peripheral device generates the request, this is transmitted eventually to a memory module, a read is performed at the module, and then the data is transferred back through intervening hardware to the peripheral unit. After this processing has been completed for the data from a first address, it is reinitiated for the next address from which data is desired.
Often a peripheral device will request a number of data words from addresses which form a sequence in memory. This is because the data words form some set or group which was written into memory addresses one after another in sequence. It has been recognized in accordance with the present invention that it is advantageous to detect when requests from a peripheral are of this sequential form, so that a request for a second data word can be initiated, before all the processing accompanying a first request has been completed. This "prefetching" of data anticipated to be requested provides an advantage, when operations processing the first request can be performed simultaneously with some of the activities fulfilling the second request. For example, the time that is required to read data from a memory module for one request can be used in the fulfillment of other requests to transmit data or addresses back and forth between memory and the peripheral and for handling the addresses or data at the peripheral.
In some systems, a number of devices communicate with plural memory modules interconnected by a bus. In addition, a number of peripherals may communicate with other parts of the system by means of an interconnecting bus. In such systems, the transfer of addresses and data on the buses can become time consuming, particularly where several devices compete for control of a bus. It then becomes particularly advantageous to be able to perform memory reads, memory bus transfers and peripheral bus transfers in an overlapping fashion.
USPTO Backgrounds
USPTO Backgrounds