Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are important building blocks of the vast majority of semiconductor integrated circuits (ICs). An FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FINFET is a type of transistor that lends itself to the goals of reducing transistor size while maintaining transistor performance. As illustrated in FIG. 1, the FINFET 200 is a non-planar, three dimensional transistor formed in part in a thin fin 212 that extends upwardly from a semiconductor substrate 214. FIG. 1 shows only one gate 216 and two fins 212 for simplicity although typically an integrated circuit can have thousands of fins and gates. The semiconductor substrate may be a bulk silicon wafer from which the fin structures are formed or may be a silicon-on-insulator (SOI) wafer disposed on a support substrate. The SOI wafer includes a silicon oxide layer and a silicon-containing material layer overlying the silicon oxide layer. The fin structures are formed from the silicon-containing material layer. The fin structures are typically formed using conventional photolithographic or anisotropic etching processes (e.g., reactive ion etching (RIE) or the like). The vertical gate 216 is disposed over the fins such that the two vertical sidewalls 218 of the fin form the channel of the transistor.
Replacement metal gate (RMG) processing is often used during FinFET formation. FIGS. 2-5 illustrate a conventional method for forming a portion of an integrated circuit 10 with a p-channel FET (PFET) 12 and an n-channel FET (NFET) 14 using an RMG process. Referring to FIG. 2, a dielectric material layer 16 overlies a semiconductor material 18. The semiconductor material is a fin structure of a non-planar transistor, such as, for example, a FinFET. The dielectric material layer is, for example, a silicon oxide. A first trench 20 corresponding to the PFET 12 and a second trench 22 corresponding to the NFET 14 are formed in the dielectric material layer 16. A gate dielectric layer 24 is deposited within the trenches. A first barrier material layer or combination of layers 26 is deposited overlying the gate dielectric layer 24 and a second barrier material layer or combination of layers 28 is deposited overlying the first barrier material layer or combination of layers 28. The first barrier material layer or combination of layers 26, for example, may be tantalum nitride overlying titanium nitride and the second barrier material layer or combination of layers 28, for example, may be titanium nitride. A mask material 30 is deposited overlying second barrier material layer or combination of layers 28 and a photoresist 32 is formed overlying mask material 30.
Referring to FIG. 3, the photoresist is patterned and the mask material 30 is correspondingly etched to cover a portion of the second barrier material layer 28 in trench 20. The second barrier material layer 28 then is etched from trench 22 and a portion of trench 20. Referring to FIG. 4, the photoresist 32 and the mask material 30 are removed and a work function material 34 is then conformally deposited within the trenches 20 and 22. The work function material, for example, is titanium aluminum (TiAl). An additional TiN layer (not shown) is deposited overlying the work function material, followed by the deposition of a gate electrode material 36, such as tungsten. Next, as illustrated in FIG. 5, a recess etch is performed to recess the gate electrode material 36 within the trenches 20 and 22.
The convention process of RMG results in high aspect ratio trenches that are difficult to fill. As illustrated in FIG. 5, deposition of tungsten often results in voids within the tungsten gate electrodes. If a void is present in a gate electrode, etch back of the gate electrode to remove the void results in removal of more of the gate electrode than is desired. In turn, such etch back of the tungsten to remove the voids results in gate electrode height variability. In addition, the conventional process leaves gate dielectric “stringers” 40. The stringers cannot be removed at this stage because, if the gate dielectric is hafnium oxide or a similar high-k dielectric constant material as is often the case, wet etching is ineffective to remove the stringers and a dry plasma etch of the gate dielectric stringers will damage the titanium nitride and tantalum nitride layers of the NFET 14. These defects are considered detrimental to threshold voltage performance.
Accordingly, it is desirable to provide methods for fabricating integrated circuits having replacement metal gates with improved threshold voltage performance. In addition, it is desirable to provide integrated circuits having replacement metal gates with improved threshold voltage performance. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.
USPTO Backgrounds
USPTO Backgrounds