As generations of processors and chipsets are scaled down to increase functionality and speed available in chip packages, designers must continually scale down cell structures to smaller and smaller dimensions to increase the density of cells per area of the substrate. In fact, the scaling theory predicts that processor sizes will decrease by half in each generation so a 50% area scalar is a goal when designing a smaller technology generation of integrated circuits. This persistent drive to scale processors and chipsets while increasing performance is pressuring designers to minimize pin count.
One current solution for reducing the pin count is to remove the interrupt pin(s) and request an interrupt service via a Message Signaled Interrupt (MSI) transaction. The MSI transaction is introduced in the Peripheral Components Interconnect (PCI) Local Bus Specifications [PCI Local Bus Specification, Revision 2.2, Dec. 18, 1998 available from the PCI Special Interest Group, Portland, Oreg., U.S.A, http://www.pcisig.com/] as an optional feature for PCI devices and a required feature for PCI Express (PCI-E) devices [PCI Express Base Specification, Revision 1.0a, Apr. 15, 2003 available from the PCI Special Interest Group, Portland, Oreg., U.S.A, http://www.pcisig.com/]. An MSI transaction enables a PCI device function to request an interrupt service by sending the MSI transaction as an inbound memory write on its PCI bus to the front-side bus (FSB). Because an MSI transaction is generated in the form of a memory write, MSI transactions support transaction conditions such as a retry, master-abort, target-abort or normal completion. As added benefits, MSI transactions simplify board design by removing out of band interrupt routing and represent another step towards a legacy-free environment.
A significant drawback of MSI transactions is the latency involved with servicing an interrupt. For instance, when a PCI, PCI Extended (PCI-X) [PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0, Sep. 22, 1999 available from the PCI Special Interest Group, Portland, Oreg., U.S.A, http://www.pcisig.com/], or PCI-E device requests an interrupt service using MSI, the device generates a MSI transaction, which is a double word (DWORD) including a system-specified message and a system-specified address. Once a processor receives the MSI transaction, the processor must transmit a request to the requesting device function to retrieve data required to service the interrupt. The processor may then service the interrupt upon receipt of a response from the PCI device. However, the latency involved with transmitting a message back to the PCI device and receiving the response from the PCI device is relatively long. Thus, each interrupt serviced via a MSI transaction involves a long latency and adds traffic to, e.g., the FSB, memory controller hub (MCH), and, in some cases, the input-output controller hub (ICH).
USPTO Backgrounds
USPTO Backgrounds