1. Field of the Invention
The invention relates to an optical semiconductor device to be fabricated employing an SOI substrate, and more particularly to a plane-type optical semiconductor device such as a plane-type light-emitting device and a plane-type light-receiving device which is capable of emitting or receiving a light perpendicularly to a plane of an SOI substrate.
2. Description of the Related Art
As an integrated circuit to be used for optical communication, there has been used optical transmission and reception modules employing III-V compounds and an transceiver for optical communication. For instance, there has been used an optical communication module having a silicon IC mounted therein which includes an InGaAsP/InP laser diode (LD) chip and a circuit for driving the chip, and an optical communication module having a silicon IC mounted thereon which includes an InGaAs/InP Pin photo diode (PD) chip and a signal amplifier. There has been also used a transceiver for optical communication having a silicon IC mounted therein which includes a LD chip, a PD chip, a driver circuit for optical transmission, and a amplifying circuit for optical reception.
In order to reduce fabrication costs, it is desired to be able to apply silicon process to the above mentioned devices. Thus, optical devices employing SiGe has been researched and studied in order to accomplish Si-OEIC having LD, PD and IC all of which are integrally formed in a single device.
For instance, there has been reported electricity-light transfer at room temperature (RT) in a mesa-type diode having a Si/SiGe super lattice layer formed on a silicon substrate in "Room-temperature 1.3 .mu.m electroluminescence from strained Si.sub.1-x Ge.sub.x /Si quantum wells", Q. Mi et al., Applied Physics Letters, Vol. 60, No. 25, June 1992, pp. 3177-3179.
For another instance, Japanese Unexamined Patent Publication No. 62-66668 has suggested Si-OEIC wherein an integrated circuit and a laser diode, a photo diode or a photo transistor having a Si/SiGe super lattice layer are formed on a common substrate.
Those suggested devices are fabricated by forming a super lattice structure having alternately deposited Si and SiGe layers by growth as a light transmission section or a light reception section, forming a highly doped layer by growth which will make an electrode, and etching in a mesa-configuration. By employing a super lattice structure, it is possible to increase a total thickness of light absorption layers made of SiGe with the result of improvement in electricity-light transfer efficiency.
FIG. 1 is a cross-sectional view illustrating a device used by Q. Mi et al. for measurement of electricity-light transfer in a light emitting device. The illustrated device is fabricated by the steps of forming an N+ type epitaxial layer 103 by growth on an N type silicon substrate 101, forming a non-doped silicon epitaxial layer 107, a Si/SiO.sub.0.65 Ge.sub.0.35 super lattice layer 108, a non-doped silicon buffer layer 109 and a P+ type contact layer 110 on the N+ type epitaxial layer 103 on this order, etching a resultant in mesa-configuration so that the N+ type epitaxial layer 103 is partially etched in thickness-wise direction thereof, covering a resultant with a silicon dioxide film 112, forming holes at P and N regions with the silicon dioxide film 112, and forming electrodes 113-1 and 113-2 on the P and N regions, respectively. Thus, there is completed a diode. The illustrated device or diode would perform electricity-light transfer to thereby emit light having a wavelength of 1.3 .mu.m when a pn junction thereof is forward-biased.
FIG. 2 is a cross-sectional view illustrating a light emission section and a light receiving section in Si-OEIC suggested in the above mentioned Japanese Unexamined Patent Publication No. 62-66668. The illustrated device is fabricated by the steps of forming an N type silicon layer 222, an Si/SiGe super lattice layer 208 and a ptype silicon layer 223 by successive growth on a silicon substrate 201, etching the layers 223, 208, 222 in mesa-configuration, further etching the silicon substrate 201 for separating the light emission section and the light reception section from each other, filling holes, which were formed by etching, with silicon dioxide to thereby form device isolation regions 221 in the silicon substrate 201, covering a resultant with a silicon nitride film 224, forming lower electrodes 213-1a and 213-1b on and in electrical connection with the N type silicon Layers 222, and forming upper electrodes 213-2a and 213-2b on and in electrical connection with the p-type silicon layer 223.
The conventional devices illustrated in FIGS. 1 and 2 have problems as follows. The light emitting device suggested by Q. Mi et al. (FIG. 1) has a problem that it cannot provide a light emission efficiency expected to have in general plane-type light emitting devices. The reason is that there is only provided the N+ type silicon layer 103 below the Si/Si.sub.0.65 Ge.sub.0.35 super lattice layer 108, and hence the N+ type silicon layer 103 cannot sufficiently act as a reflection layer.
In addition, since the above mentioned light emitting and receiving devices as illustrated in FIGS. 1 and 2 are configured in mesa-type, it is unavoidable that there are formed large steps on a silicon substrate. Such large steps make it difficult to form internal circuits together with the light emitting and receiving devices on a common chip. The reason is as follows. It is preferable for transistors used for internal circuits to have a planar structure, because integration would be accomplished relatively readily. However, if transistors are to be fabricated to have a planar structure, it would be quite difficult to form the planar type transistors and the mesa type light emitting and receiving devices by the same fabrication process.
USPTO Backgrounds
USPTO Backgrounds