The present invention relates to integrated circuits, and, more particularly, to an integrated capacitor on a silicon substrate.
It is common practice to design integrate circuits with one or more high value integrated capacitors, which advantageously replace conventional discrete capacitors. Integrated capacitors have various applications in the field of analog and RF circuits. These applications include filtering supply voltages in resonant antenna circuits, for example.
Among the known integrated capacitors, capacitors with metal electrodes have several advantages when compared to capacitors with polysilicon electrodes. Metal electrodes have an excellent electrical conductivity, whereas polysilicon electrodes need a silicide formation process in the presence of a metal like tungsten or titanium to have the same effect.
Capacitors with metal electrodes are very easy to manufacture. The lower electrode is generally made from one of the last metal layers of the integrated circuit, such as the metal layer used to make conductive tracks, for example. Compared to conventional methods of manufacturing integrated circuits, the design of a capacitor with metal electrodes only needs a step of depositing a dielectric layer on a pre-existing metal layer that is used as a first electrode layer, and a step of depositing a second electrode metal layer thereon. The dielectric layer is deposited at a moderate temperature of about 400xc2x0 C. so that the metal layer of the first electrode is not damaged. Capacitors with metal electrodes have a small parasitic capacitance with respect to the silicon substrate because they are made, as just described, on one of the last levels of the integrated circuit.
However, capacitors with metal electrodes present a poor voltage linearity. The voltage linearity is defined by the ratio xcex94C/C, where C is the value of the capacity at a voltage equal to zero and xcex94C is the variation of the capacity C according to the applied voltage. The ratio xcex94C/C of a capacitor with metal electrodes is typically on the order of 200 10xe2x88x926/V, i.e., a linearity defect that is at least 10 times above the value which is generally tolerated by designers of analog integrated circuits.
For this reason, capacitors with metal electrodes have at present only a few applications in the field of analog and RF circuits in spite of the advantages as discussed above. After various studies, the inventors of the present invention have hypothesized that the non-linearity phenomenon, which appears only in capacitors with polysilicon electrodes, is linked to the fact that the dielectric is deposited at a moderate temperature. This results in the incorporation of many impurity atoms (H, N, C . . . ) and the creation of many interface states, generally taking the form of pending linkages.
Furthermore, capacitors with metal electrodes, unlike capacitors with polysilicon electrodes, are not subject to a high temperature anneal. A high temperature anneal is conventionally performed with a temperature on the order of 850xc2x0 C. during several tens of minutes. In the manufacturing process of integrated circuits, conventional annealing steps for dopant activation are always performed before depositing the metal layers to avoid damaging them.
Thus, it appears that the poor voltage linearity of capacitors with metal electrodes is linked to the presence of impurities in the dielectric and/or to an incomplete formation of the dielectric that a high temperature annealing causes to partly disappears. This is confirmed by equations (1) to (3), which respectively provides the value of an electric capacity C as a function of the absolute permittivity ∈ of the dielectric, and the value of the permittivity ∈ of the dielectric as a function of the voltage V or the electric field E applied to the capacitor. The three equations are as follows:
C=∈*S/dxe2x80x83xe2x80x83(1)
∈=∈0+A+B*E2xe2x80x83xe2x80x83(2)
∈=∈0+A+B*V2/d2xe2x80x83xe2x80x83(3)
The variable S is the surface of the electrodes of the capacitor, d is the distance between the electrodes or a thickness of the dielectric, ∈0 is the permittivity of the vacuum, A is a constant and B is a quadratic term multiplied by the square of the applied voltage.
It is clear that the variations of a capacity according to voltage are due to variations of the permittivity ∈ of its dielectric, and, more particularly, to the existence of the quadratic term B. The quadratic term B is generally very small compared to the constant A.
However, the thickness d of the dielectric of an integrated capacitor is very small, e.g., on the order of some tens of nanometers, and supports a voltage of a few volts. In these conditions, the electric field E, equal to V/d, is very high and the effect of the quadratic term is no longer negligible. For example, a capacitor having a dielectric with a thickness of 30 nm subject to a voltage of 3V supports a very high electric field of 108V/m.
In view of the foregoing background, it is an object of the present invention to provide an integrated capacitor presenting a satisfactory voltage linearity without necessarily requiring a high temperature anneal, as well as a method of manufacturing the capacitor.
Another object of the present invention is to provide a low temperature dielectric having a quadratic term as small as possible, and a manufacturing method of such a dielectric.
These and other objects, features and advantages are provided by a dielectric comprising a homogeneous combination of molecules of at least two dielectrics having permittivities varying in an opposite way according to the electric field. The proportion of each dielectric in the combination is chosen so that the combination presents a permittivity that is less sensitive to the electric field.
According to one embodiment, the dielectric comprises SiOxNy, with x being different from y.
The present invention also relates to a capacitor integrated on a silicon substrate. The capacitor preferably comprises layers of first and second electrodes, and a dielectric layer therebetween.
The dielectric layer comprises a homogeneous combination of molecules of at least two dielectrics having permittivities varying in an opposite way according to the electric field. The proportion of each dielectric in the combination is chosen so that the capacitor presents a satisfactory voltage linearity.
According to one embodiment, the dielectric is of the SiOxNy type, with x being different from y. The material forming the layers of first and second electrodes is preferably chosen from the group comprising aluminium, copper, tungsten, titanium, titanium nitride and their alloys.
The invention also relates to a method of manufacturing a capacitor integrated on a silicon substrate. The method comprises depositing a first electrode layer, depositing a dielectric layer, and depositing a second electrode layer. Depositing the dielectric layer comprises depositing a homogeneous combination of molecules of at least two dielectrics having permittivities varying in an opposite way according to the electric field. The proportion of each dielectric in the combination is chosen so that the capacitor presents a satisfactory voltage linearity.
According to one embodiment, the two combined dielectrics are silicon oxide and silicon nitride. The dielectric comprises a composition of SiOxNy, with x being different from y. The proportion of each dielectric in the combination is determined by preliminary experiments by observing the voltage linearity of test capacitors comprising various dielectric proportions.
The dielectric is preferably deposited under vapor phase, and the proportion of each dielectric in the combination is in particular determined by an adjustment of the gaseous rates of the gases forming each of the dielectrics of the combination. The layers of the first and second electrodes are preferably made of a material chosen from the group comprising aluminium, copper, tungsten, titanium, titanium nitride and their alloys.
USPTO Backgrounds
USPTO Backgrounds