1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a CMOS transistor structure which provides for footprint savings.
2. Description of the Background Art
In employing a CMOS (Complementary Metal Oxide Semiconductor) transistor structure to form a semiconductor device, there is a need of connecting one of opposite N+-type active regions of an n-channel MOS transistor and one of opposite P+-type active regions of a p-channel MOS transistor, each of which is located in an outer portion of the CMOS transistor structure formed of the n-channel MOS transistor and the p-channel MOS transistor. Also, a wire connecting the N+-type active region and the P+-type active region should be disposed so as to be spatially separated from a gate electrode in order to avoid electrical connection between the wire and the gate electrode. Additionally, one example of a semiconductor device with a CMOS transistor structure is a CMOS inverter.
Another example is a nonvolatile semiconductor memory device as disclosed in Japanese Patent Application Laid-Open No. 2000-323590 (pages 9 through 12 and FIGS. 1 through 8), in which an interconnect layer buried in a self-aligned contact and a gate electrode are prevented from being short-circuited to each other.
While there has been no significant progress or change in a semiconductor device with a CMOS transistor structure with respect to a function thereof, attempts have been made with respect to a configuration, to reduce a footprint of the CMOS transistor structure. However, in accordance with conventional practices, reduction of a footprint of a CMOS transistor structure in a semiconductor device has been subject to some constraints. One constraint is that a gate electrode and a wire connecting an N+-type active region and a P+-type active region should not overlap each other in plan view, in order to prevent the wire and the gate electrode from being electrically connected to each other. Another constraint is that a predetermined distance should be kept between the gate electrode and the wire connecting the N+-type active region and the P+-type active region, in order to allow for variations possibly caused during formation of the wire in manufacture of the device (an alignment error, for example).
USPTO Backgrounds
USPTO Backgrounds