1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memories such as EEPROMs store data by injecting electrons into a charge accumulation layer of a memory cell and thereby changing the threshold voltage of the memory cell. In general, a state that the threshold voltage is high and no current flows through the memory cell during a read operation is a state that data “0” has been written (0-state, programmed state), and a state that the threshold voltage is low and a current flows through the memory cell during a read operation is a state that data “1” has been written (1-state, erased state). A 0-state or a 1-state is detected by comparing a current (memory cell current) that flows through the memory cell during a read operation with a reference current that flows through a reference memory cell. The outline of this kind of nonvolatile semiconductor memory is disclosed in Japanese Unexamined Patent Application Publication No. 6-61505, for example.
In general byte-rewrite-type EEPROMs, data can be written or erased on a memory cell basis. However, in EEPROMs, a select gate (select transistor) needs to be provided for each memory cell to connect a gate line (word line) and a bit line to the control gate of each memory cell. As a result, the memory cell area is large and hence EEPROMs are not suitable for large-capacity storage.
On the other hand, flash memories have been developed in which the memory cell area can be reduced though the unit of data rewriting is increased. Flash memories do not have select gates and each word line is connected to the control gates of plural memory cells together. Each source line is wired so as to be common to each of blocks that are a unit of rewriting. In flash memories, an erase operation is performed on a block-by-block basis or a full-chip basis. In general flash memories, the minimum unit of erasure (block size) is about 8 Kbytes.
Although flash memories of the above kind enable construction of a large-capacity memory, they have a disadvantage that data cannot be rewritten on a memory cell basis. As such, flash memories of the above kind are restricted in use.
In general, not all memory cells have the same characteristic. Therefore, even if the same electric field is applied to memory cells, resulting threshold voltage variations are not identical. That is, charge exchange rates vary. In flash memories, data of the memory cells in a block are erased together. Therefore, if a memory cell that is high in the tendency to release electrons from a charge accumulation layer exists in a block, the threshold voltage of that memory cell becomes negative (over-erased cell) during an erase operation.
FIG. 1 shows an attempt to read data from a memory cell that is connected to the same bit line as an over-erased cell is connected to. This example is directed to a NOR-type flash memory.
In the figure, electrons are accumulated in the floating gate of a memory cell MC1 as a result of a write operation and a logical value “0” is stored there. Memory cells MC2 and MC3 store a logical value “1” because electrons have been released from their floating gates as a result of an erase operation. Because of a high charge exchange rate, the threshold voltage of the memory cell MC2 is made negative (over-erased cell) as a result of the preceding erase operation.
To read data from the memory cell MC1, a high voltage “H” is supplied to a word line WL1 that is connected to the memory cell MC1 and a low voltage “L” (e.g., ground potential) is supplied to word lines WL2 and WL3 that are connected to the other memory cells MC2 and MC3. The ground voltage is supplied to a source line SL.
If the threshold voltages of the memory cells MC1–MC3 were set at correct values, no current would flow from a bit line BL to the source line SL even if the voltage of the word line WL1 is set at the high voltage “H.” Therefore, it could be judged as a result of the read operation that a logical value “0” is stored in the memory cell MC1. However, since the memory cell MC2 is in the over-erased state, a current flows from the bit line BL to the source line SL via the memory cell MC2 even if the gate voltage of the memory cell MC2 is 0 V. As a result, it is judged that a logical value “1” is stored in the memory cell MC1. That is, the presence of the over-erased cell causes incorrect data reading.
One measure for preventing over-erasure is to manage the threshold voltage of each memory cell so that it is set higher than usual in an erased state. However, in this case, the difference between a threshold voltage of a memory cell in an erased state and that of the memory cell in a written state is decreased. This lowers the read margin.
Another measure for preventing over-erasure is to apply erasing voltages plural times in a divisional manner. Threshold voltage variations are reduced and an event that many memory cells are rendered in an over-erased state at one time is thereby prevented. A measure for enabling an easy recovery from an over-erased state even in the event of the over-erasure is also taken. However, in this case, the erase time is increased.
USPTO Backgrounds
USPTO Backgrounds