1. Field of the Disclosure
The present disclosure is generally directed to the manufacture of semiconductor devices, and, more specifically, to various methods of forming a novel self-aligned channel drift MOS (SCDMOS) device.
2. Description of the Related Art
Lateral double diffused metal oxide semiconductor (LDMOS) field effect transistor devices are used in many applications, such as power management for cell phones, ADSL drivers, LED displays, LCD display drivers, high power amplifiers for wireless base stations, etc. LDMOS devices are sometimes referred to as so-called “drift MOS” devices, and they can be manufactured as either an N-type device or a P-type device. LDMOS devices are typically formed in an epitaxial layer deposited or grown on a semiconductor substrate. An LDMOS transistor has a source region separated from an extended drain region by a channel. The dopant distribution in the channel region is formed by lateral diffusion of dopants from the source side of the channel region, forming a laterally graded channel region. The source region and extended drain region are of the same conductivity type (e.g., N-type), while the epitaxial layer and the channel region are of the opposite conductivity type (e.g., P-type). A gate electrode is used to actuate the LDMOS transistor. LDMOS transistors are used extensively in RF applications because of their advantageous linearity, power gain and breakdown voltage characteristics.
FIG. 1A is a cross-sectional view that schematically depicts an illustrative embodiment of a prior art LDMOS device 10. In the depicted example, the illustrative LDMOS device 10 is an N-type device that is formed above a semiconductor substrate 12. Illustrative isolation regions (not shown) are formed in the substrate 12 to electrically isolate the LDMOS device 10 from other transistor devices. The device 10 generally includes a P-doped P-well 14, an N-doped N-well 16, an N+-doped source region 18 and an N+-doped drain region 20. The LDMOS device 10 further includes a gate structure 22 having a gate insulation layer 22A and a conductive gate electrode layer 22B, sidewall spacers 24 and a drain-side shallow trench isolation (STI) structure 19. As depicted, the drain-side STI structure 19 is positioned entirely within the N-well 16 and a portion of the drain-side STI structure 19 extends under the gate structure 22. In general, the drain-side STI structure 19 is provided to increase the drain resistance and to drop the voltage directly applied at the drain region 20 so that a reasonable potential is transferred at the gate on the drain side. That is, the STI structure 19 helps increase the voltage drop between the drain contact and the drain side of the gate structure 22. In some cases, the drain-side STI structure 19 may be omitted and the drain region 20 is simply laterally offset from the drain-side edge of the gate structure 22. The P-well 14 is formed so that it extends partially under the gate structure 22, but not all the way across the gate structure 22. Similarly, the N-well 16 is positioned such that it extends partially under the gate structure 22, but to a lesser degree than does the P-well 14. The channel length 30 of the device 10 shown in FIG. 1A is set by the portion of the gate structure 22 that is positioned above the P-well 14. The P-well 14 and the N-well 16 overlap by the distance 32. The dimension 34 is sometimes referred to as the “field-plate extension” because, in operation, the maximum electrical field is present at the gate corner on the drain side. The extension 34 of the gate effectively moves the location of the maximum electric field onto the STI structure 19 and away from the gate insulation layer 22A. The source region 18 is typically formed by performing both a lightly-doped extension implant region (prior to forming the spacer 24) and a heavier-doped deep source region. The drain region 20 is typically formed by only forming a deep heavier-doped drain region, i.e., the extension implant process is typically omitted when forming the drain 20. As can be observed from FIG. 1A, the channel length 30 of the device 10 is determined based upon the placement of the P-well 14 and the N-well 16. Any misalignment when forming the wells 14, 16 can impact the ultimate performance of the device 10. For example, if the N-well 16 is not positioned far enough under the gate structure 22 as intended by the design process, the channel length 30 of the device 10 will be greater than anticipated by the design process and the device 10 will operate slower than anticipated. Thus, extreme precision is required when positioning the wells 14, 16 in the substrate 12 and when forming the gate structure 22 to insure that all components of the device 10 are in their proper and intended relative positions.
FIG. 1B depicts another example of a prior art integrated circuit device 11 that includes of an illustrative N-type LDMOS device 11N and a P-type LDMOS device 11P that are formed in and above the substrate 12 and electrically isolated from one another by an illustrative STI region 21. In this example the N-type device 11N is formed above the P-well 14, while the P-type device 11P is formed above the N-well 16. Each of the devices includes a gate structure 22, spacers 24, a source region 18 and a drain region 20. In the embodiment depicted in FIG. 1B, the source/drain regions 18/20 are typically formed by forming both extension regions and deep doped regions in the substrate 12. Unlike the device 10 depicted in FIG. 1A, the device 11 includes a so-called silicide block layer 25 positioned on the drain regions 20 of the devices adjacent the spacers 24. As its name implies, the purpose of the silicide block layer 25 is to prevent the formation of a metal silicide material on the covered portion of the drain region 20 so as to effectively position the drain 20 farther away from the drain-side edge of the gate structure due to the very high electrical field present at the drain-side edge of the gate structure 22 when the devices 11N, 11P are in operation. The length of the silicide block layer 25 may vary depending upon the particular application, and it may be made of a variety of materials, e.g., silicon nitride. The operational usefulness of the illustrative LDMOS devices 11N, 11P depicted in FIG. 1B are typically limited by the junction breakdown voltages, which continues to decrease, especially in advanced CMOS applications that have very low drain voltages (Vdd).
Generally, the present disclosure is directed to various embodiments of a novel self-aligned channel drift MOS device (SCDMOS), and various methods of making such an SCDMOS device, that may solve or reduce one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds