1. Field of the Invention
The embodiments of the present invention relate to an electron emission device and a method of manufacturing the device, and in particular, to an electron emission device having an insulating layer with high aspect ratio openings and a manufacturing method thereof.
2. Description of Related Art
Generally, electron emission devices are classified into a first type where a hot cathode is used as an electron emission source and a second type where a cold cathode is used as the electron emission source.
Among the second type of electron emission devices are devices known as field emitter array (FEA) type devices, surface-conduction emission (SCE) type devices, metal-insulator-metal (MIM) type devices, and metal-insulator-semiconductor (MIS) type devices.
The FEA type electron emission devices are based on the principle that when a material having a low work function or a high aspect ratio is used as the electron emission source, electrons are easily emitted from the material in a vacuum when exposed to an electric field. A sharp-pointed tip structure including molybdenum (Mo) or silicon (Si) or a carbonaceous material, such as carbon nanotube, graphite and diamond-like carbon, has been developed to be used as the electron emission source.
In the FEA type electron emission devices, cathode electrodes, an insulating layer and gate electrodes are sequentially formed on a first substrate and openings are formed in the gate electrodes and the insulating layer. Electron emission regions are formed on the cathode electrodes within the openings. Phosphor layers and an anode electrode are formed on a surface of a second substrate facing the first substrate.
The insulating layer is formed through repeating a screen printing, drying and firing process several times such that it has a thickness of 5-30 μm. The insulating layer is patterned through wet etching to form openings. With the wet etching, as the etching is made in an isotropic manner, the insulating layer is etched in a horizontal direction as well as in a vertical direction. Accordingly, the width of the opening becomes larger than the depth of the opening, and as a result, the opening has an aspect ratio of 1 or less.
Such a phenomenon is more seriously manifested as the thickness of the insulating layer is increased and becomes a critical factor in making it difficult to conduct the micro patterning process. Accordingly, the pixels are not easily arranged on the first substrate in a compact manner and a desired high resolution display screen is not obtainable. As the number of electron emission regions arranged within a predetermined area of pixels is limited, it becomes difficult to emit a suitable amount of electrons.
USPTO Backgrounds
USPTO Backgrounds