1. Field of the Invention
The present invention relates in general to method and apparatus for fabricating semiconductor devices, and in particular to method and apparatus for implanting ions in a semiconductor device.
2. Description of Related Arts
The continuing trend in shrinking geometries and increasing monolithic integration and density of semiconductor devices has required more precise control of the process of implanting impurities. Moreover, improvements in semiconductor manufacturing tools used in production and processing of these devices are required in view of mass production technology. This applies to ion implantation methods that are commonly employed in the processing of semiconductor devices. Ion implantation involves ionizing impurities and scanning the impurities in a predetermined region on a substrate to implant a predetermined amount of impurities in a desirable region.
The ion-implantation method makes it possible to selectively implant impurities and to implant impurities having a high purity. The ion-implantation method also allows precise control of impurities, thereby providing excellent reproducibility and uniformity. The method is essential to control doses of implanted impurities, which is accomplished by measuring the ion beam current.
In fabricating a semiconductor device, distribution across the semiconductor wafer of the critical dimension (CD) of a transistor gate is directly related to yields of products. Accordingly, a control of the distribution of the CD is very important in semiconductor device manufacturing, and great efforts are made to control the distribution of the gate's CD through a mask process, an etching process and a sidewall spacer depositing process.
However, it is difficult to control variation in transistor parameters according to locations of a substrate by distribution of the gate's CD and a process for forming spacers on sidewalls of the gate. When using a substrate with a diameter greater than 300 mm, variation in the transistor parameters becomes a severe problem as the semiconductor device becomes increasingly smaller. That is, the gate hard mask and the gate pattern etching process do not have a fixed size according to the location of the substrate. Accordingly, the sizes of the gates become different, thereby generating a difference in the transistor parameters due to different lengths of the gate.
Accordingly, to control the gate's CD distribution, a new method for a photo-exposure process to a central portion and edge portions of the substrate has been developed. Also, there is an effort to perform a new process and develop equipment for improving the distribution within the substrate during the process for forming the spacers on the sidewalls of the gate and the process for patterning the gate using the etching process.
However, no method has been found for improving the distribution of the substrate and semiconductor devices are now developed without controlling the difference of the transistor parameters according to the locations of the substrate.
Furthermore, process margins are much more reduced due to a continuous size reduction of semiconductor devices, thereby inducing a problem of causing more reduction in the yields of the products created by the distribution of the gate's CD.
That is, in case of a minimum size of the gate's CD is 200 nm, the product yields are not much reduced even though the distribution of the gate's CD is ±10%. However, when the minimum size of the gate's CD is 100 nm and the distribution of the gate's CD is ±10%, a decrease in the product yields becomes a serious problem. Accordingly, the distribution should be controlled in a range within approximately ±5%.
However, the process margin due to the continuous size reduction of semiconductor devices greatly decreases, thereby making it difficult to increase the yields of the products because of the difficulty in control of the distribution and a decrease in throughput.
FIG. 1 is a diagram briefly illustrating a conventional ion-implantation apparatus.
Referring to FIG. 1, a conventional ion implanter performs the ion-implantation on the entire surface of a substrate 11 by scanning an ion beam 13 back and forth in a direction of X denoted with {circle around (X)}{circle around (•)}, i.e., in a horizontal direction, due to either electric fields or magnetic fields, and by scanning substrate 11 fixed in a holder 12 back and forth in a Y direction, i.e., in a vertical direction substantially perpendicular to the X direction. Herein, ion beam 13 is irradiated by substrate 11 fixed in holder 12 and then, ion implantation is accordingly performed on substrate 11. At this time, substrate 11 is scanned back and forth in the Y direction by a driving axis 15 connected to a driving device 14.
As explained above, the conventional ion implanter can perform a uniform ion implantation to the entire surfaces of the substrate 11 by scanning the ion beam 13 back and forth in the X direction and by scanning the substrate 11 back and forth in the Y direction. That is, for the uniform ion implantation, scanning speeds in the X and Y directions are identically applied.
However, the uniform ion implantation explained above uniformly implants the ion within the substrate and from the substrate to the substrate without any relation to the distribution of the gate's CD, thereby generating a big difference in an electrical property even within the substrate according to the distribution of the gate's CD.
That is, the electrical property tends to be different according to locations of the semiconductor device on the substrate. For instance, even though a degree of uniformity of the ion-implantation is very high, semiconductor device parameters in the edge portions of the substrate tend to be different from the central portion of the substrate. Therefore, the electrical property of a threshold voltage of a transistor in the semiconductor device parameters are different between the central portion of the substrate and the edge portions of the substrate.
USPTO Backgrounds
USPTO Backgrounds