The present invention concerns a matrix-addressable array of integrated transistor/memory structures, wherein the array comprises one or more layers of semiconducting material, two or more electrode layers, as well as memory material contacting electrodes in said at least two electrode layers, wherein the memory material is a polarizable dielectric material capable of exhibiting hysteresis, particularly a ferroelectric or electret material, wherein the electrodes in said at least two electrode layers in each layer are provided as continuous or interrupted parallel extended structures, wherein said at least one layer of a semiconducting material and said at least two electrode layers form field-effect transistor structures, wherein the electrodes of a first electrode layer form the source/drain electrode pairs of said field-effect transistor structures, wherein the electrodes of an adjacent second electrode layer forms the gate electrode of the field-effect transistor structures, the gate electrodes in any case are provided in a substantial orthogonal orientation relative to the electrodes of the first electrode layer.
A major problem in modern computing is the physical split between storage devices and processing units, more specifically between CPUs and operating software, user software and user data. Recent improvements in effective Cpu speeds (e.g. the development from Pentium II onwards) has been enabled by integrating increasingly more memory capacity inside the CPU (SRAM/EEPROM), however, the overall speed is still seriously hampered by the fact that most software and data still uses the hard disk as primary storage medium. Although the transfer rate of hard disks has improved in recent years, as have the capacity of buses, the maximum speed potential is still controlled by the very slow access speed of the hard disks, a speed which barely has improved in the last 10-15 years, and which will not improve substantially either as long as this primary storage medium remains a mechanically operated device.
If the bulk of data now using the hard disk could utilize memory capacity inside the CPU itself, not just would the speed gains become extreme, even more important could be the fact that entirely novel types of processing and computing devices could be envisaged, opening up for new approaches to (parallized) software, much more adapted to solving complex problems (e.g. non-indexed searches, continuous speech recognition, artificial intelligence, etc.).
The increasing incompatibility between storage devices and processing units deriving from the physical split therebetween not only leads to severe capacity problems, but is also causing latency and inefficient exploitation of high-speed processing circuitry.
Hence, a major object of the present invention is to obviate or eliminate the above problems by introducing a novel architecture allowing the integration of non-volatile memory and high-speed transistor circuitry which can be applied to inorganic as well as organic electronics or hybrids thereof, and which moreover is not limited to planar devices, but equally well applicable to volumetric devices.
The above object as well as further advantages and features are realized with the matrix-addressable array according to the present invention, which is characterized in that the source and drain electrodes of a single transistor/memory structure are separated by a narrow vertical recess extending therebetween and down to the semiconducting layer, that the transistor channel is provided in the semiconducting layer beneath the recess between the source and drain electrodes, that the source and drain regions of the transistor structures are provided beneath the source and drain electrodes at either side of the transistor channel, that the memory material is provided filling the recess between the source and drain electrodes and covering the top surfaces thereof, that a gate electrode is provided contacting the memory material whereby the transistor channel is defined with a length L corresponding to the width of the recess and a width W corresponding to the width of the gate electrode, L being a fraction of W, and that three memory cells are defined in the memory material respectively between the source electrode and the gate electrode, between the drain electrode and the gate electrode and in the recess between the source and drain electrodes.
In an advantageous embodiment of the matrix-addressable array according to the present invention the transistor/memory structure comprises a third electrode layer of semiconducting material opposite the source and drain electrode layer, said third electrode layer comprising a second gate electrode extending in the same direction as the first gate electrode and registering therewith, whereby the transistor/memory structure is realized as a dual gate field-effect transistor.
According to the invention the first memory cell contacts the source and the gate electrodes, the second memory cell contacts the drain and the gate electrodes, and the third memory cell contacts the source and the drain electrodes. In the latter case the memory material in the third memory cell preferably has a thickness different from that of the first and second memory cells, and in that case the memory material preferably is a ferroelectric or electret organic material, preferably a polymer or copolymer.
In the matrix-addressable array according to the invention the semiconducting material advantageously is an inorganic semiconducting material, preferably amorphous silicon, polycrystalline silicon or microcrystalline silicon; or the semiconducting material is advantageously an organic semiconducting material, preferably a semiconducting polymer or pentacene.
In a second advantageous embodiment of the matrix-addressable array according to the invention an additional transistor memory is provided in registration with the first single transistor/memory structure opposite the gate electrode thereof and inverted in relation to the first single transistor memory structure, said additional transistor/memory structure sharing the same gate electrode with the latter, thus realizing a dual transistor/memory structure with common gate and six memory cells, and then the dual transistor/memory structure preferably realizes a common gate complementary field-effect transistor. In a variant of this second embodiment the dual transistor memory structure advantageously is provided with at least one additional gate electrode, said at least one additional gate electrode being provided on one of the layers of semiconducting material opposite the source/drain electrode layer.
In a third advantageous embodiment of the matrix-addressable area according to the invention, the matrix-addressable array is realized as a three-dimensional array by stacking two or more two-dimensional arrays of transistor/memory structures, and that a two-dimensional array is isolated from an adjacent neighbouring two-dimensional array by a separation layer, and then the separation layer preferably is selected as one of the following, viz. a layer of insulating material, a layer of conducting or semiconducting material coated to form an insulating barrier, or a layer of conducting or semiconducting material surface-oxidized to form the insulating barrier.
USPTO Backgrounds
USPTO Backgrounds