With the advancement of integrated circuit formation technology, the device sizes are scaled down. The device operating voltages (power supply voltages) are also lowered, and applications utilizing increasingly higher frequencies are demanded. As such, the circuit dynamics have started posing issues during operations of integrated circuits formed using recent generations of technologies.
Since the device operating voltages kept declining over years, the device operating voltages, being a potential contributor to the devices' operation, became increasingly important due to their impact on performance and reliability. For example, the device operating voltages have been reduced to about 0.9 volts, or even lower. As a result of such a low voltage, even a few tens of milli-volts in the reduction in the device operating voltages may cause a noticeable impact to the device performance and operation, and chips may fail to meet the target speeds. Also, the reliability of the integrated circuits is adversely impacted since devices may fail to operate if the device operating voltages are lower than certain threshold values.
In an integrated circuit, several factors contribute to the voltage fluctuation, including the power network parasitic and ground network parasitic; the operational speed of the integrated circuit; the intrinsic decoupling capacitances offered by non-switching logic; decoupling capacitors intentionally placed to supply the peak requirement during switching; and the package parasitic. There are two types of voltage drops, namely static voltage drops and dynamic voltage drops. The static voltage drops occur when circuits are at a steady state, while the dynamic voltage drops occur during the switching of signals. From the circuit point of view, the static voltage drops are caused by the resistances in supply and return current paths, and are easy to control through carefully planning the power delivery network. For example, by using upper metal layers (which are thicker than lower metal layers) to deliver the power to circuits, the resistances in power networks and ground networks may be reduced. Also, by placing the blocks/macros according to the current demand, lower static voltage drops may be achieved.
The dynamic voltage drops, on the other hand, are caused by transient currents. Accordingly, controlling dynamic voltage drops is relatively difficult due to their unpredictable nature. In a known approach, designers computed the peak currents for given areas/blocks and the intrinsic capacitance provided by the circuits residing nearby, and then determined the amount of charge that is to be compensated for by using on-chip decoupling capacitors. The additional approaches for solving the dynamic voltage drop problem include placing decoupling capacitors according to the peak-current demands of the integrated circuits.
The conventional approaches for solving the dynamic voltage drop problem, however, suffer from drawbacks. For example, the decoupling capacitors leak when they are idle, and decoupling capacitors consume additional chip areas. Also, modifying the power distribution network is tedious and time consuming as routing has been already done.
On the other hand, although redundant connections may be manually added between power straps to reduce both static and dynamic voltage drops, the method is tedious and error-prone. U.S. Pat. No. 7,240,314 discloses such a method of adding redundant connections by utilizing dummy metals to form redundant straps. However, in this approach, since the dummy metals are not checked by optical proximity correction (OPC), it is not guaranteed that a connection may be made correctly in real silicon chips.
USPTO Backgrounds
USPTO Backgrounds