The present disclosure relates to a solid-state imaging element and manufacturing method of the same and electronic equipment, and more particularly, to a solid-state imaging element and manufacturing method of the same that provide compatibility between excellent sensitivity and smear characteristics, and to electronic equipment having the same.
Solid-state imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCDs (Charge Coupled Devices) have found wide application to digital still cameras and digital video camcorders. Further, recent years have witnessed frequent use of a MOS image sensor in the solid-state imaging element incorporated in mobile phones and mobile devices having imaging capability for its low source voltage and low power consumption.
For example, incident light falling on a CMOS image sensor is converted into charge by a PD (Photodiode), i.e., a photoelectric conversion section of each pixel. Then, the charge generated by the PD is transferred to an FD (Floating Diffusion), i.e., a floating diffusion region, so that an amplifying transistor outputs a pixel signal whose level is proportional to the charge accumulated in the FD.
Incidentally, a CMOS image sensor performs rolling shutter image capture in which charge is transferred from the PD to FD on a pixel row by pixel row basis, thus resulting in image distortion. In order to avoid such distortion, it is necessary to perform global shutter image capture in which charge is transferred from the PD to FD in all pixels at the same time.
For example, Japanese Patent Laid-Open No. 2011-29835 proposes a CMOS solid-state imaging device that permits simultaneous storage of an image for global shutter image capture by providing a storage element (capacitor) in each pixel.
In a CMOS solid-state imaging device configured to permit global shutter image capture by providing a storage element in each pixel, a smear may occur due to light leaking into the storage element while charge is held therein, thus resulting in degraded image quality attributable to light leaking thereinto. A possible countermeasure against such leakage of light into the storage element would be to use a light-shielding film adapted to shield light from the storage element.
It is, for example, possible to use an interconnect layer as a light-shielding film. However, it is preferred that a light-shielding film should be provided immediately on top of the storage element to ensure higher effectiveness. However, providing a metal light-shielding film immediately on top of the storage element leads to a thicker interlayer insulating film under the interconnect layer, thus resulting in deteriorated sensitivity. Further, in this case, it may be more difficult to form contacts, thus resulting in deteriorated yield. In particular, the larger the pixel count, and the larger the area occupied by peripheral circuitry, the greater the impact of the thicker interlayer insulating film under the interconnect layer tends to be.
In response thereto, Japanese Patent Laid-Open No. 2010-165753 (hereafter referred to as Patent Document 2) discloses a structure adapted to reduce the height of the interlayer structure by using a light-shielding metallic material as a gate electrode on top of the memory. However, it is difficult for the structure disclosed in Patent Document 2 to sufficiently suppress light leakage from the side of the gate.
Further, Japanese Patent Laid-Open No. 2010-177418 (hereafter referred to as Patent Document 3) discloses a structure designed to reduce the height by using a light-shielding film having a damascene structure. However, if the layout has a significantly high coverage ratio of the light-shielding electrode, the structure disclosed in Patent Document 3 leads to dishing in the metal film during the CMP (Chemical Mechanical Polishing) process adapted to form a damascene structure, significantly adversely affecting the pixel characteristics and later process steps. Among possible concerns are deterioration of light-shielding capability due to varying thickness of the light-shielding film, failure to open contacts in later process steps due to aggravation of the local and global flatness, generation of residue during patterning, and failure to open contacts due to defocusing during lithography.
As described above, it is significantly unfeasible that a countermeasure process will be achieved using the structures disclosed in Patent Documents 2 and 3.
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