The semiconductor device industry has a continuous market driven need to improve the operational speed of electronic devices. Previously improved operational speed has been obtained by scaling the devices to reduce the transistor size. Smaller transistors result in improved operational speed and clock rate, and reduced power requirements in both standby and operational modes. To reduce transistor size, the thickness of the silicon dioxide (SiO2) gate dielectric is reduced in proportion to the shrinkage of the silicon gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) might use a 1.5 nm thick SiO2 gate dielectric for a gate length of less than 100 nm. As such physical scaling continues, various issue may surface, such as short channel effect and junction leakage, and thin gate dielectrics may be a potential reliability issue with gate leakage and time dependent dielectric breakdown. Thus, as silicon based transistors scale down, they may be reaching their fundamental physical limitations of thin gate dielectrics, and very short silicon channels. Nevertheless, smaller, lower power consuming, and more reliable integrated circuits (ICs) will likely be needed for use in products such as processors, mobile telephones, and memory devices such as dynamic random access memories (DRAMs) in the future. It has been proposed to use a substrate material having higher charge carrier mobility (and thus relatively higher device speed) than the presently used silicon substrate, such as germanium. However, germanium has manufacturing issues and reliability concerns. It has also been proposed to use gate dielectrics with higher dielectric constants (k).
The semiconductor industry reliance upon the ability to scale the dimensions of its basic devices, such as the silicon MOSFET, to achieve improved operational speed and power consumption may have reached a physical limit. Device scaling includes scaling the gate dielectric, which has primarily been silicon dioxide (SiO2). A thermally grown amorphous SiO2 layer on a silicon substrate provides an electrically and thermodynamically stable material interface with superior electrical isolation. However, increased scaling and other requirements in microelectronic devices have created reliability issues as the gate dielectric has become thinner. One potential partial solution includes the use of materials with higher dielectric constants (k) which would allow a thicker physical dielectric thickness with the same equivalent electrical thickness, and thus address the gate leakage and time dependent dielectric breakdown issues.
The use of germanium substrates has been proposed as a partial solution to the short channel effect and junction leakage issues, since germanium has an electron mobility that is about two times higher than in silicon, and a hole mobility that is about four times higher than in silicon. However, substrate surfaces must have a low and repeatable trapped charge density and surface trap density, and germanium oxide is water soluble, has high current leakage and low dielectric breakdown voltage. It is thought that the thermal germanium oxide to germanium substrate interface may be too intrinsically disordered to be stable and provide a consistent interface state condition required for semiconductor manufacturing.
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