1. Field of the invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to an improved positive power supply for generating and supplying a regulated positive potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during programming.
2. Description of the Prior Art
In U.S. Pat. No. 5,077,691 to Sameer S. Haddad et al. issued on Dec. 31, 1991, there is disclosed a flash EEPROM array which includes a positive voltage charge pump 206. The '691 patent is assigned to the same assignee as in the present invention and is hereby incorporated by reference. During a sector-programming mode of operation, the charge pump 206 in FIG. 2B of the '691 patent generates a relatively high positive potential (i.e., +12 volts) which is applied to the control gates via the wordlines of the selected sectors while zero volts are applied to the control gates of memory cells in the non-selected sectors. Further, the source regions of all transistors in the selected sectors are pulled to a ground potential of zero volts, and the drain regions thereof are raised to a high positive level of approximately +6.5 volts.
In FIG. 5B of the '691 patent, there is shown a schematic circuit diagram of the positive charge pump circuit formed of four single-stages 502 for generating the high positive potential of approximately +12 volts to +15 volts. The positive charge pump circuit of FIG. 5B is used for the charge pump block 206 shown in FIG. 2B of the '691 patent. Further, in FIG. 4C there is depicted a low negative charge pump circuit formed of a single stage 402 for generating a relatively low level negative voltage of approximately -2.0 volts. The negative pump circuit of FIG. 4C is used for the charge pump block 208 shown in FIG. 2B.
In U.S. Pat. No. 5,126,808 to Antonio J. Montalvo et al issued on Jun. 30, 1992, there is disclosed a flash EEPROM array with page erased architecture which also includes a positive voltage charge pump. The '808 patent is also assigned to the same assignee as in the present invention and is hereby incorporated by reference. In FIG. 7E of the '808 patent, there is shown a schematic circuit diagram of the positive voltage charge pump, similar to FIG. 5B of the '691 patent, for generating the high positive potential of approximately +12 V. Further, in FIG. 7B there is illustrated a -13 volt charge pump 565 consisting of five interconnected single stage charge pumps 560. The output of the first stage 560-1 of the charge pump 565 is about -2.0 volts.
The present invention represents a significant improvement over the charge pump circuits shown in their respective '691 and '808 patents discussed above. The positive power supply of the present invention is used for generating and supplying a regulated positive potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during programming. The positive power supply includes a positive charge pump circuit formed of four charge pump stages for generating a high positive voltage. The positive power supply further includes a regulation circuit which is responsive to the high positive voltage and a reference potential for generating the regulated positive potential to be independent of a power supply potential VCC.
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