1. Technical Field
This invention relates generally to memory arrays, and more particularly, to sector decoding in such an array.
2. Background Art
FIG. 1 illustrates a flash memory array 50 of the prior art. This memory array 50 includes a plurality of memory banks (shown are banks BA and BB of a large number of memory banks). Each memory bank includes a plurality of sectors arranged in a column. For example memory bank BA includes sectors SA1-SA8 arranged in a column, memory bank BB includes sectors SB1-SB8 arranged in a column, and so forth. These columns of sectors are in parallel relation as illustrated FIG. 1. Each sector is operatively associated with a sector decoder as shown. For example, in memory bank BA, sector decoder SA1D is operatively associated with sector SA1, etc., while in memory bank BB, sector decoder SB1D is operatively associated with sector SB1, etc.
At the bottom of the array 50 are a plurality of read address lines R (including lines R1, R2, R3) and a plurality of write address lines W (including lines W1, W2, W3). The read address lines R1, R2, R3 communicate respectively with lines R1A, R2A, R3A, (which make up the plurality of lines RA), and the lines R1A, R2A, R3A in turn communicate with each of the sector decoders SA1D-SA8D. The read address lines R1, R2, R3 also communicate respectively with lines R1B, R2B, R3B (which make up the plurality of lines RB), and the lines R1A, R2A, R3A in turn communicate with each of the sector decoders SB1D-SB8D. The write address lines W1, W2, W3 communicate respectively with lines W1A, W2A, W3A (which make up the plurality of lines WA), and the lines W1A, W2A, W3A in turn communicate with each of the sector decoders SA1D-SA8D. The write address lines W1, W2, W3 also communicate respectively with lines W1B, W2B, W3B (which make up the plurality of lines WB), and the lines W1A, W2A, W3A in turn communicate with each of the sector decoders SB1D-SB8D. In addition, select decoders are included for selecting a particular memory bank. As illustrated, select decoder BAD has extending therefrom lines WSELA, RSELA which communicate with each of the sector decoders SA1D-SA8D, select BBD has extending therefrom lines WSELB, RSELB which communicate with each of the sector decoders SB1D-SB8D, etc.
It will be understood that while the present embodiment illustrates eight sectors in each bank, along with three read address lines R1, R2, R3 (capable of providing eight digital addresses) and three write address lines W1, W2, W3 (capable providing eight digital addresses), these numbers are chosen for illustrative purposes only and, for example, each bank may include more than eight sectors, for example 16 sectors which would be associated with four read address lines (for providing 16 digital addresses) and four write address lines (for providing 16 digital addresses).
Each of the select decoders BAD, BBD is identical in configuration, and the select decoder BAD is illustrated in FIG. 2. In selecting a bank, an external address EA is provided to a NAND gate 100 of the bank to be selected, for example, the bank BA. The signal from the NAND gate 100 is inverted by means of inverter 102, the output of which is provided to the gate of N channel transistor 104 and input to a NAND gate 106. The transistor 104 is in series with N channel transistor 108 and P channel transistor 109, with transistor 109 connected to Vcc and transistor 104 connected to ground. The node A between the transistors 108, 110 is connected to a latch 112 and also to an input to the NAND gate 106. With the signal to the gate of the transistor 108 low, and with the signal RSTB to the gate of the transistor 109 low, an address signal to the NAND gate 100 provides a low output therefrom which is inverted to a high output applied to the gate of the transistor 104 and input to the NAND gate 106. The node A is high, causing the output on line WSELA of the latch 112 to be low. At the same time, the node A provides a high signal to the NAND gate 106, providing a low output from the NAND gate 106 which is inverted by inverter 114 to provide a high output on line RSELA. To reverse these outputs, so that line WSELA is high and line RSELA is low, the input to the gate of transistor 108 is pulsed while the input signal RSTB is taken high so that node A is driven low, causing line WSELA to go high and line RSELA to go low. Each of the signals on lines WSELA, RSELA is provided to each of the select decoders SA1D-SA8D, each of the signals on lines WSELB, RSELB, is provided to each of the select decoders SB1D, SB8D, etc. The select decoders SA1D-SA8D, SB1D-SB8D are similar in configuration and will be described with reference to FIGS. 4 and 5.
FIG. 3 illustrates the array 50 of FIG. 1 with line RSELA high and line WSELA low, selecting bank BA and providing a read select signal to each of the sector decoders SA1D-SA8D (it is understood that the term “write” may include writing and erasing). Meanwhile, the signals on the lines R1, R2, R3 (read address), are provided as 111 respectively while the signals on the lines W1, W2, W3 (write address) are provided as 000 respectively. The select decoder SA8D includes AND gate 8120 and AND gate 8122 in parallel. The lines RSELA, R1A, R2A and R3A provide input signals to the AND gate 8120, while lines WSELA, W1A, W2A and W3A provide input signals to the AND gate 8122. The outputs of the AND gates 8120, 8122 are provided as inputs to NOR gate 8124, the output of which in turn is provided to inverter 8126. The output from the inverter 8126 is provided to the sector SA8. In the present example, and as illustrated also in FIG. 4, lines RSELA, R1A, R2A and R3A are high, providing a high output from AND gate 8120, while lines WSELA, W1A, W2A and W3A are low, providing a low output from AND gate 8122. This provides a low output from NOR gate 8124 and a high output from inverter 8126, so that a high (read address) signal is provided to sector SA8. Meanwhile, and with reference to FIG. 5, the high signal on line RSELA is provided to AND gate 7120 of sector decoder SA7B, while high signals on lines R1A, R2A are provided to AND gate 7120. As shown, the signal on line R3A is inverted by inverter 7128, and the output from inverter 7128 is input to AND gate 7120. The outputs of both AND gates 7120, 7122 are low, so the output from NOR gate 7124 is high and the output from inverter 7126 is low, so that a read address signal is not provided to sector SA7.
FIG. 6 illustrates the array of FIG. 3 again with line RSELA high and line WSELA low, selecting bank BA and providing a read select signal to each of the sector decoders SA1D-SA8D. Meanwhile, the signals on the lines R1, R2, R3 (read address), are provided as 110 respectively while the signals on the lines W1, W2, W3 (write address) are provided as 000 respectively. As described above, the lines RSELA, R1A, R2A and R3A provide input signals to the AND gate 8120, while lines WSELA, W1A, W2A and W3A provide input signals to the AND gate 8120. In this example, and as illustrated also in FIG. 7, lines RSELA, R1A, and R2A are high, while line R3A is low, providing a low output from AND gate 8120, while lines WSELA, W1A, W2A and W3A are low, providing a low output from AND gate 8122. This provides a high output from NOR gate 8124 and a low output from inverter 8126, so that a read address signal is not provided to sector SA8. Meanwhile, and with reference to FIG. 8, the high signal on line RSELA is provided to AND gate 7120 of sector decoder SA7B, while high signals on lines R1A, R2A are provided to AND gate 7120. The low signal on line R3A is inverted by inverter 7128, and the output from inverter 7128 is input to AND gate 7120. The output of AND gate 7120 is high, while the output of AND gate 7122 is low, so the output from NOR gate 7124 is low and the output from inverter 7126 is high, so that a read address signal is provided to sector SA7.
It will be understood that the other sector decoders include appropriately placed inverters (similar to inverter 7128) so that only one sector at a time is provided with a read or write address signal.
As will be seen with reference to FIGS. 1, 3 and 6, the pluralities of lines RA and WA, RB and WB, etc. extend and lie within the area of the memory banks between adjacent columns of sectors (for example, plurality of lines RA and plurality of lines WA lie between the column of sectors SA1-SA8 and the column of sectors SB1-SB8. These lines, included across the device between each pair of adjacent columns of sectors, take up substantial area of the finally produced die, causing the die to be large in area. As is well understood, reduction in die size for a given devices highly desirable. The problem is increased when the number of sectors in a column is increased. For example, has pointed out above, a column of 16 sectors would require four read address lines and four write address lines rather than the three read address lines and three write address lines as shown in the present example.
Therefore, what is needed is an approach wherein proper addressing up sectors in a memory array may be undertaken, meanwhile using an approach which reduces die size as compared to the prior art.
USPTO Backgrounds
USPTO Backgrounds