Computer processing architectures may include multiple different co-processing units that need to inter-communicate and exchange information with each other, and also with shared resources. Some of these computer architectures use cross-bar switches, mesh networks, Clos networks, etc., to interconnect the different co-processing units and shared resources together. Bottlenecks are created in these centralized interconnect architectures when different co-processing units try to communicate to the same destination over the cross-bar switch at the same time. These bottlenecks increase data processing latency and reduce the overall processing throughput of the processing system.
The present invention addresses this and other problems associated with the prior art.
USPTO Backgrounds
USPTO Backgrounds