1. Field of the Invention
Generally, the present disclosure relates to highly sophisticated semiconductor structures, and, in particular, to a protection layer for avoiding vertical voltage breakdown in highly advanced semiconductor technologies.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. This includes several connection lines between different components, such as transistors and diodes. The connection lines are organized on multiple vertical levels, also known as metal levels. On each metal level, a plurality of connection lines may be realized.
The proximity, both horizontal and vertical, of connection lines results in several issues. The signal in a given line may be influenced by neighboring lines due to the parasitic capacitance present between the lines. Even more dangerously, there is a risk of a voltage breakdown between neighboring lines.
The possibility of a voltage breakdown depends on the materials used, the voltages present and the dimensions and placement of the lines. In view of further device scaling, it is expected that the distance between neighboring metal lines will get smaller and smaller at each technology node, both in the vertical and horizontal direction. This increases the risk of a breakdown through the insulator between the metal lines.
Although this is at least partially compensated for by the reduction in operating voltages, there are applications in which voltages cannot be reduced enough to compensate for the reduced distance, for instance, automotive or high voltage applications such as those needed for the operation of fuses or similar devices.
Moreover, while the horizontal distance between metal lines can be varied for each metal line with respect to its neighboring lines, the same cannot be done in the vertical direction. So, for instance, if, on a metal level, only one metal line has a high voltage applied to it, horizontally neighboring metal lines can be spaced further apart to avoid any issues. However, the same cannot be done in the vertical direction since the increase in the vertical spacing would negatively reflect on all of the metal lines of the metal plane, which do not need the increased vertical spacing, and not only on the one carrying the high voltage.
In view of the situation described above, the present disclosure relates to semiconductor structures and manufacturing techniques thereof allowing the realization of at least one high voltage metal line on a metallization level of an integrated chip which avoids the risk of voltage breakdown.
USPTO Backgrounds
USPTO Backgrounds