1. Field of the Invention
The present invention relates to a memory device and fabricating method thereof. More specifically, the present invention relates to a split gate memory device and fabricating method thereof.
2. Description of the Related Art
A Non volatile-memories such as a ferro-electric random access memories (FRAMs), erasable and programmable read only memories (EPROMs), and electrically erasable and programmable read only memories (EEPROMs) have lately attracted considerable attention. EPROMs and EEPROMs accumulate electrons in a floating gate to memorize data by changes of a threshold voltage that occurs based on the presence of electrons.
EEPROMs may be characterized as either stack gate or split gate. The stack gate EEPROM suffers from the problem that data is over erased during erasing, whereas the split gate EEPROM may avoid this problem.
FIGS. 1A and 1B illustrate a cross-sectional view and a top plan view, respectively, of a split gate memory device according to the prior art. FIG. 1A illustrates a cross-sectional view taken along a line I–I′ of FIG. 1B.
Referring to FIGS. 1A and 1B, an active region is defined in a p type substrate 2 by a device isolation region 3. A common source region 20 is formed at the active region and a drain region 22 is formed apart from the common source region 20. A channel region 24 is formed between the drain region 22 and the source region 20. Floating gates 6 are formed on a portion of the channel region 24 and a portion of the source region 20. A gate insulating layer 4 is interposed between the floating gates 6 and the active region. A polyoxide layer 12 is formed on the floating gates 6 by a local oxidation of silicon (LOCOS) process. A tunnel insulating layer 14 is formed, which covers one sidewall of each of the floating gates 6 and a portion of the channel region 24. Control gates 16 are formed on a portion of the tunnel insulating layer 14, a portion of the channel region 24, and a portion of the drain region 22. A top plane view of the control gates 16 is schematically illustrated in FIG. 1B. The control gate 16 of FIG. 1A corresponds to a word line of FIG. 1B.
To program the memory device, a predetermined voltage is applied to the control gate 16 and the source region 20 and then channel-hot electrons (CHEs) are injected into the floating gate 6 from the substrate 2 through the gate insulating layer 4. The electrons define a level of either “on” or “off”.
The drain region 22 and the source region 20 are grounded during erasing. A predetermined voltage is applied to the control gate 16, so that electrons in the floating gate 6 move toward the control gate 16 (i.e., a word line) through the tunnel insulating layer 14 by Fowler-Nordheim tunneling (F-N tunneling). Arrows 26 indicate paths of electron movement during programming and erasing. During erasing, an electric field is concentrated at an acute section formed at a rim of the floating gate 6. The F-N tunneling occurs at the vicinity of the acute section. Thus, an effective erasing may be performed.
FIGS. 2A through 2F illustrate cross-sectional views for showing the steps of fabricating a split gate memory device according to the prior art.
Referring to FIG. 2A, a thermal oxidation process is applied to grow a gate insulating layer 4 on a substrate 2. A first polysilicon layer 6a and a nitride layer 8 are formed on the gate insulating layer 4. Subsequently, a photoresist pattern 10 is formed by a conventional photolithography process.
Referring to FIG. 2B, using the photoresist pattern 10 as an etching mask, the nitride layer 8 is selectively etched to form openings 11 exposing a surface of the first polysilicon layer 6a.
Referring to FIG. 2C, after the photoresist pattern 10 is removed, the exposed first polysilicon layer 6a is oxidized to form polyoxide layers 12.
Referring to FIG. 2D, the nitride layer 8 is removed, and then the first polysilicon layer 6a is selectively etched to form floating gates 6 using polyoxide layers 12 as etching masks.
Referring to FIG. 2E, a tunnel oxide layer 14 is formed on an entire surface of the substrate 2 and then a second polysilicon layer 16a is formed on the tunnel oxide layer 14.
Referring to FIG. 2F, the second polysilicon layer 16a is selectively etched using a photoresist pattern 18 formed by a photolithography process to form control gates 16. In FIG. 2F, bottom widths L1 and L2 of the control gates 16 are identical because no misalignment occurs during the photolithography process for forming the control gates 16. Ions are implanted into the substrate 2 to form a source region 20 and drain regions 22 after the photoresist pattern 18 is removed, thereby completing a memory device as illustrated in FIG. 1A.
Although a typical split gate memory device as described above may prevent the problem of over-erasing data, the typical split gate memory described above may incur other problems as described below.
First, an acute section of the tunnel oxide layer 14 may be attacked during etching of a floating gate and ion implantation.
Second, misalignment may occur during the photolithographic process for forming the control gate 16.
FIGS. 3A and 3B illustrate cross-sectional views for showing misalignment due to a photolithographic process for forming control gates 16 that commonly occurs in conventional split gate memory devices. When the misalignment occurs in the photolithographic process, a pair of transistors facing each other have different structures. Specifically, bottom widths L1 and L2 of the control gates 16 of the pair of transistors, respectively, are different from each other. In FIGS. 3A and 3B, L1 is shorter than L2.
When the control gates in a pair of transistors are formed having different bottom widths, cell current of one transistor differs from that of the other. Thus, dispersion of the cell becomes bad.
USPTO Backgrounds
USPTO Backgrounds