1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of integrated circuits. Functional verification generally refers to determining whether a design representing an integrated circuit performs a function it is designed for. The inventors have previously disclosed functional verification systems (U.S. Pat. Nos. 6,691,287, 6,629,297, 6,629,296, 6,625,786, 6,480,988, 6,470,480, and 6,138,266) in which a target design is partitioned into many combinational logic blocks connected by sequential elements. The state tables corresponding to the logic blocks are evaluated and stored in multiple random access storage devices (RASDs). Such an approach may have several disadvantages. For example, some logic blocks may exceed the convenient width of typical RASDs. Some target designs may contain functional blocks such as user specific memories, or simply require many more logic blocks and internal signals than can be practically accommodated. Accordingly, the embodiments of previous patents may not be suitable in some environments.
Thus it can be appreciated that what is needed is a system to scale a hardware simulation system for electronic circuit design which limits the number of circuit signal values shared throughout the system, limits the size of the data storage and media required for circuit signal values, tolerates the occasional early or late arrival of data without faulting, allows additional hardware resources to be incrementally added easily, and limits the media requirement for a host interface. Accordingly, what is needed is a method of operating a scalable architecture for more evaluation processors than can be practically interconnected in a single chip, board, or backplane.
USPTO Backgrounds
USPTO Backgrounds