1. Field of the Invention
This invention is concerned with a memory device, and more particularly to a memory device which reads and writes data with synchronization.
2. Description of Prior Art
One problem associated with conventional memory devices, is that its cycle time (e.g., the time period between data outputs) cannot be shortened.
In order to resolve this problem, synchronous memory devices have been constructed to carry data input and output operations synchronizing in accordance with a timing signal (e.g., a clock signal provided from outside the memory device) which is different from the timing signal for specifying an address signal. FIG. 2 shows an example of the typical structure of a conventional synchronous memory device with two levels of latches. In this device, address data are latched before a decoder, and specified data are selected by a selector from data read from a memory cell according to the decoded address data. The selected data are latched before an output buffer. Data input and output is controlled by controlling the aforementioned latches in conjunction with clock signals.
FIG. 3 and FIG. 8 illustrate the typical structure of a synchronous memory device with three levels of latches which is shown in Japanese patent laid-open print 64-21786. In this device, address data are latched before a decoder and the decoded address data are latched before a memory cell array. Specified data are selected by the selector among several data read from the memory cell, and the selected data are latched before the output buffer. By controlling these three levels of latches with the clock signal, inputting and outputting of data are controlled.
Generally, the cycle time of a synchronous memory device is limited by the maximum delay time between an input latch, in which the data of an address signal and a chip selection signal are stored, and an output latch for outputting data. Thus, the cycle time cannot be shortened because of this delay time. In the above-mentioned synchronous memory device with two levels of latches, the output latch is provided just before the output buffer. Thus, the delay time between the input latch and the output latch cannot be made smaller even if an address access time (i.e., a time period from inputting an address signal to outputting data) is shortened. As a result, there exists a problem that the cycle time cannot be made short.
In Japanese patent laid-open print 64-21786, the cycle time is shortened by reducing the delay time between the latches with an intermediate latch. The cycle time becomes shorter in this synchronous memory device with three latches, but this device is not without its problems. One problem, for example, is that the address access time becomes longer because an additional latch is inserted in the path from the address input to the data output. Another problem is that both the number of latches and the chip area is significantly large, since the latches are provided in the parts where a lot of signal lines such as word lines are formed.
USPTO Backgrounds
USPTO Backgrounds