Recent miniaturization and weight reduction of portable devices requires reduction in mounting area for semiconductor devices for use in the portable devices. In view of this, suggested are semiconductor devices of high density, which is achieved by packing a plurality of semiconductor chips are packed in one semiconductor device. Most popular kinds among such semiconductor devices are semiconductor devices in which respective semiconductor chips and a substrate are electrically connected by wire bonding method after the semiconductor chips are layered on the substrate. There are various combinations in chips to be layered because of variety in the chip sizes and methods for mounting the chips on the substrate.
In case of the semiconductor devices in which the semiconductor chips are layered as such, however, there is a case where part (protruded part) of a (upper) semiconductor chip layered on a semiconductor chip mounted on a (lower) circuit substrate is protruded out from the lower semiconductor chip. In this case, the upper semiconductor chip is vibrated by weight applied in wire bonding an electrode terminal provided in the protruded part of the upper semiconductor chip. This makes it difficult to perform the wire bonding stably. This phenomenon more severely affects a semiconductor device having a thinner upper semiconductor chip. If the upper semiconductor chip has too thin thickness, there is a possibility that the upper semiconductor chip may be broken.
In order to solve this problem, there disclosed a semiconductor device which is stabilized by having a spacer or filling a resin or paste in a gap under protruded part of an upper semiconductor chip (for example, Japanese Publication of Unexamined Patent Application “Tokukaihei No. 11-204720” (published on Jul. 30, 1999); corresponding to U.S. Pat. No. 6,100,594, No. 6,352,879, and No. 6,229,217 (Co-pending US Reissue applications)). Moreover, there disclosed a semiconductor device 110, as shown in FIG. 8 (for example, Japanese Publication of Unexamined Patent Application “Tokukai No. 2000-269407, ” (published on Sep. 29, 2000)). In the semiconductor device 110 disclosed in this publication, a first semiconductor chip 102 and a second semiconductor chip 103 are layered on a circuit substrate 101 via a bonding layer 104, the first semiconductor chip 102 and the second semiconductor chip 103 being electrically connected with the substrate 101 through a gold wire 106 wherein a supporter 108 is formed in a gap below protruded part of the second semiconductor chip 103, which is on the first semiconductor chip 102, the supporter 108 having the same thickness as the first semiconductor chip 102, which is located under the second semiconductor chip 103. The two semiconductor devices discussed above are characterized in that the supporter is formed in the gap under the protruded part of the upper semiconductor chip, the protruded part being protruded from an outer edge of the lower semiconductor chip, and the supporter having the same size as the protruded part and the same thickness as the lower semiconductor chip.
Moreover, there disclosed a semiconductor device in which a bonding agent used in bonding a lower semiconductor chip with a substrate by flip chip bonding is extruded out and the extruded bonding agent is used a supporter (for example, Japanese Publication of Unexamined Patent Application “Tokukai No. 2000-299431” (published on Oct. 24, 2000); corresponding to U.S. Pat. No. 6,353,263).
In the arts disclosed in Japanese Publication of Unexamined Patent Application “Tokukaihei No. 11-204720” and Japanese Publication of Unexamined Patent Application “Tokukai No. 2000-269407”, it is necessary to form, for example as shown in FIG. 8, the supporter 108 that has the same size as the protruded part of the second semiconductor chip, the protruded part being protruded from the outer edge of the first semiconductor chip 102, and to carry out positioning of the supporter 108 thus formed. This process is, however, very difficult and increases a number of members and steps, thereby leading to cost increase.
In the art disclosed in Japanese Publication of Unexamined Patent Application “Tokukai No. 2000-299431”, it is a problem that it is difficult to control an amount of the bonding agent to be extruded. That is, for example, in case the amount of the bonding agent to be extruded is insufficient, the protruded part of the upper semiconductor chip cannot be surely supported wholly. Further, this arrangement is applicable only in the case where the lower semiconductor chip is bonded by the flip chip bonding. Thus, this arrangement is poor in versatility.
USPTO Backgrounds
USPTO Backgrounds