The present invention relates to circuit design, and more particularly to a method and apparatus for reducing harmonic interference in highly integrated mixed-mode circuits.
Modern telecommunications equipment requires increasing levels of integration for cost-effective manufacturing and to accommodate the trend toward increasingly smaller packaging. In particular, digital and analog system components are increasingly often integrated on the same semiconductor die. For low-cost consumer wireless terminals, such as cellular phones, the trend towards integrating radio-frequency circuitry with digital signal processing elements gives rise to problems traditionally solved by segregating or otherwise isolating analog and digital sections.
Issues of electromagnetic compatibility (EMC) of digital and analog circuitry must be solved for highly-integrated systems to work reliably. In particular, harmonic components of the switching noise of digital circuits can exist with magnitudes comparable to the magnitude of the radio-frequency signals of interest to the analog circuit sections. Harmonic interference introduced by digital circuits can cause degraded receiver performance or spectrum mask violations of transmitted signals.
High levels of high-order harmonics may be caused by abrupt changes in switching currents. Using fundamental Fourier analysis it is apparent that the sharper the edge of signals such as those produced in digital switching circuits, the wider the frequency spectrum of harmonics produced thereby. The greater the magnitude of the switching current, the greater the energy of the associated harmonics, thus increasing the likelihood of in-band noise energy in adjacent RF circuits.
The most abrupt current change in a standard driver is when one device, e.g., the n-channel device, turns on as its gate-source voltage exceeds its threshold voltage. Simple transistor models assume that no current flows below threshold; in actual devices, a small current does flow. The difference between currents above and below threshold is nevertheless pronounced. Due to the speed at which such a device turns on, undesirable high order harmonics may be produced leading to noise coupling into RF sections and reduced EMC between analog and digital sections.
EMC between digital and analog circuitry has traditionally been addressed using a multitude of known methods. Standard methods for the design of low-power digital circuits attempt to reduce the average switching currents and thereby reduce the absolute levels of the harmonics produced thereby. Lowering supply voltages for digital circuits attempts to reduce edge rates, currents and charges of associated digital signals, further reducing the harmonic content of the switching noise produced thereby. Shielding or filtering methods attempt to reduce the level of substrate noise coupling from digital to analog circuit sections (see, for example, Makie-Fukuda et al. 95 K. Makie-Fukuda, S. Maeda, T. Tsukada & T. Matsuura, “Substrate noise reduction using active guard band filters in mixed-signal integrated circuits,” Symposium on VLSI Circuits, Kyoto, 8–10 June, pp. 33–34, 1995.).
Noise may be further exacerbated by small reference voltage differences between circuit components. Although these voltages may be reduced by carefully controlling reference voltage levels, they may nevertheless enter unbalanced signal paths through common-impedance coupling and further, may enter balanced paths through common-mode conversion. The periodic charge and discharge of parasitic capacitances may also cause small but significant currents to flow within substrates.
Radio-frequency circuits can be made more noise resilient through techniques such as dual-rail, balanced signal paths. (See, for example, A. Graeme, J, Applications of Operational Amplifiers—Third Generation Techniques, McGraw-Hill, 1973, pgs 53 to 57.) Such methods are increasingly expensive in terms of area, delay, or power dissipation when applied with greater rigor, and do not always provide a satisfactory solution to problems associated with noise reduction.
Some approaches exist for reducing harmonic interference which have provided varying results. For example, U.S. Pat. No. 5,514,992 to Tanaka, discloses a low-distortion cascode amplifier circuit. Distortion may be reduced in Tanaka by virtue of a higher transconductance of the cascode device in relation to the input device when a spectrally well-defined analog signal with few components is applied. However, Tanaka fails to address the spectral qualities of an output signal when a digital switching signal with a large number of ill-defined spectral components are applied to the circuitry.
A further approach to the reduction of undesirable harmonics is disclosed in Japanese Patent JP 63/074323 to Imamura. Imamura discloses a cascode current source with AC feedback wherein output conductance of the current source is frequency-dependent, e.g., some harmonic components of the output signal will be attenuated more than others providing stable current output. Imamura does not disclose, however, an approach for reducing harmonics on an output signal based on a digital switching input signal.
Yet another general approach to avoiding the deleterious effects of such abrupt switching currents is to continuously operate switching devices at a current level above a threshold, with the resulting logic styles resembling bipolar logic styles such as ECL, and the like. Such an approach, however, may be accompanied by negative side effects, including increased static power dissipation, as such devices are never fully turned off.
It would be appreciated in the art therefore for a method and apparatus for reducing the harmonic components associated with digital switching signals thus improving the EMC between analog and digital sections of mixed mode integrated circuitry without the negative side effects created by conventional solutions which attempt to address this problem.
USPTO Backgrounds
USPTO Backgrounds