1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a chip package which can protect conductive pads from damage during a cutting process and a redistribution stack layer and a fabrication method thereof.
2. Description of the Related Art
Wafer level packaging technology has been developed for packaging chips. After a wafer level package is completed, a cutting process is performed between chips to separate the chips from each other.
However, when using a cutter to form an opening between the chips in the cutting process, a lot of chipping is produced. The chippings damage and scratch bonding pads of the chip during the cutting process, such that the reliability of wire bonding of the chip package is reduced following subsequent processes and the electrical property of the conventional chip package is poor.
Thus, a chip package which can mitigate the above mentioned problems and prevent the conductive pads of chips from damage during a cutting process is desired.
USPTO Backgrounds
USPTO Backgrounds