1. Field of the Invention
The present invention relates generally to dynamic MOS memories and, in particular, to circuit structure for data retention in dynamic MOS memories having reduced propagation delay. 2. Description of the Prior Art
In data processing or computer systems the memory function is an essential part of the overall processing or computing operation. Data which is stored in a memory is in the form of some physically measurable quantity. Memories can be constructed from almost any structure which has the characteristic of retaining a physically measurable quantity. For example, if magnetic cores are used to fabricate a memory, then data is permanently retained as or by magnetic flux in each core, one flux direction representing a binary "zero" and the other flux direction representing a binary "one". For another example, in metal oxide semiconductor (MOS) memories, the data is in the form of a voltage (e.g.: a 1) or lack thereof (e.g.: a 0) which is temporarily retained on capacitance intrinsic to the MOS circuit; that is, because the circuit is constructed on a substrate or base from semiconductor materials which overlap each other (to form various circuit components such as transistors, gates, and other elements), there is inherent or intrinsic or parasitic capacitance between the various layers of semiconductor material forming these circuit elements. It is this very capacitance which is utilized in, and essential to the operation of, dynamic MOS memories. "Dynamic" is synonymous with "temporary" since capacitors continuously leak or discharge the voltages applied to them; these voltages must be replaced or refreshed periodically in order to retain the data represented by these voltages in the memory.
Examples of prior art MOS type memories are disclosed in U.S. Pat. Nos. 3,760,378 and 3,774,176; these memories can be arranged in arrays of individual memory cells. Prior art cells may contain three MOS field effect transistors (or MOSFET's) per cell, and these kinds of cells are usually referred to as three-device-per-bit cells. The array takes on an orthogonal character having rows (X direction) and columns (Y direction) that are mutually perpendicular or orthogonal. The rows are conventionally connected to X oriented precharge leads and the columns are usually connected to Y oriented control leads. The signals supplied on these leads are obtained indirectly, the leads themselves being usually integrally formed on the substrate.
The row or X oriented pre-charge leads (or busses) are signal leads which are logically operated upon to provide an output from the memory. The Y oriented control or column leads (or busses) are also logically operated upon and are normally used for providing READ and WRITE control signals to memory cells of the selected column, for reading information stored in a memory cell and for writing information onto the same cell. In addition, as noted with regard to MOS structure, the memory circuitry must provide for recirculation (refreshing) or restoration of data onto the temporary storage capacitance referred to above.
The conventional or prior art refresh method in three-device-per-bit MOS memories is to READ the data from a column of memory cells onto respective ROW BUSSES and then WRITE the inverted data back into the cells (by pulsing WRITE lead). Since a double inversion does not take place for each READ/WRITE cycle, then some columns end up with memory cells having inverted data and others do not. The polarity or status of the cell data must be kept track of by some means such as a status cell (counter) in each column. Each time the data in a column is read, its cell changes polarity. The status cell for a particular column must then be exclusive ORed with the data from the selected memory cell of that column to determine polarity. The primary disadvantage to this prior art approach is that the exclusive OR gate adds considerable propagation delay or increases READ access time.
The present invention is a improvement over the prior art memories since memories constructed in accordance with the principles of the present invention eliminate the need for an exclusive OR gate, which would otherwise be located in the path of data propagation and increase propagation delay time.
USPTO Backgrounds
USPTO Backgrounds