The manufacture of semiconductor chips essentially includes the three basic steps of wafer fabrication, die assembly, and die packaging. In the phase of wafer fabrication, a blank semiconductor wafer is made followed by integrating dice, having circuit components, on the wafer using well-known processing techniques of masking, diffusion and/or implantation, and wafer stepping. In the assembly phase, the die on the wafer are tested and marked for good and bad die, with the wafer then being sawed along scribe lines to provide individual die. Then, in the packaging phase, the good die are packaged, making them available for use as integrated circuit chips that may be placed on printed circuit boards to be interconnected with other packaged chips and thereby provide an overall electronic system.
The semiconductor industry is always seeking to reduce the cost of manufacture of its chips. Wafer fabrication and, in particular, the efficient use of the wafer "real estate" or silicon is a relatively high component of the cost factor for producing chips. The more die that can be produced on a wafer of a given size the less wasted silicon there will be, thereby making efficient utilization of the wafer and reducing chip component costs.
Typically, silicon may be wasted for several reasons. For example, common industry practice is to utilize a relatively large single array defined by a mask or mask set that may be stepped across the wafer using a wafer stepper, with scribe areas interposed between adjacent arrays. A given circuit composed of active and passive components may be implemented on the silicon within a single large array or across two or more adjacent arrays, depending on the number and size of the components. With such a relatively large array, if the circuit design is small, it may occupy only, for example, 20% of the array area, resulting in 80% of the die having wasted silicon. Alternatively, if a given circuit design requires just one more component than can be implemented in the single array, then the adjacent array must be utilized for this one component, resulting also in significant wasted silicon for the die comprised of the two adjacent arrays.
Inefficient use of silicon also results from the requirement for scribe areas. Common industry practice also is to have each array separated from one another by a scribe area. When more than one array is required for the fabrication of a die, the scribe areas between the adjacent die become wasted silicon.
Another problem which is related to the inefficient use of silicon is the fact that since disparate circuits occupying different sized areas are designed for semiconductor chips, many manufacturers have libraries of arrays varying from quite small to very large. Silicon efficiency would be improved by using the smallest array for a given circuit design. But this means that a range of arrays must be inventoried by the manufacturer, and circuit designers must work hard to eliminate that one extra component which could cause the circuit to extend onto an adjacent array.
U.S. Pat. No. 5,016,080 issued May 14, 1991, and entitled "Programmable Die Size Continuous Array", discloses a technique for more efficiently using the silicon of a wafer. As set forth in the '080 patent, among other features, a semiconductor wafer is fabricated in which either there are no scribe lines in either direction, i.e., horizontal and vertical, or preferably no scribe lines in at least one direction. Electrically isolated cells, which may be arranged in rows and columns, are provided throughout the wafer. Scribe lines may be arbitrarily placed according to an individual customized chip, with the isolated cells near the scribe lines being covered with metallization to form a bonding pad. By arranging the isolated cells in rows and columns, no matter where the scribe line is placed only one or two rows or columns of cells will be sawed. Since there are no scribe lines in at least one direction, the circuit designer can specify exactly the die size needed, which avoids wasting silicon as in the prior art.
One problem with the die size continuous array disclosed in the '080 patent is that it does not effectively provide for vertical stacking of the cells constituting the array. Also, the '080 patent does not make provision for extending the length of a given cell, and is not completely symmetrical in the peripheral cells forming an array.
USPTO Backgrounds
USPTO Backgrounds