1. Field of the Invention
The present invention relates generally to integrated circuit testing and, more specifically, the present invention relates to optical-based probing of integrated circuits.
2. Description of the Related Art
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip chip technology when packaging complex high speed integrated circuits. Flip chip technology is also known as control collapse chip connection (C4) packaging. In C4 packaging technology, the integrated circuit die is flipped upside down. This is opposite to how integrated circuits are packaged today using wire bond technology. By flipping the die upside down, ball bonds may be used to provide direct electrical connections from the bond pads directly to the pins of the C4 package.
FIG. 1A illustrates integrated circuit packaging 101 which utilizes wire bonds 103 instead of ball bonds to electrically connect integrated circuit connections in integrated circuit die 105 through metal interconnects 109 to the pins 107 of package substrate 111. With the trend towards high speed integrated circuits, the inductance generated in the wire bonds 103 of the typical integrated circuit packaging 101 becomes an increasingly significant problem.
FIG. 1B illustrates C4 packaging 151 with the integrated circuit die 155 flipped upside down. In comparison with the wire bonds 103 of FIG. 1A, the ball bonds 153 of C4 packaging 151 provide more direct connections between the integrated circuit die 155 and the pins 157 of package substrate 161 through metal interconnects 159. As a result, the inductance problems associated with typical integrated circuit packaging technologies that use wire bonds are minimized. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die, C4 technology allows connections to be placed anywhere on the integrated circuit die surface. This leads to a very low inductance power distribution to the integrated circuit which is another major advantage of C4.
A consequence of the integrated circuit die 155 being flipped upside down in C4 packaging 151 is that access to internal nodes of the integrated circuit die 155 for testing purposes has become a considerable challenge. In particular, during the silicon debug phase of a new product that is designed to be packaged into C4, it is often necessary to probe electrical signals from internal nodes of the chip, insitu, while the chip is packaged in its native C4 packaging environment. During the debug process it is often necessary to probe certain internal nodes in order to obtain important electrical data from the integrated circuit. Important data include measuring device parameters such as, but are not limited to, voltage levels, timing information, current levels and thermal information.
Present day debug process for wire bond technology is based on directly probing the metal interconnects on the chip front side with an electron beam (E-beam) or mechanical prober. Typical integrated circuit devices have multiple layers of metal interconnects and it is often difficult to access nodes that are buried deep in the chip. Usually other tools such as plasma etchers and focused ion beam systems must be used to mill away the dielectric and or metal above the node to expose nodes for probing.
With C4 packaging technology, however, this front side methodology is not feasible since the integrated circuit die is flipped upside down. As illustrated in FIG. 1B, access to the metal interconnects 159 for the purpose of conventional probing is obstructed by the package substrate 161. Instead, the P-N junctions forming the active and passive regions 163 of the integrated circuit are accessible through the back side of the silicon substrate of integrated circuit die 155.
FIG. 2 illustrates a prior art method used to probe active diffusion regions in integrated circuits. In the setup shown in FIG. 2, a device under test (DUT) 231 includes an active region 239 and non active region (metal) 241. A laser 221 is positioned to focus a laser beam 223 through a beam splitter 225, a birefringent beam splitter 227 and an objective lens 229 through the back side of the silicon of DUT 231 on the diffusion region 239 and metal 241. As shown in FIG. 2, birefringent beam splitter 227 separates the laser beam 223 into two separate laser beams, a probe laser beam 235 and reference laser beam 237. Both probe laser beam 235 and reference laser beam 237 are reflected from active region 239 and metal 241, respectively, back through objective lens 229 into birefringent beam splitter 227. Probe laser beam 235 and reference laser beam 237 are then recombined in birefringent beam splitter 227 and are guided into detector 233 through beam splitter 225.
By operating the DUT 231 while focusing probe laser beam 235 on active region 239 and reference laser beam 237 on metal 241, waveforms may be detected with detector 233 through the silicon substrate of DUT 231. Detection is possible due to the plasma-optical effect in which the refractive index of a region of free charge is different to a region with no charge. The application of a bias causes the free charge, and hence the refractive index, in the probed region to be modulated whereas the refractive index of the region under the reference beam is unaltered. This results in phase shift between probe beam 235 and reference beam 237.
Accordingly, by measuring the phase difference between the reflected reference beam 237 and probe laser beam 235, detector 233 is able to generate an output signal 241 that is proportional to the charge modulation caused by operation of the P-N junction region under the probe. This optical measurement can then be combined with conventional stroboscopic techniques to measure high frequency charge and hence voltage waveforms from the P-N junction region 239.
There are a number disadvantages with the prior art technique shown in FIG. 2. First, being a phase detection scheme, two beam beams are required (a reference beam 237 and a probe beam 235) to interfere with each other to generate the phase signal. These beams are created with birefringent beam splitter 227. Therefore, use of both probe laser beam 235 and reference laser beam 237 is limited in that they must be separated by a distance of x as shown in FIG. 2. Consequently, the layout of the diffusion regions 239 and metals 241 in DUT 231 must be such that a metal 241 is located at a distance x from diffusion region 239. It is appreciated that many modern integrated circuit layouts may not lend themselves to be probed with a setup as shown in FIG. 2 since the prior art technique shown requires a reflective surface 241 with no charge modulation ahead of it for the reference beam to be in close proximity (a distance x) to the probed region 239 undergoing charge modulation. It is difficult to meet these requirements in today's advanced technologies.
In addition, it is noted that the technique shown in FIG. 2 has only been applied to bipolar junction transistor technology and that no successful applications of the prior art technique shown in FIG. 2 have been used with CMOS technology. This is because the charge modulation in the depletion region of a reverse biased P-N junction (e.g. the drain of an MOS transistor) is much smaller than the charge modulation in the same junction when it is forward biased (e.g. the base region of a bipolar junction transistor). Furthermore, since the channels of MOS devices are lateral whereas the base-emitter junctions of bipolar devices are vertical, direct measurement of charge modulation in the channel of an MOS device is not possible due to prohibitively small laser spot size required which is far below that of the wavelength of light in silicon.
Another prior art optical technique for probing integrated circuits utilizes the electro-optic effect or Pockels effect. This electro-optic effect involves measuring the change in the optical index of refraction that occurs in an asymmetrical crystal when an electric field is applied. The refractive index of electro-optic materials changes when an electric field is applied. As a result, the polarization of an optical beam passing through the electro-optic material then changes according to the strength of the electric field or voltage impressed across the electro-optic material.
FIG. 3 illustrates an application of the electro-optic effect to an integrated circuit utilizing an asymmetrical crystal such as a gallium arsenide substrate 301. In the illustration shown in FIG. 3, a fringing electric field 307 exists between electrodes 305. A probe beam 303 enters from the back side of substrate 301, passes through the fringing electric field 307 and is reflected from an electrode 305. By measuring the changes in polarization of probe beam 303 and thus changes in the refraction index of the substrate 301, the electric field 307 can be measured. It is appreciated, however, that although this technique may be utilized in gallium arsenide based integrated circuits, electro-optic sampling in silicon is not possible because silicon is a symmetrical crystal and hence does not exhibit the electro-optic or Pockels effect.
Therefore, what is desired is a method and an apparatus for probing active regions in CMOS integrated circuits through the back side of silicon. Such a method should be able to probe active regions of a CMOS integrated circuit through the back side of silicon without the need for reference laser beam to be reflected off a metal near the diffusion region to be probed. In addition, this method should be compatible present day CMOS integrated circuit technology.
USPTO Backgrounds
USPTO Backgrounds