The present invention relates to a semiconductor memory device, in particular to a semiconductor memory device referred to as a phase-change type memory and a manufacturing method thereof.
Recently, a phase-change random access memory (PRAM) has been proposed as a semiconductor memory an alternative to DRAM. The PRAM uses a phase change material for a recording layer to record information.
The phase change material is able to freely transit between a crystal state and an amorphous state according to heat conditions. The phase change material has an electric resistance value in the crystal state that is significantly different from that in the amorphous state. Utilizing such properties of the phase change material, the PRAM stores data by changing the phase state of the phase change material according to the data to be stored.
Data writing to the PRAM is performed by supplying electric current according to the data to be written to the phase change material, and thereby heating the phase change material to change its phase state. Data reading from the PRAM is performed by supplying current for data reading to the phase change material and measuring the resistance value thereof. The current for data reading should be low enough in comparison with that for data writing to prevent phase change of the phase change material.
The phase change material will not change its phase state unless high heat is applied thereto. Therefore, the data written in the PRAM will not be lost even if power supply is cut off. This means that the PRAM is a non-volatile memory.
When writing data, it is imperative to efficiently heat the phase change material with electric current. For this purpose, it is effective to restrict the path through which current flows to thereby concentrate the current flow to the phase change material. A description will be made of a conventional PRAM cell structure in which the current path is restricted in such a manner, with reference to FIG. 1.
A pair of memory cells shown in FIG. 1 has a phase-change layer 11 serving as a recording layer, and an upper electrode 12 and lower electrodes 13 arranged, respectively, on the top and the bottom of the phase-change layer 11 to supply current through and heat the phase-change layer 11. The phase-change layer 11 is formed of a phase change material such as chalcogenide (GST: germanium antimony tellurium).
The memory cells further has transistors (not shown) formed in a substrate 14 in a diffused manner to control the supply of current to the lower electrodes 13, gate electrodes 15 connected to gates of the transistors, series of contacts 16a and 16b connecting drains of the transistors to the lower electrodes 13, a ground wiring 17, and a series of contacts 18a and 18b connecting a common source of the transistors to the ground wiring 17.
Each of the lower electrodes 13 is formed in a cup shape (the upper edge of which has a ring shape), such that the lower electrode 13 is in contact with a phase-change layer 11 only at the upper edge thereof. This allows the current path to concentrate to the phase-change layer 11.
An oxide film 19 is formed between the phase-change layer 11 and a part of the lower electrode 13 to restrict the region where the lower electrode 13 is in contact with the phase-change layer 11 to another part of the upper edge thereof (a part in the circumferential direction thereof)(by employing a CFH (ConFined Hole) method), so that the current path is more concentrated to the phase-change layer 11 (see, for example, U.S. Patent Application Publication No. 2004/0012009; E. Varesi, A. Modelli, P. Besana, T. Marangon, F. Pellizzer, A. Pirovano, R. Bez, “Advances in Phase Change Memory Technology”, EPCOS 2004 Conf. Proceedings; and S. Hudgens, B. Johnson, “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology”, MRS Bulletin, November 2004).
In the conventional phase-change type semiconductor memory device, the contact region between the phase-change layer and the lower electrode is restricted by a method in which an oxide film is formed on a plane surface from which the upper edge of the lower electrode is exposed, and the oxide film is patterned to form a hole or groove for exposing a part of the upper edge of the lower electrode. The hole or groove formed in the oxide film is then filled with a phase change material to establish contact between the lower electrode and the phase-change layer.
When formed of chalcogenide, for example, the phase-change layer is formed by a sputtering method or the like. This may induce a problem that the film thickness becomes too thin in a step portion of the patterned oxide film, or a gap is formed between the phase-change layer and the oxide film or the lower electrode. Formation of a gap may lead to peel-off of the phase-change layer.
When employing the CFH (ConFined Hole) method, the phase-change layer is formed after formation of the oxide film. Therefore, there is nothing to restrict heat transfer above the phase-change layer, and heat is liable to dissipate upwards. This makes it necessary to require more flow of current in order to cause phase change of the phase-change layer.
Further, in the conventional phase-change type semiconductor memory device, the lower electrode for supplying current to the phase-change layer for heating the same has a cup shape. This means that the lower electrode has a large surface area, and the heat from the phase-change layer is liable to be dissipated due to heat discharge from the lower electrode.
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