1. Field of the Invention
The invention relates generally to a liquid crystal display, and more particularly, to a liquid crystal display for reducing image mura.
2. Description of the Related Art
A liquid crystal display (LCD) is a high-resolution display with features of being thin, lightweight, and having low-voltage and low-power consumption. Sizes of LCDs, as broadly used, range from small-sized panels for mobile phones and digital cameras to over 40-inch large-sized panels for TVs.
An LCD operates by applying a voltage across liquid crystal material, sandwiched between two (i.e., a pair of) substrates with at least one transparent substrate, which changes the direction of liquid crystal orientation to control flux of light. Transparent electrical conduction films are formed on each pixel sandwiched between the two substrates for constructing a liquid crystal panel (i.e., between a pixel electrode arranged on a thin film transistor side substrate module and a counter electrode arranged on a counter electrode side substrate module). Therethrough, voltage is selectively applied to determine whether light of a specific pixel is transmitted or not.
FIG. 1 illustrates an equivalent circuit of a pixel of a conventional liquid crystal panel. As shown in FIG. 1, a thin film transistor (TFT) 13, as a switching component, and a storage capacitor 14 are formed on the intersection of a matrix respectively arranged by a scan line 11 and a data line 12 along X-axis and Y-axis on the substrate, wherein the storage capacitor 14 is formed to allow charging of an initial signal after inputting the signal to a pixel and before inputting a following signal.
Meanwhile, the drain electrode of the TFT 13 is coupled to one of the pixel electrodes, the source electrode is coupled to the data line 12, and the gate electrode is connect to the scan line 11. Also, an electrode (storage capacitor electrode) of a storage capacitor 14 installed on the same substrate with the TFT 13 is coupled to the drain electrode of the TFT 13. In addition, another electrode of the pixel is a common electrode connected to a common voltage VCOM formed on an opposing substrate.
As shown in FIG. 1, Clc illustrates an equivalent capacitor of a liquid crystal cell, Cgd illustrates a parasitic capacitor across the drain and the gate of the TFT 13, and Cs illustrates a storage capacitor. Cs is connected in parallel to the liquid crystal capacitor Clc formed by liquid crystal material, and is utilized to be the load of the TFT 13. A terminal of Cs is connected to the drain/source of the TFT 13 and the other terminal of Cs is connected to the scan line or the voltage VCOM. The other electrode of the storage capacitor 14 shown in FIG. 1 is coupled to a part of the display electrode (an auxiliary voltage VS as shown in FIG. 1.
If the scan line is at a high level (VGH), the data voltage is stored in the pixel capacitor Clc according to the voltage provided by the data line. When the level of the scanning signal transitions from a high level (VGH) to a low level (VGL), the drain voltage of the TFT 13 generates a level shift, which is called feed-through voltage, wherein the level shift (ΔVd) is represented by the following formula:ΔVd=Cgd/(Cgd+Clc+Cs)×(VGH−VGL)∘
FIG. 2 illustrates a level shift of a drain voltage Vd of a TFT according a conventional driving method. As shown in FIG. 2, in the same scan line (the jth scan line), a gate voltage (Vg) and a drain voltage (Vd) of the TFT is corresponding to the pixels on the first and the nth location near the input of the scanning signal.
When the voltage level of the scanning signal drops rapidly, the falling inclination edge on each scan line of the TFT is dependent on where it is located on the scan line due to the delay effect. The TFT turns off after the scan line voltage is below a threshold voltage, thereby increasing the level shift (ΔVd (1, j) as shown in FIG. 2 near the input on the scan line, and decreasing the level shift (ΔVd (n, j) as shown in FIG. 2 near the end on the scan line. That is, the level shift ΔVd of the drain voltage of the TFT on the same scan line becomes inconsistent and causes image mura such as flickers and residues, thus lowering display image quality for large liquid crystal panels.
As a result, various researches, e.g., Patent Reference 1 (Japan Pat. Appl. Kokai Publication No. 6-110025) and Patent Reference 2 (Japan Pat. Appl. Kokoku Publication No. 3406508), were directed to a method of changing the falling edge of the scanning signal as an inclination (ramp waveform) to reduce the aforementioned image mura.
For controlling the falling edge of the scanning signal as an inclination, the conventional and broadly-used timing integrated circuits and a scan line driver need to be modified, and thus it raises a problem of developing new timing integrated circuits and scan line drivers.
USPTO Backgrounds
USPTO Backgrounds