Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted; nonvolatile memory devices, however, retain their stored data even when their power supplies are interrupted. There are various types of nonvolatile memories including e.g., electrically programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is a flash EEPROM device (also referred to as “flash memory”). Nonvolatile memory devices e.g., flash memory, have become widely used for storage applications.
A conventional flash memory device includes a plurality of memory cells, each cell having a floating gate covered with an insulating layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the cell substrate. This insulating layer is an oxide layer and is often referred to as the tunnel oxide. The substrate contains doped source and drain regions, with a channel region disposed between the source and drain regions.
In one conventional process for forming flash memory, memory cells and low voltage logic transistors (e.g., MOSFETs) share the same gate oxide as memory cell transistors in order to simplify the process and reduce fabrication cost. The thickness of this gate oxide typically is between 70-90 Å to maintain proper data retention for the memory cell transistors. However, this gate oxide thickness limits the performance of the logic transistors which ideally should have a thinner gate oxide for high performance. A flash memory also typically has high voltage transistors which require a thicker gate oxide than that used for the memory cells and logic transistors. A thinner gate oxide for the logic transistors would require a triple oxide thickness process that includes a 30-50 Å thick gate oxide for logic transistors, a 70-90 Å thick gate oxide as tunnel oxide for memory cells, and a 350-400 Å thick gate oxide for high voltage transistors. Fabricating gate oxides having there different thicknesses not only increases the complexity of the process flow, but also introduces tunnel oxide quality concerns because, based on the existing conventional multiple oxide processes, one has to grow a tunnel oxide in several oxidation steps with many patterning and resist strip steps in between.
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