The present invention relates to nonvolatile semiconductor memories such as an EEPROM (electrically erasable and programmable ROM) that stores information utilizing residual polarization in a ferroelectric material. Further, the invention relates to a device having the MFSFET (metal ferroelectric semiconductor FET) structure that employs a ferroelectric film as a gate insulating film.
Referring to FIG. 1, a structure of a conventional MFSFET device is described.
In FIG. 1, reference numeral 1 represents, for instance, a p-type silicon substrate, in which an n.sup.+ -type drain diffusion layer 2 and an n.sup.+ -type source diffusion layer 3 are formed. A ferroelectric film 4 made of, for instance, lead zirconate titanate (PZT) and a gate electrode 5 are formed on the substrate 1 between the drain and source diffusion layers 2 and 3. Reference numeral 6 represents an interlayer insulating film 6, and numeral 7 represents metal leads connected to the drain and source diffusion layers 2 and 3, respectively.
The ferroelectric film 4 of the above MFSFET device exhibits a hysteresis characteristic as shown in FIG. 2. In FIG. 2, the abscissa represents an electric field E acting on the ferroelectric film 4 and the ordinate represents polarization charge P of the ferroelectric film 4. Assume here a positive voltage V.sub.max which will cause an electric field acting on the ferroelectric film 4 that is equal to or stronger than E.sub.sat. If the voltage V.sub.MAX is applied to the gate electrode 5, the ferroelectric film 4 is polarized to a state indicated by symbol A in FIG. 2, and a channel is formed between the source diffusion layer 3 and the drain diffusion layer 2 of the device of FIG. 1. Even if the gate voltage is thereafter reduced to 0 V, the polarization charge P is only slightly reduced to a state B, i.e., a polarization (spontaneous polarization) of a considerable amount remains, so that the channel is maintained.
Conversely, if a negative voltage -V.sub.MAX is applied to the gate electrode 5 (or if a positive voltage +V.sub.MAX is applied to the substrate 1), the ferroelectric film 4 is polarized to a state C. Even if the gate voltage is reduced to 0 V, the polarization charge is only slightly reduced to a state D, i.e., a negative polarization (spontaneous polarization) of a considerable amount remains. A channel is not formed between the source diffusion layer 3 and the drain diffusion layer 2 during this process.
A memory device capable of nonvolatile storage of information can be constituted by associating the above spontaneous polarization polarities of the ferroelectric film 4 with data "0" and "1," respectively.
Although the MFSFET has the above characteristics, there have not been announced to date any practically usable devices of this kind. This is due to the following reasons: (1) a silicon substrate is damaged when a ferroelectric material is deposited thereon by sputtering; (2) when the ferroelectric material deposited on the silicon substrate is subjected to a heat treatment, it diffuses into the substrate and deteriorate the FET characteristics; and (3) where the ferroelectric material is directly deposited on the silicon substrate, a desired hysteresis characteristic is hardly obtained due to incomplete crystal orientation of the ferroelectric film.
In order to avoid the problems (1) and (2), a MFSFET device has been proposed in which an insulating buffer layer made of, e.g., SiO.sub.2 is interposed between the ferroelectric film and the silicon substrate (Technical Study Reports of the Institute of Electronics and Communication Engineers, Vol. 78, No. 179, pp. 1-8, 1978).
However, in the above device employing the insulating buffer layer, the gate structure constitutes a capacitor including a multilayer of the ferroelectric film and the buffer layer. Since a large part of the voltage applied to the gate electrode 5 is allocated to the buffer layer, a divided voltage across the ferroelectric film is reduced, which will cause an another problem that the operating voltage should be increased as much. Further, even with the above buffer layer, it is difficult to improve the crystal orientation of the ferroelectric film.
FIGS. 3 and 4 shows conventional examples of nonvolatile semiconductor memories that perform information storage utilizing residual polarization in a ferroelectric material.
In the nonvolatile semiconductor memory shown in FIG. 3, one memory cell consists of one memory transistor MTr and two selection transistors STr1, STr2. The memory transistor MTr is a field-effect transistor having a gate structure of a metal film and a ferroelectric film on a semiconductor layer.
Data write, erase and read operations on a memory cell C1 are briefly described below.
To effect data writing, word lines WL1.sub.1, WL1.sub.2 are grounded and a word line WL1.sub.3 is supplied with a positive voltage (e.g., 5 V). If a positive high voltage (e.g., 10 V) is applied to a bit line BL1 in this state, it will acts on the ferroelectric film of the memory transistor MTr via the selection transistor STr2 of the memory cell C1. That is, an electric field acts on the ferroelectric film to polarize it, so that the memory transistor MTr is rendered non-conductive if it is of the n-channel type. It is assumed that this state is a written state of data "1."
To erase the written data, the word lines WL1.sub.1, WL1.sub.3 and the bit line BL1 are grounded, and the word line WL1.sub.2 is supplied with a positive high voltage. As a result, an electric field of a direction opposite to that in the write operation acts on the ferroelectric film of the memory transistor MTr of the memory cell C1, and the ferroelectric film is polarized in the opposite direction. The memory transistor Mtr is rendered conductive if it is of the n-channel type (i.e., data "0" is retained).
To effect data reading, the word lines WL1.sub.1, WL1.sub.3 are supplied with a positive voltage and the word line WL1.sub.2 is grounded. In this state, a sense amplifier SA that is connected to the bit line BL1 detects whether there exists a current. Data "1" is detected if no current flows, and data "0" is detected if a current flows.
In the nonvolatile semiconductor memory shown in FIG. 4, one memory cell consists of one selection transistor STr and one ferroelectric capacitor FC.
Data writing to a memory cell C1 is effected by rendering the ferroelectric capacitor FC in a certain polarization state by applying a positive voltage to a word line WL1 and a positive high voltage to a bit line BL1.
Data erasing is effected by polarizing the ferroelectric capacitor to the opposite polarity by applying a positive voltage to the word line WL1 and a negative high voltage to the bit line BL1.
In data reading, a positive voltage is applied to each of the word line WL1 and the bit line BL1. Whether the written data is "0" or "1" is judged by the amplitude of a current detected by a sense amplifier SA connected to the bit line BL1.
However, the conventional memories having the above configurations are associated with the following problems.
The nonvolatile semiconductor memory of FIG. 3, in which one memory cell consists of one memory transistor and two selection transistors, inevitably has a large cell area and is not suitable for higher integration.
The configuration of the nonvolatile semiconductor memory of FIG. 4 allows higher integration to a certain degree. However, during the data read operation, the polarization state in the ferroelectric capacitor is changed by a current flowing into the ferroelectric capacitor (what is called "destructive reading"). As a result, data refreshing is required and, therefore, more complex peripheral circuits are needed.
USPTO Backgrounds
USPTO Backgrounds