1. Field of the Invention
The present invention relates to a method of fabricating a memory cell, and more particularly, to a method of fabricating a flash memory cell.
2. Background of the Related Art
A flash memory cell, which has a laminated structure of a floating gate and a control gate, is a nonvolatile memory device. The flash memory cell is programmed when hot electrons are injected into the floating gate, and is erased when the electrons of the floating gate are tunneled to a source region or a substrate with a Fowler-Nordheim mechanism. The flash memory cell has a high erase rate because the memory array cells can be concurrently erased.
FIG. 1 is a layout of the flash memory cell of the related art. The flash memory cell includes a buried region 13, a field insulating layer 15, a floating gate 19 and a control gate 23. The buried region 13, which is used as data lines, is formed in a stripe shape in a first direction, and the field insulating layer 15 for defining an active region of the device is formed in a stripe shape in a second direction, which crosses the first direction. The control gate 23 is formed in the second direction on the active region between the field insulating layers 15. The floating gate 19 is overlapped with the control gate 23. Furthermore, the edged portions on both sides of the floating gate 19 overlap with the buried region 13 adjacent thereto.
FIGS. 2A-2D are flow diagrams illustrating the process for fabricating a flash memory cell in accordance with the related art, which show sectional views taken along the line II-II' of FIG. 1.
Referring to FIG. 2A, a mask layer 12 is formed by depositing a silicon oxide or a silicon nitride on a P-type substrate 11 using chemical vapor deposition (CVD). The mask layer 12 is patterned with photolithography to expose the substrate 11 in a stripe shape in the first direction. Then, an N-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into the exposed portion of the substrate 11 to form the buried region 13.
Referring to FIG. 2B, the mask layer 12 is removed. Then, the field insulating region 15 for defining an active region of device is formed on the field region of the substrate 11 using Local Oxidation of Silicon (LOCOS), and it is formed in a stripe shape in the second direction crossing the buried region 13.
As shown in FIG. 2C, a thermal oxidation is performed on the exposed portion of the substrate 11 to form the gate oxide layer 17. After a polysilicon doped with impurity is deposited on the field insulating layer 15 and the gate oxide layer 17 with CVD, the deposited polysilicon is patterned in a stripe shape in the first direction with photolithography to form the floating gate 19. The edge on both sides of the floating gate 19 overlaps the buried region 13 adjacent to the active region.
As illustrated in FIG. 2D, an interlevel insulating layer 21 is formed by carrying out an oxidation on the surface of the floating gate 19. Then, a polysilicon doped with impurity and a silicon oxide are sequentially deposited on the field and interlevel insulating layers 15 and 21 with CVD. The polysilicon and the silicon oxide are patterned with photolithography so as to remain in a stripe shape in the second direction only in the active region of device, and thus, the control gate 23 and a cap oxide layer 25 are formed. In the meantime, the portion formed on the field insulating layer 15 of the by floating gate 19 is removed.
The flash memory cell as fabricated in the above method, is programmed when, with a buried region 13, used as a source, coupled to ground, a voltage Vg applied to the control gate 23 is higher than the voltage Vd (i.e., Vg&gt;Vd) applied to another buried region 13 used as a drain region. Thus, hot electrons generated in the channel are injected into the floating gate 19. To erase programmed data in the flash memory cell, the voltage Vs is applied to the buried region used as the source with the control gate 23 grounded, or with negative voltage applied. Thus, the electrons in the floating gate 19 are tunneled to the buried region 13 used as the source region, or the substrate 11.
However, the above-described flash memory cell of the related art method has various disadvantages because the fabrication method is too complex in that the field insulating layer and the floating gate are formed through separate steps. Further, the floating gate is formed with two etching steps. Moreover, it is difficult to enhance the integration of a device using such flash memory cells because of the required space to align the floating gate with the field insulating layer during the step of forming the floating gate.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
USPTO Backgrounds
USPTO Backgrounds