This invention relates to a computer aided design system for designing a logic circuit including a plurality of functional blocks connected through path nets to one another. More particularly, this invention relates to a designing system for designing a final routing layout in response to logic connection information indicative of a connection between the functional blocks under a circuit constraint or limitation imposed on the path nets.
On designing a logic circuit comprising a plurality of functional blocks each of which may be formed by a gate, a flip-flop, or the like, it is preferable to connect the functional blocks to one another in accordance with logic connection information through final routing paths which form the final routing layout. The logic connection information is representative of the path nets between the functional blocks. Thus, the logic circuit is logically designed which is composed of the functional blocks and the final routing layout. The logic circuit may be actually formed or fabricated by a large-scale integrated circuit, a printed-circuit board, or the like after it is designed in the above-mentioned manner.
In a conventional computer aided design system, an initial routing layout which is empirically determined is first given in the form of the logic connection information to the system. The initial routing layout is assumed to be given as optimum courses of the path nets between the functional blocks. Thereafter, the initial routing layout is successively renewed under the circuit constraint until the final routing layout is obtained. The circuit constraint may be specified by a predetermined limiting value which is indicative of a maximum length uniformly determined at each of the path nets. The delay time of each of the path nets is long, as the limiting value is large.
However, consideration is not made about the delay time on renewing the initial routing layout into the final routing layout in the conventional computer aided design system. When the final routing layout is obtained, the actual delay time is often more than an allowed delay time in one path net because the limiting value is uniformly determined at each of the path nets. Any adverse influence might not occur due to the delay time when the limiting value selected is so small. It is difficult to renew the initial routing layout into the final routing layout as desired because the limiting value is small. To the contrary, when the limiting value is selected large, renewal of the initial routing layout can be achieved to obtain the final routing layout as desired. It is difficult to neglect influences of the delay times. The delay times and the limiting value have an antinomic relationship.
USPTO Backgrounds
USPTO Backgrounds