The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
It is generally understood that circuit devices, such as NMOS or PMOS transistors degrade with use over time. As an example of degradation, leakage may increase and/or mobility may decrease as the device is used over time. This problem is multiplied as device size is further reduced. To determine a useful life for the device, designers often use a device model simulator, such as the well known SPICE computer simulation system to input varying parameters for the device. After running the simulation of the proposed device, the designers may use the outputted information from the simulation and modify parameters to improve upon the device where needed.
The traditional simulation systems assume the degradation indexes can be mapped as an age factor. A circuit device's age is generally a linear function of stress time. The simulation age of the device (ΔAge) increases during operation of the circuit. Age duration is traditionally calculated from a direct integral of the age. For example, traditional age calculations may be as follows:
            D      =                        (          Age          )                n              ,          Age      =              Age        ⁡                  (          t          )                      ,          n      =      const                  Δ      ⁢                          ⁢      Age        =                  ∫        0        tran_time            ⁢                        Age          ⁡                      (            t            )                          ⁢                  ⅆ          t                                Age      new        =                  Age        old            +              Δ        ⁢                                  ⁢                  Age          ·                      dagetime            tran_time                                          D      new        =                  (                  Age          new                )            n      Where D is the degradation of the device and where this traditional system assumes that D vs. time has a constant slope (n). Thus, the system extrapolates dt(tran_time) to T to predict a stress effect for the device. Given that the age is a linear function of stress time, the estimated age after a given long stress time may be obtained by direct linear extrapolation. In other words, contemporary simulation systems use an age constant (constant n) and extrapolate a value to predict a stress effect on the device being simulated. As such, n is assumed as being constant and independent of the bias condition of the device. Thus, this type of system incorrectly simulates bias dependant conditions of aging for circuit devices.
Thus, it is desirable to have a circuit device reliability simulation system addressing one or more of the issues discussed above by having an improved system to predict device reliability.
USPTO Backgrounds
USPTO Backgrounds