According to the trend of recent years for a high performance and a high signal-processing rate, there has been enhanced a demand for making the size of the wiring substrate smaller and the pitch of the wiring pattern layers (or the built-up wiring layer) finer.
For example, one wiring pattern layer is generally restricted by a practical limit of the section of a length×a width of 25 μm×20 μm (as referred to JP-A-2003-133725 (page 6), for example). However, it has been demanded that the section is made to have a length and a width of 20 μm or less×20 μm or less.
In order to satisfy the demand, it is necessary to enhance the shaping and sizing precisions of a plated resist for forming the wiring-pattern layer.
Another problem is that the plated resists are liable to be deformed by the penetration of a plating liquid when they are electrolytically plated with copper to form the wiring pattern layers.
Heretofore, however, there has been any disclosure on the technique, by which the plated resists can be reliably formed to achieve the wiring pattern layers of the aforementioned fine pitch.
USPTO Backgrounds
USPTO Backgrounds