1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory having an electric programmable/erasable function.
2. Description of the Related Art
A memory referred to as an xe2x80x9celectric one-time erasable NOR type flash memoryxe2x80x9d has been developed in the past as a nonvolatile semiconductor memory as described, for example, in JP-A-62-27687 (laid open on Dec. 1, 1987) and JP-A-3-219496 (laid open on Sep. 26, 1991).
FIG. 7 of the accompanying drawings illustrates a schematic sectional structure of the NOR type flash memory cell according to the prior art and its operation. The NOR type flash memory cell according to the prior art comprises a floating gate type field effect transistor structure wherein a gate oxide film 2, a floating gate 3, an intermediate insulating film 4 and a control gate 5 are formed on a p type silicon substrate 1, an n type impurity layer 22 is formed on a source terminal side and an n type impurity layer 23 and a p type impurity layer 24 are formed on a drain terminal side.
The NOR type flash memory according to the prior art is formed by arranging the memory cells described above in matrix, connecting the drain terminal of each memory cell to a data line, connecting each source terminal to a common source line, and connecting each control gate to a word line.
Memory cell data is erased by applying a negative voltage to the control gate 5 and a positive voltage to the source impurity layer 22. At this time, a high electric field is applied to the gate oxide film 2 and a tunnelling mechanism of electrons takes place, so that electrons accumulated in the floating gate 3 are pulled out to the source impurity layer 22. A threshold voltage of the memory cell decreases due to this erasing operation.
Programming of data into the memory cell is effected by applying a positive voltage to the drain impurity layer 23 and to the control gate 5. At this time, hot electrons generated in the vicinity of the surface of a drain junction are injected into the floating gate 3. A threshold voltage of the memory cell increases due to this programming.
The NOR type flash memory according to the prior art described above have the function of collectively erasing at one time a chip as a whole or a certain groups of memory cells, and one transistor can constitute one memory cell. Further, when a circuit scheme wherein a source wiring is used in common for all bits, is employed, the memory chip area can be reduced.
In comparison with the NOR type flash memory cell according to the prior art described above, a nonvolatile semiconductor memory is known which utilizes a Fowler-Nordheim (F-N) tunneling mechanism.
An ACEE (Advanced Contactless EEPROM) described in IFEE Journal of Solid-State Circuits, Vol 4, No 4, April. 1991, pp 484-491, is one of the examples of the non-volatile semiconductor memory described above. Transistors used for this ACEE are those transistors which have a thin oxide film region for the F-N tunneling at only an overlapped portion between the floating gate and the source, and the thickness of the oxide film of the transistor region is set to be greater than the thickness of the oxide film in the tunnel region. The memory cells are arranged in matrix, the drain terminal of each memory cell is connected to a data line comprising an impurity layer, and the source terminal is connected to a source line comprising mutually different impurity layers. Further, the impurity layer data line and the impurity layer source lines connected to a plurality of memory cells are connected to a data line and to a common source line through a MOS transistor (select transistor), respectively.
The device operations are as follows. In the erasing operation, a negative voltage (xe2x88x9211 V) is applied to a selected control gate to turn ON a source side select transistor and a positive voltage (5 V) is applied to the common source terminal, so that electrons are released from the floating gate through the tunnel region on the source side of the selected memory cell In the programming operation, the drain side select transistor is turned ON with the source side select transistor being kept OFF, a positive voltage (18 V) is applied to the selected control gate, a positive voltage (7 V) is applied to the non-selected control gate to such an extent that programming is not made, 0 V is applied to the data line so as to set the voltage on the source side to 0 V through the non-selected memory cells which commonly share the data line but to which programming is not made, and the electrons are thus injected into the floating gate from the source side tunnel region of the selected memory cell by utilizing the F-N tunneling mechanism. Here, a 7 V voltage is applied to the data line for those memory cells which share in common the control gate voltage with the memory cell to be subjected to programming but into which programming is not made, and the electric field applied to the source side tunnel region is relaxed.
Since the ACEE utilizes the F-N tunneling mechanism for the programming/erasing operations, a consumed current per bit is small and hence, a voltage booster having small current drivability can be used inside the chip. Accordingly, a single 5 V supply can be used.
A nonvolatile semiconductor memory utilizing the F-N tunneling mechanism is also described in JP-A-4-14871 (laid open on Jan. 20, 1992). This nonvolatile semiconductor memory uses a floating gate type field effect transistor structure for memory cells, and has the structure wherein the drains of a predetermined number of memory cells are connected by a sub bit line, this sub bit line is connected to a main bit line through a MOS transistor, and the source terminals are connected in common to the source line.
To erase memory cell data, a positive voltage Vp (e.g. 22 V) is applied to the control gate, and the source terminals and the drain terminals are first grounded so as to accumulate the electrons in the floating gate. In the programming operation, the control gate of a selected memory cell is grounded and the positive voltage Vp is applied to the drain impurity layer. To inhibit programming, a voltage Vp/2 is applied to the drain terminals. Accordingly, the electrons are released from the floating gate to the drain impurity layer in the select memory cell due to the tunneling mechanism.
The non-volatile semiconductor memory using the F-N tunneling mechanism effects the programming/erasing operations of data by the use of a very small current, that is, the tunnel current. Accordingly, this semiconductor memory is effective for accomplishing lower power consumption.
An EEPROM described in IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, October 1982, pp. 821-827, is another example of the nonvolatile semiconductor memory using the F-N tunneling mechanism. In this EEPROM, the electrons are injected from the drain to the floating gate and attain a low threshold voltage in the programming operation, and the electrons are released from the floating gate to the whole channel immediately therebelow and attain a high threshold value. The cell of this EEPROM comprises a floating gate type F-N tunnel transistor and a selector transistor connected to the drain side of the former. The memory cells are arranged in matrix, the drain terminal of the select transistor of the memory cell is connected to the data line through a switch transistor outside the memory cell, and the source terminal of the floating gate type F-N tunnel transistor of the memory cell is directly connected to the common source line.
However, in the NOR type flash memory cell shown in FIG. 7, the consumed current at the time of programming is great, although the memory cell structure is miniature, and a single power supply operation is difficult. In other words, since the data programming operation to the floating gate relies on the hot carrier injection system, a current of about 500 xcexcA per bit must be supplied as a drain current, for a drain current of higher than 3.3 V, for example. Further, in the case of a single 3 V supply, an operation at a minimum power source voltage of 2.7 V must be insured. Therefore, a drain terminal voltage condition for programming cannot be satisfied. Furthermore, even when a 3.3 V stabilized power source is produced by the use of a voltage booster inside a chip, the increase of the area of the voltage booster necessary for supplying a large current for the hot carriers becomes essentially necessary, and this renders an obstacle for reducing the chip area.
In contrast, the nonvolatile semiconductor memory utilizing the F-N tunneling mechanism is effective for reducing power consumption because the program/erase operation of the data is effected using a very small current of the tunnel current.
However, the cell of the EEPROM comprising the floating gate type F-N tunnel transistor and the select transistor according to the prior art involves the problem that the cell area is great. Moreover, the inventors of the present invention have clarified, as a result of studies, the problems that the flow threshold voltage of the floating gate type F-N tunnel transistor assumes a negative value due to the circuit scheme of the memory cell and that a large drain current flows through the memory cell at the time of the programming operation because a switch transistor is not interposed between the source terminal of the floating gate type F-N tunnel transistor of the memory cell and the common source line.
The ACEE according to the prior art described above has the impurity layer wiring structure which can reduce the number of contact holes per bit of the memory cell, and reduces the memory array area. However, the memory cell itself substantially requires two regions, that is, the transistor region and the exclusive tunnel oxide film region for generating the F-N tunneling mechanism, and the increase of the memory cell area is unavoidable.
Now, let""s consider the case where the floating gate type field effect transistor structure described in JP-A-4-14871 is applied to the ACEE circuit scheme in order to avoid the increase of the memory cell area. In this case, according to the circuit operation of the ACEE of the prior art described above, the control gate selected at the time of programming of the data into the memory cell is set to 18 V and the data line to 0 V. Accordingly, the memory cell is under the inversed state, and the electrons are injected into the floating gate through the whole channel. Accordingly, it has been found out that the data write time becomes longer than when a transistor having an original exclusive tunnel region is used.
In the circuit operation of the ACEE according to the prior art described above, a 7 V voltage is applied to the data line to inhibit programming and the source line is charged through the non-selected memory cells. However, since the charge current of the source line flows from the drain terminal of the non-selected memory cell to the source terminal, injection of the hot electrons into the floating gate is more likely to occur, so that programming of electrons into the non-selected memory cells takes place This phenomenon is referred to as xe2x80x9cdisturbancexe2x80x9d. It has been found out that this disturbance invites the rise of the threshold voltage in the non-selected memory cells.
It has been found out further that when the floating gate type field effect transistor structure is applied to the ACEE, variance of the threshold voltage (low threshold voltage) at the time of erasing must be restricted. In the erasing operation, the positive voltage is applied to the source terminal and the negative voltage to the control gate, so that the electrons can be pulled out from the floating gate to the source impurity layer by the tunneling mechanism. Since the source impurity layer region serves as the tunnel region, any variance of the formation process of the source impurity layer results in variance of the tunnel current. This variance of the tunnel current is greater than variance occurring in the structure where the tunnel region is exclusively disposed. As a result, when the memory cells existing on the same word line are erased at one time, variance of the tunnel current invites variance of the erase time. Accordingly, the erase voltage is excessively applied to the memory cell which is erased at the earliest timing and its threshold voltage is likely to become negative. The greater the scale of the memory array, the greater becomes variance of the formation process of the source impurity layer as the cause of this phenomenon. Accordingly, it has been found out that a large scale memory cell is difficult to attain
As described above, the inventors of the present invention have clarified that though the circuit scheme of the ACEE is effective, there still remain the problems of programming characteristics, disturbance characteristics and expansion of the scale of the memory array when the ACEE is accomplished by the mere use of the floating gate type field effect transistor structure.
Further, when the nonvolatile semiconductor memory described in JP-A-4-14871 is examined, the following problems are found out to increase the memory array scale, though this device has the possibility of a higher integration density and a higher readout speed.
(1) To promote miniaturization, this memory employs a sub bit line structure using a silicide or a refractory metal, but one contact region per two bits must be disposed. Accordingly, the memory cell area must still be reduced effectively.
(2) The erasing operation is effected by applying the positive voltage Vp to the control gate and grounding the source and drain terminals, and the programming operation is effected by grounding the control gate and applying the positive voltage Vp to the drain impurity layer. Accordingly, degradation of the tunnel oxide film in the vicinity of the source region is remarkable and current drivability xcex2 of the memory cell drastically drops. More specifically, when the programming operation is carried out by grounding the control gate and applying the positive voltage Vp to the drain diffusion layer, holes of the electron-hole pairs occurring at the drain terminal are injected into the gate oxide film in accordance with the direction of the electric field when the number of times of program/erase is small, the injection quantity of the holes is small, and degradation occurs only at the drain terminal and does not invite the drop xcex2 of the memory cell. As the number of times for program/erase increases, the injection quantity of the holes becomes greater and drain expands from the drain terminal to portions in the vicinity of the source. For this reason, it becomes difficult to guarantee the number of times of program/erase of at least 106 which is required for a large capacity file memory.
It is therefore an object of the present invention to provide a nonvolatile semiconductor memory having low power consumption, capable of a high speed operation and having an effectively reduced cell area in a nonvolatile semiconductor memory having an electric programmable/erasable function.
It is another object of the present invention to provide a non-volatile semiconductor memory ensuring the number of times of program/erase of at least 106 and optimal for a large scale memory array in both aspects of programming characteristics and disturbance characteristics.
The objects described above can be accomplished by a nonvolatile semiconductor memory having an electric programmable/erasable function, as typified by a preferred embodiment of the present invention shown in FIG. 1, for example, which comprises memory arrays each comprising a plurality of memory cells disposed in matrix having rows and columns, wherein each memory cell comprises one MOSFET including a source region 6 and a drain region 7 disposed on a semiconductor substrate in a mutually spaced-apart relationship, a floating gate electrode 3 formed through a gate insulating film 2 having a uniform film thickness from the surface of the source region to the surface of the drain region 7 and a control gate 5 formed on the floating gate electrode 3 through an intermediate insulating film 4, wherein the drain regions of a plurality of memory cells on the same column are connected to a data line formed for each column and the control gates of the memory cells on the same row are connected to a word line formed for each row, wherein a voltage having a first polarity with respect to the semiconductor substrate 1 is applied to the drain region 7 of the memory cell which is an object of a programming operation and a voltage having a second polarity different from the first polarity with respect to the semiconductor substrate 1 is applied to the control gate 5 of the memory cell when the programming operation is effected, so as to set the source region 6 of the memory cell to the same potential as the potential of the substrate, and wherein a voltage having the first polarity with respect to the semiconductor substrate 1 is applied to the control gates 5 of a plurality of memory cells to be subjected to an erasing operation and all the other electrodes and the semiconductor substrate 1 are kept at the same potential when the erasing operation is effected.
In this way, the present invention accomplishes low power consumption by the program/erase system utilizing the tunneling mechanism. On the other hand, miniaturization of the memory cell area can be accomplished by the memory cell structure shown in FIG. 1.
In the erasing operation, the voltage having the first polarity is applied to the control gate 5 and the source region 6 and the drain region 7 are brought to the same potential as that of the substrate. Accordingly, the F-N tunneling develops through the gate oxide film 2, and the electrons are charged into the floating gate 3 from the whole channel of the memory cell. In consequence, the threshold voltage of the memory cells on the same row is raised. A plurality of memory cells having the control gates thereof connected to a plurality of word lines can be collectively erased by selecting at one time a plurality of word lines. Unlike the programming operation of the ACEE described above, this erasing operation does not charge the source line through the memory cells, into which programming is not made, by applying the voltage having the first polarity to the data line. Therefore, the problem of degradation of the hot carriers due to the charge current, etc., of the source line does not occur.
In the programming operation, the voltage having the second polarity is applied to the control gate 5 while the voltage having the first polarity is applied to the drain region 7, and the source region 6 is brought to the same potential as the substrate potential.
Accordingly, the F-N tunneling develops through the gate oxide film 2 and the electrons are released from the floating gate 3 to the drain diffusion layer side using an overlapped portion (hereinafter after referred to as the xe2x80x9cdrain diffusion layer edge regionxe2x80x9d) between the drain diffusion layer 7 and the floating gate 3, so that the threshold voltage of the memory cells becomes low. The programming operation is effected in the word line unit, the voltage of the data line connected to the memory cell to be subjected to programming is set to the voltage having the first polarity, and the voltage of the data line connected to the memory cells, for which programming is not made, is brought to the same potential as the substrate potential. In this way, programming can be made to desired memory cells.
In the readout operation, the selected word line is set to the voltage having the first polarity while the non-selected word lines are kept at the same potential as the substrate potential. The memory cell for which programming is made is turned ON and a current flows, but the memory cells for which programming is not made are turned OFF and no current flows. Accordingly, the ON/OFF state of the memory cells can be obtained by observing the current or the voltage flowing through the data line by the use of a sense amplifier connected to the data line.
USPTO Backgrounds
USPTO Backgrounds