1. Technology Field
The present invention is directed to a data writing method and more particularly, a data writing method for a rewritable non-volatile memory module, a memory control circuit unit and a memory storage apparatus using the same.
2. Description of Related Art
Digital cameras, cell phones, and MP3 players have undergone rapid growth in recent years, so that consumers' demands for storage media have also been increased drastically. Due to having the characteristics of non-volatility of data, low power consumption, small volume, non-mechanical structure, and fast reading and writing speed, the rewritable non-volatile memory is the most adaptable memory applied in a portable electronic product, e.g., a notebook computer. A solid state drive (SSD) is a storage apparatus which utilizes a flash memory as its storage medium. Therefore, the flash memory industry has become a very popular part of the electronic industry in recent years.
According to the number of bits which each memory cell thereof is capable of storing, an NAND flash memory may be classified into a Single Level Cell (SLC) NAND flash memory, a Multi Level Cell (MLC) NAND flash memory, or a Trinary Level Cell (TLC) NAND flash memory. Specifically, each memory cell in the SLC NAND flash memory can store one bit of data (i.e., “1” or “0”), each memory cell in the MLC NAND flash memory can store two bits of data, and each memory cell in the TLC NAND flash memory can store three bits of data.
In the NAND flash memory, a physical programming unit is composed of several memory cells arranged on the same word line. Since each memory cell in the SLC NAND flash memory can store one bit of data, several memory cells arranged on the same word line in the SLC NAND flash memory correspond to one physical programming unit.
By contrast, a floating gate storage layer in each memory cell of the MLC NAND flash memory can store two bits of data, and each storage state (i.e., “11,” “10,” “01,” or “00”) includes the least significant bit (LSB) and the most significant bit (MSB). For instance, the first bit from the left of the storage states is the LSB, and the second bit from the left of the storage states is the MSB. Accordingly, several memory cells arranged on the same word line may constitute two physical programming units, and therein, the physical programming unit constituted by the LSB and the MSB of the memory cell are a lower physical programming unit and an upper physical programming unit, respectively. In particular, the speed of writing data into the lower physical programming unit is faster than writing data into the upper physical programming unit, and when a program failure occurs in the process of programming the upper physical programming unit, the data stored in the lower physical programming unit may be lost.
Similarly, each memory cell in the TLC NAND flash memory can store three bits of data, and each storage state (i.e., “111,” “110,” “101,” “100,” “011,” “010,” “001,” or “000”) includes the first bit (i.e., the LSB), the second bit (i.e., the center significant bit, CSB), and the third bit (i.e., the MSB) from the left of the storage states. Accordingly, several memory cells arranged on the same word line may constitute three physical programming units, and therein, the physical programming unit constituted by the LSB is a lower physical programming unit, the physical programming unit constituted by the CSB is a middle physical programming units, and the physical programming unit constituted by the MSB of the memory cells is an upper physical programming unit. Specifically, when programming the memory cells on the same word line, only one of merely programming the lower physical programming unit or simultaneously programming the lower physical programming unit, the middle physical programming unit and the upper physical programming unit can be selected; otherwise, the stored data may be lost.
Generally, in a memory module using the TLC NAND flash memory, due to part of the physical erasing units therein being grouped as those using the single-page mode only for operating the lower physical programming units to stimulate the operation of the SLC NAND flash memory, the lifespan (the maximum threshold of erasing number) is increased, and due to the single-page mode being only used for operating the lower physical programming unit, the writing and the reading speeds are also significantly increased. The part of the physical erasing units which simulate the operation of the SLC NAND flash memory are used as a buffer area of the memory module to temporarily store data or to store system data. However, if a great portion of the data are used for the temporarily storing operation, the erasing count of the physical erasing units in the buffer area is dramatically increased, which results in physical erasing units getting old rapidly, such that unrecoverable data error occurs in the data which is later temporarily stored therein.
In light of the foregoing, how to avoid data error occurring due to the old physical erasing units in the buffer area and improve the reliability and efficiency for the flash memory of which each memory cell is capable of storing several bits has become one of the major subjects in the industry.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.
USPTO Backgrounds
USPTO Backgrounds