1. Field of the Invention
This invention relates in general to a process for fabricating semiconductor memory devices. In particular, this invention relates to a process for fabricating semiconductor read-only memory (ROM) cells by forming trenches on designated channel regions of the cells to turn them off while leaving other cells in the conducting state.
2. Description of Related Art
Read-only memory (ROM) devices, which comprise an array of memory cells, are widely utilized in digital electronic equipment. For example, computer systems including microcomputers and minicomputers use ROM devices for storing fixed software/firmware routines. Usually, the ROM devices are "programmed" with specific codes according to the customer's request. The fabrication process for ROM devices is complicated and requires sophisticated processing steps, each of which consumes precious manufacturing time for material processing and for adjusting manufacturing parameters.
Conventional ROM device memory cells use channel transistors as the electric charge storage components. In the programming stage, impurities are selectively implanted into the designated channel regions. The purpose of this selective impurity implantation is to change the threshold voltage of those "programmed" memory cells, so that the memory cell transistor may be controlled in either an ON or an OFF state to represent the binary bits one and zero respectively, or zero and one respectively, depending on the memory cell supporting logic design.
A brief examination of the specifics of a conventional ROM device helps to explain the present invention. FIG. 1 (Prior Art) of the accompanying drawing shows the top view of a conventional ROM device which exhibits the configuration of several memory cells as observed from above. FIG. 2 (Prior Art) is a cross-sectional view of the conventional ROM device memory cells taken along the II--II line which provides the details of the cells in another perspective.
As is shown in the drawing, a number of memory cells of the conventional ROM device are fabricated on a silicon substrate 10 of, for example, P-type. N.sup.+ source/drain regions (that later become bit lines 14) are formed in the designated locations of the silicon substrate 10. The top view of FIG. 1 (Prior Art) clearly shows that the N.sup.+ source/drain regions (that later become bit lines 14) are formed as long strips extending in one direction, namely, the vertical direction in the drawing which serve as the bit-lines for the memory cells of the ROM device. A gate oxide layer 12 is then formed over the surface of the silicon substrate 10, and on top of this oxide layer, gate electrodes (that later become word-lines 16) are formed to constitute the word lines for the memory cells in the ROM device. The word-lines 16 are, as is shown in the top view of FIG. 1 (Prior Art), also formed as long strips that extend in the direction substantially orthogonal to the extending direction of the bit lines 14. In this example, the word-lines 16 extend in the horizontal direction in FIG. 1 (Prior Art). Channel regions 18 for the memory cell transistors are formed between every two abutting bit-lines 14 and under each word-line 16. The status of either conducting or blocking of each of the memory cell transistor determines its memory content of either binary one or zero (or either zero or one) respectively.
A ROM device having the basic memory cells as described above has all the memory cell transistors turned on, or, in other words, in the conducting state unless they are programmed with data. To turn off a selected memory cell transistor, its channel region 18 would have to be implanted with P-type impurities. The process of programming the data bits into the selected memory cells of the ROM device is a process referred to as code implantation. Those memory cell transistors with their channel regions implanted with P-type impurities will have increased threshold voltage in the channel region.
However, such ROM devices having the memory cell configuration as described above have at least two disadvantages. Due to the need to reduce the size of virtually every dimension in the device as ROM devices become increasingly miniaturized, it is inevitable that the width of the word lines for the memory cells is also reduced. Such a reduction in the width of word lines 16 result in increased electrical resistance over the cross section of each word line. And, increased electrical resistance directly translates into reduced memory access speed. Furthermore, code implantation is a relatively inaccurate procedure, as the dimensions of the memory cell transistor are reduced. Excessive diffusion of the implants into the designated channel region, as well as implantation location shifting constitute the primary problems of these conventional ROM devices. The operating characteristics exhibited by such faulty memory cells typically include electric current leakage, or a lowering of the breakdown voltage.
USPTO Backgrounds
USPTO Backgrounds