The present invention a chip scale packaging, and more particularly to a low cost and high performance chip scale package mounted to a highly thermal conductive printed wiring board (PWB) assembly.
In order to package more electronic components in a limited space, electronic components have become smaller and smaller. For the active devices, integrated circuits (ICs), the package size has been reduced from dual in-line packages (DIPs) to flatpacks, to leadless chip carriers (LCCs), to chip-on-board (COB), and to flip chip. One of the smallest active components is the flip chip die. In a flip chip die, the IC die is flipped and soldered to the PWB directly to achieve one of the highest packaging densities. One problem with flip chip dice is that not all of the existing IC dice can be used with this technology due to small bond pad pitch and bumping requirements. To solve this problem, chip scale packaging technology (CSP) was invented. The chip scale package adds a redistribution layer to an existing die and to add some adhesive layers on the top of the IC die bond pads to protect the aluminum pads from corrosion. The redistribution layer is used to redistribute the small pitched peripheral IC bond pads to a large pitched area array solder pads; these solder pads are used to form micro ball grid array (xcexcBGA). The xcexcBGA can be soldered to the PWB with standard surface mount technology (SMT) soldering process.
There are many ways to convert an IC die to a CSP. The easiest way to package a CSP is to attach a redistribution layer on the top of the die. The xcexcBGA are placed on the other side of the redistribution layer for soldering purposes. The problem with this kind of approach is that the coefficient of thermal expansion (CTE) of the CSP (xcx9c3 PPM/xc2x0 C.) is much smaller than the PWB material (xcx9c14 PPM/xc2x0 C.). Large CTE mismatch will cause the solder joints between the CSP and PWB to fail.
One of the most popular and most reliable CSP devices are made by a company called Tessera (3099 Orchard Dr., San Jose, Calif. 95134). The Tessera CSP uses a specially designed compliant device to decouple the effect of the low CTE die from the redistribution layer. The redistribution layer has the similar CTE as the PWB. The stress caused by the small CTE mismatch between the redistribution layer of the CSP and PWB is very low, long life is expected on the solder joints. One problem with this type of CSP is that the associated non-recurring cost to design and fabricate the package is high. If the quantity usage of this package is high, the non-recurring cost can be amortized over the large quantity. However, if many different kinds of ICs are used, and the quantities of each IC are small, then, it will be non-economical and unpractical to use this technology. Besides cost issues associated with ordinary CSP, heat transfer may be another serious consideration. The device used in many reliable CSPs will not only decouple the CTE from the IC dice, but also decouple the heat transfer path and increase signal path to the PWB. When the functionality and speed of the ICs are increased, this kind of device may not serve the purpose.
It is, therefore, one object of the invention to increase reliability of an integrated circuit mounted to a printed wiring board by reducing the stress between the interconnects between the die and the printed wiring board.
In one aspect of the invention, a circuit assembly has a die with a plurality of die pads. A first circuit layer has a first side and a second side. The first side has a first plurality of circuit pads coupled to the plurality of die pads. The second side has a second plurality of circuit pads. A second circuit layer is coupled to a heat sink. The second circuit layer has a third plurality of circuit pads coupled to the second plurality of circuit pads.
In a further aspect of the invention, the first circuit layer and the second circuit layer are compliant. This allows stress to be released from the interconnects between the first circuit layer and the second circuit layer.
In a further aspect of the invention, the coefficient of thermal expansion (CTE) of the heat sink and the die are as closely matched as possible to reduce stress in the interconnect.
In another aspect of the invention, a method of assembling a circuit comprises the steps of: coupling a die to a first side of a first circuit layer to form a chip scale package assembly; bonding a second circuit layer to a heat sink to form a heat sink assembly; and, coupling the first circuit layer to a second circuit layer.
One advantage of the invention is that underfill, which is commonly required between an integrated circuit die and a small, flexible printed wiring board may be eliminated. This reduces the cost and cycle time of the assembly process time while increasing the reliability of the assembly.
Other objects and features of the present invention will become apparent when viewed in light of the detailed description of the preferred embodiment when taken in conjunction with the attached drawings and appended claims.
USPTO Backgrounds
USPTO Backgrounds