Field of the Invention
The present disclosure generally relates to a three-dimensional (3D) package including multiple integrated circuit (IC) chips, stacked one atop the other, on a laminate and a method of fabricating a hybrid 3D package including the hybrid processes of forming through-silicon-vias (TSVs) in each stacked IC chip and of tape automated bonding (TAB) from at least one stacked chip to the laminate.
Description of Related Art
A three-dimensional (3D) package contains two or more integrated circuit (IC) chips stacked vertically, so as to occupy less space and provide greater connectivity between IC chips. It can, however, be difficult to obtain low-cost, high-performance electrical connections between stacked IC chips. For example, IC chips can be electrically coupled using wire bonds between exposed bond pads on surfaces of a stack of chips, in which the chips are offset from one another to define a staircase of chip edges. But while these wire bonds can be implemented using low-cost assembly techniques, the resulting wire bonds typically have a higher resistance and lower bandwidth for signal transmission due to their length.
In contrast, through-silicon-vias (TSVs) typically have a lesser length and higher bandwidth for signal transmission when compared to wire bonds. In a TSV fabrication process, an IC chip is fabricated so that one or more of the metal layers on its active side is electrically connected to pads on its back side. Multiple IC chips are then adhesively connected in a stack, so that the pads on the back side of one chip make electrical contact with corresponding pads on the active side of an overlying chip.
However, a disadvantage of stacked IC chips with TSVs can include the large number of TSVs required for the transmission of I/O signals from the topmost chip or an upper level chip to the underlying laminate base or a lower level chip that requires a pathway of TSVs through all of the intervening chips. In addition, the efficient distribution of power/ground to upper level chips from the underlying laminate base also suffers from transmission losses through the pathways of TSVs, each of which includes the TSVs of each of the intervening chips in the stack.
Tape automated bonding (TAB) is a method for efficiently and simultaneously connecting a number of bonding pads on an IC chip to external circuitry. TAB has several advantages over wire bonding technology, including: smaller bonding pads; smaller on-chip bonding pitch; a decreased amount of solder for bonding; uniform bond geometry; and increased production rate through “gang” bonding. The method employs a continuous metallized tape having individual frames, each of which includes a pattern of metal leads formed on a tape of polyimide or polyamide film. The inner ends of the metal leads can define a rectangular pattern, corresponding to a rectangular pattern of peripheral bonding pads on the top surface of the IC chip. In TAB, it is common for a “bump” to be formed on a bonding pad of the IC chip to provide solder material. An outer end of each metal lead extends from the inner end, associated with the rectangular pattern, toward the periphery of each tape frame, where it can connect to external circuitry, such as that formed on a laminate base.
There remains a need for a three-dimensional (3D) package including multiple integrated circuit (IC) chips, stacked one atop the other, on a laminate that provides a more efficient distribution of signals and of power/ground between all levels of a chip stack and of a laminate base.
USPTO Backgrounds
USPTO Backgrounds