This invention relates to digital circuits, and, more particularly, to a buffer that uses inverters to operate at a high speed and is easily adaptable to buffer complimentary signals and/or provide hysteresis.
Input buffers are commonly used in a wide variety of digital circuits. There are also several types of input buffers. For example, there are single ended input buffers in which a single input signal is applied to the buffer to cause the buffer to transition when the input signal transitions through predetermined voltage levels. Single-ended input buffers may also compare the input signal to a reference voltage so the output of the input buffer transitions when the input signal transitions through the reference voltage. There are also complimentary input buffers in which a pair of complimentary signals cause the output of the buffer to transition when one of the input signals transitions through the level of the other input signal.
All of these varieties of buffers generally perform a number of advantageous functions when used in digital circuits. For example, input buffers generally provide a high input impedance to avoid unduly loading signal lines coupled to their inputs. They also condition signals applied to internal circuits so that internal signals have well defined logic levels and transition characteristics. Other advantages of input buffers are also well-known to one skilled in the art.
Although input buffers can provide a number of advantages, they are not without some disadvantages and limitations. For example, considerable circuitry can be required to provide a sufficient number of input buffers to accommodate a large number of input signals. Even more problematic in high speed digital circuitry can be delays in propagating digital signals through input buffers. The time required to propagate input signals through input buffers can greatly increase the time required to couple digital signals to internal circuits used in integrated circuits, thus reducing the operating speed of integrated circuits using such input buffers.
There is therefore a need for an input buffer that uses relatively little circuitry, inherently operates at a fast rate of speed, and that can be readily adapted for use as an input buffer in a wide variety of circuits and applications.
An input buffer according to the invention uses at least six inverters arranged in a specific topography. A first inverter has an input node coupled to an input terminal of the input buffer and an output node coupled to the output terminal of the input buffer. A second inverter has an input node coupled to either a complimentary input terminal of the input buffer or a reference voltage, and an output node that may be coupled to a complimentary output terminal of the input buffer. A third inverter has an input node coupled to the output terminal of the input buffer and an output node coupled to the output terminal of the input buffer. A fourth inverter has an input node coupled to the output node of the second inverter and an output node coupled to the output node of the second inverter. A fifth inverter has an input node coupled to the output node of the first inverter and an output node coupled to the output node of the second inverter. Finally, a sixth inverter has an input node coupled to the output node of the second inverter and an output node coupled to the output node of the first inverter. The inverters may be implemented using a variety of inverting circuits and amplifiers, including complimentary two-transistor inverting circuits, resistor-transistor inverting circuits and differential amplifiers. Since there is only a single inversion between the input terminal and the output terminal of the input buffer, the input buffer is able to operate at a high speed.
USPTO Backgrounds
USPTO Backgrounds