1. Field of the Invention
The present invention relates to an information transfer equipment, and in particular to an information transfer equipment which executes a monitoring control of each of channel portions by transmitting/receiving plural kinds of monitoring control information between the channel portions and a common portion.
In recent years, a communication system has aimed at a high transmission capacity and an enhanced monitoring control function regardless of its kind, resulting in an enlarged hardware scale. In a system accomplishing the monitoring control function, it is important that an information transfer equipment works efficiently on the aspects of function and cost.
2. Description of the Related Art
Generally, an information transfer equipment mounts thereon a microprocessor (CPU) and performs its main function with firmware/software. In particular, a function block which manages a monitoring control has achieved a speedup and a high-performance in the form of multi-CPU.
Also, such an information transfer equipment enlarged in its hardware scale as mentioned above is generally composed of a plurality of racks. Accordingly, the monitoring control apparatus must execute the monitoring control to all of the racks.
FIG. 7 shows an arrangement of a conventional information transfer equipment in the monitoring control apparatus of a communication system adapted to SDH (Synchronous Digital Hierarchy). The conventional information transfer equipment comprises channel portions (xe2x95x90CH portions) 50_1, 50_2, 50_3, . . . (hereinafter sometimes generally referred to as xe2x80x9c50xe2x80x9d) which are transmission system processors and a common portion 10 which is connected to each of the channel portions 50_1, 50_2, 50_3, . . . . The common portion 10 comprises a main CPU, an Engineering order wire (hereafter abbreviated as EOW) processor (processing unit), a user channel (hereinafter abbreviated as Uch) processor, a DCC (Data Communication Channel: hereinafter abbreviated as DCC) processor, a system clock source (hereinafter abbreviated as TCU) processor, and a Radio Protection switchover (hereinafter abbreviated as RPS) processor.
Between each of the channel portions 50 and the main CPU, the EOW processor, the Uch processor, the DCC processor, the TCU processor, and the RPS processor, a bus access related signal, an EOW related signal, a Uch related signal, a DCC related signal, a TCU related signal, and an RPS related signal which all form monitoring control information are transferred.
Namely, the common portion 10 and each of the channel portions 50 have processors which execute processes corresponding to the types of the above-mentioned signals. The processors transmit and receive those signals through physically different transmission/reception lines 110, 111 prepared for each signal type.
In operation, each of the channel portions 50 executes a terminal process of a main signal transmission line per channel, and transmits the monitoring control information to the common portion 10 through the reception line 111. The common portion 10 sends the monitoring control information and a control signal to the channel portions 50 through the transmission line 110.
In the common portion 10, the main CPU executes a write and a read access to each of the channel portions 50 with an address signal, a data signal, a memory read signal, a memory write signal and the like which are bus access related signals for the monitoring control to the channel portions 50.
The EOW processor, the Uch processor, and the DCC processor transmit/receive E1 and E2 byte signals for voice consultation or F1 byte signal an operator of the network uses, and D1-D12 byte signals by which the monitoring control information is transferred, respectively defined by an overhead of STM (Synchronous Transport Module) signal of the SDH, to/from each of the channel portions 50, and process them. The TCU processor transmits/receives clock quality information of the common portion 10 and the channel portion 50 to/from each of the channel portions 50. The RPS processor transmits/receives a switchover signal, an RPS initiator notification and the like which are wireless related control information peculiar to a multiplex wireless apparatus to/from each of the channel portions 50.
In such a conventional information transfer equipment, the number of an interface cable which connects the common portion to each of the channel portions increases in proportion to the number of the channel portions and the signal type. Also, in the common portion, it has been necessary to normally prepare interface access points corresponding to the largest number of the channel portion which can be connected, so that the following points have been main causes of increased cost of the equipment:
{circle around (1)} The cable cost is high;
{circle around (2)} The connector cost is high;
{circle around (3)} It is necessary to detect each cable disconnection or to generate an equivalent alarm, so that alarm items of a circuit fault increase and press the monitoring control process;
{circle around (4)} A burden of an installation and a local adjustment of the equipment increases;
{circle around (5)} Since a transmission between racks is required and it is inevitable to use an input/output device for an interface signal, the number of the devices and electric power consumption increase, leading to an increase in cost.
It is accordingly an object of the present invention to provide an information transfer equipment which executes a monitoring control of each of channel portions by transmitting/receiving plural kinds of monitoring control information between the channel portions and a common portion in which the monitoring control information is transferred without any increase in cost and burden of a monitoring control process of the equipment.
[1] To achieve the above-mentioned object, in the information transfer equipment according to the present invention, as shown by a schematic arrangement in FIG. 1, a multiplexer of a common portion 10 multiplexes and transmits, by broadcasting, monitoring control information 90 into a predetermined position of a Time Division Multiplexing (hereinafter abbreviated as TDM) frame. A demultiplexer of each of channel portions 50_1-50_8 receives the TDM frame and demultiplexes therefrom the monitoring control information 90.
Also, the multiplexer of the channel portions 50 multiplexes and transmits each of the monitoring control information 90_1-90_8 (hereinafter generally referred to as xe2x80x9c90xe2x80x9d) into a Time Division Multiple Access (hereinafter abbreviated as TDMA) frame based on a channel number preset for its own. A demultiplexer of the common portion 10 receives the TDMA frame and demultiplexes therefrom the monitoring control information 90.
Namely, the common portion 10 executes the TDM-multiplexing of plural kinds of the monitoring control information 90 on a transmission line 110 of one system and broadcasts it to the channel portions 50. Each of the channel portions 50 executes the TDMA-multiplexing of the monitoring control information 90 of its own on the reception line 111 of one system and transmits it to the common portion 10.
As a result, it becomes possible to connect the common portion 10 to the channel portions 50 with the information transfer equipment in which an interface is integrated to one system.
[2] In the above-mentioned invention [1], the multiplexer of each of the channel portions 50 may transmit a transmission timing of the TDMA frame 114 in synchronization with a timing of the TDM frame 112.
As a result, it becomes possible to easily synchronize transmission/reception timings of the multiplexers and the demultiplexers in the common portion 10 and each of the channel portions 50.
[3] In the above-mentioned invention [1], processors of the common portion 10 and each of the channel portions 50 may process the monitoring control information 90 including overhead information of an STM signal of SDH. The multiplexer of the common portion 10 may multiplex the monitoring control information 90 including the overhead information into the TDM frame synchronized with a synchronous clock of the SDH for broadcasting.
The multiplexer of each of the channel portions 50_1-50_8 multiplexes the monitoring control information 90 including the overhead information into the TDMA frame synchronized with the synchronous clock for transmission. As a result, it becomes possible to easily adapt the information transfer equipment to an SDH communication system.
[4] In the above-mentioned invention [3], a buffer of each of the channel portions 50_1-50_8 may temporarily store the overhead information in the TDM frame. The overhead information stored in the buffer is written in a predetermined position of the overhead of the STM signal at a predetermined timing.
Also, a second buffer reads out the information in the overhead of the STM signal at a predetermined timing and temporarily stores it. The overhead information stored in the second buffer is written in a predetermined position of the TDMA frame at a predetermined timing.
As a result, it becomes possible for each of the channel portions 50 to equivalently execute a speed conversion of the overhead information in the TDM frame through the buffer, which is multiplexed into the overhead of the STM signal, and to equivalently execute a speed conversion of the overhead information in the STM signal through the other buffer, which is multiplexed into the predetermined position of the TDMA frame.
[5] In the above-mentioned invention [1], a setting portion of each of the channel portions 50 sets time slots of the TDM frame and the TDMA frame corresponding to the channel number from the outside. Each of the channel portions 50 accesses the designated time slots of the TDM frame to receive the monitoring control information 90, and the designated time slots of the TDMA frame to transmit the monitoring control information 90.
As a result, it becomes possible for each of the channel portions 50 to designate and change a communication circuit channel (the time slots of the TDM and TDMA frames) which is accessed to transmit the monitoring control information 90.
[6] In the above-mentioned invention [1], a CPU of the common portion 10 processes the monitoring control information 90. The operation of the CPU upon a write access to each of the channel portions 50 will now be described referring to FIG. 2 as follows:
A packet generator in the common portion 10 extracts an address or data on the system bus of the CPU at every timing when the CPU makes the write access to each of the channel portions 50 to generate packet data (see FIG. 2A {circle around (1)}, {circle around (2)}.
A packet buffer divides the packet data into an amount which can be transmitted within one period of the TDM frame (see FIG. 2B) for the accumulation. A write data read controller reads out the packet data by a single TDM frame from the packet buffer and multiplex the same into predetermined prescribed slots of the TDM frame (see FIG. 2C {circle around (1)}, {circle around (2)}.
A CPU bus generator of each of the channel portions 50 generates a pseudo CPU bus of the CPU from the address and the data of the packet data received from the TDM frame.
As a result, it becomes possible for the common portion 10 to transmit a CPU write signal which is the monitoring control information 90 the CPU outputs on the system bus addressed to the channel portions 50 to the TDM frame, and for each of the channel portions 50 to output the CPU write signal to the pseudo CPU system bus of its own.
[7] In the above-mentioned invention [6], at least one packet write threshold may be preset. The packet generator monitors the packet data amount accumulated in the packet buffer. When the packet data amount has exceeded the threshold, the return of an acknowledge signal transmitted to the CPU is delayed.
As a result, a cycle in which the CPU makes the write access to each of the channel portions 50 is delayed, and it becomes possible to prevent the packet buffer from overflowing.
It is also possible to suppress the packet data from the CPU by setting a plurality of thresholds and delaying the return of the acknowledge signal as the remaining memory capacity of the packet buffer becomes less.
[8] In the above-mentioned invention [6], a packet read controller of the common portion 10 adds error detection data to the packet data accumulated in the packet buffer and transmit the same to the TDM frame. When an error is detected in the received packet data based on the error detection data in each of the channel portions 50, a resend demand signal of the packet data is transmitted to predetermined time slots of the TDMA frame regardless of the packet data being addressed to its own or not.
When a write data read portion receives the resend demand signal in the common portion 10, the packet data in the last frame is resent. Also, when the resend demand signal of the same packet data has reached a predetermined largest number of resend times, the resending operation is stopped.
As a result, it becomes possible for the CPU to transfer write data as the monitoring control information 90 transmitted to the channel portions 50 at a small error rate and to avoid a useless resending operation due to the fault of the equipment or the like.
[9] In the above-mentioned invention [1], an address generator in each of the channel portions 50 generates a read address for the pseudo CPU, and a CPU bus generator generates a data read signal in the pseudo CPU bus of the CPU based on the read address. The data buffer stores the data and the read address accessed by the data read signal, and the multiplexer transmits the stored data and the read address to predetermined time slots of the TDMA frame.
The demultiplexer in the common portion 10 demultiplexes the read address and the data from the predetermined time slots of the TDMA frame and stores the data at the read address in a CPU read interface memory. The CPU reads in the data from the CPU read interface memory through the system bus.
As a result, it becomes possible for the CPU of the common portion 10 to read in the data as the monitoring control information 90 read out on the pseudo CPU bus of each of the channel portions 50 through the transmission line 111 of the TDMA frame.
[10] In the above-mentioned invention [9], the multiplexer in the common portion 10 transmits a TDM multi-frame composed of a plurality of TDM frames including a TDM frame number. The demultiplexer in each of the channel portions 50 establishes a synchronization for the TDM multi-frame to demultiplex the TDM frame number.
The multiplexer in each of the channel portions 50 synchronizes the TDMA frame composed of a plurality of the TDMA frame with the TDM multi-frame and multiplexes the read data stored in the data buffer with the TDM frame number and the time slot position corresponding to the TDMA frame as address information into the TDMA frame and transmit the same.
The demultiplexer in the common portion 10 demultiplexes the read data, and the CPU interface memory stores the read data at the address corresponding to the TDM frame number and the slot position corresponding to the TDMA frame into which the read data is multiplexed. The CPU reads in the data from the CPU read interface memory through the system bus.
As a result, it becomes possible to transfer the read data as the monitoring control information 90 read out on the pseudo CPU bus in each of the channel portions 50 to the CPU in the common portion 10 through the transmission line 111 without inserting the read address into the TDMA frame 114.
[11] In the above-mentioned invention [10], an arithmetic unit in each of the channel portions 50 adds error detection data to the read data. A data error detector in the common portion 10 carries out the error detection based on the error detection data. When the error is detected, the CPU read interface memory abandons the read data and holds the read data in the previous state.
It means that error read data are not read in the CPU read interface memory and the error read data are not transferred to the CPU.
[12] In the above-mentioned invention [11], when the read data with an error detected is information indicating a mounting status of each of the channel portions 50, a fixed value indicating that an error has been detected is compulsorily written in the interface memory. When the read data is other information, the received data is abandoned and held in the previous state.
Namely, it becomes possible for the CPU of the common portion 10 to recognize that the mounting status of each of the channel portions 50 is abnormal from the fact that the fixed value is written in the address corresponding to the mounting status of the interface memory.
[13] In the above-mentioned invention [11], the monitoring control information may include transmission status information to the TDMA frame of the channel portion 50, control status information for the channel portions in the common portion 10, circuit switchover control information of the channel portions, and system clock control related information.
USPTO Backgrounds
USPTO Backgrounds