1. Field of the Invention
The invention relates generally to semiconductors and more specifically to the "antifuse" memory cell and interconnect structures used in programmable read only memories (PROMs) and application specific integrated circuits (ASICs).
2. Description of the Prior Art
Many different types of semiconductor devices use memory cells to store programs, data, and other important information. Two basic kinds of memory cells are the random access memory (RAM) and the read only memory (ROM). The memory cells in RAM may be read and written many times, but the storage is not permanent, and data will be erased when power is cutoff. The memory cells in ROM retain their data regardless of whether power is on or off, but once a memory cell is programmed, it generally cannot be reprogrammed. ROMs and ASICs can have data impressed into them by mask processing, laser, electron beam, focused ion beam (FIB), and/or electrical programming. (For laser and FIB programming, see, R. Iscoff, "Characterizing Quickturn ASICs: It's Done with Mirrors," Semiconductor International, August 1990, pp.68-73.) ROMs that can be electrically programmed, albeit only once, are called programmable read only memories (PROMs). Memory cells within some PROMs use fuse links that are literally blown open during programming. An opposite type of memory cell using "antifuse" technology, establishes a connection from an open state during programming. In large programmable or configurable systems and circuits, antifuse is much more efficient than fuse because typically only a fraction of antifuses need to be programmed for similar functions implemented with fuses. The prior art method of programming antifuses is almost always electrical programming. Raffel, et al. U.S. Pat. No. 4,585,490, issued Apr. 29, 1986, discloses using thin oxides as a metal diffusion barrier and silicon as a programming layer in a laser programmed device. However, the chemical reaction is simple aluminum alloying which does not have good reliability nor resistance to electromigration.
Polysilicon structures are conventional, and are used in fuse type PROM fabrication. One such structure is described in Preedy U.S. Pat. No. 4,420,820 issued Dec. 13, 1983. A polysilicon layer is formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and isolating diode. Because of the different impurity concentrations, one of the diodes will breakdown before the other.
Prior art antifuse methods include the use of dielectrics made of oxide, oxide/nitride/oxide sandwiched between silicon or polysilicon. These structures are characterized by high "ON" resistance (.gtoreq.1000.OMEGA.) and high electrical programming voltages (.gtoreq.15V). These two characteristics, respectively, make for low performance and difficulty in scaling to submicron processes. This structure, however, does not provide very low leakage current in the "off" state, due to its low bulk conductivity. Amorphized doped silicon by ion implantation has been used in the prior art to create PROM memory cells, and, for example, is described in Stacey, et al. U.S. Pat. No. 4,569,120, issued on Feb. 11, 1986. These structures have not exhibited good control of ON resistance and have limited scalability. Deposited amorphous-silicon on silicon has high parasitic (junction) capacitance, high series resistance and is difficult to remove inside normal contacts without damaging the underlying silicon. (Amorphous silicon is silicon without discernable crystalline grains, as opposed to polycrystalline silicon which has pronounced crystalline grain structures.) An amorphous semiconductor layer for use in a PROM is described in Lim, et al. U.S. Pat. No. 4,569,121 issued on Feb. 11, 1986. The present inventors have observed the best prior art antifuse performance comes from a sandwich layer of titanium-tungsten (TiW)/amorphous-silicon/TiW. Gordon, et al. U.S. Pat. No. 4,914,055, issued on Apr. 3, 1990 describes a TiW-Si-TiW structure that is planar and provides more uniform electric fields across an antifuse structure during programming. (The bottom TiW is not etched or damaged prior to Si deposition.) Hollingsworth U.S. Pat. No. 4,748,490, issued May 31, 1988, describes a deep polysilicon emitter antifuse memory cell having a titanium tungsten (TiW) alloy refractory conductive layer. ("Refractory" means very high melting temperature metal, compared to aluminum, gold, and silver.) There, the antifuse layer is alternatively fabricated from undoped polycrystalline silicon or amorphous silicon. A bipolar transistor that remains after programming is used to provide faster switching of the circuit. However, high temperatures must be used to deposit the amorphous layers, described above, and as such, the prior art techniques require very complicated processes to construct an antifuse element. At least four additional masks and nine more processing steps are typically necessary. Furthermore, the above prior art antifuse structures are not always compatible with standard submicron CMOS/BiCMOS metal processes. Another major disadvantage of amorphous-silicon based antifuse is that the leakage current is generally much higher than oxide or nitride based antifuse due to bulk conductivity differences.
Lower programming and operating currents in memory cells translate directly to smaller programming current devices, size and depth of the cell, and ultimately to the size and current capabilities of devices peripheral to the memory cell array. For example, Hollingsworth, supra, states that a bipolar coupling element provided with a 3100.ANG. thick polysilicon antifuse will require only a 3.12 milliamp programming current. But, still lower programming voltages and currents, e.g., under ten volts and one milliamp, are desirable for the above reasons. Prior art programming voltages and currents for fuse, antifuse, and electrically-programmable read only memory (EPROM) memory cells, each exceed ten volts or one milliamp, or both.
A prior art memory cell comprises a bipolar transistor, a read line, a program line, and a fuse link. The fuse link is literally blown open by a mini-explosion that scatters debris all around the immediate vicinity. A buffer area is required to allow for such material loss without losing circuit functionality. This buffer zone tends to require large areas of chip real estate and devices using the memory cell are not as dense as they otherwise might be. Because such a large programming current is required to blow the fuse link, the transistor must be a bipolar type. MOS transistors are not practical. Large programming currents also mean that minimum sized transistors cannot be used. Thereby further reducing functional device density.
Orbach describes a prior art programmable gate array device in U.S. Pat. No. 4,924,287, issued May 8, 1990. The device comprises laser programmable gate array logic cells where the programmable element is conventional fuselink and the resultant logic function is very limited and cannot implement MPGA functions on a direct gate-to-gate basis.
USPTO Backgrounds
USPTO Backgrounds