This invention relates to the field of electronic design automation, and in particular, the optimization of masks used for photolithographic printing of circuit designs, known in the field as optical proximity correction.
Production-scale chip manufacturing uses photolithographic techniques to build up layers of materials on a wafer to create the transistors, wires, and so on, that realize a chip design. The sizes of the features to be printed on the wafer are approaching the limits set by the wavelength of the light, the optical projection system, and the behavior of the light sensitive materials used, among many other factors.
Diffraction effects from the wavelength of the light source and the limits of the projection optics motivated the development of optical proximity correction (OPC) techniques to adjust the shapes on the mask to print more like the desired result on the wafer. For example, a square may have serifs added to its corners to compensate for excessive rounding of the corners of the printed feature, or the ends of a rectangle may have “hammerheads” added to further ensure the printed feature reaches the desired line end.
The first OPC methods were based on simple rules for modifying the shapes on the mask, but as the technology was pushed closer to optical resolution limits, model-based optimization, which adjusts the features on the mask to improve the calculated printed image, was developed. Two significant advantages of model-based OPC are the ability to account for proximity effects (warping a nearby feature will affect how a given feature prints) and to accommodate photoresist behavior.
Sometimes, features are found to print with greater fidelity if extra features are added to the mask that are too small to print themselves, but nevertheless favorably affect the way nearby main features print, especially over a range of process conditions. Introduction of these so-called subresolution assist features (SRAFs) is still generally done according to preset rules. Typically they are inserted first and held fixed as OPC is applied to the main features on the mask.
There are significant problems in applying these methods as the industry moves to ever smaller on-wafer dimensions. The rules used to insert SRAFs are becoming more complex and less reliable. The standard OPC methods do not have the flexibility needed to achieve the best results and require post-OPC verification and manual intervention.
What is needed is a practical model-based method for mask design that can automatically determine a mask that both satisfies mask manufacturing and verification criteria, and produces the desired print on the wafer over a range of process conditions, such as exposure and focus variation. Such a method will generally result in a mask that warps existing layout geometry and adds or subtracts SRAFs from anywhere, including in ways that split or join the layout features.
USPTO Backgrounds
USPTO Backgrounds