1. Technical Field
This invention relates generally to the manufacture of integrated circuit (IC) chips and, more specifically, to a method for forming images having sharp corners during lithographic processing by exposing the feature in two angularly intersecting directions and a photomask formed thereby.
2. Background Art
Corner rounding and image foreshortening are problems for both photomask fabrication (especially for laser writers) and also for wafer fabrication. This problem, as depicted schematically in FIG. 1, is usually observed for small image shapes which are near the resolution limit of the lithographic exposure tool. In mask fabrication, for example, large features print with a shape that closely approximates the designed image. The length and width of the large shapes matches the designed values, with a slight rounding of the corners of the pattern. This corner rounding can be caused by the reticle etch process, which for chrome films has historically been an isotropic, wet process. It can also be caused by the limitations in the resolution of the writing beam of the reticle expose tool, whether e-beam or optical laser. For the printing of small images, which are at or near the resolution limit of the expose tool, the corner rounding becomes more pronounced, and the length of the image can be severely shortened relative to its designed length. This can be caused by several factors, including the loss of edge acuity of the aerial image at the resolution limit of the expose tool, the variation in effective exposure dose for small images relative to larger images, and the degradation of the aerial image by chemical diffusion processes in the photoresist after expose. These problems can be compounded for lithography on the wafer because the reticle rounding and shortening effects are combined with the tool and process components from the wafer processing.
Image shortening and rounding can significantly affect the ability to scale devices to smaller groundrules. For example, the capacitance of a DRAM device is directly related to the area of the storage node. As DRAM devices are scaled to smaller dimensions, the corner rounding and shortening effects reduce the capacitance values which can be attained, and constrain the ability to scale the density of the DRAM array. In another example from DRAM, the overlap of a strap connection between storage node and diffusion areas can be limited by the rounding of strap and storage node during the lithographic process. The rounding of the strap and storage node pull the features away from each other so that they fail to intersect and make an electrical connection. In order to print the features large enough that the rounded corners intersect, an electrical short defect is created at other sections of the images where rounding and shortening effects are not observed, and the over-sized patterns fuse together.
Modeling has shown that a large percentage of the image shortening is due to mask corner rounding in the 64 Mb dynamic random access memory (DRAM) design, and becomes more pronounced for the 256 Mb DRAM design.
In the present era of very large scale integration and ultra large scale integration, new techniques are continuously being developed to more efficiently utilize the space within semiconductor devices while maintaining or improving present production efficiency.
As IC dimensions continue to shrink, printed lithographic features with minimal curvature are critical to achieve the packing density required to obtain the desired cell size.
The larger the curvatures on the images, the larger an area has to be allotted for two intersecting images. Therefore, printing of small rectangles with minimal foreshortening is becoming a difficult problem for the process fabricators as the dimensions of the structures become smaller.
Traditionally, masks have been fabricated with a single layer process in which a beam spot is rastered across an image to form a pattern. This technique inherently leads to corner rounding problems depending on the beam spot size. Smaller spots minimize the corner rounding problems, but these problems are solved at the cost of writing time and edge smoothness. Fore-shortening is also becoming an increasingly large problem at the mask level, as can be seen in FIG. 2.
What is known as the "k" factor is defined in the Rayleigh model for lithographic resolution, in the equation: EQU R=k.lambda./NA
where R is the resolution, k is an empirically derived parameter that is dependent on photoresist performance, .lambda. is the exposure wavelength, and NA is the numerical aperture of the expose tool. Presently, improving the "k" factor and reducing the wavelengths of the exposure have been the subject of much research, in order to improve resolution as feature size continues to decrease.
Issues relating to corner rounding and image foreshortening are becoming more acute as one uses lower "k" factor, i.e., lower fidelity lithography processes, in both the mask process and the wafer process in order to make increasingly smaller features. As is shown FIG. 2 in the new foreshortening data, as the design width decreases below 0.35 microns (.mu.m) the foreshortening becomes more pronounced.
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