1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing thereof, more particularly, to a semiconductor memory device and a method for manufacturing thereof in which a higher degree of integration and larger capacity can be implemented.
2. Description of the Prior Art
FIG. 1 is a block diagram showing one example of a general structure of a RAM. Referring to FIG. 1, a memory cell array 101 comprises a plurality of word lines and bit lines arranged so as to intersect with each other and a memory cell (not shown) is provided at each intersecting point between a word line and a bit line. A specific memory cell is selected in accordance with an intersecting point between one word line selected by an X address buffer decoder 102 and one bit line selected by a Y address buffer decoder 103. Data is written into a selected memory cell or data stored in the memory cell is read by a reading/writing control signal (R/W) which is applied to a R/W control circuit 104. In data writing, input data (Din) is inputted to the selected memory cell through the R/W control circuit 104. On the other hand, in data reading, data stored in the selected memory cell is detected and amplified by a sense amplifier 105 and externally outputted as output data (Dout) through a data output buffer 106.
FIG. 2 is an equivalent circuit diagram of a dynamic memory cell shown for describing writing/reading operation of the memory cell.
Referring to FIG. 2, the dynamic memory cell comprises one field effect transistor 107 and one capacitor 108. The field effect transistor 107 has one conductive terminal connected to one electrode of the capacitor 108 and the other connected to the bit line 109. The field effect transistor 107 has its gate connected to a word line 110. The other electrode of the capacitor 108 is grounded. In data writing, the field effect transistor 107 becomes conductive when a predetermined potential is applied to the word line, so that an electric charge from the bit line 109 is stored in the capacitor 108. On the other hand, in data reading, the field effect transistor 107 becomes conductive when a predetermined potential is applied to the word line 110, so that an electric charge stored in the capacitor 108 is taken out through the bit line 109. As obvious from the above description, in accordance with the fact that the storage capacity of the memory cell is based on the capacity of the capacitor 108, various attempts are made to maintain and increase the capacity of individual memory capacitors in order to implement a high degree of integration of the memory cell array. Such attempts are described in, for example Japanese Patent Publication No. 56266/1983 and 55258/1986, and Japanese Patent Laying-Open Gazette No. 65559/1985. As one example of these attempts, a trench memory cell was developed in which its storage capacity can be maintained or increased by forming a trench on a semiconductor substrate and forming an electric charge storage region on the inner surface of the trench.
FIG. 3 is a plan view showing a dynamic RAM using such trench memory cell and FIG. 4 is a sectional view taken along a line IV--IV in FIG. 3. Referring to these figures, a description is made of a structure. Referring to FIGS. 3 and 4, a plurality of memory cells 14 are formed on a surface of a P type silicon substrate 1. In FIG. 3, the memory cells 14 are separated by a separating oxide film 6. Each memory cell 14 comprises an electric charge storage region 15 storing an electric charge, a transistor region 16 and an N.sup.+ region 3 connected to a bit line 11. More specifically, the electric charge storage region 15 comprises a trench portion 5 formed on the main surface of the P type silicon substrate 1, an N type diffusion region 13 of the memory cell portion formed on the inner surface of the trench 5, an N.sup.+ region 4 formed on one portion of the main surface of the P type silicon substrate 1 and serving as a storage terminal of the memory cell capacitor, a capacitor insulating film 2 formed so as to cover the inner surface of the trench 5, a polycrystalline silicon region 5a formed on the inner portion of the trench portion 5, and a cell plate electrode 7 formed on the capacitor insulating film 2 and the polycrystalline silicon region 5a and serving as a counter electrode of the memory capacitor. The transistor region 16 comprises N.sup.+ regions 3 and 4, a channel region 17 existing therebetween, and a word line 9a forming a gate electrode. The word lines 9a, 9b and 9c are covered with the interlayer insulating film 10.
The bit line 11 formed on the interlayer insulating film 10 is connected to the N.sup.+ region 3 through a contact hole 18. The cell plate electrode 7 and the word line 9b are separated by the interlayer insulating film 8.
Referring to FIG. 4, a description is made of reading/writing operation of data of the memory cell 14. In data writing an inversion layer is formed on the channel region 17 when a predetermined potential is applied to the word line 9a and then the N.sup.+ region 3, and N.sup.+ region 4 and the diffusion region 13 of the memory cell portion become conductive. Therefore, an electric charge from the bit line 11 is transferred to the electric charge storage region 15 through the channel region 17 and stored in the diffusion region 13 of the memory portion. On the other hand, in data reading, an electric charge stored in the diffusion region 13 of the memory portion is externally taken out through the N.sup.+ region 3 and the bit line 11 when a predetermined potential is applied to the word line 9a.
Since an amount of electric charges stored in this way depends on the are of the diffusion region 13 of the memory cell portion formed on the inner surface of the trench portion 5, the formation of the trench portion 5 can contribute to the formation of relatively larger electric charge storage capacity than that of the plane occupied area of the electric charge storage region 15. More specifically, by forming the trench portion 5 and employing a trench capacitor using that trench portion, a capacitor having relatively large capacity ca be obtained in the occupied area of the memory cell which is made small.
FIGS. 5A to 5E are sectional views of schematic processes showing a method for manufacturing a conventional device.
Referring to these figures, a description is made of this manufacturing method.
First, referring to FIG. 5A, a separating oxide film 6 is formed at a predetermined portion of a main surface 1a of a P type silicon substrate 1. Then, referring FIG. 5B, a trench portion 5 having a predetermined depth is formed on a predetermined portion of the silicon substrate 1. Then, a diffusion region 13 of a memory cell portion is formed by implanting ions of a conductivity type opposite to that of the semiconductor substrate 1 (in this case, N type) on the inner surface of the trench portion 5.
Referring to FIG. 5C, a capacitor insulating film 2 serving as an oxide film is formed on the whole surface of the silicon substrate 1 including the inner surface of the trench portion 5. Thereafter, polysilicon 5a is filled in the trench portion 5 having its inner surface covered with the capacitor insulating film 2. Then, a cell plate electrode 7 having a plane portion of a predetermined configuration is formed so as to cover the trench portion 5 and interlayer insulating film 8 having a plane portion of a predetermined configuration is formed on the cell plate electrode 7.
Referring to FIG. 5D, polysilicon is deposited on the whole surface to apply a resist and word lines 9a, 9b and 9c are formed by photolithography and etching. N.sup.+ regions 3 and 4 are formed by implanting ions of a conductivity type opposite to that of the silicon substrate 1 (in this case, N type ion) on the exposed main surface of the silicon substrate 1. Then, an interlayer insulating film 10 is formed by depositing an oxide film by way of a CVD method on the whole surface of the silicon substrate 1 including the word lines 9a, 9b and 9c.
Referring to FIG. 5E, a contact hole 18 reaching the N.sup.+ region 3 is formed at a predetermined position of the interlayer insulating film 10 by performing photolithography and etching. Finally, aluminum is deposited on the interlayer insulating film 10 and in the contact hole 18, and bit line 11 connected to the N.sup.+ region 3 is formed by patterning the aluminum.
Since the conventional semiconductor memory device was structured as described above, it was necessary to form elements each having a minute length of 0.5 .mu.m or less in case the degree of integration of 16M bit or more is to be made.
However, referring to FIG. 4, there was a problem in which it is difficult to obtain enough an amount of storage electric charges because the electric charge storage region 15 serving as a storage capacity element has to be made small as the dimension of the each IC portion is made small.
USPTO Backgrounds
USPTO Backgrounds