1. Field of the Invention
The invention relates to the manufacture of semiconductor microelectronics fabrications. More particularly, the invention relates to a method for forming gate oxide insulation employed in field effect transistors within semiconductor integrated circuit microelectronics fabrications.
2. Description of the Related Art
Modern microelectronics technology is largely based on the ability to fabricate electronically functional devices of such small dimensions within semiconductor single crystal substrates that the density of electronic devices is approaching 10.sup.6 per square centimeter. This density has been achieved by constant improvements in the methods and materials employed within the microelectronics fabrication art, and by development of ever more simple and compact device designs and structure, Thus, the field effect transistor (FET) is about one order of magnitude smaller in may important aspects of its incorporation into a semiconductor integrated circuit microelectronics fabrication than a comparable bipolar transistor (BIP). It has become increasingly more desirable to employ such field effect transistor (FET) devices in the design of large arrays of electronic circuits to be implemented as semiconductor integrated circuit microelectronics fabrications. Although many forms of the FET device are known, the most widely employed embodiment is the semiconductor FET device fabricated within a silicon single crystal substrate. Such field effect transistor (FET) devices commonly employ a metallic or other conductive material as the gate electrode layer and a dielectric material such as silicon oxide as a gate insulating layer upon a semiconductor substrate, and are therefore commonly referred to as metal-oxide-semiconductor (MOS) devices.
A critical component of a field effect transistor is the gate insulation layer. This gate insulation layer comprises a thin dielectric layer across which an electrical potential between an adjacent gate electrode and a semiconductor channel formed between source and drain regions controls the density of electrical charge carriers in the semiconductor channel. Thus the potential difference or voltage on the gate electrode modulates the flow of current in the FET device between source and drain regions without the gate electrode itself conducting any electric current, since the gate dielectric layer blocks any such current form flowing. Thus the FET device operates with a high input impedance which can be readily switched from a conducting to a non-conducting state, which is an important characteristic in the functioning of microelectronics circuit applications.
In order for the FET device to operate efficiently, the gate insulation layer is desirable as thin as is practicable so that the electric field due to the voltage on the gate electrode can be high for small values of the applied gate voltage. From a different perspective, the gate insulation capacitance is desirably as high as practicable, so that the induced charge carrier density in the conduction channel adjacent to the gate insulation region is also high for a given applied voltage. This is equivalent to requiring as thin a gate insulation dielectric layer as is practicable, as before. Typically, the silicon oxide gate insulation in a silicon semiconductor FET device is of the order of 100-200 angstroms in thickness, with applied gate voltages of the order of 5 volts, so that the electric field within the silicon oxide gate oxide is about 2.5.times.10.sup.6 to about 5.times.10.sup.6 volts/centimeter. This electric filed is not far below the maximum electric field that a silicon oxide dielectric material can withstand without electrical breakdown.
The gate insulation for a silicon field effect transistor (FET) device is typically formed by thermal oxidation of silicon to form a silicon oxide dielectric layer, empolying methods and materials developed to produce within that silicon oxide dielectric layer a high quality dielectric material in terms of freedom from defects and uniformity of physical properties. It has been found that high purity oxygen to which certain other high purity gases have been added is the most satisfactory medium for the thermal oxidation of silicon to form useful silicon oxide gate insulation for FET devices within silicon semiconductor integrated circuit microelectronics fabrications, for example, additional gases including but not limited to halogen containing gases such as hydrogen chloride and trichloroethane and reducing gases such as hydrogen and water vapor have been reported to produce beneficial effects when added to pure oxygen to form the silicon oxide gate insulation by thermal oxidation.
Although the thermal oxidation of silicon in high purity oxygen with added gases to form the silicon oxide gate insulation is widely practiced, it is not without problems. The rate of formation of the silicon oxide and the microstructure of the silicon oxide layer are often less than optimum with respect to controlling the thickness and uniformity of the silicon oxide gate oxide layer, which leads to problems in the design, manufacture, yield, performance and reliability of the integrated circuit microelectronics fabrications employing the FET devices.
It is therefore towards the goal of forming within a silicon semiconductor substrate within a semiconductor integrated circuit microelectronics fabrication an improved silicon oxide gate oxide layer that the present invention is more specifically directed.
Various methods and materials have been disclosed within the are of semiconductor integrated circuit microelectronics fabrication to form the silicon oxide gate oxide insulation of silicon FET devices.
For example, Pong et al., in U.S. Pat. No. 5,210,056, disclose a method for forming silicon oxide gate oxide dielectric layers with improved resistance to electrical breakdown. The method employs annealing of a silicon substrate in nitrogen while increasing the temperature to a level where oxidation of the silicon will take place, and then changing the gaseous environment to a mixture of oxygen and hydrogen to form the silicon oxide in a "wet" oxidizing ambient, followed by a second annealing in nitrogen while first raising the substrate temperature further and then lowering it to the starting point. The method produces silicon oxide dielectric layers with improved resistance to electrical breakdown, presumably by reducing the incidence of defects such as micropores and excessively thin regions in the silicon oxide dielectric layer.
Further, Chau et al., in U.S. Pat. No. 5,244,843, disclose a method for forming silicon oxide dielectric layers suitable for use as gate oxide dielectric layers at thicknesses below 100 angstroms. The method employs a multiple oxidation of a silicon substrate, first in dry oxygen with added trichloroethane, which is then followed by oxidation in a "wet" environment of water vapor formed by pre-combustion ("torching") of oxygen and hydrogen to form the water vapor. Finally, an annealing or stabilization step and return to initial conditions is performed in a nitrogen environment. Thicker composite silicon oxide layers may be formed by depositing a first silicon oxide dielectric layer upon the silicon substrate followed by the method of the invention upon which a second silicon oxide layer is formed by a deposition method.
Finally, Yang et al., in U.S. Pat. No. 5,470,611, disclose a method for forming a composite silicon oxide dielectric layer fo ruse as a gate oxide dielectric layer in a MOS device. The method employs a first silicon oxide dielectric layer deposited by low pressure chemical vapor deposition (DVD) upon a silicon substrate followed by thermal oxidation in a wet environment produced by pre-combustion of oxygen and hydrogen to form a second silicon oxide dielectric layer intermediate between the substrate and the first silicon oxide dielectric layer.
Desirable in the art of microelectronics fabrication are additional methods and materials useful in forming improved gate oxide dielectric layers within substrates employed within microelectronics fabrications. More particularly desirable are methods for forming silicon oxide gate oxide dielectric layers with improved properties and better control of the formation process within silicon semiconductor substrates empolying thermal oxidation environments.
It is towards these foregoing goals that the present invention is generally and specifically directed.
USPTO Backgrounds
USPTO Backgrounds