In modern CMOS design, integrated circuit (ICs) are designed such that the product operates correctly under a range of operating conditions (e.g. voltage, temperature, wear) and despite some variations in process conditions. Traditional IC design approaches are typically based on the inclusion of margins to account for different process and operating conditions. In modern CMOS design, the most common technique for timing, power and area optimisation is corner-based. These design “corners” contain timing and power information of cells and macros under different process and operating conditions. To fulfil a minimum performance requirement, the IC design is optimised for operation under the worst-case combination of conditions: slow process, high temperature, large voltage drops, etc. This strategy results in a pessimistic design having a larger area and higher power consumption than would be would be the case if the IC were optimized for typical conditions, because the worst-case combination of conditions rarely occurs.
Ideally, the designer would like to design for the “typical” corner (that is, for typical process and operating conditions). However, that would result in timing violations if the IC does not correspond to a typical sample or is not operated under typical conditions.
Multiple techniques have been proposed for designing in less pessimistic corners and multiple techniques have been proposed for dealing with consequential timing violations in sequential elements that may occur with worst-case conditions.
FIG. 1 shows a classic five-stage MIPS processor, in which the various stages of the processor are separated from each other through pipelines (sequential elements such as flip-flops). In this case the pipeline stages are: PC, IF/ID, ID/EX, EX/MEM, and MEM/WB. When the processor of FIG. 1 is implemented, some performance requirements are pursued. For example, the processor may be required to run at 1 GHz. These performance requirements need to be fulfilled over a range of possible conditions. The conditions are summarised by so called “PVT corners” (process, voltage and temperature). To achieve the desired performance in every corner, the synthesis tools trade off performance against area. The slower the PVT corner, the greater the area used in the implementation of the processor.
Designing for the worst-case combination of conditions therefore requires extra area to provide margin for an unlikely combination of events. A set of techniques collectively known as better-than-worst-case design (BTWC) address this problem. BTWC design approaches enable power consumption to be reduced by optimising for better-than-worst-case operating conditions, or even for typical operating conditions, rather than worst-case conditions. In BTWC, the spread of the PVT corner is reduced. For example, if the process variability can be modelled as a Gaussian distribution having a variance of a, a worst-case design approach will assume that the process conditions range from −3σ to +3σ around typical conditions and the integrated circuit design will be optimised between these two boundaries. In contrast, BTWC will assume that the process conditions range from, for example, −2σ to +2σ. Assuming a lower process spread in this manner will reduce the IC area, but it will also reduce the number of samples of the product that achieve the desired performance. Multiple techniques have been proposed to regain yield, by addressing the timing violations which occur when the IC is operated under conditions outside of the range for which it has been designed.
USPTO Backgrounds
USPTO Backgrounds