Analog-to-digital converters are frequently used in applications which call for a delay of an analog electrical signal. For example, in a television frame synchronizer, which is used to bring the video portion of an input television signal into synchronism with a reference video signal, the input video signal is sampled at times related to the subcarrier burst of the input video signal and successive samples are converted into digital form and written into memory, and the digital signals are read out of memory and converted to analog form with timing controlled by the subcarrier burst of the reference signal. In addition, in order to achieve a desired degree of synchronism between the video and audio portions of the input signal, it may be necessary to delay the audio portion and this may be done by converting the audio portion to digital form and delaying the digital signal by a selected amount using a digital delay line prior to reconverting to analog form. Digital delay lines are particularly desirable for this purpose since they are inherently more accurate than analog delay lines.
Problems may arise, however, in controlling the conversion between analog form and digital form. For example, if the analog-to-digital converter (ADC) is of the successive approximation type, comprising a successive approximation register, a digital-to-analog converter (DAC) and a comparator, nonlinearity in the transfer function of the DAC will result in the digital signal provided to the digital delay line not representing accurately the analog input signal. Nonlinearity in the conversion into the higher order bits of the digital signal may result in it not being possible to represent certain analog input values, i.e. the transfer function of the DAC may be indeterminate for certain ranges of higher values of the analog input signal.
Another problem that arises with a conventional successive approximation DAC is that which is known as sample and hold droop. The successive approximation ADC has a sample and hold at its input to maintain the input signal to the comparator constant during operation of the ADC. The sample and hold utilizes a storage capacitor, but owing to leakage the charge on the capacitor, and consequently the voltage applied to the input of the comparator, falls. As would be expected, the voltage drops as a function of leakage current. If the signal provided by the sample and hold is digitized in successive bits, starting with the most significant bit (MSB), and the MSB conversion is effected before the output of the sample and hold has settled, and the amplitude of the drift is greater than the resolution of the higher order DAC, the digital output signal provided by the higher order DAC will be incorrect (it will not represent the settled output of the sample and hold) and the output provided by the lower order DAC will not normally have any meaning.
USPTO Backgrounds
USPTO Backgrounds