The present invention relates to semiconductor processing, and more particularly to a method for filling isolation trenches during semiconductor processing.
During the fabrication of semiconductor devices, isolation trenches are provided between active areas where transistors will be located. The trenches extend into a silicon substrate and are filled with an insulating material, such as oxide, to form lines of oxide insulating regions. As the aspect-ratio for the isolation trench structure increases, it becomes increasingly more difficult to fill the trench without forming voids in the oxide near the center of the trench. The consistency of void-free gap fill has a significant effect on the subsequent integration process steps and on final device yield and performance.
Current techniques for gap filling the isolation trenches utilize a high density plasma (xe2x80x9cHDPxe2x80x9d) deposition technique to produce a high-quality oxide filler. With HDP processing, high-aspect-ratio sub-half micron structures can be filled and locally planarized in a single processing step. Generally, ions and electrons from the plasma are generated at an electrode by means of an RF biasing power, and an RF power source is applied to another electrode (located at a holder for a wafer) to create a significant ion bombardment (sputter-etching) component during deposition. Thus, gap filling using HDP is a simultaneous deposition/etching process. This process allows trench isolation structures with high-aspect-ratios to be filled with high-quality oxide dielectric.
While HDP deposition of the oxide has been found to produce a high-quality void-free gap fill, it has been observed that deposition of the oxide is not uniform and, in some circumstances, completely lacking in some portions of the isolation trench line. This observed defect is illustrated in FIGS. 1A, 1B and 1C. FIG. 1A illustrates a view looking down onto the substrate surface 10. One of a plurality of isolation trench lines 24a is illustrated after the HDP oxide 30 has been deposited and polished back. The defect 40 is an unfilled area of the isolation trench 24a. FIGS. 1B and 1C illustrate cross-sectional views of the defect 40 at Axe2x80x94A, and Bxe2x80x94B, respectively. As is shown in FIGS. 1B and 1C, the unfilled pockets occur at the isolation trench surface 50 (FIG. 1B) and can grow to encompass the entire isolation trench 24a (FIG. 1C). This defect 40 can significantly effect final device yield and performance.
Accordingly what is needed is an improved isolation trench fill process that produces a defect-free insulating layer. The present invention addresses such a need.
The present invention provides a method for filling an isolation trench structure during a semiconductor fabrication process. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of approximately 200 Angstroms.
According to the method disclosed herein, depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of bubbles at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.
USPTO Backgrounds
USPTO Backgrounds