1. Field of the Invention
This invention relates to semiconductor devices and, in particular, to dielectrically isolated semiconductor devices.
2. Art Background
In most electronic components, such as integrated circuits, electrical isolation is produced between regions of essentially single crystal silicon by junction isolation. (Single crystal silicon is silicon having defects, e.g., linear and planar defects such as dislocations or stacking faults, respectively, in a density through the crystal of less than 10.sup.8 defects per cm.sup.+2.) In this junction approach, lateral isolation is accomplished by interposing between the active single crystal silicon regions, a region of opposite electrical type from that of the active region. The thickness of this added region is approximately equal to the depth of the active regions of the single crystal materials being separated. Similarly, vertical isolation in the junction approach is obtained by the presence of material of opposite conductivity type positioned below the active region. (The active region is that portion of the single crystal silicon which is ultimately to be modified to contain electronic device structures. The active region is typically 1 .mu.m thick for nominal voltage devices.) Such rectifying junctions formed at the boundaries of the active regions of opposite type provide lateral and vertical isolation when appropriately biased. For some applications lateral junction isolation is replaced with lateral dielectric isolation to save space and to reduce capacitance. (Lateral dielectric isolation entails the presence of an insulator, such as silicon dioxide or air, rather than a material of opposite conductivity type at the lateral boundaries of the active region.) By expedients such as junction isolation or lateral dielectric isolation, transistors or other devices formed in one single crystal region, i.e., one active region, are electrically isolated and are prevented from interacting with devices in a second active region.
However, for some significant applications, the use of junction isolation or a combination of junction and lateral dielectric isolation is not sufficient. For example, in some instances, the voltage employed in operation is often large enough to cause electrical breakdown between separate active regions. This electrical breakdown occurs through many paths such as by the penetration of charge carriers below one active region through the underlying substrate, across the substrate under the lateral isolation region, and into the second active region. When a typical junction isolation structure is employed, the voltages encountered in some applications, such as telephone line interface circuits, are sufficient to cause breakdown by charge carrier penetration through the isolation regions. To prevent such undesirable electrical interaction between two active regions, a combination of lateral and vertical dielectric isolation is employed. This dielectric isolation is provided by surrounding the single crystal silicon regions with an electrically insulating dielectric material. By this expedient, interaction between active regions even at high voltages is avoided. Although it is possible in theory to increase the insulating capability of junction isolation to prevent breakdown in high-voltage devices, a high-voltage application requires a correspondingly high resistivity in the junction isolation region. Since the size of the depletion region increases with both voltage and resistivity, enhanced breakdown characteristics require, for junction isolation, an extremely large volume devoted to isolation. By employing dielectric isolation, equivalent isolation is obtainable in a much smaller volume which, in turn, greatly reduces electronic component area and cost.
Dielectric isolation is also advantageously used in devices operating at nominal voltages where enhanced reliability and performance are desirable. The additional insulating material that provides the vertical dielectric isolation also prevents electron-hole pairs formed in the underlying substrate by thermal processes or by ionizing radiation from migrating to an active region and, thus, introducing errors in the processing of information by the electronic devices in this region. Moreover, dielectric isolation introduces significantly less capacitance than does junction isolation for comparable device feature dimensions. Lower capacitance, in turn, allows higher operating speed with less power dissipation--a result which is quite desirable especially in low-voltage logic circuitry.
Additionally, for some significant device applications junction isolation is not adequate under any circumstances. A reverse biased junction, as used in junction isolation, blocks the flow of only majority carriers (i.e., electrons in n-type semiconductor materials and holes in p-type) and collects minority carriers. For some bipolar devices it is necessary that the isolation region block the flow of both carrier types. Thus, such devices require dielectric isolation.
A variety of processes have been employed to produce semiconductor components having dielectric isolation. The majority of these processes have been directed to producing a thin, i.e., less than 3 microns, dielectrically isolated active region. In a number of these processes directed to producing thin active regions, a precursor structure is fabricated by first forming patterned regions of dielectric material, e.g., silicon oxide, on a single crystal silicon substrate. Silicon is deposited onto this structure which results in non-single crystal material, e.g., amorphous or polycrystalline silicon, overlying the dielectric regions and contacting the substrate portions exposed between these regions. The non-single crystal silicon is then treated to cause growth of single crystal silicon at the non-single crystal silicon/substrate interface and to propagate this single crystal through the non-single crystal silicon region. This propagation is done by melting a discrete zone containing both the single crystalline and non-single crystal material and then propagating this discrete zone through the non-single crystal region in a manner akin to a zone refining process.
One of the few and the most established method for producing a thick, i.e., 3 .mu.m or thicker, dielectrically isolated active region has been described by K. E. Bean and W. R. Runyan, in the Journal of the Electrochemical Society, 124, 50 (1977). This process, possibly because of the desire to produce thick, dielectrically isolated single crystal silicon, does not involve a melting procedure which propagates a nucleated crystal through the polycrystalline region by translating a discrete molten zone. Instead, an elaborate series of deposition and etching steps, as shown in FIG. 1, is utilized. Briefly, the steps involve the treatment of a high-quality single crystal substrate. This silicon substrate, 1A in FIG. 1, is coated with a suitable masking material, such as silicon dioxide, 3, and holes, 5, are formed in the oxide by conventional techniques, e.g., photolithography and oxide etching. Grooves, 7, are then anisotropically etched in the exposed portions of the silicon underlying the holes in the dielectric material. The masking oxide is removed and the entire surface is epitaxially coated with an optional layer of N.sup.+ silicon, 8. The N.sup.+ silicon is, in turn, coated with an insulator, 9, such as silicon dioxide. The insulator is once again, in turn, coated with a layer of polysilicon, 10. The structure is then inverted and the silicon substrate is ground off and polished until the structure shown at 1G is obtained. In this structure, the remaining single crystal silicon is denoted by 12 and 15, the insulating layer is indicated by 14, and polysilicon is indicated by 16. Thus, the final structure has single crystal silicon, 12 and 15, on an electrically insulating material.
As can be appreciated from the previous description and from FIG. 1, dielectric isolation of thick silicon active regions involves a multitude of complicated processing steps. Additionally, the extensive processing employed introduces high levels of defects into the single crystal active regions and results in low yields of useful devices. For example, as the silicon oxide layer, 9, is grown, an extreme amount of compressive stress develops at the apex area, 17, of the silicon oxide layer, 9. This stress exerts a concomitant force on the adjacent single crystal silicon, 12, which results in extensive defect formation. This defect formation is further aggravated by stresses induced by the polysilicon during subsequent thermal processing with a concomitant loss in yield. Thus, components involving thick, dielectrically isolated regions of silicon have only been used for applications which require production of devices where properties are critical and expense is a secondary factor.
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