(1) Field of the Invention
The invention relates to a ring oscillator circuit in an integrated circuit device, and, more particularly, to a ring oscillator circuit with variable capacitance loading on internal nodes.
(2) Description of the Prior Art
Hot carrier injection is one of the major reliability wearout mechanisms in VLSI circuits. Currently, hot carrier robustness of a CMOS process is evaluated by stressing individual devices at high stress voltages and measuring the degradation of device parameters, such as drain current, over time. The cumulative degradation is then used to extrapolate device lifetimes, defined as a certain percentage degradation, based on the operating voltage. For example, the power supply may vary between the nominal VDD level and about 1.1 times the nominal VDD level.
As technologies are scaled down to the submicron range, the hot carrier effect increases dramatically. As a result, the degradation effects are more pronounced. As a further result, the above-described method, called static HCI testing, for estimating device lifetimes has become less meaningful and less realistic. The loss of correlation between testing and actual reliability is because the static test does not adequately take into account the amount of time that the hot carrier injection (HCI) effect occurs in a real circuit. For example, in a digital circuit that is synchronized with a clock, HCI may only occur during a small percentage of time during each clock cycle. Therefore, a static HCI test may over estimate the cumulative HCI effect. As a result, dynamic HCI test methods have been developed.
Referring now to FIG. 1, a ring oscillator circuit 10 is shown. The ring oscillator 10 comprises several inverting stages U114, I118, I222, I330, and I426 that are coupled together in a feedback ring. In this example, five stages are used in the ring. In practice, however, any odd number of stages can be used. Since an odd number of inverting stages, including the NAND gate U114, are used, the ring will oscillate whenever the enable signal ENABLE 52 is high. The frequency of oscillation, which is typically very high, will depend on the number of inverting stages in the ring and on the loading at each stage of the ring. Loading inverters IA 38, IB 42, IC 48, and ID 44 are included to simulate loads in a working circuit.
This ring oscillator circuit 10 can be used on an integrated circuit wafer as a dynamic HCI test structure. For example, the wafer may include an integrated circuit that is designed with transistors of the same length as the transistors in the ring oscillator circuit 10. The ring oscillator circuit 10 can then serve as a test vehicle to simulate HCI effects that the will occur in the product design. To test HCI, the circuit supply VDD_RO and the buffer VDD VDD_BUFFER are powered at a stressing voltage, such as 1.1 VDD, while GND 68 is grounded. ENABLE 52 is then forced high to allow the circuit to oscillate at a very high frequency. The output buffer I534 provides an additional loading and also drives the oscillation signal off-chip.
As the circuit 10 operates under the stressing voltage VDD_RO 60, any HCI effects will cause degradation of the transistor drain currents and the frequency of ring oscillator as a result. An accurate extrapolation compared to static HCI stress of operating lifetime is possible since the HCI effect is simulated under dynamic switching conditions. Changes in the oscillation frequency at the OUTPUT 56 can provide a measure of HCI-induced damaged.
A problem with this prior art ring oscillator 10 is that the loading on the circuit nodes A 16, B 20, C 24, and D 28 is a fixed value based on the transistor sizes in the load inverters IA 38, IB 42, IC 48, and ID 44. However, in the product design, a range of output loading is used. For example, in the product design, a first inverting stage may drive only a second inverting stage while the second inverting stage drives four inverting stages. In this case, the load on the second inverting stage is four times greater than the load on the first inverting stage. This situation is called fan-out. Fan-out can effect HCI degradation. Therefore, it is important to measure HCI over a range of fan-out conditions. However, since fixed inverter loads are used, it is not possible to study fan-out effects on HCI using a single ring oscillator circuit. To study the effect of fan-out on HCI degradation over the range of 1 to 5, five unique ring oscillator circuits would have to be designed and each circuit would require five pads as shown in FIG. 1. Therefore, such a study requires five circuits and 25 pads. Such an approach is very expensive in terms of test chip wafer area.
Several prior art inventions relate to ring oscillator structures. U.S. Pat. No. 6,476,632 B1 to LaRossa et al teaches a ring oscillator structure for use in on-chip reliability testing. A prior art circuit shows an inverter-based, ring oscillator having load capacitors at each stage. The preferred embodiment of the invention includes a plurality of pass gates to provide access to the internal nodes of the circuit. U.S. Pat. No. 5,625,288 to Snyder et al discloses ring oscillator circuits for generating high frequency signals for further use in high frequency stressing of on-chip devices. The ring oscillators are controlled by a DC current or a DC voltage. The voltage control is applied to the gate of the NMOS devices in the first and second inverters. U.S. Pat. No. 6,320,474 B1 to Kamiya et al describes a MOS variable capacitor that is used in a voltage controlled oscillator for driving a resonator or a crystal.
USPTO Backgrounds
USPTO Backgrounds