1. Field of the Invention
The present invention relates to a method and apparatus for testing electrical circuit units having a plurality of terminals or pins on a tester that lacks the number of necessary channels to connect one circuit pin to one tester channel. More particularly, this invention relates to the utilization of a tester in which the terminals of an integrated circuit unit under test exceeds by a substantial margin the number of testing lines that the tester has available to make a connection.
2. Description of the Prior Art
Reference is made to the following prior art patents.
U.S. Pat. No. 3,787,670 entitled "Automatic Diagnostic System" granted Jan. 22, 1974 to Paul E. Nelson et al. The ABSTRACT of the Nelson et al patent reads as follows:
"In a computer having a peripheral device and a central processor including a memory and an arithmetic unit, an anticipatory diagnositc system including a plurality of monitor units for observing operation of a peripheral device, gating means for selecting the monitor unit whose output is to be interrogated, means responsive to the gating means for quantizing the output of the selected monitor unit and means for storing the quantized output for redelivery to the central processor upon a subsequent command." PA1 "The multiplexer control system for a multi-array test probe assembly for controlling the simultaneous interface contact of the probe arrays with a plurality of electronic devices and the successive interconnection of said arrays with electronic test equipment." PA1 "The present invention pertains to multiplex apparatus for an automatic computerized diagnostic testing system for selectively interconnecting peripheral measurement and stimulus devices to a unit under test (UUT) through various switching subsystems which differ in switching capability, load carrying ability, frequency bandwidth, and mode of operation. The multiplexer includes plural conducting means between each pin of the circuit under test and corresponding terminals or test points of plural switching sub-systems used to interconnect UUT pins and the peripheral testing devices. Each plural conducting means includes controllable switch means. These switch means operate automatically under programmed computer control. One of the switching subsystems has high frequency signal carrying ability, and the conducting means associated with this subsystem preferably include impedance matching buffers, and have a frequency bandwidth equal to that of the subsystem." PA1 "Multiconductor cable testing apparatus for sequentially testing the conductors of an electric cable for open-circuit, short-circuit and for incorrect connection, the results of the tests being visually displayed so that the actual fault and the conductor or conductors involved can be easily determined." PA1 "The following specification discloses a current noise and dielectric absorption kickback compensation circuit for a force line and a sense line that are to be initially compensated with regard to unwanted currents therein. The lines are placed in a shielded cable and mutually receive the same external noise signals. The unwanted currents are incurred in the force line and the sense line which is connected to a device under test, such as an integrated circuit, that is to have a particular voltage forced thereon and a determination made or sensed as to the current drain thereof. The force and sense lines can be initially connected to a tester which is controlled by a computer. The lines lead to the device under test through various lines interconnected by relay matrices which provide a number of different functions for testing the device under test, such as timed events, voltages, and external active or passive elements used cooperatively with the device under test and the other pins thereof. The invention compensates for spurious signals which are mutually incurred on the force and sense lines through dielectric absorption kickback and noise generated thereon, such as sixty cycle ambient noise. The compensation is effectuated by the sense line being clear of any driven signals thereon. This allows the provision of any spurious currents thereon to an amplifier having a zero reference point. The foregoing amplifier of the sense line has its output connected to an inverted reference to the input of a force line amplifier. This places the spurious respective currents on the force and sense lines in diametrically opposed equal values for purposes of providing a null on the two respective lines, inasmuch as they both receive the same approximate dielectric and noise factors. The nulling effect compensates for noise, and dielectric absorption kickback that is caused by the switching matrices and the ambient noise, so that a true current reading on the force line can take place as to any current thereon that relates to the device under test." PA1 "For servicing digital logic circuits, a hand-held monitor can be connected to an indefinite number of different sets of test points. Numerical and binary displays indicate the current state of the selected test points. To help the user understand what is being monitored, removable cards can be mounted adjacent the displays. Each of the cards has printed information relating to a different set of test points. An operator-controlled auxiliary clock is included to permit the operator to step the circuit being monitored through its operating sequence." PA1 "Logic and analog functions in a complex semiconductor component are stuck fault and parametrically tested through an analog/digital measurement adapter coupled to logic and analog testers. Both logic and analog testers are under computer control whose purpose is to direct the testing sequence, log test results, perform algorithmic calculations on the data and diagnose failing devices in te component under test. The adapter provides the electrical environment to match a range of components under test to the logic and analog testers. The adapter is also under computer control to permit impedance matching of a multiplicity of digitally controlled stimulus/response units connected through a multiplexer to the range of components under test." PA1 "A system is described for testing electrical circuit units, particularly printed circuit cards having a plurality of plug-in connector terminals. PA1 The testing system is first operated in the Generation Mode wherein it generates a reference test pattern produced from a series of test stimuli applied sequentially to a reference card, and stores the pattern in a bulk memory, the pattern being in the form of a series of words identified by the part number of the respective card and containing the test stimuli and the responses thereto from the reference card. To test a production card, the system is operated in the Test Mode, wherein the stored test pattern generated from the corresponding reference card is extracted from the bulk memory and the reference responses are compared in a GO, NO-GO testing operation with the actual responses produced when applying the same test stimuli to the production card. PA1 The system includes a pair of flip-flops for each pin of the tested card, one flip-flop being connected to a circuit which reflects the actual response of the pin to the test stimulus during the Test Mode, and the other flip-flop being connected to a circuit which reflects the reference response to the test stimulus as determined during the Generation Mode. The flip-flop pairs are disposed in a plurality of matrix cards each accommodating all the flip-flops of a group of pins (e.g. eight matrix cards each containing the flip-flop pairs for 25 pins, when testing a 200-pin card), providing a flexible modular arrangement easily enlargeable or alterable for testing other cards." PA1 "An apparatus for testing circuit board systems utilizing microprocessors which includes means for selectively exericizing each terminal or pin of the board system during each step of the testing protocol. Each step of the protocol can be preselected to operate according to an automatic sequence or according to a preprogrammed manner, or the apparatus may be conditioned to receive a response from the circuit board system at a selected terminal during a selected step of the testing protocol. The testing apparatus further includes an interactive interface to permit the board system under test to control the speed and sequence of the test procedure. The testing apparatus is capable of exericising the board systems under test in a simulated environment at typically normal operating speeds so that degradation of system performance related to operational speed and other factors found in an operating environment can be analyzed."
U.S. Pat. No. 3,848,188 entitled "Multiplexor Control System For A Multi-Array Test Probe Assembly" granted Nov. 12, 1974 to Frank J. Ardezzone et al. The ABSTRACT of the Nelson Ardezzone et al patent reads as follows:
U.S. Pat. No. 3,922,537, entitled "Multiplex Device For Automatic Test Equipment" granted Nov. 25, 1975 to Phillip C. Jackson. The ABSTRACT of the Jackson patent reads as follows:
U.S. Pat. No. 4,015,200, entitled "Multiconductor Cable Testing Apparatus" granted Mar. 29, 1977 to M. T. Strandh. The ABSTRACT of the Strandh patent reads as follows:
U.S. Pat. No. 4,023,097 entitled "Noise and Dielectric Absorption Compensation Circuit" granted May 10, 1977 to Richard E. Hanashey. The ABSTRACT of the Hanashey patent reads as follows:
U.S. Pat. No. 4,034,287 entitled "General Purpose Digital Logic Monitor" granted July 5, 1977 to Flavio M. Manduley. The ABSTRACT of the Manduley patent reads as follows:
U.S. Pat. No. 4,044,244 entitled "Automatic Tester for Complex Semiconductor Components Including Combinations of Logic, Memory and Analog Devices and Processes of Testing Thereof" granted Aug. 23, 1977 to Steven H. Foreman et al. The ABSTRACT of the Foreman et al patent reads as follows:
U.S. Pat. No. 4,097,797 entitled "Apparatus For Testing Electrical Circuit Units Such As Printed Circuit Cards" granted June 27, 1978 to Michel Finet. The ABSTRACT of the Finet patent reads as follows:
U.S. Pat. No. 4,125,763 entitled "Automatic Tester for Microprocessor Board" granted Nov. 14, 1978 to Richard B. Drabing et al. The ABSTRACT of the Drabing et al patent reads as follows:
The practice of testing integrated circuit components is of prime importance to the electronic device manufacturers so as to weed out defective units before they are assembled and used. It is desirable to test semiconductor devices while they are still part of a wafer so as to discover unsatisfactory components prior to being mounted on the next level of packaging. Similarly, it is also desirable to test further these integrated circuit units after that they have been assembled on modules, cards or boards. Only by means of repetitive testing can the quality assurance of the devices be safeguarded. This continuous testing at each level of packaging imposes demands on the electronic industry to design and provide equipment that is capable of performing these tests in an automatic mode, at high speeds and with precise accuracy.
The trend of the electronic industry developments is to further increase the degree of miniaturization of electronic devices. This implies decreasing the area of each circuit which, in turn, allows for an increase in the density of circuits. A higher circuit count permits more logic functions to be performed by the integrated unit. This trend towards miniaturization is also accompanied by a corresponding increase in the number of terminal pins. This is necessary to maintain adequate communication between the circuitry of the unit and the remainder of the assembly or machine which it is part of.
As integrated circuits become more sophisticated, the complexity of the supporting test equipment must increase correspondingly. This signifies that the number of tests that must be performed to locate all the faults increases rapidly. For example, on a simple integrated circuit of no more than a dozen circuits, at most, several tens of tests are sufficient to locate all possible failures. In today's integrated circuits, with its hundreds and soon thousands of circuits, the number of tests required is in the order of many tens of thousands to achieve the same result. Not only the software requirements to generate such test patterns are difficult but the time needed to apply them is inordinately long. A direct consequence of this trend toward miniaturization is that the test equipment must be able to process a large number of patterns at high speed. Such electronic tester is usually controlled by a computer. The tester generates a signal that is provided to the integrated circuit or assembly, hereinafter referred to interchangeably as a unit under test (UUT). This signal which is in the form of a forced voltage or current is supplied to the appropriate input terminal pin by an electronic network called "digital-to-analog converter" or "D/A converter", in short. This, and other pertinent circuitry forms a "tester channel". As the name states it, it converts a "logic binary level" into an electrical analog level which is applied to a single input terminal of the unit under test (UUT). In a similar fashion, the actual electrical response at the output pins of the UUT is compared to a standard acceptable response by the computer. These responses are dictated by the test patterns. For example, if the expected binary level at one output pin of the UUT is a "logic 1", the tester, by use of the channel connected to that output pin, will measure the voltage or current level. A nonconcurrence between the measured and expected levels indicates the presence of a failure inside of the integrated circuit, and the unit is discarded as defective.
Today, a one to one correspondence between each tester channel and a terminal pin of a UUT always exists. By presetting each tester channel to a defined level, it is possible to assign a voltage or current level appropriate to each terminal connection. The prior art, however, has not solved the problem when the tester falls behind the advances in the complexity of the semiconductor technology and when an inadequate number of tester channels are present to service the totality of terminal pins of the UUT.
In effect, this invention provides an advance over the prior art by enabling a tester with less channels than those required by the integrated circuit package to actually test this package as if an adequate number of channels were available. In particular, this invention is useful to test large scale integrated packages that represent the latest advances in technology with existing test equipment whose architecture and characteristics have not fully matched the advances in semiconductor technology packages.
USPTO Backgrounds
USPTO Backgrounds