1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more specifically, to a semiconductor integrated circuit device having a test function of evaluating operation delay time (access time) of a memory core contained therein, and to an access time evaluating method.
2. Description of the Background Art
In a semiconductor integrated circuit device such as represented by a microprocessor, data I/O width (number of parallel bits) has been extended, memory capacitor has been increased and operation frequency has been increased, in order to achieve higher performance.
Typically, a DRAM/logic mixed memory having a logic portion and a DRAM (Dynamic Random Access Memory) as a memory core mounted together on one same chip has been developed in order to realize wide data I/O width, to cope with those applications that require especially wide memory band width such as image processing. In the DRAM/logic mixed memory, an I/O pin and an external bus, which existed between a conventional processor and the DRAM are omitted, enabling a configuration capable of data transfer with high degree of freedom, and a number of data I/O lines capable of simultaneous data input/output to and from DRAM array portion are provided, realizing wide data I/O width.
For accurate operation of such a semiconductor integrated circuit device, it is necessary to accurately evaluate operation delay (access time) of the memory core. Here, as the data I/O width has been increased and the memory comes to have larger capacity, there arises the problem of increased circuit area and the increased test time necessary for testing the memory core.
As a solution to this problem, a technique of evaluating the access time of the memory core in a short period of time by a small scale test circuit is disclosed, for example, in Japanese Patent Laying-Open No. 10-21700. In the following, the technique disclosed in this laid-open application will be simply referred to as the prior art technique.
FIG. 30 is a block diagram representing a configuration of a first test circuit in accordance with the prior art technique.
Referring to FIG. 30, the first test circuit in accordance with the prior art technique includes a test target macro M1 that corresponds to the memory core, a selector M2 and a latch circuit M3.
The test target macro M1 starts a reading operation at a timing in response to a clock signal CLK, and provides read data DO1 to DOn. Selector M2 receives the read data DO1 to DOn from test target macro M1, and outputs one read data corresponding to a select signal SEL to latch circuit M3. Latch circuit M3 latches, in response to an activation timing of a test clock signal TCK, an output from selector M2, and provides this as a test output signal TDO.
In the first test circuit in accordance with the prior art technique, timing difference from an activation timing of dock signal CLK until an activation timing of test clock signal TCK is changed while monitoring the corresponding test output signal TDO, whereby the access time of the test target macro M1 can be evaluated.
More specifically, when the timing difference is smaller than the access time of the test target macro M1, it means that at a timing when latch circuit M3 latches the read data selected by selector M2, a correct read data has not yet been transmitted, and therefore the read data cannot be output as the test output signal TDO. When the timing difference is equal or longer than the access time of test target macro M1, latch circuit M3 provides the correct read data as the test output signal TDO.
In the configuration of the first test circuit in accordance with the prior art technique shown in FIG. 30, the influence of internally generated propagation delay of clock signal CLK and test clock signal TCK is not considered.
Therefore, when the access time is evaluated based on the activation timing difference at the time of generation of the clock signal CLK and the test clock signal TCK, a time difference between a first signal delay of the clock signal CLK from external input until reception by the test target macro M1 and a second signal delay of the test clock signal TCK from external input until reception by the latch circuit M3 may possibly affect the evaluation of the access time as an error. When the data I/O width is wide, circuit scale of selector M2 will be formidable.
Particularly, current trend is to make severe an operation specification of the memory core that corresponds to the test target macro, and therefore desired specification value of the access time comes to be smaller. When the required access time becomes shorter, the influence of the error resulting from the time difference between the first and second signal delays mentioned above becomes more significant.
FIG. 31 is a block diagram representing a configuration of a second test circuit in accordance with the prior art technique.
Referring to FIG. 31, the second test circuit in accordance with the prior art technique differs from the test circuit shown in FIG. 30 in that a multi-input logic gate M4 is additionally provided. The multi-input logic gate M4 receives read data DO1 to DOn from test target macro M1, and outputs a result of logical operation of the read data. Accordingly, the read data having the longest delay time is output, in an equivalent manner, from multi-input logic gate M4, and therefore, the area of selector M2 can be reduced. Further, as evaluation of the access time for each read data becomes unnecessary, the time for evaluating the access time can be reduced.
If the second test circuit is to be applied to the logic/DRAM mixed memory as described above, however, the circuit scale of the multi-input logic gate M4 would be very large, corresponding to the wide data I/O width. Further, the read data for evaluating the access time is transmitted to latch circuit M3 after the additional process time by multi-input logic gate M4, and therefore, an error factor is newly added in addition to the delay difference between the first and second signals described above. Therefore, highly accurate evaluation meeting the more severe access time requirement is difficult.
It is possible to evaluate the access time of the memory core by integrally operating the logic portion and the memory core in the case of the logic/DRAM (memory core) mixed memory. More specifically, a test mode is set in that the logic portion operates in response to an output from the DRAM (memory core), and the frequency of an external clock signal applied to the logic/DRAM mixed memory. Evaluation can be done by monitoring whether the logic portion operates normally or not.
By this method, however, it is necessary to increase the frequency of the external clock signal to execute highly accurate measurement of the access time, and therefore, there is a problem that the access time of the memory core cannot be evaluated unless a relatively expensive high speed tester is used.
An object of the present invention is to provide a semiconductor integrated circuit device capable of accurately evaluating an access time of a memory core contained therein, and to provide an access time evaluating method.
In summary, the present invention provides a semiconductor integrated circuit device including a memory circuit, a first signal transmitting path, a first data latch circuit and a second signal transmitting path.
The memory circuit executes a reading operation in which a plurality of data are output in parallel. One of the plurality of data is transmitted to an internal node. The first signal transmitting path transmits a control signal for instructing start of the reading operation to the memory circuit. The first data latch circuit takes in and holds a signal level of the internal node in response to a test timing signal that is activated after a prescribed time period from the activation of the control signal. The second signal transmitting path transmits the test timing signal to the first data latch circuit. A signal delay circuit is provided at least in one of the first and second signal transmitting paths, so as to make equal the signal propagation delay through the first and second signal transmitting paths.
According to another aspect, the present invention provides an access time evaluating method for a memory circuit contained in a semiconductor integrated circuit device, including the steps of: activating a control signal for instructing start of a reading operation in which a plurality of data are output in parallel, to the memory circuit; transmitting the activated control signal to the memory circuit; after a prescribed time period from the activation of the control signal, activating a test timing signal in response to a signal activated independent from the control signals; transmitting the activated test timing to a latch circuit; responsive to activation of the transmitted test timing signal, taking and holding in a latch circuit, at least one of the plurality of data output from the memory circuit; and further delaying at least one of the control signal and the test timing signal, and transmitting the delayed one to at least corresponding one of the memory circuit and the latch circuit.
According to a still another aspect, the present invention provides a semiconductor integrated circuit device including a memory circuit, a signal transmitting path, a delay circuit, and a data latch circuit. The memory circuit executes a reading operation in which a plurality of data are output in parallel. The signal transmitting path transmits a control signal for instructing start of a reading operation to the memory circuit. The delay circuit receives the control signal from the signal transmitting path, and generates an internal timing signal by delaying the control signal. The data latch circuit takes and holds at least one of the plurality of data in response to the internal test timing signal.
According to a still further aspect, the present invention provides an access time evaluating method of a memory circuit contained in a semiconductor integrated circuit device, including the steps of: activating a control signal for instructing start of reading to the memory circuit; transmitting the activated control signal to the memory circuit; delaying the control signal by a prescribed time period to generate a test timing signal; and taking and holding at least one of the read data from the memory circuit, in response to the activation of the test timing signal.
Therefore, a main advantage of the present invention is that the signal delay experienced by the control signal can be made equal to the signal delay experienced by the test timing signal by the signal delay circuit, whereby the access time of the memory circuit contained in the device can be evaluated accurately.
Further, it is possible to accurately evaluate the access time of the contained memory circuit, without the necessity of inputting an external signal instructing a latch timing of the read data.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds