1. Field of the Invention
The present invention relates generally to systems, methodologies and techniques for improving designs for manufacturability of semiconductors, and more particularly relates to systems, methodologies and technologies for automatically identifying and eliminating high risk configurations of shapes within a semiconductor layout.
2. Description of the Related Art
Traditionally, semiconductor design for even modestly complex semiconductors has involved the use of a series of masks, layered one on top of the other, to represent the completed design, where each mask represents a processing step. The impact of even small errors in the design (such as those errors on the order of nanometers) of a single mask can propagate to the complete failure of an entire design. It has therefore become important that the design of individual masks be optimized against such errors even before fabrication of the semiconductor begins.
To avoid such costly errors, a semiconductor manufacturer typically implements a fairly complex series of design rules. Design rules help the manufacturer to minimize the design errors of individual masks. Historically, these design rules were developed from empirical data. Over time, specific tools have been developed to establish and implement the various design rules, and to verify the resulting designs.
While numerous approaches have been tried for such design rules, these prior approaches have met with only limited success. Some approaches, while relatively thorough, are time-intensive and labor-intensive, and thus costly, and cannot readily be automated. Other approaches involve limited rule-based analyses which, while capable of being automated, have relatively narrow application and do not give universally reliable results.
Other typical approaches process layouts using a shape-based system, as contrasted to an image-based system, where a shape is defined by a set of associated edges in a specified configuration, for instance, as described in “General purpose shape-based layout processing scheme for IC layout modifications” invented by Agrawal et al. (U.S. Pat. No. 6,523,162 B1, granted on Feb. 18, 2003). This configuration of edges is often described as a set of one-dimensional descriptions that, taken together, might describe a two-dimensional configuration.
Thus, there exists a need for techniques to improve semiconductor design mask manufacturability that are easily implemented, offer relatively broad applicability, and include the capability of automatic operation.
USPTO Backgrounds
USPTO Backgrounds