1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to floating point multipliers for use within data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems with the ability to manipulate floating point numbers. The hardware mechanisms for providing floating point multiplication typically use the multiplier and multiplicand to generate numerous partial products. Various forms of carry-save adders are then used to reduce the partial products to two partial products. These final two partial products are then added before being rounded to produce the final product result.
A problem with the above is how to deal with subnormal results. Subnormal results are where the exponent value has the minimum permitted value and the significand is less than one, e.g. 0.001101. The nature of subnormal numbers is familiar to those in this technical field. One way of dealing with subnormal numbers is to treat them as exceptions and handle their processing in software. This is a low performance solution. If subnormal numbers are to be handled in hardware, then a problem is that the output of the adder from the two partial products is unlikely to be properly aligned for rounding. This requires that adder output is shifted and then rounded using a further adder. The shifting and the further adder for the rounding introduces undesirable additional hardware and delay.
USPTO Backgrounds
USPTO Backgrounds