In computer systems it is important to minimize the time necessary for processors to access data. Main memory is typically slow and located many machine cycles away from the processors. To solve this problem, computer systems generally utilize a memory hierarchy in which smaller and faster memories are located close to processors. Cache memories are smaller, faster memories that contain a copy of main memory data used more often by the processors. Data in a cache memory is stored in memory blocks that contain both the data and a tag that identifies the data. If the desired data is not located in cache memory, a cache miss occurs and the data must be fetched from main memory. If the fetched data can only be written into one memory block in the cache, the cache is said to be direct mapped. To reduce the miss rate, cache memories are sometimes associative so that a memory block can be written anywhere in the physical cache memory. As the cache size and the amount of associativity increases, the amount of circuitry necessary to manage the data in the cache increases. A compromise between a direct mapped cache and a fully associative cache is a set associative cache. In a set associative cache data may be written into more than one of the available memory blocks, but not into all available memory blocks. It is important to choose the algorithm used to replace memory blocks within the cache such that the cache miss rate is low yet the amount of cache management circuitry does not become too expensive in terms of development time and, ultimately, silicon area. What is needed is a system and method that uses an efficient cache replacement algorithm that has a low miss rate, and in general uses a low amount of circuitry to implement the algorithm.
USPTO Backgrounds
USPTO Backgrounds