The present invention relates to a process for fabricating an integrated circuit device including wiring layers and contacts formed of copper.
Recently higher integration of integrated circuit devices including aluminium (Al) wiring layers is accompanied by a problem of higher contact resistances due to reduction of contact areas, and problems of degradation of higher resistances and electromigration resistances due to micronization of wiring sizes.
Here is needed a technique of forming micronized wirings and contacts of materials of high electromigration resistances and lower resistances. Copper is noted as a metal material for such wiring.
Conventionally a copper wiring layer has been formed by a process in which a thin film of copper is deposited on the entire surface Of a semiconductor substrate by sputtering or vaporization and then is chemically etched in a required wiring by RIE (Reactive Ion Etching).
But because of low etching speeds due to very low vapor pressures of copper halide generated in the etching step, the usual etching cannot make a patterned profile of the wiring layer clearcut. This has been a problem.
The formation of a coating film on the formed copper wiring layer for the prevention of the oxidation of the copper makes convexities and concavities of the wiring layer large. This has been an obstacle to planarization of the surface.
USPTO Backgrounds
USPTO Backgrounds