Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
High resistance of metal lines can limit performance of devices. Generally, the narrower a metal line, the higher the resistance. In three-dimensional memory devices in which drain select gate electrodes have a narrower width than underlying control gate electrodes, the relatively higher resistivity of the drain select gate electrodes can limit performance of memory cells within a three-dimensional memory array.
USPTO Backgrounds
USPTO Backgrounds