1. Field of Invention
The present invention relates to a method of manufacturing the capacitors of a semiconductor memory. More particularly, the present invention relates to a method of manufacturing the metal-insulator-metal (MIM) capacitors of dynamic random access memory (DRAM).
2. Description of Related Art
The cell of a semiconductor memory such as a dynamic random access memory (DRAM) generally consists of a transistor and a capacitor. Therefore, performance of memory can be improved if fast-acting transistors and/or high capacity capacitors are manufactured.
As semiconductor manufacturers start manufacturing deep sub-micron devices, dimensions of each device also shrink leading to a smaller space for forming memory capacitor. On the other hand, the demand for more powerful software has increased the memory requirement in a computer. Hence, higher capacity memory unit is always in great demand. Such conflicting goals mean that basic changes to method of fabrication have to be introduced.
At present, methods capable of increasing memory capacity despite size reduction include increasing the surface area of capacitor""s lower electrode and/or using a high dielectric constant (high-k) material. Typical stacked capacitor uses polysilicon as a storage node. High-k material includes barium-strontium-titanate (BaSrTiO3, BST), whose dielectric constant can be up to a hundred or more.
Because electrical conductivity of a polysilicon storage node is conferred through dopant implant, depletion region is easily formed in the capacitor while the memory is in operation. This can lead to a serial connection of the capacitors and result in a lowering of DRAM storage capacitance. Furthermore, polysilicon and barium-strontium-titanate often react at their interface. Consequently, when BST is used in a stacked capacitor, the conventional electrode material must be replaced to boost performance.
The so-called metal-insulator-metal structure of a capacitor is a capacitor that uses metal to form the upper and the lower electrodes. Since metal has a relatively low resistance and little interfacial reaction, MIM structure is capable of increasing capacitor performance.
However, the metal lower electrode of a MIM capacitor is preferably shaped into a crown or a fin to increase surface area and hence capacitance of the capacitor. Yet, shaping the metal electrode using existing fabricating techniques is still quite difficult.
Accordingly, one object of the present invention is to provide a method of manufacturing a metal-insulator-metal capacitor structure capable of increasing capacitor performance.
Another object of the invention is to provide a metal-insulator-metal capacitor structure capable of increasing storage electrode surface area and hence storage capacitance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a DRAM capacitor. To form the lower electrode of the capacitor involves using two different materials each having a different etching rate to form an alternately laid stack above a substrate. Differences in etching rates between the two materials are utilized to etch out a capacitor opening having serrated sidewalls. A polysilicon layer is next deposited into the capacitor opening. An aluminum layer and a titanium layer are sequentially formed over the polysilicon layer. An annealing operation is carried out in a nitrogen-filled atmosphere so that aluminum displaces polysilicon inside the capacitor opening. The silicon atoms in the polysilicon layer reacts with titanium atoms in the titanium layer to form a titanium silicide layer over the aluminum layer. The aluminum layer and the titanium silicide layer that cover the stacked layer are removed. The stacked layer is also removed to expose a fin-shaped aluminum lower electrode.
Since aluminum instead of polysilicon is used to fabricate the lower electrode, problems caused by the formation of a capacitor depletion region can be prevented. Furthermore, in the fabrication of the aluminum lower electrode, polysilicon, which has good step coverage, is deposited into the mold inside the stacked layer first. In the subsequent step, the polysilicon layer inside the mold is replaced by the aluminum layer deposited over the polysilicon layer in a polysilicon-aluminum displacement process. Consequently, the aluminum lower electrode thus formed also has good step coverage.
The stacked layer is made from two different insulating materials that has different etching rates. Hence, a capacitor opening with serrated sidewalls can easily be formed in the stacked layer by etching. Utilizing the mold cavity with serrated sidewalls, a fin-shaped aluminum lower electrode that can increase overall surface area of the lower electrode is formed with ease.
In addition, the aluminum lower electrode is formed by displacing polysilicon instead of depositing directly into the mold cavity in the stacked layer. Therefore, aluminum is first deposited over the polysilicon layer by physical vapor deposition. Later, the aluminum layer displaces the underlying polysilicon layer. Because the aluminum lower electrode is formed by displacement, step coverage problems encountered by a conventional metal deposition process can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
USPTO Backgrounds
USPTO Backgrounds