Conventionally, a memory cell is proposed that includes a variable resistive element of which resistance is changed by a voltage application. The variable resistive element can decrease its resistance by a set operation. In addition, the variable resistive element can increase its resistance by a reset operation.
The characteristics of the variable resistive element may change depending on the number of times the resistance is changed (the number of times the write/erase operations are performed).
USPTO Backgrounds
USPTO Backgrounds