1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to forming a plurality of fins of a FinFET device using combined planar block and sidewall image transfer (SIT) processes.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing, and level definition, e.g., etching, implanting, depositing, etc.
The FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
Device parameters of FinFETs are extremely sensitive to semiconductor fin thickness. In order to realize the full potential of a FinFET, the silicon fin must be very thin (e.g., on the same order of thickness as that of a fully-depleted SOI). Similarly, line width control problems during gate electrode definition for small devices can lead to performance degradation, power consumption control issues, and yield loss. Previously, lithographic techniques have been used to form device components (e.g., semiconductor fins for FinFETs, gate electrodes, etc.) in a substrate. Using photolithography, a feature can be printed directly into a photo-resist layer, and the image can be transferred into an underlying film. However, current state-of-the-art lithographic technology cannot adequately and efficiently satisfy the ever-increasing demand for smaller devices and device components. Thus, the requirement for very thin and replicable device components encourages the use of a SIT process to form such components.
SIT involves the usage of a sacrificial structure (e.g., a mandrel, typically composed of a polycrystalline silicon) and a sidewall spacer (such as silicon dioxide or silicon nitride, Si3N4, for example), having a thickness less than that permitted by the current ground rules, which is formed on the sides of the mandrel (e.g., via oxidization or film deposition and etching). After removal of the mandrel, the remaining sidewall spacer is used as a hardmask (HM) to etch the layer(s) below, e.g., with a directional reactive ion etch (RIE). Since the sidewall has a sublithographic width less than the ground rules, the structure formed in the layer below will also have a sublithographic width. In other uses, the sidewall may be used as a component in the desired structure (e.g., as a portion of the fins in a FinFET).
As shown by current art device 100 of FIG. 1, the SIT process inherently results in only a single fin width (W) for each of a plurality of fins 102, which controls the final channel width. As such, for some devices, multiple fins must be combined in parallel in order to achieve desired performance, with a shallow trench isolation (STI) 104 in areas where there are no fins. However, as more fins are added to device 100, the area of each transistor increases, which increases RC delays introduced due to metal routing involved in interconnections of multiple fins. Additionally, device stability decreases as more fins are used, especially for higher current devices at more advanced nodes (e.g., 10 nm and below).
USPTO Backgrounds
USPTO Backgrounds