A bipolar junction transistor is typically comprised of two back-to-back p-n junctions that share a thin common region. Contacts are made to all three regions, two outer regions called the emitter and collector and the middle region called the base. The device is called “bipolar” since its operation involves both types of mobile carriers, electrons and holes.
HBTs are bipolar junction transistors that are composed of at least two different semiconductors. As a result, the energy bandgap, as well as all other material properties, can be different in the emitter, base and collector. Moreover, a gradual change also called grading of the material is possible within each region. The use of heterojunctions provides an additional degree of design freedom, which can result in vastly improved devices compared to the homojunction counterparts.
Improvement of transistor performance, especially operation speed, is an essential requirement for improved network communication and wireless systems. Bipolar transistors with a silicon germanium (“SiGe”) intrinsic base deliver the type of performance required for such systems. A SiGe HBT is similar to a conventional silicon (“Si”) bipolar transistor except for the base. SiGe, a material with a narrower bandgap than Si, is used as the base material. SiGe HBT speed performance of 350 GHz (fT) has been demonstrated.
Unfortunately, however, collector resistance heavily influences the maximum frequency (Fmax) at which a transistor demonstrates useful (i.e., above unity) current gain. As transistor performance improves, the collector parasitic resistance (Rc) becomes a limiting performance factor. High collector parasitic resistance Rc limits fT. Both fT and the effective Rc time constant (principally a function of base transit time and collector space-charge transit time) limit Fmax.
Referring to FIG. 1, the structure of a related bipolar transistor 100 includes a collector 130 contacted by a buried layer (also called a subcollector) 120 and a reachthrough 140. The buried layer 120 provides a horizontal path from beneath the active region of the transistor 100 to the reachthrough 140. The reachthrough 140 provides a vertical path from the buried layer 120 to the surface of the device. The buried layer 120 is formed by high dose ion implantation followed by high temperature anneal and silicon EPI layer deposition. Depth trench isolation 110 and 115 and shallow trench isolation 125, 135 and 145 are formed. The shallow trench isolation 135 and 145 defines an area at the surface of the wafer for the reachthrough 140. A doping implant and anneal complete the formation of the reachthrough 140. The active part of the bipolar transistor 100 is formed on the Si EPI layer 130. Polysilicon emitter 175 and extrinsic base 155 and 160 regions are separated by dielectric 165 and 170. Following dielectric layer deposition, vias 180 and 185 and metallization are formed on the top surface of the structure to provide emitter 194, base 196, and collector 192 electrodes.
Such conventional structures face several drawbacks. One drawback relates to collector parasitic resistance, Rc, which has three main components: the resistance vertically from the collector-base 130-150 junction to the buried layer 120, the resistance along the buried layer 120, and the resistance from the buried layer 120 up to the collector contact 192. As fT increases, Rc increases thereby limiting Fmax.
Furthermore, because conventional HBTs are partially isolated, one to another, by a depth-trench that surrounds the device and by high doping implant regions around the depth-trench, well-to-substrate capacitance and device-to-device leakage current can affect negatively the device performance.
Embodiments of the invention are directed to overcoming one or more of the problems as set forth above.
USPTO Backgrounds
USPTO Backgrounds