Non-volatile memories such as flash memory can be used to store data in a wide range of different applications, such as a solid state disk (SSD). Data is read from the non-volatile memory in blocks referred to herein as a “read unit” or as a “codeword” that is protected from error by included error correction, such as included parity bits generated using an error correction algorithm such as low density parity check (LDPC) encoding. In some cases, each read unit contains approximately 4K to approximately 32K bits of user data, plus error correction bits. Under command of a solid state disk controller, those bits are read from non-volatile memory cells, e.g., via an array access. The resulting data is decoded to apply the error correction algorithm, for example in a low density parity check decoder. If the data fails to converge in the low density parity check decoder, a retry operation can be used to re-read the data and to again apply the error correction algorithm. Although cell voltage is continuous, non-volatile memory cells generally provide only binary hard decisions after a read operation. When soft iterative decoding algorithms such as low density parity check decoding are used for error correction, it is desirable to convert the hard decisions generated by the non-volatile memory into soft decisions that give the decoder more information to help correct errors. The soft decisions converted from a single read may not be of sufficient quality for successful decoding. In this case, multiple reads with varying read voltages can be used to obtain sufficient quality of the soft decisions. Thus, the location and frequency of the read reference voltages can directly affect the quality of the soft decision and eventually, the theoretic information content of the channel reads.
USPTO Backgrounds
USPTO Backgrounds