Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAM”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay-lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3-75 through 3-96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000” (hereinafter referred to as “the Xilinx Data Book”), published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) Young et al. further describe the interconnect structure of the Virtex FPGA in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines”.
Another such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. And yet another such FPGA, the Xilinx Virtex-II Pro™ FPGA, is described in detail in pages 19-71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology.
The terms “PLD” and “programmable logic device” include these exemplary devices, as well as encompassing devices that are only partially programmable. For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
In U.S. Pat. No. 6,075,418 B1 (“Kingsley”), a ring oscillator circuit is described. The ring oscillator circuit may be located in an FPGA and used for providing an oscillating test signal. A counter may be coupled to the ring oscillator circuit to determine the period of the ring oscillator circuit. As described in Kingsley, an FPGA may be configured with multiple test circuits, among which may be the ring oscillator circuit. It is further described in Kingsley that components may exhibit different propagation delays depending on whether they are configured to respond to rising or falling clock signal edges. Moreover, it is described in Kingsley that asynchronous test circuits may be included in the ring oscillator circuit, and that these test circuits may represent propagation delays on a test path. These test circuits may be used to characterize various types of propagation delays to produce speed files which predict performance of a design instantiated in an FPGA.
Heretofore, measurement of delay line skew and delay were done using labor intensive test bench measurements. The precision of such test bench measurements was somewhat limited. This limitation made cross-correlation of delay lines even more problematic.
Accordingly, it would be desirable and useful to provide means for cross-correlation of one or more delay line characteristics that overcomes one or more of the limitations associated with use of a test bench.
USPTO Backgrounds
USPTO Backgrounds