1. Field of the Invention
The present invention relates generally to a planar DMOS power transistor and its manufacturing method and, more particularly, to a self-aligned Schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods.
2. Description of the Prior Art
A DMOS (double-diffused metal-oxide-semiconductor) power transistor with a low turn-on resistance becomes an important semiconductor device for applications in battery protection, switching, linear regulator, amplifier and power management.
FIG. 1A shows a schematic cross-sectional view for a non-self-aligned source structure of a prior-art planar DMOS transistor, in which a p-body diffusion region 104a is formed in a lightly-doped n− epitaxial silicon layer 101 formed on a heavily-doped n+ silicon substrate 100 through a patterned window surrounded by a patterned polycrystalline-silicon gate layer 103a on a gate oxide layer 102a by using a first masking photoresist step (not shown); a heavily-doped p+ diffusion region 105a is formed within the p-body diffusion region 104a through the patterned window by using a high-energy ion implantation; a heavily-doped n+ source diffusion ring 106a is formed in a surface portion of the p-body diffusion region 104a and on a side surface portion of the heavily-doped p+ diffusion region 106a through a non self-aligned implantation window formed between a patterned photoresist layer (not shown) being formed in a middle portion of the patterned window and the patterned polycrystalline-silicon gate layer 103a on the gate oxide layer 102a by using a second masking photoresist step (not shown); a non self-aligned source contact window is formed through an etching hole surrounded by a patterned oxide layer 107a through a third masking photoresist step (not shown); and a source contact metal layer 108a is formed over the patterned oxide layer 107a and on a semiconductor surface formed by the heavily-doped p+ diffusion region 105a surrounded by the heavily-doped n+ source diffusion ring 106a and a side surface portion of the heavily-doped n+ source diffusion ring 106a. Apparently, the non self-aligned source structure of the planar DMOS power transistor shown in FIG. 1A needs two critical masking photoresist steps (second and third masking photoresist steps). However, misalignments of the two critical masking photoresist steps may produce non uniform current flow distribution, resulting in serious device reliability issues. Therefore, it is difficult to scale down source area of the planar DMOS power transistor. Moreover, the patterned polycrystalline-silicon gate layer 103a being acted as a gate-interconnection conductive layer may have a higher gate-interconnection parasitic resistance to reduce switching speed if the interconnected transistor cells are many. A typical example for the planar DMOS power transistor can refer to U.S. Pat. No. 5,268,586 disclosed by S. Mukherjee et al..
FIG. 1B shows an equivalent device representation of the planar DMOS power transistor shown in FIG. 1A, in which a p-n junction diode (D1) is formed between source and drain electrodes through the p-body diffusion region 104a and the lightly-doped N− epitaxial silicon layer 101. This p-n junction diode (D1) will be turned on in certain circuit applications and minority-carrier storage of a forwardly biased p-n junction diode may largely reduce switching speed of the planar DMOS power transistor. Therefore, a Schottky-barrier diode had been proposed to form between the sources and drain electrodes.
Several complicate methods had been proposed to simultaneously integrate a planar DMOS transistor and a Schottky-barrier diode in a transistor cell. A typical example can refer to U.S. Pat. No. 6,686,614 disclosed by J. Tihanji and are shown in FIG. 2A and FIG. 2B, in which FIG. 2A shows a schematic cross-sectional view and FIG. 2B shows an equivalent device representation. From FIG. 2A, a Schottky-barrier diode (Ds) is formed on a lightly-doped n− epitaxial silicon layer 20 through a non-self-aligned trench window formed in a middle portion of a p-body diffusion region 50. It is clearly seen that there is no diffusion guard ring formed for Schottky-barrier contact metal 90 to eliminate edge leakage and soft breakdown; the p-body diffusion region 50 is floating and isn't shorted to a heavily-doped n+ source diffusion ring 60; the non self-aligned trench window formed may produce non-uniform current flow distribution for nearby planar DMOS transistor cells; and the Schottky-barrier diode with a low barrier height may produce a large reverse leakage current in a forward blocking state.
It is, therefore, a major objective of the present invention to offer a self-aligned Schottky-barrier clamped planar DMOS transistor structure without using critical masking photoresist step.
It is another objective of the present invention to offer a self-aligned Schottky-barrier clamped planar DMOS transistor structure with a moderately-doped p-base diffusion ring of a planar DMOS transistor cell being acted as a diffusion guard ring of a Schottky-barrier diode to eliminate edge leakage current and soft breakdown.
It is a further objective of the present invention to offer a self-aligned Schottky-barrier clamped planar DMOS transistor structure with the moderately-doped p-base diffusion ring being shorted to a heavily-doped n+ source diffusion ring of the planar DMOS transistor cell.
It is an important objective of the present invention to offer a self-aligned Schottky-barrier clamped planar DMOS transistor structure with the Schottky-barrier diode being pinched by a p-n junction depletion region formed between the moderately-doped p-base diffusion ring and a lightly-doped N− epitaxial silicon layer to eliminate a reverse leakage current of the Schottky-barrier diode with a low barrier height in a forward blocking state.
USPTO Backgrounds
USPTO Backgrounds