Power consumption of electronic devices is an increasingly important factor in electronic device design. From an environmental perspective, energy demands of electronic devices occupy a sizable percentage of total energy usage due to large corporate data centers and the ubiquity of personal computing devices. Environmental concerns therefore motivate efforts to reduce the power consumption of electronic devices to help conserve the earth's resources. From an economic perspective, less power consumption translates to lower energy bills. Furthermore, many personal computing devices are portable and powered by batteries. The less energy that is consumed by a portable battery-powered electronic device, the longer the portable device can operate without recharging the battery. Lower energy consumption also enables the use of a smaller battery and the adoption of a thinner form factor, which means devices can be made more portable or versatile. Thus, the popularity of portable electronic devices also motivates efforts to reduce the power consumption of electronic devices.
An electronic device consumes power if the device is coupled to a power source and is turned on. This is true for the entire electronic device, but it is also true for individual parts of the electronic device. Power consumption can therefore be reduced if parts of an electronic device are decoupled from power or turned off, even while other parts remain powered and turned on. Entire discrete components of an electronic device, such as a whole integrated circuit (IC) or a display screen, may be decoupled from power or turned off. Alternatively, selected parts of a discrete component may likewise be powered down. For example, a distinct processing portion of an integrated circuit chip, such as a processing core, may be selectively powered down for some period of time to reduce energy consumption.
Thus, powering down a portion of an integrated circuit, such as a core, can save power and extend battery life. Powering down an integrated circuit portion is referred to herein as a “power collapse,” a “power collapse event,” or as creating a “power collapse period.” Unfortunately, implementing a power collapse of an integrated circuit core can create problems. For example, resuming a computing task using a core that was powered down takes time, which slows performance and can adversely impact a user experience. Operational data, which is data needed for an ongoing computing task, may also be lost if power is removed from certain types of computer memory. Losing operational data may force an application to restart or permanently damage user files, such as documents or pictures. To avoid a loss of operational data when a core of an integrated circuit is being powered down, the operational data can be stored in one or more special types of memory that maintain data during a power collapse period. In other words, some memory types, such as flash memory, are capable of maintaining stored data when power is removed from the memory. Flash memory, however, is unsuitable for high-speed processing because read/write access times are too slow.
Another type of memory that is capable of maintaining data during a power collapse period is called a retention flip-flop (RFF). Generally, flip-flops may be implemented as retention flip-flops or non-retention flip-flops. A flip-flop (FF), or flop, is a unit of computing memory that stores one bit of operational data. Flip-flops are relatively fast memory units, so integrated circuit designers employ flip-flops frequently across different functional cores of a chip. A typical flip-flop includes a master portion and a slave portion in which data is migrated internally from the master portion to the slave portion. Clocked, or synchronous, flip-flops are configured to enable data migration such that the data stored in the master portion is transferred to the slave portion responsive to a pulse of a clock signal.
Non-retention flip-flops are volatile memory that relinquish stored data if powered down, such as because of a power collapse event occurring with a corresponding core that includes the non-retention flip-flops. Retention flip-flops, on the other hand, are capable of retaining data during a power collapse period. In one approach, a retention flip-flop obtains power from a power rail that does not lose power during a power collapse event, so the retention flip-flop can therefore retain the one bit of operational data. Consequently, such retention flip-flops can support efforts to manage power consumption by facilitating the retention of operational data during a power collapse period without resorting to a slower memory type, such as flash memory.
Unfortunately, employing retention flip-flops is not as straightforward as employing non-retention flip-flops. Operating retention flip-flops is more complicated than operating non-retention flip-flops due to the additional data retention feature. If stored data is to be properly retained before, during, and after a power collapse period, the supplying of power, the positioning of data, and the control signaling for the retention flip-flop have to be carefully orchestrated. Otherwise, data stored in a retention flip-flop is subject to being compromised by a power collapse event, and the ability to use retention flip-flops to achieve power-conserving benefits is jeopardized accordingly.
USPTO Backgrounds
USPTO Backgrounds