Conventionally, a phase-locked loop (PLL) circuit has been incorporated in a semiconductor integrated circuit. This type of PLL circuits serve to produce a clock signal for allowing a logic circuit such as a large-scale logic integrated circuit to operate, and to produce a clock circuit used for sending and receiving actions in an integrated circuit for communications or the like.
JP-A-2005-184771 discloses a means which allows a loop filter of a built-in PLL circuit of a semiconductor integrated circuit for wireless communications to be formed on a chip. According to such means, two charge pump circuits for charging and discharging a filter capacitance are used; one charge pump circuit is smaller than the other in electric current flowing therethrough. Further, the reversed phase operation is performed so that the charging current source for one of the charge pump circuits and the discharging current source for the other charge pump circuit are made to work concurrently. Thus, a zero-point frequency as gained in case that the filter capacitance is made smaller can be achieved depending on the current ratio of the two current sources. It becomes possible to form the loop filter of a PLL circuit on the chip.
JP-A-6-276090 discloses a PLL circuit which supplies an output of a phase comparator to a voltage-control oscillator through a charge pump and a loop filter, which is provided with an additional charge pump for rapidly charging and discharging the capacitance of the loop filter for achieving a high-speed response and a sufficient after-lock noise suppression effect. In a high-speed mode, both the charge pumps, i.e. originally-provided pump and additional one, rapidly charge and discharge the capacity, whereby a high-speed response is materialized. After lock, the additional charge pump is turned off, and thus the PLL circuit is put in a low-noise lock state.
Now, U.S. Pat. No. 5,892,958 discloses a hard disk drive that a controller LSI is controlled into a sleep mode of small power consumption or an active mode of large power consumption depending on whether or not a main CPU accesses a file. The power control circuit stops supplying an internal clock pulse in the sleep mode, whereas it resumes supplying the internal clock pulse in the active mode.
Further, a spread spectrum clock generator for serial ATA interface (SSCG) including a fractional PLL circuit which toggles between two frequency division ratios of a divider according to an output of a delta sigma modulator is suggested by Wei-Ta Chen et al. “A Spread Spectrum Clock Generator for SATA-II”, 2005 IEEE International Symposium Circuits and Systems, 23-26 May 2005, PP. 2643-2646. According to Wei-Ta Chen et al., the PLL circuit tggles between two frequency division ratios (73 and 75) of the dual modulus divider according to the output of the delta sigma modulator. In this way, a spread spectrum clock generator (SSCG) modulates a clock signal in frequency and lowers the peak power of fundamental and harmonic waves of the clock for reduction in undesired radiations like EMI in electronic devices. In regard to such generator, the total energy is unchanged, but clock signals are spread over a wide frequency bandwidth with the clock signal amplitudes and signal edge waveforms maintained. Therefore, the peak energy can be reduced. Also, it has been reported in the document by Wei-Ta Chen et al. that a delta sigma modulator of MASH type with a primary delta sigma modulator of multiple stages is used for the purpose of reducing quantization noise in outputs of the delta sigma modulator. In case of a typical PLL circuit which takes only an integer as its frequency division ratio, the frequency resolution of the phase-locked loop is equal to the reference frequency fREF, and therefore a small reference frequency fREF is needed for fine frequency resolution. As a result, the loop frequency bandwidth is made smaller. A narrow loop frequency bandwidth is not desirable because it makes a switching time longer. Further, with a typical PLL circuit, phase noise of a voltage-control oscillator (VCO) thereof cannot be suppressed sufficiently, and such PLL circuit is easily affected by noise from the outside. In contrast, a fractional synthesizer incorporating a fractional PLL circuit has been developed, which has a finer frequency resolution than the reference frequency fREF. In a fractional-N divider, the frequency division ratio is changed from an integer N to another integer N+1 periodically. As a result, the average frequency division ratio is increased by the duty ratio of frequency division of N+1 rather than N. Now, it is noted that SSCG is an abbreviation for “Spread Spectrum Clock Generator”, and EMI is an abbreviation for “Electromagnetic Interference”. Further, MASH is an abbreviation for “Multistage noise Shaping Technique”. ATA is an abbreviation for “Advanced Technology Attachment”.
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