At present, there is a great demand for shrinking (or scaling) semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power.
SiO2 has been the most used gate dielectric material of semiconductor devices. However, scaling the thickness of SiO2 for gate dielectric applications has placed severe limitations on the oxidation process. Sub-angstrom uniformity across the wafer and thickness control are necessary requirements to use these dielectric materials.
Furthermore, as the thickness of the dielectric layer is reduced, quantum tunneling effects tend to increase, allowing an electric current to flow between the gate and the channel. This tunneling current is undesirable.
Recent efforts involving device scaling have focused on alternative dielectric materials which can be formed in a thicker layer than for example scaled SiO2 layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are higher than that of SiO2 (dielectric constant k of SiO2 being 3.9).
The relative performance of such high-k materials is often expressed as Equivalent Oxide Thickness (EOT), because the alternative material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2.
But, a drawback of using higher k dielectric materials is that they tend to provide poor quality interfaces. This poor quality of the interface tends to impair the electrical performance of the resultant gate electrode microstructure in those instances in which a higher k dielectric material is deposited directly onto the silicon substrate.
Therefore, as described in patent WO 2005/013349, dielectric materials, such as SiO2 or the like, can provide a buffer (or interface or bridge) between a semiconductor wafer and a high-k dielectric material to improve electrical performance when using high-k dielectric materials.
Unfortunately, it has been very difficult to develop extremely thin interfacial layers (e.g. those having a thickness below about 10 angstroms) with desired uniformity characteristics.
This lack of uniformity can impair electrical properties of the resultant devices.
In order to integrate high-k materials into current CMOS processing schemes, an interfacial layer of good quality (being flat, smooth, and uniform, and showing continuous interfacial oxide growth) would be beneficial between the semiconductor substrate and the deposited high-k material.
One challenge is to optimize this quality of the interface between a semiconductor wafer substrate (especially silicon wafer substrates) and the higher k dielectric material, upon which the performance and the reliability of the resultant transistors depend.
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