1. Field of the Invention
The present invention relates to a memory switching control apparatus using open serial interfacing capable of enhancing flexibility, reliability, availability, and performance in a data communication processes between a memory and a processing unit and an operating method thereof.
The present invention is derived from a research project supported by the IT R&D program of MIC/IITA [2006-S-061-02, IPv6-Based QoS Service and Terminal Mobility Supporting Router Technology].
2. Description of the Related Art
In general, an apparatus including processing units such as personal computers (PC), embedded systems, and portable apparatuses such as mobile phones includes a data storage device for storing processor codes, data, a booting program, an operating system (OS), applications, user's information, log data, and the like. The processing unit fetches the processor codes, the data, the booting program, the OS, the applications, the user's information, and the log data to drive the apparatus.
Since data storage device stores basic information and data for driving the processing unit which may influence performance of the corresponding apparatus, interfacing between the data storage device and the processing unit is important. Particularly, in an embedded system and a server system requiring high availability, a probability of occurrence of problems in the data storage device is relatively high in comparison with other devices.
The data storage device may include various types of memories such as DRAMs and SRAMs and Hard disks, and the type of the data storage devices is becoming diversified. Particularly, due to development of semiconductor technologies, various types of high-speed or low-speed memory devices have been integrated in a single package for small-sized low-power-consumption products.
In addition, as processing units have higher-speed and become parallelized, a stable memory-accessing request in high-frequency-band, memory-accessing requests of controllers in a high-speed input/output (IO) interface, and memory-accessing requests of embedded processing units or a group of processing units occur.
Therefore, various memory interface technologies have been researched so as to satisfy various demands according to high-speed parallelized processing units and to facilitate access of the processing units to various types of data storage devices.
As an example, a high-speed parallelized memory interface for accessing limitlessly the memory of a high-performance processing unit has been proposed. In addition, a technology for increasing the speed thereof has been actively developed.
However, a conventional parallelized memory interface has a limitation to a highest speed since the memory interface is implemented on a printed circuit board (PCB). In addition, since a high-frequency-band clock is included in the parallelized memory interface, synchronization between data and the clock is a difficult task. In addition, since signal characteristics may be slightly varied according to heat, physical impact, vibration, and the like, the synchronization between parallel data and between the data and clock may be unstable or broken down. In order to solve the problem, various types of buffers may be used in the high-speed parallelized memory interface. However, due to the limitation of existing parallelized memory interface scheme, difficulty in design of the memory interface is still remained and increased.
In addition, in case of using a plurality of data storage devices, it is difficult to prevent a bottle neck of data and data input/output delays by using a memory interfacing scheme using a single interface unit. Even in case of using the aforementioned parallelized memory interface scheme, since different interfaces need to be used for different types of memory devices, a complexity in design and implementation of the memory interfaces and the number of pins are increased.
In addition, in a general processor-based apparatus including the processing unit, positions of memory spaces which are used by the processing unit to drive the OS and the applications are fixed in most cases. Therefore, when a memory interface or a memory connected to the memory interface is in disorder, the processing unit cannot operate, so that the entire system may be stopped.
Recently, high-speed IO interfaces have been provided. Therefore, in an apparatus connected to the high-speed IO interface, requests of the processing unit for a usage right to a system memory have been increased. Accordingly, the request of the main processing unit for the usage right to the memory and the requests of the IO interfaces for the usage right to the memory may be issued simultaneously, so that a method capable of distributing the usage rights to the memory effectively has been required.
For example, when peripheral component interfaces (PCIs) connected to an Ethernet controller issues an access request for the system memory, the main processing unit, in order to drive an application, may issue a request for reading program codes from the memory or the memory interface of which access is already required by the Ethernet controller. In this case, due to occurrence of the two access requests, one of the processing units needs to be waiting; otherwise the request needs to be cancelled.
USPTO Backgrounds
USPTO Backgrounds