1. Field of the Invention
The present invention relates to a semiconductor manufacturing device, a semiconductor device manufacturing method, a simulation device, and a simulation program.
2. Description of the Related Art
It is known that in semiconductor processes using particles (gas) such as a dry etching method, a CVD (Chemical Vapor Deposition) method, a PVD (Physical Vapor Deposition) method and the like, the state of a chamber wall affects an etching rate or a deposition rate.
In view of correlation between the temperature of the chamber wall and the etching rate, Japanese Patent Laid-Open No. 2002-110635 discloses techniques for maintaining the temperature of the chamber wall at a predetermined temperature by feedback control, and thereby stabilizing etching characteristics.
In addition, Japanese Patent Laid-Open No. 2002-110635 cites, as a reason that the temperature of the chamber wall affects the etching rate, an increase in amount of sticking of particles on the chamber wall with decrease in the temperature of the chamber wall and a resulting decrease in amount of deposition of particles on a wafer.
USPTO Backgrounds
USPTO Backgrounds