1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and more particularly, to a method of forming a trench isolation for isolating elements.
2. Description of the Related Art
Based on miniaturization of the semiconductor device, a shallow trench isolation (referred to as the STI hereinafter) in which a shallow trench is formed to bury an insulation film for element isolation has been widely used as a method of electrically isolating elements of sub-quarter micron devices. A conventional manufacturing method of a semiconductor device disclosed in U.S. Pat. No. 6,287,974 where shallow trench isolation is implemented will be described with reference to FIGS. 21 and 22.
In FIGS. 21 and 22, the semiconductor device includes a chamber atmosphere 500, a silicon substrate 501, a silicon oxide film 502, a silicon nitride film 503, a resist pattern 504, the thickness of the silicon oxide film 505, a silicon shoulder round part 506, and a removal preventing film 507.
The STI is formed by trench etching the silicon substrate 501. At this time, an active region of the silicon substrate 501 is etched away under such a condition that a removal preventing film (C-group deposition) 507 is formed on the side wall of a hard mask (the silicon oxide film 502 and the silicon nitride film 503). According to this, the removal preventing film 507 is formed so as to round the active region shoulder part 506. Hereinafter, the portion of the active region shoulder part protruding from the hard mask along the lateral direction of the substrate is referred to as the projecting part, and the rounded portion of the projection part is referred to as the round part. The above etching condition is determined by selecting the kind of etching gas, a gas flow rate and the like. The round part of the active region shoulder part 506 formed as described above plays an important role in reducing an electric field concentration to a gate insulation film. The shape of the round part of the active region shoulder part 506 is controlled by the amount of the removal preventing film 507 formed.
FIG. 23 shows a sectional observation image by a scanning electron microscope (SEM) at this time. FIG. 24 is a schematic view showing the SEM image in FIG. 23. In FIG. 24, a representative example of a pattern in which active regions are crowded, is described on the left side and a representative example of a pattern in which active regions are relatively isolated, is described on the right side. In below description, the part to which a term “crowding” is appended means the part in which the active regions are crowded and the part to which a term “isolated” is appended means the part in which the active regions are isolated. In FIG. 24, numeral 600 denotes a chamber atmosphere, numeral 601 denotes a silicon substrate, numeral 602 denotes a silicon oxide film, numeral 603 denotes a silicon nitride film, numeral 604 denotes a resist, numeral 605 denotes the thickness of the silicon oxide film, numeral 606 denotes a silicon shoulder round part (crowding), numeral 606′ denotes a silicon shoulder round part (isolated), numeral 607 denotes a removal preventing film, numeral 608 denotes a taper angle of the removal preventing film (crowding), numeral 609 denotes a projection part of the silicon substrate (crowding), numeral 610 denotes a taper angle of the removal preventing film (isolated), numeral 611 denotes a projection amount of the silicon substrate (isolated), and numeral 612 denotes a height of the removal preventing film, respectively. FIGS. 25A and 25B are enlarged views showing the round part, wherein FIG. 25A shows the part in which the distance between the active regions is close and FIG. 25B shows the part in which the distance between the active regions is large.
As can be clear from the drawings, the size of the projection part (referred to as the projecting size, hereinafter) and the size of the round part (referred to as the round size, hereinafter) vary depending on the density of the pattern and the like.
USPTO Backgrounds
USPTO Backgrounds