In integrated circuit (IC) devices, resistive random access memory (RRAM) is an emerging technology for next generation non-volatile memory devices. RRAM is a memory structure including an array of RRAM cells each of which stores a bit of data using resistance values, rather than electronic charge. Particularly, each RRAM cell includes a resistive material layer, the resistance of which can be adjusted to represent logic “0” or logic “1.”
In advanced technology nodes, the feature size scales down and the size of memory devices is reduced accordingly. However, the reduction of the RRAM devices is limited due to the “forming” operation. In the “forming” process, a high voltage is applied to the RRAM device to generate a conductive path in the resistive material layer of the DRRAM device. The high “forming” voltage introduces reliability concern. Furthermore, the high current during the operations of the RRAM device leads to concerns of the high power consumption and reliability since high current means high current density. To reduce the current density, the size of the RRAM device needs to be big enough in the cost of the circuit packing density.
There are various architectures to configure an array of RRAM cells. For example, across-point architecture includes only a RRAM in each cell configured between crossed a word line and a bit line. The cross-point architecture has a high packing density but has a sneak path issue, which causes a fault read during operation. In other architectures of a RRAM array, such as 1T1R that includes one transistor and one RRAM device, the operation voltage could be very high, causing the damage to the transistor.
Accordingly, it would be desirable to provide an improved RRAM structure and a method of manufacturing thereof absent the disadvantages discussed above.
USPTO Backgrounds
USPTO Backgrounds