In semiconductor manufacturing, package on package (PoP) stacking and redistribution layer (RDL) processes utilize the formation of a molding compound and subsequent and chemical-mechanical planarizing (CMP), grinding, polishing, and other mechanical material removal processes to expose the die of integrated circuit devices. However, the mechanical material removal processes can present issues for device function, and can drive up the costs associated with package assembly. For example, mechanical material removal processes can cause scratches that harm input/output (I/O) surfaces of the devices, and may further generate particles that cause PoP joints and connections to fail, or that cause RDL openings. Consequently, only about 80% of die area may be adequately exposed after the molding and mechanical material removal processes are performed. Moreover, existing molding methods too often fail to adequately prevent die shifting during assembly.
USPTO Backgrounds
USPTO Backgrounds