1. Field of the Invention
This invention relates to a multi-phase multi-access pipeline memory system.
2. Description of the Prior Art
In conventional computers and microcomputers there is a constant contention between the microprocessor and the I/O processor for memory access. This is a particularly serious problem in signal processing applications requiring high speed processing of massive amounts of data and high I/O rates. There are four approaches commonly used to enable fair sharing of the memory. One is to use dual port memories: these are generally complex and expensive and have small capacity. A second approach uses xe2x80x9ccycle stealingxe2x80x9d wherein one of the microprocessor and I/O processor has priority over the other and xe2x80x9cstealsxe2x80x9d memory access when it needs it, thereby interrupting the operation of the other. This slows down the response of the interrupted processor and of the whole system. The third approach uses a number of separate memory banks so that most of the time each of the microprocessor and I/O processor can be accessing a different bank. In order to effect his, however, the user/programmer must superimpose on the programming the goal of minimizing overlap in access demand for the memory banks by the microprocessor and I/O processor. This requires careful scheduling of the I/O and computing tasks so that simultaneous demand by both processors for the same memory bank is avoided or at least reduced. That imposes a burdensome ancillary constraint on the user. The fourth approach is to simply run the memory at twice the normal cycle speed. But this is difficult, especially in signal processing systems where memories are already operating at near capacity as a rule.
Also, even in a single processor design, there may be the need to issue two instructions and receive two data valves per system clock cycle or, one or more processors could be operating in this way while other processors in the system may issue only one instruction and receive one data value per clock cycle. In any case, the same shortcomings in the prior art are present with these designs.
It is therefore an object of this invention to provide an improved, multi-phase multi-access pipeline memory system.
It is a further object of this invention to provide such a multi-phase multi-access pipeline memory system which does not increase, expand or limit memory capacity.
It is a further object of this invention to provide such a multi-phase, multi-access pipeline memory system which does not interrupt other processors"" access to the memory and does not slow down the system operation as a whole.
It is a further object of this invention to provide such a multi-phase, multi-access pipeline memory system which requires no special programming or scheduling of processor-memory interaction.
It is a further object of this invention to provide such a multi-phase, multi-access pipeline memory system which does not require operating the memory above normal speeds.
It is a further object of this invention to provide such a multi-phase, multi-access pipeline memory system for implementing instructions or data caches.
The invention results from the realization that a truly effective multi-access memory system can be achieved in which each processor has access to the memory once in each system clock period without interfering with the access of the other processors by phase shifting the memory access of the processors and pipelining the memory so that each processor accesses memory during a different phase of the system clock period while maintaining the memory operation at its normal speed. Underlying this approach is the fundamental realization that in most cases there is no reason why all the processors, be they microprocessors or I/O processors, must access memory in phase so that their accesses start and end simultaneously: an overlapped sequence of access is acceptable and therefore pipelined memory in combination with phase overlapped sequencing can be used to full advantage. Also, it was realized that such a dual access, dual phase memory system may be used to implement instructions or data caches.
This invention features a dual phase, dual access pipeline memory system having first and second processors, a pipeline memory including latch means, and a bus means for interconnecting the processor to the pipeline memory. There is a clock circuit responsive to a system clock signal for providing a first clock signal in phase with the system clock signal for operating the access of the first processor, a second clock signal out of phase with the system clock signal for operating the access of the second processor out of phase with the first processor, and a third clock signal at twice the system clock signal rate for clocking the pipeline memory through the latch means to allow an address to be supplied to the pipeline memory by the first processor while accessing data from the address supplied in the previous cycle during one phase. Conversely, it allows an address to be supplied to the pipeline memory by the second processor while accessing data from the address supplied in the previous cycle during the other phase.
In the preferred embodiment the processors may include an I/O processor and a microprocessor, or the processors may be both microprocessors. The processors may also include subprocessors in the same microprocessor. The subprocessors may include an instruction fetch unit and a data fetch unit. The pipeline memory may include a plurality of memory banks and the bus means may include a plurality of data address bus pairs and there may be third and fourth processors. The first and third processors may include data fetch units which access different memory banks from each other in the same phase with each other and the second and fourth processors may include an instruction fetch unit and an I/O processor which access different memory banks from each other in the same phase with each other but out of phase with the first and third processors.
In a more comprehensive sense, the invention features a multi-phase, multi-access pipeline memory system which includes a number, n, of processors, a pipeline memory including latch means, and bus means interconnecting the processors and pipeline memory. There is a clock circuit responsive to a system clock signal for dividing the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating the access of each processor to allow data and addresses to be transferred only during the assigned phase, thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.
In a preferred embodiment at least one of the processors may be an I/O processor and one may be a microprocessor, or the processors may both be microprocessors. The processors may include subprocessors in the same microprocessor. The subprocessors may include a data fetch unit and an instruction fetch unit. The latch means may include a plurality of latches to enable pipelining of n accesses of the pipeline memory during each system clock signal period.
This invention also features a dual-phase, dual-access pipeline memory system comprising processor means, a pipeline memory including latch means bus means for interconnecting the processor means and the pipeline memory. A clock circuit, responsive to a system clock cycle, provides the first clock signal in phase with the system clock signal, and a second clock signal out of phase with the system clock signal, and the third clock signal with twice the system clock signal rate for clocking the pipeline memory through the latch means to allow an address to be supplied to the pipeline memory by the processor means during one phase while the processor means is accessing data from the previous cycle in the same phase, and conversely to allow another address to be supplied to the pipeline memory by the processor means during the other phase while the processor means is accessing data from the previous cycle in the same phase. The processor means may include a single processor issuing first and second instructions to the memory and receiving first and second data values from the memory for a system clock cycle. Alternatively, the processor means may include first and second processors and the first clock signal accesses the first processor and the second clock signal accesses the second processor out of phase with the first processor.
In a more comprehensive sense, the invention features a multi-phase, multi-access pipeline memory system comprising a number of processors which issue two instructions and receive two data values per system clock cycle and a number of different types of processors which only issue one instruction and receive one data value per system clock cycle. This divides the system clock signal into two phases per each first type of processor, and one phase for each second type of processor and one phase for each second type of processor. Instead of dividing the clock cycle into more phases, other processor can share the memory by cycle stealing.
This invention also features a method of operating two processors which access the pipeline memory by dividing the clock cycle into two phases, operating the first processor to issue instructions to the memory during one phase and to receive data in the same phase, and operating the second processor to issue an instruction to the memory during the second phase. For the single processor embodiment, the method includes dividing the clock cycle into two phases and operating the processor to issue an instruction during the first phase and to issue an instruction during the second phase, and operating the processor to receive data from the memory during the first phase and to receive data from the memory in the second phase.
USPTO Backgrounds
USPTO Backgrounds