In the prior art, there is an image processing system which is enabled to operate a personal computer while observing a TV program by superimposing the picture of the TV with a predetermined size and in a predetermined position on the monitor frame of the personal computer.
FIG. 21 is a block diagram showing the image processing system of the prior art. In FIG. 21: reference numeral 100 designates a video decoder for separating a first video signal VS.sub.1 into a first synchronizing signal SS.sub.1 and a first luminance signal LS.sub.1 ; numeral 200 designates an analog-digital converter (which will be shortly referred to as an "ADC") for digitizing the first luminance signal LS.sub.1 ; numeral 300 designates a video memory for storing the digitized first luminance signal LS.sub.1 ; numeral 340 designates a write control unit for controlling the writing of the first luminance signal LS.sub.1 in the video memory 300; numeral 350 designates a read control unit for controlling the reading of the first luminance signal LS.sub.1 out of the video memory 300; numeral 400 designates a digital-analog converter (which will be shortly referred to as a "DAC") for converting to analog the first luminance signal LS.sub.1 read out from the video memory 300; numeral 600 designates a CPU control unit; numeral 630 designates a multiplexer; numeral 640 designates a video decoder unit for separating a third video signal VS.sub.3 into a third synchronizing signal SS.sub.3 and a third luminance signal LS.sub.3 ; and numeral 500 designates a mixing control unit for mixing the first luminance signal LS.sub.1 and the third luminance signal LS.sub.3 to output a fourth luminance signal LS.sub.4.
In this video processing circuit of the prior art, the video decoder 100 separates the video signal VS.sub.1 into the synchronizing signal SS.sub.1 and the luminance signal LS.sub.1, and the ADC 200 digitizes and writes the luminance signal LS.sub.1 in the video memory 300.
At this time, the write control unit 340 outputs a timing clock for controlling the operations of the ADC 200 and the video memory 300 on the basis of the synchronizing signal SS.sub.1.
Here, the second luminance signal LS.sub.2 outputted from the CPU control unit 600 can be written in the video memory 300.
Moreover, the read control unit 350 reads out the first luminance signal LS.sub.1 (or the second luminance signal LS.sub.2) written in the video memory 300 through the multiplexer 630. The DAC 400 converts to analog the first luminance signal LS.sub.1 read out from the video memory 300. The mixing control unit 500 mixes the first luminance signal LS.sub.1 and the third luminance signal LS.sub.3 to output the fourth luminance signal LS.sub.4 in which an image corresponding to the first luminance signal LS.sub.1 is superimposed on the image corresponding to the third luminance signal LS.sub.3.
For a still image, on the other hand, a CPU 620 monitors the operations of the video decoder unit 100. If this video decoder unit 100 outputs a vertical synchronizing signal, the CPU 620 interrupts the digitize control by the ADC 200 during the vertical blanking period in the video signal.
In this still image, too, there can be obtained the fourth luminance signal LS.sub.4 in which the image corresponding to the first luminance signal LS.sub.1 is superimposed upon the image corresponding to the third luminance signal LS.sub.3.
When, moreover, letters or special shapes are to be superimposed upon the image corresponding to the first luminance signal LS.sub.1, the CPU control unit 600 writes the shape data of the letters or special shapes in the video memory 300.
Here, the image processing system of the prior art, as shown in FIG. 21, is troubled by a problem that it cannot cope in the least with the multi-purpose specifications such as the display by an arbitrary resolution corresponding to a smart image to be developed in the near future, the conversion of an arbitrary aspect ratio, the control of display in an arbitrary position, or the superimpose.
For the multi-purpose specifications, moreover, the price for the system rises as high as several hundreds to thousands yens as in the TV broadcasting system used at present in the commercial broadcasting stations.
This raises a problem that fundamental technical innovations are required for the level of the home appliances.
Generally speaking, on the other hand, the video memory 300 has to be refreshed because it is constructed of a dynamic memory.
For this necessity, a clock signal for refreshing the video memory 300 is fed to the serial ports of the video memory 300. This clock signal has a frequency of 10 (MHz) or more, for example.
In case, therefore, the serial output at the side of the multiplexer 630 has a clock of several hundreds (KHz) to several (MHz), a frequency of 10 (MHz) or more has to be supplied from the aforementioned serial output other than that at the side of the DAC 400.
This serial output other than that at the side of the DAC 400 has to be merely the refreshing clock aiming at no output.
If the video data of the video memory 300 is to be read out by the CPU control unit 600, the multiplexer 630 has to be switched to read out the video data from the CPU control 600 so that the video data are not sent to the DAC 400. This raises another problem that the image coming from the DAC 400 becomes the fourth luminance signal LS.sub.4 in the blanked state even if it is superimposed upon the third luminance signal LS.sub.3.
Still another problem is that it is impossible for the CPU to read the CPU control 600 by the operations always having a frequency of 10 (MHz) or more than that of the aforementioned serial output other than that at the side of the DAC 400.
For the still image, moreover, the CPU control unit 600 has to monitor the a vertical synchronizing signal VS.sub.1 thereby to raise a further problem that the CPU control unit 600 has to require a standby time of several tens mS in the worst case.
Even if, moreover, the CPU control unit 600 is equipped with a high-speed IC such as a digital signal processor (which is called the "DSP"), it takes several tens (.mu.s) to rewrite the letters or special shapes.
In case, on the other hand, the third luminance signal LS.sub.3 is related to one corresponding to a motion picture, there is required a time period for reducing the frame number of the third luminance signal LS.sub.3 and to rewrite the stored content of the video memory 300 by the CPU 620.
It is impossible to scroll the letters or special shapes vertically and horizontally in the third luminance signal LS.sub.3.
USPTO Backgrounds
USPTO Backgrounds