1. Field of the Invention
The present invention relates to a pulse output circuit, a shift register, and a display device, a semiconductor device, and an electronic device each of the devices having the shift register, particularly relates to a pulse output circuit, a shift register, and a display device, a semiconductor device, and an electronic device each having a thin film transistor (TFT) having one conductivity type.
2. Description of the Related Art
In recent years, a display device in which a circuit is formed using a thin film transistor (hereinafter also referred to as a TFT) that is formed using a semiconductor thin film over an insulator, particularly over a glass substrate or a plastic substrate has been developed, particularly an active matrix display device has been developed. An active matrix display device formed by using a TFT has several hundreds of thousands to several millions of pixels which are arranged in matrix, and an image is displayed by controlling the charge of each pixel with the TFT arranged in each pixel.
In addition, as a recent technique, a method in which a driver circuit is formed by using a TFT in the peripheral region of a pixel portion at the same time as a pixel TFT which forms a pixel has been developed. Such a method contributes greatly to reduction in the size and weight and low power consumption of a device, and along with this, a TFT is an essential device for a display portion and the like of a mobile information terminal of which an applicable field has been significantly expanded in recent years.
In general, as a circuit which forms a driver circuit of a display device, a CMOS circuit in which an N-channel TFT and a P-channel TFT are combined is used. As features of the CMOS circuit, the following can be given: one feature is that power consumption in the whole circuit can be suppressed to a very low level because current flows only at the moment when a logic is changed (from an H (High) level to an L (Low) level, or from an L level to an H level) and current does not flow ideally (actually, there is minute leakage current) while a certain logic is held, and another feature is that high speed operation is possible because TFTs having different polarities operate complementarily.
However, in consideration of manufacturing steps, since an ion doping process or the like of the CMOS circuit is complicated, a large number of manufacturing steps have an effect on production cost directly. Thus, a circuit is proposed, which is formed using a unipolar TFT that is either an N-channel TFT or a P-channel TFT instead of a CMOS circuit that is conventionally used, and which achieves high speed operation equivalent to the CMOS circuit (e.g., refer to Reference 1: Japanese Published Patent Application No. 2002-335153).
As shown in FIGS. 7A to 7C, in a circuit described in Reference 1, when a gate electrode of a TFT 2050 which is electrically connected to an output terminal is made to be in a floating state temporarily, a potential of the gate electrode can be set as a potential which is higher than a power supply potential by using capacitive coupling between the gate and a source of the TFT 2050. As a result, an output without amplitude attenuation can be obtained without generating a voltage drop due to a threshold value of the TFT 2050. Reference numerals 2010, 2020, 2030, 2040, and 2060 are TFTs. Reference numeral 2070 is a capacitor. Reference numeral 2100 is a first amplitude compensation circuit and reference numeral 2200 is a second amplitude compensation circuit.
Such operation in the TFT 2050 is referred to as bootstrap operation. With this operation, an output pulse can be obtained without generating a voltage drop due to the threshold value of the TFT.
In addition, in the circuit illustrated in FIGS. 7A to 7C, both gate electrodes of the TFT 2050 and a TFT 2060 are in a floating state during the period when there is no input and output of a pulse, so that a potential change, such as noise, occurs in a node α. However, in order to solve this problem, a circuit (see FIGS. 8A to 8C) is proposed in which noise generated in the node α is reduced when a TFT 1020 and a TFT 1060 are turned on and are in a floating state during the period when there is no input and output of a pulse (e.g., see Reference 2: Japanese Published Patent Application No. 2004-226429). Reference numerals 1010, 1030, 1040, and 1050 are TFTs. Reference numeral 1070 is a capacitor. Reference numeral 1100 is a first amplitude compensation circuit and reference numeral 1200 is a second amplitude compensation circuit.
USPTO Backgrounds
USPTO Backgrounds