As the field effect transistors (FETs) used in integrated circuits become ever smaller, it has been found that many parameters do not decrease (or scale) as the physical dimensions of the FET decrease. One of these parameters is the fringe capacitance between the source/drains of the FET and the gate electrode. As capacitance increases, FETs slow down. Since fringe capacitance does not scale, smaller FETs do not exhibit as much increase in speed as expected. Thus, to achieve continuing performance gain with decreasing FET dimensions there is a need for FET structures having reduced fringe capacitance.
USPTO Backgrounds
USPTO Backgrounds