1. Field of the Invention
The present invention relates to logic circuits with the function of controlling discharge current on pull-down and to emitter coupled logic (hereinafter referred to as ECL) circuits. More particularly, the present invention relates to a logic circuit allowing two-stage control of a discharge current of a capacitive load on pull down, and to an ECL circuit for outputting a first or second logic potential in response to a logic signal provided to an input terminal.
2. Description of the Background Art
An ECL circuit allowing high speed operation with low power consumption, in which large current is allowed to flow only when an output potential is changed from a high level to a low level by discharging capacitive load, is generally called an active pull-down ECL circuit. FIG. 4 is a circuit diagram showing a structure of a conventional active pull-down ECL circuit 4 such one as described in 1989 IEEE International Solid-State Circuits Conference pp. 224-225.
Referring to FIG. 4, active pull-down ECL circuit 4 includes a first input terminal IN1, first and second reference potential terminals VBB1, VCS1, a first output terminal OUT1, a ground potential GND, and a supply terminal VEE. A logic signal having a high level and a low level is input to first input terminal IN1. A first reference potential which is a threshold potential of a logic amplitude of the input logic signal is applied to first reference potential terminal VBB1. Ground terminal GND is connected to the ground, and a supply potential lower than the ground potential is applied to supply terminal VEE. A second reference potential higher than the supply potential is applied to second reference potential terminal VCS1. First output terminal OUT1 has a capacitive load CL including capacitance of wire and input capacitance of a gate of the next circuit.
Active pull-down ECL circuit 4 also includes a current switch circuit 4a, a bias circuit 4b, an output circuit 4c, and a capacitor C1. Current switch circuit 4a includes bipolar transistors Q12-Q14 and resistors R10-R12. Transistors Q12 and Q13 have base terminals connected to first input terminal IN1 and first reference potential terminal VBB1 respectively, collector terminals connected to ground terminal GND via resistors R10 and R11 respectively, and emitter terminals connected in common to a collector terminal of transistor Q14. Transistor Q14 has a base connected to second reference potential terminal VCS1, and an emitter terminal connected to supply terminal VEE via resistor R12.
Bias circuit 4b includes diodes D1 and D2 and a resistor R13. Diodes D1 and D2 are serially connected in a forward direction. Diode D1 has an anode terminal connected to ground terminal GND, and diode D2 has a cathode terminal connected to supply terminal VEE via resistor R13. Capacitor C1 is connected between the collector terminal of transistor Q13 and the cathode terminal of diode D2.
Output circuit 4c includes bipolar transistors Q15 and Q16, a resistor R14 and a capacitor C2. Transistor Q15 has a base terminal connected to the collector terminal of transistor Q12, a collector terminal connected to ground terminal GND, and an emitter terminal connected to first output terminal OUT1. Transistor Q16 has a base terminal connected to the cathode terminal of diode D2, a collector terminal connected to first output terminal OUT1, and an emitter terminal connected to supply terminal VEE via resistor R14. Capacitor C2 is connected in parallel to resistor R14.
Transistor Q14 and resistor R12, and transistor Q16 and resistor R14 constitute constant current sources respectively. At respective constant current sources, each of resistors R12 and R14 has each one end connected to supply terminal VEE. The potential of second reference potential terminal VCS1 or potential from the base terminal of transistor Q16 minus the on-voltage (VBE0.8 V) between the base and emitter terminals of transistors Q14 and Q16 is applied to the other end of respective resistors R12 and R14. Therefore, current of a value corresponding to the voltage applied to both ends of resistors R12 and R14 divided by the resistance of resistors R12 and R14, flows through respective constant current sources. The base terminal of transistor Q16 is biased to a lower potential by the on-voltage (VD0.8 V) of two diodes D1 and D2 than the potential of ground terminal GND.
When the input logic signal provided to first input terminal IN1 makes a transition from a high level to a low level, each transistor operates in the following manner.
Transistor Q12 turns off and transistor Q13 turns on. Accordingly, the current of the constant current source consisting of transistor Q14 and resistor R12 flows through transistor Q13 and resistor R11. No current flows through resistor R10, and thus the potential of the base terminal of transistor Q15 attains a high level. Transistor Q15 charges capacitive load CL and first output terminal OUT1 attains a high level. At this time, since current flows through resistor R11 and a node between transistor Q13 and resistor R11 attains a low level, the potential of the base terminal of transistor Q16 attains low level via capacitor C1. If the capacitance of capacitor C2 is large enough, the potential of the emitter terminal of transistor Q16 does not immediately follow the potential of the base terminal of transistor Q16 going low. As a result, the voltage between the base and emitter terminals of transistor Q16 becomes smaller than the on-voltage VBE (0.8 V), thereby turning transistor Q16 off.
When the input logic signal provided to first input terminal IN1 changes from a low level to a high level, these transistors operate in the following manner.
Transistor Q12 turns on, and transistor Q13 turns off. Therefore, the current of the constant current source consisting of transistor Q14 and resistor R12 flows through transistor Q12 and resistor R10. As a result, the potential of the base terminal of transistor Q15 attains a low level. Since no current flows through transistor Q13 at this time, the collector terminal of transistor Q13 connected to resistor R11 makes a transition to a high level. Consequently, the potential of the base terminal of transistor Q16 becomes high. Provided that the capacitance of capacitor C2 is large enough, the potential of the emitter terminal of transistor Q16 does not immediately follow the high going potential of the base terminal of transistor Q16. As a result, the voltage between the base and emitter terminals of transistor Q16 becomes greater than the on-voltage VBE (0.8 V), thereby turning on transistor Q16. The current exponentially proportional to the potential of the base terminal of transistor Q16 flows through transistor Q16, thereby rapidly discharging capacitive load CL, and the potential of first output terminal OUT1 attains a low level. This circuit thus implements the logic of an inverter.
As described above, capacitors C1 and C2 are used for controlling discharging current at the time of pull down in the conventional active pull-down ECL circuit 4, and therefore a high-cost process technique including the steps of making capacitors is required for its manufacture.
USPTO Backgrounds
USPTO Backgrounds