The semiconductor integrated circuit industry has experienced rapid growth in the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. In the course of semiconductor evolution, the number of interconnected devices per unit of area has increased as the size of the smallest component that can be reliably created has decreased.
However, as the size of the smallest component has decreased, numerous problems have arisen. One problem of particular concern that has arisen is the increase in parasitic capacitance associated with vias through inter-metal dielectric layers made from silicon oxide. This has prompted a search for “low-k” dielectrics, dielectrics with a lower dielectric constant than silicon dioxide. Promising low-k materials have been developed to allow the long trend of scaling down feature size to continue. While many low-k materials show significant potential, many such materials have been problematic to integrate into existing, traditional semiconductor processes. For example, planarizing wafers that feature low-k dielectrics can present challenges that can result during the removal excess material during metallization steps. The challenges can cause increased resistance in associated vias.
The various features disclosed in the drawings briefly described above will become more apparent to one of skill in the art upon reading the detailed description below. Where features depicted in the various figures are common between two or more figures, the same identifying numerals have been used for clarity of description. However, this should not be understood as limiting such features.
USPTO Backgrounds
USPTO Backgrounds