1. Field of Art
The present invention relates to a display device and more particularly to an array substrate for a display device including a storage capacitor without decrease of aperture ratio and a method of fabricating the array substrate by reduced a number of mask processes.
2. Discussion of the Related Art
A cathode ray tube (CRT) has been widely used as a display device. Recently, however, a flat panel display device, for example, a plasma display panel (PDP) device, a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device, is used as a display device instead of the CRT.
Among these flat panel display devices, the OLED display device has an advantage in thickness and weight because the OLED display device does not require a backlight unit. The OLED display device is a self-emission type display device. Recently, the OLED display device is used for a large display device.
FIG. 1 is a cross-sectional view of an array substrate for the related art OLED display device.
As shown in FIG. 1, in the array substrate for the OLED display device, a gate line (not shown) and a data line 32 are formed on and over a substrate 10. The gate line and the data line 32 cross each other to define a pixel region on the substrate 10. In addition, a common voltage line (not shown) may be formed in each pixel region to be parallel to the data line 32.
First and second thin film transistors (TFTs) TR1 and TR2 are formed at a crossing portion of the gate line and the data line 32. The first and second TFTs TR1 and TR2 serve as a switching element and a driving element, respectively.
The first TFT TR1 includes a first semiconductor layer 17, a first gate electrode 11, a first source electrode 12 and a first drain electrode 13. The first gate electrode 11 is spaced apart from the first semiconductor layer 17 by a gate insulating layer 14. An interlayer insulating layer 31 covers the first gate electrode 11 and includes contact holes exposing both ends of the first semiconductor layer 17. The first source electrode 12 and the first drain electrode 13 are formed on the interlayer insulating layer 31 and are respectively connected to the first semiconductor layer 17 through the contact holes in the interlayer insulating layer 31.
The second TFT TR1 includes a first semiconductor layer 27, a second gate electrode 21, a second source electrode 22 and a second drain electrode 23. The second gate electrode 21 is spaced apart from the second semiconductor layer 27 by the gate insulating layer 14. The interlayer insulating layer 31 covers the second gate electrode 21 and includes contact holes exposing both ends of the second semiconductor layer 27. The second source electrode 22 and the second drain electrode 23 are formed on the interlayer insulating layer 31 and are respectively connected to the second semiconductor layer 27 through the contact holes in the interlayer insulating layer 31.
The first source electrode 12 is connected to the data line 32, and the second source electrode 22 is connected to the common voltage line.
The first drain electrode 13 of the first TFT TR1 is connected to a second capacitor electrode 16, and the second drain electrode 23 is connected to a first capacitor electrode 15. The second capacitor electrode 16 overlaps the first capacitor electrode 15 to form a storage capacitor Cst.
An anode electrode 19 is formed to be electrically connected to the second drain electrode 23. In addition, an organic emitting layer (not shown) and a cathode electrode (not shown) are stacked on the anode electrode (19) such that the array substrate for the OLED display device is formed.
In the OLED display device, a hole from the anode electrode 19 and an electron from the cathode electrode are combined in the organic emitting layer such that light is emitted from the organic emitting layer. When the cathode electrode is formed of an opaque metallic material, the light from the organic emitting layer passes through the substrate 10 including the first and second TFTs TR1 and TR2.
A voltage for controlling an electric current of a pixel is charged in a storage capacitor Cst such that a level of the electric current is maintained to next frame. When a surface area (or area) of the storage capacitor Cst is enlarged to improve driving security, the aperture ratio is reduced because the first and second capacitor electrodes 15 and 16 are formed of an opaque metallic material.
To resolve the above problem, often the area of the storage capacitor Cst is optimized to have a minimum capacitance for a pixel driving. However, since a number of pixels in a unit area are increased according to high resolution, an area of each pixel is decreased. As a result, it is very difficult to form a storage capacitor in the pixel. On the other hand, a multi-structure type storage capacitor is introduced. However, a fabricating process for the multi-structure type storage capacitor is complicated such that production yield is reduced.
USPTO Backgrounds
USPTO Backgrounds