1. Field of the Invention
The disclosure relates generally to transistor devices and, more specifically, to Semiconductor-On-Insulator (SOI) transistors.
2. Description of the Related Art
Referring to FIG. 1, a conventional partially-depleted (PD) SOI field-effect transistor (FET) 10 is illustrated. The transistor 10 includes a source region 12 and a drain region 14 with a body 18 in between. A gate insulator 24 is positioned between a gate 16 and at least the body 18. Isolation regions 22 electrically isolate the transistor 10, and the transistor 10 is formed over a buried oxide/insulator layer 20, which is positioned over a silicon substrate (not shown).
In the PD SOI FET 10, a portion of the body region 18 above the buried oxide layer 20 is considered to be quasi-neutral, and the rest of the body region 18 is considered to be depleted. For an n-channel FET (nFET), this body region 18 is p-type. The body region 18 of a PD SOI device 10 is considered to be floating. The body region 18 is electrically isolated at the top by the gate insulator 24, at the bottom by the buried oxide layer 20, horizontally parallel to the direction of FET current flow or the channel length direction (as shown in FIG. 1) by the heavily doped n-type source and drain regions, and horizontally perpendicular the direction of FET current flow (not shown) by the isolation regions (e.g., shallow-trench isolation).
Whereas in bulk FETs, the device body is capable of being biased at an arbitrary voltage relative to the source region, with a typical PD SOI FET 10, the device body 18 is not tied to any voltage. As such, the device body 18 may acquire a voltage different than that of the source region 12. This characteristic is know as “floating-body effect” in a PD SOI FET 10, and in certain instances, has negative effects on the device 10 and the circuit in which the device 10 is positioned. Therefore, to minimize floating-body effect in a PD SOI FET 10, keeping the body voltage close to the source region voltage is desirable.
Many techniques for reducing floating-body effect in a PD FET have been proposed. One common technique involves providing an electrical connection to the device body by expanding the device body region and electrically connecting to the device body. Although this technique can control the device body voltage, the cost of this technique is significant due to larger device area and a larger associated parasitic capacitance.
Referring to FIG. 2, in a conventional PD SOI FET 10, the physical mechanism governing the device body voltage Vb is the net accumulation of majority charge in the quasi-neutral device body region 18. For an nFET 10, this is the accumulation of holes on the p-type device body region 18. For purposes of illustration, the PD SOI nFET 10 is assumed to have a gate voltage Vg and source region Vs of 0 volts. The drain region voltage is assumed to be at a positive voltage of Vdd. Assuming a gate voltage Vg of 0 volts, the FET 10 is in an off state.
With the FET 10 in the off state, no electron channel current flows directly from source region 12 to the drain region 14. Instead, the electron flow from the source region 12 to the drain region 14 is indirect. For example, electrons flow from the source n+ region 12 to the p-type device body 18, and electrons flow from the p-type device body 18 to the drain n+ region 14. With the drain region 14 at Vdd and the source region 12 at 0 volts, the device body 18 acquires a voltage Vb between 0 and Vdd. Thus, the drain-body diode 34 is reverse-biased while the source-body diode 32 is forward biased. The body voltage Vb is also the source-body forward bias voltage.
Associated with the reverse-biased body-drain diode 34 is a leakage current, which is caused by electrons flowing towards (and being collected by) the n+ drain region 14 and holes flowing towards (and being collected by) the p-type body region 18. In the forward-biased source-body diode 32, a forward-diode current is caused by electrons being injected from the n+ source region 12 into the p-type body 18 and holes being injected from the p-type body 18 into the n+ source region 12.
As holes are collected in the p-type device body 18, the body voltage Vb rises. However, as the body voltage Vb rises, the source-body diode 32 becomes more forward biased and the hole injection from the p-type body 18 into the n+ source 12 region increases. A steady state body voltage Vb is reached when the hole current flowing into the device body 18 on the drain side is balanced by the hole current flowing out of the device body 18 on the source side.
Referring to FIG. 3, the top portions 42, 44 of the source and drain regions 12, 14 are typically silicided to provide good electrical contact to the source and drain regions 12, 14. In the forward-biased source-body diode 32, the holes injected from the p-type body 18 into the n+ source region 12 recombine within the n+ region and at the silicide contact 42. That is, the hole current is a recombination current. The body voltage Vb rises when this recombination current is not large enough to prevent significant hole accumulation in the p-type body 18.
USPTO Backgrounds
USPTO Backgrounds