Technical Field
The present invention relates generally to semiconductor devices, and more specifically, to trench contact resistance reduction in semiconductor devices.
Description of the Related Art
Semiconductor device performance is dependent upon numerous factors, one being the total device resistance. The total device resistance is, in turn, a function of parameters such as contact resistance, wiring resistance, channel resistance, etc. Decreasing the total device resistance can improve device performance (i.e., improve device speed).
High contact resistance results in loss of performance, errors in data and increased heat and power loss, to name a few effects. Contact resistance in semiconductor devices increases dramatically with reduction in pitch scaling sizes. Smaller contact areas result in rapid increases in contact resistance. With nanometer scale structures, such as fins for fin field effect transistors, smaller three-dimensional structures present particular difficulties in forming suitable contact areas to make adequate electrical contact.
USPTO Backgrounds
USPTO Backgrounds