1. Field of the Invention
The present invention relates to a semiconductor memory device which has variably set data input-output terminals and control signal terminals for the same, in which there is a common supply of control signals regardless of the byte configuration of the data input-output terminals, so that variation in the data input-output timing and variation in the data mask timing according to the byte configuration is prevented.
2. Description of the Related Art
In semiconductor memory devices, there has been a proliferation of devices of various types with different memory cell structures, such as DRAM, SRAM, flash memories, ferroelectric memories and the like. These memory devices have different memory cell structures; however, addresses, data and commands such as read-write commands and the like are supplied from the outside, read data is output at a specified timing, and write data is similarly input.
Memory devices must have a configuration which can handle various types of data input-output terminal configurations such as a 4-bit configuration, 8-bit configuration, 16-bit configuration or the like in accordance with the configuration of the system in which the memory device is mounted. On the other hand, the design and production of separate memory devices for a plurality of different types of input-output bit configurations results in an increase in cost. Accordingly, such a cost increase is prevented by suing a common memory circuit, a common chip and a common package, and arranging the system to a plurality of different types of memory devices so that used and unused pins or used and unused data input-output terminals can be altered in accordance with the input-output bit configuration.
FIGS. 1, 2 and 3 are diagrams which illustrate the configurations of conventional memory devices. FIG. 1 shows a memory device in which the data input-output terminals have a 2-byte or 16-bit configuration, FIG. 2 shows a memory device in which the data input-output terminals have a 1-byte or 8-bit configuration, and FIG. 3 shows a memory device in which the data input-output terminals have a xc2xd-byte or 4-bit configuration. One of these memory devices is selected in accordance with the system in which the memory device is mounted.
In the figures, a chip 1 on which a memory circuit is formed is mounted in a package 2. In order to handle the three types of memory devices described above, the chip 1 has 16 data input-output terminals DQ0 to DQ7 and DQ8 to DQ15, and input-output buffers IO-BUF0 to IO-BUF15 that correspond to these data input-output terminals, and the package 2 has external pins P0 to P15. Furthermore, the chip 1 has strobe signal terminals STB0 and STB1 that control the data input-output timing, and corresponding input-output buffers IO-BUFS0 and IO-BUFS1 for each of the 8-bit (1-byte) data input-output terminal groups DQ0 to DQ7 and DQ8 to DQ15, and the package 2 also has corresponding external pins PS0 and PS1. Furthermore, the chip 1 has mask signal terminals MSK0 and MSK1 used to prohibit data input-output for each of the 8-bit (1-byte) data input-output terminal groups DQ0 to DQ7 and DQ8 to DQ15, and the package 2 also has corresponding external pins PS0 and PS1. The terminals of the chip and the external terminals of the package are connected by bonding wires 3.
In computer systems in which memory devices are mounted, data is generally processed in word units (1 byte or 8 bits). Accordingly, memory devices are also correspondingly constructed so that the timing control signals are utilized in respective data input-output terminal groups consisting of word units (1 byte or 8 bits).
In the case of the 16-bit configuration shown in FIG. 1, a strobe signal terminal STB0 and a mask signal terminal MSK0 are provided for the first data input-output terminal group DQ0 to DQ7, and a strobe signal terminal STB1 and mask signal terminal MSK1 are provided for the second data input-output terminal group DQ8 to DQ15. To describe the strobe signals STB0 and STB1, switches SW0 and SW1 are installed in strobe signal supply lines 10 and 20 that supply strobe signals to the respective data input-output buffers inside the chip 1; here, the switch SW0 is controlled to a conductive state, while the switch SW1 is controlled to a non-conductive state. As a result, the first strobe signal STB0 is supplied to the first data input-output buffer group IO-BUF0 to IO-BUF7, and the second strobe signal STB1 is supplied to the second data input-output buffer group IO-BUF8 to IO-BUF15. These switches are controlled by set signals L4, L8 and L16 generated by a latching circuit 4 which latches that data input-output terminal configuration.
Furthermore, the first mask signal MSK0 controls the writing operation of the write amplifier WA0-WA7 corresponding to the first data input-output signals DQ0 to DQ7, and the second mask signal MSK1 controls the writing operation of the write amplifier WA8-WA15 corresponding to the second data input-output signals DQ8 to DQ15.
Thus, strobe signals and mask signals are provided for each of the 8-bit data input-output terminal groups, so that the input-output buffers and write amplifiers of the respective subordinate data input-output terminal groups are controlled.
In the case of the 8-bit configuration shown in FIG. 2, as is indicated by the bonding wires 3, only the four bits DQ0, DQ2, DQ5 and DQ7 are used from the first data input-output terminal groups DQ0 to DQ7, and only the four bits DQ8, DQ10, DQ13 and DQ15 are used from the second data input-output terminal group DQ8 to DQ15. The other data input-output terminals are in an unused state, and the corresponding external pins P1, P3, P4, P6 and P9, P11, P12, P14 of the package are designated as NC pins. In this case, in accordance with the approach that control signals control each 8-bit data input-output terminal group, the first strobe signal terminal STB0 and the first mask signal terminal MSK0 are in an unused state, so that only the second strobe signal terminal STB1 and second mask signal terminal MSK1 are in a used state, and the second strobe signal STB1 and second mask signal terminal MSK1 are supplied to the input-output buffer circuits and write amplifier corresponding to the used 8-bit data input-output terminal group.
To describe the strobe signals, a first switch SW0 in the strobe signal supply lines 10 and 20 is controlled to a non-conductive state, while a second switch SW1 is controlled to a conductive state, so that the second strobe signal STB1 is supplied to the eight input-output buffer circuits IO-BUF that are in use. The mask signal MSK1 is also supplied to the write amplifiers WA0 to WA7 and WA8 to WA15 on both sides by a similar switching circuit.
In the case of the 4-bit configuration shown in FIG. 3, as is indicated by the bonding wires 3, only the two bits DQ2 and DQ5 are used from the first data input-output terminal group DQ0 to DQ7, and only the two bits DQ10 and DQ13 are used from the second data input-output terminal group DQ8 to DQ15. The other data input-output terminals are in an unused state. Furthermore, the first strobe signal terminal STB0 and mask signal terminal MSK0 are also in an unused state, so that the second strobe signal STB1 and mask signal MSK1 are supplied in common to the input-output buffer circuits and write amplifier corresponding to the data input-output signals of the abovementioned four bits.
Thus, switching is performed in accordance with the data input-output terminal configuration so that control signals such as strobe signals, mask signals and the like for the data input-output signals are used in common for data input-output signals in word units (8-bit units). As a result, the circuit corresponding to the first data input-output terminal group DQ0 to DQ7 is controlled by the first strobe signal STB0 and mask signal MSK0 belonging to this group in the case of a 16-bit configuration, but is controlled by the second strobe signal STB1 and mask signal MSK1 belonging to another group in the case of an 8-bit configuration or 4-bit configuration.
Accordingly, in the case of the 16-bit configuration, the strobe signal supply lines 10 and 20 are the same in the first and second data input-output terminal groups, so that the wiring length to the input-output buffer circuits corresponding to the respective terminal groups is relatively short.
However, in the case of the 8-bit configuration or 4-bit configuration, the second strobe signal STB1 belonging to the adjacent group is supplied to the first data input-output buffer group IO-BUF0-7. As a result, the length of the wiring that supplies the strobe signal STB1 to the first data input-output buffer group IO-BUF0-7 is longer than the length of the wiring that supplies this strobe signal to the second data input-output buffer group IO-BUF8-15.
Accordingly, skewing is generated in the input-output timing between the first data input-output signal group DQ0-DQ7 and the second data input-output signal group DQ8-DQ15. In cases where the memory device operates using strobe signals with a relatively low frequency, the occurrence of such skewing does not lead to erroneous operation; however, in the case of high-speed memory devices which operate using high-frequency strobe signals, there is a possibility that such skewing will cause erroneous operation.
The same problem occurs in the case of the mask signals. Specifically, in the case of an 8-bit configuration or 4-bit configuration, the length of the wiring supplying the mask signals becomes non-uniform, so that skewing occurs in the mask signals sent to the respective write amplifiers. When the operating cycle of the memory device is short, there is no margin in the timing at which masking is to be performed by the mask signals; accordingly, skewing of the abovementioned mask signals leads to erroneous operation.
Furthermore, in conventional constructions, switching circuits are installed in the supply wiring of the strobe signals and mask signals; accordingly, the wiring structure is complicated. Moreover, since the strobe signal terminals and mask signal terminals may be in an unused state depending on the type of product, the memory controller must control the supply or non-supply of these control signals in accordance with the type of product involved, so that control becomes complicated.
Accordingly, it is an object of the present invention to provide a semiconductor memory device that can prevent variation in the operational timing caused by skewing of the control signals that control the data input-output signals.
Furthermore, another object of the present invention is to provide a semiconductor memory device in which the configuration relating to control signals that control the data input-output signals is devised as common as possible in different types of products.
In order to achieve the abovementioned objects, one aspect of the present invention is a memory circuit comprising M (M is a plurality) data input (or output) terminal groups, each of which has N (N is a plurality, e.g., 8 bits) data input (or output) terminals, with control signal terminals for the data input (or output) being provided for each data input (or output) terminal group, wherein this circuit has at least N controlled circuits for the data input (or output) signals in each data input (or output) terminal group, and control signal supply wirings each of which supplies intra-group control signal to these N controlled circuits. In accordance with a data configuration control signal that controls the use or non-use of the data input (or output) terminals, the memory circuit is controlled to a first data input (or output) configuration in which a controlled data unit with a specified number of bits is constructed by a single data input (or output) terminal group, or a second data input (or output) configuration in which the controlled data unit is constructed by a plurality of data input (or output) terminal groups. Furthermore, control signals belonging to the respective data input (or output) terminal groups are supplied to (or utilized in) the controlled circuits of these data input (or output) terminal groups regardless of whether the configuration used is the first or second data input (or output) configuration.
Accordingly, in cases where the controlled data unit straddles a plurality of data input (or output) terminal groups as in the second data input (or output) configuration, the controlled circuits of the plurality of data input (or output) terminal groups are controlled by a plurality of control signals respectively. Of course, in cases where the controlled data unit is constructed within a single data input (or output) terminal group as in the first data input (or output) configuration, a plurality of controlled circuits for the controlled data unit are controlled by a single control signal.
In a preferred embodiment, the control signals are strobe signals that control the timing of data input (or output), and the controlled circuits are data input (or output) buffers.
Furthermore, in another preferred embodiment, the control signals are mask signals that prohibit a writing operation by invalidating write data, and the controlled circuits are write circuits.
Furthermore, in another preferred embodiment, the control signals are mask information signals that designate cycles in which write data is invalid, and mask signals are formed from these mask information signals. Moreover, the controlled circuits are write circuits, e.g., write amplifiers.
USPTO Backgrounds
USPTO Backgrounds