1. Field of the Invention
The present invention relates to a technique of utilizing a master slice approach and, more particularly, to a semiconductor integrated circuit device and a method of producing the device using the master slice approach.
A semiconductor integrated circuit or large scale integrated circuit device produced through the master slice approach is hereinafter referred to as a master slice type LSI device.
2. Description of the Related Art
The master slice approach generally comprises a first process of forming a master chip and a second process of forming a desired wiring pattern on the master chip. In the first process, a basic cell region including a plurality of basic cells, each consisting of a predetermined number of transistors, is formed together with an input/output (I/O) cell region on a chip using a common and fixed pattern mask. The second process is carried out in accordance with a specification or conditions demanded by a user and includes a plurality of steps.
In this case, the second process normally includes four steps of: forming contact holes in a first insulation layer formed on the master chip; forming thereon a first wiring Layer; forming through holes in a second insulation layer formed thereon; and forming thereon a second wiring layer so as to contact the first wiring layer via through holes. Therefore, four pattern masks corresponding to the contact hole, first wiring layer, through hole and second wiring layer are required to constitute a given circuit in the basic cell region.
To cope with the above drawbacks, a so-called one custom mask approach has been recently adopted in the wiring patterning process. This one custom mask approach is a method of forming a wiring pattern on the master chip using one layer custom mask (wiring pattern mask according to user's specification). According to the one custom mask approach, since the wiring: pattern mask can be made common to a plurality of master slice type LSI devices, it becomes possible to easily realize the reduction of the turnaround time and the simplification of the process.
USPTO Backgrounds
USPTO Backgrounds