In the fabrication of semiconductor integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip. There are various ways of doing this. One way is by using the well-known LOCOS (Local Oxidation Of Silicon) process, wherein the surface of the chip is masked with a relatively hard material such as silicon nitride and a thick oxide layer is grown thermally in an opening in the mask. Another way is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide, also known as trench isolation. While both LOCOS and trench isolation can prevent unwanted surface conduction between devices, they do not facilitate complete electrical isolation.
Complete electrical isolation is necessary to integrate certain types of transistors including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors including power DMOS transistors. Complete isolation is also needed to allow CMOS control circuitry to float to potentials well above the substrate potential during operation. Complete isolation is especially important in the fabrication of analog, power, and mixed signal integrated circuits.
Although conventional CMOS wafer fabrication offers high density transistor integration, it does not facilitate complete electrical isolation of its fabricated devices. In particular, the NMOS transistor contained in conventional CMOS fabricated in a P-type substrate has its P-well “body” or “back-gate” shorted to the substrate and therefore cannot float above the substrate potential. This restriction is substantial, preventing the use of an NMOS transistor as a high-side switch, an analog pass transistor, or as a bidirectional switch. It also makes current sensing more difficult and often precludes the use of integral source-body shorts needed to make NMOS devices more avalanche rugged.
Moreover since the P-type substrate in conventional CMOS is biased to the most negative on-chip potential (defined as “ground”), every NMOS device is necessarily subjected to unwanted substrate noise.
The need for complete electrical isolation is described in detail in related application Ser. No. 11/298,075, entitled “Isolation Structures For Semiconductor Integrated Circuit Substrates And Methods Of Forming The Same,” filed Dec. 9, 2005, by R. K. Williams et al., which is incorporated herein by reference in its entirety.
Conventional Isolated Process Technologies
Complete electrical isolation of integrated devices is typically achieved using triple diffusions, epitaxial junction, or dielectric isolation. The most common form of complete electrical isolation is junction isolation. While not as ideal as dielectric isolation where oxide surrounds each device or circuit, junction isolation has historically offered the best compromise between manufacturing cost and isolation performance.
With junction isolation, electrically isolating CMOS requires a complex structure requiring the growth of an N-type epitaxial layer atop a P-type substrate surrounded by an annular ring of deep P-type isolation electrically connecting to the P-type substrate to completely isolate an N-type epitaxial island by P-type material below and on all sides. Growth of epitaxial layers is slow and time consuming, representing the single most expensive step in semiconductor wafer fabrication. The isolation diffusion is also expensive, formed using high temperature diffusion for extended durations (up to 18 hours). To be able to suppress parasitic devices, a heavily doped N-type buried layer NBL must also be masked and selectively introduced prior to epitaxial growth.
To minimize up-diffusion during epitaxial growth and isolation diffusion, a slow-diffusing dopant such as arsenic (As) or antimony (Sb) is chosen to form the N-type buried layer (NBL). Prior to epitaxial growth however, this NBL layer must be diffused sufficiently deep to reduce its surface concentration, or otherwise the concentration control of the epitaxial growth will be adversely impacted. Because the NBL is comprised of a slow diffuser, this pre-epitaxy diffusion process can take more than ten hours.
Only after isolation is complete can conventional CMOS fabrication commence, adding considerable time and complexity to the manufacturing of junction-isolated processes compared to conventional CMOS.
Since junction isolation fabrication methods rely on high-temperature processing to form deep-diffused junctions and to grow epitaxial layers, these high-temperature processes are expensive and difficult to manufacture, and are incompatible with large diameter wafer manufacturing, exhibiting substantial variation in device electrical performance and preventing high transistor integration densities. Another disadvantage of junction isolation is the area wasted by the isolation structures and otherwise not available for fabricating active transistors or circuitry. As a further complication, with junction isolation, the design rules (and the wasted area) depend on the maximum voltage of the isolated devices. Obviously, conventional epitaxial junction isolation, despite its electrical benefits, is too area-wasteful to remain a viable technology option for mixed signal and power integrated circuits.
The limitations of conventional junction isolation are described in greater detail in the aforementioned application Ser. No. 11/298,075.
An Epi-less Fully-Isolated BCD Process with Contouring Implants
As disclosed in U.S. Pat. Nos. 6,855,985, 6,900,091 and 6,943,426 by Richard K. Williams, et. al., each of which is incorporated herein by reference, a fully-isolated process integrating CMOS, bipolar and DMOS transistors can be achieved without the need for high temperature diffusions or epitaxy. The principle of this modular BCD process relies on high-energy (MeV) ion implantation through contoured oxides to produce self-forming isolation structures with virtually no high-temperature processing required. The principle of conformal ion implantation through contoured oxides is the concept that by implanting through a thicker oxide layer dopant atoms will be located closer to the silicon surface and by implanting through a thinner oxide layer, the implanted atoms will be located deeper in the silicon, away from the surface. This low-thermal budget process benefits from “as-implanted” dopant profiles that undergo little or no dopant redistribution since no high-temperature processes are employed.
Dopants, implanted through LOCOS field oxide, form conformal isolation structures that in turn are used to enclose and isolate multi-voltage CMOS, bipolar transistors and other devices from the common P-type substrate. The same process is able to integrated bipolar transistors, and a variety of double-junction DMOS power devices, all tailored using conformal and chained-ion implantations of differing dose and energy.
While this epi-less low thermal budget technique has many advantages over non-isolated and epitaxial junction isolated processes, its reliance on LOCOS imposes certain limitations on its ability to scale to smaller dimensions and higher transistor densities.
To improve CMOS transistor integration density, the well-known bird's beak taper that appears at the edges of LOCOS structures must be reduced into a more vertical structure so that the devices can placed more closely for higher packing densities. A narrow LOCOS bird's beak, however, causes the width of the isolation sidewall to become unacceptably narrowed and isolation quality to be sacrificed. At dimensions much larger than photolithographic limitations, other practical limitations of LOCOS become manifest. Such limitations include distorted field oxide shapes, excessive oxide thinning, high stress, high surface state charge, poor quality gate dielectrics and more.
What is needed is new strategy for implementing a fully-isolated, low-thermal-budget, epi-less integrated circuit process, that eliminates the aforementioned limitations of LOCOS.
USPTO Backgrounds
USPTO Backgrounds