Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A typical flash memory device is a type of memory in which the array of memory cells is typically organized into memory blocks that can be erased and reprogrammed on block-by-block basis instead of one byte at a time. Changes in a threshold voltage of each of the memory cells, through erasing or programming of a charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure.
The memory array can be organized in many different architectures including NAND and NOR. In a NAND architecture memory device, the memory blocks can be organized as series strings of memory cells, such as illustrated in FIG. 1.
The array comprises an array of non-volatile memory cells 101 arranged in columns such as series strings 104, 105. The cells 101 are coupled drain to source in each series string 104, 105. An access line (e.g., word line) WL0-WL31 that spans across multiple series strings 104, 105 is coupled to the control gates of each memory cell in a row in order to bias the control gates of the memory cells in the row. Data lines, such as even/odd bit lines BL_E, BL_O, are coupled to the series strings and eventually coupled to sense circuitry, as described subsequently, that detect the state of each cell by sensing current or voltage on a selected bit line.
Each series string 104, 105 of memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line BL_E, BL_O by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
As a result of capacitive coupling from neighboring memory cells, the threshold voltages of the memory cells in an even page (e.g., even bit line) depend on whether the memory cells of the neighboring odd page (e.g., odd bit line) have been programmed. When a sense operation is performed on an even page, the memory device does not know whether the odd page has been programmed. In order to compensate for the uncertain state of the neighboring cells, the sense operation is performed with an extra threshold voltage margin. This can result in a reduced number of read threshold voltage margins within a limited threshold voltage window.
For the reasons stated above, and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce threshold voltage windows during a sense operation.
USPTO Backgrounds
USPTO Backgrounds