The present invention relates to a semiconductor memory device having memory cells, and particularly, to a semiconductor memory device having memory cell arrays divided longitudinally and laterally into four core sections.
To reduce operational currents of a semiconductor memory device, memory cell arrays are dispersively activated. In recent years, to further reduce operational currents, all memory cell arrays are divided into two groups, one of the two groups is selected, and memory cell arrays belonging to the selected group are dispersively activated.
FIG. 1 shows a structure of a conventional semiconductor memory device. In the following, same components are denoted by same reference symbols, and reiteration of those components will be omitted.
Core sections 1 to 4 generally have equal memory capacities. The core sections 1, 2, 3 and 4 are respectively positioned at the upper left, lower left, upper right, and lower right of a chip CP.
An address buffer 11 is provided at an area between the core sections 3 and 4, for example. The address buffer 11 is supplied with external address signals A0 to A11 from a pad in the chip CP and generates control signals RAt11 and RAc11 from, for example, an address signal A11.
Core section buffers 5 to 8 are arranged adjacent to the core sections 1 to 4, respectively. The core section buffers 5 and 6 are supplied with a control signal RAt11 outputted from the address buffer 11, and the core section buffers 7 and 8 are supplied with a control signal RAc11 outputted from the address buffer 11. The core section buffers 5 to 8 respectively activate the core sections 1 to 4 in accordance with the control signals RAt11 and RAc11.
Each of the core sections 1 to 4 comprises a plurality of memory cell arrays 10, sense amplifiers 90 connected to the memory cell arrays 10, and circuits (not shown) for selecting memory cells in accordance with a signal, such as an array decoder and a row decoder. As shown in FIG. 1, the memory cell arrays 10 and sense amplifiers 9 are disposed alternately, and each of the sense amplifiers 9 is shared by two memory cell arrays 10. The array decoder selects one or more memory cell arrays in a core section to be activated by an instruction, in accordance with an upper bit of an address signal supplied through a core section buffer. The row decoder selects a word line of the memory cell array selected by the array decoder, in accordance with a lower bit of an address signal supplied through a core section buffer.
Peripheral circuits 12 such as row decoders and column decoders described above are provided between the core sections 1 and 2, 3 and 4, 1 and 3, as well as 2 and 4.
A plurality of pads 50 are provided at the areas where the peripheral circuits 12 are provided such that the pads are disposed laterally, for example. A part of the pads are used as power supply pads.
The following will be an explanation of a method of activating memory cell arrays divided into four core sections.
An address buffer 11 generates control signals RAt11 and RAc11 relating to rows, from a bit A11 of an external address signal. The control signal RAc11 is an inverted signal of the control signal RAt11. In the following, "c" indicates an inverted signal and "t" indicates a non-inverted signal.
Where the signal RAt11 is of a selected state and the signal RAc11 is of a non-selected state, the upper left core section 1 and the lower left core section 2 are selected. In this state, the upper right core section 3 and the lower right core section 4 are not selected and deactivated.
Further, memory cells of each of the selected core sections 1 and 2 are divided into two groups, and memory cells belonging to one of the groups are activated in accordance with an upper address of the address signal. FIG. 1 shows a semiconductor memory device in this state. In the figure, those memory cell arrays 10 and sense amplifiers 9 which are hatched by oblique lines indicate activated arrays and sense amplifiers.
Where the signal RAt11 is of a non-selected state and the signal RAc11 is of a selected state, the memory cells of the upper right core section 3 and the lower right core section 4 are activated.
When a bit line is charged or discharged by sense amplifiers, e.g., when the potential of a bit line is changed from 1/2.times.Vcc to Vcc or Vss, noise is generated by the switching operation of a transistor for connecting a sense amplifier with a bit line.
In a conventional semiconductor memory device, activated cell arrays are concentrated at the left or right half of the semiconductor memory device. When the core sections 1 and 2 are activated, noise is generated concentrically in the left half of the semiconductor memory device. When the core sections 3 and 4 are activated, noise is generated concentrically in the right half of the semiconductor memory device.
The noise thus generated is reflected on power supply lines or the like and influences the operation of input pins and peripheral circuits in the vicinity of the activated core sections. Specifically, the potential of power supply lines supplied with a voltage Vss rises thereby hindering supply of a Vss level. As a result, threshold voltages and the like of elements forming sense amplifiers and peripheral circuits are changed, and associated circuits cause operation errors.
In FIG. 2, it is supposed that a power supply pad 13 supplied with a voltage Vss is provided in the left side of an area between the core sections 1 and 2, and a power supply pad 14 supplied with a voltage Vcc is provided in the right side of an area between the core sections 3 and 4. FIG. 2 shows a case where the core sections 3 and 4 are activated and arrows in this figure indicate main flows of currents to a power supply pad.
Power supply lines from the power supply pad 13 to the core sections 3 and 4 are longer than power supply lines from the power supply pad 13 to the core sections 1 and 2. Therefore, a voltage drop caused in the power supply lines is large when the core sections 3 and 4 are activated. An influence from the voltage drop in the power supply lines when the core sections 3 and 4 are activated is therefore greater than that when the core sections 1 and 2 are activated.
In FIG. 3, it is supposed that a power supply pad pair 15 respectively supplied with voltages Vcc and Vss is provided in the left side of an area between the core sections 1 and 2, and another power supply pad pair 16 respectively supplied with voltages is provided in the right side of an area between the core sections 3 and 4. Arrows in this figure indicate main flows of currents to the power supply pads.
In this case, a length of power supply lines from the left power supply pad pair 15 to the core sections 1 and 2 are substantially the same as that of the power supply lines from the right power supply pad pair 16. Therefore, unlike the example shown in FIG. 2, an influence from a voltage drop does not vary much depending on the positions of activated core sections.
However, when the core sections 1 and 2 are activated, currents concentrically flow through the left power supply pad pair 15. When the core sections 3 and 4 are activated, currents concentrically flow through the right power supply pad pair 16.
Generally, a semiconductor chip is sealed on a lead frame by resin and pads such as power supply pads are connected to inner leads by bonding wires thereto. A packaged semiconductor device is set on a board and outer leads are connected to wires on the board. Therefore, a pad supplied with a voltage Vss is applied with inductance from the lead frame and the wires on the board. Where L is the inductance applied to the power supply pad, noise is expressed as L.times.di/dt. Therefore, as described above, large noise is generated by the inductance when a current concentrically flows through one pair of power supply pads.
Thus, power supply noise caused by resistance or inductance reaches such a level that significantly influences the operation of circuits.
USPTO Backgrounds
USPTO Backgrounds