An example of a dynamic random access memory voltage mismatch compensated sense amplifier can be found in IEEE JSSC, Vol. 25, No. 7, July 1993 "A High Speed, Small-Area-Threshold Voltage Mismatch Compensation Sense Amplifier for Gigabit-Scale DRAM Arrays", which is hereby incorporated by reference in its entirety.
Such a conventional approach is suitable for Dynamic Random Access Memory (DRAM) arrays, but not as desirable for Static Random Access Memory (SRAM) arrays. Another example of a dynamic random access memory voltage mismatch compensated sense amplifier can be found in "Threshold Difference Compensated Sense Amplifier", Shunichi Suzuki and Masaki Hirata, JSSC, Vol. SC-14, No. 6, December 1979 is also incorporated by reference in its entirety.
FIG. 1 shows a conventional uncompensated static random access memory sense amplifier circuit 10. Such an approach has one or more of the following disadvantages: (i) no mismatch compensation; (ii) the bitline delta (i.e., differential) required for sensing is 5*94(.DELTA.Vt)=60 mV for many current SRAM designs; and/or (iii) 60 mV corresponds to a 0.5 ns to 1 ns longer access time for many SRAM designs. The following equation defines the sense voltage in the conventional circuit: ##EQU1##
where n=5 for memories of devices 2MEG, 4MEG, 8MEG, n is the number of standard deviations (as defined in the field of statistics) which is required to achieve a certain manufacturing yield and is related to the number of placements of the circuit in question that exist on a given chip, typically 1,000-4,000. W and L are the channel length and width of the sense devices 16, 18 in FIG. 1. A.sub.VTD is a constant established by experiment/experience.
The circuit 10 generally comprises a transistor 12, a transistor 14, a transistor 16, a transistor 18 and a transistor 20. A bitline BL may be connected to the transistor 12. A bitline BLB may be connected to the transistor 14. The signal STROBE may be presented to a gate at the transistor 12, a gate at the transistor 14 and a gate at the transistor 20. The circuit 10 illustrates an example of a conventional SRAM sense amplifier approach and has the disadvantages mentioned.
USPTO Backgrounds
USPTO Backgrounds