In order to reduce the power consumption of a semiconductor device, circuits that do not need to operate are stopped by power gating or clock gating. A flip-flop (FF) is a sequential circuit (storage circuit that holds a state) included a lot in a semiconductor device. Thus, a reduction in power consumption of the FF leads to a reduction in power consumption of a semiconductor device including the FF. When a general FF is powered off, a state (data) held therein is lost.
By taking advantage of extremely low off-state current of a transistor whose semiconductor region is formed using an oxide semiconductor (hereinafter, such a transistor may be referred to as an OS transistor), a retention circuit capable of retaining data even when powered off has been proposed. For example, Patent Documents 1 to 3 each disclose an FF that includes a retention circuit including an OS transistor and enables power gating. Non-Patent Document 1 discloses power gating of a processor by using a retention circuit that includes an OS transistor for each of an FF and an SRAM, for example.
USPTO Backgrounds
USPTO Backgrounds