1. Field of the Invention
The present invention relates to an adjusting circuit for an ultrasonic delay line and an ultrasonic delay line device containing such an adjusting circuit.
2. Discussion of Background
FIGS. 8 and 9 show respectively adjusting circuits for delay time adjustment in a conventional ultrasonic delay line. In the embodiments as shown in FIGS. 8 and 9, fixed resistors R1, R2, fixed coils L1, L2 and variable coils T1, T2 are used for a matching circuit in a circuit formed between input terminals 1, 1' and output terminals 2, 2' for an ultrasonic delay line DL. Adjustment of delay time is conducted by changing the inductances of the variable coils T1, T2. There is also known a circuit as shown in FIG. 10 which is disclosed in Japanese Utility Model Publication No. 64118/1988 as another conventional example. FIG. 10 shows a delay line DL formed between input terminals 1, 1' and output terminals 2, 2', having a input circuit formed by a resistor R1 disposed between input terminal 1 and a series connection of a parallel-connected coil L1 and capacitor and C1 with a variable resistor Vr, and having an output circuit consisting of the parallel connection of on a coil L2 and a resistor R2. The circuit consisting of resistors R1 and R2 and a fixed coil L2 is used for impedance matching between an outer circuit and an ultrasonic delay line. The delay time of the ultrasonic delay line is adjusted by adjusting the semi-fixed resistor VR.
A change of the resistance value of the semi-fixed resistor VR causes a change of the quantity of a signal which is fed to the input terminals through the fixed coil L1 and the fixed capacitor C1 so that it influences the delay time of the circuit of the fixed coil L1 and the fixed capacitor C1.
The variable length of the delay time is primarily determined by the values of the fixed coil L1 and the fixed capacitor C1. Namely, the impedance value of the parallel circuit of the fixed coil L1 and the fixed capacitor C1 becomes substantially infinite, causing a parallel resonance, in the vicinity of .omega.L1-1/(.omega.C1)=0 (where .omega.=2.pi.f, f being the central frequency of the ultrasonic delay line, i.e. 3.579545 MHz, L1=6.8 .mu.H, and C1=270 pF). At this point, the variable length of the delay time becomes substantially zero, whereby adjustment of the delay time becomes impossible (FIG. 3).
Thus, in the determination of the values of the fixed coil L1 and the fixed capacitor C1, it is necessary to avoid the disadvantage caused by the above-mentioned combination, which is a problem in designing a delay line. A more detailed description of the operation of the circuit shown in FIG. 10 is provided in Publication No. 64118/1988.
The conventional delay lines using such adjusting circuits had problems that there was a restriction in designing a circuit, in particular, in designing a pattern of printed wiring on a substrate since the size of a variable coil was large in comparison with other circuit elements such as a fixed coil, a fixed resistor, a fixed capacitor, a trimmer potentiometer and so on, the variable coil had a larger number of terminals, had a large height, was expensive and took much time because of custom-made production.
In the circuit of a conventional type as shown in FIG. 10, there was a problem that a delay time width to be changed was small, especially, the changeable delay time width was nearly zero depending on selection of the constants of a capacitor C1 and a fixed coil L1. In this case, it was almost impossible to adjust the delay time even by adjusting a variable resistor Vr.
USPTO Backgrounds
USPTO Backgrounds