A recent development in integrated circuit testing is the use of the JTAG (Joint Test Action Group) test port for in situ testing of integrated circuit chips mounted on a circuit board. The JTAG standard has been adopted by the Institute of Electrical and Electronics Engineers and is now defined as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated herein by reference. The IEEE Standard 1149.1 is explained in C. M. Maunder and R. E. Tulloss, "Test Access Port and Boundary-Scan Architecture" (IEEE Computer Society Press, 1990) which is also incorporated herein by reference.
In the JTAG scheme, a four (or optional five) signal Test Access Port (TAP) is added to each chip or grouping of chips on a board. The TAP includes four inputs: a test clock (TCK), a test mode select (TMS), a test data in (TDI), and an optional test reset (TRSTN). In addition, there is one output, a test data output (TDO). TDI and TDO are daisy-chained from chip to chip, whereas TCK and TMS are broadcast.
The TCK input is independent of the system clocks for the chip so that test operations can be synchronized between different chips. JTAG testing may be used to test suitably configured integrated circuits to verify operability. The operation of the test logic is controlled by the sequence of signals applied at the TMS input. The TDI and TDO are serial data input and output, respectively while TRSTN input is used to intitialize a chip or circuit to a known state. The features in the JTAG Standard provide for accessing any type of scan elements serially without requiring any more pins than the five JTAG pins, TCK, TMS, TDI, and TRSTN. This results in a single long scan chain for a chip.
USPTO Backgrounds
USPTO Backgrounds