1. Field of the Invention
The present invention relates to a phase detector circuit and method, and more particularly to a phase detector circuit and method, which have a reduced variation in a phase offset caused by variations in an input signal and external conditions.
2. Description of the Related Art
A delay locked loop (DLL) or a phase locked loop (PLL) includes a phase detector for detecting a phase difference between an internal clock signal and an external clock signal provided thereto. The delay locked loop (DLL) is used in memory devices such as a synchronous dynamic random access memory (SDRAM).
Generally, the semiconductor device operates at a frequency higher than a frequency of an external clock signal so that the semiconductor device generates the internal clock signal having a frequency higher than that of the external clock signal. During the process, a phase error from the desired clock signal may be generated. Therefore, in a digital signal transmission using binary coded clock signals, a logic value (for example, low logic level or high logic value) of the input signal should be determined.
The phase detector is used to detect the phase error, that is, a phase difference between two input signals, to generate a clock signal corresponding to the phase difference. Two input signals include a reference signal and a remaining signal. One of the two input signals may be used as the reference signal and be compared with the remaining signal. The clock signal generated when the remaining signal transitions earlier than the reference signal has an inverted phase with respect to that of the clock signal generated when the reference signal transitions earlier than the remaining signal.
FIG. 1 is a waveform diagram illustrating operation of a phase detector.
The phase detector in FIG. 1 is used to detect the phase difference between two received frequencies. With reference to the waveform shown in FIG. 1, a phase detection signal having a pulse width dependent on the phase difference between the two input signals (reference signal and feedback output signal) is outputted. While the magnitude of the pulse is invariable, the pulse width of the phase detection signal is varied according to the phase difference between the two input signals. Additionally, the sign of the phase detection signal is reversed when a sequence of a signal transition (for example, rising transition) for the two input signals changes. Thus, a quantitative amount of phase difference between a present output signal and a desired output signal may be detected.
FIG. 2 is a block diagram illustrating a conventional phase detector.
Referring to FIG. 2, the conventional phase detector receives an input signal IN and an inverted input signal INB and detects a phase difference between the input signal IN and a clock signal CLK to generate a phase detection signal OUT and an inverted phase detection signal OUTB.
FIG. 3 is a circuit diagram illustrating the conventional phase detector.
Referring to FIG. 3, the conventional phase detector includes a differential amplifier 310, an output load latch 320 and an output latch 330.
The differential amplifier 310 differentially amplifies a phase difference between a first node ND1 and a second node ND2. When a clock signal CLK has a logic low level, voltages at the first and second nodes ND1 and ND2 are forced to high voltage levels by a power supply voltage. When the clock signal CLK has a logic high level, an NMOS transistor N0 of the differential amplifier 310 is turned on. Based on the input signal IN and the inverted input signal INB, either an NMOS transistor N1 or an NMOS transistor N2 is turned on so that a predetermined potential difference is applied between the first and second nodes ND1 and ND2.
The output load latch 320 includes a first CMOS inverter 322 connected to the first node ND1 and a second CMOS inverter 324 connected to the second node ND2. An output voltage Vo of the first CMOS inverter 322 is applied to the second CMOS inverter 324 and an output voltage Vob of the second CMOS inverter 324 is applied to the first CMOS inverter 322. Thus, the first and second CMOS inverters 322 and 324 are cross-coupled to each other.
In the case in which the clock signal CLK has a logic high level, the first CMOS inverter 322 outputs the voltage Vo having a logic low level when the input signal IN has a logic high level. The voltage Vo having a logic low level is applied to a gate electrode of a PMOS transistor P0 of the second CMOS inverter 324, thereby turning on the PMOS transistor P0. Therefore, the output voltage Vob having an increased voltage level is outputted from the second CMOS inverter 324 and provided to the output latch 330.
In the case in which the clock signal CLK has a logic high level, the second CMOS inverter 324 outputs the voltage Vob having a logic low level when the inverted input signal INB has a logic high level. The voltage Vob having a logic low level is applied to a gate electrode of a PMOS transistor P1 of the first CMOS inverter 322, thereby turning on the PMOS transistor P1. Therefore, the output voltage Vo having an increased voltage level is outputted from the first CMOS inverter 322 and provided to the output latch 330. The output voltage Vo of the first CMOS inverter 322 and the output voltage Vob of the second CMOS inverter 324 are provided to the output latch 330. Since the input signal IN and the inverted signal INB are concurrently inputted to the first and second CMOS inverters 322 and 324, respectively, the output voltages Vo and Vob of the first and second CMOS inverters 322 and 324 have logic levels opposite to each other when the clock signal CLK has a logic high level.
The output latch 330 latches the output voltages Vo and Vob provided from the first and second CMOS inverters 322 and 324. Particularly, the output latch 330 includes two NAND gates 332 and 334 that are cross-coupled to each other. That is, an output of the NAND gate 332 is provided to the NAND gate 334 and an output of the NAND gate 334 is provided to the NAND gate 332. The output latch 330 latches the output voltage Vo of the first CMOS inverter 322 and the output voltage Vob of the second CMOS inverter 324 to provide phase detection signals OUT and OUTB.
FIG. 4 is an exemplary logic circuit illustrating the conventional phase detector of FIG. 3.
Referring to FIG. 4, the conventional phase detector includes a NAND gate 410 and a NAND gate 420. The NAND gate 410 receives the clock signal CLK, the input signal IN and an output VOB of the NAND gate 420. The NAND gate 420 receives the clock signal CLK, the inverted input signal INB and an output VO of the NAND gate 410. The conventional phase detector further includes a NAND gate 430 and a NAND gate 440. The NAND gate 430 receives the output VO of the NAND gate 410 and an output OUTB of the NAND gate 440, and the NAND gate 440 receives the output VOB of the NAND gate 420 and an output OUT of the NAND gate 430. That is, the NAND gates 410 and 420 are cross coupled to each other and the NAND gates 430 and 440 are cross coupled to each other.
When the clock signal CLK has a logic low level, the outputs Vo and Vob of the NAND gates 410 and 420 constantly have logic high levels. The NAND gates 430 and 440 latch the logic levels of the outputs Vo and Vob and output the logic values of the outputs Vo and Vob stored at a previous clock as the phase detection signals OUT and OUTB, respectively.
When the clock signal CLK has a logic high level, the voltage levels of the output voltages Vo and Vob are determined based on the logic levels of the input signal IN and the inverted input signal INB in the same manner as described above in FIG. 3. The voltage levels of the output voltages Vo and Vob are provided to the NAND gates 430 and 440, respectively, to generate the phase detection signals OUT and OUTB.
When the phase detector circuit is used in the delay locked loop (DLL), an offset should be extremely small and less sensitive to variations of the input signal and external conditions so as to prevent reduction in yield and degradation in performance. However, the conventional phase detector circuit causes the variation in the output signals OUT and OUTB according to the variation in the input signals IN and INB when the clock signal CLK transitions from a logic low level to a logic high level or vice versa.
In addition, when the transition of the input signal occurs concurrently with the transition of the clock signal CLK, the variation of the output signal of the phase detector becomes unpredictable.
In addition, the output signal of the phase detector may be varied according to a threshold voltage of the input signal due to the sensitivity to variations in manufacturing process, temperature, operating voltage, etc.
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