1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device, and more particularly, to a circuit for selecting a power supply voltage that may be easily tested and a semiconductor device having the same.
2. Description of the Related Art
A conventional semiconductor memory device may require one or more power supply voltages, for example, an internal power supply voltage for a peripheral circuit, an internal power supply voltage for a memory array, a plate voltage applied to a plate of a memory cell, a precharge voltage for precharging a bit line sense amplifier, and a back bias voltage for a semiconductor substrate back bias.
To test these power supply voltages, conventionally, a pad may be provided within a semiconductor chip for each of the power supply voltages. The pads in the semiconductor chip may perform a function of connecting an internal part of a semiconductor chip to an external device. The pad of the semiconductor chip may be coupled to a lead frame of a package and/or a printed circuit board (PCB) by a coupling method. For example, a wire bonding may be performed during a packaging process for the semiconductor chip. As a result, the pad may be electrically connected to a pin and/or ball of the package.
As high-density integration technology of semiconductor devices is developed, more devices may be mounted on a small-size chip. However, as semiconductor devices require higher degrees of integration, higher performance and a greater number of test items, the number of pads mounted in a chip may also increase.
Further, an area, which may be occupied by the increased number pads in the semiconductor chip, may be difficult to reduce because there are generally limits as to how much the pad size may be reduced.
USPTO Backgrounds
USPTO Backgrounds