Field of the Invention
The present disclosure relates to a shift register, and more particularly, to a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage.
Discussion of the Related Art
A shift register outputs a plurality of scan pulses in order to sequentially drive gate lines of a display device, such as a liquid crystal display. To this end, the shift register includes a plurality of switching devices therein. An oxide semiconductor transistor may be employed as such a switching device.
FIG. 1 is a view illustrating relational characteristics between gate voltage and drain current of a conventional oxide semiconductor transistor based on temperature.
For an N-type oxide semiconductor transistor used in a shift register, it is preferable that a threshold voltage thereof have a positive value. However, as temperature increases, the threshold voltage of the oxide semiconductor transistor moves negatively, as shown in FIG. 1. For this reason, the N-type oxide semiconductor transistor, which has to be turned off in an output period of the shift register, may not be normally turned off at a high temperature, thereby generating leakage current. This leakage current may lower a voltage at a set node, resulting in a problem that the output of the shift register is not normally generated.
FIG. 2 is a view illustrating a voltage at a set node and a voltage of a scan pulse based on a variation in a threshold voltage of a conventional oxide semiconductor transistor.
As can be seen from FIG. 2(a), when the threshold voltage of the oxide semiconductor transistor is −1, the voltage at the set node rapidly falls due to leakage current of the oxide semiconductor transistor, so that the voltage of the scan pulse, which is an output of a shift register, rapidly falls too.
Also, as can be seen from FIG. 2(b), when the threshold voltage of the oxide semiconductor transistor is −3, the leakage current of the oxide semiconductor transistor increases still further, so that the voltage at the set node cannot even rise, thereby causing the scan pulse not to be generated at all.
USPTO Backgrounds
USPTO Backgrounds