French patent application No. 1059919 (the disclosure of which is incorporated by reference) describes a semiconductor structure comprising a through-silicon via and a capacitor passing through the substrate. However, the electrical connection of the capacitor on one of the sides of the substrate requires provision to be made for the formation of a secondary hole for housing an electrical connecting means therein. A complication of the fabrication process therefore results.
Furthermore, the fabrication process described in this French patent application is not compatible with through-silicon vias (TSVs) and capacitors having the same diameter, and therefore the same depth during production. A risk of TSV breakage therefore results during fabrication.
USPTO Backgrounds
USPTO Backgrounds