The technology of integrated circuits has been characterized by a continuing increase in the density with which devices can be formed in a silicon semiconductor chip or substrate. The presence of a large number of devices on a chip requires the formation of a large number of conductors that are small and spaced closely together. In many instances, multiple levels of conductors are employed to interconnect individual devices. The use of two or more levels of conductors, of course, requires the deposition of a suitable dielectric over lower levels of conductors so that the overlapping upper level may be made without the risk of accidental short circuits.
Silicon dioxide is a favored material for conductor insulation because of its good thermal and electrical characteristics, and because it is easily patterned by selective masking and etching. Unfortunately, silicon dioxide cannot be deposited by ordinary chemical vapor deposition (CVD) techniques because the high temperatures normally required would melt or damage conductors made of metals such as aluminum.
Consequently, it has become a widely accepted practice to deposit silicon dioxide from a radio frequency plasma. Frequently, such plasmas are formed in reactors including opposite parallel plate electrodes, one of which is grounded and one excited by a radio frequency source, although other arrangements may be employed. The plasma provides energy for enhancing the reaction required for silicon dioxide formation and permits deposition at temperatures lower than those required for conventional CVD. Deposition processes utilizing plasmas are often termed plasma enhanced chemical vapor deposition or PECVD. Deposition processes are usually performed upon a "substrate" which may be, for example, a semiconductor surface, metal conductors, or previously deposited or grown silicon dioxide.
The source of silicon used in plasma deposition of silicon dioxide may be any of a number of silane gases or other gases containing silicon. A popular precursor gas is tetraethoxysilane (TEOS) together with oxygen in a plasma deposition atmosphere. Conventional TEOS deposition processes produce a relatively conformal dielectric.
Practitioners have found that even conformal coatings create problems when it is desired to make more than one level of conductors. In particular, the conformal coatings of closely spaced adjacent conductors tend to grow together in such a way as to occasionally create a void or other type of imperfection within the deposited silicon dioxide. Since, after deposition, the upper surface of a silicon dioxide layer is typically etched or ground to make it flat and a subsequent pattern is formed over the deposited silicon dioxide, voids or serious imperfections in the silicon dioxide may cause unpredictable variations in the quality of the coating.
U.S. Pat. No. 5,013,691, issued to Lory et al., and assigned to the assignee of the present application, and incorporated herein by reference, discloses a plasma process that favors deposition on horizontal surfaces rather than vertical surfaces and utilizes a gas which inhibits deposition on vertical surfaces.
USPTO Backgrounds
USPTO Backgrounds