a) Field of the Invention
The present invention relates to a dry etching method and apparatus for patterning a fine conductive wiring layer of a semiconductor integrated circuit or the like by using etchant gas plasma.
b) Description of the Related Art
Wafers for semiconductor integrated circuits are nowadays becoming large in diameter and have finer wiring patterns. In place of batch processing systems which process a plurality of wafers at the same time, single wafer processing systems have been used recently which process one wafer at a time in order to reduce process variations among wafers. For example, in the case of a plasma etching system, it is essential to use a high plasma density in order to ensure practical productivity of a single wafer processing system. From this reason, ECR (electron cyclotron resonance) plasma, helicon wave plasma, inductively coupled plasma, and the like are used for plasma etching systems.
An amount of etching species (active species) in high density plasma is large so that a high etching efficiency is obtained and a productivity higher than that at a low density plasma can be obtained. However, since a high gas pressure is used for a conventional RIE system in order to obtain high density plasma, the mean free path of ions becomes short. Therefore, etching anisotropy is lowered. If high ion energy is used to maintain anisotropy, etching selectivity of resist, underlying insulating layer, and the like is degraded. For realizing both a good productivity and a good etching anisotropy, plasma etching system of low pressure and high density has been developed which can independently control plasma density and ion energy and can maintain high etching anisotropy by lowering ion energy.
However, if polysilicon is etched by using plasma of a low pressure and a high density at a low ion energy, the bottom of a patterned silicon layer near at the interface to the underlying layer is locally side etched and an abnormal shape called a notch is formed. This phenomenon is reported, for example, in the following papers:
(1) N. Fujiwara, et al: Proc. 15th Symp. Dry Process, (1993) 45; PA0 (2) D. Takehara, et al: Proc. 15th Symp. Dry Process, (1993) 51; PA0 (3) N. Fujiwara, et al: Proc. 16th Symp. Dry Process, (19934) 31; PA0 (4) T. Nozawa, et al: Proc. 16th Symp. Dry Process, (1994) 37; and PA0 (5) D. Kimura, et al: Proc. 38th Symp. Semiconductors and Integrated Circuits Technology, pp. 91-96 (1995).
The following facts of the abnormal shape called a notch are known. A notch is formed at an area where fine lines with narrow adjacent spaces are densely distributed (hereinafter called a line and space (L & S) structure). A notch is not formed at the L & S structure having a plurality of lines connected in common, but it is observed at an outer line of an isolated L & S structure. A notch is not observed in the state of just etching but it is observed in the state of over etching. The cause of a notch may be ascribed to disturbance of ion orbits by charge-up of the L & S structure during plasma etching, or to other reasons.
An abnormal shape reported to date is formed in polysilicon during plasma etching at a low pressure and a high density. A similar abnormal shape has also been confirmed when Al alloy is etched at a low pressure and a high plasma density to pattern a fine L & S structure. FIG. 8 shows a test pattern of Al alloy used by notch observation experiments. This test pattern has an L & S structure including wiring patterns (lines) L1, L2, . . . , L7 of 1 .mu.m width being disposed with a space of 0.8 .mu.m between each pair of adjacent lines (L/S=1.mu.m/0.8 .mu.m). The center wiring pattern L4 is connected to an antenna 84 having a length of about 130 mm and a space of, for example, 10 .mu.m or wider.
FIG. 9 is a cross sectional view of the wiring structure of FIG. 8 taken along line A-A'. On an insulating film 81 such as a silicon oxide film deposited on a silicon substrate 80, an Al alloy layer 82 is formed on which a resist mask 83 is formed. The substrate 80 is introduced into a plasma etching system and the Al alloy layer 82 is selectively etched to form an L & S structure shown in FIGS. 8 and 9. The etching rate becomes lower at the narrow space than at the broad space. When the underlying insulating film 81 is exposed at the broad space, the Al alloy layer 82 is still left at the narrow space in the L & S structure 86 with dense wiring patterns. If over etching is performed until all the unnecessary Al alloy layer 82 is removed, notches 85 are formed, as shown in FIG. 9, at the bottoms of the wiring pattern L4 connected to the antenna 84 and of the outermost wiring patterns L1 and L7 on the pattern dense side.
Similar notches are also observed when the wiring pattern L4 is connected to the substrate 80 via a contact 87 instead of being connected the antenna, as shown in FIG. 8, and is subjected to etching.
Generation of similar notches is also recognized by any one of plasma etching systems of low pressure and high density, such as an inductively coupled plasma etching system and a microwave plasma etching system (in particular, electron cyclotron resonance (ECR) plasma etching system).
In order to prevent notches, etching may be performed at a plasma density lower than an ordinary case or at a high ion energy with a high plasma density. However, at a low plasma density, the etching rate is lowered. This contradicts the primary object of obtaining high productivity at a high plasma density. Etching anisotropy is degraded at a high pressure. If ion energy is raised in order to maintain high anisotropy, etching selectivity is lowered so that a wiring process margin becomes small, and/or production yield is lowered.
Instead of using a low pressure and high density plasma etching system, a lower plasma density RIE system may be used for effectively preventing notches. Also in this case, however, the etching rate is lower than the low pressure and high density plasma etching system, and high productivity is impossible. If the pressure is raised in order to increase the amount of active etching species, etching anisotropy (directivity) is degraded. If gas such as flon (fuorocarbon) gases easy to form a side wall protection film is added in order to maintain high etching anisotropy, a great amount of reaction byproducts are attached to the inner wall of an etching chamber.
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