1. Field of the Invention
This invention relates to a solid-state image pickup device and its fabrication process.
2. Description of the Related Art
For solid-state image pickup devices, it has been common to adopt the front-side illuminated structure that electrodes and wirings are formed over a surface of a substrate, in which photoelectric converting sections are formed, and light is allowed to enter from above the electrodes and wirings. In solid-state image pickup devices such as CCD (Charge Coupled Devices) and CMOS (Complementary Metal Oxide Semiconductor) sensors that make use of silicon substrates as such substrates, a buried structure is adopted in recent years for photoelectric converting sections as image sensors to reduce noise.
A sectional view of a solid-state image pickup device of the front-side illuminated structure is shown in FIG. 8.
As shown in FIG. 8, the solid-state image pickup device 100 is a CMOS solid-state image pickup device having the front-side illuminated structure.
A light-receiving sensor section of each pixel has a structure called “the HAD (Hole Accumulation Diode) structure,” specifically a structure that a P-type impurity is implanted in a surface of the light-receiving sensor section to cause pinning of excess electrons. By this HAD structure, reductions of white spots and dark current are realized.
Each light-receiving sensor section has a configuration that a photodiode PD is formed in a silicon substrate 101, a multilayer wiring layer 103 is arranged on the silicon substrate 101 via an interlayer insulating film 102, and further, a color filter 104 and a lens 105 are arranged in upper layers above the wiring layer 103. Incident light L passes through the lens 105, the color filter 104, and the interlayer insulating film 102 between the adjacent individual parts of the wiring layer 103, and enters the photodiode PD in the light-receiving sensor section.
Referring now to FIGS. 9A and 9B, a description will be made of a fabrication process of each buried sensor in a front-side illuminated, CMOS solid-state image pickup device.
As shown in FIG. 9A, a P-type buried region 202 is first formed in a silicon substrate 201 through an oxide film 231 formed on a surface of the silicon substrate 201 by ion implantation. This ion implantation is performed to form an overflow barrier for the HAD sensor, and to prevent electrons, which are given off from the silicon substrate 201, from entering a light-receiving sensor section.
Through the above-described oxide layer 231, a P-type element isolation region 221 is next formed in the silicon substrate 201. This P-type element isolation region 221 is formed, as a region for forming and isolating elements between pixels, in the silicon substrate 201 above the above-described P-type buried region 202. Subsequently, the oxide film 231 is removed.
As illustrated in FIG. 9B, a gate insulting film 211 is next formed on the silicon substrate 201, and via the gate insulating film 211, a transfer gate 212 is formed. Subsequently, an oxide film is formed again on the silicon substrate 201 as designated at numeral 232. At this time, the gate insulating film 211 other than a part thereof located below the transfer gate 212 may have been removed or may still remain. In the figure, the case where it has been removed is illustrated.
The formation of the light-receiving sensor section of the HAD structure is then performed as will be described hereinafter.
Through the oxide film 232, an N-type region 203 is first formed in the silicon substrate 201 by ion implantation. This ion implantation is performed in two stages, one for the formation of a layer for providing the resulting pixel with higher sensitivity, and the other for the formation of another layer for forming the light-receiving sensor section. The ion implantation for providing the resulting pixel with higher sensitivity is performed to a great depth, while the ion implantation for the formation of the light-receiving sensor section is performed to a relatively shallower depth than the ion implantation for providing the resulting pixel with higher sensitivity.
A P-type region 204 is next formed by ion implantation in the silicon substrate 201 above the N-type region 203 through the above-described oxide film 232. This ion implantation is performed to enhance pinning in the surface of the light-receiving sensor section. On this occasion, ions are obliquely implanted in view of transfer of charge so that no ions are allowed to penetrate into the silicon substrate 201 at a region adjacent a side wall of the transfer gate 212.
The photodiode PD is constructed with a PN junction formed between the N-type region 203 and the P-type region 204 as described above.
By the solid-state image pickup device of the buried sensor configuration having the above-described HAD structure, it is possible to substantially reduce noises such as dark current which have heretofore been produced in the surface of the light-receiving sensor section.
The buried solid-state image pickup device having the HAD structure is, therefore, considered to make it possible to realize excellent characteristics as a solid-state image pickup device.
The buried solid-state image pickup device having the HAD structure, however, involves a problem in that in the course of its fabrication, the boron (B) in the P-type region 204 in the light-receiving sensor section diffuses into the N-type region 203 in the silicon substrate 201 and the final impurity concentration profile of boron hence becomes broader. In the figure, the impurity profile of boron (B) is indicated by a dotted curve, and the profile of the N-type impurity (for example, phosphorus) is indicated by a solid curve.
It is, therefore, difficult to form a steep impurity concentration profile. Due to the broadening of the PN junction in the light-receiving sensor section, the saturation charge quantity (Qs) decreases significantly.
Moreover, such deviations from individual device parameters cause deteriorations of the sensor characteristics, the occurrence of increased white spots and black spots by the penetration of boron into the channel region, and variations or the like of the sensor characteristics due to instability of the amount of boron diffusion.
To solve the above-described problems, it is desired to suppress the occurrence of diffusion of boron under heat.
In MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), on the other hand, several technologies have been reported for the prevention of boron diffusion.
To suppress the short channel effect that gives a rise to a problem as a result of miniaturization, for example, in advanced MOS (Metal Oxide Semiconductor) devices (e.g., nMOSFET) after the 32 nm node, a device having a steep channel and Halo profile structure making use of an SiC layer has been proposed. This nMOSFET will be described with reference to a schematic sectional configuration view shown in FIG. 10A and sectional photographic views shown in FIGS. 10B and 10C.
As depicted in FIG. 10A, there has been reported a technology that silicon is caused to undergo epitaxial growth after implantation of ions for adjusting a threshold voltage Vt. For example, subsequent to the formation of a boron-diffused region 313, an epitaxially-grown silicon layer 311 is formed by epitaxial growth. In this case, the final channel implantation profile becomes broader because of the existence of a thermal budget throughout the formation step. This broader final channel implantation profile is attributed to the diffusion of boron under heat, so that the transistor characteristics of an nMOSFET 310 are significantly lowered to lead to increased variations in characteristics.
As illustrated in FIG. 10B, an SiC layer 312 is hence introduced. This SiC layer 312 has been formed as an impurity diffusion barrier against boron diffusion by epitaxial growth. As carbon (C) is considered to be one of materials that can reduce the diffusion of boron (B), a technology has been developed that in the nMOSFET 310, the SiC layer 312 is formed below the epitaxially-grown silicon layer 311. Owing to the formation of the SiC layer 312, the diffusion of boron can be suppressed (see, for example, A. Hakozaki, H. Itokawa, N. Kusanoki, I. Mizushima, S. Inaba, S. Kawanaka and Y. Toyoshima, “Steep Channel & Halo Profiles Utilizing Boron-Diffusion-Barrier (SiC) for 32 nm Node and Beyond,” 2008 Symposium on VLSI Technology Digests of Technical Papers (2008), hereinafter referred to as Non-patent Document 1).
As a result of practice of this technology, it has become possible to stabilize the concentration of the impurity contained in the channel part between the epitaxially-grown silicon layer 311 and the boron-diffused region 313 as depicted in FIG. 11 (see, for example, Non-patent Document 1).
As illustrated in FIG. 12, it has also been indicated that the short channel effect is suppressed owing to the possibility of suppressing variations in threshold voltage (Vth) and deteriorations of mobility and the possibility of suppressing broadening of a depletion layer at the same time (see, for example, Non-patent Document 1).
With reference to a schematic sectional configuration view shown in FIG. 13, a description will next be made about a method for suppressing diffusion of boron into an SiC layer in a heterojunction bipolar transistor.
As illustrated in FIG. 13, in a heterojunction bipolar transistor 401 in which an emitter electrode 430 is formed from silicon and a base is formed from silicon-germanium (SiGe), a silicon-germanium layer 427 with carbon contained in a base layer is formed to realize a high-frequency high-output transistor.
Described specifically, trench isolation regions 422 are formed in a P-type silicon substrate 421, and a subcollector layer 423 is formed between the trench isolation regions 422. Above the subcollector layer 423, a second collector diffusion layer 424 is formed, and further, an N+-type collector lead layer 426 is formed with an element isolation region 425 interposed between the N+-type collector lead layer 426 and the second collector diffusion layer 424. In addition, the carbon-containing, silicon-germanium layer 427 is formed on the P-type silicon substrate 421 by epitaxial growth to decrease the parasitic capacitance. Boron (B) is introduced in the carbon-containing, silicon-germanium layer 427 during its epitaxial growth, so that the carbon-containing, silicon-germanium layer 427 is provided with P-type conductivity. Its carbon concentration is about 0.5%.
On the carbon-containing, silicon-germanium layer 427, an oxide film 428 is formed further. Through an opening 429 formed in the oxide film 428, the emitter electrode 430 is formed in connection to the carbon-containing, silicon-germanium layer 427.
At a temperature of about 900° C. or so, the phosphorus in the emitter electrode 430 is caused to diffuse into the carbon-containing, silicon-germanium layer 427 as the base layer to form an emitter layer 431.
In general, diffusion of high-concentration phosphorus releases interstitial silicon, and therefore, creates a situation that the boron (B) in the base layer is facilitated to diffuse. As described above, however, the formation of the base layer with the carbon-containing, silicon-germanium layer 427 allows carbon (C) to interact with interstitial silicon so that the interstitial silicon is eliminated instead of forming interstitial silicon carbide (SiC). It has been reported that for the reasons mentioned above, accelerated diffusion of boron (B) under heat can be suppressed (see, for example, Japanese Patent Laid-open No. 2005-167125).
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