Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photosensor, e.g. a photogate, photoconductor, or a photodiode. In a CMOS imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photosensor converts photons to electrons which are typically transferred to a storage region, e.g., a floating diffusion region, which is connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photosensor to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as a pixel output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, each assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
With reference to FIGS. 1 and 2, which respectively illustrate a top-down and a cross-sectional view of a conventional CMOS pixel sensor cell 100, when incident light 187 strikes the surface of a photodiode photosensor 120, electron/hole pairs are generated in the silicon. The generated electrons (photo-charges) are collected in the n-type accumulation region 122 just below the p+ surface layer 123 of the photodiode photosensor 120. The photo-charges move from the initial charge accumulation region 122 to a floating diffusion region 110 via a transfer transistor 106. The charge at the floating diffusion region 110 is typically converted to a pixel output voltage by a source follower transistor 108 and subsequently output on a column output line 111 via a row select transistor 109.
Conventional CMOS images, such as that shown in FIG. 1, typically achieve approximately a fifty percent fill factor or less, meaning that less than half of the pixel 100 is utilized as the photosensor for converting light to charge carriers. As shown in FIG. 1, only a small portion of the cell 100 comprises a photosensitive element (i.e., photosensor 120). The remainder of the pixel cell 100 includes isolation regions 102 (FIG. 2), shown as shallow trench isolation (STI) or local oxidation on silicon (LOCOS) regions in a substrate 101, the floating diffusion region 110 coupled to a transfer gate 106′ of the transfer transistor 106, and source/drain regions 115 for reset 107, source follower 108, and row select 109 transistors having respective gates 107′, 108′, and 109′. Moreover, as the total pixel area continues to decrease (due to desired scaling), it becomes increasingly important to create high sensitivity photosensors that utilize a minimum amount of surface area and/or to develop more efficient layouts of the pixel array for the non-photosensitive components of the cells to provide an increased size for the photosensitive areas.
As briefly mentioned above, shallow trench isolation (STI) is one technique that can be used to isolate pixels from one another in a pixel array, or other integrated structures from one another. As depicted in FIG. 2, an STI region 102 is typically formed as an isolation trench 117 formed in the substrate 101 to isolate the active areas of one pixel from other pixel cells. In a typical STI isolation structure 102, a trench 117 is etched into the substrate 101 and filled with one or more layers of dielectric material 125 to provide a physical and electrical barrier between adjacent active areas within a substrate. For example, an STI structure 102 can be formed by etching a trench 117 and then filling it with a dielectric 125 such as a chemical vapor deposited (CVD) or high density plasma (HDP) silicon oxide or silicon dioxide (SiO2). The filled trench is then planarized by a chemical mechanical planarization (CMP) or etch-back process so that the dielectric 125 remains only in the trench 117 and its top surface remains level with that of the silicon substrate 101. To enhance the isolation further, ions may be implanted into the silicon substrate 101 in the area 140 directly beneath the trench 117.
Further, although deeper STI regions 102 may provide better isolation, there is a limit as to how deep the STI region 102 can be made. If the STI region 102 is too deep, filling the trench 117 with oxide layers 125 may produce voids or cracks 116 in the filled trench 117. In addition, creating an isolation trench 117 that is too wide takes away area of the pixel cell 100 that could otherwise be photosensitive, thereby decreasing the pixel's 100 fill factor.
A pixel array having sufficient pixel isolation and having an increased fill factor is therefore desired.
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