1. Field of Invention
The present invention relates to a ballast integrated circuit (IC), and more particularly to a ballast IC for automatically adjusting a dead time according to load characteristics.
2. Description of Related Art
FIG. 1 is a circuit diagram illustrating a fluorescent-lamp driving circuit including a conventional ballast IC. FIG. 2 is a graph illustrating operations of the ballast IC of FIG. 1. In FIG. 2, a horizontal axis indicates a frequency, and a vertical axis indicates a magnitude.
The inverter circuit for driving the fluorescent lamp 100 includes first and second switching elements 121 and 122 operated by ballast IC 110. The first switching element 121 and the second switching element 122 can be N-channel MOS transistors. Gate terminals of the first and second switching elements 121 and 122 are connected to the ballast IC 110. A DC voltage VDC is applied to a drain terminal of the first switching element 121, and a source terminal of the first switching element 121 is connected to the drain terminal of the second switching element 122 and the output node (a). The drain terminal of the second switching element 122 is coupled to the source terminal of the first switching element 121 and the output node (a), and the source terminal of the second switching element 122 is grounded.
A first resonance capacitor CS for resonance is coupled between the output node (a) and the fluorescent lamp 100, and a second resonance capacitor CP is coupled in parallel to the fluorescent lamp 100. An inductor L for limiting a current signal is coupled between the output node (a) and the first resonance capacitor CS, and an equivalent capacitor CCP for use in a charge pump is connected in parallel to the inductor L.
The above-mentioned driving circuit drives the first and second switching elements 121 and 122, generates an AC output voltage VO in the form of a square wave signal via the output node (a), and drives the fluorescent lamp 100. In this implementation the ballast IC 110 compensates for negative impedance characteristics of the fluorescent lamp 100, such that it ballasts (or stabilizes) the current signal when driving the first and second switching elements 121 and 122. The fluorescent lamp may be considered to be a single load resistor RL. In this case, the load resistor RL is connected in parallel to the second resonance capacitor CP.
Therefore, the characteristics of the resonance circuit composed of first and second resonance capacitors CS and CP and the load resistor RL vary according to the magnitude of the load resistor RL. The ballast IC is operated in three different modes according to the different resonance-circuit characteristics.
Referring to FIG. 2, no current will flow if the fluorescent lamp 100 is switched off. This can be represented as a load resistance RL with a very high resistance. Therefore, the resonance curve of the resonant circuit will have a very steep slope and a very high resonance peak value, as denoted by the graph 210. Here a load resistance RL of 100 kΩ was assumed. However, if the fluorescent lamp 100 is switched on, the load resistance RL decreases. This lowers the resonance peak value and the resonance frequency, as can be seen from the graph 220, 230, or 240. Graph 220 indicates a load resistance RL of 10 kΩ, graph 230 indicates a load resistance RL of 1 kΩ, and graph 240 indicates a load resistance RL of 500Ω.
According to the above-mentioned resonance characteristics, the ballast IC drives the fluorescent lamp 100 using three modes: a preheating mode, an ignition mode, and a running mode. The fluorescent lamp 100 is sequentially driven in the order of the preheating mode→ignition mode→running mode.
During the preheating mode, denoted by “A” in FIG. 2, the fluorescent lamp 100 is driven at a frequency higher than a resonance frequency corresponding to the very high load resistance RL. During the preheating mode, the current signal does not flow in the fluorescent lamp 100. Instead, it flows in a filament contained in the fluorescent lamp 100 and a second resonance capacitor CP. The hot electrons can be easily emitted by the above-mentioned current signal.
During the ignition mode, denoted by “B” in FIG. 2, the fluorescent lamp 100 is switched on by the increasing voltage VL between the ends of the fluorescent lamp 100 because it quickly reduces a frequency for a predetermined time shorter than the time of the preheating mode.
If the fluorescent lamp 100 did not break down, no faulty- or erroneous-operation occurred, or there was no error in the circuit, the running mode allows the fluorescent lamp 100 to be driven at a constant frequency.
The running mode, denoted by “C” of FIG. 2, occurs after the fluorescent lamp 100 switched on. The lower the load resistance RL, the lower the resonance peak value and the lower the quality factor Q of the resonance circuit. The driving frequency is generally set to a specific frequency slightly less than the resonance frequency of the resonance circuit. The resonance frequency of the resonance circuit is distinguished by the fluorescent lamp 100 having infinite resistance at that frequency—at least in principle.
The described driving circuit is based on a zero-voltage switching control scheme. Generally, the zero-voltage switching indicates a specific switching technique capable of switching on the MOS transistor when a voltage difference between a drain terminal and a source terminal of the MOS transistor is almost zero, thereby minimizing the conduction loss and the EMI (Electro-Magnetic Interference).
Typically, the absence of zero-voltage switching indicates that the load resistance RL is extremely high or is not present. In this case, the resonance frequency of the resonance circuit is higher than the frequency of the running mode, such that the driving circuit is driven at a frequency lower than the resonance frequency of the resonance circuit.
In this case, the resonance circuit is operated similarly with the capacitive load (also called capacitor load), such that the current signal of the inductor L is leading the phase of the output voltage Vo. As a result, a so-called “hard switching” occurs instead of zero-voltage switching.
During hard switching the output signal is changed by the switching operation and the switch is switched on by a maximum voltage. In this case, the conduction loss is high, and an abrupt current flow occurs in the switch, resulting in a high level of EMI. Also, the IC may be operated erroneously. Typically, most of the ballast ICs connect a capacitor CCP to an output terminal of the driving circuit and generate an auxiliary power-supply using the current signal of the capacitor CCP. This generates an operating voltage of the IC using the voltage signal of the auxiliary power-supply. The current signal of the capacitor CCP is determined by the rising slope of the output voltage Vo. The slope of the output voltage Vo is very steep, such that the current signal of the capacitor CCP increases and the increasing current signal encounters a high-voltage peak in the auxiliary power-supply unit. These can generate a high-frequency noise in the IC, such that the IC may be erroneously operated.
FIGS. 3A-3D are circuit diagrams illustrating the zero-voltage switching operation of the ballast IC shown in FIG. 1. FIG. 4 is a timing diagram illustrating signal states of individual circuits of FIGS. 3A-3D.
In FIG. 3A and FIG. 4, a high-side input signal HIN drives the first switching element 121, and a low-side input terminal LIN drives the second switching element 122. During a period T1 in which only the first switching element 121 is switched on, the resonance current flows in the inductor L, and the resonance frequency is less than a driving frequency as denoted by “C” in FIG. 2, such that the resonance current is lagging the driving-voltage phase. As a result, the current signal flows in the (negative (−)) direction from the inductor L to the driving circuit. After a time interval, the current direction changes by a current signal generated from the first switching element 121, and the changed current increases in time.
In FIG. 3B and FIG. 4, during an interval Td in which the first switching element 121 and the second switching element 122 are switched off, the current signal of the inductor L flows in the capacitor CCP, and the capacitor CCP voltage is gradually reduced. Since the interval Td is very short, a DC current is provided regardless of a variation of the inductor L current. This reduces the output voltage Vo along the almost-constant slope by the capacitor CCP and the inductor L current.
In FIG. 3C and FIG. 4, the current direction of the inductor L is not changed after the capacitor CCP voltage drops to zero by the inductor L current, a diode D2 connected in parallel to the second switching element 122 is switched on during the period T3, such that the current signal flows in the ballast IC. In this case, the ON voltage of the diode D2 is applied to the drain and source terminals of the second switching element 122.
In FIG. 3D and FIG. 4, the capacitor CCP voltage reaches 0V, or if the second switching element 122 is switched on during the interval T4, a voltage between the drain terminal and the source terminal of the second switching element 122 becomes extremely low, such that an almost zero-voltage switching is performed. Although the second switching element 122 is switched on, the current does not vary with time, so that EMI, generated by the time derivative of the current, “di/dt”, does not occur. Since the voltage between the drain terminal and the source terminal is almost 0V, there will be minimal conduction loss in the ballast IC, caused by the ON resistance of the MOS transistor.
The above-mentioned interval Td is generally called a dead time. Generally, the ballast IC guarantees the above-mentioned dead time. However, if the dead time is not properly adjusted according to load states, the zero-voltage switching may be incorrectly performed. If a faulty- or erroneous-operation occurs, the system may not be protected from danger and harm, making it is impossible to guarantee the stability of the system.
USPTO Backgrounds
USPTO Backgrounds