An operation in an integrated circuit may be initiated following a certain delay after the occurrence of some triggering event. In digital processing systems, for example, a sense amplifier may be enabled to read data from a random access memory array after a delay measured from the activation of the word lines in the memory array. This type of circuit, in which one portion of the circuit is controlled by another portion in response to some triggering event, is commonly referred to as a self-timed circuit. Many types of circuits used in digital processors are commonly implemented as self-timed circuits.
Self-timed circuits are difficult to implement in certain cases. A multiple-clock system in which the clock signals may be underlapped presents one instance in which a self-timed circuit is difficult to implement. In an underlapped condition, a first clock signal ends before a second clock signal appears. If, for example, the first clock signal is used as an event to initiate the operation of a self-timed circuit, and if the result from the self-timed circuit must be available during the second clock signal, some mechanism must be employed to maintain the result from the self-timed circuit after the end of the first clock signal. That is, the result from the self-timed circuit must be maintained until some point after the second clock signal appears.
Properly maintaining the result from a self-timed circuit for a sufficient period of time is not a trivial task because the delay must allow for process variations. Simply gating the output from the self-timed circuit with the second clock signal would ensure that the self-timed circuit output was available during the second clock signal. However, gating the signal from the self-timed circuit with the second clock signal would at least slow the operation performed by the self-timed circuit.
USPTO Backgrounds
USPTO Backgrounds