This invention relates to semiconductor devices, and for example, is a technique applicable to a semiconductor device in which a first semiconductor chip and a second semiconductor chip are stacked on a wiring board.
One of the methods for coupling a semiconductor chip to another semiconductor chip employs through-silicon vias. Through-silicon vias pass through a substrate of a semiconductor chip in the thickness direction. For example, Japanese Unexamined Patent Publication No. 2011-243724 discloses a method including stacking memory chips, each having through-silicon vias formed therein and coupling these memory chips using the through-silicon vias.
In this publication, the lowermost memory chip is coupled to a wiring board through solder bumps. Around the lowermost memory chip, a frame-like metal material member is provided so as to enclose the memory chip. In addition, a metal substrate is mounted over the uppermost memory chip with an adhesive member therebetween.
USPTO Backgrounds
USPTO Backgrounds