The present invention relates to formation of contact holes of a semiconductor device.
FIG. 1A is a plan view of the memory cell array of a conventional EEPROM, FIG. 1B is a sectional view taken along the line 1B--1B in FIG. 1A, and FIG. 1C is a sectional view taken along the line 1C--1C in FIG. 1A.
As shown in FIGS. 1A to 1C, element isolation regions 102 made from silicon dioxide are formed in a p-type silicon substrate 100. The element isolation regions 102 define an element region 104 in the substrate 100. In the element region 104, n-type source and drain 106S and 106D are formed. A floating gate 110 is formed on the substrate 100 between the source and drain 106S and 106D via a tunnel oxide film (SiO.sub.2) 108. A control gate (word line) 114 capacitively coupled to the floating gate 110 is formed on the floating gate 110 via an insulating film 112. An interlevel insulating film 116 made from silicon dioxide is formed on the substrate 100. A contact hole 118 is formed in the interlevel insulating film 116 to reach with the drain 106D. On the interlevel insulating film 116, a bit line will be formed to be connected to the drain 106D through the contact hole 118.
In the memory cell array having the above arrangement, if the contact hole 118 is formed to overlap the element isolation region 102 or the control gate 114, the bit line short-circuits with the substrate 100, or the control and floating gates 114 and 110.
FIG. 2A is a sectional view showing a short circuit between the bit line and the substrate, and FIG. 2B is a sectional view showing a short circuit between the bit line and the control/floating gate.
As shown in FIG. 2A, if the contact hole 118 is formed to overlap the element isolation region 102, the element isolation region 102 is etched. This is because both the element isolation region 102 and the interlevel insulating film 116 are made from silicon dioxide, and the etchant that etches the interlevel insulating film 116 also etches the element isolation region 102. If the element isolation region 102 is etched to the substrate 100 below the drain 106D, the substrate 100 is exposed in the contact hole 118.
As shown in FIG. 2B, if the contact hole 118 is formed to overlap the control gate 114, the control and floating gates 114 and 110 are exposed in the contact hole 118. As a result, a bit line 120 short-circuits with the control and floating gates 114 and 110.
To avoid the short circuits shown in FIGS. 2A and 2B, the contact hole 118 is formed with margins M in the X direction (margins for the control gate 114) and the Y direction (margins for the element isolation region 102) in advance (FIGS. 1A to 1C). The size of the margin M is determined in consideration of a misalignment in mask alignment, a processing size error in etching, and the like.
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