The present invention generally relates to direct memory access controllers, and more particularly to a direct memory access controller which controls a direct memory access between an input/output control unit and a memory or between two memories.
FIG. 1 shows a data processing system which includes an example of a conventional direct memory access controller (hereinafter simply referred to as a DMAC). The data processing system has a DMAC 1, a central processing unit (CPU) 2, an input/output control unit 3, and memories 4 and 5 which are coupled via a system bus 6 which includes an address bus, a data bus and a control bus.
When making a desired data processing on this data processing system, a data transfer is made between the input/output control unit 3 and the memory 4 or 5 or between the memories 4 and 5. In order to improve a data transfer rate of the data transfer, a direct memory access (DMA) transfer is made between the input/output control unit 3 and the memory 4 or 5 or between the memories 4 and 5 by hardware and not through the CPU 2. This DMA transfer is controlled by the DMAC 1 so that the DMA transfer takes place during a time when the CPU 2 does not make access to the system bus 6 or by stopping the operation of the CPU 2. When making the DMA transfer, it is desirable that the DMA transfer can be terminated with an arbitrary timing.
When controlling the data transfer between the input/output control unit 3 and the memory 4 or 5 by the conventional DMAC 1, the data transfer is started responsive to a transfer request signal REQ from the input/output control unit 3 and the data transfer is terminated in a normal termination at an intermediate stage of the data transfer responsive to an interrupt request signal DONE from the input/output control unit 3. The data transfer between the memories 4 and 5 can be started responsive to a trigger signal which is continuously generated within the DMAC 1.
However, the memories 4 and 5 do not have the function of generating the interrupt request signal DONE. For this reason, once the DMAC 1 starts the DMA transfer, there is a problem in that it is impossible to terminate the DMA transfer at an intermediate stage of the data transfer in a normal termination unless an abnormality such as a bus error occurs.
On the other hand, a Japanese Laid-Open Patent Application No. 61-133460 discloses a method of interrupting the DMA transfer at an intermediate stage of the data transfer by a terminate signal which is supplied directly from the input/output control unit to the DMAC via a signal line which is provided exclusively for the terminate signal. In this case, the DMAC stops operating responsive to the terminate signal which is supplied directly to the DMAC and not through the CPU which carries out the main control of the data processing system. For this reason, the CPU may not be aware that the DMAC has stopped operating. As a result, this method introduces problems when it is necessary to make some kind of a decision or discrimination in the CPU before stopping the operation of the DMAC.
USPTO Backgrounds
USPTO Backgrounds