1. Field of the Invention
The present invention relates to a method for fabricating an integrated circuit or more concretely to a semiconductor circuit having a matrix device (including an electro-optic display and semiconductor memory) having a matrix structure and a MOS or MIS (metal-insulator-semiconductor) type field effect element (hereinafter generally referred to as a MOS type element) as a switching element and characterized in its dynamic operation such as a liquid crystal display device and dynamic RAM (DRAM) and a driving circuit therefor or an integrated driving circuit like an image sensor. The present invention particularly relates to a device employing a thin film semiconductor element such as a thin film semiconductor transistor or the like which is formed on an insulating surface as a MOS type element and to a device having a thin film transistor whose active layer is formed by crystal silicon.
2. Description of the Related Art
Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate type field effect transistor (TFT) has been fabricated by crystallizing an amorphous silicon film formed by a plasma CVD or thermal CVD method within such an apparatus as an electric furnace for many hours of more than 24 hours at a temperature more than 600.degree. C. The many hours of heat treatment has been required in order to obtain sufficient characteristics such as a high field mobility and high reliability.
However, such conventional method has many problems. One of the problems is that its throughput is low and accordingly, a product cost becomes high. For example, if it takes 24 hours for the crystallization process and if it takes two minutes of processing time per sheet of substrate, 720 substrates must be processed in the same time. However, a tube furnace normally used can process 50 sheets of substrates at most in one time, and when only one apparatus (reaction tube) is used, it takes 30 minutes per sheet. That is, in order to process one sheet in 2 minutes, 15 reaction tubes must be used. It means that a scale of investment must be increased and that because the investment is greatly depreciated, it cannot but be reflected in the product cost.
Another problem lies in the temperature of the heat treatment. Normally, substrates used for fabricating a TFT are roughly divided into those composed of pure silicon oxide such as silica glass and non-alkaline boro-silicated glass such as CORNING No. 7059 (hereinafter referred to as CORNING 7059). Among them, the former has no problem in terms of temperature because it has an excellent heat resistance and can be handled in the same manner with the wafer process of normal semiconductor integrated circuits. However its cost is high and increases exponentially as the substrate area increases. Accordingly, it is used only for TFT integrated circuits having a relatively small area.
On the other hand, non-alkaline glass has a problem in terms of heat resistance, though its cost is sufficiently low as compare to that of silica glass. Because its strain point is generally around 550 to 650.degree. C., or less than 600.degree. C. in case of a readily available material, such problems as irreversible shrinkage and warp are caused on the substrate in a heat treatment at 600.degree. C. and it is remarkable in such a substrate whose diagonal distance exceeds 10 cm. From above reasons, it has been considered to be indispensable to keep the heat treatment conditions under 550.degree. C. and within 4 hours to reduce the cost in crystallizing silicon semiconductor films. It is then an object of the present invention to provide a semiconductor fabricating method that clears such conditions and a semiconductor device fabricating method using such a semiconductor.
Lately, a study on an insulated gate type semiconductor device having a thin film active layer (or called as an active region) has been conducted. Especially, a thin film insulated gate transistor or so-called a thin film transistor (TFT) has been fervently studied. They are formed on a transparent insulating substrate to use to control each picture element and to drive its matrix in a display device such as a liquid crystal display having a matrix structure or to use as a driving circuit of an image sensor formed similarly on an insulating substrate. They are categorized as an amorphous silicon TFT or crystalline silicon (or called as polycrystalline silicon) TFT depending on a material and crystal state of a semiconductor used.
Lately, a study to use a material which presents an intermediate state between crystalline silicon and amorphous is also being conducted. Although the intermediate state is being discussed, all those which reached to some crystal state by any thermal process (such as by annealing at a temperature more than 450.degree. C. by irradiating strong energy such as laser light) shall be called as crystalline silicon in this specification.
A crystalline silicon TFT is used also in a monocrystal silicon integrated circuit as a so-called SOI technology and it is used as a load transistor for example in a highly integrated SRAM. In this case, however, an amorphous silicon TFT is rarely used.
Further, a very high speed operation is possible in a semiconductor circuit on an insulating substrate because there is no capacitive coupling between the substrate and wires, so that a technology to use it as a very high speed microprocessor or very high speed memory is being proposed.
Generally, a field mobility of a semiconductor in an amorphous state is small and accordingly, it cannot be used for a TFT requiring a high speed operation. Furthermore, because a field mobility of P-type is remarkably small in an amorphous silicon, a P-channel type TFT (a TFT of PMOS) cannot be fabricated and accordingly, a complementary MOS circuit (CMOS) cannot be formed by combining with a N-channel type TFT (a TFT of NMOS).
However, a TFT formed by an amorphous semiconductor has an advantage that OFF current is small. Then it is utilized in the use in which a very high speed operation is not required, only one conductive type will do and a TFT having a high charge retaining ability is required such as transistors of an active matrix of a liquid crystal display having a small matrix scale. However, it has been difficult to use the amorphous silicon TFT for an advanced application such as a liquid crystal display having a large scale matrix. Further, it could not be used naturally for peripheral circuits of a display and for a driving circuit of an image sensor which require a high speed operation.
On the other hand, a crystalline semiconductor has a field mobility larger than that of the amorphous semiconductor and accordingly, a high speed operation is possible. For example, such a large value as 300 cm.sup.2 /Vs has been obtained as a field mobility in a TFT using a silicon film recrystallized by laser annealing. It is an extremely large value considering that a field mobility of a MOS transistor formed on a normal monocrystal silicon substrate is around 500 cm.sup.2 /Vs. Whereas an operation speed of the MOS circuit on the monocrystal silicon is limited by a parasitic capacity between the substrate and wires, there is no such limit in terms of the TFT using crystallized silicon film because it is formed on the insulating substrate. Accordingly, a remarkable high speed operation is being expected to be achieved in such TFT.
Further, it is possible to form a CMOS circuit by the crystalline silicon because not only a NMOS TFT but also a PMOS TFT can be similarly obtained. For example, among liquid crystal displays in an active matrix system, one having a so-called monolithic structure in which not only the active matrix section but also peripheral circuits (such as a driver) are constructed by a CMOS crystalline silicon TFT is known. The TFT used in the aforementioned SRAM is what this point is noticed, wherein the PMOS is constructed by the TFT as a load transistor.
Furthermore, whereas it is difficult to form a source/drain region by such a self-aligning process as those used in monocrystal IC technology in a normal amorphous TFT and a parasitic capacity caused by the geometrical overlap of a gate electrode and the source/drain region causes a problem, the crystalline silicon TFT has such an advantage that a parasitic capacity can be remarkably suppressed because the self-aligning process can be adopted.
However, a leak current of the crystalline silicon TFT when no voltage is applied to the gate (non-selection time) is great as compare to that of the amorphous silicon TFT, and such countermeasures have been taken that an auxiliary capacity is provided to compensate the leak current and that two TFTs are connected in series to reduce the leak current when it is used in a liquid crystal display.
For example, a method to form an amorphous silicon and to irradiate laser selectively on it to crystallize only a peripheral circuit has been proposed for forming the peripheral circuit of polysilicon TFTs having a high mobility monolithically on the same substrate while utilizing a high OFF resistance of the amorphous silicon TFT.
Presently, however, its yield is low due to a problem of reliability of the laser irradiating process (such as a bad homogeneity of the irradiated energy within the irradiated surface), so that a method to construct a matrix by amorphous silicon TFTs and to construct driving circuits by connecting monocrystal integrated circuits by a TAB method or the like is being adopted in the end. However, this method requires a more than 0.1 mm of pixel pitch from the physical restriction in the connection and its cost becomes high.
The present invention is intended to solve such difficult problems, but it is not desirable to complicate the process and to lower its yield or to increase its cost for that end. What the present invention intends is to fabricate two kinds of TFTs, i.e. a TFT in which a high mobility is required and a TFT in which a leak current is required to be low, readily and discriminately while keeping mass-producibility and while minimizing changes of its process.
Further, it is another object of the present invention to reduce a difference between the mobility of the NMOS and of the PMOS in the CMOS circuit. The reduced difference between the NMOS and PMOS allows to increase a degree of freedom in designing the circuit.
Semiconductor circuits to which the present invention is applied are not universal. That is, the present invention is suited for an active matrix circuit for displaying images by utilizing such materials which change transmittivity or reflectivity of light by an effect of electric field, by sandwiching those materials between electrodes facing to each other and by applying the electric field between those electrodes such as a liquid crystal display; a memory device for holding memory by storing charge in capacitors such as DRAM; a circuit having a dynamic circuit such as a dynamic shift register which drives the next circuit by capacitors of MOS structure portion of MOS transistors or other capacitors; and a circuit having a digital circuit and a circuit for controlling analog signal outputs such as a driving circuit of an image sensor. The present invention is suited especially to a circuit in which dynamic circuits and static circuits are mixedly mounted.
USPTO Backgrounds
USPTO Backgrounds