(a) Field of the Invention
The present invention relates generally to bit recovery in a digital communication system and, more particularly, to an apparatus for bit synchronization.
(b) Description of Related Art
In digital communication systems, a transmitter transmits digital signals that represent digital symbols. The digital signals are transmitted synchronously with a transmit symbol clock, which has a frequency and a phase. A receiver receives the transmitted signal, containing the transmitted digital symbols as well as noise. In order to determine the values of the transmitted symbols with minimum errors, the receiver must know the frequency and phase of the transmit symbol clock. Most receivers derive the frequency and phase of the transmit symbol clock from the transmitted signal itself, thereby creating a derived symbol clock. Receivers derive the frequency and phase of the transmit symbol clock from the transmitted signal using a classical analog phase-locked loop (PLL). The classical analog PLL evaluates the transmitted signal in the frequency domain to derive the frequency and phase of the transmit symbol clock.
When transmitting non-return-to-zero (NRZ) data, the transmit symbol clock frequency and phase are derivable only from the instances when a symbol transitions to a symbol of a different value. This creates a problem in that a sequence of identical symbols contains no information that may be used to derive the frequency and phase of the transmit symbol clock. Because the analog PLL evaluates the transmitted signal in the frequency domain, the transmit symbol clock of NRZ data with no symbol transitions appears to the analog PLL to have a frequency of zero.
Another problem occurs with receivers using analog PLLs when transmitting NRZ data with low transition densities, i.e. data containing long sequences of symbols of the same value. Because of the low transition densities, the frequency of the transmit symbol clock appears to be lower than it actually is. Therefore, during periods when the transmitted NRZ data contains few transitions, the derived symbol clock will drift in frequency and phase from the transmit symbol clock. Symbol clock drift results in increased symbol error rates and reduced efficiency of the communication system.
Currently, the problem of derived symbol clock drift due to low transition densities is overcome by transmitting data using a return-to-zero (RZ) symbol scheme, such as a Manchester Code, which results in a transition for each symbol. RZ symbol schemes guarantee adequate symbol clock components in the data signal from which to derive the symbol clock frequency and phase. However, as is well known in the art, using a Manchester Code effectively doubles the required transmission bandwidth and requires a doubling of transmission power to maintain the same error rate.
Another existing solution for symbol clock drift due to low transmission densities artificially creates symbol transitions by encoding the data before transmission, using, for example, an encryption technique. However, the complexity of the communication system is increased because of the additional steps of encoding the data prior to transmission, as well as decoding the data subsequent to receiving the data.
The use of the analog PLL in digital communication systems involves additional shortcomings. For instance, cost is increased because a high quality voltage controlled oscillator is often required in order to achieve acceptable symbol error rates. Additionally, the analog PLL is more sensitive to temperature changes than digital components. Moreover, the use of an analog PLL requires interfacing of analog and digital components, resulting in increased complexity, size, weight, and cost.
The present invention overcomes the problem of derived symbol clock drift caused by transmission of NRZ data with low transition densities. Additionally, the present invention utilizes digital circuitry instead of an analog PLL, thereby overcoming the above mentioned problems related to analog PLLs.
The present invention is embodied in a bit recovery subsystem for synchronizing a received digital signal with a transmitted digital signal. The bit recovery subsystem includes a demodulator that receives an RF signal encoded with digital information representative of a transmit bit clock and producing a baseband signal, voltage comparators that process the baseband signal to produce two digital logic signals and a latch that converts the two digital logic signals into unsynchronized data and inverted unsynchronized data. The bit recovery subsystem also includes a bit synchronizer that processes the unsynchronized data and inverted unsynchronized data to produce a derived bit clock and a reclock latch that processes the unsynchronized data and the derived bit clock delayed by a phase to produce synchronized data.
The present invention may also be embodied in a method of synchronizing a received digital signal with a transmitted digital signal. The method includes the steps of receiving an RF signal encoded with digital information representative of a transmit bit clock and producing a baseband signal, processing the baseband signal to produce two digital logic signals, and converting the two digital logic signals into unsynchronized data and inverted unsynchronized data. The method also includes the steps of processing the unsynchronized data and inverted unsynchronized data to produce a derived bit clock and processing the unsynchronized data and the derived bit clock to produce synchronized data.
USPTO Backgrounds
USPTO Backgrounds