Multi-processor systems, although they vary in specific architecture, typically use a sub-system to handle signals and interrupts from devices and from processor tasks. A typical multi-processor system may include a central processor, a plurality of sub-processors, a memory, a system bus, and an input/output channel for communication with devices and data networks.
Some multi-processor systems attempt to handle interrupts through a central processor. The central processor designates one or more sub-processors to handle interrupts as they occur, and upon receipt of an interrupt from a system device, an interrupt task is transmitted over the system bus to the designated sub-processor. However, centralization of interrupt handling can result in a “bottleneck” at the central processor, especially in systems of higher complexity.
In other systems, the multi-processor system uses a parallel bus to broadcast interrupts to all sub-processors. One or more of the sub-processors are designated to accept the interrupt, and thereafter execute the interrupt task. However, such systems may suffer congestion problems as the size of the multi-processor system, and hence the number of interrupts broadcast to all processors, increases.
USPTO Backgrounds
USPTO Backgrounds