BIST (Built-In Self-Test) is performed to test and verifie the proper operation of memory devices, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and Pseudo SRAM (Pseudo Static Random Access Memory) by using a BIST module (refer to Japanese Unexamined Patent Publication No. 6-242190 and Japanese Patent No. 3867146). The BIST module is incorporated in a memory controller implemented in the form of LSI (Large Scale Integration) circuits.
When testing a memory by BIST, data write/read operations are performed to all the addresses in the memory space. Accordingly, if the number of address bits is 20, for example, in other words, if the number of address lines is 20, at least 220 data write/read operations will have to be performed.
It is also practiced to test not only a memory but also the address lines or the BIST itself by connecting a test circuit in place of the memory. However, if the test is to be performed throughout the entire memory space, it will take an enormous amount of time to complete the testing of the BIST itself. Accordingly, when performing the test to verify the operation of the BIST, the test has been performed only to the lower address bits by employing a simplified test mode. However, since the test is not performed by driving the higher address bits, it has not been possible to check the higher address lines for faults such as shorts and opens. Furthermore, it has not been possible to use the simplified test mode for actually testing the memory.
USPTO Backgrounds
USPTO Backgrounds