1. Field of the Invention
The present invention relates to a signal detecting circuit for detecting a designated signal specified in a designated frequency, from an input signal to the signal detecting circuit, having a plurality of frequency components.
With respect to the above detection, there is an example of a public telephone set in a telephone system. When a calling party speaks with his called party by using a public telephone set through a central office, a metering signal is sent for accounting from the central office to the public telephone set in an accounting cycle. The metering signal is a pulse-shaped burst signal of a sine wave specified in a designated frequency such as 50 Hz, 12 kHz or 16 kHz, and the metering signal is sent to the public telephone set together with a voice signal transmitted between the calling party and the called party. Therefore, the metering signal must be detected from a signal consisting of the voice signal and the metering signal, for accounting at the public telephone set. The same kind of example can be cited from PBX in a telephone system when a subscriber of PBX speaks with his called party accommodated to a central office of the telephone system. That is, a metering signal same as mentioned above is sent to the PBX from the central office for accounting together with a voice signal transmitted between the subscriber and his called party. Therefore, in order to perform the accounting, the metering signal must be detected from a signal consisting of the voice signal and the metering signal at the PBX.
Same as the above examples, in other communication systems or signal processing system, there are many cases that a designated signal specified in a designated frequency component is required to be detected from an input signal having proper frequency components. In order to detect this kind of designated signal, a phase-lock loop circuit has been widely used in the telephone system, called PLL.
2. Description of the Prior Art
FIG. 1 shows an example of a signal detecting circuit (500) of a prior art used in a telephone system, and signals appearing in signal detecting circuit 500 in FIG. 1 are illustrated in FIGS. 2a, 2b, 2c, 2d and 2e respectively.
As well known, signal detecting circuit 500 consists of a Phase-Lock Loop circuit (PLL) 1 and a phase-lock detector 2 and outputs a detection signal S.sub.d (see FIG. 2e) when signal detecting circuit 500 receives an input signal S.sub.i (see FIG. 2a). In FIG. 2a, input signal S.sub.i is depicted in a style of a rectangle-shaped burst wave and the voice signal mentioned before is omitted, for simplicity. This rectangle-shaped burst wave is produced by limiting and waveform shaping the burst sin wave metering signal mentioned before. Means for limiting and waveform shaping the metering signal is not depicted in FIG. 1.
The PLL 1 consists of a Voltage Controlled Oscillator (VCO) 11, a Phase Comparator (PC) 12 and a Low Pass Filter (LPF) 13. The VCO 11 produces a rectangle-shaped oscillation signal S.sub.11 specified in an oscillation frequency f.sub.11 proportional to a DC voltage V.sub.13 output from LPF 13. The PC 12 compares phases of input signal S.sub.i and oscillation signal S.sub.11 every cycle of S.sub.11 and produces a rectangle-shaped signal S.sub.12 in a duty ratio corresponding to a phase difference (lead or lag) between phases of input signal S.sub.i and oscillation signal S.sub.11 or to a frequency difference between frequencies of S.sub.i and S.sub.11. And LPF 13 outputs DC voltage V.sub.13 to VCO 11 by performing low pass filtering to signal S.sub.12.
When input signal S.sub.i (metering signal) is not given to the signal detecting circuit, the duty ratio of signal S.sub.12 is kept to 50%, DC voltage V.sub.13 is kept to a proper value and oscillation frequency f.sub.11 of signal S.sub.11 is also kept to a proper frequency so-called free-running frequency (f.sub.0). When input signal S.sub.i is given to the signal detecting circuit and a frequency f.sub.i of input signal S.sub.i is higher than oscillation frequency f.sub.11 or when a phase .phi..sub.i of input signal S.sub.i leads a phase .phi..sub.11 of signal S.sub.11, the duty ratio of signal S.sub.12 becomes larger than 50%, resulting in increasing DC voltage V.sub.13 and oscillation frequency f.sub.11. On the contrary, when frequency f.sub.i is lower than frequency f.sub.11 or when phase .phi..sub.i lags behind phase .phi..sub.11, the duty ratio of signal S.sub.12 becomes less than 50%, which results in decreasing DC voltage V.sub.13 therefore lowering oscillation frequency f.sub.11.
When frequency f.sub.i is equal to free-running frequency f.sub.0, the comparison between the phases (or frequencies) of input signal S.sub.i and signal S.sub.11 is repeated in PLL 1 until the phase-lock is established between input signal S.sub.i and signal S.sub.11. When the phase-lock is established, oscillation frequency f.sub.11 becomes equal to frequency f.sub.i and the phase difference (.phi..sub.i - .phi..sub.11) between the phases of signals S.sub.i and S.sub.11 is kept to a fixed value of .pi.. If free-running frequency f.sub.0 or a frequency nearby free-running frequency f.sub.0 is not included in input signal S.sub.i, frequency f.sub.11 and phase .phi..sub.11 of signal S.sub.11 cannot be locked, establishing no phase-lock.
The phase-lock detector 2 consists of an exclusive OR gate 21, an LPF 22, a voltage comparator 23 and a reference voltage source 24. The exclusive OR gate 21 performs exclusive OR operation to input signals S.sub.i and S.sub.11 and produces output signal S.sub.21. The LPF 22 performs low pass filtering to signal S.sub.21 and produces a DC voltage V.sub.22. The voltage comparator 23 compares DC voltage V.sub.22 with a reference voltage V.sub.24 from reference voltage source 24 and produces detection signal S.sub.d which is equal to the output from the signal detecting circuit 500. The detection signal S.sub.d becomes a signal representing an undetected state such as logic "0" when DC voltage V.sub.22 is lower than reference voltage V.sub.24 and becomes a signal representing a detected state such as logic "1" when V.sub.22 is higher than V.sub.24.
In FIG. 1 and FIGS. 2a to 2e, since input signal S.sub.i is not given to signal detecting circuit 500 till t.sub.1 (see FIG. 2a), VCO 11 oscillates in free-running frequency f.sub.0 till t.sub.1 as shown in FIG. 2b, so that signal S.sub.21 becomes a rectangle-shaped signal having 50% duty cycle till t.sub.1 as shown in FIG. 2c. In such state, DC voltage V.sub.22 from LPF 22 is maintained lower than reference voltage V.sub.24, so that voltage comparator 23 outputs detection signal S.sub.d representing the undetected state (logic "0").
When input signal S.sub.i specified in frequency f.sub.i equal or nearly equal to free-running frequency f.sub.O is given to signal detecting circuit 500 in a time interval from t.sub.1 to t.sub.3 (see FIG. 2a), VCO 11 operates so as to bring phase .phi..sub.11 close to phase .phi..sub.i by varying oscillation frequency f.sub.11 of signal S.sub.11 around free-running frequency f.sub.0, so that the phase difference (.phi..sub.i - .phi..sub.11) approaches .pi. (compare FIGS. 2a and 2b near t.sub.3) As the phase difference approaches .pi., the duty ratio of output signal S.sub.21 from exclusive OR gate 21 gradually increases (see a waveform at the time interval from t.sub.1 to t.sub.3 in FIG. 2c) and DC voltage V.sub.22 from LPF 22 also rises as shown in FIG. 2d. Then, the phase-lock is established in PLL 1 and the phase difference (.phi..sub.i - .phi..sub.11) becomes .pi.. When the duty ratio in signal S.sub.21 reaches 100%, DC voltage V.sub.22 becomes reference voltage V.sub.24 at t.sub.2 as shown in FIG. 2d and voltage comparator 23 outputs detection signal S.sub.d representing the detected state (logic "1") as shown in FIG. 2e.
Thus, the free-running state of PLL 1 till t.sub.1 is changed to a phase-lock state at t.sub.2. In other words, the time interval from t.sub.1 to t.sub.2 is a transition time for changing the state of PLL 1 from free-running to phase lock. When input signal S.sub.i is ended at t.sub.3, PLL 1 starts to bring back the state from phase-lock to free-running by a process opposite to the above, passing through the similar transition time to the above, which is not depicted in FIGS. 2a to 2d.
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