1. Field of the Invention
The present invention relates to microprocessors and particularly to microprocessors with a fixedly preset logical address space.
2. Description of the related art
Although the development of microprocessors and microcontrollers, respectively, has lead to significant performance increases, older CPU architectures are still given preference to later architectures in the integration of a CPU in an integrated circuit in certain technical fields of applications, such as in the chip card area or in SOC designs. One reason therefore is that later CPU architectures with a higher performance are often over dimensioned for the respective intended field of application and thus require too much power with regard to the tasks to be performed and take up too much chip area. Another reason to give preference to an older CPU architecture to a newer, more powerful one is that the software development environment for the older CPU architectures, such as the 8051 or 8052 based microcontroller architecture is often more popular with customers and more software designers are available for them.
The problem of the software development environment for older controller architectures, which is more popular with customers, is particularly significant in the chip card area, since here the development of the machine programs processable on the chip card and the executable machine code, respectively, lies not within the responsibility of the chip manufacturer but in the responsibility of the big customers, such as banks and their software development companies as well as the respective operating system development company. Further, due to the high required part number, it is of great significance for the chip card customers to use chip card controllers, which are adapted to the respective requirements to keep the costs as low as possible. Accordingly, in order to satisfy the low-end chip card area as well as to fulfill the wish of some customers for known software development environments, the chip card manufacturer has to be able to provide chip cards, which are based on an older microcontroller architecture.
One problem in using older controller architectures in the chip card production is, however, that their addressing possibilities are not sufficient. Thus, the performance of an 8051 based CPU generally is sufficient in the chip card area to take on the management tasks of a chip card, but due to the high security requirements, cryptography algorithms, which comprise calculating operations with regard to very high operands, have to be processed by cryptoprocessors on the chip card. In the known RSA (Rivest, Shamir and Adleman) algorithm, for example, operand lengths of 1024 are common. Due to these high operand lengths to be processed, as well as the complexity of the cryptoalgorithms themselves, the access to a memory as large as possible is required in chip cards. The problem with using CPUs, which are based on older controller architectures, is that they only allow the addressing of merely small memory sizes. 8051-based CPUs, for example, allow merely the addressing of 64 kBytes.
A possible approach to make a large memory addressable despite the usage of a controller of an older architecture, is to use externally stored descriptors and base addresses, respectively, which determine the position of a memory window to be addressed by the CPU, so that the memory area addressable by the CPU can be shifted over the whole larger memory via the memory window.
To explain the differentiation between a logical address space and a physical address space in more detail, reference will be made to FIG. 6A. In the embodiment shown in FIG. 6A the physical address space extends from an address “00000” to an address “FFFFF”. Thus, the physical address space comprises 1 MByte. It should be noted that a physical memory has to be present not necessarily for every physical address of the physical address space. Rather, the great number of physical address will not refer to a physical memory cell. Particularly in chip cards, one is currently far from providing 1 MByte. Typical sizes for present chip cards comprise 64 kBytes as EEPROM, 4 kBytes as XRAM and 136 kbytes as ROM. However, the flexibility requires designing the physical address space larger to enable a further upgrade of memory chips, depending on requirements and technical development.
Known and fully developed microcontroller architectures based on the 8051 standard support the access to a total of 64 kbyte data and 64 kByte code efficiently. Thus, the logical address space of the microcontroller comprises merely 64 kBytes as it is illustrated on the left in FIG. 6A. In the basic 8051 architecture, the access to larger memory areas (data and code) by known concepts is slow with regard to the required block cycles, and complex and expensive in programming, since additional management codes are required.
For simplifying the access to a larger physical address space, a memory management unit (MMU) was introduced, with the help of which the 64 kByte address space, which is also referred to as logical address space, is remapped to a physical address space of 1 MB. This remapping, however, does not lead to an increase of the logical 64 kByte address space, but that at a certain time still 64 kBytes of a physical address are visible, but that the actually visible 64 kByte address can be changed. Therefore, the MMU is reconfigured by using a descriptor. The descriptor identifies a certain physical memory area, which is 64 kBytes in size and contiguous in the example shown in FIG. 6A. The descriptor is, for example, the lowest address of the visible physical memory area, wherein then the current physical address can be determined by the basic address known by the descriptor and the logical address as “offset”.
For addressing a logical address space with a size of 64 kBytes, addresses with a length of 16 bits, which means 2 bytes, are required.
For addressing a physical address space of 1 MByte, however, physical addresses with a length of 20 bits are required. Since for the identification of different physical memory windows with a length of 64 kBytes, the physical base addresses are merely required in a raster of 64 kbytes, a descriptor with a length of eight bit, which means one byte, is more than sufficient to address all physical memory windows with a size of 64 kbyte. It should be noted that not necessarily the top 8 bits of the physical base address have to be taken as descriptor, but that a table can be stored in a MMU, which contains a descriptor as input information, and outputs, for example, the top 8 bits of the physical base address or the physical base address in full length as output information.
Often, it is not favorable to have a physically contiguous memory area, as is illustrated in FIG. 6A, for certain requirements, such as in chip cards. Instead, it can be much more favorable for certain requirements to see, for example, 16 kBytes of the ROM, 16 kbytes XRAM and 32 kBytes in the EEPROM, but at different positions in the EEPROM.
For that reason, as it is shown in FIG. 6B, the logical address space is divided in, for example, four logical address segments, wherein one descriptor is associated to every address segment, such as descriptor 1, descriptor 2, descriptor 3, descriptor 4. A logical address in the lowest segment is converted into a physical address, which is on the right hand side in the 16 kByte area in FIG. 6B, by the memory management unit by using the descriptor 1.
A logical address in the logical address space, to which the descriptor 2 is associated, is converted in a respective physical address in the 16 kbyte window of the physical address space. Analogous to that, the logical address in the third segment, to which descriptor 3 is associated, is treated.
Further, in FIG. 6B a fourth segment of the logical address space is marked, which is also referred to as a Far segment FS. As well as to the other three segments, a descriptor (descriptor 4) is associated to the Far segment. If a logical address is present in the Far segment, the physical address associated to it is determined by using the descriptor 4, which is also referred to as Far descriptor, and the logical address in the Far segment. In the example shown herein, as agreed, the descriptors 1 to 3 are set to fixedly preset values, while merely the descriptor 4 is variable, as it is illustrated by an arrow in FIG. 6B. If a sequence of instructions, which is processed by the microprocessor, requires that a memory space is accessed, which is not within the four windows illustrated in FIG. 6B with a respective size of 16 kbytes, a logical address has to be generated in the Far segment (FS) together with a changed descriptor 4, by which a MMU is reconfigured, so that the part of the physical memory, where the currently required construction is, becomes visible.
In the following, reference will be made to FIG. 1, to illustrate the processes in a jump to a sub-program and a re-jump from the sub-program in more detail.
FIG. 1 shows an instruction sequence 10, which, for example, comprises a main program (HP) and three sub-programs (UP1, UP2 and UP3).
First, the main program is started. Thereupon, a sequence of instructions of the main program is processed, until an instruction 10a is met. The instruction is jump to sub-program 1 (UP1). The jump is performed to then perform the sub-program (UP1) as illustrated in FIG. 10b. At the end of the sub-program (UP1), as illustrated in FIG. 10c, a re-jump to the main program is made again. Thereupon, the main program is again processed, until an instruction 10d is reached, which says “jump to sub-program 2 (UP2)”. Here, an interleaving is present, in such that first, as illustrated at 10e, part of the sub-program UP2 is processed, that then after processing the part a jump is made to another sub-program UP3 (10f). Then, the sub-program UP3 is performed completely (10g), and a re-jump is made to the sub-program UP2 (10h). Thereupon, another part of the sub-program UP2 is performed, namely the remaining part of it (10i), to re-jump then to main program (10k). Thereupon, further instruction sequences and instruction sub-sequences (sub-programs) are performed, until, finally, the end of the main program (10m) is reached.
No further problems will occur when both the main program and all sub-programs are within the contiguous physical memory window of FIG. 6A or in the non-contiguous physical memory window of FIG. 6B. The call of a sub-program can then be handled with an instruction LCALL (logical address), in such if a CPU, meets, for example, the instruction 10a, takes the argument of the instruction LCALL, which means the logical address of the logical address space, passes it on to the MMU, whereupon the MMU determines the respective physical address by using the descriptor associated to the contiguous logical address space (case of FIG. 6A) or by using the descriptor associated to the logical address segment, wherein the logical address is (case of FIG. 6B). From this physical address, the next instruction in the sequence, which will then be the first instruction of the sub-program, is fetched and performed.
In order for the CPU to continue after the performance of the sub-program in the main program again, which means after a re-jump instruction (10c of FIG. 1), re-jump information is stored. In this case, the re-jump information is the logical addresses, where the next instruction of the main program to be performed is.
Analogous to that, nested sub-programs (row 10d to 10k of FIG. 1) are performed.
If there is not the situation that all sub-programs are stored within the currently visible physical memory window, a call instruction FCALL (physical address) is used. The physical address in the instruction FCALL is expressed by a logical address and a descriptor. If the MMU receives the instruction FCALL and interprets information coming from the CPU as an instruction FCALL, respectively, the MMU is reconfigured by using the obtained descriptor, to retrieve and perform an instruction of the sub-program, such as the sub-program 2 of FIG. 1, from the physical address, which is now within the memory window, by the altered descriptor.
For ensuring a correct re-jump after performing the sub-program UP2, a reconfiguration of the MMU has to be performed again, since the instructions of the main program are within a memory window, which, with high probability, does not coincide with the memory window where the sub-program UP2 is visible. When performing sub-programs in unmapped memory areas, the MMU first has to be configured for the desired address area and after ending, which means after a re-jump instruction or “return”, it has to be restored again. This restoring of the MMU is currently solved within a current compiler/linker solution by a so-called banking concept, which provides a code for setting and resetting for every possible memory bank, i.e., for every possible physical address area of FIG. 6A or FIG. 6B. This concept costs additional code memory in the constantly visible memory and is expensive and complicated.
In the re-jump of a sub-program jumped to by FCALL, the MMU descriptor of the Far segment has to be restored. One possibility for the realization of these different return mechanisms is the usage of two different return instructions, e.g., Ret for LCALL and FRet for FCALL. A return instruction (Ret) is a simple re-jump, which does not require any descriptor change, while the other return instruction is a Far return instruction, where the MMU has to be reconfigured to the old descriptor, which means the descriptor “from which” an original jump has taken place.
A disadvantage of this concept is particularly the usage of two different return instructions, since these instructions require interventions into the sub-programs. Typically, every sub-program is terminated with a return instruction. Sub-programs, however, exist already as preconstructed software components, which are only reluctantly intervened in, or which cannot be intervened at all, for example when the chip card manufacturer would be required to do so. For security reasons, it is often the case that the chip card manufacturer merely provides the hardware with specification, and that the actual sub-programs, such as cryptographical programs, etc., are developed by the user and loaded to the chip card. In other words, this means that often, particularly in security relevant applications, the chip card manufacturer himself has no access to the sub-programs or is not supposed to have access, to modify, for example the return instructions of the individual sub-programs from case to case into Far return instructions or simple return instructions.
An additional reason for using a return instruction for both options is that a software program can be jumped to both with FCALL and with LCALL (depending on current visibility).
Thus, such a procedure would, if it is possible at all, lead to increased effort (costs) and accompanying increased error-liability.
USPTO Backgrounds
USPTO Backgrounds