Field
This disclosure relates generally to integrated circuits (ICs), and more specifically, to protection from transient electrical stress (TES) events for integrated circuits.
Related Art
Electronic circuits are designed to operate over limited voltage ranges. Exposure to voltages beyond those limited voltage ranges can damage or destroy those circuits. The problem is particularly notable for integrated circuits, which often have many external terminals connected to circuitry fabricated on a very small scale.
While transient voltage suppression circuits for integrated circuits exist, they tend not to function well for both unpowered transient events (i.e., those transient events occurring when the integrated circuit is not powered up for normal operation) and powered transient events (i.e., those transient events occurring when power is applied to the integrated circuit for normal operation). Unpowered TES events may include, but are not limited to, Electrostatic Discharge events (ESD), for example Human Body Model (HBM), Machine Model, or Charged Device Model (CDM) events. Powered TES events may include, but are not limited to, Powered ESD (PESD), Electric Fast Transient (EFT), Power Surge, or Ring Wave events.
USPTO Backgrounds
USPTO Backgrounds