In the field of microelectronics, an electrostatic discharge can occur throughout the lifetime of an integrated circuit and can constitute a significant problem with regard to the reliability of that integrated circuit, as well as a major cause of failure.
An electrostatic discharge generally results in a more or less large and more or less short current peak. An ESD protection device must therefore evacuate this current peak. Moreover, this current peak induces thermal stress in the protection device. A conventional ESD protection component comprises a triac.
The production of such a protection component using a technology of the solid substrate type easily allows the dissipation of the heat generated by the ESD pulse through the contacts and the solid substrate in which the protection component is produced.
This being so, other types of technology exist and, in particular, the technologies using a substrate of the silicon on insulator type. Such a substrate comprises a layer of silicon positioned on top of a buried substrate commonly referred to by those skilled in the art by the acronym “BOX” (Buried Oxide). The components are then produced in this layer of silicon.
In a partially depleted SOI technology (PDSOI: Partially Depleted SOI) with a 65 nm technology node, the thickness of the buried oxide is of the order of 145 nm and that of the layer of silicon on top of this buried oxide is of the order of 60 nm.
In a fully depleted SOI technology (FDSOI: Fully Depleted SOI), the thickness of the buried oxide is variable as is that of the layer of silicon. By way of example, the thickness of the buried oxide can be of the order of 145 nm and that of the layer of silicon on top of this buried oxide can be of the order of 7 nm. Lesser thicknesses are also possible, for example of the order of 10 or 20 nanometers for the buried oxide.
In an SOI technology, the presence of the buried oxide prevents the evacuation of heat in the downward direction, that is to say through the silicon situated under the buried oxide, thus reducing the volume available for this thermal evacuation. Moreover, in the FDSOI technology, the very small volume available has a negative impact on the reliability of the triacs formed in the thin upper layer of silicon.
Finally, in an SOI technology, and especially in the FDSOI technology, there can be up to six decades (orders of magnitude) of difference between the concentration of dopants in an N+ zone of a triac and that of an intrinsic P zone, which results in an extremely large depleted zone of the associated PN junction and therefore in a virtual absence of energy gap, which results in triggering voltages and holding voltages that can be very low and even lower than the power supply voltage of the device.
Moreover, in general, ESD protection devices of the triac type are associated with triggering circuits, for example MOS transistors whose gate and substrate are connected to earth (GGNMOS transistors), connected to their gate. This of course has a negative impact on the surface dimensions of the assembly. What is needed is a device that ameliorates or overcomes the shortcomings of the prior art.
USPTO Backgrounds
USPTO Backgrounds