The present invention relates to metal oxide semiconductor field effect transistors (MOSFETs) and more particularly to MOSFETs having elevated sources and drains.
MOSFETs fabricated in silicon usually have a generally planar structure as illustrated in FIG. 1. The MOSFET device is formed in a region of silicon 1 surrounded by a silicon oxide barrier 2. The barrier 2 is formed using a self-aligned oxidation process in which surface regions of the silicon wafer are oxidised, and the resulting silicon oxide expands to extend above the wafer surface. Within the active region 1, a gate oxide 3 is grown on top of the MOSFET channel 4 and a metal gate 5 deposited on top of the gate oxide 3. At each end of the channel 4, a lightly doped region 6 is formed in the planar wafer surface by implantation, before sidewall spacers 7 (usually silicon oxide) are formed on either side of the metal gate 5. Heavily doped source and drain regions 8,9 are formed in the wafer surface, i.e. in the same plane as the lightly doped regions 6 and the channel 4, by contact diffusion.
Although the structure of the MOSFET shown in FIG. 1 represents a standard MOSFET design, it still presents a number of serious problems. Firstly, transistors made to this design suffer from so-called xe2x80x9cshort channelxe2x80x9d effects when the gate length (i.e. the distance between the heavily doped drain regions 8,9) is very short. Where high electric fields are present, electrons can be accelerated to their maximum velocity within the channel 4. At this velocity, and in the high electric fields next to the drain 9, hot electrons can damage the insulating gate oxide 3 as well as cause increased leakage currents through ionisation. The electric field ionises electrons and holes near the drain site of the device which can lead to damage in the vicinity of the drain. Charges can build up as a consequence of this damage, reducing parameters such as gain (beta) or transconductance (gm). FIG. 2 illustrates the current flow along the surface of a planar MOSFET device.
Another problem presented by the MOSFET structure of FIG. 1 is the classic short-channel effect. This conventional short channel effect arises due to the depletion region which is formed in any semiconductor diode junction. In a MOSFET, the drain to channel region gives rise to just such a diode and therefore has a depletion region surrounding it. As the drain voltage increases, as would be the case for a MOSFET wired into a functional circuit, the depletion region spreads outwards. This removes charge from under the gate region and lowers the threshold voltage for the device. In the extreme, the depletion region lowers the threshold so much that the transistor enters a triode-like mode of operation known as xe2x80x9cpunch-throughxe2x80x9d.
A further problem with MOSFETs of the type shown in FIG. 1 results from the method used to provide electrical contact to the source and drain regions 8,9. Typically, technologies of 0.35 microns and below use silicide material to form a low resistance path from the metal connectors to the contact diffusion 8,9. FIG. 3 illustrates a typical MOSFET with silicided source, drain (and gate), where the silicide regions are indicated by reference numeral 10. The material which forms the silicide 10 (e.g. titanium) is deposited onto the source and drain 8,9 and subsequently processed so that the material forms a silicide region. This process requires the surface of the source/drain to react with the deposited material and a proportion of the original source/drain 8,9 is consumed. As the source and drain 8,9 are made shallower, the volume of silicon available to form a silicide, whilst still retaining the electrical diode junction, is reduced. In order to main the characteristics of the MOSFET, the silicon has to be topped up with an epitaxial layer, or the junctions have to be made deeper than would otherwise be optimal.
An alternative MOSFET structure has been proposed and has been presented as overcoming the problems of planar MOSFETs as described above. This alternative structure is known is an xe2x80x9celevatedxe2x80x9d source and drain structure. An elevated source-drain MOSFET is illustrated in FIG. 4 and can be seen to comprise a planar base layer 11 in which an active channel 13 is defined between two lightly doped regions 14. The heavily doped source and drain regions 15,16 lie above this planar region and more particularly above the plane of the active channel 13. The metal gate 17 is formed above the active channel 13 and between the source 15 and drain 16.
It has been shown that the elevated source-drain MOSFET can offer improved resistance against hot electron damage by moving the drain diffusion 16 away from the main current flow path. The elevated source and drains 15,16 also provide additional material available for silicidation allowing a lower resistance silicide to be formed even in transistors with junctions of less than 0.1 microns. Finally, by moving the heavily doped drain 16 away from the channel region 14, the spread of the depletion region under the gate 17 is eliminated or at least substantially reduced. The parasitic junction capacitance is also reduced as the total surface area of the junction is reduced and the overall performance of the MOSFET is enhanced.
A number of elevated source drain MOSFET structures have been proposed: see for example (1) Wakabayashi, H. xe2x80x9cA High Performance 0.1 micron CMOS with Elevated Silicide Using Novel SI-SEG Processxe2x80x9d, IEDM, 1997, pp97-102; (2) Shibata, H. xe2x80x9cHigh Performance Half-Micron PMOSFETS with 0.1 micron Shallow PN Junctions Utilising Selective Silicon Growth and Rapid Thermal Annealingxe2x80x9d, IEDM, 1987, pp590-593: (3) Mazure, C. xe2x80x9cFacet Engineered Elevated Source Drains by Selective Si Epitaxy for 0.35 micron MOSFETsxe2x80x9d, SSDM, 1195, pp538-539; and (4) Chau, M. xe2x80x9cLow Resistance Ti or Co Silicided Raised Source/Drain Transistors for Sub 013 m CMOS Technologyxe2x80x9d, IEDM, 1997, pp103-107. In these earlier proposals, the elevated source and drain are formed by epitaxially growing additional silicon on top of a planar silicon substrate. A problem with this approach is that an epitaxial silicon deposition reactor is required. Furthermore, the selective deposition of silicon is difficult to control and is a technique which is rarely, if ever, used in production.
It is an object of the present invention to overcome or at least mitigate the above noted disadvantages of existing elevated source-drain MOSFET structures. This and other objects are achieved at least in part by forming an elevated source-drain structure by etching into a substantially planar silicon substrate to form a recessed channel region between the source and drain.
According to a first aspect of the present invention there is provided a method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, the method comprising the steps of:
defining a MOSFET region on the surface of a semiconductor substrate;
removing a central area of said MOSFET region down to a predefined depth to form a recess in the substrate; and
doping areas on either side of said recess to provide a drain and a source,
wherein the active channel of the MOSFET device is provided wholly beneath a planar base of said recess.
Embodiments of the present invention provide a fabrication method which is simplified relative to existing methods of fabricating elevated source-drain MOSFETs.
It will be appreciated that the invention is not limited by the order in which the steps of the method of the invention have been presented. The steps may be carried out in any suitable order.
Preferably, the semiconductor substrate in which the MOSFET is fabricated is a silicon substrate. More preferably, the step of removing a central area of said MOSFET region comprises oxidising a region of silicon at the surface of the wafer and removing at least a part of the resulting oxide by etching.
Preferably, the method comprises controlling the steps of oxidation and/or etching such that said recess has sloping side walls. More preferably, said side walls slope at an angle of 45xc2x0 relative to the surface of the silicon wafer, with the recess being wider at its upper end relative to its lower end.
Preferably, the method comprises the steps of:
(1) forming a layer of silicon oxide on the surface of a silicon substrate;
(2) forming a masking layer on the surface of the silicon oxide;
(3) patterning the masking layer to expose a region of silicon oxide;
(4) further oxidising a region of the silicon substrate beneath the exposed region of silicon oxide;
(4) etching away said exposed region of silicon oxide and at least a part of the underlying silicon oxide.
More preferably, said masking layer is a layer of silicon nitride. The masking layer may additionally be used to provide a mask for forming an isolation barrier around the periphery of the MOSFET device.
More preferably, the method comprises the further steps of:
(6) forming a gate above the etched region;
(7) doping source and drain regions of the silicon substrate on either side of the etched region; and
(8) forming respective electrical contacts with the source and drain regions.
Steps (6) to (8) may each comprise multiple sub-steps and may be performed in any suitable order.
Preferably, the method of the present invention comprises in sequence:
forming said recess in the substrate;
forming a gate in said recess;
lightly doping source and drain regions adjacent to the base of said recess;
forming gate sidewalls of an insulating material such that the sidewalls cover a fraction of the doped source and drain regions proximal to the gate; and
heavily doping the lightly doped source and drain regions except for the fractions masked by the gate sidewalls.
In order to enable electrical contact to the source, drain, and gate regions, the surfaces of these regions may be silicided.
According to a second aspect of the present invention there is provided a MOSFET device fabricated using the method of the above first aspect of the present invention.
According to a third aspect of the present invention there is provided a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device in a region of a semiconductor substrate, the device comprising:
a central region provided by a recess in the substrate; and
doped source and drain regions on either side of said recess,
wherein the active channel of the MOSFET device is provided wholly beneath a planar base of said recess.
Preferably, the active channel of the MOSFET lies wholly beneath a substantially planar base of said recess.
Preferably, said source and drain regions each comprise a lightly doped region in contact with the active channel and a heavily doped region in contact with the lightly doped region and lying substantially above the lightly doped region. More preferably, each said lightly doped region lies beneath the plane of the base of the recess.
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