1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate. Thereafter, the gate provides an implant mask during the formation of source and drain regions by ion implantation, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
An important parameter in IGFETs is the threshold voltage (V.sub.T), which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel. There are, however, exceptions to this general rule. For example, depletion-mode devices already have a channel with zero gate voltage, and therefore are normally on. With N-channel depletion-mode devices a negative gate voltage is required to turn the devices off, and with P-channel depletion-mode devices a positive gate voltage is required to turn the devices off.
Depletion-mode devices are often used as nonlinear load circuits to provide a more favorable current-voltage relationship than is possible with linear load circuits using resistors or enhancement-mode devices. Enhancement-mode devices are often used as switches in digital circuits to prevent or allow the flow of electrical currents.
Enhancement-mode and depletion-mode devices are often fabricated on the same semiconductor substrate or chip to provide an integrated circuit such as a microprocessor. An array of devices can be fabricated in an integrated circuit layout, with some adjusted by implantation to obtain the desired enhancement-mode doping and others implanted to become depletion loads. A separate implantation step is typically used to provide some channel regions with depletion-mode doping while others retain enhancement-mode doping.
For example, prior to gate oxide formation, a masking layer can cover the device regions intended for enhancement-mode devices while providing openings over device regions intended for depletion-mode devices, and then the structure can be subjected to ion implantation so that only the exposed device regions are provided with depletion-mode doping.
Alternatively, after-gate implantations (such as wells, channel-stop doping, V.sub.T control, source/drain, etc.) can be used to provide depletion-mode doping after the gates are patterned. Studies indicate that after-gate implantations do not degrade the gate oxide integrity or the device characteristics. For example, U.S. Pat. No. 4,329,186 to Kotecha et al. discloses a technique for forming enhancement-mode and depletion-mode devices, in which after the gates are formed, a photoresist layer is patterned to cover some gates and expose other gates, and then ions are implanted through the exposed gates directly into the underlying channel regions to provide depletion-mode doping in these channel regions. Since the photoresist layer provides an implant mask, the channel regions underlying the gates covered by the photoresist layer retain enhancement-mode doping.
A drawback to these approaches, however, is that a separate implantation step is required to provide depletion-mode doping in selected channel regions.
A problem encountered in P-channel devices with polysilicon gates containing a high concentration of boron is that when a thin gate oxide is used, poor V.sub.T control may arise due to unwanted boron penetration into the gate oxide, or further, into the underlying channel region. It is reported that boron will penetrate gate oxides that are less than 125 angstroms thick during a 900.degree. C. 30-minute post-implant anneal in nitrogen. It has also been found that the presence of fluorine in the gate oxide worsens the boron penetration problem. Such fluorine can be introduced into the gate oxide if boron difluoride (BF.sub.2) is the implant species. Unfortunately, in some instances, the boron penetration may be sufficiently large to provide depletion-mode doping in channel regions intended for enhancement-mode devices.
Accordingly, a need exists for an improved method of making enhancement-mode and depletion-mode IGFETs in the desired device regions that reduces the number of implant steps.
USPTO Backgrounds
USPTO Backgrounds