1. Field of the Invention
This invention relates to a Thin-Film Transistor array structure. More particularly, this invention relates to a Thin-Film Transistor array structure for sustaining all capacitance-coupling effects between a pixel electrode and a data line of a panel.
2. Description of Prior Art
For the manufacture of a Thin-Film Transistor (TFT) array of a panel, especially in the case of those with a larger size, the exposure process on the TFT has to be divided and proceeded by several steps.
However, the alignment of the layers between each two adjacent exposed blocks of the TFT is easily dislocated during the exposure process, and the capacitance-coupling effects between a pixel electrode and a data line on each of the adjacent exposed blocks are very different. Thus, the penetrating rates of each block of the TFT are different in typical TFT structures.
Referring to FIG. 1A, FIG. 1A is a plan view showing the structure of one pixel of typical TFT structure. Symbol xe2x80x9cCExe2x80x9d represents a common electrode, symbol xe2x80x9cSLxe2x80x9d represents a scanning line, symbol xe2x80x9c10xe2x80x9d represents a TFT, and symbol xe2x80x9cDLxe2x80x9d represents a data line. The source electrode 12 of the TFT 10 is coupled to an ITO electrode (i.e. pixel electrode) 16 via a contact hole 14 formed on an isolated layer, and the data line DL is coupled to a drain electrode 18 of the TFT 10.
FIG. 1B is a cross-section according to a line Ixe2x80x94I of FIG. 1A. A distance xcex94d existing between the data line DL and the ITO electrode 16 is formed during the exposure process and is an important parameter related to the capacitance-coupling effect of two adjacent blocks of the TFT 10. Once the distance xcex94d exceeds a predetermined value, the capacitance-coupling effect of the adjacent blocks is easily affected and causes a visible line on the panel.
To solve the above problem, the primary object of this invention is to provide a TFT array structure, which comprises a Thin-Film Transistor, a data line, a scanning line, a pixel electrode and an auxiliary electrode. The data line is connected to the drain of the Thin-Film Transistor, and the scanning line is connected to the gate of the Thin-Film Transistor. The scanning line is oriented substantially orthogonally with respect to the data line to form a plurality of rectangular pixels in matrix. The auxiliary electrode is formed at the place where the pixel electrode is close to the edge of the data line, and the auxiliary electrode is coupled to the pixel electrode and located at a mask on which the data line is located. The capacitance-coupling effect generated between the pixel electrode and the data line is the same as that generated between the predetermined electrode and the data line, and the performances of all pixels are uniform despite errors occurring during the aligning process on the pixel electrode.
USPTO Backgrounds
USPTO Backgrounds