1. Field of Invention
The present invention relates to an integrated circuit. More particularly, the present invention relates to an I/O pad of an integrated circuit. The I/O pad can export signals with a delay time.
2. Description of Related Art
The usual manner for transmitting data needs an enabling control circuit device, so as to control the ON/OFF status of the transmitting circuit. This can save consumption of the resource of the data bus in integrated circuit (IC) operation. The data bus is the data transmitting bridge between two IC's, so as to allow the data to be transmitted in proper efficiency.
While the data is under transmission, the enabling control circuit would enable a data transmitting circuit, so that the data transmitting circuit starts to transmit desired data to the data bus. During the transmitting period, the enabling control circuit continuously drives the data transmitting circuit, so as to avoid interruption of data transmission. After the data are completely transmitted, the enabling control circuit then issues an disable signal, which can stop the operation of data transmission and puts the circuit at the OFF status, so that the resource for operating the IC can be saved.
In the above manner, it has no difficulty or defect for the operation at low frequency. Data can be successfully transmitted from one circuit to another circuit. However, the high frequency transmitting technology has greatly developed for use. In the data transmitting process operated at high frequency operation process, the delay time due to a delay of the data bus could be too large when comparing with time of the high frequency. In this situation, while the data are still under transmitting, the IC has finished data transmitting. By the normal operation, the enabling control circuit then turns OFF the IC circuit. However, the data are not yet completely transmitting to the data bus. This also means that the voltage level still does not achieve a stable status. The driving voltage does not continue to drive the data transmitting action, due to the OFF of the IC circuit.
With respect the foregoing operation principle, FIG. 1 shows the structure diagram of a conventional I/O pad. In FIG. 1, INT data are input to the I/O pad. By the path of data bus 12, input data are output to the desired IC. The enabling control circuit 14 in the I/O pad 10 judges the INT data to determine whether data are still continuously transmitting data to the I/O pad 10. Accordingly, the enabling control circuit 14 also issues an output enabling signal, which triggers the tri-state buffering circuit 16 to the data bus 12. When the data transmission from INT has finished, the enabling control circuit 14 does not issues the output enabling signal. As a result, the tri-state buffering circuit 16 stops operating, and the I/O pad has finished one action of data transmission.
FIG. 2 is the output signal waveform for the conventional I/O pad. In FIG. 2, data at the firs period 20, the second period 22, the third period 24 can be successfully transmitted. However, during the fourth period 26, since the delay of transmission occurs, the data haven't been completely transmitted to the data bus yet, but the I/O pad has been Off. This causes the data within the fourth period is incomplete. This problem occurs at the operation under high frequency.
USPTO Backgrounds
USPTO Backgrounds