The present invention relates, in general, to the field of integrated circuit (IC) logic devices. More particularly, the present invention relates to nonvolatile memory ICs and to the integration of nonvolatile memory elements with logic in the form of a nonvolatile latch and D-type register.
The semiconductor industry has employed transparent latches and D-type registers (also known as D-type flip-flops) for many years. These are ordinary complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) and transistor-transistor logic (xe2x80x9cTTLxe2x80x9d) circuits often referred to as members of the standard logic family. Standard logic parts have a variety of uses, but the information they contain while working is volatile. That is, the state of the logic is lost when power is removed. Similarly, the industry has employed nonvolatile memory for many years. These memory devices allow users to store information in nonvolatile form by supplying addresses and the data to be stored. To date, no one has merged these functions to create a standard logic device that retains its state in the absence of power.
What is desired, therefore, is a nonvolatile octal transparent latch that operates just as an industry standard CMOS version, except that the state is retained in the absence of power and is restored when power returns. Likewise, what is also desire is a nonvolatile octal D-type register that operates just as its industry standard counterpart, except that its state is nonvolatile and is automatically restored on power up.
It is an object of a nonvolatile octal latch embodiment of the present invention to provide a user controlled (as opposed to embedded) transparent latch with a nonvolatile shadow circuit to retain its state in the absence of power. Eight CMOS user controlled transparent latches are ideally provided in an industry standard product pin-out configuration each having nonvolatile shadow equivalents. The latch of the present invention maintains a volatile copy of the nonvolatile storage element contents for comparison purposes in order to avoid reading of the nonvolatile structure. The octal latch product of the present invention compares the state of each CMOS latch to the reference value and writes only changes of state to the nonvolatile shadow circuit to reduce write endurance cycles. The state of the latch, not the input, is monitored to store only latched conditions to reduce nonvolatile write cycles. Circuitry is provided to detect the status of power and to restore the state of the CMOS user latch on power up automatically from a nonvolatile shadow latch. The user state of the CMOS latch is restored by reading the nonvolatile shadow, placing the data in the input of the user latch, and creating an internal (not user generated) latch enable signal to load it. User access to internal latches through the inputs is prevented while the state is being restored.
It is an object of a nonvolatile D-type register embodiment of the present invention to provide a user controlled (as opposed to embedded) D-type register with a nonvolatile shadow element to retain its state in the absence of power. Eight CMOS user controlled D-type registers are provided in the product pin-out configuration each having nonvolatile shadow equivalents. A volatile copy of the nonvolatile storage element contents are maintained for comparison purposes, to avoid reading the nonvolatile structure. The state of each CMOS D-type register is compared to the reference value and only changes of state are written to the nonvolatile shadow to reduce write endurance cycles. The state of the D-type register, not the input, is monitored to load only stored conditions in nonvolatile memory in order to reduce nonvolatile write cycles. Circuitry is provided to detect the status of power and to restore the state of the CMOS user D-type register on power up automatically from a nonvolatile shadow storage. The user state of the CMOS D-type register is restored by reading the nonvolatile shadow, placing the data in the input of the register and creating an internal (not user generated) clock signal to load it. User access to internal D-type registers through the inputs is prevented while the state is being restored.
According to the present invention an octal latch or D-type register product is disclosed with an industry standard logic pin-out and configuration but having nonvolatile properties such as automatically recording the output state in nonvolatile form and restoring it on power up. The nonvolatile memory elements are ideally provided by a ferroelectric capacitor, using well known ferroelectric materials as lead ziconate titanate (PZT), SBT, or BST, or other well known ferroelectric materials. Non-volatility can also be provided by EEPROM, Flash, SNOS, or other writeable nonvolatile technologies. The benefits due to ferroelectric technology are related to writing all state changes. Other nonvolatile technologies can be used with power down writes and these can also be used with the present invention. It is also possible to configure the transparent latch or D-type register of the present invention to maintain a nonvolatile copy of the user-controlled latch that is written with the last state on power down.
Particularly disclosed herein is an integrated circuit device comprising a volatile latch circuit having data and latch enable input terminals and a data output terminal thereof. The volatile latch circuit is operative such that a data signal applied to its data input terminal is passed to the data output terminal when a clock signal applied to the latch enable input terminal is in a first state thereof and the data signal is latched when the clock signal is in a second state thereof. The device further comprises a nonvolatile circuit section including a nonvolatile latch circuit. The nonvolatile latch circuit stores the data signal latched in the volatile latch circuit when the clock signal is in the second state thereof, and the nonvolatile circuit section is operative for restoring the data signal stored in the nonvolatile latch circuit to the volatile latch circuit in the event that power to the integrated circuit device is interrupted.
Also particularly disclosed herein is a method for providing a nonvolatile integrated circuit logic device comprising the steps of latching a first data value in a volatile latch circuit; also latching the first data value in an associated nonvolatile latch circuit; monitoring a supply voltage level to the logic device; and retaining the first data value in the nonvolatile latch circuit when the monitored supply voltage level falls below a predetermined minimum level.
USPTO Backgrounds
USPTO Backgrounds