1. Field of the Invention
The present invention relates generally to a duty cycle correction circuit and, more particularly, to a duty cycle correction circuit correcting a duty of a clock input signal so as to exchange data on both edges of rising and falling of clock.
2. Description of the Related Art
Generally, a clock signal is employed as a basic signal in processing signals of a semiconductor integrated circuit and of other electronic circuits. In a semiconductor memory device, the clock signal includes an external clock signal inputted from the exterior of the semiconductor memory device and an internal clock signal employed in the interior of the semiconductor memory device. The difference between the external clock signal and the internal clock signal is referred to herein as a duty rate or a duty.
As a conventional semiconductor memory device, DRAM inputs and outputs data on a rising edge of a clock signal. However, it is desirable to exchange data on both edges of a clock signal, that is, on both the rising and falling edges, in order to improve a data transmission rate.
However, in the conventional semiconductor memory device, the external clock signal, inputted from the exterior, is inputted with duty errors (40:60 or 60:40). Therefore, there is a problem that it is difficult to exchange data on both the rising and falling edges of a clock signal.
Therefore, the present invention has been made to solve the above-mentioned problems and an object of the present invention is to provide a duty cycle correction circuit capable of exchanging data on both rising and falling edges of a clock signal by correcting duty errors of the input clock signal by using a multi phase signal generator.
In order to accomplish the above object, the present invention comprises: a phase detection unit for receiving an input clock signal and a reference clock signal to generate a phase difference detection signal comparing the phase difference; a loop filter unit for converting the phase difference detection signal into a voltage signal and outputting the inverted signal; a multi phase signal generation unit for generating a clock signal having a plurality of phase differences by controlling the delay time of the input clock signal and selecting and outputting one clock signal by means of a the voltage signal; and a duty correction unit for receiving the input clock signal and the clock signal outputted from the multi phase signal generation unit and logically combining then, to correct the duty of input clock signal.
When the reference clock signal has a phase difference of 360xc2x0 with respect to the input clock signal, the multi phase signal generation unit generates 4 clock signals respectively having phase differences of 90 xc2x0 if the phase of the input clock signal corresponds with that of the reference clock signal.
When the reference clock signal has a phase difference of 720xc2x0 with respect to the input clock signal, the multi phase signal generation unit generates 8 clock signals respectively having phase differences of 90xc2x0 if the phase of the input clock signal corresponds with that of the reference clock signal.
The multi phase signal generation unit comprises: a first phase signal generation unit for generating, by means of the voltage signal, a first clock signal having a phase of 90xc2x0 with respect to the input clock signal; a second phase signal generation unit for generating, by means of the voltage signal, a second clock signal having a phase of 180xc2x0 with the input clock signal by controlling the delay of the first clock signal; a third phase signal generation unit for generating, by means of the voltage signal, a third clock signal having a phase of 270xc2x0 with the input clock signal by controlling the delay of the second clock signal; and a fourth phase signal generation unit for generating, by means of the voltage signal, a clock signal having a phase of 360xc2x0 with the input clock signal by controlling the delay of the third clock signal.
The duty correction unit comprises: a first frequency division unit for receiving a clock signal from the multi phase signal generation unit as its clock input signal and its output signal as an input signal to generate a two-frequency divided signal of the clock signal; a second frequency division unit for receiving the input clock signal as a clock input signal and its output signal as an input signal to generate a two-frequency divided signal of the input clock signal; and a logic operation unit for receiving the two signals respectively of the two-frequency divided signal generated by the first frequency division unit and the second frequency division unit to generate an exclusive OR logic operated signal.
The first frequency division unit comprises a first D-flip flop and a first inverter for receiving the output signal of the first D-flip flop and outputting the inverted signal.
The second frequency division unit comprises a second D-flip flop and a second inverter for receiving the output signal of the second D-flip flop and outputting the inverted signal.
The logic operation unit comprises an exclusive OR gate.
USPTO Backgrounds
USPTO Backgrounds