Phase-locked loops (PLLs) are an integral part of many electronics circuits and are particularly important in communication systems or circuits. Depending upon a particular desired application, the PLL may be implemented in a number of different ways i.e., fully-analog implementations, fully-digital implementations, and/or software implementations. Furthermore, two or more PLLs may be coupled together in implementations for various applications. For example, in a frequency multiplier circuit, two or more PLLs may be coupled to provide a certain desired frequency.
The PLL may further be subdivided into two main architectures i.e., a divider-based digital PLL (DPLL) or a divider-less DPLL architecture. The divider based DPLL employs a fractional divider whose ratio may dynamically change in response to a detection of a phase difference between, for example, an output signal of the DPLL and an input signal to the DPLL. As opposed to the divider-less DPLL, the divider-less DPLL does not utilize a fractional divider in its circuitry.
In current designs of the divider based and the divider-less DPLL, there is a need to lower power, area, and complexity, while having better noise shaping and reduction of fractional spurs.
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