In a semiconductor device fabrication process, a wafer having a device area with a plurality of devices partitioned by a plurality of division lines is divided into individual dies. This fabrication process generally comprises a grinding step for adjusting the wafer thickness and a cutting step of cutting the wafer along the division lines to obtain the individual dies. The grinding step is performed from a back side of the wafer which is opposite to a wafer front side on which the device area is formed.
In known semiconductor device fabrication processes, such as Wafer Level Chip Scale Package (WLCSP), the device area of the wafer is formed with a plurality of protrusions, such as bumps, protruding from a plane surface of the wafer. These protrusions are used, for example, for establishing an electrical contact with the devices in the individual dies, e.g., when incorporating the dies in electronic equipment, such as mobile phones and personal computers.
In order to achieve a size reduction of such electronic equipment, the semiconductor devices have to be reduced in size. Hence, wafers having the devices formed thereon are ground in the grinding step referred to above to thicknesses in the μm range, e.g., in the range from 30 to 100 μm.
However, in known semiconductor device fabrication processes, problems may arise in the grinding step if protrusions, such as bumps, protruding from a plane surface of the wafer are present in the device area. Specifically, due to the presence of these protrusions, the risk of breakage of the wafer during grinding is significantly increased. Further, if the wafer is ground to a small thickness, e.g., a thickness in the μm range, the protrusions of the device area on the front side of the wafer may cause a deformation of the wafer back side, due to the reduced thickness of the wafer and the pressure applied thereto in the grinding process. This latter effect is referred to as “pattern transfer”, since the pattern of the protrusions on the wafer front side is transferred to the wafer hack side, and results in an undesired unevenness of the back side surface of the wafer, thus compromising the quality of the resulting dies.
Moreover, the presence of the protrusions in the device area of the wafer also significantly increases the risk of damage to the wafer in the cutting step referred to above. In particular, due to the reduced wafer thickness after grinding, the sidewalls of the dies may crack in the cutting process, thus severely damaging the resulting dies.
Hence, there remains a need for a reliable and efficient method of processing a wafer having a device area with protrusions formed on one side thereof which allows for any risk of damage to the wafer to be minimised.
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USPTO Backgrounds