Large synchronous electrical systems, such as e.g. computers, are traditionally constructed so that each desired function is successively broken down into smaller and smaller partial functions or operations. In the end there is a collection of operations which each can be executed within one clock period. The transmission of the results to a subsequent operation should timewise be included in the same clock period. Alternatively, the transmission can take place in the subsequent clock period. However, in this case the performance of the system is reduced. In order to insure that all the parts of the system work synchronously, a common reference signal or clock is distributed for the whole system. This traditional construction means that an upper limiting frequency for the system is obtained which is inversely proportional to the area of the system.
Currently, the ambition is to have faster and faster systems with higher and higher clock frequencies, preferably in the order of several GHz in order to be able to increase the performance of the system. The clocks in this case can work within a certain propagation area where the propagation time for the clock signal is relatively short in relation to the cycle time.
It is easy to estimate the limiting frequency for a digital system with a physical size of 30 cm.times.30 cm. An example of such a system is a portable Personal Computer (PC). However, the present invention is not to be limited to computers but applies to any digital system whatsoever. With the assumption that the system is built upon a circuit board with a dielectric constant .di-elect cons.=5, the propagation speed v=c/.sqroot..di-elect cons., where c=the speed of light in a vacuum. The transport time from one circuit block in one corner to a circuit block in a diametrically opposite corner can in this case be T.sub.d =2L/v, where L is the length of the sides of the system, if the conductors run along the sides. In this case T.sub.d will be approximately 4.5 ns. It is assumed that for every block the input signal is stable before the beginning of the current clock period, and that the operation is performed and transported to the subsequent block within the clock period. Just taking account of the propagation speed of the signal means that the clock period is limited down to about 9 ns. This gives a maximal theoretical clock frequency of approximately 100 MHz for the system. The time for the performance of the operations, the limited drive capacity of the components, RC-delays etc often reduce the maximal clock frequency to 10-40 MHz.
The constituent components can often work at considerably higher frequencies, in the order of several GHz. It is obvious that the traditional way of construction and traditional assumptions result in the performance for the system which, by a long way, does not correspond to the performance of the constituent components.
This problem has been noticed earlier and a solution is suggested in German Patent document DE-A1-44 12 419. This document shows a system which can be divided into partial circuits. In each partial circuit there is at least one signal buffer. The partial circuit receives a reference clock signal as an input signal. The partial circuit also has a sequential connection that is driven as a reaction to a clock signal which is synchronized with the reference clock signal. An output signal from the sequential connections is fed back to the input. With a phase-locked connection, the timing signal is synchronized with the reference clock signal to the sequential connection through the clock signal being phase-controlled. This means that it is the reference clock signal source which directly gives the clock signal for the partial circuit and that it is the incoming clock signal which is phase-shifted.
A circuit, e.g. comprising internal registers, which is equipped with its own clock signal generator with a phase-locked loop is shown in U.S. Pat. No. 5,204,555. The clock signal generator is not phase-adjustable. It receives a reference clock signal from the surroundings and converts the reference clock signal frequency to a higher or lower frequency. The object of this arrangement is to be able to make, for example, internal registers work faster than the surrounding circuits. No phase-shifting is necessary in such a connection.
USPTO Backgrounds
USPTO Backgrounds