Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 discloses a split gate non-volatile memory cell. FIG. 1 illustrates an example of such a split gate memory cell formed on a semiconductor substrate 12. Source and drain regions 16 and 14 are formed as diffusion regions in substrate 12, and define a channel region 18 there between. The memory cell includes four conductive gates: a floating gate 22 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 16, a control gate 26 disposed over and insulated from the floating gate 22, an erase gate 24 disposed over and insulated from the source region 16, and a select gate 20 disposed over and insulated from a second portion of the channel region 18. A conductive contact 10 can be formed to electrically connect to the drain region 14. U.S. Pat. No. 7,315,056 discloses another split gate non-volatile memory cell, which is similar to that of U.S. Pat. No. 7,927,994, but without a control gate. FIG. 2 illustrates the memory cells of the '056 patent (with similar elements indicated with the same element number).
The memory cells are arranged in an array to form a device, with columns of such memory cells separated by columns of isolation regions. Isolation regions are portions of the substrate in which insulation material is formed. Logic (core) devices and high voltage devices can be formed on the same chip as the memory array, often formed sharing some of the same processing steps. Those dedicated areas of the substrate in which logic device and high voltage devices are formed will be referred to herein as the logic and high voltage areas, respectively.
One issue with conventional split gate memory cells is the height of the memory cells on the substrate is greater than that of the devices in the logic and high voltage areas. Yet, it can be challenging to reduce the height of the memory cells while still preserving desired performance. The present invention is a novel technique for forming a split gate non-volatile memory device on the same chip as logic and high voltage devices, with the memory cells utilizing control gates having a metal material with conventional ONO (oxide/nitride/oxide) or OHKO (oxide/HK/oxide) under the control gate as the coupling dielectrics to the floating gate.
USPTO Backgrounds
USPTO Backgrounds