The present invention relates to a dynamic random access memory, and more particularly to the memory cell structure, arrangement, driving scheme and sensing scheme of a dynamic memory having high speed, high density, low power dissipation and high signal to noise ratio.
A conventional dynamic memory (hereinafter referred to as DRAM) has been mainly a so-called one transistor (hereinafter referred to as 1T) cell composed of one transistor and one capacitor. However, since 1T cell has no function of amplification within the cell, the capacitance of a capacitor within the cell must be made larger as the cell integration and size become large, thereby complicating the cell structure and making its manufacture more difficult. For this reason, it has become necessary for future high integration of DRAMs to reconsider a memory cell having amplification function, such as a 3-transistor (3T) cell. However, a conventional 3T cell has still many problems to be solved, for example, low speed operation, high power dissipation, high noise or low integration.
In order to explain these problems, an example of a 3T cell having a smallest cell size among known 3T cells is shown in FIG. 1A. The operation of this 3T cell is detailed in Digest of Technical Papers, p. 10, 1972 IEEE International Solid-State Circuits Conference, and in the paper of the Institute of Electronics and Communication Engineers of Japan, June 1975, Vol. 58-C, No. 6, P. 327. The operation will be briefly described with reference to FIGS. 1A and 1B.
Symbols used in FIG. 1A have the following meanings:
MC: memory cell, PA0 TW: write terminal of memory cell, PA0 TR: read terminal of memory cell, PA0 W.sub.o, W.sub.n : word line, PA0 D: data line, PA0 I/O: common data line, PA0 TY: Y select line, PA0 TV: power supply terminal for precharge PA0 TP: precharge terminal, PA0 Q.sub.W : write transistor, PA0 Q.sub.R : read transistor, PA0 Q.sub.S : store transistor, PA0 Q.sub.Y : Y select transistor.
Transistors are assumed hereinafter N-channel MOS transistors unless specifically indicated otherwise. A memory cell MC is composed of a write transistor Q.sub.W, a store transistor Q.sub.S, a read transistor Q.sub.R ; and other necessary circuitries. The operation of the memory cell is performed as in the following. First, a pulse of 5V is applied to the gate terminal TP of a precharge transistor to precharge the data line to 4V from the power supply terminal TV to which 5V is applied. The threshold voltage of transistor is here assumed 1V. After TP terminal becomes 0V and the data line becomes floating state, a pulse voltage of 1.5V is applied to a selected word line W.sub.o. If the gate voltage of Q.sub.S is 4V corresponding to stored information "1", Q.sub.S and Q.sub.R become turned on so that the data line voltage is discharged toward 0V. On the other hand, if the gate voltage is 0V corresponding to stored information "0", Q.sub.S is cut off so that the data line voltage remains 4V. These data voltages are outputted to an I/O line, when a select signal from Y decoder is applied to TY, and to the external of the chip as a data output. The write operation starts when the word voltage is made 5V after the above-described read operation has been suitably completed, e.g., at point a in FIG. 1B. Particularly, write information of 4V or 0V inputted to data line D from I/O line is written in as the gate voltage of Q.sub.S because the word voltage is 5V. In the other memory cells unnecessary for writing information on the selected word line W.sub.o, corresponding voltages on their data lines are rewritten as they are.
USPTO Backgrounds
USPTO Backgrounds