In the manufacturing of integrated circuits, patterning techniques such as photolithography and etching are used to form various features such as polysilicon lines, devices (e.g., transistors, diodes, and the like), interconnect structures, contact pads, and the like in device dies on a wafer. As design features in integrated circuits become increasingly complex (e.g., having smaller critical dimensions and/or more complex shapes), double patterning processes may be used to form a single feature. However, due to process limitations, critical dimensions of the various patterned features may not be uniform within a device die/wafer, which may degrade the performance of the device die/wafer.
In order to improve critical dimension uniformity (CDU) and within wafer (WiW) uniformity, dose mapper (DoMa) maps may be calculated for wafers to measure the actual critical dimensions of patterned features. These DoMa maps may then be used to adjust lithography conditions of the patterning process to improve CDU and WiW uniformity. However, conventional DoMa maps and applications thereof may suffer from various limitations.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
USPTO Backgrounds
USPTO Backgrounds