1. Field of the Invention
The present invention relates to a data processing device, more particularly, to a microprocessor including an internal cache memory for storing a part of the contents of a main memory. The microprocessor is applied to a computer system having a mass storage external cache memory and an external device such as a direct memory access controller, and is used to control the external cache memory.
2. Description of the Related Art
Recently, in a data processing system (computer system) having an internal cache memory (which may be simply called an internal cache) provided in a microprocessor (microprocessor unit: MPU), an external cache memory (which may be simply called an external cache), an external device such as a direct memory access controller, and a main memory, a block transfer process for transferring data is carried out. In this data processing system, when data for an operand access or an instruction fetch for executing an instruction is not stored in the internal cache, that is, when the data for the instruction fetch or the operand access do not exist (which may be called a "miss-hit"), the microprocessor fetches block unit data (block data) from an external main memory and inputs the block data into the internal cache (which may be called a block-in operation). Therefore, a part of the internal cache memory is changed, and a cache control for coinciding the contents of the external cache with the contents of the internal cache should be carried out.
In one aspect of a previously known cache control system, when a block transfer operation is carried out by a microprocessor through a system bus, block data transferred through the system bus is fetched by the external cache such that the external cache steals the block data on the system bus, so that the contents of the internal cache and the external cache coincide with each other. In another aspect of a previously known cache control system, when a block-in operation is carried out through a system bus and a part of a main memory is rewritten by an external device through the system bus, and also when data corresponding to the rewritten part of the main memory coincides with the block data of being fetched by the block-in operation, a microprocessor controls the cache control system to break the block-in operation thereof.
Nevertheless, when the external cache carries out a steal operation, the block-in operation is broken by the microprocessor and another block-in operation following the broken block-in operation is started, as a result of which the external cache cannot discriminate whether the block-in operation is a new block-in operation or not, and thus an error in operation may be caused in the external cache.
USPTO Backgrounds
USPTO Backgrounds