The present invention relates generally to the testability of digital logics circuitry and specifically to the scan-set testability of an embedded, edge-triggered flip-flop.
As digital logic circuits at all levels (chips, boards and subsystems), have become increasingly complex, the difficulty of thoroughly testing each level has markedly increased. As the gate-to-I/O pin ratio continues to increase with new technologies, the ability to control and observe internal modes of digital logic circuits continues to decrease. Where the ratio of logic gates to I/O pins is large, as in gate array technology, the utilization of the scan-test technique greatly increases the testability of a logic circuit, allowing nearly 100 percent coverage of the contained gates. The scan-set technique allows the internal registers of the circuit under test to be used as virtual I/O pins, thus reducing the logic gate-to-I/O pin ratio. This has the advantage of increasing the controllability of the digital logic circuit under test. The use of the scan-set technique eliminates the requirement for manual generation of test vectors for digital logic circuitry. Manual generation of test vectors is very undesirable because of the excessive amount of designer time required, and because of the potential inadequacy of test coverage.
Scan-set testability is implemented by utilization of flip-flops which have two inputs: a parallel data input for normal operation and a serial data input for scan-set test operation. The selection between the two data inputs, normal and scan-set data, is controlled by the distribution of functional clock and scan-set test enablement signals. The use of scan-set testable flip-flops provides two major advantages. The first advantage is to allow the utilization of such flip-flops during normal operation of the digital logics circuitry as latches or, combinatorially, as a functional register. The second advantage is to allow information to be shifted into the flip-flop (providing controllability) as well as allowing retrieval of information from the flip-flops (providing observability). The input function is termed "set" while the output shift is termed "scan". Both operations can be performed at once if the data to be input for the next test step may be anticipated while the output of the present step is being examined.
The flip-flops that have priorly been used in scan-set testable logic have previously been predominantly of the bistable type. The prior art bistable flip-flop exhibits the following characteristic: regardless of the time sequence between the clock signal and the data signal the output of such flip-flop is stable (which is not to say invariant, but only that no critical time relationship exists between the clock and data signals). Existing edge-triggered flip-flop, for example dual D-type positive-edge-triggered flip-flop with preset and clear industry standard part number 74, or additionally for example edge-triggered J-K flip-flop industry standard part number 109, do not exhibit this property. Therefore the use of such edge-triggered flip-flop in embedded logic subject to scan-set test techniques has priorly been generally proscribed.
A prior art circuit for a scan-set testable (embedded) edge-triggered flip-flop is shown and described as "LATCH CIRCUIT OPERATIONAL AS A D-TYPE EDGE-TRIGGER" in the IBM Technical Disclosure Bulletin Volume 22, number 12 for May, 1980 at pages 5261 and 5262. This "latch circuit operational as a D-type edge-trigger" shows, when compared with a nonscan-set-testable edge-triggered D-type flip-flop industry standard part number 74, that the incorporation of scan-set test capability required the addition of several NAND gates to the basic circuit. Despite the added NAND gates, a limitation to the scan-set testability of the prior art "latch circuit operational as a D-type edge-trigger" exists because of the inability to observe the correct function of some of the gates within the circuit being scan-set tested. Furthermore, a second limitation is that system data can only be observed after the "latch circuit operational is a D-type edge-trigger" has been reset by the scan-in operation. Thusly, this prior art edge-triggered flip-flop structure is not fully and completely scan-set testable, but merely shows a partial accommodation to the incorporation of scan-set test techniques into edge-triggered flip-flop digital logic structure.
USPTO Backgrounds
USPTO Backgrounds