1. Field of the Invention
The present invention relates generally to the semiconductor processing. More particularly, the present invention relates to a method of forming gate conductor structures with improved line edge roughness (LER) and reduced resist budget.
2. Description of the Prior Art
As known in the art, one limitation to achieving smaller sizes of IC device features is the capability of conventional lithography. Lithography is the process by which a pattern or image is transferred from one medium to another. Conventional IC lithography uses ultra-violet (UV) sensitive photoresist. UV light is projected to the photoresist through a reticle or mask to create device patterns on an IC. Conventional IC lithographic processes are limited in their ability to print small features, such as contacts, trenches, polysilicon lines or gate conductor structures.
Generally, conventional lithographic processes (e.g., projection lithography and EUV lithography) do not have sufficient resolution and accuracy to consistently fabricate small features of minimum size. Resolution can be adversely impacted by a number of phenomena including: wavelength of light, diffraction of light, lens aberrations, mechanical stability of the resist, contamination, optical properties of resist, resist contrast, resist swelling, thermal flow of resist, etc. As such, the critical dimensions of contacts, trenches, gates, and, thus, IC devices, are limited in how small they can be.
Another difficulty arising from the continuing small dimensions involved in the creation of gate conductor structures is the tendency in the lithography process to experience resist erosion, pattern collapse, uncontrolled line edge roughness (LER). Typically, to etch fine gate conductor lines or structures on a substrate, a thick photoresist (high resist budget) and a single hard mask are used. However, severe corner rounding defects are found at the upper portion of the hard mask, which adversely affects the integrity of the gate conductor and results in worsened LER.
USPTO Backgrounds
USPTO Backgrounds