It is critical in semiconductor manufacturing and packaging to control wafer level core array threshold voltage (Vt) variation. This is especially true as electronic designs become smaller and more densely packed. In addition, charge can accumulate on a semiconductor surface if the surface is resistive to the point where a catastrophic breakdown or an Electrostatic discharge (ESD) event occurs. ESD events can damage, for example, semiconductors, the photoresist-masks or hard-masks, and the like. Electrostatic discharge can also produce electrical signals or electromagnetic interference (EMI) that interferes with the operation of equipment, such as, the production equipment. These ESD problems can occur, for example, throughout the semiconductor manufacturing and packaging process, including silicon wafer creation, photoresist-mask layering and etching, device manufacturing, and back-end processing, packaging and test. Many of these ESD problems persist through the entire “life” cycle of the semiconductor device. In addition, damage may be more subtle, for example, permanent alteration of the dielectric breakdown properties.
Implanted dopant ions, well known in the art, are electrically charged, a consequence of the ion implantation process. Charge imbalance related with ion implantation is attributed to a number of occurrences, for example, ejection of secondary electrons, discharge of other charged species from the wafer, absorption of ions from surrounding area, and the like. The charging properties or effects associated with ion implantation are difficult to model. Furthermore, the charge distribution will fluctuate over the surface of the wafer because of variations in the ion beam, the variable characteristics of the wafer surface, surface areas with different conductivities, excess charge already present on the wafer, and the like. Charge distributions vary over the surface of a wafer, from wafer to wafer, etc. All of these factors contribute to non-uniform charge distributions on the wafer surface which can have serious consequences on semiconductors devices that are continuously being reduced in size.
Semiconductor manufacturing technologies will continue to move toward smaller device geometries in the foreseeable future and acceptable ESD levels will continue to decrease with decreasing device dimensions, as well as the need for uniform charge distributions. The use of integrated passive substrate components (e.g., resistors, inductors, capacitors, etc.) offers ESD discharge and charge distribution advantages in semiconductor packaging efficiency, miniaturization, performance, manufacturing, and processing. Decoupling capacitors, for example, act as charge reservoirs and suppress charge buildup and ESD events, promote uniform charge distributions, and the like, by directing charge away from the core array of a flash memory, for example, yet these devices can be expensive to implement in the fabrication process.
Thus, there is a need to provide a method which improves the conductivity associated with the poly-1 deposition but which does not suffer from the problems that are currently present with processes employing integrated passive components.
USPTO Backgrounds
USPTO Backgrounds