In recent years, there has been proposed a ReRAM (Resistive RAM) that utilizes as a memory a variable resistance element whose resistance value is reversibly changed. Moreover, in this ReRAM, an even higher degree of integration of a memory cell array has been made possible by a structure in which the variable resistance element is provided between a sidewall of a word line extending parallel to a substrate and a sidewall of a bit line extending perpendicularly to the substrate. In the memory cell array of such a structure, a select gate transistor is connected to a lower end of the bit line, and each of the bit lines is selectively connected to a global bit line by this select gate transistor.
The semiconductor memory device according to the embodiments lowers power consumption.
USPTO Backgrounds
USPTO Backgrounds