1. Field of the Invention
The present invention relates to the field of electronic design. More specifically, the present invention relates to design creation tools for use by electronic designers to create designs for electronic components, including in particular, integrated electronic components.
2. Background Information
Assisting electronic designers in dealing with the ever increasing complexity of electronic designs (hereinafter, most of the time, simply designs) has long been a recognized need. In the last two decades, the electronic design automation (EDA) tool industry has grown into a multi-billion dollar industry, with a wide range of tools available from an array of manufacturers covering design activities from the beginning to the end of the design cycle.
In the area of design creation, various synthesis tools were introduced in the mid-'80s to assist the designers. These early synthesis tools (which are still in use today) operate at a relatively low level, allowing the designers to specify and optimize the designs at the logic level, also referred to as the gate level. As the complexity of integrated electronic components continued to increase, merely being able to optimize designs at the logic or gate level was no longer sufficient for the designers. A more productive approach was desired. In the late '80s, a new generation of improved synthesis tools became available. These new improved synthesis tools (which have now become the primary design creation tools) are capable of operating at a higher level, allowing the designers to specify and optimize designs at the register transfer level (RTL) as well as at the logic or gate level.
Since then, the complexity of integrated electronic components has continued to increase unabated. Merely being able to optimize designs at the RTL has also become insufficient for the designers for many large designs. Once again, another more productive approach was desired. In recent years, a new type of synthesis tool that complements the earlier RTL and logic level synthesis tools has become available. Together, these synthesis tools enable a designer to operate at an even higher level, specifying and optimizing designs at the behavioral level. However, the current generation of complementary behavioral synthesis tools suffer from a number of drawbacks. First of all, they continue to operate with the RTL and/or logic level synthesis tools' "black box" or batch approach. That is, an "optimized" RTL specification (optimized in the judgment of the synthesis tools) is generated for a designer in response to each set of behavioral specification and constraints provided. (The behavioral specification and constraints are jointly specified.) The designer is unable to interact with the intermediate stages of the generation process to inject or apply his/her knowledge in guiding the generation of the "optimal" design. Once generated, if the designer wants to consider different alternatives, the designer must alter the constraints, which are jointly specified with the behavioral specification, and start the whole synthesis process again. For large designs, it is not uncommon to take hours to re-synthesize, even if the re-synthesis is performed on the more powerful high end workstations. Secondly, the current generation of behavioral synthesis tools have relatively limited capacity. Some of these behavioral synthesis tools recommend having designs partitioned into smaller designs that have less than 150 operations and a speed limit of not more 30 clock cycles (also referred to as c-steps). The smaller designs are behaviorally synthesized individually, and then "merged back" together into the "larger" design.
The increase of complexity of integrated electronic components is not expected to plateau any time in the near future. In fact, the very contrary of an even faster rate of increase is expected. Notwithstanding the relatively recent introduction of the behavioral synthesis tools, it is expected that the prior art approaches to creating electronic designs will be unsatisfactory for handling the larger designs in the near future, which will become the "average" designs in the not too distant future. Thus, an even more productive approach to electronic design creation is desired.
USPTO Backgrounds
USPTO Backgrounds