The present invention relates to edge stress reduction in integrated circuit structures and fabrication methods.
Background: Stress-Induced Defects
Nearly all films are found to be in a state of internal stress, regardless of the means by which they have been produced. The stress may be compressive or tensile. Compressively stressed films are characterized by the fact that they would like to expand parallel to the substrate surface, and in the extreme, a compressively stressed film will buckle up on the substrate (the stress in the substrate is opposite in sign). Films in tensile stress, on the other hand, would like to contract parallel to the substrate, and may crack if their elastic limits are exceeded. Films in tensile stress tend to cause concave bending of the substrate (bending toward the film), while films in compressive stress tend to cause convex bending (bending away from the film).
For example, during the formation of silicides, there is a net volume shrinkage which could possibly result in a large tensile stress in the film. This stress can result in delamination and other problems during subsequent processing.
Highly stressed films are undesirable as they are more likely to exhibit poor adhesion, they are more susceptible to corrosion, they may undergo cracking in tensile stress (especially for brittle films, such as inorganic dielectrics), and they tend to exhibit higher resistivities. In addition, the stress increases with increasing thickness.
One conventional approach of reducing the stress in metal films (e.g. tungsten), which is discussed in U.S. Pat. No. 5,480,529 to Kola et al., includes employing a continuously operating capacitance-based measurement technique to allow adjustment of the deposition conditions in rapid response to changes in the stress of the film being deposited. However, this approach requires frequent and rapid measurements and constant adjustment of process parameters, both of which are cumbersome and increase the cost of the devices. Not all processes can be optimized in this way and not all films can be made stress-free (especially refractory metals and silicides).
A stressed film will tend to cause a corresponding stress in the layer(s) to which it is bonded. For example, a transistor gate layer which is in strong compressive stress will tend to induce a tensile stress in a substrate to which it is bonded.
Particularly large stresses and gradients occur at the edges of layered device structures such as gate edges, nitride moat (e.g. active device area) mask edges, and LOCOS edges. The stress level often reaches hundreds of Mega-Pascals at tens of nanometers within the vicinity of the edge. This stress level can cause structural reliability problems, such as peeling, or induce crystal defects in silicon during device processing. Furthermore, stress-induced defects can undesirably increase the leakage current in transistors.
Background: DRAM Gate Structures
One of the driving forces in shrinking integrated circuit geometries is the distributed resistance and parasitic capacitance of the signal lines, which reduce the propagation speed of signals. The additional delays thus introduced reduce the potential speed of the chip.
This is a particular problem for DRAMs, since the wordlines are densely packed together, and the capacitive coupling between adjacent lines becomes very significant. Moreover, the sheet resistance of the lines cannot usefully be improved by increasing the height of the lines, since this also increases the capacitive coupling between adjacent lines. There has therefore been great pressure to find materials with a lower resistivity to replace the traditional polysilicon/silicide lines. This has impelled efforts to design metal into the gate line structure. One example of this is a gate stack structure which includes tungsten (or other refractory metal) over polysilicon with a diffusion barrier layer therebetween (e.g. 5 nm of TiN), but many other gate stack structures have been proposed.
Stress in the refractory metal and barrier layers is typically tensile and very high (e.g. between 1000 and 3000 MPa), while the stress in the polysilicon and gate oxide is compressive and much lower (e.g. 100 to 300 MPa). (Thus, the tensile stress of the metal layer dominates over the compressive stress of the polysilicon layer.) The stress distribution in the silicon substrate near the gate structure is tensile at external edges, and rapidly changes to compressive toward the center of the gate. This polar reversal of layer stresses occurs within tens of nanometers. The interaction of stress and point defects in the silicon substrate (due to ion implantation or grown in micro-defects) during annealing can undesirably cause crystal dislocations.
Background: Inverse-T-Gates
Inverse-T-gate structures are usually formed by forming sidewall spacers on an upper polysilicon layer portion prior to etching the lower polysilicon layer portion (and possibly an intervening barrier layer). Thus in a single patterning step this produces a conductor line in which the upper portion is narrower than the lower portion. (However, inverse-T-gate structures do not normally contain a thick, highly-stressed metal layer, and are usually designed to control profiling of the implanted diffusions.) Inverse-T-gate structures are discussed in, for example, the following articles: Wen et al., xe2x80x9cA Self-Aligned Inverse-T Gate Fully Overlapped LDD Device for Sub-Half Micron CMOS,xe2x80x9d 1989 IEDM paper 32.1; Goranova et al., xe2x80x9cA Pragmatic View of Inverse-T-Gate Lightly-Doped-Drain Transistors,xe2x80x9d 34 SOLID-STATE ELECTRONICS 1169 (1991); and Chen et al., xe2x80x9cSelf-Aligned Silicided Inverse-T Gate LDD Devices for Sub-Half Micron CMOS Technology,xe2x80x9d 1990 IEDM, 829; all of which are hereby incorporated by reference.
Edge Stress Reduction Structures and Methods
The present application discloses structures and methods which enable the reduction of the edge stress to avoid device reliability and performance problems. In cases where the choice of materials is limited, reduction of edge stress can be achieved by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).
Advantages of the disclosed methods and structures include:
optimization of the stress at the edge to reduce or eliminate device reliability and/or performance problems; and
can be implemented in any integrated circuit device to reduce stress at the edges.
USPTO Backgrounds
USPTO Backgrounds