There are already a series of methods for embedding semiconductor structural parts into flexible substrates or foil arrangements which in part are already used in manufacturing.
US 2007/0227761 A1 describes, for example, a method for embedding electronic components, in which the electronic component is placed onto a foil arrangement composed of a conductive layer and carrier foil by means of an adhesive layer and is surrounded by an insulating compound.
In the method described in said document, the carrier layer is removed, and holes are drilled from the side of the conductive layer in order to produce a connection with the bumps or the contact areas of the at least one electronic structural part.
In the method described in said document, the conductive layer is then provided with a metalization, and both are structured according to the specifications.
DE 102009058764 A1 relates to a method for producing an electronic subassembly, in which at least one electronic structural part is at least partially embedded in an insulating material.
The method described in said document comprises the following steps:
providing a foil arrangement comprising at least one conductive layer and a carrier layer, structuring the conductive layer of the foil arrangement in such a manner as to produce openings for receiving bumps which are connected to the contact areas of the at least one tip electronic structural part.
The method described in said document furthermore comprises applying an adhesive layer to the conductive layer provided with openings, placing the at least one structural part onto the foil arrangement, depositing a metalization layer on the side of the conductive layer with the exposed bumps.
USPTO Backgrounds
USPTO Backgrounds