This invention relates to dielectric isolation for integrated semiconductor devices, and more particularly to a method of manufacturing semiconductor integrated circuit devices, which is adapted to simultaneously form a narrow and deep isolation region and a wide and thick field region.
In bipolar type integrated semiconductor circuit devices, the active regions or elements are electrically isolated by the PN junctions. However, with increasing demand for smaller device sizes and higher element densities, it has become necessary to reduce the isolation areas. The PN junction isolation has been gradually superseded by the oxide isolation (the so-called Isoplanar) using a thick oxide formed in the silicon substrate through selective oxidation.
The oxide isolation method typically comprises the steps of; placing on a silicon substrate an oxidation-resistant masking layer formed of a composite layer of a thin silicon oxide film and a silicon nitride film, etching the surface of the silicon substrate to form mesa regions for active elements under the masking layers, and thermally oxidizing the silicon substrate to form thick silicon oxide as field isolation regions surrounding the mesa regions.
As compared with the PN junction isolation, the oxide isolation can reduce the areas of the isolation regions, and can also reduce stray capacitances between the surface conductors and the substrate due to the thick silicon oxide (hereinafter called "the field region(s)") forming all regions other than the active regions, thereby contributing to an increase of the switching speed of the resulting transistors.
However, during the above thermal oxidation step, since lateral oxidation causes formation of the "bird's beak" or "bird's head" in the silicon substrate under the oxidation-resistant masking layer, the widths of the isolation regions become greater than an allowable minimum dimension obtained by the conventional photolithography.
Therefore, the bird's beak and bird's head make difficult to obtain finer isolation regions less than 10 .mu.m, and also spoil the formation of a planar surface over the substrate.
To overcome such disadvantages, an improved isolation technique is represented, e.g. by a process described in a paper entitled "A Method for Area Saving Planar Isolation Oxidation Protected Sidewalls" by D. Kahng et al, published in Solid-State Science And Technology issued by J. Electro-Chemistry Society, Vol. 127, No. 11, November, 1980, pp. 2468-2470. According to this process, in addition to a first oxidation-resistant layer of silicon nitride deposited over the top surfaces of mesa regions, a second oxidation-resistant layer of silicon nitride is deposited by chemical vapor diposition on the sidewalls of the mesa regions. The Improved Selective Oxidation Process can thus prevent widening of the isolation regions caused by the lateral oxidation, and also can prevent the formation of bird's beak and bird's head so as to achieve the flattened silicon substrate surface irrespective of the width of the isolation regions to be formed.
However, according to this process, it takes an impracticably very long time to form deep and narrow isolation regions extending through an epitaxial layer on the entire surface of the silicon substrate by oxidation process. To shorten the oxidation time, buried regions have to be formed in the surface of a silicon substrate by using another photomask before the formation of an epitaxial layer on the entire surface of the silicon substrate. This requires more critical mask aligning tolerances in aligning a second mask with the formerly formed buried region. Furthermore, since a P.sup.+ channel stop layer formed under the bottom of the isolation region is placed so as to contact with N.sup.+ buried regions, the junction capacitance between the P.sup.+ channel stop region and the N.sup.+ buried region tends to increase. Also, this process tends to increase leak current between the base region and the P.sup.+ channel stop layer, resulting in reduced breakdown voltage.
Recently, a U-groove isolation technique has been developed, which utilizes a reactive ion-etching (RIE) process capable of etching a silicon substrate vertically to the substrate to form deep grooves of a given width having vertical sidewalls. The U-groove isolation technique is described in a paper entitled "U-Groove Isolation Technique For High Speed Bipolar VLSIC's" by Akio Hayasaka et al, published in IEDM 82, 1982, pp. 62-65. According to this process, a silicon substrate is etched by using RIE to form deep, sheer U-grooves or -trenches. The grooves are oxidized to form a silicon dioxide layer along their walls, and covered with a silicon nitride layer. A polycrystalline silicon material is then deposited over the silicon substrate so as to bury the grooves, and then etched back to form a flat surface on the silicon substrate.
In fabricating bipolar integrated circuit devices by means of the U-groove isolation process, deep isolation grooves can be formed in the silicon substrate so as to penetrate a buried layer formed by diffusion throughout the whole area of the silicon substrate, thereby dispensing with the use of a mask for formation of such buried layer, which has conventionally been employed.
However, according to the U-groove isolation process, it is difficult to obtain a flat surface over larger width field regions formed by filling with dielectric material in a wide groove. That is, an additional mask is required to obtain flattened surfaces, which leads to an increased number of fabricating steps, and also requires critical aligning tolerances.
USPTO Backgrounds
USPTO Backgrounds