1. Field of the Invention
The invention relates to the field of electronics. More particularly, the invention relates a logically determined system that does not rely on a clock for timing and control of data processing behavior.
2. Related Art
The field of logically determined design as described in:
Karl Fant. Logically Determined Design: Clockless System Design with NULL Convention Logic. New York: Wiley, 2005 (“Fant 2005”)
Proposals are known for making asynchronous systems as reflected in the documents listed below.                Traver, C., Reese, R. B., Thornton, M. A.: Cell Designs for Self-timed FPGAs. Proc. of the 2001 ASIC/SOC Conf. (2001).        How, D. L.: A Self Clocked FPGA for General Purpose Logic Emulation. Proc. Of the IEEE 1996 Custom Integrated Circuits Conf. (1996).        Ho, Q. T., et al.: Implementing asynchronous circuits on LUT based FPGAs. Proc. 12th Int'l Conf. on Field Programmable Logic and Applications (2002).        Song Peng, David Fang, John Teifel, and Rajit Manohar. Automated Synthesis for Asynchronous FPGAs. 13th ACM International Symposium on Field Programmable Gate Arrays, February 2005.        John Teifel and Rajit Manohar. An Asynchronous Dataflow FPGA Architecture. IEEE Transactions on Computers (special issue), November 2004.        John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, April 2004.        John Teifel and Rajit Manohar. Highly Pipelined Asynchronous FPGAs. 12th ACM International Symposium on Field-Programmable Gate Arrays, Monterey, Calif., February 2004.        John Teifel and Rajit Manohar. Programmable Asynchronous Pipeline Arrays. Proceedings of the 13th International Conference on Field Programmable Logic and Applications, pp. 345-354, Lisbon, Portugal, September 2003.        S. Hauck, S. Burns, G. Borriello, C. Ebeling, “An FPGA For Implementing Asynchronous Circuits”, IEEE Design & Test of Computers, Vol. 11, No. 3, pp. 60-69, Fall, 1994.        G. Borriello, C. Ebeling, S. Hauck, S. Burns, “The Triptych FPGA Architecture” (PDF), IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 491-501, December, 1995.        Janusz A. Brzozowski, Carl-Johan H. Seger, Asynchronous Circuits. New York: Springer-Verlag, 1995.        David L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits, Cambridge: MIT Press, 1989.        Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky, Concurrent Hardware, The Theory and Practice of Self-timed Design. New York, Wiley, 1994.        Alain J. Martin, “Programming in VLSI: From communicating processes to delay-insensitive circuits”, In C. A. R. Hoare, editor, Developments in Concurrency and Communication, Addison-Wesley, 1990, pp. 1-64.        Chris J. Meyers, Asynchronous Circuit Design. New York, Wiley, 2001.        Jens Sparse, Steve Furber, eds, Principles of a synchronous Circuit Design. Boston, Kluwer, 2001.        Ivan E. Sutherland, “Micropipelines”, Communications of the ACM, Vol. 32, No. 6, June 1989, pp. 720-738.        Steve H. Unger, Asynchronous Sequential Switching Circuits. New York, Wiley-Interscience, 1969.        Victor I. Varshavsky, Self-Timed Control of Concurrent Processes. Dordrecht, The Netherlands., Kluwer Academic, 1990.        
Patents                U.S. Pat. No. 5,367,209, issued Nov. 22, 1994, S. Hauck, G. Borriello, S. Burns, C. Ebeling, “Field Programmable Gate Array for Synchronous and Asynchronous Operation.”        
U.S. PATENT DOCUMENTS referenced by above4,293,783October 1981Patil307/4654,918,440April 1990Furtek340/825.834,969,121November 1990Chan307/4655,089,973February 1992Furtek364/4895,208,491May 1993Ebeling307/465.1
USPTO Backgrounds
USPTO Backgrounds