The mobilities of charge carriers (especially electrons) for group III-V semiconductors, particularly binary, ternary, and quaternary alloys of group III elements such as gallium, aluminum, and indium, and group V elements such as nitrogen, phosphorus, arsenic, and antimony, are generally higher than those of the group IV semiconductors such as silicon and germanium. It has also been shown that the III-V group metal-oxide-semiconductor field-effect transistor (MOSFET) has low gate leakage current, high channel mobility and high drive current. However, since silicon is the most used semiconductor for discrete devices and integrated circuits, the integration of III-V semiconductors on silicon substrate provides a unique opportunity to combine the superior characteristics of the advanced III-V semiconductor materials with the capabilities of the established silicon technologies.
For the integration of III-V semiconductors on silicon substrate, various approaches have been investigated, including: growth of buffer layers to alleviate the lattice mismatch between the III-V semiconductor structure and the Si substrate, wafer bonding, epitaxial layer transfer process, epitaxial lateral overgrowth, interfacial misfit array formation, and aspect ratio trapping (ART) techniques. ART is a promising method for forming high crystal-quality semiconductor materials on a highly lattice-mismatched substrate. ART uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon, and is shown to be very effective for a wide variety of materials including III-V semiconductors.
In view of utilizing III-V semiconductors on Si platform, III-V-on-insulator (III-V-O-I) structures are favorable because of the capability of alleviating the short-channel effects in metal-insulator-semiconductor field-effect transistor (MISFET) and the applicability to multi-gate structures. Thus, it is necessary to fabricate high quality III-V-O-I structures having high electron mobility. Since ART is capable of growing high crystal-quality III-V semiconductor materials on a highly lattice-mismatched substrate, it may be used in a method of forming the III-V-O-I structures on Si substrate with low sub-channel leakage current. However, such a method for forming a satisfactory III-V-O-I structures on Si substrate still needs to be established.
USPTO Backgrounds
USPTO Backgrounds