Semiconductor devices, typified by DRAMs (Dynamic Random Access Memory), include those in which the bit lines are separated hierarchically into local bit lines and global bit lines (see patent literature article 1). The local bit lines are lower-order bit lines which are connected to memory cells. Meanwhile, the global bit lines are higher-order bit lines which are connected to global sense amplifiers. Separating the bit lines hierarchically makes it possible to increase the number of memory cells allocated to one global sense amplifier, while reducing the wiring line length of the local bit lines, which have a relatively high electrical resistance.
The semiconductor device described in patent literature article 1 is provided with local sense amplifiers (LSA) connected to local bit lines.
USPTO Backgrounds
USPTO Backgrounds