The invention relates to the processing of wafer devices to form multi-level interconnects for micro-electronic circuits. Typically, the processing of a monolithic integrated circuit includes the step of etching the wafer, removing the photo resist, back sputtering the entire wafer, and then depositing the next layer of interconnect material. Heretofore, the surface cleaning and deposition of the next level of interconnect material have been done in a vacuum chamber while the initial etching step and the photo resist removal steps are done in separate processes and separate vacuum chambers. However, the problem exists that when the wafer is removed from the separate vacuum chambers for the next step in the process, the wafer comes in contact with the atmosphere, which causes problems in oxidation in the first level of interconnect. Furthermore, contamination problems occur when the wafer is exposed to the atmosphere. Particulate matter from the atmosphere will deposit on the surface of the wafer. This particulate matter that has deposited on the surface of the wafer may lead to discontinuities and/or shorts in the next level of interconnect after it has been deposited and defined.
In addition, the processing of integrated circuits in separate steps in separate apparatus requires additional pieces of equipment. It is a longer process because now each process must go through an individual vacuum pump down sequence and bringing back to the normal pressure and then a transfer of the wafers from one piece of equipment to the next and then sequencing through the vacuum system again. Additional time is involved and additional equipment is necessary since each one of these steps must have its own distinct piece of equipment and distinct vacuum chamber associated with it.
Accordingly, an important object of the present invention is to provide a method and system wherein sequential processing of multi-level interconnects in microelectronic circuits may be had without escaping the wafer to the atmosphere during the process.
Still another important object of the present invention is to provide a method and system for processing multi-level interconnects for microelectronic circuits in which the density of the circuit is improved.
Still another important object of the present invention is to provide a method and system for the processing of multi-level interconnects for microelectronic circuits which increases the cleanliness of the wafer and the circuitry being formed thereon in the process to increase the reliability thereof.
USPTO Backgrounds
USPTO Backgrounds