MOSFETs and various methods of their manufacture are well known. Typically, a MOSFET includes source and drain regions at a surface formed in or on a suitable substrate, and a gate disposed therebetween. Silicide electrical layers or contacts are formed on the gate, and on the source and drain regions. Substrates include, for example, bulk semiconductor (e.g. silicon), silicon-on-insulator substrates (SOI), among other substrates. See, for example, U.S. Pat. No. 6,930,030 B2, METHOD OF FORMING AN ELECTRONIC DEVICE ON A RECESS IN THE SURFACE OF THIN FILM OF SILICON ETCHED TO A PRECISE THICKNESS, issued Aug. 16, 2005, Rausch et al. which is hereby incorporated in its entirety by reference. FIG. 2M of the '030 patent, partially reproduced as FIG. 9 herein, shows the silicide layer/contact 54 disposed on a top surface of a polysilicon gate 4 of an nFET 20 formed in an SOI substrate. Also shown are an oxide layer 42 disposed below the gate and spacers 48 disposed at sidewalls of the gate.
It is also known to reduce electrical resistance of certain materials by means of using conductive type implants/dopants. See, for example, the following United States Patents: amorphization implants (U.S. Pat. No. 5,593,923), laser annealing to form silicide in combination with amorphizing implants (U.S. Pat. Nos. 6,387,803, 6,746,944B1), Ge implants (U.S. Pat. No. 5,258,637), implanting Flouride (U.S. Pat. No. 6,232,220B1), retrograde implants (U.S. Pat. No. 6,156,615), implanting metal into silicon (U.S. Pat. No. 5,654,241), amorphous silicon deposition (U.S. Pat. No. 5,899,741) and then metal/silicide formation, or implanting through silicide (U.S. Pat. No. 6,319,785) formed inside a contact hole which adds a mask, and silicon rich metal deposition (U.S. Pat. No. 6,492,264B1).
However, the present inventors believe that the methods and resulting structures according to the prior art have not proven to be entirely satisfactory. Silicide contact resistance is sensitive to the dopant concentration at the silicide/silicon (in both the, lateral extension and vertical source/drain) boundary. In general, the typical known silicidation process is as follows: source/drain implants are done followed by metal deposition and then an anneal to react the metal and doped silicon to form the silicide; as the reaction progresses, the dopant in the silicon is incorporated with large segregation into the silicide and causes the dopant concentration at the silicide/silicon interface to be low. This results in a relatively large contact resistance such as 100-200Ω-μm. A large contact resistance is typically undesirable.
The present inventors believe improvements are achievable in making low resistance silicide contacts for semiconductor device structures such as FETs.
USPTO Backgrounds
USPTO Backgrounds