Conventional flash analog to digital converters receive an analog input signal through a conventional input buffer amplifier designed to drive the diode bridge of a sample and hold circuit. The sample and hold circuit includes a sampling gate and a hold amplifier that must have sufficient output source and sink currents to slew the input capacitance of a flash quantizer at the operating frequency. The quantizer contains comparators for use in decoding the analog input signal into a digital output. The number of comparators within the quantizer is approximately 2.sup.n, where n is the number of bits of resolution for the digital output. The hold amplifier current must slew the input capacitance of the quantizer through the full scale voltage in about one-fourth of the sampling period to allow sufficient time for comparator acquisition and decode settling. The required current from the hold amplifier scales exponentially with increasing bit resolution. The comparators are strobed with a clock line in order to produce the thermometer code that is then decoded into the digital output.
Future advanced digital phased-array radar and electronic countermeasures systems will require high frequency, high resolution analog to digital converters to capture the analog information as near to the front-end RF electronics as possible. Conventional analog to digital circuit topologies will have great difficulty in achieving 20 GHz Nyquist sampling with dynamic linearity better than about three bits for all current and projected IC technologies. The exponential increase of hold amplifier current with quantizer resolution severely limits the scalability of conventional quantizer designs. Further, transmission characteristics of the long clock lines needed to strobe the quantizer's comparator banks require that the lines be kept shorter than about one-sixteenth of a wavelength or reflections and other undesirable transmission line phenomena will make accurate phase matching of the input signal to the clock extremely difficult.
From the foregoing, it may be appreciated that a need has arisen for a quantizer that can operate under higher bandwidths and bit resolutions than prior art quantizers. A need has also arisen for a flash quantizer that does not require an exponential increase in hold amplifier current in order to increase the bit resolution of the device. Further a need has arisen for a flash quantizer which does not require long clock lines for higher bit resolutions.
USPTO Backgrounds
USPTO Backgrounds