1. Field of the Invention
The present invention relates generally to the planarization of substrates, and more specifically to methods and apparatus for low stress metallization removal and substrate planarization.
2. Description of the Related Art
In the fabrication of semiconductor devices, integrated circuits are defined on semiconductor wafers by forming a plurality of layers over one another resulting in multilevel structures. Features such as trenches, vias, interconnect lines, and the like are defined within and through one or more layers, typically followed by the deposition of metallization or other conductive material fill, hereinafter referred to as conductive fill, over the defined pattern features. Chemical Mechanical Planarization (CMP) is one fabrication process used to remove overburden resulting from conductive fill deposition, and to planarize the surface of a semiconductor wafer in which a surface topography develops as a result of the various layers disposed over one another. Additional applications of CMP include cleaning, buffing, polishing, planarizing, and otherwise processing substrates used in such applications as flat panel displays, hard disks, and the like.
In general, CMP processes involve a chemically-assisted mechanical removal of material from the surface of a substrate. Usually, CMP is accomplished by the holding and rotating of a substrate which is applied against a preparation surface under a controlled pressure. FIG. 1A shows a typical linear CMP apparatus 10 having a substrate 12 attached to a carrier 14, and applied against a preparation surface 16. The preparation surface 16 is a surface of a continuous loop belt supported between two or more drums or rollers 18 which move the belt through a rotary path, as indicated by arrow 26, presenting a flat preparation surface 16 against which the substrate 12 is applied. Typically, the substrate 12, supported by the carrier 14, is rotated as shown by arrow 24, and applied against the preparation surface 16 with a downward pressure or force as indicated by arrow 22. A platen 20 may be configured on the underside of the belt traveling in its circular path. The platen 20 provides a stable surface over which the belt travels, and the wafer 12 is applied to the preparation surface 16 of the belt against the stable surface provided by the platen 20.
CMP apparatus further include rotary CMP processing tools having a circular pad configuration for the preparation surface. FIG. 1B shows one example of a rotary CMP processing tool 30. In the configuration illustrated in FIG. 1B, a substrate 32 is attached to a carrier 34 and applied against a preparation surface 36 of a rotary table 38. The substrate 32 on carrier 34 is typically rotated as indicated by arrow 42 and applied against the preparation surface 46 with a downward force 44. The preparation surface 36 is also rotated with the rotation of the rotary table 38 as indicated by arrow 46.
FIG. 1C illustrates yet another configuration of CMP processing apparatus. FIG. 1C shows a subaperture CMP tool 50. In a subaperture CMP tool 50, a substrate 52 is attached to a carrier 54, and applied against a preparation surface 56 attached to a polishing head 58. Carrier 54 is typically configured to rotate as indicated by arrow 60, and to apply the substrate 52 against the preparation surface 56 with a downward force as indicated by arrow 62. Further, lateral movement of the substrate 52 across the preparation surface 56 is shown by arrows 64. The preparation surface 56 is rotated with polishing head 58 as shown by arrow 66.
As illustrated in FIGS. 1A, 1B, and 1C, typical CMP processing results in a plurality of forces acting upon the surface of a substrate. Such forces include the downward force of the application of the substrate against the processing surface, and the rotational and lateral forces of the rotating substrate, the rotating preparation surface, and the lateral positioning of the substrate on the preparation surface. The processing forces result in significant shear stress on the surface of the substrate being planarized or otherwise processed. As described above in reference to semiconductor manufacturing, the surface of the substrate may include overburden of conductive fill, and as the overburden is removed, the substrate surface may include a barrier layer and the dielectric layer in which patterns and other features have been formed, with the conductive fill filling the patterns and other features.
In the continuous process of improving integrated circuit performance, semiconductor manufacturing is migrating more and more to copper as the metal of choice for interconnects, and low-k dielectric layers that are increasingly porous in order to achieve a low dielectric constant. The porous, low-k dielectric material which serves as an insulating material for the copper or other metal wiring is fragile, and particularly susceptible to fracture and tearing under applied shear stress.
In addition to the fragile, porous low-k dielectric material, fabrication challenges also include progressively smaller feature sizes. In order to effectively define and fill features of some current and next generation fabrication processes, at least molecular manipulation of copper or other metal selected is rapidly becoming desired or necessary. In response, the industry has begun to further develop electroplating deposition of conductive fill and to expand and implement electropolish processes to remove overburden and planarize the surface of the substrate.
Electropolish processes for the removal of copper or other metal overburden, and for planarization of a substrate, are generally deficient with respect to stringent overburden removal and planarization requirements. Electropolish material removal is intrinsically isotropic, and is unable to be implemented for selective removal of hundreds or a few thousands of angstroms (Å) of topography. Further, the material removal process for copper (Cu) is governed by grain boundary activation for initiating material removal. A polycrystalline material, Cu exhibits wide variation in grain boundary density as a function of in-laid pattern feature geometry and density. As a result, electropolish and other removal rates can vary widely between feature sizes of, for example, 1.0μ in width down to 0.25μ in width.
In view of the foregoing, methods and apparatus are needed that can be successfully and efficiently implemented to realize precise material removal within stringent tolerances of current and evolving feature sizes, and that can be implemented with porous, low-k dielectric layers forming and within a substrate.
USPTO Backgrounds
USPTO Backgrounds