1. Field of the Invention
The present invention is related to an electronic circuit technology, more specifically, to a data comparator, which utilizes a pair of non-inverting and inverting strobe signals as a dynamic reference voltage, and a data buffer using the same.
2. Description of the Prior Art
FIG. 1 (Prior Art) is a circuit diagram of a conventional input buffer in the digital circuits, which usually includes a data comparator 10 and a strobe signal comparator 20. Generally speaking, non-inverting/inverting strobe signals (STROB/STROB#) constitute a periodic differential signal with a T/2 phase difference, where T represents the period of these two strobe signals. Strobe signal comparator 20 receives the non-inverting/inverting strobe signals (STROB/STROB#) via its positive/negative input terminals, respectively, and produces a data-sampling strobe signal (STB) in view of crossing points of these two strobe signals. Since the differential signal of the non-inverting/inverting signals (STROB/STROB#) has a T/2 phase difference, adjacent rising/falling edges of the data-sampling strobe signal (STB) are spaced out T/2 apart. In addition, data comparator 10 receives a data signal (DATA) and a reference voltage (VREF) via its positive/negative input terminals, respectively, and compares them based on the rising/falling edges of the data-sampling strobe signal (STB), for determining logic levels of the output signal (DOUT), such as xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d
FIG. 2 (Prior Art) is a timing diagram illustrating the relationships between the data signal (DATA), the reference voltage (VREF) and the non-inverting/inverting strobe signal (STROB/STROB#) in the conventional input buffer. As shown in the figure, a crossing point T1 exists when the level of the non-inverting strobe signal (STROB) is going down and the level of the inverting strobe signal (STROB#) is going up. At this time, the level of the data signal (DATA) is lower than the reference voltage (VREF) and thus the output signal (DOUT) is set to be xe2x80x9c0.xe2x80x9d On the other hand, a crossing point T2 exists when the level of the non-inverting signal (STROB) is going up and the level of the inverting signal (STROB#) is going down. At this time, the level of the data signal (DATA) is higher than the reference voltage (VREF) and thus the output signal (DOUT) is set to be xe2x80x9c1.xe2x80x9d
The data comparator 10 of the conventional input buffer is called a pseudo-differential comparator, and compares an arbitrary data signal with a constant reference voltage. In addition, the strobe signal comparator 20 is called a fully differential comparator, comparing a pair of strobe signals in the differential form. In the conventional case, there is a T/4 phase difference between the data-sampling strobe signal (STB) and the data signal (DATA) for latching the data. A variety of industry standards, such as AGP4X, VLINK and Pentium 4 buses, adopt this kind of the center-aligned scheme.
However, the conventional data comparators still suffer from some disadvantages. As shown in FIG. 1, the data comparator 10 determines the logic levels of the output data (DOUT) based on the difference between the data signal (DATA) and the reference voltage (VREF). In fact, the slew rate of the data signal (DATA) and the variation of the reference voltage (VREF) may change the timing of the output signal (DOUT), which is dangerous for high-speed input/output buses which has very short bit time.
FIG. 3 (Prior Art) is a timing diagram for illustrating the neighborhood of a crossing point of the data signal (DATA) and the reference voltage (VREF), explaining the influence of the slew rate of the data signal on the output signal. Suppose that data comparator 10 needs a voltage difference xcex94Vm to detect the signal. In FIG. 3, numeral 1 stands for a first slew rate case and numeral 3 stands for a second slew rate case, where the first slew rate is higher than the second slew rate. Thus, the output signal (DOUT) suffers from a timing shift At when the slew rate of data signal (DATA) changes from the first slew rate case to the second slew rate case. Furthermore, the reference voltage (VREF) is usually a DC voltage, which is liable to be coupled by electrostatic discharge (ESD) devices or adjacent signal/power sources along the paths, which also affects the latch timing of the output signal (DOUT).
Therefore, the object of the present invention is to provide a data comparator structure and an input buffer using the same which can solve the above-mentioned problems, such as the influence of the slew rate and the instability of the reference voltage on the timing of the output signal.
The present invention achieves the above-indicated objects by providing a data comparator, which can be utilized in the input buffer circuit for processing the received data signal and comparing it with a dynamic reference voltage created by a pair of non-inverting/inverting signals. The data comparator comprises a comparator circuit for receiving a data signal and the non-inverting/inverting signals. The output signal is generated by comparing twice the data signal with the sum of the non-inverting signal and the inverting signal. In the preferred embodiment, the non-inverting signal and the inverting signal are periodic and complementary, coming from the same power/ground source as the data signal, such as strobe signals for creating the sampling signal in the data buffer. Thus, in the present invention, the non-inverting/inverting signals are used as a dynamic reference voltage to overcome the problems in the prior art.
In addition, the comparator circuit can comprise a current source having a first end coupled to a first high voltage, a load component with a current mirror configuration having a first end and a second end, a first transistor having a gate electrode coupled to the data signal and source/drain electrodes coupled to a second end of the current source and the first end of the load component, a second transistor having a gate electrode coupled to the data signal and source/drain electrodes coupled to the second end of the current source and the first end of the load component, a third transistor having a gate electrode coupled to the non-inverting signal and source/drain electrodes coupled to the second end of the current source and the second end of the load component, and a fourth transistor having a gate electrode coupled to the inverting signal and source/drain electrodes coupled to the second end of the current source and the second end of the load component. The output signal is a voltage on a node coupled between the first transistor and the load component.
In addition, the present invention also provides a data comparator, which comprises a two-input differential comparator circuit having a first transistor for receiving a data signal from and a second transistor for receiving a non-inverting signal, a third transistor in parallel with the first transistor for receiving the data signal and a fourth transistor in parallel with the second transistor for receiving an inverting signal. The comparator structure is used to compare twice the data signal with the sum of the non-inverting signal and the inverting signal.
USPTO Backgrounds
USPTO Backgrounds