1. Field of the Invention
The present invention relates to a system-in-package module and a manufacture method for a system-in-package module, and particularly to a system-in-package module and a manufacture method for a system-in-package module that can make a plurality of pads of a non-memory chip of the system-in-package module be electronically coupling with a plurality of pads of each memory die within a bundled memory without longer wire bonding or additional redistribution layers by rearranging locations of a plurality of pads of each memory die within the bundled memory.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a wafer 11 with a plurality of memory dies and a magnified structure of a memory die, wherein the wafer 11 includes a plurality of repeating units called dies. As shown in FIG. 1, in the wafer 11, a first memory die 121 is isolated from other dies, and separated from a second memory die 122 by a scribe line 12. In addition, after fabrication of the wafer 11 is completed, a plurality of memory dies of the wafer 11 are separated from each other by scribe lines, and each memory die of the plurality of memory dies has a plurality of pads disposed over the same location. For example, the first memory die 121 has a first group of pads 1211 disposed over or near an upper side of the first memory die 121, and the second memory die 122 has a second group of pads 1221 disposed over or near an upper side of the second memory die 122.
Generally speaking, after fabrication of the wafer 11 is completed, the wafer 11 is scribed into a plurality of individual separable memory dies (e.g. the first memory die 121 and the second memory die 122). However, sometimes it is required to scribe two memory dies together into one bundled memory 13 or four memory dies together into one bundled memory 14. For example, if a memory size and a bus width of each memory die are 2M×32 bit, respectively, the bundled memory 13 could have a bigger memory size (4M) and the same bus width (32 bits), or a bigger bus width (64 bits) and the same memory size (2M). In addition, the bundled memory 14 also has a bigger memory size (8M) and the same bus width (32 bits), or a bigger bus width (128 bits) and the same memory size (2M).
When the bundled memory 13 is stacked with another logic integrated circuit (a non-memory circuit, wherein the non-memory integrated circuit can be comprised of logic based semiconductor processes, RF, Analog and mix-mode circuits, etc. and the memory can be comprised of memory-based semiconductor processes, including DRAM, SRAM, NAND, MRAM, PRAM, RRAM, etc., wherein US Patent Application Publication No. 2013/0091315 and US Patent Application Publication No. 2013/0091312 have disclosed that memory ICs are stacked with a logic unit) each other, and then the bundled memory 13 and the logic integrated circuit (IC) are packaged or encapsulated together, if a portion of the second group of pads 1221 (or the first group of pads 1211) is covered by an active circuit region of the logic IC, it is difficult to electronically coupling with a plurality of pads of the logic IC to the portion of the second group of pads 1221 (or the first group of pads 1211) covered by the active circuit region of the logic IC without costly effort. That is to say, the plurality of pads of the logic IC either need longer wire bonds or extra redistribution layers (RDL) to be electronically coupling with the portion of the second group of pads 1221 (or the first group of pads 1211) covered by the active circuit region of the logic IC. On the other hand, a conventional dicing process is more lengthened, a form factor of a system-in-package module (or Multi-Chip Packaging (MCP)) is larger, and cost of materials is higher. Therefore, the prior art is not a good choice for the system-in-package module.
USPTO Backgrounds
USPTO Backgrounds