Epitaxy refers to the deposition by growth of an overlayer on a crystalline substrate where the overlayer is in registration with the substrate. The substrate surface acts as a seed layer for the growth. Epitaxial material may be grown from gaseous or liquid precursors. Because the substrate surface acts as a seed crystal, the epitaxial growth locks into one or more crystalline graphic orientations of the crystalline substrate. Epitaxial growth is widely used in the manufacture of integrated circuitry and may be fabricated on various types of crystalline—base materials, for example, semiconductor substrates, and be formed of various epitaxial materials. As an example, an epitaxial silicon growth may be provided on a silicon substrate, such as bulk silicon substrates, and silicon on insulators (SOI) substrates. However, an epitaxial grown material tends to form crystalline defects, known as dislocations and stacking faults, during growth, at confined side edges of the grown material. These crystalline defects can result in undesired charge leakage within or between devices fabricated from the epitaxial material, or undesired electron-hole charge recombination sites which reduces device electrical efficiency.
FIG. 1 illustrates one example of a silicon epitaxial (EPI) material 111 formed over a bulk silicon substrate 101. The illustrated structure includes a first dielectric 103, which may be an oxide, e.g., silicon dioxide, a polysilicon 105, and a second dielectric 107, which may be silicon nitride. Materials 103, 105 and 107 may be used for transistor gate structures in an integrated circuit formed on substrate 101. An opening is provided in the materials 103, 105 and 107 which extends to and exposes the upper surface 120 of substrate 101. A silicon nitride sidewall spacer 109 is also provided on the sidewalls of the polysilicon 105 so that epitaxial growth does not occur on the polysilicon 105 sidewall. The EPI material 111 begins its growth at the exposed upper surface 120 of substrate 101. During vertical growth of the EPI material 111, stresses develop at the side edges of the growth and can produce undesirable dislocations and stacking faults 113 which encompass some distance “d”.
FIG. 2 illustrates a planar view of the FIG. 1 structure later showing the dislocations and stacking faults 113 as extending around the confined side edges of EPI material 113.
One solution to the dislocation and stacking fault problem has been to use a particular crystal orientation of an underlying silicon on which the epitaxial material is grown. For example, U.S. Pat. No. 7,906,830 describes an integrated structure in which a silicon substrate orientation is changed to “111” so that silicon crystal orientation along a confined sidewall is in the “100” direction. Although the wafer reorientation described in U.S. Pat. No. 7,906,830 can reduce dislocations and stacking faults, it is often undesirable to orient the wafer in this manner for other technical reasons, such as optimizing performance of fabricated transistors and other structures.
A method and resulting structure which can produce an epitaxial growth with fewer dislocations and stacking faults and which does not require a particular crystal orientation of the substrate is desired.
USPTO Backgrounds
USPTO Backgrounds