Interconnect challenges for future microprocessors and other high performance chips arise from the continued push to lower k-effective of interlevel dielectric materials, higher aspect ratio for all wiring levels, and increasing number of metalization layers. At this point the back-end-of-the-line (BEOL) consists of as many as ten metalization levels that contain wires to provide interconnections for signal, clock, power, repeaters, devices, decoupling elements, etc.
Optimization of the microelectronic interconnects is critical for high performance, minimizing the energy dissipation, and maintaining a high level of signal integrity. However, as future interconnects shrink in dimension to allow gigascale integration, the signal delay and the signal fidelity problems associated with the interconnects become significant limiters of the overall system performance (e.g., maximum supportable chip clock frequencies or via blockage due to the need of a large number of vias to connect the multiplicity of wiring levels).
Since changes in system architectures of the planar CMOS IC technology do not achieve a significant performance yield increase per year, and further increase of the number of the interconnect levels raises significant reliability questions, new solutions become a necessity if significant improvements of planar CMOS technology are to be achieved in future IC generations.
Improved performance at a system level can also be achieved by changing the systems architecture. This solution comes at a high cost and is very time consuming as every new generation of products has to be redesigned and verified. Changes in architecture are difficult as they encompass a span of many critical building blocks including: memory and logic, routing, hierarchy, etc.
Therefore, it has been realized that there will be a slow down in the rate of performance improvements for new generations relative to the famous Moore's law of microprocessors if one were to depend on planar architecture alone.
To overcome the limitations of the fully planar integration schemes a variety of three-dimensional (3D) integration and packaging techniques are being evaluated in the art. The main considerations behind the use of 3D Integration are: minimization of the wire length, incorporation of new processes that are currently limited by conventional planar technology, and implementation of related design flexibility including new system architectures. All of which would allow significantly reduced interconnect delay as well as enable mixed system integration to increase both performance and functionality.
At this point 3D wafer-scale integration is a relatively new technology and further investigations including methodologies for reliable etching, cleaning, filling, aligning, bonding integrity, wafer-scale planarity, and integration with active circuits still have to be demonstrated. 3D integration based on stacking of wafer-level device layers has been a main focus of 3D IC technology. This process includes fabrication of each component on a separate wafer with its optimized processing technology, followed by aligning, bonding, and vertical interconnection of the wafers to build a new high functionality system.
The proposed 3D IC solutions show a great potential for future microprocessor generations. However the cost/benefit balance is likely to be favorable only for mature technology elements as in order to implement them in a 3D stacked IC solution reliability and high yields of individual elements along with very high bonding yields need to be realized. In addition, to fully utilize the capability of the 3D technology architectural changes at the micro and macro level of the system need to be implemented. Hence the time of clear insertion of 3D IC in the semiconductor technology road map is not well defined. Therefore, solutions in which some of the elements of the 3D integration schemes can be implemented with only small changes to the current ICs technology offerings to achieve performance and cost benefits are very desirable.
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