1. Field of the Invention
The invention relates in general to a method of removing the HDP oxide deposition, and more particularly to the method of using two-step etching to remove the HDP oxide deposition.
2. Description of the Related Art
In the fabrication of very large scale integration (VLSI), chemical-mechanical polishing (CMP) is the typical technique that provides global planarization. Since the feature size of the semiconductor device is greatly reduced, the manufactures depend on the technique for planarization process. An etch back process is also performed before CMP in order to obtain a better uniformity.
For the semiconductor device with small dimension, such as a line width of 0.25 μm or even 0.18 μm, it is very important to planarize the wafer surface, especially to planarize the oxide layer within in a trench. For example, the top oxide layer (composed of silicon oxide) above the silicon nitride (SIN) layer has to be planarized by CMP, so that the trench filled with the silicon oxide is coplanar with the SIN layer. However, there is an problem for an HDP oxide layer, which the silicon oxide layer formed by high-density plasma (HDP) method is too thick to be completely polished by CMP.
A conventional process of forming a shallow trench isolation (STI) is taken for illustration. FIG. 1A˜FIG. 1C depict the cross-sectional view of a conventional process for forming a shallow trench isolation by chemical-mechanical polishing (CMP). In FIG. 1A, a bottom oxide layer 102 and a silicon nitride (SIN) layer 104 are formed on the substrate 100. Then, the shallow trench 106 is formed by photolithography. In FIG. 1B, a HDP oxide layer 108, the silicon oxide (SIO2) deposited by using high-density plasma (HDP) method, is formed over the SIN layer 104 and fills the shallow trench 106. The characteristic of the HDP oxide layer is that the oxide film is about 8 K (8000 Å) thick and the surface of the deposited film is undulating. If the HDP oxide layer 108 is directly polished by the CMP method for remove, some of the HDP oxide is still remained on the SIN layer 104, as shown in FIG. 1C. Those HDP oxide residues denoted as 108a will cause the serious problem in the post manufacturing process.
For solving the over-thick problem of HDP oxide layer, an etching back process is also applied before the CMP method. FIG. 2A˜FIG. 2D depict the cross-sectional view of another conventional process for forming a shallow trench isolation. In FIG. 2A and FIG. 2B, the bottom oxide layer 202 and a SIN layer 204 are formed on the substrate 200. Also, the shallow trench 206 is formed by photolithography. Then, the HDP oxide layer 208 is formed on the SIN layer 204 and fills the shallow trench 206. A photo-resist (PR) is coated on the HDP oxide layer 208 and patterned to be a PR mask 210 using photolithography, as shown in FIG. 2C. Then, the exposed part of the HDP oxide layer 208, which is the part not covered by the PR mask 210, is etched away. This etch back process can partially remove the HDP oxide film 208 and the remained HDP oxide 208a is easy to be polished away by CMP method.
However, the etch back process performed by the typical etch tool has a drawback that the etching rate is not uniform. The etch tool typically set as an in-side-out model or out-side-in model. The in-side-out model means that the etching rate in the center of the wafer is faster than in the two ends of the wafer. On the contrary, the out-side-in model means that the etching rate in the two ends of the wafer is faster than in the center of the wafer. Also, the deposition tool for forming the HDP oxide film has its structural limit, so that the deposited HDP oxide film close to the wafer's periphery is thinner than the wafer's center. If this uneven HDP oxide film is etched by an etch tool with out-side-in model, the thinner part of the oxide film (closed to the wafer's edge) will be quickly etched and become much thinner while the thicker part of the oxide film (closed to the wafer's center) will be slowly etched and maintain thicker, as shown in FIG. 2D.
The poor uniformity of the remained HDP oxide layer 208a causes the abnormal result in the CMP process of removing SIN layer, that is the over-thinner SIN around the wafer's edge. It not only increases the difficulty in controlling the SIN-removing process, but also causes stringer during SAMOS etch. The yield of the wafer is therefore affected.
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