1. Technical Field
The present invention relates to an apparatus and method of generating a reference clock for a DLL (Delay Locked Loop) circuit, and more particularly, to an apparatus and method of generating a reference clock for a DLL circuit that generates a reference clock having a constant duty ratio even if the amount of power supply changes.
2. Related Art
In general, the DLL circuit is used to generate an internal clock whose phase leads a phase of a reference clock, which is obtained by converting an external clock. In a semiconductor integrated circuit, such as a synchronous DRAM (SDRAM), which has relatively high integration, the internal clock operates in synchronization with the external clock.
More specifically, the external clock is input to a clock buffer through an input pin of the semiconductor integrated circuit. The clock buffer outputs an internal clock. Then, the internal clock controls a data output buffer so as to output data. Here, the phase of the internal clock is delayed more than a phase of the external clock by a clock buffer. The internal clock having the delayed phase is further delayed by delay elements in the semiconductor integrated circuit and transmitted to the data output buffer.
Therefore, there occurs a problem in that output data is output after being delayed for an extended period of time as compared with the external clock. In other words, the time for which data is output after the external clock is applied, that is, output data access time is increased.
The DLL circuit may prevent an extension of the output data access time. The DLL circuit allows the phase of the internal clock to lead that of the external clock by a predetermined time. Therefore, output data is output without delay with respect to the external clock. That is, the DLL circuit receives the external clock and generates the internal clock whose phase leads a phase of the external clock.
The DLL circuit includes the clock buffer so as to generate a reference clock that is obtained by converting the amplitude of the external clock. Here, the generated reference clock is used to compare a phase thereof with a phase of a feedback clock by a phase comparator. Further, the reference clock is used as an input signal of a delay line that generates the internal clock under the control of a shift register.
Hereinafter, the operation of a DLL circuit according to the related art will be described with reference to the accompanying drawing.
FIG. 1 is a timing diagram illustrating the operation of an apparatus for generating a reference clock for a DLL circuit according to the related art.
In FIG. 1, a positive external clock clk_ext, a negative external clock /clk_ext, and a reference clock clk_ref are shown. A clock buffer receives the positive external clock clk_ext and the negative external clock /clk_ext so as to generate the reference clock clk_ref that has the same phase as a phase of the positive external clock clk_ext. Substantially, there is a difference in amplitude between the positive external clock clk_ext and the reference clock clk_ref, but the difference is not shown in FIG. 1.
As shown in FIG. 1, a level of a DLL power supply voltage Vdll that is used as a power supply for the DLL circuit may be arbitrarily changed. Examples of factors causing the voltage level to be changed may include a voltage level change of an external power supply, a change in the amount of load that occurs due to an entrance to or exit from a power down mode, a change in temperature, or the like. If the level of the DLL power supply voltage Vdll is changed due to one of the factors, a ratio between a low-level period and a high-level period in the reference clock clk_ref output by the clock buffer is not exact “1:1”. Here the ratio is called a duty ratio. This is because when the level of the DLL power supply voltage Vdll falls, the low-level period of the reference clock clk_ref increases, and when the level of the DLL power supply voltage Vdll rises, the high-level period of the reference clock clk_ref increases. In FIG. 1, a level change of the DLL power supply voltage Vdll is denoted by dV, and a change in phase of the reference clock clk_ref is denoted by dD.
As described above, when the duty ratio of the reference clock is variable, an operation of a phase comparator is not performed in a normal state. Due to an error of the duty ratio, an internal clock output through a delay line does not have a pre-set phase, and thus, reliability of the operation of the DLL circuit is reduced. As a result, the operation may cause the semiconductor integrated circuit having the DLL circuit therein not to operate. However, in the related art, there may be an erroneous operation of the DLL circuit because the duty ratio of the reference clock is variable.
USPTO Backgrounds
USPTO Backgrounds