1. Field of the Invention
The present invention relates to semiconductor fabrication processes. More particularly, the present invention relates to an after-etch-inspection critical dimension (AEI CD) control method for contact process.
2. Description of the Prior Art
In the fabrication of semiconductor devices, it is typical to use photoresist layer on a semiconductor wafer to mask a predetermined pattern for subsequent etching or ion implantation processes. The patterned photoresist is usually formed by, firstly, coating the photoresist, exposing it to suitable radiation (UV, EUV, e-beam, etc.), and then developing (and baking) the exposed photoresist. For positive-type photoresist, for example, the irradiated parts of the photoresist are chemically removed in the development step to expose areas of the underlying layer where are to be etched.
As known in the art, quality inspections are carried out after development and after etching, respectively, to ensure good quality of the device critical dimensions (CDs), which are also referred to as After-Develop-Inspection CD (ADI CD) and After-Etch-Inspection CD (AEI CD). These quality control procedures are designed to remedy any process anomaly in time.
As the feature size of the semiconductor devices shrinks, the difference between the ADI CD and AEI CD becomes larger. This turns out to be a serious problem when the device dimension shrinks to nano scale and beyond. In some circumstances, the AEI CD that is smaller than the ADI CD is required. For example, in the fabrication of contact holes of a SRAM device, the contact hole is in close proximity to the polysilicon gate. In such case, even very slight deviation of the AEI CD may result in short between the contact device and the gate, thus causing malfunction of the memory unit. It is desired to precisely control the AEI CD in order to improve product quality and reliability.
USPTO Backgrounds
USPTO Backgrounds