1. Field of the Invention
The present invention relates to a modulation technique, and more particularly, to a sigma-delta modulation method and a related sigma-delta modulator.
2. Description of the Prior Art
Sigma-delta modulators are implemented in a variety of applications. For conventional sigma-delta modulators, their performance (e.g., signal-to-noise ratio, SNR) can only be enhanced by increasing an order of the loop filter or increasing a bit number of the quantizer for a given over-sampling ratio. High-order sigma-delta modulations may have stability issues and suffer from unstable oscillation. However, the employment of multi-bit quantizers with an increased number of bits guarantees a resolution boost at the expense of a more complicated circuit structure, leading to undesirable outcomes such as higher power consumption, a larger chip area requirement and a more serious mismatch due to numerous DACs in the feedback path. Therefore, it is a remaining issue to simplify the overall circuit structures of sigma-delta modulators without sacrificing performance, for example, the integrator and the truncater utilized in a traditional sigma-delta modulator may put a certain design restrictions; a better efficiency will be achieved if those components can be realized in more compact topologies.
USPTO Backgrounds
USPTO Backgrounds