Packaging of semiconductor devices, such as wireless communication devices, has lead to the implementation of various techniques to effect electrical connections to the semiconductor devices, as well as thermal paths to dissipate heat. Heat dissipation, in particularly, is significant as specifications require devices to be more compact, resulting in the various electronic components, many of which generate heat during operation, occupying smaller spaces.
For example, a radio frequency (RF) power amplifier transistor needs to generate large-amplitude output signals while occupying a small physical volume, as a result of final product form factor constraints and/or manufacturing cost minimization. This results in very high power density. One exemplary implementation of such RF power amplifiers uses III-V heterojunction bipolar transistors (HBT) in a flip-chip configuration with copper pillars used to attach the RF power amplifier die to a module printed circuit board (PCB). The mismatches in thermal expansion coefficients of the different materials of such a device can produce significant undesirable physical stress. Such stress, in turn, may result in break-down and/or separation of layers and components within the device.
FIG. 1 shows a cross-sectional view of an example of a conventional amplifier device. Referring to FIG. 1, the amplifier device 100 includes multiple transistor fingers, indicated by representative transistor finger 110, arranged in parallel on a substrate 101, which may be formed of a semiconductor material. Each transistor finger 110 may be an HBT, for example. Although one transistor finger 110 is depicted in FIG. 1, it is understood that the other transistor fingers (not shown) of the amplifier device 100 have substantially the same configuration as the transistor finger 110.
The amplifier device 100 further includes first-level interconnects 131 and 132, a planarizing dielectric layer 140, a second-level interconnect 145, and a common conductive pillar 150. As indicated, there are two first-level interconnects, indicated by illustrative first-level interconnects 131 and 132, associated with each of the multiple transistor fingers 110 of the amplifier device 100. The second-level interconnect 145 and the conductive pillar 150 generally provide electrical and thermal conductivity with respect to the transistor finger 110. The amplifier device 100 also includes a planarizing dielectric layer 140, which fills the various spaces among the transistor finger 110, the first-level interconnects 131 and 132, and the second-level interconnect 145. The planarizing dielectric layer 140 also provides planarized surfaces on which the second-level interconnect 145 is formed.
The transistor finger 110 itself includes a base/collector mesa stripe 111, which includes a base 113 stacked on a collector 112 of the transistor finger 110. The collector 112 is disposed on a subcollector 114, which may be at least partially embedded in the substrate 101 and extends continuously beneath the stacked first-level interconnects 131 and 132 situated on opposite sides of the transistor finger 110, respectively, to the adjacent transistor fingers (not shown). Collector contacts 133 are disposed on the subcollector 114 beneath the stacked first-level interconnects 131 and 132. The subcollector 114 carries collector current to the collector contracts 133, providing electrical connection between the collector 112 and the stacked first-level interconnects 131 and 132, respectively. Base contacts 117 are disposed on a top surface of the base 113 to provide electrical connection to the base 113.
The transistor finger 110 further includes a set of emitter mesa stripes 121 and 122 arranged on the base/collector mesa stripe 111. Each of the emitter mesa stripes 121 and 122 comprises semiconductor emitter layers 124 stacked on a top surface of the base 113. The semiconductor emitter layers 124 are typically formed of ternary and/or quaternary semiconductor materials, for example. Emitter contacts 125 are stacked on the semiconductor emitter layers 124, respectively. Metal layers 126 are selectively disposed over emitter contacts 125 of the emitter mesa stripes 121 and 122, which provide traces for carrying electrical signals to and from the emitter mesa stripes 121 and 122, respectively.
Emitter metallization 123 is formed over the emitter mesa stripes 121 and 122, electrically and mechanically contacting the emitter contacts 125 of the emitter mesa stripes 121 and 122. Otherwise, the emitter metallization 123 is separated from the remaining portions of the emitter mesa stripes 121 and 122, as well as from the base/collector mesa stripe 111, by a conformal dielectric layer 115, electrically isolating the emitter metallization 123 from the remaining portions of the emitter mesa stripes 121 and 122, and from the base/collector mesa stripe 111. The emitter metallization 123 also directly contacts the second-level interconnect 145, which provides electrical and thermal connectivity between the set of emitter mesa stripes 111 and 112 of the transistor finger 110 and the conductive pillar 150.
Notably, the width (horizontal dimension) of the emitter metallization 123 is contained within (less than) the width of the top surface of the base 113 of the base/collector mesa stripe 111. That is, no portion of the emitter metallization 123 extends to (or beyond) the outer edges of the base/collector mesa stripe 111. Accordingly, heat generated during operation of the transistor finger 110 is dissipated generally upwardly, through the emitter metallization 123 to the second-level interconnect 145 and the conductive pillar 150.
More particularly, heat is generated primarily in regions 170 and 180 of the collector 112 in the base/collector mesa stripe 111, located beneath the emitter mesa stripes 121 and 122, respectively. From region 170, the generated heat dissipates through the emitter mesa stripe 121 and the emitter metallization 123 via thermal path 171, and around the emitter mesa stripe 121 and through the emitter metallization 123 via thermal paths 172 and 173. From region 180, the generated heat dissipates through the emitter mesa stripe 122 and the emitter metallization 123 via thermal path 181, and around the emitter mesa stripe 122 and through the emitter metallization 123 via thermal paths 182 and 183. This provides relatively few thermal paths for accommodating heat dissipation, particularly from an HBT (e.g., transistor finger 110), for example, confined in a compact amplifier device 100. Also, the ternary and/or quaternary materials of the semiconductor emitter layers 124 have relatively poor thermal conductivity, and the conformal dielectric 115 also typically has relatively poor thermal conductivity. This configuration therefore results in relatively high thermal resistance.
Accordingly, there is a need for semiconductor devices able to simultaneously manage thermal resistance and physical stress, while minimizing required physical volume and manufacturing cost.
USPTO Backgrounds
USPTO Backgrounds