Embodiments of this invention relate generally to methods of operating a semiconductor device and, more particularly to program methods of a semiconductor device.
A semiconductor device includes a memory cell array in which data is stored. The memory cell array includes a plurality of cell blocks. Each of the cell blocks includes a plurality of cell strings. The cell strings have the same structure, and only one of the cell strings is described below in detail.
FIG. 1 is a sectional view of a cell string for illustrating known phenomenon.
Referring to FIG. 1, the cell string includes a plurality of memory cells and switching elements which are formed over a semiconductor substrate 10. The switching elements comprise a drain select transistor and a source select transistor. In case of a NAND flash memory device, the plurality of memory cells is formed, for example, between the drain select transistor and the source select transistor, and a junction 11 is formed in the semiconductor substrate 10 between the transistors and the respective memory cells. Each of the drain and source select transistors includes a gate insulating layer 12 and a gate electrode 14 which are sequentially stacked over the semiconductor substrate 10. Each of the memory cells includes the gate insulating layer 12, a floating gate 16, a dielectric layer 17, and a control gate 18 which are sequentially stacked over the semiconductor substrate 10. The gate insulating layer 12 is made of an insulating material, such as an oxide layer. The dielectric layer 17 may have a stack structure including an oxide layer, a nitride layer, and an oxide layer, or it may be made of a high-k material. The floating gate 16, the control gate 18, and the gate electrode 14 are made of a conductive material, such as polysilicon. The drain select transistors included in different cell strings are coupled to a drain select line DSL, the source select transistors included in different cell strings are coupled to a source select line SSL, and the memory cells included in different cell strings are coupled to respective word lines WLn−k to WLn+k.
A method of programming a semiconductor memory device including the cell string is described below.
Referring to FIGS. 1 and 2, a program permission voltage (for example, a ground voltage) is applied to the channel of a selected cell string (it is hereinafter assumed that the cell string of FIG. 1 has been selected), a program voltage Vpgm is applied to a selected word line (for example, WLn) coupled to a selected memory cell, and a pass voltage Vpass is applied to the remaining unselected word lines WLn−k to WLn−1 and WLn+1 to WLn+k. When the program voltage Vpgm is applied to the selected word line WLn, the potential of the floating gate 16 rises owing to coupling between the control gate 18 and the floating gate 16. As a result, electrons within the semiconductor substrate 10 are introduced into the floating gate 16 through the gate insulating layer 12 because of a tunneling phenomenon. An operation in which the electrons are introduced into the floating gate 16 is called a program operation. In contrast, an operation in which electrons in the floating date 16, for example, electrons introduced into the floating gate 16 are drained out to the semiconductor substrate 10 is called an erase operation.
Recently, a multi-level cell (MLC) method of programming one memory cell in various levels is chiefly used. In order to program one memory cell in various levels, the distribution widths of the threshold voltages of memory cells must be narrow. To this end, a program operation using an Incremental Step Pulse Program (hereinafter referred to as an ‘ISPP’) method is used.
A program operation using an ISPP method is performed by applying the program voltage Vpgm to the selected word line WLn and applying the pass voltage Vpass to the remaining unselected word lines WLn−k to WLn−1 and WLn+1 to WLn+k. In general, the pass voltage Vpass has a level lower than the program voltage Vpgm. More particularly, the program voltage Vpgm having a low level is applied at the early stage of program, and the program voltage Vpgm is raised by a step voltage. After the program voltage Vpgm and the pass voltage Vpass are applied, a verify operation for determining whether the threshold voltage of the selected memory cell has reached a target voltage is performed. If, as a result of the verify operation, the threshold voltage of the selected memory cell is determined not to have reached the target voltage, the program operation and the verify operation are repeated by applying the program voltage Vpgm and the pass voltage Vpass while gradually raising the program voltage Vpgm by the step voltage until the threshold voltage of the selected memory cell reaches the target voltage. If, as a result of the verify operation, the threshold voltage of the selected memory cell is determined to have reached the target voltage, the program operation is terminated.
While the program operation is performed, the program voltage Vpgm gradually rises, whereas the pass voltage Vpass(1) having a constant level is applied to the remaining unselected word lines WLn−k to WLn−1 and WLn+1 to WLn+k. Accordingly, a difference between the program voltage Vpgm and the pass voltage Vpass gradually increases. Furthermore, while the program operation is performed, whereas an increasing pass voltage Vpass(2) is applied to the remaining unselected word lines WLn−k to WLn−1 and WLn+1 to WLn+k. The increasing pass voltage Vpass(2) increases as a step-up level lower than that of the program voltage Vpgm. In case of unselected memory cells adjacent to the selected memory cell, if the program voltage Vpgm applied to the selected word line WLn becomes higher than a specific level, the unselected memory cells may be erased under the influence of the raised program voltage Vpgm of the adjacent selected memory cell. That is, if the program voltage Vpgm gradually rises and then voltage difference between the program voltage Vpgm and the pass voltage Vpass reaches a Critical voltage Difference (hereinafter referred to as a ‘CD’), a breakdown BD between the unselected memory cells and the selected memory cells may be occurred. Furthermore, electrons which are stored in the floating gate 16 of the unselected memory cells adjacent to the selected memory cell may be ejected to the control gate 18 of the selected memory cell, and so the threshold voltages of the unselected memory cells may be decreased
As described above, when the program voltage Vpgm applied to the selected word line WLn in the program operation gradually rises and thus a difference between the program voltage Vpgm and the pass voltage Vpgm reaches the CD, the threshold voltages of unselected memory cells adjacent to the selected memory cell may be shifted, and the reliability of the program operation may deteriorate.
USPTO Backgrounds
USPTO Backgrounds