1. Field of Invention
The present invention relates to a delay circuit. More particularly, the present invention relates to a delay circuit in a reset integrated circuit (IC).
2. Description of Related Art
For a conventional reset integrated circuit (IC) employed for circuit protection, a delay circuit therein is usually provided for preventing the reset IC from mis-operation caused by a power glitch, in which the delay time configured by the delay circuit can be correspondingly changed by using different extrinsic capacitors. However, it is not convenient to replace different extrinsic capacitors whenever various kinds of delay time are to be configured.
USPTO Backgrounds
USPTO Backgrounds