The present invention applies to the error amplifier used in either a linear regulator or a switching regulator. The drawbacks of the prior art will be discussed with reference to a linear regulator.
FIG. 1 illustrates one representative prior art linear regulator 10 integrated circuit, which is a negative voltage regulator, although the invention applies equally to positive voltage regulators. The term “linear regulator” is generally synonymous with a “low dropout (LDO) regulator.” The term “low dropout” refers to the small minimum voltage differential that can occur between the input voltage terminal and the regulated output voltage terminal while still achieving regulation.
LDO regulators operate by varying the conductivity of a series transistor, connected between the input terminal and the output terminal, to achieve a predetermined output voltage. The output level of an operational amplifier (op amp), which is a type of differential amplifier, controls the conductivity of the series transistor. The op amp is sometimes referred to herein as an error amplifier. Typically, the regulator's output voltage is fed back into one input terminal of the op amp, and the conductivity of the series transistor is controlled to match the output voltage to a reference voltage applied to the other input of the op amp. The user selects the reference voltage. Alternatively, a divided output voltage is fed back and matched to a fixed reference voltage, where the user selects resistors for the divider to achieve the desired output voltage.
In FIG. 1, the user connects an Rset resistor 15 to a Set pin 16 of the IC to set the output voltage Vout provided at the Vout pin 18. A load is typically connected between the Vout pin 18 and ground. The input voltage (a negative voltage in this example, usually Vee) is applied to the Vin pin 19, so Vout will be somewhere between Vin (plus the dropout voltage) and ground. A fixed precision current source 20 supplies a fixed current through the Rset resistor 15 to generate a reference voltage Vref at the inverting input of the op amp 22, being used as an error amplifier. The output voltage Vout is applied to the non-inverting input of the op amp 22. The terms inverting and non-inverting simply refer to the two branches of the differential amplifier in the op amp 22, shown in FIG. 2.
Using an internal current source 20 and Rset resistor 15 to set the reference voltage is preferred to dividing the output voltage and matching the divided voltage (typically about 1.2 volts) to a fixed bandgap reference voltage source, since, by using the current source, the loop gain and bandwidth of the regulator are not affected by the output voltage, and Vout is allowed to go to a very low voltage.
The op amp 22 controls the conductivity of the pass transistor 24 so that Vout matches Vref.
FIG. 2 is a basic example of one type of op amp 22, which represents a conventional op amp. The input signals Vout and Vref (from FIG. 1) are applied to NPN transistors 28 and 30. A current source 33 supplies a fixed current to the tied emitters of the transistors 28/30. Well known circuitry 32 provides a single ended output for driving the pass transistor 24 (FIG. 1). The circuitry 32 may include other differential amplifiers, current minors, current sources, and other well-known circuitry. The pertinent feature of the op amp 22 represented is the bipolar transistor input stage, drawing a base current Ib from the current source 20. The present invention applies to any type of op amp having a bipolar transistor input stage.
FIG. 3 illustrates the op amp 22 along with a conventional base current compensation circuit 40 connected to the base of the transistor 30. No base current compensation is needed for the transistor 28. Since the current source 20 current (Isource) is a fixed known value and the user selects the precise Rset resistor value (R) to achieve a desired Vref equal to (Isource×R), any base current (Ib) into the transistor 30 will increase the voltage drop across the Rset resistor and distort the desired Vref value. Accordingly, it is known to provide the compensation circuit 40 to supply the same Ib current that is drawn by the transistor 30 to effectively cancel the effect of the base current drawn by the transistor 30. Many circuit configurations are possible, and FIG. 3 shows a representative example. FIG. 3 may also represent the op amp (error amplifier) in a switching regulator.
Assuming the current source 33 is designed to draw a current of 2I, the current source 42 in the compensation circuit 40 is designed to draw a current of I through the transistor 43 (since transistors 28 and 30 are assumed to be drawing equal currents I during regulation). Transistor 43 is matched to transistor 30. This will cause Ib to flow through the current minor of transistors 44 and 46. The mirrored current Ib is then added to the node coupling Vref to the base of the transistor 30 to cancel the Ib drawn by the transistor 30.
One problem with the conventional base current compensation circuit 40 of FIG. 3 is that it requires Vref to be at least about 0.3 volt below ground for proper operation. This limits the allowable Vout range. For some applications, a regulated output voltage between −0.3 volt and ground is needed. Similarly, in positive voltage regulators, the Vref cannot go within 0.3 volt of ground without adversely affecting the operation of the base current compensation circuit. Other types of base current compensation circuits require even more headroom to operate. Further, in a floating configuration (typically used for high voltages), where the ground pin is connected to Vout, the conventional base current compensation circuit does not have sufficient headroom to operate.
The problem occurs equally for error amplifiers in linear regulators and switching regulators.
What is needed is a base current compensation technique for a positive or negative regulator employing an error amplifier, where the compensation circuit does not limit the range of output voltage regulation due to the level of Vref.
USPTO Backgrounds
USPTO Backgrounds