This invention relates in general to electronic assemblies and testing thereof. In particular, the invention relates to a method of manufacture of protruding, controlled aspect ratio and shape contacts for uses in interconnections of assemblies and testing thereof.
Interconnections which involve protruding electrical contacts are used extensively in packaging of electronics. Pin grid array packages, both plastic and ceramic, housing a variety of semiconductors, use area arrays of pins as interconnect contacts for connection to circuit boards. Pins can be attached to their receiving package conductors by use of a variety of methods. For ceramic packages, pins are inserted into non-reacting brazing fixtures and are then gang-brazed to corresponding conductive terminals on the package. This approach is characterized by significant non-recurring engineering costs and lead times involved in production of the brazing fixture. Plastic pin grid array packages most commonly use pins which are inserted into metallized through holes in a circuit board, while the dimensions of pins and the holes normally chosen to facilitate good contact between the walls of the pins and the coating of the holes. This approach has a disadvantage in that the coated holes and the pins block some circuit routing channels within the circuit board, thus forcing either use of narrow circuit traces, or increase in circuit board area, either of which results in increased costs.
Permanent connection of the pin grid array packages to circuit boards often is accomplished by inserting pins through corresponding holes in a circuit board, the pins protruding to a predetermined length beyond the circuit board. A resulting assembly then is passed through a wave soldering machine, and the pin grid array thus is soldered to the circuit board. Alternatively, a pin grid array can be inserted into a low insertion force or zero insertion force socket for a demountable assembly. Such a socket, in its turn, normally is connected permanently to a board.
A current trend in interconnections is toward face-to-face surface mounting of components to boards and semiconductor chips to substrates. This approach is best accomplished with protruding contact structures on top of (or otherwise protruding from) contact carrying conductive terminals or traces. Conductive terminal arrangements on facing components and substrates are increasingly being made of the area array type, as this allows for larger contact-to-contact separation as compared with components characterized by peripheral arrangement of interconnection contacts.
Pins attached to either ceramic or plastic packages according to the traditional methods are, in general, not appropriate for mounting to patterns of surface contacts on circuit boards, due to pin length variation. For surface mounting, the pins would have to be planarized, which represents an additional expensive step subsequent to pin assembly. In addition, there is a significant cost penalty associated with production of pin-carrying packages with pin-to-pin separations of 50 mils, or lower.
There is currently an increasing need for a low cost method of attaching protruding contacts from conductive terminals, arising from proliferation of surface mountable area array contact packages. Stand-off height of protruding contacts is particularly important when coefficients of thermal expansion of components and of circuit board materials differ significantly. The same is true for attachment of un-packaged semiconductor chips to interconnection substrates. These expansive concerns call for a low cost, high volume method of manufacturing protruding, controlled aspect ratio or shape electrical contacts on top of (or otherwise protruding from) contact carrying conductive terminals, on top of any device or circuit bearing substrate, board material or component, and its applications to surface mount interconnections of devices, components and substrates.
USPTO Backgrounds
USPTO Backgrounds