Embodiments of the present invention relate generally to processors, and more particularly to processors including multiple cores such as many-core processors.
A many-core processor includes multiple processing cores on one or more die, typically on a single die. As process technologies scale to very small dimensions, the prevailing design approach of achieving high performance by increasing processor frequency is limited due to increased power consumption. One alternative approach to achieve high performance is to distribute an application across many “small” cores that run concurrently at slower speeds than a typical “larger” core. Because each “small” core is simpler, smaller and far less power hungry than a “large” core while still delivering significant performance, a many-core design can help manage power consumption more efficiently than a single or large-core design.
Although a many-core processor has advantages over a processor with a single core or a few large cores, it also faces many challenges as process technologies scale down. For example, process variations, either static or dynamic, can make transistors unreliable; transient error rates may be high since capacitance on storage nodes is small and voltages are low; and reliability over time may deteriorate as transistor degradation becomes more severe as years pass. Thus one-time factory testing and burn-in, as implemented for conventional processors, becomes less effective to ensure reliable computing over time with a many-core processor.
USPTO Backgrounds
USPTO Backgrounds