Field
The present disclosure relates generally to layout construction, and more particularly, to a source separated cell that may be part of a standard cell library.
Background
A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. Reducing a size/area footprint of ASICs is beneficial. Reducing a size of the process technology may allow for the size/area footprint of ASICs to be reduced. In some instances, when reducing the size/area footprint of ASICs, resistance of one or more current paths through one or more of the standard cells may be increased. There is currently a need to address such an increased resistance in one or more current paths within a metal oxide semiconductor (MOS) device in a standard cell.
USPTO Backgrounds
USPTO Backgrounds