1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and fabricating method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for forming a high voltage device gate oxide layer having a uniform thickness in a manner of previously performing a prescribed pre-processing on an STI edge area in forming a dual-gate oxide layer.
2. Discussion of the Related Art
Recently, as a semiconductor device design technology has gradually developed with an enhanced degree of integration, a system integrated on one semiconductor chip has been attempted. Such a one-chip implementation developing into a technology combining the functions of a controller, a memory, a circuit driven at low voltage, and other components into one chip.
To reduce the size of the system, a circuit functioning as input and output ends for adjusting power of a system may be merged into one chip. This can be enabled by unifying high voltage and low voltage transistors into one chip.
In integrating high and low voltage devices on one chip, a gate oxide layer of the high voltage device should be thicker than that of the low voltage device. Accordingly, a dual gate oxide layer is typically used. An oxide layer formed by thermal oxidation is typically preferred as the dual gate oxide layer as compared to an oxide layer formed by chemical vapor deposition (CVD). The oxide layer formed by thermal oxidation can provide a better quality oxide layer.
For a high voltage device employing a thick oxide layer as a gate oxide layer, the edge of the oxide layer is affected by the structure around its circumferential area. If the thickness of the gate oxide layer is reduced, an off-current is increased by this influence. The increase of the off-current increases static power consumption of the device to have a negative influence on the operation of the device and causes a breakdown voltage drop. As such, the increase of the off-current limits the fabrication of the high voltage device.
FIGS. 1A to 1F are cross-sectional views illustrating a conventional method of fabricating a dual gate oxide layer.
Referring to FIG. 1A, an active area and an inactive area are defined on a semiconductor substrate 10. A device isolation layer 12 is formed on the inactive area of the semiconductor substrate 10 by STI shallow trench isolation (STI).
The semiconductor device is driven by receiving high or low voltage. Semiconductor devices can be classified as a high voltage device driven at high voltage and/or a low voltage device driven at low voltage. Hence, the active area of the semiconductor substrate 10 is divided into an area for forming the high voltage device (high voltage device area) and an area for forming the low voltage device (low voltage device area) to implement both functions of the high and low voltage devices. Each of the areas is considered in designing a circuit.
Subsequently, while the inactive area is covered with a mask pattern, ion implantation is performed on the semiconductor substrate 10 to form a well region 14 in the active area.
Referring to FIG. 1B and FIG. 1C, wet oxidation is performed on the semiconductor substrate to form a first gate oxide layer 16 that is the thicker portion of a dual gate oxide layer.
A photoresist is coated over the semiconductor substrate. Exposure and development are performed to form a photoresist pattern 18 that exposes the inactive area and the low voltage device area. The first gate oxide layer 16 is then patterned by etching using the photoresist pattern 18 as a mask to form a first gate oxide layer pattern 16a on the high voltage device area only.
Referring to FIG. 1D, a prescribed photoresist strip process is carried out to remove the photoresist pattern 18. Thermal oxidation is then carried out on the low voltage device area using NO gas to form a second gate oxide layer (not shown). Subsequently, a second gate oxide layer pattern 20 corresponding to a thin part of the dual gate oxide layer is formed. In doing so, a nitride layer 19 is formed on an interface between the semiconductor substrate 10 and the second gate oxide layer pattern 20. Subsequently, a polysilicon layer 22 is formed over the semiconductor substrate to form a gate electrode.
Referring to FIG. 1E, a first gate electrode 24 for a high voltage device is formed on the high voltage device area and a second gate electrode 26 for a low voltage device is formed on the low voltage device area by selectively etching the polysilicon layer 22, the first gate oxide layer pattern 16a, and the second gate oxide layer pattern 20 simultaneously using a gate electrode pattern mask. Hence, a dual gate electrode including the first and second gate electrodes 24 and 26 is formed.
Referring to FIG. 1F, light ion implantation to form a shallow junction on the active area of the semiconductor substrate 10 is carried out to form lightly doped drain (LDD) regions 28. In doing so, the first and second gate electrodes 24 and 26 are used as a mask and are doped with predetermined ions by the light ion implantation.
Subsequently, by carrying out the prescribed deposition and etch sequentially, lightly doped drain (LDD) and high temperature low pressure dielectric (HLD) spacers 30 are formed on sidewalls of the first and second gate electrodes 24 and 26, respectively.
Source/drain regions 32 are formed by carrying out heavy ion implantation using the first and second gate electrodes 24 and 26 and the spacers 30 as a mask.
Subsequently, a metal, such as Ti, Co and the like, is deposited over the semiconductor substrate. By carrying out the prescribed annealing and etch, salicide (for example, self-aligned silicide) is formed on the first and second gate electrodes 24 and 24 and the source/drain regions 32.
In forming the dual gate oxide layer, the relatively thick first gate oxide layer is formed by wet oxidation. The first gate oxide layer is patterned by photolithography, and then removed by stripping. Subsequently, thermal oxidation fixation is carried out in the presence of NO gas to form the relatively thin second gate oxide layer.
However, in case of forming the dual gate oxide layer by the conventional method, the oxidation reaction, as shown in FIG. 2, occurs slowly at the STI edge to bring about a thinning effect such that the gate oxide layer on the high voltage device area is thinned. In this case, the quality and robustness of the gate oxide layer are degraded due to the irregular thickness of the gate oxide layer. To prevent the thinning effect, the gate oxide layer may be formed, not by thermal oxidation, but by chemical vapor deposition (CVD). The quality of the oxide layer formed by CVD may be poorer than that of the oxide layer formed by thermal oxidation.
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