The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device including a compact and stable wordline driving device.
Semiconductor memory devices, such as a dynamic random access memory (DRAM), need to store a large amount of data and operate at a high speed using a low input voltage.
Highly integrated semiconductor memory devices have small memory cells and read/write components. For this, lines and transistors of the highly integrated semiconductor memory devices are integrated so as to remove unnecessary parts and reduce the size of the highly integrated semiconductor memory devices.
Each cell of a semiconductor memory device includes a capacitor for storing data and a transistor for controlling read and write operations of the capacitor. The cells are connected to control wordlines and data transfer bit lines. Specifically, a gate of the transistor is connected to the wordline, and one of a drain and a source of the transistor is connected to the bit line. In a cell of a highly integrated semiconductor memory device, a gate of a transistor and a wordline are integrated such that a portion of the wordline is used as the gate of the transistor. However, due to the integration of the gate and the wordline, the capacitance of the wordline increases, and the gate of the transistor needs to be formed of polysilicon having a relatively high resistance. Therefore, it takes much more time to activate or deactivate the wordline. That is, time delay occurs when the wordline is activated using a wordline driving signal produced according to decoded address information. Therefore, data access time increases, and the operating speed of the highly integrated semiconductor memory device decreases.
To address these problems, a semiconductor memory device having a hierarchical wordline structure has been introduced. In a hierarchical wordline structure, a plurality of sub wordlines are connected to a main wordline, and the sub wordlines are driven through the main wordline. Only the sub wordlines are formed of polysilicon and signal transfer lines for selecting the main wordline and the sub wordlines are formed of a metal such as aluminum (Al) so as to minimize signal delay. Sub wordline driving circuits for driving a plurality of sub wordlines through a main wordline will now be described.
FIG. 1A is a circuit diagram illustrating sub wordline driving circuits each including three transistors, and FIG. 1B is a waveform diagram for explaining how the sub wordline driving circuits of FIG. 1A operate.
Referring to FIG. 1A, a semiconductor memory device includes a first sub wordline driving circuit and a second sub wordline driving circuit. The first sub wordline driving circuit drives a first sub wordline SWLi in response to a signal received through a main wordline MWLB. The second wordline driving circuit drives a second sub wordline SWLj in response to a signal received through the main wordline MWLB. The first sub wordline driving circuit includes three transistors, and the second sub wordline driving circuit includes three transistors.
Generally, the main wordline MWLB may be connected to eight sub wordline driving circuits, and each of the eight sub wordline driving circuits receives a wordline driving voltage FX to be applied to a sub wordline SWL, and a wordline discharge signal FXB for controlling the sub wordline SWL. Each of the eight sub wordline driving circuits includes a p-channel metal oxide semiconductor (PMOS) transistor, a first n-channel metal oxide semiconductor (NMOS) transistor, and a second NMOS transistor. The PMOS transistor applies the wordline driving voltage FX to the sub wordline SWL in response to a signal transmitted through the main wordline MWLB. The first NMOS transistor applies a ground voltage to the sub wordline SWL in response to a signal transmitted through the main wordline MWLB. The second NMOS transistor discharges the sub wordline SWL to a ground voltage level in response to the wordline discharge signal FXB.
Referring to FIG. 1B, when the main wordline MWLB is activated to a low logic level and a first wordline driving voltage FXi to the first sub wordline driving circuit is activated, a first wordline discharge signal FXBi is deactivated to a low logic level such that the first sub wordline SWLi can be activated by the first wordline driving voltage FXi. On the other hand, when a second wordline driving voltage FXj to the second wordline driving circuit is deactivated, a second wordline discharge signal FXBj is activated to a high logic level such that the second sub wordline SWLj is deactivated to a low logic level.
In detail, there are eight wordline driving voltages FX0 to FX7 corresponding to the main wordline MWLB. Each of the wordline driving voltages FX0 to FX7 has a level corresponding to an input address. When the wordline driving voltage FX is not activated although the main wordline MWLB is activated to a low logic level, the sub wordline SWL can be connected to the ground through the second NMOS transistor in response to the wordline discharge signal FXB so as to prevent the sub wordline SWL from being floated.
The semiconductor memory device includes eight sub wordline driving circuits for each main wordline MWLB. Furthermore, two additional lines as well as the main wordline MWLB are connected to each of the eight sub word line driving circuits to apply the wordline driving voltage FX and the wordline discharge signal FXB to the sub word line driving circuit. Therefore, the size of the semiconductor memory device increases and it is difficult to highly integrate the semiconductor memory device due to a number of lines connected to the sub wordline driving circuits.
To address these problems, an improved sub wordline driving circuit has been introduced. FIG. 2A is a circuit diagram illustrating sub wordline driving circuits each including two transistors, and FIG. 2B is a waveform diagram for explaining how the sub wordline driving circuits of FIG. 2A operate.
Referring to FIGS. 2A and 2B, each of the sub wordline driving circuits includes two transistors. That is, each of the sub wordline driving circuits includes a PMOS transistor and an NMOS transistor. The PMOS transistor applies a wordline driving voltage FX to a sub wordline SWL in response to a signal transmitted through a main wordline MWLB. The NMOS transistor adjusts the voltage level of the sub wordline SWL to a ground voltage in response to a signal received through the main wordline MWLB.
When the main wordline MWLB is activated to a low logic level and an activated first wordline driving voltage FXi is applied to a first sub wordline SWLi, the sub wordline driving circuit operates in the same way as the sub wordline driving circuits depicted in FIG. 1A. When a second wordline driving voltage FXj is not activated although the main wordline MWLB is activated to a low logic level, the main wordline MWLB has the same voltage level as the threshold voltage level of the NMOS transistor instead of a ground voltage level so as to prevent the sub wordlines SWL from being floated. That is, the sub wordlines SWL are connected to the ground through the NMOS transistors, thereby preventing the sub wordlines SWL from being in a floating state. Therefore, since each of the sub wordline driving circuits includes only two transistors and does not require lines for receiving a wordline discharge signal, the sub wordline driving circuits occupy smaller areas.
However, the NMOS transistor needs to have a threshold voltage different from that of the PMOS transistor. For this, for example, the sub wordline driving circuit should be designed in consideration of the turn-on resistances of the NMOS and PMOS transistors in a manner such that the NMOS transistor and the PMOS transistor have different channel widths and lengths.
FIG. 3 is a circuit diagram illustrating wordline line driving circuits of a typical semiconductor memory device.
Referring to FIG. 3, the semiconductor memory device includes a main wordline driving circuit 320 and sub wordline driving circuits 340_0 to 340_7. The main wordline driving circuit 320 activates a main wordline in response to first to third control signals DR1 to DR3 produced according to address information decoded using a decoder. The sub wordline driving circuits 340_0 to 340_7 activate sub wordlines SWL0 to SWL7 in response to a signal transmitted through the main wordline and wordline driving voltages FX0 to FX7.
The main wordline driving circuit 320 includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a second PMOS transistor. The first PMOS transistor applies a high voltage VPP to the main wordline in response to the first control signal DR1 so as to deactivate the main wordline. The first NMOS transistor activates the main wordline to a ground voltage level in response to the second control signal DR2. The second NMOS transistor maintains the main wordline at the same voltage level as the threshold voltage level of NMOS transistors of the sub wordline driving circuits 340_0 to 340_7 in response to the third control signal DR3. Here, the voltage level of the main wordline is determined between a core voltage level VCORE and a ground voltage level by a ratio of the resistances of the second PMOS transistor and the second NMOS transistor.
The sub wordline driving circuits 340_0 to 340_7 have the same structure as the two-transistor sub wordline driving circuit shown in FIG. 2A. Thus, detailed descriptions of the sub wordline driving circuits 340_0 to 340_7 will be omitted.
FIGS. 4A and 4B are waveform diagrams for explaining how the wordline driving circuits of FIG. 3 operate. Referring to FIG. 4A, the main wordline MWLB is activated to a low logic level in response to control signals DR1 to DR3, and an activated wordline driving voltage FX is applied to the sub wordline driving circuits 340_0 to 340_7 to activate the sub wordlines SWL. Referring to FIG. 4B, the wordline driving voltage FX is not activated although the main wordline MWLB is activated to a low logic level in response to control signals DR1 to DR3 such that the sub wordline driving circuits 340_0 to 340_7 deactivate the sub wordlines SWL.
Referring again to FIG. 4B, the activated main wordline MWLB is maintained at a predetermined voltage level instead of maintaining the main wordline MWLB at a ground voltage level so as to prevent the sub wordlines SWL from being floated. For this, as described above, the turn-on resistance of the second NMOS transistor included in the main wordline driving circuit 320 is adjusted using the third control signal DR3 so as to maintain the ratio of the resistances of the second PMOS transistor and the second NMOS transistor. However, in this case, since the voltage level of the activated main wordline MWLB is sensitive to the third control signal DR3, the semiconductor memory device may operate unstably. Furthermore, since the activated main wordline MWLB is maintained at a predetermined voltage level, a current path can be formed between the PMOS transistor and the NMOS transistor of the main wordline driving circuit 320, and thus the voltage levels of the sub wordlines SWL0 to SWL7 can be unstable.
USPTO Backgrounds
USPTO Backgrounds