1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof, particularly to a package type semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
A CSP (Chip Size Package) has been gathering attention as a package type semiconductor device. The CSP means a small package having almost the same outside dimensions as those of a semiconductor die packaged in it.
Conventionally, BGA (Ball Grid Array) type semiconductor device have been known as a kind of CSP. In such a BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of metal such as solder is arrayed in a grid pattern on one surface of the package, and electrically connected with the semiconductor die mounted on the other side of the package. The BGA type semiconductor device of the conventional art will be described with reference to drawings.
FIG. 9 is a cross-sectional view for explaining the semiconductor device of the conventional art. As shown in FIG. 9, pad electrodes 61 are formed on a front surface of a semiconductor die 60A of a semiconductor device 2. Furthermore, the front surface of the semiconductor die 60A is covered with a sealing member 63. Via holes are formed in the semiconductor die 60A, penetrating the semiconductor die 60A from its back surface to the pad electrodes 61. Embedded electrodes 68 are formed in the via holes, being connected with the pad electrodes 61. Ball-shaped conductive terminals 71 are formed on the embedded electrodes 68 exposed at the via holes on the back surface of the semiconductor die 60A.
The semiconductor device 2 is mounted on a circuit board 80 formed with a conductive pattern (not shown) so that the circuit board 80 and the back surface of the semiconductor die 60A face to each other. Conductive paste 90 made of, for example, solder is formed by printing on a surface of the circuit board 80 formed with the conductive pattern (not shown), in regions to be connected with the conductive terminals 71. Furthermore, a so-called under filler 91 for preventing a vacant space from forming between the back surface of the semiconductor die 60A and the circuit board 80 is formed on the surface of the circuit board 80, in a region where the conductive paste 90 is not formed.
The conductive paste 90 increases its fluidity by a reflow process and partially covers the conductive terminals 71. This makes the conductive terminals 71 electrically connected with the conductive pattern (not shown) of the circuit board 80 and fixed to the circuit board 80.
The relevant technology is disclosed in the Japanese Patent Application Publication Nos. 2003-309221, 2002-512436 and 2003-229518.
However, there has been a problem that adhesion failure occurs when the described semiconductor device 2 of the conventional art and the circuit board 80 are connected to each other with the conductive paste 90. This is because that the amount of the conductive paste 90 formed on the circuit board 80 is limited and sometimes the conductive paste 90 does not properly extend to both the conductive terminals 71 and the conductive pattern (not shown) of the circuit board 80 in the reflow process. Furthermore, when the amount of the conductive paste 90 is increased for solving the adhesion failure, there arises a problem that the adjacent conductive terminals 71 are short-circuited in the reflow process because of excess conductive paste. Furthermore, it has been difficult to check whether the semiconductor device 2 and the circuit board 80 are properly connected with each other.
Furthermore, even if the semiconductor device 2 and the circuit board 80 are properly connected to each other with the conductive paste 90, mechanical strength of the connection is not enough because of the small amount of conductive paste. For solving this, a so-called under filler made of an epoxy resin is formed between the semiconductor die 60A and the circuit board 80 to prevent the short-circuit between the conductive terminals 71 and increase the mechanical strength. Since the formation of the under filler is generally performed by a user of the semiconductor device, there has been a problem that the mounting processes performed by the user increases.
As a result, the mounting processes to be performed by the user of the semiconductor device become complex, and the mounting accuracy lowers.
USPTO Backgrounds
USPTO Backgrounds