Technical Field
The present application relates to memory devices, and particularly to 3D array memory devices in which include 3D capacitors.
Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers look for techniques to stack multiple levels of memory cells to achieve greater storage capacity and lower costs per bit. Therefore, various three-dimensional structures are developed, such as vertical channel and vertical gate NAND memories. Capacitors can be used to help reduce voltage variations and can be used to help save data in memories, such as SRAM, DRAM and Flash, either during normal operations or due to unexpected power failures. In the program and erase operation, the bias voltages applies to word lines/bit lines using charge pumps to elevate the voltage at a high voltage level, which requires high capacitance. However, conventional capacitors providing large capacitance take a large area footprint, which in turn affects the scalability of the memory device.
It is desirable to provide a capacitor including stable yet large capacitance, but having a reduced area without increasing manufacturing cost.
USPTO Backgrounds
USPTO Backgrounds