The present invention generally relates to copper precursors that are used to deposit thin copper films. More specifically, the present invention relates to non-fluorinated copper precursors which are volatile, thermally stable and can be used, for example, to deposit thin copper films using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.
The semiconductor industry uses metal-containing interconnects, such as copper (Cu), in electronic devices such as, for example, state of the art microprocessors. The metal-containing interconnects, which may be embedded fine metal lines, form the three dimensional grid upon which millions of transistors at the heart of the microprocessor can communicate and perform complex calculations. In these and other applications, copper or alloys thereof may be chosen over other metals such as, for example, aluminum because copper is a superior electrical conductor, thereby providing higher speed interconnections of greater current carrying capability.
Interconnect (IC) pathways within electronic devices are typically prepared by the damascene process, whereby photolithographically patterned and etched trenches and vias in the dielectric insulator are coated with a conformal thin layer of a diffusion barrier material. A diffusion barrier layer is typically used in conjunction with a metal or copper layer to prevent detrimental effects caused by the interaction or diffusion of the metal or copper layer with other portions of the integrated circuit. Exemplary barrier materials include, but are not limited to, titanium, tantalum, tungsten, chromium, molybdenum, zirconium, ruthenium, vanadium, palladium and/or platinum as well as carbides, nitrides, carbonitrides, silicon carbides, silicon nitrides, and silicon carbonitrides of these materials and alloys comprising same. In certain processes, such as when, for example, the interconnect comprises copper, the diffusion barrier layer may be coated with a thin ‘seed’ or ‘strike’ layer of copper, prior to completely filling in the features with pure copper. In still other cases, the seed layer of copper may be replaced by—or used in addition to—an analogous cobalt or similar conducting thin film ‘glue’ layer. Excess copper may then removed by the process of chemical mechanical polishing. Since the smallest features to be filled can be less than 0.2 microns wide and over 1 micron deep, it is preferable that the copper seed layer, copper glue layer and/or the diffusion barrier layers be deposited using metallization techniques that are capable of evenly filling these features, without leaving any voids, which could lead to electrical failures in the finished product.
In addition to the aforementioned processes for building the interconnect pathways within silicon chips, there is also the new and rapidly emerging technology of three-dimensional (3D) packaging which requires the fabrication of relatively larger scale copper interconnects known as TSV (Through Silicon Vias). TSV refers to the relatively large conducting vias which, when run through thinned IC, memory, or Micro Electromechanical (MEMS) silicon chips, enable them to be stacked and wired together into high functioning energy efficient devices that bear a small footprint. There are a number of approaches to 3-D packaging. The ‘via first’ approach entails first etching vias into the silicon wafer, filling them with copper before doing the Complementary Metal Oxide Semiconductor (CMOS) or before doing Back End of Line (BEOL) processing on top of the wafer. The wafer underside is then thinned and multiple chips from it are stacked and bonded. The ‘via last’ approach has two methods. The first method involves etching and filling the vias after BEOL, then sequentially thinning, stacking, and bonding the devices together. The second method involves taking finished wafers, thinning them, stacking them and bonding them, then etching vias through the stack and filling the vias with copper. Each approach to 3-D packaging has its own pros and cons. For instance, in the ‘via last’ approach, there can still be some signal routing possible above the TSVs whereas via first permits the TSV vias to be constructed in unthinned (i.e., mechanically robust) wafers. In all cases, TSV vias are relatively deep because they need to span the entire thickness of the thinned silicon wafer, which is oftentimes greater than 100 microns deep. The density of these interconnects can be in the region of 104 vias/mm2 of silicon surface. Once the chips are stacked and aligned, the vias are fused together by a variety of techniques to form continuous conducing lines thereby ‘wiring’ the chips together.
There are many reasons behind the growing importance and pursuit of TSV. The device density and short conducting pathways between chips that it affords directly translates to compact, high performance low energy consuming systems that are critical for the burgeoning mobile application markets such as, for example, camera phones, i-phones, personal data assistant (PDA) devices, global positioning systems (GPS), and the like where miniaturization and battery life are of paramount importance. Another very important factor driving TSV 3-D packaging is that since the TSV vias represent a 3 orders of magnitude shortening of the typical interchip interconnects encountered using other packing techniques such as Package on a Package (PoP), System in a Package (SiP) and System on a Chip (SoC), the clock speed of the resulting packages can rival or equal that of devices manufactured at finer geometries. TSV therefore presents a strong economic driver by not needing to stay on the CMOS shrink curve. For instance, an IC with stacked memory shows a 1000 fold increase in speed with a 100 fold decrease in power consumption by eliminating the signal delays and power consumption from horizontal wiring.
Numerous methods such as ionized metal plasma (IMP), physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), cyclic chemical vapor deposition (CCVD), plasma-assisted chemical vapor deposition (PACVD), plasma-enhanced chemical vapor deposition (PECVD), electroplating, and electroless plating have been used to deposit metal-containing layers such as the metallization, diffusion barrier, and/or other layers. Among them, CVD and ALD methods using one or more organometallic precursors may be the most promising methods because these methods provide excellent step coverage for high aspect ratio structures and good via filling characteristics. In a typical CVD process, a vapor of a volatile organometallic precursor containing the desired metal is introduced to a substrate surface whereupon a chemical reaction occurs in which a thin film containing the metal as a compound or as a pure element is deposited on the substrate. Since the metal is typically delivered in a vapor form as a volatile precursor, it can access both vertical and horizontal surfaces to provide an evenly distributed thin film. In a typical ALD process, a volatile organometallic precursor is alternately pulsed into a reactor with a reagent gas such that self-limiting alternating monolayers of precursor/reagent are deposited on the substrate wherein the monolayers react together to form a metal film or a metal-containing film which is subsequently reduced to metal or used as deposited. For example, if a copper organometallic precursor was reacted with a suitable oxidant in an ALD process, the resulting cuprous oxide or cupric oxide monolayer or multilayer could be used for semiconductor applications or reduced to copper metal.
For copper thin films, some of the same precursors suitable for CVD and other depositions may also be suitable as ALD precursors. In certain applications, it may be preferable that the precursor be highly volatile, deposit copper films that are substantially pure (i.e., have a purity of about 95% or about 99% or greater copper), and/or minimize the introduction of potentially contaminating species into the reaction chamber or onto the diffusion barrier or other underlying surfaces. Further, in these applications, it may be preferable that the copper film exhibits good adhesion to the diffusion barrier layer because poor adhesion may lead to, inter alia, delamination of the copper film during chemical mechanical polishing.
Several organometallic precursors have been developed to deposit low electrical resistivity copper films by the aforementioned processes, particularly CVD or ALD processes. Two of often-used families of copper organometallic precursors that have been studied extensively are the Cu(I) and Cu(II) precursors. One commonly used Cu(i) precursor is a precursor having the formula “Cu(I)(hfac)(W)” precursor where “hfac” represents the 1,1,1,5,5,5-hexafluoro-2,4-pentanedionate anion and (W) represents a neutral stabilizing ligand, such as, for example, an olefin, an alkyne, or a trialkylphosphine. One particular example of a Cu(I) precursor having the above formula is 1,1,1,5,5,5-hexafluoro-2,4-pentanedionato-copper (I) trimethylvinylsilane (hereinafter Cu(hfac)(tmvs)), which is sold under the trademark CUPRASELECT™ by Air Products and Chemicals, Inc. of Allentown, Pa., the assignee of the present application. These Cu(I) precursors can deposit films via a disproportionation reaction whereby two molecules of the precursor react on a heated substrate surface to provide copper metal, two molecules of free ligand (W), and the volatile by-product Cu(+2)(hfac)2. Equation (1) provides an example of a disproportionation reaction:2Cu(+1)(hfac)W→Cu+Cu(+2)(hfac)2+2W  (1)
In CVD depositions, the disproportionation reaction illustrated in Equation (1) is typically run at a temperature of around 200° C.; however, other temperatures may be used depending upon the deposition process. As Equation (1) illustrates, the Cu(+2)(hfac)2 constitutes a byproduct from the reaction and may need to be removed from the reaction chamber.
Yet another type of Cu(I) precursor is a precursor having the formula “(Y)Cu(Z)”. In these particular Cu(I) precursors, “Y” is an organic anion and “Z” is a neutral stabilizing ligand, such as, for example, trialkylphosphine. An example of such a precursor is CpCuPEt3, where Cp is cyclopentadienyl and PEt3 is triethylphoshine. Under typical CVD conditions, two of these precursor molecules may react on a wafer surface, whereby the two stabilizing trialkyphosphine Z ligands become disassociated from the copper centers, the two (Y) ligands become coupled together, and the copper (I) centers are reduced to copper metal. The overall reaction is shown below in Equation (2).2(Y)Cu(Z)→2Cu+(Y—Y)+2(Z)  (2)However, in certain instances, this type of chemistry may present problems because the released trialkylphosphine ligands may contaminate the reaction chamber and act as undesired N-type silicon dopants.
As mentioned previously, yet another type of precursor used to deposit copper-containing films is Cu(II) precursors. Unlike the Cu(I) precursors, the Cu(II) precursors require the use of an external reducing agent such as, for example, hydrogen or alcohol to deposit copper films that are largely free of impurities. An example of a typical Cu(II) precursor has the chemical formula Cu(II)(Y)2 wherein (Y) is an organic anion. Examples of this type of precursor include, but are not limited to, Cu(II)bis(β-diketonates), Cu(II) bis(β-diimine), and Cu(II) bis(β-ketoimine) compounds. Equation (3) provides an illustration of a deposition reaction wherein hydrogen is used as the reducing agent.Cu(II)(Y)2+H2→Cu+2YH  (3)The Cu(II) precursors are typically solids and the temperatures required for film deposition are typically above 200° C.
In addition to the copper precursors described above, U.S. Pat. No. 7,205,422, which is commonly assigned to the assignee of the present application and incorporated herein by reference, describes non-fluorinated as well as fluorinated metal precursors which are suitable for ALD or CVD depositions of thin metal films.
In certain applications such as 3-D packaging, it is desirable to provide a copper metallization process which is cost effective and rapid. To use copper electroplating to fill these features, a seed layer of copper is first needed to line the inside of the TSV features. Currently, physical vapor deposition (PVD) copper is used for this purpose, but this line-of-sight technique is typically limited in its ability to provide vertical sidewall coverage. This is particularly problematic for TSV vias due to its relatively great depth. In addition, as 3-D packaging evolves, the density of TVS per unit area will increase and thereby drive the ratio of via depth to diameter higher to minimize the surface area of the chip that is consumed. This increased aspect ratio will further compromise the ability of PVD to provide adequately conformal copper seed layers with good sidewall coverage. For these reasons, CVD copper represents an excellent technology for proving good sidewall coverage and possibly a means by which to fill entire TSV structures with copper in one step. Thus, good CVD copper precursor may need to be thermally stable yet chemically reactive to permit high vapor pressures of precursor and high growth rates of copper respectively.
Accordingly, there is a need in the art for copper precursors that exhibit at least one of the following properties in ALD or CVD processing: thermal stability, chemically reactive, volatility, and allows for a high growth rate of copper metal.
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