The present invention relates to semiconductor integrated circuits, and more particularly, to an input-output (I/O) buffer having a pull up device which pulls the I/O pad to a voltage that is greater than transistor tolerances.
Advancements in semiconductor integrated circuit fabrication technology enable the geometries of semiconductor devices to be progressively reduced so that more devices can fit on a single integrated circuit. As a result, core voltages of the integrated circuits are being reduced to prevent damage to the small devices and to reduce power consumption. For example, power supplies are now being reduced from 5 V to 3.3 V, and from 3.3 V to 2.5 V.
These low voltage devices are often interconnected at a board level to TTL logic and other devices that operate at higher supply voltages of 5 V or 3.3 V. If no precautions are taken, an external 3.3 V level signal applied to the output terminal of a 2.5 V I/O buffer can cause voltage drops across the transistor devices in the I/O buffer that exceed the transistor tolerances, which can cause the gate oxide of the transistors to break down. I/O buffers are therefore being developed to interface with large voltages without exceeding the tolerance levels of the devices within the integrated circuit.
Also, when multiple integrated circuits share a board level bus, it is desirable that the bus have a known logic value when all I/O buffers connected to that bus are in a tri-state mode. This prevents "crow bar" current in the I/O buffers and unknown states within the integrated circuits. One methodology of defining the logic state of a board level bus is to provide I/O buffers with small, built-in pull-up or pull-down devices that can be easily overdriven when the I/O buffer is in use but will drive the bus to a supply voltage rail when all I/O buffers connected to that bus are in the tri-state mode.
USPTO Backgrounds
USPTO Backgrounds