Many battery-powered electronic products require so-called "micropower" data conversion circuitry that drains extremely low levels of battery current. In particular, implantable medical products require micropower analog-to-digital converters (ADCs) that operate at low voltage and low current. Pacemakers, for example, include miniature transmitters for transmitting to an external receiver a wide variety of signals concerning the heart or the state of the pacemaker itself. A physician may monitor electrocardiogram signals detected by the pacemaker to determine whether pacemaker parameters, such as shock voltage or pacing rate, need to be adjusted. Alternatively, the physician may need to examine measured data concerning battery voltage or lead impedance to determine whether the pacemaker requires replacement.
The complex signals measured by the pacemaker can be transmitted to the external receiver in analog form. As an illustration, the pacer may measure the voltage of an ECG signal and use that voltage to create a frequency modulated (FM) signal by employing a voltage controlled oscillator (VCO). The external receiver would demodulate the FM signal to recover the analog ECG waveform. A major problem with this technique lies in the fact that this analog modulation scheme is highly susceptible to noise, resulting in an unreasonably noisy signal at the external receiver.
Converting the signals measured by the pacer to digital form before transmission overcomes many of the problems encountered in analog telemetry. Digital signals are inherently less susceptible to noise and permit the pacer to take advantage of noise reduction techniques well known in the field of digital signal processing. In addition, providing a clean digitized signal, such as an ECG waveform, to a physician allows a comprehensive examination of the waveform morphology of cardiac signals. Important parameters such as ECG amplitude, slope and frequency content can be analyzed.
The widespread use of ADCs to provide digital data has been hampered by the stringent power requirements of implantable medical devices. The power consumed by those devices is one of the most important design factors. Implantable systems are customarily powered by a long-lasting non-replaceable internal battery. As an example, the life of a pacemaker battery averages approximately five to seven years. During normal operation, conventional pacemakers experience a current drain on the order of tens of micro amperes (mA), while conventional low-power ADCs drain on the order of 0.1 to 1.0 mA. When the battery voltage decreases below a prescribed amount, the entire pacemaker must be surgically replaced. Consequently, it is desired to keep ADC power drain to the lowest possible level to minimize the need for pacer battery replacement.
Obtaining a low enough current drain is usually accomplished by drastically reducing the sample rate. This limits the conversion bandwidth of the ADC and so may compromise its ability to properly encode dynamic signals. Alternatively, one may sacrifice resolution (bits) to obtain lower current at a desired sample rate. This limits accuracy. What is needed is an ADC that can sample different types of signals (measured data, IEGM, sense amp, sensors, etc.) at the appropriate sample rate and resolution while at the same time drawing an acceptable current drain. An ADC with these capabilities may be multiplexed with any of these input signals to allow multiple input signal sources to share the same ADC. Multiplexing saves chip area and reduces current by eliminating the redundant conversion circuitry that would otherwise be dedicated to each signal.
Device design considerations dictate the selection of the optimal ADC architecture for a given data acquisition environment. For example, a cardiac pacemaker manufactured by the assignee of the present invention requires a multiplexed ADC that consumes less than one mA of current and operates at a sample rate on the order of one kilosample per second (KSPS). The ADC must also exhibit a resolution of approximately eight bits and operate with a supply voltage range of approximately -1.8 to -2.8 volts.
The successive approximation architecture is an effective implementation that meets the above-mentioned constraints. This architecture calculates a bit at a time and thus inherently requires less power than a parallel architecture such as a flash ADC, which requires 2.sup.n -1 comparators for an n-bit converter. Alternatively, an integrating slope converter is unsatisfactory because it requires a very high speed internal clock to achieve each bit of resolution. Finally, a sigma delta modulation architecture cannot be used for multiplexed input signals because the sigma delta architecture relies on the correlation between successive signal samples, while successive multiplexed samples from different signal sources are inherently uncorrelated. As a consequence, the successive approximation architecture is an optimal micropower ADC architecture.
FIG. 1 illustrates a conventional successive approximation ADC, which includes a digital-to-analog converter (DAC) 100, a comparator 102 and control logic circuitry 104. As is well known in the art, the DAC of a successive approximation ADC that is employed in low power CMOS applications is often implemented using a binary weighted, switched capacitor array 106, such as that shown in FIG. 1. High quality capacitors can be fabricated in double poly CMOS processes. Moreover, matching of these capacitors to within a 0.1% error measure has been demonstrated. Matching of the relative values of the capacitors in a binary weighted array is crucial to obtaining an accurate, linear digital conversion.
Based on an analog input voltage V.sub.IN and a reference voltage V.sub.REF, the DAC 100 initially provides a first approximation to the analog voltage V.sub.IN. This first approximation is the analog version of a digital code word D.sub.out provided by the logic 104. For example, the most significant bit (MSB) D.sub.1 of the control logic 104 may initially be set to one (1) and the remaining bits to zero (0) in order to represent a midrange value. The resulting analog output of the DAC 100 is input to the comparator 102 effectively to determine whether the approximation is greater than or less than the input voltage V.sub.IN. Based upon this decision, the logic 104 respectively sets or resets the MSB. This process is continued with subsequent bits until a code word D.sub.out representing the input analog voltage V.sub.IN is achieved.
In the conventional architecture, the input voltage V.sub.IN enters the ADC through the bottom plates of the capacitors in the array 106. Each bit conversion is accomplished through a sequence of three operations. In the first operation, the "sample mode," the top plate is connected to ground by a top plate grounding switch 108 and the bottom plates are connected to the input voltage V.sub.IN by a configuration of bottom plate grounding switches 110 and a bottom plate input switch 112. This results in a stored capacitor charge that is proportional to the input voltage V.sub.IN. In the "hold mode," the top grounding switch 108 is opened and the bottom plates are connected to ground by bottom plate grounding switches 110. Because of the conservation of charge, the top plate potential goes to -V.sub.IN. The "redistribution mode" begins by testing the value of the most significant bit (MSB) by raising the bottom plate of the largest capacitor to the reference voltage V.sub.REF by a proper configuration of the switches. The voltage V.sub.x at the input to the comparator 102, which was equal to -V.sub.IN previously, is now increased by one-half the reference voltage as a result of this operation, so that EQU V.sub.x =-V.sub.IN +V.sub.REF /2.
The output of the comparator is one (1), and the MSB D.sub.1 is set to 1, if V.sub.IN &gt;V.sub.REF /2, while the comparator output and the MSB D.sub.1 is set to zero (0) if V.sub.IN &lt;V.sub.REF /2. The output of the comparator therefore is the value of the binary bit being tested. Typically, the settling of the DAC 100 in response to the comparator update and the comparator acquisition of a new input must occur together in the same one-half of a bit-clock cycle time (the acquisition phase). The other half cycle is dedicated to the comparator latching operation in which the comparator output is provided at a logic level to update the bit. The above-described sequence of operations is repeated for each bit to complete the conversion process.
A number of error sources found in conventional successive approximation ADCs result in increased power consumption and a reduction in conversion speed. For example, a disadvantage of the bottom plate charging method is that one-half of a bit-clock cycle time must be spent opening the top grounding switch 108 and grounding the bottom plates to shift the input voltage potential to the top plate for comparison by the comparator 102. The alternative to this method would be to introduce the input voltage to the top plates initially. However, the capacitor switches are implemented using FETs, for which the channel charge injected into the top plate is a function of V.sub.IN. This signal dependent charge integrates onto the top plate capacitance to cause an input signal hold pedestal. The pedestal creates offset, gain, and distortion errors in the final ADC conversion result. As a consequence, in conventional ADCs, the bottom plate charging method is preferred, even though it requires an extra conversion step.
Offset errors introduced by the different components comprising the ADC are also encountered in analog-to-digital converters. A typical ADC implements buffers and comparators using subcircuits such as operational amplifiers (op amps). The ideal op amp responds to a zero input voltage with a zero output voltage. However, in actual operation, because of device non-idealities, a small input offset voltage exists between the differential terminals of an op amp even when no input voltage is applied. The cumulative effect of the offset voltages found in the components of an ADC results in an offset error in the digital conversion output.
Typically, offset voltage is eliminated as a source of error by a technique known as auto-zeroing. Auto-zeroing is a technique that is well known in the art. Two good references in the art which explain this, as well as other techniques related to the invention, are Analog MOS Integrated Circuits for Signal Processing, Gregorian, Temes et al. (Wiley and Sons--1986) and Switched Capacitor Circuits, Allen, Sanchez-Sinencio et al. (Van Nostrand Reinhold--1984).
Auto-zeroing is a popular technique, but it typically requires unity gain stability of the circuit being auto-zeroed, which reduces its bandwidth and thereby increases power. This problem is especially true for the ADC comparator which operates at a multiple of the sampling rate, and whose speed ultimately limits the conversion speed of the ADC. Moreover, the accuracy of the auto-zero technique is limited by switch charge injection and so requires a relatively large capacitance to achieve a sufficient level of offset correction. The cumulative effect is the addition of a large capacitance to the entire analog-to-digital converter. The charging of this capacitance consumes power and slows the overall conversion speed because of the additional time required to charge the larger capacitors. Further, each auto-zeroed op amp is typically implemented using two gain stages cascaded or one gain stage cascoded to obtain satisfactory offset cancellation. These op amps are wasteful of power and may degrade conversion speed significantly.
Another factor mitigating against micropower operation is the high current required to quickly charge the large capacitance of the DAC capacitor array to VIN.
The circuitry driving the array with the input and reference voltages typically must operate at relatively high power to charge the array at a sufficiently high rate.
Further, the comparator must rapidly amplify small signals up to full logic levels to determine each bit of the resulting ADC output. The comparator is biased at a low current input as part of the overall effort to minimize current drain. Unfortunately, starving the comparator in this manner can cause the comparator output to exhibit unacceptably slow slew rates. Slow slew rates can lead to disastrous crossover currents in subsequent logic circuitry. The crossover currents cause high current spikes, resulting in a substantial drain on the battery supplying the ADC.
It is therefore appreciated that there exists a substantial need for an analog-to-digital converter which is capable of operating in an implantable medical device at a rate fast enough to acquire rapidly changing data, while at the same time minimizing current consumption.
USPTO Backgrounds
USPTO Backgrounds