1. Field of the Invention
The present invention generally relates to pulsewidth modulation of an electronic signal, more specifically to a programmable circuit for pulsewidth modulation of a clock signal in an integrated circuit, and particularly for use in clocking an array such as static random-access memory (SRAM).
2. Description of the Related Art
Integrated circuits are used for a diverse number of electronic applications, from simple devices such as wristwatches to the most complex computer systems. Integrated circuits rely on a variety of clock signals to ensure proper circuit performance, but timing closure is becoming more difficult with the latest technologies like 65-nanometer integrated circuit design. There is an additional challenge for the circuit designer in constructing clock circuits that use reduced power. Low power circuits are becoming more prevalent due to power consumption problems. In particular, power dissipation has become a limiting factor for the yield of high-performance circuit designs (operating at frequencies around 1 gigahertz or more) fabricated in deep submicron technologies. Clock nets can contribute up to 50% of the total active power in multi-GHz designs. Low power designs are also preferable since they exhibit less power supply noise and provide better tolerance with regard to manufacturing variations.
A typical clock control system has a pulsed clock generation circuit (e.g., a phase-lock loop) that generates a master clock signal. The master clock signal is fed to a clock distribution network that renders synchronized global clock signals at clock distribution structures such as local clock buffers (LCBs). Each LCB adjusts the global clock duty cycle and edges to meet the requirements of respective circuit elements, for example, local logic circuits, latches or memory arrays. In the example of static, random-access memory (SRAM) control, the LCB first generates a local clock signal, and a delayed local clock signal is obtained by delaying and extending the pulse width of the local clock signal using inverter chains. The local clock signal and delayed local clock signal are buffered to generate wordline, precharge and latching signals for the array of memory storage elements. The most critical timing component in the SRAM control is the local clock signal pulse width which determines SRAM read and write time windows.
Since these pulsed clocks are not changing with frequency, several programmable settings can be provided for the pulsed-clock generation circuitry to allow for pulsewidth modulation so that the hardware can have a better chance at satisfactory operation if the default pulsed clock was inadequate due to design error, model-to-hardware differences, etc. Pulsewidth modulation (PWM) is also useful for margin testing in the hardware—shrinking or expanding the pulsewidth from the default width provides an indication of design robustness. However, the capability of programmable settings adds unwanted overhead to the circuit design, as illustrated in FIGS. 1A and 1B.
FIG. 1A shows a prior art programmable PWM circuit 10 that may be used for array clock generation. An input line (clock signal) is connected to an inverter 12 formed by a p-type field-effect transistor (PFET) 14 and an n-type field-effect transistor (NFET) 16. The drain of PFET 14 is connected to the circuit power supply (Vdd), the source of PFET 14 is connected to the drain of NFET 16, and the drain of NFET 16 is connected to electrical ground. The input line controls the gates of PFET 14 and NFET 16, so the signal value at the node between these two transistors is the complement of the input line. This node is further connected to another inverter 18 formed by a PFET 20 and an NFET 22. The drain of PFET 20 is again connected to the circuit power supply, the source of PFET 20 is connected to the drain of NFET 22, and the drain of NFET 22 is connected to a plurality of programmable paths that lead to electrical ground connections 24a, 24b, 24c. The node between PFET 20 and NFET 22 (i.e., the output of inverter 58) is connected to an output line of PWM circuit 10. The output line is also connected to a default path through NFET 22 leading to electrical ground connection 26.
The pulse width of the output signal is modulated by selecting one of the programmable paths, or just the default path, to control the pulldown rate, i.e., the speed at which the output line is brought to electrical ground. The pulldown rate is determined by the minimum number of NFETs along the available paths to ground. The programmable path to ground connection 24a passes through NFET 28a with no interconnecting transistor, so this path has a total of two NFETs (including NFET 22). The programmable path to ground connection 24b passes through an interconnecting NFET 32a and through NFET 28b, so this path has a total of three NFETs. The programmable path to ground connection 24c passes through another interconnecting NFET 32b and through NFET 28c, so this path has a total of four NFETs. The default path to ground connection 26 through NFET 30 also has four NFETs.
Programmable bits PW0, PW1, PW2 control the gates of NFETs 24a, 24b, 24c, respectively, so the setting of the programmable bits determines the minimum number of NFETs in the pulldown stack to ground. If the setting is PW0=0, PW1=0 and PW2=0, then NFETs 24a, 24b, 24c will all be non-conducting and the only available path to ground is through the default path, having four NFETs. NFET 30 is relatively weak so the default path is effective only when all of the programmable paths are non-active. If PW0=0, PW1=0 and PW2=1, then only NFET 28c closes, providing an additional path to ground; there would still be a minimum of four NFETs in either of the two stacks but there is effectively a bigger NFET at the bottom of the stack since NFETs 28c and 30 are active and connected in parallel to ground. If PW0=0, PW1=1 and PW2=0, then only NFET 24b closes and there would be three NFETs in the minimum stack to ground. If PW0=1, PW1=0 and PW2=0, then only NFET 24a closes and there would be two NFETs in the minimum stack to ground. When there are more NFETs stacked in series along the ground path, the result is a slower pulldown rate; more NFETs connected in parallel results in a faster pulldown.
Programmable bits PW0 and PW1 are also used to control PFETs 34a and 34b which couple the power supply voltage to the interconnecting NFETs 32a, 32b through respective PFETs 36a, 36b. NFETs 32a, 32b and PFETs 36a, 36b are controlled by the output of inverter 12, to shut off the power supply voltage when PWM circuit 10 is pulling down the output line.
These four possible combinations of PW0, PW1, PW2 are encoded into two control bits a and b which are decoded using the decoder circuit 40 illustrated in the gate-level schematic of FIG. 1B. Decoder circuit 40 generates complements of the a and b signals using two inverters 42a, 42b. A first NOR gate 44a generates the PW0 bit from signal b and the complement of signal a. A second NOR gate 44b generates the PW1 bit from signals a and b. A third NOR gate 44c generates the PW2 bit from signal a and the complement of signal b. This construction results in the orthogonal generation of programmable bits PW0, PW1, PW2, i.e., it generates the programmable bits in such a manner as to result in four exclusive modulation values. The control bits a and b may for example be stored in general purpose timing registers (GPTRs).
The inclusion of an explicit (separable) decoder as part of the PWM circuit adds more devices to the circuit design and, hence, leads to more chip area and power consumption. The only alternative to the addition of a decoder structure is to provide the three programmable bits PW0-PW2 directly from the general purpose timing registers, but this alternative still requires the addition of one more GPTR bit. Also, the non-encoded signals utilized in such a case would lose the orthogonal attribute of a decoded structure. It would, therefore, be desirable to devise an improved PWM circuit which could provide efficient pulsewidth modulation with reduced or minimum control overhead to save chip area and power. It would be further advantageous if the circuit could still retain the orthogonal benefit of encoded control signals.
USPTO Backgrounds
USPTO Backgrounds