In the prior art, a traditional Phase Locked Loop (PLL) may produce a clock or several clocks synchronized to a reference clock. In many systems, a PLL is integrated onto an integrated circuit chip that also contains the system circuitry, such as a super IO chip for a floppy disk controller. In other applications, such as in data transmission, oftentimes receiving and decoding clocks are synchronized to a transmitting or system clock (e.g., an MPEG decoder chip). In any case, the greater the time required for synchronization, the less throughput produced by a given system.
FIG. 1 shows a traditional PLL 100 having a Phase-Frequency Detector (PFD) 120. The PLL 100 is a closed loop system wherein an clock output 150 is fed back to the PLL 100 and in turn results in a change in the clock output 150. In operation, the PFD 120 produces an output signal 180 in response to a reference clock 110 and a correcting signal 170 from a frequency divider (.div.N) 160. The output signal 180 is related to the phase error between the reference clock 110 and the correcting signal 170 and contains a difference frequency and a DC offset V.sub.i. The difference frequency is removed by a filter 130 and the DC offset V.sub.i is provided to a Voltage Controlled Oscillator (VCO) 140.
The DC offset V.sub.i causes the VCO 140 to produce the clock output 150. The frequency divider 160 receives the clock output and produces the correcting signal 170. The larger the difference between the reference clock 110 frequency and the clock output 150 frequency, the larger the correcting signal 170. The DC offset V.sub.i varies the frequency of the clock output 150 in the direction of the reference clock 110. When the clock output 150 frequency equals the frequency of the reference clock, the difference frequency becomes zero Hz and the VCO 140 locks to the reference clock 110. The response time for the VCO 140 to lock to the reference clock 110 may be adjusted by altering system parameters such as changing the N value of the frequency divider 160.
FIGS. 2A and 2B illustrate the effects of varying the response time for the PLL 100 to synchronize to a reference clock. FIG. 2A shows a case wherein the system parameters are selected to result in a slow rise time for the DC OFFSET V.sub.i. As shown, for a slow rise time t.sub.1 for the DC offset V.sub.i, there is a small damping prior to the DC offset voltage V.sub.i reaching a steady state.
FIG. 2B shows a case wherein the system parameters are selected to result in a fast rise time for the DC OFFSET V.sub.i. As shown, for a fast rise time t.sub.2 for the DC offset V.sub.i, there is a large damping prior to the DC offset voltage V.sub.i reaching a steady state. Consequently, in the prior art, a PLL having a PFD may synchronize the clock output to the reference clock either quickly with a larger damping, or slowly with less damping. The goal of a PLL system is to quickly synchronize to the reference clock with less damping. The quicker the PLL system becomes stable, the sooner the output clock may be used by a system. In addition, during the design of a PLL system, the longer the output clock takes to reach a steady state (e.g., oscillates), the more time required for simulating and developing the PLL system.
Logically therefore, the PLL that has a fast rise time and requires a larger damping is desirable. Yet, the large overshoot of the DC offset voltage V.sub.i may damage portions of the PLL 100 and may result in latch-up. The PLL 100 may be designed to handle the large voltage surges but as a consequence would utilize more chip surface area. This results in less chip surface area available for other circuit integration. In addition, a PLL having a fast rise with large damping consumes more peak power than a PLL having a slow rise time.
Other systems are known that can accelerate the time of the PLL to reach steady state with less damping. In one such system, a frequency detection counter (FDC) is incorporated in to the closed loop of the PLL. The FDC detects a frequency difference between the reference clock and a correcting signal. In addition, the FDC has a relatively fast response time for synchronizing to the frequency of the reference clock. However, when the PFD and the FDC are combined in a single closed loop system, the PFD and FDC tend to interfere with each other. Consequently, this system may become unstable or may have difficulty reaching a steady state.
In another prior art system, U.S. Pat. No. 5,446,416 entitled "Time Acquisition System with Dual-Loop for Independent Frequency Phase Lock", utilizes a dual loop system comprised of a frequency lock loop (FLL) and an independent PLL. The FLL employs an FDC while the PLL employs a PFD.
In operation, when an output frequency of an output clock is outside a range of target output frequencies, the FLL operates to synchronize the frequency of the output clock to the reference clock. At this time, the PLL is not operating. When the output frequency is within the range of target output frequencies, the FLL stops operating and the PLL begins operating to correct the phase of the output clock. The problem with this system is that for a case where the reference clock signal drifts (e.g., changes frequency or phase) beyond the range of target output frequencies, the PLL will stop operating and the FLL will again begin operating. In a case wherein the reference clock continues to drift, both the PLL system and the FLL system will alternate between operating and not operating. Consequently, the alternating between the FLL and the PLL results in an unstable system.
To solve the above problems, a novel PLL accelerating system is hereby disclosed.
Consequently, it is an object of the present invention to provide a PLL that has both a fast response time to reach a steady state and has small damping.
Another object of the present invention is to provide a method for a frequency detection counter (FDC) to cooperate with a phase frequency detector (PFD) without resulting in an unstable system.
A further object of the present invention is to provide a self-stop FDC which can be used in a PLL system.
A still further object of the present invention is to provide an integrated circuit that requires relatively less chip surface area yet produces a quick stable PLL for frequency generation.
USPTO Backgrounds
USPTO Backgrounds