1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically to a semiconductor memory device having a high-speed read mode adopting a redundancy compensation system, in which data in a defective memory cell is compensated for without delay in access time in the high-speed read mode.
2. Description of the Related Art
Recently, as the operation of the microprocessor has become faster, faster-operating semiconductor memory devices have been strongly demanded. While faster usual random access is now being developed on one hand, a semiconductor memory device having a high-speed read mode referred to as the "page mode" is being developed on the other hand as described in, for example, Japanese Laid-Open Publication No. 8-63990.
In the page-mode read operation, a plurality of memory cells, the number of which corresponds to a plurality of addresses in the memory cell arrays in accordance with the column address and the row address in an input address, are simultaneously selected. Data in the selected plurality of memory cells is simultaneously read into a sensing amplifier as one-page data. When the address for the page mode is changed in the state where the one-page data has been read into the sensing amplifier, the cell data at the corresponding address is switched at a fast speed from the selected one-page data and sequentially output.
There are other read modes than the page mode, such as the burst mode, the serial mode, and the like. These modes are similar to the page mode in that groups of data are read at a high speed, and thus are included in the scope of the present invention.
FIG. 12 is a block diagram illustrating a conventional non-volatile memory operable in a page mode. Specifically, FIG. 12 illustrates a general configuration for performing the page-mode operation in a mask ROM (read-only memory in which stored data is set at the production stage). FIG. 13 shows a detailed configuration of a memory cell array included in a main memory of the mask ROM.
As shown in FIG. 12, a mask ROM 200 operable in a conventional page mode receives an address signal (A0 through A19) and outputs 16-bit output data DO. The mask ROM 200 has a main memory section 10 in which memory cells Mmijn are arranged in a matrix. The memory cells Mmijn are divided into memory cell arrays MA0, MA1, . . . MAm, . . . MA15, each corresponding to one bit of the output data DO. The memory cell arrays MA0 through MA15 respectively output read cell data DO0, DO1, . . . DOm, . . . DO15, each corresponding to one bit of the output data DO.
The mask ROM 200 includes a row selector for selecting memory cells of a row corresponding to the row address (A7 through A19) of the input address signal, and a column selector for selecting memory cells of a plurality of columns corresponding to the column address (A3 through A6) of the input address signal. The row selector includes an input buffer 11 for receiving the row address (A7 through A19), a pre-row decoder (PRD) 12 connected to an output of the input buffer 11, and an X decoder 13 for selecting a row in the memory cell arrays based on the output from the pre-row decoder 12. The column selector includes an input buffer 21 for receiving the column address (A3 through A6), a pre-column decoder (PCD) 22 connected to an output of the input buffer 21, and a Y decoder section 23 for selecting a plurality of columns in the main memory section 10 (memory cell arrays MA0 through MA15) based on the output from the pre-column decoder 22.
The Y decoder section 23 includes a plurality of Y decoders YD0, YD1, . . . YDm, . . . YD15 respectively corresponding to the memory cell arrays MA0 through MA15. Each of the Y decoders YD0 through YD15 outputs read cell data DmB0, DmB1, . . . DmBn, . . . DmB7 (m=0 through 15) as one-page data from the memory cells Mmij0, Mmij1, . . . Mmijn, . . . Mmij7 of a prescribed row of the plurality of columns simultaneously selected from each of the memory cell arrays MA0 through MA15.
The Y decoders YD0 through YD15 are respectively connected to sensing amplifier groups SAG0, SAG1, . . . SAGm, . . . SAG15 for sensing read cell data D0Bn through D15Bn (n: an integer from 0 through 7) from the memory cell arrays MA0 through MA15. The sensing amplifier groups SAG0 through SAG15 each include a plurality of (eight in this example) sensing amplifiers. The sensing amplifier groups SAG0, SAG1, . . . SAGm, . . . , SAG15 are respectively connected to selectors SLN0, SLN1, . . . SLNm, . . . SLN15 for selecting sense cell data D0Sn through D15Sn (n: an integer from 0 through 7) from the respective sensing amplifiers based on a sensing amplifier selection signal Pn (n: an integer from 0 through 7) which is based on an address (A0 through A2) for the page mode.
The sensing amplifier selection signal Pn (n=0 through 7) is supplied to the selectors SLN0 through SLN15 by a page mode decoder (PMD) 32, and the page-mode decoder 32 receives the in-page address (i.e., address for the page mode; A0 through A2) via an input buffer 31.
The selectors SLN0 through SLN15 are respectively connected to output circuits OUT0, OUT1, . . . OUTm, . . . OUT15. The output circuits OUT0 through OUT15 perform signal processing, such as amplification, of cell data D0 through D15 selected by the selectors SLN0 through SLN15, and output the resultant signals as output cell data DO0 through DO15.
Next, specific configurations of the memory cell array MAm and the Y decoder YDm will be described.
FIG. 13 shows a detailed configuration of the memory cell array MAm among the memory cell arrays MA0 through MA15 included in the main memory section 10, and FIG. 14 shows a detailed configuration of the Y decoder YDm among the Y decoders YD0 through YD15 included in the Y decoder section 23, as well as the memory cell array MAm.
As shown in FIGS. 13 and 14, the memory cell array MAm includes a plurality of memory cells Mmijn in a matrix of 128 (horizontal).times.8192 (vertical). The number 128 corresponds to 8 words.times.16 pages, and the number 8192 corresponds to 16 rows.times.512 banks. In the mask ROM 200, the memory cell array MAm is divided into a plurality of bank areas 10a. The bank areas 10a are arranged in a matrix of 512 (vertical).times.128 (horizontal). In each bank area 10a, 16 memory cells are arranged vertically. Rows of the plurality of bank areas 10a arranged horizontally (hereinafter, referred to as "bank rows") R1, R2, . . . Rk, . . . R512 are each provided with 16 word lines WL0 through WL15. Each word line WLi (i: an integer of 0 through 15) is connected to gates of transistors (memory transistors) included in the memory cells Mmijn (i: an integer of 0 through 15) in the corresponding bank area 10a.
Between each two bank areas 10a adjacent to each other horizontally, a sub ground line SG formed of a diffusion layer is provided common to both of the bank areas 10a. On the other side of each bank area 10a, sub bit lines SB0 and SB1 formed of a diffusion layer are provided in correspondence with the respective bank area 10a. A main ground line MG formed of a metal layer is provided common to each two adjacent vertical columns of the bank areas 10a. The sub ground line SG common to two horizontally adjacent bank areas 10a is connected to the main ground line MG via a ground-side bank selection transistor TB1. Main bit lines MB0 and MB1 are provided in correspondence with the respective vertical column of the two adjacent columns of the bank areas 10a. The sub bit lines SB0 and SB1 provided for the respective bank areas 10a are connected to the main bit lines MB0 and MB1 via a supply-side selection transistor TB0.
To gates of the bank selection transistors TB0 and TB1, bank selection lines BS0 and BS1 are respectively connected. The bank selection lines BS0 and BS1 and the word lines WL0 through WO15 are driven by the X decoder 13.
The main bit lines MB respectively corresponding to columns of a plurality of bank areas 10a arranged vertically (hereinafter, referred to as the "bank columns") C1, C2, . . . Cr, . . . C128 are divided into groups. Each group includes 16 adjacent main bit lines MB corresponding to 16 adjacent bank columns. The first through 16th bit lines MBj (j: an integer of 0 through 15) of each group are connected to output terminals Y0, Y1, . . . , Yn, . . . Y7 of the Y decoder (the output terminals Y0, Y1, Yn, . . . Y7 corresponds to the group) via column selection transistors TC0, TC1, . . . TCj, . . . TC15 of the Y decoder (FIG. 14). To gates of the column selection transistors TC0 through TC15, column selection lines CS0 through CS15 are respectively connected. The column selection lines CS0 through CS15 are driven by the pre-column decoder 22.
According to the above-described configuration, when prescribed bank selection lines BS0 and BS1 and a prescribed word line WLi are selected by the X decoder 13 based on the row address (A7 through A19), a prescribed bank row Rk is selected, and also the memory cells in a prescribed bank row Rk in each of the bank areas 10a belonging to the selected bank row Rk are selected. Then, when a prescribed column selection line CSj is selected by the pre-column decoder 22 based on the column address (A3 through A6), a prescribed bit line MBj in each group is selected. In this manner, based on the row address (A7 through A19) and the column address (A3 through A6), data in the memory cells Mmij0 through Mmij7 in the memory cell array MAm is output as one-page data, namely, read cell data DmB0 through DmB7, from the Y decoder YDm to the sensing amplifier group SAGm.
In the above description, the detailed configurations of the memory cell array MAm and the Y decoder YDm corresponding to the memory cell array MAm are explained. The other memory cell arrays MA0, MA1, . . . and the Y decoders YD0, YD1, . . . corresponding thereto have the same configurations as those of the memory cell array MAm and the Y decoder YDm.
Hereinafter, the operation of the mask ROM 200 will be described.
FIG. 15 is a timing diagram illustrating the read operation in the page mode.
In the mask ROM 200, when input of an input address (A0 through A19) is determined at time t0, page data of page P(h) corresponding to a prescribed page address (h) is read to each of the sensing amplifier groups SAG0 through SAG15 as read cell data D0Bn through D15Bn (n=0 through 7). The data read from the memory cells in this case is performed in a usual random access mode as follows.
First, when the row address (A7 through A19) is determined, the bank selection lines BS0 and BS1 for selecting one of the bank rows Rk among the bank rows R1 through R512 and one word line WLi among the word lines WL0 through WL15 in the selected bank row Rk are driven by the X decoder 13. At this point, the bank selection lines BS0 and BS1 and the word line WLi become active ("high" level).
When the column address (A3 through A6) is determined, one column line CSj among the column lines CS0 through CS15 of each group is driven by the pre-column decoder 22, and the signal level of the one column line CSj becomes active ("high" level). The column selection transistor TCj which receives a signal from the column selection line CSj becomes "ON".
The memory cells Mmij0, Mmij1, . . . Mmij7 (m=0 through 15) in the selected row and bank columns are selected in each memory cell array, and the cell data in each memory cell is input to the sensing amplifier groups SAG0 through SAG15 via the column selection transistors TCj.
Next, at time t1, sensing amplifier outputs DmS0, DmS1, . . . DmS7 (m=0 through 15) from the sensing amplifier groups SAG0 through SAG15 (i.e., the sensing amplifier groups SAGm) are determined. Thus, the read of the page data PD(h) at address h designated by the address signal (A3 through A19) is completed.
Since only one of the output signals P0, P1, . . . , P7 from the page mode decoder 32 becomes active ("high" level) in accordance with the in-page address (A0 through A2), one of the sensing amplifier outputs DmSn among the sensing amplifier outputs DmS0 through DmS7 (m=0 through 15) from the corresponding sensing amplifier group SAGm (m=0 through 15) is selected by each selector SLNm (m=0 through 15). Thus, a first word W0 in the page data PD(h) at address h, i.e., data in the memory cell Mjij0 in the memory cell array MAm (m=0 through 15) corresponding to each data bit is output to the output circuit OUTm (m=0 through 15) corresponding to each bit. (time t2)
Then, when the in-page address (A0 through A2) starts changing at time t3, data in the sensing amplifier output DmSn (n=0 through 7) is sequentially selected by each selector SLNm. When the output signal (P0 through P7) from the page mode decoder 32 is determined at time t4, a second word W1 in the page data PD(h) at address h, i,e., data in the memory cell Mmij1 in the memory cell array MAm (m=0 through 15) corresponding to each data bit is output to the output terminal DOm of each output circuit OUTm.
After that, each time the in-page address (A0 through A2) changes and the sensing amplifier selecting signal (P0 through P7) from the page mode decoder 32 is determined, a third word W2 through an eighth word W7 in the page data PD(h) at address h are sequentially output to the output terminal DOm of each output circuit OUTm.
As described above, after the page data is determined by random access and the first word of the page data is determined, when a prescribed time period has passed since the start of the change in the in-page address signal (A0 through A2), the mask ROM 200 goes into the page mode allowing the high-speed read. Thus, the data in the memory cell is output at a high speed.
Then, when the page address (A3 through A19) changes, page data PD(h+1) at address (h+1) is read to the sensing amplifier groups SAG0 through SAG15 again in the random access mode. After the first word in the page data PD(h+1) is determined, the mask ROM 200 goes into the page mode allowing the high-speed read. Thus, the data in the memory cell is output at a high speed.
As described above, when a page designating address signal, i.e., an inter-page address signal (A3 through A19) changes, determination of the data to be sent to the output terminal DOm (m=0 through 15) requires determination of the main bit line, an output of the sensing amplifier group, and an output of the selector. By contrast, when a word designation address signal, i.e., the in-page address (A0 through A2) changes, the data to be sent to the output terminal DOm is determined only after the time period required to switch the selector SLNm.
Accordingly, the mask ROM operable in the page mode allows high-speed read with respect to a change in the in-page address, thus realizing a high-speed read operation.
In the field of read-only memories, such as mask ROMs, a redundancy compensation system has already been developed in order to improve the production yield. Japanese Laid-Open Publication No. 6-76591, for example, discloses a mask ROM adopting a redundancy compensation system.
Such a mask ROM includes a redundant memory cell group having rewritable data memory devices, and a replacement address storage section having address memory devices for addresses into which the address of a defective memory cell group including a defective bit can be written. The address of the defective memory cell group is stored in the replacement address storage section, and thus the defective memory cell group is replaced with a redundant memory cell group.
FIG. 16 is a block diagram illustrating a conventional non-volatile memory adopting the above-described redundancy compensation system. Specifically, FIG. 16 illustrates a general configuration of such a read-only memory (mask ROM). FIG. 17 shows a detailed configuration of a memory cell array included in a main memory of the mask ROM.
In FIG. 16, reference numeral 300 denotes a mask ROM adopting a conventional redundancy compensation system. Identical elements previously discussed with respect to FIGS. 12 through 14 will bear identical reference numerals therewith and the descriptions thereof will be omitted. As the mask ROM 200 operable in the conventional page mode, the mask ROM 300 receives an address signal (A0 through A19) and outputs 16-bit output data DO. The mask ROM 300 has a main memory section 10 having the same configuration as in the mask ROM 200.
As shown in FIG. 17, the memory cell array MAm has the same configuration as in the mask ROM 200. Briefly, the memory cell array MAm includes a plurality of memory cells Mmit in a matrix of 128 (horizontal).times.8192 (vertical). The number 128 corresponds to 8 words.times.16 pages, and the number 8192 corresponds to 16 rows.times.512 banks. The memory cell array MAm is divided into a plurality of bank areas 10a. The bank areas 10a are arranged in a matrix of 512 (vertical).times.128 (horizontal). In each bank area 10a, 16 memory cells are arranged vertically.
The mask ROM 300 adopting the redundancy compensation system includes a redundant circuit section 300a for storing data to be stored in place of the defective memory cell group including a defective bit, in addition to the main memory section 10.
The redundant circuit section 300a stores replacement cell data, treating each bank area 10a as a unit (bank area by bank area). The redundant circuit section 300a includes a replacement bank address storage section 310 for storing the address of the bank area 10a including the defective memory cell to be replaced, a replacement cell data memory section 320 which can store pieces of data, the number of which corresponds to the number of memory cells included in the bank area 10a to be replaced, and a replacement bit designation storage section 330 for storing replacement bit designation data which designates the bit to be replaced among the sense cell data from the sensing amplifier corresponding to each bit.
The mask ROM 300 includes a row selection device including an input buffer 11, a pre-row decoder 12 and an X decoder 13 having the same configurations as in the mask ROM 200.
The mask ROM 300 includes a column selection device for selecting memory cells of a plurality of columns corresponding to the column address (A0 through A6) of an input address signal. The column selection device includes an input buffer 21a for receiving the column address (A0 through A6), a pre-column decoder (PCD) 22a connected to an output of the input buffer 21a, and a Y decoder section 23a for selecting a plurality of columns (corresponding to 16 bits) in the main memory section 10 (memory cell arrays MA0 through MA15) based on the output from the pre-column decoder 22a.
The Y decoder section 23a includes a plurality of Y decoders Yd0, Yd1, . . . Ydm, . . . Yd15 respectively corresponding to the memory cell arrays MA0 through MA15. From each of the Y decoders Yd0 through Yd15, read cell data Dmb (m: an integer of 0 through 15) from the memory cell Mmit of a prescribed row ("i"th row) of one column selected in each of the memory cell arrays MA0 through MA15 is output as output data corresponding to each bit.
The Y decoders Yd0 through Yd15 are respectively connected to sensing amplifiers SA0, SA1, . . . SAm, . . . SA15 for sensing read cell data D0b through D15b from the memory cell arrays MA0 through MA15. The sensing amplifiers SA0 through SA15 are respectively connected to selectors SL0, SL1, . . . SLm, . . . SL15 for selecting either one of sense cell data MDAT0 through MDAT15 from the respective sensing amplifiers SA0 through SA15 or the replacement cell data RDAT from the redundant circuit section 300a, based on the replacement bit designation data.
The selectors SL0 through SL15 are respectively connected to output circuits OUT0, OUT1, . . . OUTm, . . . OUT15 (hereinafter, referred to also as "output circuits" OUT0 through OUT15). The output circuits OUT0 through OUT15 perform signal processing, such as amplification, of cell data D0 through D15 selected by the selectors SL0 through SL15, and output the resultant signals as output cell data DO0 through D015.
Hereinafter, the operation of the mask ROM 300 will be described.
The mask ROM 300 adopting the redundancy compensation system operates in the following manner in the case where a defective memory cell is included in a prescribed bank area in a prescribed memory cell array MAm.
First, the bank address (A0 through A6, A11 through A19) for designating the bank area including the defective memory cell to be replaced is stored in the replacement bank address storage section 310. The replacement bit designation data (D0 through D15) representing the bit of the 16-bit data which corresponds to the memory cell array including the defective memory cell is stored in the replacement bit designation storage section 330. Data to be stored in each memory cell in the defective bank area is stored in the replacement cell data memory section 320 in accordance with the address (A7 through A10) corresponding to the position in the bank area.
When prescribed bank selection lines BS0 and BS1 become active based on the row address (A7 through A19) of the input address signal at the time of reading data in the mask ROM 300, bank selection transistors TB0 and TB1 in each of the bank areas of a prescribed bank row Rk become conductive. Thus, the source and the drain of the memory transistor in each of the memory cells Mmit in each of the bank areas belonging to the bank row Rk are connected to main bit lines MB0 and MB1 and a main ground line MG via sub bit lines SB0 and SB1 and a sub ground line SG. Simultaneously, a prescribed word line WLi becomes active when the "i"th memory cell in each of the bank areas of the bank row Rk is selected.
When a main bit line corresponding to a prescribed bank column Cr (i.e., memory cell column) in each of the memory cell arrays MAm is selected by the Y decoder Ydm, information in the memory cell Mmit (t=r) selected in each of the memory cell arrays MAm is read as read cell data Dmb from each Y decoder Ydm to the sensing amplifier SAm corresponding to each bit.
In the case where there is no defective memory cell in the bank area selected in each memory cell array MAm, the sense cell data MDATm is selected by the selector SLm corresponding to each bit. The sense cell data MDATm is supplied as the selector output Dm to the output circuit OUTm corresponding to each bit and then output from the output circuit OUTm, the output data DOm as the cell data from the mask ROM 300.
By contrast, in the case where the input address externally provided matches the bank address stored in the replacement bank address storage section 310, the replacement cell data RDAT at the position corresponding to the word line which has become active among the data stored in the replacement cell data memory section 320 is read and supplied to each selector SLm. At this point, each selector SLm is supplied with replacement bit designation data by the replacement bit designation storage section 330. Accordingly, the selector SLm corresponding to the bit to be replaced replaces the cell data MDATm from the memory cell array MAm corresponding thereto with the replacement cell data RDAT and outputs the replacement cell data RDAT to the output circuit OUTm.
In order to enable replacement of any of m bits (0.ltoreq.m&lt;16) of the data D0 through D15 simultaneously read, the selector needs to have a configuration which enables switching of the cell data MDATm (m: an integer of 0 through 15) from each memory cell array MAm in the main memory section 10 and the replacement cell data RDAT. Accordingly, in order to enable data replacement of any of a plurality of bits, e.g., m-bit data, the selectors each are required to be a switching circuit with a plurality of inputs corresponding to (m+1) bits.
In a hierarchical memory cell array having a sub bit line corresponding to each bank area and a main bit line corresponding to each bank column, generation of one defect (e.g., one defective memory cell) in the memory cell array makes it difficult to read data from other memory cells in the bank area including the defective memory cell.
The defect can be efficiently compensated for by treating the memory cells connected to the sub bit line and the sub ground line in the bank area as one unit as described above.
In the above description, a NOR-type mask ROM is explained as the mask ROM. The same effect can be obtained for a NAND-type, i.e., vertical mask ROM by setting a bank area as a prescribed number of memory cells arranged vertically.
In the above-described read-only memory operable in the page mode, the output is determined only after the time period required for switching the selector since the page address changes during page access. Thus, a high-speed operation is possible. However, in the case where the redundant circuit system is adopted in the mask ROM operable in the page mode, read of redundant data requires access time to the redundant memory and also the operation time of the switching circuit. Such a time period is longer than the page access time. Therefore, when the data read from the redundant memory occurs during page access, the access timing is restricted.
In the case where a non-volatile memory operable in the high-speed access mode such as page mode includes a redundant circuit, delay in data access due to the read of the redundant data and data switching makes it difficult to shorten the access time.
USPTO Backgrounds
USPTO Backgrounds