1. Field of Invention
The present invention relates to the field of multiple-time programmable memory bitcells and array architectures.
2. Description of Related Art
Typical non-volatile memory architectures used in such devices as Erasable Programmable Read-Only Memory (EPROM) are often complicated and need complex drive and power circuitry.
Multiple-Time Programmable (MTP) memory bitcells comprising bi-stable cantilevers have been developed in order to reduce the drive and power circuitry required by large arrays of non-volatile memory. The bi-stability of the cantilever design is achieved by employing adhesion forces at the contacting surfaces of the activation electrodes positioned at either side of the cantilever. Once the cantilever is in contact with either of these activation electrodes, it will remain in this position until these adhesion forces are overcome by electrostatic pulling forces from the activation electrode located on the opposite side of the cantilever, at which point the cantilever moves towards this pulling electrode until it contacts this electrode. Such devices have advantages when compared to traditional semiconductor-based memory cells in that they can operate as non-volatile memories without the need for supporting power supplies.
However, such devices also have disadvantages in that control of their programming can be complicated. Moreover, the switching speeds of these bi-stable cantilevers will depend on the voltage being applied between the cantilever and one of two activation electrodes. A higher voltage will create a larger electrostatic force, thereby urging the cantilever towards the activation terminal more rapidly. When the cantilever contacts the activation terminal, a current will pass from the cantilever to the activation electrode. Accordingly, if the voltage applied to the activation electrode is high, the resulting current may also be high.
High current bridging the cantilever and the activation electrode can cause damage to the cantilever and/or the activation electrode. In some circumstances, the current can weld these two elements together such that further movement and programming is not possible, thereby effectively destroying the memory bitcell.
Accordingly, there is a clear need for a simple three-terminal multiple-times programmable memory bitcell and array architecture which prevents excessive current transfer between the cantilever and the activation electrodes whilst ensuring reliable operation.
USPTO Backgrounds
USPTO Backgrounds