Pulse width modulation (PWM) signals often are used for precise control of electronic devices, such as electric motors, light emitting diode (LED) backlights, and the like. In some systems, an input PWM signal is used to generate multiple PWM signals in parallel, and the multiple PWM signals are then used to drive one or more respective components. To illustrate, in LED display systems, each PWM signal of a set of parallel PWM signals is used to drive a separate set of LEDs connected in series. In generating multiple output PWM signals, it often is advantageous to synchronize the output PWM signals with the input PWM signal. To illustrate, in LED systems the input PWM signal often is synchronized with the display frame frequency, so a lack of synchronization between the output PWM signals and the input PWM signal can result in visual noise due to beating between the display frame frequency, the output PWM frequency, and their harmonics. Further, it can be advantageous to phase-shift the parallel output PWM signals in relation to each other to avoid or reduce undesirable effects, such as increased electromagnetic interference (EMI), large ripple in the power supply voltage when the components driven by the multiple PWM signals share the same power supply, and audible noise when the output PWM signals have a frequency in the human audible range (e.g., between approximately 0 Hz and 20 kHz). However, conventional systems typically utilize one or more phase-locked loops (PLLs) to generate multiple output PWM signals that are both synchronized with the input PWM signal and phase-shifted relative to each other. The use of these PLLs often substantially increases the cost and complexity of the system or introduces other undesirable effects. Further, the input PWM signal may have a relatively low frequency (e.g., as low as 100 Hz in a display system), thereby requiring a particularly complex PLL having a small loop bandwidth, which can result in a long locking time for the PLL, a relatively large silicon area to implement the PLL, and which may even require off-chip loop filtering and thus necessitate additional pins to interface with an-off chip filter. Accordingly, an improved technique for generating multiple phase-shifted PWM signals synchronized to an input PWM signal would be advantageous.
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