(1) Field of the Invention
The present invention relates to a superconducting system and a superconducting circuit chip and, more particularly, to a superconducting system for transmitting a signal outputted from a superconducting circuit to another circuit via an interface circuit and a superconducting circuit chip including such a superconducting circuit and interface circuit. Furthermore, this invention relates to a high-temperature superconducting junction device with a shunt resistor and, more particularly, to a high-temperature superconducting junction device with a shunt resistor for optimally driving a ramp-edge high-temperature superconducting junction included in a superconducting circuit.
(2) Description of the Related Art
Among superconducting circuits, single flux quantum (SFQ) circuits which operate with an SFQ pulse as an information carrier are characterized by ultrahigh speed and low energy. Accordingly, it is expected that these SFQ circuits will be components in future high-speed information processing systems. To build a high-speed information processing system using such an SFQ circuit, a superconducting system for taking a signal out of the SFQ circuit and for transmitting the signal at a high speed to a semiconductor device which is in an environment kept at room temperature must be developed. However, this SFQ circuit operates at a voltage of about several hundred microvolts, so it cannot drive the semiconductor device directly. Therefore, an interface circuit must be located between the SFQ circuit and the semiconductor device to amplify the signal taken out of the SFQ circuit to about several tens of millivolts so that the semiconductor device can be driven.
FIG. 19 shows an example of the structure of a conventional superconducting system in which a metal superconductor is used. A conventional superconducting system 100 includes a chip 101 on which an Nb superconducting circuit and an Nb latch interface circuit, for example, are formed. This chip 101 is located in an environment kept at a liquid helium temperature (4.2 K) by a refrigerator. The Nb superconducting circuit is an SFQ circuit having a Josephson junction formed by the use of Nb, being a metal superconductor. Like the Nb superconducting circuit, the Nb latch interface circuit is a latch driver as an interface circuit having a Josephson junction formed by the use of Nb. The Nb latch interface circuit is connected to a high-speed semiconductor amplifier 102 and the high-speed semiconductor amplifier 102 is connected to a semiconductor circuit 103. A signal in the Nb superconducting circuit usually has a voltage of about several hundred microvolts and the Nb superconducting circuit should be connected to a comparatively high-speed and high input sensitivity semiconductor amplifier. Accordingly, a semiconductor circuit, such as a GaAs heterojunction bipolar transistor (HBT) which can operate at an input voltage of 6 mV at a speed of 10 Gbps, will be used as the high-speed semiconductor amplifier 102.
Techniques for fabricating a superconducting circuit included in such a superconducting system have advanced. An Nb superconducting circuit having several thousands of junctions has already been fabricated on an experimental basis.
Moreover, an attempt to use an oxide high-temperature superconductor, such as YBaCuO, which produces a superconductive phenomenon even at a higher temperature in a superconducting system in place of a metal superconductor like the one described above has been made. In this case, a superconducting circuit and an interface circuit included in a superconducting system include Josephson junctions formed by the use of an oxide high-temperature superconductor (see, for example, Japanese Unexamined Patent Publication No. 2000-353831). Oxide high-temperature superconductors represented by yttrium-based superconductors go into a superconductive state at temperatures higher than the liquid helium temperature, so in recent years cooling mechanisms have been simplified compared with conventional metal superconductors which involve cooling by liquid helium. Accordingly, it is expected that such oxide high-temperature superconductors will widely be applied to sensors, logic circuits, and the like.
In these oxide high-temperature superconductors, a superconducting current has the property of being able to flow along a Cu—O plane in a crystal made up of Cu and O, so a junction should cross in a direction parallel to this Cu—O plane. Accordingly, ramp-edge junctions have been proposed as superconducting junctions used in high-temperature superconducting devices. Such ramp-edge junctions are of two types (see, for example, Japanese Unexamined Patent Publication No. 2001-244511). With ramp-edge junctions of one type, a barrier layer is formed by a deposited film. With ramp-edge junctions of the other type, a barrier layer is formed by modifying the property of a surface by ion irradiation. A surface-modified ramp-edge junction will now be described with reference to FIG. 20.
FIG. 20A is a rough perspective view of a conventional surface-modified ramp-edge junction. First, a lower electrode 202 of La-doped YBCO (YBa2Cu3O7-x) and an insulating layer 203 of SrSnO3 which will be an interlayer dielectric are deposited in order on an MgO substrate 201 by pulse laser deposition. Then a resist pattern (not shown) is formed by coating resist and patterning (exposure and development). Ion milling is performed by irradiating with Ar ions with this resist pattern as a mask to form a ramp-edge structure.
Then the ramp-edge portion is irradiated again with Ar ions to form a damaged layer 204 as a barrier layer. An upper electrode 205 of YBCO is deposited by pulse laser deposition. After that, ion milling is performed to form a ramp climbing portion 206. As a result, the basic structure of a ramp-edge junction is completed.
FIG. 20B shows the volt-ampere characteristic of the ramp-edge junction. As shown in FIG. 20B, the ramp-edge junction exhibits an overdamp characteristic. That is to say, unlike an Nb superconducting junction which operates at a low temperature, hysteresis in the volt-ampere characteristic is sufficiently small.
Among superconducting circuits including such a ramp-edge junction, SFQ circuits have the property of operating at ultrahigh speeds with a small amount of energy. To design and fabricate an SFQ circuit with an oxide high-temperature superconductor, it is necessary to meet the condition that in a superconducting loop including a ramp-edge junction, or a Josephson junction, in the circuit, the product (L×Ic product) of the inductance L of the loop and a critical current Ic for the Josephson junction should be equal to one quantum flux Φ0 or Φ0/2.
In this case, if critical current density JC for the junction used in the SFQ circuit is increased, then the product (Ic·Rn product) of the critical current Ic and normal conduction resistance Rn increases. Therefore, it is said that the width of an SFQ pulse given by τ=Φ0/(Ic·Rn) (Φ0=2.07×10−15 wb) becomes narrower and that the SFQ circuit can operate at a higher speed.
As stated above, the hysteresis in the volt-ampere characteristic of the ramp-edge junction is sufficiently small, so the ramp-edge junction is used in an SFQ circuit without making any changes. Accordingly, no consideration has been given to the structure of a ramp-edge junction in which shunting is performed with a resistor.
By the way, if the Nb superconducting circuit (currently, techniques for fabricating Nb superconducting circuits are more advanced than techniques for fabricating superconducting circuits including an oxide high-temperature superconductor) and the Nb latch interface circuit (as an interface circuit between the Nb superconducting circuit and the semiconductor circuit) having a Josephson junction formed by the use of Nb are used for building a superconducting system, there is a limit to the operation speed of the superconducting system due to the punch through probability, CR time constant, etc., of the Josephson junction.
For example, current density for the Josephson junction formed by the use of Nb widely used at present is 2.5 kA/cm2. In this case, the operation speed of the Nb latch interface circuit is, at the most, about 8 Gbps due to the punch through. Consideration has been given to increasing the current density to 10 kA/cm2. However, even if this value is realized, the operation speed of the Nb latch interface circuit is, at the most, about 20 Gbps. If the high-speed semiconductor amplifier operates at a speed of 40 Gbps, high operation speeds of the Nb superconducting circuit and the semiconductor circuit will be limited by this Nb latch interface circuit.
As described above, the performance of the Nb latch interface circuit is not yet adequate enough to serve as an interface circuit between the Nb superconducting circuit and a semiconductor circuit. It is hoped that an interface circuit capable of making the best use of not only high operation speeds of Nb superconducting circuits including a large number of Josephson junctions but also high operation speeds of semiconductor circuits will be developed.
As stated above, with a superconducting system in which an oxide high-temperature superconductor is used, it is said that in a ramp-edge type SFQ circuit fabricated by the use of the oxide high-temperature superconductor, an increase in critical current density Jc for the ramp-edge junction will lead to a decrease in the width of an SFQ pulse and that the SFQ circuit can operate at a high speed. According to a further study by the present inventor, however, an increase in the critical current density Jc leads to a significant increase in the hysteresis. Such an increase in the hysteresis tends to decrease a bias margin for the SFQ circuit. When the hysteresis exceeds 10%, it is difficult for the SFQ circuit to operate. If the SFQ circuit is complex, it cannot operate.
FIG. 21 is a view for describing the dependence of an Ic−Rn product and hysteresis for a conventional high-temperature superconducting ramp-edge junction on critical current density Jc. An Ic−Rn product is proportional to the 0.3rd power of the critical current density Jc (Ic×Rn∝Jc0.3). The McCumber parameter βc, being one of the parameters indicative of the hysteresis, is expressed by the following formula (1). That is to say, an increase in the critical current density Jc leads to a steep increase in the hysteresis.βc∝Jc0.3/[ln(a)−ln(Jc)]  (1)
where ln means a logarithm, and a is a physical quantity including the barrier height of the junction and is expressed by the following formula (2).a=(4π∈0∈r/h)×(2mΦ)1/2  (2)
where ∈r is a barrier relative dielectric constant, ∈0 is the permittivity of free space, h is plank's constant, m is the mass of an electron, and φ is the barrier height.
USPTO Backgrounds
USPTO Backgrounds