1. Field of the Invention
This invention relates to Wireless Baseband Processors (Baseband Decoder) and Forward Error-Correction (FEC) Codes for 3rd Generation (3G) Wireless Mobile Communications. More particularly, the invention relates to a very high speed Turbo Codes Decoder implementing diversity processing and pipelined Max Log-MAP decoders for 3G Code Division Multiple Access (CDMA2000) and 3G Wideband Code Division Multiple Access (WCDMA).
2. Description of Prior Art
Diversity processing computes signals from two or more separate antennas using so-called “multipath” signals that arrive at the terminal via different routes after being reflected from buildings, trees or hills. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to deliver data rates up to 2 Mbit/s.
Turbo Codes decoding is based upon the classic forward error correction concepts that include the use of concatenated Decoders and Interleavers to reduce Eb/N0 for power-limited wireless applications such as digital 3G Wireless Mobile Communications.
A Turbo Codes Decoder is an important part of baseband processor of the digital wireless communication Receiver, which was used to reconstruct the corrupted and noisy received data and to improve BER (10−6) throughput. FIG. 1 shows an example of a diversity processing 3G Receiver with a Turbo Codes Decoder 13 which decodes data RXDa and RXDb from Demodulators 11 and Soft Decoders 12, and sends decoded data to the Media Access Control (MAC) layer 14. The data from the two or more received data paths pass through two or more diversity antennas, two or more Demodulators 11, and two or more Soft Decoders 12 to produce soft decoded data RXDa and RXDb for the Turbo Codes Decoder 13.
A widely used Forward Error Correction (FEC) scheme is the Viterbi Algorithm Decoder in both wired and wireless applications. A drawback of the Viterbi Algorithm Decoder is that it requires a long wait for decisions until the whole sequence has been received. A delay of six times the memory processing speed of the received data is required for decoding. One of the more effective FEC schemes, with higher complexity, uses a maximum a posteriori (MAP) algorithm to decode received messages. The MAP algorithm is computationally complex, requiring many multiplications and additions per bit to compute the posteriori probability. A major difficulty with the use of the MAP algorithm has been the implementation in semiconductor ASIC devices. The complexity of the multiplications and additions slow down the decoding process and reduce the throughput data rates. Furthermore, even under the best conditions, multiplication operations in the MAP algorithm require implementation using large circuits in the ASIC. The result is costly design and low performance in bit rates throughput.
Recently, the 3rd Generation Partnership Project (3GPP) organization introduced a new class of error correction codes using parallel concatenated codes (PCCC) that include the use of the classic recursive systematic constituent (RSC) Encoders and Interleavers as shown in FIG. 2. An example of the 3GPP Turbo Codes PCCC with 8-states and rate ⅓ is shown in FIG. 2. Data enters the two systematic encoders 31 and 33 separated by an interleaver 32. An output codeword consists of the source data bit followed by the output bits of the two encoders.
Other prior work relating to error correction codes was performed by Berrou et al., describing parallel concatenated codes which are complex encoding structures that are not suitable for portable wireless device. Another U.S. Pat. No. 6,023,783 to Divsalar et al. describes an improved encoding method over Berrou et al., using mathematical concepts of parallel concatenated codes. However, patents by Berrou et al., Divsalar et al., and others only describe the concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects, but are not feasible, economical, and suitable for consumer portable wireless devices. In these prior systems, the encoding of data is simple and can be easily implemented with a few xor and flip-flop logic gates. But decoding the Turbo Codes is much more difficult to implement in ASIC or software. The prior art describes briefly the implementation of the Turbo Codes Decoder which are mostly for deep space communications and requires much more hardware, power consumption and costs.
All the prior art Turbo Codes fail to provide simple and suitable methods and architectures for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices, including the features of high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environments.
USPTO Backgrounds
USPTO Backgrounds