Japanese Patent Application Laid-Open Publication No. 2009-49087 (Patent Document 1) discloses a configuration in which a plurality of substrates are laminated and warpage deformation of the substrates is cancelled by providing a stepped portion at an end portion of each substrate.
Also, Japanese Patent Application Laid-Open Publication No. 2004-165328 (Patent Document 2) discloses that a volume of a solder bump is changed in accordance with a height of an electronic component mounting portion as a method of mounting an electronic component on a warped insulating substrate.
Also, Japanese Patent Application Laid-Open Publication No. 2005-340393 (Patent Document 3) discloses that when a semiconductor chip is mounted on a warped circuit substrate, a plurality of stud bumps provided on the circuit substrate are deformed to electrically connect a plurality of electrodes of the semiconductor chip to the plurality of stud bumps.
USPTO Backgrounds
USPTO Backgrounds