1. Technical Field
The present disclosure relates to semiconductor devices, such as semiconductor devices including fin structures composed of strained semiconductor materials.
2. Description of the Related Art
The dimensions of semiconductor field effect transistors (FETs) have been steadily shrinking over the last thirty years or so, as scaling to smaller dimensions leads to continuing device performance improvements. Planar FET devices typically have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate oxide. Current through the channel is controlled by applying voltage to the conducting gate. With conventional planar FET scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional geometries that will facilitate continued device performance improvements. One such class of device is a fin field effect transistor (finFET).
USPTO Backgrounds
USPTO Backgrounds