1. Field of the Invention
The present invention relates to SOI wafer techniques, and particularly relates to SOI wafer techniques which be made by SIMOX process in which oxygen ions are implanted into a silicon wafer and the resulting a buried oxide layer is formed in the silicon wafer, that is an SIMOX wafer techniques.
2. Description of the Related Art
There are some known methods for manufacturing SOI (Silicon on Insulator) wafers each including two silicon layers and an oxide layer, serving as an insulating layer, sandwiched therebetween. For example, U.S. Pat. No. 3,036,619 and U.S. Pat. Nos. 5,930,643, 6,043,166, and 6090689 each disclose a SIMOX (Separation-by-Implanted-Oxygen) process in which oxygen ions are implanted into a silicon wafer and the resulting silicon wafer is annealed at a predetermined temperature such that a layer referred to as a BOX (Buried Oxide) layer or an insulating layer is formed in the silicon wafer. Also, for example, Japanese Patent No. 3031904 and U.S. Pat. No. 5,374,564 each disclose a bonding process in which an oxide layer is formed on a first silicon wafer and then bonded to a second silicon wafer and the thickness of the first silicon wafer is reduced to a predetermined value.
An oxide layer is partly exposed from an end region of an SOI wafer manufactured by the known SIMOX process or the bonding process. Therefore, if the SOI wafer is cleaned with a hydrofluoric acid solution during the manufacture of electronic devices and the like, an exposed portion of the oxide layer is dissolved in the solution, whereby silicon layers separated by the oxide layer are peeled off from the oxide layer. This causes a reduction in the yield of the electronic devices. Hence, the oxide layer must be prevented from being exposed from the SOI wafer.
However, a side face of an oxide layer is usually exposed from an SOI wafer manufactured by the bonding process as disclosed in Japanese Patent No. 3031904 and U.S. Pat. No. 5,374,564. Therefore, it is difficult to prevent the exposure of the oxide layer.
On the other hand, for the SIMOX process, Japanese Unexamined Patent Application Publication No. 2001-308025 discloses a technique for preventing the exposure of a buried oxide layer from a SOI wafer. In the technique, oxygen ions are implanted into the SOI wafer in such a manner that end regions of the SOI wafer is covered with a mask such that the oxygen ions are not implanted into the covered end regions, whereby the buried oxide layer is prevented from extending to end regions of the SOI wafer.
USPTO Backgrounds
USPTO Backgrounds