1. Field of Invention
The present invention relates generally to methods for debugging a program on a processor, and more particularly to a method by which a host processor can control the execution of a tightly coupled target processor such that the target processor executes one instruction at a time, with the host processor being capable of inspecting target processor information between each instruction.
2. Description of the Prior Art
When a new program is written it is desirable to determine that it operates correctly. One way to ensure that a new program operates correctly is by setting a breakpoint at a known place in the program. Conditions are then set up so that the program will execute on the processor at normal speed until it encounters the breakpoint and stops. Once the execution stops, the user can observe important information in the program for correctness. Another way to help ensure that the program operates correctly and which allows more information to be collected about the operation of the program, is to allow a single instruction at a time to execute on the target processor. This practice of single-stepping the program allows the user to move slowly through the program flow observing the effects on system resources and locating bugs and errors that cannot be easily observed during full speed execution of the program. Using both breakpointing and single-stepping, the user can observe much about what the program is doing and take corrective steps if the program makes an error.
One kind of support for these modes of debugging has been to employ a host processor system to help in the debugging process of a program on a processor called the target processor. The host processor system supplies the input and output devices needed by the programmer to debug the program on the target processor and an executive routine that operates independently of the single-stepping process. The executive typically allows the user to examine and display resources on a display device and waits for user feedback from an input device, such as a mouse or keyboard, to re-enter the single-stepping process for the next step.
In order for the host processing system to enable the programmer to set breakpoints and perform single-stepping operations, a special version of the target processor and a special interface between the host and target processors is many times necessary because many processors lack certain features in hardware which are required for these debugging methods. The special version of the target processor called a xe2x80x98bond-outxe2x80x99 chip provides the missing support for breakpointing and single-stepping the target processor. The xe2x80x98bond-outxe2x80x99 target processor usually resides in a pod and is connected via a large cable or umbilical cord to the target processor system in a way to make it appear that the target processor physically resides in the target processor system. The special interface circuitry between the host and the target processor also resides in the pod and allows the host to communicate with the target processor to set the target processor up for breakpointing and single stepping. The combined system is called an In-Circuit Emulator or xe2x80x9cICExe2x80x9d.
Typically ICEs are expensive, costing thousands of dollars and consuming significant physical space with umbilical cords often six feet long and book-size pods in which the bond-out chip resides.
Another problem encountered with ICE solutions occurs in the case of a network of closely connected processors. In such a network there can be a large number of processor units, each dedicated to a portion of a large execution task or job. An ICE for each processor in a such a case, would prove to be exorbitantly expensive and impracticable.
Finally, a problem commonly encountered occurs when the target processor executes a program that is fixed in a Read-Only Memory (ROM) device. In such a case, it is difficult to set breakpoints in the target processor program because doing so requires alteration of the target processor program, which is not a simple process if at all even possible depending on the type of ROM device used by the target processor.
Therefore, it is desirable to reduce the cost of an ICE for a single processor and mandatory if multiple processors are involved in a system. Simple economics demands a better solution to obtaining important information from target processor in a target system when running a program in real time.
One solution that works with very slow applications is to have the target processor execute an interpreter and have a simulator on the host processor execute the program to be debugged, but send to the target processor commands that affect the I/O subsystems related to the target processor. Referring to FIG. 1, after the target processor 110 on target system circuit board 120 performs the I/O operation, it reports back to the host 112 the results of the I/O operation over a dedicated communications link 130. The host 112 keeps track of all resources, including the I/O resources, and the target processor 110 controls and senses the states of signals in the target processor system 120. If the simulation speed is fast enough for the host processor to interact correctly with the target processor system, proper results are obtained. However, for most systems, such a scheme is far too slow to interact with devices surrounding the target processor.
Thus, given the expense of an ICE and the impracticability of using such a device in multiple processor cases and given the slow speed of other solutions, it is desirable to have a method for debugging one or more processors with the processors running at their normal execution speed even if executing from a ROM and without the expense of complex ICEs.
A system in which the above needs can be met includes a host processor connected to at least one target processor unit having a target processor, a code memory, a shared memory, and a shared control register. Both the host and target processor can access the code memory, shared memory and shared control register so that the host can load target processor programs into the code memory, and the host processor and target processor can pass information to each other and can set and reset control flags via the shared memory. In such a system, a method according to an embodiment of the present invention includes the target processor fetching and executing an instruction from a location in a code memory based on the current instruction pointer; the target processor testing a single-step flag in the shared memory after executing the instruction; if the single step flag is not set, the target processor continuing to execute instructions; if the single-step flag is set, the target processor copying the instruction pointer into a mailbox location in shared memory; the target processor interrupting the host processor; and the target processor stopping execution of instructions. In one embodiment the target processor is a processor related to the 8051 family of processors. In another system in which the above needs can be met the host processor is the same type of processor as the target processor, and the host processor system is tightly coupled to the target processor unit to allow chains of target processor units to be constructed. In yet another embodiment according to the present invention a method of controlling execution of a target processor unit embedded in a chain of like processor units includes the steps of a head processor in the chain sending single-step control information via the intervening processor units to the processor unit immediately adjacent to and preceding the target processor unit in the chain; the immediately adjacent processor acting as the host processor for the target processor by interpreting the single-step control information to set the single-step flag in the target processor""s shared memory; the target processor responding to the single-step flag in its shared memory to stop execution and copy its instruction pointer into its shared memory; the immediately adjacent processor receiving the host interrupt from the target processor and clearing the source of the interrupt; and the immediately adjacent processor sending the instruction pointer information back up the chain to the head processor in the chain.
USPTO Backgrounds
USPTO Backgrounds