1. Field
The present invention relates to semiconductor fabrication, and, more particularly, to systems and methods of manufacturing low etch pit density (EPD) group III-V wafers that can be used to manufacture devices, such as Heterostructure Bipolar Transistors (HBT) and pseudo-morphic High Electron Mobility (pHEMT) devices, as well as to wafers produced thereby.
2. Description of Related Information
It is well known in the group III-V/Gallium Arsenide (GaAs) industries that a etch pit density (EPD) level of a substrate is very important in minority carrier device reliability and in the yield of devices from the substrate. For example, regarding certain GaAs electronic devices, such as hetero-structure bipolar transistors (HBTs) and pseudomorphic high electron mobility transistors (pHEMTs), historically, substrate EPD is not known to be a determining factor in device yield. However, it is now known that dislocations may bear relation to at least certain device failure, for example HBT device failures, as recently shown by Low et. al. (Low, T. S. et al., The Role of Substrate Dislocations in Causing Infant Failures in High Complexity InGaP/GaAs HBT ICs, 2007). Furthermore, light point defects (LPDs) [also known as localized light scatterers (LLS) (see SEMI M54-0304—attached)] are undesirable for the subsequent steps, such as epitaxial growth, which are performed on the substrates. Of particular importance is the reduction of crystal “non-particulate” LPDs which may occur as a result of the arsenic precipitates in the grown ingots. For GaAs, these high LPDs typically originate as a result of the high arsenic overpressure used during the crystal growth of the ingots.
Wafer annealing is well known. In addition, ingot annealing is known as described in “Improved Uniformity of LEC Undoped Gallium Arsenide Produced by High Temperature Annealing” by Rumsby et al., GaAs IC Symposium, pp. 34-37 (1983).
Techniques for growing semiconductor crystals using a vertical gradient freeze (VGF) and carbon doping are known, such as those disclosed in U.S. Pat. No. 6,896,729 to Liu et al. It is desirable to provide systems and methods of manufacturing low etch pit density (EPD) GaAs and other III-V compound wafers, as well as the wafers themselves, using VGF and annealing techniques, and aspects consistent with the innovations herein relate to the provision thereof.
USPTO Backgrounds
USPTO Backgrounds