1. Field of Invention
This invention relates to semiconductor device packages, and more particularly to grid array packages using electrically conductive signal traces to form signal paths between bonding fingers and device terminals.
2. Description of Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device packages are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the chip to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. Mishandling can result in a loss of lead coplanarity, adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Unlike more conventional peripheral-terminal device packages, grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from the chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. A BGA device includes a chip mounted upon a larger substrate substantially made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AlN). Many BGA device packages have die areas dimensioned to receive integrated circuit chips and use established wire bonding techniques to electrically connect the I/O pads of the chips to corresponding flat metal "bonding fingers" adjacent to the die areas. During wire bonding, the I/O pads of the chip are electrically connected to corresponding set of bonding pads arranged in a two-dimensional array across the underside surface of the device package. Members of the set of bonding pads are coated with solder and function as device package terminals. The resulting solder balls on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. During PCB assembly, the solder balls are placed in physical contact with corresponding bonding pads of the PCB. The solder balls are then heated long enough for the solder to flow. When the solder cools, the bonding pads on the underside of the chip are electrically and mechanically coupled to the bonding pads of the PCB.
FIG. 1 is a top plan view of a typical BGA semiconductor device package 10. Semiconductor device package 10 includes a die area 12 dimensioned to receive an integrated circuit chip. Die area 12 is located substantially in the center of an upper surface of semiconductor device package 10. An underside surface of the integrated circuit chip is attached to semiconductor device package 10 within die area 12. The integrated circuit chip includes multiple input/output (I/O) pads arranged in rows about the periphery of an upper surface. Die area 12 is surrounded by a continuous ground ring 14 and a continuous power ring 16. Ground ring 14 is connected to an electrical ground potential at several points by vertical conductors (i.e., vias) 18, and power ring 16 is connected to a source of electrical power at several points by vias 20. Bonding fingers 22 of semiconductor device package 10 are arranged outside of power ring 16. Bonding wires are used to connect the I/O pads of the chip to ground ring 14, power ring 16, and corresponding bonding fingers 22. Electrically conductive signal traces connect bonding fingers 22 to bonding pads arranged upon an underside surface of semiconductor device package 10 with the help of vias. The bonding pads are coated with solder and function as device package terminals. For example, in FIG. 1, an electrically conductive signal trace 24 connects a bonding finger 26 to a via 28, and via 28 connects signal trace 24 to a solder-coated bonding pad on the underside surface of semiconductor device package 10.
Die area 12 is typically covered with a layer of an electrically conductive material (e.g., a flat metal sheet). The flat metal sheet is connected to ground ring 14 at multiple points by conductors 30. In addition, the flat metal sheet may be connected to dedicated grounding device package terminals by vias which extend from the flat metal plate on the upper surface to the device package terminals on the underside surface.
As greater levels of circuit integration cause an increase in the required numbers of bonding fingers and device package terminals, the routing of signal traces between bonding fingers 22 and device package terminals (e.g., solder-coated bonding pads) becomes more difficult. Two or more layers of signal traces may be required to route signals from bonding fingers 22 to the device package terminals. Additional signal layers make device packages more complex and expensive. In addition, more vias are necessary to connect signal traces on different levels. This presents a problem as signal traces have minimum width and spacing requirements, and must be routed between such vias.
It would be beneficial to have a semiconductor device package which includes additional bonding fingers and signal traces within an electrically conductive ring surrounding a die area for the routing of signals from I/O pads of an integrated circuit to device package terminals located on the underside surface. Such a semiconductor device package would greatly reduce the density of bonding fingers surrounding the conductive ring. In addition, the substantial amount of space typically existing between the conductive ring and the die area in a conventional device package would be better utilized, allowing the overall size of the semiconductor device package to be reduced. Such size reduction would be advantageous, especially in portable applications.
USPTO Backgrounds
USPTO Backgrounds