1. Field of the Invention
This invention relates to semiconductor fabrication processes, and more particularly, to a method of fabricating a semiconductor device with self-aligned silicide, which can help prevent the occurrence of junction leakage in the semiconductor device due to a downsizing of the line width of the semiconductor device and also help increase the anti-static capability of the semiconductor device against electro-static damage.
2. Description of Related Art
The self-aligned silicide (usually referred to as "salicide") process is customarily utilized in the fabrication of VLSI (very large-scale integration) integrated circuit with a line width less than 0.5 .mu.m (micrometer). A conventional method for fabricating a semiconductor device with self-aligned silicide is illustrated and described in the following with reference to FIGS. 1A through 1C.
Referring first to FIG. 1A, in the first step, a raw semiconductor wafer, such as a silicon substrate 10, is prepared. Over the substrate 10, a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor is formed, which includes a polysilicon gate 11, a pair of source/drain regions 12, and spacers 13. Subsequently, a metallization layer 14 is deposited over the entire top surface of the wafer to a thickness of from 200 .ANG.(angstrom) to 1,000 .ANG..
Referring next to FIG. 1B, in the subsequent step, the wafer is subjected to heat treatment, whereby part of the metal in the metallization layer 14 is reacted with the silicon in the source/drain regions 12 and the polysilicon in the gate 11, thus forming metal silicide 15 over the gate 11 and the source/drain regions 12.
Referring further to FIG. 1C, in the subsequent step, a selective wet-etching process is performed on the wafer so as to remove the unreacted part of the metal in the metallization layer 14. The remaining metal silicide layers 15 are the so-called self-aligned silicide.
Through the foregoing process, as illustrated in FIG. 1C, the resultant metal silicide layers 15 are separated away from the substrate 10 only by a thin portion of the source/drain regions 12, as indicated by the reference numeral 16.
As component size is downsized for increased integration, the length of the channel between the source and drain regions of the MOS transistors is correspondingly shortened. This allows an increase in the operating speed of the MOS transistors. However, there is still a limit to the channel length of the MOS transistors. When the channel is shortened to less than a certain length, the threshold voltage of the MOS transistors will be lowered to a level that causes the so-called short-channel effect. This effect is particularly evident in the thin portion 16 of the source/drain regions 12 that separates the metal silicide layers 15 from the substrate 10 illustrated in FIG. 1C. The shortened channel length will cause junction leakage current from the metal silicide layers 15 through this thin portion 16 of the source/drain regions 12 to the substrate 10.
Moreover, the shortened channel will allow some electrons near the junction between the channel and the drain to gain energy and thus become the so-called hot electrons. These hot electrons will then strike on other electrons, whereby increased number of electron-hole pairs are produced. This can cause the undesired effect of electrical breakdown and thus breakthrough, in the MOS transistors, which significantly affects the reliability and performance of the MOS transistors.
USPTO Backgrounds
USPTO Backgrounds