1. Field of the Invention
The present invention relates to a clock signal correction circuit and a semiconductor device implementing the same. More particularly, the present invention relates to a clock signal correction circuit which corrects duty cycle distortions of clock signals, and to a semiconductor device on which such a duty cycle correction circuit is integrated.
2. Description of the Related Art
Clock signal correction circuits are used to correct duty cycle distortions of a clock signal. FIG. 16 shows a typical configuration of such circuits. The illustrated clock signal correction circuit is composed of a frequency divider 10, a delay element array 11, a selector 12, and an exclusive OR (XOR) array 13. The frequency divider 10 divides the frequency of a given input clock signal by two, producing a divider output signal. The delay element array 11 consists of a plurality of delay elements connected in series to give a small delay, xcfx84 per stage, to the divider output signal. The resulting signals, referred to as xe2x80x9cdelay output signalsxe2x80x9d C(1) to C(m), are supplied to the selector 12. These signals C(1) to C(m) are intended to subdivide one half-cycle period of the divider output signal equally into n sections, so that the selector 12 will send them to the XOR array 13 as xe2x80x9cselector output signalsxe2x80x9d D(1) to D(m), enabling one of them. The XOR array 13 contains a plurality of XOR gates to perform an exclusive OR operation on the divider output signal and selector output signals D(1) to D(m).
To provide a clock signal with a desired duty ratio, the above conventional circuit operates as follows. The input clock signal is first directed to the frequency divider 10 to supply a half-rate divider output signal to the delay element array 11, selector 12, and XOR array 13. With its cascaded delay units, the delay element array 11 produces a plurality of delayed signals having successively larger delays with respect to the preceding signal. Such outputs of the delay elements are then supplied to the selector 12 as delay output signals C(1) to C(m). This means that one half cycle period of the divider output signal is evenly subdivided into n sections at fixed intervals of xcfx84. While those signals C(1) to C(m) are sent to the XOR array 13 as the selector output signals D(1) to D(m), the selector 12 enables only a particular signal selected from among D(1) to D(m) as desired. The XOR array 13 performs an exclusive OR operation on the divider output signal and selector output signals D(1) to D(m). During the high-level period of the divider output signal, the resultant signal becomes low when the enabled selector output signal is high, and high when the enabled selector output signal is low.
The above-described clock signal correction circuit can give a desired duty cycle to the input clock signal according to which selector output signal to enable. Such a conventional circuit, however, is not accurate enough, and not suitable for integration into a small device.
In view of the foregoing, an object of the present invention is to provide a clock signal correction circuit which is simple enough to be integrated into a small device, besides providing a highly accurate duty ratio. It is another object of the invention to provide a semiconductor device which implements such a clock signal correction circuit.
To accomplish the above objects, according to one aspect of the present invention, there is provided a clock signal correction circuit which corrects duty cycle distortions of an input clock signal. This circuit comprises the following elements: a frequency divider which divides the frequency of the input clock signal by a natural number n, thereby producing a divided clock signal; a phase detector which identifies the phase of the divided clock signal; a delay unit which produces a delayed divided clock signal by adding a delay to the divided clock signal according to the identified phase of the divided clock signal; and a logical operator which produces an output clock signal by performing a logical operation on the divided clock signal and delayed divided clock signal.
Further, according to another aspect of the present invention, there is provided a clock signal correction circuit which corrects duty cycle distortions of an input clock signal. This circuit comprises the following elements: an input circuit which receives a clock signal; a correction circuit which corrects duty cycle distortions of the received clock signal; an output circuit which outputs the clock signal with a duty cycle that is corrected by the correction circuit; and a notification circuit which notifies other circuits that the duty cycle of the received clock signal has been corrected.
Moreover, according to yet another aspect of the present invention, there is provided a semiconductor device on which a clock signal correction circuit is integrated to correct duty cycle distortions of an input clock signal. This clock signal correction circuit comprises the following elements: a frequency divider which divides the frequency of the input clock signal by a natural number n, thereby producing a divided clock signal; a phase detector which identifies the phase of the divided clock signal; a delay unit which produces a delayed divided clock signal by adding a delay to the divided clock signal according to the identified phase of the divided clock signal; and a logical operator which produces an output clock signal by performing a logical operation on the divided clock signal and delayed divided clock signal.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
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