1. Field of the Invention
The present invention relates to a memory cell implemented in complementary (e.g., CMOS) technology which can be independently accessed from two ports.
2. Description of the Prior Art
Conventional memory systems store binary information in memory cells, and access the cells in a standard sequence. After the addresses of the desired cell is supplied to the memory subsystem, the requested data is returned. There is typically one information path for writing information into each cell and one path for reading information out. These are often multiplexed into a single bidirectional path, producing what may be referred to as a "single port" memory.
Conventional single port memories are asynchronous internally. That is, the times for accessing a multiplicity of cells do not necessarily occur at fixed intervals. However, the memories usually require a synchronous interface between themselves and the bus structure on which they communicate with a variety of other hardware units. This synchronizing usually occurs through time slot multiplexing on a shared address or data bus. The net result is an apparent reduction in bandwidth to any individual request for memory data in comparison to the asynchronous speed of any individual memory. Furthermore, there are applications in which synchronization cannot be maintained efficiently. For these, system designers have resorted to component level subsystems that allow multiple access paths to the storage array without the attendant timing problems. Such memories that allow independent access of memory cells over multiple paths are referred to as "multiport" memories. The most common type is the dual port memory. Though not exhaustive, the subsystems employing multiport memories include video screen buffers, common system data bases, arithmetic unit data buffers, address translators, and various forms of caches.
Several manufacturers are now introducing monolithic memory devices specifically tailored to multiport requirements. These devices provide various schemes for resolving "contentions" that arise when two ports seek to access the same memory cell. One such dual port device uses independent channel demultiplexers and address decoders. Semaphore registers are provided to allow users to coordinate access to shared memory resources by handing messages back and forth.
First-in-first-out, FIFO, register files are another form of commercially available multi-port devices. One such dual port CMOS memory, adds a second n-channel access transistor pair in parallel with the conventional set of access devices. Both access paths can reach cells for reading and writing, so long as contention conditions are properly handled; see FIG. 1.
The third area of commercial monolithic multiport activity is with dynamic memory configured to have a parallel and serial access path. Based on a conventional NMOS dynamic random access memory (DRAM), they contain several internal shift registers to allow data access by random address or serial time slot. The memory can be read or written as a conventional DRAM by providing row and column addresses in the conventional multiplexed mode. With proper timing, the internal array row structure can be read to, or written from, shift registers that can then be clocked in or out at a much higher rate than conventional DRAM multiplexed address access methods allow.
USPTO Backgrounds
USPTO Backgrounds