1. Field of the Invention
The invention relates to a process of producing semiconductor components and integrated semiconductor circuits and somewhat more particularly to a process for gettering semiconductor components and integrated semiconductor circuits whose structures are produced in monocrystalline semiconductor material wafers.
2. Prior Art
Novel semiconductor components and/or integrated semiconductor circuit devices as presently used in electronics impose extreme requirements on reverse and leakage currents associated with such devices as well as on the minority life-times of such devices. In order to meet these requirements, so-called gettering steps are undertaken during the production of such semiconductor devices to extract impurities, for example, heavy metals, from the active areas of the devices and deposit them in other less critical areas.
Generally, gettering areas consisting of extensive dislocation networks are arranged on a surface (back side) of a semiconductor crystal wafer which is averted or opposite from the wafer surface which contains the active components. For example, J. electrochem. Soc.: Solid-State Science and Technology, Vol. 122, pages 1725-1729 (1975) suggests covering the rear sides of semiconductor crystal wafers with a phosphorous dopant layer so as to produce a dislocation network at such rear sides. Another prior art process is described in German Offenlegungsschrift 27 14 413 wherein a gettering layer in the form of a polycrystalline or amorphous semiconductor layer is produced on the rear side of monocrystalline semiconductor wafers.
It is apparent that the best effect of a getter layer would be achieved if the getter layer could be regenerated before each critical process step, i.e., high temperature processes, ion-implantation processes, etc. However, this is not possible with current semiconductor technology for commercial reasons and because of the controlled run-through of the individual masking and separation processes typically required to re-generate a layer on a semicondcutor wafer.
USPTO Backgrounds
USPTO Backgrounds