In semiconductor fabrication processes, the photo resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch. As feature sizes decrease to 20/22/14 nm and beyond, various methods are used to address the resolution issue. Particularly, double exposure techniques using two masks can circumvent the resolution limit.
Double exposure involves forming patterns on a single layer of a substrate using two different masks in succession. As a result, line spacing in the combined pattern can be reduced while maintaining good resolution. In a method referred to as double dipole lithography (DDL), the patterns to be formed on the layer are decomposed and formed on a first mask having only horizontal lines, and on a second mask having only vertical lines. The first and second masks are said to have 1-dimensional (1-D) patterns, which can be printed with existing lithographic tools.
Another form of double exposure is referred to as double patterning technology (DPT). Unlike the 1-D approach of DDL, DPT in some cases allows a vertex (angle) to be formed of a vertical segment and a horizontal segment on the same mask. Thus, DPT generally allows for greater reduction in overall IC layout than DDL does. DPT is a layout splitting method analogous to a two coloring problem for layout splitting in graph theory. In its simplest form, the two coloring problem is a way of coloring the vertices (or edge or face) of a graph such that no two adjacent vertices share the same color. Two adjacent vertices connected with an edge should be assigned different colors. Only two “color types” can be assigned. If a 2 color solution exists, the graph is said to be 2-colorable.
An IC layout includes multiple patterns on many layers. The distance between adjacent elements may be too small to be on the same mask, referred to herein as G0-space, but not so small to be beyond the process capability of the technology node. Each pattern on a layer is assigned a first or second “color”; the patterns of the first color are formed by a first mask, and the patterns of the second color are formed by a second mask. DPT is computationally intensive because IC layouts have many solutions and each solution has different consequences and is evaluated separately. Layouts that cannot be simply resolved into two masks, i.e. not 2-colorable, are solved by moving one or more patterns or resizing one or more patterns.
Design Rule Checker (DRC) software can systematically check design rules by showing all G0-spaces in a layout design. A designer would enter the necessary design rules, referred to as a deck, into the DRC using its design rule language, such as Standard Verification Rule Format (SVRF) or a software specific Tool Command Language (TCL). The design rules would specify the criteria for a particular spatial relationship to be a G0-space, such as corner-to-corner distance, end-to-end distance, or run-to-end distance. The DRC software would then take the layout input in a standard format, such as Graphic Data System II (GDSII), and produce an output that shows all the spatial relationships that are G0-spaces. Commonly used DRC software includes Calibre by Mentor Graphics; Hercules by Synopsys; Diva, Dracula, Assura, and PVS by Cadence Design Systems.
If a layout cannot be separated into two masks, the problem can be addressed by changing the layout design, usually one cell at a time. A cell contains a number of related patterns that forms a simple circuit having shared input and/or output. The layout design is usually changed manually by a designer reviewing the G0-space output from a DRC software. Changing a layout design is time-consuming for large cells, because a designer aims to minimize the total volume of a cell and a change often affects structures in other layers. Once the layout design is changed for the cell, the layout design is propagated to the entire chip as the cell is often used in multiple instances.
USPTO Backgrounds
USPTO Backgrounds