1. Technical Field
The present invention relates to semiconductor FETs (field effect transistors), and more specifically, to FETs with contact holes close to gates.
2. Related Art
During the fabrication of a typical FET (field effect transistor), after gate and source/drain (S/D) regions of the typical FET device are formed, a dielectric layer is deposited on top of the entire FET. Next, S/D contact holes are created in the dielectric layer and then filled with an electrically conducting material so as to provide electrical access to the S/D regions of the FET. As a result, to increase device density, there is a need for a transistor structure (and a method for forming the same) in which S/D contact holes are formed close to but electrically insulated from the gate of the transistor structure.
USPTO Backgrounds
USPTO Backgrounds