1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly to a structure of a stacked-gate nonvolatile semiconductor memory and method of manufacturing the same.
2. Description of the Related Art
A NAND-type flash memory is well known as one of nonvolatile semiconductor memories. Such the NAND-type flash memory comprises a semiconductor substrate on which memory cells and selection transistors are formed together with peripheral circuits required for memory operation. A memory cell may include a floating gate composed of conductive polysilicon formed on the semiconductor substrate with a gate insulator interposed, and a control gate composed of conductive polysilicon formed on the floating gate with an intergate insulator interposed.
On the other hand, the selection transistors and the transistors in the peripheral circuits are formed through process steps in accordance with formation of the memory cells. The transistors may include a lower gate composed of conductive polysilicon formed on the semiconductor substrate with the gate insulator interposed, and an upper gate composed of conductive polysilicon formed thereon with an insulator interposed.
In this way, the NAND-type flash memory comprises a stacked-gate nonvolatile semiconductor memory having a plurality of gates stacked with insulators interposed.
As for the selection transistors and the transistors in the peripheral circuits, it is required to cause an electrical short circuit between the upper gate and the lower gate in accordance with formation of memory cells such that they can serve as transistors. The electrical short circuit maybe caused with an aperture formed through part of the intergate insulator between the upper gate and the lower gate.
If the transistor has a gate length of 50 nm or below on the other hand, the gate resistance increases and causes problems associated with lack of the voltage applied to the gate and the signal speed delay. These problems may be solved by a full silicide structure including the entire gate silicided as proposed (see, for example, JP 2005-228868A).
Such the full silicide structure may be applied to the above-described stacked-gate nonvolatile semiconductor memory. In this case, together with fully siliciding the control gate, the upper gate of the selection transistor is also fully silicided. When the upper gate is fully silicided, metal atoms can diffuse into the lower gate via the aperture formed through the insulator between the upper gate and the lower gate, thereby siliciding part of the lower gate electrode as well.
If the lower gate electrode is progressively silicided to the gate insulator, the silicide contacts the gate insulator in some portions and the conductive polysilicon touches the gate insulator in other portions in mixture in the structure close to the gate insulator.
In that case, the operating characteristics of the transistor, such as the threshold of the selection transistor, may vary and make it difficult to keep stable transistor operation.
USPTO Backgrounds
USPTO Backgrounds