The present invention relates to a scan test circuit which can be suitably used as a scan test circuit that executes a delay fault test, for example.
In recent years, there is a tendency toward a reduction in the area and cost of semiconductor integrated circuits. To reduce the test time and percent defective which affect the cost, almost all types of semiconductor integrated circuits have been subjected a scan test for a delay fault. Modes for generating a test pattern for use in a scan test for a delay fault (hereinafter referred to as “delay fault test pattern”) include a broadside mode and a skewed-load mode. The delay fault test pattern is generally generated using the broadside mode in terms of ease of design. However, the broadside mode has a problem that the number of test patterns is relatively increased as compared with the skewed-load mode, and it is difficult to increase a delay fault coverage. For this reason, there is an increasing demand for reducing the number of delay fault test patterns and improving the test quality to reduce the test cost, by generating a delay fault test pattern using the skewed-load mode, though there are many restrictions in design in the skewed-load mode.
Japanese Unexamined Patent Application Publication No. 2008-096440 discloses a configuration in which one or more normal scan FFs are replaced with extended scan FFs in a scan chain including a plurality of normal scan FFs. Japanese Unexamined Patent Application Publication No. 2008-096440 also discloses a technique in which extended scan FFs are controlled in the skewed-load mode and normal scan FFs are controlled in the broadside mode. Assume herein that a component area occupied by the extended scan FFs is larger than a component area occupied by the normal scan FFs.
USPTO Backgrounds
USPTO Backgrounds