The present invention relates to an integrated circuit package in which signal wirings and ground planes (or ground meshes) are formed. And, the signal wirings or the ground planes alternate with laminal insulation layers.
For example, in high density multilayer wiring substrate, copper-polyimide multilayer part formed on a ceramic substrate is constituted by a plurality of laminal insulating layers of polyimide resin, and signal wirings, ground meshes, etc. are laminated alternatively with them. In order to improve the signal transfer characteristics, it is desired that impedance of the signal wirings formed inside such a multilayer part shall be matched with impedance of integrated circuit mounted on the substrate.
Conventionally, therefore, the mismatching of impedance of the signal wirings has been prevented from occurring by providing signal wirings between ground planes.
However, the present inventor found that comparatively large capacitance is generated between a conductor pad and a ground plane if the conductor pad having an inner size five or more times as large as the width of a signal wiring is provided on the top- or bottom-surface of a multilayer part, or inside the multilayer part so that the impedance of the signal wiring is lowered at the place in which this capacitance is generated.
That is, there has been a problem that the impedance of the signal wirings disposed within a region under/above a conductor pad are lowered locally, and as the result, the impedance mismatching occurs. On the other hand, if the inner size of the conductor pad is selected to be less than five folds of the width of a signal wiring lying within the region vertically under/above the conductor pad, the influence of capacitance between the pad and ground planes is small and therefore the disorder of impedance of the signal wirings is well small.
USPTO Backgrounds
USPTO Backgrounds