The present invention relates to a nonvolatile memory and a data processing device incorporating the same, specifically to a control method of the erase and write processing by applying a boosted voltage to nonvolatile memory cells, which is an effective technique for use in an IC (Integrated Circuit) card incorporating, for example, an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a CPU (Central Processing Unit) and so forth.
The EEPROM is widely used together with a logical unit such as a CPU, in a microcomputer for an IC card. The nonvolatile memory cell of the EEPROM is composed of a two-transistor unit including a memory MOS transistor that takes charge of storage and a selection MOS transistor that selects the concerned memory MOS transistor and takes out the information. The memory MOS transistor often adopts the MONOS structure. The memory MOS transistor is made up with a source, drain, insulated silicon nitride film, and control gate. To attain a state in which the threshold voltage of the memory cell is programmed to a comparably high voltage, namely, the write state, it is needed to capture electrons in the silicon nitride film by applying a supply voltage (Vcc), for example, 3V to the control gate, and a high voltage (xe2x88x92Vpp), for example, xe2x88x9210V to a well region (back gate). To attain a state in which the threshold voltage of the memory cell is programmed to a comparably low voltage, namely, the erase sate, it is needed to store holes in the silicon nitride film by applying high voltage (xe2x88x92Vpp), for example, xe2x88x9210V to the control gate, and the supply voltage (Vcc), for example, 3V to the well region. In a microcomputer for an IC card and the like, a booster to generate the above high voltage is built in on one chip, so that operational power supplies are unified into a single supply voltage.
In order to evaluate the performance of an electrically erasable and rewritable nonvolatile memory, the rewritable frequency and the data retention characteristic are used as the indicator of performance. The characteristic deterioration of the silicon nitride film and so forth due to repeated applications of the high voltage gives a limitation to the rewritable frequency. As the applications thereat of the high voltage become more precipitous, the electric stresses become severer, which further advances the characteristic deterioration, so that the rewritable frequency becomes still lower. On the other hand, as the application time of the high voltage in the erase and write processing becomes longer, the amount of electrons and holes to be captured becomes increased; accordingly, the data retention characteristic (characteristic of time during which data are held stably without mutations) becomes improved.
Therefore, in order to achieve a satisfactory rewritable frequency and better data retention characteristic, it is necessary to comparably slow the boosting speed of applying the high voltage and to comparably elongate the application time of the high voltage.
The inventor examined the measures to counter the application program described in the programming language such as the JAVA (registered trademark) or the like (hereunder, simply referred to as virtual machine program), where it was found that the shortening of the rewrite time to the EEPROM was very important. It is necessary to frequently rewrite multiple variables in the execution of the virtual machine program; here, the inventor considered that it would become necessary to appropriate the EEPROM to the temporary areas for manipulating the variables, in such an environment that cannot afford to plentifully use RAMs (Random Access Memory) as the work areas. The inventor further discovered that the use of the nonvolatile memory represented by the EEPROM as the temporary areas retains temporary information as it is even when the power supply is unexpectedly cut off to enable restarting the processing without requesting the host machine to resend necessary information.
The applicant of this invention has already applied for PCT/JP00/05860, which is not yet disclosed internationally. This application discloses the technique that controls the boosting speed of a booster in rewriting an EEPROM. Focusing on the erase processing, it is only needed to apply the high voltage (xe2x88x92Vpp) such as xe2x88x9210 Volts to the control gate of the memory cell to be erased, however the high voltage (xe2x88x92Vpp) for the memory cell to be erased is to be applied to the well region of the memory cells not to be erased that share the control gate line. Since the capacitances of the control gate and the well region are considerably different, provided that the number of bits to be written in parallel is different, the number of memory cells to be erased in parallel, which is executed beforehand, is also different; and accordingly, the driven load of the booster that supplies the high voltage is to vary. Such a change of the driven load leads to a change of the boosting speed, and produces a difference of voltage stresses to be given to the memory cells; inconsequence, significant electric stresses are accumulated in a part of the memory cells, and the rewritable frequency is anticipated to become abnormally insignificant. Accordingly, the above application by the applicant is to vary the frequency of the synchronous clock signal for the boosting operation in the booster according to the magnitude of the driven load, in a manner that the speed in the boosting operation becomes constant even if the number of memory cells to be erased in parallel varies.
An object of the present invention is to provide a technique relating to the nonvolatile memory to easily meet the mode of use that finds precedence in fast rewrite to the nonvolatile memory, and the mode of use that finds precedence in the data retention characteristic.
Another object of the invention is to provide a technique relating to the nonvolatile memory to easily meet the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.
The foregoing and other objects and the novel features of the invention will become apparent from the descriptions of this specification and the appended drawings thereof.
The typical disclosures of the invention will be summarized in brief as follows.
[1] According to one aspect of the invention, the nonvolatile memory is made capable of an information storage operation to nonvolatile memory cells by the erase and write processing through a boosted voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and includes a control means for the information storage operation. The control means is able to select a first information storage operation that requires a first time, and a second information storage operation that requires a second time shorter than the first time.
In the mode of use that finds precedence in fast rewrite to the nonvolatile memory, or the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, the control means selects the second information storage operation. In the mode of use that finds precedence in the data retention characteristic, the control means selects the first information storage operation.
Many cases find that the influence to the data retention characteristic by the erase and write processing is different. When the influence to the data retention characteristic is less in the erase processing time, it is more favorable in terms of reliability to gain the difference of the first time and second time by the time difference of the erase processing. When the influence to the data retention characteristic is less in the write processing time, it is needed to gain the difference of the first time and second time by the time difference of the write processing.
The foregoing nonvolatile memory facilitates to meet both of the mode of use that puts fast rewrite to precedence, and the mode of use that puts the data retention characteristic to precedence.
As a concrete mode of this invention, the erase processing time and write processing time each can be defined as the sum of the boosting operation time to gain the boosted voltage and the clamping operation time to maintain the boosted voltage. Or, the times may be defined as the claiming operation time. In the latter case, it is only needed to first detect the timing to reach the clamping voltage level, and to control the times of the erase processing and write processing, by using the timing as the starting point.
In another concrete mode of this invention, a register is provided which designates to select either the first information storage operation or the second information storage operation. Only a change of the set value of this register will easily change the selection of the first information storage operation or the second information storage operation. It becomes possible to arbitrarily change the selection according to the processing contents by the operation program of the CPU utilizing the nonvolatile memory and so forth.
The difference of the boosting speed of the voltages applied to the nonvolatile memory cells in the erase and write processing leads to the difference of the electric stresses given to the memory cells when the high voltage is applied. Since the electric stresses affect the rewritable frequency of the nonvolatile memory cells, the difference thereof effects the dispersion of secular characteristic deterioration. In order to prevent this sort of dispersion from occurring, it is needed to control the boosting speed of the voltages applied to the nonvolatile memory cells in the erase and write processing to be constant according to the magnitude of the load of the booster. For example, in the first information storage operation and the second information storage operation, the control means controls to regularize the boosting speed of the boosted voltage applied in the erase processing and/or write processing, regardless of the number of the nonvolatile memory cells to be erased in parallel and/or to be written in parallel.
As another concrete mode of this invention, the nonvolatile memory is able to adopt the MONOS structure that the nonvolatile memory cells possess an insulating charge trapping region between the channel and the control gate, and store different information according to the amount of the electrons or holes trapped in the charge trapping region. The minimum unit of the foregoing information storage operation is specified as a plurality of nonvolatile memory cells that share the well region. In the erase processing, for example, the supply voltage is applied to the well region of the objective nonvolatile memory cells, the boosted voltage is applied to the control gate line, and with regard to the nonvolatile memory cells of the non-selection of erase (inhibition of erase) that share the control gate line, the boosted voltage is applied to the well region thereof. The load of the booster differs depending on that the load is the control gate line or the well region, and the load driven by the booster varies according to the number of the objective memory cells of the erase processing.
As another concrete mode of this invention, the control means is able to select the clamping level of the boosted voltage. As the clamping level is heightened, the data retention characteristic is bettered according to the level. The withstand voltage of the circuit has to meet the maximum of the clamping level.
[2] According to another aspect of the invention, the IC card possesses a nonvolatile memory, which is made capable of an information storage operation to nonvolatile memory cells by the erase and write processing through a boosted voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and includes a control means for the information storage operation. The control means executes a selection control that selects an application interval of the boosted voltage applied during the information storage operation, and a boosting operation control that regularizes the boosting speed of the voltage applied from the start of boosting until the start of clamping.
By means of the selection control, the IC card satisfies both of the mode of use that finds precedence in fast rewrite to the nonvolatile memory, or finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. And, by means of the boosting operation control, the IC card is able to prevent the dispersion of the electric stresses given to the memory cells due to the difference of the boosting speed of the voltage applied to the nonvolatile memory cells in the erase and write operations, or to avoid the experience of excessive stresses; and it is possible to maintain a satisfactory characteristic related to the rewritable frequency of the nonvolatile memory cells.
In a concrete mode of the invention, the sum of a boosting interval of the voltage applied to the nonvolatile memory cells and a clamping interval of the boosted voltage is defined as the application interval of the boosted voltage, and the objective to which the boosting operation control regularizes the boosting speed is defined as the boosting interval. In another mode, a clamping operation interval of the boosted voltage is defined as the application interval of the boosted voltage, and the objective to which the boosting operation control regularizes the boosting speed is defined as the boosting operation interval.
In a concrete mode relating to the selection control, the IC card further includes a register, and the control means obtains information for designating the application interval to be selected by the selection control from the register. In another concrete mode of the invention, the IC card further includes a central processing unit and an external interface circuit, and the central processing unit sets the information for designating the application interval to be selected by the selection control in the register. In another concrete mode, the external interface circuit inputs the information that the central processing unit is to set in the register from the outside. In another concrete mode, the control means includes a clock generator that generates plural clock signals of different frequencies, a clock selector that selects the clock signals generated by the clock generator, and a timing controller that inputs the clock signals selected by the clock selector and generates timing signals for defining the application interval of the boosted voltage, in which the timing controller generates timing signals of different cycles in accordance with the frequencies of the clock signals inputted thereto, and the clock selector selects the clock signals on the basis of the values set in the register. For example, the timing controller is composed to possess a binary counter of plural bits that transmits the clock signals outputted from the clock selector to post-stages. If the clock signal frequency is made different, the frequencies of the frequency-divided signals obtained from each storage stage of the binary counter are made varied.
In the concrete mode relating to the boosting operation control, the control means generates boosting speed control data for determining the boosting speed to be controlled by the boosting operation control, on the basis of the number of the nonvolatile memory cells being objectives of the information storage operation in parallel. In another concrete mode, a booster to generate the boosted voltage includes a charge-pump circuit that executes the boosting operation synchronously with a clock signal, and the boosting speed control data controls the charge-pump circuit in accordance with the number of the nonvolatile memory cells being the objectives of the information storage operation in parallel, so as to make the frequency of the clock signal higher as a driven load is heavier. In another concrete mode, the control means is capable of selecting a clamping level of the boosted voltage.
[3] According to another aspect of the invention, the data processing device includes a central processing unit and a nonvolatile memory. The central processing unit executes an information storage control to the nonvolatile memory. The information storage control is to execute the erase and write processing of the data stored in the nonvolatile memory. In a first information storage control of the information storage control, an information storage control is executed which requires a first time for the erase of the data stored in the nonvolatile memory. In a second information storage control of the information storage control, an information storage control is executed which requires a second time shorter than the first time for the erase of the data stored in the nonvolatile memory. And, either of the first information storage control and the second information storage control is made selectable. In another concrete mode, in the first information storage control, the write of the data to be stored in the nonvolatile memory requires a third time, and in the second information storage control, the write of the data to be stored in the nonvolatile memory requires a fourth time shorter than the third time.
With regard to the selection of the first or the second information storage control, in a concrete mode, the selection is made by means of a program executed by the central processing unit. That is, the data processing device includes a memory area that stores a program executed by the central processing unit, and the program controls a step, in storing data in the nonvolatile memory, that selects either to store the data by the first information storage control, or to store the data by the second information storage control.
In another concrete mode, the data processing device includes a register that designates to select either of the first information storage control and the second information storage control. And, the step sets information for indicating the register to select either of the first information storage control and the second information storage control. In this case, the register may contain an area that allows setting at least one of the second time and the fourth time. The memory area is, for example, a part of the nonvolatile memory.
With regard to the selection of the first or the second information storage control, according to another aspect, the central processing unit is able to receive control information for selecting either to execute the first information storage control, or to execute the second information storage control, from the outside of the data processing device.
USPTO Backgrounds
USPTO Backgrounds