1. Field of the Invention
The invention relates in general to a receiving circuit for a data driver, and more particularly to a receiving circuit for receiving a reduced swing differential signal (RSDS).
2. Description of the Related Art
FIG. 1 shows a conventional receiving circuit 100 for receiving a reduced swing differential signal (RSDS). The receiving circuit 100 receives input differential data signals D1 and P1, and generates output data signals S1 to S4. The input data signals D1 and P1 and the input clock signal C1 are all RSDSs.
Referring to FIG. 1, the comparator 131 receives the input clock signal C1 and generates a compared clock signal C2. The compared clock signal C2 is transmitted to flip-flops 117, 119, 128 and 130 via a wire 132 and a buffer 133. After the compared clock signal is transmitted via wire 132, buffer 133 and an inverter 134, the compared clock signal C2 is inverted to produce an inverse compared clock signal C2′. Then the inverse compared clock signal C2′ is transmitted to flip-flops 118 and 129. The flip-flops 117, 119, 128 and 130 are positive edge-triggered. The flip-flops 118 and 129 are both negative edge triggered.
The comparator 111 receives an input data signal D1 and generates a compared data signal D2. The compared data signal D2 is transmitted to the flip-flops 117 and 118 via a wire 112 and buffers 113 to 116.
The flip-flops 117 and 118 produce an output data signal S2 and a negative edged data signal T1 from the compared data signal D2, respectively, according to the compared clock signal C2 and the inverse compared clock signal C2′. The negative edged data signal T1 is then transmitted via a positive edge triggered flip-flop 119. The flip-flop 119 adjusts the timing of the negative edged data signal T1 to generate an output data signal S1.
Similarly, the comparator 121 receives the input data signal P1 and generates a compared data signal P2. The compared data signal P2 is transmitted to the flip-flops 128 and 129 via a wire 122 and buffers 123 to 127. The flip-flops 128 and 129 produce an output data signal S4 and a negative edged data signal T2, respectively, from the compared data signal P2 according to the compared clock signal C2 and the inverse clock signal C2′. The negative edged data signal T2 is then transmitted via a positive edge triggered flip-flop 130. The flip-flop 130 adjusts the timing of the negative edged data signal T2 to generate an output data signal S3. The circuit structures of the data comparators 111, 121 and a clock comparator 131 are the same.
Since the input clock signal C1 lags the input data signals D1 and P1, the buffers are positioned after the wires 112 and 122 to delay the compared data signals D2 and P2.
In addition, since in the conventional receiving circuit 100, the distance between the comparator 111 and its corresponding flip-flop, and the distance between the comparator 121 and its corresponding flip-flop are not equal, the wires 112 and 122 have different lengths. Therefore, the delay time after the compared data signal D2 is transmitted via the wire 112 is unequal to the delay time after the compared data signal P2 is transmitted via the wire 122. To compensate for the different delay times, different numbers of buffers are used after the wires 112 and 122. For buffering the compared data signal D2, four buffers 113 to 116 are used, and for buffering the compared data signal P2, five buffers 123 to 127 are used. Thus, the total delay time after the compared data signal D2 is transmitted via the wire 112 and the buffers 113 to 116, is more consistent with the delay time after the compared data signal P2 is transmitted via the wire 122 and the buffers 123 to 127.
A buffer is very sensitive to its driving voltage. When the driving voltage changes, the delay time of the buffer, changes. Thus, when a conventional receiver is used under different driving voltages, the delay times of the buffers change. Thus, the delay times after the compared data signals D2 and P2 are transmitted via the two ways will still be different again.
FIG. 2 shows an example of the relationship between the compared data signal D2 and the compared clock signal C2 received by the flip-flop 117 in a conventional receiving circuit under different driving voltages. The compared data signal D2 and the compared clock signal C2 are transmitted via the wire 112 and the buffers 113 to 116 before being received by the flip-flop 117. Referring to FIG. 2, the waveform 201 is the waveform of the compared clock signal. The waveforms 202 and 203 are the waveforms of the data signal D2 in the conventional receiving circuit 100 in, respectively, the hold time condition and the setup time condition when the driving voltage is 3.3 V.
The waveforms 204 and 205 are the waveforms of the compared data signal D2 in the conventional receiving circuit 100 in, respectively, the hold time condition and the setup time condition when the driving voltage is 3.6 V. The waveforms 206 and 207 are the waveforms of the compared data signal D2 in, respectively, the hold time condition and the setup time condition when the driving voltage is 2.2 V.
At the time point tf, the waveform 201 forms a negative edge. Take the flip-flop 117 to be a negative edge triggered flip-flop as an example. In FIG. 2, the hold times th1, th2, and th3 formed by the waveforms 202 and 201, 204 and 201, and 206 and 201, respectively, are unequal. The setup times ts1, ts2, and ts3 formed by the waveforms 203 and 201, 205 and 201, and 207 and 201, respectively, are also unequal. Hence, different driving voltages will change the delay times of the buffers in the flip-flop 117, so that the phase difference between the compared data signal and the compared clock signal will change.
After the compared data signal D1 is transmitted via the wire 112 and the buffers 113 to 116, the setup time and the hold time formed by the compared data signal D1 and the compared clock signal C2 will not match the setup time and the hold time required by the flip-flop 117. Thus the flip-flop 117 may output an incorrect output data signal S2. From the above, if the conventional receiving circuit is to be used under different driving voltage conditions, the influence of the driving voltage on the buffers must be considered, which is very inconvenient for the designer
Also, the inverse compared clock signal C2′ is generated by the inverter 134. It will cause a phase difference between the inverse compared clock signal C2′ and the compared clock signal C2, which means the two clock signals C2 and C2′ have different phases. Therefore, the negative edge triggered flip-flops 118 and 129 may output incorrect negative edged data signals T1 and T2 from the compared data signals D1 and D2.
USPTO Backgrounds
USPTO Backgrounds