1. Field of the Invention
The present invention relates to a frequency divider and a frequency dividing method, and more particularly, to a frequency divider and a frequency dividing method utilizing retimed control signals for phase selection.
2. Description of the Prior Art
As the progress of modern technology goes on, clock generating systems, e.g., a phase locked loop or a delay locked loop system, find a variety of applications in wireless communication systems. In order to minimize interfering impacts between crucial components within a system-on-chip (SOC) chip, signals with large power should be well-defined and separated from each other in frequency domain to obtain a better performance. As a result, fractional frequency dividers become significant building blocks within a wireless transmitter or receiver.
Conventional frequency dividers in low frequency range are usually implemented with dual-modulus or multi-modulus prescalers, for example, a divide-by-4.5 circuit can be realized by a prescaler of which the modulus equally distributed between 4 and 5. However, since those prescalers are required to change its modulus during outputting divided signals simultaneously, noise generated from modulus transition may also bring degradation to the outcome of the prescaler, leading to more undesired jitters.
Besides, dual-modulus or multi-modulus prescalers work in a digital fashion and both are not suitable to operate at high frequency. Some conventional high-speed frequency dividers utilize self-mixing mechanism to overcome speed issue at the expense of inductor area, whereas those inductors are necessary to filter out undesired signal among mixed results. Therefore, circuit designers seek a solution to derive a compact frequency dividing solution with less jitter noise and more efficiency.
In addition to the topologies introduced in the aforementioned paragraphs, phase selection is also another popular architecture to implement frequency dividing. Please refer to FIG. 1, which is a diagram of a conventional phase selection frequency divider 1000. The frequency divider 1000 includes a phase selection circuit 1100 and a control circuit 1200. The phase selection circuit 1100 receives a plurality of input signals, for example, four quadrature signals SI, SQ, SIB and SQB, to generate an output signal Sout by selectively outputting one of the input signals SI, SQ, SIB and SQB according to control information Sctrl. The control signal 1200 receives the output signal Sout to generate the control information Sctrl (in this example, the control information Sctrl should includes all the control signals for selecting one from all the input signals SI, SQ, SIB and SQB), wherein a period interval of the output signal Sout is composed of partial intervals selected from each of the input signals SI, SQ, SIB and SQB.
Please refer to FIG. 2 for operation details of the frequency divider 1000 shown in FIG. 1, FIG. 2 is an exemplary timing diagram of partial signals within the frequency divider 1000, the phase selection circuit 1100 choose to output one of the input signals SI, SQ, SIB and SQB to compose the frequency-divided output signal Sout with a dividing ratio 1.25 and a duty cycle of 40%. Please note that, when the phase selection circuit 1100 is switching from the input signal SI to the input signal SQ, the exact switching timing point should be limited from a time point ta to another time point tb, i.e., during a time interval Tc (a glitch-free window) when the input signal SI and the input signal SQ are both indicative of a low voltage level, therefore the control information Sctrl, after a series of gate delay, should make the phase selection circuit 1100 to perform phase selection during the time interval Tc, or else a glitch will occur at the output signal Sout. Since the time interval Tc is exactly ¼ of a period of each input signal, the limitation of the glitch-free window puts a hard constrain on the design of frequency dividers, particularly to the high-speed frequency dividers with very tiny glitch-free windows. Therefore, the phase selection circuit 1100 must be carefully designed to perform the switching accurately; in other words, the delay time and slew rate of each building block in the signal transmission path must be carefully considered to achieve a glitch-free performance, or else the jitter resulted from the transition will deteriorate the system performance. FIG. 3 is another exemplary timing diagram of partial signals within the frequency divider 1000. Compared with the timing diagram shown in FIG. 2, the phase selection circuit 1100 chooses to compose the frequency-divided output signal Sout with a duty cycle of 60% instead of 40%, and the exact switching timing should also be limited to a time interval Tc′ of a same length as the time interval Tc, i.e., ¼ period of the input signal.
USPTO Backgrounds
USPTO Backgrounds