1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a method for manufacturing such a semiconductor memory device. More specifically, the present invention relates to a static random access memory (SRAM) having P-channel thin-film transistors (TFTs) as load MOS transistors and a method of manufacturing such a static random access memory.
2. Description of the Related Art
In the presently available SRAM memory cells, the major method thereof is to use high resistance elements as load elements since the SRAM memory cells can be integrated in higher integration. However, another method using P-channel TFTs as load elements becomes more important in order to secure stabilities for soft errors caused by leakage currents, noise, or .alpha.-rays, as SRAM memory cells are made smaller and smaller, and also are made operable under further low voltages.
Referring now to FIG. 1, which illustrates an equivalent circuit diagram of a first conventional example of an SRAM memory cell, such an SRAM memory cell having P-channel MOS transistors as load elements is constructed as follows. That is, this memory cell is composed of six MOS transistors. For instance, this memory cell is composed of one pair of information transfer MOS transistors, i.e., two N-channel transfer MOS transistors TT1 and TT2, one pair of driver MOS transistors, i.e., two N-channel driver MOS transistors TD1 and TD2, and two P-channel load MOS transistors TL1 and TL2.
These six MOS transistors are connected to each other in the below-mentioned manner. The first inverter composed of MOS transistors TD1 and TL1 is cross-coupled to the second inverter composed of MOS transistors TD2 and TL2 at two connection points or nodes N1 and N2. The N-type source regions of the MOS transistors TD1 and TD2 are connected to a ground line which is applied with the voltage Vss, whereas the P-type source regions of the MOS transistors TL1 and TL2 are connected to a power supply line which is applied with the voltage Vcc. The gate electrodes of the transfer MOS transistors TT1 and TT2 are connected to a word line WL. The source regions of the transfer MOS transistors TT1 and TT2 are connected to a pair of bit lines BL1 and BL2, respectively, and the N-type drain regions of the transfer MOS transistors TT1 and TT2 are connected to the nodes N1 and N2, respectively.
When the first conventional example of the SRAM memory cell is manufactured, if the six MOS transistors TT1, TT2, TD1, TD2, TL1, and TL2 are formed on the same surface of the silicon substrate, such an SRAM memory cell having the P-channel MOS transistors as the load elements would require the cell area 1.5 to 2 times larger than that of a memory cell using high resistance elements as the load elements. Thus, the first conventional example of SRAM memory cell could not be suitably manufactured in high integration. However, if a stacking layer structure is employed as the second conventional example of SRAM memory cell described below, then the resultant SRAM memory cell can be formed with the same cell area as that of the memory cell using the high resistance elements as the load element, resulting in high integration. That is, the four N-channel MOS transistors TT1, TT2, TD1, and TD2 are formed on the silicon substrate, and the two P-channel MOS transistors TL1 and TL2 are formed as one pair of load thin-film transistors (TFTs), and are stacked on a layer composed of the N-channel MOS transistors TT1, TT2, TD1 and TD2.
Then, nowadays, such an SRAM memory cell becomes important, in which an upper gate type TFT in which the gate electrode of a thin-film transistor (TFT) is provided in an upper portion of a channel portion is employed as a load element. This is because the source/drain regions of the thin film transistor can be formed in self-alignment with the gate electrode. On the contrary, in the lower gate type thin film transistor in which the TFT gate electrode is located in the lower portion of the channel portion, the above-described source/drain cannot be formed in the self-alignment with the gate electrode. As a consequence, this SRAM memory cell cannot be suitably made very fine.
The above-described technique which employs the upper gate type thin film transistor has been reported in, for instance, 1991 Symposium on VLSI Technology Digest of Technical Papers (pages 23 to 24). Referring now to FIG. 1 corresponding to the equivalent circuit diagram of the SRAM memory cell having the P-channel MOS transistors as the load elements, and FIG. 2 schematically illustrating a cross sectional view of the SRAM memory cell, a description will be made of the second conventional example of SRAM memory cell reported in the above-described publication.
Although a plan view of the memory cell is not shown in this publication, it is conceivable that FIG. 2 is such a cross sectional view of this memory cell along a direction parallel to bit lines BL1 and BL2 involving one of nodes N1 and N2 indicated in FIG. 1. Also, it could be considered that one cross sectional view involving the node N1 has a symmetrical structure with respect to that of the other cross sectional view involving the node N2. Under such considerations, the following description is made based on such an idea that FIG. 2 is the cross sectional view, taken along the direction parallel to the bit line BL1 involving the node N1. As to the other cross sectional structure involving the node N2, the N-channel transfer MOS transistors TT1 and TT2, the N-channel driver MOS transistors TD1 and TD2, the nodes N1 and N2, and the bit lines BL1 and BL2 may be replaced with each other.
As shown in FIG. 2, field oxide films 102 and a gate oxide film 103 are formed on the surface of a silicon substrate 101. Then, a gate electrode 104 of the N-channel driver MOS transistor and a gate electrode 105 of the N-channel transfer MOS transistor are formed on the gate oxide film 103. Furthermore, N-type diffusion layers 106a and 106b are provided in self-alignment with the field oxide film 102 and the transfer transistor gate electrode 105 in an active region of the surface of the silicon substrate 101.
In this manner, the driver MOS transistor TD2 is composed of the driver transistor gate electrode 104, the gate oxide film 103, and the N-type diffusion layers (not shown) arranged along the direction perpendicular to the drawing plane of FIG. 2 to sandwich the driver transistor gate electrode 104. Also, the transfer MOS transistor TT1 is composed of the transfer transistor gate electrode 105, the N-type diffusion layer (N-type drain region) 106a, and the N-type diffusion layer (N-type source region) 106b. It should be noted that the transfer transistor gate electrode 105 functions as a word line WL, and the N-type diffusion layer 106a may be used as the drain region of the N-channel driver MOS transistor (not shown in FIG. 2).
A ground line 108 having a polycide structure is provided on the first interlayer insulating film 107 for these N-channel MOS transistors. Although not shown in this figure, this ground line 108 is connected via a ground contact hole to the N-type diffusion layers which will constitute the sources of the N-channel driver MOS transistors TD1 and TD2. Then, the surface of the first interlayer insulating film 107 involving the ground line 108 is covered with the second interlayer insulating film 109.
A node contact hole 110 and a bit line contact hole 111 are formed through the first interlayer insulating film 107 and the second interlayer insulating film 109 in such a manner that the node contact hole 110 reach the driver transistor gate electrode 104 and the N-type diffusion layer 106a, and the bit contact hole 111 reaches the N-type diffusion layer 106b. The contact plugs 112 and 113 made of the N-type doped polysilicon are formed inside these node contact hole 110 and bit contact hole 111. In this manner, the driver transistor gate electrode 104 is connected via the contact plug 112 to the N-type diffusion layer 106a inside the node contact hole 110.
A titanium silicide layer 114 is formed on the uppermost portion of the contact plug 112 in order to avoid the PN diode formed in a parasitic manner between the P-type TFT drain region and the N-type contact plug 112. At the same time, a titanium silicide layer 115 is also formed on the upper portion of the contact plug 113.
Then, the P-channel thin film transistors having an upper gate structure are formed as the load elements on the surface of the second interlayer insulating film 109. That is, the polysilicon film pattern is formed on the second interlayer insulating film 109. From this polysilicon film pattern, a high-concentration P-type polysilicon region 116 for constituting the TFT source region, the N-type polysilicon region 117 for constituting the channel region thereof, the high-concentration P-type polysilicon region 118 for constituting the drain region thereof, and the low-concentration P-type polysilicon regions 119a and 119b for constituting lightly doped drain (LDD) regions thereof are fabricated. Then, a power source wiring 121 made of a P-type polysilicon film, and TFT gate electrodes 122a and 122b are formed on the TFT gate insulating film 120. The power source wiring 121 and the TFT gate electrode 122b are connected via the contact holes to the high concentration P-type polysilicon regions 116 and 118, respectively.
As described above, the P-channel thin film transistor TL1 is composed of the gate electrode 122a, the high concentration P-type polysilicon region 116, the low concentration P-type silicon region 119a, the N-type polysilicon region 117, the low concentration polysilicon region 119b, and the high concentration P-type polysilicon region 118. The gate electrode 122b is the gate electrode of the P-channel load thin film transistor TL2.
Furthermore, the protection insulating film 123 is deposited, the third interlayer insulating film 124 is formed, and the bit line 125 is provided. In this case, the bit line 125 is connected via the contact hold to the titanium silicide 115.
Next, the conventional manufacturing method of the SRAM having the P-channel TFTs as the load elements will now be briefly explained with reference to FIGS. 3A to 3C. FIGS. 3A to 3C are a cross sectional view for schematically representing the manufacturing sequential steps of the SRAM memory cell.
As shown in FIG. 3A, the field oxide film 102 is formed in the isolation region on the surface of the P-type silicon substrate 101, and the gate oxide film 103 is formed in the active region. The N-type polysilicon film and the tungsten silicide film are sequentially formed on the entire surface. Then, these stacked films are patterned, so that the driver transistor gate electrode 104 and the transfer transistor gate electrode 105 are formed. N-type impurity ions are implanted to form the N-type diffusion layers 106a and 106b on the surface of the P-type silicon substrate 101 using the field oxide film 102, the driver transistor gate electrode 104, and the transfer transistor gate electrode 105 as a mask.
Next, the first interlayer insulating film 107 is formed on the entire surface. After the ground contact (not shown) has been formed, the N-type polysilicon film, and the tungsten silicide film are successively formed on the overall surface. These stacked films are patterned to form the ground line 108.
Next, the second interlayer insulating film 109 having a flat surface is formed over the entire surface, and the connection contact hole 110 is formed to pass through the first and second interlayer insulating films 109 and 107, and then to reach both of the driver transistor gate electrode 104 and the N-type diffusion layer 106a. Similarly, the bit contact hole 111 is formed to reach the N-type diffusion layer 106b. The insides of this node contact hole 110 and this bit contact hole 111 are filled with the N-type polysilicon film, so that the contact plugs 112 and 113 are formed. Now, titanium is formed on the entire surface and then is subjected to heat treat, so that the titanium silicide layers 114 and 115 are formed in the self-alignment manner only on the upper portions of the contact plugs 112 and 113.
Next, the polysilicon film containing the N-type impurity ions is formed on the entire surface, and then is patterned to thereby form the N-type polysilicon region 117. The TFT gate insulating film 120 is formed on the entire surface of this N-type polysilicon region 117, and the contact hole is formed. Thereafter, the P-type polysilicon film is formed on the entire surface. Then, this silicon film is patterned to form the power source wiring 121, and the TFT gate electrodes 122a and 122b (FIG. 3A).
In this case, BF.sub.2 ions corresponding to the P-type impurity are implanted at a dose of order of 3.times.10.sup.13 cm.sup.-2. The low concentration polysilicon regions 119'a and 119'b are formed in the self-alignment manner using the TFT gate electrode 122a as a mask (FIG. 3B).
Subsequently, a protection insulating film 123 used to form the LDD structure is formed on the entire surface, and BF.sub.2 ions corresponding to the P-type impurity ions are implanted at a dose of order of 1.times.10.sup.15 cm.sup.-2, so that the high concentration P-type polysilicon regions 116 and 118 are formed. At this time, the following assumption is made as follows: the regions 116' and 118' which are masked and into which the impurity ions are not implanted are left in the portions covered by the power source wiring 121 and the TFT gate electrode 122b. However, since the power source wiring 121 and the TFT gate electrode 122b are made of the P-type polysilicon film, if the heat treatment is sufficiently carried out later, then the P-type impurity ions are diffused through the contact hole. As a result, these regions 116' and 118' into which the impurity ions are not implanted will disappear (FIG. 3C).
Next, the third interlayer insulating film 124 is formed on the entire surface, and then the contact hole is formed in such a manner that this contact hole passes through the third interlayer insulating film 124, the protection insulating film 123, and the TFT gate insulator 120, and thereafter reaches the titanium silicide layer 115. Finally, the bit line 125 is formed, so that the SRAM structure shown in FIG. 2 is accomplished.
In the above-described conventional SRAM memory, as shown in FIG. 3C, the regions 116' and 118' into which no impurity ion has been implanted are formed in the lower portions of the power source wiring 121 and the TFT gate electrode 122b. Also, in order to form the LDD structure in the self-alignment manner, the low concentration P-type polysilicon regions 119'a and 119'b are also formed in the edge portions of the power supply wiring 121 and the TFT gate electrode 122b. When these regions are left, these regions may function as a series resistor with respect to the P-channel load thin film transistor, so that the current drivability of the thin film transistor would be considerably lowered. For instance, a polysilicon film into which no impurity ion is implanted may represent such a very high layer resistance of on the order of 10.sup.12 .OMEGA./.quadrature. per unit area, and a low concentration polysilicon film used in an LDD region may represent such a very high layer resistance of on the order of 10.sup.6 .OMEGA./.quadrature.. As previously described, in order to remove these regions, the P-type impurity ions must be necessarily diffused by sufficiently performing the heat treatment. However, such a sufficient heat treatment can be hardly applied to productions of very fine SRAMs in the future, because of the below-mentioned three reasons.
As a first reason, both N-channel MOS transistor and P-channel MOS transistor are formed under the load type P-channel thin film transistor, i.e., on silicon substrate surface. These N-channel and P-channel MOS transistors have been thermally treated during the steps such as the step for planerizing the interlayer insulating film before the load type P-channel thin film transistor is manufactured. As a consequence, since such heat treatment is carried out at high temperatures and for a long time duration after the thin film transistor has been formed, there are high risks that the characteristics of these very fine MOS transistors would be considerably deteriorated by the short channel effect.
As a second reason, in a case where the LDD structure is formed, in order that the electric field in the drain region is effectively relaxed so as to reduce leakage current of the thin film transistor, it is desired that the high concentration P-type polysilicon region 118 which will constitute the drain region is offset from the TFT gate electrode 122a. This is because if the high concentration P-type polysilicon region 118 is overlapped with the TFT gate electrode 122a, the electric field in the drain region is emphasized by receiving the influences of the electric field in the gate. To avoid such a problem, the above-described heat treatment at high temperatures and for a long time duration should be avoided, because the diffusion of the P-type impurity ions contained in the high concentration P-type polysilicon region 118 should be reduced as much as possible.
As a third reason, the titanium silicide layers 114 and 115 are formed in the upper portions of the contact plugs 112 and 113. When these titanium silicide layers 114 and 115 are thermally treated at high temperatures and for a long time duration, the film aggregation will occur, resulting in a rapid increase of the resistance.
Accordingly, the above-described conventional SRAM memory cell has the various problems. That is, the regions 116' and 118' into which no impurity ion has been implanted, and the low concentration P-type polysilicon regions 119'a and 119'b are easily left in the conventional SRAM memory cell. Thus, the parasitic resistance is increased, and the current drivability of the load type P-channel thin film transistor is considerably lowered.
Also, in the conventional SRAM memory cell, if the contact hole is formed out of either the power supply wiring 121 or the TFT gate electrode 122b, when the power supply wiring 121 and the TFT gate electrodes 122a and 122b are patterned, the polysilicon film which will constitute the main body of the thin film transistor is also etched away during the etching treatment. As a consequence, when this contact hole is formed, the anisotropic dry etching is required. Thereafter, a photoresist film is removed by way of oxygen plasma, and cleaning treatment is carried out by using ammonia and sulfuric acid, so that a native oxide film is formed in the contact hole. If the polysilicon film is directly deposited on this native oxide film, then no electric conductivity could be established between the power supply wiring 121, the TFT gate electrode 122b, and the high concentration P-type polysilicon regions 116 and 118. To avoid this difficulty, an oxide film etching must be lightly carried out by using diluted hydrofluoric acid as the pretreatment of forming the polysilicon. As a result, the TFT gate insulator 120 is locally made thinner. Thus, there is another problem that a break down voltage failure of the gate insulator may readily occur.
These problems are caused by the manufacturing method itself, but also the structure of the semiconductor memory device.
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