In the pursuit of faster and more powerful computers, more and more functions are being implemented into computers while their operating frequencies have been raised. Consequently, the probability that computer or circuit designers may have inadvertently provided too small a timing margin for noise induced signal fluctuations has also increased. When noise induced fluctuations push a signal over a given margin, a timing error will result.
Because of their dependence on noise, timing errors are usually very unpredictable, making the isolation thereof extremely difficult. Often, the only practical way to isolate a timing error is by "aggravating" the error, that is, by varying the system clock frequency so as to cause it to occur more consistently. There is thus a need for an apparatus whereby a system clock can be switched to different frequencies.
There is another reason for changing the frequency of a system clock. When a timing problem suddenly occurs (due to a change in component characteristics, such as current amplification of a transistor) during critical operations of a computer, it may be desirable to temporarily bypass the timing error by dynamically lowering the frequency of the system clock and thereby increasing the timing margin.
Varying the system clock frequency to either aggravate or to avoid a timing error should desirably be done incrementally because the frequency cannot be changed too much that other timing errors are introduced. Thus, it is desirable for a system to have many sources providing different frequencies so that an optimal one can be chosen.
The capability to change frequency source is also useful in a multiprocessor system when, in order to make the system processors tightly-coupled, the system clock of one processor is used to drive the other processors.
When switching a system clock to a new frequency source, the clock is typically stopped, the new frequency source switched in, and the system clock then restarted. Because the old and the new frequency sources are usually not synchronized, there is a possibility that the system clock may be turned off or on during the active period of a system clock cycle. However, because prespecified activities are scheduled for each active system cycle period, narrowing an active clock period may erroneously cut off or introducing errors into some of these activities. Thus, it is desirable that the switch-over process be synchronized, that is, the old frequency source is disconnected and the new frequency is switched in during inactive periods.
A conventional clock switching circuit whereby the above-identified requirements have been satisfied is shown in FIG. 1. In each oscillator path of this conventional circuit, a pair of latches 101, 102 (e.g. LN1 and LN2), both clocked by a corresponding frequency source, are used to perform the above mentioned synchronization at switch-over. In this conventional clock switching circuit, however, each addition of a new oscillator to the system requires a substantial change in the circuit: including the addition of two latches 101, 102 (LNI, LN2) and a 2-input AND gate 103 (BN), the addition and the changing of the n-input AND gates 104 (A1, A2,..AN), as well as changing the n-input OR gates 105.
There is thus a need for a clock switching circuit whereby a system clock can dynamically be switched to a new frequency source and in which new frequency sources can be added without requiring substantial changes to the circuit.
USPTO Backgrounds
USPTO Backgrounds