This invention relates generally to integrated circuits and more particularly to on-chip inductors.
As is known, wireless communications standards place stringent requirements on a wireless communication device""s dynamic range of operation because the signal strength of received signals may vary by many orders of magnitude. To meet these requirements, wireless communication devices are designed using radio frequency (RF) integrated circuits (IC) that consume low power and produce little noise. As is also known, on-chip inductors are significant components of RF integrated circuits and are used in oscillators, impedance matching networks, emitter degeneration circuits, filters, and/or baluns. Thus, it is desirable to use on-chip inductors that consume as little power as possible and produce as little noise as possible.
As is further known, inductor performance is expressed as a quality factor (Q-factor), which is associated with the resonance of the inductor and describes both the ability of the inductor to produce a large output at the resonant frequency and the selectivity (i.e., the power ratio in decibels versus frequency) of the inductor. As such, the Q-factor is a key component in determining power dissipation and phase noise of integrated circuits. In general, inductors having a high Q-factor dissipate less power and thus improve the achievable gain. Further, high Q inductors allow an oscillating circuit to perform with minimal power injection from the driving transistor and hence minimize noise.
In addition, high Q inductors minimize the power leaking into adjacent channels that corrupts a receiver performance in nearby channels of communication chips, which degrade a receiver""s sensitivity. Furthermore, higher dynamic range of wireless communication devices is obtained due to the intrinsic linearity of passive devices.
Not surprisingly, high Q inductors are a key element for RF integrated circuits to have low power consumption and to achieve the desired noise performance. While performance of wireless communication devices is a critical design issue it is typically balanced with manufacturing costs of the devices.
As is known, CMOS technology is widely used for cost effective fabrication of integrated circuits, including RF integrated circuits. However, on-chip inductors using CMOS technology are known to have a modest quality factor in the range of 5 to 10, which limit their usefulness is applications that require a high Q inductor, including some wireless communication applications.
Therefore, needs exist for a high quality factor on-chip inductor for use in many applications including wireless communication applications.
The high Q on-chip inductor of the present invention substantially meets these needs and others. In general, the high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding (i.e., reversed biased). Further, the auxiliary winding has a real part of its admittance greater than the real part of the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor (e.g., at least 30) for an on-chip inductor.
Another embodiment of a high Q on-chip inductor includes the primary winding, the auxiliary winding, and a poly-silicon shield. The primary and secondary winding are as described in the preceding paragraph and are fabricated proximally located to a poly-silicon shield such that the quality factor of the primary winding increases at least 15 times that of the quality factor of current on-chip inductors (e.g., the quality factor is at least 150).
A further embodiment includes a primary winding, a primary auxiliary winding, a secondary winding, and a secondary auxiliary winding thus producing a high quality factor on-chip transformer. The secondary auxiliary winding is coupled to receive a proportionally opposite representation of the signal of the secondary winding. Further, the secondary auxiliary winding has a real part of its admittance greater than the real part of the admittance of the secondary winding thereby yielding an asymmetry in the admittances.
In any of the embodiments, the number of turns comprising the winding (e.g., primary, auxiliary, secondary, and/or secondary auxiliary) may vary depending on the inductance needed, a desired Q factor, various winding shapes (e.g., square, rectangular, spiral, etc.) and/or a desired turns ratio. In addition, the number of layers on which the windings are created may also vary depending on the inductance needed, a desired Q factor, and/or a desired turns ratio.
USPTO Backgrounds
USPTO Backgrounds