During chemical vapor deposition (CVD) of silicon oxide and other layers onto the surface of a substrate, the deposition gases released inside the processing chamber may cause unwanted deposition on areas such as the walls of the processing chamber. Unless removed, this unwanted deposition is a source of particles that may interfere with subsequent processing steps and adversely affect wafer yield.
To avoid such problems, the inside surface of the chamber is regularly cleaned to remove the unwanted deposition material from the chamber walls and similar areas of the processing chamber. This procedure may be performed as a standard chamber dry clean operation where an etchant gas, such as nitrogen trifluoride (NF3), is used to remove (etch) the deposited material from the chamber wall and other areas. During the dry clean operation, the chamber interior is exposed to a plasma from the etchant gas so that the etchant gas reacts with and removes the deposited material from the chamber walls. Such cleaning procedures are commonly performed between deposition steps for every wafer or every n wafers.
The clean step can, in itself, be a source of particle accumulation however. Fluorine from the clean plasma can be adsorbed and/or trapped in the chamber walls and in other areas of the chamber such as areas that include ceramic lining or other insulation materials. The trapped fluorine can be released during subsequent processing steps (e.g., by reacting with constituents from the plasma in a high density plasma CVD (HDP-CVD) step) and can be adsorbed in subsequently deposited silicon oxide layers.
To prevent such fluorine adsorption and to provide protection against other contaminants within the chamber walls (e.g., the diffusion of metal fluorides) a CVD chamber is often “seasoned” after the dry clean operation. Such seasoning includes depositing a thin silicon oxide layer over the chamber walls before a substrate is introduced into the chamber for processing. The deposited silicon oxide layer covers the chamber walls, reducing the likelihood that contaminants will interfere with subsequent processing steps. After deposition of the seasoning layer is complete, the chamber is used for 1 to n substrate deposition steps before being cleaned by another clean operation as described above and then reseasoned.
The dielectric properties of the seasoning layer also provide an insulating barrier that prevents electrical arcing between the plasma and the walls of the chambers. The chambers typically include conductive materials (e.g., metals), and when the electric potential of the plasma exceeds a threshold level it begins to ground itself by discharging through the exposed conductive surfaces of the chamber. This discharging can damage the chamber by ablating away parts of the conductive surface. Coating these exposed conductive surfaces with the seasoning film reduces (or prevents) plasma arcing.
A conventional method used to season deposition chambers includes the steps of forming a plasma from a process gas of silane (SiH4), oxygen (O2), and argon (Ar). In one particular implementation of this previously known method, the preferred flow ratio of oxygen to silane used in the method is 1.375:1. O2 is introduced at 110 sccm, SiH4 is introduced at 80 sccm and Ar is introduced at 20 sccm. This seasoning process has been used to protect subsequent processing steps form contaminants in the HDP-CVD chamber.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced decades ago. Today's wafer fabrication plants are routinely producing integrated circuits having 0.13 micron feature sizes and smaller.
As device sizes become smaller and integration density increases, issues that were not previously considered important by the industry are becoming a concern. Also, improved control over criteria such as particle generation and contaminant control is necessary to ensure that deposited layers meet stringent manufacturers specifications. In order to meet processing demands created by such small scale geometry devices, new technology for substrate processing equipment is constantly being developed.
Another trend in semiconductor fabrication is for a larger numbers of copies of an integrated circuit design to be formed on a single substrate. For example, the current industry standard is to form integrated circuits on circular silicon wafers having a 200 mm diameter. Current trends in the industry, however, favor forming ICs on larger, 300 mm diameter wafers. The larger wafers allow more copies of an IC to be fabricated in a single process than could be accommodated on the smaller 200 mm wafers.
However, the larger wafers can place extra demands on the fabrication chamber, including the need to operate the chamber at higher power to generate an adequate sized plasma for depositing a film on the larger substrate. The higher operating powers can heat-up chamber components to temperatures that may hit or exceed high-temperature thresholds for those components. Thus, there is a need for components that can operate in the high power environments used with larger substrates that also have the low particle generation characteristics needed for efficient production of today's densely packed ICs.
USPTO Backgrounds
USPTO Backgrounds