1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having an improved surge protection function at an input stage. The present invention particularly relates to an improvement in the input stage of an input buffer circuit in a semiconductor integrated circuit comprising a gate array system.
2. Description of the Background Art
Since semiconductor devices are ever advancing in integration, and size is decreasing, electrostatic breakdown becomes an important problem particularly in MOS devices, because MOS devices have a particularly high input impedance. Static electricity in a semiconductor device is subject to temperature and humidity, and generally decreases as temperature rises or humidity increases. Static electricity is particularly influenced by humidity. When relative humidity is 40 to 50% or less, static electricity increases dramatically.
Breakdown of a chip due to static electricity is roughly divided into three modes. The first mode is fusion of an internal lead, e.g., aluminum or polysilicon, the second mode is breakdown of an oxide film, and the third mode is breakdown of a junction. Fusion of a wire lead such as gold wire or thin aluminum wire may occur together with the above breakdown of a chip.
The three modes frequently appear in combination. On the other hand, in case of a slight damage, no trouble is detectable from the appearance of the chip, but leakage current of a junction may increase or the amplification factor of a transistor may decrease. Therefore, in case of an MOS device, a surge protection circuit is generally provided in an input buffer circuit to protect internal circuits from static electricity.
FIG. 5 shows a circuit diagram of an input stage of a conventional semiconductor integrated circuit. In the conventional input stage circuit shown in FIG. 5, an input pad 1 receives an input signal. The input signal is then transferred to an input buffer circuit 2 via a resistance element 11. The input buffer circuit 2 is comprised of a P-channel MOS transistor 6 and an N-channel MOS transistor 8 connected in series between a power-supply potential node 4 and an earth potential node 7. Each gate of the transistors 6 and 8 is connected at an input node 3. Each internal wiring 9 and 10 is connected respectively to the input node 3 and an output node 5 of the input buffer circuit 2.
A first diode 12 is connected between the input pad 1 and the power-supply potential node 4. A second diode 13 is connected between the input pad 1 and the earth potential node 7. Each diode 12 and 13 is comprised of an off-state P-channel or N-channel MOS transistor with its source and gate short-circuited. The resistance element 11, the first diode 12, and the second diode 13 work as a surge protection circuit.
FIG. 6 is a layout diagram of the input-stage input buffer circuit 2 shown in FIG. 5. In the case of a CMOS gate array as shown in FIG. 6, the P-channel MOS transistor 6 comprises gates 6a and 6b made of polysilicon and connected to the power-supply potential node 4, a gate 6c made of polysilicon and disposed between the gates 6a and 6b, a P-type drain region 6d formed at the surface of a semiconductor substrate between the gates 6a and 6c, and a P-type source region 6e at the surface of the semiconductor substrate between the gates 6band 6c.
Further, as shown in FIG. 6, the N-channel MOS transistor 8 comprises gates 8a and 8b made of polysilicon and connected to the earth potential node 7, a gate 8c made of polysilicon disposed between the gates 8a and 8b, an N-type drain region 8d at the surface of the semiconductor substrate between the gates 8a and 8c, and an N-type source region 8e at the surface of the semiconductor substrate between the gates 8b and 8c.
The gate 6c of the P-channel MOS transistor 6 is connected with the gate 8c of the N-channel MOS transistor 8 by an aluminum wiring 3a on each gate 6c and 8c. The wiring 3a corresponds to the input node 3 in FIG. 5.
In operation of the circuit shown in FIGS. 5 and 6, when a surge equal to or higher than a power supply voltage is applied from the input pad 1, the surge flows to the power supply through the first diode 12. When a surge equal to or lower than a ground potential is applied from the input pad 1, then the surge flows to the ground through the second diode 13.
FIG. 7 is a circuit diagram showing another input circuit means of a conventional semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 59-208771. In FIG. 7, two transistors 14a and 14b are connected to the input pad 1 of the input buffer circuit 2 of the input stage of a semiconductor integrated circuit. The two transistors 14a and 14b have structures similar to the first diode 12 and the second diode 13 as shown in FIG. 5, and have a surge protection function. The other reference numerals in FIG. 7 refer to the same or similar elements as shown in FIG. 5, so that a detailed description is omitted.
The surge protection circuit of the input buffer circuit in the input stage of a conventional semiconductor circuit is constructed as described in FIG. 5 or FIG. 7. In those semiconductor integrated circuit devices, transistors which are not used in the input buffer circuit in an input stage are connected to an input pad capacitively or through a diode. Thus, a certain level of surge protection is attained. However, a surge protection circuit with higher surge protection function for higher surge voltage and with reduced area on a semiconductor chip is demanded for an input buffer circuit in a input stage of a semiconductor circuit.
USPTO Backgrounds
USPTO Backgrounds