1. Field of the Invention
The various embodiments described herein relate to a test bench for performing a test case on an integrated circuit. Furthermore, the various embodiments relate to a method for performing a test case on an integrated circuit.
2. Description of the Related Art
The main method for a functional hardware verification of an integrated circuit such as a microprocessor is a directed random simulation. The directed random simulation requires a test bench in order to simulate and check the hardware under verification. The test bench is coded in a standard programming language such as C++.
According to the prior art, the test bench is developed together with the hardware model for the device under verification. The test bench includes a reference model, which is developed together with the hardware model. In an early verification stage, the environment is very unstable, since the reference model and the hardware model contain many bugs. A considerable amount of time is required to stabilize the test bench and to find the first bug in the hardware. The required amount of time depends on the complexity of the test bench. During that time, new features are added to the hardware model. The new features cause a constant discrepancy between the hardware design and verification environments of the prior art; specifically, the verification environments lag behind the hardware design. Usually, this discrepancy ends only after the hardware design matures and no more features are added.
FIG. 3 illustrates a schematic timing diagram of a test case according to the prior art. The timing diagram illustrates the aforementioned discrepancy issue. A first curve represents the number of found environment bugs 22. A second curve represents the number of found hardware bugs 24. At the beginning of the verification cycle, all occurring bugs are typically environment bugs 22. After a certain time, the test bench is stable enough so that real hardware bugs 24 can be found. Since the bug rate is usually limited by the resources available for verification, the elapsed time before the first hardware bug 24 is found cannot be reduced arbitrarily.
A known method for addressing this problem is to raise the level of abstraction for coding the test bench. This may be achieved by using dedicated languages for test bench developments, such as the IEEE P1647 e functional verification language from Cadence. Another way to raise the level of abstraction is to automate the creation of the test bench. Such a method is known from U.S. Pat. No. 6,175,946, which describes a method for automatically generating checkers for finding functional defects in a description of a circuit.
Moreover, the article “Using a formal specification and a model checker to monitor and direct simulation” by S. Tasiran, Y. Yu and B. Batson (Proc. 40th Conference on Design Automation 2003, Anaheim, Calif., USA, p. 356) describes a technique for verifying that a hardware design correctly implements a protocol-level formal specification.
Furthermore, a combination of formal verification and random simulation in a single test case is known from the paper “Functional formal verification on designs of pSeries microprocessors and communication subsystems” by R. M. Gott, J. R. Baumgartner, P. Roessler and S. I. Joe (IBM Journal of Research and Development, Volume 49, Number 4/5, 2005). The results of the formal verification and the random simulation can be compared. However, this method depends on the hardware model, and thus the single steps of a test case can be performed only after the corresponding steps in the hardware model have been created.
The above prior art methods have the drawback that the development of the test bench is performed together with the verification of the hardware design. Thus, these prior art methods do not provide a complete solution to the aforementioned discrepancy issue.
FIG. 4 illustrates a schematic diagram of a test bench and a method for performing a test case according to the prior art. A hardware model 30, a reference model 32, and a random simulation environment 34 are provided. The hardware model 30 is generated from a hardware description language (HDL). The HDL describes the logic. The hardware model 30 should be synthesized to a semiconductor chip in a later step. Thus, the hardware model 30 contains the logic written by the hardware designer in order to simulate a function in accordance with the relevant specification. The hardware model 30 can be used for both a formal verification 36 and a random simulation 38 of the random simulation environment 34.
The reference model 32 and the random simulation environment 34 are two distinct models provided for different kinds of verification activities. Both the reference model 32 and the random simulation environment 34 are derived from the same specification that is used to code the hardware model 30, which represents the HDL for synthesizing the semiconductor chip.
The HDL of the reference model 32 is created by a verification team. The reference model 32 is also provided to simulate the function according to the specification. The reference model 32 may comprise elements of a higher level, which are not synthesizable. The HDL of the reference model 32 is written only for checking the hardware model 30.
The formal verification 36 can ensure that the reference model 32 and the hardware model 30 are equivalent. Usually, the reference model 32 describes only a part of the logic of the device under test. Specifically, the reference model 32 typically describes such parts of the logic that are suitable for the formal verification 36. For example, the data path of a microprocessor may be described by the reference model 32. Such part is compared with a corresponding part of the hardware model 30.
The formal verification 36 finds bugs 40 in both the reference model 32 and the hardware model 30. The random simulation 38 finds bugs 42 in both the random simulation environment 34 and the hardware model 30.
The hardware model 30 is simulated randomly by the random simulation 38, and the obtained results are compared with expectation values. The expectation values may be obtained from a database with test values.
The failures in the formal verification may be due to bugs in both the reference model 32 and the real hardware. The failures in the random simulation may be due to bugs in both the random simulation environment 34 and the real hardware.
FIG. 5 illustrates a schematic diagram according to the prior art of the relation between bugs 44 found in the formal environment and bugs 46 found in the simulation environment. The bugs 48 in the real hardware are partially found in the formal environment 44 and partially found in the simulation environment 46. Some bugs may be found by both verification environments, as depicted by the overlapping areas of 44 and 46. A further portion of the real hardware bugs 48 may not be found in either verification environment.
While the prior art implementations permit finding bugs by using verification environments, such verification environments cannot be validated without the use of a hardware model as a design under verification. Thus, as previously discussed, the discrepancy between the hardware design and the verification environments may not be resolved before the hardware design matures, and there is a significant amount of elapsed time before a first hardware bug can be found using the verification environments.
USPTO Backgrounds
USPTO Backgrounds