In a typical FET switch, control voltages with complimentary polarity had to either be supplied to, or generated by, a circuit employing the FET switch. If the typical FET switch is on a monolithic microwave integrated circuit (MMIC), the complimentary voltages are supplied to the MMIC or generated on the MMIC. If supplied to the MMIC, then twice as many control interfaces are required; one for each control voltage and one for its compliment. If generated on the MMIC, then a foundry process with both enhancement and depletion mode FETs is required or RTL logic must be used. If enhancement and depletion mode is used, then this limits the foundry process selection, which can lead to a severe compromise in RF performance. Additionally, employing RTL logic dissipates DC power. Therefore, it would be desirable to control a FET switch and/or phase-shifter using a single polarity control voltage in order to eliminate the complimentary voltages and associated drawbacks.
One particular type of application employing FET switches are phase shifter circuits, which allow control of insertion phase of a network. They find application in electronic circuitry, such as for example, for shifting the phase of signals propagating on a transmission line. Additionally, phase-shifters on a MMIC typically are designed with switches that require control voltages with complimentary polarity. However, the use of complimentary polarity control voltages adds complexity and the need to provide complimentary voltages to the circuit.
FIG. 1 illustrates a prior art embodiment of a phase-shifter with single pole double throw (SPDT) switches having complimentary control voltages Vcntl and Vcntl*. Furthermore, a reference voltage Vref is used. As shown, the prior art phase-shifter includes both series transistors and shunt transistors. Specifically, phase shifter 100 comprises a first SPDT switch using FETs 106, 108, 110, 112 and a second SPDT switch using FETs 114, 116, 118, 120. In phase shifter 100, control voltage Vcntl is provided to the gate of FETs 106, 110, 114, 118, and complimentary control voltage Vcntl* is provided to the gate of FETs 108, 112, 116, and 120. Moreover, reference voltage Vref is provided to the source-drain terminals of all the FETs.
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