The present invention generally relates to Z-level correction methods in the patterning of integrated semiconductor wafers.
The alignment and patterning of integrated silicon wafers during semiconductor chip manufacturing involves the application, sensing, and imaging of a photosensitive layer (photoresist) over complex underlying topography. Such buried topography usually consists of a multilayer stack that includes metal, dielectric, insulator or ceramic materials and combinations thereof, which are patterned and provide vertical and in-plane functionality to the chip. Photoresist patterning over such a multilayer stack requires wafer pre-alignment and surface level sensing in order to properly determine the focal plane position on the photoimageable layer. For this purpose, a broadband infrared source and photosensor combination is used to determine the focus position for the photoresist surface. In cases where the underlying topography consists of patterned reflective structures, reflection from such buried microstructures can induce an erroneous focal plane determination. Furthermore, in those cases where a sublayer contains a patterned metallic material (e.g., metals such as copper, aluminum, and tungsten), unwanted reflective notching or specular reflectance can also contribute to incorrect height level determination. Such erroneous focus determination results in image blur and poor contrast, which translates into defective image printing.
Proposed Z-leveling correction methods include the use of highly reflective coatings, such as metal layers on top of underlying topography or height-sensitive alignment devices. In the first case, the metallic layer presents an integration problem at the time of manufacturing a functional three-dimensional structure, and thus, is generally not a viable solution. In the second case, a substrate-specific calibration of the optical leveling system is performed, e.g., with AGILE or an offline calibrat ion method (FEM+‘focus mapper’); however, this approach has several drawbacks, including being generally too slow to be performed on every wafer, and within lot (across-wafer and wafer-to-wafer) substrate changes are uncompensated.
Accordingly, there is a need in the art for a Z-leveling correction method which is generally simple to employ, accurate, readily integratable with microelectronic fabrication processes, and which does not suffer from the drawbacks described above.
USPTO Backgrounds
USPTO Backgrounds