1. Field of the Invention
The invention relates to a method for reading out defect information from an integrated memory chip. The invention furthermore relates to an integrated memory chip from which defect information items can be read out.
2. Description of the Related Art
During the fabrication of DRAM memory chips, the occurrence of defects relating to individual memory cells or groups of memory cells is virtually unavoidable. To increase the yield of usable memory chips after the production of memory chips, redundant memory cells are usually provided in the memory chip. After the fabrication of the memory chip, the entire chip, together with the redundant memory cells, is tested, and the memory cells identified as defective are replaced by redundant memory cells.
To replace the defective memory cells, the defective memory cells firstly have to be disconnected in the memory chip, and then redundant memory cells are provided at the corresponding memory address. For this purpose, fuses, i.e., programmable switches, are provided in the memory chip and can be actuated after the completion and prior to fabricating the housing of the memory chip. Laser fuses are usually used, which are severed or not severed in a corresponding laser trimming process with the aid of a laser beam. The information about which of the laser fuses is to be severed or not severed is determined on the basis of defect information items communicated from the respective chip in a test system.
The defect information items indicate the area, i.e., the address, at which a defective memory cell or a defective memory area is situated on the memory chip. The defect information items have to be transmitted from the memory chip to the test system. This transmission of the defect information items requires test time.
It is often the case that individual memory cells are not replaced by redundant memory cells. Rather, redundant memory areas having a plurality of redundant memory cells are provided, which completely replace the corresponding memory area in which a plurality of defective memory cells are present. Redundant word line groups having a plurality of word lines for the replacement of a word line group having one or a plurality of defective memory cells and redundant bit line groups having a plurality of bit lines for the replacement of a defective bit line group are usually provided for this purpose. Thus, for the repair, it is not necessary to know the specific word line from the word lines of a word line group or that the specific bit line from the bit lines of a bit line group on which the defect has occurred, since said group would be replaced by a word line group or a bit line group, respectively, anyway in the event of a defect occurring.
It is generally known to buffer-store defects identified during testing in the memory chip and to transmit them to the test system during or after testing. Since test systems have only a limited number of tester channels, the defect information items should be transmitted via the fewest possible tester channels from the memory chip to the test system, in order that as many memory chips as possible can be tested simultaneously by means of a test system.
Hitherto, a plurality of tester channels have been used for transmitting defect information items. In this case, defect information items are often already compressed internally in the memory chip such that no information required for the repair of the defective memory cells is lost. This is possible, for example, in that the memory cells located on a bit line group can be combined to form a single defect information item and be transmitted as a single defect information item to the test system. In the case of a bit line group having four bit lines, the number of tester channels required can thus be reduced by the factor 4, for example.
It is also possible to process the defect information on-chip and thus identify in the chip which elements have to be repaired. The volume of data which has to be transmitted can thus be reduced. Without increasing the transmission time, the number of channels can be reduced to a single tester channel by means of this method. However, this requires internal logic circuits by which the calculation, which would usually be carried out in the test system, is carried out on-chip. These internal logic circuits require a considerable chip area and are typically dispensed with for cost reasons.
In the context of determining defective memory cells, testing memory cells along a bit line or along a bit line group to find out whether word lines of a word line group that are to be jointly repaired have defects on the same bit line or in the same bit line group has been dispensed with hitherto for time reasons. In order to detect this by means of a simple circuit, it is necessary to effect read-out along the bit line or bit line group. This is very slow, however, since, each time an address is read out, the previous word line has to be deactivated and a new word line activated, which gives rise to a read-out pause. By contrast, reading the memory cells along a word line is fastest since, after the activation of a word line, the memory cells along the entire word line can be read without interruption. To be able to transmit defect data to the test system without relatively long pauses, the read-out of memory cells along a bit line or bit line group is therefore usually dispensed with.
USPTO Backgrounds
USPTO Backgrounds