This invention relates to adders for binary numbers and, more particularly, to a carry chain adder using regenerative push-pull differential logic.
Traditional adders for binary numbers typically add bit pairs sequentially from the least significant bit position to the most significant bit position. Sequential operation is usually necessary because each addition must take into account the possibility of a carry from the previous addition. Consequently, addition of large numbers often takes an excessively long time.
Carry chain adders are frequently used to quickly add two binary numbers without the performance penalty inherent with traditional serial adders. Carry chain adders add subsets of bits at a time, typically one byte of each input number, and each byte addition is performed in parallel with the other byte additions. Of course, each byte addition, in order to be correct, must take into account the possibility of a carry from the previous byte addition in the series. To accommodate the possibility of a carry from the previous byte addition in the series, two parallel additions are performed for each byte of the input numbers. One addition assumes that a carry will be generated from the previous byte addition in the series, and the other addition assumes no carry will be generated from the previous byte addition in the series. By the time the two additions are complete, the existence or nonexistence of a carry from the previous set of additions will be known, and that information may be used by byte carry select circuitry to select the correct result from among the two parallel additions.
Some carry chain adders employ static logic elements which require switching serially connected transistors in order to bring about the desired logic state. This limits the speed at which the circuit may operate and consumes excessive power as some transistors attempt to counteract current flow through other transistors in a crowbar configuration. Other carry chain adders use dynamic logic connected in series, but self-loading of the serially connected logic elements limits the number of dynamic logic elements which may be connected together. For a more detailed discussion of the problems encountered when using known static and dynamic logic elements, refer to copending U.S. patent application Ser. No. 08/121,136, filed Sep. 14, 1993, entitled "CMOS Circuit for Implementing Boolean Functions", incorporated herein by reference.
USPTO Backgrounds
USPTO Backgrounds