This invention relates to latch circuits in integrated circuits, and more particularly, to configurable time borrowing latch circuits and associated circuitry that may be used to help logic designers improve circuit performance.
Integrated circuits typically contain combinational logic and sequential logic. Combinational logic does not include storage elements. The output of a given combinational logic circuit is therefore determined solely by its present inputs. Sequential logic circuits contain storage elements with outputs that reflect the past sequence of their input values. As a result, the output of a sequential circuit is determined by both its present inputs and by the data stored in its storage elements.
Commonly-used sequential circuit storage elements include level-sensitive latches and flip-flops.
In a level-sensitive latch, the latch output is controlled by the level of a clock (enable) input. When the clock is high, the latch output tracks the value of the input. When the clock transitions from high to low, the output state of the latch is frozen at whatever value was present just prior to the transition. So long as the clock is low, the output of the latch will be maintained in its frozen state.
Flip-flops are edge-triggered devices that change state on the rising or falling edge of an enable signal such as a clock. In a rising-edge-triggered flip-flop, the flip-flop samples its input state only at the rising edge of the clock. This sampled value is then maintained until the next rising edge of the clock.
Flip-flop-based logic circuits are often preferred over latch-based circuits, because the regularity imposed by the edge-triggered properties of flip-flops makes circuit timing behavior relatively straightforward to model and hence simplifies design.
However, in a conventional flip-flop-based logic circuit, the clock frequency must generally be slowed down sufficiently to accommodate the delay associated with the circuit's slowest combinational logic paths. Even if circuitry in a fast logic path produces a valid signal in less time than a slow logic path, that signal is not used until the edge of the next clock pulse. While the regularity imposed by conventional flip-flop circuits is beneficial for ease of circuit design, it tends to limit performance in certain situations.
Time borrowing schemes have been developed to try to address this problem. For example, time borrowing schemes have been developed in which various delays are provided in the clocks feeding the edge triggered flip-flops on a circuit. By selecting appropriate delays for the clocks, a circuit designer can configure a logic circuit so that flip-flops in slower paths have their clock edges delayed. This allows time to be borrowed from fast logic paths and provided to slow logic paths, so that the clock speed for the entire circuit need not be slowed to accommodate worst-case delays.
With these conventional time borrowing schemes, it can be difficult to obtain optimal performance due to the limited number of delays that are available from the clock network. Other such schemes for improving timing performance may have limited applicability or require unacceptably complex analysis. For example, time borrowing flip flops have been developed that provide a fixed and relatively small amount of time borrowing. These schemes cannot provide optimal performance in many circuits.
Moreover, conventional time borrowing schemes may be prone to problems associated with race conditions and clock timing issues.
It would be desirable to be able to provide improved time borrowing circuits to optimize circuit performance on integrated circuits such as programmable logic devices.
USPTO Backgrounds
USPTO Backgrounds