1. Field of the Invention
The present invention relates to an electrically data-rewritable nonvolatile semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, an LSI is formed by integrating elements in a two-dimensional plane on a silicon substrate. It is common practice to increase a storage capacity of memory by reducing dimensions of (miniaturizing) an element. However, in recent years, even this miniaturization is becoming difficult in terms of cost and technology. Improvements in photolithographic technology are necessary for miniaturization, but costs required for lithographic processes are steadily increasing. Moreover, even if miniaturization is achieved, it is expected that physical limitations such as those of withstand voltage between elements are encountered, unless the drive voltage and so on are scaled. In other words, there is a high possibility that operation as a device becomes difficult.
Accordingly, in recent years, there is proposed a semiconductor memory device in which memory cells are disposed three-dimensionally in order to increase a degree of integration of memory (refer to patent document 1: Japanese Unexamined Patent Application Publication No. 2007-266143).
One conventional semiconductor memory device in which memory cells are disposed three-dimensionally uses transistors with a cylindrical column-shaped structure (patent document 1). The semiconductor memory device using the transistors with the cylindrical column-shaped structure is provided with multi-layer conductive layers configured to form gate electrodes, and pillar-shaped columnar semiconductor layers. The columnar semiconductor layer functions as a channel (body) portion of the transistors. A vicinity of the columnar semiconductor layer is provided with a memory gate insulating layer. A configuration including these conductive layer, columnar semiconductor layer, and memory gate insulating layer is called a memory string.
The above-described columnar semiconductor layer is constituted by polysilicon and formed from amorphous silicon by subjecting the amorphous silicon to crystallization heat treatment. However, the crystals thus formed easily become minute and increase a cell current value, thereby hindering realization of a speeding up of the memory.
USPTO Backgrounds
USPTO Backgrounds