1. Field of the Invention
This invention relates to a process and a lead frame for making leadless semiconductor packages.
2. Description of the Related Art
Lead frame packages have been used for a long period of time in the IC packaging history mainly because of their low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both a faster speed and a smaller size, the traditional lead frame packages have become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array Packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice.
However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a solution for chip scale and low profile package due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both the footprint and the package profile can be greatly reduced. Due to the elimination of the outer leads, leadless packages are featured by lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
FIGS. 1–2 show a conventional leadless package 10 including a chip 12 disposed on a die pad 11b sealed in a package body 13. The chip 12 is provided with a plurality of bonding pads electrically connected to leads 11a. The leads 11a are exposed from the lower surface of the package body 13 for making external electrical connection.
However, the conventional leadless package 10 has various design and production limitations. For example, in order to reduce the size of the package while not increasing the number of I/O connections or to increase the number of I/O connections while not increasing the package size, the density of the leads 11a should be increased since the leads 11a are only arranged about the lateral periphery of the package 10. This is especially apparent when the chip 12 has high density and high frequency digital circuitry. Such an increase in the density of leads inherently requires a reduced pitch or spacing between adjacent leads thereby increasing likelihood of cross-talk and signal interference and making such packages more difficult to fabricate.
USPTO Backgrounds
USPTO Backgrounds