Field of the Invention
The present invention relates to a semiconductor device applying a so-called WL-CSP (Wafer Level-Chip Size Package) technology.
Description of Related Art
With the recent making of semiconductor devices more advanced in function and multifunctional, practical use of WL-CSP technology is progressing. With a WL-CSP technology, a packaging process is completed in a wafer state, and a size of each individual chip cut out by dicing becomes a package size.
FIG. 4 is a schematic sectional view of a structure of a semiconductor device to which a WL-CSP technology is applied.
The semiconductor device 101 includes a semiconductor chip (not shown) making up a base thereof. An interlayer insulating film 102 made of SiO2 (silicon dioxide) is formed on the semiconductor chip. A wiring 103 made of Al (aluminum) is formed in a predetermined wiring pattern on the interlayer insulating film 102. A passivation film 104 made of SiN (silicon nitride) is formed on the interlayer insulating film 102 and the wiring 103. An opening 105 for exposing a portion of the wiring 103 from the passivation film 104 is formed in the passivation film 104.
A barrier film 106 made of Ti (titanium) is formed on a portion of the wiring 103 facing the opening 105. A peripheral edge portion of the barrier film 106 rides on the passivation film 104. A post bump 107 made of Cu (copper) is formed on the barrier film 106. A side surface of the post bump 107 is flush with a side surface of the barrier film 106. A solder ball 108 is formed on the post bump 107. The solder ball 108 is an external terminal connected to an external wiring on a wiring substrate. By the solder ball 108 being connected to the external wiring on the wiring substrate, electrical connection of the wiring 103 and the external wiring is achieved and the semiconductor device 101 is supported on the wiring substrate.
With such a structure, when an external force is applied to the solder ball 108, stress concentrates at the peripheral edge portion of the barrier film 106 and the post bump 107. By the concentration of stress, a crack may form in the passivation film 104 positioned immediately below the peripheral edge portion of the barrier film 106.
To prevent crack formation in the passivation film 104, forming of a polyimide layer having a penetrating hole in communication with the opening 105 on the passivation film 104 and positioning of the peripheral edge portion of the barrier film 106 on the polyimide layer may be considered. Because the polyimide layer is interposed between the peripheral edge portion of the barrier film 106 and the passivation film 104, even when stress concentrates at the peripheral edge portions of the barrier film 106 and the post bump 107, the stress is absorbed by the polyimide layer and is not transmitted to the passivation film 104. Crack formation in the passivation film 104 can thus be prevented.
However, because a step of forming the polyimide layer must be added, a number of manufacturing steps of the semiconductor device 101 is increased and this causes increase in manufacturing cost. Also, the polyimide layer must be formed to an adequate thickness capable of absorbing the stress. Thus, there is an issue of increase in thickness of the semiconductor device 101.
USPTO Backgrounds
USPTO Backgrounds