The present invention relates to a semiconductor device, and a manufacturing method of the same, in particular, semiconductor device having a slit made over a main surface of a semiconductor substrate so as to surround an element formation region for the purpose of preventing an interlayer dielectric, an interconnection and some other from being peeled or cracked, and a method useful for manufacturing the device.
For example, Japanese Unexamined Patent Publication No. 2007-115988 (Patent document 1) discloses a semiconductor device having the following members: an interlayer dielectric in which a first non-low-k film having a dielectric constant larger than 3.5, a low-k film having a dielectric constant of 3.5 or less, and a second non-low-k film having a dielectric constant larger than 3.5 are successively laminated upwards; a sealing formed to surround an element formation region; a trench pattern arranged outside the sealing and made in the second non-low-k film; and a passivation film covering the inner walls of the trench pattern.
Japanese Unexamined Patent Publication No. 2006-140404 (Patent document 2) discloses a semiconductor device having a low-dielectric-constant film inside which a copper interconnection is formed, an interlayer dielectric arranged over the low-dielectric-constant film, a surface protecting film arranged over the interlayer dielectric, a sealing formed to surround the circumference of a circuit formation region, and a trench which is made outside the sealing as viewed from the above, in which the bottom of the trench is formed above the low-dielectric-constant and below the upper end of the copper interconnection.
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