In general, memory devices such as a Flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped, deeply diffused region and a more heavily doped, shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a "stacked gate" structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as "contacts", must be made to connect the stack gated structure, the source region and the drain regions to other parts of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. A liner material, typically a high temperature oxide (HTO), is then formed over the entire substrate, including the stacked gate structure. A dielectric layer, generally of oxide, is then deposited over the etch stop layer, and a layer of photoresist is placed over the dielectric layer and photolithographically processed to form the pattern of contact openings. Then an anisotropic etch is used to etch out portions of the dielectric layer to form gate, source and drain contact openings in the dielectric layer. The contact openings stop at the source and drain in the substrate, and the gate contact openings stop at the silicide layer on the stacked gate structure. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer to fill the gate, source and drain contact openings. The substrate is then subjected to a chemical-mechanical polishing (CMP) process, which removes the conductive material above the dielectric layer to form the contacts through a contact CMP process.
For miniaturization, it is desirable to dispose adjacent stacked gate structures as closely together as possible. In the conventional process, the formation of the contact mask does not require the use of an anti-reflective coating (ARC) on the dielectric layer. An ARC is typically formed of a material such as silicon oxynitride or silicon nitride and is used for enhancing the imaging effect in subsequent photolithography processing associated with the formation of a contact mask. When the contact size is less than or equal to 0.35 micron, an ARC must be used to meet the increasingly critical dimension requirement of such devices.
One significant problem with using an ARC on the dielectric layer is that after the formation of conductive contacts, the ARC layer needs to be removed in order for the ultraviolet erase process to work on the Flash memories. The CMP removal of the ARC will also remove portions of the conductive contacts as well as the dielectric layer, producing deep scratches therein. The scratches vary significantly from cell to cell, creating non-uniformity and adversely affecting device performance. Attempts have been made to develop an etch chemistry that is more selective so that it etches the ARC at a much higher rate than the conductive contacts and the dielectric layer.
A solution, which would selectively remove the ARC from the surface of a dielectric layer over the surface of a substrate for 0.35 micron or sub-0.35 micron devices without scratching the dielectric layer and/or conductive contacts formed therein, has long been sought, but has eluded those skilled in the art. As miniaturization continues at a rapid pace in the field of semiconductor, it is becoming more pressing that a solution be found.
USPTO Backgrounds
USPTO Backgrounds