In fabrication of semiconductor memories, one technique utilized to increase production yield is to provide redundant circuits on the chip to allow for replacement of key circuits which prove defective. During testing of the chip, the defective portion of the circuit is identified and the redundant circuit, if one exists, is activated by opening an associated fuse or similar mechanism. The disadvantage to this technique is that only certain circuits on the chip can be given redundancy, which is sometimes impractical from a cost versus yield standpoint.
Redundancy is especially suited for repetitive circuits having a large number of repeating elements arranged in some form of an array, such that one redundant circuit can replace a single defect in any of a large number of circuit elements. One such device is a semiconductor memory comprised primarily of memory elements. These memory elements are arranged in rows and columns wherein the redundant element would be either a row of memory elements or a column of memory elements. If, for example, one element in a given column was determined to be defective, this would classify the device as defective. This defective column could then be replaced by a redundant column and the device would be fully operational. A typical memory would have, for example, 256 rows and 256 columns. One redundant column would therefore be able to replace one of the 256 columns, thus constituting an efficient use of a redundant circuit.
One problem encountered in replacing a column or row in a semiconductor memory is maintaining address integrity; that is, the redundant column must have the same address as the defective column. This is normally implemented by providing a universal decode circuit in association with the redundant column circuitry. Appropriate fuses are included that can be opened to both activate the redundant column circuitry and also program the universal decode circuitry for the appropriate address. One disadvantage to this type of circuitry is that the actual physical sequence of columns with the redundant circuitry activated is different than that with the redundant circuitry being inactive. For example, if the redundant column were placed parallel to the memory array and the 64th column were determined to be defective, this column would be inactivated and the redundant column activated and programmed for an address corresponding to the 64th column. However, the redundant 64th column would now be physically outside of the array rather than between the 63rd and 65th columns. In some applications, this would require additional circuitry to maintain the sequential nature of the memory output.
One application which requires the outputs of the memory array to be in a predetermined sequence is a video Random Access Memory (RAM). In the video RAM, the memory elements are arranged such that they are directly mapped to the pixel location on a display. Addressing of a single row of memory elements in the video RAM outputs data corresponding to a group of adjacent pixels. This data is output in parallel and loaded into a serial shift register having a length equal to the number of columns in the array. This data is then serially output from the shift register to place a sequence of adjacent pixels on the display for a given scan line. The length of the shift register and the corresponding number of columns in the array may be sufficient to supply all of the pixels in a given line or, alternatively, the number of rows of memory may be required to define a given scan line.
By utilizing the serial shift register, the rate at which the pixel elements are displayed on the screen can be much higher than the rate at which the memory is addressed. For example, for a memory array with 256 columns, data will be loaded into a 256 element shift register. Once addressed and loaded into the shift register, the data is then serially output to the display. New data is then loaded in the shift register. Since it requires 256 clock cycles to shift out all of the data in the serial shift register prior to reloading, the rate of the shift register clock as compared to the addressing sequence can be up to 256 times greater.
In replacing a defective column in a video RAM, it is necessary that the output of the redundant column have the same address as the defective column and also have the output loaded into the shift register at the same physical location as that of the output for the defective column. By utilizing conventional redundant circuitry techniques and merely changing the address for the redundant column, this would require additional circuitry to feed the output of the redundant column to the appropriate one of the shift register inputs. Since the redundant column must be universal, it would be necessary to provide circuitry that would allow for interface of the output with each of the shift register inputs. This would require a large amount of circuitry which would present a significant disadvantage.
In view of the above disadvantages, there exists a need for redundant column circuitry for a video RAM to both replace a defective column and to insert the output of the redundant column into the physical sequence of outputs from the memory array such that the integrity of the physical sequence is maintained.
USPTO Backgrounds
USPTO Backgrounds