1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory, and more particularly to a novel nonvolatile memory integrated circuit architecture and related method for providing access to program data during programming of a nonvolatile array of the memory.
2. Description of the Related Art
Nonvolatile semiconductor memory arrays retain stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. Many different types of nonvolatile semiconductor memory devices are known, including a class of single transistor devices that are based on the storage of charge in discrete trapping centers of a dielectric layer of the structure, and another class of devices that are based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide. Stored charge typically is in the form of electrons, which typically are removed from the charge storage structure using the Fowler-Nordheim mechanism to achieve one state, typically called an erased state, and which typically are injected into the charge storage structure using the Fowler-Nordheim (xe2x80x9cFNxe2x80x9d) mechanism, the channel hot electron (xe2x80x9cCHExe2x80x9d) mechanism, the channel induced secondary electron injection (xe2x80x9cCHISEIxe2x80x9d) mechanism, or the source side injection (xe2x80x9cSSIxe2x80x9d) mechanism to achieve another state, typically called a xe2x80x9cprogrammedxe2x80x9d state. Techniques are also known for achieving multiple bit storage in a single transistor nonvolatile memory cell by programming the multiple bits into a memory cell as different voltage levels.
Nonvolatile memory arrays have been used in a variety of different memory integrated circuit architectures. In one type of common memory architecture, the nonvolatile memory array is of the FN/FN type, and uses the Fowler-Nordheim mechanism for both erase and programming. The nonvolatile memory array is programmed from a page of latches, which are part of the memory array input and are used during page mode programming of the nonvolatile memory array to drive a fill page of program data onto the column lines of the nonvolatile memory array for programming into a selected page of memory cells of the nonvolatile memory array. The nonvolatile memory array is read using sense amplifiers, which are part of the memory array output and are used to read the values stored on selected memory cells of the nonvolatile memory array. The latch typically is bypassed by data that is read out of the nonvolatile memory array.
A different memory architecture known as a program/program verify architecture is disclosed in Tomoharu Tanaka et al., xe2x80x9cA Quick Intelligent Program architecture for 3Vxe2x80x94only NAND-EEPROMs,xe2x80x9d Symposiun on VLSI Circuits Digest of Technical Papers, 1992, pp. 20-21. The architecture uses a NAND array as its memory array, but access to the memory array is not through an input/output circuit. Instead, each of the data bit lines (to be distinguished from the dummy bit lines) of the memory array is connected to a respective volatile memory element called a read/write (xe2x80x9cR/Wxe2x80x9d) circuit. Each R/W circuit acts like a flip-flop type differential sense amplifier in read operation and as a data latch circuit in program operation, thereby providing a fully functional volatile memory element that eliminates the need for separate and dedicated latches and sense amplifiers. A page of such volatile memory elements is provided, so that external page read and write operations are performed not on the memory array itself, but rather on the page of volatile memory elements. Pages of data are transferred between the nonvolatile memory array and the volatile page memory along the bit lines, as required for programming, for a verify read, and for a regular read.
A further advantage of the Tanaka et al. architecture is that as fully functional volatile memory elements, the R/W circuits are used for automatic program verify to verify that all programmed cells have approximately about the same high threshold voltage VTH. The program-verify process begins with a write to the nonvolatile memory. To accomplish this, a page of program data is loaded into the R/W circuits and a page of the nonvolatile NAND memory array is programmed from the R/W circuits. The NAND memory array is erased prior to programming, so that the cells begin in a low threshold voltage state. For purposes of programming, xe2x80x9c0xe2x80x9d data is represented by 8 volts on the bit line node of the R/W circuit, while xe2x80x9c1xe2x80x9d data is represented by 0 volts on the bit line node of the R/W circuit. Next, the R/W circuit is coupled to the bit line BLa and the complement (dummy) bit line BLb and 18 volts is applied to the control gate of the selected transistor. For 0 data, the 8 volts on the bit line prevents tunneling in the selected transistor, which remains at low VTh. For 1 data, the 0 volts on the bit line allows tunneling to occur in the selected transistor, which raises the VTh thereof. Hence, a low VTH charge state is found in an erased or incompletely programmed cell, and a high VTH charge state is found in a satisfactorily programmed cell.
The program-verify process includes a read-verify operation, which begins with precharging the bit and bit complement lines. If a cell stores completely programmed xe2x80x9c1xe2x80x9d data, its high VTH does not permit it to pull down the bit line, which remains high. On the other hand, if a cell stores 0 data or incompletely programmed data, its low VTH allows it to pull down the bit line.
Next, the charge state of each bit line is adjusted based on the value stored in the R/W circuit to distinguish between xe2x80x9c0xe2x80x9d data and incompletely programmed data, and the charge state of the bit line is sensed by the R/W circuit. On the first pass, the value stored in the R/W circuit is program data and during subsequent passes it is verify data. In either case, a high voltage on the bit line node of the R/W circuit indicates xe2x80x9cno programxe2x80x9d because the cell is either erased or fully programmed. If the cell is erased, the bit line is pulled down at first but is recharged by the verify circuit. If the cell is completely programmed, the bit line remains high and is not affected by the verify circuit. The high voltage on the bit line then is read by the R/W circuit, which stores the xe2x80x9cno programxe2x80x9d message for the next pass. On the other hand, low voltage on the bit line node of the R/W circuit indicates xe2x80x9cprogramxe2x80x9d and defeats the verify circuit, so that the charge on the bit line controls. If the cell is not completely programmed, the bit line is pulled down and the low voltage is read by the R/W circuit, which stores a xe2x80x9cprogramxe2x80x9d message for the next pass. If the cell is completely programmed the bit line is high and is read by the R/W circuit, which stores a xe2x80x9cno programxe2x80x9d message for the next pass.
The values in each of the R/W circuits is monitored and the program-verify stopped when all cells are properly programmed. This happens when the bit line nodes of all of the R/W circuits store a high voltage or a logical xe2x80x9c1xe2x80x9d value.
Unfortunately, the volatile memory formed by the R/W circuits is not independent of the program operation. Program data placed in the R/W circuits for programming to the nonvolatile memory array is destroyed during the program-verify operation, and is therefore unavailable from the R/W circuits after the first verify-read. While the program data can be recovered from memory simply by reading it into the R/W circuits from the memory array after completion of the program-verify operation, disadvantageously the program data is not available from the R/W circuits during programming of the nonvolatile memory array. This situation is illustrated in FIG. 1, which generally shows the timing of a sequence of paired programming and verify read operations 10, 20, 30, 40, 50 and 60, followed by a standard read operation 70. The number of programming and verify read operations during any given program-verify operation is variable depending on the condition of the memory cells in the nonvolatile memory array. As shown in FIG. 1, the volatile memory formed by the R/W circuits is indicated as being BUSY during the entire program-verify operation, as well as during the standard nonvolatile memory read that follows.
In memory integrated circuits, it would be desirable to have page mode programming with program-verify of the type that uses a verify read to nonvolatile memory, even while maintaining the original program data in nonvolatile memory. It would further be desirable, in some embodiments of such memory, to have the program data fully available externally even during page mode programming.
The disadvantages described above and other disadvantages are overcome individually or collectively in one or more of the various embodiments of the present invention. One embodiment of the present invention is an integrated circuit memory comprising a nonvolatile memory array programmable in a page mode; a first memory connected to the memory array, the first memory being volatile memory and of a size sufficient to hold a page of data, and having a program latch capability, a sense amplifier capability, and a verify read capability; a second memory coupled to the first memory, the second memory being volatile memory and of a size sufficient to hold a page of data, and having a buffer capability; and an input/output circuit coupled to the second memory to provide access to the second memory externally of the integrated circuit memory.
Another embodiment of the present invention is an integrated circuit memory comprising; a nonvolatile flash memory array comprising a plurality of single transistor floating gate memory cells, the memory array being programmable in a page mode; a gate circuit for providing a page of simultaneous connections to the flash memory array-during flash memory array program operations and a plurality of successive simultaneous fractional page connections during flash memory array read operations; a volatile utility memory of a size for holding a page of data, the utility memory being connected to the memory array by the gate circuit; a plurality of volatile SRAM buffers, each being of a size for holding a page of data; an input/output circuit; and a plurality of data cells having respective first byte inputs and first byte outputs respectively coupled to the SRAM buffers. Each of the data cells further comprises a second byte input coupled to the utility memory; a second byte output coupled to the utility memory; a shift register having a bit serial input coupled to the input/output circuit, a bit serial output coupled to the input/output circuit, a byte input, and a byte output; a comparator coupled to the first and second byte inputs and having a byte output for providing comparison bits, the byte input of the shift register being coupled to the byte output of the comparator; and a program verifier coupled to the second byte input and having a byte output for providing program verify bits. The memory farther comprises a zero detector having an input coupled to the byte output of the program verifier and having a flag output coupled to the input/output circuit.
Another embodiment of the present invention is a method of writing a page of write data to an integrated circuit nonvolatile memory comprising writing the write data to a page of buffer memory; writing the write data from the buffer memory to a page of utility memory without disturbing the write data in the buffer memory, the utility memory having a latch capability and a verify read capability; programming the write data from the utility memory into a page of a nonvolatile memory array utilizing the latch capability of the utility memory; reading the page of the nonvolatile memory array utilizing the verify read capability of the utility memory to provide verify data in the utility memory; programming the verify data from the utility memory into the page of the nonvolatile memory array utilizing the latch capability of the utility memory when the verify data in the utility memory indicates that programming is incomplete; rereading the page of the nonvolatile memory array utilizing the verify read capability of the utility memory to refresh the verify data in the utility memory in response to the verify data programming step; and ceasing programming of the nonvolatile memory when the verify data in the utility memory indicates that programming is complete.
Another embodiment of the present invention is a method of writing a page of write data to an integrated circuit nonvolatile memory comprising writing the write data to a page of buffer memory; writing the write data from the buffer memory to a page of utility memory without disturbing the write data in the buffer memory, the utility memory having a latch capability and a verify read capability; programming the write data from the utility memory into a page of a nonvolatile memory array utilizing the latch capability of the utility memory; reading the page of the nonvolatile memory array utilizing the verify read capability of the utility memory to provide verify data in the utility memory; programming the verify data from the utility memory into the page of the nonvolatile memory array utilizing the latch capability of the utility memory when the verify data in the utility memory and the write data in the buffer memory indicate that programming is incomplete; re-reading the page of the nonvolatile memory array utilizing the verify read capability of the utility memory to refresh the verify data in the utility memory in response to the verify data programming step; and ceasing programming of the nonvolatile memory when the verify data in the utility memory and the write data in the buffer memory indicates that programming is complete.
USPTO Backgrounds
USPTO Backgrounds