Computer memory can be addressed in multiple ways. One model is sometimes referred to as a flat model, in which the memory is considered a single block, or segment, of memory locations. The segment is generally treated as a single long line of memory locations. When a processor accesses a memory location, the processor generally uses an offset from the beginning of the segment to address the desired memory location. The offset is often referred to as an effective address. The processor then reads or writes to a specified number of memory locations starting from the offset address (from the effective address).
Another memory model uses multiple segments. In that case, the processor uses a segment identifier, along with the offset, to address a desired memory location. Under that model, the address of a certain location in a certain segment is generally referred to as the logical address. Older software is often based on logical addresses for multiple segments of memory. Newer software is often based on the flat memory model. It is desirable for a processor to support both models so that older and newer software can run on the processor.
One way to support both models is to define a memory address as a segment base address plus the effective address, but set the segment base address to zero when the processor is executing software that is based on the flat model. X86 processors generally provide this support. These processors generally refer to the resulting memory address as the linear address. Note that the terms “linear address” and “logical address” generally define the same calculation for a memory address, but the term “linear address” is used herein, because the segment base address can be zero. However, this method requires adding the segment base address for every address calculation.
The speed of loading or storing data depends on the speed of calculating the linear address. In current x86 processors, the linear address is determined by adding the segment base address as an operand to operands of the effective address. Thus, even when the segment base operand is zero (e.g., when newer software is executed), the segment base operand takes up computing resources, and slows determination of a linear address.
This is exacerbated if a memory misalign occurs when trying to access a set of memory locations that wrap from one memory line to another memory line. In that case, two addresses must be calculated. It is desirable to provide a processor that supports older software, but minimizes the time and resources needed to determine memory addresses and to handle memory misaligns.
USPTO Backgrounds
USPTO Backgrounds