An integrated circuit chip (hereinafter referred to as an “IC” or “chip”) includes cells and inter-cell connections supported by a substrate. A cell is a group of one or more circuit elements, such as transistors, capacitors, resistors, and other basic circuit elements grouped to perform functions, both arithmetic and logical.
On an IC, each cell may include one or more pins, which in turn may be connected to one or more pins of other cells by wires or wire traces. A net comprises circuitry coupling two or more pins. A typical IC includes a large number of cells and requires complex wire interconnections between the cells. A typical chip has thousands, tens of thousands or even hundreds of thousands of pins, which are connected in various combinations.
Signal buses are formed on the IC to carry data and control signals between various circuit elements. Signal buses may be composed a plurality of wires. Metal layers, separated by layers of insulator material, are configured to define circuit routing wires for connecting various elements of the IC. Usually, certain metal layers are dedicated to horizontal routing wires and other metal layers are dedicated to vertical routing wires. For example, horizontal routing wires may be formed on even numbered metal layers, while odd numbered metal layers are dedicated to vertical routing wires. Metal posts or channels called “vias” between horizontal and vertical routing wires provide connections between them so that signals and power can propagate through the IC.
In general, cells are organized into functional modules, which are then placed within a layout pattern for the IC. Each module has a fixed width and a variable height and contains input and output pins. Each pin is assigned to one of two opposite sides of the module and is arranged at a given coordinate within the layout pattern, such as a horizontal coordinate (x) and/or vertical coordinate (y) on an x-y axis. Output pins are assigned to one or more input pins of other cells in the layout pattern, and both input and output pins are electrically connected to pins of other cells in the layout pattern through one or more conductive segments that define a “net” or “wire”.
One continuing problem associated with IC design is to place cells within a module in an optimal arrangement and to allow for efficient routing through the module. This is particularly true for high density modules such as Redundant Random Access Memory (RRAM) configuration modules.
There is an ongoing need in the IC design art for systems and algorithms for optimizing cell placement in density-driven layouts.
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