The present disclosure relates to voltage reference circuits, and in particular, although not necessarily, to band-gap voltage reference circuits.
FIG. 1 shows an example of a band-gap voltage reference circuit 100 comprising a first diode 110 (D1), a second diode 112 (D8), a first resistor 114 (R1) and an amplifier 120. The amplifier 120 has two input terminals, a first input terminal 122 and a second input terminal 124, and an output terminal 126. The output terminal 126 provides a reference-voltage-output-signal (which will also be referred to as an output voltage (Vout)), which is the output signal of the band-gap voltage reference circuit 100. This band-gap voltage reference circuit 100 topology uses two branches of input components, one for each of the input terminals, 122, 124, to bias the first diode 110 and the second diode 112, respectively. This voltage biasing creates a potential difference (ΔVD) across the first resistor 114 (R1). The amplifier input terminals are connected at about Vout/2 (at 25 C). The output voltage is approximately 1.2V. The amplifier 120, which does not have a common mode potential difference between the first input terminal 122 and the second input terminal 124, therefore needs a supply voltage that is higher than the output voltage Vout. The supply voltage is provided to the amplifier 120 by the voltage supply terminal (Vsup) 128.
The amplifier 120 is a zero voltage DC offset amplifier. Therefore, for the circuit shown in FIG. 1, the voltage levels at the first input terminal 122 and the second input terminal 124 will be approximately equal. The 0 DC offset amplifier brings its own error at the ΔVbe error. That is, there will be a voltage error between the first input terminal 122 and the second input terminal 124 because of the input components of the amplifier 120, but without a DC value. The voltage error may arise from finite manufacturing tolerances, for example, that result in a time-varying offset voltage being slightly different to zero. This results in more offset error, and so the natural standard deviation of the band-gap value in production will be higher. Also, the first diode 110 (D1) and the second diode 112 (D8) will introduce an error to the DC value of ΔVD.
A first equation that describes the operation of the circuit of FIG. 1 is shown below.Vout=VD8+[1+(R2/R1)]ΔVD 
The first equation describes the relationship between the output voltage Vout, the voltage ΔVD across the first resistor 114 and the voltage VD8 across the second diode 112, in terms of the resistance R1 of the first resistor 114 and the resistance R2 of a second resistor 116 also present in the circuit 100.
A second equation, which defines the error in the voltage across the first resistor 114 (error(VR1)), is:error(VR1)=[(σΔVD)2+(σVoff)2]1/2/(ΔVD+0)Where:
ΔVD is the voltage across the first resistor 114,
σΔVD is the standard deviation error of the voltage across the first resistor 114 (ΔVD), and
σVoff is the standard deviation error of the offset voltage between the first 122 and second 124 input terminals.
In the second equation, a zero is shown in the denominator. This zero is shown to reflect the voltage offset having a zero value. Therefore, there is no voltage offset to contribute to any reduction in the overall percentage voltage error.
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