The present invention relates generally to the multiplication and clamping prediction of fixed-point multipliers. More particularly, the invention relates to a method and apparatus for increasing the speed of fixed-point data paths that involve multiplication of operands and parallel overflow detection and clamping based upon the magnitude of those operands.
Electrical circuits are routinely employed to perform arithmetic operations of operands represented by logical representations. Generally, it is desirable for arithmetic circuitry, and in particular multiplication circuitry, to have the fewest number of bits in order to perform the required calculations. Minimization of the required number of bits facilitates speed of the calculating circuit. However, counter-balancing the desire to have a limited number of bits to perform a given calculation is to avoid answer overflow. Overflow, or the situation in which an answer will exceed the number of bits designed for the answer, is not acceptable, as valuable valid data may be lost in performing the calculations. In circuits that perform calculations with a number of bits that may yield answers that overflow the set number of bits, clamping can be used to ensure that a result that overflows is clamped to a given acceptable value. Normally, the largest magnitude positive or negative representable number is employed as the overflow value. While the employment of a clamping operation is not always desirable, it is generally considered to be better than an overflow which may cause wrapping or undesired bits stored in the particular multiplication circuitry.
Typically, when clamping is desired, it is performed in a sequential fashion. In other words, the arithmetic operation is performed first, and when the result is available, it is then analyzed for overflow. If clamping is required, a clamping value replaces the computed value.
Referring now to FIG. 1, a prior system illustrates the serial processing in which the clamping analysis follows multiplication of particular operands. In this instance, operand 1 (reference numeral 2) and operand 2 (reference numeral 4) are input into an arithmetic operator 6. The output 8 from the arithmetic operator 6 is then directed into the overflow detection scheme 10. Any delays between arithmetic operator 6 and the overflow detection 10 are compounded, with each of their respective delays adding to the overall circuit delay. The clamp value 12 as determined by the overflow detection 10 is input along with the result 14 of the arithmetic operation 6, and a preset clamp value 16 into multiplexer 18. Multiplexer 18 selects the operation result 14 or the preset clamp value 16 in the instance of overflow detection based upon the logical level of clamp bit 12. The result is then output into register 20.
A major problem with sequential operation is that any delays, for both the arithmetic operation and the overflow analysis, tend to compound and therefore yield a relatively slow circuit to the extent that all delays are combined and added together to determine the total circuit delay. In any arithmetic operation, multiplication delays tend to be the largest. Therefore, there exists a need to implement a circuit and method in which arithmetic operations such as multiplication may be performed along with overflow detection. The result is a circuit that eliminates the compounded delay made up of the accumulation of each individual delay associated with sequential overflow analysis and operand processing.
USPTO Backgrounds
USPTO Backgrounds