1. Field of the Invention
The invention relates to a method of producing a wiring board and, particularly, to a method of producing a wiring board in which a plurality of wiring layers, each being located on an electrical insulation layer, are formed.
2. Description of the Related Art
Among wiring boards used for mounting semiconductor devices thereon, there are products formed by a build-up process in which a plurality of wiring layers, each being located on an electrical insulation layer, are laminated. For the formation of the wiring layers, a resin material having an electrical insulation properties, such as a polyimide or epoxy, is coated on a substrate, or a resin film having an electrical insulation property is pressed on and adhered to a substrate, to thereby form an electrical insulation layer, after which a conductor layer is formed on the surface of the insulation layer through plating or the like. The conductor layer on the insulation layer can be then etched to provide a wiring layer having a certain pattern.
FIG. 5 shows an example of wiring board in which a wiring layer 14 is formed on an insulation layer 12 provided on each of surfaces of a core substrate 10, with the wiring layer 14 being formed by etching a conductor layer located on the insulation layer 12.
When a conductor layer is formed on the surface of an insulation layer by plating, it is conventional that the surface of the insulation layer is roughened (a desmear process) in advance of a plating process, in order to enhance the adhesion of the plated conductor layer to the surface of the insulation layer. The roughening is effected by etching the surface of the insulation layer (resin layer) using an etchant, such as potassium permanganate or sodium permanganate.
FIG. 6 is an enlarged cross sectional view schematically showing the surface of an insulation layer 12 roughened using an etchant. As seen in the drawing, a conductor is filled in surface pores or concavities of the insulation layer 12 formed by the roughening and, consequently, a patterned wiring layer 14a is intimately adhered to the insulation layer 12 through an anchor effect.
Nevertheless, in the case where a roughness of the surface of the roughened insulation layer is large, the surface roughness has an effect, during the formation of a conductor pattern by the etching of a conductor layer, on a precision of the conductor pattern, giving rise to problems, such as failure to create a very small wiring pattern with high precision.
FIG. 7 is a graph in which penetration of an etchant, during the patterning of a conductor layer by etching to form wiring lines, into the interface between an insulation layer and a patterned wiring line and measured from a side of the wiring line, is plotted versus a line space, as a function of a ten-point average surface roughness, Rz, of the insulation layer. The Rz is measured according to JIS B 0601. The drawing reveals that the larger the surface roughness of the insulation layer, the larger the penetration. Thus, when the insulation layer has large surface pores, an etchant tends to penetrate into the interface between the insulation layer and the patterned wiring line via the surface pores of the insulation layer, during the formation of the patterned wiring lines by etching, causing the wiring lines having raised sides. Consequently, in the case of large surface roughness of the insulation layer, it is difficult to obtain a small and fine wiring pattern.
The increase in the surface roughness of an electrical insulation layer causes a problem of an increase in high-frequency signal transmission loss in view of the electrical properties of a wiring board. FIG. 8 shows graphs of calculated results of the change in high-frequency signal transmission loss depending on the surface roughness Ra (center-line average roughness) of an insulation layer. The calculation was based on a width of wiring pattern of 20 micrometers, a thickness of insulation layer of 12 micrometers, a length of wiring line of 30 millimeters, and a dielectric constant of 3.4. The graphs reveal that the smaller the surface roughness of the insulation layer, the smaller the transmission loss.
On the other hand, the increase in the surface roughness of an insulation layer lowers the migration resistance of a wiring board. It is preferred for the insulation layer to have as a small surface roughness as possible. Thus, a technique which enables an insulation layer to have a small surface roughness, and the adhesion between an insulation layer and a conductor layer to be improved, is in demand.
As a method improving the adhesion between an insulation layer and a conductor layer, a method in which an insulating surface of a substrate is subjected to a plasma treatment, ion beam radiation, or ultraviolet radiation, is known (JP-A-11-214838, etc.). This technique improves the adhesion between an insulation layer and a wiring layer. The present invention provides a wiring board by forming a conductor layer by electroless plating and electroplating with copper, in order to improve the electrical properties of the wiring board. Since plated copper has a small adhesion to a resin material compared to plated nickel and others, plated copper is required to have a much stronger adhesion to an insulation layer when it is used to form a conductor layer.
The invention relates to a method of producing a wiring board in which a plurality of wiring layers, each being located on an electrical insulation layer, are formed.
An object of the invention is to provide a method of producing a wiring board in which, for the formation of a conductor layer on the insulation layer by electroless plating and electroplating thereof with copper, the surface roughness of an electrical insulation layer can be kept small, the adhesion between the insulation layer and the conductor layer can be satisfactory so as to enable a very fine pattern to be produced, and the wiring board has excellent electrical properties.
According to the invention, there is provided a method of producing a wiring board having a plurality of wiring layers each being located on an electrical insulation layer, in which an electrical insulation layer is formed on a substrate using a resin material, and a conductor layer is formed on the surface of the electrical insulation layer by successive electroless plating and electroplating with copper, and is patterned to form a wiring layer, wherein, after the formation of the electrical insulation layer on the substrate, the electrical insulation layer is subjected to a plasma treatment and a subsequent ultraviolet treatment, and the electroless plating and the electroplating are then performed.
It is preferred that the resin material for the formation of the electrical insulation layer comprises a nitrogen-containing compound, in that it improves the adhesion of the insulation layer to copper.
It is preferred that the electrical insulation layer after the plasma and ultraviolet treatments has a surface roughness Rzxe2x89xa61 micrometer.
USPTO Backgrounds
USPTO Backgrounds