The field of my invention relates to a fail-safe decoder for digital track circuits. More particularly, the invention pertains to fail-safe decoding apparatus for audio frequency track circuits in which a section-identifying comma-free code is transmitted through the rails of each section to provide train detection.
As more sophisticated train and/or traffic control systems are planned for railroads, the track rails, in addition to train detection and control, are used for communication purposes and information sources such as train-to-wayside communication and distance traveled or specific train location indications. Where alternating current track circuits are used, particularly in the audio frequency range, the amount of other apparatus connected to the railroad track may become so great that the track circuit transmitter carrier frequency alone cannot guarantee that a track receiver responds only to the correct transmitter. One possible solution is that each transmitter send a unique digital code capable of being detected only by its companion receiver. If there are 100 unique codes available, then the amount of apparatus connected to the track can be increased by about an order of magnitude over what can otherwise be safely used. One form which the transmitted digital codes may take is the so-called comma-free code (CFC) type in which each code comprises a continuouous and repetitive stream of digital bits (1 and 0) automatically divided into words without requiring word synchronizing signals. One definition of comma-free codes is that no overlap portion of two successive code words, even identical code words, can also be a separate code word. To meet these requirements, only a relatively few words are usable of the total combinations available in accordance with the selected word length, that is, the number of bits per word. The consequence of this is that all rotated versions of a selected code word are excluded from the dictionary of usable words but may be assigned the same meaning as the basic word from which they develop. For example, a practicable system using 10 bit words has only 99 usable comma-free words. If such codes are used in a track circuit arrangement, a failsafe decoder is then required at the receiver end of the section to assure that only the reception of the proper code word is registered as an unoccupied track section.
Accordingly, an object of my invention is fail-safe decoder apparatus for a digital code track circuit.
A further object of the invention is fail-safe decoder apparatus, for an n-digit code word track circuit, requiring reception only of n bits to determine a valid code.
A further object of the invention is decoding apparatus for a digital code track circuit in which a unique comma-free code of n-bit words transmitted through the rails of each section is registered to indicate an unoccupied condition of a corresponding track section.
A still further object of the invention is fail-safe decoding apparatus, for a track circuit in which an identifying comma-free code is transmitted through the rails, including a shift register for sequentially storing the received track code, a read only memory storing all possible bit patterns of the unique CFC word identifying that track circuit, and a fail-safe comparator sequentially comparing the received track code and successive words selected from the read only memory to assure reception of the correct track code through the rails.
Yet another object of the invention is decoding apparatus for assuring the reception of a correct identifying n-bit comma-free code word over a communication channel, including a register for sequentially storing and then supplying in parallel format the continuous CFC received over the channel, a read only memory means for storing a predetermined number of digital words equivalent to all versions of the comma-free code word identifying the channel, a fail-safe comparator for comparing each registered CFC pattern with successively selected read only memory words and which outputs a test signal only when a comparison is obtained, and a processing network for stepping the read only memory when no test signal output is obtained and for processing the periodic test signal output to register the reception of the correct CFC word over the channel.
Other objects, features, and advantages of the invention will become apparent from the following specification and appended claims when taken in connection with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds