1. Technical Field
Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same. More particularly, exemplary embodiments relate to a semiconductor device having a multi-level metal interconnect structure for minimizing the impact of a thermo-mechanical stress on electrical contact characteristic of the interconnect structure and a method of manufacturing the same.
2. Discussion of the Related Art
A through silicon via (TSV) technology is used for stacking a semiconductor device on another semiconductor device. A through silicon via or a through electrode penetrates both an insulation layer and a silicon substrate. The through electrode is formed of a conductive metal including copper, aluminum, gold, indium, and nickel. The thermal expansion coefficient of the conductive metal differs from that of the insulation layer. Due to the difference of the thermal expansion coefficient, a heat budget resulting from a subsequent process after forming the through electrode may result in a thermo-mechanical stress around the through electrode. The stress may cause the through electrode to lift off or crack another structure surrounding the through electrode, and may in turn cause to occur an electrical contact failure in a multi-level metal interconnect including the through electrode. Therefore, a multi-level metal interconnect structure is required to minimize the impact of the thermo-mechanical stress on electrical contact characteristic.
USPTO Backgrounds
USPTO Backgrounds