1. Field of the Invention
This invention relates to a wafer level package, and more particularly to a wafer level package structure, the wafer level package structure can avoid the open circuit caused by the solder ball cracking due to the temperature variation inducing the reinforcing stress between the solder balls and a print circuit board.
2. Description of the Prior Art
The earlier lead frame package technology is already not suitable for the advanced semiconductor dies due to the density of the terminals thereof is too high. Hence, a new package technology of BGA (Ball Grid Array) has been developed to satisfy the packaging requirement for the advanced semiconductor dies. The BGA package has an advantage of that the spherical terminals has a shorter pitch than that of the lead frame package, and the terminals of the BGA are unlikely to be damage and deform. In addition, the shorter signal transmitting distance benefits to raise the operating frequency to conform to the requirement of faster efficiency. Most of the package technologies divide dice on a wafer into respective dies and then to package and test the die respectively. Another package technology, called “Wafer Level Package (WLP)”, can package the dies on a wafer before dividing the dice into respective individual die. The WLP technology has some advantages, such as a shorter producing cycle time, lower cost, and no need to under-fill or molding.
Besides, a partial package structure using in the present marketing is shown as FIG. 1. The package structure comprises an isolation layer 103 and a passivation layer 102 of an IC device 100. The material of the isolation layer 103 may be a dielectric layer with a thickness of 5 micron such as BCB, polyimides etc. The material of the passivation layer 102 is polyimides or SiN. The redistribution layer (RDL) 104 is combined with the isolation layer 103, Al pads 101 of the IC device. The material of the redistribution layer (RDL) 104 may be Cu/Ni/Au alloy with a thickness of 15 micron. Moreover, an isolation layer 105 covers the redistribution layer (RDL) 104. And, the redistribution layer (RDL) 104 has a plurality of openings. Each of the openings has a solder ball 106 to electrically couple with a print circuit board or external parts. The material of the isolation layer 105 may be a dielectric layer such as BCB, epoxy, or polyimides etc.
The aforementioned package structure generally needs an additional material to intensively fix the solder ball 106. It has a drawback mentioned as follows: the adhesion between the redistribution layer (RDL) 104 and the isolation layer 105 is too strong, which is a drawback to the solder ball. When the solder ball 106 joints to the print circuit board, the stress may be induced by temperature influence at the joint part between the solder ball 106 and the redistribution layer (RDL) 104, it is indicated by the area 107, the solder ball 106 will be cracked owing to reinforcing stress raised by temperature variation, thereby causing an open circuit between the solder ball and pad.
In view of the aforementioned, the present invention provides an improved wafer level package structure to overcome the above drawback.
USPTO Backgrounds
USPTO Backgrounds