The present invention generally relates to an apparatus and to a method for fabricating semiconductor wafers and, more particularly, to chemical-mechanical polishing (CMP).
Chemical-mechanical polishing (CMP) removes material from the top layer of a wafer in the production of ultra-high density integrated circuits (instead of xe2x80x9cpolishingxe2x80x9d, xe2x80x9cplanarizationxe2x80x9d is also used). Often, the top layer is an oxide film (e.g., silicon dioxide), but other materials can also be removed. In a typical CMP process, the top layer of the wafer is exposed to an abrasive medium under controlled chemical, pressure, velocity, and temperature conditions. Conventional abrasive media include slurry solutions and polishing pads.
The slurry solutions generally contain small, abrasive particles (e.g., silicon dioxide for oxide polishing), and chemically-reactive substances (e.g., potassium hydroxide for oxide polishing).
The polishing pads are generally planar pads made from a relatively porous material such as blown polyurethane, and the polishing pads may also contain abrasive particles.
Thus, when the pad and/or the wafer moves with respect to each other, material is removed from the top layer mechanically by the abrasive particles in the pad and/or slurry, and chemically by the chemicals in the slurry.
In the competitive semiconductor industry, it is desirable to minimize the number of defective or impaired circuits on each wafer.
Therefore, CMP must consistently and accurately produce a uniform, planar surface of the top layer because it is, for example, important to accurately focus the image of circuit patterns in further fabrication steps. As the density of integrated circuits increases, it is often necessary to accurately focus the critical dimensions of the circuit pattern to better than a tolerance of approximately 0.01 micro meter (xcexcm). Focusing the circuit patterns to such small tolerances, however, is very difficult when the distance between the lithography equipment and the surface of the wafer varies because the top layer surface is not uniformly planar.
For the application of CMP and for prior art designs, the following references are useful: U.S. Pat. No. 5,205,082 (Shendon et al.), U.S. Pat. No. 5,533,924 (Stroupe et al.), U.S. Pat. No. 5,571,044 (Bolandi et al.), U.S. Pat. No. 5,624,299 (Shendon), U.S. Pat. No. 5,635,083 (Breivogel et al.), U.S. Pat. No. 5,643,061 (Jackson et al.), U.S. Pat. No. 5,664,988 (Stroupe et al.), U.S. Pat. No. 5,664,990 (Adams et al.), U.S. Pat. No. 5,700,180 (Sandhu et al.), U.S. Pat. No. 5,707,492 (Stager et al.), U.S. Pat. No. 5,755,614 (Adams et al.), U.S. Pat. No. 5,762,539 (Nakashiba et al.), U.S. Pat. No. 5,762,544 (Zuniga et al.), U.S. Pat. No. 5,795,215 (Guthrie), U.S. Pat. No. 5,803,799 (Volodarsky et al.), U.S. Pat. No. 5,857,899 (Volodarsky et al.), U.S. Pat. No. 5,868,896 (Robinson et al.), U.S. Pat. No. 5,879,226 (Robinson) U.S. Pat. No. 5,882,243 (Das et al.), U.S. Pat. No. 5,948,204 (Maveety et al.), U.S. Pat. No. 5,993,302 (Chen et al.), U.S. Pat. No. 6,004,193 (Nagahara et al.), U.S. Pat. No. 6,012,964 (Arai et al.); as well as European and PCT documents EP 0 548 846 B1 (Shendon et al.), EP 0 589 433 B1 (Hirose et al.), EP 0 599 299 B1 (Okumura et al.), EP 0 786 310 A1 (Volodarsky et al.) and WO 99/58297 (Perlov et al.).
USPTO Backgrounds
USPTO Backgrounds