Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity and not limitation, FPGAs are described below though other types of integrated circuits having embedded circuits may be used. FPGAs may include one or more embedded blocks, such as one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Heretofore, performance of an embedded block in programmable logic of an FPGA (“FPGA fabric”) was determined by building a ring oscillator and measuring timing associated with an input or output of an embedded block. A maximum frequency of operation may be determined from what is known as a Minimum Cycle Time of the ring oscillator. In other words, the minimum time in which a signal cycles through the ring oscillator may be used to determine a maximum frequency of operation of an embedded block included as part of the ring of the ring oscillator. Unfortunately, as embedded blocks become more complex, it becomes more problematic to test to find a Minimum Cycle Time as associated with a particular active path in an embedded block. For example, an embedded block may involved complex input sequences to operate properly. Or, it may take many cycles to observe results of testing.
Accordingly, it would be desirable and useful to provide means for determining timing associated with a maximum frequency of operation of an embedded block in an integrated circuit that is not as constrained by complex input sequences or has less test cycle latency or both than in the past.
USPTO Backgrounds
USPTO Backgrounds