Ultra large-scale integrated (VLSI) circuits with high performance are demanded in order to lower the power consumption and to increase integration of the devices on a wafer. Salicided process is one of the most popular technique for improving the operation speed for ULSI devices. This is due to the fact that the salicided devices have a lower contact resistance than the non-salicided devices, as reference to IEDM Tech. Dig. page 451, 1996, entitled "A Thermally Stable Ti--W salicide for Deep-Submicron Logic with Embedded DRAM".
According to the above article, the devices with salicided process have a faster operation speed and a better short channel effect than devices with conventional technique. However, the devices with a self-aligned silicided contact shows a worse electrostatic shielding discharge (ESD) performance than the non-salicided devices. As is described as below descriptions in detail, using salicide process have great influence on the performance of devices.
The relation between self-aligned silicide process and the ESD capability was studied in a article, entitled "Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN behavior, with the ESD/EOS performance of a 0.25 .mu.m CMOS Process", as reference to IEDM Tech. Dig., p. 893, 1996. The authors discussed about that the current gain of a self-biased lateral NPN transistor was affected by the salicide thickness in a 0.25 .mu.m CMOS process, and the relationship between the current gain and the ESD performance was examined. The current gain was strongly influenced by the effective drain/source diffusion depth below the salicide, which was determined by the implant energy and the amount of the active diffusion consumed in silicidation. The devices with lower current gain are found to have lower ESD capability. The current gain was affected by the NMOS drain junction property so that the ESD performance could be enhanced by either increasing the drain/source implant energy or reducing the salicide thickness. Neither the increase of the implant energy nor the decrease of salicide thickness significantly changed the NMOS characteristic.
A method to fabricate an electrostatic discharge protection circuit is disclosed in U.S. Pat. No. 5,672,527 which was filed on Mar. 8, 1996. The inventors of the patent proposed a method with a photomask instead of several masks as in a conventional process during the salicide process of ESD circuits. However, a complicating etching process was used for accomplishing the salicide process, the devices could be degraded from the etching process. Many stages are used to simultaneously fabricate ESD devices and MOS devices on a substrate in the patent so that the devices have a long processing time and a difficult processing flow.
As stated above, a salicide process for MOS devices without complicated etching process is needed and the ESD performance of the circuits of the MOS devices is not affected by the salicide process.
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