This application is based upon and claims priority of Japanese Patent Application No. 11-215601 filed on Jul. 29, 1999, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to semiconductor memory devices and methods for manufacturing the same, and more particularly to a semiconductor memory device including a plurality of semiconductor memory cells, sources of which are coupled to source lines, and a method for manufacturing such a semiconductor memory device.
1. Description of the Prior Art
FIG. 1 shows an array of NOR flash memory cells MC of a conventional non-volatile semiconductor memory device. It is indispensable for a method of manufacturing the non-volatile semiconductor memory device to scale down the NOR flash memory cells MC provided thereon.
As shown in FIG. 1, the NOR flash memory cells MC, which are transistors, are arrayed such that the transistors in each row have sources S coupled to a common source line SL and gates G coupled to a common word line WL parallel to the common source line SL. Also, the transistors in each column have drains DR coupled to a common bit line BL.
In addition, such a source line SL may be used to perform flash-erasing or the like.
FIG. 2 is a cross-sectional diagram showing a configuration of the conventional semiconductor memory device, taken along the source line SL of FIG. 1. In this diagram, reference numeral 1 denotes a silicon semiconductor substrate, 17 a CVD (Chemical Vapor Deposition) oxide film, 18 a BPSG (Boro-Phospho Silicate Glass) film, and 21 a field oxide film.
As shown in FIG. 2, in order to scale down the semiconductor memory cells MC provided on the semiconductor substrate 1, the source line SL is formed such that the field oxide film 21 is formed on the silicon semiconductor substrate 1 by means of a LOCOS (local oxidation of silicon) element isolation process and is etched by means of a SAS (Self-Aligned Source) process after the gates G are formed, and a continuous impurity diffusion region including source diffusion regions 12 of the semiconductor memory cells MC (transistors) is formed as the source line SL on the silicon semiconductor substrate 1.
Next, a description will be given below of a method of using the SAS process to manufacture the NOR flash memory cells MC, by referring to FIG. 3 through FIG. 7.
FIG. 3 is a plan view partly showing a configuration of the conventional semiconductor memory device including the NOR flash memory cells MC.
FIGS. 4A through 4D are diagrams partly showing a cross-sectional configuration of the conventional semiconductor memory device, taken along a word line WL A-Axe2x80x2 in FIG. 3.
As shown in FIG. 4A, on the silicon semiconductor substrate 1, a pad oxide film 2 with a thickness of approximately 25 nm is formed by means of a thermal oxidation process, which may be performed at 900xc2x0 C. for example. On the pad oxide film 2, a silicon nitride film 3 with a thickness of approximately 170 nm is stacked by a Chemical Vapor Deposition (CVD) process. And then, by using lithography and etching techniques, the silicon nitride film 3 is patterned and etched so as to remain on element regions alone.
As shown in FIG. 4B, the silicon semiconductor substrate 1 is thermally oxidized at approximately 1100xc2x0 C. by means of the silicon nitride film 3 serving as a mask, so that a LOCOS element isolation region 4 with a thickness of approximately 300 nm is formed.
As shown in FIG. 4C, the silicon nitride film 3 and the pad oxide film 2 are removed so that a tunnel insulation film 5 with a thickness of approximately 10 nm is formed on the silicon semiconductor substrate 1 by means of the thermal oxidation process, which may be performed at 900xc2x0 C. for example. After that, a polysilicon film 6 with a thickness of approximately 100 nm is stacked as a floating gate on the tunnel insulation film 5 by means of the CVD process. And then, the polysilicon film 6 is patterned to form a striped pattern covering the element regions by means of the lithography and etching techniques.
As shown in FIG. 4D, an ONO film 7 for combining capacitance of the floating gate and a control gate may be formed such that an oxide film with a thickness of approximately 10 nm is formed by means of the CVD process, a silicon nitride film with a thickness of approximately 10 nm is stacked on the an oxide film, and an oxide film with a thickness of approximately 4 nm is further stacked on the silicon nitride film by means of the thermal oxidation process which may be performed at 950xc2x0 C. for example.
After that, a polysilicon film 8 with a thickness of approximately 120 nm is formed as the control gate by means of the CVD process. On the polysilicon film 8, a WSi film 9 with a thickness of approximately 150 nm is stacked. And further on the WSi film 9, a polysilicon film 10 with a thickness of approximately 50 nm is stacked. Furthermore, on the polysilicon film 10, a silicon nitride oxide film 11 with a thickness of approximately 100 nm is stacked, serving as an anti-reflection film at the time of resist patterning.
FIGS. 5A through 5C are, on the other hand, diagrams partly showing a cross-sectional configuration of the conventional semiconductor memory device, taken along a bit line (aluminum wire) D-Dxe2x80x2 in FIG. 3.
As shown in FIG. 5A, resist in a pattern extending in a direction intersecting a pattern of the LOCOS element isolation region 4 shown in FIG. 3 is applied thereon (not shown), and by using the resist as a mask, the silicon nitride oxide film 11, the polysilicon film 10, the WSi film 9, and the polysilicon film 8 are etched in order.
Thereby, the word line WL connected to the control gate of the semiconductor memory cell MC is thus formed. After that, the ONO film 7 and the polysilicon film 6 are etched by using the silicon nitride oxide film 11 as a mask, and thereby a stacked gate electrode is formed.
Then, by performing a self-aligned ion implantation for the stacked gate, impurities are implanted into the silicon semiconductor substrate 1, and a thermal process is performed half an hour in a nitrogen atmosphere of, for example, approximately 900xc2x0 C. Thereby, a source diffusion region 12 and a drain diffusion region 13 are formed. In addition, the above-mentioned ion implantation is performed such that, for example, AS+ ions are accelerated with energy of 60 KeV and then are irradiated into he silicon semiconductor substrate 1 by a dose of 4xc3x971015 ions/cm2.
As shown in FIG. 5B, a silicon oxide film 14 with a thickness of approximately 100 nm is stacked thereon by means of the CVD process and then is etched back. Thereby, the silicon oxide film 14 becomes a side wall spacer. After that, in order to expose the source diffusion region 12 by means of the lithography technique, the resist covering the drain diffusion region 13 is patterned and the LOCOS element isolation region 4 shown in FIG. 3 is etched.
Then, By implanting the As+ ions, which have been accelerated with the energy of 60 KeV, thereinto by a dose of 4xc3x971015 ions/cm2, and by performing the thermal process half an hour in the nitrogen atmosphere of, for example, 850xc2x0 C., a continuous diffusion region connecting the source diffusion regions 12 of the semiconductor memory cells MC is formed as the source line SL.
As shown in FIG. 5C, the silicon oxide film 17 with a thickness of approximately 100 nm and the BPSG film 18 with a thickness of approximately 900 nm are stacked thereon by means of the CVD process. After that, a contact hole 19 is formed, and an aluminum wiring film is stacked on the BPSG film 18 by using a spattering process. Then, the aluminum wiring film is patterned into the bit line BL.
After the previously described steps are completed, metal wiring is carried out, which is the same as that of a common MOS integrated circuit, and a surface protecting insulation film is formed.
Accordingly, the semiconductor memory device is thus manufactured.
FIG. 6 is a cross-sectional diagram showing a configuration of the semiconductor memory device, taken along a line B-Bxe2x80x2 in FIG. 3.
As shown in this diagram, on the silicon semiconductor substrate 1, the LOCOS element isolation region 4 and the drain diffusion region 13 are formed, and the silicon oxide film 17 and the BPSG film 18 are stacked thereon. After that, the contact hole 19 is opened, and the aluminum wiring film is formed as the bit line BL.
FIG. 7 is a cross-sectional diagram showing a configuration of the semiconductor memory device, taken along a line E-Exe2x80x2 in FIG. 3.
As shown in this diagram, the LOCOS element isolation region 4 and the source line SL are formed on the silicon semiconductor substrate 1. The polysilicon film 8, the WSi film 9, the polysilicon film 10, and the silicon nitride oxide film 11 are stacked on the LOCOS element isolation region 4 in order. And the silicon oxide film 14 is formed as the side wall spacer. Further, the silicon oxide film 17 and the BPSG film 18 are stacked thereon in order.
There is, however, a limitation in the LOCOS element isolation process in terms of scaling down the element isolation regions. In recent years, a trench element isolation process performed by etching a semiconductor semiconductor substrate has been become popular, which is required to be able to form elements the same as those formed by the LOCOS element isolation process.
FIG. 8A is a cross-sectional diagram along a line C-Cxe2x80x2 of FIG. 3, showing the source line SL of the NOR-type flash memory manufactured by the conventional manufacturing method that makes use of the trench element isolation process.
As shown in FIG. 8A, it is difficult for the trench element isolation process to form the source line SL. Specifically, in the case of employing the LOCOS element isolation process shown by FIG. 2, since parts 21 formed by etching element isolation regions on the silicon semiconductor substrate 1 have gently inclined surfaces, the source line SL can be easily formed by the ion implantation. On the other hand, in the case of employing the trench element isolation process, since parts Mt, which are formed by etching the element isolation regions on the silicon semiconductor substrate 1 by means of the SAS process, have sharp steps, the impurities cannot be effectively introduced into the steps by means of anisotropic ion implantation, and the source line SL cannot be formed.
As a result, the conventional manufacturing method cannot be used to manufacture the semiconductor memory device including the NOR-type flash memory cells in the case of employing the trench element isolation process.
FIG. 8B is a cross-sectional diagram showing a non-volatile memory device formed by using the trench element isolation process, which is disclosed in Japanese Laid-open Patent Application No. 2-833030.
As shown in this diagram, a CVD tungsten layer is formed like a bridge built over n-type source diffusion regions of semiconductor memory cells. Since the element isolation regions and the n-type source diffusion regions are formed unevenly, there brings about a problem in that resistance of the CVD tungsten layer becomes high on the element isolation regions and the breaking thereof may occur in the most case.
As a result, it is difficult to form the source line SL with high-reliability and low-resistance by means of the above-mentioned prior art.
It is a general object of the present invention to provide a semiconductor memory device and a method for manufacturing the same, in which the above-mentioned problems can be eliminated.
Another and a more specific object of the present invention is to provide a semiconductor memory device with high density and a method for manufacturing the semiconductor memory device including a plurality of semiconductor memory cells, sources of which are connected to source lines.
The above object and other objects of the present invention are achieved by a semiconductor memory device including a semiconductor substrate, a plurality of memory cells arranged on the semiconductor substrate in an array which is made up of a plurality of rows and columns, each of the memory cells having a gate, a drain, and a source, a plurality of word lines, each coupled to gates of the memory cells in a corresponding row, a plurality of bit lines, each coupled to drains of the memory cells in a corresponding column, a plurality of isolation regions formed on the semiconductor substrate and isolating the memory cells, and a plurality of source lines, disposed approximately parallel to the word lines, and each coupled to sources of the memory cells in a corresponding row, wherein each of the source lines is made up of a conductive pattern formed on an approximately flat region of the semiconductor substrate.
The above object and other objects of the present invention are achieved by a method for manufacturing a semiconductor memory device which includes an isolation region formed on a semiconductor substrate, source and drain diffusion regions formed in the semiconductor substrate, a gate oxide film formed on the semiconductor substrate between the source and drain diffusion regions, a floating gate formed on the gate oxide film, and a control gate formed on the floating gate via a first insulation film, the method comprising the steps of forming an second insulation film on an exposed portion of the substrate not covered by the isolation region and etching the second insulation film to expose the source diffusion regions, and forming a conductor on the exposed source diffusion region.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
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