1. Field of the Invention
The invention relates to the field of metal-oxide semiconductor transistors. More particularly, it relates to the field of high speed, submicron channel transistors. The invention realizes a transistor with a VLSI manufacturable process.
2. Description of the Relevant Art
In submicron transistors hot electron injection into the gate is a serious reliability problem. Structures have been proposed in the attempt to design a high speed VLSI manufacturable submicron MOS transistor which exhibits resistance to hot electron degradation.
An inverse T-gate lightly doped (ITLDD) transistor or similar structures are effective devices at reducing hot electron generation for submicron transistors. The ITLDD transistor features a self-aligned n- gate-to-drain overlap and a self-aligned n+ source/drain implant. The inverse T-gate lightly doped drain structure is inappropriate for VLSI manufacturing because its process requires a timed etch for the polysilicon etch. When etching the polysilicon layer to form the inverse T-gate, there is no end point detection available to signal that the appropriate polysilicon shelf thickness is present. Since the n- lightly doped source/drain region is implanted through the polysilicon shelf, any inconsistency in shelf thickness would create a nonuniform doping structure.
USPTO Backgrounds
USPTO Backgrounds