1. Field of the Invention
The present invention relates to a duty detection circuit that detects deviation in clock duty, a duty correction circuit incorporating the duty detection circuit, and a duty detection method.
2. Description of Related Art
In recent years, along with the speeding-up and reduction in voltage of application specific integrated circuits (ASICs), microprocessors, and the like, interfaces such as memories have increased in speed. In particular, when data is retrieved using both the rising and falling edges of a clock signal as in a double data rate (DDR) system, deviation in duty of clock signals fed into a circuit can be a major cause of the deterioration in setup/hold characteristics.
With the recent speeding-up of ASICs, microprocessors, and the like, the deviation in duty with respect to a clock cycle cannot be neglected. For this reason, a circuit for detecting and correcting a clock duty is often incorporated into delay locked loop (DLL) circuits, phase locked loop (PLL) circuits, input first-stage circuits, and the like.
FIG. 7 shows a duty detection circuit disclosed in Japanese Unexamined Patent Application Publication No. 2007-121114, and FIG. 8 shows a timing diagram of the operation of the duty detection circuit. The duty detection circuit shown in FIG. 7 includes a current source 27, MOS transistors 25 and 26 for inputting clocks to be compared, load MOS transistors 23 and 24, and precharge MOS transistors 20, 21, and 22. The duty detection circuit further includes an input control circuit 28 including logic circuits 29 and 30, an input control circuit 31, and a comparator 32 for comparing outputs.
Referring now to FIGS. 7 and 8, the operation of the duty detection circuit disclosed in Japanese Unexamined Patent Application Publication No. 2007-121114 will be described. Prior to duty detection, the precharge MOS transistors 20, 21, and 22 charge outputs DUTY_HB and DUTY_LB to a power supply potential. Signals LDCSMT/LDCSMB are activated to start the detection. During a time period when a clock LCLKOET is at high level, the MOS transistor 25 is turned on and electric charge of the charged output DUTY_LB is extracted, thereby decreasing the potential. During a time period when an inverted clock LCLKOEB is at high level, the MOS transistor 26 is turned on and electric charge of the charged output DUTY_HB is extracted, thereby decreasing the potential.
During a time period when the clock signals LCLKOET/LCLKOEB are at low level, the MOS transistors 25 and 26 are turned off and the potentials of the outputs DUTY_HB and DUTY_LB are maintained. The potentials of the outputs DUTY_HB and DUTY_LB are decreased in proportion to the period for which the clock is at high level. As shown in FIG. 8, for example, after inputting two cycles of the clock, the potentials of the outputs DUTY_HB and DUTY_LB obtained at the time are compared to determine a potential difference. A determination signal LDCT is then output.
When the clock duties are equal, the potentials of the outputs DUTY_HB and DUTY_LB are also equal to each other. Consideration is given to the case where there is duty deviation and the duty is 40% (40% high level period in a cycle period), for example. In this case, the ON period of the MOS transistor 26 on the inverted clock LCLKOEB side becomes longer, and the potential of the output DUTY_HB is further decreased.
In the case of the duty of 60%, in contrast, the ON period of the MOS transistor 25 on the clock LCLKOET side becomes longer, and the potential of the output DUTY_LB is further decreased. The charged potential is extracted during the period proportional to the duty, to thereby produce and hold a potential difference. Then, the comparator compares the potential difference and detects deviation in duty.
Japanese Unexamined Patent Application Publication No. 2006-303553 discloses a duty detection circuit that repeats charging and discharging of a plurality of capacitors based on a clock signal, and detects a potential difference between the capacitors, thereby detecting the duty of the clock signal.
USPTO Backgrounds
USPTO Backgrounds