The present invention relates to fixed information content memories often referred to as readonly memories (ROM) and, more particularly, to such memories which are subject to charge generating disturbances.
Radiation can be loosely categorized into longterm global radiation, short-term global radiation, and short-term local radiation. Short-term global radiation is typically ionizing photon or electron radiation and is called "dose rate". The effect of the dose rate is to generate large photocurrents in silicon circuits. The photo currents are collected by circuit nodes and may cause an undesirable change in logic state by charging or discharging of the node.
Various circuit approaches are utilized to reduce the effects of radiation of the various categories. Among these approaches is the construction of memory circuits to minimize the effects of the large photocurrents due to dose rate radiation. For example, limiting the volume of circuit material exposed to dose rate can limit the photocurrent collection. Bipolar ROM operates at high speed and can be made quite small thereby limiting the volume of material exposed to dose rate. For example, a prior art bipolar ROM can be constructed as a vertical PNP device with the bit line connected to the P+ emitter and the word line connected to the N+ base. However, the bit line of the ROM just described will be at approximately 0.6-0.7 volts after being discharged and this will create a high power to ground current in data sensing circuitry.
The use of silicon on insulator (SOI) technology permits the design of circuits which have the charge collection volume reduced vertically by the buried oxide layer. SOI technology provides a dramatic increase in dose rate upset hardness when compared to bulk technology. Circuits such as the previously described vertical PNP ROM cannot be processed in SOI technology.
The one transistor N-channel or P-channel ROM cell available in the commercial market typically has the gate connected to the word line and the drain connected to the bit line when programmed in one state and not connected to the bit line when programmed in the opposite state. When subjected to dose rate, all the memory cells connected to the bit line will collect photocurrent and the bit line voltage will change contrary to what is desired from the ROM cell programmed by not being connected to the bit line. A load cell can be added to the bit line to compensate the bit line photocurrent to maintain a high or low state as required, but this solution will create high power to ground current when the selected ROM cell state cell connected to the bit line is the opposite of the load cell state DC since the ROM cell must overdrive the load cell state. Even when a ROM using MOSFETS is implemented in SOI technology, and other dose rate resistant circuit layout and packaging techniques are used, there continues to be a significant risk due to photo currents generated by dose rate radiation causing an unwanted change in the bit line voltage. This unwanted change in bit line voltage is referred to as bit line sag. Bit line sag can result in a data output error condition in a ROM.
Thus a need exists for a ROM cell that will reliably provide a full rail output voltage during dose rate and does not cause excessive power to ground current loading.
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