Semi-conductor devices are fabricated on substrates which are in the form of thin wafers. Silicon is commonly used as the substrate material, but other materials, such as III-V compounds (for example GaAs and InP) are also used. In some instances (for example, the manufacture of LED's) the substrate is a sapphire or silicon carbide wafer on which a thin layer of a semi-conducting material is deposited. The size of such substrates ranges from 2 inches and 3 inches up to 200 mm, 300 mm, and 450 mm diameter and many standards exist (e.g., SEMI) to describe such substrate sizes.
Plasma etching equipment is used extensively in the processing of these substrates to produce semi-conductor devices. Such equipment typically includes a vacuum chamber fitted with a high density plasma source such as Inductively Coupled Plasma (ICP) which is used to ensure high etch rates, necessary for cost-effective manufacturing. In order to remove the heat generated during the processing, the substrate is typically clamped to a cooled support. A cooling gas (typically Helium) is maintained between the substrate and the support to provide a thermal conductance path for heat removal. A mechanical clamping mechanism, in which a downward force is applied to the top side of the substrate, may be used, though this may cause contamination due to the contact between the clamp and the substrate. More frequently an Electrostatic chuck (ESC) is used to provide the clamping force.
Numerous gas chemistries appropriate to the material to be etched have been developed. These frequently employ a halogen (Fluorine, Chlorine, Bromine, or Iodine) or halogen-containing gas together with additional gases added to improve the quality of the etch (for example, etch anisotropy, mask selectivity and etch uniformity). Fluorine containing gases, such as SF6, F2 or NF3 are used to etch silicon at a high rate. In particular, a process (Bosch or TDM) which alternates a high rate silicon etch step with a passivation step to control the etch sidewall, is commonly used to etch deep features into silicon. Chlorine and Bromine containing gases are commonly used to etch III-V materials.
Plasma etching is not limited to semiconducting substrates and devices. The technique may be applied to any substrate type where a suitable gas chemistry to etch the substrate is available. Other substrate types may include carbon containing substrates (including polymeric substrates), ceramic substrates (e.g., AlTiC and sapphire), metal substrates, and glass substrates.
To ensure consistent results, low breakage and ease of operation, robotic wafer handling is typically used in the manufacturing process. Handlers are designed to support the wafers with minimal contact, to minimize possible contamination and reduce the generation of particulates. Edge contact alone, or underside contact close to the wafer edge at only a few locations (typically within 3-6 mm of the wafer edge) is generally employed. Handling schemes, which include wafer cassettes, robotic arms and within process chamber fixtures including the wafer support and ESC, are designed to handle the standard wafer sizes as noted previously.
After fabrication on the substrate, the individual devices (die or chips) are separated from each other prior to packaging or being employed in other electronic circuitry. For many years, mechanical means have been used to separate the die from each other. Such mechanical means have included breaking the wafer along scribe lines aligned with the substrate crystal axis or by using a high speed diamond saw to saw into or through the substrate in a region (streets) between the die. More recently, lasers have been used to facilitate the scribing process.
Such mechanical wafer dicing techniques have limitations which affect the cost effectiveness of this approach. Chipping and breakage along the die edges can reduce the number of good die produced, and becomes more problematic as wafer thicknesses decrease. The area consumed by the saw bade (kerf) may be greater than 100 microns which is valuable area not useable for die production. For wafers containing small die (e.g., individual semiconductor devices with a die size of 500 microns×500 microns) this can represent a loss of greater than 20%. Further, for wafers with many small die and hence numerous streets, the dicing time is increased, and productivity decreased, since each street is cut individually. Mechanical means are also limited to separation along straight lines and the production of square or oblong shaped chips. This may not represent the underlying device topology (e.g., a high power diode is round) and so the rectilinear die format results in significant loss of useable substrate area. Laser dicing also has limitations by leaving residual material on the die surface or inducing stress into the die.
It is important to note that both sawing and laser dicing techniques are essentially serial operations. Consequently, as device sizes decrease, the time to dice the wafer increases in proportion to the total dicing street length on the wafer.
Recently plasma etching techniques have been proposed as a means of separating die and overcoming some of these limitations. After device fabrication, the substrate is masked with a suitable mask material, leaving open areas between the die. The masked substrate is then processed using a reactive-gas plasma which etches the substrate material exposed between the die. The plasma etching of the substrate may proceed partially or completely through the substrate. In the case of a partial plasma etch, the die are separated by a subsequent cleaving step, leaving the individual die separated. The technique offers a number of benefits over mechanical dicing:
1) Breakage and chipping is reduced;
2) The kerf dimensions can be reduced to well below 20 microns;
3) Processing time does not increase significantly as the number of die increases;
4) Processing time is reduced for thinner wafers; and
5) Die topology is not limited to a rectilinear format.
After device fabrication, but prior to die separation, the substrate may be thinned by mechanical grinding or similar process down to a thickness of a few hundred microns, or even less than a hundred microns.
Prior to the dicing process, the substrate is typically mounted on a dicing fixture. This fixture is typically comprised of a rigid frame that supports an adhesive membrane. The substrate to be diced is adhered to the membrane. This fixture holds the separated die for subsequent downstream operations. Most tools used for wafer dicing (saws or laser based tools) are designed to handle substrates in this configuration and a number of standard fixtures have been established; however, such fixtures are very different from the substrates which they support. Though such fixtures are optimized for use in current wafer dicing equipment, they cannot be processed in equipment which has been designed to process standard substrates. Thus, current automated plasma etching equipment is not suitable for processing substrates fixtured for dicing and it is difficult to realize the benefits that plasma etch techniques should have for die separation.
Some groups have contemplated using plasma to singulate die from wafer substrates. U.S. Pat. No. 6,642,127 describes a plasma dicing technique in which the substrate wafer is first attached to a carrier wafer via an adhesive material, before plasma processing in equipment designed for processing silicon wafers. This technique proposes adapting the form factor of the substrate to be diced to be compatible with standard wafer processing equipment. While this technique allows standard plasma equipment to dice the wafer, the proposed technique will not be compatible with standard equipment downstream of the dicing operation. Additional steps would be required to either adapt the downstream equipment or revert the substrate form factor for standard downstream equipment.
U.S. Patent Application 2010/0048001 contemplates the use of a wafer adhered to a thin membrane and supported within a frame. However, in the 2010/0048001 application, the masking process is achieved by adhering a mask material to the backside of the wafer and using a laser to define the etch streets prior to plasma processing. In contrast to standard dicing techniques which cingulate the substrate from the front side, this technique introduces additional complex and expensive steps which may negate some of the advantages of plasma dicing. It also requires the additional demand of aligning the backside mask with the front side device pattern.
Therefore, what is needed is a plasma etching apparatus which can be used for dicing a semiconductor substrate into individual die and which is compatible with the established wafer dicing technique of handling a substrate mounted on tape and supported in a frame, and which is also compatible with standard front side masking techniques.
Nothing in the prior art provides the benefits attendant with the present invention.
Therefore, it is an object of the present invention to provide an improvement which overcomes the inadequacies of the prior art devices and which is a significant contribution to the advancement to the dicing of semiconductor substrates using a plasma etching apparatus.
Another object of the present invention is to provide a method for plasma dicing a substrate, the method comprising: providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate on a carrier support to form a work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
Yet another object of the present invention is to provide a method for plasma dicing a substrate, the method comprising: providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber, the work piece support having an electrostatic chuck; placing the substrate on a carrier support to form a work piece; loading the work piece onto the work piece support; clamping the work piece to the work piece support through the electrostatic chuck; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; etching the work piece through the generated plasma; and controlling temperature of the cover ring during the etching step.
Still yet another object of the present invention is to provide a method for plasma dicing a substrate, the method comprising: placing the substrate on a carrier support to form a work piece; loading the work piece into a plasma processing chamber; exposing the work piece in the plasma processing chamber to a first plasma etch process using a first etchant gas; terminating the first plasma etch process after singulation; and exposing the work piece in the plasma processing chamber to a second plasma etch process using a second etchant gas.
Another object of the present invention is to provide an apparatus for plasma dicing a substrate comprising: a process chamber having a wall; a plasma source adjacent to the wall of the process chamber; a work piece support within the process chamber, the work piece support having an electrostatic chuck; a work piece having the substrate on a carrier support, the work piece being placed onto the work piece support; and a cover ring disposed above the work piece, the cover ring is thermally coupled to the wall of the process chamber.
The foregoing has outlined some of the pertinent objects of the present invention. These objects should be construed to be merely illustrative of some of the more prominent features and applications of the intended invention. Many other beneficial results can be attained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to the summary of the invention and the detailed description of the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds