The present invention relates to an electrostatic discharge protection (ESD) circuit suitable for use in integrated circuits and more particularly, the present invention relates to a protection circuit employing high reverse breakdown voltage diodes for ensuring that no avalanche and consequent leakage occurs at input pads.
As is well known in the semiconductor art, electrostatic discharge can deleteriously affect the circuit components or in some cases even destroy the circuit entirely. Electrostatic charges can readily accumulate on the human body or can be generated by machines in production processes or friction during transport. There is a strong tendency for integrated circuit p/n junctions to show greatly increased leakage when subjected to reverse stress. Since p/n junctions are commonly used for the protection of integrated circuits against ESD events, this increased leakage is a serious problem where low leakage is necessary.
Further, it is established that the leakage current in protection diodes increases by several orders of magnitude after being subjected to ESD.
To contend with this problem, the use of chip diodes has had widespread application to protect circuits.
Advantageously, the present invention alleviates the complications and limitations in previously proposed solutions and contributes the following:
i) a protection circuit that avoids reverse breakdown at inputs;
ii) diodes distributed across power supply rails; and
iii) a low resistance return loop through the substrate and power rails.
The present invention provides a solution to this leakage problem at inputs by ensuring that no diode attached to an input can sustain a voltage close to that required for reverse breakdown.
According to one object of one embodiment of the present invention, there is provided an electrostatic discharge protection circuit suitable for use with an integrated circuit. The electrostatic discharge protection circuit includes a first high voltage p/n junction diode connected between a positive supply of the circuit and a first input and a second high voltage p/n junction diode connected between a negative supply of the circuit and the input. The first diode and the second diode each comprise a field plated diode for increasing reverse breakdown voltage of the diodes. A third diode is connected between the positive supply and the negative supply for conducting in two directions at low voltage. The third diode has a reverse breakdown voltage exceeding the voltage of the supply.
In accordance with a further object of one embodiment of the present invention, there is provided a method of preventing input diode leakage in a circuit with a positive supply and a negative supply from reverse stress during ESD events.
A first high voltage diode and a second high voltage diode are provided and the first diode is connected between the positive supply and an input of the circuit. The second diode is connected between the negative supply and the input and a third diode is connected between the positive supply and the negative supply. The third diode conducts in two directions and has a reverse breakdown voltage third diode for conducting in two directions and having a reverse breakdown voltage exceeding the voltage of the first supply and the second supply to substantially prevent diode leakage during ESD events.
Successful results have been achieved by modifying the input diodes to increase the breakdown voltage for avoiding over stressing of the input diodes. In the examples, field plating is used for field relief on the input diodes. Alternatively, special diffusion, i.e. p-base may be used to increase the breakdown voltage. By making use of field plating in the protection circuits, a new failure mechanism is provided. The use of field plates has been proposed in the art previously to increase breakdown voltage and accordingly this is not a new concept. The instant invention relates to the use of field plating in protection circuits used as a new failure mechanism as indicated above.
Having thus generally described the invention, reference will now be made to the accompanying drawings illustrating preferred embodiments.
USPTO Backgrounds
USPTO Backgrounds