1. Field of the Invention
The present application relates generally to semiconductor circuits, and in particular to a hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only.
2. Description of the Related Art
Shift register latches (SRLS) are commonly used for testing and debugging of digital semiconductor chips. A shift register latch may be directly arranged on a logic semiconductor chip or on a storage chip. The semiconductor chip may comprise logic paths which provide their inputs and outputs to certain memory elements in the circuit. These memory elements are configurable to become shift register latches.
Shift register latches serve a dual purpose, one during test and one during normal system operation. When testing the circuit, shift register latches store predetermined data patterns through a shifting operation. Multiple shift register latches may create a scan path with the output signals from each latch supplied to a register for comparison and analysis with known results. When operating the circuit in the normal system environment, the shift register latches function as memory elements passing signals for processing from one block to another, and at the same time typically receiving input signals for subsequent application to logic blocks in subsequent clock cycles.
USPTO Backgrounds
USPTO Backgrounds