1. Field of the Invention
The present invention generally relates to simulations of electronic circuits such as application specific integrated circuits (ASICs) and, more particularly, to techniques for interpreting results obtained from simulating integrated circuits when gate-level implementations are derived from a higher level implementation (e.g., from a cell-based design).
2. State of the Art
Circuit designers often have difficulty interpreting and analyzing data generated during the simulation of complex integrated circuits. One reason for the difficulty is that simulation data normally is generated in the form of logical 1s and 0s to represent signal states that are present at the nodes of the simulated circuits. Circuit designers ordinarily do not design integrated circuits at the gate level but, instead, design at a high level specification using, for example, logic gate or cell-based implementations. However, although techniques have been suggested for assisting circuit designers in analyzing detailed data derived from simulations of gate-level circuits, none of these techniques provide information that can be correlated with higher level circuit designs.
USPTO Backgrounds
USPTO Backgrounds