Fabrication flows for microelectromechanical systems (MEMS) and IC architectures incorporate smaller and smaller feature sizes. This places a restraint on the surface flatness requirement for obtaining these critical dimensions (CDs). As such, filling/planarization processes are considered some of the critical process steps for device fabrication. Currently, planarization layers are obtained by a multi-step process that includes spin coating and etching back in order to fill isolated/dense features uniformly. Consequently, a single step planarization technique that deposits a uniform film between isolated and dense features can improve the process efficiency.
USPTO Backgrounds
USPTO Backgrounds