1. Field of the Invention
The present invention relates to a light emitting display element mounted on a wiring substrate in a state that a PN junction surface of a chip is perpendicular to a substrate, a method for connecting the same to the wiring substrate and a method for manufacturing the same.
2. Description of the Related Art
Although a light emitting display element such as a light emitting diode (hereinafter, refer to a "LED") is used as an individual element, it is sometimes used for the purpose that a plurality of elements are disposed in a matrix manner so as to form a dot matrix display unit. Such a use includes a display for means of transportation disposed within a train and a taxi, a letter display portion and a back light of a button for a portable telephone, a display for a control apparatus or a display for an amusement apparatus.
In a typical prior art relating to a method for mounting the LED chip on the dot matrix display unit, after die bonding one of electrodes of the LED chip having the electrodes formed on two surfaces parallel to a PN junction surface onto a wiring substrate of the dot matrix display unit so as to directly junction, the electric connection between the other of the electrodes on the chip surface and the wiring substrate is performed by a wire bonding. In this method for mounting the LED chip, since only one of the electrodes is mounted on the wiring substrate, the PN junction surface becomes in parallel to the wiring substrate and the other of the electrodes is apart from the surface of the wiring substrate, it is necessary to electrically connect by the wire bonding. A disadvantage of this mounting method is that since it is necessary to perform a wire bonding by using a gap between the LED chips, the distance between the chips can not be reduced, a distance of about at least 2 mm is required and a more precise display for the dot matrix display unit can not be performed.
In order to solve this disadvantage, as shown in FIGS. 20A, 20B and 20C, a method for perpendicularly mounting a PN junction surface 2 of an LED chip 1 on a wiring substrate by thin film electrodes 3, 4 has been developed. Here, in the present specification, the method for mounting the chip in such a manner that the PN junction surface is in parallel to the wiring substrate is called as a vertically mounting method, and the method for mounting the chip in such a manner that the PN junction surface 2 is perpendicular to the wiring substrate as shown in FIGS. 20A, 20B and 20C is called as a horizontally mounting method. In the LED chip 1, the thin film electrodes 3, 4 are provided on both ends thereof in the perpendicular direction to the PN junction surface 2, and is electrically connected to wiring patterns 6, 7 formed on the surface of a unit substrate 5 or wiring substrate. At a time of performing this connection, at first, the side surface of the LED chip 1 is fixed to the unit substrate 5 by an adhesive 8 and the thin film electrodes disposed on the both sides are electrically connected to the wiring patterns 6, 7, respectively.
FIG. 20A shows the case that an accuracy for mounting the LED chip 1 to the unit substrate 5 is good. However, as shown in FIG. 20B, in the case that the accuracy for mounting the LED chip 1 to the unit substrate 5 is bad, since a crystal surface 10 is exposed to the side surface of the LED chip 1 and the side edge of the PN junction surface 2 is in a naked state, there is a risk that the PN junction surface 2 is electrically shorted by the wiring pattern 6. FIG. 20C shows a state that the LED chip 1 is vertically disposed in such a manner as to arrange the thin film electrode 4 to a bottom surface. Since the PN junction surface 2 is so structured that a P layer is made thinner than an N layer, the PN junction surface 2 is disposed at a position closer to the other, for example, the thin film electrode 3 among the thin film electrodes 3, 4. The thickness of the thin film electrode 3 is about one-some tenth .mu.m (some thousands angstroms) and is made of a gold (Au) electrode.
The prior art for mounting the LED chip on the wiring substrate in a horizontal state is disclosed in, for example, Japanese Examined Patent Publication JP-B2 56-44591 (1981), and Japanese Unexamined Patent Publications JP-A 54-22186 (1979), JP-A 57-49284 (1982), JP-A 6-177435 (1994), JP-A 6-326365 (1994), JP-A 7-283439 (1995), 8-172219 (1996) and JP-A 9-51122 (1997).
In JP-B2 56-44591 (1981), in a state that an electrically insulating adhesive is applied to an LED chip mounting position on a wiring substrate, one side surface of an LED chip and each part of both electrodes are fixed to each other by the electrically insulating adhesive. The other electrodes of the LED chip and a wiring pattern on the wiring substrate are connected to each other by an electrically conductive adhesive or a solder alloy. A PN junction portion of the LED chip is in a naked state.
In JP-A 54-22186 (1979), a solder is applied on a wiring substrate so as to form a solder layer. An electrode of the LED chip is made of a metal compatible with the solder while leaving a light permeability space. When an LED chip is heated with being mounted at a chip mounting position on the wiring substrate, the solder is melted so that the solder connects between the wiring substrate and the electrode of the LED chip. A PN junction portion of the LED chip is in a naked state.
In JP-A 57-49284 (1982), in a state that an electrically insulating adhesive is applied on an electrically insulating substrate between electrode connecting portions on a wiring substrate, after one side surface of an LED chip is bonded so as to be temporarily connected, the electrode of the LED chip and the wiring pattern on a wiring substrate are connected by a solder alloy. A PN junction portion of the LED chip is in a naked state.
In JP-A 6-177435 (1994), in a state that a window is opened on a tape attached on a wiring substrate so as to determine a mounting position of an LED chip, a heat melted type electrically conductive material is formed on electrodes in both sides of the LED chip, the electrically conductive material melts by heat, thereby electrically connecting the electrode of the LED chip and the wiring pattern on the wiring substrate. A PN junction portion of the LED chip is in a naked state.
In JP-A 6-326365 (1994), an electrically insulating coating is applied to a side surface of an LED chip including both electrodes. Although a PN junction surface is not in a naked state, the electrically insulating coating is also attached to the side end surface of the electrode, so that there is a risk that a trouble occurs in an electrical connection with respect to a wiring pattern. In JP-A 8-172219 (1996), a multi-color LED including a plurality of PN junction surfaces is electrically conducted to a wiring substrate by using an electrically conductive adhesive and a metal brazing material. In these prior arts, the side edge of the PN junction surface is in a naked state. Accordingly, when the PN junction surface is mounted on the wiring substrate in a deteriorated accuracy, there is a risk that the PN junction surface is electrically shorted by the wiring pattern as mentioned above.
FIGS. 21A and 21B show a method for mounting an LED chip and a shape of the same in JP-A 7-283439 (1995) and JP-A 9-51122 (1997). An LED chip 11, a cross section of which is shown in FIG. 21A and a perspective view of which is shown in FIG. 21B, has a recess portion in which a part of a side surface including a periphery of a PN junction surface is sunk with respect to the other crystal portion so as to form an electrically insulating film 12. Thick film electrodes 13, 14 are respectively formed in further both sides of a thin film electrode which is in parallel to the PN junction surface and are electrically conducted to wiring patterns 6, 7 formed on a unit substrate 5 by means of electrically conductive pastes 16, 17, respectively. The electrically conductive pastes 16, 17 have a thermosetting performance.
FIGS. 22A, 22B and 22C show a state that the LED chip 11 of the type shown in FIGS. 21A and 21B is mounted on the unit wiring substrate 5. FIG. 22A shows the case that the mounting accuracy of the LED chip 11 is good and FIG. 22B shows the case that the mounting accuracy of the LED chip 11 is bad. Even when the mounting accuracy is bad, since the electrically insulating film 12 is formed around the PN junction surface, the electric trouble such as an electrical short and a leak is hard to occur. FIG. 22C shows a state that a plurality of LED chips 11 are mounted on the unit substrate 5. The plurality of LED chips 11 are mounted on a lower mold 21 heated by a heater 20 in a state of being fixed to the unit substrate 5 by means of the electrically conductive pastes 16, 17, and each of the LED chips 11 is pressed by an upper mold 22 through a rubber layer 23 from the upper portion. Accordingly, the thick film electrodes 13, 14 of each of the LED chips 11 is in close contact with the wiring patterns 6, 7 on the unit substrate 5, so that the electrically conductive pastes 16, 17 attached on the wiring patterns 6, 7 are set. As a result of this, in a state that the electric connection between the thick film electrodes 13, 14 and the wiring patterns 6, 7 is maintained, the LED chip 11 is fixed on the unit substrate 5 by means of the electrically conductive pastes 16, 17.
FIG. 23 shows a process of manufacturing the LED chip 11 having a partial electrically insulating film 12 on the side surface thereof as shown in FIGS. 22A, 22B and 22C. Step s1 shows a state that a P layer 31 and an N layer 32 are formed on a substrate by diffusion or the like, a PN junction surface 2 is formed on the boundary between the P layer 31 and the N layer 32, and an electrode layer 33 and an electrode layer 4 are respectively formed on one and the other surfaces. The electrode layers 33, 4 are formed by a vapor deposition of metal such as gold (Au) or gold beryllium (AuBe). In step s2, the P electrode provided in the P layer 31 end is manufactured by a photo etching. In step s3, a resist layer 34 is formed on the electrode layer 33 wholly formed on the one surface of an wafer 30, after exposed in accordance with a glass mask, the resist layer is treated by a developer and a rinse, the photo etching of the P electrode is performed, and the electrode layer 33 is removed while respectively leaving the terminal electrode 3. In step s4, a resist layer 35 is again applied on the terminal electrode 3 so that the photo etching is performed so as to leave the periphery of the terminal electrode 3 in a protected state. In step s5, a half-dicing for cutting out a portion between the terminal electrodes 3 from the one surface of the wafer 30 is performed. An adhesion tape is attached to the other surface end of the wafer 30. Cutting of the blade from the one surface end is performed in such a manner as not to completely separate the whole body but to leave the leavings of the dicing, for example, 110 .mu.m. Next, the adhesion sheet is removed from the other surface of the wafer 30, and etching is performed using a mixture of such as a sulfuric acid (H.sub.2 SO.sub.4) and a hydrogen peroxide solution (H.sub.2 O.sub.2).
Next, in step s6, the resist for protecting is removed. An OMR remover is used for removing the resist. Next, in step s7, a resin made by mixing an epoxy resin and an acrylic resin is applied so as to form a resin layer 37 in the cut portion formed by the dicing in step s5. In step s8, an Ag paste electrode 38 is formed on both surfaces of the wafer 30, and in step s9, full-dicing for separating into each of the LED chips 11 is performed. At a time of the full-dicing, the other surface of the wafer 30 is attached to the adhesion sheet and each of the LED chips 11 is completely separated.
In the LED chips 1 and 11 shown in FIGS. 20A, 20B, 20C, 21A and 21B, since the side surface is fully or partly exposed as the crystal surface 10, when the chip mounting position is shifted at a time of being mounted to the unit substrate 5, there is a risk that the portion exposing as the crystal surface 10 is in contact with the wiring patterns 6, 7 on the unit substrate 5. When such a contact is generated, no current flows through the "PN junction surface 2" useful for emitting light of the LED chips 1 and 11, so that a trouble such as the reduction of the chip brightness and no-lighting of the chip is generated. As shown in FIGS. 21A and 21B, even in the case of the LED chip 11 of the type in which the electrically insulating film 12 covers the periphery of the PN junction surface 2, when the shift amount of the chip mounting position exceeds over a certain limit, the exposed portion of the crystal surface 10 is in contact with the wiring patterns 6, 7 on the unit substrate 5, so that the brightness reduction of the chip and the non-lighting of the chip are generated in the same manner as the LED chip 1 shown in FIGS. 20A, 20B and 20C. Accordingly, taking the dispersion of the chip mounting accuracy, the structure is not deemed to be a complete chip structure.
USPTO Backgrounds
USPTO Backgrounds