This invention relates to integrated-circuit chips and, more particularly, to an assembly that includes multiple such chips interconnected by means of a multilevel conductive pattern formed on a wafer.
It is known to utilize a pattern of lithographically formed conductors of semiconductor chips. In some cases, the chips to be interconnected are mounted on the surface of the wafer or in recesses formed in the wafer surface. In other cases, the chips are formed in the wafer as integral parts thereof. Herein, all of these and similar arrangements will be referred to as wafer-scale-integrated (WSI) assemblies.
WSI assemblies are potentially faster than approaches based on individually packaged chips mounted and interconnected on a standard printed-circuit board. In such a standard assembly, the size of the chip package limits the density of circuits in a system. By contrast, in a WSI assembly, unpackaged chips can be packed extremely closed on a single wafer, thus avoiding the major size limitations imposed by package size and thereby enabling faster performance due to substantial decreases in chip interconnection lengths.
WSI assemblies can also improve system reliability. This is so because the major failure sites in conventional electronic assemblies are the connections between different packaging levels: for example, between chips and packages, between packages and boards, and between boards and cables. In a WSI assembly, the placement and interconnection of multiple chips on a single wafer in an integrated array greatly reduces the number and type of these interlevel connections.
In a WSI assembly, it is known that it is desirable to include large-area power and ground conductors in the conductive pattern formed on one surface of the wafer. Separate power and ground metallization planes at respectively different levels would be ideal from an electrical standpoint. But since separate X- and Y-signal metallization levels are also typically required in the assembly, the electrically ideal structure would include four separate metallization levels on the one surface of the wafer. However, such a four-level-metallization structure is quite complex from a fabrication standpoint.
Therefore, in practice, one feasible WSI assembly includes large-area power and ground conductors suitably separated from each other in a common plane in a three-level-metallization structure formed on one surface of the wafer. While not electrically ideal, such a structure is considerably easier and less costly to manufacture than a four-level-metalization one.
Virtually all WSI assemblies require decoupling capacitors. It is known to include such a capacitor under or adjacent to each chip on the wafer. For high-speed operation, it is vital that these capacitors be located as close as possible to their respective chips. But even relatively short leads extending between a decoupling capacitor and its associated chip may have sufficient inductance to deleteriously affect the performance of very-high-speed circuits. Additionally, the intrinsic inductance of the multiple individual capacitors also tends to limit the speed of operation of the circuits includes in the WSI assembly.
Accordingly, considerable technical efforts have been directed at trying to improve the structure and performance of WSI assemblies. It was recognized that these efforts, if successful, had the potential for providing improved highly reliable low-cost electronic systems characterized by extremely high speed.
USPTO Backgrounds
USPTO Backgrounds