1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to a fast method and apparatus for repairing memories by replacing defective rows or columns with redundant rows or columns.
2. Description of the Related Art
Since users generally depend upon the reliability of memory chips for their own systems to function properly, it is common practice for the manufacturers of memory chips to test the functionality of chips at the manufacturing site before the chips are sold to users. The manufacturers"" reputations depend upon the reliability of their chips. As the line width of memory cells within a memory array circuit chip continues to shrink, this reliability becomes more difficult to achieve. An ongoing challenge for the manufacturers of memory devices is to increase memory capacity without sacrificing reliability or suffering decreasing chip yields due to malfunctioning parts.
Before the memory chips are released for shipment, they typically undergo testing to verify that the support circuitry for the memory array and the individual circuitry for each of the memory cells within the memory array is functioning properly. One standard way for testing chip memories involves using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External memory testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive in terms of time requirements and equipment costs.
Partly to address these issues, and partly to provide off-site testing, built-in self-test (BIST) units are now commonly incorporated into memory chips. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the memory chip, and to monitor a single output signal from the chip. The on-board BIST unit generates all the test patterns and asserts (or de-asserts) the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
The BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the BIST unit is able to determine whether the memory cell is faulty. If too many errors are detected, then the fault may exist in the support circuitry.
It is not uncommon for a significant percentage of the memory cells within the chip to fail because of defects in the substrate or errors in the manufacturing process. To compensate for this, many memory chips are provided with a set of extra memory cells that can be used in place of the defective ones. Configuring the memory chip to replace the defective cells is termed xe2x80x9cRepairingxe2x80x9d the memory array. Some memory repair is performed at the manufacturing site. Conventional repairing techniques bypass the defective cells using fuseable links that cause address redirection. However, these techniques require significant capital investment for implementing the repairing process, and moreover fail to address the possibility of failure after shipment from the manufacturing facility.
To reduce repair costs and allow field repairs, some memory chips have been equipped with built-in self test (BIST) and built-in self repair (BISR) circuitry. The BIST circuit detects faults in the memory array and notifies the BISR circuit of the fault locations. The BISR circuitry generally reassigns the row or column containing the failing cell to a spare row or column in the memory array. BIST and BISR are typically performed each time power is applied to the system. This allows any latent failures that occur between subsequent system power-ups to be detected in the field.
BISR circuits traditionally employ content-addressable memories (CAM) that store the addresses of the failing rows or columns. During operation, incoming addresses are supplied to the CAM, and the CAM asserts a xe2x80x9chitxe2x80x9d signal if the incoming address corresponds to one of the stored failing addresses. A rerouting operation is then performed to conduct the desired memory operation on a replacement row or column in the memory array. In fast memories, this multi-step process requires a substantial fraction of the memory access time. A faster BISR method and apparatus would advantageously reduce memory access time, thereby allowing memories to operate at higher clock frequencies.
Accordingly, there is disclosed herein a fast method and apparatus for built-in self-repair (BISR) of memory arrays. In one embodiment, an integrated circuit includes a repair circuit coupled between the address decoder and the memory array. The address decoder receives memory addresses and asserts corresponding word lines. The memory array has default words associated with the word lines, but also includes extra words. By default, the repair circuit maps the word lines from the address decoder to the memory array word lines for the default words. However, the repair circuit includes at least one latch for each of the decoder word lines. When a latch is set, the repair circuit isolates the decoder word line from the default word and remaps the decoder word line to an extra word in the memory. The latches remain set while as long as power is applied, so that accesses to faulty memory words are automatically rerouted without any additional overhead relative to accesses to functional memory words. This may advantageously provide significantly reduced memory access times for only a small increase in hardware cost.
USPTO Backgrounds
USPTO Backgrounds