FIG. 1 shows an example of the conventional semiconductor disk device. This semiconductor disk device 99 is made up of a disk controller 1 and one or more chips of flash memory 3. The controller 1 includes a host interface logic circuit 14 a flash control interface logic circuit 17, I/o buffers 15 and 16, an MPU 12, an MPU interface logic circuit 13, and a data transfer logic circuit 11. It implements data writing to the flash memory 3 in response to a write request and for data 25 transferred from the host 2, which is a workstation, personal computer, or the like.
FIG. 2 shows an example of the arrangement of the flash memory 3. This example shows the arrangement including eight flash memory chips indicated by 31 through 38. The flash memory chips have individual lines 521 through 528 of chip select signals wired from the controller 1 (the chip select signal lines 521–528 are shown generically as a wiring 52 at the controller 1 and the interconnection is not shown). Another wiring 51 represents a data bus, address bus and various control signal lines, and it is a common wiring to all flash memory chips. In other words, the data-pin, the address pin, and the control signal lines other than the wiring 52 have in common the eight flash memory chips, and for example, a signal line A0 in the address bus is connected with each terminal A0 of the eight flash memory chips.
In this arrangement, the controller 1 controls each flash memory chip by selecting a chip in accordance with the chip select signal end issuing a command and address for data to be written.
FIG. 3 shows the write operation of the conventional semiconductor disk device which is arranged as shown in FIG. 2. The case of sequential and cyclic data writing to the flash memory chips 31–38 is shown by the flow chart.
Each block STSn (n=31,32, . . . ,38) is the operation of the controller 1 to check the operational state of a flash memory chip n, and it branches in the direction of “Ready” if the chip is in a Ready status or in the direction of “Busy” if the chip is in a Busy status. Each block DTn (n=31,32, . . . ,38) is the operation of the host 2 to issue a write command to a flash memory chip n and to issue a command of initiating the automatic write operation within the chip for data to be written which is held by the data buffer. Following the operation of DTn, the flash memory chip n writes the data to memory cells based on the in-chip automatic write operation, and it stays in Busy status until the end of the writing.
The foregoing arrangement and operation enable the transfer of data and the issuance of a write command to the next flash memory chip during the automatic write operation within the former chip, and accomplishes the speed-up of data writing based on the parallel writing to multiple flash memory chips.
Recently, an efficient flash memory 15 access method has been devised based on the early execution of a write operation for a flash memory chip which is detected early to be Ready, as illustrated by FIG. 10 of Japanese Patent Unexamined Publication No. H10-63442.
This patent publication No. H10-63442, shown by FIG. 10, 20 is a semiconductor disk having 16 flash memory chips, and for one pattern of the write operation, it can proceed to the write operation for any flash memory chip which becomes Ready among three flash memory chips having high, medium and low write-in priority levels.
However, a description is given of the problem which occur when the write operation is performed with the aforementioned configuration.
The case is considered in which, as shown in FIG. 4, a flash memory chip indicated by chip No. 1 (hereinafter, called chip 1) is a high write-in priority chip, chip 2 is a medium write-in priority chip and chip 3 is a low write-in priority chip. When chips No. 8 and No. 13 are in Ready status and other chips than the chips No. 8 and No. 13 are in Busy status, the write operation is performed according to the flow chart in FIG. 10 of the patent publication No. H10-63442. Although the chip in which the write operation is performed has its execution ability at the steps S19, S21 and S23 as in the FIG. 10, the decision of the execution ability is performed only for a high priority chip (chip 1) in the step S19, for a medium priority chip (chip 2) in the step S21, and for a low priority chip (chip 3) in the step S23. Despite the existence of chips (chips No. 8 and No. 13) being in the Ready status where the write operation is available, the decision that the write operation is unavailable is made and while the write operation is not performed, the next step S25 is carried out.
In other words, in the conventional configuration, even if one or more flash memory chips exist in a Ready status after the write operation is completed, the problem is raised in which the next write operation can not be performed immediately.
Recently, in Symp. on VLSI Circuits Tech. Digest, 1996, pp. 174–175, a flash memory having multiple banks (hereinafter called “multi-bank flash memory”) as a scheme of increasing the number of bits of simultaneous writing on a flash memory chip has been introduced. However, the multi-bank flash memory chip has Busy status during the writing of data to memory cells of one bank, while other banks are left inaccessible. Therefore, this flash memory is problematic in that individual banks cannot be controlled separately from the outside.
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