1. Field of the Invention
The present invention relates to priority encoders.
2. Description of the Related Art
Priority encoders are circuits that serve to acknowledge the request having the highest priority from among a plurality of requests arriving as active signals to the encoder via request lines. A request acknowledgment includes enabling a circuit (often a microprocessor) so that the circuit, for example, executes the task corresponding to the request. One or more of several agents or components of a computer system, for example, may simultaneously request permission to use a shared resource such as a random access memory (RAM). The priority encoder operates based on an implicit priority ordering or encoding scheme which defines which of the request inputs has which priority.
Each request line is associated with a given agent and with a given rank. For N request lines corresponding to N agents, there may be, for example, rankings from 1 to N associated with each of the N request lines, where each has a unique ranking. The priority encoder acknowledges one request at a time through acknowledgment lines. These may be respectively coupled to the particular devices making the requests, to let the requesting device know whether or not its request is acknowledged. In some encoders, the acknowledgment lines directly correspond to request lines, and the encoder transmits on the acknowledgment lines the acknowledged request only. In other encoders, the acknowledgment lines provide the binary rank of the acknowledged request.
Priority encoders typically contain a set of logic gates which implements a given priority encoding scheme. The priority scheme is thus hardwired and not easy to change. Priority encoders are typically fabricated as part of an integrated circuit (IC), for example, within a semiconductor chip. Chips are formed in the substrate of a physical wafer, e.g. a silicon wafer. Typically, several chips are formed in each wafer. A wafer is a very thin, flat disc of a given diameter. The manufacturing process consists of operations on the surface and substrate of the wafer to create a number of chips. Once the wafer is completely processed, it is cut up into the individual chips, the size of which depends on the number of components and complexity of each chip. For a given chip and the IC it contains the priority schemes of priority encoders within the IC cannot be changed once the IC has been fabricated.
In the present invention, a programmable priority encoder having a plurality of request inputs and a corresponding plurality of acknowledge outputs. A configurable priority encoder subunit implements one of a plurality of priority schemes in response to a priority control word corresponding to the priority scheme. The configurable priority encoder subunit acknowledges, on a corresponding one of the acknowledge outputs, a request having a highest priority, in the priority scheme, of all current requests on the plurality of request inputs.
USPTO Backgrounds
USPTO Backgrounds