1. Field of the Invention
The present invention relates to a semiconductor device having a configuration in which a signal voltage of a complementary bit line pair is amplified by a sense amplifier.
2. Description of Related Art
In semiconductor devices of recent years such as DRAM, operating voltages of a memory cell array have been lowered with a reduction in manufacturing scale. This causes a problem that when a signal voltage transmitted from a memory cell through a bit line is amplified by a sense amplifier in a read operation of a semiconductor device, sufficient sensing margin cannot be obtained. Thus, techniques for improving the sensing margin in the read operation have been proposed, in which dummy cells having the same structure as memory cells or dummy cells having a structure of a metallic capacitance element in the memory cell array are provided (for example, see Patent References 1 to 4).
For example, Patent Reference 1 discloses a technique in which all dummy cells connected to a bit line are brought into a selected state in a bit line equalizing operation, and after temporarily setting all the dummy cells into a non-selected state prior to a read operation, dummy cells on the side of a non-selected bit line are subsequently selected simultaneously with selected memory cells. Further, for example, Patent Reference 2 discloses a technique in which dummy cells on the side of a non-selected bit line are controlled in both an amplification operation and a bit line equalizing operation so that capacitances of a bit line pair become equal to each other. Further, for example, Patent Reference 3 discloses a technique in which memory cells and dummy cells on a non-selected bit line are selected simultaneously and thereafter the both cells are brought into a non-selected state and are disconnected from a bit line pair so that capacitances of the bit line pair become equal to each other in an amplification operation, and only memory cells selected after the amplification operation are selected again. Further, for example, Patent Reference 4 discloses a technique in which when activating a word line, a dummy word line connected to a bit line via a capacitance is driven by a predetermined driving method.    [Patent Reference 1] Japanese Patent Application Laid-open No. H7-153258    [Patent Reference 2] Japanese Patent Application Laid-open No. H9-82084    [Patent Reference 3] Japanese Patent Application Laid-open No. H11-149785 (U.S. Pat. Nos. 6,023,438 and 6,288,961)    [Patent Reference 4] Japanese Patent Application Laid-open No. H7-201199
However, even when applying the above techniques to the memory cell array, it is insufficient to improve the sensing margin in the read operation. That is, in the technique of Patent Reference 1, an increase in consumption current is inevitable when potentials of all dummy word lines are temporarily lowered. The increase in consumption current brings noise to the sense amplifier. Further, since the capacitances of the bit line pair are not balanced when a restoring operation after the read operation is finished, there is a risk that an equalizing potential that should be stabilized to VDD/2 deviates from VDD/2. Further, in the techniques of Patent References 2 and 3, potentials of the dummy cells deviate from VDD/2 in a situation where current leak occurs in the dummy cells, which causes noise to occur in the read operation and thereby the sensing margin is reduced. In order to deal with this problem, Patent Reference 2 also discloses a configuration (a transistor and a control signal) for arbitrarily setting the potentials of the dummy cells. However, this configuration inevitably requires an increase in area of the dummy cells, and additionally there arises a problem that the capacitance balance is lost due to a difference in structure between the dummy cells and the memory cells. Further, in the technique of Patent Reference 3, since the amplification operation is started after allowing the memory cells and the dummy cells to be in a non-selected state temporarily, there arise problems of a decrease in reading speed and an increase in consumption current. Meanwhile, in the technique of Patent Reference 4, since each memory cell is controlled to be in the selected state and each dummy cell is controlled to be in the non-selected state respectively at the same timing in the read operation, electric charge supplied from the memory cell to the bit line flows into the dummy cell, which reduces the signal voltage of the bit line so as to decrease the sensing margin.
USPTO Backgrounds
USPTO Backgrounds