The present invention relates to a charge coupled device image sensor, and more particularly to a horizontal signal charge transfer device capable of operating at high speed.
Charge coupled device (CCD) image sensors typically include a silicon or other semiconductor substrate, an optical-electrical conversion region for generating charges corresponding to a image signal in which a plurality of optical-electrical conversion devices (for example, photodiodes) for converting an optical signal into an electrical signal are arranged in a matrix formation, a plurality of vertical charge coupled devices (VCCD) for transferring image signal charges generated by the optical-electrical conversion devices in a single vertical direction and formed in the single vertical direction with constant spacing between the optical-electrical conversion devices, a horizontal charge coupled device (HCCD) formed at the output sides of the VCCDs to transfer image signal charges transferred from the VCCDs in a horizontal direction, and a sensing amplifier for sensing image signal charges transferred from the output side of the HCCD.
A conventional HCCD of the CCD image sensor will hereinafter be described in conjunction with the accompanying drawings. FIG. 1a is a sectional view showing the structure of the conventional HCCD. FIG. 1b is a diagram showing potential profiles in the structure of FIG. 1a. FIG. 1c is a clock timing diagram for transferring signal charges in the structure shown in FIG. 1a.
Referring to FIG. 1a, the conventional HCCD comprises a n-type silicon substrate, a p-type well 1 formed in the surface of the n-type silicon substrate, an n-type buried CCD (BCCD) 5 formed in the surface of the p-type well 1 to transfer signal charges, an insulation film 2 formed on BCCD 5, a plurality of equally spaced first charge transfer electrodes 3 of n-type semiconductor formed on the insulation film 2 to apply the clock signals shown in FIG. 1c, and a plurality of second charge transfer electrodes 4 of n-type semiconductor formed between the plurality of first charge transfer electrodes 3 and isolated electrically from the first charge transfer electrodes 3 by insulation film layer 2a.
Two clock signals H0.sub.1, H0.sub.2 are alternately applied to a plurality of electrode pairs where each electrode pair comprises a first charge transfer electrode 3 and an adjacent second charge transfer electrode 4. One clock signal H0.sub.1 always has an inverted level with respect to that of the other clock signal H0.sub.2.
In the conventional HCCD shown in FIG. 1a, p-type ions are implanted in the BCCD region 5 below the second charge transfer electrodes 4, using the first charge transfer electrodes 3 as a mask, before the formation of the second charge transfer electrodes 4. A plurality of barrier layers 6 having a low concentration are thereby formed.
The operation of the conventional HCCD with the above-mentioned construction will hereinafter be briefly described. As shown in FIG. 1c, when the clock signals H0.sub.1, H0.sub.2 are alternately applied to the plurality of electrode pairs in which each pair comprises a first charge transfer electrode 3 and an adjacaent second charge transfer electrode 4, the HCCD has step-shaped potentials, thereby enabling signal charges to be moved in a single direction. Although one of the clock signals H0.sub.1, H0.sub.2 is simultaneously applied to a first charge transfer electrode 3 and an adjacent second charge transfer electrode 4, the HCCD always has step-shaped potentials since the plurality of barrier layers 6 are formed in the BCCD region 5 at locations below the lower parts of associated second charge transfer electrodes 4. The signal charges are therefore transferred in a single direction if the clock signals H0.sub.1, H0.sub.2 are alternately applied to the first charge transfer electrodes 3 and the second charge transfer electrodes 4.
As mentioned above, the conventional HCCD manufacturing technique involves implanting impurity ions additively in the BCCD channel 5 to form the barrier layers 6 which make the step-shaped potentials in the HCCD upon the application of clock signals H0.sub.1,H0.sub.2. It is, however, easy for the signal charges to be trapped in the barrier layers 6, due to the implanted impurity ions, when the signal charges are transferred in a single direction. Unfortunately; this trapping of the signal charges causes a deterioration of the charge transfer efficiency (CTE).
USPTO Backgrounds
USPTO Backgrounds