1. Field
The present invention relates to an improvement of a reverse block-type insulated gate-type bipolar transistor (hereafter abbreviated to IGBT) manufacturing method that allows an IGBT, with which it is normally common to secure reliability only for forward blocking voltage capability, to maintain reliability for reverse blocking voltage capability equivalent to that of the forward blocking voltage capability.
2. Description of the Related Art
A reverse block-type IGBT is a semiconductor device that allows an IGBT, normally and commonly used in a circuit in which it is sufficient to secure reliability only for forward blocking voltage capability, to maintain reliability for reverse blocking voltage capability equivalent to that of the forward blocking voltage capability.
Normally, in a power converting device such as an inverter circuit or chopper circuit using a semiconductor device, a normal IGBT designed in such a way that reliability of only forward blocking voltage capability is secured has been used as a switching element, as it is used with a direct current power source. However, consideration is being given to a matrix converter such as a direct link type converter circuit that uses a bidirectional switching element, being an AC (alternating current)/AC conversion, an AC/DC (direct current) conversion, or a DC/AC conversion, and has a better power conversion efficiency. In this case, when configuring the bidirectional switching element with an inverse-parallel connection of the normal IGBT, it becomes necessary to connect diodes for blocking a reverse voltage in series with the IGBT, the cost increases commensurately, and the external form becomes larger. Therefore, to make the bidirectional switching element less costly and more compact, there has been a demand for a reverse block-type IGBT that can eliminate reverse voltage blocking diodes by adopting a structure that provides reverse blocking voltage capability, which previously had not been considered for the normal IGBT, with reliability equivalent to that of the forward blocking voltage capability.
With the normal IGBT, as a flat, reverse pressure resistance p-n junction between a p-type collector layer and an n-drift layer on the rear surface side of a semiconductor substrate is left exposed in a semiconductor chip side edge surface, which is a cutting surface when the semiconductor substrate is cut and made into semiconductor chips, it does not have reliability as a reverse block. In the reverse block-type IGBT, in order to secure reverse block voltage capability, the flat, reverse pressure resistance p-n junction is configured such that it is bent so as not to be cut and exposed, and extended to the front surface side of the semiconductor chip. Furthermore, its jointing end is protected by a front surface insulating film, and reliability is secured. In order to cause the flat, reverse pressure resistance p-n junction to bend to the front surface side, there is a need for a p-type diffusion layer, which is a p-type diffusion layer of the same conductivity type as the p-type collector layer, formed on the semiconductor chip side edge surface from the rear surface (the p-type collector layer side) to the front surface of the semiconductor chip. The p-type diffusion layer is a separation layer. The invention relates to a manufacturing method whereby the separation layer is formed.
FIGS. 2A to 2C are main portion sectional views of a semiconductor substrate (which may hereafter be referred to as a wafer) showing in step order one manufacturing method whereby a separation layer in a previously known reverse block-type IGBT is formed. FIGS. 2A to 2C show a method of forming the separation layer using a coating diffusion. First, a dopant mask oxide film 2 with a thickness of around 2.5 μm is formed on a wafer 1 using a thermal oxidation method (FIG. 2A). Next, an aperture 3 for causing boron, a p-type impurity source, to diffuse is formed on the oxide film using patterning and etching (a photolithography technique) (FIG. 2B). Next, a boron source 5 is applied over the aperture 3, after which a high temperature, long-time heating process is carried out using a diffusion furnace, and a p-type diffusion layer with a depth of around a few hundred micrometers is formed (FIG. 2C). The p-type diffusion layer becomes a separation layer 4. Subsequently, as shown in FIG. 3, which is a reverse block-type IGBT completion diagram, after a front surface side MOS structure 10 is formed, the wafer is made thinner by grinding from the rear surface side until reaching the vicinity of the leading edge of the separation layer 4 (the broken line of FIG. 2C). A rear surface structure configured of a p-type collector layer 6 and a collector electrode 7 is formed on the ground surface (FIG. 3). By cutting the wafer along a scribe line positioned on a central line of a surface pattern of the separation layer 4, the reverse block-type IGBT chip shown in the FIG. 3 sectional view of a vicinity of a cutting end portion 8 is obtained.
FIGS. 4A to 4C are main portion sectional views of a wafer showing in step order another manufacturing method whereby the separation layer 4 in the previously known reverse block-type IGBT is formed. FIGS. 4A to 4C are main portion sectional views of a semiconductor substrate showing in order steps of forming a separation layer 4a having the same function as the separation layer 4 by forming a diffusion layer along approximately perpendicular side edge surfaces of a trench (groove) 11 dug perpendicularly from the front surface in the wafer 1.
First, a trench formation etching mask is formed with the oxide film 2 of a thickness of a few micrometers (FIG. 4A). Next, the trench 11 of a depth of around a few hundred micrometers is formed by dry etching (FIG. 4B). Next, an impurity (boron) is introduced to the side walls of the trench 11 using vapor-phase diffusion, forming the p-type separation layer 4a (FIG. 4C). The inside of the trench is filled with an insulating film and a reinforcement material such as polysilicon, and the front surface side MOS structure 10, rear surface collector layer 6, and collector electrode 7 necessary for the rear surface grinding and IGBT are formed. Next, by cutting the IGBT chip off from the wafer 1 by dicing along a scribe line positioned in the center of the trench 11, or between two trenches not shown, the reverse block-type IGBT shown in the FIG. 5 sectional view of the vicinity of the cutting end portion 8 is obtained (JP-A-2-22869, JP-A-2001-185727, and JP-A-2002-76017).
With the method of forming the separation layer of the reverse block-type IGBT shown in FIGS. 2A-2C using coating diffusion, in order to apply the boron source (a liquid boron diffusion source) from the front surface, to cause the boron to diffuse, and to form the p-type separation layer with a diffusion depth of around a few hundred micrometers, a high temperature, long-time thermal diffusion process is necessary. As a result, a depreciation of quartz fixtures such as a quartz board, quartz tube, and quartz nozzle configuring the diffusion furnace, contamination from a heater, a reduction in strength due to a quartz fitting devitrification phenomenon, and the like, are liable to occur more frequently, and the manufacturing cost increases. Also, in the coating diffusion method of forming the separation layer, a thick oxide film of good quality must be used in order that the mask oxide film can tolerate a long-time boron diffusion, and that there is no penetration of the oxide film by the boron. As a method of obtaining a mask which is highly durable in this way, that is, a good-quality silicon oxide film, a thermal oxidation method is known.
When forming the p-type separation layer using high temperature, long-time (for example, 1,300° C., 200 hours) boron diffusion in this way, a thermally oxidized film with a thickness of approximately 2.5 μm is necessary for effective durability of the mask oxide. For the formation of a thermally oxidized film with a thickness of 2.5 μm, the oxidation time needed at an oxidizing temperature of 1,150° C., for example, is approximately 200 hours for a dry (a dry oxygen atmosphere) oxidation with which a good-quality oxide film can be obtained. Furthermore, as a large amount of oxygen is introduced to the inside of the wafer during the oxidation processes, crystal defects such as oxygen precipitates and oxidation-induced stacking faults occur, and problems of device characteristic depreciation and reduction in reliability also occur due to the occurrence of an oxygen donor phenomenon.
Furthermore, with the diffusion after the boron source application, because a high temperature, long-time diffusion process is normally carried out in an oxidizing atmosphere, interstitial oxygen is introduced to the inside of the wafer. As a result, crystal defects such as oxygen precipitates, the oxygen donor phenomenon, oxidation-induced stacking faults (OSF), and slip dislocation also occur in this diffusion process. It is known that the leakage current increases at a p-n junction formed in the vicinity of these crystal defects, and the pressure resistance and reliability of a thermally oxide film formed in the vicinity of the crystal defects of the wafer depreciate considerably. Also, the oxygen taken into the wafer during the diffusion may become a donor, causing a problem wherein the pressure resistance decreases. Also, with the separation layer formation method using the coating diffusion as shown in FIGS. 2A to 2C, the boron diffusion proceeds from the aperture of the mask oxide film approximately isotropically up, down, left, and right in the silicon bulk. As a result, when carrying out boron diffusion of 200 μm in the depth direction, the boron simultaneously diffuses and spreads 160 μm in a sideways direction too, forming an obstacle to the problem of reducing the chip size.
With the separation layer formation method utilizing the trench shown in FIGS. 4A to 4C, a trench is formed by dry etching, and boron is introduced to the side walls of the formed trench, thereby forming the p-type separation layer. Subsequently, the trench is filled with an insulating film and a reinforcement material such as polysilicon. As the p-type separation layer shown in FIG. 4 formed in this way can utilize a narrow trench with a high aspect ratio, it is more advantageous with relation to the contraction of a device pitch than the p-type separation layer using the thermal diffusion of FIGS. 2A to 2C. However, the processing time needed for etching to a depth of around 200 μm when using a typical dry etching device is around 100 minutes per wafer, which presents other problems such as an increase in lead time, and an increase in maintenance frequency. Also, when using a silicon oxide (SiO2) film as a mask when forming a deep trench using a dry etching, the selectivity is 50 or less, meaning that a thick silicon oxide film of around a few micrometers is necessary. As a result, new problems occur in that there is an increase in cost and a reduction in yield rate due to the introduction of process-induced crystal defects such as oxidation-induced stacking faults and oxygen precipitates. Furthermore, with the separation layer formation process using dry etching and utilizing a trench with a high aspect ratio, a chemical residue 12, a resist residue 13, or the like, is likely to occur inside the trench 11, as shown in FIG. 6, which causes problems of a yield reduction, decreased reliability, and the like.
Normally, when introducing a dopant such as phosphorus or boron to the side walls of the trench 11, as the side walls of the trench 11 are perpendicular, the introduction of the dopant to the side walls of the trench 11 is carried out by implanting ions with the wafer inclined. However, the introduction of a dopant to the side walls of a trench with a high aspect ratio causes adverse effects such as an effective dose reduction, an accompanying increase in implantation time, an effective projection range reduction, a dose loss due to a screen oxide film, and a reduction in implantation uniformity. As a method for introducing impurities into the trench 11 with a high aspect ratio in order to combat this problem, a vapor-phase diffusion method may be used whereby the wafer is exposed to a gasified dopant atmosphere such as phosphine (PH3) or diborane (B2H6) instead of the ion implantation, but this is inferior to the ion implantation method with regard to precision controllability of the dose. Also, although a step of filling the trench 11 with a high aspect ratio with an insulating film or polysilicon is necessary in order to increase the wafer strength, a space called a void may form inside the trench, and reduced reliability or similar problems occur.
A method of solving the above kinds of problem has been proposed. It is a method whereby, by implanting ions and annealing along tapered surfaces (side edge surfaces) formed by etching V-shaped grooves in the wafer in a latticed pattern in each rectangular, flat chip region, a separation layer 4b is formed on the side edge surfaces of the chip region, as in the trapezoid wafer sectional view shown in FIGS. 7A and 7B. The tapered surfaces formed on the four side edge surfaces of each of the kind of rectangular chip region shown in FIG. 7A can be fabricated by forming a V-shaped groove from either one of the main surfaces of the wafer with a selective anisotropic etching using an alkaline etching solution (JP-A-2006-156926, JP-A-2004-336008, and JP-A-2006-303410). Furthermore, a reverse block-type IGBT having the tapered side edge surfaces shown in FIG. 7B, having tapered surfaces with an inclination reverse of that of the tapered surfaces shown in FIG. 7A, can utilize an emitter side (the upper side of the diagram in FIGS. 7A and 7B) surface more widely than the reverse block-type IGBT shown in FIG. 7A can utilize. Because of this, as an area that can be utilized for an n-type emitter region 15 and p-type base region 16 formed on the emitter side surface layer increases, there is an advantage in that it is possible to increase the current density, and it is possible to reduce the chip area with respect to the same current rating. Also, it is possible, with the reverse block-type IGBT having the tapered surfaces, to form the separation layer 4b using ion implantation and annealing in a far shorter processing time than that of the high temperature, long-time diffusion. Therefore, it is possible to solve the problem of defects caused by crystal defects and oxygen associated with the separation layer 4b formation method using the long-time, high temperature diffusion, and to solve the problem of diffusion furnace damage. Furthermore, as the aspect ratio is lower than with the manufacturing method using the perpendicular trench digging, there is no void or residue, which is a problem when filling the trench with the insulating film, and the dopant can be easily introduced when implanting the ions.
As disclosed in JP-A-2006-156926, JP-A-2004-336008, and JP-A-2006-303410, with the reverse block-type IGBT having a separation layer formed along the tapered surfaces of the V-shaped groove formed by an anisotropic etching, it is possible to avoid the long-time diffusion accompanied by the various previously described adverse effects. However, as the depth of the impurity distribution of the separation layer formed is small, if crystal defects formed accompanying the ion implantation are insufficiently restored even by an activation process and the defects remain, the leakage current when reverse biasing is likely to increase because the crystal defects are near the p-n junction, and it becomes difficult to maintain the reverse pressure resistance. Also, when employing a laser annealing process as a method for a crystal defect recovery process, as it is a short (a few tens of nanoseconds to a few microseconds) laser irradiation and the focal position of the laser irradiation differs between the wafer front surface and side edge surface separation layer, it is known that displacement of the focal point can occur, that the activation of the side edge surface separation layer is likely to be insufficient, and that the crystal defects cannot be sufficiently restored. Furthermore, when carrying out laser annealing, as the laser irradiation regions are small, it is necessary to scan with the laser and irradiate in such a way as to connect the small irradiation regions in a plane, covering the whole of the ion implantation layer, in order to activate sufficiently. At this time, an irradiation mark may be formed during the scan, causing an adverse effect on the pressure resistance characteristics.
USPTO Backgrounds
USPTO Backgrounds