(1) Field of the Invention
The present invention relates to a field-effect transistor, and in particular, to a process of manufacturing the field-effect transistor that operates with stability, which allows the transistor to be miniaturized.
(2) Description of the Related Art
As a field-effect transistor (hereinafter to be referred to as “FET”), a gallium arsenide field-effect transistor (hereinafter to be referred to as “GaAs FET”) as disclosed in Japanese Laid-Open Patent Application No. 6-163604 can be taken as an example. FIG. 1 is a cross-sectional view of a structure of the GaAs FET described in the patent literature as mentioned above.
In the GaAs FET, a mesa 141 having a channel layer (i.e. active layer) is formed on a semi-insulating substrate 140, while a gate electrode 142, a source electrode 143 and a drain electrode 144 are formed on the mesa 141.
FIG. 2 is a top view of the GaAs FET having the structure as described above.
The GaAs FET is a multi-finger FET in which plural unit FETs are electrically connected in parallel. Such GaAs FET has a wiring layout in which the finger portions of the respective source electrode 143 and drain electrode 144 are positioned opposite each other so as to interdigitate, and the finger portions of the comb-shaped gate electrode 142 are formed between the source electrode 143 and the drain electrode 144.
In the GaAs FET having the wiring layout as shown in FIG. 6, it is necessary to reserve a space outside the transistor for forming a common portion (a part A indicated by a dotted line in FIG. 2) that is a base part of the finger portions of the gate electrode 142. Therefore, it is difficult to reduce the chip size of such GaAs FET.
The respective structures shown in FIGS. 3A, 3B, 3C and 3D are some examples (see reference to Japanese Laid-Open Patent Application No. 2005-72671) of the conventional GaAs FET that solves the above problem. FIG. 3A is an outer view of the GaAs FET and FIG. 3B is a top view of the GaAs FET, while FIG. 3C is a cross-sectional view of the GaAs FET at the line b-b′ shown in FIG. 3A and FIG. 3D is a cross-sectional view of the GaAs FET at the line a-a′ shown in FIG. 3A.
In such GaAs FET, a GaAs epitaxial layer 132, a GaAs layer 133 that is to become an operating layer, a AlGaAs layer 134 that is to become a carrier supplying layer, and an n-type GaAs layer 135 that is to become a contact layer with low resistance are sequentially stacked on a substrate 131 that is made of semi-insulating GaAs. Here, the source electrode 123 and the drain electrode 124 are formed on the n-type GaAs layer 135 while the gate electrode 122 is formed on the AlGaAs layer 134. The mesa 121 is made up of the GaAs epitaxial layer 132, the GaAs layer 133, the AlGaAs layer 134 and the n-type GaAs layer 135.
The GaAs FET has a wiring layout in which finger portions 123a and 124a of the respective comb-shaped source electrode 123 and drain electrode 124 are positioned opposite each other so as to interdigitate and the gate electrode 122 is formed in meandering-shape between the drain electrode 123 and the drain electrode 124.
Here, the finger portions 123a and 124a of the respective source electrode 123 and drain electrode 124, and a straight portion 122a of the gate electrode 122 are formed on the mesa 121. The common portions 123b and 124b of the finger portions 123a and 124a of the respective source electrode 123 and drain electrode 124, and a corner portion 122b of the gate electrode 122 are formed on the substrate 131.
The GaAs FET having the structure as described above has a wiring layout in which the meandering gate electrode 122 is formed between the source electrode 123 and the drain electrode 124. Therefore, it is possible to eliminate the common portions of the gate electrode 122, so that the GaAs FET that allows the reduction of the chip size can be realized.
According to the GaAs FET having the above structure, the corner portion 122b of the gate electrode 122 is not formed on the mesa 121 that includes a channel layer. Thus, it is possible to prevent the part located below the corner portion 122b of the gate electrode 122, that is, the part that does not operate as a stable FET, from operating as a FET. As a result, it is possible to realize the GaAs FET that can operate, as a whole, with stability, so as to obtain desired characteristics.
USPTO Backgrounds
USPTO Backgrounds