1. Field of the Invention
The present invention generally relates to analog-to-digital conversion and more particularly to an analog-to-digital conversion circuit and related method.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “analog,” “digital,” “voltage,” “current.” “signal,” “logical signal,” “clock,” “transistor,” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “source,” “gate,” “drain,” “circuit node,” “comparator,” “amplifier,” “latch,” “inverter,” “NAND gate,” “flip-flop,” “resistor,” “current source,” “common-mode,” and “differential circuit.” Terms and basic concepts like these are understood to those of ordinary skill in the art and thus need not be explained in detail here.
Through this disclosure, reference to a logical signal refers to a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal.
A logical signal is said to be asserted when it is high. A logical signal is said to be de-asserted when it is low.
A clock signal is a cyclic logical signal. For brevity, hereafter, “clock signal” may be simply referred to as “clock.”
As is known, an analog-to-digital converter (ADC) receives an analog signal and output a digital signal to represent a value of a sample of the analog signal in accordance with a sampling rate defined by a clock signal. An ADC converter is said to have a high speed if the sampling rate is high. For instance, an ADC of sampling rate of 500 Ms/s (mega-samples per second) may be said to have a high speed. The digital signal output from an ADC is a multi-level signal comprising a certain number of levels. The number of levels determines a resolution of the ADC: the more levels, the higher resolution. For instance, an ADC outputting an 8-level digital signal may be considered a low-resolution ADC. An 8-level signal can be represented by a 3-bit word using a binary code, or a 7-bit word using a thermometer code. Binary code and thermometer code are well known to those of ordinary skill in the art and thus not described in detail here.
A high-speed low-resolution ADC usually employs a flash ADC architecture comprising a plurality of comparators and outputting a digital code of a certain number of bits determined by a resolution of the ADC. For instance, a 8-level flash ADC receives an analog signal and periodically compares the analog signal with 7 reference voltages in accordance with a clock signal, resulting in a digital signal comprising a 7-bit thermometer code representing a value of the analog signal. The 7 reference voltages are equally spaced in levels, wherein a difference between two neighboring levels determines a level of a LSB (least-significant bit) of the ADC. Flash ADC is well known to those of ordinary skill in the art and thus not described in detail here.
One drawback of a flash ADC is that it requires L-1 comparators for outputting a L-level digital signal, and therefore the hardware cost may be too high when L is large. Another drawback of a flash ADC is that the analog signal needs to be compared with L-1 reference voltages, and therefore the loading to the source device that outputs the analog signal may be too heavy when L is large.
What is desired is an ADC that requires fewer comparators and does not require the analog signal to be compared with a large number of reference voltages.
USPTO Backgrounds
USPTO Backgrounds