This invention relates to dynamic random-access-memory (DRAM) arrays made in very-large-scale-integrated (VLSI) form and, more particularly, to a high-performance VLSI DRAM cell that includes a trench capacitor of the high-capacitance (Hi-C) type.
As the trend toward further miniaturization of VLSI DRAM arrays continues, considerable efforts are being directed at trying to reduce the area of the basic memory cell from which the arrays are formed. One such common cell configuration known in the art comprises a single transistor and an associated capacitor, as described, for example in U.S. Pat. No. 3,387,286.
In practice, the surface area of conventional planar-type capacitors included in VLSI DRAM memory cells has been reduced to the point where the charge capacity of such a small-area capacitor barely exceeds the charge levels produced by noise mechanisms such as those attributable to alpha particles. Even planar capacitors of the so-called Hi-C type do not satisfy some of the current design requirements specified for increasingly small-area VLSI DRAM memory cells. (See, for example, "The Hi-C RAM Cell Concept" by A. F. Tasch et al, IEEE Transactions on Electron Devices, Vol. Ed-25, No. 1, January 1978, pages 33-41, for a description of a planar Hi-C memory capacitor.)
In order to realize specified values of capacitance in relatively small-surface-area capacitors, proposals have been recently made for fabricating each cell capacitor as a vertical structure that extends into the substrate of the semiconductor chip in which the VLSI DRAM memory is formed. This so-called trench capacitor design has a major portion of its plates extending into rather than along the surface of the chip. The amount of surface area required per capacitor is only the area of the trench at the surface of the chip. (An article entitled "Depletion Trench Capacitor Technology for Megabit Level MOS dRAM" by T. Morie et al, IEEE Electron Device Letters, Vol. EDL-4, No. 11, November 1983, pages 411-414, contains a description of a memory capacitor of the trench type.)
Many motivations exist for desiring to make VLSI DRAM trench capacitors in Hi-C form analogous to the Hi-C capacitors used in planar structures. The capacitance-to-chip surface area ratio of a Hi-C trench capacitor is high. Additionally, the relatively high capacitance values that are thereby achievable in a VLSI chip minimize the chances of alpha-particle-induced errors occurring therein. Also, since a Hi-C capacitor can operate with its upper plate at the potential of the chip substrate, it is not necessary in such an arrangement to provide isolation between memory cells (beyond satisfying a minimum spacing criterion set by the largest depletion width encountered). All of these advantages of a memory cell that include a Hi-C trench capacitor make it possible to achieve high-density cell packing in a high-performance memory array characterized, for example, by relatively low leakage currents, relatively low parasitic capacitances, relatively low sheet resistance and relatively high cell capacitance per unit area.
In principle, the concept of making the aforementioned memory trench capacitors in Hi-C form is therefore extremely attractive. But the attainment of such a Hi-C structure requires controlled doping of steeply sloped trench walls and, heretofore, no completely effective practical procedure for achieving this has been disclosed. Nor has a simple and reliable procedure been devised heretofore for interconnecting the Hi-C trench capacitor of a memory cell with its associated adjacent transistor. It was apparent that such a fabrication procedure, if developed, would constitute a significant contribution to the realization of very-high-bit-capacity VLSI DRAM arrays.
USPTO Backgrounds
USPTO Backgrounds