The present invention relates in general to a method of manufacturing a semiconductor device and, more in particular, to a method of manufacturing Schottky gate type field effect transistors which comprise a compound semiconductor material such as GaAs.
Conventional Schottky gate field effect transistors or metal oxide semiconductor field effect transistors which comprise GaAs have been used as semiconductor devices in a variety of applications so as to constitute high-frequency amplifiers, oscillators and the like. The importance of these transistors as basic unit elements in integrated circuits (ICs) has been increasing recently.
Under these circumstances, various technical approaches have been made in an attempt to improve high-frequency characteristics of the GaAs MESFETs. In order to improve the high-frequency characteristics of the MESFETs, (1) a capacitance Cgs between the gate and the source must be decreased and/or (2) a transconductance gm of the FET must be increased. A parasitic capacitance must be decreased in order to decrease the capacitance Cgs. On the other hand, a distance between gate and source regions in a substrate must be shortened as much as possible in order to increase the transconductance gm. When the gate-source distance is decreased, a series resistance Rs in the source-gate path can be decreased, so that the transconductance gm can approach an intrinsic transconductance gmO determined in accordance with electrical characteristics of the FET channel region. It is also possible to increase the transconductance gmO itself by decreasing a length of a gate layer.
In order to improve the high-frequency characteristics of the MESFETs, a self alignment technique is adopted in accordance with the above principle. For example, a gate layer is used as a mask when ion implantation is performed to form the source and drain regions. The gate region can be properly aligned with the high impurity regions (i.e., source and drain regions) without overlapping these high impurity regions, thereby decreasing the parasitic capacitance of the MESFETs. However, according to the method described above, a metal which can withstand annealing at a high temperature (e.g., 800.degree. C.) after ion implantation and which has a good Schottky barrier must be used as the gate material. The metal (e.g., W, Mo, Ta, Ti) has generally poor mechanical adhesion (bonding) with GaAs, thereby decreasing the yield of the MESFETs.
In order to solve the above problem, according to Japanese Patent Disclosure (Kokai) No. 58-96769 (Y. Sano et al), a technique is described wherein side portions of the insulating layer for supporting a metal layer as a mask for ion implantation are overetched. By controlling the amount of overetching, the gate-source distance can be decreased so as to decrease the series resistance component. However, overetching is performed prior to ion implantation for forming the source and drain regions in the substrate. As a result, the metal layer as the mask and the side-etched insulating layer are exposed to a high temperature during annealing. Therefore, a mask metal must comprise a metal having a high heat resistance.
According to Japanese Patent Disclosure (Kokai) No. 57-196581 (T. Konuma et al), in order to enhance the maximum oscillation frequency of the GaAs MESFET, a self alignment technique is disclosed to decrease the series resistance between the source and the gate. This self alignment technique provides FETs each having a gate electrode with a T-shaped section. A two-layer structure consisting of a side-etched silicon nitride film and a silicon oxide film is used in place of a metal as a mask layer for ion implantation. In this conventional method, the silicon nitride film is side-etched prior to ion implantation.
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