1. Field of Invention
The present invention relates to an image sensor and a fabricating method thereof. More particularly, the present invention relates to a System-On-Chip (SOC) image sensor having high fill-factor and a fabricating method thereof.
2. Description of Related Art
Image sensors have been widely used in various electronic devices, such as web-cameras, mobile phones with built-in camera, digital still cameras (DSC), and digital video cameras (DV). Typically, image sensors are mainly classified into CCD image sensors and CMOS image sensors. In recent years, concept of System-On-Chip (SOC) is gradually introduced into image sensors. Since CMOS image sensors can be fabricated using standard CMOS processes, it is possible to integrate CMOS image sensors with digital and analog signal processing circuitry.
FIG. 1 is a schematic cross-sectional view of a conventional CMOS image sensor. Referring to FIG. 1, the conventional CMOS image sensor 100 includes a substrate 110, an interconnection layer 120 disposed on the substrate 110, a color filter array 130 disposed on the interconnection layer 120, and a micro-lens array 140 disposed on the color filter array 130. The substrate 110 includes a plurality of isolation regions 112, a plurality of active regions 114 defined by the isolation regions 112, a plurality of CMOS transistors 116 formed on the active regions 114, and a plurality of photo-diodes 118 formed in the active regions 114. The interconnection layer 120 includes a plurality of insulating films 122 and a plurality of metal films 124 stacked on the substrate 110 alternately. The color filter array 130 includes a plurality of color filters 130R for red light penetration, 130G for green light penetration and 130B for blue light penetration. Additionally, the micro-lens array 140 includes a plurality micro-lens 142, wherein each micro-lens 142 is located on one of the color filters 130R, 130G and 130B, respectively.
There are two major drawbacks for the conventional CMOS image sensor. Firstly, the fill-factor, i.e., the ratio of the sensitive area of photo diode 118 to the area of the pixel 114, is low. That is because the photo diode 118 and 4 transistors 116 in a pixel are fabricated on the same silicon substrate, as shown in FIG. 1. Low fill-factor would decrease the signal-to-noise ratio (S/N), deteriorating the quality of the image. This limitation becomes severer with the CMOS technology upgrade or pixel scaling down. Secondly, the conventional CMOS image sensor has thickness and metal layers limitation for the interconnection 120. In order to reduce light R (or G, B) loss before reaching at the photo diode 118 and to suppress the crosstalk between two neighbor pixel 114, the vertical distance between the photo-diode 118 and the color filter array 130 is required to be kept at about 4 micrometers or less. That means both CMOS image sensor and the other circuit parts of SOC can only use at most four layers of metal films 124 for interconnection. In addition, light R (or G, B) scattering and absorption is severer at low-permittivity-dielectric/barrier-dielectric interfaces in region 120 for <=0.13 um Cu/low-k process. These would cause decreases in both S/N and photo sensitivity.
U.S. Pat. No. 6,902,946B2, entitled “Simplified Upper Electrode Contact Structure For PIN Diode Active Pixel Sensor”, and U.S. Pat. No. 6,018,187A, “entitled “Elevated PIN Diode Active Pixel Sensor Including a Unique Interconnection Structure”, discloses a elevated PIN diode sensor, in which the PIN diode is located above the image processing circuitry. However, sensors share a common P-type amorphous silicon layer. This would result in crosstalk between the adjacent sensors.
USPTO Backgrounds
USPTO Backgrounds