1. Field of the Invention
The present invention relates to a driving device for driving load such as a speaker.
2. Description of the Related Art
Information apparatuses such as a mobile telephone have products having functions in which various types of functions are incorporated. Since these information apparatuses are mostly driven by batteries, a time of continuous use is limited. In consideration of many more functions in the near future, it is desirable that each component incorporated in products become consume lower power. For example, as components incorporated in mobile telephones consume higher power, a transmitting power amplifier and a backlight for liquid crystal display are included. Further, a speaker that reproduces sounds such as ring tone melody is one of the components. In recent years, as one of the measures for reduction of power consumption, there are products that the conventional class AB amplifier is replaced by the switching amplifier having high power efficiency in the speaker drive method.
FIG. 8 shows an exemplary configuration of a driving device constructed as a switching amplifier (class D amplifier) having inductive load such as a dynamic speaker as load (see e.g. U.S. Pat. Nos. 614,297 and 6,262,632).
The driving device 3 includes a driving circuit 20 outputting an output signal Vp-n2, an error suppression circuit 11 generating a first error suppression signal Vout1, a pulse width modulation circuit (PWM) 12 as a pulse modulation means outputting switching control signals Vp1 and Vp2 corresponding to pulse modulation signals, a gate driver 13, and low pass filters (LPF1, LPF2) 14 and 15 as a first feedback means.
The driving circuit 20 includes a switching circuit 100 having a plurality of switching elements 101, 102, 103 and 104, and inductive load L1 as the load is connected at terminals between connection points OUTP and OUTN.
Each of the switching elements 101, 102, 103 and 104 (i.e. transistors such as MOSFET) has a first terminal 40 (connection points OUTP and OUTN) connected to one output terminal 50 of the inductive load L1, a second terminal 41 connected to the power source (Vcc) or ground terminal, and a third terminal 42 to which switching control signals Vp1p, Vp1n, Vp2p and Vp2n are inputted.
The switching circuit 100 control the switching elements 101, 102, 103 and 104 with on/off behavior based on the switching control signals Vp1p, Vp1n, Vp2p and Vp2n, respectively, thus controlling supplying of electric power to the inductive load L1. Output terminals 50 and 51 at connection points (OUTP and OUTN) between the terminal of the inductive load L1 and the each first terminal 40 of the switching elements 101, 102, 103 and 104 output an output signal Vp-n2 as a voltage across the inductive load L1.
The low pass filters (LPF1, LPF2) 14 and 15 feed back output signal Vp-n2 at the output terminals 50 and 51 of the driving circuit 20 to terminals 9a and 9b via feedback resistors RF1 and RF2 of the error suppression circuit 11. Here, as the signals fed back, output signals V2a and V2b are used.
The error suppression circuit 11 is constructed as an integrator including a differential amplifier circuit 111, a capacitor C2 connected between terminals 9a and 10a, a capacitor C3 connected between terminals 9b and 10b, input resistors RS1 and RS2 connected between input terminals 8a and 9a and between input terminals 8b and 9b, respectively, and the feedback resistors RF1 and RF2 connected to the terminals 9a and 9b, respectively. The error suppression circuit 11 compare the amplitude of output signals V2a and V2b fed back via the low pass filters (LPF1, LPF2) 14 and 15 with the amplitude of input signal Vin inputted to the input terminals 8a and 8b, thus detecting an error of amplitude between signals. Then, a corrected voltage (i.e. first error suppression signal Vout1 is produced such that the detected error of amplitude between signals is suppressed. Here, continuous processing is performed but discrete processing is not performed.
Here, in FIG. 8, in order to evaluate input reproducibility of the switching amplifier, low pass filters (LPF3, LPF4) 16 and 17 are connected to the output terminals 50 and 51 of the driving circuit 20. Then, output signal Vp-n20 is produced from the output terminals 52 and 53 of the low pass filters (LPF3, LPF4) 16 and 17. In this case, these low pass filters (LPF3, LPF4) 16 and 17 are not necessitated structure elements in the driving device 3, and are no relationship with the operation as a switching amplifier.
The circuit operation is as follows. The pulse width modulation circuit (PWM) 12 produces switching control signals Vp1 and VP2 based on the produced first error suppression signal Vout1. Then, the produced switching control signals Vp1 and VP2 are inputted via the gate driver 13 to the third terminal 42 of the switching elements 101, 102, 103 and 104, thus performing on/off behavior of the switching elements 101, 102, 103 and 104 to control supplying of a current I to the inductive load L1.
FIG. 9 shows the internal configuration of the pulse width modulation circuit (PWM) 12 and gate driver 13.
The pulse width modulation circuit (PWM) 12 includes a triangular wave generator 90 and two comparators 91a and 91b. The triangular wave generator 90 generates a triangular wave as a reference signal. The produced triangular wave is inputted as the comparison processing of the comparators 91a and 91b. The gate driver 13 includes two dead time generation circuits 92a and 92b, and two driving circuits 93a and 93b. 
FIG. 10 shows a timing chart of waveforms of various signals outputted from the pulse width modulation circuit (PWM) 12 and gate driver 13 shown in FIG. 9.
In the pulse width modulation circuit (PWM) 12, the first error suppression signal Vout1 outputted from the terminals 10a and 10b of the error suppression circuit 11 is compared with a triangular wave 302 being the reference signal, and pulse modulation signals Vp1 and Vp2 are outputted as the comparison result.
In the gate driver 13, pulse modulation signal Vp1 is inputted to the dead time generation circuit 92a, and the dead time generation circuit 92a delays the rise or fall time of pulse modulation signal Vp1 by a dead time. Then, the delayed signal is buffered by the drive circuit 93a and outputted as switching control signals Vp1p and Vp1n. The transistors 101 and 102 are controlled based on these switching control signals. Vp1p and Vp1n. 
Similarly, pulse modulation signal Vp2 is inputted to the dead time generation circuit 92b, and the dead time generation circuit 92b delays the rise or fall time of pulse modulation signal Vp2 a dead time. Then, the delayed signal is buffered by the drive circuit 93b and outputted as switching control signals Vp2p and Vp2n. The transistors 103 and 104 are controlled based on switching control signals Vp2p and Vp2n. 
In this manner, in the gate driver 13 of FIG. 10, a non-overlap period (dead time) of about several ns to several 10 ns is inserted in pulse modulation signals Vp1 and Vp2, respectively. Thus, the number of output lines for switching control signals Vp1p, Vp1n, Vp2p and Vp2n become four. As a result, the pair of transistors 101 and 102, or the pair of transistors 103 and 104 performs on-behavior simultaneously at the moment when each signal varies, thus preventing large current from flowing from the power source to the ground.
In the switching amplifier of FIG. 8, output signals V2a and V2b having distorted waveforms due to various error generation factors, such as rise delay of switching signal, fluctuations of power source voltage, and voltage error between the switching waveforms due to a mismatch between the on-resistances of the switching elements, are fed back to the terminals 9a and 9b. Then, an error component between this fed back output signals V2a and V2b and input signal Vin is detected by the error suppression circuit 11. That error is suppressed based on feedback loop gain, and first error suppression signal Vout1 is generated as the voltage in which the error is corrected. This first error suppression signal Vout1 is inputted to the pulse width modulation circuit (PWM) and processed.
FIG. 11 shows a variation of signal level of input signal waveform inputted to the pulse width modulation circuit (PWM) 12. Here, as an input signal waveform in first error suppression signal Vout1 inputted from the error suppression circuit 11 to the pulse width modulation circuit (PWM) 12, the signal waveform at the terminal 10a of the error suppression circuit 11 is shown.
While input signal waveform 300 indicates an input signal waveform under the scheme of FIG. 8, input signal waveform 301 indicates an expected input signal waveform having high input reproducibility. In FIG. 11, the input signal waveform 300 is shifted to an error of Δ from the expected value, compared to the expected input signal waveform 301. Here, reference numeral 302 denotes a triangular wave being the reference signal used when producing a pulse width modulation signal.
As described above, in the pulse width modulation circuit (PWM) 12 as shown in FIG. 8, only the correction of input signal waveform 300 based on feedback loop gain cannot suppress waveform distortion. Then, a predetermined signal having high input reproducibility can not be outputted, thus producing distortion in the output waveform of output signal Vp-n2 (for example, distortion in the waveform illustrated in FIG. 4(C) described later). As a result, in the case that a high-performance product is requested, specification cannot be satisfied.
In the switching amplifier shown in FIG. 8, output signals V2a and V2b are fed back, whereby signal waveform distortion is suppressed by feedback loop gain. However, it is desirable to further improve the input reproducibility of output signal.
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