1. Field of the Invention
This invention relates to an integrated circuit typically exemplified by custom LSI circuits of the gate array type or other types, and more specifically to an integrated circuit having protection devices or circuits for preventing breakdown or degradation of the MOS structure due to transient phenomena, such as excessive voltage pulses or excessive current flows due to static discharges.
2. Description of Related Art
It is generally known in semiconductor integrated circuit art to provide MOS structures with protection circuit or devices for protecting input/output (I/O) cells from damage due to static electricity discharges. In recent semiconductor integrated circuits, especially in Application Specific Integrated Circuits (ASICs) typically exemplified by custom LSI circuits of the gate array type, as described in U.S. Pat. No. 4,942,317, the so-called slice type-I/O cell, in which a plurality of I/O cells (I/O buffers) are connected to one bonding pad to increase the available output current, has been increasingly used. On the other hand, a protection device or circuit for a I/O cell selectively use the following two conventional structures.
1) In the first structure, mutually compensating protection devices or circuits are arranged at opposed polar positions (to be at opposed polar positions means to be at a position on the scribe line side of a bonding pad at a position on the inside of the die on which the bonding pad is formed). The term "mutually compensating protection devices or circuits" means a combination of protection devices or circuits, one protection circuit having a protection function against, e.g., positive voltage pulses, and the other protection circuit having a protection function against negative voltage pulses.
FIG. 1 shows one example of such mutually compensating protection circuits. A first protection circuit 32a (the protection circuit A in FIG. 1) and a secondary protection circuit 33a (the protection circuit B in FIG. 1) are provided, respectively, on the input side of a bonding pad 31a and on the output side of the bonding pad 31a. The first protection circuit 32a is connected to a power bus 34a, and the secondary protection circuit 33a is connected to an internal circuit. The power bus connected to the secondary protection circuit 33a is not shown in FIG. 1. FIG. 2 shows a circuit which is equivalent to the mutually compensating protection circuits of FIG. 1, in which the first protection circuit 32a is provided by, e.g., a p.sup.+ /n.sup.- diode 32b, and the secondary protection circuit 33a is provided by, e.g., an n.sup.+ /p.sup.- diode 33b. In this arrangement, when a positive voltage with respect to ground (GND) is applied to the bonding pad 31 b, the first protection circuit 32b operates forwardly to lower the voltage of the bonding pad 31b with respect to GND. When a negative voltage with respect to GND is applied to the bonding pad 31b, the secondary protection circuit 33b is biased forward to lower the voltage of the bonding pad 31b.
As one example of the protection circuits based on the same idea, FIG. 3 shows the protection circuits described in, e.g., Robert J. Antinone, "Electrical Overstress Protection for Electronic Devices", at page 19. In this circuit, a guard ring 42 is provided around a bonding pad 41. A protection circuit 43 is formed between the guard ring and an n+ diode formed on both sides of the bonding pad 41. A nearby diode 44 is an n.sup.+ diffused resistor diode.
2) In the second structure, the protection circuits are not positioned in an opposed arrangement, but remain mutually compensating. As one example of such mutually compensating protection circuits, FIGS. 4 and 5 show the protection circuits described in Robert J. Antinone "Electrical Overstress Protection for Electronic Devices", at page 18. FIG. 4 is a plan view of the protection device of this circuit, as viewed from above. FIG. 5 is a cross-sectional view of the respective protection circuits. As shown in FIGS. 4 and 5, the two protection circuits 52 and 53 are not positioned in an opposing relationship with respect to the bonding pad 51. However, these protection circuits 52 and 53 also operate in a mutually compensative fashion.
USPTO Backgrounds
USPTO Backgrounds