A programmable logic device (PLD, e.g., a field programmable gate array (FPGA) or a complex programmable logic device (CPLD)) may be used in a variety of applications and may provide certain advantages over other types of devices. For example, a PLD offers the advantage of being reprogrammable in the field (e.g., a field update, with the PLD in its operational environment).
A conventional PLD may be designed for low power applications (e.g., referred to as low power, ultra low power, or zero power PLD) and may provide, for example, a very low standby current (SICC) and consume very little power when PLD signals are not active. For example, PLD signals may include signals to input buffers (e.g., via an input pin) and signals within the PLD (e.g., signals being driven by the input buffers).
A common technique to reduce PLD power usage is to deactivate certain signals, as needed, which are not required to be active. A conventional PLD approach may statically and/or dynamically allow a user of the PLD to deactivate certain internal PLD signals. However, a drawback with this conventional approach is that it only addresses internal PLD signals and does not address power usage of the input buffers or associated circuitry.
As a result, there is a need for improved power management techniques for PLDs.
USPTO Backgrounds
USPTO Backgrounds