In the design and packaging of semiconductor integrated circuits (ICs), there are several areas of concern. Moisture needs to be prevented from entering the circuits because: (1) moisture can be trapped in oxides and increase the dielectric constant thereof; (2) moisture can create trapped charge centers in gate oxides causing threshold voltage shifts in complementary metal-oxide-semiconductor (CMOS) transistors; (3) moisture can create interface states at the Si-gate oxide interface causing degradation in the transistor lifetime through increased hot-electron susceptibility; (4) moisture can cause corrosion of the metal interconnect, reducing the reliability of the IC; and (5) when trapped in Si-oxide, moisture can reduce the oxide mechanical strength and the oxide may become more prone to cracking due to tensile stress. Ionic contaminants can also cause damage to the IC as they can diffuse rapidly in silicon oxide. For instance, ionic contaminants can cause threshold voltage instability in CMOS transistors and alter the surface potential of the Si surface in the vicinity of the ionic contaminants. Dicing processes that separate adjacent IC dies from one another may cause potential damage to the IC. Furthermore, subsequent wet etch and/or curing processes can cause layer peeling.
A seal ring has been used in the industry to protect the IC from moisture degradation, ionic contamination, and dicing processes, but improvement has been desirable. In particular, subsequent wet etch and curing processes may cause peeling of a polyimide layer over the seal ring resulting from stress inducement and chemical attack (e.g., dilute HF) at the polyimide layer interface. Accordingly, improved methods of semiconductor device fabrication and devices fabricated by such methods are desired.
USPTO Backgrounds
USPTO Backgrounds