1. Field of the Invention
The present invention relates to an antifuse replacement determination circuit of a semiconductor memory device, and in particular, those circuits for detecting that the replacement using an antifuse element has been reliably performed, and also relates to a relevant antifuse replacement determination method.
Priority is claimed on Japanese Patent Application No. 2007-146718, filed Jun. 1, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
With respect to dynamic memory circuits, a so-called “AF (antifuse) circuit” is known, in which an address of a bad bit (i.e., a bad memory cell) is stored by destroying a semiconductor element (a capacitance element or a MOS transistor), and when this address is selected, data is stored not in an ordinary DRAM memory cell, but in an SRAM element (or a flip-flop circuit). In the following description, such a replacement of an ordinary memory cell with an SRAM element (or a flip-flop circuit) is called “replacement by AF” or “AF replacement”. In addition, the destroyed semiconductor element is called an “AF element”.
When a memory device having an AF circuit is initialized so as to be actually used, the target address with respect to the AF replacement should be defined (this is called “Load”, which will be explained in detail later) by determining whether the relevant AF element has been destroyed. Such a determination is performed by supplying, in advance, an (electric) charge having a specific level to a node (or contact point) in the vicinity of a node of the AF element, and comparing the level of the charge with a reference level so as to determine whether the charge has escaped through the node due to the destruction of the AF element. Generally, the reference level is set to an optimum value for determining whether or not the AF element has been destroyed (called “AF destruction determination” below).
With respect to DRAMs, the yield decreases when a device, which does not normally operate and is determined to be a substandard product in a screening process, is found. Such a decrease in the yield prevents the reduction of the screening and forwarding cost. Recently, in most cases, approximately one or two bits which have a physical defect in each relevant memory cell cause a substandard product. Therefore, when such one or two bits are replaced by an AF circuit so as to produce a standard product, the screening yield can be improved, and the manufacturing cost can be reduced.
More specifically, when one bit is replaced, the AF circuit generally have a number of AF elements, the number corresponding to the number of addresses (e.g., 26 addresses, where X=X0 to X13, Y=Y0 to Y9, Bank0, and Bank1); corresponding AF circuits for destroying and determining the AF elements; and another AF element and another AF circuit for determining whether the antifuse of the relevant one bit is to be activated. That is, when there are 26 addresses, 27 sets of the AF element and the AF circuit are provided.
When a substandard product is found in a screening process, first, the address of the bad bit is confirmed, and the AF element corresponding to this address is destroyed. This operation is called “Store”, and the process of performing Store is called a “Store process”. Next, it is confirmed if the address, which has been stored due to the destruction of the AF element, coincides with the anticipated address. This operation is called “Verify”, and the process of performing Verify is called a “Verify process”.
After that, AF replacement is performed, and normal operation of the relevant DRAM is confirmed by performing the screening process again. In the normal function of re-screening or ordinary use thereafter, when the relevant DRAM is initialized immediately after the power-on, an AF destruction determination similar to the above Verify is performed, and the result thereof is latched (i.e., stored). This operation is called “Load”, and the process of performing Load is called a “Load process”.
When the address of the relevant bit, to which the AF replacement has been applied, is selected, data is written to or read from the relevant SRAM or flip-flop, instead of the corresponding DRAM memory cell, in accordance with an AF hit signal which is output from the relevant AF circuit based on the determination result stored in the Load process. As a bad memory cell is replaced with an SRAM or flip-flop, the relevant device, which is determined to be a substandard product without AF replacement, is converted into a standard product.
FIG. 5 shows a conventional AF destruction determination circuit. In FIG. 5, an AF destruction determination sequence control part 1A controls each part shown in FIG. 5 so as to perform the AF destruction determination. A charging control part 2 generates a “/Charge” signal for charging a node (or contact point) X1 of an AF element 11 via a node X0 in the vicinity of the AF element 11. A Verify execution part 3A generates a Verify signal for commanding the execution of the Verify process. A Load execution part 5 generates a Load signal for commanding the execution of the Load process. An AF destruction result determination part 6 determines whether a result of the AF destruction determination coincides with the anticipated result, based on a determination result BB obtained through the Verify and Load processes.
Although detailed explanations of the AF element 11 and an AF element destruction circuit 12 are omitted, a DRAM-cell capacitance element or an N-channel transistor is used as the AF element, and the AF element destruction circuit 12 generates and controls a high voltage for destructing such a capacitance element or a gate oxide film of the transistor. The AF element has the node X1, and the other node thereof is ordinarily connected to VSS (the source potential). Therefore, the node X1 of the destroyed AF element is conductive with VSS (via a low resistance).
The gate of a P-channel transistor P1 is connected to the output of a NOR circuit 13. When the Verify or Load signal input into the NOR circuit 13 has a value of “1”, the P-channel transistor P1 is switched on. That is, in the Verify and Load processes, a control for making the node X1 of the AF element be conductive with the node X0 of a comparison and determination circuit 20 (“AMP”).
In the Verify and Load processes, a P-channel transistor P0 is switched on when charging the nodes X0 and X1 to an initial precharge level VCHARGE (e.g., 1.4V). The comparison and determination circuit 20 compares the potential of the node X0 with a reference level VREF0 (e.g., 1.1V). A flip-flop circuit 30 above the comparison and determination circuit 20 latches (i.e., stores) a determination result BB output from the comparison and determination circuit 20.
Below, the relevant AF destruction determination in accordance with a conventional technique will be explained with reference to FIGS. 5 and 6. In the AF destruction determination in the structure of FIG. 5, first, (i) the P-channel transistor P1 is switched on by means of the Verify or Load signal, so that the nodes X0 and X1 are conductive with each other, and (ii) the P-channel transistor P0 is switched on by means of the /Charge signal (see time t1 in FIG. 6), so as to precharge the nodes X0 and X1 to the level VCHARGE. This process corresponds to the “precharge period T1 using VCHARGE” in FIG. 6.
Next, the state of the /Charge signal is switched so as to switch off the P-channel transistor P0, thereby setting the nodes X0 and X1 to be in a floating state (see time t2 in FIG. 6). If the AF element 11 has not been destroyed, no charge loss occurs at the nodes X0 and X1, and thus they maintain the level VCHARGE (here, 1.4V, see the discharge curve Ds1 in FIG. 6). This level is higher than the reference level VREF0 (here, 1.1V) applied to the other input of the comparison and determination circuit 20. Therefore, a result of the AF destruction determination, which indicates that the AF element has not been destroyed, is obtained, and is stored as the determination result BB. In this case, as the anticipated value with respect to Verify indicates that the AF element has not been destroyed, it coincides with BB, so that the result of Verify is “Pass” (which means passing the relevant examination).
If the AF element 11 has been destroyed, the node X1 is conductive with the other node VSS, so that charge loss occurs from the nodes X0 and X1, and the potential levels thereof decrease (see the discharge curve Ds2 in FIG. 6). When the decreased level is lower than VREF0 (1.1V), a result of the AF destruction determination, which indicates that the AF element has been destroyed, is obtained, and is stored as the determination result BB. In this case, as the anticipated value determined in Verify indicates that the AF element has been destroyed, it coincides with BB, so that the result of Verify is Pass.
The speed and level of the above decrease with respect to the nodes X0 and X1 are considerably affected by the degree of the destruction of the AF element. That is, when the AF element has been sufficiently destroyed, it has a sufficiently low resistance, and the potential of the node X0 becomes sufficiently lower than VREF0 (1.1V). In this case, the determination is accurately performed. However, when the AF element has not been sufficiently destroyed, it has a relatively high resistance, so that the decreasing speed of the potential of the node X0 is low, and the potential level stays around VREF (1.1V) (see the discharge curve Ds3 in FIG. 6).
When the potential of the node X0 stays higher than VREF (1.1V), the result of the AF destruction determination, which indicates that the AF element has not been destroyed, is obtained even though the operator or user believes that the AF element has been destroyed. As this result is stored as BB, it does not coincide with the relevant anticipated value, so that the result of Verify is “Fail” (which indicates failing the relevant examination).
The above-described process corresponds to the “X0-reference level comparison and determination period T2”, in which the level of the /Charge signal is high, the P-channel transistor P0 is switched off, and the comparison and determination circuit 20 is activated.
With respect to a device, which has been determined to be a Fail device in the Verify process, no address replacement by means of the AF element 11 is performed in the Load process during actual use. In the re-screening process (performed after the AF replacement process) or during actual use, a DRAM memory cell (in such a device), which has been determined to be a bad cell in the former screening, is selected, so that the device is determined to be a substandard product, and thus does not contribute to an increase in the yield. Therefore, the operation from the Store process is performed again.
The relevant conventional AF replacement processes will be shown in FIG. 7. In a screening process 51, a bad address is extracted from a device which is determined to be a substandard product. The AF element 11 corresponding to the above address is destroyed in a Store process 52. In a Verify process 53, the result of the AF element destruction is confirmed by the Verify operation using VREF0 (1.1V) as the reference voltage. When the relevant device obtains a result of Pass, it is forwarded to the next re-screening process 54.
In a DRAM initializing sequence of the re-screening process 54, an AF destruction determination similar to that performed in the Verify process 53 is performed in the Load operation. The result thereof is stored, and the relevant bad bit is replaced by means of the AF element 11, so that the device which obtains the Pass result is forwarded for shipment.
On the other hand, a device which obtains a Fail result in the Verify process 53 is subjected to the Store process 52 again, so as to repeat the series of the relevant processes until it obtains a Pass result in the Verify process 53.
The most serious problem with respect to the above-described AF replacement is that the decreased potential of the node X0 reaches almost the same level of VREF0 (1.1V) due to insufficiently-decreased resistance of the AF element. In this case, every time the AF replacement determination is performed, a different result may be obtained. For example, if a device obtains a Pass result (in the Verify process 53) due to “the level at X0<VREF0” (which is narrowly satisfied) by which it is determined that the AF element has been destroyed, then it may be determined that the AF element has not been destroyed (in the Load operation of the re-screening process 54) due to “the level at X0>VREF0”. In this case, this device is determined to be a substandard product in the relevant re-screening process, and cannot contribute to an increase in the yield. Additionally, if such a device accidentally obtains a Pass result in the re-screening process 54 due to a determination that the AF element has been destroyed, and it is determined in the Load process during actual use (after the shipment) that the AF element has not been destroyed, then it causes a worse result such as the occurrence of a substandard market product.
In a conventional semiconductor integrated circuit device disclosed in Patent Document 1 (Japanese Unexamined Patent Application, First Publication No. 2002-074980), a specific node (e.g., “FUADD” in FIG. 1) is monitored so as to determine whether or not the relevant fuse should be subjected to a programmed operation.
As described later, the present invention provides a voltage comparison circuit for comparing the voltage at a node of the AF element with a plurality of reference voltages so as to more reliably determine the destruction or non-destruction of the AF element. Therefore, the method and structure for the determination are different between Patent Document 1 and the present invention.
As described above, in the conventional technique, a device having an unstable result of the AF replacement is obtained due to an insufficiently decreased resistance of the destroyed AF element, and such a device does not contribute to an increase in the relevant yield, or produces a substandard market product as a worse result.
USPTO Backgrounds
USPTO Backgrounds