1. Field of the Invention
The present invention relates to a semiconductor device, an adjustment method thereof and a data processing system including the semiconductor device. More particularly, the present invention relates to a semiconductor device that includes plural core chips and an interface chip to control the cores, an adjustment method thereof and a data processing system including the semiconductor device.
2. Description of the Related Art
A memory capacity that is required in a semiconductor device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor device, is suggested (for example, Japanese Patent Application Laid-Open No. 2004-327474). According to this method, with respect to plural core chips each of which is integrated with the back end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor device that has a large memory capacity and a high operation speed as a whole.
However, since there occurs a deviation in operation speed among the core chips due to the manufacturing process conditions, the period of time from the receipt of a read command to the outputting of read data also varies among the core chips. As a result, the latch margin of the read data for the interface chip becomes smaller, and in some cases, read data cannot be accurately latched.
As a method for solving the above problem, in Japanese Patent Application Laid-Open No. 2004-185608, although a semiconductor device that has a front-end unit and a back-end unit separated from each other is not disclosed, it is disclosed that a method of adjusting a latch timing of data output from a memory in a device which has the memory and an LSI connected thereto.
In a semiconductor device that has a front-end unit and a back-end unit separated from each other, however, a plurality of the core chips constituting the back-end unit are allotted to the single interface chip forming the front-end unit. Therefore, if the technique disclosed in Japanese Patent Application Laid-Open No. 2004-185608 is applied to this type of semiconductor device, the same number of latch timing control circuits as the number of core chips are required in the interface chip. In other words, latch timing control circuits corresponding to the respective core chips are required in the interface chip. This is because the core chips are independent of one another, and variations due to the manufacturing process conditions exist among the core chips. Even if the respective core chips have the same functions and are manufactured with the use of the same manufacturing mask, the core chips have different properties from one another due to the respective specific manufacturing process conditions (for example, the delay speed per unit circuit). As a result, the core chips operate at different speeds from one another. Furthermore, the number of core chips to be allotted to an interface chip is not necessarily determined during the manufacture of the interface chip. Therefore, according to the technique disclosed in Japanese Patent Application Laid-Open No. 2004-185608, it is necessary to prepare the same number of latch timing control circuits as the maximum number of core chips that can be allotted to an interface chip, resulting in a large amount of wastes in some chip structure.
USPTO Backgrounds
USPTO Backgrounds