Optical encoders are typically employed as motion detectors in applications such as closed-loop feedback control in motor control systems. By way of example, many optical encoders are configured to translate rotary motion or linear motion into a two-channel digital output for position encoding.
Many optical encoders employ an LED as a light source. In transmissive encoders, the light is collimated into a parallel beam by means of a lens located over the LED. Opposite the emitter is a light detector that typically consists of photo-diode arrays and a signal processor. When a code scale such as a code wheel or code strip moves between the light emitter and light detector, the light beam is interrupted by a pattern of bars and spaces disposed on the code scale. Similarly, in reflective or imaging encoders, the lens over an LED focuses light onto the code scale. Light is either reflected or not reflected back to the lens disposed over the photo-detector. As the code scale moves, an alternating pattern of light and dark patterns corresponding to the bars and spaces falls upon the photodiodes. The photodiodes detect these patterns and corresponding outputs are processed by the signal processor to produce digital waveforms. Such encoder outputs are used to provide information about position, velocity and acceleration of a motor, by way of example.
A typical reflective optical encoder comprises a light detector, a light emitter and a code wheel or code scale. The detector generates an output by processing photocurrents provided by photodiode arrays included in the light detector. In general, reflective optical encoders include four photodiode channels, namely A, A/, B and B/, which are arranged along a single track in a 2-channel optical encoder. The photodiodes are arranged so that gaps separating adjacent photodiodes are sufficiently large to prevent or inhibit crosstalk from being generated between such adjoining photodiodes. In the prior art, as the resolution of an optical encoder increased, the spacing between adjoining photodiodes decreased, which in turn led to increased crosstalk between channels.
Interpolation circuitry is commonly employed in incremental and absolute digital motion encoding systems, where the interpolation circuitry is configured to generate digital pulses having higher frequencies than base sinusoidal analog signals input to the circuitry. As the interpolation factor of the circuitry increases, the accuracy of the interpolation circuitry becomes ever more critical since the output provided by such circuitry ultimately determines the accuracy of the encoding system. Unfortunately, due to the architecture of most interpolation circuitry—which typically relies on a large number of comparators—the outputs provided by interpolation circuitry tend to be noisy and contain undesired noise spikes arising from excessive switching in the comparators. As a result, the comparators employed in interpolation circuitry for motion encoders are typically characterized by a significant amount of hysteresis, which can provide some immunity from noise spikes. The hysteresis itself can become a source of inaccuracy for the interpolation circuitry, however, especially at high interpolation factors.
Referring to FIG. 1, there is shown an optical encoder system 10 of the prior art comprising light emitter 20 (typically an LED), code wheel or code strip 30 having apertures 31a-31f disposed therein, and light detector 40 comprising photodiodes 41a (A) and 41b (A\). In optical encoder 10, collimated light beam 22 emitted by light emitter 20 projects light onto code wheel 30. Collimated light beam 22 is interrupted by masked or optically opaque sections disposed between apertures 31a-31f as code wheel or code strip 30 rotates in first direction 111 or in second direction 112. (Note that code wheel or code strip 30 rotates substantially in a plane defined approximately by collimated light beam 22 as it is projected from light emitter 20 towards light detector 40.) Portions 50a and 50b of collimated light beam 22 project through apertures 31c and 31d and sweep across light detector 40 and photodiodes 41b (A\) and 41a (A) as code wheel or code strip 30 rotates in direction 111 or 112 in the plane. As code wheel 30 moves in direction 111 or 112, the light patterns projected onto first vertical portion 70 of light detector 40 by beam portions 50a and 50b change, and the output signals provided by photodiodes 41a and 41b change correspondingly. These output signals are generally employed to generate a pair of quasi-triangular signals (as shown, for example, in FIG. 2), which are then used to determine any one or more of the position, speed and direction of code disk 30.
Referring now to FIG. 2, there are shown “triangular” signals A and A\, which are compared to one another and employed to generate pulse 109 using circuitry and methods well known to those skilled in the art of optical encoders. Typically, another set of photodetectors B and B\ is also provided, where photodetectors B and B\ are positioned 90 degrees out of phase with respect to photodetectors A and A\, and which are employed to generate another pulse (not shown in FIG. 2). Pulses for photodetectors A and A\, and B and B\, are generated which are 90 degrees out of phase with respect to one another. As shown in FIG. 2, pseudo-triangular signals A and A\, which for purposes of subsequent interpolation processing would optimally be linear or straight between maximum and minimum portions thereof, exhibit curved portions near the tops and bottoms thereof. These curved portions are due to undesirable capacitance effects, and complicate considerably any subsequent attempts at interpolation.
In an encoder of the type shown in FIG. 1, the spatial resolution of device 10 is generally determined and set according to the specific requirements of the end user. More particularly, the distances or spacing between adjoining photodetectors A and A\ (41a and 41b, respectively), are typically determined according to the particular requirements of a given customer or end user. Time and effort are required to implement such requirements, especially in respect of wafer fabrication when an unusual or new spatial resolution for device 10 is required.
One technique employed in the prior art to change or adjust the spatial resolution provided by device 10 is to employ one or more reticles disposed between light emitter 20 and light detector 40. FIG. 3 shows one such arrangement, where reticle strip 60 has reticles 61 and 62 disposed therein. Reticles 61 and 62 are configured to interfere with the light beams impinging thereon, and to modify them so that the pattern of light projected on light detectors 40 is changed. Reticles 61 and 62 are specifically configured to provide the degree, amount and type of spatial resolution desired of encoder 10.
FIG. 4 shows a conventional prior art single track optical encoder 10 with photodiode array 20 comprising detectors A, A\, B and B\ in a two-channel encoder with associated code strip 30. Signals generated by detectors A and A\ (channel A) and B and B\ (channel B) are also shown in FIG. 4, where the Channel B output signal lags the Channel A output signal by 90 degrees. (The relatively simple circuitry employed to generate output signals for channels A and B is not shown in FIG. 4, but is well known to those skilled in the art and therefore need not be discussed further herein.) The separation between adjoining photodiodes in array 20 and the width of each photodiode is selected according to the resolution that is required of the optical encoder. When the resolution of optical encoder 10 is increased, either the spacing w between adjoining photodiodes is reduced, or the width of each photodiode along common axis 15 is reduced, or both, resulting in photodiode spacing z being decreased, where z is the spacing between the leading or trailing edges of adjoining photodiodes.
Note that in optical encoder 10 illustrated in FIG. 4, the spacing z between the leading or trailing edges of adjoining photodiodes corresponds to one-quarter the combined width of a single pair of adjoining light and dark strips on code scale 30. As a result, two photodiodes are contained within a distance defining the length of each such strip along common axis 15. Note further that in optical encoder 10 illustrated in FIG. 4, all photodiodes disposed along single track or common axis 15 are arranged in the order or sequence A, B, A\, and B\.
Two issued patents which discuss interpolation circuits are U.S. Pat. No. 6,355,927 entitled “Interpolation Methods and Circuits for Increasing the Resolution of Optical Encoders” to Snyder and U.S. Pat. No. 6,816,091 entitled “Interpolator” to Chee, the respective entireties of which are hereby incorporated by reference herein.
A block diagram of a prior art interpolation circuit 120 is shown in FIG. 5. The A, A\, B and B\ ramp signals are input to a signal generating circuit 140. The signal generating circuit 140 provides A, A\, A\/3, B, B\, and B\/3 ramp signals to a comparator circuit 142. Comparator circuit 142 compares selected pairs of the A, A\, A\/3, B, B\, and B\/3 ramp signals and generates a set of eight intermediate signals on lines 144. The intermediate signals are supplied to a logic circuit 150, which combines the intermediate signals and generates channel A and channel B output signals as described below.
FIG. 6 shows a schematic block diagram of prior art signal generating, comparator and logic circuitry configured to receive input signals A, A\, B and B\ and to provide channel A and channel B outputs therefrom. Signal generating circuit 140 includes attenuating amplifiers 220 and 222, each having a gain of one third. Amplifier 220 generates the fractional A\/3 ramp signal, and amplifier 222 generates the fractional B\/3 ramp signal. The A, A\, B and B\ input ramp signals may be scaled if desired. The A\ and B\ ramp signals may be generated by inverting the A and B ramp signals if desired. However, the A, A\, B, B\, fractional A\/3 and fractional B\/3 ramp signals supplied to comparator circuit 142 have the amplitude and phase relationships shown in FIG. 7 and described below.
Comparator 142 includes comparators 240, 242, 244, 246, 248, 250, 252 and 254. Each of the comparators compares a selected pair of ramp signals and outputs an intermediate signal. In particular, comparator 240 compares the B and B\ ramp signals and generates a B-B\ intermediate signal. Similarly, comparator 242 outputs an A\-B\ intermediate signal; comparator 244 outputs an A\-A intermediate signal; comparator 246 outputs a B\-A intermediate signal; comparator 248 outputs an A\/3-B\ intermediate signal; comparator 250 outputs an A\-B\/3 intermediate signal; comparator 252 outputs a B\/3-A intermediate signal; and comparator 254 outputs an A\/3-B intermediate signals. As described below, the intermediate signals are uniformly distributed in phase for ideal input signals.
Logic circuit 150 includes exclusive OR gates 270, 272, 274 and 276, and OR gates 280 and 282. Exclusive OR gate 270 receives the B-B\ and A\-B\ intermediate signals and supplies an output to OR gate 280. Exclusive OR gate 272 receives the A\-A and the B\-A intermediate signals and provides an output to OR gate 280. The output of OR gate 280 is the channel B output signal. Exclusive OR gate 274 receives the A\/3-B\ and A\-B\/3 intermediate signals and provides an output to OR gate 282. Exclusive OR gate 276 receives the B\/3-A and A\/3-B intermediate signals and provides an output to OR gate 282. The output of OR gate 282 is the channel A output signal.
In the circuitry shown in FIG. 6, voltage amplifiers are employed to generate fractional signals. One of the disadvantages by using voltage amplifiers in signal generating circuit 140 is that the range of fractional signals generated is to the voltage output swings of the various voltage amplifiers that are employed. The output of each voltage amplifier is limited by its particular circuit topology and architecture, the process technology that has been employed, and the power supply that is provided thereto during operation. The greater the number of interpolation factors required for a given application, the greater the number of fractional signals that need to be generated using additional voltage amplifiers. When interpolation encoders are used in for high frequency applications, speed becomes a major concern for voltage amplifiers.
In addition, many motion control encoders feature designs that have reached their limits with respect to frequency, performance, and accuracy due to process and delay variations caused by the varying hystereses associated with different comparators. For higher-frequency interpolated outputs provided by an optical encoder, and without appropriate signal calibration, the performance of the encoder may depend heavily on the quality of the incoming signal, as well as on part-to-part variations between comparators in the interpolator block. Moreover, the hysteresis of the comparators may vary in accordance with changes in the frequency of the incoming signals, or because of process mismatches. Without expensive signal conditioning circuitry, distorted incoming signals can cause errors, inaccuracies and distortions in the output signals provided by the comparators.
What is needed is an interpolation encoder that can overcome at least some of the foregoing problems.
USPTO Backgrounds
USPTO Backgrounds