Typically, known data processors comprise a microsequencer and an execution unit. The execution unit is where data operations are performed and typically comprises an arithmetic unit, registers, buses, and a data shifter. The microsequencer is usually either `hardwired`, i.e. designed using combinatorial logic gates, or `microcoded`, i.e. designed using a programmable memory. Microcode design has the advantage that the microsequencer architecture is more simple and straight-forward, and the microsequences can be easily modified by reprogramming the memory. The memory which stores the microcode is referred to as the microstore, and is often implemented as read-only-memory (ROM), or as read/write, random access memory (RAM). In a microcoded design, the user visible `macroinstruction` of the data processor is executed by one or several microinstructions. These microinstructions control the execution unit so as to perform the function of the macroinstruction. A sequence of microinstructions, referred to as a microroutine or a microprogram, may be necessary in order to execute a complex macroinstruction.
There are two known primary approaches to sequencing a microprogram. The first approach utilizes an incrementor, or microprogram counter (.mu.PC), to address sequential microinstructions in the microstore. Microcode branching is handled by loading a new value, specified by the microinstruction, into the .mu.PC. A second approach to sequencing the microprogram requires that each microinstruction explicitly specify the address of the next microinstruction to be used, such that branching is inherent in each microinstruction. With this approach, conditional branching requires that an additional next microinstruction address (NMA) be specified for the second branch case. In this second approach, there is often a holding register, also referred to as a .mu.PC, which temporarily holds the NMA during microstore accesses.
In a typical pipelined dataprocessor, macroinstructions are "fetched" from a main memory and stored in an instruction pipeline (pipe) made up of "instruction registers" (IRs). The pipe is structured such that instructions enter at one end, and the values are shifted toward the other end where they are used and then discarded. Instruction decode logic (often a programmable logic array (PLA)) accesses the instructions in the pipe and "decodes" the macroinstruction. This "decode" provides the initial microstore address of the microroutine that is to be used to perform the particular macroinstruction. At the conclusion of a microroutine, the microinstruction will request another instruction decode to determine which microroutine to execute next. This instruction decode may be a further decode of the same macroinstruction word, a decode of additional words of a multiword macroinstruction, or a decode of a new macroinstruction.
Macroinstructions are often performed by using several general purpose microroutines in succession. Allowing macroinstructions to share common microroutines reduces the amount of memory required in the microstore. Linking between microroutines is accomplished by microcode branching or by instruction decode requests.
USPTO Backgrounds
USPTO Backgrounds