1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit using a double-triggered silicon controlling rectifier (DT_SCR), and more particularly to an electrostatic discharge circuit using a double-triggered silicon controlling rectifier with low-switching voltage and high-trigger speed.
2. Description of the Related Art
During the development of the semiconductor technology, electrostatic discharge (ESD) protection circuit is an essential component for integrated circuits. Especially for deep sub-micron semiconductor technology, the gate thickness and the chip size are shrunk making device easily vulnerable to ESD damage. Therefore, ESD protection circuits are usually applied to input/output (I/O) pads for preventing internal circuits from ESD damage.
FIG. 1A is a configuration showing a conventional silicon controlling rectifier. The conventional silicon controlling rectifier shown in FIG. 1A is widely used in ESD circuits because of its excellent performance. The conventional silicon controlling rectifier comprises: a N-well region 103, a N+ diffusion area 109 and a P+ diffusion area 111 in a P-type substrate 101. The N+ diffusion area 109 of the silicon controlling rectifier serves as a cathode 117, and the P+ diffusion area 111 is grounded. A N+ diffusion area 107 and a P+ diffusion area 108 are formed within the N-well region 103. The P+ diffusion area 108 serves as an anode 115 of the silicon controlling rectifier, and the N+ diffusion area 107 is coupled to the external power terminal VDD. The diffusion areas are isolated by shallow trench isolation (STI). In detail, the N+ diffusion area 107 and the P+ diffusion area 108 are isolated by STIs 119, 121 and 123. The N+ diffusion area 109 and the P+ diffusion area 111 are isolated by STIs 123, 125 and 127.
FIG. 1B is an equivalent circuit of the conventional silicon controlling rectifier shown in FIG. 1A. Referring to FIG. 1B, the transistor Q1 is a PNP bipolar transistor formed from the N+ diffusion areas 107 and 108 and the P+ diffusion area 111, and R1 is the equivalent resistor between the N+ diffusion area 107 and the N-well region 103. The transistor Q2 is a NPN bipolar transistor formed from the N+ diffusion areas 107 and 109 and the P+ diffusion area 111, and R2 is the equivalent resistor between the P+ diffusion area 111 and the P-type substrate 101. When a positive ESD voltage is coupled to the circuit, avalanche breakdown occurs at the interface between the collector/base of the transistor Q1. The transistor Q2 turns on and regenerative conduction action arises so that the ESD charges are introduced to the ground terminal. When a negative ESD voltage is coupled to the circuit, forward-bias occurs at the interface between the collector/base of the transistor Q1, and the ESD charges are introduced to the ground terminal.
Although the silicon controlling rectifier has excellent performance for preventing damage due to ESD pulses, the switch voltage of the device is larger than the breakdown voltage of the gate oxide layer. Accordingly, the conventional silicon controlling rectifier cannot effectively protect the internal circuit from the ESD damage.
USPTO Backgrounds
USPTO Backgrounds