Multilevel metal interconnect structures are routinely employed to provide electrical wiring for a high density circuitry, such as semiconductor devices on a substrate. Continuous scaling of semiconductor devices leads to a higher wiring density as well as an increase in the number of wiring levels. Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure sometimes referred to as a Bit Cost Scalable (BiCS) architecture. Such ultra high density storage devices include a large number of interconnect wiring levels. For example, a 3D NAND stacked memory device may include at least as many number of wiring levels as the total number of control gate electrodes employed for the 3D NAND stacked memory device.
Various schemes for constructing electrically conductive via contacts extending to different electrically conductive electrodes located at different wiring levels of memory devices have been proposed in the art. For example, U.S. Pat. No. 8,394,716 to Hwang et al. and U.S. Patent Application Publication No. 2009/0230449 to Sakaguchi et al. teach formation of conductive via structures extending from a same top surface to top surfaces of electrically conductive electrodes located at different levels by staggering end portions of the electrically conductive electrodes. Specifically, end portions of electrically conductive electrodes are staggered such that an edge of each overlying electrically conductive electrode is laterally offset inward from an edge of any underlying electrically conductive electrodes throughout the entirety of a stack of the electrically conductive electrodes.
USPTO Backgrounds
USPTO Backgrounds