1. Field of the Invention.
The present invention relates to clock systems used in digital computers. In particular, the present invention is an electronic clock tuning system for tuning the delay of clock pulses distributed throughout the computer.
2. Description of the Prior Art.
Modern digital computers are formed by hundreds of thousands and even millions of logic elements. In computer architectures which are highly integrated, these logic elements are fabricated on very large-scale integrated (VLSI) circuit chips known as gate arrays. The gate arrays themselves are organized onto a plurality of major function circuit boards which are dedicated to the performance of specific tasks. A supercomputer, for example, can include a central processing unit (CPU), memory interface, and input/output (I/O) major function circuit boards. Each of these circuit boards will typically be formed by hundreds of gate arrays.
In order to achieve a high data throughput, operations are distributed throughout the computer, and performed in "parallel." Processed data and microinstructions are communicated between individual gate arrays, and between major function circuit boards. It is extremely important, therefore, that all microinstructions and data transfers executed by the gate arrays be synchronized with those of other gate arrays. To this end, the computer includes a central clock system for dividing and or "clocking" operations performed by all gate arrays.
The clock system will include a master oscillator which is the source of clock signals for all gate arrays. A clock pulse train produced by the master oscillator is divided, and replicas thereof distributed to each major function circuit board by a master fanout circuit. On each major function circuit board the clock pulse train is further divided, and distributed to each gate array through a local fanout circuit. Each gate array is, therefore, clocked by a replica of the pulse train produced by the master oscillator. While this technique helps maintain synchronization between gate arrays, it is inadequate for the high degree of performance demanded of modern supercomputers.
Even minute discrepancies between the phases of the clock pulse trains arriving at different gate arrays can have disastrous consequences on computer operation. These discrepancies, or skews, are the product of numerous factors. Variables such as operating temperature, supply voltage, component tolerance variables due to manufacturing processes, and differing path lengths between master oscillator and gate arrays, all contribute to skew between the clock pulse trains. Adding to the problem is the fact that many of these factors cannot be accurately controlled.
Obviously, the higher the frequency of the clock pulse train, the faster the computer can process data. Frequency of the clock pulse train, however, is limited by the uncertainty, or maximum skew, introduced between clock pulse trains supplied to various gate arrays. Simply put, computer performance can be greatly increased by reducing skews introduced by the clock system.
Currently used techniques for tuning computer clock systems are primarily manual. A technician will measure the time delay in the distribution path between the master oscillator and each and every gate array. A length of coaxial cable in each path is then removed, trimmed, and reinserted. This procedure is repeated until the delay in the clock pulse train at each gate array is within predetermined tolerances. This procedure is obviously very labor intensive. It must be performed for each and every one of the hundreds of gate arrays on the computer. On a supercomputer, this procedure can take several weeks.
There is clearly a continuing need for improved apparatus for tuning clock systems in digital computers. An electronic clock tuning system would be especially desirable. Electronic test equipment could then be used to tune the clock pulse train supplied to each gate array. Computer "setup" time could be greatly reduced by the elimination of tedious and labor intensive tasks. An electronic clock tuning system of this type could also be extremely accurate, and significantly increase computer performance by permitting gate arrays to be clocked at frequencies approaching their specified maximums. The system should, of course, also be relatively simple and inexpensive.
USPTO Backgrounds
USPTO Backgrounds