The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for automatically generating a list of wire tags for chip design optimization and routing for a given technology metal stack.
Modern day electronics include components that use integrated circuits. Integrated circuits are electronic circuits formed using silicon as a substrate with added impurities to form solid-state electronic devices, such as transistors, diodes, and resistors. Commonly known as a “chip”, an integrated circuit is generally encased in hard plastic. The components in modern day electronics generally appear to be rectangular black plastic pellets with connector pins protruding from the plastic encasement.
Circuit designers use a variety of software tools to design electronic circuits that accomplish an intended task. For example, a digital circuit may be designed to accept digital inputs, perform some computation, and produce a digital output. An analog circuit may be designed to accept analog signals, manipulate the analog signals, such as my amplifying, filtering, or mixing the signals, and produce an analog or digital output. Generally, any type of circuit can be designed as an integrated circuit (IC).
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout at very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in silicon. The designs produced and manipulated using these software tools are complex, often including millions of such components interconnected to form an intended electronic circuit. Such an interconnected group of components is called a net.
The software tools manipulate these components at the components level, or at the level of blocks of components, i.e. block level. A block of components is also known as a cell. One way of identifying cells in an IC design is to overlay a grid of imaginary vertical and horizontal lines on the design, and deeming each portion of the IC design bound by horizontal and vertical lines as a cell. The horizontal or vertical lines bounding a cell are called cut-lines. Cells formed in this manner are commonly known as global routing cells, or g-cells. Imposing such a grid on an IC design abstracts the global routing problem away from the actual wire implementation and gives a more mathematical representation of the task. A net may span one or more cells and may cross several cut lines.
An IC design software tool can, among other functions, manipulate cells, or interconnect components of one cell with components of other cells, so as to form nets. The interconnects between components are called wires. A wire is a connection between parts of electronic components, and is formed using a metallic material that conducts electricity.
One aspect of IC design is referred to as the placement problem, i.e. the problem of placing the cells of a chip such that the design meets all the design parameters of the chip. Routing is the process of connecting the pins after placement. In other words, placement results in a rendering of the components of various cells as being located in certain positions in the design, whereas routing results in a rendering of how the metal layers would be populated with that placement. A wire can be designed to take any one of the several available paths in a design. Placement of a wire on a certain path, or track, is a part of routing.
A layer is typically designated to accommodate wires of a certain width, (wirecode). Generally, the wider the wire width of a layer, and the thicker the wire height of a layer, the faster the signal propagation speed for the net routed on that layer. Faster layers, to wit, layers with larger wire widths or higher wire height, can accommodate fewer components or nets as compared to slower layers with narrower wire widths.
A router is a component of an IC design tool that performs the routing function. Once the placement component, known as a “placer,” has performed the placement function, the router attempts to connect the wires without causing congestion. For example, if a design parameter calls for no more than five wires in a given area, the router attempts to honor that restriction in configuring the wiring. Such limitations on the wiring are a type of design constraints and are called congestion constraints. Other types of design constraints may include, for example, blocked areas—cell areas where wires may not be routed.
A global router divides the routing region into small tiles and attempts to route nets through the tiles such that no tile overflows its capacity. After global routing, wires must be assigned to actual tracks within each tile, followed by detail routing which must connect each global route to the actual pin shape on the cell. Another type of router, known as the “detailed router,” performs the detailed routing. The global and detailed routing produced during the design process is collectively referred to as “routing” and is usually further modified during optimization of the design.
USPTO Backgrounds
USPTO Backgrounds