Typically, a memory unit stores information in an array of memory cells. Modern day electronic memory includes millions of memory cells, each respectively configured to store one or more bits of data (e.g., as an amount of electric charge). Retrieval of data from a memory cell can be accomplished by a read operation, wherein electric charge stored in a memory cell is provided directly to a bitline or sensed indirectly via the current of a transistor controlled by the charge. To conserve power, in one implementation, the electric charge generates a small voltage on the bitline, which is subsequently amplified by a sense amplifier into a voltage level representing a logic “1” or a “0” state by amplifying the small change in the bitline voltage into a full logic voltage swing (e.g., 2.5V for DRAM applications). In other solutions, a readout of the memory cell generates a higher or a lower read current compared to a reference current at a given readout voltage. In these solutions, the readout current compared to the reference current represents a logic “1” or a “0” state.
For example, in flash memory, the cells are made from floating-gate transistors. In single-level cells, each cell stores one bit of information. In multi-level cells, one cell can store more than one bit by choosing between multiple levels of electrical charge to apply to the transistor's floating gate. A typical memory cell resembles a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The MOSFET includes a control gate configured to control current in a channel, herein also referred to as the MOSFET channel, between a source and a drain. Depending on the type of charge responsible for the conductivity of the field-induced inversion channel, MOSFETS are nMOSFETs or pMOSFETS. In nMOSFETs, the channel below the control gate is positively doped and the active areas source and drain are negatively doped. In pMOSFETs, the doping is inverted. Due to a higher mobility of electrons compared to holes, nMOSFET devices are preferred in terms of speed. nMOSFETs are self-closing, i.e., if no voltage is applied to the gate, or the gate voltage is not exceeding a minimum threshold level, the flow of current between the drain and the source is inhibited, and, thus, the transistor is closed. By applying a positive voltage, the MOSFET turns into a conductive state. It is clear that principles of operation of a pMOSFET can be applied as well, however resulting in complementary switching behavior. In a MOSFET-based memory cell, in addition to the control gate as in other MOSFETs, there is a floating gate between the control gate and the MOSFET channel. The floating gate is insulated from the control gate. Charging the floating gate with electrons sets the transistor to a physical state where the MOSFET channel does not conduct. By definition, the memory cell is thus programmed into a logic state representing a “1”. The electrons screen the electric field from the control gate, whereby a threshold voltage of the cell is increased and a higher voltage must be applied to the control gate in order to make the MOSFET channel conductive.
Removing the electrons from the floating gate or even charging the floating gate positively sets the transistor to a physical state where the MOSFET channel conducts. The memory cell is thereby erased and brought into a logic state representing a “0”. The positively charged floating gate supports the build-up of the inversion channel and reduces the threshold voltage when the transistor turns on. There are many variations of flash memory cell construction and different approaches in how to inject charge onto the floating gate, such as hot electron injection or electron tunneling. There are also many variations of the flash cell construction, for example, such as providing an additional gate to separate the selection and the charge control of the floating gate.
In order to read a value from the transistor, an intermediate voltage, i.e., a voltage at a level between the threshold voltage level in a state where the floating gate is not charged and the threshold voltage level in a state where the floating gate is charged, is applied to the control gate. This voltage is called a read voltage (Vread), and is also referred to as an activation voltage, and is adjusted to a point of operation of the flash memory cell array. If the nMOSFET channel conducts at this intermediate voltage, then the floating gate is not charged with electrons. This means that at an earlier time, for example by performing an erase operation, a logic value “0” was stored in the memory cell. If the channel does not conduct at the intermediate voltage level, then the floating gate is charged with electrons. This means that at an earlier time, for example by performing a programming operation, a logic value “1” was stored in the cell. It should be understood that the representation of a logic “1” or “0” state depends on the logic circuitry used to sense the current and represent the sense level.
In a multi-level cell device, a level of charge on the floating gate represents one of multiple bits that can be stored in the cell. Accordingly, instead of merely sensing a non-zero current, an amount of current flow in the MOSFET channel is sensed in order to determine the level of charge stored on the floating gate.
Memory cells are typically organized in sectors. A sector comprises one or more wordlines configured to activate memory cells that are connected to the wordline, i.e., to set the control gate of the memory cells to an activation voltage level on the wordline. A sector comprises one or more bitlines configured to sense current flowing through memory cells connected to the bitline when activated.
Wordlines and bitlines can be subject to malfunction. For example, a resistance of a wordline can increase whereby a voltage drop across the wordline may be greater than was designed for in order for the memory sector to function properly.
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