Conventional electronic memories may be implemented by arrays of discrete memory cells. Many types of memory cells and many systems for writing a value to and reading a value from a memory cell currently exist.
FIG. 1 shows a cross-sectional view of floating-body dynamic random access memory (FBDRAM) memory cell 1. Cell 1 comprises a single transistor and is known as a gain cell because a value may be stored within and read from the transistor. The transistor is fabricated upon oxide 2 in a silicon-on-insulator (SOI) arrangement. The transistor includes n-type source region 3, p-type body region 4 and n-type drain region 5. Oxide 6 is disposed over gate region 4 and conductive element 7 overlays oxide 6.
A value is stored and read by manipulating charge carriers within body region 4. To improve charge retention, body region 4 may be isolated from adjacent memory cells by oxide 6, by the pn junctions between itself, source region 3 and drain region 5, and by shallow trench isolation in front of and behind the plane of FIG. 1. SOI process technology may, however, be undesirable in some instances.
USPTO Backgrounds
USPTO Backgrounds