Phase-locked loops (PLLs) have been applied to many applications ranging from generating clock signals in microprocessors to synthesizing frequencies. In general, a PLL may include an oscillator that generates an output signal with a frequency that is locked onto a frequency of a reference signal. To lock the frequency of the output signal with the frequency of the input signal, a PLL may include a phase detector (PD) configured to compare the phase of the reference signal to the phase of an output signal generated by the oscillator, and to generate a PD output that is proportional to the phase difference between the phase of the input signal and the phase of the output signal.
Through the feedback of the output signal to the PD, the PLL drives the frequency of the output signal to the frequency of the input signal and matches the phase of the output signal with the phase of the input signal. The PLL may also assist in correcting any phase misalignment resulting from internal or external noise sources.
PLLs may be digital or analog. Both digital PLLs and analog PLLs have strengths. For example, an output of a digital PLL may be locked quicker to a frequency than an output of an analog PLL, while an analog PLL may have lower power consumption than a digital PLL.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.
USPTO Backgrounds
USPTO Backgrounds