The silicon (Si) integrated circuit (IC) has dominated electronics and has helped it grow to become one of the world's largest and most critical industries over the past thirty-five years. However, because of a combination of physical and economic reasons, the miniaturization that has accompanied the growth of Si ICs is reaching its limit. The present scale of devices is on the order of tenths of micrometers. New solutions are being proposed to take electronics to ever smaller levels; such current solutions are directed to constructing nanometer scale devices.
Prior proposed solutions to the problem of constructing nanometer scale devices have involved (1) the utilization of extremely fine scale lithography using X-rays, electron, ions, scanning probes, or stamping to define the device components; (2) direct writing of the device components by electrons, ions, or scanning probes; or (3) the direct chemical synthesis and linking of components with covalent bonds. The major problem with (1) is that the wafer on which the devices are built must be aligned to within a fraction of a nanometer in at least two dimensions for several successive stages of lithography, followed by etching or deposition to build the devices. This level of control will be extremely expensive to implement. The major problem with (2) is that it is a serial process, and direct writing a wafer full of complex devices, each containing trillions of components, could well require many years. Finally, the problem with (3) is that the only known chemical analogues of high information content circuits are proteins and DNA, which both have extremely complex and, to date, unpredictable secondary and tertiary structures that causes them to twist into helices, fold into sheets, and form other complex 3D structures that will have a significant and usually deleterious effect on their desired electrical properties as well as make interfacing them to the outside world impossible.
The present inventors have developed new approaches to nanometer-scale devices, comprising crossed nano-scale wires that are joined at their intersecting junctions with bi-stable molecules, as disclosed and in application Ser. No. 09/282,048, filed on even date herewith [PD-10981971-1]. Wires, such as silicon, carbon and/or metal, are formed in two dimensional arrays. A bi-stable molecule, such as rotaxane, pseudo-rotaxane, or catenane, is formed at each intersection of a pair of wires. The bi-stable molecule is switchable between two states upon application of a voltage along a selected pair of wires.
The present inventors have also developed new approaches to nanometer-scale interconnect arrays as disclosed and in application Ser. No. 09/280,225, filed on even date herewith [PD-10981966-1]. A molecular-wire crossbar interconnect for signal routing and communications between a first level and a second level in a molecular-wire crossbar is provided. The molecular wire crossbar comprises a two-dimensional array of a plurality of nanometer-scale switches. Each switch is reconfigurable and self-assembling and comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. Each level comprises at least one group of switches and each group of switches comprises at least one switch, with each group in the first level connected to all other groups in the second level in an all-to-all configuration to provide a scalable, defect-tolerant, fat-tree networking scheme. The primary advantage is ease of fabrication, because an active switch is formed any time two wires cross. This saves tremendously on circuit area (a factor of a few times ten), since no other wires or ancillary devices are needed to operate the switch or store the required configuration. This reduction of the area of a configuration bit and its switch to just the area of two crossing wires is a major advantage in constructing a defect-tolerant interconnect network.
Having developed a nanometer-scale crossbar innterconnect, effective utilization requires development of memories in order to construct a computer.
Magnetic random access memory (MRAM) is one route currently being explored for high density active memory applications, i.e., as a replacement for dynamic RAM (DRAM). The primary disadvantages of MRAM are that the spin-tunneling switch that is used to store individual bits at present only has about a 30% difference in resistance between the ON and OFF state, which means that memories must either be small or relatively slow to be read reliably. Such memories also would be damaged either by strong magnetic fields or by high temperatures, either of which can erase the memory. Finally, relatively large currents are required to set the sense of a bit, and this leads to problems with designing the electrical circuitry that accompanies the MRAM and also with the power consumption of the device.
There were also significant early attempts to build cross-point memories using ferroelectrics, but these were unsuccessful. The history of ferroelectric-based memories, especially the FeRAM, is described, for example, by R. E. Jones, Jr. et al, "Ferroelectric non-volatile memories for low-voltage, low-power applications", Thin Solid Films, Vol. 270, pp. 584-588 (Dec. 1, 1995).
The primary problem with ferroelectric cross-point memories has been crosstalk between memory elements--a phenomenon referred to as the `half-select disturb-pulse`. Briefly, addressing a cell by splitting the write voltage between bit and word lines had the side effect that adjacent cells could be set as well. This occurred because of the fundamental properties of ferroelectrics, which do not have a sharp switching threshold voltage (they switch when a coercive field is exceeded, and there are many issues that vary the voltage required to achieve that field). Also, the switching depends upon the time over which a field is held, and thus there is a finite probability that a ferroelectric will switch if even a field below the coercive field is held on long enough. These problems have been addressed recently by using a pass-gate architecture in which each ferroelectric capacitor is controlled by its own field effect transistor (FET) (the 1T-1C configuration). Thus, the bit densities of these ferroelectric memories (FeRAM) will most likely never exceed the density of the FETs in the generation of CMOS (complementary metal-oxide semiconductor) used to build them. Another annoying issue with FeRAM is that reading a cell will necessarily destroy a bit if it is set "ON", and thus reading actually requires a read-rewrite cycle, which adds to the complexity, temporal overhead, and power consumption of the devices.
Thus, a need remains for high density memory, employing nanometer-scale architecture.
USPTO Backgrounds
USPTO Backgrounds