Integrated circuit design and fabrication is a vastly complex effort and involves designers managing interaction between numerous steps in a manufacturing process. To effectively handle the steps in the design process, designers must understand the limitations of the manufacturing process. Shapes must be designed which can be fabricated in a manner that allows for the implementation of desired electronic circuit function at the resulting end of fabrication. Frequently, millions and even hundreds of millions of transistors can exist on a single semiconductor chip. Each transistor is composed of shapes for diffusion, polysilicon, contacts, and metallization, along with other structures. The ability to design chips with such large numbers of essential transistors can be quite challenging, and circuit optimization can prove a daunting task, even with the help of electronic design automation (EDA) software tools.
Numerous metal lines of miniscule dimension lie in close proximity to one another on each semiconductor chip. Further, diffusions, polysilicon shapes, and insulator layers share space on the chip, and must be fabricated to exacting tolerances. As technologies have advanced, the lithographic process used to fabricate these structures uses smaller and smaller dimensions. These smaller dimensions allow for more structures on a chip, but also allow even small defects to have a greater impact. A defect can impact a circuit in many ways. For example, a defect may bridge between two structures, thereby causing a short or resistive short. In some cases, a defect may even increase capacitance between adjacent structures. Defects can enter a semiconductor chip at each step in the fabrication process. No amount of effort will ever completely eliminate defects from the manufacturing process. Further, failures on semiconductor chips may be the result of random defects or systematic defects on the chips.
Failure analysis (FA) of an integrated circuit (IC) may involve preparing samples by cutting though silicon at a precise location and depth, and then examining each sample using optical microscopy, scanning electron microscopy (SEM), transmission electron microscopy (TEM), or some other inspection method. Before the integrated circuit under evaluation is cut, it may be valuable to examine the surface of the integrated circuit to help determine the place to cut, and/or to look for visible defects on the surface. Using layout-driven navigation software it is possible to drive a machine to locate an area of interest of the integrated circuit and examine the surface of the integrated circuit, but, short of cutting into the integrated circuit, the structure and materials beneath the area are often unknown to failure analysis engineers. Because of the difficulty of determining what is below a specific area on the surface of the integrated circuit, identifying areas of interest using surface examination is an error prone venture, which may result in mistakes in identifying the actual area of interest and delays in the failure analysis process. Actually cutting the integrated circuit is a destructive process; thus, cutting into the integrated circuit in the wrong location may destroy the area with the defect, rendering any attempt to diagnose the defect in the particular integrated circuit impossible.
USPTO Backgrounds
USPTO Backgrounds