In many systems, there is often a time invariant frequency and phase difference between the received signals and the output signals as well as a time variant phase difference between the signals. The time invariant frequency and phase differences are commonly attributed to the differences between the transmitter and receiver such as the fixed frequency delta. Time variant phase differences are rapid, short term random fluctuations in the phase of the waveform such as phase noise. One manner in which phase noise may be added to the received signals is through a mixing operation in the tuner.
For coherent reception, synchronization of both the phase and frequency of the received and output signals is used. Typically, the synchronization is performed on an analog form of these signals. FIG. 1 illustrates an embodiment of a conventional prior art analog Phase Locked Loop (PLL) used to synchronize the received RF signals with a local replica. The PLL 100 includes phase detector 105, loop filter 110, and voltage controlled oscillator 115.
The phase detector 105 is a device that produces an error signal. The error signal is a time varying signal that measures the phase difference between the phases of the received RF signals and the local replica. The loop filter 110 governs the response of PLL 100 to the time variations in the error signal. A well designed loop filter tracks the changes in the received signals phase but is not overly responsive to receiver noise. Voltage controlled oscillator 115 receives control signals from loop filter 110 and generates a carrier replica based upon the control signals. The voltage controlled oscillator 115 is an oscillator that provides an output frequency that is a linear function of an input voltage over a specific range of input and output.
Analog to Digital Converters (ADCs) have greatly improved since ADCs were first introduced. Current ADCs can sample signals at multiple GHz speeds and dissipate less power than traditional RF mixer based tuners. As such, ADC based RF tuners, such as the ADC-based tuner shown in FIG. 2, have been developed. The ADC-based tuner 200 shown in FIG. 2 includes a Low Noise Amplifier (LNA) 205, a high-speed ADC 210, channelizer 215, and a high-speed PLL 220. The LNA 205 amplifies received RF signals for analog to digital conversion. The high-speed ADC 210 receives the amplified signals from the LNA 205 and converts the amplified RF signals from analog signals to digital signals. The high-speed ADC 210 is clocked by the high speed PLL 220. The channelizer 215 receives the digital signals from the high-speed ADC 210 and performs mixing and filtering operations in the digital domain to output in-phase (I) signals and a quadrature (Q) signals from the tuner 200. Similar to a traditional RF mixer, phase noise is introduced into the signals by the ADC-based tuner 200.
To synchronize the received signals with the local signals a digital PLL may be added to an ADC-based tuner. An embodiment of a prior art digital PLL is shown in FIG. 3. The illustrated digital PLL 300 includes an ADC 305, a digital mixer 310, a Phase Error Detector (PED) 315, a loop filter 320, a phase accumulator 335, and a Direct Digital Frequency Synthesizer (DDFS) 340. The ADC 300 converts the received analog RF signals into digital signals. The digital mixer 310 performs phase adjustment on the distorted digital signals received from the ADC 300. The PED 315 calculates the phase difference between the incoming signals and the output digital signals output from the digital mixer 310. The phase difference calculated by the PED 315 is then filtered by the loop filter 320 to generate a current intermediate phase adjustment signal. The intermediate phase adjustment signal represents the phase change between the current signal and a previous signal. The phase accumulator 335 then adds a previous intermediate phase adjustment signal to the current intermediate phase adjustment signal to provide the phase adjustment signal which a signal that indicates the phase change needed in the output signals to synchronize the output signal. The DDFS 340 receives the phase adjustment signal and generates a phase adjustment estimation used by mixer 310 to perform the phase adjustment of the output digital signals. However, the phase noise from the PLL of an ADC-based tuner amplitude and phase modulates the received signals in the digital domain instead of phase modulating the signals as happens in the analog domain. A digital PLL 300 can only correct for the phase modulation, not amplitude modulation. The un-tracked amplitude modulation can cause significant performance degradation for a receiver.
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