1. Field of the Invention
The present invention relates to a system and method for providing a software trap and patch function, and more specifically, a software trap and patch function to low power and space constrained applications.
2. Related Art
The microprocessor is an integral part of many modern consumer electronic devices. The microprocessor, in combination with one or more software programs, provides many of the features and functions of the consumer electronic device. Such software programs are typically stored on the microprocessor device or as a standalone device in read only memory (xe2x80x9cROMxe2x80x9d) and installed during the manufacturing process.
Programs that are stored in ROM cannot generally be altered. Thus, a problem occurs when it is discovered that a bug or program error exists within the pre-programmed code stored in the ROM of fabricated devices. It is prohibitively expensive to scrap devices whenever a programming error is discovered, and it would unduly delay the shipment of the product if it were necessary to ship devices fabricated with the correct ROM code.
Several solutions to this problem have been proposed. According to one such approach, detailed in U.S. Pat. Nos. 5,799,144 and 5,701,506, the microprocessor is configured with a writeable memory, such as a random access memory (xe2x80x9cRAMxe2x80x9d) or a similar storage device, and a new section of code, referred to herein as the xe2x80x9cpatchxe2x80x9d code, in which the programming error has been corrected, is downloaded into the writeable memory. Circuitry is provided to detect an access to the error-containing code, and responsive thereto, signal a trap condition. Responsive to the trap condition, additional circuitry imposes on the data bus a JUMP instruction, with the operand thereof being the start address of the patch code. Upon execution by the microprocessor of this JUMP instruction, program control is passed to the patch code, which is then executed in lieu of the error-containing code.
The problem with this approach is that, because of the complexity and size of the circuitry required to perform the trap and patch function, it is not particularly well-suited for low power, cost conscious and space constrained applications, such as wireless or cordless handsets. For example, in U.S. Pat. No. 5,799,144, the JUMP instruction (and its operand, the start address of the patch code) is provided to the data bus in multiple bus cycles, and control unit 8 is required to set the proper sequencing and timing with which this information is provided to the data bus. This control unit comprises a particular form of sequential circuitry known as a state machine in which the outputs thereof depend on the present state of the inputs thereof, in addition to the present xe2x80x9cstatexe2x80x9d of the machine. For purposes of this disclosure, the definition of xe2x80x9csequential circuitxe2x80x9d is taken from The IEEE Standard Dictionary of Electrical and Electronics Terms, Sixth Edition, p. 970. The power consumed, cost, and space occupied by circuitry such as this will, in many cases, render this approach unsuitable for use in low power, cost conscious and space constrained applications, such as cordless or wireless handsets.
Therefore, what is needed is a system and method for implementing a software trap and patch function that is appropriate for these low power, cost conscious, and space constrained applications.
Accordingly, the present invention provides a system and method for implementing a software trap and patch function for program code that requires only the addition of combinational circuitry to the microprocessor for purposes of placing a predetermined instruction on the data bus responsive to a trap condition and does not require the addition of any sequential circuitry such as a state machine to perform this function. As is known to those of skill in the art, a combinational circuit is one in which the outputs thereof depend only on the present state of the inputs thereof. For purposes of this disclosure, the definition of xe2x80x9ccombinational circuitxe2x80x9d is taken from the IEEE Standard Dictionary of Electrical and Electronics Terms, Sixth Edition, p. 177.
In particular, when a programming error is discovered in program code stored in a first memory, patch code is provided in a second memory accessible by the microprocessor. In addition to the patch code, a trap address and a patch address, are also provided. The trap address is the address of the beginning of the code segment in the first memory that contains the error. The patch address is the address of the area in the second or other memory at which the patch code will reside during execution thereof. Typically, the first memory is ROM, but it should be appreciated that other forms of memory are possible. In addition, the second memory is typically non-volatile RAM (xe2x80x9cNVRAMxe2x80x9d), electronically-erasable programmable ROM (xe2x80x9cEEPROMxe2x80x9d), or external ROM, but again, it should be appreciated that other forms of memory are possible. In one implementation, since the cost/bit of the second memory is typically greater than that of the first memory, it is not generally economically feasible to replicate the entire program code, with the bug or error corrected, in the second memory. Also, in this implementation, other distinctions between the first and second memories are that the first memory tends to be larger than the second memory, and the second memory is modified in the field. In one embodiment, the microprocessor transfers the patch code from the second memory to a third memory which is also accessible by the microprocessor. The patch code is then executed while resident in the third memory. In this embodiment, the third memory is typically RAM, but it should be appreciated that other forms of memory are possible.
The patch code is designed to replace the code segment containing the error. In one embodiment, the patch code is added by a distributor, value added reseller (xe2x80x9cVARxe2x80x9d), or original equipment manufacturer (xe2x80x9cOEMxe2x80x9d) to a second memory already being installed by the distributor, VAR or OEM to add additional features and functionality to the device. In this embodiment, the patch code is stored in the second memory as part of an integrated data structure containing the patch code, the trap address, and optionally, the start address of the patch code. In another embodiment, the second memory is already present in the device, and this data structure is downloaded to this second memory from a remote location through a wireless or other communications link, such as telephone lines or the Internet.
According to the subject invention, a power-on-reset (xe2x80x9cPORxe2x80x9d) process is provided to detect the presence of the patch code in the second memory upon power-up of the microprocessor or upon occurrence of a reset condition. If patch code is present, pursuant to the process, the trap address is downloaded into a holding circuit, the patch address is downloaded into a predetermined patch address vector, the patch code is optionally copied into the third memory, and an enable circuit is activated to enable the trap and patch function.
A compare circuit compares addresses sent out over the address bus by the microprocessor with the contents of the holding circuit. If a match is detected, indicating an attempted access to the error-containing code in the first memory, a trap condition signal is asserted. Responsive to the occurrence of the trap condition, a disable first memory switch disconnects the first memory from the data bus. In addition, in one embodiment, a predetermined bit in the processor status register (xe2x80x9cPSRxe2x80x9d), which, if placed in a first state, is placed in a second state, and a predetermined instruction circuit places on the data bus the operation code of a predetermined software instruction. Preferably, the predetermined instruction circuit comprises solely combinational circuitry. In one embodiment, this circuit places the predetermined instruction on the data bus in a single bus cycle. In an implementation example of this embodiment, the predetermined instruction is a software interrupt instruction lacking any operands in which the operation code thereof is all zeroes, and the predetermined instruction circuit simply places all zeroes on the data bus upon the occurrence of a trap condition.
In accordance with the invention, when the microprocessor executes the predetermined instruction placed on the data bus, a jump is automatically made to an interrupt service routine. In this interrupt service routine, in one implementation, the predetermined bit in the PSR is examined to determine if the interrupt is a hardware interrupt. If it is in the first state, indicating that the interrupt was prompted by a hardware interrupt condition, the hardware interrupt service procedure is executed. If, however, it is in the second state, indicating that the interrupt was prompted by a trap condition or a software interrupt, the following procedure is executed. In one implementation, in the initial part of this procedure, a check is made to determine if the interrupt was caused by a trap condition or a software interrupt. In one example, this is accomplished by comparing the patch address with the address stored on the stack. If the address stored on the stack is the next sequential location following the trap address, it is determined that the interrupt was caused by a trap condition. Otherwise, it is determined that the interrupt was caused by a software interrupt.
In this manner, the software interrupt instruction need not be dedicated to the function of responding to a trap condition, and a user is not precluded from also utilizing the software interrupt instruction in program code to generate a software interrupt responsive to a user-defined condition. That is to say, the software interrupt instruction is capable of serving the dual purpose of generating a software interrupt responsive to a user-defined condition and an interrupt responsive to a trap condition.
Of course, in a scenario in which software interrupts are not supported, the foregoing step could be avoided. Also, it should be appreciated that other methods are possible for detecting whether the interrupt is a hardware interrupt. For example, a hardware interrupt could be serviced by an entirely different service routine than that used to service software interrupts or interrupts due to trap conditions. There would then be no need to determine if the interrupt is a hardware interrupt in the service routine for software interrupts or interrupts due to trap conditions.
Responsive to the predetermined bit being in the second state, a portion of the service routine responsible for responding to either a software interrupt or a trap condition is executed. First, the context of the microprocessor is optionally saved. Then, in one implementation in which software interrupts are supported, the address stored on the stack is compared with the patch address to determine if the address stored on the stack is the next sequential address following the patch address, indicating that the interrupt was caused by a trap condition. (In another implementation, in which software interrupts are not supported, this step could be avoided, as it could safely be assumed that a trap condition caused the interrupt.) If a software interrupt caused the interrupt, the software interrupt service routine is executed, while, if a trap condition caused the interrupt, the start address of the patch code is retrieved from the predetermined patch address vector, and stored in the program counter (xe2x80x9cPCxe2x80x9d) of the microprocessor. In this fashion, a jump to the patch code is executed. The microprocessor then executes the patch code and, when this has been accomplished, selectively restores context, and returns to an address within the first memory immediately after the program code containing the software error.
An advantage of the present invention is that it requires only the addition of combinational logic to the microprocessor for the purpose of placing a predetermined instruction on the data bus, rather than the sequential logic which characterizes conventional approaches. The result is an overall circuit design that consumes less power and requires less space and cost than the conventional approaches, and thus is more suitable for many consumer electronic devices.
Another advantage of one embodiment of the present invention is that, by distinguishing between an interrupt generated responsive to a trap condition, and a software interrupt generated upon the occurrence of a user-defined condition, the predetermined instruction, in this case, the software interrupt instruction, need not be dedicated to the function of generating an interrupt responsive to a trap condition, but can serve the additional purpose of generating a software interrupt.
Still another advantage of one embodiment of the present invention is that the software trap and patch function is implemented using a predetermined instruction that can be placed on the data bus in a single bus cycle. This eliminates the need for a state machine as required in conventional approaches to place a predetermined instruction on the data bus in multiple bus cycles.
Yet another advantage of one embodiment of the present invention is a software trap and patch system that does not require specialized circuitry to handle other interrupts, either hardware or software, that may occur during the trap and patch process.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds