The present invention relates, in general, to electronics and, more particularly, to semiconductor device structures and methods of forming semiconductor devices.
Semiconductor diodes are common device structures used in integrated circuit designs and are typically used to control the direction of current flow. Diodes are two terminal devices with the positive terminal referred to as the anode and negative terminal referred to as the cathode. In general, diodes have two modes of operation: forward bias with substantial current conduction, and reverse bias with negligible current conduction.
In most integrated circuit devices utilizing bulk semiconductor substrate technology, both the cathode terminal and the anode terminal need to be biased either positive or negative versus the potential or bias of the bulk substrate in which the diode is formed, and designers have been required to pre-select which bias (i.e., positive or negative) will be used in the integrated circuit application. Otherwise diode structures, such as isolation structures (i.e., parasitic diodes become forward biased), start conducting current, which leads to, among other things, unwanted large currents, latch-up phenomena, permanent electrical shorts, and noise issues if the wrong bias is encountered during operation. This requirement to pre-select whether the diode terminals are biased either positive or negative versus the substrate potential limits design flexibility particularly in higher voltage automotive applications where large negative voltage spikes, inductive transients, and battery reversal problems often conflict with the bias condition the designer selected. To solve this problem, designers have resorted to using external diodes, which requires added costs, requires extra connective pins, and requires additional printed circuit board space, among other unwanted constraints. Designers have also resorted to silicon-on-insulator (SOI) technologies to solve this problem, but SOI technologies are quite expensive and more difficult to manufacture. Moreover, the buried oxide in SOI creates an extra thermal resistance that is unwanted in many automotive or other high power applications.
Accordingly, it is desirable to have a diode structure and a method of forming the diode structure that enables both a positive bias and a negative bias versus the potential of the bulk substrate in order to increase design flexibility and enhance device performance under adverse operating conditions. It is also desirable for the diode structure to have low current injection into the bulk substrate in order to minimize the effects of parasitic structures adjacent the diode structure, such as parasitic bipolar transistor structures.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.
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