1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device in which a memory cell array is divided into a plurality of blocks.
2. Description of the Related Art
When data is to be written into a flash memory, high potential is applied to the gate and drain of a memory cell, thereby injecting channel hot electron into the floating gate. The potential applied to the drain of the memory cell is preferably set to as high potential as possible when considering the speed of data writing. If this potential is too high, however, drain disturb occurs at memory cells that are not selected. This causes charge loss, i.e., electron trapped in the floating gate leaks. The potential applied to the drain should thus be set within a predetermined range.
In conventional flash memories, such drain potential is set to a predetermined level by a booster circuit and a regulator circuit. As the length of bit lines increases together with the size of flash memories, a potential drop caused by bit-line resistance becomes increasingly noticeable when electric currents run through bit lines. This is especially so near the endpoint of the bit lines. This makes it difficult to set the drain potential at the time of write operations within a predetermined range with respect to all the memory cells.
In order to obviate this problem, Japanese Patent Application No. 2001-303709, which was filed by the same applicant as this application, adjusts a potential regulated by a regulator circuit according to address signals that determine the position of accessed memory cells, thereby setting the drain potential within a predetermined range. The regulator circuit divides a boosted potential generated by a booster circuit by use of a series connection of condensers, and adjusts the output potential (drain potential) according to the comparison of the divided potential with a reference potential. The capacitances of the condensers are controlled based on the address signals, thereby adjusting the output potential in accordance with the position (i.e., address position) on the bit lines.
A further example of the related art (Patent Document 1) adjusts a potential by which data is written.
[Patent Document 1]
Japanese Patent Application Publication No. 11-297086
In semiconductor memory devices such as flash memories, provision is often made to provide a memory cell array that is divided into a plurality of blocks. Such division into blocks can reduce the load on bit lines and word lines, providing the advantage of high-speed data access. In the multi-block configuration, only one set of a booster circuit and a regulator circuit is generally provided, and the output of the regulator circuit is supplied to each memory cell in each block. In such a case, the distance from the regulator circuit to memory cells is not related to addresses in a straightforward manner. Because of this, the technology disclosed in the above-cited patent application does not properly work where a memory cell array is divided into blocks.
Accordingly, there is a need for a nonvolatile semiconductor memory device in which a constant data-write potential is supplied to memory cells regardless of the position of the memory cells even when a memory cell array is divided into a plurality of blocks.
USPTO Backgrounds
USPTO Backgrounds