1. Field of Invention
The present invention relates to an integrated circuit (IC) fabrication, and particularly to a patterning method.
2. Description of Related Art
As the level of integration of integrated circuits is getting increased, the demand for increasing the feature density or reducing the pitch size becomes the mainstream in the semiconductor industry, and the key technology is in photolithography.
However, when the pitch size is beyond the photolithography resolution, a single exposure step is no longer applicable due to the pitch constraint. The pattern decomposition (or called “pattern split” or “double patterning”) technique is accordingly developed to meet the process requirements. After the target pattern is decomposed into two patterns respectively defined on two photomasks, the 2P2E (photo-etch-photo-etch) approach utilizing two photolithography steps and two etching steps is implemented.
In the case that the first photolithography step and the first etching step are completed and the second photolithography step has to be removed for rework, a portion of components (e.g. SiGe source/drains) exposed after the first etching step may be damaged during the rework, and the device performance may be therefore deteriorated.
USPTO Backgrounds
USPTO Backgrounds