The present invention relates to a method of fabricating a semiconductor device having an N.sup.+ -type layer or P.sup.+ -type layer containing an impurity in a concentration of 1.times.10.sup.19 /cm.sup.3 or more, or a semiconductor device having a silicon based gate electrode structure containing an impurity.
In fabrication of various semiconductor circuits such as MOS circuits and bipolar circuits, heat treatments at 700.degree. C. or more are performed in many processing steps for the purpose of activation of impurities in diffusion layers and polysilicon based gate electrodes, densification of insulating films, and the like. For example, in a MOS structure, a polysilicon (hereinafter, referred to as poly-Si) or a polycide having a stacked structure of poly-Si and metal silicide is often used as a gate electrode for ensuring reliability of a gate oxide film in a high temperature process, and in a fabrication process of such a MOS structure, a heat treatment at 700.degree. C. or more is usually performed for activation or the like of an impurity in a poly-Si.
One of these heat treatments performed at 700.degree. C. or more is a high temperature/short-time anneal, that is, a rapid thermal anneal (hereinafter, referred to as RTA) for effectively activating an impurity while suppressing diffusion of the impurity. In recent years, the RTA is being variously carried out as a technique essential for fabrication of semiconductor devices.
Incidentally, in fabrication of a semiconductor device, heat treatments at temperatures of from 600 to 850.degree. C., such as high temperature/long-time anneal for densifying an insulating film and high temperature CVD, are usually performed after the above-described RTA.
The long-time heat treatment performed after the RTA, however, is disadvantageous in that the impurity once activated by the RTA is inactivated again, tending to increase resistances of Si constituting a diffusion layer and poly-Si constituting a gate electrode or to deplete a gate electrode, resulting in the degraded device characteristics. This leads to reduction in performances of the semiconductor device.
FIG. 1 is a graph showing variations in sheet resistance of an N.sup.+ -type diffusion layer and a P.sup.+ -type diffusion layer of a semiconductor device subjected to post-anneal for 30 minutes after RTA (1000.degree. C..times.10 seconds). In addition, the ion implantation of the N.sup.+ -type diffusion layer and the P.sup.+ -type diffusion layer is performed such that ions of As (As.sup.+) are implanted into the N.sup.+ -type diffusion layer in a dose of 3.times.10.sup.15 /cm.sup.2 and ions of BF.sub.2 (BF.sub.2.sup.+) are implanted into the P.sup.+ -type diffusion layer in a dose of 4.times.10.sup.15 /cm.sup.2.
As seen from FIG. 1, the sheet resistance of the semiconductor device is significantly increased in the case where the semiconductor device is subjected to the high temperature/long-time anneal (post-anneal) at a temperature of from 800 to 850.degree. C., as compared with the case where the semiconductor device is not subjected to the post-anneal, that is, it is subjected only to RTA.
The same is true for a silicon based gate electrode. For example, a high temperature/long-time anneal performed at a temperature of from 800 to 850.degree. C. for 30 minutes after RTA tends to cause depletion of poly-Si and hence to reduce a gate capacity.
To cope with such an inconvenience, an attempt may be made to set higher a temperature of high temperature/long-time anneal for lowering the resistances of a diffusion layer and a gate electrode and for improving depletion of the gate electrode. In this attempt, however, a depth (Xj) of the diffusion layer is increased, failing to suppress a short channel effect, and further in the case where an N.sup.+ -type gate of a NMOS is connected to a P.sup.+ -type gate of a PMOS in a CMOS structure, there arises a disadvantage in causing mutual diffusion of impurities in the gate electrodes, tending to vary (increase) a threshold voltage (Vth).
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