The present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFET""s to include increasingly smaller device features. New device structures are, therefore, being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the present invention provide an exemplary process for forming double fins for a double-gate FinFET. The exemplary process, consistent with the invention, improves short-channel effects in the FinFET by thinning the double fins to create narrow fins using, for example, a thermal oxidation process. The exemplary double fin formation process may also, consistent with the invention, increase the device density, thus, reducing the pitch.
Additional advantages and other features of the invention will be set forth in pale in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming fins for a double-gate fin field effect transistor (FinFET). The method includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
According to another aspect of the invention, a method of forming fins for a double-gate fin field effect transistor (FinFET) is provided. The method includes depositing a silicon layer over a buried oxide layer and depositing a Si3N4 layer over the silicon layer. The method further includes etching the Si3N4 layer to form double caps, wherein each of the double caps comprises a rectangular cross-section with a width ranging from about 100 xc3x85 to about 1000 xc3x85, and depositing and etching an oxide material to form spacers adjacent sides of each of the double caps, wherein the oxide material includes SiO or SiO2. The method also includes etching the silicon layer to form fins beneath each of the double caps and thermally oxidating the fins to thin the fins so as to produce narrow fins, wherein each of the narrow fins has a thickness ranging from about 50 xc3x85 to about 500 xc3x85.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.
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USPTO Backgrounds