The present invention relates to a semiconductor integrated circuit device, for example, a semiconductor integrated circuit device including an ECL (Emitter Coupled Logic) circuit. More particularly, the present invention pertains to a technique which may be effectively applied to a logic integrated circuit or the like which includes ECL flip-flop circuits defined by ECL series gate circuits (cascade circuits).
Known ECL flip-flop circuits include, for example, those which are described in "SEMICONDUCTOR DATA BOOK ECL", published from Hitachi, Ltd. in Sept. 1983, pp. 63 to 65.
A high-speed logic integrated circuit including a multiplicity of ECL flip-flop circuits is known. As an ECL flip-flop circuit for use in such a logic integrated circuit, the present inventors proposed one such as that shown in FIG. 3. More specifically, the illustrated flip-flop circuit is arranged such that two differential transistor pairs (T13 and T14; and T15 and T16) are cross-coupled to each other through two emitter follower circuits (T19 and R11; and T20 and R10).
USPTO Backgrounds
USPTO Backgrounds