1. Field of the Invention
This invention relates to integrated circuit chip testing, and more particularly, to flexible modular redundancy allocation logic for memory built in self test of SRAM with redundancy.
2. Description of Background
In order to test random access memory (RAM) macros, e.g., static random access memory (SRAM) macros with redundant elements for failure relief, by means of Array Built In Self Test (ABIST), the data from the array is usually compared to expected data generated by the self test ABIST function. To this end, the ABIST circuitry is used for vector generation of address and data, and subsequent comparison circuitry is used to provide a bit wise fail vector corresponding to each of the data outs of the memory array, or device under test. This additional circuitry is either embedded in the SRAM or provided in surrounding logic.
This fail vector, or the situation of determining that a fail has occurred, is then processed to determine whether the failure can be repaired using the redundant elements/circuitry of the memory array under test. This processing for establishing the redundant element configuration for failure relief is traditionally handled “off-chip” by various test equipment apparatus and peripheral computer software analysis of the component under test as described in U.S. Pat. No. 6,594,788 issued on Jul. 15, 2003, entitled “Method of Analyzing a Relief of Failure Cell in a Memory and Memory Testing Apparatus Having a Failure Relief Analyzer Using the Method”; and U.S. Pat. No. 5,790,559 issued on Aug. 4, 1998, entitled “Semiconductor Memory Testing Apparatus.”
Similarly, apparatus involving large memory storage (e.g., storage equal to the target memory array) can be used to support memory integrated circuit (IC) testing with redundant circuits as described in U.S. Pat. No. 5,337,318 issued on Aug. 9, 1994, entitled “Memory IC Testing Apparatus With Redundancy Circuit”, and which recites an apparatus for processing and determining repairability of a target memory array.
The memory array redundant elements can be provided in a plurality of configurations, usually based on the overall size of the memory array macro, addressing configuration, and the number of data outs provided. Memory arrays can be viewed as three dimensional binary storage elements: considering a row dimension and a column dimension to describe an array of memory cells, and this array of cells can be replicated to provide for a plurality of data input/output bits, each composed of the two dimensional array of memory cells. To generalize the categories for background purposes here, DRAM macros (due to the high number of memory bits) will usually contain a plurality of column and word addressable redundant elements. That is, both spare rows of memory cells and spare columns of memory cells are provided for relief of manufacturing defects, each spanning the total number of data input/output pins for the memory array. SRAM macros are generally smaller in total size and, due to the larger memory cell requirements, are generally provided fewer spare elements, although these elements may be provided as both column and row addressable elements. In fact, due to generally fewer column addressable elements of a high speed SRAM macro, column addressable spare or redundant elements become costly in terms of the overall number of memory array cells. Therefore a secondary scheme of column spare elements can be provided by providing spare data inputs/outputs or some fraction of a data bit group of cells, as disclosed in patent application Ser. No. 10/814,719 entitled “Skip Over Redundancy Decode with Very Low Overhead”, filed on Mar. 31, 2004, and which is incorporated by reference herein in its entirety. A more general case is to reduce the number of repair actions, or to limit the redundant elements to a single dimension of row addressable or column addressable elements only.
The support for two dimensional redundancy allocation is described in U.S. Pat. No. 5,859,804 issued on Jan. 12, 1999, entitled “Method and Apparatus for Real Time Two Dimensional Redundancy Allocation”, which discloses an array built in self test (ABIST) system disposed on a single semiconductor chip. The chip provides a memory array having a plurality of column lines and a plurality of row lines and at least one redundant column line and at least one redundant row line with cells coupled to the lines at intersections thereof. This patent thus describes a method and apparatus provided in an array built in self test (ABIST) environment formed on the semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.
What is needed, therefore, is a way to reduce the complexity of the logic and process to establish a repairable configuration of a memory array with redundant elements, thereby reducing the test time and cost required. What is further needed is a way to reduce the circuit overhead of the test compare and processing for establishment of the redundant element configuration for failure relief of memory arrays with redundant circuits.
USPTO Backgrounds
USPTO Backgrounds