In modern electronic devices such as mobile phones, computers etc. there is a continuous strive for miniaturization and close-packing of components. In the continuous strive of making micro components more densely packed, problems are encountered in particular where wafer through structures (also referred to as vias) are provided in very close proximity to each other. In particular where the vias are made from a material that is different from the substrate material in which they are provided, e.g. metal and silicon in the vias and substrate respectively, different thermal expansion effects may lead to substrates being subject to cracking and breaking during manufacturing, or other reliability issues during use.
Among other things it is desirable to be able to stack chips carrying various devices on top of each other, so called interposers. Also, it is desirable to be able to provide so called redistribution layers or routing structures for signals coming from integrated circuits having large numbers of I/O contacts. Such contacts can be as many as several thousand on a chip of a size of the order of 10 mm square. If the signals are to be routed through the substrate, the through-substrate connections (vias) would have to be equally closely spaced. When such vias are made of metal and very closely spaced, thermal expansion effects due to different coefficients of expansion may cause damage to the very thin and brittle chips in which they are made. This frequently occurs both during processing but also in use in the end product, if it is subjected to temperature changes over large intervals. Also, the thickness of the substrate for such vias would have to be in the order of 100 μm, which is extremely.
Thus, in modern electronic devices such as mobile phones, the different thermal expansion coefficients for the various materials in the housing, the circuit boards, and the micro chips (MEMS, CMOS and the like), respectively, inevitably will cause problems unless relevant design measures are taken.
It is not suitable to provide routing by vias directly from each I/O point on a IC chip through the substrate on which the chip is mounted. Instead one provides for the above mentioned redistribution structures on the surface of the substrate on which the chip is mounted. The routings are “fanned out”, i.e. the individual conductive strips diverge from the I/O points to a more widely spaced structure, where vias for routing through the substrate are provided.
However, even with such precautions there will be a tendency for thermal stress in the interface between the I/O points and the substrate. To alleviate this effect a conventional procedure is to provide so called “underfill” in the very small space between the substrate and IC chip, using capillary forces. However, this requires that the vias are completely filled to be hermetically sealed such that there will be no leakage of underfill between the stacked structures, which could lead to improper underfill, degradation of the final product, reliability issues and packing issues, rendering final product useless.
Thus, it is desirable to provide filled vias. However, filling conventional vias with metal again will bring the thermal expansion effects into play, in particular if they were to be provided directly beneath the IC chip.
Also, as mentioned above, from a processing point of view, the thickness of the substrate normally cannot be as small as 100 μm without the use of carriers, but rather 300 μm and more is more reasonable not requiring carriers. However, for 300 μm thick wafers it is difficult not to say impossible to make void free hermetically tight vias of the size desirable, e.g. 15-100 μm in diameter, that extend through the substrate, in a cost efficient manner, i.e. in volume production.
No suitable conductive metal for making TSVs that has CTE that matches the Silicon is known at present.
USPTO Backgrounds
USPTO Backgrounds