This invention relates to electronic integrated circuits (ICs) of the type having multiple layers of metal interconnects formed on top of one another on a substrate of the IC. More particularly, the present invention relates to a new and improved metal-insulator-metal capacitor which is formed within an interconnect layer of the IC to create a more reliable capacitor, to simplify the process of the capacitor fabrication, and to facilitate the formation of multiple layers of interconnects on the IC, among other things.
The ongoing advances in the field of fabricating miniaturized electronic integrated circuits (ICs) has involved the fabrication of multiple layers of interconnects. Interconnects refer to the layer of separate electrical conductors which are formed on top of the substrate and which connect various functional components of the substrate and other electrical connections to the IC. Electrical connections between the interconnect layers and the functional components on the substrate are achieved by xe2x80x9cvia interconnects,xe2x80x9d which are post-like or plug-like vertical connections between the conductors of the interconnect layers and the substrate. Presently manufactured ICs often have five or more interconnect layers formed on top of the substrate.
Only a relatively short time ago, it was impossible or very difficult to construct an IC with more than one or two layers of interconnects. The topology variations created by forming multiple layers on top of one another resulted in such significant depth of focus problems with lithographic processes that any further additions of layers were nearly impossible to achieve. However, recent advances in semiconductor fabrication planarization techniques, such as chemical mechanical polishing (CMP), have been successful in smoothing relatively significant variations in the height or topography of each interconnect layer. As a result of the smoothing, or planarization, conventional lithographic processes are repetitively employed without significant limitation to form considerably more layers of interconnects than had previously been possible.
The multiple interconnect layers consume volume within the IC, although they do not necessarily consume additional substrate surface area. Nevertheless, because surface area and volume are critical considerations in ICs, attention has been focused upon the effective use of the space between the interconnect layers. Normally the space between the interconnect layers is occupied by an insulating material, known as an interlayer dielectric (ILD) or intermetal dielectric (IMD), to insulate the electrical signals conducted by the various conductors of the interconnect layers from each other and from the functional components in the underlying substrate.
One effective use for the space between the interconnect layers is to incorporate capacitors between the interconnect layers in the IMD insulating material separating the interconnect layers. These capacitors form part of the functional components of the IC. Previously, capacitors were constructed in the first layers of IC fabrication immediately above the substrate alongside other structures, such as transistors, so the capacitors were formed of generally the same material used to construct the other functional components, such as polysilicon. Capacitors formed of these materials are generally known as poly-plate capacitors. The aforementioned inventions described in the referenced U.S. patent applications focus on different techniques for combining capacitors with the conductors of the interconnect layers to achieve desirable functional effects within the IC.
Because the conductors of the interconnect layers are metal in construction, the capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction to take advantage of processing steps and performance enhancements. A MIM capacitor has metal plates, usually formed on the metal conductors of the interconnect layers. Because metal fabrication is required for the conductors of the interconnect layers, the simultaneous or near-simultaneous formation of the metal capacitor plates is readily accomplished without significant additional process steps and manufacturing costs. The fifth above identified invention describes a technique for the simultaneous formation of one of the metal capacitor plates integrated with the conductors of the interconnect layers. Thus, at least part of the capacitor is readily fabricated without significant additional process steps and manufacturing costs.
Forming other parts of the capacitor between the interconnects does, however, require additional process steps. The additional process steps involve forming the components of the capacitor in the IMD insulating material and connecting the capacitor components to the conductors of the interconnect layers. In comparison, if the capacitor was not formed in the interlayer insulating material, the entire IMD layer could be conventionally formed. Furthermore, for this method, the via interconnects between the interconnect layers would all have approximately the same depth or height dimension, thereby facilitating the construction of the via interconnects through the IMD insulating material and the formation of the interconnects within the vias. With the presence of the capacitor in the IMD layer, however, the via interconnects do not all have the same depth because the top of the capacitor is higher than the top of the interconnect layer, upon which the capacitor sits. For this case, the selectivity of the IMD material has to be sufficiently high relative to the top electrode material, or the top electrode has to be sufficiently thick, to prevent the via etch process from etching through the top electrode and shorting out the capacitor. In addition, the orientation of the capacitor between the interconnects increases the thickness of the IMD insulating material between the interconnect layers and presents a bulge in the IMD insulating material deposited on top of the capacitor, thereby requiring additional effort, time and/or processing steps in performing the planarization steps to achieve a sufficiently planar surface for the formation of the next vertically-spaced interconnect layer. The increased thickness of the IMD insulating material also consumes additional insulating material, prolongs the fabrication process and increases the variation in IMD thickness, resulting in degraded performance of the IC and/or an increase in defectivity of the ICs thus manufactured. Furthermore, an increased thickness of the IMD increases the overall volume of the IC. In addition to the greater complexity in IC fabrication processing, further design rules must be added to equalize the pattern density of the interconnect layer to prevent formation of topography that cannot be planarized in a conventional CMP process.
It is with respect to these and other background considerations that the present invention has evolved.
One aspect of the present invention relates to the discovery that the typical process thermal cycles required for insulator densification, dielectric deposition, alloying (transistor passivation) and the formation of the interconnects in layers may diminish or destroy the functionality of capacitors connected to the interconnect conductors. There is a relatively large thermal expansion mismatch between aluminum layer components of the interconnect layers and the interlayer insulating material. The normal temperature excursions inherent in the thermal fabrication processes may cause metal deformation known as a xe2x80x9chillockxe2x80x9d in the softer aluminum layer of the interconnect. If the hillock is significant in size, it will penetrate through the dielectric material between the plates of the MIM capacitor, thereby shorting together the capacitor plates. Even if the size of the hillock is not significant enough to short the capacitor plates, the dielectric between the capacitor plates at the location of the hillock is highly stressed, increasing the leakage current, which diminishes the value of the capacitance and may eventually result in an early failure of the IC. In the cases of diminished capacitance and shorted capacitor plates, the functionality of part or all of the IC is either destroyed or greatly diminished.
The new and improved MIM capacitor of the present invention, and the method of fabricating it, are effective in overcoming the problem associated with hillock formation and its resulting detrimental impact on the capacitors formed, as well as permitting vias to be formed through the IMD insulating material to both the capacitor and the interconnect layer at substantially the same depth and dimension, allowing the IMD insulating material to assume a normal height over the capacitor preventing the formation of bulges in the IMD layer requiring extensive planarization steps to smoothen. This process also eliminates the need for additional design rules associated with interconnect pattern density equalization. The plates of the capacitor do not utilize or require the aluminum layer within the interconnect conductors, thereby avoiding the problem of thermal mismatch and hillock formation. The capacitor itself is embedded within the thickness of the conductor interconnect layer, thereby avoiding the difficulties associated with forming the capacitor above the interconnect layer in the IMD insulating material. By embedding the capacitor within the thickness of the interconnect layer, the fabrication process is simplified by reducing the amount of planarization required, reducing the number of fabrication steps connected solely with forming the capacitor, and allowing the IMD insulating material to be formed in a more uniform thickness and/or reduced thickness because the structure of the capacitor itself does not need to be accommodated in the IMD layer between the interconnect layers. This process also prevents variability in IMD thickness, resulting in a more precise interconnect delay model and in performance improvements. The reduction in IMD variability also improves IC component fabrication yield from a wafer substrate. Furthermore, because the capacitor components are embedded within the interconnect layer, the height or level of the capacitor components may be made approximately the same as the height of the interconnect layer, thereby allowing the process of forming the holes for the via interconnects through the IMD to proceed uniformly throughout the IC structure without the added risks of damaging components of different heights, as would be the case with the capacitor formed in the interlayer insulating material between the distinct interconnect layers.
These and other improvements are achieved in an IC that has a substrate overlaid by an interconnect layer with a cavity in the interconnect layer and a capacitor embedded within the cavity. Additional preferred aspects of the present invention relate to the interconnect layer preferably including upper, middle and lower conductive layers, and the cavity being located principally within the middle conductive layer, which may be subject to deformation under temperature changes due to thermal processing of the IC, as may occur in an aluminum layer. Preferably, the capacitor comprises a pair of plates, e.g. top and bottom plates, separated by a capacitor dielectric material with one of the plates formed by a portion of the interconnect layer in the cavity. For example, the bottom plate is preferably integral with the lower conductive layer of the interconnect layer. Additionally, it is preferable that the bottom plate of the capacitor be about level with the lower conductive layer of the interconnect layer, and that the top plate be about level with or lower than the upper conductive layer. Where the interconnect layer comprises upper, middle and lower conductive layers, the cavity preferably extends through the upper and middle layers, and the capacitor bottom plate is formed by a portion of the lower conductive layer. Alternatively, the bottom plate is electrically connected to the interconnect layer, and preferably, via interconnects connect to the top plate and to the next interconnect layer above the capacitor. Additionally, the bottom plate may be connected to the interconnect layer below through a previously formed via.
Another aspect of the present invention involves an embedded capacitor structure formed in an interconnect layer of an integrated circuit comprising a lower conductive layer of the interconnect layer and both an upper conductive layer and a top capacitor plate overlying the lower conductive layer and laterally offset from each other. Additional preferred aspects of this embodiment of the present invention relate to a top surface of the top plate being level with or lower than a top surface of the upper conductive layer. It is also preferable that the capacitor is located in the middle section of the conductive layer of the interconnect layer, made up primarily of aluminum. A bottom capacitor plate is preferably integral with or defined by the lower conductive layer. Via interconnects preferably connect directly to the top plate and electrically communicate indirectly to the bottom plate through the conductive layers of the interconnect layer. The via interconnects preferably extend through an intermetal dielectric (IMD) layer for connecting to another interconnect layer.
The previously mentioned and other improvements are achieved in a method of fabricating a capacitor in an IC having an interconnect layer overlying a substrate, which generally involves the steps of forming a cavity into the interconnect layer and forming a capacitor substantially within the cavity. Additional preferred method aspects of the present invention relate to forming the capacitor with substantially horizontal top and bottom plates and a horizontal layer of dielectric material therebetween, and locating the top plate level with or below an upper surface of the interconnect layer. Likewise, the bottom plate is preferably located at about a lower surface of the interconnect layer. The method preferably forms top and bottom capacitor plates with one of the plates formed as an integral portion of the interconnect layer. The cavity is preferably formed through an upper conductive layer of the interconnect layer, or through upper and middle conductive layers of the interconnect layer, and exposes a lower conductive layer, on which a dielectric layer is formed with a top capacitor plate formed on top of the dielectric layer. On top of the top plate and the upper conductive layer, an IMD layer is preferably formed, and via interconnects are formed therethrough to electrically contact the top plate and upper conductive layer. The via interconnects are preferably formed to about the same depth.
A more complete appreciation of the present invention and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments of the invention taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.
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