1. Field of the Invention
The present invention relates to a boosting circuit in a semiconductor device and, more particularly, to a boosting circuit in a semiconductor memory device that has rapid read access time in a read operation, and can minimize consumption of current and generate a stabilized word line voltage (W/L), by rapidly raising a boosting voltage (VBOOT) to a given voltage level in two steps using a preboosting circuit unit and a bootstrap circuit unit and then dropping the boosting voltage (VBOOT) through a clamp circuit unit to generate a final target voltage.
2. Discussion of Related Art
In memory cells of electrically erasable and programmable read only memory (EEPROM) being a kind of a nonvolatile semiconductor device, a program operation is performed by accumulating electrons on a floating gate electrode, and a read operation of data is performed by detecting variation in the threshold voltage (Vth) depending on the existence or nonexistence of the electrons. The EEPROM includes a flash EEPROM (hereinafter referred to as ‘flash memory device’) in which the erase operation of data is performed over the whole memory cell array or in each block unit after dividing the memory cell array into given blocks.
In order for the program operation, the erase operation and the read operation of the flash memory device to be performed, the role of a high voltage-generating circuit to generate high voltages (for example, Vpgm; program voltage, Vera; erase voltage, Vrea; read voltage) that are supplied to the control gate of the memory cell is very important. Due to the tendency that all the semiconductor memory devices have a low voltage, recently, it is required that the flash memory device operates under a low voltage (for example, below 2V or below 1.7V). In accordance with this trend, in order to keep a rapid operating speed of the flash memory device, the role of the high voltage-generating circuit is very important.
Of the high voltage-generating circuit, a read voltage-generating circuit for performing the read operation employs a bootstrap circuit in order to increase the speed of the read operation. Such bootstrap circuit boosts a low potential power supply voltage to supply the boosted voltage to a word line through a row decoder. In the event that the low potential power supply voltage is boosted using this bootstrap circuit, if the word line voltage boosted by the bootstrap circuit is too low, it is difficult to exactly read the current of the memory cell. On the contrary, if the word line voltage boosted by the bootstrap circuit is too high, stress is given to the control gate of the memory cell. This causes a problem in data retention characteristics.
In the above, in order to solve the latter, a clamp circuit is positioned in the rear of the bootstrap circuit in order to drop the voltage boosted by the bootstrap circuit (hereinafter referred to as ‘boosting voltage’) to a target voltage.
FIG. 1 is a block diagram illustrating the construction of a boosting circuit in a conventional flash memory device and FIG. 2 shows an enable signal generator.
Referring to FIGS. 1 and 2, a boosting circuit 100 includes a bootstrap circuit unit 110, a reference voltage generator 120 and a clamp circuit unit 130. The bootstrap circuit unit 110 boosts a low potential power supply voltage (Low Vcc) or a high potential power supply voltage (High Vcc) to output the boosting voltage (VBOOT). The reference voltage generator 120 is driven by an enable bar signal (ENb) to output a reference voltage (Vref). The clamp circuit 130 is driven by an enable signal (EN) and the enable bar signal (ENb) and compares the boosting voltage (VBOOT) outputted from the bootstrap circuit 110 and the reference voltage (Vref). As a result of the comparison, if the boosting voltage (VBOOT) is higher than a target voltage, the clamp circuit 130 drops the boosting voltage (VBOOT) to the target voltage.
In order to generate the stable boosting voltage (VBOOT), however, access time (i.e., time taken to drop the boosting voltage, after raising the boosting voltage to the target voltage) is lengthened.
USPTO Backgrounds
USPTO Backgrounds