1. Field of the Invention
Embodiments of the present invention generally relate to a method and an apparatus of forming a high-k dielectric layer. More particularly, embodiments of the invention relate to a method of forming a gate dielectric layer.
2. Description of the Related Art
Integrated circuits are composed of many, e.g., millions, of devices such as transistors, capacitors, and resistors. Transistors, such as field effect transistors, typically include a source, a drain, and a gate stack. The gate stack typically includes a substrate, such as a silicon substrate, a gate dielectric, and a gate electrode, such as polycrystalline silicon, on the gate dielectric. The gate dielectric layer is formed of dielectric materials such as silicon dioxide (SiO2), or a high-K dielectric material having a dielectric constant greater than 4.0, such as SiON, SiN, hafnium oxide (HfO2), hafnium silicate (HfSiO2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), Zirconium silicate (ZrSiO2), barium strontium titanate (BaSrTiO3, or BST), lead zirconate titanate (Pb(ZrTi)O3, or PZT), and the like. It should be noted, however, that the film stack may comprise layers formed of other materials.
FIG. 1A shows a cross section of FET (field effect transistor) 10 incorporating a gate dielectric layer 14. The figure shows a substrate 12 on which a gate dielectric layer 14 and gate electrode 16 are disposed. Side wall spacers 18 are shown adjacent to the vertical sidewalls of gate dielectric layer 14 and gate electrode 16. Source/drain junctions 13 are formed in substrate 12 substantially adjacent the opposing vertical sidewalls of gate electrode 16.
As integrated circuit sizes and the sizes of the transistors thereon decrease, the gate drive current required to increase the speed of the transistor has increased. The drive current increases as the gate capacitance increases, and capacitance=kA/d, wherein k is the dielectric constant of the gate, d is the dielectric thickness, and A is the area of the device. Decreasing the dielectric thickness and increasing the dielectric constant of the gate dielectric are methods of increasing the gate capacitance and the drive current.
Attempts have been made to reduce the thickness of SiO2 gate dielectrics below 20 Å. However, it has been found that the use of SiO2 gate dielectrics below 20 Å often results in undesirable effects on gate performance and durability. For example, boron from a boron doped gate electrode can penetrate through a thin SiO2 gate dielectric into the underlying silicon substrate. Also, there is typically an increase in gate leakage current, i.e., tunneling current, with thin dielectrics that increases the amount of power consumed by the gate. Thin SiO2 gate dielectrics may be susceptible to NMOS hot carrier degradation, in which high energy carriers traveling across the dielectric can damage or destroy the channel. Thin SiO2 gate dielectrics may also be susceptible to PMOS negative bias temperature instability (NBTI), wherein the threshold voltage or drive current drifts with operation of the gate.
A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET (metal oxide semiconductor field effect transistor) includes nitridizing a thin silicon oxide film in a nitrogen-containing plasma. Increasing the net nitrogen content in the gate oxide to increase the dielectric constant is desirable for several reasons. For example, the bulk of the oxide dielectric may be lightly incorporated with nitrogen during the plasma nitridation process, which reduces the equivalent oxide thickness (EOT) over the starting oxide. This may result in a gate leakage reduction, due to tunneling during the operation of a FET, at the same EOT as the un-nitrided oxide dielectric. At the same time, such an increased nitrogen content may also reduce damage induced by Fowler-Nordheim (F-N) tunneling currents during subsequent processing operations, provided that the thickness of the dielectric is in the F-N tunneling current range. Another benefit of increasing the net nitrogen content of the gate oxide is that the nitridized gate dielectric is more resistant to the problem of gate etch undercut, which in turn reduces defect states and current leakage at the gate edge.
In U.S. Pat. No. 6,610,615, titled “Plasma Nitridation For Reduced Leakage Gate Dielectric Layers” and issued on Aug. 26, 2003, McFadden et al. compares nitrogen profiles in a silicon oxide film for both thermal and plasma nitridation processes (see FIG. 1B). The nitrided oxide films are disposed on a silicon substrate. FIG. 1B further shows the nitrogen profiles in the crystalline silicon beneath the oxide film. The nitrogen profile data 22 for the thermally nitrided oxide shows a first concentration of nitrogen at a top surface of an oxide layer, a generally declining concentration of nitrogen deeper in the oxide, an interfacial accumulation of nitrogen at the oxide-silicon interface, and finally, a nitrogen concentration gradient that is generally declining with distance into the substrate. In contrast, it can be seen that the plasma nitridation process produces a nitrogen profile 24 that is essentially monotonically decreasing from the top surface of the oxide layer through the oxide-silicon interface and into the substrate. The undesirable interfacial accumulation of nitrogen seen with a thermal nitridation process does not occur with the ionic bombardment of the nitrogen plasma. Furthermore, the nitrogen concentration in the substrate is lower, at all depths, than is achieved with the thermal nitridation process.
As mentioned earlier, a benefit of increasing nitrogen concentration at the gate electrode-gate oxide interface is that dopant, such as boron, out-diffusion from polysilicon gate electrodes into or through the gate oxide is reduced. This improves device reliability by reducing defect states in the bulk of the gate oxide caused by, for example, in-diffused boron from a boron doped polysilicon gate electrode. Another benefit of reducing nitrogen content at the gate oxide-silicon channel interface is the reduction of fixed charge and interface state density. This improves channel mobility and transconductance. Therefore, plasma nitridation process has advantages over thermal nitridation process.
As semiconductor devices become smaller, the size of the silicon nitrided gate oxide layer has reached it practical limit. However, with the further scaling of nitrided silicon dioxide gate dielectric to smaller physical thicknesses (from 10 Å), the gate leakage has increased to unacceptable levels for practical device applications. Since the demand for reduced device sizes remains, new gate dielectric materials and/or processes are needed.
Replacement of silicon dioxide (SiO2) with a high-k dielectric type material has presented challenges. For example, high-k dielectric materials are typically deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques that tend to cause the carbon containing precursor material and other contaminants to be incorporated in the deposited film. The carbon and other contaminants adversely affect the dielectric properties of the gate dielectric layer. Also, the quality of the interface between a chemical vapor deposition (CVD) or atomic layer deposition (ALD) deposited high-k film and the channel region is not as robust as a silicon dioxide layer.
Therefore, there is a need in the art for a method and an apparatus for forming a gate dielectric layer that has improved dielectric properties and a smaller EOT.
USPTO Backgrounds
USPTO Backgrounds