1. Field of the Invention
The present invention relates to a pipeline processing apparatus including a plurality of serially-connected stages, each stage having a plurality of flip-flops and a logic gate combination circuit.
2. Description of the Related Art
A microprocessor such as a pipeline processing apparatus includes a plurality of stages each having a plurality of flip-flops and a logic gate combination circuit. About half of the entire power consumption is dissipated in the flip-flops. Also, about half of that half is dissipated in a clock driving circuit for driving a clock signal supplied to the flip-flops, and the remainder of that half is dissipated in the flip-flops per se and their outputs.
Generally, in a complementary metal oxide semiconductor (CMOS) large scale integrated circuit (LSI), power consumption is mainly dependent upon dynamic power consumption caused by charging and discharging operations performed upon a load capacity, and can be represented by (see Neil Weste et al, "PRINCIPLES OF CMOS VLSI DESIGN", pp. 144-149, 1985) EQU P=C.sub.L V.sub.DD.sup.2 f.sub.p (1)
where
P is a power consumption; PA1 C.sub.L is a load capacity; PA1 V.sub.DD is a power supply voltage; and PA1 f.sub.p is the frequency of a signal.
If the signal is a clock signal whose frequency is f.sub.c, then f.sub.p =f.sub.c. If the signal is an output signal of a flip-flop, then f.sub.p .apprxeq.1/4 f.sub.c in view of the probability of transition of the output signal from high to low and vice versa.
In the pipeline processing apparatus, however, the output signals of the flip-flops are not always changed from high to low or vice versa in accordance with the clock signal. Each output signal of the flip-flops may be changed once for ten clock signals on the average, and in this case, f.sub.p .apprxeq.1/10 f.sub.c. This means about 90% of the power consumption dissipated in the clock driver circuit can be wasted. This will be explained later in detail.
USPTO Backgrounds
USPTO Backgrounds