1. Technical Field
Disclosed herein is a semiconductor memory apparatus, and more particularly, a semiconductor memory apparatus capable of detecting an error in data input/output.
2. Related Art
Referring to FIG. 1, a conventional semiconductor memory apparatus 100 includes a memory cell block 110, a pad 120, a serial-to-parallel converter (SPC) 130, a latch unit 140, a register 150, and a parallel-to-serial converter (PSC) 160.
The number of data input/output pins the pad 120 has depends on the memory capacity, model, etc. In FIG. 1, a pad 120 with eight data input/output pins DQ<0:7> is shown by way of example.
The SPC 130 receives serial data from a graphic processing unit (GPU) 200 of a chipset having a built-in semiconductor memory apparatus 100 through each pin of the pad 120, converts the serial data into parallel data, and outputs the parallel data to the latch unit 140.
The latch unit 140 latches the parallel data output from the SPC 130, and outputs it to a memory cell block 110 through a write global data input/output (WGIO) line.
The register 150 receives the parallel data from the memory cell block 110 and outputs it to the PSC 160 through a read global data input/output (RGIO) line by a first-in, first-out (FIFO) method.
The PSC 160 receives the parallel data from the register 150 converts the parallel data into the serial data, and outputs the serial data to the GPU 200 via the respective pins of the pad 120.
With this configuration, data input/output is performed between the semiconductor memory apparatus 100 and the GPU 200. In this instance, data input/output denotes not only a write operation whereby the data output from the GPU 200 is stored in a predetermined address of a memory cell block 110 via the pad 110, the SPC 130 and the latch unit 140, but also a read operation that the data is output from the memory cell block 110 to the GPU 200 via the register 150, the PSC 160 and the pad 110.
In a conventional semiconductor memory apparatus such as a very high speed graphic memory of more than 2 giga bits per second (GBPS), error probability in the data transmission increases on a data transmission path between the GPU 200 and the semiconductor memory apparatus 100 as the speed of the data transmission becomes higher.
However, a conventional semiconductor memory apparatus has no means to detect or solve an error in the data transmission, which may arise on the data transmission path between the GPU 200 and the semiconductor memory apparatus 100, thereby causing a fatal error.
USPTO Backgrounds
USPTO Backgrounds