1. Field of the Invention
The present invention relates to a method for forming a bit line of a flash device and, more specifically, to a method for forming a bit line of a flash device capable of reducing a crosstalk phenomenon by significantly holding an interval between bit lines.
2. Discussion of Related Art
In a flash device with a level of 100 nanometers (nm) or less, an interval between bit line patterns is gradually decreased as a pattern size of an underlying element is decreased, whereby a RC delay caused due to coupling capacitances has been looming large as a serious problem.
Shown in FIG. 1 is a cross-sectional view illustrating a problem due to a decrease in an interval between bit line patterns of the conventional flash device. Referring to FIG. 1, metal films such as a lower word line W/L, neighbor bit lines B and C, and an upper metal line M2 are coupled with a bit line A to form coupling capacitances. The word line W/L and the bit line A are electrically isolated by a first interlayer insulation film, and a first inter-capacitance C01 is formed therebetween. In addition, the bit line A and the neighbor bit lines B and C are electrically isolated by a second interlayer insulation film, and a second inter-capacitance C11 is formed therebetween. In addition, the bit line A and the upper metal wire M2 are electrically isolated by a third interlayer insulation film, and a third inter-capacitance C12 is formed therebetween.
The calculation of coupling capacitances associated with the bit line A using a SAKURAI Model is as follows: “D” indicates an interval between the word line W/L and the bit line B/L; “T” indicates a height of the bit line B/L; “W” indicates a thickness of the bit line B/L; “S” indicates an interval between the neighbor bit lines B/L; “H” indicates an interval between the bit line B/L and the upper metal wire M2; “C01” indicates a first inter-capacitance; “C11” indicates a second inter-capacitance; and, “C12” indicates a third inter-capacitance.
The first to third inter-capacitances according to the SAKURAI Model are as follows:C01/εox=1.15×(W/D)+2.80(T/D)×0.222−0.07(T/D)×0.222×(S/D)×1.34C11/εox=(0.03×(W/D)+0.83(T/D))×(S/D)−1.34C12/εox=1.15×(W/H)+2.80(T/D)×0.222−0.07(T/D)×0.222×(S/H)×1.34
The total capacitance C generated at the bit lines due to the first to the third inter-capacitances becomes as follows:C=C01+2C11+C12.
As shown in the aforementioned equations, it is noted that in the coupling capacitances, the thickness W of the bit line pattern and the interval S between the bit lines are important components. Namely, in order to reduce the bit line capacitances, it is efficient to decrease the thickness W of the bit line and increase the interval S between the neighbor bit lines. However, if the thickness W of the bit line and the interval S between the neighbor bit lines are excessively decreased, the bit line resistance is increased. Therefore, it is necessary to find optimum conditions for considering two components, that is, the thickness W of the bit line and the interval S between the neighbor bit lines. However, although the optimum conditions are taken by using the aforementioned equation and simulation, it is difficult to actually apply the optimum conditions to the bit line forming process.
Shown in FIG. 2 is a layout diagram illustrating a problem due to the conventional method of forming a bit line of a flash device. Referring to FIG. 2, the bit line B/L is formed vertically with respect to the lower word line W/L. In this figure, a dot line indicates a final bit line pattern, and a solid line indicates a bit line pattern formed using conventional processes. As shown in FIG. 2, S10 indicates a target interval between the bit lines, and S20 indicates an interval between the bit lines formed using conventional processes. In other words, the target interval S10 between the bit lines becomes larger than the interval S20 between the bit lines. Therefore, according to the aforementioned equation, the capacitance C11 becomes large and the total capacitance of the bit lines B/L is increased, whereby a serious problem caused by RC delay is generated.
Shown in FIGS. 3A to 3C are cross-sectional views taken by a II–II′ line in FIG. 2. Referring to FIG. 3A to 3C, a barrier film 14 and an interlayer insulation film 16 are sequentially formed on the semiconductor substrate 10, on which a word line (not shown) and a bit line contact plug 12 are formed. A bit line trench 20 is formed by etching the interlayer insulation film 16 and the barrier film 14 using a photosensitive film pattern 18. A bit line 30 is formed by, for example, carrying out a planarization process using a chemical and mechanical polishing process after burying metal in the bit line trench 20. However, it is difficult to hold the interval S10 between the target bit lines 30 because a part of the photosensitive film pattern 18 is also etched in the etching process for forming the bit line trench 20. Furthermore, there is a problem that the interval S10 between the bit lines 30 is decreased because a part of the inter insulation film 16 also is etched in a cleaning process prior to the process of burying metal. A dot line of FIG. 3B indicates a shape of the target bit line trench, and a solid line of FIG. 3B indicates a shape of the bit line trench formed actually after carrying out the etching process. As shown in these figures, it is difficult to set the interval between the bit lines, that is, difference between S10 and S20 to target critical dimensions. Generally, in the etching process for forming the bit line trench 20, a thickness of about 25 nm of the interlayer insulation film 16 is lost, and in the cleaning process prior to the process of burying metal, thickness of about 30 nm of the interlayer insulation film 16 is lost.
USPTO Backgrounds
USPTO Backgrounds