The present invention relates to a semiconductor integrated circuit device for driving an external load such as laser diode, and more specifically relates to a semiconductor integrated circuit device of the GaAs digital IC type having a GaAs substrate formed thereon with a plurality of Schottky junction type field effect transistors.
With the development of high speed digital signal processing technology including optical communication technology, the GaAs digital IC becomes more important for use as a semiconductor laser driver (hereinafter, referred to as "laser driver") for driving directly a semiconductor laser at an ultra high speed (c.f. Japanese Electrocommunication Society, technology research report SSD-85-140).
Hereinafter, the conventional laser driver will be explained in conjunction with the attached drawings. FIG. 1 shows a driver described in the above-mentioned document, constructed of field effect transistors (FETs) and diodes which are composed of Schottky junction type field effect transistors and diodes. These FETs and diodes are formed on a GaAs substrate together with other components.
Referring to FIG. 1, the laser driver is provided with an earth terminal 31 and a power supply terminal 32. Normally, a power supply voltage of -5.2V is applied to the power supply terminal 32 with respect to the earth terminal 31. An input signal is inputted from an input terminal 33 through a level shifting circuit comprised of FET Q.sub.41, level shifting diode D.sub.41 and current supplying FET Q.sub.43 into a gate electrode of FET Q.sub.46 which constitutes a part of output differentially operating circuit. Further, the laser driver is provided with a reference terminal 34 receptive of a reference signal such as an opposite phase signal or a reference voltage of -1.3V. The reference signal received at the reference terminal 34 is inputted through another level shifting circuit composed of FET Q.sub.42, level shifting diode D.sub.42 and current supplying FET Q.sub.44 into a gate electrode of FET Q.sub.45 which is contained in the output differentially operating circuit.
The output differentially operating circuit is comprised of the FET Q.sub.45, a FET Q.sub.46 and a current supplying FET Q.sub.47, and carries out switching of an output current at ultra high speed. The gate electrode of FET Q.sub.47 is connected to a switching current control terminal 35, and the drain terminal of FET Q.sub.46 is connected to an output terminal 37. Further, an FET Q.sub.48 has a function of supplying an offset current, and the gate electrode thereof is connected to an offset current control terminal 36 and the drain terminal thereof is connected to the output terminal 37.
In the prior art laser driver having the above-described structure, the drain current flowing through the FET Q.sub.48 is applied to a load in the form of a laser diode 38 as an offset current I.sub.o, and the drain current flowing through the FET Q.sub.47 included in the output differentially operating circuit is also applied to the load as a switching current I.sub.s. The offset current I.sub.o can be controlled by applying externally a control voltage to the offset current control terminal 36, and the switching current I.sub.s can be controlled by applying externally another control voltage to the switching current control terminal 35.
In general, a needed maximum value of the switching current I.sub.s is about 50 mA, and a needed variable range of the offset current I.sub.o is from 0 mA to 100 mA. The set value of offset current I.sub.o is determined according to a threshold current of the laser diode 38.
FIG. 2 shows the relation between the above-described offset current I.sub.o and switching current I.sub.s. In FIG. 2, a waveform a represents a time-responsive waveform of the output current where the magnitude of offset current I.sub.o is indicated by b, and the amplitude of switching current I.sub.s is indicated by c.
However, the above-described prior art laser driver has the following drawbacks. As apparent from FIG. 2, when the set value of offset current I.sub.o (indicated by b) is zero, the minimum magnitude of the output current becomes zero. In such a case, as apparent from FIG. 1, a voltage V.sub.DS between the drain and source electrodes of FET Q.sub.48 which has the function of supplying the offset current is held about 5.2V. Further, in a similar manner, when the offset current I.sub.o is set to a zero value, a voltage V.sub.GS between the gate and source electrodes of FET Q.sub.48 must satisfy the following relation (1) such that the value of V.sub.GS exceeds the threshold value V.sub.th of the FET Q.sub.48. EQU V.sub.GS &lt;V.sub.th ( 1)
Normally, the threshold value V.sub.th is set within the range from about -1.0V to about 0.5V for the high speed operation. On the other hand, a high performance FET is utilized as FET Q.sub.48 in the laser driver so as to obtain the high speed operation characteristic. Such a high performance FET has a reverse withstanding voltage of about -6V to -5V between the gate and drain electrodes.
In this connection, the voltage V.sub.GD applied between the gate and drain electrodes of FET Q.sub.48 used in the prior art shown in FIG. 3 is represented according to the following relation (2) by using the relation (1). EQU V.sub.GD =V.sub.GS -V.sub.DS &lt;V.sub.th -V.sub.DS (2)
As described above, since the value of V.sub.th is set to -1.0V to -0.5V and the maximum value of V.sub.DS is 5.2V, the value of V.sub.GD is represented by: EQU V.sub.GD &lt;-6.7V to -5.7V
Consequently, the maximum value of V.sub.GD can be very close to -6.7V through -5.7V and therefore is comparable to the reverse withstanding voltage of -6V through -5V in the offset current supplying FET Q.sub.48 used in the prior art laser driver of FIG. 1. For this reason, when carrying out the high speed operation, the FET Q.sub.48 is actually operated under the state close to the limit capacity, thereby causing reliability problems such as deterioration of FET Q.sub.48.
In order to eliminate the drawbacks of the first prior art laser driver, the inventor devised a laser driver such as shown in FIG. 3. In the figure, the same components are designated by the same reference numerals as in FIG. 1, and therefore the detailed description thereof is omitted.
Referring to FIG. 3, an offset current supplying FET Q.sub.49 and voltage dividing FET Q.sub.50 are connected between the power supply terminal 32 and output terminal 37. Namely, the source electrode of FET Q.sub.49 is connected to the power supply terminal 32, the drain electrode of FET Q.sub.49 is connected to the source terminal of FET Q.sub.50, and the drain electrode of FET Q.sub.50 is connected to the output terminal 37. Further, the gate electrode of FET Q.sub.49 is connected to the offset current control terminal 36.
A pair of voltage dividing resistors R.sub.41 and R.sub.42 are series-connected between the earth terminal 31 and power supply terminal 32, and the junction point therebetween is connected to the gate electrode of FET Q.sub.50.
In this devised structure, the FETs Q.sub.49 and Q.sub.50 are formed to have the same structure and parameters such as pattern dimensions of parts and threshold voltage. Further, the voltage dividing resistors R.sub.41 and R.sub.42 are formed to have the same parameters such as resistance. For this reason, a potential at the gate electrode of FET Q.sub.50 is set to -2.6V which is a half of the power supply voltage -5.2V applied between the earth terminal 31 and power supply terminal 32. In addition, the resistance of the resistors R.sub.41 and R.sub.42 is set to about 1k.OMEGA., respectively, so as to avoid the increase in current consumption. In this case, the total power consumption of about 13.5 mW is consumed by the resistors R.sub.41 and R.sub.42 , and such a value can be negligible in actual use.
As described above, in FIG. 3, the FETs Q.sub.49 and Q.sub.50 have the identical structure and the gate potential of FET Q.sub.50 is fixed to -2.6V. For this reason, when both of the offset current I.sub.o and switching current I.sub.s become zero, a voltage V.sub.DS between the drain and source electrodes of FET Q.sub.49 is held 2.6V+V.sub.th, and another voltage V.sub.DS between the drain and source electrodes of FET Q.sub.50 is held 2.6V-V.sub.th where V.sub.th (V) is a threshold voltage of FET Q.sub.49. Further, a voltage V.sub.GD between the gate and drain electrodes of FET Q.sub.50 is held -2.6V and another V.sub.GD between the gate and drain electrodes of FET Q.sub.49 is held about 2V.sub.th -2.6V. In this case, the value of V.sub.GD of FET Q.sub.49 is held in the range from -4.6V to -3.5V when the value of V.sub.th is set to the range between -1V and -0.5V. Accordingly, in FIG. 3, since a load voltage exceeding the reverse withstanding voltage from -6V to -5V between the gate and drain electrodes cannot be applied to the respective FETs Q.sub.49 and Q.sub.50, a laser driver having high reliability can be obtained.
However, in the laser driver of FIG. 3, the additional function to vary the offset current I.sub.o within the range from 0 mA to 100 mA is needed in accordance with the threshold current value of laser diode 38 to be driven as described above. On the other hand, with the need for higher speed processing in a general digital IC including GaAs digital IC, a new problem relating to the interface emerges, and therefore the additional function is needed to vary the offset voltage of output signal.
In this regard, when providing the function to change the offset current (or offset voltage) over a wide range in the circuit shown in FIG. 3, there is caused a problem that a waveform of high frequency modulation is deteriorated.
Hereinafter, this problem will be explained. As described already, the variable range from about 0V to 100 mA is needed for the offset current I.sub.o in the laser driver. In this case, the respective gate electrode of FETs Q.sub.49 and Q.sub.50 must have the gate width of about 400 .mu.m through 600 .mu.m in order to flow a relatively large current through the FETs Q.sub.49 and Q.sub.50. In addition, when controlling the offset current I.sub.o by applying an external control voltage to the offset current control terminal 36, the respective voltage V.sub.GS between the gate and source electrodes of FETs Q.sub.49 and Q.sub.50 is set to 0.4V through 0.5V.
In this case, a parastic capacitor C.sub.gd between the gate and drain electrodes of FET Q.sub.50 has a capacitance more or less exceeding 0.3 pF through 0.5 pF due to the great width of the gate electrode and the forward biasing of 0.4V through 0.5V between the gate and source electrodes. Further, by the combination of capacitance of capacitor C.sub.gd of FET Q.sub.50 and resistances of voltage dividing resistors R.sub.41 and R.sub.42, the transition characteristic of output current outputted from the output terminal should have long time-dependent component.
Since the resistors R.sub.41 and R.sub.42 have the resistance of 1k.OMEGA., respectively, and the capacitor C.sub.gd has the capacitance of 0.3 pF through 0.5 pF, a time constant defined as the product of the parallel composite resistance of resistors R.sub.41 and R.sub.42 and the capacitance of capacitor C.sub.gd is calculated to 150 psec through 250 psec. Such order of time constant cannot be neglected in ultra high speed modulation characteristic on the order of Gb/sec. Such a situation will be explained with reference to FIG. 4.
Referring to FIG. 4, the level of offset current I.sub.o is indicated by d when I.sub.o =0, the amplitude of switching current I.sub.s is indicated by e when I.sub.o =0, and the waveform of switching current I.sub.s is indicated by f when I.sub.o =0. In case of I.sub.o =0, the respective voltage V.sub.GS of FETs Q.sub.49 and Q.sub.50 is reverse biased as V.sub.GS &lt;V.sub.th so that the above described deterioration of high frequency modulating signal waveform due to the capacitor C.sub.gd is not remarkable.
On the other hand, the DC level of offset current I.sub.o is indicated by g when the respective FETs Q.sub.49 and Q.sub.50 are forward biased at 0.4V through 0.5V between the gate and source electrodes thereof. The level of offset current I.sub.o is set to a great value of 80 mA through 100 mA, and the amplitude of switching current I.sub.s is indicated by h and the output waveform of switching current I.sub.s is indicated by i. In this case, due to the affect of time constant defined by the product of the parallel composite resistance of resistors R.sub.41 and R.sub.42 and the capacitance of capacitor C.sub.gd, the peak level of output current waveform i cannot reach the level of offset current I.sub.o indicated by g. Accordingly, the high level of envelope of output current waveform is different from the DC level of offset current I.sub.o.
Such deterioration of high frequency modulating signal waveform becomes remarkable when the modulating or switching speed exceeds about 1 Gb/sec, thereby causing practically difficult problem. In this case, it is apparent that the maximum operating speed is affected.
By reducing the resistances of voltage dividing resistors R.sub.41 and R.sub.42, the above-mentioned time constant could be reduced as desired. For example, if the resistances of resistors R.sub.41 and R.sub.42 were set to 100 .OMEGA., respectively, the above-mentioned time constant could be 15 psec through 25 psec and the problem of waveform deterioration could be avoided. However, in such a case, the total electric power consumed in the resistors R.sub.41 and R.sub.42 could reach 140 mW through 150 mW to cause practical problem.
USPTO Backgrounds
USPTO Backgrounds