1. Field of the Invention
The present invention relates to an interconnection such as a line and/or a via in a semiconductor device and a method for forming the interconnection, and more particularly, to a single or dual damascene interconnection which is formed in a low dielectric constant layer and coated with a capping layer and a method for forming the same.
2. Description of the Related Art
In order to obtain high-speed semiconductor devices, it is necessary to reduce the thickness of a gate oxide layer and the length of a gate. However, RC (resistance capacitance) delay that is proportion to the resistance of an interconnection and the capacitance of an interlayer insulating film has a negative influence on the speeds of semiconductor devices. Thus, various attempts have been made to reduce the RC delay by using a low resistance interconnection and a low dielectric constant interlayer insulating film.
Conventionally, aluminum (Al) was widely used as an interconnection material. However, recently, copper (Cu) has been gradually considered to be more useful for integrated circuits. The resistivity of copper (Cu) is half the resistivity of aluminum (Al), and thus it is possible to increase the speed of signal transmission with copper (Cu) of a small width. Besides, since copper (Cu) has a high resistance to electro-migration, the reliability of semiconductor devices can be improved. Moreover, copper (Cu) shows low power consumption and is cheaper than aluminum (Al).
One drawback to using copper (Cu), however, is that copper (Cu) is difficult to etch and pattern after a desired interconnection. Therefore, copper interconnections are formed by a damascene process. The damascene process comprises the following general steps. An opening in a shape of the desired interconnection is formed in an interlayer insulating film. Then, a planarization process is performed after a copper layer is formed to fill the opening. Generally, chemical mechanical polishing (CMP) is used as the planarization process. In particular, a dual damascene process is used to form the copper (Cu) interconnections. The dual damascene process comprises the following steps. A via trench and a wiring trench are formed such that the wiring trench overlaps with an upper portion of the via trench. Then, the planarization process is performed after a copper layer is formed to fill both the via trench and the wiring trench. As already known to those skilled in this field, the copper layer must be formed twice to separately form a via and a wiring line. Each process for forming the via and the wiring line is referred to as a single damascene process.
FIG. 1 is a cross-sectional diagram illustrating a conventional single damascene interconnection. Referring to FIG. 1, a damascene interconnection 7 fills an opening 3 in an interlayer insulating film 1 and is surrounded by a barrier metal layer 5. A capping layer 9 such as a silicon nitride layer covers the interlayer insulating film 1 and the damascene interconnection 7. The capping layer 9 is deposited on the damascene interconnection 7 after CMP is performed during the damascene process. The capping layer 9 should effectively prevent copper (Cu) from diffusing into the interlayer insulating film 1 and has a high etching selectivity to other interlayer insulating films to be formed on the damascene interconnection 7. Since a material of a low dielectric constant, e.g., 2-4, is recently used as an interlayer insulating film, the need for a substitute for silicon nitride becomes apparent. Actually, silicon nitride has been typically used as a capping layer, but it has a high dielectric constant, e.g., 6-8, and a low etching selectivity to a low dielectric constant layer. Silicon carbide has a low dielectric constant, e.g., 4-5, and a high etching selectivity to the low dielectric constant layer. Therefore, silicon carbide is an appropriate substitute for silicon nitride as the capping layer. However, if silicon carbide is used as the capping layer, leakages in the interface between planarized interlayer insulating film and the capping layer become more difficult to suppress.
USPTO Backgrounds
USPTO Backgrounds