1. Field of the Invention
The present invention relates to a nonvolatile memory. More particularly, the present invention is directed to a silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) memory having an improved storage capacity.
2. Description of the Related Art
FIG. 1 illustrates a sectional view of a conventional flash electrically erasable programmable read only memory (EEPROM) cell. The flash EEPROM, as nonvolatile memory, stores data even in a power off state.
Referring to FIG. 1, a gate electrode 17 is located on a substrate 11 having a source electrode 13 and a drain electrode 15. A gate oxide 21, a floating gate 23, and an insulating layer 25 are sequentially stacked between the gate electrode 17 and the substrate 11.
In general, a flash memory is programmed using hot carriers that are injected from a portion of the substrate 11, in particular, the channel of electrons that is formed between the source electrode 13 and the drain electrode 15. A hot carrier injection mechanism includes converting the electrons flowing through the channel from the source to the drain into energetic electrons, which are then injected into the floating gate 23, under proper voltage conditions. The source electrode 13 and a corresponding portion of the substrate 11 are grounded. A relatively high positive voltage is applied to the gate electrode 17 in order to induce an electric field that attracts the electrons. In addition, a proper positive voltage is applied to the drain electrode 15 to generate hot carriers (electrons). The hot carriers are injected into the floating gate 23 by the electric field of the gate electrode 17. When a sufficient amount of negative charge is accumulated in the floating gate 23, the negative potential of the floating gate 23 is increased, causing the net gate voltage to go below the threshold voltage of a field effect transistor (FET), in order to obstruct the electrons from flowing through the channel. The amount of read current is used as a factor to determine whether the flash memory is programmed. The discharge of the floating gate is referred to as “erasing.” Here, erasing is performed by a tunneling mechanism between the floating gate and the substrate. An erasing operation of data from a flash memory is performed by applying a high positive voltage to the source electrode and grounding the gate electrode and the substrate, while floating the drain electrode of a memory cell.
However, since a flash memory has a disadvantages of low retention, a silicon/oxide/nitride/oxide/silicon (SONOS) memory device may only be used for increasing information storage capacity and improving process performance.
FIG. 2 illustrates a sectional view of a conventional SONOS memory cell. Referring to FIG. 2, a gate electrode 37 is formed on a substrate 31 having a source electrode 33 and a drain electrode 35, and silicon oxide layers 41 and 45 as insulating layers are formed between the substrate 31 and the gate electrode 37. In addition, a non-conductive dielectric layer 43 for trapping electrons is interposed between the silicon oxide layers 41 and 45.
When a SONOS memory having two bits per cell is operated, two bits, i.e., a right bit and a left bit, of the SONOS memory cell use a conventional programming method using hot carriers (electrons); however, each bit reads data at a relatively low gate voltage in different directions. For example, the right bit of the SONOS memory is programmed by applying a programming voltage to the gate electrode or to the drain electrode, while grounding or applying a low voltage to the source electrode. Accordingly, hot carriers are sufficiently accelerated and injected into a region of the non-conductive dielectric layer near the drain electrode. However, the SONOS memory is read by applying a reading voltage to the gate electrode and the source electrode in an opposite direction while grounding or applying a low voltage to the drain electrode. Accordingly, the left bit is programmed and read by exchanging the voltages of the source electrode and the drain electrode. When one bit is programmed, the information in the other bit is maintained.
The SONOS memory reads data in a reverse direction using a relatively low level of gate voltage so that the drop of the potential across the channel is significantly reduced. Accordingly, the effects of the charges trapped in a local trapping region are increased to enable the programming of the SONOS memory at a high rate. In addition, the SONOS memory is able to improve the erasing mechanism by applying a proper erasing voltage to the gate electrode and the drain electrode of the right bit and the source electrode of the left bit. Furthermore, the SONOS memory can improve the lifespan of the device by preventing the SONOS memory from being worn down in a cycling operation.
However, regardless of the advantages of the SONOS memory, a memory that has a larger storage capacity than the conventional SONOS memory and that can be programmed at a higher rate than the conventional SONOS memory is required.
USPTO Backgrounds
USPTO Backgrounds