1. Field of the Invention
This invention relates to semiconductor manufacturing and, in one aspect, to a method and apparatus for controlling a thickness of a deposited layer in a semiconductor manufacturing operation.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher-quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. For example, in conventional semiconductor wafer manufacturing operations, thicknesses of deposited conductive layers (e.g., copper leads, lines, interconnects, contacts, vias, plugs, and the like) either go unmonitored or are checked on a lot-by-lot basis. In general, such conductive layers undergo a subsequent chemical mechanical planarization (CMP) step, wherein the exposed surface of the conductive layer is planarized and the thickness of the conductive layer is brought into tolerance. If the thickness of a conductive layer is below the tolerance range, there may be insufficient material within the conductive layer for the conductive layer to properly conduct electrons. If the thickness of the conductive layer is above the tolerance range, additional time and materials may be required in the CMP step to remove the excess material. If thickness of conductive layers are checked on a lot-by-lot basis by measuring one or more wafers within the lot, whether they be production wafers or expendable qualification wafers, adjustments to the deposition process can generally be made no more frequently than between lots.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
USPTO Backgrounds
USPTO Backgrounds