Voltage regulator has been applied in various electronic products to provide stable supply voltages for load on the voltage regulator. FIG. 1 schematically shows a typical voltage regulator 10 operated with constant on-time duty-cycle, which comprises a pair of high side MOS transistor 12 and low side MOS transistor 14 coupled between input voltage VIN and ground GND, inductor 18 coupled between the phase node 16 between the MOS transistors 12 and 14 and output VOUT of the voltage regulator 10, output capacitor COUT coupled between the output VOUT and ground GND and having equivalent series resistance (ESR) RESR, resistors R1 and R2 coupled in series between the output VOUT and ground GND to divide the output voltage VOUT to generate feedback signal VFB, error amplifier 20 to compare the feedback signal VFB with reference voltage VREF to generate error signal PM for constant on-time circuit 22 to generate a pulse width modulation (PWM) signal PWM accordingly, to switch the MOS transistors 12 and 14 by driver 24 to thereby produce an output current IOUT flowing through the inductor 18 to charge the output capacitor COUT to produce the output voltage VOUT supplied to load 26.
In the voltage regulator 10, the PWM signal has a constant on-time duty-cycle. However, the switching frequency of the PWM signal is variable. FIG. 2 shows waveforms of the output voltage VOUT and PWM signal in the voltage regulator 10, in which waveform 50 represents the output voltage VOUT and waveform 52 represents the PWM signal. As shown at time T in FIG. 2, when the load 26 changes from light to heavy, the output voltage VOUT drops down instantly, causing a greater difference between the feedback signal VFB and reference voltage VREF, which reflects on the error signal PM, having the constant on-time circuit 22 to increase the switching frequency of the PWM signal. As a result, the high side MOS transistor 12 turns on more frequently, and thereby the output voltage VOUT recovers back to the original level gradually.
In response to load transient, it is the switching frequency, but not the on-time duty-cycle, of the PWM signal being varied in the voltage regulator 10, and this constant on-time duty-cycle operation is easily to cause the output voltage VOUT to overshoot, as shown by the dotted curve 54 in FIG. 2. Therefore, the system becomes not stable, and the output capacitor COUT is required to have larger capacitance, resulting in higher cost and poor conversion efficiency.
USPTO Backgrounds
USPTO Backgrounds