The present invention relates to testing delay paths in integrated circuits. More specifically, a low overhead storage element for delay testing is described.
Manufacturing defects during the fabrication of integrated circuits (ICs) can introduce faults that will cause circuit delays to exceed permissible limits. Such failures, called delay faults, if not detected during IC test, can cause systems incorporating such ICs to fail during system operation. It is therefore desirable to detect delay faults during IC testing.
Automatic test pattern generation (ATPG) for delay testing requires the generation of a sequence of patterns of control and input signals known as test vectors. The test vectors are scanned into a series of storage elements in an integrated circuit using well known scan testing techniques, thereby causing signal transitions on the inputs of signal paths for the purpose of measuring the time required for the transition to propagate through the signal paths. In the past, such signal transitions were generated by a bistable multivibrator or a flip-flop, such as flip-flop 10 shown in FIG. 1. During regular system operation, scan-in and scanout clock signal lines, 12 and 14 respectively, are inactive and the double-strobe and master-load control signal lines, 16 and 18 respectively, are in their deasserted states. This allows flip-flop 10 to operate as a master/slave flip-flop in which master-latch 20 updates with data on input terminal 22 while system clock line 24 is at the logic "0" level, and master-latch 20 is copied into slave-latch 26 with the rising edge of the clock signal. To generate the desired signal transition at output terminal 28 of flip-flop 10, both the double-strobe and master-load control signal lines 16 and 18 must be asserted. Scan-in clock line 12 and scan-out clock line 14 are then used to load the value on scan-in input terminal 29 into both master-latch 20 and slave-latch 26. By deasserting master-load control signal line 18, a different value may then be loaded into slave-latch 26. By then asserting a pulse on clock signal line 24, the contents of master-latch 20 are moved to slave-latch 26, causing the desired signal transition in synchronism with the clock signal transition.
One of the limitations of the above-described flip-flop resides in the fact that an extra holding latch 27 must be incorporated into the flip-flop in order to implement standard scan testing. Therefore, each flip-flop results in a considerable amount of pin-out and die area overhead. For example, the above-described flip-flop requires six additional signal lines and five additional gates. (This is based on the assumption that four transistors are equivalent to one gate). The six additional signals include the scan-in input, the scan-out output, the scan-in clock, the scan-out clock, the double-strobe enable input, and the master-load enable. The additional gates include the two inverters of the scan-out latch as one gate, the two switches driven by the scan-out clock as one gate, the two switches driven by the scan-in clock as one gate, the two switches driven by the master-load enable as one gate, and the OR gate.
Because of the need to reduce the size and pin-out of integrated circuits while, at the same time, maintaining or increasing a sufficient level of fault coverage, there is a need for a storage element for delay testing with a reduced pin-out overhead.
USPTO Backgrounds
USPTO Backgrounds