Field of the Invention
The invention relates to a method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. Such semiconductor components contain a semiconductor substrate of a first conductivity type that is covered by a gate insulator layer. The essential method steps exhibited by the known methods are the production of a well of a second conductivity type in the semiconductor substrate and the production of a contact region of the first conductivity type in the well.
The smallest possible on resistances are striven for when fabricating MIS power transistors. On resistances of less than 3 m.OMEGA. (in the TO220 housing) have already been achieved for planar MIS power transistors having reverse voltages of up to 100V. The channel resistance, the JFET resistance and the epitaxial resistance, i.e. the resistance of the semiconductor substrate through which the current flows after the channel to the drain terminal, each make up approximately one third of the on resistance. Since the epitaxial resistance cannot be influenced very much, it is necessary to reduce the channel resistance and the JFET resistance in order to reduce the on resistance.
In addition to reducing the on resistance, a high cell density and therefore a small cell size are striven for for components for high switching capacities. "Self-aligning" techniques are used nowadays for this purpose during the fabrication of the component. In this case, heavily doped polysilicon is used as the gate material and as a mask for the doping of source and drain. The gate serves as a mask for the doping, and the source and drain terminate exactly under the edge of the gate.
The actual fabrication of the cell with a small size is then carried out according to one of three techniques essentially used nowadays. In the first technique, a self-aligned channel is fabricated by diffusion after implantation via the edge of the polysilicon gate and an aligned contact hole is then produced on the semiconductor. The corresponding transistors are known as DMOS or DIMOS and SIPMOS transistors.
Since the threshold voltage, channel length and penetration depth mutually influence one another, however, in the case of the diffusion MOS transistors, the parameters cannot be optimized individually. In addition, the charge carrier concentration decreases in the channel between the source and the drain in the transistors fabricated by diffusion. However, the maximum concentration of the charge carriers (at the source) determines, for its part, the threshold voltage of the transistor, with the result that the channel length cannot be reduced to significantly below 1 .mu.m.
In a second technique, a double diffused (DMOS) FET is fabricated and a self-aligned contact hole is provided with the aid of the known "spacer" technology. The self-aligned contact hole fabricated using spacer technology enables the spacing of the contact hole from the gate to be reduced to approximately 0.5 .mu.m without a high requirement being made on the alignment. This results in a geometrical length from the contact hole up to the end of the channel at the drain of approximately 1.5 .mu.m.
A further reduction in the channel length to below 1 .mu.m is not possible using this method.
Finally, in a third method according to the prior art, the channel and the contact hole are produced by traditional methods (without self-alignment) by aligning the corresponding masks with one another.
USPTO Backgrounds
USPTO Backgrounds