1. Field of the Invention
The present invention relates to a test handler, and more particularly to an apparatus and method for loading semiconductor devices of user trays onto a test tray.
2. Description of the Related Art
In general, a test handler supports a test of semiconductor devices manufactured through a predetermined manufacturing process, sorts the semiconductor devices into different levels according to the test results, and loads the semiconductor devices onto user trays. The test handler has been disclosed in many publication documents.
FIG. 1 is a schematic perspective view illustrating a conventional test handler 100. The major parts of the conventional test handler 100 will now be briefly explained with reference to FIG. 1.
The conventional test handler 100 includes a loading unit 110, a soak chamber 120, a test chamber 130, a de-soak chamber 140, and an unloading unit 150.
The loading unit 110 picks semiconductor devices loaded on user trays 10a and 10b, adjusts a front/rear pitch and a right/left pitch between the semiconductor devices, aligns the semiconductor devices at an alignment block 112, and loads the semiconductor devices onto a test tray 11.
The soak chamber 120 has a temperature environment for preheating or precooling the semiconductor devices loaded on the test tray 11, and receives the test tray 11 on which the semiconductor devices have been loaded by the loading unit 110. The test tray 11 entering the soak chamber 120 is translated toward the test chamber 130 in the vertical posture. During the translation, the semiconductor devices loaded on the test tray 11 are sufficiently preheated or precooled.
The test chamber 130, installed with the test handler, includes a tester which tests the semiconductor devices loaded on two test trays 11 supplied from the soak chamber 120. For this, the test chamber 130 has a temperature environment for testing the semiconductor devices.
The de-soak chamber (or restoring chamber) 140 restores the heated or cooled semiconductor devices to room temperature.
The unloading unit 150 sorts the semiconductor devices transferred from the de-soak chamber 140 into different levels, and unloads (transfers and loads) the semiconductor devices onto user trays 10c. 
Here, since the user trays load the semiconductor devices for keeping, the front/rear pitch and the right/left pitch between the semiconductor devices must be minimized to keep as many semiconductor devices as possible. However, the semiconductor devices loaded on the test tray must have appropriate front/rear pitch and right/left pitch for test. As shown in the user trays 10a and 10b and the test tray 11 of FIG. 2, the front/rear pitch b′ and the right/left pitch a′ between the semiconductor devices loaded on the test tray 11 must be greater than the front/rear pitch b and the right/left pitch a between the semiconductor devices loaded on the user trays 10a and 10b. 
The loading method of the test handler 100 of FIG. 1 will now be described in more detail with reference to FIG. 2, a schematic plan view illustrating the major elements of the test handler 100 of FIG. 1.
As shown in FIG. 2, the loading unit 110 includes a picking apparatus 110a (called a pick and place apparatus or a loader hand) that has 8 pickers 110a-1 in its front and rear rows, respectively, to pick up 16 semiconductor devices at a time. The picking apparatus 110a carries out the loading operation. As described above, in order to load the semiconductor devices of the user tray 10a or 10b onto the test tray 11, it is necessary to adjust the different pitches between the semiconductor devices. Therefore, the front/rear pitch and the right/left pitch between the pickers 110a-1 must be adjustable. That is, when the picking apparatus 110a picks the semiconductor devices from the user tray 10a or 10b, the front/rear pitch and the right/left pitch between the pickers 110a-1 must be minimized to the pitches between the semiconductor devices loaded onto the user tray 10a or 10b. And, when the picking apparatus 110a loads the semiconductor devices onto the test tray 11, the front/rear pitch and the right/left pitch between the pickers 110a-1 must be maximized. Accordingly, the picking apparatus 110a needs an apparatus that adjusts the pitch between the front and the rear rows, and an apparatus that adjusts the pitch between the pickers 110a-1 arranged in each row.
The picking apparatus 110a picks the 16 semiconductor devices from the user tray 10a or 10b, widens the pitch between the front and the rear rows and the pitch between the pickers 110a-1 arranged in each row, aligns the semiconductor devices at the alignment block 112, and loads the semiconductor devices onto the test tray 11.
However, since the picking apparatus 110a requires the apparatus that adjusts the pitch between the front row and the rear row and the apparatus that adjusts the pitch between the pickers 110a-1 arranged in each row, such a configuration makes it complicated and increases its weight. Accordingly, it is disadvantageous in that the loading time increases because inertia caused by its heavy weight decreases its moving speed.
Furthermore, when the picking apparatus 110a picks the semiconductor devices from the user tray 10a or 10b and adjusts the front/rear pitch and the right/left pitch, the semiconductor devices picked by the pickers 110a-1 becomes misaligned. The semiconductor devices are realigned at the alignment block 112 and loaded onto the test tray 11. As a result, the entire loading time increases due to the realignment of the semiconductor devices using the alignment block 112.
USPTO Backgrounds
USPTO Backgrounds