As portable electronic devices become smaller, the dimensions of semiconductor chip packages must be reduced. In order to reduce the dimensions of the semiconductor chip packages, various packaging technologies have been developed. In addition, in order to implement high-performance requirements for the semiconductor chip packages, it may be required to form bonding pads in contact with solder balls or bonding wires at desired positions, regardless of the chip pad locations formed on a semiconductor chip. In this case, the bonding pads are electrically connected to the chip pads through redistributed metal interconnections.
A semiconductor chip having redistributed metal interconnections is disclosed in U.S. Pat. No. 6,211,576 B1 to Shimizu, et al., entitled “Semiconductor Device”. According to Shimizu, et al., a power wiring section, a ground wiring section, and a signal wiring section are provided at the same level, and the power wiring section or the ground wiring section is formed adjacent to both sides of at least one portion of the signal wiring section.
USPTO Backgrounds
USPTO Backgrounds