Fabricating microelectronic devices typically includes forming features on selected layers of a semiconductor wafer using photolithography. Individual features are often formed by using a photolithographic reticle or mask to project a selected pattern onto a layer of photoreactive material, and then removing selected portions of the pattern during subsequent processing steps. Photolithographic masks may be used in the fabrication of virtually any type of microelectronic device, including memory devices (DRAMs, SLDRAMs, RDRAMs, etc.), field emission displays, processor chips, and many other types of semiconductor devices.
FIG. 1 shows a typical apparatus 10 for patterning semiconductor wafers using photolithography. The apparatus 10 includes a light source 12 that directs light 13 through a condenser 14 onto a reticle 18. The condenser 14 collimates and filters the light to a desired wavelength. The light passes through the reticle 18 and then through a lens system 20 which focuses the light onto a semiconductor wafer 24 that has been coated with a layer of photoreactive material (or photoresist) 26. The wafer 24 is supported on a moveable stage 30.
FIG. 2 shows a representative light intensity pattern 32 on the photoreactive layer 26 of FIG. 1. As is well known in the art, the reticle 18 creates the light intensity pattern 32 of relatively light and dark areas 34, 36 on an exposed portion 28 corresponding to the features that are to be formed in the photoreactive layer 26. After each portion 28 is exposed, the position of the wafer 24 is incrementally advanced by “stepping” or moving the stage 30 supporting the wafer 24. Another portion 28 is then exposed having an identical pattern to the first exposed portion 28, and the stage 30 is incrementally advanced until all of the wafer 24 has been exposed.
If the photoreactive layer 26 is a “negative resist” layer, the dark or shadow pattern produced by the reticle 18 corresponds to the negative of the features that are to be formed in the resist 26. Conversely, for a “positive resist” layer (FIG. 2), the dark pattern corresponds directly to the features that are to be formed. In either case, after the photoreactive layer 26 has been exposed, it is processed in a conventional manner to remove the brightly-illuminated portions in the case of a positive resist material or unexposed or dark portions in the case of negative resist material. Known photolithographic apparatus and processes of the type shown in FIGS. 1 and 2 are disclosed, for example, in U.S. Pat. No. 5,384,219 issued to Dao et al., U.S. Pat. No. 5,906,910 issued to Nguyen et al., and U.S. Pat. No. 5,308,741 issued to Kemp.
Although desirable results have been achieved using conventional photolithographic apparatus and processes, some drawbacks exist. For example, during research and development of new semiconductor designs, it is often desirable to conduct trial-and-error studies in order to optimize a design. Such trial-and-error studies involve introducing minor variations into the design, and then testing the design to determine which variation provides optimal performance. For each new design of the trial-and-error study, a new reticle 18 is constructed.
In the case of memory circuits, trial-and-error studies are commonly used to investigate design variations in a so-called “periphery” portion of the memory circuit containing the access circuitry necessary for transmitting control and data signals to, and receiving signals from, the individual memory elements of the memory array. The region of the periphery is typically a fraction of the total patterned area of a reticle, with the memory array occupying the majority of the patterned area. Additionally, the patterning of the periphery region is not nearly as dense as in the memory array because there is not the same need for small feature sizes. Thus, in the case of memory circuits, a relatively large portion of each new reticle 18, which is associated with the array of memory elements, remains unchanged between successive trial-and-error tests, while a relatively small portion of each new reticle, which is associated with the periphery portion in which design variations are systematically conducted, is modified. In many situations, only minor modifications are made in the periphery, however, an entirely new reticle is made.
It is generally the case that the cost of a new reticle increases with the complexity and density of the pattern. As previously mentioned, the patterning of the periphery is not as dense as for the memory array, which is not that complicated, but much denser than for the periphery. Thus, relatively speaking, the portion of the costs of making a new reticle that are attributed to the pattern of the memory array is considerably greater than the portion of the costs attributed to the pattern of the periphery. Although minor modifications may be made in the periphery, an entirely new reticle is still made. Because the cost of fabricating each new photolithographic reticle 18 is relatively high, the overall cost of trial-and-error studies can be exorbitant before a satisfactorily optimized design is achieved.
USPTO Backgrounds
USPTO Backgrounds