The present invention relates to a semiconductor integrated circuit device and, more particularly, to technology which is effectively applied in a semiconductor integrated circuit device including nonvolatile storage elements of a single layer polysilicon gate structure.
An example of a mask ROM (Read Only Memory), in which data are written using a mask, is disclosed in U.S. Pat. No. 4,939,386. Since this type of mask ROM can be fabricated by a poly-Si (polysilicon) one-layer process and is capable of storing one bit in one transistor, it is suitable for achieving larger capacity at lower cost. As mask ROMs are becoming more and more miniaturized, however, thereby increasing packaging density, some type of defect control technique must necessarily be adopted for improving yield. A known technique for controlling defective bits of the mask ROM is disclosed in, for example, ISSCC (International Solid-State Circuit Conference) Dig. Tech. Papers, February 1989, pp. 128–129, 311. In this paper, a redundancy technique using polycrystalline Si fuse is disclosed.
USPTO Backgrounds
USPTO Backgrounds