Medium- to high-speed data transmission systems for time-invariant or high-frequency channels implemented with dedicated hardware signal processors use digital filtering and least-mean-square adaptive equalizer algorithmic techniques. The precision required to represent the digital sequence in the signal path and filter coefficients may not be the same. For example, with a conventional least-mean-square adaptive equalizer, to make the adaptation noise acceptable, the coefficients of the transversal equalizer should be updated with coefficients having sixteen-bit precision. To cope with this precision requirement, a conventional digital signal processing architecture requires a sixteen by sixteen bit multiplier and a thirty-two bit accumulator to carry out the computation. Although only the high-order eight bits of the updated coefficients are used to perform the filtering, the word-length of the multiplier is determined by the highest precision required.
As another example, the receiver section of a modem data transmission system consists of the analog front end, automatic gain control, echo cancellation, matched filters and processors. Before the automatic gain control and echo cancellation take place, sixteen bits are required to represent the input digital data. However, at this stage, eight-bit coefficients can be used to do the filtering operation. Conventional architectures require a sixteen-bit multiplier to do the filtering because the word-length of the multiplier used is determined by the highest precision required.
Needless storage of the low-order bits consumes extra die area on an integrated circuit chip embodying the architecture and extracts a time penalty during the processing of these excess low-order bits. For instance, the attenuation characteristic and the propagation velocities experienced by the various frequency components in a signal are not constant, resulting in distortion in a transmitted signal. Initial training time is significant because it reduces the net data throughput. (See, e.g. Digital. Analog, and Data Communication, by William Sinneman, Reston Publishing Company, Reston, VA, 1982, ISBN 0-8359-1301-5 at pp. 148-152.) It is therefore a principal object of this invention to provide a word-sliced signal processor that uses shorter word-length hardware to represent and process digital signals while maintaining a desired level of accuracy. Another object of this invention is to reduce the chip area required for implementation of the signal precessing algorithms. Another object of this invention is to eliminate unnecessary computation and decrease cycle time so as to shorten processing time for adaptive equalization of the signal.
USPTO Backgrounds
USPTO Backgrounds