1. Field of the Invention
The present invention relates to techniques for limiting the level of an output potential at an MOS transistor output circuit.
2. Description of the Background Art
In general, output circuits of MOS transistor output circuits have been complementary MOS output circuits as shown in FIG. 13. In the conventional complementary MOS output circuit, a P-channel transistor 1P and an N-channel transistor 1N which are common-source circuits are connected in series. An input terminal Tin is connected to the gates of the transistors 1P and 1N in common, and an output terminal Tout is connected to the drains thereof in common. An input signal is applied to the input terminal Tin, so that an inverted signal of the input signal is outputted as an output signal to the output terminal Tout.
In the conventional MOS transistor output circuit thus constructed, the level of the output signal thereof oscillates from a ground potential GND to a power supply potential V.sub.DD by the transition (change in logical state) of the input signal unless a load current is a direct current.
A large amplitude of the output signal causes various problems under certain circumstances. One of the problems is known as undesired radiation which is to jam other electronic equipments. Another problem is the malfunctions of logic circuits due to noises generated when a logical state changes. It is preferable in some cases that the output signal has a small amplitude in terms of delay times of the logic circuits, heat generation in integrated circuits and other characteristics.
USPTO Backgrounds
USPTO Backgrounds