1. Field of the Invention
The present invention relates to a line of fabrication of integrated circuits containing, in particular, bipolar and complementary MOS (CMOS) components. This type of line is generally called a BICMOS line.
2. Summary of the Invention
The present invention provides such a line in which the dimensions of an element designed on a mask can be of a dimension lower than or equal to 0.4 .mu.m, for example, from 0.2 to 0.35 .mu.m.
The present invention is to provide such a line in which the properties of the MOS-type components and those of the components of bipolar type are optimized.
Furthermore the present invention is to provide such a line which is compatible with known lines of fabrication of CMOS components.
Furthermore the present invention is to provide such a line which is as simple as possible to reach the desired results.
Furthermore the present invention is to provide such a line which is adapted to the fabrication of capacitors of high capacitance per unit of surface area.
The present invention provides a fabrication method in which are successively implemented the buried layers of the bipolar transistors, the CMOS transistors, the bipolar transistors, and then the interconnects, to decouple the characteristics of the MOS transistors from those of the bipolar transistors and optimize each of these components. After the formation of the MOS transistors, a protection layer enables protection of the MOS transistors during the formation of the bipolar transistors. This same protection layer is then used as a mask for the formation of silicided areas.
More specifically, the present invention provides a method for fabricating an integrated circuit including complementary MOS transistors and a bipolar transistor of NPN type, including the following steps:
forming an N-type epitaxial layer on a P-type substrate, a buried layer being provided at least at the location of the bipolar transistor, PA1 forming a thick oxide layer at the locations other than the locations of the wells of the MOS transistors, of a collector well region of the bipolar transistor and of a base-emitter region of the bipolar transistor, PA1 forming the MOS transistors and the collector well of the bipolar transistor, PA1 covering the entire structure with a protection layer including a first layer of silicon oxide and a first layer of silicon nitride, PA1 opening the protection layer at the base-emitter location of the bipolar transistor, PA1 forming a first P-type doped layer of polysilicon or amorphous silicon, a second layer of silicon nitride and a second layer of encapsulation oxide, PA1 opening these last three layers at the center of the emitter-base region of the bipolar transistor, PA1 diffusing the doping contained in the first silicon layer in the underlying epitaxial layer, to form the extrinsic base of the bipolar transistor, PA1 implanting an N-type collector doping, PA1 implanting a P-type doping to form the intrinsic base of the bipolar transistor, PA1 depositing a third silicon nitride layer, depositing a second layer of polysilicon, anisotropically etching the second polysilicon layer to leave in place spacers in the vertical portions thereof, and removing the apparent parts of the third layer of silicon nitride, PA1 depositing a third N-type doped polysilicon layer and diffusing the doping to form the emitter of the bipolar transistor, PA1 depositing a planarized insulating layer, and PA1 performing the metallizations.
According to an embodiment of the present invention, the first layer of silicon oxide has a thickness of around 20 nm and the first to third silicon nitride layers have a thickness of around 30 nm.
According to an embodiment of the present invention, the first silicon layer has a thickness of around 200 nm and the second silicon oxide layer has a thickness of around 300 nm.
According to an embodiment of the present invention, the first silicon layer is obtained by deposition of undoped amorphous silicon, and then by superficial implant of BF.sub.2.
According to an embodiment of the present invention, during the step of opening of the first P-type doped polysilicon or amorphous silicon layer, of the second silicon nitride layer, and of the second encapsulation oxide layer, an opening wider than in the second silicon nitride layer is formed in the encapsulation oxide layer, whereby, upon deposition of the third silicon nitride layer, this layer has a larger contact surface area with the second silicon nitride layer.
According to an embodiment of the present invention, this method further includes, before the step of deposition of the third N-type doped polysilicon layer, the step of performing an opening in the second encapsulation oxide layer, to expose a portion of the second silicon nitride layer, whereby, at the level of this opening, the first and third polysilicon layers form a capacitor, the dielectric of which is formed of a portion of the second silicon nitride layer.
According to an embodiment of the present invention, this opening is formed above a thick oxide area.
These characteristics and advantages as well as others, of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments of the present invention, in relation with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds