1. Field of the Invention
The present invention relates generally to a method of designing semiconductor devices, an apparatus for designing semiconductor devices, and a semiconductor device designed by this method. More particularly, this invention relates to efficient designing of the interconnection for cells laid out on a chip that reduces interconnection resistance and capacitance.
2. Description of the Related Art
Recent advances in computer-aided design (CAD) allow semiconductor devices to be designed using a CAD apparatus which is equipped with a library that stores data on various kinds of cells. In the field of designing semiconductor devices, "cell" represents one unit having function as a single electric element, which is typified by an invertor or a two-input NAND gate, and exists in a CAD apparatus in data form, such as pattern data, connection data, electrical characteristic data and a truth-table.
In designing a logic circuit, desired cells are selected from a cell data library prepared in advance. The pattern of each selected cell is displayed on the screen (display) of a CAD apparatus is based on pattern data. The screen of the CAD apparatus displays the layout of a semiconductor chip, and an operator lays the cell pattern at the desired position in the chip layout. After completion of the layout of all the cells needed for the logic circuit, the interconnections between terminals of the individual cells are automatically made in automatic interconnection mode to complete the designing of the semiconductor chip.
FIG. 1 shows a part of a logic circuit that is to be designed. An invertor 100 has a CMOS structure constituted by a PMOS transistor 101 and an NMOS transistor 102. The transistors 101 and 102 have gates connected to an input terminal A, and have drains connected to an output terminal X. The transistor 101 has a source connected to a power line 103 of a high-potential power source V.sub.DD. The transistor 102 has a source connected to a power line 104 of a low-potential power source V.sub.SS.
When data of a cell 110 corresponding to this invertor 100 is read from a cell library, a pattern PA of this cell 110 is displayed on a display based on the cell data. An operator lays the pattern PA at the desired position in the chip layout.
The layout of the cell 110 is illustrated in FIG. 2. The pattern PA of the cell 110 includes the first and second transistor forming areas 111 and 112, and first, second and third interconnection forming areas 113 to 115. The first interconnection forming area 113 is located between the transistor forming areas 111 and 112.
The first transistor forming area 111 is defined by the cell data as an area where the transistor 101 is to be formed. The first transistor forming area 111 includes a region 111D where a drain is formed, a region 111G where a gate is formed and a region 111S where a source is formed. Defined in the drain region 111D is a region C1 where a contact hole to connect to a signal line is formed. Defined in the source region 111S is a region C2 where a contact hole to connect to the power line 103 is formed.
The second transistor forming area 112 is defined by the cell data as an area where the transistor 102 is to be formed. The second transistor forming area 112 includes a region 112D where a drain is formed, a region 112G where a gate is formed and a region 112S where a source is formed. Defined in the drain region 112D is a contact region C3 where a contact hole to connect to a signal line is formed. Defined in the source region 112S is a contact region C4 where a contact hole to connect to the power line 104 is formed.
The first interconnection forming area 113 is defined as an area where a signal line is to be laid out. The first interconnection forming area 113 has an interconnection region L1 for connecting both gate regions 111G and 112G of the transistor forming areas 111 and 112 by a polysilicon wire, and an interconnection region L2 for connecting the drain regions 111D and 112D by an aluminum wire. Defined on the interconnection region L1 is a contact region C5 where a contact hole to connect to a signal line is formed.
The second interconnection forming area 114 is defined as an area where a signal line is to be laid out. The second interconnection forming area 114 has an interconnection region L3 for connecting the gate region 111G of the first transistor forming area 111 to a signal line by a polysilicon wire, and a contact region C6 where a contact hole to connect to the power line is formed. Defined on the interconnection region L3 is a contact region C7 where a contact hole to connect to a signal line is formed.
The third interconnection forming area 115 is defined as an area where a signal line is to be laid out. The third interconnection forming area 115 has an interconnection region L4 for connecting the gate region 112G of the second transistor forming area 112 to a signal line by a polysilicon wire, and a contact region C8 where a contact hole to connect to the power line is formed. Defined on the interconnection region L4 is a contact region C9 where a contact hole to connect to a signal line is formed.
The individual contact regions C5, C7 and C9, and the individual interconnection regions L1, L3 and L4 are provided to improve the interconnecting efficiency (the number of wires per unit area) in the automatic interconnecting process. The individual contact regions C5, C7 and C9 are recognized as interconnection points (i.e., input terminal A) in automatic interconnection mode, and provide nodes at which the gates of the transistors 101 and 102 are connected to the signal lines. Even if the signal lines cannot be laid out on the first interconnection forming area 113, the contact region C7 or C9 allows a signal line to be laid on either the second interconnection forming area 114 or the third interconnection forming area 115, so that each gate can be connected to the signal line via the contact region C7 or C9. Likewise, the contact regions C1 and C3 are recognized as interconnection points (i.e., output terminal X) in automatic interconnection mode and contribute to improving the interconnecting efficiency.
If the contact region C9 is selected as the input terminal A for an aluminum signal line LA as shown in FIG. 2, for example, this signal line LA is coupled via the contact region C9 to the polysilicon interconnection formed in the interconnection region L4. When a semiconductor device is actually fabricated based on this interconnection plan, another polysilicon interconnection formed in the interconnection region L3 remains as a wasteful and redundant interconnection in the semiconductor device.
If the contact region C5 is selected as the input terminal A for an aluminum signal line, this signal line is coupled via the contact region C5 to the polysilicon interconnection formed in the interconnection region L1. When a semiconductor device is actually fabricated based on this interconnection plan, polysilicon interconnections formed in the interconnection regions L3 and L4 remain as wasteful redundant interconnections.
Those redundant interconnections impart undesirable extra resistance and capacitance to the signal lines. The extra resistance and capacitance degrade the operational characteristics of the transistors 101 and 102 in the form of operational delays.
FIG. 3 shows the pattern PA of another invertor cell 120. In the pattern PA of the cell 120, unlike that of the cell shown in FIG. 2, the second and third interconnection forming areas 114 and 115 do not have the contact regions C7 and C9. Further, the interconnection regions L3 and L4 of the second and third interconnection forming areas 114 and 115 extend to respective nodes 121 and 122. Furthermore, a new interconnection region L5 for an aluminum interconnection extending to a center node 123 from the contact region C5 is defined in the first interconnection forming area 113. In other words, the interconnection region L5 is provided when the signal line is an aluminum interconnection. When the signal line is a polysilicon interconnection, either the interconnection region L3 or L4 is provided.
If the node 122 is selected as the input terminal A for a signal line made of polysilicon LP as shown in FIG. 3, this signal line LP is connected via the node 122 to a polysilicon interconnection formed in the interconnection region L4. When a semiconductor device is actually fabricated based on this interconnection plan, an aluminum interconnection formed in the interconnection region L5 and a polysilicon interconnection formed in the interconnection region L3 remain as wasteful interconnections and become redundant interconnections. When the node 123 (interconnection region L5) is selected for an aluminum signal line, polysilicon interconnections formed in the interconnection regions L3 and L4 remain as unnecessary interconnections in the semiconductor device and become redundant interconnections.
USPTO Backgrounds
USPTO Backgrounds