1. Field of the Invention
The invention relates to high gain, MOS field effect transistor differential amplifier.
2. Prior Art
Conventional differential amplifiers achieve relatively low voltage gain. Moreover, these amplifiers are typically implemented by the interconnection of non-complementary transistor devices. This has the undesirable effect of limiting the output voltage swing of the amplifier due to an inherent threshold level drop in voltage. What is more, many amplifier circuits are dynamic in operation, requiring bootstrap capacitor means and clocked precharge circuits. This is disadvantageous, inasmuch as the size and cost of the amplifier circuit are increased.
Examples of prior art circuits include the following:
U.S. Pat. No. 3,700,981 Oct. 24, 1972 PA1 U.S. Pat. No. 3,775,693 Nov. 27, 1973 PA1 U.S. Pat. No. 3,875,887 Apr. 8, 1975
Another improved field effect transistor differential amplifier, which operates from a 5.0 volt power supply, is shown in U.S. Pat. No. 4,079,332, issued Mar. 14, 1978. Although such circuits achieve good voltage gain, the demanding requirements of certain applications make such a circuit disadvantageous for use therein.
One of the important applications for such a differential amplifier is as a sense amplifier in a memory circuit. The development of high speed static memories which incorporate a plurality of field effect transistors in series result in voltage swings of less than 500 milivolts. Such prior art differential amplifiers as discussed above, could not distinguish voltage swings having a difference of less than 500 milivolts. The prior art differential amplifiers are therefore unsuitable for such applications.
USPTO Backgrounds
USPTO Backgrounds