The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit device including a stressed semiconductor device for improved operational speed and fabrication process thereof.
With progress in the art of device miniaturization, it is now possible to fabricate ultrafine and ultra high-speed semiconductor devices having a gate length of less than 100 nm.
With such ultrafine and ultra high-speed transistors, the area of the channel region right underneath the gate electrode is extremely reduced as compared with conventional semiconductor devices, and thus, the mobility of electrons or holes traveling through the channel region is influenced heavily by the stress applied to such a channel region.
Thus, various attempts have been undertaken to improve the operational speed of semiconductor devices by optimizing the stress applied to such a channel region.
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