In a processor that processes memory accesses in an out-of-order manner, a cache control unit can process requests of memory access from an instruction control unit regardless of the order of the requests, or in no particular order.
FIGS. 16 and 17 are diagrams for explaining examples of reference, registration, and replacement of data in a primary cache control unit. In the examples illustrated in FIGS. 16 and 17, a primary cache RAM 210 of a primary cache control unit 200 is formed by a set associative system which includes two ways, way-0 and way-1.
When an instruction control unit 100 requests an instruction of memory access, the primary cache control unit 200 temporarily holds the request in an FP (Fetch Port) 220 which includes a plurality of entries. FIG. 16A illustrates an example that a load instruction is issued as an instruction of memory access.
The primary cache control unit 200 uses a part of a virtual address of the requests held in the FP 220 as cache indexes to refer to a line corresponding thereto of the primary cache RAM 210. At the same time, a physical address corresponding to the virtual address is obtained by address conversion (refer to FIG. 16A).
When the physical addresses of data registered in the reference lines of the primary cache RAM 210 do not correspond to the physical address converted from the virtual address, or when the data registered in the reference lines of the primary cache RAM 210 is invalid (Invalid), the primary cache control unit 200 requests a secondary cache control unit 300 to transfer data indicated by the physical address converted from the virtual address. In this case, both data of the reference lines of the way-0 and the way-1 are valid (Valid) in the primary cache RAM 210, but the both data do not correspond to a physical address-A converted from the virtual addresses. Therefore, a data transfer request is issued to the secondary cache control unit 300 (refer to FIG. 16A).
At this point, when both data of the way-0 and the way-1 registered in the reference lines of the primary cache RAM 210 are valid (Valid) data, a replacement control unit 290 selects one of the two ways as a replacement target. And, the replacement control unit 290 evicts out the data registered in the reference line of the selected way from the primary cache RAM 210 to the secondary cache control unit 300, or invalidates (Invalid) the data. Hereinafter, as illustrated in FIG. 16B, it is assumed in the description that the way-0 is selected as a replacement target, and that the data registered in the reference line of the way-0 is invalidated (Invalid).
The primary cache control unit 200 registers, in the selected way, data transferred from the secondary cache control unit 300 and the physical address of the data. In this case, the transferred data and the physical address-A are registered in the way-0 (refer to FIG. 17A).
The primary cache control unit 200 re-executes an instruction of memory access held in the FP 220. In this case, the load instruction held in the FP 220 is re-executed, and the line corresponding thereto of the primary cache RAM 210 is referred. At this point, there is a valid data in the way-0 that the physical address corresponds. Therefore, the data is transmitted to the instruction control unit 100, the FP 220 is released, and then the processing is finished (refer to FIG. 17B).
Patent Document 1 is an example of a document describing a prior art related to the control of cache memory. Patent Document 1 describes a technique for increasing throughput of instructions in a processor that executes load instructions and store instructions in an out-of-order manner.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2000-259412
USPTO Backgrounds
USPTO Backgrounds