The present invention in general relates to integrated circuits, and, in particular, to trimming operations of integrated fuses.
Integrated circuits are often required to store data on a permanent basis, or to form permanent connections on the integrated circuit once its fabrication process is concluded. This may be done using a plurality of fusible connections that can be subsequently and selectively burnt according to a certain scheme. These fusible connections are thin strips of conductor material, typically polysilicon, providing low resistance current paths that may be interrupted by burning the polysilicon by forcing a current pulse of sufficient magnitude therethrough.
The process of selecting the fuses to be burnt as well as the burning of selected fuses is referred to as trimming, and it is commonly carried out in analog devices, such as in operational amplifiers and also specific telecommunications devices, for example. These analog devices are often required to have certain electrical circuit parameters ranging in a well-defined interval, while the fabrication process spread may often go beyond these stringent limits.
To understand the utility of the trimming process, reference may be made to an integrated circuit, wherein the adjustment of a time constant (velocity) could be implemented by adjusting the actual value of an integrated resistance. An integrated resistance may be physically structured such that the current circulates through a number of resistances connected among each other by fuses in a certain network scheme. By interrupting the electrical continuity of selected fuse connections, i.e., by burning selected fuses and leaving the other fuses intact, the total resistance may be adjusted.
During a trimming process three distinct operations may be recognized. A first operation includes a write and simulation operation that forces control signals for the components to be trimmed to determine which fuses should be burned to obtain the most appropriate configuration. A second operation includes a burning operation of the fuses according to the configuration previously determined. A third operation includes testing of the state of the fuses, which may even be carried out before the burning process. This is done to verify the integrity of the elements to be burnt, and this operation is repeated after the burning process to verify that the configuration obtained is the desired one.
The trimming process requires particular attention because the fuses are subject to an irreversible burning. The need of forming an ever-increasing number of fuses for the trimming process of complex integrated systems has imposed the implementation of circuits, procedures and methods to safely burn the correct fuses, and above all, to simulate the circuit behavior before irreversibly burning the selected fuses.
Generally, these circuits have a latch that stores the state of the fuses and a logic circuitry which, during the simulation phase, substitutes the latch content or else forces the trimming signal to an externally set value. Some examples of such circuits as well as methods are disclosed in the following U.S. Pat. Nos. 5,838,076; 5,731,733; 5,517,455; 5,412,594; 5,384,727; 5,361,001; 5,047,664; 4,532,607; and 4,446,534. The systems disclosed in these patents use circuits specifically dedicated to check, simulate and eventually burn the fuses.
Integrated systems often include a special circuit to test the integrity and proper functioning of logic circuitry contained therein. An example of a known scan test device is referred to as a Scan Chain. This is formed by connecting the flip-flops that make up the logic circuitry to be tested to configure them as a shift register. During testing, the shift register is loaded with a number of bit vectors (Scan Path) allowing the interaction of the logic circuits with the loaded register and modification of its content. The bit vector contained in the register, which at each interaction varies depending on the previously stored vector, may be read via a procedure similar to the one used during the loading process. If the read vector is not as expected, one of the components of the device must have failed.
The insertion of the Scan Chain in the logic circuitry to be tested, as well as the generation of the Scan Path, are formed automatically using dedicated systems. These systems use appropriate algorithms to optimize the formation of the shift register and the number of vectors required to ensure that all the components are involved in the test.
As discussed above with respect to existing systems, the control circuits of the trimming process are distinct from the circuits that implement the scan test of the functional state of the digital components of the logic circuitry of the integrated system. It is evident that an approach that implements with a unique circuit the operations of Scan Chain, control and simulation, as well as the burning of the fuses would be desirable. Such an approach would result in simplified circuitry.
It is an object of the present invention to provide a circuit that fulfills the functions of fuse check and burning of the fuses according to a post fabrication trimming process using latches that are integrated in a structure suitable to perform a scan test of the functional logic circuitry of the device.
While existing fuse check and burning circuits are normally dedicated to the trimming operations alone, the proposed invention simplifies the entire integrated circuit architecture by using for trimming operations part of the structures that are formed and utilized for performing scan tests. The new system of the invention only requires an additional pin besides the number of pins that are normally required to manage Scan Chain operations for controlling the burning of the fuses according to a normal trimming process.
In addition, a further simplification is obtained because the read/write operations and burning of the fuses refer to the same digital channels and to the same procedures that perform the loading and unloading of the Scan Chain.
More specifically, the object of the present invention is to provide a multifunction circuit for controlling, simulating and burning integrated fuses according to a post fabrication trimming procedure, and for performing scan tests of an integrated device. The circuit comprises a plurality of scan flip-flops connected to form a scan chain. The command inputs of which are coupled to a first circuit to be subjected to functionality tests. The outputs of which, besides each being coupled to a second scan input of the successive flip-flop in the chain, are coupled to as many inputs of a second circuit to be subjected to functionality tests.
At least a scan bit vector is coupled through a first pin of the integrated device to the input of the scan bit vector of the first flip-flop of the scan chain. The output of the last flip-flop of the chain is connected to a second pin of the integrated device. An enabling signal of the scan is applied through a third pin in common to a third conditioning input of all the flip-flops of the chain. A scan timing signal is applied through a fourth pin of the device in common to timing inputs of all the flip-flops of the chain.
The multifunction characteristics of the circuit is due to the fact that the above scan test circuit further comprises a first array of a number N, equal to the number of integrated fuses, of scan flip-flops forming a fuses register. The Q1 . . . N outputs of which are coupled to as many inputs of the functional circuits of the integrated device conditioned by the trimming.
A second array of a number K of scan flip-flops forms, in conjunction with a modulus N counter, a counter register. A third array of a number M of scan flip-flops, each configured as a memory cell, forms a control register of the trimming parameters.
A timing signal is applied in common to relative inputs of all the flip-flops. The first scan command is applied to the relative input of the first flip-flop of the fuses register. The output of the last flip-flop thereof is coupled to the input of the scan command of the first flip-flop of the counter register. The output of the last flip-flop thereof is coupled to the input of the scan command of the first flip-flop of the control register. The output of the last flip-flop thereof is coupled to the input of the scan command of the first flip-flop of the plurality of chained flip-flops, thus forming the chain.
The outputs of the counter register are coupled to the inputs of a decoder and logically combined with respective outputs of the fuses register, with the enabling signal, and with an additional signal for conditioning the sequential burning of the selected fuses. This additional signal is applied through a dedicated fifth pin of the integrated device.
A number N of burning commands are generated that are fed through a bus to the respective inputs of a number N of logic gates for controlling the command inputs of the N scan flip-flops forming the fuses register. As compared to a dedicated trimming circuit approach, the approach of the present invention is advantageous when the integrated device includes a scan chain, or when there are enough fuses to justify a serial loading of data and a burning process carried out sequentially fuse by fuse.
USPTO Backgrounds
USPTO Backgrounds