1. Technical Field
The present invention relates generally to power driver circuits and their operation and in particular to a method and apparatus for controlling output voltage slope of a power driver.
2. Introduction
Reference is made to FIG. 1 which shows a circuit diagram of a power driver circuit 100. The circuit 100 includes a high side driver 102 and a low side driver 104. The output of the high side driver 102 is coupled to a high side node 106 of a load 108. The output of the low side driver 104 is coupled to a low side node 110 of the load 108. In the exemplary implementation of FIG. 1, the load 108 is a display panel of an AMOLED type and the high side node 106 and low side node 110 are the voltage supply nodes (Va and Vb) for the display panel. It will be understood, however, that the load 108 may comprise any suitable load driven from both the high and low side.
The high side driver 102 comprises a pair of series connected transistors 120 and 122. The transistors 120 and 122 are of the n-channel MOSFET type coupled in series through their source-drain paths. It will be understood that transistors of other type may instead be used, the reference to n-channel MOSFET devices being exemplary only of a preferred implementation. P-channel MOSFETs, combinations of n-channel and p-channel MOSFETs, bi-polar devices and/or IGFET type devices may alternatively be used.
The transistor 120 includes a conduction (drain) terminal coupled to a first power supply node 124 and a conduction (source) terminal coupled to the high side node 106. A control (gate) terminal of the transistor 120 is coupled to a first control node 126. The transistor 122 includes a conduction (drain) terminal coupled to the high side node 106 and a conduction (source) terminal coupled to a second power supply node 128. A control (gate) terminal of the transistor 122 is coupled to a second control node 130.
The low side driver 104 comprises a pair of series connected transistors 140 and 142. The transistors 140 and 142 are of the n-channel MOSFET type coupled in series through their source-drain paths. It will be understood that transistors of other type may instead be used, the reference to n-channel MOSFET devices being exemplary only of a preferred implementation. P-channel MOSFETs, combinations of n-channel and p-channel MOSFETs, bi-polar devices and/or IGFET type devices may alternatively be used.
The transistor 140 includes a conduction (drain) terminal coupled to a third power supply node 144 and a conduction (source) terminal coupled to the low side node 110. A control (gate) terminal of the transistor 140 is coupled to a third control node 146. The transistor 142 includes a conduction (drain) terminal coupled to the low side node 110 and a conduction (source) terminal coupled to a fourth power supply node 148. A control (gate) terminal of the transistor 142 is coupled to a fourth control node 150.
The first and third power supply nodes 124 and 144 are preferably coupled to receive high supply voltages (for example, Vdd1 and Vdd2). These may, for example, be different high supply voltages, or the same high supply voltage, depending on circuit application.
The second and fourth supply nodes 128 and 148 are preferably coupled to receive low supply voltages. These may, for example, be different low supply voltages, or the same low supply voltage (for example, ground), depending on circuit application.
Reference is now made to FIG. 2 which illustrates voltage waveforms for the voltage signals at the high side node 106 (voltage signal Va) and low side node 110 (voltage signal Vb). These waveforms are specific to the exemplary implementation of FIG. 1 where the load 108 is a display panel of an AMOLED type. It will be understood, however, that high and low side waveforms having a similar shape and timing may be applicable with other types of loads.
During a period of time associated with resetting the display panel load 108 (of an AMOLED type), the high side driver 102 and low side driver 104 are controlled by application of appropriate control signaling to the first, second, third and fourth control nodes 126, 130, 146 and 150 of the transistors 120, 122, 140 and 142, respectively, to pull down the voltage at the high side node 106 (voltage signal Va) as indicated at reference 160. The reset time period terminates when the voltage at the high side node 106 (voltage signal Va) returns high. During a first time period t1 associated with initially pulling down the voltage at the high side node 106, it is important to exercise control over the downward voltage slope. In particular, there is a need to control the slope in a manner which ensures that no voltage/current spike is introduced during the power driving operation.
During a period of time associated with emission in the display panel load 108 (of an AMOLED type), the high side driver 102 and low side driver 104 are controlled by application of appropriate control signaling to the first, second, third and fourth control nodes 126, 130, 146 and 150 of the transistors 120, 122, 140 and 142, respectively, to pull down the voltage at the low side node 110 (voltage signal Vb) as indicated at reference 162. The emission time period terminates when the voltage at the low side node 110 (voltage signal Vb) returns high. During a second time period t2 associated with initially pulling down the voltage at the low side node 110, it is important to exercise control over the downward voltage slope. In particular, there is a need to control the slope in a manner which ensures that no voltage/current spike is introduced during the power driving operation.
USPTO Backgrounds
USPTO Backgrounds