1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory device and particularly to a non-volatile semiconductor memory device suitable for storing multivalued data.
2. Description of the Related Art
Recently, Erasable and Programmable ROMs (EPROMs) and Electrically Erasable and Programmable ROMs (EEPROMs), which can substitute for magnetic memories including hard disks, and floppy disks, are drawing attention. EPROMs and EEPROMS each have a plurality of memory cells (memory cell transistors). Each memory cell has a floating gate electrode for storing a carrier and control gate for detecting the threshold voltage, which changes depending on the presence and absence of the carriers accumulated in the floating gate electrode. EEPROMs include flash EEPROMs, which can perform data erasure for all the memory cells or partial data erasure for each array of block memory cells.
In each memory cell, a first gate insulating layer is provided between the floating gate electrode and a channel area, and a carrier is implanted from the channel area into the floating gate electrode through the first gate insulating layer. The carrier is implanted according to any of the following methods:
1) by generating hot carriers in the channel area (channel hot carrier); and PA1 2) causing the flow of a Fowler-Nordheim (FN) tunnel current between the floating gate electrode and the channel area. PA1 1) Two-layer polysilicon type: An FN tunnel current is flowed between the channel area or source/drain area and the floating gate electrode through the first gate insulating layer; and PA1 2) Three-layer polysilicon type: A second gate insulating layer is provided between the floating gate electrode and the control gate electrode, and an FN tunnel current is flowed between the floating gate electrode and the control gate electrode through the second gate insulating layer.
An increase in the carrier implantation energy increases damage to the first gate insulating layer. Such serious damage to the first gate insulating layer allows formation of charge trap. The charge trap causes a change in the I-V characteristics, that is, the relationship between the current flowing through a memory cell and the control gate voltage. As a results the threshold voltage of the memory cell is changed. This makes accurate writing and reading of data impossible.
The damage to the first gate insulating film limits the number of feasible data rewrites for the memory cell, In other words, the first gate insulating layer is damaged each time carriers are implanted into the floating gate electrode. If the degree of damage exceeds a certain level, insulatability of the first gate insulating layer is lowered to permit leakage of the carrier accumulated in the floating gate electrode. In this state, the memory cells no longer function properly.
In order to increase the number of feasible data rewrites, carrier preferably has a smallest possible implantation energy. The thinner the first gate insulating layer is, the smaller the carrier implantation energy can be. However, an extremely small film thickness increases leakage of the carrier from the floating gate electrode, and thus the data retention time in the memory cell becomes short. Accordingly, when data retention time is taken into consideration, it is not preferred to allow the first insulating layer to have a small thickness.
The method of extracting the carrier from the floating gate electrode differs depending upon the following two types:
In the two-layer polysilicon type, damage to the first gate insulating layer is caused when the carriers are extracted. In the three-layer polysilicon type, damage to the second gate insulating layer but not to the first gate insulating layer is caused when the carriers are extracted. The adverse influence of the damage in the second gate insulating layer is smaller than that of the first gate insulating layer. Flash Memory Engineering Handbook (published by Science Forum) describes in detail the structures of memory cells in EEPROMs and EPROMs and damage to gate insulating layers.
FIG. 1 shows schematically a cross-sectional view of an example of a conventional stacked gate type memory cell generally employed in a flash EEPROM. The stacked gate type memory cell consists of a single crystal silicon substrate 201 with a source area 202a, a drain area 202b and a channel area 203, which is defined between the former two areas 202a and 202b, all being defined on the surface of the substrate 201. The stacked gate type memory cell further includes a gate insulating layer 204, a floating gate electrode 205, a gate insulating layer 206 and a control gate electrode 207, which are laminated successively on the channel area 203 in that order. The layers 204 to 207 have the same dimensions in the horizontal directions. Accordingly, the control gate electrode 207 is laminated exactly on the floating gate electrode 205 without dislocation. Further, the source area 202a and the drain area 202b are defined symmetrically on each side of the gate electrodes 205, 207 and channel area 203.
With respect to the terms "source area" and "drain area" in a memory cell used herein, provided that the reading operation is determined as the basic operation, the area to which a high voltage is applied in the reading operation is referred to as the drain area; whereas the area to which a low voltage is applied is referred to as the source area. These terms shall also apply in the writing operation and in the erasing operation.
Next, operations (writing, reading and erasing operations) of the stacked gate type memory cells will be described referring to FIG. 2. In any of these operations, a voltage maintained at the ground level (0 V) is applied to the substrate 201.
(a) Writing Operation;
In the writing operation, voltages of +12 V, 0 V and 5 V are applied to the control gate electrode 207, the drain area 202b and the source area 202a respectively. Thus, the potential of the floating gate 205 is elevated by the capacitive coupling between the floating gate electrode 205 and the control gate electrode 207. Further, channel hot electrons generated in the channel area 203 near the source area 20a are implanted into the floating gate electrode 205. Consequently, electrons are accumulated in the floating gate electrode 205, and one-bit data is written and stored therein.
(b) Reading Operation:
In the reading operation, a voltage of +5 V is applied to the control gate electrode 207 and to the drain area 202b, and a voltage of 0 V is applied to the source area 202a. Thus, the cell current flowing from the drain area 202b to the source area 202a in the memory cell assuming the written state becomes smaller than the current flowing through a memory cell assuming the erased state. This is because the channel area 203 is turned off since hot electrons are implanted into the floating gate electrode 205 in the memory cell assuming the written state, and the channel area 203 in the memory cell assuming the erased state is turned on. The values of cell current flowing through those memory cells are determined, and, for example, a value of written data "1" and a value of erased data "0" can be read depending on the thus determined cell current values.
(c) Erasing Operation:
In the erasing operation, voltages of 0 V and +12 V are applied to the control gate electrode 207 and to the drain area 202b, respectively, and the source area 202a is set to assume an open state. Then, an FN tunnel current flows from the drain area 202b to the floating gate electrode 205, and the electrons accumulated in the floating gate electrode are extracted into the drain area 202b. Thus, the data stored in the memory cell is erased.
In order to improve the integration degree of the semiconductor memory, a multivalued data memory device is proposed. In this memory device, one memory cell can be allowed to store multivalued data of three values or more instead of binary data (erased state and written state), or one-bit data.
FIG. 3 is a characteristic graph showing a relationship between the value Id of cell current flowing through the stacked gate type memory cell and the potential Vfg of the floating gate electrode 205 in a memory cell. In FIG. 3, the floating gate potential Vfg indicates the potential of the floating gate electrode 205 with respect to the source area 202a.
As shown in this graph, when the floating gate potential Vfg is less than the threshold voltage Vth (approx. +1 V), the cell current value Id indicates zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id and the floating gate potential Vfg assume a directly proportional relationship.
The floating gate potential Vfg can be expressed by the following equation: EQU Vfg=Vfgw+Vfgc
wherein Vfgw is the potential generated by the electrons accumulated in the floating gate electrode 205 in the writing operation, and Vfgc is the potential to be generated by the capacitive coupling with the source area 202a. In the reading operation, since the potential Vfgc is fixed, the cell current value Id is determined essentially by the potential Vfgw. In the writing operation, the charge quantity of the floating gate electrode 205, i.e., the potential Vfgw, can be controlled by adjusting the writing operation time. This control of the floating gate potential Vfg allows desired setting of the cell current value Id in the reading operation.
For example, as shown in FIG. 3, assume that data values "11", "10", "01" and "00" correspond to the areas having cell current values Id of less than 40 .mu.A, 40 .mu.A or more and less then 80 .mu.A, 80 .mu.A or more and less than 120 .mu.A, and 120 .mu.A or more and less than 160 .mu.A, respectively. In this case, in the writing operation, the time of the writing operation is adjusted so that floating gate potentials Va, Vb, Vc and Vd corresponding to the cell current values Id (40, 80, 120 and 160 .mu.A) may be obtained. Thus, four-value (two bit) data can be stored in one memory cell.
However, in the erasing operation, when electrons are excessively extracted from the floating gate electrode 205, the channel area 203 is turned on even if a predetermined voltage (0 V) is applied to the control gate electrode 207 so as to maintain the memory cell in the OFF state. Consequently, the memory cell is constantly allowed to assume the ON state, giving rise to a problem of excessive erasure where a cell current flows even if the memory cell is in the stand-by state, Accordingly, it is not desired to use such area since it can cause excessive erasure of data storage.
In the reading operation, the potential of the floating gate electrode 205 is also determined according to the equation Vfg=Vfgw+Vfgc. In the reading operation, the area where the condition Vfg-Vfgc=Vfgw&gt;Vth is established causes an excessive erasure when the potential Vfg of the floating gate electrode 205 is elevated to +5 V by the capacitive coupling with the control gate electrode 207. In this case, the area having a floating gate potential Vfg of +6 V or more causes an excessive erasure.
Further, since the cell current value Id assumes substantially a constant value when the floating gate potential Vfg is less than 1 V, the cell current value Id cannot be allowed to assume a plurality of data values depending on the value Id correspondingly. In order to prevent writing errors and reading errors from occurring in a multivalued semiconductor memory device, it is preferred that the range of the floating gate potential and that of the cell current value Id corresponding to the respective values of multivalued data have sufficient margins. However, in a flash EEPROM employing stacked gate type memory cells, the range of cell current values suitable for storing multivalued data is limited to the area where the electric current fluctuates a lot due to the reasons described above, and no excessive erasure occurs. Accordingly, it is difficult to achieve sufficient margins for the floating gate potentials Vfg and the cell current values Id corresponding to the multivalued data values.
Since the range corresponding to the data values of the floating gate potential Vfg is relatively narrow, it is difficult to achieve a sufficient margin in the writing operation for accurately setting the floating gate potential Vfg. Further, since the range corresponding to the respective data values of cell current value Id is relatively narrow, it is difficult to achieve sufficient margin in the reading operation for accurately reading the cell current value Id. The achievement of sufficient margins becomes further difficult in an 8-value or 16-value system compared with the 4-value system, because the range corresponding to the multivalued data values of the floating gate electrode Vfg and of the cell current value Id are further narrowed.
USPTO Backgrounds
USPTO Backgrounds