1. Field of Invention
The present invention relates to the field of computer systems. More particularly, this invention relates to a system control unit that processes multiple coherent memory accesses in parallel.
2. Description of Related Art
Computer systems typically include a memory and a processor. The memory generally includes a main memory and a cache memory for storing data and instructions for the processor. The cache memory in the processor may include one or more caches that may be xe2x80x9csplit,xe2x80x9d i.e. separate caches for instructions and data addresses, or xe2x80x9cunified,xe2x80x9d i.e., a single cache for both instructions and data, or a combination of the two. The cache memories store blocks of data and/or instructions that are received from the main memory. Typically, instructions from the main memory that are used by the processor are stored in the instruction cache. In addition, the data for that particular instruction is stored in the data cache.
When the processor requests data from the main memory, it takes much longer for the processor to receive the data than it does when it requests the data from the cache memory. Thus, when accessing data from the main memory, the processor may require additional clock cycles to retrieve the data. The additional clock cycles increase the amount of time required by the processor to complete a particular transaction. The speed of the computer system is further reduced when the processor has to access multiple data values from the main memory. Further, if a transaction that the processor is executing takes extra clock cycles to execute, the processor must wait until the transaction is complete before executing another transaction. Hence, the processor executes transactions one instruction at a time. For example, the instructions x=y+1 and z=w+10 each may take approximately 5 cycles to execute. Therefore, the total processor time to execute these two instruction is 10 cycles. In this example, the processor retrieves the value for y and executes the x=y+1 transaction before the processor retrieves the value for w and executes the z=w+10 transaction. Executing instructions one at a time is inefficient because some instructions can be processed independent of other instructions.
It should therefore be appreciated that there remains a need for a computer system that performs multiple coherent memory accesses in parallel. The present invention fulfills this need.
The present invention is embodied in a computer system, and related method, that includes a system control unit that accesses information from multiple coherent memories for processing in parallel. The computer system includes a number of processors that issue transactions and a number of main memories configured to store information. Each partition of memories is attached to a system control unit, designated as the home system control unit for that memory partition. Each system control unit is composed of a number of finite state machines (FSMs) that receive the transactions from the processors and execute the transactions in parallel. The transactions may include transmitting requests to other system control units for accesses to their memories and processing requests from the home or other system control units for accesses to its own memory partition.
The method of processing multiple coherent memory accesses in parallel includes the system control unit receiving a transaction from a processor. The system control unit decodes the transaction to determine the corresponding command and locality. The transaction may include command such as xe2x80x9creadxe2x80x9d or xe2x80x9cwrite,xe2x80x9d along with an address specifying the memory location of the data. The system control unit further includes a qualifier that may deny or accept a request received from the processor and a scheduler that assigns each request and transaction to a particular FSM. Each FSM maintains a record or keeps track of the state of progress of a single transaction being executed by the system control unit and executes the transaction until completed. The FSMs keep track of each transaction by storing data related to the transaction, such as the current state of the transaction, the status of the data, and an identifier describing which processor issued the transaction, in a data buffer. Since a different FSM is used to perform each coherent memory access, multiple transactions can be performed in parallel. xe2x80x9cIn parallelxe2x80x9d means that the transaction are being performed simultaneously or the transactions overlap in time. For example, two transactions are performed in parallel if there is a moment in time that the execution of the transactions overlap. Parallel processing of coherence memory accesses using multiple FSMs enhances the speed and efficiency of multi-processor system designs.
Other features and advantages of the present invention will be apparent from the detailed description that follows.
USPTO Backgrounds
USPTO Backgrounds