1. Field
An aspect of the embodiments discussed herein is directed to a method of manufacturing a semiconductor device.
2. Description of the Related Art
A method of manufacturing a conventional semiconductor device is described below.
A transistor including a gate electrode and source/drain diffusion regions is formed on a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate so as to reach over the transistor. A photoresist layer is formed on the interlayer insulating layer. Openings are formed in the photoresist layer by photolithography. Contact holes are formed in the interlayer insulating layer by dry etching so as to reach to the source/drain diffusion regions. Conductive plugs are provided in the contact holes. Interconnects are formed on the interlayer insulating layer so as to be connected to the conductive plugs.
The conventional semiconductor device is manufactured as discussed above.
The packing density of recent semiconductor devices is high; hence, components of the recent semiconductor devices need to have a small size and contact holes need to have a small diameter. The prior arts regarding to the manufacturing method how to form conductive plugs in the insulating layer formed by the nitride layer and the oxide layer are known in the patent documents as follows: Japanese Laid-open Patent Publication No. 2005-136097, Japanese Laid-open Patent Publication No. 2005-229052 and Japanese Laid-open Patent Publication No. 2001-332510.
The reduction in the diameter of contact holes requires precisely forming the contact holes; hence, it is desirable to keep the yield and/or reliability of products high.
USPTO Backgrounds
USPTO Backgrounds