Non-volatile memory devices are in common use today. Such devices are used for storage of data and programming instructions. They are frequently used for the storage of “content” in consumer electronic devices such as music players, telephones, navigation devices and electronic cameras. Most NVMs are configured generally as shown in block diagram form in FIG. 1A. The NVM device 100 of FIG. 1A comprises an NVM memory array 102 as described in more detail below, a controller 104 configured to execute instructions and process write commands and read commands so as to write to and read from memory array 102, and some kind of external interface 106 which may be an electrical circuit supporting communication with a device external to the NVM device 100. The interface may, for example, be a common interface such as Universal Serial Bus, Secure Digital, Compact Flash and the like.
Two common forms of NVM exist. One form is “binary” memory in which data is represented as one single binary bit per memory cell, the bit normally representing a binary “1” or “0”. Another form is multi-level cell (MLC) memory in which one cell is used to store more than one binary bit.
Binary memory cells store charge on a floating gate of a floating gate transistor where different charge distributions correspond to the two different stored bit configurations. FIG. 1B is a charge plot illustrating charge distributions for the two states of such a binary NVM cell. These two configurations or states are illustrated as a “1” (erased) and a “0” (programmed). Note that this is only a convention and a “1” could instead represent a programmed bit and a “0” could likewise represent an erased bit. Accordingly, the 1=erased, 0=programmed convention will be used throughout this disclosure.
MLC memory cells likewise store charge on a floating gate of a floating gate transistor where different charge distributions correspond to different stored bit configurations. For example, in a two-level MLC Flash memory two bits are stored in the cell and the two bits are referred to as an upper page bit (upage) and a lower page bit (lpage). Four charge distributions represent the four possible states of the upper and lower page bits. FIG. 1C is a charge plot illustrating charge distributions for the various states of a 2-bit MLC NVM cell. In FIG. 1C, the four charge distributions are illustrated as a “11”, “10”, “00” and “01”. The “11” state is called the “erased” state. The remaining states are “programmed” states. (As discussed above with respect to binary memories, this is only a convention and while these states are referred to with “1”s and “0”s, it is not required that a “1” always represent a data 1 or that a “0” always represent a data 0. If desired, a “1” and a “0” may be interchanged).
Initially the cell is in the erased state. When the bits are programmed, the distribution is moved from the erased state on the left of FIGS. 1B and 1C to a programmed state on the right. Physically this corresponds to charge being stored on the floating gate. This is normally accomplished using an electron injection mechanism to force channel electrons across an insulator onto the floating gate. Cell erasure is normally achieved through a tunneling mechanism to remove electrons from the floating gate. The transition of a cell from the erased state to a programmed state and back to the erased state is called a “write/erase cycle”. Each write/erase cycle causes “wear” on the cell and once a cell has accumulated enough wear, it may experience a failure mode. A cell already in the erased state experiences little or no wear when repeatedly erased.
It would be desirable to further improve the longevity and reliability of MLC memory cells.
USPTO Backgrounds
USPTO Backgrounds