This invention pertains to semiconductor capacitor constructions and to methods of forming semiconductor capacitor constructions. The invention is thought to have particular significance in application to methods of forming dynamic random access memory (DRAM) cell structures and to DRAM cell structures.
A commonly used semiconductor memory device is a DRAM cell. A DRAM cell generally consists of a capacitor coupled through a transistor to a bitline. A continuous challenge in the semiconductor industry is to increase DRAM circuit density. Accordingly, there is a continuous effort to decrease the size of memory cell components. A limitation on the minimal size of cell components is impacted by the resolution of a photolithographic etch during fabrication of the components. Although this resolution is generally improving, at any given time there is a minimum photolithographic feature dimension obtainable in a fabrication process. It would be desirable to form DRAM components having at least some portion with a cross-sectional dimension of less than a given minimum capable photolithographic feature dimension.
Another continuous trend in the semiconductor industry is to minimize processing steps. Accordingly, it is desirable to utilize common steps for the formation of separate DRAM components. For instance, it is desirable to utilize common steps for the formation of DRAM capacitor structures and DRAM bitline contacts.
The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; methods of forming capacitor and bitline constructions; DRAM memory cell constructions; and capacitor constructions. For instance, the invention encompasses a method wherein a first layer is formed over a node location; a semiconductive material masking layer is formed over the first layer; an opening is etched through the semiconductive material masking layer and first layer to the node location; an upwardly open capacitor storage node layer is formed within the opening and in electrical connection with the masking layer; a capacitor storage node is formed comprising the masking layer and the storage node layer; and a capacitor dielectric layer and outer capacitor plate are formed over the capacitor storage node.
As another example, the invention encompasses a capacitor structure which includes an insulative layer over a substrate and a semiconductive material layer over the insulative layer. The capacitor structure further includes an opening which extends through the semiconductive material layer and the insulative layer to an electrical node, and which comprises an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions. The capacitor further comprises a spacer over the step, and a storage node layer over the spacer, semiconductive material layer and electrical node; wherein the storage node layer physically contacts the semiconductive material layer, the spacer, and the electrical node. Additionally, the capacitor comprises a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.
USPTO Backgrounds
USPTO Backgrounds