Technical Field
The present invention relates generally to amplifier circuits, and in particular to operational transconductance amplifier circuits.
Introduction
Reference is made to FIG. 1 which shows a circuit diagram of a conventional operational transconductance amplifier 100 configured as a non-inverting unity gain buffer.
The amplifier 100 includes differential input stage 101 including a first current source 102 functioning as a tail current source for a differential pair of transistors 104 and 106. The transistors 104 and 106 comprise MOSFET transistors of the n-channel type whose source terminals are connected together at node 108. The first current source 102 is coupled between node 108 a reference node 110 (which in the illustrated circuit comprises circuit ground GND). The gate of transistor 104 is coupled to a non-inverting input terminal IN+ of the amplifier 100. The gate of transistor 106 is coupled to an inverting input terminal IN− of the amplifier 100. The differential input stage 101 further includes a load circuit formed by a pair of MOSFET transistors 114 and 116 of the p-channel type connected in a current mirror configuration. The transistor 114 has a drain terminal coupled to the drain terminal of the transistor 104 at node 120 and a source terminal coupled to a reference node 111 (which in the illustrated circuit comprises a positive supply node VDD). The transistor 116 has a drain terminal coupled to the drain terminal of the transistor 106 at node 122 and a source terminal coupled to the reference node 111. The gates of transistors 114 and 116 are connected together and to the drain terminals of transistors 104 and 114 at node 120. Node 122 forms the output of the differential input stage 101.
The amplifier 100 further includes a single-ended output stage 131. The output stage 131 includes a second current source 134 and a MOSFET transistor 136 of the p-channel type. The second current source 134 and transistor 136 are coupled in series between the reference node 111 and the reference node 110. Specifically, a source terminal of transistor 136 is coupled to the reference node 111, a drain terminal of transistor 136 is coupled to an output node 140, and the second current source 134 is coupled between the output node 140 and the reference node 110. The gate of transistor 136 is coupled to node 122 at the output of the differential input stage 101.
To implement the configuration of the amplifier 100 as a non-inverting unity gain buffer, a shunt connection 144 is made between the output node 140 and the inverting input terminal IN− of the amplifier 100.
A resistor 148 and capacitor 150 are coupled in series between the output node 140 and node 122 to form a Miller compensation network.
A drawback of the amplifier 100 is that it does not respond with a satisfactory current sinking action in response to the application of a current I_sink to the output node 140. The reason for this is that the sinking current I_sink applied to output node 140 is discharged solely by the second current source 134. There is a danger that current source 134 presents an insufficient sink capability, which will result in an undesirable rise in voltage at the output node 140. This rise in voltage at the output node 140 could present a danger to downstream (for example, next stage) circuitry that is coupled to the output node.
A need exists in the art for an improved single-ended output stage circuit with enhanced current sinking capabilities.
USPTO Backgrounds
USPTO Backgrounds