1. Field of the Invention
The present invention relates to a column address strobe (CAS) latency circuit and a semiconductor memory device including the same, and more particularly, but without limitation, to a CAS latency circuit that generates a stable latency signal in a high-speed semiconductor memory device and a semiconductor memory device including the CAS latency circuit.
2. Description of the Related Art
Semiconductor memory devices are synchronized with externally-applied clocks and input/output data. Semiconductor memory devices can establish in advance which clock cycle outputs valid data after receiving a request from a controller to read data.
Column address strobe (CAS) latency is the number of external clock cycles that elapse from the time the request to read data or column address is sent to a memory device until the data is output. In other words, the memory device receives the request for data and outputs the data after a number of clock cycles defined by the CAS latency (CL).
FIG. 1 is a circuit diagram of a conventional CAS latency circuit 10 that generates a latency signal LATENCY. Referring to FIG. 1, the CAS latency circuit 10 can include at least one flip-flops 11_1 through 11_4 and at least one signal delay units 12_1 through 12_3.
The latency signal LATENCY is generated by latching an internal read command signal PREAD. Each flip-flop 11_1 through 11_4 receives a corresponding one of clock signals platclk_1 through platclk_4 at a clock input terminal. The clock signal platclk_1 through platclk_4 can be generated by delaying an output clock CLKDQ.
The CAS latency circuit 10 outputs the latency signal LATENCY when CAS latency (CL) is set to 4. The internal read command signal PREAD is input at the flip-flop 11_1 and latched by a rising edge of the clock signal platclk_1. An output signal of the flip-flop 11_1 is input to the flip-flop 11_2 and latched by a rising edge of the clock signal platclk_2. The internal read command signal PREAD is latched four times through the above process so that the CAS latency circuit 10 outputs the latency signal LATENCY.
FIG. 2 is a waveform diagram of the operation of the CAS latency circuit 10 illustrated in FIG. 1. Waveforms of an external clock CLK, an internal clock INTCLK, and a phase delay locked loop PDLL clock are illustrated in FIG. 2. The internal clock INTCLK is generated in response to a point A of the external clock CLK and delayed compared to the external clock CLK by a predetermined period of time. The phase delay locked loop PDLL clock is generated in response to a point B of the external clock CLK and a phase thereof precedes that of the internal clock INTCLK by a predetermined period of time.
A pulse width of the internal read command signal PREAD corresponds to a period of the external clock CLK. The output clock CLKDQ is generated in response to the phase delay locked loop PDLL clock and has the same frequency as the external clock CLK.
In the CAS latency circuit 10, the internal read command signal PREAD is latched by the rising edges of the clock signals platclk_1 through platclk_4 that are generated by delaying the output clock CLKDQ. However, the faster the speed of a semiconductor memory device becomes, the more the frequency of the external clock CLK increases, making a time interval between the points A and B shorter.
In order to stably output the latency signal LATENCY, the internal read command signal PREAD must be stably latched by the output clock CLKDQ and signals that are generated by delaying the output clock CLKDQ. However, the more the frequency of the external clock CLK increases, the more the margin between the internal read command signal PREAD and the output clock CLKDQ reduces. In detail, the increase in the frequency of the external clock CLK results in a reduction in the pulse width of the internal read command signal PREAD and precedence of the phase of the output clock CLKDQ to the pulse width of the internal read command signal PREAD. Since the internal read command signal PREAD is a clock domain and the output clock CLKDQ is a delay locked loop (DLL) clock domain, a skew between the two domains is influenced by a clock frequency, a surrounding pressure, temperature, or the like.
As addressed above, the internal read command signal PREAD is not properly latched due to the reduced margin between the internal read command signal PREAD and the output clock CLKDQ or the precedence of the phase of the output clock CLKDQ to the pulse width of the internal read command signal PREAD, making a proper counting based on the CAS latency (CL) impossible. Although the internal read command signal PREAD can be latched by the clock signals platclk_1 through platclk_4 that are generated by delaying the output clock CLKDQ for a predetermined period of time using the signal delay units 12_1 through 12_3 as shown in FIG. 1, there is a limit to sufficiently delaying a high frequency signal used by a high-speed semiconductor memory device.
USPTO Backgrounds
USPTO Backgrounds