The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
Conventional IC processing often involves performing one or more implantation processes on a substrate (or wafer). For example, each implantation process may involve forming a photoresist layer; patterning the photoresist layer to form an implantation pattern; and performing the implantation process. It is often desired for each implantation pattern to be associated with a different critical dimension. Thus, for each implantation process performed, a separate patterning and masking process is utilized to form the desired critical dimension. It has been observed that the traditional processes for performing one or more implantation processes associated with varying critical dimensions is less cost-effective than desirable. Further, traditional processes present difficulty in adequately decreasing (or shrinking) spacing (i.e., the critical dimension).
Accordingly, what is needed is a method for manufacturing an integrated circuit device that addresses the above stated issues.
USPTO Backgrounds
USPTO Backgrounds