In related art, an imaging device is assembled as a module in which two chips, which are a CMOS image sensor (CIS) chip and an image processor chip, are respectively mounted on packages.
Alternatively, the chips may be mounted chip-on-board (COB).
Recently, there has been a need for reduction in mounting areas and in size for mounting an imaging device on a cellular phone or the like, and a System on Chip (SOC) that integrates the two chips on one chip has been developed (see FIG. 2(A)).
A process combining a CIS process and a high-speed logic process for integration on one chip, however, results in an increase in the number of processes and high cost, and moreover, it is difficult for such process to produce both analog characteristics and logic characteristics, which may cause degradation in the characteristics of the imaging device.
In this regard, methods for assembling the two chips at the chip level while both reducing the size and improving the characteristics are proposed (see Patent Literatures 1 and 2).
Patent Literatures
Patent Literature 1: Japanese Patent Application Laid-Open No. 2004-146816
Patent Literature 2: Japanese Patent Application Laid-Open No. 2008-85755
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