1. Field of the Invention
The present invention refers to a direct-comparison reading circuit for a nonvolatile memory array.
2. Description of the Related Art
It is known that the circuits traditionally used for reading nonvolatile memory cells, wherein the current flowing in selected memory cells and the current flowing in a reference cell are compared by current-mirror architectures, present considerable limits of use in presence of low supply voltages or whenever a particularly high reading speed is required.
To overcome the above limits, it has recently been proposed to use direct-comparison reading circuits (the so-called dynamic sense circuits) which enable lower access times to be achieved and, moreover, low supply voltages to be used. In this type of reading circuits, array bit lines, connected to respective selected array memory cells to be read, and a reference bit line connected to a reference cell, are initially brought to a preset precharge voltage through a precharge circuit. The array capacitance and the reference capacitance, respectively associated to each of the array bit lines and to the reference bit line, are thus charged at the same precharge voltage. In addition, a read voltage is supplied to the gate terminals of the array cells and of the reference cell.
Subsequently, the precharge circuit is disconnected, and the array and reference capacitances are discharged via the array cells and the reference cell to which they are respectively connected. In this phase, programmed array cells (ie., ones having a high threshold voltage) conduct a practically zero current, and consequently discharging of the associated capacitances takes place very slowly. Erased array cells (which have a low threshold voltage) are instead on and enable fast discharge of the capacitances connected thereto. The discharge speed of the reference capacitance is intermediate with respect to the above two cases, since the reference bit line is designed to conduct a current equal to approximately one half of the cell current.
Consequently, the voltage on the reference bit line is always higher than the voltages on the array bit lines connected to erased array cells, and always lower than the voltages on the array bit lines connected to programmed array cells.
The voltages on the array bit lines are then compared with the voltage on the reference bit line using respective comparators. In this way, the logic values at the outputs of the comparators are correlated to the logic values stored in the cells associated to the comparators.
Since no current mirrors are used to compare the currents flowing in the array cells and in the reference cells, direct-comparison reading circuits can operate with lower supply voltages than in traditional reading circuits and, moreover, have shorter access times and lower consumption.
However, known direct-comparison reading circuits have certain drawbacks, mainly on account of the capacitive mismatching between the array bit lines and the reference bit line. In fact, since a same voltage should be present on all the array bit lines and on the reference bit line at the start of the discharge phase (reading), it is necessary to carry out an equalization. Equalization is normally obtained by connecting each array bit line to the reference bit line through a respective equalization switch. Therefore, the reference bit line is associated not only to the capacitance of a single array bit line, but also the capacitances connected to all the equalization switches, even if the latter are open. In addition, the reference bit line is connected to all the comparators, which affect the operation due to their respective input capacitances. Consequently, discharge of the reference bit line takes place more slowly than expected, and errors may occur when reading erased cells (also these discharge slowly).
In addition, also regulation of the precharge voltage is problematic. Normally, in fact, a regulating circuit is used which is connected to all the array bit lines and to the reference bit line. In this case, oscillations of the precharge voltage may be set up, due to the various lines reaching the precharge voltage according to different transients. Alternatively, precharging is performed for a preset time interval, without feedback control. In this case, an imprecision in the precharge time may lead to a non-optimal precharge voltage.
An embodiment of the present invention provides a reading circuit free from the above described drawbacks.
An embodiment of the invention provides a direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and a bit line. The reading circuit includes: an array line, selectively connectable to the bit line; a reference line; a precharging circuit for precharging the array line and the reference line at a preset precharging potential; a comparator having a first terminal connected to the array line and a second terminal connected to the reference line; and equalization means for equalizing potentials of the array line and reference line in a precharging step. The equalization means include an equalization line distinct from the reference line and controlled connection means for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line (from the array line and from the reference line, at the end of the precharging step.
USPTO Backgrounds
USPTO Backgrounds