Flash memory device cells are used widely in the industry as memory storage. The flash memory device cell must be able to program, erase and retain charge on its floating gate. During program or erase the flash memory device cell is subject to high electric field to support oxide tunneling and hot electron injection. Those are the mechanisms that may cause reliability failure. Most of the available digital integrated circuits (IC) operate on rail-to-rail logic, flash memory device operation is distinctively analog. The digitally stored information induces analog distribution of the threshold voltage for read operations. In multi-level flash memory device cells, multiple bits are stored by precise placement of threshold voltage in each cell. The readout of the threshold voltage requires precise placement of the sense amplifier decision threshold.
The voltage programming and readout are statistical, and there is therefore a probability of error in each decision. The use of error correction codes (ECC) enables reduction of the error rate to an acceptable value, e.g. 10−15.
There are currently three common methods of programming flash memory device memory: channel electron ejection, Fowler-Nordhiem (F-N) tunneling from the source or drain, and F-N tunneling from the channel. There are also three common methods for erasing data from the flash memory device memory: F-N tunneling through the channel, F-N tunneling through the source or drain, and F-N tunneling to the floating gate. These techniques, however, require a high electric field in the oxide and may create traps and leakage current.
The result of performing program and erase (P/E) cycles with a fixed set of flash memory device parameters may be highly inefficient. Currently known flash memory device s may be using a single set of program and erase parameters to control the desired program distribution. A significant increase of cycle count for a given margin may be obtained by adapting program and erase parameters to the effective endurance state of the flash memory device.
Another effect of the P/E cycles is the increase of the threshold variance. As the number of cycles increases, the number of traps also increases. The average number of traps reduces the threshold window as discussed above. However, it also increases the threshold variance for every level in the program. The relation to the number of cycles is derived, for example, in an empirical model described in: Mielke, N. Belgal, H. Kalastirsky, I. Kalavade, P. Kurtz, A. Meng, Q. Righos, N. Wu, J. “flash memory device EEPROM Threshold Instabilities Due to Charge Trapping During Programming and/or erase Cycling”. IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3, September 2004, p 335-344, which is incorporated herein in its entirety by reference. The bit error rate of a given flash memory device memory may be related to the threshold voltage window and to the threshold voltage variance at the highest cycle count.
The probability of error may be approximated in different ways, as to allow analytical modelling of the flash memory device cells. One approximation for calculating the probability of error is a Gaussian distribution of the threshold voltage: Where:
The minimum threshold voltage window and the maximum threshold voltage variance may be measured at the maximum cycle counts of a given device (100,000 at Single Level Cell, 1,000 at Multi-Level Cell and 1,000 at 3 bits per cell). The device bit error rate (BER) may therefore not be constant with respect to the cycle count and the numbers of errors may constantly increase as the number of cycle increases. The flash memory device memory controller ECC is designed to correct the highest number of errors at the maximum number of cycles.
There is a growing need to provide computer readable media, methods and systems for increasing the lifespan of flash memory devices.
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