Non-volatile memories such as NAND and NOR flash memories store information in a grid or array of memory cells. Generally, each cell stores a single bit, although some designs enable storage of multiple bits per cell. For example, various state-of-art flash memory architectures may be configured to hold one of 2n levels in a cell, thereby effectively storing n bits of data per cell. Alternatively, some non-volatile memory architectures such as NROM store charges on both drain side and source side, and may therefore contain two bits per cell.
FIG. 1 shows a cross-sectional view of a conventional nonvolatile memory transistor 10 with a floating gate 12. Transistor 10 represents a single cell, configured to store one or more states representable as binary values (e.g., “1” or “0”). Nonvolatile memory cell 10 includes a control gate 14, gate oxide 16, floating gate 12, tunnel oxide 18, source/drain terminals 20a and 20b, and channel 22. The control gate 14 and source/drain terminals 20a and 20b each have an electrode (24 and 26a-26b, respectively) in electrical communication therewith. Programming, reading and erasing operations are all well-known to those skilled in the art. In a flash memory, the erase operation is performed on a large number of cells (e.g., a block, page or other array) simultaneously. The presence, absence or quantity of charge on the floating gate 12 changes the effective threshold voltage of the control gate 14. Reading the state of the memory cell is done by driving the control gate 14 with an appropriate voltage and measuring the resulting current across the source/drain terminals 20a and 20b, as is known in the art.
In one multi-bit nonvolatile memory architecture, the quantity of charge stored on the floating gate determines the threshold voltage of the cell and/or the amount of current that can pass through channel 22. Detection of this threshold voltage and/or current determines the state or level of the cell. During the lifespan of a non-volatile memory, the threshold voltage may change from an initial programmed value due to disturbances in the non-volatile memory transistor. To track such changes in threshold voltage and therefore minimize errors when reading back the memory, reference cells are often used. Reference cells (also known as pilot cells) refer to memory cells at pre-defined locations in an array. A pilot cell in such a multi-bit memory is typically not used for data storage, although it typically has the same physical structure as data storage cells. Rather, the pilot cell may provide a reference voltage, current or level by which the value of a data storage cell can be determined, generally by estimating the non-linear gain and/or offset of the data storage cell. As a result, each pilot cell generally has a single known or predetermined level.
FIGS. 2A-2B compare exemplary voltage levels of conventional regular data storage cells (FIG. 2A) with that of a pilot cell (FIG. 2B). For example, as shown in FIG. 2A, data storage cells may have one of 16 different levels 31-46. In contrast, the pilot cells are generally allowed to have only a single value (e.g., level 50).
Increasingly, nonvolatile memory is used for bulk data storage (e.g., flash memory cards or memory “sticks” having a data storage capacity of 256 Mb, 1 Gb or more). In such devices (and others), the cells may be defective as a result of errors in the manufacturing or) packaging process, or they may become defective after a number of write and read cycles. Defective cells can cause problems during write and/or read processes in nonvolatile memories. Basically, information stored in defective cells may become distorted. To recover information from defective cells, a memory controller or other type of controller/processor (e.g., an encoder and/or decoder) may use an error correction code (ECC); a sophisticated defect management scheme, or both. However, such codes and schemes have limitations and/or inefficiencies.
It is therefore desirable to know which cells in a nonvolatile memory are defective, to enable use of that information either to avoid reading from and/or writing to those positions, or to indicate some status information regarding data stored in such defective cells to facilitate error recovery. Knowing the position(s) of defective cells may thus enhance the reliability and/or increase the storage efficiency of non-volatile memories. In addition, knowing the location of data from defective cells can increase error correction capability and/or efficiency, and enable use of error correction capability in a system for correction of other errors (e.g., transmission errors resulting from channel noise or interference, etc.).
USPTO Backgrounds
USPTO Backgrounds