Semiconductor memory devices are used extensively to store data. Volatile memory such as Static and Dynamic Random Access Memory (SRAM and DRAM, respectively) are widely used in many applications. However, volatile memory loses its data when power is not continuously supplied.
DRAM based on the electrically floating body effect has been proposed (see, for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 (“Okhonin-1”), which is incorporated by reference herein in its entirety and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002) (“Ohsawa-1”), which is incorporated by reference herein in its entirety). Such a memory eliminates the capacitor used in conventional one transistor, one capacitor (1T/1C) memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Both Okhonin-1 and Ohsawa-1 describe a DRAM memory cell comprising a single standard metal-oxide-semiconductor field effect transistor (MOSFET) having a gate terminal, two source/drain terminals, and a floating body fabricated using silicon-on-insulator (SOI) complimentary metal-oxide-semiconductor (CMOS) technology. Ohsawa-1 further describes a current mirror sense amplifier which compares the current of a sensed cell to the average of two reference cells, one written to logic-0 and the other written to logic-1.
It would be desirable to provide memory devices having improved read operations to what is currently known.
It would further be desirable to provide such memory devices having a size that is not prohibitively larger than comparable volatile memory devices.
The present invention meets all of the above desires and more.
USPTO Backgrounds
USPTO Backgrounds