1. Field of the Invention
This invention relates to a semiconductor memory device having a configuration for suppressing an increase in a leakage current caused by a short circuit fault between a bit line and a word line.
2. Related Art
In general DRAM, it is particularly desired to reduce current flowing when the DRAM is in standby mode. One problem arising in the DRAM in standby mode is an increase in leakage current caused by a short circuit fault between a bit line and a word line. It is general to adopt a configuration provided with redundancy cells to rectify faults occurring in normal memory cells in the conventional DRAM. By such a configuration, it is possible to replace faulty cells each of which has the short circuit fault occurring between the bit line and the word line with the redundancy cells. However, even when the faulty cells changes to non-faulty cells by replacing with the redundancy cells, the leakage current caused by the short circuit fault between the bit line and the word line still flows in standby mode, and is a cause of decreasing the yield.
A method has been proposed for reducing the leakage current caused by the short circuit fault between the bit line and the word line as described above (for example, see JP 3280223). FIG. 10 shows an example of a circuit configuration of DRAM adopting such a method. In the circuit configuration as shown in FIG. 10, an equalizing circuit 50 connected to bit line pair BLT and BLN, and a current limit element 51 which limits the current flowing from a bit line pre-charge voltage VHB to the equalizing circuit 50 are provided. The equalizing circuit 50 includes three NMOS transistors each having a gate to which a control signal EQ is applied. The current limit element 51 includes a PMOS transistor TP10 having a drain connected to node N10 of the equalizing circuit 50.
The PMOS transistor TP10 has a source to which the bit line pre-charge voltage VHB is applied and a gate to which a constant voltage V0 is applied. Further, a back bias voltage VPP is applied to an N-well in which the PMOS transistor TP10 is formed. In such a state, when equalizing operation is performed in the equalizing circuit 50, the current flowing into the bit line pair BLT and BLN through the equalizing circuit 50 is limited by the current flowing through the PMOS transistor TP10. By setting the voltage V0 properly, even when the short circuit fault occurs between the bit line and the word line, it is possible to set a desired limiting current corresponding to characteristics of the PMOS transistor TP10.
However, in the configuration of FIG. 10, when the constant voltage V0 is applied to the gate of the PMOS transistor TP10, it becomes a problem that the limiting current fluctuates with changes in the threshold voltage of the PMOS transistor TP10. FIG. 11 shows an example of subthreshold characteristics of the PMOS transistor TP10 of FIG. 10. In FIG. 11, a graph shows the relationship between the gate-source voltage VGS and the drain current IDS in the PMOS transistor TP10. Since the drain current IDS fluctuates exponentially in a threshold region, the logarithm of the absolute value |IDS| is plotted on the vertical axis. In this case, it is understood that |IDS| changes by about one digit when VGS changes by 0.1V. Herein, the threshold voltage Vtp of the PMOS transistor is defined as VGS when |IDS| is 1.0 μA. Generally, the threshold voltage Vtp of the PMOS transistor changes by about 0.2 V with a temperature fluctuation of 100° C., and further changes with fluctuations in manufacturing.
In FIG. 11, three different characteristics C1, C2 and C3 are compared with each other, taking the fluctuation of threshold voltage Vtp into consideration. The characteristic C1 corresponding to Vtp=−1.0 V to be used as a basis shifts to the characteristic C2 in the case that the absolute value of Vtp decreases (Vtp=−0.9 V), and shifts to the characteristic C3 in the case that the absolute value of Vtp increases (Vtp=−1.1 V). As shown in FIG. 11, |IDS|=1.0 μA is satisfied in the characteristic C1 (operation point A1) on condition that VGS=−1.0 V. For example, in the circuit configuration of FIG. 10, settings of VHB=0.6 V and V0=−0.4 V are assumed. Then, using the operation point A1 of the characteristic C1 to be used as a basis, if changes in the above-described threshold voltage Vtp are assumed in the PMOS transistor, |IDS|=10 μA is satisfied in the characteristic C2 (operation point A2) and |IDS|=0.1 μA is satisfied in the characteristic C3 (operation point A3), on the same condition of VGS=−1.0 V.
Thus, as a result of extremely large changes of operation points A1, A2 and A3, the limiting current set for the current limit element 51 also changes largely. In FIG. 10, even when the same voltage condition is set, it is unavoidable that the threshold voltage Vtp of the PMOS transistor TP10 changes with temperature and fluctuations in manufacturing, and it is a risk that it is made impossible to suppress the influence of the leakage current caused by the short circuit fault between the bit line and the word line.
USPTO Backgrounds
USPTO Backgrounds