1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory cell, and more particularly to a method of manufacturing a flash memory cell capable of preventing a poor coverage due to undulations in the structure caused by the floating gates.
2. Description of the Prior Art
In general, a flash memory cell includes a floating gate and a control gate both of which are stacked on a channel region of a semiconductor substrate, and a junction region formed in the semiconductor substrate at both sides of the floating gate, which is constructed to be programmed as hot electrons are injected into the floating gate, or to be erased as the injected electrons are discharged, depending on a bias voltage condition applied to the control and the junction region.
A method of manufacturing a conventional flash memory cell constructed as above will be below explained by reference to FIG. 1.
A tunnel oxide film 3 and a polysilicon layer 4 are sequentially formed on a semiconductor substrate 1 in which a device separation film 2 is formed and are then patterned to form a floating gate 4. After a dielectric film 5 consisting of an oxide film, a nitride film and an oxide film is formed on the entire structure, a polysilicon layer 6 is formed on the dielectric film 5. Then, a tungsten silicide layer 7 is formed on the polysilicon layer 6. Next, the tungsten silicide layer 7, the polysilicon layer 6 and the dielectric film 5 are sequentially patterned to form a control gate consisted of the polysilicon layer 6 and the tungsten silicide layer 7. Thereafter, impurity ions are injected into the semiconductor substrate 1 at both sides of the exposed floating gates 4 to form a junction region (not shown).
If the above-mentioned conventional method is used, the coverage of the dielectric film 5, the polysilicon layer 6 and the tungsten silicide layer 7 becomes poor due to the floating gates shown at 4.
This poor coverage becomes severe as the distance between the neighboring floating gates 4 is reduced by reduction in the size of the memory cell. At its worst case, voids 8 are generated as the polysilicon layer 6 and the tungsten silicide layer 7 are deposited, thus increasing the self-resistance (Rs) of the floating gate.
In order to prevent generation of the voids 8, it is required that the thickness of the polysilicon layer constituting the floating gates 4 be thinner and the distance between the floating gates 4 must be increased. Reduction in the thickness of the floating gates 4, however, causes a change in the capacitance of the memory cell. Also, it is difficult to reduce the distance between the floating gates 4 since it is affected by a design rule and a lithography process. Therefore, there is a need for a new process development.
A method of manufacturing a flash memory cell capable of solving the aforenoted problem is disclosed whereby a floating gate is formed between oxide film patterns using a damascene pattern and then the thickness of the oxide film patterns is reduced, so that the thickness undulations in the structure of the cell caused by the of the floating gates can be reduced.
A method of manufacturing a flash memory cell comprises the steps of forming an oxide film on a semiconductor substrate in which a device separation film is formed and then patterning the oxide film to expose the semiconductor substrate at a portion in which a floating gate will be formed; sequentially forming a tunnel oxide film and a first polysilicon layer on the entire structure, and then flattening the first polysilicon layer until the tunnel oxide film is exposed to form a floating gate; etching the tunnel oxide film and the oxide film in the exposed portion to a given thickness and the forming a dielectric film on the entire structure; sequentially forming a second polysilicon layer, a tungsten silicide layer and a hard mask and then patterning them to form a control gate; and injecting impurity ions into the semiconductor substrate at the both sides of the floating gate to form a junction region.
The oxide film is one of a high temperature oxide film or a high-density plasma oxide film. The flattening process is performed by chemical mechanical polishing process or by spin wet etching process using rotation. The tunnel oxide film and the oxide film in the exposed portion are etched more than 20% of the thickness of the floating gate.
USPTO Backgrounds
USPTO Backgrounds