With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and have increased device density. To accomplish this, devices with aggressive scaling and multiple-layered devices with transistor cells arranged in horizontal and vertical arrays have been under development.
In one approach, planar memory cells, for example NAND memory cells, are formed in a conventional horizontal array. Multiple horizontal arrays are then stacked in a vertical direction. Limitations associated with this approach include poor reliability in the resulting device, since critical lithography steps are required for each layer in achieving the minimum feature size. In addition, in this configuration, the size of the driver transistors for driving the control gates is a function of the number of layers; therefore, the driver transistors are scaled as a multiple of the number of layers. This can lead to integration issues and heat removal concerns.
In another approach, multiple-layered memory devices with vertically oriented channels have been under development. In one configuration, a plurality of gate layers are formed on a substrate, and a vertical channel penetrates the plurality of gate layers. In each vertical channel, a lower gate layer is configured to operate as a lower select gate, a plurality of middle gate layers are configured to operate as control gates, and an upper gate layer is configured to operate as an upper select gate. Upper select gates neighboring each other in a first horizontal direction are connected to operate as row selection lines for the device. Vertical channels neighboring each other are connected in a second horizontal direction to operate as bit lines for the device.
Others attempting the vertically oriented channel approach have met with limited success. In one configuration, vertical edge surfaces of the lower and upper select gates are isolated from the vertical channel using a conventional oxide layer, while vertical edge surfaces of the control gates of the middle gate layers are isolated from the vertical channel using an ONO-type charge trapping layer, in an attempt to form floating-gate type non-volatile memory devices. However, a floating gate is difficult to achieve under this approach.
In addition, others have attempted the vertically oriented channel approach using a poly-silicon vertical channel region. Grain boundaries in a poly-silicon vertical channel lead are associated with crystalline defects, which can increase resistance and form trap sites in the resulting structure. This can lead to increased resistance in the resulting device, which can decrease device speed and increase device power consumption.
Also, others attempting the vertically oriented channel approach have formed the tunnel oxide layer of the ONO charge-trapping layer using a CVD-formed tunnel oxide. Tunnel oxide formed in this manner can quickly degrade over time, leading to poor device reliability and poor device endurance.
USPTO Backgrounds
USPTO Backgrounds