1. Field of the Disclosure
The present disclosure relate to an in-plane switching (IPS) mode liquid crystal display (LCD) device, and more particularly, to an array substrate for an IPS mode LCD device and a fabrication method for the array substrate having a higher quality image display and improved aperture ratio.
2. Discussion of the Related Art
A conventional LCD device uses an optical anisotropic property and polarization properties of liquid crystal molecules to display images. The liquid crystal molecules have orientation characteristics related to the arrangement of multiple molecules that result from their thin and long shape. The arrangement of liquid crystal molecules, and their direction may be controlled by applying an electrical field to them. Accordingly, when the electric field is applied to the liquid crystal molecules, the polarization properties of light are changed based on the arrangement of the liquid crystal molecules, which enables an LCD device to display images.
Among the common type of LCD devices, are active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) arranged in a matrix form. Active matrix LCD devices are subject to relatively significant research and development because of their high resolution and superior ability in displaying moving images.
The LCD device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. A common electrode and a pixel electrode are respectively formed on the first and second substrates. The first and second substrates may be referred to as a color substrate and an array substrate, respectively. The liquid crystal layer is driven by a vertical electric field induced between the common and pixel electrodes. Although, LCD devices tend to have good transmittance and aperture ratios, LCD devices using a vertical electric field have a narrow viewing angle. An IPS mode LCD device may have a wider viewing angle.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the IPS mode LCD device 1 includes an array substrate AS, a color filter substrate CS and a liquid crystal layer LC. The array substrate AS and the color filter substrate CS are adjacent one another, and the liquid crystal layer LC is interposed therebetween. The array substrate AS includes a first substrate 10 including a pixel region P, a thin film transistor (TFT) T, a plurality of common electrodes 30 and a plurality of pixel electrodes 32. The TFT T, the plurality of common electrodes 30 and the plurality of pixel electrodes 32 are formed at the pixel region P. The TFT T is disposed at the pixel region P and includes a gate electrode 14, a semiconductor layer 18, a source electrode 20 and a drain electrode 22. The source and drain electrodes 20 and 22 are spaced apart from one another. The plurality of common electrodes 30 and the plurality of pixel electrodes 32 are formed on the same layer. The plurality of common electrodes 30 and the plurality of pixel electrodes 32 are parallel to and arranged to alternate with one another.
Although not shown, a gate line connected to the gate electrode 14 is formed along a first direction on the first substrate 10, and a data line is connected to the source electrode 20 along a second direction on the first substrate 10. The gate line crosses the data line to define the pixel region P. In addition, a common line, which is connected to the plurality of common electrodes 30 and parallel to the gate line, is formed along a first direction on the first substrate 10.
The color filter substrate CS includes a second substrate 40, a black matrix 42 and a color filter layer 34. The black matrix 42 shields portions except for the plurality of pixel regions P. The color filter layer 34 is formed on the black matrix 42 and corresponds to the plurality of pixel regions P. Particularly, the color filter layer 34 including a red sub-color filter 34a, a green sub-color filter 34b and a blue sub-color filter (not shown). The liquid crystal layer LC is driven by a horizontal electric field 45 induced between each common electrode 30 and each pixel electrode 32.
FIG. 2 is a schematic plan view of an array substrate for an IPS mode LCD device according to the related art. The array substrate in FIG. 2 is fabricated through a four mask process. As shown in FIG. 2, a gate line 54 along a first direction is formed on a substrate 50, and a data line 92 along a second direction is formed on the substrate 50. The gate line 54 crosses the data line 92 to define a pixel region P. A gate pad 56 is disposed at one end of the gate line 54, and a data pad 94 is disposed at one end of the data line 92. A common line 58 is formed to be parallel with and spaced apart from the gate line 54. A gate pad terminal GP contacting the gate pad 56 is disposed on the gate pad 56, and a data pad terminal DP contacting the data pad 94 is disposed on the data pad 94.
A TFT T including a gate electrode 52, an active layer 84, an ohmic contact layer (not shown), a source electrode 88 and a drain electrode 90 are disposed at a crossing of the gate and data lines 54 and 92. The gate electrode 52 is connected to the gate line 54. The active layer 84 is disposed at the gate electrode 52, and the ohmic contact layer (not shown) is disposed at the active layer 84. The source and drain electrodes 88 and 90 are disposed at the ohmic contact layer (not shown) and the source and drain electrodes 88 and 90 are spaced apart from each other. The source electrode 88 is connected to the data line 92. A plurality of pixel electrodes 99 connected to the drain electrode 90 are disposed at the pixel region P. A plurality of common electrodes 97 connected to the common line 58 are disposed at the pixel region P. The plurality of pixel electrodes 99 are alternately arranged with the plurality of common electrodes 97.
Since the source electrode 88, the drain electrode 90, the data line 92 and the active layer 84 are formed using a single mask, they have the same shape. As a result, an intrinsic amorphous silicon layer 72 which extends the active layer 84 protrudes beyond the source electrode 88, the drain electrode 90 and the data line 92. The intrinsic amorphous silicon layer 72 and the active layer 84 are exposed by light to generate a photo-current. The photo-current may cause an off current in the TFT T such that a property of the TFT T is degraded. In addition, the light leakage current may cause a coupling of signals in the data line 92 and the pixel electrode 99, which may generate deterioration of displayed images, including a wavy noise on an image. As discussed above, as a result of the source electrode 88, the drain electrode 90, the data line 92 and the active layer 84 being formed using a single mask, the off current and resulting image defect may be generated.
FIGS. 3A to 3H, FIGS. 4A to 4H, FIGS. 5A to 5H, FIGS. 6A to 6H are schematic cross-sectional views taken along lines “III-III,” “IV-IV,” “V-V,” “VI-VI” of FIG. 2, respectively, showing a fabricating process of an array substrate for an IPS mode LCD device according the related art.
FIGS. 3A, 4A, 5A and 6A show a first mask process. As shown in FIGS. 3A, 4A, 5A and 6A, a substrate 50 includes a pixel region P including a switching region S, a gate region GA, a data region DA and a common signal region CA. A gate line (not shown), a gate pad 56 and a gate electrode 52 are formed on the substrate 50. The gate pad 56 is formed in the gate region GA and disposed at one end of the gate line. The gate electrode 52 is connected to the gate line and disposed in the switching region S. A common line, which is parallel to and spaced apart from the gate line, is formed in the common signal region CA.
FIGS. 3B to 3F, 4B to 4F, 5B to 5F and 6B to 6F show a second mask process. As shown in FIGS. 3B, 4B, 5B and 6B, a gate insulating layer 60, an intrinsic amorphous silicon (a-Si:H) layer 62, an impurity-doped amorphous silicon (n+ or p+ a-Si:H) layer 64 and a first conductive metal layer 66 are sequentially formed on the substrate 50 including the gate electrode 52, the gate line, the gate pad 56 and the common line 58. A photosensitive material layer 68 is formed on the first conductive metal layer 66 by coating a photoresist. Then, a mask M having a transmitting area TA, a shielding area SA and a half-transmitting area HTA is disposed over the photosensitive material layer 68.
The transmitting area TA has a relatively high transmittance so that light through the transmitting portion TA can change the chemical characteristics of the photosensitive material layer 68. The shielding area SA shields light completely. The half-transmitting area HTA has a slit structure or a half-transmitting film so that the intensity or transmittance of light through the half-transmitting area HTA may be lowered. As a result, a transmittance of the half-transmitting area HTA is smaller than that of the transmitting area TA and is greater than that of the shielding area SA. The half-transmitting area HTA with shielding areas SA at both sides of the half-transmitting area HTA corresponds to the switching region S as in FIG. 3B. One of the shielding areas SA shields a portion of the pixel region P. The transmitting area TA corresponds to the other portion of the pixel region P and the gate region GA. The shielding area SA corresponds to the data region DA as in FIG. 4B. The photosensitive material layer 68 is exposed to light through the mask M.
As shown in FIGS. 3C, 4C, 5C and 6C, the photosensitive material layer 68 (of FIGS. 3B, 4B, 5B and 6B) is developed to form first and second photosensitive patterns 70a and 70b in the switching region S and the data region DA, respectively. The first photosensitive pattern 70a corresponding to the gate electrode 52 has a portion of a relatively lower thickness than other portions. The first conductive metal layer 66 is exposed through the first and second photosensitive patterns 70a and 70b. The first conductive metal layer 66, the impurity-doped amorphous silicon layer 64 and the intrinsic amorphous silicon layer 62 are etched using the first and second photosensitive patterns 70a and 70b as an etching mask. For example, after the first conductive metal layer 66 is etched, the impurity-doped amorphous silicon layer 64 and the intrinsic amorphous silicon layer 62 may be etched using a dry-etching method. The etching may depend on the type of the first conductive metal layer 66.
As shown in FIGS. 3D, 4D, 5D and 6D, a first semiconductor pattern 76 including an intrinsic amorphous silicon pattern 72 and an impurity-doped amorphous silicon pattern 74 and a first metal pattern 78 are formed in the switching region S under the first photosensitive pattern 70a. A second semiconductor pattern 80 extending from the first semiconductor pattern 76 and a second metal pattern 82 extending from the first metal pattern 78 are formed in the data region DA under the second photosensitive pattern 70b. Then, the first and second photosensitive patterns 70a and 70b are partially removed.
As shown in FIGS. 3E, 4E, 5E and 6E, the first metal pattern 78 corresponding to the gate electrode 52 and both sides of the first photosensitive pattern 70a is exposed. Likewise, the second metal pattern 82 at both sides of the second photosensitive pattern 70b is also exposed. In particular, a portion of the first photosensitive pattern 70a having a relatively small thickness is completely removed to expose the first metal pattern 78. The other portion of the first photosensitive pattern 70a, and the second photosensitive pattern 70b are partially removed.
As shown in FIGS. 3F, 4F, 5F and 6F, the first metal pattern 78 (of FIG. 3E) exposed through the first photosensitive pattern 70a and the impurity-doped amorphous silicon pattern 74 (of FIG. 3E) under the exposed first metal pattern 78 are etched using the first photosensitive pattern 70a to from an active layer 84, an ohmic contact layer 86, a source electrode 88 and a drain electrode 90. The active layer 84 is disposed on the gate insulating layer 60 and corresponds to the gate electrode 52. The ohmic contact layer 86 is disposed on the active layer 84. The source and drain electrodes 88 and 90 are disposed on the ohmic contact layer 86 and spaced apart from one another. Since the first metal pattern 78 (of FIG. 3E) and the impurity-doped amorphous silicon pattern 74 (of FIG. 3E) are etched to form the source electrode 88, the drain electrode 90 and the ohmic contact layer 86, the active layer 84 is exposed through the source electrode 88, the drain electrode 90 and the ohmic contact layer 86. The exposed active layer 84 is defined as a channel. When the impurity-doped amorphous silicon pattern 74 (of FIG. 3E) is etched, the active layer 84 is over-etched so that impurities do not remain on the active layer 84.
The second metal layer 82 (of FIG. 4E) and the impurity-doped amorphous silicon pattern 74 of a second semiconductor pattern 80 may be etched simultaneously using the second photosensitive pattern 70b to form a data line 94 in the data region DA. The data line 92 crosses the gate line to define the pixel region P. A data pad 94 is formed at one end of the data line 92. The second mask process is finished by removing the first and second photosensitive patterns 70a and 70b. Further, an edge “AT” of the active layer 84 and the intrinsic amorphous silicon pattern 72 is exposed at the source and drain electrodes 88 and 90 and the data line 92.
FIGS. 3G, 4G, 5G and 6G show a third mask process. As shown in FIGS. 3G, 4G, 5G and 6G, a passivation layer 96 is formed on the source electrode 88, the drain electrode 90, the data pad 94 and the data line 92. The passivation layer 96 is patterned to form a drain contact hole 98a, a common line contact hole 98b, a gate pad contact hole 98c and a data line contact hole 98d. The drain contact hole 98a exposes the drain electrode 90, the common line contact hole 98b exposes the common line 58, the gate pad contact hole 98c exposes the gate pad 56, and the data pad contact hole 98d exposes the data pad 94.
FIGS. 3H, 4H, 5H and 6H show a fourth mask process. As shown in FIGS. 3H, 4H, 5H and 6H, a transparent conductive material layer (not shown) is formed on the passivation layer 96. The transparent conductive material layer is etched to form a plurality of pixel electrodes 99 and a plurality of common electrodes 97 in the pixel region P. The plurality of pixel electrodes 99 and the plurality of common electrodes 97 are alternately arranged with one another. The plurality of pixel electrodes 99 are connected to the drain electrode 90 through the drain contact hole 98a (of FIG. 3G). The plurality of common electrodes 97 are connected to the common line 56 through the common line contact hole 98b. A gate pad terminal GP is formed on the gate pad 56, and a data pad terminal DP is formed on the data pad 94. The gate pad terminal GP is connected to the gate pad 56 through the gate pad contact hole 98c. The data pad terminal DP is connected to the data pad 94 through the data pad contact hole 98d. 
Through the above four mask process, the array substrate is fabricated. As discussed above, since the second metal layer, the impurity-doped amorphous silicon layer and the intrinsic amorphous silicon layer are patterned using a single mask, the intrinsic amorphous silicon pattern of the second semiconductor pattern is formed under the data line and may protrude beyond the data line. The protrusion of the intrinsic amorphous silicon pattern may result in an image defect such as a wavy noise. In addition, since the active layer extends from the intrinsic amorphous silicon pattern of the second semiconductor pattern, a portion of the active layer is not covered by the gate electrode. Accordingly, an off current may be generated in the thin film transistor, which may degrade a property of the thin film transistor.
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