The present invention is directed to a memory circuit and, more particularly, a memory circuit having an array of memory cells wherein at least one cell in the array is a reference memory cell.
A print head on a printer (e.g., an ink-jet printer) typically includes a memory circuit located directly on the print head for storing various data. For example, the memory circuit may store data such as the type of ink/toner cartridge being used, the type of printer, the amount of ink/toner used, diagnostic data and the like.
The memory circuit may be an array of memory cells. One such memory array is a floating gate memory array utilizing CMOS EPROM technology. The floating gate memory array is a two-dimensional array of memory cells, wherein each cell may be programmed to store data. An alternative memory array is a fuse memory array.
The memory array may operate as follows. Initially, each data cell is in a native (i.e., unprogrammed) state and therefore corresponds to a digital “0.” The cell is programmed by converting the digital “0” into a digital “1” when a sufficient voltage (e.g., 10 volts) is applied to the cell.
Thus, data may be stored to the memory array by selectively programming cells in the array. In contrast, data may be read from the memory array by applying a second voltage to the cell (e.g., 2.5 volts) and measuring the current generated. The second voltage is not sufficient to write to (i.e., program) the cell. The generated current is compared to a reference current to determine whether a particular cell is programmed or unprogrammed.
Variations in the applied voltage/current throughout the memory circuit may cause inaccuracies that negatively affect the reliability of the circuit. Accordingly, there is a need for a circuit that addresses the variation in the applied voltage/current such that an accurate determination of whether or not a cell has been programmed can be made.
USPTO Backgrounds
USPTO Backgrounds