This application claims priority to S.N. 99400472.9, filed in Europe on Feb. 26, 1999 (TI-27700EU) and S.N. 98402455.4, filed in Europe on Oct. 6, 1998 (TI-28433EU).
The present invention relates to the field of digital signal processors and signal processing systems and, in particular, to a method and apparatus for accessing a memory core multiple time in a single clock cycle.
Signal processing generally refers to the performance of real-time operations on a data stream. Accordingly, typical signal processing applications include or occur in telecommunications, image processing, speech processing and generation, spectrum analysis and audio processing and filtering. In each of these applications, the data stream is generally continuous. Thus, the signal processor must produce results, xe2x80x9cthrough-putxe2x80x9d, at the maximum rate of the data stream.
Conventionally, both analog and digital systems have been utilized to perform many signal processing functions. Analog signal processors, though typically capable of supporting higher through-put rates, are generally limited in terms of their long term accuracy and the complexity of the functions that they can perform. In addition, analog signal processing systems are typically quite inflexible once constructed and, therefore, best suited only to singular application anticipated in their initial design.
A digital signal processor provides the opportunity for enhanced accuracy and flexibility in the performance of operations that are very difficult, if not impracticably complex, to perform in an analog system. Additionally, digital signal processor systems typically offer a greater degree of post-construction flexibility than their analog counterparts, thereby permitting more functionally extensive modifications to be made for subsequent utilization in a wider variety of applications. Consequently, digital signal processing is preferred in many applications.
Within a digital signal processor, a memory wrapper is an interface between a memory core and a sea of gates. A combination of a memory core and a memory wrapper can be considered a memory module. In FIG. 1, a memory interface (10) couples a CPU (12) to a single access memory module (14). Memory module (14) comprises a single bus (16) coupling a single access memory core (18) to a memory wrapper (20). Multiple buses (22) couple memory wrapper (20) to memory interface (10). In a single access memory module, such as memory module (14), only one access is performed in one cycle. In this embodiment, a system clock typically serves as the strobe of the memory core and the memory wrapper serves solely as a bus arbitrator that allows a CPU to perform a single access to the memory core in one cycle.
In accordance with a first aspect of the invention, there is provided an apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle. In one embodiment of the invention, a memory wrapper incorporating self-timing logic and a mux(es) is used to couple a multiple access memory core to a memory interface unit. The memory interface unit couples a central processing unit to the memory wrapper. The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle.
In another embodiment of the invention, a memory core incorporating the self-timing architecture is incorporated directly into the processor core thereby avoiding the need for a memory wrapper and the time delay associated with passing information from the processor core via the memory interface unit and to the memory core. Direct incorporation of a memory core into the processor core facilitates more intensive accessing and additional power savings.
In accordance with a second aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP).
In accordance with a third aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) is further incorporated into an electronic computing system, such as a digital cellular telephone handset.
USPTO Backgrounds
USPTO Backgrounds