The present invention relates to analog delay circuits, and particularly to analog circuits that present an adjustable, or variable, delay between input and output.
1. Field of the Invention
The introduction of a time delay .DELTA. into a digital system has many useful applications. As pointed out by J. Millman, et al in Microelectronics, (McGraw-Hill, 1987) at page 328, where .DELTA. is an integral multiple of a clock T, a shift register having n stages may be employed to delay an input pulse stream by a time (n-1) T=.DELTA..
It is useful that such delay be adjustable, particularly for purposes of intersignal synchronization in logic circuits. However, if the adjustment in .DELTA. must respond to a continuously-variable voltage, or if it must be continuous itself, some or all, of the adjustment must be implemented in analog circuitry. In this regard, reference is given to U.S. Ser. No. 08/856,259, filed May 14, 1997, now U.S. Pat. No. 5,847,621, entitled "LC OSCILLATOR WITH DELAY TUNING", in which continuously-variable delay is used for tuning the frequency of a voltage-controlled oscillator (VCO). As is known, a VCO is a necessary component of a phase-locked loop. Therefore, implementation of variable delay in a form that can be accommodated in integrated circuit technology is highly desirable, especially in the mixed analog-digital VL,SI technology that is described, for example, by Y. Tsividis in Mixed Analog-Digital VLSI Devices And Technology, (McGraw-Hill, 1996). As Tsividis points out at page 3, mixed analog-digital circuits "help make possible the high performance of the digital systems and circuits themselves". Tsividis at p. 3.
Therefore a general need exists for the provision of mixed analog-digital circuits that will enhance the performance of digital systems. More specifically, a need exists for a voltage-controlled, variable analog delay circuit that can be built entirely in an integrated circuit (IC) for interfacing with digital circuits.
USPTO Backgrounds
USPTO Backgrounds