Power metal oxide semiconductor field effect transistors (MOSFETs) are commonly used power devices due to their low gate drive power, fast switching speed and superior paralleling capability. Most power MOSFETs feature a vertical structure with source and drain regions on opposite sides of a gate trench filled with polysilicon as gate electrodes. In such structures, the MOS channels are formed along the vertical walls of the trenches.
In recent years, split-gate trench structures are developed and are preferred for certain applications over conventional trench MOSFETs because they have good high frequency switching performance and low on-state resistance. A split-gate trench power MOSFET comprises two electrodes in a gate trench. A first electrode serves as the gate electrode to control the channel formation of the MOSFET, and a second electrode serves as shield electrode to decrease the capacitance Cgd between drain electrode and gate electrode. Existing fabrication techniques for split-gate trench MOSFETs are typically complex and expensive, usually requiring 8 or more masks to be applied during processing.
It is within this context that embodiments of the present invention arise.
USPTO Backgrounds
USPTO Backgrounds