1. Field of the Invention
The embodiments of the invention generally relate to a design structure for a state saving circuit, and, more particularly, to a design structure for a high performance state saving latch.
2. Description of the Related Art
With the increasing popularity of portable electronic devices, such as laptops, cell phones and personal digital assistants (PDAs), there is a growing need for systems that can reduce power consumption in order to extend energy storage times of the device's power supply (e.g., battery). Namely, applications that utilize CMOS integrated circuits (IC's) require circuits that utilize a minimal amount of power and have the capability to be powered down when not in use.
The term “dynamic latch,” typically refers to an architecture of latch used for high performance designs where the latch node is pre-charged. Instead, the term “state-saving latch” is typically used to describe a power saving latch where at least part of the latch may be powered down. However, the state saving latches often have a multiple latch, e.g., a master and a slave latch, flip-flop, etc., configuration where only one latch is powered down. This still leaves one full latch powered up.
To save states, static latches with extra devices that are isolated and connected to an extra voltage rail are used to save the state during the period that a voltage island is disconnected. This overhead to the voltage islands increase power routing complexity, i.e., latch overhead, and generally reduces the advantage of using state saving latches and reduces the ability to effectively power down voltage islands.
U.S. Pat. No. 6,667,645 discloses a circuit comprising a dynamic latch controlled by a pulsed clock signal. U.S. Pat. No. 6,927,614 discloses a state saving circuit powered by an uninterruptible power supply.
USPTO Backgrounds
USPTO Backgrounds