A load circuit incorporated in a semiconductor substrate requires a constant voltage to be supplied from a power supply line of a semiconductor substrate and various techniques for supplying a constant voltage are conventionally proposed (e.g., see Patent Document 1). When a voltage of a power supply path which connects a power supply and semiconductor substrate becomes unstable, an electromotive force induced by the inductance of this voltage supply path increases and power supply noise produced on the power supply line in the semiconductor substrate increases. The power supply noise produced on the power supply line must be suppressed because it destabilizes the voltage to be supplied to a load circuit. For this purpose, there are conventionally proposals on techniques of monitoring the potential of the power supply path which connects the power supply and semiconductor substrate, passing an amount of current corresponding to the monitoring result through the power supply path or passing an amount of current corresponding to the monitoring result from the power supply path (e.g., see Patent Document 2). Furthermore, since reducing the inductance of the power supply path leads to suppressing power supply noise, packages of a semiconductor apparatus having long terminals such as DIP (Dual In-line Package) or QFP (Quad Flat Package) are being replaced by packages having short terminals such as BGA (Ball Grid Array) package or LGA (Land Grid Array) package.
However, the actual state of a semiconductor apparatus represented by a processor is that with an improvement in the degree of integration of transistors and speed enhancement of operating frequencies, a variation of current passing through the power supply line in the semiconductor substrate is increasing and the speed of the variation is also increasing. The increase in current variations and increase in the variation speed on the power supply line lead to increase in power supply noise produced on the power supply line, resulting in an excessive counter-electromotive force in the power supply path which connects the power supply and semiconductor substrate. Moreover, with the increase in the degree of integration, the potential supplied from the power supply tends to decrease due to a reduction in power consumption and power supply noise increases notably.
Under such circumstances, even if an attempt is made to stabilize the voltage of the power supply path using the technique described in Patent Document 2, it is not possible to follow up the rate of change of the speed-enhanced current and it is difficult to stabilize the voltage of the power supply path. Furthermore, even if the inductance of the power supply path is reduced by means of a package, the increase in current variation is so notable that it is still difficult to stabilize the voltage of the power supply path.
In addition to the technique described in Patent Document 2 and package technique, various techniques are conventionally adopted to stabilize the voltage of the power supply path, but all these techniques have problems. For example, a semiconductor circuit incorporated in a semiconductor substrate has a parasitic capacitance in the own circuit, and it was possible to confine power supply noise within an allowable range using this parasitic capacitance in the era when the degree of integration of transistors and operating frequency were not so high, but at the present time, it is not possible to confine power supply noise within an allowable range using only this parasitic capacitance and it is becoming a general practice to give a decoupling capacitance by means of a capacitance of a gate oxide film or junction capacitance. However, the degree of integration and speed enhancement of operating frequencies are advancing at a dramatic pace at the present time and it is becoming difficult to confine power supply noise within an allowable range by only giving a decoupling capacitance. Here, it may be possible to increase the size of a semiconductor substrate to increase the parasitic capacitance or decoupling capacitance, but increasing the size of the semiconductor substrate will increase the cost, extend signal lines and produce a delay, which is not desirable.
On the other hand, suppressing a variation in the current flowing through the power supply line in the semiconductor substrate will consequently stabilize the voltage of the power supply path which connects the power supply and semiconductor substrate. Here, the variation in the current flowing through the power supply line and variation in the voltage of the power supply line are mutually correlated, and therefore there is a proposal on a circuit which compensates for a voltage drop of the power supply line (e.g., see Patent Document 3), and in addition, there is also a proposal on a circuit which suppresses a voltage increase in the power supply line.
FIG. 1 conceptually illustrates a circuit that compensates for a voltage drop of the power supply line.
A circuit 800 shown in this FIG. 1 includes a voltage drop detection section 810 connected between a power supply line Vdd and ground line Vss. Furthermore, a charge supply section 820 is disposed between the power supply line Vdd and the ground line Vss and this charge supply section 820 is provided with two capacitors 821, 822 and a changeover switch 823. The two capacitors 821, 822 are switched by the changeover switch 823 between a state in which they are connected in series between the power supply line Vdd and ground line Vss (see the changeover switch 823 indicated by solid lines) and a state in which they are connected in parallel therebetween (see the changeover switch 823 indicated by dotted lines) as indicated by arrows in the figure. The voltage drop detection section 810 detects that the potential of the power supply line Vdd has changed toward the low potential side and outputs a detection signal indicating that the potential has changed toward the low potential side. This detection signal is input to the changeover switch 823. The two capacitors 821, 822 remain connected in parallel between the power supply line Vdd and ground line Vss until immediately before the detection signal is input to the changeover switch 823. When the two capacitors 821, 822 are connected in parallel in this way, the capacitors 821, 822 are charged with power from the power supply line Vdd. When the detection signal is input to the changeover switch 823, the changeover switch 823 changes the connection state of the two capacitors 821, 823 from the parallel connection to the serial connection once and then returns the connection state to the parallel connection again. When the two capacitors 821, 822 are connected in series, the power from the power supply line Vdd is boosted and a current flows into the power supply line Vdd. Such a circuit 800 shown in FIG. 1 is monitoring a potential drop of the power supply line Vdd, and can thereby follow up the rate of change of a speed-enhanced current, but the upper limit of the amount of current that can be passed through the power supply line Vdd is determined by the capacitances of the two capacitors 821, 822.
FIG. 2 conceptually illustrates a circuit that suppresses a voltage increase in the power supply line.
In the circuit 900 shown in this FIG. 2, a monitoring section 910 is connected between the power supply line Vdd and ground line Vss. The monitoring section 910 monitors the potential of the power supply line Vdd and outputs, when the potential of the power supply line Vdd changes toward the high potential side, a monitor signal indicating the variation toward the high potential side. Furthermore, the circuit 900 shown in FIG. 2 is provided with a current control section 920 having a capacitor 921. One end of this capacitor 921 is connected to the power supply line Vdd and a monitor signal output from the monitoring section 910 is input to the other end thereof. The potential at this other end changes according to the monitor signal and a current corresponding to the potential difference between both ends of the capacitor 921 flows through the capacitor 921. When the voltage of the power supply line Vdd increases, a current flows out of the power supply line Vdd and can suppress the voltage increase. Such a circuit 900 shown in FIG. 2 is also monitoring the potential increase of the power supply line Vdd, and can thereby follow up the rate of change of a speed-enhanced current, but the upper limit of the amount of current that can be passed from the power supply line Vdd is determined by the capacitance of the capacitor 921.
As shown above, as the current variation increases, both the circuit 800 shown in FIG. 1 and the circuit 900 shown in FIG. 2 require a correspondingly large capacitor and the mounting area on the semiconductor substrate increases. In the circuit 900 shown in FIG. 2, even when the voltage of the power supply line decreases, the voltage drop seems to be complemented by the power charged into the capacitor 921, but the charge therefor is supplied from the power supply line Vdd through an operational amplifier 911, and therefore it is after all not possible to compensate for the drop of the power supply line Vdd.
(Patent Document 1)
Japanese Patent Laid-Open No. 2000-242344 (pp. -4, FIG. 1)
(Patent Document 2)
Japanese Patent Laid-Open No. 8-190436 (p3, FIG. 2)
(Patent Document 3)
U.S. Pat. No. 6,069,521 (FIG. 4A)
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