Presently, most memory systems in computers are either constructed from static random access memory devices (SRAMs) or dynamic random access memory devices (DRAMs). Each type of memory device has advantages and disadvantages, and as a result DRAMs and SRAMS are typically restricted to different applications. SRAMs are faster and are typically used in applications where fast access times and high bandwidth are critical, such as in cache memories. SRAMs however consume more power, are more expensive to fabricate, and provide fewer cells (bits) per given chip space. On the other hand, while slower than SRAMs, DRAMs are typically less expensive, consume substantially less power, and provide more bits in the same chip space (i.e. have a higher cell density). DRAMs are typically used to construct those memory subsystems, such as system memories and display frame buffers, where power reduction and cell density are more critical than speed. In most computing systems, it is these subsystems which dominate the system architecture, and hence, DRAMs remain the prevalent type of memory device on the market.
In the vast majority of presently available commercial DRAMs, the maximum number of available data input/output pins is 16, allowing access to a maximum of 16 bits per random access (or page) cycle. This presents a problem in the construction of state of the art computing systems, where the data buses are as wide as 64 or 72 bits. For example, to support a 64-bit wide data bus, four parallel "by 16" devices are required per bank of memory. Multiple chips in turn require additional board space, increase power consumption and increase the number of required interconnections on the printed circuit boards. Further, since DRAMs (monolithic) are constructed in fixed sizes, such as 512 Kbytes or 2 Mbytes, memory space is often wasted. For example, depending on whether 512 KByte or 2 MByte devices are used, each system memory bank would have a corresponding capacity of 1 MByte or 4 MBytes respectively (in this case). If only an intermediate capacity is required per bank, such as 3 MBytes, the larger incrementation must be selected and substantial memory space is wasted.
It would be advantageous to construct DRAMs with wider data ports For example, two DRAMs each with 32 data pins or one DRAM with 64 data pins could support a 64-bit bus during a single random access. However, increased pin count almost always increases device cost. In devices such as the CPU, where only a single unit is required per system, the increased cost associated with increased pin count can usually be tolerated. In contrast, such cost increases normally cannot be tolerated in the case of memory devices, since a significant number of memory devices are normally required per system, typically between 10 and 20 in current architectures. The problem of pin count is particularly difficult if a 64-bit wide device is considered. Here, at least 64 data pins and approximately 21 other pins (for addresses, power and control signals) would be required. Currently available packages come in 60 and 100 pin counts, and therefore, in this case, the more expensive 100 pin package would have to be selected, even though a large number of pins would go unused.
Thus, the need has arisen or circuits and methods for implementing wide memory devices. In particular, such circuits and methods should be applicable to DRAM memory devices, although not necessarily limited thereto. In implementing such a wide memory device, pin count should be minimized.
USPTO Backgrounds
USPTO Backgrounds