In the related art, a solid-state imaging device having a built-in analog-to-digital converter (hereinafter referred to as an “AD conversion circuit”) has been put to practical use as a solid-state imaging device mounted on a digital camera, a digital video camera, an endoscope, or the like. In the solid-state imaging device having an AD conversion circuit built thereinto, a column AD conversion circuit includes an AD conversion circuit for each column of a pixel array unit in which pixels are arranged in a matrix form, to realize a so-called column ADC type solid-state imaging device. In the column ADC type solid-state imaging device, a digital signal obtained by the column AD conversion circuit performing analog-to-digital conversion on an analog signal after noise is removed from a pixel signal generated by each pixel arranged in the pixel array unit is output.
Further, a single slope type AD conversion circuit that performs analog-to-digital conversion using a ramp wave is known as one AD conversion circuit built in a solid-state imaging device. The single slope type AD conversion circuit compares an input analog signal (that is, a potential of a pixel signal) with a potential of the ramp wave, and counts the time required from a timing of an initial value of the potential of the ramp wave to inversion of the comparator (a period (time interval) from a timing of start of analog-to-digital conversion to a time when the analog signal and the ramp wave come to the same potential) with a clock at a predetermined frequency to thereby obtain a digital signal indicating a magnitude of the analog signal. In the following description, the AD conversion circuit refers to a single slope type AD conversion circuit.
In the single slope type AD conversion circuit, a time detection circuit detects the length of the time interval (that is, detects the time interval). In a time detection circuit of the related art, a latch unit and a counting unit included in the time detection circuit operate while the length of the time interval is being counted. Therefore, power consumption of the AD conversion circuit including the time detection circuit of the related art depends on the length of the time interval. Accordingly, shortening a period in which the latch unit and the counting unit in the time detection circuit operate (that is, shortening the length of the time interval) is conceivable as a method of reducing the power consumption of the AD conversion circuit. However, in the time detection circuit of the related art, if the length of the time interval is simply shortened, a count value in the latch unit and the counting unit decreases and resolution of the AD conversion circuit is degraded. Therefore, in the time detection circuit of the related art, increasing the frequency of the clock when the length of the time interval is counted is conceivable in order to improve the resolution of the AD conversion circuit. However, in this case, since a frequency at which the latch unit and the counting unit included in the time detection circuit operate increases, power consumption increases. Thus, in the time detection circuit of the related art, it is difficult to achieve both of improvement in resolution and reduction in power consumption. That is, in the AD conversion circuit including the time detection circuit of the related art, it is difficult to achieve both of improvement in resolution and reduction in power consumption when analog-to-digital conversion is performed.
Therefore, for example, Japanese Patent No. 5536584 or “Low-Power-Consumption Driving in Single-Slope ADC with Multi-phase TDC” (Graduate School of Information Science and Technology, Hokkaido University, Daisuke UCHIDA, Makito SOMEYA, Masayuki IKEBE, Junichi MOTOHISA, and Eiichi SANO, ITE Technical Report Vol. 37, No. 29, The Institute of Image Information and Television Engineers, p. 97 to 100, Jul. 5, 2013) (hereafter, “Literature Document 1”) discloses a configuration of a time detection circuit capable of reducing power consumption while maintaining resolution when the length of a time interval is detected, and a configuration of an AD conversion circuit including the time detection circuit. If the time detection circuit disclosed in Japanese Patent No. 5536584 or Literature Document 1 is included in an AD conversion circuit, it is possible to reduce power consumption while maintaining resolution when analog-to-digital conversion is performed.
A configuration of an AD conversion circuit of the related art including a time detection circuit disclosed in Japanese Patent No. 5536584 or Literature Document 1 will be described herein. FIG. 8 is a block diagram showing a schematic configuration of the AD conversion circuit of the related art. The AD conversion circuit 8 shown in FIG. 8 includes a clock generation circuit 81, a comparison unit 82, and a time detection circuit 83.
In the clock generation circuit 81, a plurality of delay units DU[0] to DU[7] that delay an input signal by a predetermined time and output a resultant signal are connected in an annular form. A start pulse StartP is input to the first delay unit DU[0]. A plurality of clock signals CK0 to CK7 having different phases are generated at regular intervals from a timing at which the start pulse StartP is input, by the clock generation circuit 81.
The comparison unit 82 receives an analog signal Vin that is a target of analog-to-digital conversion and a ramp wave Vramp of which a potential decreases over time. The comparison unit 82 includes a comparator that inverts a logic of an output signal (=comparison signal CO) at a timing at which a potential of the analog signal Vin and the potential of the ramp wave Vramp match. The comparison unit 82 outputs the comparison signal CO to the time detection circuit 83. In the AD conversion circuit 8 of the related art, a period from a timing at which the comparator begins to compare the potential of the analog signal Vin with the potential of the ramp wave Vramp (that is, a timing at which the analog-to-digital conversion starts) to a timing at which the logic of the comparison signal CO is inverted is the length of the time interval indicating the magnitude of the analog signal Vin. The comparison unit 82 operates with the power supply voltage Vcmp.
The time detection circuit 83 includes a signal generation circuit 831, a latch unit 832, and a counting unit 833. The signal generation circuit 831 includes a delay circuit DLY that outputs a control signal xCO_D obtained by delaying the comparison signal CO input from the comparison unit 82 by a predetermined time and inverting a resultant signal, and a logical product circuit AND that outputs a signal obtained by performing logical product on the comparison signal CO and the control signal xCO_D as a latch driving signal Hold_L. The latch unit 832 includes latch circuits D_0 to D_7 that hold (latch) the logical states (phase states) of the corresponding clock signals CK0 to CK7 when an operation ends, and a logical product circuit AND that outputs a control signal Hold_C obtained by performing logical product on a control signal Enable input from the outside to the AD conversion circuit 8 and the control signal xCO_D input from the signal generation circuit 831. The latch circuits D_0 to D_6 operate according to the latch driving signal Hold_L input from the signal generation circuit 831. Further, the latch circuit D_7 outputs the same output signal as the corresponding clock signal CK7 to the counting unit 833 according to the control signal Hold_C. The counting unit 833 includes a counter circuit that is initialized by a reset signal RST input from the outside to the AD conversion circuit 8, and counts the number of output signals (=clock signal CK7) output from the latch circuit D_7 in the latch unit 832. The respective components in the time detection circuit 83 operate with the power supply voltage Vlat.
The time detection circuit 83 sums the phase states of the clock signals CK0 to CK7 latched by the respective latch circuits D_0 to D_7 in the latch unit 832 and a count value of the clock signal (=clock signal CK7) counted by the counting unit 833 and outputs a result thereof as a digital signal Dout indicating the length of the time interval. A value of the digital signal Dout corresponds to a digital value indicating a voltage (magnitude) of the analog signal Vin.
Next, an operation of the AD conversion circuit 8 of the related art including the time detection circuit disclosed in Japanese Patent No. 5536584 or Literature Document 1 will be described. FIG. 9 is a timing chart showing the operation of the AD conversion circuit 8 of the related art.
First, the potential of the ramp wave Vramp decreases over time from a timing t0 at which the AD conversion circuit 8 starts analog-to-digital conversion. The comparator starts comparison of the potential of the analog signal Vin with the potential of the ramp wave Vramp. Further, at a timing t0, the start pulse StartP is input to the clock generation circuit 81. Accordingly, the clock generation circuit 81 starts an operation, and the leading delay unit DU[0] to which the start pulse StartP has been input outputs an output signal obtained by delaying the start pulse StartP by a predetermined time and inverting a resultant signal to the delay unit DU[1] in a subsequent stage, and outputs the output signal to the time detection circuit 83 as the clock signal CK0. The respective delay units DU[1] to DU[7] also output output signals obtained by delaying the output signals of the delay units DU[0] to DU[6] in a preceding stage by a predetermined time and inverting resultant signals to the delay units DU[2] to DU[0] in a subsequent stage, and output the output signals to the time detection circuit 83 as the clock signals CK1 to CK7. Accordingly, as shown in FIG. 9, the respective clock signals CK0 to CK7 with a phase difference corresponding to a predetermined time are input to the corresponding latch circuits D0 to D7 in the latch unit 832.
Further, since the comparison signal CO output by the comparator is at the “low” level at the timing t0, the latch driving signal Hold_L output by the logical product circuit AND in the signal generation circuit 831 is at a “low” level indicating that the operation of the latch circuits D_0 to D_6 is invalid (disabled). Therefore, the latch circuits D_0 to D_6 do not operate. On the other hand, since the comparison signal CO is at the “low” level, the control signal xCO_D output by the delay circuit DLY is at a “high” level. Further, at the timing t0, the control signal Enable at a “high” level is input from the outside to the AD conversion circuit 8. Accordingly, the control signal Hold_C output by the logical product circuit AND in the latch unit 832 comes to a “high” level indicating that the output of the latch circuit D_7 is valid (enabled), and the latch circuit D_7 outputs the same output signal Q7 as the clock signal CK7 to the counting unit 833. The counter circuit in the counting unit 833 counts the number of output signals Q7.
Thereafter, at a timing t1 at which the potential of the analog signal Vin matches the potential of the ramp wave Vramp, the comparison signal CO output by the comparator is inverted to a “high” level. Accordingly, the latch driving signal Hold_L comes to a “high” level indicating that the operation of the latch circuits D_0 to D_6 is valid (enabled), and the respective latch circuits D_0 to D_6 start the operation of capturing the phase states of the corresponding clock signals CK0 to CK6. Accordingly, respective output signals Q0 to Q6 of the latch circuits D_0 to D_6 come to values indicating the phase states of the clock signals CK0 to CK6.
Thereafter, the control signal xCO_D is inverted to a “low” level at a timing t2 at which a predetermined time for delaying the comparison signal CO in the delay circuit DLY has elapsed. Accordingly, the latch driving signal Hold_L comes to the “low” level (that is, invalid (disabled)), and the respective latch circuits D_0 to D_6 end an operation of capturing phase states of the corresponding clock signals CK0 to CK6, and hold (latch) the phase states of the clock signals CK0 to CK6 at this time. Further, as the control signal xCO_D is inverted to the “low” level at the timing t2, the control signal Hold_C comes to a “low” level indicating invalid (disabled), and the latch circuit D_7 stops output of the output signal Q7 to the counting unit 833, and holds (latches) the phase state of the clock signal CK7 at this time. Accordingly, the counting of the number of the output signals Q7 in the counter circuit of the counting unit 833 is also stopped, and the counter circuit holds a current count value.
Thereafter, the time detection circuit 83 outputs the digital signal Dout according to the phase states of the clock signals CK0 to CK7 latched in the respective latch circuits D_0 to D_7 in the latch unit 832 and the count value of the output signal Q7 counted by the counter circuit in the counting unit 833.
Thus, the time detection circuit 83 disclosed in Japanese Patent No. 5536584 or Literature Document 1 includes the signal generation circuit 831 to operate the latch circuits D_0 to D_6 only in a short period (a period of the “high” level) indicating that the latch driving signal Hold_L is valid (enabled). That is, the latch circuits D_0 to D_6 are operated during the time interval (a period from a timing t0 to a timing t1) in a previous period, whereas the latch circuits D_0 to D_6 are stopped in a period other than a short period in which the latch driving signal Hold_L is at the “high” level. Accordingly, in the AD conversion circuit 8 of the related art including the time detection circuit 83, it is possible to reduce power consumption when the length of the time interval is detected in a state in which the resolution of the analog-to-digital conversion is maintained. In other words, in the AD conversion circuit 8 of the related art, the operation of the signal generation circuit 831 included in the time detection circuit 83 greatly contributes to the reduction in power consumption. Since the column ADC type solid-state imaging device as described above includes the AD conversion circuit 8 of the related art, it is possible to realize low power consumption of the column ADC type solid-state imaging device.
However, in the column ADC type solid-state imaging device, it is conceivable that a power supply is common to the AD conversion circuits arranged in the respective columns. More specifically, in the column ADC type solid-state imaging device, it is conceivable that the power supply voltage Vcmp and the power supply voltage Vlat shown in FIG. 8 are common to the AD conversion circuits 8 included in the respective columns. This is because, in the column ADC type solid-state imaging device, thousands of AD conversion circuits 8 are included corresponding to the respective column since thousands of pixels are arranged in the pixel array unit, and if power supplies for the AD conversion circuits 8 are separately provided, it is difficult to miniaturize the column ADC type solid-state imaging device.
Therefore, in the column ADC type solid-state imaging device in which the column AD conversion circuit is configured with the AD conversion circuits 8 of the related art including the time detection circuit 83, if the time detection circuits 83 included in the plurality of AD conversion circuits 8 simultaneously detect the length of a time interval and operate, a malfunction may occur due to fluctuation in a power supply voltage or a GND of the AD conversion circuit 8. More specifically, in the column ADC type solid-state imaging device, when the analog signals Vin with the same magnitude are input to the plurality of AD conversion circuits 8, a potential of the analog signal Vin matches a potential of the ramp wave Vramp at the same time in the comparators in the comparison units 82 included in the plurality of AD conversion circuits 8, and the logic of the comparison signal CO is inverted. Then, in the column ADC type solid-state imaging device, the comparators in the plurality of comparison units 82 simultaneously operate. Accordingly, the amount of current of the power supply voltage Vcmp greatly changes, and the entire potential of the power supply voltage Vcmp greatly fluctuates. Further, in this case, in the column ADC type solid-state imaging device, the plurality of signal generation circuits 831 simultaneously operate according to the inversion of the logic of the comparison signal CO, and the latch units 832 simultaneously operate due to the latch driving signals Hold_L generated by the respective signal generation circuits 831. Accordingly, in the column ADC solid-state imaging device, a large current instantaneously flows with the power supply voltage Vlat due to operations of the latch unit 832 according to pulses of the latch driving signals Hold_L, and the entire potential of the power supply voltage Vlat greatly fluctuates. In the column ADC type solid-state imaging device, it is conceivable that the detection of the length of the time interval has already been completed and the pulses of the latch driving signals Hold_L are further input to the latch circuits D_0 to D_6 holding the phase states of the clock signals CK0 to CK6 at a timing at which the potentials of the power supply voltage Vcmp and the power supply voltage Vlat that have greatly fluctuated return to an original state. That is, in the column ADC type solid-state imaging device, it is conceivable that the signal generation circuit 831 included in the AD conversion circuit 8 malfunctions due to an influence of the fluctuation in the power supply voltage or the GND.
In the column ADC type solid-state imaging device, in this case, the latch circuits D_0 to D_6 that have already normally held the phase states of the clock signals CK0 to CK6 change the phase states of the clock signals CK0 to CK6 to different phase states (that is, rewrite the normally held phase states), and the length of the time interval cannot be detected normally. Accordingly, the AD conversion circuit 8 cannot perform normal analog-to-digital conversion.
For example, in the column ADC type solid-state imaging device, a state in which the AD conversion circuits 8 arranged in a certain column have already completed the detection of the length of the time interval and hold the phase states of the clock signals CK0 to CK6 is conceivable. Thereafter, in the column ADC type solid-state imaging device, if the plurality of AD conversion circuits 8 arranged in another column simultaneously detect the length of the time interval and simultaneously operate, it is conceivable that the AD conversion circuit 8 that has already completed the detection of the length of the time interval malfunctions due to an influence of fluctuation in the power supply voltage or the GND, and a value of the length of the time interval is rewritten to a different value.
An example of a case in which the AD conversion circuit 8 arranged in a certain column malfunctions due to an influence of fluctuation in a power supply voltage or a GND in a column ADC type solid-state imaging device will be described. FIG. 10 is a timing chart showing an example of a malfunction in the AD conversion circuit 8 of the related art. The timing chart shown in FIG. 10 indicates an example of operation timings in a case in which the analog signal Vin_i is input to an AD conversion circuit 8 arranged in an i-th column and an analog signal Vin_o is input to a plurality of other AD conversion circuits 8 arranged in another column. In FIG. 10, only timings of respective signals of the signal generation circuit 831 in the time detection circuit 83 included in the AD conversion circuit 8 arranged in the i-th column are shown.
First, from a timing t0, the AD conversion circuit 8 arranged in each column starts analog-to-digital conversion. In the following description, the AD conversion circuit 8 arranged in the i-th column is referred to as an “AD conversion circuit 8i”, and the plurality of AD conversion circuits 8 arranged in the other columns are referred to as “AD conversion circuits 8o”. Here, the comparator in the comparison unit 82 of the AD conversion circuit 8i performs comparison of the potential of the analog signal Vin_i with the potential of the ramp wave Vramp, and the comparator in the comparison unit 82 of the AD conversion circuit 8o performs comparison of the potential of the analog signal Vin_o with the potential of the ramp wave Vramp.
Then, from a timing t1 at which the potential of the analog signal Vin_i and the potential of the ramp wave Vramp match, the comparator in the comparison unit 82 of the AD conversion circuit 8i starts inversion of logic of the comparison signal CO. At a timing t2 at which the level of the comparison signal CO comes to an input threshold voltage of the logical product circuit AND in the signal generation circuit 831 included in the time detection circuit 83, the latch driving signal Hold_L comes to a “high” level. Further, the delay circuit DLY in the signal generation circuit 831 delays the comparison signal CO by a predetermined time and inverts a resultant signal. If the control signal xCO_D comes to a “low” level at a timing t3, the latch driving signal Hold_L correspondingly comes to the “low” level. Accordingly, the respective latch circuits D_0 to D_6 in the time detection circuit 83 included in the AD conversion circuit 8i hold (latch) the phase states of the clock signals CK0 to CK6. This operation of the AD conversion circuit 8i is a normal operation.
Thereafter, the AD conversion circuits 8o simultaneously operate at a timing t4 at which the potential of the analog signal Vin_o and the potential of the ramp wave Vramp match. Accordingly, the potentials of the power supply voltage Vcmp and the power supply voltage Vlat of the AD conversion circuit 8i may decrease to the vicinity of a level of the GND. In this case, the level of the comparison signal CO output by the comparator in the comparison unit 82 of the AD conversion circuit 8i also decreases according to the decrease in the potentials of the power supply voltage Vcmp and the power supply voltage Vlat.
Thereafter, the potentials of the power supply voltage Vcmp and the power supply voltage Vlat of the AD conversion circuit 8i begin to return to the original state. Accordingly, the comparison signal CO output by the comparator in the comparison unit 82 of the AD conversion circuit 8i returns to the “high” level according to the return of the potential of the power supply voltage Vcmp. However, according to characteristics of a response speed of the comparator, a timing at which the comparison signal CO returns to the “high” level may be later than a timing at which the potential of the power supply voltage Vcmp returns. Then, since the level of the comparison signal CO is at a low level (“low” level), the delay circuit DLY in the signal generation circuit 831 operates to output the control signal xCO_D at a “high” level with the return of the potential of the power supply voltage Vlat. Accordingly, the logical product circuit AND in the signal generation circuit 831 sets the latch driving signal Hold_L to a “high” level at a timing t5 at which the level of the comparison signal CO during the return to the “high” level comes to the input threshold voltage.
Further, the delay circuit DLY in the signal generation circuit 831 delays the “high” level of the level of the comparison signal CO by a predetermined time from the timing t5 at which the level of the comparison signal CO during the return to the “high” level comes to the input threshold voltage, and inverts the resultant level. The delay circuit DLY in the signal generation circuit 831 sets the control signal xCO_D that is about to be set to the “high” level, to the “low” level at a timing t6. The logical product circuit AND in the signal generation circuit 831 sets the latch driving signal Hold_L to a “low” level according to the “low” level of the control signal xCO_D. That is, the signal generation circuit 831 malfunctions to generate the pulse of the latch driving signal Hold_L that comes to the “high” level between the timing t5 and the timing t6 due to the fluctuation in the potentials of the power supply voltage Vcmp and the power supply voltage Vlat.
Accordingly, the respective latch circuits D_0 to D_6 in the AD conversion circuit 8i hold (latch) the phase states at the timing t6 of the clock signals CK0 to CK6. That is, the respective latch circuits D_0 to D_6 in the AD conversion circuit 8i change the phase states of the clock signals CK0 to CK6 held (latched) at a timing t3 normally to the phase states at the timing t6 at which the malfunction has occurred due to the fluctuation in the potentials of the power supply voltage Vcmp and the power supply voltage Vlat of the AD conversion circuits 8i. 
Thus, in the configuration of the AD conversion circuit of the related art and, more specifically, in the configuration of the signal generation circuit in the time detection circuit disclosed in Japanese Patent No. 5536584 or Literature Document 1, malfunction caused by fluctuation in the power supply voltage or the GND is a concern. That is, in the configuration disclosed in Japanese Patent No. 5536584 or Literature Document 1, the time detection circuit cannot detect the length of the time interval normally.
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