1. Field of the Invention
This invention relates generally to memory testing, and more particularly, to a CPU-based system and method for testing embedded memory.
2. Description of the Prior Art
As the amount of repairable memory increases in digital signal processing (DSP) solutions, traditional test methods have become more time consuming due to the amount of data that needs to be collected. Address and data information related to each memory failure is required to determine a repair solution and also to provide wafer fabrication information necessary to diagnose failure mechanisms. Memory tests have become more difficult to implement due to increased pin and routing requirements, especially in system on a chip (SoC) applications. Dedicated memory testers are expensive, and add complexity to the test flow. Further, implementing traditional memory test techniques on an existing base of logic testers is problematic due to lengthy test times, which are due primarily to inefficient methods of capturing failure data.
U.S. Pat. No. 5,680,544, entitled Method For Testing An On-Chip Cache For Repair, issued Oct. 21, 1997 to Edmondson et al. discloses a CPU-based method of testing an internal cache memory. The method taught by Edmondson et al., however, teaches the added requirement of a special test coprocessor to assist with computing the repair solution.
In view of the foregoing, it would be both desirable and advantageous in the memory testing art to provide a simple, cost-effective technique that substantially reduces memory test time requirements and that is more easily implemented when compared with existing programmable memory test methods.
USPTO Backgrounds
USPTO Backgrounds