1. Field of the Invention
The invention relates generally to semiconductors and, more particularly, to metal-insulator-metal (MIM) capacitors for integrated circuits.
1. Background of the Invention
The integration of MIM capacitors and field effect transistors (FETs) on an integrated circuit are important because analog circuits usually require precision capacitors as well as transistors. The on-chip integration of MIM capacitors, FETs, and other devices reduces the cost associated with fabricating integrated circuits.
Semiconductor capacitors are prone to dielectric damage during fabrication that lead to reliability fails due to dielectric breakdown. For example, a MIM capacitor can have a reliability sensitivity to the etch of the inter-level dielectric (ILD) for the vias used to contact the top plate of the MIM capacitor. The integration of high performance inductors with MIM capacitors on a semiconductor chip is done in part with relatively large, tall vias in the inter-level dielectric above the MIM capacitor, which results in prolonged exposure of the MIM capacitor to the via etch.
To reduce the exposure of the top plate to the prolonged via etch, an insulator layer such as, for example, silicon nitride, is formed covering the entire substrate including the top plate of the capacitor and the inter-level dielectric. Referring to FIG. 1, a substrate 10 is provided upon which front-end-of-line (FEOL) levels 20 including semiconductor structures such as, for example, FETs (not shown) and inter-level dielectric layer 25 are formed. Back-end-of-line levels 30 are subsequently formed upon the FEOL levels 20, and include semiconductor structures such as, for example, interconnect 35 and MIM capacitor 40. Conventionally, MIM capacitor 40 is formed on inter-level dielectric layer 25 by depositing a bottom metal layer 45, a portion of which forms a bottom metal plate of the MIM capacitor and another portion of which forms an electrical contact area, depositing a dielectric layer 50 on the bottom metal layer 45, and depositing on the dielectric layer 50 a top metal layer 55, a portion of which forms a top metal plate of the MIM capacitor and another portion of which forms an electrical contact area. Over the MIM capacitor, an insulator layer 60 is deposited to cover inter-level dielectric 25, interconnect 35 and MIM capacitor 40. Processing continues with a deposition to form inter-level dielectric 65 and a reactive ion etch to form via 70. The insulator layer 60 acts as an etch stop for the MIM capacitor top plate 55 to prevent exposure to the via etch, thus preventing breakdown of the MIM capacitor dielectric.
Although reliability of the capacitor dielectric is improved in conventional MIM capacitor fabrication, it has been observed that the performance of FETs formed on FEOL levels 20 below the insulator layer 60 are degraded. The formation of a MIM capacitor with reduced sensitivity to dielectric damage without degrading the performance of FETs is desired.
USPTO Backgrounds
USPTO Backgrounds