1. Field of the Invention
The present invention generally relates to a semiconductor memory apparatus, and particularly, to a dual-port type semiconductor memory apparatus.
2. Description of the Related Art
A conventional dynamic random access memory (DRAM) is constructed with a memory core circuit including a memory cell array that is divided into a plurality of row blocks and a plurality of column blocks, and in which a memory block is provided at each intersection of a row block and a column block. A plurality of memory blocks in each row block share the same word line, and a plurality of memory blocks in each column block share the same column line.
When the core circuit thus constructed is being accessed for reading or writing, data stored in memory blocks in a row block having a common word line can be accessed continuously. Data stored in memory blocks in another row block, however, are not accessible unless the access to the currently accessed row block is completed.
By the way, a dual-port type semiconductor memory apparatus having two input and output (I/O) ports is provided with two series of control pins, address pins, and DQ pins. A core circuit of such a dual-port type semiconductor memory apparatus is accessed through the two I/O ports independently.
In the case where the dual-port type semiconductor memory apparatus of a conventional technique is simultaneously accessed from external devices through both I/O ports and the core circuit responds to an access through one of the I/O ports, the dual-port type semiconductor memory apparatus is required to keep the external device making the other access through the other I/O port waiting by outputting to the external device, if the external device is requesting for an access to read data, a signal indicating the core circuit is busy, or requesting, if the external device is requesting for an access to write data, the external device to make the request again later.
As described above, while the core circuit is busy processing an access through one of the I/O ports, another access to the core circuit through the other I/O port is rejected with a probability of 100%. A dual-port type semiconductor memory apparatus of such a conventional technique is disclosed in the Japanese Laid-open Patent Application No. 2001-43674. The dual-port type semiconductor memory apparatus described in this specification cannot accept simultaneous accesses to the same column block. An external device is required to wait until a prior access to the core circuit is completed.
USPTO Backgrounds
USPTO Backgrounds