1. Field of the Invention
This invention relates generally to the field of semiconductor device design and fabrication. Specifically, the invention relates to methods for manufacturing metallization structures in integrated circuit devices and the resulting structures.
2. State of the Art
Integrated circuits (ICs) contain numerous individual devices, such as transistors and capacitors, that are interconnected by an intricate network of horizontal and vertical conductive lines commonly termed “interconnects.” Exemplary interconnect structures are disclosed in U.S. Pat. Nos. 5,545,590, 5,529,954, 5,300,813, 4,988,423, and 5,356,659, each of which patents is hereby incorporated herein by reference.
Aluminum interconnect structures are decreasing in size and pitch (spacing), as the industry trend continues toward, and includes submicron features and pitches. The resultant reduction in structure sizes leads to numerous reliability concerns, including electromigration and stress voiding of the interconnect structures.
Stress notches (also known as stress voids) on the surface of conductive interconnect structures are of concern because the voids or notches degrade reliability and device performance. Stress notches, when formed in a conductive line, may render the line substantially discontinuous and unable to effectively transmit a signal. Stress notches at a grain boundary are extremely detrimental, as they may propagate along the boundary and sever the conductive line completely.
Stress notches are also undesirable because they can alter the resistivity of a conductive line and change the speed at which signals are transmitted. Resistivity changes from stress notching are especially important as line dimensions shrink, because notching in a submicron conductive line alters resistivity more than notching in a larger line with its consequently greater cross-sectional area. Thus, the ever more stringent pitch sizing and higher aspect ratios (height to width of the structure or feature) sought by practitioners in the art have imitated considerable stress voiding concerns.
It is believed that stress notching results from both structural and thermal stresses between conductive lines and adjacent insulating and passivation layers. Kordic et al., Size and Volume Distributions of Thermally Induced Stress Voids in AlCu Metallization, Appl. Phys. Lett., Vol. 68, No. 8, Feb. 19, 1996, pp. 1060–1062, incorporated herein by reference, describes how stress voids begin at the edge of a conductive line where the density of the grain boundaries is largest. As illustrated in FIG. 12 herein, stress notches form at the exterior surfaces and surface intersections of the conductive lines in order to relieve areas of high stress concentration. The notches may then propagate into, and across, the interior of the conductive line until the line becomes disrupted, cracked, and/or discontinuous.
Aluminum (Al) and Al alloy (such as Al/Cu) lines are especially susceptible to stress notching because of both the thermal expansion mismatch between Al and adjacent layers and the relatively low melting point of Al. As the temperature changes, stresses are induced in Al or Al alloy lines because aluminum's coefficient of thermal expansion (CTE) differs from the CTE of the materials comprising the adjacent layers. To relieve these stresses, Al atoms migrate and form stress notches. Further, because Al has a low melting point, Al atoms migrate easily at low temperatures and aggravate a tendency toward stress notch formation.
Several methods have been proposed to reduce stress notching. One proposed method uses a material less susceptible to stress notching, such as copper (Cu) or tungsten (W), in the conductive line. Using Cu in conductive lines, however, has in the past resulted in several problems. First, copper is difficult to etch. Second, adhesion between copper and adjacent insulating layers is poor and thus poses reliability concerns. Third, adding Cu to Al lines may reduce stress notching, but beyond a certain Cu concentration, device performance may begin to degrade. Fourth, as conductive line geometries shrink, adding Cu to Al lines seems less effective in reducing stress notching. Finally, even using Cu interconnects in the manner employed in the prior art can still lead to notching effects, especially at 0.1 μm geometries and below since, at such dimensions, line widths have become so small that any imperfection can cause openings. Using W in Al conducting lines is also undesirable—W has a high resistivity and therefore reduces signal speed.
Another proposed method to reduce stress notching modifies how the layers adjacent conductive lines (e.g., insulating and passivation layers) are formed. This method has focused, without notable success, on the rate, temperature, and/or pressure at which the adjacent layers are deposited, as well as the chemical composition of such layers.
Yet another proposed method to reduce stress notching comprises forming a cap on the conductive lines. Such caps can be formed from TiN, W, or Ti—W compounds. These materials have higher melting points than Al and, therefore, have a higher resistance to stress notching. A disadvantage in using such caps, however, is that additional process steps, such as masking steps, are required.
U.S. Pat. No. 5,317,185, incorporated herein by reference, describes still another proposed method for reducing stress notching. This patent discloses an IC device having a plurality of conductive lines, where the outermost conductive line is a stress-reducing line. This stress reducing line is a non active structure that reduces stress concentrations in the inner conductive lines.
USPTO Backgrounds
USPTO Backgrounds