1. Field of the Invention
The present invention relates to a phase synchronization circuit. The phase synchronization circuit according to the present invention may be used for a graphic display device in a teletext receiving system.
2. Description of the Related Art
In a graphic display system, in general, a clock pulse is produced phase-synchronized with a synchronizing signal of a television receiver. This clock pulse is used for reading picture data from a picture memory and preparing dot signals for displaying characters, etc. for input into the television receiver. It is necessary that the phase synchronization circuit used for such a graphic display system is improved in reliability and reduced in cost through large-scale integration.
At the same time, it is necessary that no falling out of synchronization is liable to occur and, if synchronization is lost, the pulling-in to synchronization is achieved in a short time.
Of the prior art phase synchronization circuits, the phased-locked loop (PLL) circuit is well known. A PLL circuit includes a voltage-controlled oscillator and a comparator. In the circuit, the phase difference between the input signal and the output of the voltage-controlled oscillator is compared by the comparator to generate a voltage proportional to the phase difference. The voltage is fed back to the voltage-controlled oscillator for the phase synchronization.
Accordingly, the PLL circuit is basically built on a feedback circuit. By enlarging the loop gain, it is possible to considerably reduce the phase difference between the input signal and the output signal.
However, since such a PLL circuit requires use of an integrated circuit (IC) for the feedback circuit, pull-in takes a longer time. Once synchronization has been lost for some reason, there is the disadvantage that it takes a long time, for example, several milliseconds, before the PLL circuit restores the synchronization state. Moreover, the PLL circuit requires external electronic components, for instance, capacitors, making complete circuit integration difficult, thus increasing the cost of the circuit and reducing reliability.
USPTO Backgrounds
USPTO Backgrounds