1. Field of the Invention
The present invention relates generally to radio paging receivers, and more specifically to a battery saving technique for a paging receiver which suffers from disturbances such as fading.
2. Description of the Related Art
Battery saving is an important Mature for hand-held paging receivers in order to keep the battery consumption to a minimum. As described In U.S. Pat. No. 4,839,639, T. Sato et al., a battery saving circuit reduces battery usage by powering the radio section of the receiver when it is in a standby mode at intervals sufficient to receive a preamble of a paging signal that is followed by a series of batches each including a synchronization codeword and a plurality of frames each comprising an address codeword and a message codeword. Each pager is associated with one of the frames to seek the codewords of the associated frame of each batch. On receiving the preamble, the receiver establishes a bit timing synchronization and then enters an address receiving mode during which the radio section is powered at such intervals that the address codeword and a message codeword can be received in each batch. However, If fading should occur in one of the batches, the receiver will fall to detect an address codeword in successive batches and returns to the standby mode, recognizing that the received page is not directed to the receiver. Therefore, the prior art receiver must wait for the next paging signal when the incoming signal is disturbed by fading during the address receiving mode.
Japanese patent 90-12422 discloses a paging receiver having a phase-locked loop bit rate detector for establishing a bit timing synchronization with a preamble and simultaneously detecting the arrival of the preamble. The bit rate detector includes an edge detector for producing a transition pulse in response to each of the leading and trailing edges of a data pulse from the receiving section. The transition pulses are compared by a phase comparator with an output signal from a frequency divider to produce a phase difference signal, which is then applied through an integrator to a pulse insertion/depletion circuit to which a local clock is applied. The frequency divider receives the output of the pulse insertion/depletion circuit to constitute a phase lock loop. The transition pulse is also applied to a latch whose output is coupled to the up-count Input of a counter. A window pulse generator Is responsive to the output of frequency divider for feeding a reference or window pulse, to the down-count input of the counter and to the reset terminal of the latch. When the transition pulse coincides with the window pulse, the latch produces a coincidence output to increment the counter, otherwise the counter is decremented by the window pulse. In the absence of a signal, noise is randomly generated and the duty ratio of the data pulses deviates randomly from the nominal 50% value, causing the transition pulses to be displaced from the window pulses. As a result, the inputs of the counter are cancelled out. The counter output is applied to comparators for comparison with threshold values. Different patterns of battery saving are effected in accordance with the results of the comparisons.
USPTO Backgrounds
USPTO Backgrounds