Static timing analysis (STA) is a method used to compute the expected timing of a digital circuit without the need to perform simulation. Computing the expected timing of a digital circuit is important because it determines if a circuit can operate at a specific clock frequency. STA is also conventionally used as part of other algorithms in the digital circuit design process to help guide design decisions to produce a design that will work at a specified clock frequency.
STA has typically been used instead of simulation because the runtime of STA is orders of magnitude smaller compared to simulation techniques. The runtime is important since obtaining accurate delay information is required by multiple other algorithms for which STA is embedded in. STA is typically used to measure two values for each path that is being analyzed: the setup margin and the hold margin, which refer to the margin available on a signal path for which the signal has to be stable before and after a clock signal arrives.
To account for the operation of the digital design across different operating conditions which affect delay and to guarantee that the design will work across various operating conditions, STA is typically run across many extreme conditions or corners. If the design works at each extreme condition, then under the assumption of monotonic behavior, the design is also qualified for all intermediate points.
In an effort to increase their bandwidth, many interface standards, such as DDR3 and RLDRAM II, have been increasing the data rates that they operate at. To meet the timing requirements and operate at speed at these high data rates electronic devices that use the interface standards are required to calibrate at power-up to reduce skew between signals, and to centre-align clock signals.
As with all other electronic designs, timing analysis needs to occur on these interface standards to compute the expected timing of the interface and determine if the design can operate at the desired clock frequency. While, STA works well in defining the expected timing behavior of a circuit when the topology of the circuit is known, when the topology of the circuit changes during operation (as in the calibration and tracking processes described above), the STA paradigm no longer holds and cannot be used to obtain accurate delay information. Simulation of the design can be used to obtain accurate delay information, but simulation runtimes are orders of magnitude larger than STA. These larger runtimes make simulation unsuitable for real time feedback or optimizations for which STA has typically been used.
One alternative to using simulation to determine the timing analysis of a calibrated path is to first assume that the calibration occurs perfectly, and then to remove certain uncertainties from the analysis. The problem with this methodology is that not every delay uncertainty can be specified, and in particular all of the analysis and data that is performed and used as part of the STA remains unused. Furthermore, this type of analysis does not consider the actual operations that occur within the calibration process and how those affect the delays in the electronic device since no STA calls are performed to obtain accurate delays. Furthermore, this type of analysis cannot consider the effects on timing when the device is operating at multiple operating conditions.
USPTO Backgrounds
USPTO Backgrounds