The present invention relates in general to a semiconductor memory device, and more particularly to a multiple-valued mask programmable read only memory semiconductor device with an improved word level voltage generator circuit for generating word level voltages to be supplied to word lines on determination of the multiple values.
In general, the mask programmable read only memory semiconductor device has memory cell arrays which comprise a plurality of mask programmable read only memories, individuals of which have any one of two threshold voltages. Two kirids of the mask programmable read only memories having the two different threshold voltages have impurity diffusion regions implanted with an impurity at different doses. If the mask programmable read only memory cells with the different threshold voltages are applied with a voltage level intermediate between the above two different threshold voltages, then only the mask programmable read only memory cells with the lower threshold voltage turn ON to flow cell-currents through the mask programmable read only memory cells with the lower threshold voltage whilst the remaining mask programmable read only memory cells with the higher threshold voltage remain OFF to flow no cell current through them. The cell currents are supplied to sense amplifiers to be read out thereby obtain binary digit values "0" and "1".
In recent years, however, in order to increase the memory capacity of the memory cell arrays, it was proposed to utilize three different threshold values of the mask programmable read only memory cells so that each of the mask programmable read only memory cells is capable of storing data more than one bit. Such memory device is so called as "multiple-valued mask programmable read only memory semiconductor device. Individuals of multiple-valued mask programmable read only memory cells have any one of three threshold voltages. Three kinds of the mask programmable read only memory cells having the three different threshold voltages have impurity diffusion regions implanted with an impurity at three different doses from each other. If the mask programmable read only memory cells with the three different threshold voltages are applied with a voltage level intermediate between adjacent two of the three different threshold voltages, then only the mask programmable read only memory cells with the lower threshold voltage or voltages than the applied voltage level turn ON to flow cell-currents through the mask programmable read only memory cells whilst the remaining mask programmable read only memory cells with the higher threshold voltage or voltages than the applied voltage level remain OFF to flow no cell current through them. The cell currents are supplied to sense amplifiers to be read out thereby obtain ternary digit values "0", "1" and "2".
It was also proposed to utilize four different threshold values of the mask programmable read only memory cells. Individuals of multiple-valued mask programmable read only memory cells have any one of four threshold voltages. Four kinds of the mask programmable read only memory cells having the four different threshold voltages have impurity diffusion regions implanted with an impurity at four different doses from each other. If the mask programmable read only memory cells with the four different threshold voltages are applied with a voltage level intermediate between adjacent two of the four different threshold voltages, then only the mask programmable read only memory cells with the lower threshold voltage or voltages than the applied voltage level turn ON to flow cell-currents through the mask programmable read only memory cells whilst the remaining mask programmable read only memory cells with the higher threshold voltage or voltages than the applied voltage level remain OFF to flow no cell current through them. The cell currents are supplied to sense amplifiers to be read out thereby obtain two bits of binary digit values "0", "1". The multiple-valued mask programmable read only memory semiconductor device having four kinds of the mask programmable read only memory cells with the four different threshold voltages will be described in detail with reference to FIGS. 1 and 2. FIG. 1 is a block diagram illustrative of the conventional multiple-valued mask programmable read only memory semiconductor device having four kinds of the mask programmable read only memory cells with the four different threshold voltages.
The conventional multiple-valued mask programmable read only memory semiconductor device has a memory cell array 110 having four kinds of mask programmable read only memory cells 111 with four different threshold voltages. Each of the mask programmable read only memory cells 111 comprises a MOS field effect transistor having a gate which is connected to a word line 112. The above four kinds of the mask programmable read only memory cells 111 have four different threshold voltages, for example, a first threshold voltage Vt0 (0.5 V), a second threshold voltage Vt1 (1.5 V), a third threshold voltage Vt2 (2.5 V), and a fourth threshold voltage Vt3 (3.5 V). The conventional multiple-valued mask programmable read only memory semiconductor device also has a word level generator circuit 120 connected to the word lines 112 for supplying any one of three different word level voltages, each of which lies adjacent two of the four threshold voltages. The three different word level voltages comprise a first word level of 1.0 V, a second word level of 2.0 V and a third word level of 3.0 V, The word level generator circuit 120 is connected through the word lines to the gates of the four kinds of the mask programmable read only memory cells 111. If the word level generator circuit 120 generates the first word level of 1.0 V, then only the mask programmable read only memory cells 111 having the first threshold voltage Vt0 (0.5 V) turn ON, whilst the remaining three kinds of the mask programmable read only memory cells 111 having the second, third and fourth threshold voltages Vt1 (1.5 V), Vt2 (2.5) and Vt3 (3.5) remain OFF. If the word level generator circuit 120 generates the second word level of 2.0 V, then two kinds of the mask programmable read only memory cells 111 having the first and second threshold voltages Vt0 (0.5 V) and Vt1 (1.5 V) turn ON, whilst the remaining two kinds of the mask programmable read only memory cells 111 having the third and fourth threshold voltages, Vt2 (2.5) and Vt3 (3.5) remain OFF. If the word level generator circuit 120 generates the third word level of 3.0 V, then three kinds of the mask programmable read only memory cells 111 having the first, second and third threshold voltages Vt0 (0.5 V), Vt1 (1.5 V) and Vt2 (2.5) turn ON, whilst the remaining mask programmable read only memory cells 111 having the fourth threshold voltage Vt3 (3.5) remains OFF.
The conventional multiple-valued mask programmable read only memory semiconductor device also has a sense amplifier 130 which is connected to drains of the MOS field effect transistors as the mask programmable read only memory cells 111 Sources of the MOS field effect transistors as the mask programmable read only memory cells 111 are connected to a ground line. Further, first, second and third latch circuits 140, 150 and 160 are connected to the sense amplifier 130 for receiving outputs from the sense amplifier 130. A data decoder circuit 170 is also provided which is connected to the first, second and third latch circuits 140, 150 and 160 for receiving outputs from the first, second and third latch circuits 140, 150 and 160. First and second output buffer circuits 180 and 190 are provided which are connected to the data decoder circuit 170 for receiving outputs from the data decoder circuit 170. The first output buffer circuit 180 outputs binary digit output signals "1" or "0". The second output buffer circuit 190 outputs binary digit output signals "1" or "0".
The following table 1 illustrates relationships among the above four threshold voltages, ON/OFF states of the individual mask programmable read only memory cells 111 for three different word levels and output data from the first and second output buffer circuits.
TABLE 1 ______________________________________ word level threshold first second third output data voltage (1.0 V) (2.0 V) (3.0 V) first-buffer second-buffer ______________________________________ 0.5 V(Vt0) ON ON ON 0 0 1.5 V(Vt1) OFF ON ON 0 1 2.5 V(Vt2) OFF OFF ON 1 0 3.5 V(Vt3) OFF OFF OFF 1 1 ______________________________________
The above table 1 shows the followings. The first kind of the mask programmable read only memory cells 111 having the first threshold voltage Vt0 of 0.5 V is operated to turn ON when any of the first, second and third word level voltages is supplied by the word level generator circuit 120. The second kind of the mask programmable read only memory cells 111 having the second threshold voltage Vt1 of 1.5 V is operated to turn ON when any of the second and third word level voltages is supplied by the word level generator circuit 120, but the second kind of the mask programmable read only memory cells 111 remains OFF only when the first word level voltage is applied The third kind of the mask programmable read only memory cells 111 having the third threshold voltage Vt2 of 2.5 V is operated to turn ON only when the third word level voltage is supplied by the word level generator circuit 120, but the third kind of the mask programmable read only memory cells 111 remains OFF when any of the first and second word level voltages is applied. The fourth kind of the mask programmable read only memory cells 111 having the fourth threshold voltage Vt3 of 3.5 V is operated to remain OFF when any of the first, second and third word level voltages is supplied by the word level generator circuit 120. Consequently, the four kinds of the mask programmable read only memory cells 111 having the first, second, third and fourth threshold voltages Vt0, Vt1, Vt2 and Vt3 show individually different combinations of the ON/OFF states for applications of the three different word levels. This means that it is possible to determine the four kinds of the mask programmable read only memory cells 111 or determine the four different threshold voltages of the mask programmable read only memory cells 111 by confirming the ON/OFF state combinations for applications of the three different word levels. This further means that it is possible to allocate two bits of binary digits to the four kinds of the mask programmable read only memory cells 111 or the four different threshold voltages of the mask programmable read only memory cells 111. The data decoder circuit 170 is operated to decode the data from four kinds of combinations of the ON/OFF states of individuals of the mask programmable read only memory cells 111 for applications of the three different word levels. The three different word levels are in general given by step-up of the word levels as illustrated in FIG. 2, which is a diagram illustrative of a profile of increase in step-up of word levels from the first to third levels supplied by a word level generator circuit in the conventional multiple-valued mask programmable read only memory semiconductor device of FIG. 1. The three different word levels are pre-determined in consideration of relationship to the different threshold voltages of the mask programmable read only memory cells 111.
The word level generator circuit 120 generates the word levels increasing in step-up from the first to third word levels which are supplied through the word lines to the gates of the four kinds of the mask programmable read only memory cells 111 having the four different threshold voltages. As a result, the four kinds of the mask programmable read only memory cells 111 show different variations of ON/OFF states as shown in the above Table 1. The sense amplifier 130 is operated to sense the ON/OFF states of the four kinds of the mask programmable read only memory cells 111 for every three levels of the word voltages applied. When the first word level voltage is applied by the word level generator circuit 120, then the ON/OFF states of the four kinds of the mask programmable read only memory cells 111 are detected by the sense amplifier 120 and then held by the first latch circuit 140 When the word voltage level is increased or stepped up to the second level so that the second word level voltage is applied by the word level generator circuit 120. then the ON/OFF states of the four kinds of the mask programmable read only memory cells 111 are detected by the sense amplifier 120 and then held by the second latch circuit 150. When the word voltage level is increased or stepped up to the third level so that the third word level voltage is applied by the word level generator circuit 120, then the ON/OFF states of the four kinds of the mask programmable read only memory cells 111 are detected by the sense amplifier 120 and then held by the third latch circuit 160. The data decoder circuit 170 fetches data about ON/OFF states of the mask programmable read only memory cells 111 held in the first to third latch circuits 140, 150 and 160 in order to decode the combinations of the ON/OFF states of the mask programmable read only memory cells 111 for every steps of the first to third word levels. Two bits of the decoded binary digit signals are outputted through the first and second output buffer circuits 180 and 190 respectively.
As described above, the three different word levels are determined pre-supposing that the every mask programmable read only memory cells 111 have any of the four threshold voltages. Actually, however, some of the mask programmable read only memory cells 111 may have threshold voltages which are slightly different from the above four threshold voltages. Even though the impurity is diffused into the diffusion region of the MOS field effect transistor as the mask programmable read only memory cell 111 to attempt to obtain a specific one of the four different threshold voltages, this mask programmable read only memory cell 111 may have a threshold voltage slightly different from the intended one of the four different threshold voltages. Further, even a dose of the impurity implantation into the diffusion region of the MOS field effect transistor as the mask programmable read only memory cell 111 to attempt to obtain a specific one of the four different threshold voltages, this mask programmable read only memory cell 111 may have a threshold voltage slightly different from the intended one of the four different threshold voltages. Accordingly, the mask programmable read only memory cells 111 have a distribution in the number of the mask programmable read only memory cells 111 versus variations of the actual threshold voltage from any one of the four intended threshold voltages different from each other. The distribution in the number of the mask programmable read only memory cells 111 versus variations of the actual threshold voltage from any one of the four intended threshold voltages is due to manufacturing processes and other factors. The width of the distribution or variation profile is also variable. FIG. 3 is a graph illustrative of a distribution in the number of the mask programmable read only memory cells 111 versus variations of the actual threshold voltage from any one of the second and third threshold voltages Vt1 and Vt2, wherein a read line dtbVt2 represents the third threshold voltage distribution having a width of .+-.0.3 V from the third threshold voltage Vt2, whilst a broken line dtbVt2' represents the third threshold voltage distribution having a width of .+-.0.6 V from the third threshold voltage Vt2. Some of the mask programmable read only memory cells 111 have threshold voltages which fall into the second or third threshold voltage distributions dtbVt1 or dtbVt2 or dtbVt2'.
By contrast, the word levels have no variation nor distribution from the predetermined voltage levels. The second word level is fixed at an intermediate between the second threshold voltage Vt1 and the third threshold voltage Vt2 independently from the distribution in the number of the mask programmable read only memory cells 111 versus variations of the actual threshold voltage from any one of the second and third threshold voltages Vt1 and Vt2. The large distribution represented by dtbVt2' in the number of the mask programmable read only memory cells 111 versus variations of the actual threshold voltage from any one of the second and third threshold voltages Vt1 and Vt2 has a base which superimposes over the second word level. In this case, a small number of the third kind of the mask programmable read only memory cells 111 as having attempted to possess the third threshold voltage Vt2, actually, however, possess threshold voltages lower than the third threshold voltage Vt2 by not less than 0.5 V. This results in that the small number of the third kind of the mask programmable read only memory cells 111 possessing threshold voltages lower than the third threshold voltage Vt2 by not less than 0.5 V turn ON by applying the second word level although all of the third kind of the mask programmable read only memory cells 111 should have to remain in the OFF state. As a result, incorrect output data are obtained.
Japanese laid-open patent publication No. 7-176636, it is attempts to solve the above problem by widening differences among the threshold voltages. This conventional attempt widens a range of the threshold voltages, for which reason there is a limit to widen the differences of the threshold voltages. If there is a large distribution represented by dtbVt2' in the number of the mask programmable read only memory cells 111 versus variations of the actual threshold voltage from any one of the predetermined or intended threshold voltages, then the above problem with superimposition of the base of the distribution over the fixed word level to cause the incorrect outputs. In the light of this, the conventional attempt does not solve basically the above problem.
In the above circumstances, it had been required to develop a novel multiple-valued mask programmable read only memory semiconductor device free from the above problem.
USPTO Backgrounds
USPTO Backgrounds