The telecommunications industry has long relied upon Global Positioning System, GPS, technology for mobile backhaul synchronization. However, some in the industry would prefer not to be tied to GPS, given its ownership and control by the United States government. For this reason and others, telecommunication companies are interested in using technologies like Synchronous Ethernet or “SYNC-E” and the IEEE 1588 Standard for “A Precision Clock Synchronization Protocol for Networked Measurement and Control Systems”, to meet their network synchronization needs.
IEEE 1588, which has been around for a number of years, is a protocol for maintaining synchronization between distributed “devices” that are communicatively interconnected. Here, the term “device” is used generically and may denote geographically distributed nodes in a communications network or different cards and backplanes within a rack of circuitry. According to IEEE 1588, master and slave clocks exchange timing messages to maintain synchronization between the slave clock and the corresponding master clock. A given device may have both master and slave clock ports, and may act as a synchronization slave with respect to one device and act as a synchronization master with respect to another device.
Critically, IEEE 1588 introduced hardware-based time stamping as a mechanism to significantly improve the synchronization between devices. With hardware-based time stamping, each device maintains a continuous, current local time in seconds and nanoseconds, e.g., based on a 1 GHz clock signal, and uses this time to timestamp the arrival and departure times of timing messages exchanged between devices having a master/slave synchronization relationship. Moreover, the message protocol implemented by IEEE 1588 enables the master and slave devices to estimate the path delays between them. The ability to estimate the path delays, also sometimes referred to as the “wire” delays, enables synchronization slaves to “see” the difference between their local times and the local time at the synchronization master at a high resolution, e.g., at the nanosecond resolution.
However, this level of precision specified in the standard makes implementation of these technologies challenging. Exceedingly careful design and implementation is needed to meet the applicable timing requirements. Timing performance problems arise for a variety of reasons, such as from practical limits on the quality or precision of the timing circuitry included in the devices included in the distributed timing system. Further, even where clock circuitry of suitable precision and stability is used, the failure to address timing jitter and other clocking errors may prevent compliance with the applicable timing requirements over a broad range of operating conditions and component tolerances.
USPTO Backgrounds
USPTO Backgrounds