Exemplary embodiments relate generally to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device and a method of manufacturing the same, which reduce an interference phenomenon between conductive lines.
A semiconductor memory device includes a plurality of memory cells. An electrical signal is supplied to the memory cells through conductive lines. An insulating layer is formed between the conductive lines, and the conductive lines are thus electrically insulated from each other. Accordingly, parasitic capacitance may be generated between the conductive lines adjacent each other with the insulating layer interposed therebetween. An interference phenomenon is generated between the conductive lines because of the parasitic capacitance, and increases with a reduction in the size of the gap between the conductive lines due to a high degree of integration of semiconductor memory devices.
FIG. 1 is a cross-sectional view illustrating an interference phenomenon between conductive lines, for example, in a conventional NAND flash memory device.
Referring to FIG. 1, a gate of the NAND flash memory device has a stack structure, including a gate insulating layer 3, a first conductive layer 5, a dielectric layer 7, and a second conductive layer 9 stacked over a semiconductor substrate 1. The first conductive layer 5 of a memory cell is used as a floating gate, and the second conductive layer 9 is used as a control gate. Furthermore, the control gates of the memory cell are coupled to a word line and are supplied with signals. An insulating layer 11 fills the spaces between the stack-type gates. With an increase in the degree of integration of semiconductor memory devices, the gap between the gates narrows and the interference phenomenon between the gates therefore tends to increase.
FIG. 2 is a diagram illustrating the deterioration of a threshold voltage distribution characteristic due to an increase of the interference phenomenon.
Referring to FIG. 2, it is ideal that threshold voltages Vth of memory cells having a specific program state are distributed as shown in S1. However, the distribution of program threshold voltages Vth of the memory cells may expand as shown in S2 due to the interference phenomenon between gates, leading to a reduction in the yield of semiconductor memory devices. Accordingly, there is a need for a method capable of reducing the interference phenomenon.
USPTO Backgrounds
USPTO Backgrounds