Random access volatile storage apparatus, such as semi-conductor device storage apparatus, have gained wide acceptance in the data processing industry because of low cost and high performance and cost. Access to registers within such semi-conductive data storage apparatus requires high speed address register selection circuits of diverse design. These circuits being high speed can be subject to errors. It is, therefore, desired to have various error checking schemes for ensuring that the addressing operations are error free.
Semi-conductor data storage apparatus are used as cache or buffering devices for peripheral data storage apparatus, such as direct access storage devices (disk storage apparatus). See Eden et al U.S. Pat. No. 3,569,938. In some applications of the transfer of data between disk storage apparatus and semi-conductor data storage apparatus and between semi-conductor data storage apparatus and host computers are in blocks of a large plurality of data signals, for example, 4,096 bytes of data. When the buffer is a designated portion of a larger data storage apparatus which can store other data including control data signals, then the blocks of data are stored in so-called allocated portions of the buffer. When transferring blocks of data, the transfer can become skewed with respect to the mapping of the blocks in the buffer; accordingly, the integrity of the data is destroyed by such addressing errors.
In some applications, such as paging and swapping applications, it is desired that the blocks of data within the buffer be logically independent. This logical independence is achieved by requiring that the address register driving the addressing circuitry for the data storage apparatus be loaded with a new address each time a block of data is to be stored in the data storage apparatus or fetched from the data storage apparatus. When such logical independence is not followed, error conditions can occur in the host system in that the logical relationships of the blocks of data as stored in the data storage apparatus have no relationship to the usage of such blocks of data by the host computer. Therefore, it is extremely important that the data storage apparatus independently access each block of data such that the logical relationship between the blocks of data in the data storage apparatus are maintained with respect to the logical characteristics of such data. This requirement can be easily achieved by requiring that the address register be loaded with a new address each time an area of the data storage apparatus is accessed for either recording data signals or reading data signals. A low cost and efficient error checking system is desired to ensure proper operation of such data storage apparatus.
USPTO Backgrounds
USPTO Backgrounds