1. Field of the Invention
The present invention generally relates to latch circuits and, more particularly, to an improved dynamic random access memory (DRAM) input latch circuit that makes the transition from "set" to "latched" states without the need for multiple phases, critical timing or introduction of extra periods into any timings to account for worst case scenarios.
2. Description of the Related Art
In low power computer applications, such as battery powered lap top computers, it is conventional to provide a "row address receiver" for dynamic random access memories (DRAMs) which is completely quiescent; that is, the circuit uses no power until an activation signal is presented. Such a no-quiescent-power requirement is standard in low power applications. To this end, the input receiver(s) for the circuit must be turned off when not being used.
In the prior art, when the receiver is turned off, activation is accomplished in two phases. First, the receiver is powered up. After a suitable delay, its output is evaluated and the result is driven to other circuits on the chip. There is, however, a problem in determining what the "suitable delay" should be since it is not clearly known exactly how long the receiver will take to establish a valid output, this being determined in part by the amplitude of the input signal. An input at one of the supply rails will cause the receiver to establish a valid output quickly, while if it is at the input "specification values", a longer time may be taken.
It is then necessary, in the prior art, to add "fat" (i.e., extra time periods) to the "suitable delay" in order to give the receiver adequate time to develop output with the worst case input signal. This "fat" is then present in every case and usually does not represent real-world operation. Therefore, in most cases, there is a performance penalty.
USPTO Backgrounds
USPTO Backgrounds