1. FIELD OF THE INVENTION
This invention relates to sensing systems for nonvolatile memory transistor arrays.
2. DESCRIPTION OF THE PRIOR ART
Nonvolatile memory transistor arrays have seen substantial development over the last several years. Of course, the nonvolatility of these transistor arrays is a highly desirable characteristic in that the information, the logic state written into the transistor, is not lost during a power-off state. A significant part of this continuing development has been in the specific fields of MNOS (Metal Nitride Oxide Silicon) memory transistors and floating gate memory transistors. However, for both of these specific types of memory transistors, the electrical characteristics of the transistor change over the course of time as the transistor is continually written and erased. Indeed, such degradation occurs even during static states.
In the nonvolatile MNOS memory application, the information in the form of digital "1" and "0" states is recorded within the MNOS transistor by stressing the transistor gate with high voltages of opposite polarities, usually on the order of .+-.20 to 25 volts. The MNOS memory transistor is specifically constructed such that the stressing of the transistor gate will cause a substantially permanent change in the threshold voltage level of the transistor. The two different threshold voltage levels correspond to the "1" and "0" digital logic states desired to be recorded. By appropriately sensing the state of an individual memory transistor within the memory transistor array, the digital logic information recorded within each transistor within the array may be accessed.
More specifically, in the case of an N-channel MNOS transistor, the application of a positive voltage on the order of 20 to 25 volts to the gate of the transistor in a write operation will cause the threshold of the device to shift in the positive direction. Conversely, a negative voltage of similar amplitude in an erase operation will cause the threshold voltage level to shift in a negative direction. Normally the more positive threshold is defined as a binary "0" and the less positive is defined as a binary "1".
The threshold shift in the MNOS transistor is due to the trapping by the silicon nitride layer of charges which tunnel through the thin gate oxide layer under the influence of the high field produced by the gate voltage stress. In some instances the charges can also be injected directly from the gate. In any case, the charges initially reside near the SiN (silicon nitride)-SiO.sub.2 (silicon dioxide) interface, but, over time tend to redistribute themselves through out the SiN due to Coulombic repulsion. Additionally, some of the stored charge will leak back to the silicon substrate by tunneling through the thin silicon dioxide layer. By the action of either of these processes, the device will tend to lose the stored information over time, a property characterized as limited "retention".
Additionally, the MNOS memory transistor "degrades" with the number of times it has been programmed. Its characteristics change because of this endurance defect. In most cases, this degradation will be manifested by either a worsening in the retention properties of the device or a gradual drift in the threshold voltage level towards a more positive voltage. Also, interrogation of the device (sensing) is only partially nondestructive. This phenomenon is known as the read-disturb effect.
In order to sense the threshold voltage level of an individual transistor within the memory array, a "reference" must be provided which will distinguish between the two possible threshold voltage levels of the individual memory transistor. In the ideal case, the reference should function over a wide range of programming voltages and programming times, since both voltage and time determine the programmed threshold voltage level of the individual MNOS transistors. The reference procedure must track the individual MNOS transistor characteristics as they change over time under the influence of the retention, endurance, and redisturb effects. Prior art devices commonly use separate MOS non-memory transistors as the reference devices. These MOS transistors are specifically constructed to produce the desired threshold voltage level for the reference device. However, these prior art MOS reference devices have threshold reference characteristics which are constant over time. Since the memory MNOS transistors have threshold voltage characteristics which change over time, the prior art MOS reference devices are not entirely suitable. In the present invention, identical MNOS transistor devices are utilized as reference transistors, thereby imparting a self-tracking ability to the sensing system.
Floating gate nonvolatile memory transistors represent another nonvolatile memory technology. As in the MNOS technology, the threshold voltage level of an individual floating gate memory transistor can be programmed to either a logic "1" or a logic "0" state. Either tunnelling or avalanche injection mechanisms can be employed to transfer the charges into the isolated polysilicon layer by the action of a large programming field across the gate dielectric. Although the readisturb and retention effects are less severe for the floating gate devices than for the MNOS devices, the floating gate devices exhibit much more severe endurance effects because of the large electric field required to program the device. Strategies for the design of the sensing system for the floating gate nonvolatile transistors are similar to the design strategies for the MNOS memory arrays.
USPTO Backgrounds
USPTO Backgrounds