In the related prior art there have been logic circuit types or families known as Si CMOS, GaAs DCFL and GaAs super buffer; an example of a typical prior Si CMOS being shown schematically in FIG. 1, an example of a typical GaAs DCFL being shown schematically in FIG. 2 and an example of a typical prior art GaAs super buffer being shown in FIG. 3.
In the present invention the generalized circuit or conceptual diagram is shown in FIG. 4 to be followed by specific circuit embodiments. Some of the advantages of the present invention over the previously known circuits include:
the new circuit is faster than Si MOS or GaAs DCFL PA0 it has a higher noise margin than GaAs DCFL PA0 the power is lower than in a super-buffer PA0 this circuit drives high capacitance much faster and at lower power than DCFL or other circuits that don't turn off after the output transition (i.e., the capacitance charging current is relatively large and this current nearly turns off after output is "high", thus saving power) PA0 unlike CMOS, only one type of transistor (enhancement mode) is needed for some embodiments of the invention.
USPTO Backgrounds
USPTO Backgrounds