1. Field of the Invention
The present invention relates to diode arrays and, more particularly, to means for separating individual diode array chips from a fabrication wafer.
2. Description Relative to the Prior Art
Light-emitting diode (LED) array chips are made in the same way as are many other types of solid state chip devices, by forming a large number of identical rectangular shaped array areas in rows and columns on a substrate wafer and then subsequently sawing or cleaving the wafer between the rows and columns to separate it into individual chips. An LED array chip is provided with a central row of uniformly spaced light-emitting sites and is subsequently mounted in end-to-end relation with other identical chips to produce an array assemblage with a continuous row of uniformly spaced light-emitting sites. The light-emitting sites of such an array may have a density of 200 or more per centimeter with a typical array assemblage being 25 centimeters or more in length. In order that the spacing between the diode sites at the ends of adjacent chips will be the same as that between the other diode sites, the ends of the chips must extend beyond the adjacent endmost diode sites by no more than half the distance between such sites along the chips, but must not encroach upon the endmost sites. For example, if the spacing between adjacent diode sites is 20 .mu.m, this means that the end of each chip must be not more than 10 .mu.m beyond the adjacent endmost diode site, but must be spaced from that site sufficiently to prevent a threat of physical damage to the site. Because of this demanding tolerance, sawing techniques have proven insufficiently accurate to define the ends of the diode array chips without resort to expensive subsequent lapping operations or the like. Sufficient dimensional accuracy can be achieved without secondary operations by scribing a cleavage groove on the wafer and then cleaving it along the cleavage plane established by scribed groove, and machines for carrying out this process are commercially available.
Various different techniques are commonly employed to cleave the wafer; for example, striking a knife-like edge positioned along the cleavage groove; inducing a bending force in the wafer at opposite sides of the cleavage groove by resiliently supporting the back face of the wafer and by pressing on the top face at opposite sides of the scribe line with a resilient roller or platen; or clamping the wafer at one side of the groove and applying a bending force beyond the groove to induce cleavage. The resulting fractured edge of the wafer can be very precisely located, but, in many cases, a small ledge or lip will be formed at the edge of the fracture opposite the scribe line, projecting beyond the cleavage plane sufficiently to prevent end-to-end positioning of the chips. Because the cleaving forces exerted on the chip by the foregoing techniques are generally symmetrical relative to the cleavage line, such a ledge or lip can occur on either of the two fracture faces. Such a lip or projection can be removed by a subsequent lapping operation or the occurrence of this phenomenon can be reduced by sawing a groove or channel along the back face of the wafer in the cleaving area, but such operations obviously add to the production costs.
USPTO Backgrounds
USPTO Backgrounds