A 3D semiconductor device (or stacked IC device) can contain two or more semiconductor devices stacked vertically so they occupy less space than two or more conventionally arranged semiconductor devices. The stacked IC device is a single integrated circuit built by stacking silicon wafers and/or ICs and interconnecting them vertically so that they behave as a single device.
Conventionally, the stacked semiconductor devices are wired together using input/output ports either at the perimeter of the device or across the area of the device or both. The input/output ports slightly increase the length and width of the assembly. In some new 3D stacks, through-silicon vias (TSVs) completely or partly replace edge wiring by creating vertical connections through the body of the semiconductor device. By using TSV technology, stacked IC devices can pack a great deal of functionality into a small footprint. This TSV technique is sometimes also referred to as TSS (Through Silicon Stacking). Furthermore, critical electrical paths through the device can be drastically shortened, reducing capacitance and resistance and therefore improving power dissipation, and performance.
Assembly and packaging of semiconductor devices should take into account the adverse affects of electrostatic discharge. Conventionally, there are several ways of reducing ESD. One is to provide proper grounding of assembly equipment parts to prevent charge buildup that may result in discharge capable of destroying circuit components, such as transistors. A second is use of ionized air-flow to reduce charge build-up on the ICs and the assembly fixtures. Another way is to eliminate or reduce ESD damage by providing ESD protection circuitry on the semiconductor device.
However, in stacked IC device assembly and connection, to maximize the density of connections and reduce electrical parasitics, circuit-level ESD protection is reduced or eliminated. The semiconductor devices may then be more susceptible to damage from ESD during assembly. The same ESD susceptibility concerns apply whether the assembly process is chip-to-chip (i.e., IC-to-IC) or chip to wafer (i.e., IC-to-wafer) or wafer to wafer. Therefore, there is a need to develop methods and structures to enable the assembly of stacked IC devices with reduced sensitivity to ESD when protection circuitry is not included in every individual IC or wafer.
USPTO Backgrounds
USPTO Backgrounds