1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor chip accommodated in a package.
2. Description of the Related Art
Generally, packages for semiconductor devices are not newly designed as being uniquely manufactured for certain semiconductor device configurations, but are manufactured beforehand in several sizes and shapes according to certain classifications and standards. When a semiconductor device is manufactured, a package which has the number of pins and the bent lead shape that are suitable for the type and current capacity of a semiconductor chip to be accommodated is selected from among the available packages, and the semiconductor chip is placed in the selected package.
FIG. 1 of the accompanying drawings shows a discrete semiconductor device with a small-size SMT (Surface Mount Type) package. The discrete semiconductor device shown in FIG. 1 is manufactured as follows: A semiconductor chip 1 is mounted on an island 2 of a lead frame by an adhesive according to die bonding. A bonding pad of the semiconductor chip 1 is connected to lead terminals 4 by bonding wires 5 according to bonding wire bonding. The lead frame is then set in a mold whose mold cavity has a desired shape, after which an epoxy resin is injected into the mold cavity. When the epoxy resin is solidified, the lead frame and the semiconductor chip 1 are encased by an epoxy resin body 6. The lead terminals 4 extending out of the epoxy resin body 6 are bent into a Z shape for a surface mount application.
Efforts are being made to reduce the size and increase the capacity of the illustrated discrete semiconductor device. Consequently, there is a demand for mounting larger semiconductor chips in packages of the same size.
The maximum size of a semiconductor chip that can be accommodated in a package is mainly governed by the area of the island 2 of the lead frame. The area of the island 2 depends on the outer dimensions of the semiconductor device minus a removal clearance required for the island 2 and the lead terminals 4 and the thickness of a layer between the loop of the bonding wires 5 and the upper surface of the epoxy resin body 6. The area of the island 2 is also limited by a loop height t of the bonding wires 5. For these reasons, certain difficulties are encountered in mounting larger semiconductor chips in packages of the same size.
In FIG. 1, the bonding wires 5 are connected by a first bond to the bonding pad on the semiconductor chip 1, then shaped into a loop by a capillary tool, and finally connected by a second bond to the lead terminals 4. The bonding wires 5 thus bonded electrically interconnect the semiconductor chip 1 and the lead terminals 4 through the loop having the loop height t. In order to reduce a thickness 7 of the semiconductor device, it is necessary to reduce the loop height t. When the loop height t is reduced, however, the angle 0 of the bonding wires 5 with respect to the lead terminals 4 is also reduced. If the size of the semiconductor chip 1 were increased under such a limitation, then a corner of the semiconductor chip 1 would be brought into contact with the bonding wires 5 at a region A, resulting in an electric short circuit.
Because of the above limitation imposed by the bonding wires 5 in addition to the dependency on the area of the island 2, it is impossible to accommodate semiconductor chips whose sizes are greater than a certain size in the package.
Furthermore, if the bonding wires 5 are increased in diameter because of an increase needed in the current capacity of the semiconductor chip 1, then since the mechanical strength of the bonding wires 5 increases, the curvature of the bonding wires 5 has to increase in a region B. Since the increase in the curvature of the bonding wires 5 results in an increase in the loop height t, there is a certain limitation on increasing the diameter of the bonding wires 5. If the curvature of the bonding wires 5 were excessively large, then the bonding wires 5 would tend to be detached from the semiconductor chip 1 in a region C.
For example, when the diameter of the bonding wires 5 increases from 20xcexc to 60 xcexc, the loop height t increases by the diameter difference of 20xcexc to 40xcexc even if the bonding wires 5 are shaped into the same loop.
It is therefore an object of the present invention to provide a semiconductor device which allows a larger semiconductor chip to be mounted in a package of the usual size.
Another object of the present invention is to provide a semiconductor device which includes bonding wires bent at relatively large angles to prevent their loops from being positioned at an unwanted height when the bonding wires have a relatively large diameter.
According to the present invention, there is provided a semiconductor device comprising an island, a semiconductor chip fixedly mounted on the island and having a bonding pad thereon, a lead terminal having an end disposed closely to the island, a bonding wire connecting the bonding pad to the lead terminal, and a molded resin body encasing the semiconductor chip and the bonding wire.
The bonding wire may include a first extension bonded to the bonding pad and ascending substantially vertically from the bonding pad to a predetermined height, a second extension extending from the first extension to a location near an end of the semiconductor chip substantially at the predetermined height, and a third extension descending from the second extension and bonded to the lead terminal.
The bonding wire may also include a first bend positioned upwardly of the bonding pad, a second bend positioned upwardly of an end of the semiconductor chip or between the end of the semiconductor chip and a bond by which the bonding wire is joined to the lead terminal, and a third bend positioned between the first bend and the second bend.
The third extension of the bonding wire extends downwardly at a large gradient toward the lead terminal, with the second bend being positioned upwardly of the end of the semiconductor chip. This arrangement is effective in reducing the distance between the end of the semiconductor chip and the bond by which the bonding wire is connected to the lead terminal. Consequently, a relatively large semiconductor chip may be accommodated in a package of the usual size. The second and third bends keep the bonding wire out of contact with a corner of the semiconductor chip. The height of the first extension can thus be reduced, and hence the thickness of the package can also be reduced.
The first and second bends have relatively large angles, thus preventing the bond by which the bonding wire is bonded to the bonding pad from suffering excessive stress. As a result, the bonding wire may have a relatively small loop height even if the bonding wire has a relatively large diameter. The semiconductor chip may have an increased chip size for an increased maximum rated output, and the bonding wire may be relatively thick for an increased current capacity to meet such an increased maximum rated output. The semiconductor chip of increased size and maximum rated output capability can be accommodated in a package of the usual size.
The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
USPTO Backgrounds
USPTO Backgrounds