1. Field of the Invention
The present invention relates to a packaged semiconductor device in which a package for mounting high-speed LSI elements at a high density is made of glass or a ceramic, and a method of manufacturing the same.
2. Description of the Prior Art
For a future multimedia society, a demand for smaller, higher-speed electronic apparatuses and systems is becoming more and more intense, as is represented by personal computers and portable telephones. In addition, a demand in recent years for a lower cost is very strict.
In order to solve these problems, the semiconductor chips themselves are highly integrated at a high density, as a matter of course. Also, a chip packaging method and a mounting technique concerning how to mount packaged chips on a board become important.
In the manufacture of semiconductor chips and LSIs, development of the micropatterning technique as well as an increase in diameter of the wafer are the most significant techniques to decrease the cost. Development of wafers having a diameter of 8 to 12 inches and furthermore 16 inches has been started.
Concerning chip packaging, as the integration degree increases, the number of I/O connection points increases accordingly. Thus, in the conventional DIP and QFP structures, connection between the leads and the board has become difficult to perform. If a chip package is forced to have the DIP or QFP structure, the package size becomes very large compared to the chip size. Then, not only the mounting efficiency is degraded, but also the parasitic L and C components in the lead portion adversely affect a high-speed chip.
In order to solve these problems, a technique has been developed with which a chip is not packaged but is connected in a bare state to a board without using leads. When chip-side electrodes and board-side electrodes are connected to each other in a point contact manner through solder balls or Au bumps, two-dimensional planar connection rather than conventional one-dimensional linear connection becomes possible, thus remarkably improving the mounting performance. This technique is called leadless chip (LLC) connection or flip-chip (FC) connection.
As described above, as a means of realizing a reduction in cost, an increase in wafer diameter has been made. Here, in a large-diameter wafer such as one having a diameter of 12 or 16 inches, since the strength of the wafer is low, with the current wafer thickness, cracking and the like occur. It is, therefore, difficult to employ the state-of-the-art LSI manufacturing process. If this process is employed, the thickness of Si wafer which will not be fractured becomes as large as 5 mm, and the effective utilization factor of the ingot decreases extremely. Accordingly, brittleness of the Si wafer is the largest problem in increasing the wafer diameter.
In order to decrease the cost, the bare-chip mounting method called LLC connection or FC connection has been developed, as described above. With this method, how to inspect a bare chip poses a problem. Since an inspection process in the bare-chip level has not been established yet, sometimes the semiconductor manufacturer cannot guarantee the defectiveness/non-defectiveness of the chip to the system manufacturer. If a plurality of defective chips are mixedly mounted on the board, the board yield is degraded immediately. A chip not protected by the package cannot be handled well by the system manufacturer. Furthermore, a major problem exists as to how to manufacture a substrate having electrodes with the same precision as that of the small-pitch electrodes of the chips at a low cost. In a substrate employed for LLC connection or FC connection, in order to ensure the reliability of connection, very strict limitations arise concerning not only the positional precision of the electrodes but also the smoothness and warp of the substrate. Then, the number of processes, e.g., the substrate polishing process and a developing/exposure process for circuit formation, that lead to a high cost, increases.
In order to solve the problem of chip protection and inspection process and to increase the mounting efficiency, a concept of chip size package (or chip scale package) is recently proposed and its development has started. According to this concept, a package close to the chip size is fabricated. An Si chip is connected to this package without using leads, and the Si chip together with the package is further connected to a board. According to this method, although the problem of chip protection and inspection is solved, since the board is merely replaced with the chip size package, the problem of whether a package that can realize leadless connection at a low cost still remains unsolved.
USPTO Backgrounds
USPTO Backgrounds