The present invention relates to flash electricall-erasable, programmable read-only memories (EEPROMs). In particular, the present invention relates to source biasing circuits for flash EEPROMs.
FIG. 1 shows a conventional EEPROM 20. The EEPROM 20 includes a number of cell transistors 22, a number of bit lines 24 running vertically, a number of word lines 26 running horizontally, a number of source lines 28 running horizontally, and a source bias generator circuit 30. The cell transistors 22 store the information in the EEPROM 20. Information may be written to or read from the cell transistors via the bit lines 24, word lines source lines 28 and associated read/write circuitry (not shown).
During a read or programming operation, the source bias generator 30 receives a control signal 32 indicating that the source bias generator 30 should couple the source lines 28 to ground. (During other operations the source bias generator 30 may couple the source lines 28 to a positive voltage Vsource). The source lines 28 are coupled by an N+ active diffusion layer.
In order to reduce source line resistance, a number of metal lines 34 running vertically couple the source lines 28. The source line resistance is manageable when the number of bit lines 24 (or cell transistors 22) between every metal line 34 is limited to sixteen or fewer, as further detailed below.
The source line resistance RSL may be calculated as follows. The N+ resistance for a narrow N+ active width is approximately 100 ohms per square (xcexa9/s). (Ohms per square means the resistance when length is equal to width.) Each cell transistor 22 has an X size (width) of approximately 1.0 xcexcm. The width of each source line is approximately 0.5 xcexcm. With 16 cell transistors 22 separating each metal line 34, the worst case source line resistance will be for the center cell transistor 22, as follows:
RSL=16*100xcexa9/s*1.0 xcexcm /0.5 xcexcm /4=800xcexa9
where the final division factor of 4 is due to having a metal line on each side.
During the programming operation, for a cell transistor 22 its gate is charged to approximately 9 V (via its word line 26), its drain is charged to approximately 5 V (via its bit line 24), and its source is coupled to ground (via source bias generator 30). However, the actual voltage present at the source of the cell transistor 22 will be nonzero due to the source line resistance. Generally, the Ids current in the stack gate using channel hot electron injection is approximately between 300 and 600 xcexcA, depending upon cell size and process conditions. If you assume a median value of 500 xcexcA, then the worst-case cell source voltage is as follows:                               V          s                =                  800          ⁢                      xe2x80x83                    ⁢          Ω          *          500          ⁢                      xe2x80x83                    ⁢          µ          ⁢                      xe2x80x83                    ⁢          A                                        =                  0.4          ⁢                      xe2x80x83                    ⁢          V                    
This nonzero source voltage affects programming efficiency. In addition, the Actual source voltage of a cell transistor 22 will depend upon its distance from the closest metal line 34, which causes programming inconsistency. For this reason, it is generally necessary to have one metal line 34 between every 16 or fewer cell transistors 22. This is a constraining factor when attempting to reduce the cell array size of the EEPROM 20.
Similarly, during the read operation, the Ids current for one cell is approximately between 50 and 150 xcexcA. If you assume a median value of 100 xcexcA, then the worst-case cell source voltage is as follows:                               V          s                =                  800          ⁢                      xe2x80x83                    ⁢          Ω          *          100          ⁢                      xe2x80x83                    ⁢          µ          ⁢                      xe2x80x83                    ⁢          A                                        =                  0.08          ⁢                      xe2x80x83                    ⁢          V                    
This 0.08 volts can also affect the bit line sensing voltage when the bit line voltage is approximately 1.0 volts. For these reasons, it is generally necessary to have one metal line 34 between every 16 or fewer cell transistors 22, which is a further constraining factor when attempting to reduce the cell array size of the EEPROM 20.
There is a need to reduce the cell array size of the EEPROM while maintaining a low source voltage during a read or programming operation on the EEPROM.
According to one embodiment, a source biasing circuit for an EEPROM includes a first set of two transistors, a second set of two transistors, and a third set of two transistors. The first set is coupled between an upper node supplying a source voltage and a lower node supplying a negative biasing voltage. The second set is coupled between the upper node and the lower node, and the second set is cross-couple to the first set. The third set is also coupled between the upper node and the lower node, and the third set is controlled by the second set to selectively couple one of the source voltage and the negative biasing voltage to a source connection of the EEPROM.
According to another embodiment, an EEPROM includes a number of bit lines, a number of word lines, a source connection, a number of cell transistors, and a source biasing circuit. The source biasing circuit is coupled to selectively provide a negative biasing voltage to the source connection.
According to yet another embodiment, a method of improving read or programming performance of an EEPROM includes the act of selectively providing a negative biasing voltage to a source connection of the EEPROM. The method further includes the act of.
One benefit of the present invention is that it reduces the number of required metal lines while maintaining an acceptable source voltage. In this manner, the cell array size of the EEPROM may be reduced.
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