This invention relates generally to semiconductor integrated circuit fabrication techniques and, more particularly, to techniques for ensuring adequate electrical isolation of multiple semiconductor devices formed on a common substrate. Device isolation is important in any integrated circuit (IC) and is critical to the design of integrated circuits that operate at higher frequencies, such as microwave monolithic integrated circuits (MMICs). In MMICs, a typical transistor device is the high electron mobility transistor (HEMT), which behaves much like a conventional field effect transistor (FET), but incorporates a conducting channel created by a heterostructure that confines charge carriers to a thin layer. The concentration of the carriers and their speed in this layer enables the transistor to maintain a high gain at very high frequencies. The heterostructure in a HEMT typically comprises multiple semiconductor layers formed epitaxially and appropriately etched to form a mesa projecting above the substrate. Device connections are made through contacts at the top of the mesa and device isolation is attained by ensuring that there is sufficient geometric clearance between adjacent devices.
The mesas of HEMTs or similar semiconductor structures are formed on a substrate that, for purposes of electrical isolation, must include areas of a relatively non-conducting material. This requirement is relatively easy to meet if the semiconductor structures are based on materials that are inherently semi-insulating, such as structures based on gallium arsenide (GaAs). There are, however, significant advantages, in terms of improved electrical properties, in using semiconductor heterostructures that include antimony-based layers as electron barriers. Unfortunately, there is no compatible semi-insulating substrate material for antimony-based semiconductors, and growing any antimony-based layer on a semi-insulating substrate of another material, such as GaAs, results in lattice defects, referred to as threading dislocations, in the antimony-based layer because the lattice parameter of the layer does not match that of the substrate. One way to mitigate the effect of the threading dislocations is to include a relatively thick metamorphic buffer layer of an antimony-based material, such as aluminum antimonide (AlSb). This effectively “buries” the dislocations, which become less pronounced towards the top of the buffer layer. Although the desired antimony-based layers may be formed epitaxially on the antimony-based (AlSb) buffer, this approach suffers from a significant disadvantage in that the AlSb material is not stable in air. Components or electrodes formed over an AlSb buffer inevitably suffer serious damage as the AlSb buffer disintegrates with exposure to air.
Accordingly, there is still a need for a technique for achieving mesa isolation in antimony-based semiconductor structures. The present invention satisfies this need.
USPTO Backgrounds
USPTO Backgrounds