1. Field of the Invention
This invention is related to the field of processors and, more particularly, to combining write buffers in caches.
2. Description of the Related Art
Processors often implement combining write buffers to capture write operations that have been written to a higher level write-through cache (e.g. an L1 cache), to buffer those writes prior to updating a lower level cache (e.g. an L2 cache). The combining write buffer combines two or more write operations that target data within the same cache block, and thus present fewer writes to the L2 cache.
The combining write buffer can accumulate write operations for some time. Determining when to flush write operations from one or more combining write buffer entries is a tradeoff between bandwidth and performance. Buffering write operations in the combining write buffer can lead to better bandwidth efficiency. On the other hand, if data is buffered for too long, the performance may suffer as data that needs to be pushed to lower level caches or memory remains in the combining write buffer.
USPTO Backgrounds
USPTO Backgrounds