Field
Embodiments generally relate to methods for forming three dimension structures with desired materials on a semiconductor substrate. More specifically, embodiments relate to methods for forming three dimension structures on a semiconductor substrate with different materials at different locations of the structure by a selective atomic layer deposition process utilizing patterned self assembled monolayers and a directional plasma process for fin field effect transistor (FinFET) semiconductor manufacturing applications.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. In order to enable the fabrication of next generation devices and structures, three dimensional (3D) stacking of features in semiconductor chips is often utilized. In particular, fin field effect transistors (FinFET) are often utilized to form three dimensional (3D) structures in semiconductor chips. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reduced short channel effect and higher current flow.
FIG. 1A depicts an exemplary embodiment of a fin field effect transistor (FinFET) 150 disposed on a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a substrate formed from other semiconductor materials. In one embodiment, the substrate 100 may include p-type or n-type dopants doped therein. The substrate 100 includes a plurality of semiconductor fins 102 formed thereon isolated by shallow trench isolation (STI) structures 104. The shallow trench isolation (STI) structures 104 may be formed by an insulating material, such as a silicon oxide material, a silicon nitride material or a silicon carbon nitride material.
The substrate 100 may include a portion in NMOS device region 101 and a portion in PMOS device region 103 as needed, and each of the semiconductor fins 102 may be sequentially and alternatively formed in the NMOS device region 101 and the PMOS device region 103 in the substrate 100. The semiconductor fins 102 are formed protruding above the top surfaces of the shallow trench isolation (STI) structures 104. Subsequently, a gate structure 106, typically including a gate electrode layer disposed on a gate dielectric layer, is deposited on both of the NMOS device region 101 and the PMOS device region 103 and over the semiconductor fins 102.
The gate structure 106 may be patterned to expose portions 148, 168 of the semiconductor fins 102 uncovered by the gate structure 106. The exposed portions 148, 168 of the semiconductor fins 102 may then be doped with dopants to form lightly doped source and drain (LDD) regions using an implantation process.
FIG. 1B depicts a cross sectional view of the substrate 100 including the plurality of semiconductor fins 102 formed on the substrate 100 isolated by the shallow trench isolation (STI) structures 104. The plurality semiconductor fins 102 formed on the substrate 100 may be part of the substrate 100 extending upwards from the substrate 100 utilizing the shallow trench isolation (STI) structures 104 to isolate each of the semiconductor fins 102. In another embodiment, the semiconductor fins 102 may be individually formed structures disposed on the substrate 100 that are made from materials different than the substrate 100 using suitable techniques available in the art. In the embodiment wherein different materials of the semiconductor fins 102 are required to be formed on different surfaces 120, including a first sidewall 120a and a second side wall 120b connected by a top surface 110, additional process steps may be performed to alter the materials of the semiconductor fins 102 formed on the different surfaces 120 of the semiconductor fins 102.
A conventional method for selective deposition may be performed to locally form a material layer on only certain locations of a planer surface on a substrate made from a material different than the substrate material. FIG. 2A-2C depict an existing process utilized to perform the deposition process. The process utilizes self assembled monolayers (SAM) as a surface modification layer to selectively modify surface properties of the different surface materials, exposed on the substrate. For example, a substrate 202 may include a feature 204 formed from a first material (e.g., a silicon oxide layer) disposed on the substrate 202 formed from a second material (e.g., silicon), as shown in FIG. 2A. The feature 204 has an opening 208 defined therein exposing a surface 206 of the substrate 202. Self assembled monolayers (SAM) 210 may then be formed on the substrate 202 by a solution based precursor, as shown in FIG. 2B. Generally, the self assembled monolayer (SAM) 210 may only be formed on the surface that has chemical reaction capability with the molecules from the self assembled monolayer (SAM) 210. In the embodiment depicted in FIG. 2B, the precursor utilized to form the self assembled monolayer (SAM) 210 is selected to only chemically react with a surface 212 of the feature 204, (e.g., a silicon oxide material), rather than the surface 206 of the substrate 202 (e.g., a silicon material). By doing so, the self assembled monolayers (SAM) 210 may be predominantly formed on the feature 204 on the substrate 202, leaving the surface 206 of the substrate 202 free of self assembled monolayers (SAM) 210. Subsequently, an atomic layer deposition (ALD), which is a process highly sensitive to surface conditions, having selected precursors, is then performed to form a structure 214 selectively on the designated surface 206 of the substrate 202, as shown in FIG. 2C.
By utilizing the self assembled monolayers (SAM) 210 formed the features 204, the structure 214 may be formed selectively on only designated surface 206 of the substrate 202. However, in cases when a substrate only contains one type of material, the self assembled monolayer (SAM) 210 may be globally formed on the entire surface of such substrate, thereby making the selective material deposition difficult to achieve. In other words, in the case wherein a structure on a substrate is formed by a single type of material, selective deposition via utilization of the self assembled monolayers (SAM) may not be successfully enabled, as the self assembled monolayer (SAM) is to be globally applied across without selectivity. For example, the fin structure 102 as depicted in FIG. 1B may be formed by one type of material. However, when only one type of material is desired to be selectively formed only on one side wall or one top or bottom surface, either the first sidewall 120a, top surface 110 or the second sidewall 120b of the fin structure 102, utilization of the self assembled monolayer (SAM) may not be successful as the self assembled monolayer (SAM) may globally formed on the whole outer surface 120 of the fin structure 102 without selectivity.
Thus, there is a need for improved methods for a selective deposition process suitable for three dimensional (3D) stacking of semiconductor chips or other semiconductor devices.
USPTO Backgrounds
USPTO Backgrounds