This invention relates to memory devices. More particularly, this invention relates to memory devices that use fewer circuit components for the same memory capacity while maintaining the same memory redundancy.
Many approaches have been used to increase memory density on dies. A die is a single piece of silicon (or other semiconductor) on which integrated circuits are fabricated. Memory density is the number of bits that can be stored in memory on a die. One way to increase memory density is to make the memory devices smaller. Another way is to reduce the number of circuit components required to implement the same memory capacity. For example, if one hundred circuit components can be interconnected to provide the same memory capacity as one hundred and fifty similarly sized circuit components, memory density is increased (because less area on the die is used, which allows for more memory capacity).
Memory devices are typically implemented on a die as a plurality of redundancy structures and memory cells. Memory cells store data, and redundancy structures store addresses for memory cells. Those structures may be used if any of those cells are identified as being damaged by pre-ship testing. Memory cells are typically arranged on a memory device as an array of rows and columns (primary rows and columns). Each intersection of a row and a column has an address. An external device such as a microprocessor uses an address of a memory cell (stored in a redundancy structure) to access the content of that memory cell.
Memory devices are tested for damaged rows and columns prior to shipping to a customer. Memory devices have several spare (redundant) rows and columns. If a portion of a primary row or column is damaged, a redundant row or column can be used to replace the damaged row or column. This is known as “repairing.” When a redundant row or column is used, the memory device is “programmed” to access a redundant memory cell of that row or column instead of the primary cell of the damaged row or column.
One way to program which memory cells are accessed is by using fusible links. Fusible links (hereinafter “fuses”) are integrated circuit components that are designed to break (or burn) when a relatively high current is selectively applied. This severs the connection between two points. Alternatively, “anti-fuses” are designed to connect two points. Memory cell programming usually occurs before the memory device is shipped to a customer.
A test circuit determines which memory cells, if any, are damaged. The addresses of damaged memory cells are programmed into “fuse banks” on the redundancy structure. If an address for a memory cell matches an address programmed into the fuse bank, logic is set up such that the access to the damaged cell is redirected to the replacement cell.
To provide full redundancy in a memory device using fuses, the number of fuses should equal the number of bits used to address the memory cell. Additionally, an equal number of XNOR gates are required. For example, if a seven-bit address is used to address a memory cell, then seven fuses and seven XNOR gates are required to provide full redundancy.
Fuses and XNOR gates consume large amounts of area on a die. Attempts have been made to reduce the number of fuses and XNOR gates on a die while maintaining substantially the same degree of memory redundancy. The success of these attempts has been limited, primarily because they have been based on trial and error.
In view of the foregoing, it would be desirable to be able to provide algorithms and other non-trial and error techniques that reduce the number of fuses and other circuit components (e.g., XNOR gates) on a memory die while maintaining the same memory redundancy.
USPTO Backgrounds
USPTO Backgrounds