Message signaled interrupts (MSI) are a feature that enables a device function to request service by writing a system-specified data value to a system-specified address using, for example, a memory write transaction. An MSI transaction enables a device function to request an interrupt service by sending the MSI transaction as an inbound memory write on its bus to the front-side bus (FSB) or the processor bus. Because an MSI transaction is generated in the form of a memory write, MSI transactions support transaction conditions such as a retry, master-abort, target-abort or normal completion. As added benefits, MSI transactions simplify board design by removing out of band interrupt routing and represent another step towards a legacy-free environment.
Message signaled interrupts allow a device to write a small amount of data to a special address in memory space. The chipset will deliver the corresponding interrupt to a processor (also referred to as a central processing unit or CPU). A common misconception with message signaled interrupts is that they allow the device to send data to the CPU as part of the interrupt. The data that is sent as part of the write is used by the chipset to determine which interrupt to trigger on which CPU; it is not available for the device to communicate additional information to the interrupt handler.
A drawback of MSI transactions is the latency involved with servicing an interrupt. For example, when a device requests an interrupt service using MSI, the device generates a MSI transaction including a system-specified message and a system-specified address. Once a processor receives the MSI transaction, the processor has to communicate with the requesting device to retrieve data required to service the interrupt. The processor may then service the interrupt using interrupt data received from the device. However, the latency involved with communications with the device may be relatively long. As a result, each interrupt serviced via a MSI transaction involves a long latency and adds traffic to, for example, the FSB, the memory controller hub (MCH), and/or, the input-output controller hub (ICH) coupling the device to the processor.
USPTO Backgrounds
USPTO Backgrounds