The present invention relates generally to the packaging of integrated circuits. More particularly, the invention relates to a stacked die configuration that permits a stacked die to be electrically connected to the die it is stacked on.
There are a number of conventional processes for packaging integrated circuits. In many situations it is desirable to incorporate multiple integrated circuit dice into the same package in what is commonly referred to as a multi-chip package. Some multi-chip packages are arranged to stack two or more dice on top of each other. These stacked die packages have several potential advantages including the possibility of a reduced die or package footprint and certain performance advantages (e.g., by reducing the path length of electrical connections between integrated circuits and thus potentially increasing speed and reducing inductance of inter-chip communications).
One stacked die configuration is generally illustrated in FIG. 1. In this configuration a first die 104 is mounted on a planar substrate 106. Bonding wires 108 are then used to electrically connect the first die 104 to the substrate 106 using conventional wire bonding. After wire bonding, an encapsulant 108 is screen printed over first the die 104 to form an internal package structure 110 that covers the first die. A second die 113 may then be adhesively secured to the top surface of the internal package 110 thereby creating a stacked die configuration. The second die 113 is then wire bonded to the substrate and an encapsulant material 115 is molded over the substrate to provide an encapsulant cap. Although this process can be used to create stacked die packages, the top die cannot be wire bonded directly to the bottom die because the screen printed encapsulant used to form the internal package structure covers all of the various bond pads. Since screen printing is used to form the internal packages, the process is not well suited for use with lead frames. Additionally, spacers may be required between adjacent device areas on the substrate panel to support the screen. The spacers take up valuable space on the substrate panel thereby reducing the device density on the panel.
Another stacked die approach is generally illustrated in FIG. 2. In this approach, an adhesive material 130 having ball like spherical support structures 132 therein is dispensed on the top surface of the lower die 138 in a region that is interior to the bond pads. The balls 132 effectively provide structural support for the adhesive so that the adhesive can be formed into a plateau that can be used to support a second die 141 (which includes a top surface 135). Both the top die 141 and bottom die 138 can be wire bonded (e.g., 127) to a substrate 120 or a lead frame after the dice have been stacked. However, the presence of the balls in the adhesive prevents the adhesive from being used to encapsulate the bonding wires, which limits the permissible size of the top die. Additionally, this approach does not work well in power chips, which frequently have bond pads located near the middle of the active surface.
FIG. 3 illustrates a stacked die approach that has been used in power die applications. In the illustrated embodiment, a power die 145 has several elongated bus bar styled bond pads 150 (e.g., 150a, 150b, 150c) and 152 (e.g., 152a, 152b, 152c) that are suitable for connection to multiple bonding wires 151 as well as some smaller bond pads 154 that are suitable for connection to a single bonding wire 159. Some of the bond pads (e.g., pad 150(b)) are located or extend into a middle region of the power die 145. A second die 156 is then adhered directly to the top surface of the base die 145 and electrically connected to the base die by bonding wires 157. This stacked die approach works allows the top die to be electrically connected to both the underlying base die 145 and to a substrate or lead frame. However, the placement of the stacked die 156 directly on the base die 145 prevents the placement of bond pads on a significant amount of the active surface of the base die which may force the use of larger base dies than may otherwise be necessary for a particular application.
Although the described techniques work well in many applications, in the semiconductor industry, there are continuing efforts to provide more efficient approaches stacking integrated circuits. The described packaging arrangements are particularly useful in stacking devices (such as power devices) that require die-to-die electrical connections.
USPTO Backgrounds
USPTO Backgrounds