A conventional dynamic random access memory (DRAM) cell uses a stack capacitor or a deep-trench capacitor for storage, which is leading to prohibitive processing complexity as the memory technology is scaled [1]. Accordingly, study and development of “capacitorless” one-transistor (1T) DRAM cells that utilize the floating body of a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) as the storage element have intensified [2]-[9], mainly for complementary metal oxide semiconductor (CMOS) embedded-memory applications [10]. In such 1T floating-body cells (FBCs), charging and discharging the MOSFET body define the memory states, and the stored data are sensed via a difference, or signal margin, in the channel current (ΔIDS) corresponding to the threshold-voltage variation (ΔVt) that results from the body charging/discharging, i.e., from the varying body-source junction voltage (VBS) [11]. The widespread FBC studies, which began with partially depleted (PD) SOI MOSFETs [2], have recently focused on fully depleted (FD) devices, including planar FD/SOI MOSFETs [3], [8], [9] and FD double-gate (DG) FinFETs [4], [5], [7], to avoid body-doping issues [4] and to render the FBC more scalable with the CMOS. The FD devices require a substrate, or back-gate bias to create an accumulation layer that emulates the PD body, and enables effective charge storage and data sensing [11].
While FinFET CMOS technology could enable scaling of the 1T FBC to gate lengths (Lg) less than 10 nm [12], there are other issues that tend to inhibit mainstream adaptation of the 1T FBC utilizing FinFET technology. In particular, the 1T FBC utilizing FinFET technology relies on current sensing of the stored data, which can be less desirable than conventional voltage sensing because of more sophisticated sense amplifiers and added power consumption. The 1T FBC utilizing FinFET technology requires the noted bias-induced accumulation, which can complicate the cell/chip design, undermine reliability, and sacrifice layout area. In addition, because the attainable ΔVt is fundamentally limited, several paralleled fins are needed to increase the device effective width and current to get acceptable ΔIDS, thus severely under mining the memory density actually achievable. For example, in the paper “Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on FinFET and tri-gate devices,” by Nagoda et al., with the SOI substrate biased at −30 V to get the needed accumulation, 10 fins yielded a current margin of less that 10 μA from an Lg=100 nm composite n-channel double gate (DG) FinFET.
Thus, there exists a need in the art for a scalable memory.
USPTO Backgrounds
USPTO Backgrounds