As semiconductor devices become denser and circuit features smaller, prior fabrication processes often become less effective. For example, certain materials (dopants, ions, etc.) are implanted and/or diffused in particular patterns into semiconductor substrates. Increased miniaturization of semiconductor devices means that these implantation patterns have become more vulnerable to subsequent heat treatments in the manufacturing process. Such heat treatments, which often follow those implantations, may cause excessive further diffusion of the implantation materials. This will unfavorably affect their distribution, harming desired physical features such as retrograde wells or very sharp channel implantation profiles. This can lead to various problems such as fluctuations in threshold voltage, increases in junction capacitance, deterioration of carrier mobility on the surface of a substrate, and so forth, causing degraded operational performance.
Various technologies are known for controlling implantations and subsequent heat diffusions, but they typically involve multiple mask, implantation, and heat steps. These must be coordinated so that subsequent heat steps do not harm earlier implantation profiles by causing undue additional movement of prior implantation materials. For example, when such a subsequent heat treatment is conducted rapidly (e.g., on the order of minutes), the portions of the semiconductor wafer nearer the top and bottom surfaces are heated more than those in between, making it difficult to maintain implantation profiles that were created earlier. Such problems are increasingly difficult to manage as circuit features on the semiconductor become increasingly smaller.
For example, product development efforts in electrically erasable programmable read only memory (“EEPROM”) device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, and reducing cell dimensions. In this regard, one important dielectric material for the fabrication of the EEPROM devices is the so-called “ONO” structure. That is, the production of nonvolatile memory (“NVM”) devices typically involves formation of an oxide-nitride-oxide (“ONO”) layer on the silicon substrate. Such an ONO layer structure is three dielectric materials layered on one another, usually silicon oxide (“SiO2”), silicon nitride (“SiN”), and SiO2, respectively. During programming, electrical charge is transferred to the SiN layer in the ONO structure, where it is retained even after the device has been turned off. A flash memory cell that utilizes the ONO structure is often referred to as a Silicon-Oxide-Nitride-Oxide-Silicon (“SONOS”) type cell.
An advantage of SONOS flash memory transistors is that they may have a lower programming voltage than some other nonvolatile memory devices. As an example, a SONOS transistor may be programmed and/or erased with a voltage of about half the voltage of other nonvolatile memory technology. Such a lower programming voltage can result in a nonvolatile storage circuit that may be more easily utilized with existing manufacturing processes and circuit technologies.
Although there are many advantages with SONOS type memory devices, there are disadvantages as well. In some instances, it is difficult to form the charge trapping layer over a silicon substrate or gate oxide layer with precision, uniformity, high quality (no defects), and without contamination. Another disadvantage is the high-temperature process that is needed to make the ONO structures. This high heat can cause undesirable distortion of prior structures already formed on the semiconductor substrate die, such as channel and well implantation profiles. In this regard, it should be noted that channel and well implantations into the underlying substrate are ordinarily done before formation of other layers on top of the substrate, such as the ONO layer. However, as indicated, the ONO formation is a high-temperature process that unfortunately can considerably change the profiles of such prior channel and well implantations.
Such well implantation profiles provide important operational benefits. One example relates to exposure to radiation, which can cause a memory cell to lose its data. For example, in a memory-type integrated circuit, a so-called “soft error” may arise in which information that is stored in the integrated circuit is accidentally lost. A typical cause of such a soft error is radiation (e.g., cosmic rays; x-rays; alpha, beta, and/or gamma radiation) passing through the circuit. One means for solving this problem is to use an implantation profile such as a retrograde well. A retrograde well consists of a doped region with a dopant concentration that varies with depth (i.e., a concentration level that is “vertically graded”). Preferably, the implanted dopant concentration is lowest at or near the substrate upper surface and highest at the bottom of the well into which it is implanted. This increase in the dopant or impurity concentration at the bottom of a well is usually achieved by implanting the impurity in the semiconductor substrate by means of high-energy ion implantation. Almost all retrograde well structures are formed by this means.
Whether the implantation is conducted to form a retrograde well or to form a conventional well, it is important that the shape or profile of the implanted well be preserved during subsequent manufacturing operations as the integrated circuit is being completed. Conventional wells are formed by implanting dopants at the well locations and then diffusing them (usually through a high temperature diffusion process) to the desired depth. For this reason, such wells are also referred to as diffusion wells. One drawback associated with diffusion wells is that the diffusion occurs laterally as well as vertically, e.g. the diffusion well gets wider as it gets deeper. A second drawback associated with diffusion wells is that relatively large spaces between the edges of the wells and the device active areas are required.
A retrograde well profile attempts to overcome the lateral spreading problem by implanting high-energy dopants to the desired depth so that high temperature diffusion is not necessary. Retrograde wells require less space between the edges of the well and device active areas than the space required by diffusion wells. Retrograde wells are therefore desirable for high-density applications.
In certain applications, it makes sense to use both well types (conventional and retrograde) on a single integrated circuit. For example, in flash memory applications, which contain a low voltage peripheral circuit portion and a high voltage circuit portion, it is desirable to have the low voltage peripheral circuit portion formed in retrograde wells and the high voltage circuit portion formed in conventional diffusion wells.
In all such cases, unfortunately, subsequent high-temperature operations (such as ONO formation) can lead to distortion of these well configurations and profiles. This is especially true when high-temperature treatments are conducted, since this can cause further diffusion (spreading) of the dopants beyond the boundaries where they are supposed to remain.
Thus, a need remains for semiconductor fabrication methods that will preserve implantation profiles and protect them from thermal degradation during ONO layer formation. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
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