Testing of data processing systems is important to ensure proper operation. Testing may be performed in a factory following manufacture and prior to using the data processing system in a user application. The factory testing ensures an end user receives a properly functioning product. However, during operation of the data processing system by an end user, it may also be desirable to test the data processing system so that any failures which occur during normal operation of the product can be detected.
Currently, to provide a low cost method of real-time testing of the integrity of a data processor, while maintaining reasonable interrupt latency, on-line testing is performed by sampling a collected set of test points within a data processor and accumulating the sampled signals into one or more compressed results via accumulating the sample signals into one or more compressed results via MISRs. A well known technique to permit integrated circuits to be tested during operation is the use of logic testing registers, called Multiple Input Shift Registers (MISRs). Multiple input shift registers implement any of a variety of polynomials by receiving data from various internal nodes of the integrated circuit and performing signature compression and accumulation. The signature compression and accumulation is a series of logic operations which result in a single output value known as a signature value. The signature value is compared with a desired value to determine whether the integrated circuit being tested is functioning correctly. In order to reduce interrupt latency, processors may be designed such that interrupts may be injected into the pipeline, causing the results of uncompleted instructions to be discarded without compression and accumulation. The results are discarded because if the discarded results were  otherwise accumulated into a compressed signature, a faulty signature value would result.
Since the testing of the integrated circuit is performed on-line or while the integrated circuit is functioning in a real-world application, it is highly desirable to have minimal impact or intrusiveness on system characteristics. A critical component of real-time systems is the interrupt latency or the amount of time required to respond to an interrupt request. Since on-line testing must not adversely affect the responsiveness of a data processing system, known systems typically completely disable the interrupt exception handling of a data processor when testing with a MISR is performed. As a result, known data processing systems also typically strictly limit the length of MISR test sequences.
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USPTO Backgrounds
USPTO Backgrounds