a) Technical Field of the Invention
The present invention relates to a fabrication method of thin film integrated passive component with ceramic or glass materials as substrate, and to a method of thick film packaging technique of the fabricated components.
b) Description of the Prior Art
In recent years, with the widespread application of SMT technology, passive components are made into chips. Currently, thin film method and thick film method are used to form chipped integrated passive components.
U.S. Pat. No. 5,495,387 issued to Mandai et al. discloses a RC array fabricated by thick film method. As shown in FIG. 1 of the US patent, the RC array comprises a thin laminated block 11. Two capacitor electrodes opposite to each other are formed in the interior of this block.
The block 11 is fired at a temperature of 1,200.degree. C. to 1,300.degree. C. to provide a sintered body in order to form the ceramic block 11. On the ceramic surface 12 of the ceramic block 11, a first terminal electrode 15, a second terminal electrode 16, a ground terminal electrode 17 and a plurality of resistors 18 are formed, and the first terminal electrode 15 is connected to a terminal electrode of each capacitor, and one terminal of the individual resistor 18 is connected to the first terminal electrode 15, and the other terminal of the resistor 18 is connected to the second terminal electrode 16. The other electrodes of the individual capacitor are co-connected to the ground terminal electrode 17. The RC array is formed from the above mentioned capacitors, the plurality of resistors 18, the first terminal electrode 15, the second terminal electrode 16 and the ground electrode 17. Finally, the RC array is packaged by means of thick film packaging technology to complete the fabrication of a thick film RC integrated component
The advantage of the above RC array is that the cost of production is low. The drawbacks of the fabrication method are (i) the obtained products are not stable for the reason that the process requires high sintering temperature of above 1,000.degree. C.; (ii) other problems exist in combination of various materials, and (iii) the size of the elements is not easy to miniaturize.
U.S. Pat. No. 5,355,014, issued to Rao, et al. discloses a method of fabricating RC integrated component by employing thin film fabricating technique, wherein conventional semiconductor fabrication technology is used to form a RC network having Schottky Diode on a silicon substrate, and then the product is packaged by IC packaging technique. Normally, this conventional technique comprises the steps of wafer polishing, wafer-chip cutting, chips mounting, wire bonding, sealing, marking, lead finish, trim/form, and packaging.
The advantages of this conventional fabricating method are (i) the RC integrated component is smaller in size, and (ii) the yield is high. However, the disadvantage is that the cost of this type of product is much higher than the similar thick film integrated passive component.
This is due to the complicated process of thin film packaging. Thus, the cost of this type of component is high.
USPTO Backgrounds
USPTO Backgrounds