The present invention relates to technology for checking the performance characteristics of an integrated circuit device (for example, an integrated circuit device having a memory circuit section), and more particularly to technology for testing the memory circuit section of an integrated circuit device which includes not only the memory circuit section but also a logic circuit section arranged around the memory circuit section, without being adversely affected by the time delay shift of the input and output of the memory circuit section due to the pipeline control in the logic circuit section (that is, the clock-control in the logic circuit section). It is a matter of course that the present invention is not limited to such an integrated circuit device.
In an integrated circuit device (hereinafter referred to as an "IC device") which is formed on a single chip and includes a memory circuit section, the performance characteristics of the memory circuit section is checked by an IC tester (namely, integrated circuit tester) in the following manner. That is, an address signal and an enable signal are sent from the IC tester to the IC device which is to be measured, and an output signal from the to-be-measured IC device responsive to the address and enable signals is compared with an expected signal generated by the IC tester, to check the performance characteristics of the memory circuit section.
The integration density in IC devices has been greatly increased in recent years. Accordingly, a large number of IC devices have been produced which have the following structure. That is, a memory circuit section and a multi-stage logic circuit section including a plurality of series-connected logic circuits cooperative with the memory circuit section are provided on a single chip to form an IC device. For example, an IC device includes a memory circuit section and such a multi-stage logic circuit section formed around the memory circuit section.
In such an IC device, plural logic stages in the multi-stage logic circuit section successively transmit a signal under control of a clock signal, and thus a time delay shift of the signal associated with the period of the clock signal is generated. Hence, the delay time of the output data signal from the to-be-measured IC device is different from the delay time of the expected signal from the IC tester, and moreover the difference in delay time between the output data signal and the expected signal varies. Thus, it is difficult to check the performance characteristics of the memory circuit section accurately.
In order to solve the above problem which arises in testing the memory circuit section of an IC device having a logic circuit section in addition to the memory circuit section, the following methods have hitherto been known.
For example, according to Japanese patent application JP-A-No. 59-119,595 (laid open on July 10, 1984), a circuit part operable in accordance with a predetermined clock signal in a test mode is formed in the IC device, to synchronize the output data signal from the IC device with the expected signal, thereby eliminating the differences in delay time between the output data signal and the expected signal. According to this method, the IC tester and the to-be-tested IC device are operated in synchronism with each other, and thus it can be prevented that the signal delay in the IC device is different from that in the IC tester. In this method, however, it is required to add a logic circuit section used only for testing the memory circuit section, to the IC device, and thus the whole of the IC device becomes large in scale and complicated in structure.
According to another method, a circuit for putting a latch circuit, which is included in the logic circuit section of a to-be-measured IC device to transfer an input signal under control of a clock signal, in a "through" state (that is, the state of the latch circuit capable of transferring the input signal thereto to the next stage without producing any delay time) is additionally provided, to prevent the signal delay in the IC device from being different from that in the IC tester. This method will be explained below in more detail, with reference to FIG. 1.
FIG. 1 is a block diagram showing a state that an IC tester is connected to an IC device which includes a memory circuit section and a logic circuit section, to test the memory circuit section.
Referring to FIG. 1, a logic circuit section L' is arranged around a memory circuit section M' of a to-be-measured IC device 1, and the memory circuit section M' is applied with an address signal through a series combination of latch circuits 10 and 11 and applied with an enable signal through a latch circuit 12. Further, a data signal from the memory circuit section M' is sent out to the outside through a latch circuit 13. Meanwhile, an IC tester 2 includes therein an algorithmic pattern generator (hereinafter referred to as "ALPG"), and the address and enable signals are sent from the ALPG to the memory circuit section M' through the logic circuit section L'. Further, an expected signal is sent from the ALPG to a comparator circuit C which is provided in the IC tester 2.
In the circuit configuration of FIG. 1, in order that the address and enable signals generated by the ALPG may reach the comparator circuit C in the IC tester 2 through the to-be-measured IC device 1 in the form of an output data signal, it is required that the latch circuits 10, 11 and 12 applied with the address or enable signal and the latch circuit 13 for sending out the output data signal are all put in a "through" state. Accordingly, the IC tester 2 includes means for applying a test clock signal having a logical value "1" to respective clock input terminals of the latch circuits 10 to 13, and each latch circuit is put in the through state by the test clock signal. Thus, the address, enable and output data signals can pass through the logic circuit section, and the output data signal reaches the comparator circuit C in the IC tester 2, to be compared with the expected signal.
This method, however, is not satisfactory as described below. In a case where a large number of latch circuits are connected in cascade to form a multi-stage circuit, it is difficult to provide input pins applied with the test clock signal, in the to-be-measured IC device 1. Further, this method is not applicable to a flip-flop circuit which does not have the through state but is triggered by a pulse edge. Accordingly, it is impossible to measure the switching time and other characteristics of a high-speed IC device which includes flip-flop circuits in place of latch circuits.
USPTO Backgrounds
USPTO Backgrounds