For its high-speed and short cycle time, the SRAM (Static Random Access Memory) is utilized extensively as a cache memory in computer systems. Furthermore, the SRAM is simple to use with no refresh cycle, while DRAM (Dynamic Random Access Memory) requires refresh cycle. As such, the SRAM constitutes a key component that holds sway on the speed and performance of the computer system. Efforts of research and development have been under way primarily to boost the operating speed of the memory.
FIG. 1 illustrates a circuit diagram of a conventional SRAM including memory cell array, a write circuit and a sense amplifier, as published, U.S. Pat. No. 7,158,428, No. 6,075,729 and No. 4,712,194. The memory block 100 includes memory cells 110, 111, 112 and 113 having six transistors. The memory cells are connected to local bit lines 121, 122, 123 and 124, which bit lines are pre-charged by pre-charge circuits 125 and 126, respectively. During standby, the pre-charge circuits 125 and 126 preset the bit lines to high. After then, the bit lines are released from the pre-charge state when read and write. Thus the stored voltage of the memory is transferred to the sense amp 160 through the transfer gate. When the memory cell 110 is selected, the transfer gates 141 and 142 are turned on, while the other transfer gates 143 and 144 keep turn-off state. In doing so, the memory cell data is read by the sense amp 160 through the common bit lines 151 and 152. The read output of the sense amp 160 is transferred to output node 190 through a transfer gate 161, while unselected memory block 170 and unselected sense amp 180 are in pre-charge state and transfer gate 181 keeps turn-off state. When write, write buffers 131 and 132 transfer input data to tri-state buffers 133 and 134, respectively, so that the input data is transferred to the bit lines and the bit line voltages are transferred to the memory cell nodes when word lines of the memory cell are asserted to high.
In the conventional SRAM, six-transistor memory cell 110 is used to store data, such that a latch including two cross coupled inverters stores voltage data. In order to achieve fast access, the inverters should be strong enough to drive heavily loaded bit line, but the inverters should be weak enough to be flipped by the write buffers 133 and 134 through the transfer gates 141 and 142. Furthermore, floating bit lines may flip the unselected memory cells during write operation. For example, the unselected memory cell 112 receives same word line voltage in the selected memory cell 110, so that the memory cell 112 will lose its data when the latch is too weak and the bit line loading is too heavy because both bit lines 123 and 124 are pre-charged to high voltage, while the selected bit line 121 and 122 receive input data from write drivers 133 and 134. And the transfer transistor of the memory cell should be strong enough to transfer the stored data to bit lines and receive the input data. As a result, the transistors in the memory cell are bigger than minimum feature size within the fabrication process limit typically, which increases the chip area. And access time is also slow because the whole chip area is big, which increases propagation delay with heavy loaded routing line.
There are many efforts to improve the conventional SRAM, with new circuit concepts, such that memory array is multi-divided in order to reduce parasitic loading of local bit line by introducing hierarchical bit line architecture, as published U.S. Pat. No. 7,158,428. However, each memory segment including the local bit line comprises more circuits such as a cross-coupled keeper transistor circuit, a local read amplifier circuit, pre-charge transistors, and transfer transistors, which increases chip area. And another prior art is shown, “A low power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers”, Yang et al, IEEE Journal of Solis-State Circuits, Vol. 40, No. 6, June 2005, such that the local sense amplifier improves write operation, but is can not improve read operation because the local sense amplifier is not activated for read cycle, in order to avoid wrong flip with the charges from heavily loaded global bit line. As a result, the access time is still slow and area is increased more.
In this respect, there is still a need for improving the static random access memory, in order to achieve fast access and reduce cell area. Furthermore, there is one more need for preventing flip of unselected cell by heavily loaded bit line during write operation. In the present invention, multi-divided bit line architecture is introduced to reduce the parasitic capacitance of the bit line, so that a segment read circuit is added for reading the local bit line more effectively, which realizes fast reading. The lightly loaded bit line does not disturb the unselected cells in the same row during write operation. Alternatively, a time-domain sensing scheme is introduced in order to differentiate low voltage data and high voltage data in the time-domain, which does not require the conventional sense amp and achieves fast access. More detailed explanation will be followed as below.
USPTO Backgrounds
USPTO Backgrounds