The invention relates in general to digital logic circuits fabricated as integrated circuits, and more particularly to a nano-electron fluidic logic (NFL) device that operates by steering the propagation direction of a surface plasma wave (SPW) set up in an electron fluid (EF), with device speed as a function of SPW propagation velocity.
Advanced digital circuits for logic and digital applications fabricated with CMOS integrated technology become a dominant technology in semiconductor industry. The continuous improvement in the basic CMOS integrated devices is attributed to scaling of the device's dimensions for enhancing speed. Without a commensurate increase in operating speed, the point of diminishing returns for CMOS scaling is imminent. Accordingly, new device concepts and technologies that may shift CMOS scaling necessitates another paradigm effectively utilizing manipulation of plasmons in a channel cavity.
Surface plasmons may exist on a boundary between two materials when the real parts of dielectric constants have different signs, for example, between a metal and a dielectric. The material or structure forming the boundary with the material may be air, vacuum, or its equivalent, a substantially homogeneous dielectric material, or a different material or structure. The boundary, although being substantially continuous and planar, may have different shapes. The plasmon, although including substantially exponential functions with a field maximum at the boundary, may include only approximately exponential functions, may be described by a different function, and/or may have a field maximum some place other than the boundary.
Several optical waveguiding structures with the utilization of plasmon propagation have been developed in the art. For example, U.S. Pat. No. 6,977,767 issued to Sarychev discloses a method for controlling, guiding, manipulating, and circuiting light, and performing surface-enhanced spectroscopy in medium comprising plasmonic nanomaterials via the excitation of plasmon modes in the materials. The plasmonic nanomaterials are based on metal films with or without arrays of nanoholes and/or on metal nanowires and/or spheroids. There are also devices and methods employing such plasmonic nanomaterials. A device operating according to the method may comprise integrated optical elements to control light at telecommunications wavelengths between approximately 1.3 microns to 1.6 microns. A device operating according to the method may comprise one or more photonic chips comprising one or more photonic circuits.
U.S. Pat. No. 7,447,392 issued to Hyde discloses a plasmon gate and a method of controlling energy propagation comprising guiding energy at a first plasmon frequency along a first path, blocking the guided energy at the first plasmon frequency from propagating along the first path responsive to a first signal at a first time, blocking the guided energy at the first plasmon frequency from propagating along the first path responsive to a second signal, different from the first signal, at a second time, and receiving an output that is a function of the first signal and the second signal.
There are many advanced digital circuits fabricated in CMOS technology which uses FET transistors for yielding high speed and low power consumption. For example, U.S. Pat. No. 5,001,367 issued to Vinal explains a CMOS logic circuit that includes a driving stage having a plurality of parallel FETs of a first conductivity type for receiving logic input signals and a load FET of second conductivity type connected to a common output of the driving stage. A complementary FET inverter including serially connected FETs of the first and second conductivity type is connected to the common output and the load FET. According to the invention, the voltage transfer function of the complementary inverter is skewed so that the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the first conductivity type is made substantially greater than the product of the carrier mobility and the ratio of channel width to the length of the inverter FET of the second conductivity type. By skewing the voltage transfer function of the complementary inverter the voltage lift-off interval is dramatically decreased, thereby improving the speed. A multigate serial load transistor further reduces power consumption.
Hence it can be seen that the conventional MOS structures are limited in various ways like increase in power consumption due to increased leakage currents, short channel effects, source-drain tunneling, pn junction tunneling, decrease in channel mobility, increase in the interconnection resistance concomitant with the smaller process geometries, and the like. Advancements in submicron CMOS processing greatly benefit digital logic and memory, but result in poor analog and RF performance and a high level of complexity in both lithography and design resulting in high manufacturing cost.
Although the above inventions serve a similar purpose, the object of the present invention is to provide a NFL device that operates by steering the propagation direction of a SPW set up in an electron fluid. A further object of the present invention is to provide a NFL device with device speed as a function of SPW propagation velocity. Other objects of the present invention will become better understood with reference to the appended Summary, Description, and Claims.
USPTO Backgrounds
USPTO Backgrounds