Solar cells typically utilize a p-n junction to separate electron-hole pairs that are created by photons penetrating the substrate. This may be achieved by disposing a p-type region adjacent to an n-type region. Traditionally, one of these regions, such as the n-type region, may be provided through the use of a previously doped bulk material. For example, the bulk silicon used to create a solar cell may be n-type silicon. Methods of creating bulk silicon with n-type or p-type dopants incorporated therein are well known in the art. One surface of this bulk n-type silicon is then doped with p-type ions to create a p-type region, adjacent to the remainder of the n-type bulk silicon.
Variations in the resistivity of the bulk silicon may have an adverse impact on the efficiency of the solar cell. For example, high resistivity of the bulk silicon may decrease lateral carrier mobility, which negatively impacts series resistance and therefore fill factor. While the resistivity of the bulk material may impact solar cell performance, few techniques are currently employed to determine and counteract the affect of high resistivity of the bulk material.
Therefore, an improved method of processing a substrate, using information related to the bulk material's resistivity, is needed.
USPTO Backgrounds
USPTO Backgrounds