1. Field of the Invention
The invention relates generally to nonvolatile computer memory devices and more specifically to very high density devices made possible by using one, as opposed to two, transistors per memory cell.
2. Description of the Prior Art
Electrically programmable read only memory (EPROM) cells are among the smallest memory cells in the prior art. Electrically erasable EPROMs (called E.sup.2 PROMs) traditionally have had larger cell sizes because two transistors were necessary for each memory cell. Some so called "flash" EPROMs also have cells as small as EPROMs. Flash memories sort themselves into two basic approaches, distinguished by whether they require one or two voltage supplies. (See, Samuel Weber, "Look Out, Here Comes Flash," Electronics, November 1990, pp. 44-50.) These designs also differ in their cell structure--whether they require one or several transistors per cell. Intel Corporation (Santa Clara, Calif.) has a one-transistor self-aligned stacked-gate cell, based on its proprietary ETOX (EPROM tunnel-oxide) technology. Intel recently announced a very high density flash device, the 28F020, that stores two megabits. Catalyst, Excel, Hitachi, Mitsubishi, and Toshiba all offer competing devices. A problem with the the single-transistor cell is the possibility of over-erasure and consequent current leakage. This can result in false data readings when a cell in the zero state receives an erase pulse that drives it into the depletion mode. The column-sense amplifier will read this incorrectly as an erased cell. Intel, and others, have overcome this with a programming algorithm that first programs up all the cells on a chip to a "one" before erasing. Seeq Technology (San Jose, Calif.) solves the problem by using a different cell structure. A split-gate cell amounts to a two-transistor architecture, but takes only a little more chip area than a single transistor cell. (According to Weber, supra.) Through a diffusion process, the split-gate creates a phantom transistor that looks like a series transistor. This allows the cell to be isolated from others in a column. The Seeq devices (e.g., 48F512 and 48F010) have the ability to do sector-erase of any of 128 columns.
FIG. 1 illustrates a typical EEPROM memory cell 10 of the prior art comprising a bit line 12, a select transistor 14, a floating gate transistor 16 having a floating gate 18 and a control gate 20, a select gate 22 connected to a word line 24, and an array source 26. Transistor 16 is a floating-gate avalanche-injection metal oxide semiconductor (FAMOS) and is well known in the prior art. (For a background of these devices see, U.S. Pat. No. 4,884,239, issued Nov. 28, 1989, to Ono, et al.) To erase cell 10, a high voltage (about 20 V) is placed on gates 20 and 22, while array source 26 and bit line 12 are at ground. The high voltage on gate 20 is coupled to floating gate 18 by virtue of capacitive coupling. The voltage on gate 18 is a function of the coupling ratio gamma. (Depending on the technology used, the coupling ratio will vary, and so will the voltages used.) Therefore V.sub.18 =gamma * V.sub.20. Once V.sub.18 reaches a critical level (typically.about.11 V) the field across the tunnel oxide area of transistor 16 is enough to start electron tunneling from the drain of transistor 16 to gate 18 through the thin (.about.100 .ANG.) tunnel oxide. This results in a relatively high threshold voltage (V.sub.th) for transistor 16. To program cell 10, control gate 20 is grounded, high voltages (.about.20 V) are placed on bit line 12 and select gate 22, while array source 26 is left to float. The high voltage on bit line 12 transfers through transistor 14 to the drain of transistor 16. An electric field is produced across the tunnel oxide area of transistor 16 to start tunneling of electrons in the direction opposite to the above. This results in transistor 16 having a low threshold voltage (V.sub.th, which can be -2 V to -3 V). This threshold voltage is the reason that transistor 14 is needed in read mode because transistor 16 cannot be reliably controlled for reading by gate 20. Since a high voltage on only one terminal, control gate 20 or the drain of transistor 16, is needed to program and erase, the select gate 22 is needed for these modes.
FIG. 2 illustrates a prior art single-transistor flash EPROM memory cell 30 comprising a bit line 32 and a memory transistor 34 having a floating gate 36, a control gate 38 connected to a word line, a drain 40, and an array ground 42. To erase cell 30, control gate 38 and bit line 32 have a high voltage (.about.12 V to 15 V) applied. This puts transistor 34 in a high current mode drawing about one milliamp from bit line 32 to array ground 42. Hot electrons are generated and get trapped in floating gate 36. (This is the standard EPROM programming mode.) To program cell 30, control gate 38 is grounded and array ground 42 is at high voltage. Bit line 32 is floating and electrons tunnel through the thin gate oxide of transistor 34 to array ground 42. This results in a low V.sub.th state for transistor 34.
A pass transistor can prevent memory cells from drawing current when the floating gate structure is erased into depletion. (See, Gill, et al., "A 5-Volt Contactless Array 256KBIT Flash EEPROM Technology," IEDM 88, IEEE, pp. 428-431.) Such pass, or read select, transistors are routinely used in the prior art. A contactless cell array technology is described by Gill, et al. (supra), for a single power supply 5 V-only flash EEPROM. The contactless flash EEPROM cell is a one-transistor floating gate structure (defined by double poly stack process) merged with a series enhancement pass gate. The cell erase is accomplished by Fowler-Nordheim tunneling from floating gate to source junction by applying a negative voltage on the word line and Vcc=5 V on the source line (Id., FIG. 4). There is no significant change in the erased state threshold voltage because of the merged pass gate. Since the floating gate structure can be over-erased into depletion, the cell V.sub.th is dominated by the pass gate characteristics.
The prior art has developed a method of combining eight memory transistors in a bank having only two select transistors. These structures save as many as six transistors in an eight-bit memory bank, and are known as NAND structure cells. (See, Momodomi, et al., "New Device Technologies for 5 V-Only 4 Mb EEPROM With NAND Structure Cell," IEDM 88, 1988, pp. 412-415 [ULSI Research Center, Toshiba Corp., Japan].) NAND structure cells have been nominated as the most promising ultra high density EEPROM that is capable of replacing magnetic memories, such as floppy disk. By using one micron design rules, cell units as small as 12.9 square microns per bit are possible, which is good enough to fabricate a 4 Mb EEPROM. A Toshiba paper presented to the 1990 IEDM conference, revealed an experimental 16 Mb NAND EEPROM having a bit cell area that has been squeezed down to 2.3 square microns. (Bursky, et al., "IEDM Unveils the Latest Semiconductor Advances," Electronic Design, Vol. 38, No. 22, Nov. 22, 1990, pp. 39-51.) The new, smaller cell is reported to have used a new self-aligned stacked-gate pattern, a new high-voltage field isolation technology, and a larger NAND string of sixteen memory bits. The main features of the NAND structure cell are that they have a wide threshold voltage window achieved by a new programming operation, and tolerate successive program/erase operations by using high voltage CMOS processes.
FIG. 3(a) shows a NAND structure of eight memory transistors MT1-MT8, having respective control gates CG1-CG8, connect their drains and sources in series with one another and two select transistors ST1-ST2 having select gates SG1-SG2. FIG. 3(b) is a layout of the NAND structure of FIG. 3(a) and FIG. 3(c) is a cross-sectional view of the layout. The process and device parameters are given in Table I.
TABLE I ______________________________________ Technology N-Well CMOS Triple Level Poly-Si Single Aluminum Layer Gate Length Memory Cell 1.0 micron Select Gate 1.5 micron NMOS 2.0 micron PMOS 2.5 micron Oxide Thickness Transistor 400 .ANG. Memory Cell 100 .ANG. ______________________________________
Select transistor SG1 ensures the selectivity, and SG2 prevents current from passing during programming operation. (Momodomi, et al., supra.) Each memory cell has therefore only one memory transistor, a quarter of a select transistor, and a sixteenth of a contact hole area per bit. The NAND structure can be fabricated by conventional self-aligned double poly silicon gate technology. A typical 4 Mb EEPROM is composed of 256.times.2048 NAND structure cell arrays.
In the NAND structure described by Momodomi, et al., (supra) the cell is programmed and erased by Fowler-Nordheim tunneling. The current dissipation during these operations is therefore very small. To erase, 17 V is applied to the control gates while the bit lines are grounded. All cells in a block are erased simultaneously. The threshold voltage (V.sub.th) of erased cells becomes an enhanced mode at approximately 2 V after one millisecond erasing time. To program, 22 V is applied to the nonselected control gates and the selected bit lines, while the selected control gate is grounded. Half of the programming voltage (11 V) is applied to the nonselected bit lines in order to keep the V.sub.th of the nonselected cells.
U.S. Pat. No. 4,959,812, issued Sep. 25, 1990, to Momodomi, et al., describes an erasable programmable read-only memory with NAND cell structure which has memory cells provided on an n-type substrate. The memory cells are divided into NAND cell blocks each having a series array of memory transistors. Each of the transistors has a floating gate, a control gate connected to a word line and n-type diffusion for the source and drain. These diffusions are formed in a p-type well in the surface of the substrate. The well serves as a surface breakdown prevention layer. During a data erase, data stored in all of the memory cells is erased simultaneously. During data write, which is subsequent to erase, a certain NAND cell is selected and memory transistors within the NAND cell block are written in a hierarchical sequence. (Unprogrammed cells nearer the selection transistor interfere with the writing operation.) When data is written, the respective control gate is supplied with a voltage high enough to form an electric field that will promote tunneling of electrons between the floating gate of the memory transistor and the well layer. Consequently, only the selected cell is written into.
An "EEPROM Device with Plurality of Memory Strings Made of Floating Gate Transistors Connected in Series" is the subject of U.S. Pat. No. 4,962,481, issued Oct. 9, 1990, to Jung-Hyuk Choi, et al. This device has a plurality of memory strings arranged in a single column respectively disposed at both sides of each column line and an upper and lower row between reference lines. A single select transistor is used in each string.
The disadvantages of the prior art for EEPROM are that select transistors are needed, making high density difficult, and bit lines have high voltages on them causing spacing concerns between adjacent lines. In flash EPROMs the problems are again high voltages being placed on bit lines, high currents needed to program memory cells, and a loss of the page mode of operation because too much current is needed. Often, the write operation can produce negative thresholds and complicated algorithms are necessary to work around the problem.
USPTO Backgrounds
USPTO Backgrounds