A Dual damascene process is a technology widely applied in a semiconductor process. To reduce the RC delay caused by a parasitic capacitance, the current dual damascene process adopts an ultra low-k (ULK) material as a dielectric layer. Further, with the minimization of the device, a titanium nitride (TiN) hard mask layer is formed on the dielectric layer, and then the required patterns are precisely transferred to the dielectric layer by utilizing different etching selectivities of the TiN hard mask layer and the dielectric layer.
The pattern transfer is usually achieved by a dry etching process. However, during the etching process, the reactive gases passing into a reaction chamber may also undergo a polymerization reaction. Therefore, the organic polymer formed from the polymerization reaction is deposited on the surface of the device. Moreover, the reactive gases used for etching the dielectric layer are mostly fluorine-containing gases. These fluorine-containing gases may react with the TiN hard mask layer to produce titanium fluoride (TiFx) on the surface of the device, and thus, a profile change of the device, abnormal conduction, leakage or short circuiting between film layers is caused, and the reliability of the device is accordingly reduced.
The effect produced by the polymer and titanium fluoride residues is particularly significant in the deep sub-micro fabrication process. Further, upon the study, the post-etch cleaning process may effect the conduction ability of the device by etching the exposed metal lines below the dual damascene opening, cause a profile change by swelling the dielectric layer with the cleaning solution, or lead to an increase in the dielectric constant. Therefore, the post-etch cleaning process has become a very important step in the duel damascene process.
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USPTO Backgrounds