Floating point units perform various arithmetic operations such as addition, subtraction, multiplication, division, square root on numerical operands represented in floating point notation. Floating point notation utilizes the format of a sign, a mantissa, and an exponent to represent a number. Floating point units recognize floating point numbers because floating point numbers include a predetermined binary bit field with the sign, mantissa, and exponent each occupying the same bit positions regardless of the sign and magnitude of the actual number. Thus, a floating point unit ascertains the sign, mantissa, and exponent for any input floating point number by decoding bit positions and then determining the sign, the numeric value of the mantissa, and the magnitude of the exponent from the decoded binary bits representing the floating point number.
The IEEE promulgates standards (specifically the ANSI/IEEE 754-1985) that govern the representation of numbers in floating point notation to ensure uniformity among floating point notation users. The IEEE standards include extended, double word, and single word precision normalized formats. Denormalized formats are also included in the standard. Denormalized formats are particularly useful in representing very small numbers. The formats determine the quantity of significant figures or size of the bit field for any number represented in floating point notation. For example, a double precision format defines 64 bits in a double word operand with one bit representing the sign, eleven bits representing the magnitude of the exponent, and 52 bits representing the numeric value of the mantissa. Alternatively, a single precision format defines 32 bits in a single word operand with one bit representing the sign, 8 bits representing the magnitude of the exponent, and 23 bits representing the numeric value of the mantissa.
Normalization of a floating point number requires the leading one in the mantissa always be placed to the left of the decimal point with the magnitude of the exponent adjusted accordingly. Consequently, the IEEE standard places the leading one in the most significant bit of the mantissa bit field so that the leading one appears not included and is referred to as a "hidden" bit. Accordingly, in double precision format, the mantissa bit field actually constitutes 53 bits with the leading one "hidden", while in single precision format, the mantissa bit field actually constitutes 24 bits with the leading one "hidden".
Since a normalized number requires that the leading binary one bit in the mantissa be in the most significant position of the mantissa field, the exponent ends up being a smaller value than would be required if the leading one bit could be placed in a less significant position. Accordingly when a very small number is to be represented, in denormalized form, the most negative exponent is used in combination with movement of the mantissa to a less significant position thereby gaining the ability to represent numbers that are orders of magnitude smaller than in could be represented in normalized formats but at the cost of carrying fewer significant digits in the mantissa. In the IEEE standard, the exponent field is biased so that in effect, an exponent value of binary one is the most negative exponent that can be represented, and in a double precision number, an exponent of hexadecimal 3FF is an exponent value of zero. To represent a number smaller than two to the minus 1023, the number must be in denormalized format. In denormalized format, the exponent field is set to a binary zero and the mantissa is shifted in the mantissa field until the number can be represented.
Due to their adjusted mantissa, normalized floating point numbers rarely have equal exponents. Accordingly, when floating point units add or subtract a second operand represented in floating point notation with a first operand represented in floating point notation, the mantissa of the second operand typically must be shifted because an addition or subtraction cannot be performed until the exponent of the second operand equals the exponent of the first operand. The floating point units equalize the first and second exponents by shifting the mantissa of the second operand relative to the mantissa of the first operand. Shifting the second mantissa to the right increases its exponent one for each shift, while shifting the second mantissa to the left decreases its exponent one for each shift.
Some of the present processing systems detect an instruction and the type of operand(s) associated with the instruction prior to the instruction's execution. Under the IEEE 754-1985 standard, the types of operands include ZERO, INFINITY, QUIET NOT A NUMBER, SIGNALING NOT A NUMBER, DENORMALIZED, and NORMAL NUMBER. For example, if one of the operands is denormalized, the processing system must execute a special instruction that normalizes the operand before execution of the original instruction. Alternatively, if the instruction is add and one of the operands is infinity, the processing system must execute a special handling operation that replaces the result of the addition with the number that represents infinity in IEEE 754-1985 standard. After determining whether special handling is necessary, the processing system executes the original instruction.
Although some of the operand types require special handling, only the denormalized operand type requires the execution of special instructions prior to the execution of the original instruction. The remaining five types of operands either require no special instructions (e.g., a normal number operand) or require a special instruction be executed during the execution of the original instruction (e.g., an infinity operand). Consequently, the majority of instructions and operand types do not require detection prior to the execution of instruction using the instruction's associated operand(s). Accordingly, detecting the instruction and operand types prior to the execution of every instruction unnecessarily increases the number of clock cycles required to perform every floating point instruction, resulting in the decrease in operating speed of the processing system.
Accordingly, a processing system that eliminates unnecessary clock cycles in detecting the instruction and operand types will have an increased operating speed.
One present floating point processing system includes a multiple stage processing pipeline for executing instructions, and circuitry within the pipeline for detecting the validity of the instruction concurrently with the execution of the instruction by the pipeline. In this system, the circuitry detects the type of operand concurrently with the processing of the operand by the pipeline. If the operand type is denormalized, the circuitry cancels the instruction and directs the processing system to normalize the operand and re-launch the instruction and the normalized operand into the pipeline. When the operand type and instruction produce a special case, the circuitry replaces the result from the processing of the operand by the pipeline with a predicted result such as, a not a number operand, or an actual zero for two simple examples. Accordingly, every denormalized number operand now requires that the instruction be canceled and re-launched after the number has been normalized which can have a significant impact on processor performance.
USPTO Backgrounds
USPTO Backgrounds