Semiconductor integrated circuits typically include multiple levels of metallization to provide electrical connections between large numbers of active semiconductor devices. Advanced integrated circuits, particularly those for microprocessors, may include five or more metallization levels. In the past, aluminum has been the favored metallization, but copper has been developed as a metallization for advanced integrated circuits.
A typical metallization level is illustrated in the cross-sectional view of FIG. 1. A lower-level layer 110 includes a conductive feature 112. If the lower-level layer 110 is a lower-level dielectric layer, such as silica or other insulating material, the conductive feature 112 may be a lower-level copper metallization, and the vertical portion of the upper-level metallization formed in a hole is referred to as a via since it interconnects two levels of metallization. If the lower-level layer 110 is a silicon layer, the conductive feature 112 may be a doped silicon region, and the vertical portion of the upper-level metallization is referred to as a contact because it electrically contacts silicon. An upper-level dielectric layer 114 is deposited over the lower-level dielectric layer 110 and the lower-level metallization 112. There are yet other shapes for the holes including lines and trenches. Also, in dual damascene and similar interconnect structures, as described below, the holes have a complex shape. In some applications, the hole may not extend through the dielectric layer. The following discussion will refer only to via holes, but in most circumstances the discussion applies equally well to other types of holes with only a few modifications well known in the art.
Conventionally, the dielectric layer is silicon oxide formed by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS) as the precursor. However, low-k materials of other compositions and deposition techniques are being considered. Some of the low-k dielectrics being developed can be characterized as silicates, such as fluorinated silicate glasses. Hereafter, only silicate (oxide) dielectrics will be directly described, but it is contemplated that other dielectric compositions may be used.
A via hole is etched into the upper-level dielectric layer 114 typically using, in the case of silicate dielectrics, a fluorine-based plasma etching process. In advanced integrated circuits, the via holes may have widths as low as 0.18 μm or even less. The thickness of the dielectric layer 114 is usually at least 0.7 μm, and sometimes twice this, so that the aspect ratio of the hole may be 4:1 or greater. Aspect ratios of 6:1 and greater are being proposed. Furthermore, in many circumstances, the via hole often has a vertical profile.
A liner layer 116 may be deposited onto the bottom and sides of the hole and above the dielectric layer 114. The liner 116 can perform several functions. It can act as an adhesion layer between the dielectric and the metal since metal films tend to peel from oxides. It can also act as a barrier against inter-diffusion between the oxide-based dielectric and the metal. It may also act as a seed and nucleation layer to promote the uniform adhesion and growth and possibly low-temperature reflow for the deposition of metal filling the hole and to nucleate the even growth of a separate seed layer. One or more liner layers may be deposited, in which one layer may function primarily as a barrier layer and others may function primarily as adhesion, seed or nucleation layers.
An interconnect layer 118 of a conductive metal such as copper, for example, is then deposited over the liner layer 116 to fill the hole and to cover the top of the dielectric layer 114. Conventional aluminum metallizations are patterned into horizontal interconnects by selective etching of the planar portion of the metal layer 118. However, a preferred technique for copper metallization, called dual damascene, forms the hole in the dielectric layer 114 into two connected portions, the first being narrow vias through the bottom portion of the dielectric and the second being wider trenches in the surface portion which interconnect the vias. After the metal deposition, chemical mechanical polishing (CMP) is performed which removes the relatively soft copper exposed above the dielectric oxide but which stops on the harder oxide. As a result, multiple copper-filled trenches of the upper level, similar to the conductive feature 112 of the next lower level, are isolated from each other. The copper-filled trenches act as horizontal interconnects between the copper-filled vias. The combination of dual damascene and CMP eliminates the need to etch copper. Several layer structures and etching sequences have been developed for dual damascene, and other metallization structures have similar fabrication requirements.
Lining and filling via holes and similar high aspect-ratio structures, such as occur in dual damascene, have presented a continuing challenge as their aspect ratios continue to increase. Aspect ratios of 4:1 are common and the value will further increase. An aspect ratio as used herein is defined as the ratio of the depth of the hole to narrowest width of the hole, usually near its top surface. Via widths of 0.18 μm are also common and the value will further decrease. For advanced copper interconnects formed in oxide dielectrics, the formation of the barrier layer tends to be distinctly separate from the nucleation and seed layer. The diffusion barrier may be formed from a bilayer of Ta/TaN, W/WN, or Ti/TiN, or of other structures. Barrier thicknesses of 10 to 50 nm are typical. For copper interconnects, it has been found useful to deposit one or more copper layers to fulfill the nucleation and seed functions.
The deposition of the liner layer or the metallization by conventional physical vapor deposition (PVD), also called sputtering, is relatively fast. A DC magnetron sputtering reactor system has a target composed of the metal to be sputter deposited and which is powered by a DC electrical source. The magnetron is scanned about the back of the target and projects its magnetic field into the portion of the reactor system adjacent the target to increase the plasma density there to thereby increase the sputtering rate. However, conventional DC sputtering (which will be referred to as PVD in contrast to other types of sputtering to be introduced) predominantly sputters neutral atoms. The typical ion densities in PVD are often less than 109 cm−3. PVD also tends to sputter atoms into a wide angular distribution, typically having a cosine dependence about the target normal. Such a wide distribution can be disadvantageous for filling a deep and narrow via hole 122 such as that illustrated in FIG. 2, in which a barrier layer 124 has already been deposited. The large number of off-angle sputter particles can cause a layer 126 to preferentially deposit around the upper corners of the hole 122 and form overhangs 128. Large overhangs can further restrict entry into the hole 122 and cause inadequate coverage of the sidewalls 130 and bottom 132 of the hole 122. Also, the overhangs 128 can bridge the hole 122 before it is filled and create a void 134 in the metallization within the hole 122. Once a void 134 has formed, it is often difficult to reflow it out by heating the metallization to near its melting point. Even a small void can introduce reliability problems. If a second metallization deposition step is planned, such as by electroplating, the bridged overhang makes subsequent deposition more difficult.
One approach to ameliorate the overhang problem is long-throw sputtering, in which the sputtering target is spaced relatively far from the wafer or other substrate being sputter coated. For example, the target-to-wafer spacing can be at least 50% of the wafer diameter, preferably more than 90%, and more preferably more than 140%. As a result, the off-angle portion of the sputtering distribution is preferentially directed to the chamber walls, but the central-angle portion remains directed substantially to the wafer. The truncated angular distribution can cause a higher fraction of the sputter particles to be directed deeply into the hole 122 and reduce the extent of the overhangs 128. A similar effect can be accomplished by positioning a collimator between the target and wafer. Because the collimator has a large number of holes of high aspect ratio, the off-angle sputter particles tend to strike the sidewalls of the collimator, and the central-angle particles tend to pass through.
Another technique for deep hole lining and filling is sputtering using a PVD sputtering process called ionized metal plasma (IMP). A typical high-density plasma is one having an average plasma density across the plasma, exclusive of the plasma sheaths, of at least 1011 cm3, and preferably at least 1012 cm−3. In IMP deposition, a separate plasma source region is formed in a region away from the wafer, for example, by inductively coupling RF power into a plasma from an electrical coil wrapped around a plasma source region between the target and the wafer. The plasma generated in this fashion is referred to as an inductively coupled plasma (ICP). An IMP chamber having this configuration is commercially available from Applied Materials of Santa Clara, Calif. Other IMP sputter reactor systems are available. The higher power ionizes not only the argon working gas, but also significantly increases the ionization fraction of the sputtered atoms, that is, produces metal ions. The wafer either self-charges to a negative potential or is RF biased to control its DC potential. The metal ions are accelerated across the plasma sheath as they approach the negatively biased wafer. As a result, their angular distribution becomes strongly peaked in the forward direction so that they are drawn deeply into the via hole. Overhangs become much less of a problem in IMP sputtering, and bottom coverage and bottom sidewall coverage are relatively high.
Another technique for depositing metals is sustained self-sputtering (SSS). Examples are described by Fu et al. in U.S. Pat. No. 6,692.617 issued Feb. 17, 2004 and by Fu in U.S. Pat. No. 6,183,614 B1 issued Feb. 6, 2001. For example, at a sufficiently high plasma density adjacent a copper target, a sufficiently high density of copper ions develops that the copper ions will resputter the copper target with yield over unity. The supply of argon working gas can then be eliminated or at least reduced to a very low pressure while the copper plasma persists. Aluminum is believed to be not readily susceptible to SSS. Some other materials, such as Pd, Pt, Ag, and Au can also undergo SSS.
Techniques and reactor structures have been developed to promote sustained self-sputtering. It has been observed that some sputter materials not subject to SSS because of sub-unity resputter yields nonetheless benefit from these same techniques and structures, presumably because of partial self-sputtering, which results in a partial self-ionized plasma (SIP). Furthermore, it is often advantageous to sputter copper with a low but finite argon pressure even though SSS without any argon working gas is achievable. Hence, SIP sputtering is the preferred terminology for the more generic sputtering process involving a reduced or zero pressure of working gas so that SSS is a type of SIP.
In the formation of semiconductor devices, it is often useful to remove a deposited layer or a portion of a layer. Plasmas may be employed in etch processes to provide ions to facilitate the removal of material from a semiconductor workpiece. In some processes, the ions may react chemically with a layer on the workpiece. In other processes, the ions may strike the workpiece with sufficient force to sputter material from the workpiece.
The etch process is often performed in a separate etch chamber designed for that purpose. The progress of the etch process may be monitored to determine an endpoint at which the etch process should be terminated. For example, in etching a first material disposed on a second material, it is often useful to terminate the etching process once the first material has been etched away sufficiently to expose the underlying second material. One known method for monitoring plasma etching is to monitor the light emitted by the plasma. Chemical constituents in the plasma such as reactant species or plasma etch products can be excited by the plasma. As the excited atoms decay, they will emit light having wavelengths which are characteristic of the atoms. The light or other radiation emitted by the plasma may be monitored through a chamber window by an appropriate detector positioned outside the chamber window. By monitoring the intensity of the plasma emissions at the wavelength or wavelengths characteristic of particular species in the plasma, the concentration of those species in the plasma can be determined. These concentrations can in turn be used to indicate the progress of the plasma etch which can then be terminated at the appropriate point.
USPTO Backgrounds
USPTO Backgrounds