1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same. More particularly, it relates to a stacked gate flash memory device that can achieve high memory cell capacity.
2. Description of the Related Art
Complementary metal oxide semiconductor (CMOS) memory is generally categorized into two groups: random access memory (RAM) and read only memory (ROM). RAM is a volatile memory, wherein the stored data is erased when power is turned off. On the contrary, turning off power does not affect the stored data in a ROM.
In the past few years, market share of ROM has been continuously expanding, and the type attracting the most attention has been flash memory. The fact that a single memory cell is electrically programmable and multiple memory cell blocks are electrically erasable allows flexible and convenient application, superior to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and programmable read only memory (PROM). Furthermore, fabricating flash memory is cost effective. Having the above advantages, flash memory has been widely applied in consumer electronic products, such as digital cameras, digital video cameras, mobile phones, notebooks, personal stereos and personal digital assistants (PDA).
Since portability of these electrical consumer products is strongly prioritized by consumers, the size of the products must be minimal. As a result, capacity of flash memory must increase, and functions must be maximized while size thereof is continuously minimized. Having an increased amount of access data, capacity of memory cells has been enhanced from 4 to 256 MB, and even 1G byte will become the market trend in the near future.
Hence, there is a need for a flash memory device with high memory cell capacity.
Accordingly, an object of the invention is to provide a stacked gate flash memory device that can achieve high integration of memory cells thereof.
Another object of the invention is to provide a method of fabricating a stacked gate flash memory device, wherein the size of memory cells thereof can be reduced and the coupling ratio of the control gate to the floating gate can be also increased.
Moreover, the invention provides a method of fabricating a stacked gate flash memory device, wherein the driving currents thereof can be increased without increasing the surface size thereof.
Thus, a stacked gate flash memory cell in accordance with the present invention comprises a substrate having a trench therein. A conductive layer is disposed on the bottom of the trench. A pair of source regions are each respectively disposed in the substrate adjacent one sidewall of the trench and electrically connected by the conductive layer. A source isolation layer is disposed on the conductive layer. A pair of tunnel oxide layers are each respectively disposed on one sidewall of the trench and the source isolation layer. A U-shaped floating gate is disposed on the source isolation layer, and connects the tunnel oxide layers thereby. A pair of control gate spacers are each respectively disposed on each vertical portion of the U-shaped floating gate, substantially having the same width as the vertical portions. A U-shaped inter-gate dielectric layer is disposed on the U-shaped floating gate and the control gate spacers. A control gate is disposed in the U-shaped inter-gate dielectric and a drain region is disposed in the substrate adjacent to the trench.
Furthermore, the method of fabricating the stacked gate flash memory cell in accordance with the present invention comprises providing a substrate, forming a plurality of parallel long trenches along a first direction in the substrate, forming a conductive layer and a pair of source regions on the bottom of each long trench, wherein the source regions are respectively disposed in the substrate adjacent to two sidewalls of each long trench and electrically connected by the conductive layer therein, forming a source isolation layer on each conductive layer, forming a tunnel oxide on two sidewalls of each long trench, forming a U-shaped floating gate on each source isolation layer, contacting the tunneling oxide layers, forming a pair of control gate spacers respectively disposed on the vertical portion of the U-shaped floating gate, substantially having the same width as the vertical portions, forming an U-shaped inter-gate dielectric layer on each U-shaped floating gate and the control gate spacers, forming a control gate in each U-shaped inter-gate dielectric layer, forming a plurality of parallel shallow trench isolation (STI) regions along a second direction, defining a plurality of cell trenches and forming a drain region in the substrate adjacent to each cell trench.
In the present invention, the trench-type stacked gate flash memory device disposed in cell trenches within a substrate can achieve higher integration of memory cell capacity than that in the Prior Art.
In addition, most of the fabricating processes in the invention are self-aligned and additional lithography processes and number of masks for the whole fabricating process can be reduced. The complexity of fabrication is reduced and can be easily achieved. The higher coupling ratio by the memory cells also provides a lower operating voltage thereof.
Furthermore, most patterns of the masks for fabricating the stacked gate flash memory device are rectangular and can be easily fabricated. The costs of mask fabrication can be reduced and resolution limitations by the photolithography tools can be reduced.
USPTO Backgrounds
USPTO Backgrounds