1. Technical Field
This invention relates to voltage sampling circuits. More particularly, it relates to circuits which sample monotonic input voltage changes and hold an output precisely derived from an input voltage.
2. Background Art
Present day thin film transistor liquid crystal displays (TFT/LCD's) are limited in color rendition to about 4 bits (16 levels) per color. If these displays are to compete with CRT's in most application areas, 8-bit performance is needed. One of the key problems in achieving that goal is the economical designability of the data-line driver circuits. The stage of such circuits which most restricts the application range is the analog sample-and-hold or track-and-hold stage, which must capture an analog level corresponding to the intensity of each sub-pixel in one sub-pixel time and hold it for up to one line time. Some design relief may be obtained by dividing the display into segments operated in parallel. Nevertheless, existing methods and circuits are not promising for 8 bits per color in a large display.
Many methods of deriving the data line signals and applying them to the display data lines are in use or have been described in the literature. A first method which appears to be most extendable to the megapixel, 8-bit per color range is the "TV method" in which the analog video signal representing a line is sampled and held at each column in sequence at a time appropriate to the column. A second is the "ramp method" in which the digital data for a line is distributed to the column circuits and an analog voltage ramp representing the range of analog data is sampled and held at each column at the instant that the ramp voltage is equivalent to the digital word stored at that column.
The ramp method is the more extendable of the two because of two advantages which tend to reduce the required circuit bandwidth: First, in the design range addressed here there are fewer sampling intervals within a line time; 256 (corresponding to 256 analog levels) for the ramp method compared to 3000 (corresponding to 3000 sub-pixels per line) for the TV method. Second, the ramp voltage changes monotonically and gradually during the line time, while in the TV method the analog video can change abruptly and arbitrarily over the full dynamic range at any pixel time.
The ramp method may be improved by using a staircase waveform with discrete analog steps instead of a ramp so that performance is less influenced by errors due to time jitter, delay tolerances and propagation dispersion. In the preferred embodiments the present invention finds application in this staircase method.
FIG. 1 shows the commonly used MOS sampling switch 10 of the prior art in an NMOS implementation. It consists of NMOS field effect transistor 12 and a capacitor 14. Another commonly used sampling switch is CMOS, consisting of an NMOS and a PMOS device with sources and drains connected together respectively and with gates connected to complementary control signals. In the circuit of FIG. 1, the analog input to be sampled is applied to the source electrode 16 and a sample pulse is applied to the gate electrode 18 of the transistor. When the sample pulse is in a high state the output voltage across capacitor 14 charges to, and tracks, the analog input. When the sample pulse falls, the output voltage at that time is held on capacitor 14. It is advantageous to turn on the gate pulse at the beginning of the ramp and operate in the track mode, since the circuit bandwidth required is smaller.
While simple and economical, this circuit has certain limitations and drawbacks that are undesirable in some applications. Specifically, the output change is always noninverted and equal to the input change; the output dc level of the output is the same as that of the input; the charging current for the capacitor comes from the analog input source, loading the input; and as a consequence multiple stages cannot be cascaded without charge sharing errors, unless buffer amplifiers are provided between stages. Finally, when the number of bits and the number of pixels are large, the sampling window becomes short and the accuracy required of the capacitor voltage becomes large. This leads to a large channel width for the switch and a small value of capacitance. In this type of sample and hold, there is inherently a considerable amount of charge stored in the switch channel at the instant before the gate pulse falls because the source and drain voltages are virtually equal and the gate-to-source/drain voltage is above threshold. At the fall of the gate pulse much of this charge is transferred to the capacitor where it creates a data-dependent "pedestal error" which is large because of the wide channel and small capacitor. At the same time, the tolerance of the system to pedestal error is small because of the large number of bits. (A second source of pedestal error is the gate to source stray capacitance, but with modern self-aligned technologies this can be negligible.) In commercial sample-hold circuits this error is avoided by complex techniques employing operational amplifiers, which are too complex and space-consuming for this application. Partial fixes are also known, but are both complex and inadequate.
USPTO Backgrounds
USPTO Backgrounds