Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a method for forming fine patterns in a semiconductor device. Exemplary embodiments of the present invention are useful for a method for forming fine metal interconnections.
As a semiconductor device become highly integrated, formation of fine patterns is desirable. However, due to the limited resolution of exposure equipment, it is difficult to fabricate a device having fine patterns using 20 nm or under 20 nm process.
In order to address such a concern, a spacer patterning technology (SPT) which forms spacers on sidewalls of a hard mask and performing indirect patterning is often used. Such a technology is, for example, disclosed in Korean Unexamined Patent Publication No. 2008-0113857.
FIGS. 1A to 1G are cross-sectional views illustrating a method for forming metal interconnections by using a typical SPT process.
Referring to FIG. 1A, contact plugs 102a, 102b and 102c are formed through an insulation layer 101 while being spaced apart from one another by a predetermined distance. An insulation layer 103 is formed on the plugs 102a, 102b and 102c and the insulation layer 101, and a hard mask layer 104 and a non-reflective layer 105 are formed on the insulation layer 103. Photoresist patterns 106 are formed on the non-reflective layer 105 to overlap the plugs 102a and 102c. The insulation layer 103 includes silicon oxide and the hard mask layer 104 includes a carbon-based thin film.
Referring to 1B, the non-reflective layer 105 and the hard mask layer 104 are etched by using the photoresist patterns 106 as an etch barrier, and remaining photoresist patterns and non-reflective layer are removed, thereby forming hard mask patterns 104a and 104c. 
Referring to 1C, a thin film 107 for a spacer is deposited on the resultant structure including the hard mask patterns 104a and 104c. The thin film 107 for a spacer includes a metal having an etching selectivity with respect to the insulation layer 103. Referring to 1D, the thin film 107 is etched to form spacers 107a. 
Referring to 1E, the hard mask patterns 104a and 104c are removed, and the insulation layer 103 is etched by using the spacers 107a as an etch barrier, thereby forming an insulation pattern 103a. 
Referring to 1F and 1G, a metal layer 108 is deposited on a resultant structure including the insulation pattern 103a and is planarized using chemical mechanical polishing (CMP) until the insulation pattern 103a is exposed, thereby forming metal interconnections 108a. 
As described above, in the conventional method for forming the metal interconnections, the process is relatively complicated.
For example, according to the prior art, the total of five layers including the insulation layer, the hard mask layer, the non-reflective layer, the thin film for a spacer, and the metal layer are used. Furthermore, according to the prior art, etching processes are performed three times, that is, etching of the hard mask layer, etching for the spacer, and etching of the insulation layer.
USPTO Backgrounds
USPTO Backgrounds