1. Field of the Invention
This invention relates to the field of programmable interconnect structures within an integrated circuit. More specifically, the present invention relates to local interconnect lines contained within field programmable gate arrays.
2. Background Technology
Programmable integrated circuits, specifically field programmable gate arrays (FPGAs) typically include configurable logic blocks (CLBs) and a programmable interconnect structure. Typically, the interconnect structure is used for providing signals to the CLBs, for routing signals between CLBs, and for routing signals to other devices within the FPGA. Routing of signals, especially address signals, from global longlines to a look-up table (LUT) of a CLB is important to programmable integrated circuits, such as FPGAs. Often, a LUT can be configured as a memory, with address lines which extend both vertically and horizontally from the CLB within the semiconductor substrate. The address lines are then electrically coupled to vertically arranged global longlines disposed near columns of CLBs. The global longlines are used to supply common addressing signals to a plurality of CLBs and, as such, extend across a large portion of the FPGA.
FIG. 1, illustrates a CLB 10, which includes a LUT 12, and a plurality of global longlines 14a-14f. Horizontal local interconnect lines 16a-16d are provided above and below CLB10. Horizontal input/output lines 18a-18d, hereinafter referred to as horizontal input/output lines, hereinafter referred to as address lines, extend horizontally from LUT 12. Additionally, vertical address lines 20a-20d, extend vertically from LUT 12. Horizontal address lines 18a-18b are electrically coupled to desired global longlines using a programmable interconnect points (PIPS) such as PIPs 22a-22d positioned at line intersections. Prior art FIG. 2 illustrates a diagrammatic and a more detailed representation of a PIP 30 including a transistor 36a coupled between lines 32 and 34. If programmed ON via a programmable memory cell 36b, transistor 36a couples line 32 and 34. If transistor 36a is programmed OFF, lines 32 and 34 are not connected.
In prior art configurations, to connect the vertical address lines to the global longlines of FIG. 1, two PIPs are required because the vertical address lines are parallel to the global longlines. For example, as shown in FIG. 1, PIP 24b and PIP 24a are required to connect vertical address line 20a to global longline 14b. Specifically, PIP 24b couples address line 20a to horizontal interconnect line 16b, and PIP 24a couples local interconnect line 16b to global longline 14b. The use of multiple PIPs increases impedance and reduces signal speed. Furthermore, using PIPs on horizontal interconnect line 16b to address LUT 12 prevents horizontal interconnect line 16b from being used for other routing purposes. Thus, when the number of vertical address lines increases, the number of horizontal interconnect lines available for other routing purposes is correspondingly reduced. Therefore, multiple PIP connection schemes create a substantial routing barrier within an FPGA. Thus, a need exists for an interconnection mechanism or structure which minimizes the number of PIPs, and which eliminates routing barriers associated with the prior art.
USPTO Backgrounds
USPTO Backgrounds