Dual In Line Memory Modules (DIMM) specifications define a modular memory device comprising small Printed Wiring Boards (PWB) boards with an array of memory devices. DIMM achieve high-speed data transfer rates of up to 100 Mhz in part by using an architecture that synchronizes the output data from the DIMM to a system clock. DIMMS with Synchronous Dynamic Random Addressable Memory (SDRAM) utilize clock signals provided to each DIMM for synchronization. DIMM modules with SDRAM having bus transfer rates of 66 MHz and above typically require about 1 ns worst case clock skew between the clock to the DIMM and clock to the SDRAM. DIMM modules commonly use a phase-lock-loop (PLL) circuit on each DIMM to re-drive the clock signals to both the memory devices and registers to minimize system clock loading and to provide low skew between input and output clock signals.
Timing error resulting from clock to data skew becomes an increasingly significant factor as memory device speed and bus transfer rates increase. Microprocessor system boards commonly have sockets for two to eight DIMMs and provide a duplicate copy of a single reference clock signal to each DIMM. Typically, the DIMM share a common bidirectional data bus resulting in each DIMM having a different data signal propagation time. Each inch of signal trace typically has more than 1 ns of signal propagation time, and sockets add additional capacitance and inductance that increase the skew in data propagation times between each DIMM.
Allowable timing error margins are reduced as bus transfer rates are increased. When worst case error margins are exceeded, reliability in mass production decreases. Timing problems show up as sporadic system crashes in some systems, which is unacceptable in systems such as servers that require consistent high reliability. DIMM specifications define a board outline and a system interface to provide for interchangeability between DIMMs having different memory device types and manufactures. Different types of DIMNs will have different AC characteristics, such as the data pin input capacitance and characteristic transmission line impedance that when combined with the variations in the AC characteristics of microprocessor systems boards result in worst case error margins being exceeded when minimum and maximum specifications and electrical characteristics of connectors are considered. Error margins are further reduced when the effects of temperature variations are taken into consideration. Device speeds vary with temperature. Memory systems are becoming increasingly more dependent on precision trace propagation times. Temperature swings of 0.degree. C. to 70.degree. C. results in 10% to 20% change in signal propagation times.
DIMM specifications allow the CAS latency to be varied on read cycles to provide additional clock periods to increase the read cycle time to SDRAM, however, the additional cycles typically results in microprocessor wait states that will degrade system performance. DIMM specifications do not provide flexibility in the number of clock periods in a write memory cycle. For DIMMs having long data propagation paths, a delayed clock signal to the individual SDRAM is needed that will allow additional set up time for the data signal to propagate and settle prior to being sampled; however, a delayed clock will increase the time for the data from the SDRAM on read cycles to reach the microprocessor or, alternately, be latched by a register on the system board requiring increased number of read clock periods to complete the memory read cycles. Phase-lock-loop clock drivers are available that provide selectable phase-offset magnitudes, but the prior art phase-lock-loop drivers do not allow for the phase-offset to be changed instantaneously (within a single clock period) in response to external stimuli. New methods are needed for providing precise and instantaneous phase-offset adjustment of the clock signal to each SDRAM based on the type of bus cycle in progress.
USPTO Backgrounds
USPTO Backgrounds