1. Technical Field
The present invention relates to signal delay devices for integrated circuits and, in particular, to testability of digital delay lines.
2. Description of Related Art
Delay elements perform the function of delaying a signal in accordance with a control signal. For proper functioning of synchronous circuits, it is important for data to arrive at the right time relative to a clock signal. Due to process variations and other design constraints, this is not always the case. Digital delay lines are commonly employed to compensate for variations in design and fabrication. Digital delay lines provide a mechanism for adding a set amount of delay into the receipt of a signal.
As the chip sizes grow, the requirements for delay compensation also grow. These linear delay stepping devices occupy a huge amount of chip area and, therefore, are susceptible to structural defects during the manufacturing process. It is important and economical to be able to test for these structural faults very early in the production cycle of the chip. Currently delay lines are either not testable or are only partially testable at the wafer level using a static fault model.
A primary cause of non testability comes from a pattern fault model for the delay element selection multiplexer. A pattern fault model dictates that a wafer tester should be able to observe as well as independently control every input of a multiplexer. This is required because multiplexers are constructed using transmission gates wired together. Even when one of the inputs is selected, other another input might have an effect on the output based upon weak coupling due to an improperly manufactured device. These kinds of faults can only be detected when the test pattern generator creates a pattern that looks at the output when a first input is selected and varies the value of another input to check if the output has changed. If the devices have been manufactured properly, the output should not change.
Most current delay line circuits use a chain of delay elements, such as buffers or inverters, switched into or out of the signal path using a multiplexer. An input of logic value “1” into the delay line input will force a “1” on all inputs to the multiplexer. This is the expected operation during functional mode; however, during a static fault test at wafer level, this circuit cannot be tested for pattern faults. When a tester selects a first input of the multiplexer, the tester should also be able to vary the values of a second, third, or fourth input, for example, and check the effect on the output. This inability to verify the design for pattern faults reduces the testability coverage. Reduction in testability coverage leads to poor diagnostics in case of the lower yields.
USPTO Backgrounds
USPTO Backgrounds