There is a conventional method of fabricating a semiconductor device in which a metal silicide layer with low resistivity is formed by reacting an upper portion of polycrystalline silicon as a control gate of a flash memory with a metal film. This technique, for example, is disclosed in JP-A-2007-207947.
However, according to the conventional method, when a metal silicide layer is formed on a control gate, a silicidation reaction may proceed above an upper surface of an insulating film between control gates in a metal film. Above the upper surface of the insulating film between the control gates, the silicidation reaction proceeds not only in a vertical direction but also in a horizontal direction, thereby narrowing a distance between metal silicides of the adjacent control gates. Therefore, voltage endurance characteristics of an electrode structure may be deteriorated. Furthermore, as a result of the silicidation reaction proceeded in the horizontal direction, the metal silicides of the adjacent control gates may contact each other, thereby causing short circuit.
USPTO Backgrounds
USPTO Backgrounds