1. Field of the Invention
The present invention relates to a power and signal line bussing method for high density and high speed memory devices.
2. Description of the Prior Art
A conventional power line bussing method is shown in FIG. 1. Chip 1 has two memory cell arrays 2 centered around peripheral circuitry 4, which comprises multiple logic circuits. Power line 3a supplies power from Vcc pad 5 to peripheral circuitry 4. Power line 3a runs from Vcc pad 5, around memory cell array 2, to peripheral circuitry 4. Ground line 3b electrically connects peripheral circuitry 4 with GND pad 5'. Ground line 3b runs from GND pad 5', around memory cell array 2, to peripheral circuitry 4.
However, employing a single power line 3a to couple power to peripheral circuitry 4 does not effectively reduce noise. To best reduce noise, a power line should be coupled independently to each circuit in peripheral circuitry 4. Yet, separating power line 3a further would increase the chip size because the area around memory cell arrays 2 would need to be enlarged. Thus, the bussing arrangement according to the conventional bussing method is not conductive to noise reduction nor high density packing.
A conventional signal line bussing arrangement for chip 1 is shown in FIG. 2. Pad signal line 3', positioned around memory cell arrays 2, supplies signals from external pad 6 to peripheral circuit 4. Circuit signal line 3", also positioned around memory cell array 2, supplies signals from internal circuit 6' to peripheral circuitry 4.
However, signal line bussing according to this arrangement results in large signal delays because signals from pad 6 or internal circuit 6' must propagate the extra distance required to circumvent memory cell arrays 2.
A final disadvantage of conventional bussing arrangement arises inherently from the design. During conventional packaging processes, a passivation layer and an insulation layer are formed above the memory cell array. A final package material layer is then formed on top of the passivation layer. Yet, even with the passivation and insulation layers, radiation generated from the package material layer penetrates the memory cells and causes a soft (or operation) error. To prevent this soft error, an additional shield layer formed on the memory cell array is desired.
USPTO Backgrounds
USPTO Backgrounds