(a) Field of the Invention
The present invention relates to a wiring board to be used with being mounted on a packaging board such as an interposer or another wiring board. More specifically, the invention relates to a chip component mounted wiring board including a passive device (chip component) such as a chip-shaped capacitor or inductor surface-mounted on the surface facing the packaging board.
The aforementioned chip component mounted wiring board is also referred to as a “semiconductor package” or simply as a “package” in the description below for the sake of convenience, because it has the role as a package for mounting an electronic component such as a semiconductor element on the surface opposite to the side facing the packaging board.
(b) Description of the Related Art
While smaller and thinner semiconductor devices with higher performance (higher functionality) have increasingly been developed, POP (package-on-package) bonding is in demand in order to reduce the mounting area in the case where a semiconductor device is formed by mounting a semiconductor element or the like on a wiring board (semiconductor package). In the POP bonding, the packages each including the semiconductor element or the like mounted thereon are stacked in a vertical direction (height direction).
With such a demand, still finer and higher-density wirings are in demand also in semiconductor packages. Such a demand leads to a situation where the wiring patterns are arranged in closer proximity. As a result, a problem such as a crosstalk noise generated between the wirings or a fluctuation in the potential of a power source line or the like may occur. In particular, in a package on which an electronic component such as a semiconductor element requiring a high speed switching operation (such as an MPU) is mounted, an increase in frequency makes a crosstalk noise easy to be generated. In addition, a high speed on/off operation of a switching element generates a switching noise, which causes the potential of the power source line or the like to easily fluctuate. In this respect, for the purpose of stabilizing the power source voltage and reducing the switching noise or the like, an approach has been conducted in which a capacitor function is implemented in the semiconductor package and thus “decoupling” of the power source line or the like is performed.
As an example of the approach, the following structure with POP bonding is cited. In this structure, a chip capacitor is mounted on a back surface of a wiring board (the surface thereof on a side facing the other wiring board (package)), and the chip capacitor is then connected to the other package, thereby making an electrical connection between the wiring board and the other package. As a typical structure of the chip capacitor used in the aforementioned structure, the chip capacitor includes a substantially cuboid-shaped capacitor body (element portion) and a pair of terminal electrodes formed at both end portions of the capacitor body. Furthermore, a metal layer (typically, tin (Sn) plated layer) for enhancing the wettability of solder is provided on the uppermost surface of each of the terminal electrodes, the solder being used as a bonding member when the chip capacitor is mounted on a wiring board or the like.
Where the aforementioned mounting structure is implemented using such a chip capacitor, an appropriate amount of solder (paste-like) is first attached to each of the pads exposed from a solder resist layer on the back surface of the wiring board. Then, terminal electrodes of the capacitor are aligned with the positions of the pads, respectively. Thereafter, the terminal electrodes are bonded to the pads by melting the solder through reflow soldering. Thus the chip capacitor is mounted on the wiring board. Furthermore, required terminals (pads) are also prepared on the other package on which the wiring board is to be stacked. Then, an appropriate amount of solder (paste-like) is attached to the corresponding pads. Subsequently, the terminal electrodes of the capacitor are aligned with the positions of the pads, respectively. Thereafter, the chip capacitor is bonded to the other package by melting the solder through reflow soldering.
An example of the technique related to the aforementioned prior art is described in Japanese unexamined Patent Publication (JPP) (Kokai) 2000-77257. This publication discloses an axial type electronic component in which bottomed cylindrical-shaped metal caps are put over terminals of a chip-shaped electronic component element, respectively, and coated by resin. In this electronic component, a redundant metal layer made of solder is provided on the inner circumferential surface of the cylindrical portion of each of the metal caps. With this structure, the solder of the redundant metal layer flows outside the cylindrical portion when the resin expands. Thereby, a plated layer of each of the terminals is prevented from being affected by the expansion of the resin.
In addition, another technique related to the aforementioned prior art is described in JPP (Kokai) 2007-134398. This publication discloses a chip-shaped electronic component provided with terminal electrodes at both end portions of an element body, respectively. In this electronic component, a recessed portion is provided at a substantially center portion of the end surface of each of the terminal electrodes, and the width and the maximum depth of the recessed portion to be formed are selected to be predetermined values, respectively. With this structure, the occurrence of chip-standing is suppressed while the occurrence of solder spattering at the time of mounting of the electronic component is avoided.
In the prior art as described above, there is a case where the chip capacitor surface-mounted on the wiring board (package) is also connected to the other package and thus an electrical connection is made between both the packages. In that case, a problem below occurs due to the fact that the Sn plated layers are provided on the surfaces of the terminal electrodes of the chip capacitor.
Namely, when the chip capacitor is mounted on a wiring board (package), tin (Sn) contained in the plated layer on the surface of each of the terminal electrodes flows to the wiring board side due to the heat during reflow soldering, so that the amount of Sn in the portion on the opposite side (the other package side) of the terminal electrode is relatively reduced. In some cases, the metal portion of a layer (nickel (Ni) layer or another alloy layer, for example) below the Sn plated layer is exposed in the reduced portion, so that the solder wettability of the portion is reduced.
Accordingly, there occurs a problem in that, when the chip capacitor is bonded to solder prepared on the other package side, the solder on the other package and the plated portion of the chip capacitor do not wet sufficiently, so that the chip capacitor cannot be bonded to the solder. This is because the solder wettability of the portion on the other package side of the terminal electrodes is reduced as described above.
Namely, the terminal electrodes of the chip capacitor are provided in the form of being shared by the wiring board (package) side and the packaging board (other package) side. Accordingly, there occurs a problem in that, when a chip capacitor surface-mounted on a wiring board is bonded to a packaging board side, the chip capacitor is not sufficiently bonded to the packaging board and thus a closely-bonded state cannot be secured (poor connection) because of the insufficient wettability of the plated surface of the chip capacitor as described above.
USPTO Backgrounds
USPTO Backgrounds