1. Field of the Invention
This invention relates to pre-conditioned CMOS gates and more specifically to such gates having improved switching speed, noise immunity, reduced power consumption and simplified layout.
2. Previous Art
Dynamic CMOS logic gates ("logic elements") have been used in applications where speed and reduced silicon area are at a premium, such as in high speed arithmetic units and state vector generation circuits (Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, pages 61, 210). On the other hand, static CMOS circuits have been preferred when simplicity and reliability of operation are required (id., at page 61).
At least one researcher has suggested that static CMOS circuits and a single phase clocking system can be modified to exhibit the speed, power and silicon area advantages of dynamic CMOS (id., pages 377, 378 and FIG. 8.18). However, to date no one has succeeded in fulfilling the promise of the suggestion, and in fact, the same researcher has expressed the view that it would be "risky" to construct an entire pipelined system by dynamic logic and dynamic latches (id., at page 236).
What is needed is a dynamic CMOS logic element which can be used in pipelined circuits and which exhibits improved switching speed.
What is also needed is a dynamic CMOS logic element having improved switching speed and noise immunity.
What is also needed is a dynamic CMOS logic element having improved switching speed, improved noise immunity and reduced power consumption.
Finally, what is needed is a dynamic CMOS logic element having improved speed and noise immunity, reduced power consumption and simplified layout.
USPTO Backgrounds
USPTO Backgrounds