This invention relates to a binary logic circuit for approximating a mathematical curve over a predefined range as a series of linear segments, and a method of deriving a hardware representation of such a binary logic circuit.
It is often desirable to perform certain functions at high speed in hardware. For example, integrated circuits for performing computer graphics processing and digital signal processing can frequently need to calculate the value of a log or gamma function for a given input value. Hardware for performing such calculations will typically operate over a defined range of input values and will typically be required to calculate the function to a certain level of accuracy. This allows hardware designers to use an approximation to a given function so as to provide a low latency solution which does not consume an inordinate amount of area on an integrated circuit.
The log2 function is one such function which is often implemented in silicon and, conventionally, has often been approximated over the interval [1, 2] by a straight line. This is the so-called Mitchell approximation 102 illustrated in FIG. 1. While it provides a fast approximation when implemented in hardware, it can be seen that the Mitchell approximation differs from the curve of the log2 function 101 in particular near the middle of the interval [1,2].
The poor accuracy of the Mitchell approximation has led to the development of look-up table based approaches, such as is described in U.S. Pat. No. 4,583,180. These approaches replace the calculation of an approximation function (such as the straight line of Mitchell) with a look-up into a large table of pre-calculated values for the function itself. Such an approach is accurate but the memory requirements for the look-up table consume a large area of integrated circuit and can be relatively slow.
Further refinements of the look-up table approach have been developed which use interpolation between values in a smaller look-up table to provide a similar degree of accuracy whilst reducing the size of the table. One recent approach of this variety has been proposed by Paul et al. in their paper “A fast hardware approach for approximate, efficient logarithm and antilogarithm computations”, IEEE Transactions on VLSI Systems, Vol. 17, No. 2, February 2009. However, this approach requires the use of a multiplication array in hardware which is adapted to perform multiplication of two variables. Such a construct is complex and consumes a large area on an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds