The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly, to technology for preventing a semiconductor device from malfunctioning due to a capacitive coupling between lines, where the lines are used for transmitting test mode signals.
With technology developments, fabrication of a semiconductor memory device has improved to enable the production of such devices with elements of smaller and smaller size for high integration.
With improvements in the fabrication process, chip sizes have decreased, allowing more and more metal lines to be disposed in a given space. As more and more metal lines are disposed in a given space, the effect of a capacitive coupling (i.e., a capacitive effect as if discrete capacitors were present between the metal lines) increases. A variety of signals and data are affected by noise due to such coupling capacitors. Thus, a method for reducing this effect is useful.
FIG. 1 is a diagram illustrating transmission lines for test mode signals disposed between global data input/output (I/O) lines in order to reduce a capacitive coupling between the global data I/O lines.
Referring to FIG. 1, when toggle signal lines such as global data I/O lines GIO1, GIO2 and GIO3 are disposed adjacent to each other, they are significantly subject to interference due to a capacitive coupling. Thus, supply voltage (VDD) lines (not illustrated in FIG. 1) or ground voltage (VSS) lines (not illustrated in FIG. 1) are disposed between the global data I/O lines GIO1, GIO2 and GIO3 in order to prevent or reduce a capacitive coupling effect between the global data I/O lines GIO1, GIO2 and GIO3.
However, since the number of power lines such as VDD lines or VSS lines is limited, disposing a sufficient number of power lines between the global data I/O lines GIO1, GIO2 and GIO3 is relatively difficult. Thus, as illustrated in FIG. 1, transmission lines for DC signals such as test mode signals TM_A and TM_B are disposed between the global data I/O lines GIO1, GIO2 and GIO3.
Here, the test mode signals TM_A and TM_B are level signals. In general, the test mode signals TM_A and TM_B are at a ‘High’ level in a test mode and at a ‘Low’ level in a non-test mode. Thus, in designing a memory device, the transmission lines for the test mode signals TM_A and TM_B having the same level as the ground voltage (VSS) are disposed between the global data I/O lines GIO1, GIO2 and GIO3 in a normal case (that is, a non-test mode) in order to prevent a capacitive coupling effect between the global data I/O lines GIO1, GIO2 and GIO3.
FIG. 2 is a diagram illustrating a problem that occurs when the transmission lines for the test mode signals TM_A and TM_B are disposed between the global data I/O lines GIO1, GIO2 and GIO3.
Referring to FIG. 2, when data of the global data I/O lines GIO1, GIO2 and GIO3 around the transmission lines for the test mode signals TM_A and TM_B change from ‘Low’ to ‘High’ level, the test mode signals TM_A and TM_B also change from ‘Low’ to ‘High’ level due to a capacitive coupling effect between the global data I/O lines GIO1, GIO2 and GIO3. Thus, internal circuits receiving the test mode signals TM_A and TM_B may enter into a test mode unintentionally.
The internal circuits receiving the test mode signals TM_A and TM_B have a test mode and a normal mode (i.e., a normal operation mode not being the test mode). Normal operations are performed in the normal mode, whereas test operations different from the normal operations are performed in the test mode with a change in an operation frequency or a voltage level. Thus, when the internal circuits enter into the test mode due to the capacitive coupling effect during a normal operation, the memory device cannot perform the normal operation, which causes a failure in data read/write operations.
FIG. 3 is a diagram illustrating another problem that occurs when the transmission lines for the test mode signals TM_A and TM_B are disposed between the global data I/O lines GIO1, GIO2 and GIO3.
Referring to FIG. 3, the data of the global data I/O lines GIO1, GIO2 and GIO3 rise to a ‘High’ level at the time when the internal circuits are to exit the test mode while the test mode signals TM_A and TM_B drop to a ‘ Low’ level. In this case, the test mode signals TM_A and TM_B drop slightly from a ‘ High’ level, rise slightly toward the ‘ High’ level, and then drop toward the ‘ Low’ level. Thus, there is a delay for the test mode signals TM_A and TM_B in dropping from the ‘ High’ level to the ‘ Low’ level. This delay time changes the entry time from the test mode into the normal mode, thus causing another malfunction.
As described above, when the transmission lines for the test mode signals TM_A and TM_B are disposed between the global data I/O lines GIO1, GIO2 and GIO3, the capacitive coupling effect between the global data I/O lines GIO1, GIO2 and GIO3 may be reduced. However, the memory device may still malfunction due to an unintentional entry into the test mode or a delay in entering the normal mode.
USPTO Backgrounds
USPTO Backgrounds