The present disclosure relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present disclosure relates to a method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes.
Deep-submicron complementary metal oxide semiconductor (CMOS) is conventionally the primary technology for ultra-large scale integrated (ULSI) circuits. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry.
Transistors, such as, MOSFETs, are often built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (SixGe(1xe2x88x92x)) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. Conventional processes typically utilize polysilicon based gate conductors because metal gate conductors are difficult to etch, are less compatible with front-end processing, and have relatively low melting points. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Conventional polysilicon-based gate conductors must be doped and annealed to achieve a suitable conductivity. Generally, the annealing process can adversely affect the formation of source/drain extensions, and pocket regions. For example, the high thermal budget can cause transient enhanced diffusion (TED). Further, the high thermal budget can preclude the use of high-K gate dielectric materials.
Replacement gate processes have been proposed in which a sacrificial gate material is removed after source/drain formation. The sacrificial gate material (e.g., polysilicon) is then replaced with a metal material that does not require the doping and annealing steps of a polysilicon-based gate conductors. However, such processes can damage the substrate when removing the sacrificial gate material. Further, such processes have not been utilized with amorphous carbon lithographic processes which can achieve smaller critical dimensions.
Generally, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirous to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
Thus, there is a need to form metal gates using an improved method. Further, there is a need to use amorphous carbon as a sacrificial layer in replacement gate integration processes. Even further, there is a need to avoid the difficulties of etching a metal gate directly while using a process capable of achieving small critical dimensions (CDs).
An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric layer over the patterned amorphous carbon layer, removing a portion of the deposited dielectric layer to expose a top of the patterned amorphous carbon layer, removing the patterned amorphous carbon layer leaving an aperture in the dielectric layer, and forming a metal gate in the aperture of the dielectric layer.
Another exemplary embodiment relates to a method of forming a metal gate using a sacrificial amorphous carbon structure. The method can include patterning an amorphous carbon layer to form a sacrificial amorphous carbon structure, forming a material layer over the sacrificial amorphous carbon structure, polishing the material layer to expose the sacrificial amorphous carbon structure, removing the sacrificial amorphous carbon structure, and forming a metal gate structure where the sacrificial amorphous carbon structure was located before removal.
Another exemplary embodiment relates to a method of using amorphous carbon in the formation of a metal structure. The method can include forming an amorphous carbon structure having a critical dimension corresponding to a desired critical dimension for a metal structure, forming a first oxide layer adjacent a first side of the amorphous carbon structure and a second oxide layer adjacent a second side of the amorphous carbon structure, and replacing the amorphous carbon structure with a metal structure.
USPTO Backgrounds
USPTO Backgrounds