1. Field of the Invention
The invention relates in general to a fabricating method of a non-volatile memory device, and more particularly to a fabricating method of a split gate non-volatile memory device.
2. Description of the Related Art
The non-volatile memory device is now widely used in electronic devices. For example, it is used for storing structure data, program data, and re-access data. For the programmable nonvolatile memory device, the electrically erasable programmable ROM (EEPROM) is more used and is widely applied in personal computers and other electronic equipment. The conventional EEPROM is a transistor with a floating gate. Even though the EEPROM can be written to, be erased, and store data, it still has the defect of a low accessing rate, whereas the EEPROM with a flash memory device can process at a faster accessing rate nowadays.
FIG. 1 shows a cross-sectional view of a conventional flash memory device. The conventional flash memory mainly comprises a floating gate. Referring to FIG. 1, a tunneling oxide 11 is formed on the p-substrate 10. A floating gate 12 is then formed on the tunneling oxide 11, and a controlling gate 14 is formed on the floating gate 12. A dielectric layer 13 forms between the floating gate 12 and controlling gate 14. On the sides of the floating gate 12 and the controlling gate 14, there are oxide spacers 17 to protect the transistor, and there is a n-type drain region 15 and a source region 16 formed under the surface of the semiconductor substrate 10. The flash memory takes on the nature of Fowler-Nordheim tunneling. For example, when the flash memory stores data, a high voltage, on the order of 12 volts, is applied between the source region 16 and the drain region 15. A high voltage is also applied to the controlling gate 14. Hot electrons generated by the source region 16 will flow from the source region 16 toward the floating gate 12 through the tunneling oxide layer 11 near the drain region 15. By this mechanism, the threshold voltage of the floating gate transistor is raised to store data.
When the data is to be erased, a negative voltage is applied to the controlling gate 14. The electrons trapped in the floating gate 12 will tunnel through the tunneling oxide layer 11 to erase the data, and the floating gate 12 comes back to the uncharged state. In the erasing process, the erasing time is long to ensure the uncharged state of the floating gate 12. If the erasing time takes too long, not only do the electrons trapped in the floating gate 12 reflow, but the electrons belonging to the floating gate 12 are also pulled out. When so many electrons are pulled out, the floating gate 12 will leave many holes, and the transistor becomes a depletion-type transistor. That is to say, even if no voltage source is applied to the controlling gate 14, the transistor is turned on to cause an over-erased effect.
USPTO Backgrounds
USPTO Backgrounds