Early non-volatile memory technology provided for either programming or erasing a floating gate. Because such transistors were selectively in one of two states, programmed or erased, a single bit of data could be programmed. It is known that more than one bit of information can be stored in a single non-volatile cell. Such data storage is normally accomplished by carefully placing a specific amount of charge on a floating gate of a transistor to control its threshold voltage. As is known, at least four distinct states must be provided to store two bits of data, at least eight states for 3 bits and so forth. A sense amplifier is provided to detect the cell current corresponding to those thresholds to decode the bits.
There are two conventional EEPROM architectures for constructing memory arrays of the type that incorporate non-volatile transistor memory cells: NOR and NAND architectures. In an EEPROM NOR type architecture, each transistor memory cell is provided its own select transistor. Accordingly, with the NOR there is no interference from other cells in the memory array during program and read operations. As such, it is easier to design a circuit to program and sense multiple levels of programming using NOR type architecture. Unfortunately, because each storage cell requires its own select transistor, the area per bit size is large and costly.
One prior art reference teaches an apparatus which provides up to eight bits of information (256 analog levels) and a method for programming and detecting this information using a NOR type EEPROM memory cell which uses Fowler-Nordheim tunneling. Programming this type of cell can be done by incremental programming. In other words, a certain amount of charge is stored on the floating gate. The cell current is then verified against a predetermined reference current. If the cell current is not within an acceptable variance from the reference current, a small amount of charge is removed from the floating gate and the cycle is repeated until the cell current and reference currents are substantially equal. Because the threshold voltage for a cell is reduced by this procedure of successively removing charge from the floating gate, the cell current will initially be lower than the reference current. Once the cell current is incrementally above the reference current, the programming operation will cease.
According to another prior art reference, two bits (four analog levels) are stored on a NOR type EPROM memory cell which uses Hot Channel Electron Injection for programming. Because this programming technique is more difficult to control, it becomes increasingly more difficult to store more than four levels on a single cell. Additionally, the prior art teaches that the gates of the storage cells are all applied with a constant gate voltage. The current drawn by the cells is measured to determine which level the cell is programmed. In an embodiment introduced by Intel Corporation of Santa Clara, Calif., the level of the cell is determined by applying a known and constant gate voltage to the cell. The cell is designed to draw current within a specified range depending upon the level of programming of the floating gate. A sense amplifier is coupled to determine whether the current drawn by the accessed cell is over or under the mid-point of the current range. Once that determination is made, one of two additional sense amplifiers is used to determine whether the current drawn by the cell is over or under one-fourth or three-fourths of the range as appropriate, and so on, until the amount of current drawn by the accessed cells is found to fall within a corresponding current range.
A NAND EEPROM type architecture uses several cells in series as each group shares a bit-line contact with an adjacent group. In this way, only two select transistors are needed for the entire group using the NAND architecture. By eliminating all but two select transistors for each group, significantly greater storage cell density is achieved. This is in marked contrast to the NOR architecture where each cell has its own select transistor and shares one contact between two adjacent cells.
A problem which exists in a NAND type architecture is the current that is detected during a read or a program verify operation of a single cell is influenced by the threshold value of all the other cells in the group. After accurately programming a cell, subsequent programming of the other cells within the group could adversely change the current detected and make it very difficult to differentiate its level from adjacent program levels. This level of interference can be tolerated for a single bit (two levels) programming but makes it very difficult to reliably store and detect more levels.
What is needed is a multi-level non-volatile storage architecture that allows the use of NAND type configuration, yet avoids the pitfalls of intragroup interference.
USPTO Backgrounds
USPTO Backgrounds