1. Field of the Invention
The present invention relates to a data processor having a cache buffer, wherein, utilizing the cache buffer, an application program can input/output data to/from a memory device. The data is a series of data which is inputted/outputted as a block; e.g. a sector on a recording medium where the recording medium can be a flexible disk unit, a hard disk unit, an optomagnetic disk unit, or the like.
2. Description of the Related Art
FIG. 1 is a block diagram showing functions of hardware and software for managing the cache buffer in a conventional data processor having a cache buffer. In FIG. 1, reference numeral 10 denotes a block type device such as a hard disk unit mentioned above, 9 is an input/output unit for controlling input/output processing of data to/from the block type device 10, 1 is a cache buffer managing unit composed of a cache buffer 5 and an input/output control unit 4, and 11 is an application program which uses the block type device 10 as a memory device.
The cache buffer managing unit 1 comprises the cache buffer 5 and the input/output control unit 4 as a software. The cache buffer 5, specifically, is provided in a block unit in a memory built in a microcomputer, in order to hold the data corresponding to the block which is a storing unit of data on a recording medium of the block type device 10. The input/output control unit 4 controls the input and output processing of the data through the cache buffer 5 by using the input/output unit 9.
In FIG. 1, arrows of reference numerals in the seventies denote the control signal lines, and arrows in the eighties represent the data transfer routes.
In such prior art, processing flow when an input or output is requested from the application program 11 to the cache buffer managing unit 1 is explained below.
At first, the input processing is described.
When the application program 11 needs to input data from the block type device 10, a data input request is issued and sent to the input/output control unit 4 through the signal line 71. For example, when the application program 11 issues an input request of data for n blocks from block number m of the block type device 10, the input/output control unit 4 at first checks whether there are blocks of the cache buffer 5 corresponding to the requested blocks on the block type device 10 or not. When the corresponding blocks of the cache buffer 5 are present, the input/output control unit 4 transfers the data stored in the cache buffer 5 to the application program 11 of the requesting side through the route of arrows 80 and 81, so that input processing is terminated without using the input/output unit 9.
On the other hand, when there is no block of the cache buffer 5 corresponding to the blocks of the block type device 10 to which an input request is issued from the application program 11, the input/output control unit 4 at first allocates the necessary blocks of the cache buffer 5 to the memory, and then gives the input request to the input/output unit 9 through the signal line 72. In consequence, the input/output unit 9 reads out the data of the blocks to which input request has been issued by giving the input request to the block type device 10 through the signal line 73, from the block type device 10, and stores the data through the routes 83, 82 and 80 into the blocks newly allocated to the cache buffer 5. Thereafter, the data is transferred from the cache buffer 5 into the application program 11 of the requesting side through the routes 80 and 81, thereby terminating the input processing.
When the application program 11 needs to output the data to the block type device 10, a data output request is issued, and is given to the input/output control unit 4 through the signal line 71. For example, when an output request is issued from the application program 11 to the data for n blocks from block number m of the block type device 10, the input/output control unit 4 at first checks whether there are blocks of the cache buffer 5 corresponding to the requested blocks on the block type device 10 or not. When the corresponding block of the cache buffer 5 is present, the input/output control unit 4 transfers the data from the application program 11 at the requesting side to the cache buffer 5 through the routes 81 and 80, so that the output processing is terminated without using the input/output unit 9.
On the other hand, when there is no block of the cache buffer 5 corresponding to the blocks of the block type device 10 to which output request is issued from the application program 11, the input/output control unit 4 at first allocates the necessary blocks of the cache buffer 5 to the memory, and then transfers the data from the application program 11 at the requesting side to the cache buffer 5 through the routes 81 and 80, thereby terminating the output processing.
In the above output processing, the blocks which are necessary in the block type device 10 when output request is issued from the application program 11 is supposed to be newly allocated. Therefore, the processing of reading data from the input/output unit 9 into the block type device 10 of the output destination after the cache buffer 5 is allocated is omitted.
In the data processor having the conventional cache buffer, all input and output processings relating to the block type device has been conducted through the cache buffer as mentioned above. Therefore, when the number of blocks requested from the application program is large, the number of blocks allocated to the cache buffer is also large, and hence exchange of cache buffers occurs very frequently. Such situation may cause to lower the hit rate of the cache buffer, and the effect of the cache buffer installed for the purpose of enhancing the performance of the microcomputer is not exhibited fully. Moreover when the number of blocks exceeding the number of prepared cache buffers is requested, the input or output request to the block type device is divided plural times, and hence it takes a very long time.
In this background, for example, inventions are proposed and disclosed in the Japanese Patent Application Laid-Open No. 4-60730 (1992) and Japanese Patent Application Laid-Open Ko Kai No. 3-196345 (1991). The former discloses the constitution for bypassing the cache buffer in case of input or output of data exceeding the capacity of the cache buffer. The latter discloses the constitution for performing input or output of data only after judging whether the cache buffer is used or not.
In either invention, however, in case of input or output of data by bypassing the cache buffer, an unmatched state may occur, that is, the inputted or outputted data does not coincide with the data stored in the cache buffer.
USPTO Backgrounds
USPTO Backgrounds