1. Field of the Invention
The present invention relates to an electrically erasable programmable read only memory (EEPROM) and, more particularly, to an EEPROM having a memory cell array composed of NAND cells.
2. Description of the Related Art
Recently, NAND-cell type EEPROMs have been proposed as one type of EEPROMs. The memory cell of the EEPROM has an N-channel FET MOS structure in which a floating gate acting as a charge storage layer and a control gate are stacked in that order. The EEPROM is composed of a plurality of memory cells, which are connected in series in such a manner that the source and drain of each cell are shared by adjacent ones one after another and which are treated as a unit connected to a bit line. The drain side of the NAND cell is connected to a bit line via a first select gate, and the source side is connected to a source line via a second select gate. The control gate and the first and second select gates of the memory cell are placed sequentially in the row direction.
The write operation of the NAND-cell EEPROM type is effected as follows. First, an erase operation makes a threshold value of all memory cells in the NAND cell negative. After this, data is written simultaneously into a plurality of memory cells which share the control gate, starting sequentially with the farthest one from the bit line contact. The control gate of the selected memory cell is applied with a high voltage Vpp (up to nearly 20 V), the control gates of the unselected memory cells are applied with a middle voltage vm10 (up to nearly 10 V), and the bit line is applied with a middle voltage Vm8 (up to nearly 8 V) according to the data. At this time, the first select gate is turned on and the second select gate is turned off. When 0 V is supplied to the bit line, the voltage is transferred to the drain of the selected memory cell, which injects electrons into the floating gate. As a result, the threshold value of the selected memory cell goes positive. This state is determined to be "0", for example. When vm8 is supplied to the bit line, electron injection does not take place. Consequently, the threshold value remains unchanged and holds negative. This state is determined to be "1". Since data are written into a plurality of memory cells simultaneously in this way, data circuits are provided for storing the data to be written. The data circuits are also used to temporarily store the read-out data. To shorten the time required to load data, data are not loaded into the data circuits of the memory cells which do not have to be written. Thus, before data loading, write data "1" is set in the data circuits collectively.
The data is read simultaneously from a plurality of memory cells sharing the control gate by setting the control gate of the selected memory cell at 0 V and setting the control gates of the remaining memory cells at a power supply voltage Vcc (e.g., 3 V), and then sensing whether a current flows through the selected memory cell. The read-out data are stored in the data circuits and then outputted.
To operate the NAND-cell type EEPROM from a single power supply, the voltages Vpp, Vm10, and Vm8 used in the write operation are generated by raising the power supply voltage Vcc by means of an internal circuit. If there is any current leak source at the circuit to be boosted, the voltage multiplexer circuit cannot raise an output voltage potential to a desired voltage potential level since it generally has a small current supply capacity. This is true in a case where the defective column is replaced with a redundant column in a redundant circuit. Because data are written simultaneously into a plurality of memory cells sharing the control gate, the current leak source on the bit line of the defective column prevents the voltage vm8 from raising the desired voltage level, causing an erroneous write operation. On the other hand, there is provided following another method. In the data circuits for storing the writing data to be written into a plurality of memory cells, when the data corresponding to bit lines having the current leak source are loaded, writing data "1" is set in the data circuits before data are loaded, and then writing data "0" is reset in the data circuit before the writing data are loaded into the data circuits.
However, these kinds of methods require time to check the bit line with a current leak source during the time from when the write mode is turned on until data are loaded or before the write mode is turned on. Further, since the checking process cannot be effected automatically, it must be done under the control of the CPU. As a result, the control of the NAND-cell type EEPROM is made complex. As described above, conventional NAND-cell type EEPROMs require time to check bit lines having a current leak source during the time from when the write mode is turned on until data are loaded or before the write mode is turned on. These drawbacks have made them difficult to be used.
USPTO Backgrounds
USPTO Backgrounds