Various semiconductor devices are manufactured through a wafer process and a packaging process. A substrate, usually a silicon wafer, is masked, etched, and doped through several process steps, the steps depending on the type of devices being manufactured.
Generally, a method that stacks the wafers before dicing the wafers and thereby performs dicing after stacking (Wafer to Wafer method, hereafter called “W2W method”). The W2W method yields high manufacturing efficiency, but has a disadvantage that, when defect rate in each of the wafers increases, the defect rate rises cumulatively with increasing number of stacked wafers, thereby leading to a fall in product yield and rise in final product cost.
Thus, there is a need to provide a method for manufacturing wafer stacking which may obtain high product yield and reduce product cost. It is also to be appreciated that while three dimension package applications are discloses, there can be numerous different dies attached in a multi-chip package.
USPTO Backgrounds
USPTO Backgrounds