1. Field of the Invention
The present invention relates to an integratable semi-conductor memory cell having two bipolar transistors which are identical with one another and whose collectors are connected in series with respective circuit portions which have a non-linear current characteristic, and in which the circuit portions are connected in common to a first electrical potential and are respectively connected to the base of the opposite transistor, and more particularly to such a circuit in which an emitter of each of the transistors is provided for receiving logic control signals.
2. Description of the Prior Art
Memory cells of the type mentioned above are generally described in the German Published Application No. 17 74 929 and in the German Patent No. 2,204,562. The non-linear circuit portion in the current supply circuit of the collectors of both transistors, in the first case, is a diode having a pn-junction, and in the second case is a diode having a Schottky contact. In each case, the transistors are provided with two emitters, whereby one emitter each of the one transistor is connected to one emitter each of the second transistor and are connected to a second electrical potential, while the unconnected emitters of the transistors are used as inputs for receiving logic control signals.
A further improvement in circuits of the type mentioned above is illustrated in FIG. 1. The improvement relates to a double emitter memory cell having a pn diode load and a resistor connected in parallel with the diode load. The advantage of such arrangements lies in load dissipation losses, particularly in the rest condition of the memory cell, as well as in a good possibility of realization as a monolithically integrated semi-conductor circuit. In a selected state, such a memory cell can consume high currents, so that the recording and reading of data in memories integrated from such memory cells can be accomplished at a very high speed. The embodiment represented in FIG. 1 distinguishes itself additionally by a minimum of quiescent current, a favorable recording pulse width and good packing density.
According to the circuit illustrated in FIG. 1, a connection point A carrying the first electrical potential is connected by way of respective diodes D.sub.1 and D.sub.2, poled in the forward direction, and a series resistor R.sub.S1 and R.sub.S2, respectively, at the collectors of the npn transistors T.sub.1 and T.sub.2. In addition, the collector of each of the two transistors is connected, by way of an additional ohmic resistor R.sub.P1 and R.sub.P2 to the point A. Finally, each collector is connected to the base of the other transistor so that both the transistors are cross-coupled.
Both of the transistors T.sub.1 and T.sub.2 are provided with two emitters. One emitter of each transistor is connected to a like emitter of the other transistor and in common therewith to a second switching terminal B, while the other emitters of the transistors receive logic control signals at the respective inputs L.sub.1 and L.sub.2.
The voltage .DELTA.U between the collectors of the transistors T.sub.1 and T.sub.2 is critical for the electrical performance of such a memory cell. In FIG. 2 the function of the current I.sub.Z flowing by way of both the terminals A and B is illustrated. If the resistors R.sub.S1 and R.sub.S2 have the value zero, the parallel resistors R.sub.P1 and R.sub.P2 a value of infinity, so that the collectors of the transistors T.sub.1 and T.sub.2 are merely connected to the point A by way of both diodes D.sub.1 and D.sub.2, the voltage .DELTA.U is independent of the current I.sub.Z, that is a straight line extending parallel with the abscissa at a distance of less than 0.1 volt. It should be noted in this respect that on the abscissa of the natural logarithm of the current value is plotted, while the ordinate .DELTA.U is linear.
It would be desirable for the voltage .DELTA.U to have values higher than 0.1. This is accomplished by the resistors provided in FIG. 1. However, as can be seen from FIG. 2, the voltage .DELTA.U no longer remains connected purely exponentially with the memory cell current I.sub.Z ; rather, the operating condition for the memory cell depends to a large extent on the operating point set by the resistors R.sub.S and R.sub.P, because the recording pulse width, the scope of parasitic substrate currents and the static freedom from interference depend on the voltage .DELTA.U. Moreover, a switching relation between the rest current and the operating current exceeding beyond the value 100 cannot be set safely without problems.
In the curves for .DELTA.U shown in the diagram according to FIG. 2, in each case the value shown in the diagram and indicated at the curve involved is used for the two parallel resistors R.sub.P1 and R.sub.P2, while the series resistors R.sub.S1 and R.sub.S2 are determined to be 300 ohms, the temperature voltage U.sub.T of the diodes D.sub.1 and D.sub.2 is determined to be 28 millivolts, the saturation current I.sub.o for the individual diode is 0.3.times.10.sup.-15 amps and the static amplification of each of the two transistors T.sub.1 and T.sub.2 is determined to be 20. The curves were derived by computation and verified experimentally.
Bearing in mind that such a memory cell is consolidated in the art with a multiplicity of identical memory cells, integrated monolithically into a memory matrix and since, moreover, for static reasons it is almost impossible that in the manufacture of such a matrix via all points to be subjected to a certain production apparatus, of a semi-conductor disc, identical conditions will prevail everywhere, the behavior of the voltage .DELTA.U between the collectors of both transistors T.sub.1 and T.sub.2 of an apparatus according to FIG. 1 is unfavorable.
If, on the other hand, the use of the resistors R.sub.S1, R.sub.S2, R.sub.P1, R.sub.P2 is waived, so that the power supply of both the transistors T.sub.1 and T.sub.2 is accomplished exclusively by way of the two diodes D.sub.1 and D.sub.2 equipped either as pn diodes or Schottky diodes, in fact the voltage .DELTA.U becomes independent of the setting of the operating point of the memory cell involved. However, the slope of the characteristic curve is too small and thus the voltage .DELTA.U is too low to assure an adequate static and dynamic freedom from interference of the memory cell and thus of the entire memory at the desired high densities of integration.
USPTO Backgrounds
USPTO Backgrounds