Many communication systems include devices that transmit and/or receive signals synchronously, i.e., in accordance with one or more clock signals. In some systems, the one or more clock signals may be generated based on data patterns that correspond to the signals. In other systems, the one or more clock signals may be provided to devices or communicated between devices. For example, an external clock signal may be provided or a clock signal may be communicated over a link that couples a transmitting device and a receiving device.
The devices in these communication systems may include frequency synthesizer circuitry to generate or modify the one or more clock signals. For example, the frequency synthesizer circuitry may select or adjust a phase or a frequency of the one or more clock signals that are provided to the devices. The output clock signals from this frequency synthesizer are then coupled to additional circuitry, such as transmit or receive circuits, in the devices. This approach is referred to as a clock-forwarding architecture.
Unfortunately, many systems and devices that include a clock-forwarding architecture are sensitive to timing drift effects, such as those associated with path-length differences, as well as process, voltage and/or temperature variations. For example, timing drifts may occur at a variety of locations in a respective device, including in the frequency synthesizer (such as in a phase-frequency detector or a charge pump), over signal lines and wires that couple the additional circuitry to the frequency synthesizer (such as clock-path mismatch, which gives rise to clock skew), and/or in the additional circuitry (such as in sample and hold circuits in a receiver). Timing drift may cause timing offset between clock and data. If this timing offset is not corrected, system or device performance (such as a bit-error rate) may be degraded.
In some existing systems and devices, open-loop circuit matching of a path length and/or one or more components are used to reduce or eliminate timing drift. However, this approach is limited by an accuracy of the matching. In more advanced processes, this matching may be difficult to achieve, or it may be realized at a prohibitive power and area penalty.
Closed-loop or continuous time timing drift cancellation techniques often offer better performance than open-loop matching. These approaches may be able to eliminate or significantly reduce timing drift. However, existing closed-loop techniques often incur significant increases in power consumption and overhead (such as significant circuit redundancy in the frequency synthesizer for each transmit or receiver circuit). The existing closed-loop techniques may also need a minimum transition density in the data that is communicated. If this is achieved using coding there may be a reduction in an efficiency of the link. And if a periodic timing calibration technique is used, there will be data interrupts that may not be acceptable in certain applications.
There is a need, therefore, for improved timing drift cancellation circuits and techniques that reduce and/or eliminating timing drift without the aforementioned problems.
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USPTO Backgrounds
USPTO Backgrounds