1. Field of the Invention
The present invention relates to the design of semiconductor devices. More specifically, the present invention relates to the use of a transistor pattern matching algorithm to efficiently partition logic on a semiconductor device, wherein each transistor pattern corresponds to a scaleable physical realization of the transistor pattern referred to herein as a parameterized tile.
2. Description of the Related Art
Creating the physical representation of an integrated circuit in an automated fashion is commonly referred to as layout synthesis. The state of the art includes the following methods:
Transistor Synthesis is the method of mapping each transistor in the design into a physical representation of a transistor and placing them into the design. Typically the physical representation has length, width, and possibly folding parameters. The layout synthesis tool takes a cell schematic as input, and outputs a “symbolic layout” for the cell by converting each circuit element, such as a transistor, capacitor, resistor or diode, into predefined geometric shapes or symbols representing a manufacturing plan for the circuit element. The layout synthesis tool also preserves connectivity between the circuit elements represented as symbols in the layout. In a later stage, the symbolic layout of the cell is compacted into a smaller area than it originally occupied, typically based on manufacturing groundrules defined for the desired semiconductor manufacturing technology. The compaction process is designed to increase the density of electronic circuits to the maximum extent permitted by the manufacturing technology. Designing integrated circuits using transistor synthesis methods can be laborious, time-consuming, and error-prone.
Standard Cell Synthesis is the method of mapping the design into a collection of non-parameterized cells. Each cell in the standard cell collection has an associated mapping function. The design is reduced into a collection of these mapping functions. Typically each standard cell has a set pitch so the cells can be placed in row. This method requires extensive libraries of standard cell designs, and layout designers using a standard cell synthesis method often find that predesigned library cells are either not available or not optimal for certain areas of the design. Accordingly, although automated standard cell synthesis methods are generally less labor-intensive than transistor synthesis methods, a substantial amount of human intervention is often required to achieve an optimized design.
Tile Synthesis is the method of mapping the design into a collection of non-parameterized tiles. The tiles are mapped generally by name. Tile synthesis favors a design that instantiates a limited set of cells like a RAM design. Like standard cell synthesis, tile synthesis is a less laborious automatic layout method than transistor synthesis, but tile synthesis methods do not provide for design flexibility, due to limited tile design choices and fixed device sizes.
An ideal layout methodology would combine the advantages of all of these methods while eliminating the disadvantages. While the transistor synthesis method enables substantial design flexibility, particularly in sizing individual devices, it is labor-intensive and can result in inefficient logic partitioning and routing problems. Standard cell synthesis and tile synthesis are much less laborious and enable more efficient partitioning and inter-cell routing, but design flexibility is sacrificed.
The present invention combines the best aspects of these methods by providing an automatic layout methodology that uses a collection of parameterized tiles. Each tile consists of geometric shapes representing the physical design of a pattern. Some of the coordinates of each tile are variable and are said to be parameterized. Thus a single parameterized tile can support a variety of device widths, device lengths, wire widths, etc.
Each tile has a corresponding network of connected devices. This network is referred to as a pattern. The design is mapped to an ordered list of these patterns. When a pattern match is obtained the matching topology is checked for appropriate parameter range for each device. The goal is to partition the design into an optimum number of patterns. Each device in the design must be covered by one and only one device in a pattern.
USPTO Backgrounds
USPTO Backgrounds