The present invention relates to the modularization of a semiconductor memory embedded as a macrocell in a semiconductor device.
Large-scale integrated (LSI) circuits are often designed by combining standardized units referred to as cells, macrocells, macros, or cores. In recent years, it has become possible to combine dynamic random-access memory macrocells, referred to below as DRAM macros, with processor cores and other data-processing logic circuits on a single semiconductor chip, to create devices that can process large quantities of data without the need for external memory.
A DRAM macro includes one or more arrays of memory cells, together with peripheral circuits such as sense amplifiers, decoders, line drivers, and internal power sources. All of these components are pre-designed as standard modules and stored in a database or library. The circuit designer creates a DRAM macro with a desired memory capacity by combining the necessary number of standard modules, using the stored designs. The design process can be automated by the use of a hardware description language.
A consequence of this design process is that certain standard peripheral modules have to supply the needs of varying numbers of memory cell array modules, depending on the overall size of the DRAM macro. Peripheral modules of this type include word line drivers for main word lines, power-source modules that supply power to sense amplifiers, column drivers that select the sense amplifiers, and charge pumps that generate voltages higher than the power-supply voltage. Since they must be capable of functioning in DRAM macro configurations with the maximum memory capacity, these standard modules are large in size, and are unnecessarily large when used in smaller DRAM macro configurations. Resulting problems include wasted layout space and unnecessary power consumption.
These problems are not unique to DRAM macros, but occur in other types of memory macros as well.
Further information about these problems will be given in the detailed description of the invention. This application also claims priority of Japanese Patent Application No. H11-364210, the disclosure of which is hereby included by reference.
An object of the present invention is to save space in a memory macro.
Another object of the invention is to reduce power consumption in a memory macro.
The invention pertains to a memory macro having a first number of memory cell arrays aligned in a first direction, with associated circuits disposed adjacent the memory cell arrays. The first number varies according to the memory capacity of the memory macro. The invented method of fabricating this memory macro includes the following steps:
(a) selecting a second number according to the first number;
(b) placing the second number of peripheral circuit elements side by side in the first direction, aligned with the memory cell arrays in the first direction; and
(c) electrically interconnecting the peripheral circuit elements, in parallel, to the associated circuits.
The invention provides memory macros, fabricated in this way, in which the associated circuits are sub-word line drivers and the peripheral circuit elements are capacitors; in which the associated circuits are sub-word line drivers and the peripheral circuit elements are unit main word line drivers; in which the associated circuits are sense amplifier arrays and the peripheral circuit elements are transistors supplying power to the sense amplifier arrays; and in which the associated circuits are sense amplifier arrays and the peripheral circuit elements are column line drivers.
The peripheral circuit elements drive the associated circuits, or supply power to the associated circuits. The required amount of power or driving capability depends on the number of memory cell arrays (the first number). The invention saves space and prevents unnecessary power consumption by enabling the second number to chosen so that the requirement is met without being over-fulfilled.
USPTO Backgrounds
USPTO Backgrounds