Integrated circuits are typically fabricated onto and within a monolithic substrate. A typical result is a semiconductor device encompassed into or by a chip/die. Such is usually encapsulated within a solidified liquid encapsulant which is bonded or connected with another substrate, for example to a printed circuit board or encapsulated with a lead frame which is ultimately joined with a printed circuit board or another substrate. Typically, a plurality of integrated circuit chips or die is fabricated onto and from a single larger wafer or substrate. At the conclusion of fabricating the integrated circuit die, the larger substrate is typically cut to form singulated individual integrated circuit chips.
Typical fabrication of an integrated circuit occurs almost entirely relative to one side of a semiconductor substrate, typically referred to as the circuit side or frontside. Yet in many instances, it is the backside of the semiconductor substrate that is conductively and operatively connected with a lead frame or other substrate after dicing into individual chips. A typical manner of providing substrate backside conductive contacts for electrically connecting with the lead frame or other substrate includes the fabrication of through wafer interconnects. Such are conductive paths which typically extend perpendicularly from the circuit side of the substrate to the backside of the substrate.
Bond pads are typically fabricated over an area of the substrate below which no circuitry has been created lower within the substrate. Such might be provided in a single row or column over a central area of the circuit side of the substrate, in multiple rows/columns, around the perimeter of the die area, etc. Regardless, through wafer interconnects are typically first formed by patterning a series of openings of a common shape on the substrate frontside through the bond pads and partially into the substrate material therebelow. Internal walls of the openings down within the substrate are then insulated. The openings are then filled with conductive material which electrically connects with areas of the frontside bond pads.
The backside of the substrate is then typically polished to expose the conductive material formed within the openings, thereby providing a conductive pattern of conductive interconnects which extend form the circuit side of the substrate to its backside in a self-aligned manner to the patterning of such openings through the bond pads which occurred on the circuit side of the substrate.
In most instances, it is desirable to provide a patterned protective dielectric passivation layer over the backside of the substrate and to assure electric isolation between adjacent through wafer interconnects and intervening material of the substrate. However, alignment marks for mask placement/alignment are not typically provided on the backside of the substrate. Further even if such were provided, they would be removed by the above typical processing where the backside is polished to expose the conductive material of the through wafer interconnects.
If patterning of the material on the backside of such a substrate is desired, typical existing methods examine the substrate frontside for the appropriate alignment marks, and then suitable x-y axis substrate positioning/moving is conducted for the desired processing or action to be taken relative to the substrate backside. Such typically requires underside examination of the frontside of the substrate from below. This can be problematic when the substrate frontside is resting upon a surface which must thereby typically be made transparent to enable the typical optical imaging equipment to see the underside of the substrate. Alternately, equipment must be designed to view the alignment marks on and from the substrate frontside in order to align the substrate backside.
Further and regardless, a singulated chip must also be properly aligned relative to a lead frame or other substrate to which the backside of the integrated circuit chip is to be connected. The absence of alignment marks on the backside of the integrated circuit chip can make it difficult to properly align the backside of the chip for desired placement or bonding with another substrate to which the chip backside electrically connects.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.
USPTO Backgrounds
USPTO Backgrounds