1. Field
Embodiments of the present invention generally relate to methods of manufacturing a vertical type semiconductor device, and more particularly to methods of manufacturing a vertical type semiconductor device with stair-like structures using interferometric endpoint detection.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer, is commonly used in forming structures, such as gate structure, shallow trench isolation (STI), bite lines and the like, on a substrate by etching process. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portion of the photoresist, thereby creating openings in the remaining photoresist.
In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
When forming stair-like structures in a film stack disposed on a substrate, an etching process along with a photoresist trimming process are repeatedly performed to etch the film stack with sequentially trimmed photoresist layer as etching masks. In an exemplary embodiment depicted in FIG. 1A, a trimmed photoresist layer (not shown) may serve as an etching mask layer to transfer structures onto a film stack 100 disposed on a substrate 104 to form stair-like structures 110 on the substrate 104. The film stack 100 typically includes alternating layers of layers 102a, 102b (shown as 102a1, 102b1, 102a2, 102b2, . . . , 102n1, 102n2), either conductive layers or insulating layers. During etching, the photoresist layer is sequentially trimmed to different dimensions while serving as an etch mask to form stair-like structures 110 having different widths.
During manufacturing of the stair-like structures 110 on the substrate 104, each stair formed in the stair-like structures 110 has its intended width to allow channels 120 to be formed thereon. In the situations wherein inaccurate control of the photoresist trimming rate or film stack etching rate has occurred, widths of each of the stair may not be formed as precisely as intended during manufacturing, resulting in asymmetric stair structure that may result in the in ability to properly locate the channels 120 on an intended location on the stair structure.
In the example depicted in FIG. 1B showing a magnified view of a portion of the stair-like structures 110 circled in FIG. 1A, the widths 150, 152 of each stair structure 120 are formed wider or narrower in different cases, as expected due to the inaccurate process control, thus resulting in the channels 120 (shown as 120a, 120b) not being properly located on each designated surface 164 or 160 of each stairs 110 (shown as 110a, 110b), resulting in a location shift in the channels 120 formed on the stair structure 110. For example, the first channel 120a is not entirely located on the designated surface 164, but rather partly located on the nearby undesignated surface 160. Similarly, a portion of the second channel 120b is formed on the undesignated surface 162, rather than the designated surface 160, resulting in channel location shift, eventually leading to device failure.
Thus, there is a need for improved methods and apparatus for forming symmetric stair-like structures with accurate profiles and dimension control for three dimensional (3D) stacking of semiconductor chips.
USPTO Backgrounds
USPTO Backgrounds