1. Field of the Invention
The present invention relates to the technical of dual-port static random access memory (SRAM) and, more particularly, to a ten-transistor (10T) dual-port SRAM with shared bit-line architecture.
2. Description of Related Art
In recent years, the IC design demands more transmission bandwidths, such that the memory requirement is evolved from a single-port SRAM into a dual-port SRAM. Because of having advanced feature of parallel operation for high speed communication and video applications which the single-port SRAM does not have, the dual-port SRAM can perform a parallel read or write operation on different ports, but it introduces read/write disturb issues in the same row access.
FIGS. 1(A)-1(D) schematically illustrate an access of a conventional dual-port SRAM. FIG. 1(A) shows an access to an A-port and a B-port at different rows and different columns. FIG. 1(B) shows an access to the A-port and the B-port at different rows and the same column. As shown in FIGS. 1(A) and 1(B), both of the access modes activate only single port on one row. Namely, when an activated memory cell of a word line WL is operated as a single-port access, no access conflict occurs to the access modes of FIGS. 1(A) and 1(B).
FIG. 1(C) shows an access to the A-port and the B-port at the same row and different columns. FIG. 1(D) shows an access to the A-port and the B-port at the same row and the same column. In this case, there is an access conflict on the access modes of FIGS. 1(C) and 1(D).
FIG. 1(C) shows that, when the memory cell 110 on the left of row 1 executes a read/write operation at the A-port, the A-port of the memory cell 120 becomes a dummy read, with the bit lines BL pre-charged to high. When the B-port attempts to write a low voltage (0) in the memory cell 120 through the bit line, the internal storage node of the memory cell 120 is difficult to change its storage state, which is referred to as a write data disturb.
FIG. 2 shows a schematic diagram of a conventional write data disturb. For an access to the memory cells 110, 120, all the bit lines are pre-charged to a high voltage (1). When the A-port attempts to execute a read/write operation on the left, i.e., the memory cell 110, the word line WL, i.e., AWL1, is first activated to the high voltage (1). In this case, when the B-port attempts to write a low voltage (0) in the memory cell 120 through the bit line BBL2, the word line WL, i.e., BWL1, is activated to a high voltage (H), and the bit line BBL2 is low (0). Since the word lines AWL1 and BWL1 are high (1), the transistors N1 and N2 are all turned on, so as to bring the bit line ABL2 to high (1) and the bit line BBL2 to low (0). Thus, the bit line ABL2 is pulled up, so that the internal storage node X of the memory cell 120 is difficult to change its storage state.
FIG. 3 shows a schematic diagram of a conventional read data disturb. For an access to the memory cells 110, 120, all the bit lines are pre-charged to a high voltage (1). When the A-port attempts to execute a read/write operation on the left, i.e., the memory cell 110, the word line WL, i.e., AWL1, is first activated to the high voltage (1), and the transistor N1 is turned on. Since the word line ABL2 is pre-charged to high (1), the internal storage node X is slightly pulled up to a voltage, denoted as 0+, by the bit line ABL2 as it stores a data with the low voltage (0), so that a read data disturb occurs. Namely, when the voltage 0+ of the internal storage node X of the memory cell 120 is read through the bit line BBL2 and amplified by a sensing amplifier, it can easily cause an erroneous read data.
To overcome the write data disturb and the read data disturb, in Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, and Hirofumi Shinohara, “Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, March 2009, pp. 977-986, it uses a row-address comparator to detect whether the same row is accessed and, if yes, the B-port row decoder is turned off to avoid the conflict of concurrently accessing the A-port and the B-port. However, such a way reduces the entire access efficiency and has to add the column-address comparator and peripherals, resulting in increased cost.
Accordingly it is desirable to provide an improved dual-port SRAM to mitigate and/or obviate the aforementioned problems.
USPTO Backgrounds
USPTO Backgrounds