As integrated circuit complexity increases, the dimensions of the devices within the circuit necessarily decrease. In fact, integrated circuit technology is rapidly approaching submicron feature size. Although one generally first thinks of reducing the source, gate and drain dimensions of field effect transistors, another device element whose dimension must also be shrunk is the dielectric layer commonly used, e.g., for a gate dielectric. Thicknesses less than several tens of nms are now desirable for many of these device elements. However, as the gate dielectric becomes thinner, the importance of dielectric quality, including both low defect density (D.sub.o) and dielectric processing sensitivity, becomes greater with respect to device performance. Low defect density and processing sensitivity are, of course, also important in other integrated circuit applications.
In fact, in VLSI circuits, the quality of dielectric layers ultimately becomes a dominant factor in determining device performance. Consider field effect transistors (FETs) which use a voltage applied to a gate electrode to control current flow in a channel between source and drain regions. The electrode includes a capacitor and a typical dielectric is silicon oxide. If the source and drain regions have n-type conductivity, a positive gate voltage, V.sub.g, induces negative charges in the channel. Current flows in the channel when the gate voltage exceeds the threshold voltage.
In an ideal FET, the gate voltage may be arbitrarily large with no current flow through and charge storage in the dielectric. In practice, however, it is impossible to eliminate trapped charges in the dielectric which cause operating instabilities due to charge induced shifts in the threshold voltage. This shift may be better understood from the following considerations. The voltage shift due to the trapped charges is proportional to Q.sub.t /C, where Q.sub.t is the trapped charge and C is the capacitance. Although the voltage shift decreases as the oxide thickness decreases, the compensation for trapped charges need not be reduced in the scalling to smaller dimensions. In fact, charge trapping, and defect induced dielectric breakdown set the scaling limits for thin oxides. It is thus essential that the number of defects in the dielectric be minimized for best device performance. However, Yamabe et al, Proceedings of the 21st Reliability Physics Symposium, pp. 184-190, Phoenix, Ariz., 1983, reported that the defect density, in particular, pinholes, increased with decreasing silicon oxide thickness once the oxide was less than 20 nm thick.
The silicon oxide, SiO.sub.2, is the most commonly used dielectric material, at least for Si integrated circuits, and may be formed either by thermal growth or material deposition. Thermal oxidation of silicon involves a reaction of the oxide/silicon interface that is driven by inward movement of the oxidizing species. Thus, the silicon surface is continually renewed and the bulk SiO.sub.2 is maintained with sufficient oxygen to remove the majority of the bulk and surface defects. Surface passivation reduces the number of states within the bandgap by lowering the number of dangling bonds because a stable SiO.sub.2 film is formed.
Although deposited films can be grown more quickly than can thermal oxides, the dielectric qualities of deposited films are generally inferior to those of thermally grown oxide films. Thus, deposited oxides have not been used as dielectrics because they typically have a high D.sub.o, greater than 5 cm.sup.-2 ; low breakdown fields, F.sub.bd approximately 3 MV/cm; and high interface state densities, Q.sub.it greater than 10.sup.12 cm.sup.-2 eV.sup.-1. However, a low temperature plasma enhanced chemical vapor deposition process was reported as yielding a moderately high quality SiO.sub.2 layer. See, Journal of Applied Physics, 60, pp. 3136-3145, Nov. 1, 1986. The interface trap density was reduced by a fast deposition anneal. Other deposition processes generally have an annealing step to both densify the oxide and improve its electrical integrity, but the results have not been as good as is desired if the oxide will be used as a gate dielectric.
Attempts have been made to avoid some of the problems resulting from the high defect density in deposited oxides by fabricating a dual dielectric such as that formed by Si.sub.3 N.sub.4 /SiO.sub.2. For example, Watanabe et al., IEEE International Reliability Physics Symposium, pp. 18-23, 1985, fabricated a SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 structure with an oxide thickness between 10 nm and 20 nm and a D.sub.o of 0.5 cm.sup.-2 together with a F.sub.bd greater than 9 MV/cm. The bottom oxide layer was thermally grown and the Si.sub.3 N.sub.4 layer was then deposited and partially oxidized. While the dual dielectric structure has a low leakage current and a high breakdown voltage, the Si.sub.3 N.sub.4 /SiO.sub.2 interface has a high density of states that act as traps. These states cannot be removed by annealing because the nitride is impervious to the oxidizing species. Moreover, the interface states can be populated or depopulated by varying the electrode bias. They thus cause instabilities in device operation because of charge induced shifts in the threshold voltage and a reduction in the channel conductance. Therefore, this dual dielectric is not ideally suited for use as a gate dielectric as well as for other uses.
USPTO Backgrounds
USPTO Backgrounds