1. Field of the Invention
The present invention relates generally to a field transistor monitoring pattern for shallow trench isolation (STI) defects in semiconductor devices and, more particularly, to a field transistor pattern that is capable of monitoring dimple defects potentially produced in an STI area.
2. Description of the Related Art
Isolation structures, such as LOCOS and STI, are frequently used for electrically isolating active areas in semiconductor devices. STI is a relatively new process that may be implemented on sub-0.18-micron technologies as an alternative to LOCOS. STI eliminates certain problems traditionally associated with LOCOS, while enabling formation of active areas with higher density. Additionally, the flatness or planarity of the resulting wafer enables more precise pattern definition for subsequent layers.
The typical STI process starts from forming, in sequence, a pad oxide layer and a pad nitride layer on a silicon substrate. Both pad layers are patterned to expose substrate portions predetermined as isolation (or field) areas. Exposed portions of the silicon substrate are etched to form a trench therein. Oxide material is deposited sufficient to fill the trench and then polished for planarization. Finally, the remaining pad layers are completely removed, and the remaining trench oxide layer defines an STI area.
In order to obtain a better trench-filling property, a high-density plasma chemical vapor deposition (HDP-CVD) is widely used in the art. However, in case of a narrow trench, unfavorable voids or seams may often occur in the trench oxide layer during a trench-filling process. FIG. 1 shows, in a cross-sectional view, the voids (V) in the trench oxide layer 20. In FIG. 1, reference numerals 10, 11 and 12 represent the silicon substrate, the pad oxide layer, and the pad nitride layer, respectively.
Unfortunately, after polishing the trench oxide layer 20, such a void or seam may invite a waterdrop-like dimple filled with polysilicon when a polysilicon layer is deposited over the STI area in a subsequent process. FIGS. 2 and 3 respectively show, in a cross-sectional view and a plan view, dimple images obtained by scanning electron microscope (SEM). In FIGS. 2 and 3, reference numerals 30 and 22 represent the polysilicon layer and the dimple, respectively. Furthermore, reference characters A and F indicate an active area and a field (oxide) area, respectively. The dimple filled with polysilicon may often cause leakage current between adjacent gate lines that may be formed from the polysilicon layer, resulting in poor isolation properties of semiconductor devices.
A field transistor monitoring pattern has been conventionally used to measure field oxide isolation properties. FIG. 4 shows, in a plan view, a conventional field transistor monitoring pattern.
Referring to FIG. 4, the field transistor monitoring pattern includes a source region 1a and a drain region 1b, which are formed in the silicon substrate and which are spaced apart from each other by the field oxide area F. The monitoring pattern further includes a gate pattern 1c formed on the silicon substrate. The gate pattern 1c has a plurality of gate branches Gb that cross over and extend at right angles to the source region 1a, the drain region 1b, and the field oxide area F.
The above-discussed monitoring pattern is used for measuring the isolation property of the field oxide area F. Specifically, by applying a voltage to the gate pattern 1c, it is possible to check if leakage current exists or not between the source region 1a and the drain region 1b. 
However, the conventional monitoring pattern is generally used for measuring electrical isolation between the active areas separated by the field oxide area F, and is not believed to be capable of in-line monitoring the aforementioned dimple defects in the STI area. That is, it is hard to measure leakage current that may arise between polysilicon gate patterns due to the dimples in the STI area using the conventional monitoring pattern. Thus, there is a need for a solution to check whether or not a dimple defect exists in the STI area.
USPTO Backgrounds
USPTO Backgrounds