The present invention relates to a non-volatile semiconductor memory device in which redundant cells are provided in a regular cell array in which memory cells are disposed.
As an example of a non-volatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) non-volatile semiconductor memory device is known. In the MONOS non-volatile semiconductor memory device, a gate insulating layer between a channel and a gate is formed by stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charges are trapped in the silicon nitride film.
The MONOS non-volatile semiconductor memory device is disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123. This literature discloses a MONOS flash memory cell including two non-volatile memory cells (MONOS memory cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites.
A regular cell array is formed by arranging a plurality of MONOS flash memory cells having such a structure in a row direction and a column direction.
Redundant cells are provided to the regular cell array. When a defective memory cell is found, the redundant cell is used in place of the defective cell.
Taking a memory device in which 16 bits of data are read at the same time as an example, 16 divided memory blocks are provided corresponding to 16 input/output terminals I/O0 to I/O15.
Conventionally, the redundant cells are provided to each of the 16 memory blocks. For example, one redundant memory cell column is provided for a plurality of regular memory cell columns in each memory block. When a defect occurs in one of the memory cells in one regular memory cell column, the redundant memory cell column is used in place of this regular memory cell column.
In such a conventional structure, the number of redundant memory cell columns is increased as the number of consimultaneously accessed bits is increased. This is because the redundant memory cell columns are disposed in each of the memory blocks provided corresponding to the number of simultaneously accessed bits.
Moreover, it is necessary to provide a switch for switching from the regular memory cell column including the defective cell to the redundant memory cell column on the side of the input stage of a sense amplifier. The presence of the switch causes a signal delay to occur, whereby the access time is increased.
USPTO Backgrounds
USPTO Backgrounds