1. Field of the Invention
The present invention relates to an improved salicide process useful in the manufacture of integrated circuits and other electronic devices.
2. Background of the Related Art
One process for constructing integrated circuits uses self-aligned silicide (salicide) technology to form contacts for metal oxide semiconductors (MOS). A conventional salicide process involves the steps of depositing a metal film over a MOS structure under processing conditions which result in the reaction of the metal with exposed silicon areas of a source/drain region and of a polysilicon gate to form silicide contacts.
FIGS. 1A-H are schematic cross-sectional views of a substrate illustrating one conventional salicide process. In such a process, as shown in FIG. 1A, a field oxide layer 10 is deposited on a substrate 12. Then, as shown in FIG. 1B, the field oxide layer 10 is patterned and etched and a gate oxide layer 14 is formed on the substrate 12. Then, as shown in FIG. 1C, a polysilicon layer 16 is formed on the gate oxide layer 14. The polysilicon layer 16 and the gate oxide layer 14 are patterned to form a gate 18. A lightly doping process is performed and the gate 18 acts as a mask to form a lightly doped region 20. Then, as shown in FIG. 1D, a dielectric layer 22, such as silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), is deposited over the gate 18. Then, as shown in FIG. 1E, the dielectric layer 22 is anisotropically etched to form insulating sidewall spacers 24 flanking the gate 18 and leaving the exposed source/drain regions 26. Ion implantation is performed using spacers 24 as a mask to more heavily dope the source/drain regions 26. Then, as shown in FIG. 1F, a reactive metal 28, such as cobalt (Co) or titanium (Ti), is deposited on the structure by chemical vapor deposition or physical vapor deposition. A first anneal causes the metal 28 to react primarily with the exposed silicon regions to form a metal silicide 30 that exists initially as a high resistivity phase silicide. In the reaction of the metal 28 with the exposed silicon regions, metal diffuses into the exposed silicon regions and silicon diffuses to the metal layer 28. Then, as shown in FIG. 1G, the unreacted metal is etched away leaving the metal silicide 30. A second anneal forms the desired low resistivity phase of the silicide 30. Then, as shown in FIG. 1H, after deposition of a passivation layer 32, opening of the contacts 34, and metallization of the contacts 34, the final structure of the salicide process is formed.
However, as shown in FIG. 2, which is a schematic cross-sectional view of a silicide formation over a polysilicon gate, a problem with the salicide process is lateral formation of the silicide on the sides of the gate structure. If a continuous layer of silicide 30 is formed between the polysilicon gate 16 and the source/drain regions 26, a short can occur which can render the device useless. The spacers 24 are formed to prevent silicide from forming on the edge of the polysilicon gate 16. The spacers 24 are made of materials which do not react with the metal 28 deposited during the silicide process and thus, provide electrical isolation of the polysilicon gate 16 from the source/drain regions 26. However, because of diffusion 40 of silicon atoms from the polysilicon gate 16 and the source/drain regions 26, a silicide layer 30 can be formed over the spacers 24 and can bridge the separation of the polysilicon gate 16 and the source/drain regions 26. Silicide formation easily bridges the spacers 24 since spacers are typically only 2000 to 3000 Angstroms wide. The problem of silicide formation occurs more readily as the length of the polysilicon gate shrinks with each process node.
FIG. 3 is a schematic cross-sectional view of a substrate showing a low temperature deposition of a metal 28 over the polysilicon gate 16 and the source/drain regions 26 in a conventional salicide process. The metal 28, such as cobalt (Co) or titanium (Ti), is deposited over the polysilicon gate 16 and source/drain regions 26 by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Generally, during deposition of the metal, the substrate is maintained at a low temperature (i.e. at about 100xc2x0 C.) to prevent silicide formation during the deposition step and to prevent greater material coverage of the spacers 24 through the increased surface mobility of the metal 28. Material coverage of the spacers 24 increases the likelihood that silicide will form over the spacers 24 during the first annealing step. As a consequence, physical vapor deposition of the metal is preferred because chemical vapor deposition generally provides improved material coverage of the spacers 24 and, in addition, is generally more expensive than physical vapor deposition. However, metals sputtered from a PVD source, with the material flux from the sputtering source following a cosine type distribution (J=Ao Cosxcfx86 Cos xcex8), still provides the undesirable effect of having good material coverage over the spacer 24. Thus, deposition of metal 28 at low temperatures still provides a continuous layer of metal 28 over the spacers 24. As a consequence, the formation of a continuous layer of metal over the spacers 24 increases the likelihood of the formation of a continuous layer of silicide forming over the spacers 24 during the first annealing step.
Therefore, there is a need for an improved salicide gate and a process of making an improved salicide gate which reduces the likelihood of lateral silicide formation.
The present invention generally relates to an improved salicide gate and process of making an improved salicide gate. One embodiment of the process comprises forming a gate structure on a substrate; forming spacers by the sidewalls of the gate; and depositing a relatively thin metal film, such as cobalt or titanium, over the gate at temperatures of about 350xc2x0 C. or higher. In one aspect of the invention, the metal film agglomerates and forms a discontinuous film over the dielectric spacers. Thus, lateral silicidation over the spacers is prevented because silicon cannot diffuse through the discontinuous metal film layer over the spacers.
USPTO Backgrounds
USPTO Backgrounds