A first-in first-out in a conventional memory refers to a scheme for storing and retrieving data, wherein data primarily stored to the memory are primarily retrieved therefrom.
Hereinafter, a prior art first-in first-out memory circuit is described with reference to accompanying drawings.
FIG. 1 shows a block diagram for illustrating the prior art first-in first-out memory circuit. FIG. 2 illustrates an input/output state of the prior art first-in first-out memory circuit.
As illustrated in FIG. 1, the first-in first-out memory circuit includes a memory 60 of n-bit×m-word, a memory controller 20 for controlling a first-in first-out operation of the memory 60, a read and a write pointer 30 and 40 for designating read and write positions and a flag generator 50.
As illustrated in FIG. 2, when a write signal WR is inputted, the memory controller 20 synchronizes at rising edges of a clock signal Clk to store input data DI0-DIn-1 in the memory 60. Further, when a read signal RD is inputted, the memory controller 20 synchronizes at rising edges thereof to sequentially output the stored data.
In other words, when the write signal WR is inputted, the memory controller 20 synchronizes at the rising edges of the clock signal to sequentially record 1st, 2nd, 3rd, . . . , nth input data (DI0-DIn-1) in the memory 60. Meanwhile, when the read signal RD is inputted, the memory controller 20 synchronizes at the rising edges thereof to sequentially output the data inputted into the memory 60.
Since the first-in first-out memory circuit has an inner memory of which a width is constructed to be fixed to be a bit width, it is difficult to extend the bit width of input/output data. Further, an operational speed of the first-in first-out memory circuit is limited depending on that of the inner memory, so that the speed is hardly improvable.
As a semiconductor manufacturing technology develops, a size of a transistor becomes smaller. Accordingly, an operational speed of a circuit becomes faster to thereby improve a whole operational speed of the semiconductor. However, the whole operational speed of the semiconductor circuit is limited by the memory speed.
Especially, a memory used in an ASIC circuit employing a standard cell library is manufactured by using a memory compiler. Therefore, a speed of the manufactured memory is much slower than an operational speed of a logic circuit library of a same process. In case a first-in first-out memory used in a system to be designed is required to operate faster than the manufactured memory, a speed of the memory used in the conventional ASIC circuit should be raised by improving a design process, so that design costs of the circuit are increased.
To that end, a plurality of prior arts has been suggested. A first-in first-out memory circuit disclosed in the Korean Patent No. 10-0223626 issued in Jul. 10, 1999 is described as follows.
The first-in first-out memory circuit (DRAMs), which is able to double a bit width, has two memories, a control logic unit, a read and a write pointer, a data distribution unit and a data combination unit. The two memories have the bit width of a byte unit. The control logic unit controls to primarily perform a read/write operation in one memory and then perform a read/write operation in the other memory after the primary memory is used, wherein the two memories correspond to a byte mode and a word mode as well. The read and the write pointer correspond to the byte and the word mode and thus designate addresses to each memory. The data distribution unit and the data combination unit read and write input data in a form corresponding to each mode, respectively.
The data width of the memory in the first-in first-out memory circuit may extend, but a first-in first-out speed on a given process is still limited to an operational speed of an inner memory.
A first-in first-out memory disclosed in Japanese Patent Laid-Open Publication No. 6-52677 is described as follows.
The Japanese Patent provides a method for improving a whole speed of a first-in first-out memory and hardware therefor. Specifically, a high speed of the memory is realized by reducing time intervals of a read signal. The patent uses two shift registers, i.e., an indicator shift register (ISR) and a data shift register (DSR), having a bit width of 8-bit as an inner memory, instead of RAM, and includes an input conversion circuit, an output conversion circuit, an input conversion timing generator and an output conversion timing generator. The first-in first-out memory stores input data into the two shift registers in rotation by a control of the input conversion circuit and outputs the stored data therefrom in rotation by a control of the output conversion circuit.
The first-in first-out memory uses the two shift registers instead of the RAM in order to improve a speed rather than to extend the bit width. However, when the shift registers are used as a storage circuit of data, a design of the memory circuit becomes complicated. Further, a size of the circuit becomes large, so that it is difficult to realize a high capacity circuit of a small size.
While a first-in first-out memory using the RAM can perform a queue operation, a first-in first-out memory having the shift registers cannot perform such queue operation. Besides, primarily inputted data have a delay time corresponding to a depth of the shift registers. As a result, an additional circuit is required to solve the delay time and realize the queue operation.
A sequential memory disclosed in U.S. Pat. No. 5,255,242 uses a plurality of interleaved memory cells to improve an input/output speed of data.
The sequential memory includes two memories having N number of successive storage memory cells of a single bit width, a data access control circuit and an output buffer circuit. The sequential memory generates signals for performing a read/write of data on the memory cells in a predetermined order and at a high speed. Further, the sequential memory controls the output buffer circuit to thereby realize a read/write sequential memory operation at a high speed.
The sequential memory as an inner data storage device uses specialized memory cells and N number of independent memory cell blocks having a single bit width. Therefore, if a plurality of data bit widths are realized, a first-in first-out circuit becomes complicated.
USPTO Backgrounds
USPTO Backgrounds