The present disclosure relates in general to a computer system, and more particularly to an apparatus and method for reducing the amount of time to execute a POST routine.
As technology advances, the number of devices coupled to a computer system continues to increase. With the addition of more devices, the delay before an operating system loads onto the computer system also increases. During initialization of the computer system, a basic input/output system (BIOS) executes a power-on self-test (POST) routine that scans for devices coupled to a local bus associated with the computer system. The POST routine obtains system information about the devices coupled to the computer system and stores the information in a memory associated with the computer system. In a conventional computer system, when a subsequent POST routine is executed, such as with a warm or cold boot, the BIOS enumerates the devices on the local bus and compares the newly acquired system information with the system information stored in memory. This comparison helps reduce the time for resource conflict detection and resolution of the devices in the computer system, thus reducing POST time. However, the difficulty remains that the BIOS must scan the buses for the devices and enumerate the devices on the bus during each boot in order to obtain the current hardware configuration information.
Therefore, a need has arisen for a method and apparatus which reduces the amount of time to execute a power-on self-test (POST) routine.
A further need exists for a method and apparatus which detects a hardware configuration change when the computer system is powered down.
A further need exists for a method and apparatus which detects a change in hardware configuration while the computer system is running.
In accordance with the teachings of the present disclosure, a method and apparatus for reducing the amount of time to execute a POST routine is provided that substantially reduces disadvantages and problems associated with previously developed methods and apparatus for reducing the amount of time to execute a POST routine. Detection of changes in the configuration of devices associated with the computer system allows elimination of a POST scan for devices when no change in hardware configuration is detected.
More specifically, a detection circuit communicates with a card slot via a local bus. The card slot communicatively couples a device to the local bus. The detection circuit generates a status bit that indicates whether a change in hardware configuration occurred after completion of a first boot sequence. During a second boot sequence, a processor reads the status bit to determine whether the computer system was reconfigured since the completion of the first boot sequence. If the status bit indicates that no devices were added to or removed from the computer system, the scan for devices coupled to the local bus is eliminated and the second boot sequence is completed by configuring the computer system with system information stored in a storage medium associated with the computer system.
In one embodiment, a computer system includes a device that interfaces with a local bus through a card slot. The card slot communicates via a local bus with a detection circuit that generates a status bit indicating whether the configuration of devices for the computer system changed after completion of a first boot sequence. A processor communicates with the card slot and the detection circuit via the local bus. During a second boot sequence, a scan for the devices coupled to the local bus is eliminated if the status bit indicates that the computer system device configuration remained the same after completion of the first boot sequence.
In accordance with another embodiment, the status bit has a first logic state if the computer system device configuration remains the same after completion of the first boot sequence and a second logic state if the device was added to or removed from the computer system after completion of the first boot sequence. If the status bit has the first logic state, the second boot sequence accesses first system information stored in a storage medium associated with the computer system and configures the computer system with the first system information. If the status bit has the second logic state, the second boot sequence scans the local bus for the device to obtain second system information and configures the computer system with the second system information.
In accordance with a further embodiment, the detection circuit includes a latch that stores a data signal communicated from the card slot during the first boot sequence. A comparator generates the status bit by comparing the stored data signal with a current data signal communicated by the card slot after completion of the first boot sequence.
Important technical advantages provided by certain embodiments of the present disclosure include a computer system that decreases the amount of time to run a boot sequence. A detection circuit generates a status bit that indicates if the hardware configuration changed after completion of a first boot sequence. If the detection circuit indicates that the hardware configuration did not change, a second boot sequence eliminates a scan of a local bus for a device and configures the computer system with system information stored in a storage medium associated with the computer system that was obtained during the first boot sequence. Thus, by eliminating the scan of the local bus, the amount of time to execute the second boot sequence is reduced.
Another important technical advantage provided by certain embodiments of the present disclosure includes a computer system that detects a change in hardware configuration when the computer system is powered down. The detection circuit and its corresponding connections to the card slots are connected to a battery or a similar source of auxiliary power. When the computer system is turned off, the battery provides power to the card slots and the detection circuit, allowing the detection circuit to either maintain or change the state of the status bit based on the hardware configuration. Therefore, the accuracy of the configuration information is maintained even if power is not applied to the computer system.
A further important technical advantage provided by certain embodiments of the present disclosure includes a computer system that detects a change in hardware configuration when the computer system is running. A computer system supporting hot plugging allows a device, such as a hot-pluggable device, to be added to the computer system while the computer system is operational. When the device is added, the computer system automatically configures the device so that it can be used without powering down the system. On a subsequent reboot, the computer system provided by the present disclosure detects the change in hardware configuration via the detection circuitry and performs a complete scan of local buses to obtain new system information. The new system information is then used to properly reconfigure the computer system.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
USPTO Backgrounds
USPTO Backgrounds