Complementary metal-oxide semiconductor (CMOS) devices are being scaled to improve performance. As supply and transistor threshold voltages are decreased, CMOS circuits exhibit greater sub-threshold leakage in their off-states. In high-performance circuits, a significant portion of total microprocessor power dissipation may be contributed by leakage power alone. In all designs, and particularly for low power designs, it is desirable to control and reduce the total leakage power.
Additionally, as the operating frequency of high-performance circuits increases, it is becoming more difficult to test the circuits to ensure correct functionality while maintaining high reliability. Advances in testing equipment have historically lagged behind advancements in semiconductor manufacturing technology. Thus, as clock speeds increase, the demands of testing high-performance circuits often surpasses the capabilities of conventional testing equipment. Thus, there is a need for test strategies that will allow slow speed testing. Additionally, the use of lower speed, less expensive testing equipment may reduce testing costs of high-speed circuits.
Finally, burn-in is a technique for stressing microprocessors at elevated temperatures and high voltage to ensure long-term reliability. By using burn-in to test devices beyond normal operating limitations, it is possible to reduce early device failures.
USPTO Backgrounds
USPTO Backgrounds