The invention presented in this document refers to field-effect transistors (FETs) in a complementary coupling with transistor emitters connected together. The purpose of the protective circuit is to provide simultaneous protection of the transistors against overvoltage and overcurrent. A prerequisite for the invention is the high input impedance of FETs.
A common method in present techniques is to have a zener diode connected between gate and drain. In this way, the transistor is gated to higher current when the voltage across the transistor reaches too high a value, thus counteracting the increase. However, this solution is practicable only in circuits with limited current capacity, because otherwise the transistor would be destroyed as a result of the power loss.
USPTO Backgrounds
USPTO Backgrounds