The present invention is directed toward forming a series of nanocrystalline silicon quantum dots within a thin oxide layer, and, more particularly, to a process for forming the nanocrystalline quantum dots using a lower processing temperature than in previous processes.
Advanced electronics and opto-electronic devices can be fabricated using carrier confinement and Coulomb blockage effects of a layer of nanometer-sized Silicon crystals, commonly referred to as Si quantum dots.
References in the area of Si quantum dots include Nanotechnology, Gregory Timp, Editor, Springer-Verlag, New York (1999) (and references contained within); as well as A Silicon nanocrystals Based Memory, S. Tiwari et al., Appl. Phys. Lett. 68, 1377 (1996); The Integration of Nanoscale Porous Silicon Light Emitters: Materials Science, Properties and Integration with Electronic Circuitry, P. M. Fauchet, Journal of Luminescence 80, 53 (1999); and Room-Temperature Single-Electron Memory, K. Yano et al., IEEE Trans. on Electronic Devices ED-41, 1628 (1994).
One area of electronics using Si quantum dots to a great success is the formation of non-volatile memory devices. In such devices, a layer of Si quantum dots within a thin dielectric layer, such as a gate oxide, is used in place of the more typical structure of an entire polysilicon layer (floating gate) formed within a thicker oxide. Examples of non-volatile memories formed by nanocrystalline silicon include U.S. Pat. Nos. 5,852,306 and 5,959,896, the teachings of which are incorporated herein in their entirety.
Additionally, light emitting Silicon devices are being produced with a layer of Si nanocrystals that are embedded within a Silicon Dioxide layer.
Forming the Si nanocrystals can be achieved by a variety of techniques, such as plasma-enhanced vapor deposition, aerosol techniques, or Si implantation, for example.
Several strict requirements must be met for a successful use of Si quantum dots in most applications. First, it is necessary that a localized layer of small (1-3 nanometer in diameter) Si nanocrystals that have a very uniform size distribution be formed within a very thin (10-40 nm) layer of Silicon Dioxide (SiO2) that has excellent electronic properties. Second, the density of defect states at the interface between the Si nanocrystals and the SiO2 must be minimal. Finally, the thermal temperature of the processing or annealing step should be as low as possible.
This last requirement, that of a low processing temperature, can be crucial in many applications. In particular, for this application, the nanocrystal array should be formed with a thermal process at temperatures below 1000xc2x0 C. High temperatures are not compatible with the fabrication flow of advanced devices. These high temperatures are therefore to be avoided, to the extent possible.
Until now, the only method by which this goal can be achieved is by depositing amorphous Silicon and crystallizing it into polysilicon at 750xc2x0 C., as disclosed in the K. Yano et al. article cited above. However, this method creates a discontinuous polysilicon layer, and the thickness variations in the film makes reproducibility and control of the process quite critical.
On the other hand, alternative methods using Silicon rich oxide layers that are produced by deposition of a substechiometric oxide layer, require a thermal process at a temperature above 1050xc2x0 C. in order to form the Si nanocrystals through the agglomeration of the excess Silicon.
Thus, in the prior art there is no controlled process whereby the necessary processes can be performed in a low thermal environment. Therefore, until now, there was no method available for implanting Silicon ions into a thin oxide layer such that a subsequent thermal processing step can be performed within a low thermal budget that ensures that the Silicon ions are implanted at a precise depth, such that no over lateral or horizontal dispersion occurs.
Embodiments of the present invention implant Silicon ions by ion implantation at a low energy into a thin oxide layer, such that annealing needed for the formation of the nanocrystal can be performed within a low thermal budget. Additionally, Silicon ions implanted at such a low energy level have low incidence of horizontal or lateral dispersion. In some embodiments, ultra-low energy Silicon ion implantation successfully introduces Si ions in an oxide layer to produce a localized layer of Si nanocrystals in a process that is easily integrated with existing semiconductor fabrication processes.
Presented is a process for forming an oxide layer containing either a continuous polysilicon layer or a series of quantum dots. The process includes forming the oxide layer on a semiconductive substrate. Silicon ions are then introduced within the oxide layer by ionic implantation of the Silicon ions at a low energy level. Next the semiconductive substrate is thermally treated to cause the Silicon ions to become either the continuous polysilicon layer, or the series of quantum dots, depending on how the thermal treatment is performed. In some embodiments the energy of the implanted ions is between 0.1 and 7 keV.
Also presented is a method of forming a non-volatile memory device using the above methods to fabricate a floating gate.
The characteristics and advantages of the device according to the invention will be seen from the description, following herein, of an embodiment given as an indication and not limiting with reference to the drawings attached.
USPTO Backgrounds
USPTO Backgrounds