1. Field of the Invention
The present invention relates to a signal transmission circuit and a characteristic adjustment method thereof, and, more particularly relates to a signal transmission circuit capable of detecting an impedance mismatch between transmission lines and a characteristic adjustment method thereof. The present invention also relates to a memory module, and, more particularly relates to a memory module capable of reading an impedance of a transmission line. The present invention also relates to a manufacturing method of a circuit board, and, more particularly relates to a manufacturing method of a circuit board capable of reading an impedance of a transmission line.
2. Description of Related Art
In information processing systems such as a personal computer and a server, a mother board has mounted thereon a large number of semiconductor chips including not only control system chips such as a CPU (Central Processing Unit) and a memory controller but also semiconductor memories represented by a DRAM (Dynamic Random Access Memory). Among these semiconductor chips, generally, a DRAM is mounted in a memory module called a DIMM (Dual Inline Memory Module), which is mounted on a mother board via a socket.
In recent years, a data transfer rate between a memory controller and a DRAM is increasingly accelerated. When the data transfer rate is accelerated, deterioration in signal quality becomes conspicuous, and thus presently, an impedance adjustment function of an output buffer, an ODT (On Die Termination) function or the like are mounted on the DRAM to inhibit the deterioration in signal quality. Regarding the impedance adjustment function of an output buffer, the ODT function or the like, those described in Japanese Patent Application Laid-open Nos. 2000-332591, 2003-223784, 2005-333222, and 2006-140548 are known.
However, a further accelerated data transfer rate has been recently requested. For example, a data transfer rate of about 3.2 Gbps is demanded. When the data transfer rate is increased to about 3.2 Gbps, the deterioration in signal quality becomes more conspicuous, and as a result, reflection noise resulting from an impedance mismatch between the transmission lines cannot be ignored.
Such an impedance mismatch is mainly a problem between the transmission lines formed on the mother board and that formed on the memory module. The impedance mismatch is generated due to the fact that a predetermined acceptable range is allowed in the impedance of the transmission line in consideration of production variation or the like. Generally, the acceptable range of the impedance is set to about ±15%.
FIG. 15 is a graph for explaining deterioration in signal quality resulting from the impedance mismatch, and shows a signal quality of a case that a memory controller 10 shown in FIG. 16 writes data to a DRAM 21.
As shown in FIG. 16, the memory controller 10 is connected to a signal line 31, and the DRAM 21 is connected to a signal line 32. The signal line 31 is formed on a mother board, and the signal line 32 is formed on a memory module. The signal lines 31 and 32 are connected to each other via a connector 40. The memory module also has another DRAM 22 mounted therein; however, this DRAM 22 is a non-selected one.
In FIG. 15, the X-axis indicates a termination resistance value of the non-selected DRAM 22 (Off Rank DRAM), and the Y-axis indicates amplitude (Eye Height) of write data inputted to the DRAM 21 (On Rank DRAM) that is a write target. More specifically, the Eye Height indicated on the Y-axis represents the amplitude of a signal supplied to an input buffer of the DRAM 21.
The termination resistance value of the DRAM 22 is set to 40 Ω, for example, by the ODT function. However, the termination resistance value also has a variation to some degree by a temperature change, a power voltage fluctuation or the like. In this example, the fluctuation of the termination resistance value resulting from a temperature change, a power voltage fluctuation or the like is estimated at ±15%. The larger the Eye Height, the more preferable. In this case, the minimum acceptable value is set to 200 mV.
A characteristic A shown in FIG. 15 indicates a case that the impedance of the transmission line 31 matches a design value (=Zmp), and the impedance of the transmission line 32 also matches a design value (=Zdp). In this case, when the termination resistance value of the DRAM 22 is a design value (=40 Ω), the Eye Height has a maximum value. Eye Height gradually decreases as the termination resistance value of the DRAM 22 moves farther away from 40 Ω. Even so, in a range of ±15% that is a fluctuation width of the termination resistance value, Eye Height still obtains a sufficiently large value. Thus, a sufficient margin for the temperature change, the power voltage fluctuation or the like is secured.
On the contrary, a characteristic B shown in FIG. 15 indicates a case that the impedance of the transmission line 31 is a minimum value (=Zmn) within an acceptable range and that of the transmission line 32 is a maximum value (=Zdx) within an acceptable range. Accordingly, when the acceptable range of the impedance is ±15%, Zmn=Zmp×0.85 and Zdx=Zdp×1.15. Thus, in total, an impedance mismatch of about 30% is generated.
In this case, it is understood that Eye Height of a case that the termination resistance value of the DRAM 22 is a design value (=40 Ω) is more decreased than a characteristic A. In this case, when the termination resistance value is about 36.5 Ω that is lower than the design value, the Eye Height has a maximum value and decreases as the termination resistance value moves farther away from 36.5 Ω. Thus, when the termination resistance value of the DRAM 22 is high, Eye Height is greatly reduced, and when the termination resistance value is higher by 15% than the design value, Eye Height decreases to near the minimum acceptable value (=200 mV). Thus, in this case, when the termination resistance value of the DRAM 22 is high, the margin of Eye Height is greatly decreased.
On the other hand, a characteristic C shown in FIG. 15 indicates a case that the impedance of the transmission line 31 is the maximum value (=Zmx) within the acceptable range, and that of the transmission line 32 is the minimum value (=Zdn) within an acceptable range. Accordingly, when an acceptable width of the impedance is ±15%, Zmx=Zmp×1.15 and Zdn=Zdp×0.85. Thus, in total, an impedance mismatch of about 30% is generated.
Also in this case, Eye Height of a case that the termination resistance value of the DRAM 22 is a design value (=40 Ω) is more decreased than the characteristic A. In this case, when the termination resistance value is about 44 Ω that is higher than the design value, Eye Height has a maximum value and decreases as the termination resistance value moves farther away from 44 Ω. Thus, when the termination resistance value of the DRAM 22 is low, Eye Height is greatly reduced, and when the termination resistance value is lower by 15% than the design value, Eye Height decreases to near the minimum acceptable value (=200 mV). Thus, in this case, when the termination resistance value of the DRAM 22 is low, the margin of Eye Height is greatly decreased.
As described above, when the impedance mismatch is present between the transmission lines, the signal quality is deteriorated. As a result, there is a problem that the margin for the temperature change, the power voltage fluctuation or the like is decreased.
To solve such a problem fundamentally, it is necessary to enhance a design precision/fabrication precision of a mother board or a memory module so that the impedance mismatch does not occur in the first place. However, in this case, a decrease in manufacture yield of the mother board or the memory module and a significant price increase is inevitable, and hence, not realistic as a solution. To solve this problem, there is demanded a technique capable of recognizing the presence of such an impedance mismatch at the time of actual use while accepting the fact that the impedance mismatch is present in reality.
USPTO Backgrounds
USPTO Backgrounds