1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to contact structures in semiconductor devices.
2. Description of the Related Art
In semiconductor memory devices, a static random access memory (SRAM) device may offer advantages of lower power consumption and faster operating speed as compared to a dynamic random access memory (DRAM) device. Therefore, the SRAM may be widely used for cache memory in computers and/or other portable devices.
A unit cell of a SRAM device may be categorized as either a resistor-load SRAM cell or a complementary metal-oxide semiconductor (CMOS) SRAM cell. A resistor-load SRAM cell may employ a high-resistance resistor as a load device, while a CMOS SRAM cell may employ a p-channel metal-oxide semiconductor (PMOS) transistor as a load device.
The CMOS SRAM cell may be categorized as one of two types. One type of CMOS SRAM cell is a thin film transistor (TFT) SRAM cell, which may employ TFTs stacked on a semiconductor substrate as the load device. The other is a bulk CMOS SRAM cell, which may employ bulk transistors formed on a semiconductor substrate as the load device.
The bulk CMOS SRAM cell may exhibit higher cell stability as compared to the TFT SRAM cell and the resistor-load SRAM cell. In other words, the bulk CMOS SRAM cell may have excellent low voltage characteristics and low stand-by current. This may be because the transistors that make up the bulk CMOS SRAM cell are typically formed of a single crystalline silicon substrate. In contrast, the TFTs of the TFT SRAM cell are typically formed using a polysilicon layer as a body layer. However, the bulk CMOS SRAM cell may have lower integration density as well as weaker latch-up immunity as compared to the TFT SRAM cell. Therefore, in order to produce a highly integrated SRAM device having high reliability, characteristics of load transistors employed in the TFT SRAM cell may need to be improved.
In addition, each of the SRAM cells may include a pair of node contact structures. More particularly, in the TFT SRAM cell, each of the node contact structures may electrically connect a P-type drain region of a load transistor to an N-type drain region of a driver transistor.
Semiconductor devices having TFTs stacked on a semiconductor substrate are described in U.S. Pat. No. 6,022,766 to Chen et al. According to Chen et al., an improved field effect transistor (FET) structure comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFTs can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Chen also discloses a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell.
Furthermore, a body layer of a TFT may be formed by depositing an amorphous silicon layer on the semiconductor substrate having the metal plug, and by crystallizing the amorphous silicon layer using a thermal treatment process. The body layer may be a polysilicon layer having large grains. As such, it may be difficult to convert the body layer into a perfect single crystalline silicon layer. Consequently, it may be difficult to form TFTs having electrical characteristics comparable to that of a bulk transistor.
USPTO Backgrounds
USPTO Backgrounds