As well known in the art, a semiconductor memory device has awfully many memory cells arranged in rows and columns, and the memory cells are grouped into a number of memory arrays. With the increase of the integration of electronic systems, the density of the memory device is also increased. Accordingly, an area that can be occupied by a single memory cell becomes smaller. In the high density memory device, a redundancy technology is commonly utilized to improve production yield.
The redundancy technology is to provide spare or redundant memory cells which can replace any defective elements in regular memory cell arrays. During electrical tests of a memory device, the defective memory cells are identified and the redundant cells, which are also arranged in rows and columns, are activated in place of the defective elements. In case of a column redundancy circuit, a defective cell in the regular memory cells can be replaced by decoding column address associated with the defective element and by activating only a redundant memory cell. Whether the redundant cells are to be activated or the regular nondefective memory cells are to be activated can be determined by using a fuse circuit (or a redundancy circuit), which is divided into two: a dynamic type fuse circuit as shown in FIG. 1, and a static type as shown in FIG. 3.
In present, the dynamic fuse circuit has been used as a row redundancy circuit for repairing any defective memory cells by decoding row addresses in a synchronous memory device as well as an asynchronous device (though in this device, the row addresses are activated synchronously with a reference signal or Row Address Strobe signal). On the other hand, the latter static fuse has been used in both a column and a row redundancy circuits.
FIG. 1 is a circuit diagram of a conventional dynamic fuse circuit used in a memory device. Referring to FIG. 1, the dynamic fuse circuit comprises two P-channel type metal oxide semiconductor (PMOS) transistors 1.sub.-- 1 and 1.sub.-- 2, and an inverter 3.sub.-- 1, a plurality of fuses f1 to fn, a switching circuit and an output driving circuit. The PMOS transistors 1.sub.-- 1 and 1.sub.-- 2 together with the inverter 3.sub.-- 1 act as a precharging element for precharging a node ND1 to a high voltage level (Vcc) when an external clock signal CLK in a synchronous memory device (or RAS in case of an asynchronous device) remains in a low voltage level. Each of the fuses f1 to fn is connected in parallel to the node ND1 at its one end. The switching circuit comprises a corresponding number of NMOS transistors to the fuses, each of NMOS transistors has a source connected to a ground voltage Vss, a drain connected to the other end of each of the fuses, and a gate electrode to which row address signal A1, /A1, A2, /A2, . . . , Am and /Am are applied, where `/` presents a complementary signal, i.e., if A1 is high, then /A1 must be low, and vice verse. The output driving circuit provided with two serially connected inverters 3.sub.-- 2 and 3.sub.-- 3 is to buffer or amplify the voltage signal placed on node ND1 and to output a row redundancy addressing signal REDn for activating a selected redundant memory cell.
FIG. 2 shows a timing diagram of the conventional dynamic fuse circuit of FIG. 1. With reference to FIGS. 1 and 2, the operation of the dynamic fuse circuit will be described in detail.
When the clock signal CLK or RAS is in low voltage level, the PMOS transistor 1.sub.-- 1 conducts, which allows the node ND1 to go high its precharing level Vcc. If a memory cell is found to be defective, some fuses corresponding to the address of the defective memory cell must be opened or cut-off by using, e.g., a laser cutting method. As an example, if the defective memory cell has a row address of A1, A2, A3, . . . ,Am-1 and Am being `011 . . . 11`, among the fuses, f2 and f3, f5, f7, . . . ,f(n-1) must be cut off. In other word, the fuses connected NMOS transistors receiving address bits including the complementary signals which have logical value of `1` (i.e., high voltage level) must be cut off. This is to make the node ND1 and ground Vss be disconnected, resulting in the high voltage level of ND1. When the address signal is active, the clock signal CLK remains high, which causes the PMOS transistor 1.sub.-- 1 to turn off. However, the high voltage level of ND1 can be maintained by a latch circuit consisted of the inverter 3.sub.-- 1 and the PMOS transistor 1.sub.-- 2, because the positive electrical charges are continuously supplied to ND1 through the conduction of PMOS transistor 1.sub.-- 2. When the ND1 remains high, the row redundancy addressing signal REDn outputs high voltage signal, so that the defective row is deactivated and the redundancy row is addressed.
Of course, if there is no defective memory cell, the fuse cutting will not be done. At this time, because at least one of the NMOS transistors 2.sub.-- 1 to 2.sub.-- n turn on, the node ND1 is discharged to Vss. As a result, from the output driving circuit 3.sub.-- 2 and 3.sub.-- 3 is out a low redundancy addressing signal REDn, so that no redundancy memory cell is selected.
The dynamic fuse circuit explained above has a relatively small layout area, but the precharging action of the node ND1 should be followed by each of address reset operation after CLK goes low. This inevitably limits the application of the dynamic fuse circuit to such a memory device having high speed address input, i.e., having a very short or no address reset time as in asynchronous memory devices.
FIG. 3 is a circuit diagram of a conventional static type fuse circuit used in memory devices. The static fuse circuit comprises a number of fuses f1-fn, of which two adjacent fuses are connected together, COMS transmission gates, a transmission gate control circuit, a switching circuit, and an output logic circuit. The COMS transmission gates 11.sub.-- 1/12.sub.-- 1, 11.sub.-- 2/12.sub.-- 2, . . . , 11.sub.-- n/12.sub.-- n have conduction paths between the fuses and address input nodes A1, /A1, A2, /A2, . . . , Am and /Am. The transmission gate control circuit comprises a master fuse fm, a PMOS transistor 14, NMOS transistors 16.sub.-- 1 and 16.sub.-- 2, and inverters 14.sub.-- 1 to 14.sub.-- 4. The switching circuit is a plurality of NMOS transistors 17.sub.-- 1 to 17.sub.-- m, each having a gate electrode connected to node ND2, and a source and a drain connected to a pair of fuses (i.e., two adjacently connected fuses) and to the ground terminal Vss, respectively. The output logic circuit comprises NAND gates 18.sub.-- 1, 18.sub.-- 2 and 18.sub.-- 3, NOR gates 19.sub.-- 1 and 19.sub.-- 2, and an inverter 14.sub.-- 5. Inputs of the output logic circuit are connected to drains of the switching circuits 17.sub.-- 1 to 17.sub.-- m, so that if all of the drains are high voltage levels, an output signal REDn goes high, while if any one of the drains goes low the output REDn of the output logic circuit is converted to a low voltage. When the output REDn remains high, a row or a column redundancy addressing signal is active, and therefore corresponding word line or bit line of redundant memory cells is activated. Of two adjacent CMOS transmission gates, PMOS transistors (e.g., 11.sub.-- 1 and 11.sub.-- 2) have gate electrodes commonly connected to node ND2, and NMOS transistors (e.g., 12.sub.-- 1 and 12.sub.-- 2) have gate electrodes connected to an output of an inverter 14.sub.-- 4 which reverts the voltage level of node ND2.
With this structure of static fuse circuit, when the redundant memory cells are to be used in place of defective memory cells, the fuses associated with low `0` address signals of the defective address bits (A1, /A1, . . . , Am and /Am) must be cut off on the contrary to the dynamic fuse circuit. For example, if the row address bits of a defective memory cell is `01 . . . 11`, then fuse f1 and fuses f4, f6, f8, . . . , and fn (i.e., fuses having even numbered subscripts) must be cut off, while the fuses f2, f3, f5, f7, . . . and f(n-1) are not opened. That is to say, what is to be cut off are fuses connected to the transmission gates which receive address bits of `0` including the complementary address signals.
The master fuse fm prevents the collision of two complementary signals (e.g., A1 and /A1) through two adjacently connected transmission gates when the redundant memory cells activated by the static fuse circuit are not to be used, i.e., when there are no defective memory cells.
When the static fuse circuit is not to be used, all of the fuses f1 to fn (here-in-after referred to as `slave fuses`) and the master fuse fm are in closed states. Therefore, if an initiating signal V.sub.INIT is supplied, the node ND2 goes high through the conduction of PMOS transistor 14 of the transmission gate control circuit. This causes the transmission gates 11.sub.-- 1 to 11.sub.-- n and 12.sub.-- 1 and 12.sub.-- n to turn off, and the switching transistors 17.sub.-- 1 to 17.sub.-- m to turn on. As a result, drain nodes of all of the switching transistors 17.sub.-- 1 to 17.sub.-- m go low, which allows the output logic circuit to output a low leveled redundancy addressing signal REDn.
FIG. 4 is a timing diagram of various signals used in the conventional static fuse circuit.
As explained before, when the redundant memory cells are to be used half the slave fuses connected to the transmission gates and the master fuse fm are opened by e.g., a laser cutting method. If the initiating signal V.sub.INIT remains low, NMOS transistors 16.sub.-- 1 and 16.sub.-- 2 of the transmission gate control circuit turn on, and hence the node ND2 goes low. Accordingly, all of the transmission gates turn on, while the NMOS switching transistors 17.sub.-- 1 to 17.sub.-- m turn off.
On the other hand, if an address signal for normal non-defective memory cell (e.g., `10 . . . 01`) is input, at least one low address bit is placed on a corresponding drain node of the NMOS transistors 17.sub.-- 1 to 17.sub.-- m through a non-opened fuse. Accordingly, the output logic circuit supplies low leveled, i.e., inactive row redundancy addressing signal REDn, so that the normal word line corresponding to the input address signal is activated.
When defective address signal (e.g., `01 . . . 11`) is supplied, high address bits (e.g., `/A1, A2, A3, , Am) place high voltage on all of the drain nodes of the NMOS transistors 17.sub.-- 1 to 17.sub.-- m, which causes all of the NAND gates 18.sub.-- 1 to 18.sub.-- m to receive high inputs, so that the output of the output logic circuit REDn becomes active high.
Next, when the initiating signal V.sub.INIT goes high, NMOS transistors 16.sub.-- 1 and 16.sub.-- 2 of the transmission gate control circuit turn off, but the node ND2 still remains low due to the cut off master fuse fm together with the latching action of the transistor 16.sub.-- 2 and the inverter 14.sub.-- 2. Accordingly, the transmission gates are all turned on and on the contrary the switching NMOS transistors 17.sub.-- 1 to 17.sub.-- m are all turned off. In this state, if the defective address signal URA for redundant memory cell is input, at least one of the drain nodes of the NMOS transistors 17.sub.-- 1 to 17.sub.-- m receives high address bit through the closed fuse, which causes the output logic circuit to output low redundancy addressing signal REDn.
On the other hand, when defective address signal (`01 . . . 11`) is input with maintaining the signal V.sub.INIT to be high, high address bits (`/A1, A2, A3, . . . , Am`) are delivered to all of the drain nodes of the switching transistors 17.sub.-- 1 to 17.sub.-- m, and hence the redundancy addressing signal REDn goes high.
As explained so far, because the static fuse circuit dislike the dynamic fuse circuit need not to reset the address signal or to precharge a certain node which determines the voltage value of the redundancy addressing signal, it can be properly used in high speed memory devices such as synchronous DRAM and SRAM in which the addressing is preformed at high frequency. However, it has critical drawback in that the layout is much larger than the dynamic fuse circuit.
USPTO Backgrounds
USPTO Backgrounds