Field of the Invention
Embodiments of the present invention relate generally to computer processing and, more specifically, to in-rush current limiting switch control.
Description of the Related Art
In computer systems, in general, and in graphics processing units (GPUs), in particular, functionality is implemented by very-large-scale integrated (VLSI) microcircuits. Within a VLSI microcircuit, functionality is typically partitioned into groups of elements forming circuit domains that perform specific, related operations. Frequently the functionality provided by such a domain is required for only intermittent use. As power consumption within a VLSI microcircuit is a critical parameter, in such a case it is desirable to remove voltage from such a domain when the functionality is not required. One example of such a domain is a random access memory (RAM) that is accessed for a limited period of time and is idle whenever access is not occurring. Often a VLSI microcircuit may include multiple RAMs, and gating voltage to these multiple domains separately, as they are needed, can provide significant power savings. Further, gating of any domain that is used intermittently can provide significant benefit by reducing the power usage of the microcircuit.
Typically a multiplicity of field effect transistors (FETs) performs the switching function that gates the global supply voltage of the microcircuit to the intermittently required circuit domain. FETs function as voltage-controlled resistors. FET resistance is extremely high in cut-off mode, which produces an effective open circuit. In conduction mode, the resistance of the FET is low enough to produce an effective short circuit for the low levels of current involved in data processing within a VLSI microcircuit. However, the bulk resistance of a single FET in conduction mode limits the current that it can pass. As the total domain current is typically very large relative to the bulk resistance of a single FET, very many FETs are connected in parallel to reduce the effective series resistance between the global supply voltage source and the gated domain.
An aspect of this approach is that, when all FETs are switched to conduction mode simultaneously, a large transient current is required to charge the distributed capacitance of the gated domain. This so-called in-rush current causes the supply voltage level to sag while the capacitance of the domain is charging. The resulting decrease in supply voltage imposes a limitation on the operating frequency of the microcircuit, as the maximum frequency of operation is closely correlated to the minimum level of the supply voltage. Because of this, a limited number of the multiplicity of FETs is conventionally switched to conduction mode first. The series resistance provided by the smaller number of parallel FETs provides charging current to the gated domain while limiting the magnitude of the initial transient, or in-rush, current. In this way, turning on a small number of the multiplicity of FETs effects a wake-up function that charges the domain capacitance at a slower rate, thus minimizing the voltage sag. After the domain voltage has charged to a sufficient level, the balance of the multiplicity of FETs are switched to conduction mode to pass the full operating current to the domain circuitry through the resulting very small series resistance.
One drawback to the above approach is that it is uncertain when the domain voltage reaches a sufficient level. The timing of the charge of the domain is dependent on the distributed capacitance of the domain circuitry as well as the bulk resistance of the FETs. Both of these parameters vary due to process differences across a semiconductor wafer and from wafer to wafer. It is possible to delay the turn-on of the full complement of FETs for a fixed amount of time based an analytical estimation the domain capacitance and the equivalent series resistance of the FETs. This approach typically results in an undesirably long interval before the domain is fully powered and guaranteed operational. This extremely long interval degrades system performance by reducing availability. Similarly, an approach that sequentially turns on successive subgroups of FETs after the initial wake-up can also reduce the in-rush current and may accommodate some of the uncertainty but also results in an undesirably long interval.
As the foregoing illustrates, what is needed in the art is a technique for managing in-rush current and turn-on delay.
USPTO Backgrounds
USPTO Backgrounds