1. Field of the Invention
The present invention relates to electronic components and methods for mounting the same, and particularly to an electronic component having an external connection electrode that allows highly reliable electric connection because of prevention of the lowering of the bonding strength between the external connection electrode and a substrate, arising due to side etching (undercut) at the time of removal of the unnecessary part of an underlying metal layer by wet etching. The invention relates also to a semiconductor device employing this electronic component, and a method for manufacturing an electronic component.
2. Description of the Related Art
There are very strong demands for electronic apparatuses typified by mobile products such as cell phones to have higher density, smaller size, higher performance, and higher reliability. Various kinds of mounting technique are being studied in order to meet these demands.
Along with enhancement of the integration degree and performance of LSIs, the chip size is ever-increasing, which leads to serious problems such as the lowering of the yield and increases in the mounting area and costs. In recent years, attention has been paid on SiP (System in Package), which can address these problems and offer higher LSI performance simultaneously. The SiP can be classified into various structures such as a package-stack structure, chip-stack structure, and chip-on-chip structure. Of these structures, the chip-on-chip structure is advantageous in achievement of higher speed and lower power consumption because it can interconnect chips with a short interconnect length.
The chip-on-chip SiP is realized by connecting e.g. a memory chip and a logic circuit chip to each other via bumps formed on the chips in such a way that the active surfaces of the chips are in face-to-face. A large number of reports on formation of bumps have been issued.
Japanese Patent Laid-open No. Hei 10-189635 (hereinafter Patent Document 1, Paragraphs 0006 to 0008, FIG. 2) titled “Handoutai souchi no setsugou houhou” (“Bonding method for semiconductor device” in English) includes the following description.
FIGS. 15A to 15E are equivalent to FIG. 2 in Patent Document 1, and are sectional views showing the respective forming steps for a semiconductor device having a bump electrode.
With reference to FIGS. 15A to 15E, a method for forming an external electrode 116 over a silicon wafer 110 will be described below. Referring initially to FIG. 15A, an internal electrode 111 and an insulating film 112 composed of a silicon oxide are formed on the silicon wafer 110, and then an electrode pad 113 composed of aluminum or an aluminum alloy is formed thereon. Subsequently, an insulating film 114 composed of a silicon nitride is formed on the electrode pad 113 and the insulating film 112. In the insulating film 114, an opening 114a of which size is slightly smaller than the outline size of the electrode pad 113 is formed by etching, so that the electrode pad 113 is exposed from the opening 114a. In this state, an under-bump layer composed of an alloy such as a titanium-tungsten alloy and a gold film are sequentially deposited by sputtering, so that an under-bump layer 115 and a gold thin film 116a are formed to each have a thickness of several thousand angstroms over the entire surfaces of the electrode pad 113 and the insulating film 114 over the silicon wafer 110. The thickness of the gold thin film 116a may be several hundred angstroms. In this case, sputtering is the optimum method for uniformly disposing metal particles. Before this film deposition, treatment for removing an aluminum oxide film is carried out according to need.
Referring next to FIG. 15B, a photoresist chemical is dropped on the gold thin film 116a and spin-coating is carried out, so that a thick photoresist film 119 (having a thickness of about 20 to 30 μm) is formed. Subsequently, the formed photoresist film 119 is dried, and then a mask (not shown) is aligned with the top face of the photoresist film 119. The size of the optically-transparent part of this mask is such that the outer peripheral edge of the optically-transparent part is positioned between the outer peripheral edge of the electrode pad 113 and that of the opening 114a in the insulating film 114. The photoresist film 119 is subjected to exposure through this mask and developed by a developer, to thereby form an opening 119a in the photoresist film 119 as shown in FIG. 15C. Subsequently, gold is deposited by electrolytic plating on the gold thin film 116a exposed through the opening 119a to thereby form a bump electrode 116b. The deposition of the bump electrode 116b is stopped before the top face level of the bump electrode 116b becomes higher than that of the photoresist film 119, so that the thickness of the bump electrode 116b is set to about 20 to 30 μm. As a result, the bump electrode 116b has a column shape and a substantially flat top face.
Subsequently, as shown in FIG. 15D, the photoresist film 119 is removed by an organic solvent. In this state, the gold thin film 116a is etched by an iodine etchant, so that the unnecessary part of the gold thin film 116a, i.e., the part of the gold thin film 116a not corresponding to the bump electrode 116b, is removed. The resultant state is shown in FIG. 15E.
A document titled “Bump mekki souchi” (“Bump plating apparatus” in English, Kuriyama et al., Ebara Engineering Review, No. 207, p. 34-38 (2005-4), (Section 3. Bump process, FIG. 1), hereinafter Patent Document 1) includes a description relating to a solder bump plating process as a representative example of bump formation schemes.
Japanese Patent Laid-open No. 10-92830 (hereinafter Patent Document 2, Paragraphs 0006 to 0008, FIGS. 1 and 2) titled “Handoutai souchi no seizou houhou” (“Manufacturing method for semiconductor device” in English) includes the following description.
FIGS. 16A to 16F are equivalent to FIGS. 1 and 2 in Patent Document 2, and are sectional views showing a manufacturing method for a semiconductor device.
With reference to FIGS. 16A to 16F, steps of a manufacturing method for a semiconductor device according to the first embodiment described in Patent Document 2 will be described below.
Step of FIG. 16A:
An oxide film 212 is formed on a semiconductor substrate 211 by CVD, and then a semiconductor device such as an LCD driver IC is formed. An Al film is formed on the entire surface by sputtering or the like and the Al film is patterned through photolithography and etching, so that an Al electrode pad 213 having a size of e.g. about 50 μm×70 μm is formed at the position over which a bump electrode is to be formed. An insulating film composed of SiO2 or the like is formed on the entire surface by CVD, to thereby form a surface protective film 214 to a film thickness of e.g. about 0.8 to 1.4 μm. Subsequently, the surface protective film 214 on the Al electrode pad 213 is removed by photolithography and etching, so that a through hole 15 is opened on the Al electrode pad 213.
Step of FIG. 16B:
Plural underlying metal layers are sequentially deposited over the entire surface of the semiconductor substrate 211 by sputtering or the like. As the underlying metal layers, a Ti/W film 216a showing good adhesion to Al and a Pd film 216b for preventing diffusion of Au are deposited for example.
Step of FIG. 16C:
Over the Ti/W and Pd underlying metal layers 216a and 216b, a positive photosensitive resin film is deposited across the entire surface to a film thickness of about 25 to 30 μm. Subsequently, the part of the photosensitive resin film on the Al electrode pad 213 is subjected to exposure with use of a mask, and then is immersed in an etchant solvent for the photosensitive resin film, so that the exposed part is etched (developed). This process forms a bump electrode formation pattern 217 that has an absent part having a size of about 30 μm×50 μm and positioned above the Al electrode pad 213 and inside the Al electrode pad 213 by a distance of about 20 μm. Subsequently, a bump electrode 218 having a height of e.g. about 15 to 20 μm is formed through Au plating. In this Au plating, with use of the Ti/W and Pd underlying metal layers 216a and 216b as a common cathode, a constant current with a current density of e.g. about 1 A/cm2 is supplied to the semiconductor substrate 211 with the semiconductor substrate 211 immersed in a plating solution such as a potassium gold cyanide or sodium gold sulfite solution.
Step of FIG. 16D:
The part of the photosensitive resin film with a width of e.g. about 5 μm around the absent part of the bump electrode formation pattern 217 is subjected to exposure with use of a mask, and then is immersed in an etchant solvent for the photosensitive resin film, so that the exposed part is etched. This process forms a pattern 217a for forming an underlying-metal protective layer. Each dimension size of the pattern 217a is larger by about 5 μm than that of the bump electrode formation pattern 217.
Step of FIG. 16E:
For Au plating again, with use of the Ti/W and Pd underlying metal layers 216a and 216b as a common cathode, a constant current (e.g., 1 A/cm2) is supplied to the semiconductor substrate 211 with the substrate 211 immersed in a plating solution. Through this Au plating, an underlying-metal protective layer 219 having a film thickness of 1 μm or less (this film thickness is determined depending on the film thicknesses of the Ti/W and Pd underlying metal layers 216a and 216b) is formed in the gap surrounding the bump electrode 218. Through this plating, the same Au film is formed also on the bump electrode 218.
Step of FIG. 16F:
The photosensitive resin film 217 is removed by a removal solvent or the like. Furthermore, with use of the underlying-metal protective layer 219 as a mask, the Pd and Ti/W underlying metal layers 216b and 216a are immersed in an etchant solution so as to be removed by wet etching. Thereafter, the underlying-metal protective layer 219 is etch-removed according to need, so that a final bump electrode structure is obtained. Because the Pd underlying metal layer 216b is covered by the underlying-metal protective layer 219, the part of the Pd and Ti/W underlying metal layers 216b and 216a side-etched at the time of the wet etching thereof is located outside the region directly beneath the bump electrode 218. Therefore, the Pd underlying metal layer 216b under the bump electrode 218 is not etched. After the formation of this bump electrode structure, an inner lead of a tape carrier is connected to the bump electrode 218 through inner lead bonding, which is the end of the mounting.
As described above, according to the first embodiment described in Patent Document 2, the underlying-metal protective layer 219 is provided on the surface of the Pd underlying metal layer 216b around the bump electrode 218 and on the entire surface of the bump electrode 218. This prevents the occurrence of a phenomenon in which at the time of the etching of the Ti/W underlying metal layer 216a, the Ti/W and Pd underlying metal layers 216a and 216b are etched to a part under the bump electrode 218. This phenomenon is referred to as side etching. Thus, it is possible to always keep constant the bonding area between the bump electrode 218 and the Ti/W and Pd underlying metal layers 216a and 216b, which will enhance the quality and yield of the forming step for the bump electrode 218.
Japanese Patent Laid-open No. 2005-322705 (hereinafter Patent Document 3, Paragraphs 0005 to 0012, FIGS. 3 to 7) titled “Handoutai wafer oyobi handoutai chip narabini sorerano seizou houhou” (“Semiconductor wafer, semiconductor chip, and manufacturing method for them” in English) includes the following description.
FIGS. 17A to 17G are equivalent to FIGS. 3 to 7 in Patent Document 3, and are sectional views showing a manufacturing method for a semiconductor wafer, including formation of a bump on a metal layer.
With reference to FIGS. 17A to 17G, steps of a manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3 will be described below.
The manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3 includes formation of a bump 330 on a metal layer 320 (see FIG. 17C). The bump 330 is formed on an uppermost metal layer 324. The bump 330 is formed to overlap with an opening 318. The bump 330 is formed in a region inside the opening 318. In the manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3, the bump 330 is formed in an electrolytic plating step. For example, as shown in FIG. 17A, a mask 335 is formed over a semiconductor substrate 310. The mask 335 has an opening 336 that overlaps with the opening 318 of a passivation layer 316. As shown in FIG. 17A, the opening 336 may be formed in a region inside the opening 318. The mask 335 having the opening 336 may be formed by providing a mask material on the entire surface of the metal layer 320 (the uppermost metal layer 324) and then carrying out exposure and development.
After the formation of the mask 335, an electrolytic plating step is carried out to form the bump 330 inside the opening 336 as shown in FIG. 17B. The material of the bump 330 is not particularly limited. The bump 330 may be formed of e.g. Au. As shown in FIG. 17B, the bump 330 may be monolithic with the uppermost metal layer 324. After the formation of the bump 330, as shown in FIG. 17C, the mask 335 is removed to complete the bump 330. The mask may be so formed that the opening thereof has the same outline shape as that of the opening 318 of the passivation layer 316. By using such a mask, the bump 330 may be so formed that the sectional shape thereof is the same as the shape of the opening 318 of the passivation layer 316 (not shown).
The manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3 includes removal of the part of the metal layer 320 other than a lowermost metal layer 322, outside the bump 330 in an etching step as shown in FIG. 17D. In the example shown in FIG. 17D, the part of the uppermost metal layer 324 outside the bump 330 is removed. If another metal layer is formed between the lowermost metal layer 322 and the uppermost metal layer 324, the part of this metal layer outside the bump 330 is also removed. For the removal, an etching step may be carried out with use of the bump 330 as the mask. Using the bump 330 as the mask eliminates the need for a step of providing a mask separately, and thus allows a semiconductor wafer to be manufactured efficiently. In the present step, the etching is so carried out that the lowermost metal layer 322 is not removed. That is, the etching is so carried out that the lowermost metal layer 322 is left.
The manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3 includes formation of a mask 340 on the lowermost metal layer 322 around the bump 330 as shown in FIG. 17E. As shown in FIG. 17E, the mask 340 is formed to overlap with a peripheral part 319 of the opening 318 in the passivation layer 316. Furthermore, the mask 340 is formed in close contact with the side surface of the bump 330 as shown in FIG. 17E. The material for forming the mask 340 is not particularly limited. The mask 340 may be formed by providing a mask material on the lowermost metal layer 322 and then carrying out exposure and development for example. This mask material may be any of positive materials and negative materials.
The manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3 includes removal of the part of the lowermost metal layer 322 exposed outside the mask 340 in a second etching step as shown in FIG. 17F. A metal layer 321 may be formed by etching the lowermost metal layer 322 (see FIG. 17G).
The manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3 may include removal of the mask 340 as shown in FIG. 17G.
In the manufacturing method for a semiconductor wafer according to an embodiment described in Patent Document 3, as described above, the lowermost metal layer 322 is etched after the step of removing the part of the metal layer other than the lowermost metal layer 322, outside the bump 330. Therefore, it is possible to prevent the lowermost metal layer 322 from being side-etched to a larger extent compared with the upper metal layer, and thus separation between the metal layers can be avoided. Furthermore, the step of etching the lowermost metal layer 322 is carried out with use of the mask 340 formed around the bump 330. Therefore, the size of the metal layer 321 is larger than those of other metal layers and the bump 330. This can offer a reduced tendency of separation of the bump 330 from the metal layer 321. In addition, the mask 340 is formed so as to be in close contact with the side surface of the bump 330 and overlap with the peripheral part 319 of the opening 318 in the passivation layer 316. Therefore, the metal layer 321 can be formed to cover an exposed part 315 of the pad 314. That is, exposure of the pad 314 can be prevented. Thus, a semiconductor wafer having high reliability can be manufactured.
FIGS. 18A to 18E are diagrams for explaining steps for forming a bump electrode and the occurrence of side etching in a related art.
As shown in a plan view and a sectional view along the line W-W of FIG. 18A, a pad electrode (Al pad electrode) 14 is formed on an insulating layer (SiO2) 12 deposited on a Si substrate 10, and then a passivation layer formed of a silicon oxide (SiO2) film 16b and a silicon nitride (Si3N4) film 18 is formed on the entire surface, followed by formation of an opening 15a in the passivation layer by etching.
Subsequently, as shown in a sectional view along the line W-W of FIG. 18B, an underlying metal layer (seed layer) 22 is formed on the entire surface by sputtering or the like. The underlying metal layer 22 includes a part to be removed by etching in a later step. Therefore, the underlying metal layer 22 is indicated as the black area in order to allow clear understanding of the before-etching and after-etching states thereof.
After the formation of the underlying metal layer 22, as shown in a sectional view along the line W-W of FIG. 18C, a resist (photoresist) 24 is applied on the entire surface, and then a bump electrode formation pattern is exposed and developed, so that an opening for forming a bump electrode 28 (having the bump electrode diameter 28a indicated by the arrowheads) is formed. Subsequently, a barrier metal layer 26 is formed by electrolytic plating on the underlying metal layer 22 exposed inside the formed opening. Furthermore, the bump electrode 28 is formed on the barrier metal layer 26 by solder plating.
Subsequently, as shown in a sectional view along the line W-W and a partially enlarged sectional view thereof in FIG. 18D, the resist 24 is removed, and then the underlying metal layer 22 other than the layer 22 under the bump electrode 28 is removed by wet etching with use of the bump electrode 28 as the mask. At the time of the wet etching, the underlying metal layer 22 under the barrier metal layer 26 is also etched (side-etched) simultaneously, which generates a side-etched part 36 resulting from removal of the underlying metal layer 22 under the barrier metal layer 26.
After the wet etching, as shown in a sectional view along the line W-W of FIG. 18E, solder flux is applied on the bump electrode 28, and then heat treatment in a reflow furnace is carried out to homogenize the composition and shape of the bump electrode, followed by clean-removal of the flux. This is the end of the forming steps for the bump electrode 28.
As described in the explanation based on FIG. 18 for the forming steps for the bump electrode in a related art, if the bump electrode is formed by using electrolytic plating, at the time of removal of the underlying metal layer by wet etching, the underlying metal layer under the barrier metal layer is also etched (side-etched) simultaneously, and hence the area of the underlying metal layer becomes smaller than that of the barrier metal layer. That is, an undercut is developed in the underlying metal layer under the barrier metal layer. This decreases the bonding area between the barrier metal layer and the underlying metal layer, which lowers the bonding strength between the bump electrode and the semiconductor substrate. This problem becomes more serious as the pitch and diameter of the bump electrodes become smaller along with increase in the integration degree of LSIs. In addition, depending on the case, the bump electrodes will be separated at the time of the removal of the underlying metal layer by wet etching. Therefore, an undercut due to side etching is a big problem: it causes the lowering of the yield and reliability.
In order to prevent the side etching, as disclosed in e.g. Patent Documents 2 and 3, the following schemes are employed: a scheme in which a protective layer for preventing progression of side etching of an underlying metal layer is provided around a bump electrode; and a scheme in which a mask is provided around a bump electrode. However, these schemes need addition of steps of forming the protective layer, removing the protective layer, forming the mask, and removing the mask. Therefore, these schemes problematically cause increases in the manufacturing costs and TAT.
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