1. Field of the Invention
The present invention relates to a system for testing electric properties of objects such as packaged logic circuit elements.
2. Description of the Related Art
Before being put on the market as a product, each of packaged elements or devices is tested about its electric properties. When the pitch of lead terminals of each device is relatively large, a tester system provided with a handler for handling devices and a test head for testing them is usually used in the test of this kind. According to this tester system, devices are automatically carried and attached to a socket of the test head by the handler and tested while electrically contacting lead terminals of the devices with electrodes of the test head via the socket. According to test results thus obtained, the devices are sorted and stored by the handler.
Conventional one of these tester systems is shown in FIG. 6. It has sections 1A-1D, on which plural trays are mounted, on its front (or upper) side. These tray-mounted sections 1A-1D are arranged on it along a direction X in FIG. 6. A tray T on which devices D to be tested are arranged in lines is mounted on each of the tray-mounted sections 1A and 1B, while a tray T on which devices D tested are arranged in lines is mounted on each of the tray-mounted sections 1C and 1D. A loader 2 and an unloader 3 which serve as the handler are arranged above an area in which the tray-mounted sections 1A-1D are included. The loader 2 serves to suck and hold four devices D from each of the trays T on the tray-mounted sections 1A and 1B and carry them to an supply section 5 which is on a devices-carrying line. The devices D at the supply section 5 are then carried to a test position, where a socket 7 of the test head is located, by a carrier mechanism 6, which sucks and holds four devices D from the supply section 5 at the same time and the carries them to the test position in this case. Those devices D which have been carried to the test position by the carrier mechanism 6 are attached to the socket 7 one by one and their electric properties are then tested through the test head. After the test, the carrier mechanism 6 carries them to a housing or storing section 8 which is in the operation area of the unloader 3. The unloader 3 sucks and holds four devices D tested from the housing section 8 at the same time and carries them to one of the trays T at the tray-mounted sections 1C and 1D while sorting them responsive to their test results obtained. To add more, the supply alignment section 5 serves to previously and correctly position or align each of them relative to the socket 7, while the housing alignment section 8 serves to previously and correctly position or align them relative to each of the trays T.
In order to increase the throughput of the test, it is usually necessary to shorten the index time (i.e., a period between the end of testing of devices D and the start of testing of next devices D moved to the test position after tested devices D have been removed from the test position). In the case of the conventional tester system shown in FIG. 6, therefore, four devices are carried to the test position at the same time, as described above. The average carrying time for each device is thus shortened, which leads to the shortening of the index time.
In the conventional tester system, however, one test head is provided with only one carrier mechanism 6. Even though the carrier mechanism 6 can carry plural devices D at the same time, each of them cannot be tested while the carrier mechanism 6 is moving. The test head is therefore left inoperative while devices D are being carried by the carrier mechanism 6. This makes it impossible to make the index time zero, thereby preventing the index time from being shortened.
Two test heads can be used to shorten the index time. In the conventional tester system, however, the test head is arranged to correspond to one handler. When two test heads are used in this case, therefore, two-line handlers are needed. This makes the tester system in FIG. 6 larger in size. Its installing space must be thus made larger and its making cost becomes higher, accordingly. Particularly in the logic test, contents of test become more complicated and test time also becomes longer, because objects such as logic circuit elements to be tested become larger in size and more complicated. This makes it difficult to increase the throughput.
USPTO Backgrounds
USPTO Backgrounds