1. Field of the Invention
The present invention relates to a semiconductor memory device and a defect repair method for a semiconductor memory device, and more particularly, it relates to a redundant structure for defect repair in a semiconductor memory device and a structure for simplifying a test therefor.
2. Description of the Background Art
FIG. 28 is an explanatory diagram schematically showing the structure of a conventional dynamic semiconductor memory device (DRAM) having a plurality of dynamic memory cells. As shown in FIG. 28, a memory cell array 10 is divided into a plurality of (eight in FIG. 28) normal cell array blocks BLK1 to BLK8. Sense amplifier zones SRi and SR(i+1) formed with sense amplifiers (not shown) are provided on both sides (vertical direction in FIG. 28) of each normal cell array block BLKi (i=1 to 8), and each sense amplifier zone SRj (j=2 to 8) is shared by normal cell array blocks BLK (j-1) and BLKj.
A column decoder CD is provided for the memory cell array 10, and row decoders RD1 to RD8 are provided for the normal cell array blocks BLK1 to BLK8 respectively. Each normal cell array block BLKi (i=1 to 8) is provided therein with memory cells (not shown in FIG. 28) which are arranged in the form of a matrix, word lines (not shown) for selecting rows of the memory cells, and bit lines (not shown) for reading/writing data from/in the memory cells.
FIG. 29 is an explanatory diagram for illustrating a redundant structure for defect repair in the aforementioned dynamic semiconductor memory device. As shown in FIG. 29, a memory cell array 1 further comprises a spare cell array block SBLK which is identical or similar to each normal cell array block BLKi and a row decoder SRD1 for the spare cell array block SBLK. Referring to FIG. 29, the sense amplifier zones SR1 to SR9 and the column decoder CD shown in FIG. 28 are omitted for convenience of illustration.
When a memory cell provided in any block BLKp (p=any of 1 to 8) includes a defect in the aforementioned structure, the defective normal cell array block BLKp is electrically replaced with the spare cell array block SBLK by a laser fuse program system or the like, for repairing the defect.
FIG. 30 is an explanatory diagram showing another exemplary redundant structure for defect repair in relation to the dynamic semiconductor memory device. As shown in FIG. 30, a memory cell array 2 consists of a normal cell array 3 having generally used memory cells, and spare row and column cell arrays 4 and 5 having memory cells for defect repair of the normal cell array 3.
The spare row and column cell arrays 4 and 5 have spare memory cells provided on a spare row and a spare column respectively, and the spare memory cells of the spare row and column cell arrays 4 and 5 are formed on the same columns and rows as the memory cell columns and rows of the normal cell array 3 respectively.
When any memory cell provided in the normal cell array 3 includes a defect in the aforementioned structure, the defective memory cell is electrically replaced with a memory cell provided on the spare row or column of the spare row or column cell array 4 or 5 by the laser fuse program system or the like, for repairing the defect.
In the conventional dynamic semiconductor memory device having the aforementioned structure, the defect cannot be effectively repaired by a general hard error defect repair system if the spare cell array block SBLK or the spare row or column cell array 4 or 5 includes a memory cell having inferior data holdability (data retention ability).
While the data retention ability of the spare row or column cell 4 or 5 or the spare cell array block SBLK may be tested for thereafter repairing the defect in order to solved the aforementioned problem, the time for the data retention ability test is so long that the capacity of a fail memory of a test circuit necessary for storing defect repair information is disadvantageously increased. Thus, this method is impractical.
USPTO Backgrounds
USPTO Backgrounds