This invention generally relates to methods for processing semiconductor wafers and more particularly to a method and apparatus for burning-in or stressing an entire wafer or some portion thereof.
Semiconductor lasers are widely used in applications such as optical communications. The edge emitting laser diode is a semiconductor laser that emits light from a plane that is a continuation of the p-n junction of the diode. Cleaved surfaces at the ends of the diode act as mirrors that together define an optical cavity. Optical feedback provided by the cleaved mirrors creates a resonance of the emitted light that results in lasing. Because of this, the wafer must be cleaved prior to testing or stressing of the devices.
The vertical cavity surface emitting laser (VCSEL) is another type of semiconductor laser in which the optical cavity is normal to the p-n junction of the semiconductor wafer from which it was fabricated. Ordinarily VCSELs are manufactured with many layers of semiconductor material deposited upon the substrate. VCSELs typically include highly reflective optical mirrors above and below the active layer which, in contrast to the edge emitting laser, enable laser output normal to the surface of the wafer. As a result, a VCSEL may be tested or stressed while the wafer is intact. VCSELs are also efficient, small in size, readily assembled into arrays, and easy to manufacture.
Therefore, VCSELs have become preferred in today""s optoelectronics. Because of their complexity, however, existing processes for manufacturing edge emitters or VCSELs do not always yield devices with consistent characteristics. The process involves many layers that depend on numerous parameters including, but not limited to, doping concentration, substrate temperature, material sources, and growth rate.
Therefore, manufacturers of semiconductor lasers often use a burn-in procedure to cause device performance characteristics to stabilize and to induce early failure of weak devices. Both of these effects usually occur sometime after power has been applied to the device under operating conditions. Burn-in testing is typically conducted on individual active devices at elevated temperatures for prolonged periods of time (e.g., 40-80 hours). This requires the expenditure of additional time to fully verify each of a large number of active devices on a wafer or the development of a relatively complicated and costly probe assembly with numerous contact electrodes that may individually contacting each of the active devices on the wafer.
Ideally, burn-in stressing is conducted prior to integrating the device into a sub-assembly, module or system. This is because at each higher level of integration, the cost of a latent failure increases. For example, a latent failure on single device results in only a minor cost. However the failure of a single device in a subassembly may result in the rejection of the entire subassembly, at a cost many times that of the VCSEL die. Likewise, the failure of a single device in a module results in the rejection or rework of the entire module, at a cost many times that of the subassembly.
In one aspect of the present invention a method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers. The interconnect layers may separately couple at least a portion of the anodes of the active devices together and or at least a portion of the cathodes of the devices together. A simplified probed pad, having a reduced number of contacts may then be utilized to apply a substantially constant voltage or current to the devices. In another aspect of the present invention device or array level resistors may be integrated in series with the active devices to mitigate the effects of short circuits or open circuits on the processing of the devices.
In another aspect of the present invention a process for burning in a wafer having a plurality of active device, wherein each device has a first and a second electrode, includes depositing an insulator layer adjacent one side of the wafer. Vias may be formed in the insulator layer to provide access to at least one of the electrode of the active devices., A conductive interconnect layer may be deposited adjacent the insulator layer, wherein said conductive interconnect layer is electrically couples together at least the first electrode of at least a portion of the active devices.
In another aspect of the present invention a method for burning in a wafer having a plurality of active device, wherein each device has a first and second electrode, includes depositing an insulator layer adjacent one side of the wafer, forming a conductive interconnect layer adjacent the insulator layer. The conductive interconnect layer may be processed to form a plurality of first electrode contact traces wherein each of the first electrode contact traces separately couples together the first electrode of each active device within an array. The conductive interconnect layer may be further processed to form a plurality of second electrode contact traces wherein the second electrode contact traces simultaneously couple together the second electrode of at least a portion of said active devices.
USPTO Backgrounds
USPTO Backgrounds