Semiconductor memories are used to store and retrieve large quantities of digital data at electronic speeds. Semiconductor memory features are continually being scaled down in size to integrate greater numbers of memory cells into a single chip. A typical semiconductor memory consists of an array of memory cells organized in rows and columns. Typically, the memory cells are connected along the rows through word lines, and along the columns through bit lines. Each memory cell therefore has a unique memory location, or address, which can be accessed through selection of the appropriate word and bit line, for the purpose of either reading or writing data. The contents of all of the memory array cells can be erased simultaneously in flash memories, e.g., flash EEPROMs, through the use of an electrical signal.
FIG. 1 shows a cross sectional view 100 of a typical flash EEPROM cell. Two layers of polysilicon separated by an interpoly dielectric layer 104 form a control electrode 105 over a floating gate 103, as shown in FIG. 1. Floating gate 103 is deposited on a gate oxide 102 on a p-type silicon substrate 101. N+-type source and drain regions 106 are formed in substrate 101 at opposite sides of floating gate 103. Floating gate 103 does not have an electrical connection, and is capacitively coupled to control gate 105 through interpoly dielectric layer 104. Currently, a gate coupling ratio of control gate 105 to floating gate 103 (“GCR”) is only about 50% to 60%. That is, out of, e.g., 10 volts applied to control electrode 105, only 5-6 volts is coupled to floating gate 103 that limits the performance of a memory cell. Typically, to increase the coupling ratio of control gate 105 to floating gate 103, the thickness 108 of floating gate 103 is increased. That increases the surface area that couples floating gate 103 to control gate 105 through a wrap around feature. In a memory array, however, the increased thickness of floating gate 103, invokes a parasitic floating gate to floating gate coupling of adjacent memory cells, for example, across a word line.
Additionally, the parasitic floating gate to floating gate coupling between adjacent memory cells increases as feature sizes of memory integrated circuits decrease to incorporate more memory cells into a single chip. The parasitic floating gate- to- floating gate coupling between gates of adjacent memory cells severely impacts the operation of a memory integrated circuit.
USPTO Backgrounds
USPTO Backgrounds