With the spread of mobile telephones, portable computers and other small electronic equipment, the demand for the semiconductor devices mounted on them to be smaller and thinner has increased. BGA packages and CSP packages have been developed and put into use to respond to such demand.
Patent Citation 1 relates to a molding die for resin molding an article to be molded, wherein multiple semiconductor chips are mounted in a matrix form on one surface of a substrate, and a resin molding method using said molding die. FIG. 15(b) illustrates a QFN (Quad Flat Non-leaded) type of semiconductor package. Semiconductor chips 52 are mounted in a matrix form on die pad parts 57 on one surface of lead frame 56, which is the article to be molded. Each semiconductor chip 52 and the peripheral lead part 58 are wire bonded, and the electrode part of semiconductor chip 52 and one surface of lead part 58, which is the terminal connection part, are electrically connected by bonding wire 54. Semiconductor chips 52 mounted in a matrix form are housed in cavity recess 60 when resin substrate 51 or lead frame 56 is mounted in lower mold 59. Resin substrate 51 or lead frame 56 is clamped by upper mold 61 and lower mold 59 at the substrate peripheral edge, cavity recess 60 is filled with mold resin through lower mold runner gate 62, and one surface is resin molded all at once. After resin molding, the molded article (resin substrate 51 or lead frame 56) is diced for individual semiconductor chips, cut into individual pieces, and semiconductor devices are manufactured. (C) is a dice cutter line.
Patent Citation 1
Japanese Kokai Patent Application No. 2003-234365
FIG. 16 is a figure explaining the semiconductor device molding process used for a conventional POP. In the figure, only one representative semiconductor chip is shown, but multiple semiconductor chips are mounted on substrate 70 and liquid resin is supplied to cover each semiconductor chip. Substrate 70 on which semiconductor chip 72 is mounted is guided by guide pin 76 of lower cavity block (lower die) 74 and is mounted on said block. The material of lower cavity block 74 is steel, and its surface is treated by hard chrome plating. Next, an upper die 80 in which a shape-forming part (recess) 78 is formed is pressed onto lower cavity block 74, and liquid resin on the substrate is molded at or below a constant temperature. In order to improve the releasability of mold resin 82 from upper die 80, a release film 84 is used between upper die 80 and substrate 70. Release film 84 is a plastic, polymer film that is electrically insulating and heat-resistant, and the liquid resin is molded while it is tightly adhered to shape-forming part 78 of upper die 80.
With a multilayer circuit board 70 for the POP, a land 86 is a conductive material such as Cu is formed on the substrate surface. Land 86 is exposed to the outside from mold resin 82, and when another semiconductor substrate is stacked, will be connected to its terminal. Land 86 is also electrically connected to a wiring pad 88, bonding wire 90 or the like in mold resin 82. At the same time, a conductive region 92 of Cu or the like for connecting a terminal, such as a solder ball, is formed on the reverse surface of the substrate. Conductive region 92 on the substrate reverse surface is electrically connected to land 86 or semiconductor chip 72 on the substrate front surface through a via contact in the substrate.
When liquid resin supplied onto the substrate is molded through the medium of release film 84, release film 84 is charged with about 20 KV of static electricity. When upper die 80 is released in this state, the static electricity charged release film 84 is discharged into lower cavity block 74 through semiconductor chip 72, and the integrated circuitry in the semiconductor chip is electrostatically destroyed. That is, release film 84 is touching land 86 exposed at the substrate surface, so the electrostatic charge in release film 84 passes from land 86 through the inside of semiconductor chip 72 via wiring pad 88 and bonding wire 90 in resin 82, again passes through land 86, the via contact in the substrate and conductive region 92 on the substrate reverse surface from bonding wire 90 and flows to lower cavity block 74. Because of this, the circuitry of semiconductor chip 72 maybe destroyed electrostatic discharge. The result is that the semiconductor device yield drops, and reducing the manufacturing cost is difficult.
The present invention solves the aforementioned conventional problems. Its objective is to provide a semiconductor manufacturing device and a semiconductor manufacturing method with which electrostatic destruction of semiconductor chips during molding can be effectively prevented.
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