1. Field of the Invention
This invention relates to content addressable memory (CAM). In particular, the invention relates to CAM access.
2. Description of Related Art
When a memory region or memory block is accessed by multiple processors or agents, it is commonly necessary to provide a locking and unlocking structure to allow orderly accesses. When an agent or thread attempts to use a memory block, it has to determine if the block is free or available and if it can enter the memory block. If not, it has to wait until the block becomes available. When an agent finishes using the memory block, it updates the unlocking mechanism to unlock the memory block indicating to other threads that the memory block now is available.
A typical technique is to provide a fixed number of entries in a lock content addressable memory (CAM) and a fail queue. When the entries in the lock CAM are used up, subsequent requests will have to be placed in the fail queue waiting for their turns. If a request has to wait behind other requests requesting different memory blocks in the fail queue, there is a possibility that this request has to wait for a long time for an entry in the lock CAM even though the other requests and this request access to different memory blocks. Techniques to resolve this problem includes the use priority encoder. However, these techniques have a number of drawbacks. First, the processing speed is significantly impacted by the size of the CAM. Second, the test cases for the priority scheme may become prohibitively large. Third, the number of clock cycles for the lock and/or unlock operation may be high.
Therefore, there is a need to have a technique to provide efficient memory accesses from multiple agents or processors.
USPTO Backgrounds
USPTO Backgrounds