1. Technical Field
The present disclosure relates to a wiring board, and a semiconductor device.
2. Description of the Related Art
A wiring board in which a plurality of wiring layers and a plurality of insulating layers are formed alternately by a buildup method in order to increase a density of a wiring pattern has been heretofore known as a wiring board on which an electronic component such as a semiconductor chip is mounted. As this type of wiring board, a wiring board in which a high-density wiring layer including insulating layers made of a photosensitive resin is formed on a low-density wiring layer including insulating layers made of a thermosetting resin has been proposed (e.g. see JP-A-2015-191968).
FIG. 13 shows an example of a related-art wiring board. The wiring board 200 has a low-density wiring layer 201, a solder resist layer 202 which is formed on a lower surface of the low-density wiring layer 201, and a high-density wiring layer 203 which is formed on an upper surface of the low-density wiring layer 201. The low-density wiring layer 201 has a structure in which a wiring layer 211, an insulating layer 212, a wiring layer 213, an insulating layer 214, a wiring layer 215, and an insulating layer 216 are formed in the named order. Each of the insulating layers 212, 214 and 216 is made of an insulating resin containing a thermosetting resin as a main component. The high-density wiring layer 203 has a structure in which a wiring layer 220, an insulating layer 221, a wiring layer 222, an insulating layer 223, a wiring layer 224, an insulating layer 225, and a wiring layer 226 are formed on an upper surface of the insulating layer 216 in the named order. Each of the insulating layers 221, 223 and 225 is made of an insulating resin containing a photosensitive resin as a main component.
Since a core substrate (support substrate) having high rigidity and thicker than the insulating layer 212, 214 or 216 etc. is not provided in such a wiring substrate 200, the wiring board 200 as a whole can be made thin.
In the wiring board 200, for example, the wiring layer 211, the insulating layer 212, and the solder resist layer 202 differ from one another in thermal expansion coefficient. Moreover, in the wiring board 200, the wiring layer 211 is formed on a lower surface of the insulating layer 212, and an interface between the insulating layer 212 and the solder resist layer 202 is present in corner portions A2 of the wiring layer 211. When thermal stress occurs in such a wiring board 200 due to heating treatment etc., stress is concentrated in the vicinities of the corner portions A2 of the wiring layer 211 and cracking etc. occurs easily in respective interfaces among the wiring layer 211, the insulating layer 212 and the solder resist layer 202.
USPTO Backgrounds
USPTO Backgrounds