In the efforts for optimizing and improving operation in various high-speed microcontroller-based devices, such as various instrumentation and measurement equipment and the like, significant attention has been given to the further improvement of the high-speed amplifiers utilized. One category of high-speed amplifiers commonly utilized is transimpedance amplifiers. In some high-performance instances, such transimpedance amplifiers are configured with a composite amplifier arrangement, for example with a high-speed amplifier combined with a lower speed auto-zero amplifier.
For example, with reference to FIG. 1, a prior art composite amplifier circuit 100 is illustrated that comprises a high-speed amplifier 102 and a lower-speed, e.g., an auto-zero, amplifier 104. High-speed amplifier 102 is configured for providing an output voltage at output terminal VOUT. The inverting input terminal of amplifier 102 is configured to provide a negative input terminal INN for composite amplifier circuit 100. Auto-zero amplifier 104 together with a resistor R0 and a capacitor C0 comprise an integrator circuit. With low frequency signals provided through the integrator circuit comprising auto-zero amplifier 104, resistor R0 and capacitor C0,
low DC offset and low 1/f noise is generally realized. A non-inverting input terminal of auto-zero amplifier 104 is configured to provide a positive input terminal INP for composite amplifier circuit 100. An output terminal of auto-zero amplifier 104 is coupled to a non-inverting input terminal of amplifier 102 through a first order low-pass filter comprising resistor R1 and capacitor C1 configured at the output terminal of auto-zero amplifier 104. The low-pass filter is configured to reduce noise from auto-zero amplifier 104, including auto-zero switching noise.
In many applications, it is highly desirable for composite amplifier circuit 100 to provide a fast settling time, which is defined as the amount of time for composite amplifier circuit 100 to finally settle to an ideal final amplified signal at output terminal VOUT corresponding to a given input signal provided to input terminals INN and INP. For faster settling times in composite amplifier circuit 100, the frequency response is configured to provide a single-pole response. However, the overall frequency response tends to fluctuate due to pole-zero doublets, thus resulting in a dramatic slowing down of the settling time to a high precision of composite amplifier circuit 100.
For example, with reference to FIG. 2A, a diagram illustrates an output signal at output terminal VOUT based on a step input signal configured to provide an ideal final value 4.00000 volt signal. As realized by a “zoomed-in” view illustrated in FIG. 2B, upon receiving the step input signal, the output signal of composite amplifier circuit 100 immediately settles to within 0.1% accuracy; however circuit 100 requires approximately another 1 mS before the output signal reaches within 0.001% accuracy.
A main reason for the slower settling time is due to the existence of a slow path for certain signals to pass through to output terminal VOUT, as well as difficulties in zero-pole cancellation. For example, for a large step at output terminal VOUT, a small voltage is required at input terminal INN. This small voltage causes a current through resistor R0 of the integrator circuit. This same current also passes through capacitor C0 that provides a slow path. This slower settling time can be further exacerbated by process variations on the various resistors and capacitors, as well as the amplifier gains, realized in composite amplifier circuit 100. Thus, while composite amplifier circuit 100 can provide a good DC response, due to difficulties in pole-zero cancellation and the slower path, any step responses for composite amplifier circuit 100 will not completely settle until the integrator loop has settled to a final value.
USPTO Backgrounds
USPTO Backgrounds