Many electronic systems use memory to store information. Memory devices include an interface to communicate with other elements of the system. An ordinary interface provides several inputs and outputs, including various bus connections to accommodate multi-bit transfers in parallel. In particular, memory devices typically include a command bus and an address bus that transmit command and address information from a controller to the memory device.
For example, many existing DRAM devices include a command/address bus having three command signals, ordinarily row address strobe (RAS), column address strobe (CAS), and write enable (WE), and several address signals, including row/column address (A[X:0]), bank address (BA[1:0]), and chip select (CS). The command signals decode yielding several commands, such as ACTIVATE ROW, COLUMN SELECT with WRITE/READ, PRECHARGE ROW, PRECHARGE ALL, AUTO REFRESH, SELF REFRESH, WAKE, LOAD MODE, and LOAD EXTENDED MODE.
Certain access processes saturate the command/address bus, limiting the throughput/bandwidth of the memory device. For example, referring to FIG. 9 illustrating a simplified memory access process, if the addressing patterns dictate all page misses, each burst transfer operation 900 of data to/from the memory devices requires one ACTIVATE command 910 for the row address 911 and one READ or WRITE command 912 corresponding to the column address data 913. Bank selection data is transferred via a bank selection bus 924. A PRECHARGE command 914 for the selected bank 915 is then asserted to close the selected bank. If the burst size does not allow time for three commands, however, the data transfer rate is throttled. A common example is a burst size of four data bus transfers 916A-D with the data bus 920 running at double the rate of the command/address bus 922. This is a simplified, illustrative example, for memory accesses typically utilize interleaved commands to the various banks to optimize the operation of the memory system, but it serves to illustrate that each data bus burst transfer operation 900 provides two command/address slots 910, 912. Because three commands are required to effect the transfer, however, the data bus efficiency may be reduced to two-thirds of its capacity.
USPTO Backgrounds
USPTO Backgrounds