The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for providing low latency memory access control for non-volatile memories.
Various volatile and non-volatile memory technologies have been developed to improve modem computing devices. One example of a volatile memory, i.e. a memory in which the contents of the memory are lost when power to the memory is discontinued, is a Dynamic Random-Access Memory (DRAM). One example of a non-volatile memory, i.e. a memory in which the contents of the memory are not lost when power to the memory is discontinued, is a Magnetoresistive Random-Access Memory (MRAM).
Many modern computing devices use DRAM structures, such as in a main memory, system memory, cache memory, or other memory structures of the computing device. DRAM is a type of volatile random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since capacitors leak charge, the information in the DRAM cells eventually fades unless the capacitor charge of the DRAM cells is refreshed periodically. Because of this refresh requirement, DRAM is “dynamic” memory as opposed to static random access memory (SRAM) which is “static.” The advantage of DRAM over SRAM is that it only requires one transistor and a capacitor per bit of data that is stored as opposed to six transistors in an SRAM per bit of data. This allows DRAM to reach very high density.
Refreshing DRAM cells may be performed on a periodic basis, such as at a predetermined refresh interval. The refreshing of DRAM cells may also occur, for example, in response to the reading of data out of the DRAM cells. That is, a typical read of a portion of a DRAM structure involves reading out the data from the DRAM cells, which effectively deletes the contents of the DRAM cells due to the loss of charge from the reading operation, with a subsequent rewriting of the data back into the same DRAM cells. Thus, each read of a DRAM structure involves the sensing of charge in the DRAM cells with a subsequent recharging of the DRAM cells to their previous state by rewriting the data back into the DRAM cells, consuming power and leading to a source of inefficiency in operation.
Unlike conventional RAM technologies, such as DRAM, data in MRAM is not stored as electric charge or current flows, but is stored using magnetic storage elements. The elements are formed from two ferromagnetic plates, separated by a thin insulating layer, and the resultant magnetic field. One of the two ferromagnetic plates is a permanent magnet set to a particular polarity while the other plate's magnetic field can be changed to match that of an external field to store memory. This configuration is known as a spin valve and is the simplest structure for an MRAM bit. A memory device is built from a gridded array of such “cells” similar to a DRAM. Since the MRAM stores data using magnetic storage elements, the MRAM is a non-volatile memory structure as opposed to the volatile memory structure of a DRAM.
USPTO Backgrounds
USPTO Backgrounds