This invention relates to an ultrahigh-speed semiconductor memory device with high-density circuit integration and more specifically to a Bipolar CMOS dynamic RAM (BiCMOS DRAM).
The conventional method of isolating devices from one another in BiCMOS DRAM is discussed in the IEDM Technical Digest 1986, in pages 802 to 804.
The above conventional technique employs a reverse-biased p-n junction for device isolation, especially for isolating bipolar transistors from one another.
In a typical construction of a semiconductor device formed by such a technique, an n-type epitaxial layer is grown on a p-type substrate, and a p-type impurity for device isolation is diffused into the n-type epitaxial layer to a depth reaching the p-type substrate, thus forming a large number of isolated n-type islands on the p-type silicon substrate.
This method of device isolation by use of a p-n junction increases the parasitic capacitance of the bipolar transistor and particularly the capacitance between the collector and the substrate, and this has been an obstacle to improving the operation speed.
As a method of reducing the parasitic capacitance, a so-called U-isolation or trench isolation is used, in which a trench formed for device isolation is filled with silicon dioxide SiO.sub.2 or polycrystalline silicon. This trench is also used for forming capacitance. An example of forming capacitance by using a trench is given in the Japanese Patent Application Laid-Open No. 226657/1987.
These trench constructions, however, have problems such as a high possibility of deformation when stress concentrates at the trench, a reduction in yield and reliability, and a cost increase.
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USPTO Backgrounds