1. Field of the Invention
The present invention relates to a method of fabricating a capacitor of a memory cell and, more particularly, to a method of fabricating a memory cell capacitor having a larger capacitance.
2. Discussion of Related Art
As semiconductor memory devices become highly integrated, the area occupied by a memory cell is reduced. Generally, the reduction of the cell size results in the decrease of the effective area of a storage capacitor of the cell. This reduces its capacitance. In a dynamic random access memory (DRAM) cell, the reduction of its capacitance increases soft error or deteriorates the refreshing function of its cell. Accordingly, studies have been carried out for the purpose of increasing the cell capacitance through the extension of the effective area of the cell. Increasing the cell capacitance is an important factor in the high integration of semiconductor memory devices. Structures for extending the effective area of a capacitor include a stacked structure and a trench structure. The stacked structure is formed in such a manner that several layers of capacitors are stacked on a semiconductor substrate. In the trench structure, a trench is formed in a semiconductor substrate and a capacitor is formed in the trench.
A conventional method of fabricating a capacitor of a memory cell will be explained now with reference to the accompanying drawings. FIGS. 1A to 1F are cross-sectional views showing a conventional method of fabricating a fin-structured stacked capacitor. As shown in FIG. 1A, a field oxide layer 101 is formed on a p-type silicon substrate 100. A gate insulating layer 102, a polysilicon layer 103 and a cap insulating layer 104 are sequentially formed on the substrate 100, and selectively etched through photolithography to form a gate electrode. Then, n-type impurities are ion-implanted into the substrate at a low concentration. A chemical vapor deposition (CVD) oxide layer is formed on the overall surface of the silicon substrate 100, and etched through photolithography to form sidewall spacers 105 on the sides of the gate electrode. Thereafter, n-type impurities are ion-implanted into the substrate at a high concentration to thereby form source and drain regions 106.
As shown in FIG. 1B, an etch stop layer 107, a first insulating layer 108, a first storage node polysilicon layer 109 and a second insulating layer 110 are sequentially formed on the overall surface of the silicon substrate 100. The etch stop layer 107 is formed of silicon nitride. As shown in FIG. 1C, a storage node contact region of a capacitor is defined, and then the second insulating layer 110, first storage node polysilicon layer 109, first insulating layer 108 and etch stop layer are selectively removed to expose the storage node contact region.
As shown in FIG. 1D, a second storage node polysilicon layer 111 is deposited on the overall surface of the second insulating layer 110 including the exposed portion of the substrate. Then, as shown in FIG. 1E, the second and first insulating layers are removed through an etching process to thereby form a storage node electrode consisting of the first and second storage node polysilicon layers 109 and 111. Thereafter, as shown in FIG. 1F, a dielectric layer 112 is formed on the overall surface of the storage node electrode. A conductive layer 113, such as a polysilicon layer, is formed on the overall surface of the dielectric layer 112 and patterned to form a plate electrode.
In the aforementioned fin-structured capacitor, as the cell area is reduced, a multilevel storage electrode is required to maintain its capacitance. This results in poor topography in the memory cell. Accordingly, the reliability of the memory device is deteriorated.
USPTO Backgrounds
USPTO Backgrounds