The importance of integrating different materials and different device functions, a process generally termed heterogeneous integration, is widely recognized. So too are the problems inherent in combining different materials. Principal amongst those problems is that of thermal expansion coefficient differences because the thermal expansion mismatch between silicon, the primary material of interest for large-scale high-density integrated circuits, and III-V compounds, the materials of interest for optoelectronic and microwave devices and circuits, is very large. The difference between the thermal expansion coefficient of GaAs, for example, and the thermal expansion coefficient of Si exceeds 4×10−6° C.−1.
To put this in perspective, the diameters of GaAs and Si wafers that are identical at room temperature (150 mm) will differ by 70 μm at 100° C. Such large mismatches make it difficult to grow device-quality III-V heterostructures directly on silicon wafers, or to bond full wafers of III-V devices with full silicon integrated circuit wafers.
Several methods have been proposed for fabricating individual electronic components (or generally microstructures) and assembling such structures onto a substrate. One approach is to grow GaAs devices directly onto a silicon substrate. This approach becomes limiting because the lattice structure of GaAs mismatches that of silicon. In addition, growing GaAs onto silicon is inherently difficult and therefore costly. Accordingly, GaAs or InP cannot efficiently be grown on a silicon substrate.
However, for the most part, heterogeneous integration today is done by using some variation of flip-chip solder-ball (or solder-bump) bonding to attach modest size arrays of, for example, vertical-cavity surface emitting lasers (VCSELs) on individual integrated circuit chips. This approach works, but it also has serious limitations.
In particular, the size of the device array that can be bonded depends on the bonding temperature, and is typically limited to a centimeter on a side. Also, for the best results, the substrate of the device array must be thinned and, ideally, totally removed leaving the device in the array separated one from the other. This involves extensive additional processing. Finally, because the industry standard for silicon integrated circuit wafers is 200 mm in diameter, and for GaAs wafers it is 150 mm, bonding full wafers is impractical. One is forced to bond pieces of wafers and to use a tiling process to cover a full wafer.
Another approach to heterogeneous integration is called the optical solder bump process. The essential approach of the optical solder bump process is to put compound semiconductor heterostructures in recesses in the surface of commercially-processed integrated circuit wafers and to then fabricate those heterostructures into devices (typically, but not exclusively, optoelectronic devices) monolithically integrated with the pre-existing VSLI-level electronic circuitry.
An alternative approach to bonding ensembles of devices that are then divided into individual devices is to begin with individual devices and to attach each in its proper place on the integrated circuit surface. Such an approach sounds impractical at first, but upon further thought one realizes that it offers significant advantages once the assembly process is perfected. It circumvents the problem of smaller compound semiconductor wafer sizes, it can be used with any material with minimal concern with thermal expansion coefficient, and it can be used to assemble several different types of devices on a single substrate.
Two approaches of this type are the DNA and electrophoresis-assisted assembly techniques, and the fluidic self-assembly technique. These techniques each involve the location and attachment of many individual units on processed integrated circuits (or other electronic substrates), and their subsequent electrical interconnection. The individual units may be single devices, small assemblies of devices, or full integrated circuits.
In the DNA and electrophoresis-assisted assembly approach, a DNA-like polymer film is put on the individual units and a complementary film is patterned on the circuit (or a handle wafer) surface where the units are to be placed. The attraction between the two complementary DNA films then locates and holds the units in position. Electrophoresis can also be used to attract and locate device units in place on a surface electrode pattern.
In the fluidic self-assembly approach, the individual units are etched to have slanted slides which match the size and shape of recesses formed in the substrate, the idea being that the units only fit in the recesses in one way. A fluid carrying many units is flowed over the surface of the substrate, and gravity is relied upon to get the units into the recesses and to hold them there.
Another approach is described by Yando in U.S. Pat. No. 3,439,416. Yando describes components or structures placed, trapped, or vibrated on an array of magnets. Such magnets include magnetized layers alternating with non-magnetized layers to form a laminated structure. Components are matched onto the array of magnets forming an assembly thereof. However, severe limitations exist on the shape, size, and distribution of the components. Component width must match the spacing of the magnetic layers and the distribution of components are constrained by the parallel geometry of lamination. In addition, self-alignment of components requires the presence of the laminated structure. Furthermore, the structures disclosed by Yando typically possess millimeter-sized dimensions and are therefore generally incompatible with micron sized integrated circuit structures. Accordingly, the method and structure disclosed by Yando is thereby too large and complicated to be effective for assembling a state-of-art microstructure or component onto a substrate.
Another approach involves mating physical features between a packaged surface mount device and substrate as described in U.S. Pat. No. 5,034,802, Liebes, Jr. et al. The assembly process described requires a human or robotics arm to physically pick, align, and attach a centimeter sized packaged surface mount device onto a substrate. Such a process is limiting because of the need for the human or robotics arm. The human or robotics arm assembles each packaged device onto the substrate one-by-one and not simultaneously, thereby limiting the efficiency and effectiveness of the operation. Moreover, the method uses centimeter sized devices (or packed surface mount integrated circuits), and would have little applicability with micron sized integrated circuits in die form.
Another approach, such as the one described in U.S. Pat. No. 4,542,397, Biegelsen et al. involves a method of placing parallelogram shaped structures onto a substrate by mechanical vibration. Alternatively, the method may also employ pulsating air through apertures in the support surface (or substrate). A limitation to the method includes an apparatus capable of vibrating the structures, or an apparatus for pulsating air through the apertures. Moreover, the method described relies upon centimeter-sized dies and would have little applicability with state-of-art micron sized structures.
A further approach such as that described in U.S. Pat. No. 4,194,668 by Akyurek discloses an apparatus for aligning and soldering electrode pedestals onto solderable ohmic anode contacts. The anode contacts are portions of individual semiconductor chips located on a wafer. Assembling the structures requires techniques of sprinkling pedestals onto a mask and then electromagnetic shaking such pedestals for alignment. The method becomes limiting because of the need for a shaking apparatus for the electromagnetic shaking step. In addition, the method also requires a feed surface gently sloping to the mask for transferring electronic pedestals onto the mask. Moreover, the method is solely in context to electrode pedestals and silicon wafers, thereby limiting the use of such method to these structures.
Still another approach requires assembling integrated circuits onto a substrate through electrostatic forces as described in U.S. Pat. No. 5,355,577 to Cohn. The electrostatic forces vibrate particles such that the particles are arranged at a state of minimum potential energy. A limitation with such method includes providing an apparatus capable of vibrating particles with electrostatic forces. Moreover, the method of Cohn creates damage to a portion of the integrated circuits by mechanically vibrating them against each other and is also generally ineffective. Accordingly the method typically becomes incompatible with a state-of-art microstructure.
In another approach, to assemble GaAs microstructures onto a silicon wafer, trapezoidal shaped GaAs blocks self-align into inverted trapezoidal shaped recessed regions located on the top surface of the silicon wafer. Steps for such a process include forming the GaAs blocks, transferring the GaAs blocks into a solution forming a slurry, and spreading the slurry evenly over the top surface of a silicon substrate having recessed regions. During the spreading steps, the GaAs blocks self-align and settle into the recessed regions while being transported with the fluid across the top surface. A limitation with such method is the lack of a mechanism to keep the trapezoidal shaped GaAs blocks in the inverted trapezoidal shaped recessed regions of the surface once the GaAs blocks are aligned with the recesses. As the slurry moves over the surface of the silicon wafer, the trapezoidal shaped GaAs blocks may disengage from the inverted trapezoidal shaped recessed regions and become part of the slurry again, thereby reducing the effectiveness of this approach.
A further approach to assembling microstructures onto a substrate, Epitaxy-on-Electronics, is illustrated in FIGS. 1-3. As illustrated in FIG. 1, upon a GaAs wafer 1, GaAs MESFET circuitry 3 with multi-layer interconnects is formed. The GaAs wafer 1 further includes a dielectric growth well or recess 5 that includes an n+ region 7 at its base. Upon the GaAs MESFET circuitry 3, as shown in FIG. 2, a polycrystalline 9 is deposited and an epitaxial heterostructure 11 is formed in the dielectric growth well or recess 5. A monolithically integrated surface emitting diode is formed from the epitaxial heterostructure 11, as illustrated in FIG. 3, and thereafter a glass overlay 13 is formed over the entire surface.
The integrated circuits in the Epitaxy-on-Electronics process, as illustrated in FIGS. 1-3, are GaAs integrated circuits because the recesses 5 in the dielectric penetrate all of the way to the substrate 1 and the heterostructures 11 are formed in the recesses 5 by direct Epitaxy.
Epitaxy-on-Electronics is a very effective technique, but it does have limitations. First, it requires epitaxy on the integrated circuit substrate, which, as a practical matter, means that Epitaxy-on-Electronics cannot be used with silicon integrated circuits for the majority of heterostructure devices of interest. The epitaxy must also be done at less than 500° C. to avoid damaging the preexisting electronics, and this, and the semi-insulating IC substrate itself, can place a limitation on material quality.
To get around some of the limitations of the Epitaxy-on-Electronics process the aligned pillar bonding technique (APB) was developed. The aligned pillar bonding process is illustrated in FIGS. 4-8.
In the aligned pillar bonding process, as illustrated in FIG. 4, a wafer 21 has formed thereupon electronics 23 and a recess or well 25. The compound semiconductor heterostructures 29 are grown, as shown in FIG. 5, on optimal substrates 27 under optimum conditions. The compound semiconductor heterostructures 29 are then etched into a pattern of pillars mirroring the pattern of recesses 25 on the integrated circuit wafer 21. The etched compound semiconductor heterostructures 29 are aligned, as shown in FIG. 6, with the recesses 25 using techniques common to MEMS processing. The etched compound semiconductor heterostructures 29 are then bonded into position, as shown in FIG. 7, by a semiconductor-to-metal bond. Lastly, in FIG. 8, further processing of the bonded semiconductor heterostructures 29 produce an integrated photodiode with a dielectric overcoat 31 thereon.
The heterostructure and IC substrates must have matching thermal expansion coefficients if the aligned pillar bonding process is to be performed over large areas, i.e., on a full wafer scale, and this in turn means that the IC must be fabricated using a GaAs or a Si-on-sapphire process. Aligned pillar bonding process thus does allow access to silicon circuitry, but it does not take advantage of the very large diameter Si wafers that are available because it is limited by the diameter of the heterostructure substrate. It also, of course, can only be used with standard silicon CMOS, for example, if used on partial wafers.
Therefore, it is desirable to develop a method of assembling microstructures onto a substrate that is compact, low cost, efficient, reliable, and requires little maintenance. Moreover, it is desirable to develop a method of assembling microstructures onto a substrate that can be done in such a manner to avoid damaging the preexisting electronics. Furthermore, it is desirable to develop a method of assembling microstructures onto a substrate that takes advantage of the very large diameter Si wafers.
USPTO Backgrounds
USPTO Backgrounds