FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing a design, performing synthesis, placement, and routing on a system design can be the most challenging and time consuming. The complexity of large systems often requires the use of EDA tools that utilize algorithms that assist in determining which components to use in a system design and how to map the components onto a physical target device. These algorithms allow the system design to satisfy area and timing constraints.
Although the design process is automated with EDA tools, generating a satisfactory system design may still be time consuming. It is an ongoing effort for EDA tool designers to shorten the runtime of its algorithms. By shortening the runtime of its algorithms, more flexibility may be offered to the system designer using the EDA tool and/or additional algorithms may be implemented in the EDA tool in order to further improve a system design.
In FPGA design, system designs are very structured in nature. It is not uncommon for a system design to include a plurality of subnetworks (subnets) that have common characteristics. Current EDA tools execute algorithms on a subnet regardless of whether an identical subnet had been previously processed. For system designs that include a large number of subnets having identical characteristics, this results in the consumption of a significant amount of time and computing resources for repetitive computations.
Thus, what is needed is an efficient and effective method and apparatus for reducing synthesis runtime.
USPTO Backgrounds
USPTO Backgrounds