Referring to FIG. 1, as described in U.S. Pat. Nos. 6,462,376 and 6,888,196, an epitaxial layer 105 with a plurality of trenches is formed on a substrate 100. The sidewalls and bottoms of the trenches are covered with oxide layer 115. There are p-type doping regions 110 (P-body) and n+ doping regions (n+ source) formed in the epitaxial layer, and a p+ doping region at the bottom of the trench contact for ohmic contact to P-body. The trenches are filled with N+ doped polysilicon layer to form gate structures 120. The gate structure 120 and the P-type doping regions 110 (P-body) are connected to metal plugs 125, and in turns to a respective gate metal pad 130 and source metal pad 140 used as metal connections for the trench MOSFET.
In the cross-sectional schematic diagram of the trench MOSFET of FIG. 1, during formation of the gate structures 120, a layer of polysilicon material is deposited on top of silicon mesa and into trench after gate oxide is grown by a chemical vapor deposition (CVD) process. Thereafter, the excess polysilicon material above silicon mesa is removed by a back-etching process, thereby forming gate structures inside the trenches. During filling of the polysilicon material in the trenches, a polysilicon seam A may be inherently formed in the middle of the gate structure 120 due to structure imperfections resulted by CVD process, thus it may cause problems such as short circuit in metal connections when metal plugs 125 formed as the metal contacts for the gate structures.
Referring to FIG. 2, a schematic top view of the gate structure 120 and the metal plug 125 is shown, wherein the gate structure 120 has a polysilicon hole at intersection of three polysilicon seams A. If the metal plug 125 is located on top of the polysilicon hole, then the metal plug 125 may penetrate the gate structure. Referring to FIG. 3, another schematic top view of the gate structure is shown, wherein the metal plug is located at one polysilicon seam of the gate structure, thus the problem with short-circuit between gate/drain may be alleviated. However, this still requires the metal plug 125 to be precisely positioned to avoid any polysilicon seam for better yield and reliability.
Referring to FIGS. 4A and 4B, cross-sectional schematic diagrams of the gate structure 120 are shown. As can be seen, the gate structure has a polysilicon seam A, if the metal plug 125 overlaps this polysilicon seam A, the metal plug 125 may be formed with a penetration 126, which penetrates the gate structure 120 to the oxide layer 115, thereby forming a short-circuited region 127.
Therefore, there a need for manufacturing a trench MOSFET that solves the problem related to poor gate contact. Moreover, the prior arts forming gate structures inside the trenches, have higher gate resistance Rg when trench width becomes narrower and shallower for lower gate charge to achieve higher switching speed.
USPTO Backgrounds
USPTO Backgrounds