This invention relates to electrical circuits for introducing time delays into an electrical path.
There is often a requirement in electrical or electronic circuits for an electrical signal or signals to be delayed by some specified time interval. A common way in which the time delay can be introduced is by means of an analogue delay line. Such delay lines are physically bulky, which can present problems when used in devices employing printed circuit boards, have relatively poor tolerances typically of the order of 5% and often are only available in certain standard values. Delay lines are usually the only option available when it is required to delay analogue signals. Digital delays can be implemented in one of a number of ways including the following:
1. An analogue delay line of the type just discussed in conjunction with logic buffers.
2. Using monostable devices.
3. Using high frequency clocks and counters.
Monostable devices are commonly employed to provide time delays in digital electronic systems. In such devices the delay provided by the monostable device is determined by a resistor capacitor arrangement which is usually external to the device. The main problem with such devices is the uncertainty in the actual value of the generated delay. The delay is a function of the values of the resistor and capacitor in the RC network, the temperature and supply voltage and variations in device to device parameters. This uncertainty can often be very large and can thus make the devices impractical in applications where delays of moderate accuracy are required. The third technique referred to above relies on the use of a counter and a high frequency clock to provide delays which are a multiple of some basic delay. At the start of the time delay interval the counter is loaded and allowed to count until it reaches some predetermined value at which the delay is deemed to have ended. Arrangements of this type require a moderate amount of hardware for their implementation and a high frequency clock. The technique does however have the advantage that a delay can be readily varied in steps equal to the period of that high frequency clock. The main disadvantage of the system is that the actual value of the delay generated has a quantisation error corresponding to one period of the high frequency clock, i.e. a high frequency clock of 1 Mhz means delays will have one microsecond tolerance.
An example of apparatus in which time delays are required is in the data separator circuit of a digital tape recording device. In such devices there is a phase locked loop which generates a read reference clock from read transitions. The phase controlled loop operates by adjusting a reference clock in dependence on the misalignment between transitions and the edges of clock signals. To facilitate measurement of the misalignment, the phase controlled loop incorporates a delay line which is provided to allow for the fact that transitions can arrive after a reference clock edge has passed. In the ideal situation the delay introduced by the delay line should be equal to half the reference clock period. It is conventional to use a fixed delay which only provides an nominal delay when the apparatus is operating under ideal conditions, namely when the read transitions occur at a predetermined fixed frequency. What the apparatus essentially does is determine the center of a time window in which data can arrive from the tape. If data arrives in that window it is decoded without error, but if it arrives outside the window a decoding error occurs. Such errors are clearly undesirable. A problem associated with tape drives is that small changes in the speed at which the drive runs affect the size of the decoding time window. For example if the drive is running fast then the window shrinks slightly below its nominal value. Thus, if the selected delay has been optimised for a drive running at 120 inches per second it is not the optimised value the same drive running 1% slower., this can lead to errors.
USPTO Backgrounds
USPTO Backgrounds