The power dissipated during operational use of an electronic circuit reveals itself as heat. The heat generated by an integrated circuit typically increases with increasing transistor density and with increasing clock frequency. The eventual temperature of a semiconductor substrate in a stationary state is determined by the balance between the heat generated and the heat carried off of the substrate. A conventional way to handle excessive heat is attaching the substrate to a heat sink and/or by providing additional equipment for forced cooling such as a fan. Clearly, such measures not only are very costly, but also may preclude packaging due to the physical constraints. The use in portable equipment, e.g., in a PDA, becomes practically impossible: there is simply no room to accommodate all this equipment, the battery has very limited power and the weight would increase beyond an acceptable threshold.
Certain kinds of circuits tend to operate in bursts. That is, the circuit may, alternately, remain idle for a period of time and then operate at its maximum or near-maximum capacity for another period of time. Heat generation peaks are caused by the activity in the latter period. Because of the thermal inertia in the integrated circuit, the heat build-up and dissipation will lag behind the high-power consumption periods. That is, the heat generated during high-power operation may be carried off during those periods wherein the circuit is operating at low power.
Semiconductor packaging is designed to dissipate the amount of heat generated when the circuitry is operating at peak power. This guarantees that junction temperatures in semiconductor devices does not exceed prescribed operational limits. The semiconductor packaging cost premium due to measures required to handle peak power dissipation can be seen as wasteful. As already mentioned above, certain applications preclude special packaging due to physical constraints determined by the apparatus that is to accommodate the semiconductor device.
International Application WO92/10032 discloses a control system as specified in the preamble with multiple processor circuits that operate in a bursty fashion. In order to prevent heat damage, the known system senses the rate of change of operating temperature of the integrated processor circuits and adjusts the rate of operation of the circuits. The system includes a plurality of CMOS semiconductor chips, accommodating the processor circuits, and a sequence controller operative to supply instructions or data to the chips. Each chip is provided with a temperature sensor to generate an analog signal, indicative of the temperature sensed. In a particular embodiment, the sensor is physically integrated with the semiconductor substrate. The analog signal is supplied to a microprocessor via an A/D converter. The microprocessor serves as a PID controller and uses the received signal to calculate a quantity representative of the rate of change of the temperature. PID control allows taking into account the thermal inertia between the chip as a whole and the sensor. If the rate of change indicates that the chip's temperature will exceed a first predetermined value, no-op (no operation) instructions are supplied to the integrated circuit at a predetermined frequency. This allows the circuit to cool down. The rate of change of the temperature may indicate that the chip will reach a temperature higher than a second, higher predetermined value. In such case, additional no-op instructions are provided or the chip will be shut down completely. Alternatively, the clock frequency may be adjusted in response to the sensed rate of change of the temperature to achieve the desired cooling of the chip.
USPTO Backgrounds
USPTO Backgrounds