1. Field of the Invention
This invention relates generally to input/output circuits for integrated circuits, and particularly to a high-voltage tolerant receiver device for protecting low-power semiconductor (e.g., MOS) integrated circuits.
2. Discussion of the Prior Art
Receiving high voltage signals, e.g., 5.0 V in a five volt system, with current semiconductor CMOS integrated circuit receiver devices presents several problems to the IC designer. Over-voltage stress at the receiver input may result in damage ranging from performance degradation to catastrophic failure. Typically, care must be taken to prevent device latch-up, hot-electron performance degradation, gate-oxide breakdown, ESD damage; and, in the case of IC devices including PFETs, P-N diode reverse bias breakdown.
FIG. 1 illustrates an example high-voltage protected interface circuit 10 according to the prior art. This circuit is designed to receive 5V signals at an input xe2x80x9cPADxe2x80x9d 12 associated with the circuit implementing 2.5V CMOS technology, for example. As shown in FIG. 1, the NFET device N114 is a thick oxide device that is capable of handling the maximum voltage that is safely allowed in the 2.5V CMOS technology.
Devices N1 and devices P116a and N216b forming a first inverter structure 15 are powered off a 3.3 V voltage supply, and provide an intermediate voltage allowing for a wider receiver threshold range for 5V high logic level signals at the input PAD. Devices P246a and N246b form a second inverter device 45 that is powered off the IC core voltage which may be 3.3 V, or when the technology permits, 2.5V as shown in FIG. 1. It is understood that the IC core voltage may be as low as 1.8 VDC as the technology permits. The second inverter 45 performs the necessary level translation (i.e., voltage pull-up or pull-down) of the input signal and maintains the non-inverting polarity of the data received.
The high voltage protection provided by the circuit shown in FIG. 1 is maintained by NFET device N114. This NFET is configured as a pass gate that limits the voltage at node NA 13 to one threshold voltage xe2x80x9cVtxe2x80x9d below the gate voltage at node G1. Node G1 is tied to the 3.3V power supply which limits the voltage at node NA 13 to (3.3 Vxe2x88x92Vt) volts when the PAD voltage rises above 3.3 volts. The signal at node NB 17 switches between 0V and 3.3V and the signal 48 at the output swings between 0V and 2.5V. The problem with this type of design is the effect the voltage at node NA 13 has on inverter devices P116a and N216b. Because the voltage at node NA 13 is limited to (3.3 Vxe2x88x92Vt), the voltage on the gate of P116a is never going to be high enough to completely cut off current flow through P1. When the voltage at PAD input 12 is at a high logic level in the 5V system, node NA 13 will be sitting at (3.3Vxe2x88x92Vt). NFET N216b will be turned on and conducting current to pull down the voltage at node NB 17. The PFET P116a will not be completely turned off thereby allowing a leakage current to flow from the 3.3V supply through devices P116a and N216b continuing to circuit ground 18. It should be understood that the amount of current will vary with process temperature and voltage. This unwanted power consumption defeats the purpose of using a low power CMOS technology, which is to reduce power consumption.
Circuits have been designed and used in the industry to address this problem. The circuit 20 shown in FIG. 2 corresponds to the circuit 10 of FIG. 1 but has been modified to include one additional PFET transistor device P322. This PFET device P322 utilizes feedback from the output of first inverter 15 at node NB 17 to pull up the voltage at node NA to 3.3V when receiving 5V signals at input PAD 12. As such, PFET device P322 is also known as a xe2x80x9ckeeperxe2x80x9d, xe2x80x9cpull-upxe2x80x9d or xe2x80x9cboot strapxe2x80x9d device. When PAD input 12 is at a high level and the voltage at node NA. 13 is at (3.3 Vxe2x88x92Vt), the output of the inverter 15 formed by devices P116a and N216b is low. A low level on the gate of device P322 causes device P3 to turn on and conduct current between 3.3V and node NA 13. This causes the voltage at node NA 13 to rise to 3.3V which now turns off PFET P116a that was partially on. This solves the original problem of leakage or quiescent power-consumption, but causes a host of additional problems for some interfaces.
For instance, the added PFET device P322 in the circuit 20 of FIG. 2 introduces a path 23 for current between the PAD input 12 and the 3.3V power supply used to power pull-up device P322. When PAD input voltage 12 switches from high to low and the voltage at node NB 17 switches from low to high, there exists a range of input voltages where PFET device P3 is conducting. This situation requires a stronger external signal to drive PAD 12 to overcome the current path through transistor device P322. Another problem with the circuit in FIG. 2 occurs when external pull-up or pull-down devices are used. For example, the resistor R124 in FIG. 2 represents a pull-down device used to keep the PAD voltage at a valid logic level (e.g., low) when the PAD input is not being driven. The resistor R1 must be low enough in impedance to overpower device P3 to guarantee a zero level at the PAD. This puts a size limitation on the pull-down resistor R1 which is greater than the limitation set by the leakage current of the technology. A weak source driving the PAD input 12 may also cause the receiver to hang-up at mid-rail when device P322 is conducting. The turning on and off of transistor device P322 during a PAD transition also causes the input impedance of the receiver to become nonlinear. This nonlinear receiver front end can have an adverse effect on signal integrity.
While a solution may be to implement the circuits in FIGS. 1 and 2 by specifying or placing restrictions on the power supply ranges and pull-down resistors in order to bound the negative aspects of power consumption and leakage by some specified amount, this just limits the problem and does not provide a total solution that eliminates the problem.
It would be highly desirable to provide a receiver circuit for a semiconductor device that eliminates the aforementioned power dissipation problems of excess leakage current and the requirement for higher input drive at the input.
It is an object of the present invention to provide a receiver circuit for a semiconductor device that eliminates prior art receive device deficiencies such as power dissipation problems of excess leakage current and the requirement for higher input drive at the input.
According to the principles of the invention, there is provided a receiver circuit for interfacing a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor integrated circuit devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device, and responsive to pulled up voltage at the second node for enabling activation of the circuit element to facilitate pulling up voltage at the second node,
Advantageously, stable switching voltages is achieved at said second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.
USPTO Backgrounds
USPTO Backgrounds