A liquid crystal display device is one of the most widely used flat thin display devices at present, and is applied to a laptop personal computer, a liquid crystal monitor, a liquid crystal television, and the like. A general liquid crystal display device includes two glass substrates on which transparent electrodes are provided, and between which a liquid crystal layer is sandwiched. The liquid crystal layer has transmittance which changes in accordance with voltage applied between an upper electrode and a lower electrode. On this account, by applying voltage to electrodes provided on arbitrary coordinates, a desired image is displayed.
In recent years, products, such as a laptop personal computer, a liquid crystal television, and the like, need a color liquid crystal display device, and most of them have adopted an active matrix liquid crystal display device, in which switching elements such as TFTs (thin film transistors) are used. The active matrix liquid crystal display device includes an active matrix substrate, in which the switching elements and pixel electrodes are provided in matrix, i.e., they are provided in a vicinity of intersections in which signal lines and scanning lines orthogonally cross with one another. An image is displayed by applying voltage to the pixel electrodes via the switching elements such as TFTs. The use of the switching elements makes it easier to control the voltage applied to the liquid crystal layer. Thereby, it becomes possible to attain a display device having a higher contrast, or having a larger number of gradation colors. On this account, the active matrix liquid crystal display device has dramatically higher visibility than a passive matrix liquid crystal display device, which does not include a switching element.
Here, the following description discusses a conventional active matrix substrate (hereinafter, referred to as “first conventional art”) with reference to FIG. 10(a) and FIG. 10(b), FIG. 11, and FIG. 12. FIG. 10(a) is a perspective plan view illustrating a structure of an active matrix substrate of the first conventional art. FIG. 10(b) is an explanatory view showing a cross section taken along line E-E′ of FIG. 10(a). FIG. 11 and FIG. 12 are enlarged perspective plan views illustrating a TFT (thin film transistor) 130 of the active matrix substrate shown in FIG. 10(b).
As shown in FIG. 10(a) and FIG. 10(b), an active matrix substrate 101 is so arranged that, on a transparent insulation substrate 100 (shown in FIG. 10(b)), a signal line 30, a scanning line 120, a pixel electrode 80, a gate electrode 110, a semiconductor layer 50, a drain electrode 60, and a source electrode 70 are provided.
On the gate electrode 110, a gate insulation film 40 is formed, and on the gate insulation film 40, a semiconductor layer 50 is formed. The semiconductor layer 50 has an end portion (located toward the signal line 30) on which an n-type semiconductor layer 20b is formed. Further, the semiconductor layer 50 has another end portion (located toward the pixel electrode 80) on which an n-type semiconductor layer 20a is formed. On the n-type semiconductor layer 20a, the drain electrode 60 is formed, whereas on the n-type semiconductor layer 20b, the source electrode 70 is formed. Thereby, a TFT having three terminal elements is constituted.
As shown in FIG. 11, the drain electrode 60 and the source electrode 70 face each other, with a certain space between them in such a direction that the scanning line 120 extends. The gate electrode 110 controls electric conduction between the source electrode 70 and the drain electrode 60. For example, when voltage is applied to the gate electrode 110, channel is formed via the n-type semiconductor layers 20a and 20b, and resistance is decreased. Thereby, an electric conduction between the drain electrode 60 and the source electrode 70 is attained.
Note that the gate electrode 110 is connected to the scanning line 120, the source electrode 70 is connected to the signal line 30, and the drain electrode 60 is connected to the pixel electrode 80. Further, an interlayer insulating film 95 is so provided that the interlayer insulating film 95 covers the drain electrode 60, the source electrode 70, and the semiconductor layer 50, which is exposed between the drain electrode 60 and the source electrode 70 facing each other.
Here, the drain electrode 60 and the source electrode 70 need to at least partially overlap with (be formed above) the gate electrode 110. In this case, the gate insulation film 40 and the semiconductor layer 50 are interposed between them. A region (cgd contribution region) 90, an area of which determines a gate-drain capacitance cgd, is constituted of (a) that overlapping portion of the drain electrode 60 which overlaps with the semiconductor layer 50, (b) that overlapping portion of the gate electrode 110 which overlaps with the semiconductor layer 50, and (c) vicinities of those overlapping portions of the drain electrode 60 and the gate electrode 110. The gate-drain capacitance cgd has a great effect on a display characteristic of a liquid crystal display device.
Therefore, it is necessary that the areas of the cgd contribution areas 90 of the TFTs formed on the active matrix substrate 101 should not be greatly different from what it is supposed to be (designed value), that is, it is necessary to suppress unevenness among the areas of the cgd contribution regions 90 of the TFTs formed on the active matrix substrate 101. In order to avoid the unevenness among the cgd contribution areas 90, it is necessary to carry out an accurate positional alignment with tolerance of not more than ±several μm between (i) an electrode layer including the drain electrode 60 and a source electrode 70 and (ii) an electrode layer including the gate electrode 110. Note that, in an actual manufacturing step, positional alignment for an exposure device is so accurate that its tolerance is ±1 μm or less.)
Incidentally, in recent years, use of an ink jet printing is becoming popular way of manufacturing the active matrix 101.
Unlike a conventional photolithography method, the ink jet printing possibly causes not only the problem of misalignment of the electrode layers, but also such a problem that sizes and/or shapes of patterns thereof become different (deviated) from what they are supposed to be (from its designed value), due to miss-shot of the droplets (the droplets are inaccurately shot and land off of a predetermined positions of the TFTs), which causes unevenness among the droplets in terms of their shapes.
For example, when the ink jet printing is carried out to form a resist pattern in a step of forming the semiconductor layer 50, there is a possibility that misalignment occurs and/or the pattern deviates in terms of its size and shape. This leads to deviation in the area of the cgd contribution region 90 (the region that includes (a) those portions of the drain electrode 60 and the gate electrode 110 which overlap with each other, and (b) a vicinity of those portions). The deviation in the area of the cgd contribution region 90 results in deviation in the gate-drain capacitance cgd. Accordingly, the gate-drain capacitances cgd among the TFTs becomes uneven with one another. This adversely affects a display characteristic of the liquid crystal display device.
Therefore, for forming the active matrix substrate 101 by using the ink jet printing as described above, it is necessary to have such an arrangement that the cgd contribution region 90 would not be greatly different from what it is supposed to be, even if misalignment occurred or the pattern was different from what it is supposed to be, in terms of sizes and shapes.
However, with the foregoing first conventional art, the cgd contribution region 90 becomes greatly different from its designed value when misalignment occurs.
For example, as shown in FIG. 12, when the semiconductor layer 50 has a size different from what it is supposed to be (the semiconductor layer 50 has a smaller area which is reduced at its side facing the scanning line 120), the area of the cgd contribution region 90 becomes greatly different from what it is supposed to be.
Further, in FIG. 11, when the formation position of the semiconductor layer 50 is shifted in a length of X (indicated by an arrow in FIG. 11) toward the source electrode 70, the region in which the drain electrode 60, the gate electrode 110, and the semiconductor layer 50 overlap with one another loses almost half of its area. Further, when the formation position of the semiconductor layer 50 is shifted in a length of Y (indicated by an arrow in the figure) toward the source electrode 70, it becomes impossible to form the channel between the drain electrode 60 and the source electrode 70. This adversely affects the display characteristic of the liquid crystal display device.
In view of the misalignment between the layers, Japanese Laid-Open Patent Application Tokukai 2002-14371 (published on Jan. 18, 2002; hereinafter, referred to as “Reference 1”), for example, discloses an arrangement (hereinafter, referred to as the second conventional art) in which a wider margin for the alignment is provided.
FIG. 13(a) is a perspective plan view illustrating a structure of an active matrix substrate 101 of the second conventional art. FIG. 13(b) is an explanatory view showing cross section taken along line F-F′ in the FIG. 13(a). FIG. 14 to FIG. 16 are enlarged perspective plan views illustrating a TFT (thin film transistor) 130 of the active matrix substrate 101 (shown in FIG. 13(a)). Note that, for ease of explanation, sections having the equivalent functions as those shown in the active matrix substrate shown in FIG. 10(a) and FIG. 10(b) will be given the same reference symbols.
The second conventional art is different from the first conventional art in terms of the shape of the drain electrode 60 and the shape (formation region) of the semiconductor layer 50. Namely, as shown in FIG. 14, the drain electrode 60 includes a counter portion 60a that faces the source electrode 70, and a connecting portion 60b that connects the counter section 60a to the pixel electrode 80. The drain electrode 60 has a T-shape, i.e., the connecting portion 60b has a smaller width than the counter portion 60a. Further, the semiconductor layer 50 is formed under the source electrode 70 and the drain electrode 60, and has such a shape that the semiconductor layer 50 has an area whose margin surrounds the drain electrode 60 and the source electrode 70. Specifically, the semiconductor layer 50 includes (i) a region 50a whose margin surrounds the source electrode 70 and the counter portion 60a of the drain electrode 60, and (ii) a region 50b whose margin surrounds the connecting portion 60b of the drain electrode 60.
With this arrangement, even if a photolithography device is misaligned in forming the patterns of the gate electrode 110, the drain electrode 60, and the source electrode 70, resultant deviation in the area of the region that includes (a) the overlapping portion of the drain electrode 60, and (b) the overlapping portion of the gate electrode 110 is smaller than in the first conventional art.
For example, when, in FIG. 14, the formation position of the semiconductor layer 50 is shifted in a length of X (indicated by an arrow in FIG. 14) toward the source electrode 70, the area of the overlapping portion of the drain electrode 60 and the overlapping portion of the gate electrode 110 is still reduced, however, the area is less reduced than in the first conventional art because the connecting potion 60b of the drain electrode 60 has a smaller width than the counter portion 60a. Further, even when the formation position of the semiconductor layer 50 is shifted in a length of Y (indicated by an arrow in FIG. 14) toward the source electrode 70, the channel can be formed, unlike in the first conventional art, because the semiconductor layer 50 includes the region 50b which has a shape having a margin surrounding the connecting portion 60b. 
This suppresses a display defect even when the misalignment occurs.
However, the second conventional art does not completely prevent the deviation in the gate-drain capacitances cgd when the pattern of the semiconductor layer 50 is different, in terms of size and shape, from what it is supposed to be.
For example, when the semiconductor layer 50 has a size different from what it supposes to be, (the semiconductor layer 50 has a smaller size, that is, reduced in size at a side facing the scanning line 120) as shown in FIG. 15, or when the semiconductor layer 50 has a shape different from what it is supposed to be (the semiconductor layer 50 becomes a circular shape) as shown in FIG. 16, the area of the cgd contribution region 90 is greatly changed.
As described above, the conventional arts can hardly suppresses the gate-drain capacitances cgd from being changed when the sizes or the shapes of the semiconductor layers deviate from what they are supposed to be, for example, in forming the active matrix substrate by using the ink jet printing.
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