This invention relates to semiconductor devices, and more particularly to a method of planarization in integrated circuit manufacture where trench isolation is employed.
Trench isolation is employed in manufacturing processes for integrated circuits to avoid the topographical uncertainties caused in using the more coventional thick field oxide isolation. Particularly, the growth of thermal field oxide using a mask such as nitride creates an encroachment of the oxide into the active areas, this encroachment being referred to as the bird's beak effect. Trench isolation technolgy, however, requires the use of a planarization process to remove oxide from the active areas and keep oxide in the trenches. Due to varying pattern densities, sufficient planarization is sometimes not achieved. In some areas of the wafer face, there will be narrow trenches with narrow active areas between them, in others there will be wide active areas and wider trenches, while various combinations of trench width and active area width occur at other places along the face of the wafer due to variations in circuit density.
Several techniques have been developed for planarization of wafer surfaces when employing trench isolation. For example conformal oxide deposition with etchback can produce local smoothing and planarization, but problems occur with this technique for wide trenches. Another technique uses spin-on photoresist or glasses followed by etchback, but again the smoothing is dependent upon the trench geometries, and global planarization is not achieved when variable circuit density is present.
The prior techniques have been able to produce adequate planarization over local regions, but not global planarization over large areas of diverse trench patterns. More nearly global planarization has been reported using a two-layer photoresist structure, in which the first layer is patterned to provide a uniform surface for coating by the second layer. The two-layer stack is etched back to the original level, leaving a planar surface. This two layer photoresist method can use a so-called planarization block mask, in which the first level is patterned to leave photoresist only in sufficiently wide trenches, increasing the degree of planarization achieved.
In copending application Ser. No. 545,858, filed Jun. 29, 1990, by Scoopo, Alvarez and Grula, for Planarization Process Utilizing Three Resist Layers, assigned to Digital Equipment Corporation, now U.S. Pat. No. 5,077,234, a method of planarizing a surface of a silicon wafer is disclosed which employs three successive photoresist layers. The first layer is patterned as discussed to leave photoresist only in the wider trenches, then the second and third layers are added, and etchback to the original silicon surface in the active areas provides a planar surface.
In spite of the improvements discussed in planarization methods, there are still variations in surface level in the resulting structures, in some situations, particularly when mask misalignment and lapses in critical dimension control occur.
USPTO Backgrounds
USPTO Backgrounds