The present invention relates to a memory apparatus comprising at least two memory cards inserted into a back board. Such a memory apparatus has a relatively small capacity and addresses must be continuously assigned to respective memory cards. The back board includes an address bus with a memory card on which a semiconductor memory comprising one chip or a plurality of chips and a peripheral circuit are provided. The memory apparatus generally uses two memory cards, each having the same capacity. Therefore, by using the upper-most bit of the address, one of the two memory cards can be selected and accessed, thereby performing contiguous address assignment.
For example, respective address circuits of the memory cards are formed such that a memory card on the lower address side can be accessed when the upper-most bit of the address is "0" and a memory card of the higher address side can be accessed when the upper-most bit of the address is "1". The memory cards are installed in a back board.
When various memory cards with various discretional capacities are combined and installed, it is necessary in the prior art when performing a contiguous address assignment that the address of the respective memory cards be manually and previously set by a user using switches. The user determines which memory card is on the lower address side and which memory card is on the upper address side, and the user detects the capacity of the memory card on the lower address side so that the memory card on the upper address side has as the minimum address the address following the maximum address of the memory card on the lower address side.
Therefore, before the memory card is installed in a back board, the address assignment must be set by the user as described above, thus complicating the handling of the memory cards. If the installing position of the memory card is wrong, it causes the continuity of the address to be lost and will not operate as a memory apparatus with the desired capacity.
USPTO Backgrounds
USPTO Backgrounds