1. Field of the Invention
The present invention is directed in general to integrated circuit devices and methods for manufacturing same. In one aspect, the present invention relates to formation of a capacitor with metal interconnect structures.
2. Description of the Related Art
Integrated circuit devices, such as dynamic random access memory (DRAM) devices, increasingly require high performance capacitors with sufficient capacitance to extend the refresh period and increase tolerance to alpha particles. For example, a typical DRAM cell configuration includes a capacitor for storing a charge (i.e., the bit of information) and an access transistor that provides access to the capacitor during read and write operations. To provide the required capacitance for such high performance cell capacitors, the overlap area between an upper electrode (plate electrode) and a lower electrode (storage node electrode) should be increased and/or the thickness of a dielectric film interposed between the upper and lower electrodes should be reduced. While thinner dielectric films can be made using a high-k dielectric material having a high dielectric constant k, the thickness parameter of such high-k dielectric films is difficult to optimize as technological generations progress. While plate overlap can be increased by forming large, overlapping lateral capacitor plate layers, such structures reduce the pattern density at the memory region, resulting in loading effects during photo lithography, etch, and polishing steps. Another technique for increasing capacitance is to fabricate the capacitor in the semiconductor substrate as cylinder-shaped electrode plate that is concentrically positioned around a lower or storage node electrode plate to create the increased capacitance from the surface area of the storage node electrode. However, the height of such cylindrical capacitors is effectively limited by the constraints from high aspect ratio contact etch limitations which prevent contact etching from proceeding to a sufficient depth. Another approach for increasing the capacitor height (and charge storage) is to form embedded metal interconnect capacitors by using a wet etch chemistry to completely remove an exposed interconnect metal (e.g., copper) prior to forming the capacitor plate electrode and high-k dielectric layers, thereby preventing contamination of the high-k dielectric layer by the interconnect metal. However, such metal interconnect capacitors are typically limited to the height of one metal level due to the blocking of barrier metal at the bottom of the metal interconnect, and also require expensive photo step and etching of high aspect ratio contacts for capacitors.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.
USPTO Backgrounds
USPTO Backgrounds