1. Field of the Invention
The present invention relates generally to junction field effect transistors and more particularly to the fabrication of a junction field effect transistor with the aim of minimizing the devices "on resistance" and thereby increasing the yield of acceptable devices.
2. The Prior Art
Typically, it has been the practice heretofore to fabricate the top gate of a junction field effect transistor using standard photolithic and diffusion techniques. Oxide is grown over the source and drain material, photoresist is deposited and developed, and the oxide and photoresist is selectively removed by planar etching to form a rectangular gate aperture. Gate material is then deposited and diffused into the aperture in the oxide. The width of the diffuse gate is limited by the minimum oxide line width that can be obtained by planar etching of the mask formed using present photolithic techniques. Since minimum "on resistance" (R.sub.on) of a junction field effect transistor (JFET) is determined in part by the effective width of the gate, the R.sub.on of the JFET of the prior art have been limited by said minimum oxide line width.
USPTO Backgrounds
USPTO Backgrounds