A read path of a RAM (Random-access Memory) device may require a delay to be added to a clock path to strobe data in the center of an eye pattern. The delay may be subject to process, voltage and temperature (PVT) variation, which may limit the speed of read operations. A method may be utilized for first removing process variation. Further updates may be applied to remove voltage variation and temperature variation. Current solutions may utilize a master delay cell to emulate a correct delay setting. The correct delay setting may then be applied to slave delay cells within the actual clock path. The master delay cell may then be monitored for voltage and temperature changes, corrected for said changes, and the slave delay cells updated with the new setting. However, the current solutions may introduce mapping errors due to on-chip process variation from the master to slave delays. Further, the current solutions may require that data flow be interrupted in order to update the slave delay cells. In addition, the currently implemented master-to-slave systems do not account for internal skew across multiple data paths which are strobed with a single clock. Still further, the currently implemented master-to-slave systems may have stringent duty cycle requirements. Also, current solutions may require custom-designed delay cells for reducing mapping error and may further require custom-designed overhead delay cells for accurately delaying data paths to match the clock path delay cell when the clock path delay cell is set to its minimum delay setting.
Therefore, it may be desirable to have a system and method for providing swap path voltage and temperature compensation which addresses the above-referenced problems and limitations of the current solutions.
A SDRAM (Synchronous Dynamic Random Access Memory) bi-directional data strobe (DQS-Data Strobe Signal) may require gating for removing unwanted write strobes and idle period noise from entering a read path of a memory controller. Without gating, false read strobes may corrupt read data. Further, latch up of data registers may occur if noise is not removed from DQS. With current solutions, DQS is gated (i.e., forced to zero) before and after read clock bursts by two methods. The first currently implemented method involves adjusting programmable delays within the memory controller to match round trip delay of clock to the SDRAM (CK) and DQS back from the SDRAM. Said programmable delays adjust gating logic on the DQS strobe so that only read burst transitions are received into the memory controller. The second currently implemented method involves gating the DQS before and after read clock bursts by utilizing a fixed feedback loop, external to the memory controller, with a delay that matches CK (controller to SDRAM) and DQS (SDRAM to controller). Further, the fixed feedback loop supplies a signal that gates the DQS read burst transitions. However current solutions have drawbacks in that, although the first method of gating DQS may remove process variation, it suffers from voltage and temperature variation after initial setup. Further, the second method, although it may track voltage and temperature variation, it does not remove process variation. Still further, when implementing the second method, it may be difficult to accurately determine correct trace length required on a circuit board, due to different loading of the memory controller compared to the SDRAM.
Therefore, it may be desirable to have a system and method for providing feedback path voltage and temperature compensation of programmable delay read data strobe gating which addresses the above-referenced problems and limitations of the current solutions.
A number of memory applications may require a continuous read clock. The continuous read clock may require a delay to center it within a data eye. However, the delay may suffer from voltage and temperature (VT) variation and may require adjusting while maintaining continuous memory reads. Current solutions may attempt to keep latency across a memory controller read path to a minimum. For instance, some current solutions may pass the read clock (DQS) via a delay cell to a memory controller, while a data path, once registered, is passed to the memory controller with zero cycle timing. This may allow a memory controller designer to take advantage of the minimized/short latency. In order to update for VT variation of the delay cell, and maintain a continuous read operation, a number of solutions are currently implemented. For example, a first current solution may not compensate a clock delay cell for VT variation, but may simply adjust the clock delay cell once after power on reset, with further VT variation being considered small enough to be ignored. A second current solution may include memory systems which provide an extra signal for indicating valid read data, with a delay cell being updated for VT variation when read data is not valid. A third current solution may provide a delay cell which may be designed so that it may be updated without output glitches occurring. With the third current solution, an offline master delay cell may be used to monitor VT variation, the VT variation being applied to an online slave delay cell in minimum increments so as not to introduce a large shift on a DQS clock. However, the current solutions suffer from drawbacks. For instance, the first current solution may only work for slow frequency applications and, after an initial setting of the clock delay cell, VT variation may cause data errors if the frequency is too high. The second current solution may require a fast update of the delay cell during non-valid data periods. Further, the second current solution may not allow for continuous read data, such as where the data is always valid or at least where the non-valid data periods are so short that a safe update would be impossible. The third current solution, with its master-slave approach, may lead to mapping errors due to PVT variation across a chip. Further, designing a glitch-free delay cell may be difficult and limited in its operating frequency. Moreover, most glitch-free designs may require control logic clocked from within a DQS domain. In addition, synchronization of control across a DQS/system clock boundary may add greatly to the complexity of the design.
Therefore, it may be desirable to have a system and method for providing asynchronous clock regeneration which addresses the above-referenced problems and limitations of the current solutions.
USPTO Backgrounds
USPTO Backgrounds