The present invention relates generally to instruction grouping, and instruction and micro-operation level parallelism, and more specifically, it relates to an Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System to resolve or lighten the cost of branch penalty, save cache memory and operating energy, tolerate memory latency, and improve the performance of the adaptive microprocessor system. The Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System identifies the qualified instruction segments for grouping. In the invention, a non-grouped instruction is an instruction that does not satisfy the conditions to be an element of the qualified instruction segment. The Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System eliminates the number of branch instruction appearances; groups the branch instructions with non-branch instructions; combines non-branch consecutive instructions; and converts the qualified instruction segments to user-defined compact formats of instructions before runtime or at adaptive compilation time. In addition, the Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System executes both the non-grouped and the grouped instructions to achieve functional compatibility and performance enhancements by adaptively ungrouping and executing the non-grouped and the grouped instructions at runtime. Therefore, the Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System drastically reduces and ciphers software code while maintaining the compatibility of the software code. Furthermore, the Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System considerably conserves instruction cache memory or simplifies the cache organization from the hierarchical instruction memory without employing any binary compression hardware/software and instruction translation/packing techniques present in prior arts. Additionally, the Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System drops the signal switching frequency per unit time (i.e., second) to save operational energy as fewer instructions are fetched from memory to microprocessor via a bus in the same unit time. Since more operations, including branches, are grouped into an instruction, a cheap, slow memory system can be used continuously in fast microprocessors without causing any performance bottleneck. The Instruction Grouping and Ungrouping Apparatus and Method for an Adaptive Microprocessor System also provides functional compatibility by using adaptive hardware integrated to various back-end processing engines. Through this invention, software developers can have their own compatible, compact and ciphered instruction sets after performing the invented apparatus and method with existing software compilers and the target adaptive microprocessor systems.
USPTO Backgrounds
USPTO Backgrounds