1. Field of the Invention
The present invention relates to data transfer between semiconductor devices and, more particularly, relates to drain current controlled CMOS output driver circuits for constant current applications.
2. Description of the Prior Art
It is known that in high frequency data transfer applications, such data transfer is typically accomplished with transmission lines and terminal resistors in order to avoid signal reflections which may cause distortion and/or ringing on input/output signals. Particularly, a termination resistor may be located at either the end, or both at the end and the beginning, of the transmission line. The value of such termination resistor(s) is not fixed; however, typical values may be 50, 60, 75 or 100 ohms. It is to be appreciated that such termination resistor(s) may be connected to ground, to the device power supply, or to an externally provided reference voltage as disclosed in the Stub Series Terminated Logic (SSTL) EIA/JEDEC Standard.
By way of example, FIG. 1 illustrates an off chip driver (OCD) circuit located in Chip A and referred to as an output buffer. A typical application of an OCD is to drive output data bits from a semiconductor memory device, such as a dynamic random access memory (DRAM) device, to another device (receiver). Such an OCD typically must deliver a specified voltage swing at an input stage of the device receiving the data bits in order to ensure proper operation of the data transfer system. In order to ensure such a specified voltage swing, it would be advantageous for the OCD to provide a controllable current source (p-channel transistor) and current sink (n-channel transistor). In such a case, the controlled current causes a voltage drop across the termination resistor RT which is used as the input voltage VIN of an input circuit (Receiver/Chip B).
Attempts have been made to develop output current controlled driver circuits.
For instance, U.S. Pat. No. 5,495,184 (Des Rosiers et al.), issued Feb. 7, 1996, discloses a high-speed low-power CMOS positive-shifted ECL I/O transmitter.
The transmitter contains a totem-pole structure of four CMOS transistors. The top two CMOS transistors are PMOS devices and the bottom two transistors are NMOS devices. The top and bottom transistors function as output current switches which alternatively turn on and off the current flow from either a source voltage power supply VSS or a drain voltage power supply VDD to a resistive termination load Rt.
The middle two devices are connected to DC voltage references which control a precise amount of current sourced to a load using a precision current source and sunk from a load using a precision current sink. The reference voltages for the precision current source and the current sink use a negative feedback circuit which is referenced to a resistor ladder and a current source controlled by a band-gap reference source. The arrangement in the Des Rosiers et al. transmitter allows for on-chip referencing of ECL levels and control of reference voltages and currents in spite of variation in process, voltage, and temperature. Internal ECL reference level signals VOL and VOH are used to control the output levels. Operational amplifiers drive the respective transistors such that voltage at the drains of the current source and sink transistors equals the ECL reference inputs VOH and VOL. These control voltages generate a precise current through a replica stage and are also applied to the output stage. All of the devices in the reference control circuit are scaled to reduce DC power dissipation.
However, the DC voltage references generated by the Des Rosiers et al. transmitter, which control the current sourced to the load and sunk from a load disadvantageously do not take into account the external reference voltage coupled to the resistive termination load Rt. As a result, the Des Rosiers et al. output driver's applicability to various data transfer standards is severely limited.
USPTO Backgrounds
USPTO Backgrounds