1. Field of the Invention
The invention relates the formation of doped p-type gate, more particularly forming doped p-type gate with removed anti-reflection layer.
2. Description of the Prior Art
Scaling of CMOS technology to the deep sub-micron regime has been driven by the need for higher speed and integration density, as well as lower power operation. Also, dual gate technology offers several advantages, including reduced short channel effect by the surface channel operation of both NMOS and PMOS device, low and symmetric threshold voltages required for low supply voltages.
However, new problem such as the poly-gate-depletion effect (PDE) emerges as the dimensions of devices enter the deep submicron regime is very difficult to be controlled for conventional polysilicon type gate CMOS.
Therefore, due to the conventional polysilicon gate has no close-to-midgap work function, so device process need to be modified by a much more fabrication.
In accordance with the present invention, a method is provided for forming doped p-type gate that substantially achieves close-midgap work function.
In the preferred embodiment, with the disposable silicon nitride film which can be removed, pure p+ doped single gate can be obtained without n+ implantation dose compensate problem happened for CMOS device.
In the preferred embodiment, the height of polysilicon gate was lower than oxide spacer, good salicidation can be formed for polysilicon gate, by the way, source/drain to gate bridging for salicidation can be suppressed.
In the preferred embodiment, the silicon nitride film can be the anti-reflection layer. Thus, the critical dimension control of polysilicon gate can be efficiently improved.
In the preferred embodiment, the process is compatible with the conventional technology for the sub-0.13 um device design.
In the preferred embodiment, firstly, a semiconductor substrate is provided. A first photoresist is formed on the surface of semiconductor substrate. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. The first photoresist is removed. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, also named as doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer is formed on the surface of silicon germanium layer. A second photoresist is formed on the surface the silicon nitride layer, also named as anti-reflection layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. Then the second photoresist is removed. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region. A source/drain region is formed into the semiconductor substrate by implantation using the gate region and the spacer as a mask. The silicon nitride layer is removed. Finally, salicide region is formed into the source/drain region and upon the surface of silcion layer to complete the silicon gate structure.
USPTO Backgrounds
USPTO Backgrounds