The present invention is generally related to digital phase locked loops for controlling the frequency and phase of a clock. In particular, the present invention relates to digital generating an error signal from data being recovered from a storage system to be used in controlling the frequency and phase of a clock in the storage system.
The use of phase locked loops to control the frequency and phase of a clock in storage systems is well known and understood in the art. In such systems as magnetic disk drive systems and magnetic tape system, phase lock loops are used to control the frequency and phase of a voltage controlled oscillator as a function of signals read from the magnetic media. The output of the voltage controlled oscillator is the clock which is used to recover data from the signals read from the magnetic media.
Generally, the disk drive system records data on the magnetic media in the form of data blocks or sectors. The data blocks or sectors are usually formatted with a preamble field including synchronization data and then a data field including the data. The length of the data field is much longer then the length of the synchronization data in the preamble field. The synchronization data is used to initially lock the voltage controlled oscillator in the phase locked loop to the phase and frequency of the synchronization data. The data in the data field is used to maintain the phase and frequency relationship between the clock and the phase and frequency of the data.
With the advent of digital processing of signals read from the magnetic media to recover the data encoded from the read signal, digital phase locked loops have been developed to digitally generate digital correction signals for correcting any phase or frequency error between the clock and the read data. At present data can be recorded at frequencies greater than the than the response time of the digital logic processing the read signals. Some digital data decoders therefore split the sequence of digital samples into a sequence of even numbered samples and a sequence of odd number samples. The even data bits recovered from the sequence of even samples were then combined with the odd data bits recovered from the sequence of odd samples to form the original sequence of data bits.
While the splitting of the data into sequences of even and odd samples has allowed data to be detected at half the clock frequency used to sample the analog signal, the information necessary for determining any phase or frequency error between the clock and the data was destroyed. The digital phase detectors needs more than one consecutive sample to obtain the relative frequency and phase error, if any, between the clock and the data and therefore has to be operated at the clock frequency used to sample the analog signal. Therefore the response time of the logic employed in the digital data phase detector remains as a major limiting factor of the overall response time of the digital phase locked loop.
USPTO Backgrounds
USPTO Backgrounds