Extensive work has been done in the field of silicon on insulator (SOI) integrated circuits, in which two wafers of silicon are bonded together with an oxide layer in between. One of the two wafers is ground or otherwise thinned down to the desired thickness. Commercially available wafers have a top silicon device layer having a nominal thickness of 2 .mu.m.+-.0.3 .mu.m. The art has long sought the development of a device layer of thinner dimensions in order to isolate the final devices from each other and also to produce fully depleted CMOS field effect transistors, which, for standard voltages and doping concentrations, require a device layer of thickness less than 1000 .ANG..
Thin device layers made by implanting oxygen and forming the buried oxide insulating layer in situ (SIMOX) are commercially available, but the top surface of the buried insulator normally has crystal defects that produce leaky devices.
U.S. Pat. No. 4,735,679 illustrates a technique for providing thin uniform layers of top silicon, called device silicon, above an underlying oxide insulator to form SOI integrated circuits. This patent illustrates a technique in which a polish stop of refractory metal, defined by a lift off technique, is used to define the uniformity of the silicon device layer.
U.S. Pat. No. 4,824,795 illustrates a process that uses a concentration dependent oxidation process which leads to a RIE step that is not well controlled and therefore will have manufacturing difficulty. Further, the use of side crystallization of the polysilicon means that defects in the crystal structure will be located in the transistor area.
One skilled in the art would not consider the use of a wet etch process for devices in SOI having a device layer thickness of about 1000 .ANG. because such devices use small linewidths (less than 1 .mu.m) for which the horizontal etching characteristic of wet etches is considered intolerable.
USPTO Backgrounds
USPTO Backgrounds