A circuit may be categorized as being a static circuit or a dynamic circuit. A static circuit is a circuit whose output is not triggered by a clock signal. On the other hand, a dynamic circuit is a circuit whose output is triggered by a clock signal. An advantage of dynamic circuits is that they typically operate faster than static circuits.
Since the output of a dynamic circuit is triggered by a clock signal, a dynamic circuit operates in two different modes, namely an evaluation mode and a pre-charge mode, depending on whether the value of the clock signal is a logical high (in other words, a “1”) or a logical low (in other words, a “0”).
When the clock signal applied to the dynamic circuit has a logical high value, the dynamic circuit is in evaluation mode. In evaluation mode, the logic of the dynamic circuit is evaluated using the inputs to the dynamic circuit. Thus, when a dynamic circuit is in evaluation mode, the output of the dynamic circuit depends upon the evaluation of the logic of the dynamic circuit using the inputs applied to the dynamic circuit.
When the clock signal applied to the dynamic circuit has a logical low value, the dynamic circuit is in pre-charge mode. In pre-charge mode, the logic of the dynamic circuit is not evaluated. The output of a dynamic circuit in pre-charge mode is driven to a logical low value, since the logic of the dynamic circuit is not being evaluated.
FIG. 1 is a diagram illustrating the output signal of a dynamic circuit in both evaluation mode and pre-charge mode. As FIG. 1 illustrates, the rising edge of the clock signal causes the dynamic circuit to be in evaluation mode, while the falling edge of the clock signal causes the dynamic circuit to be in pre-charge mode. Thus, the evaluation of the logic of a dynamic circuit, using the applied inputs, is triggered by the rising edge of the clock, and the output of the dynamic circuit is driven to a logical low at the falling edge of the clock.
A dynamic circuit may be used in conjunction with an input flop and an output flop. A flop (alternately called a “flip-flop”) is a type of circuit that will maintain its state indefinitely until it receives an input signal, called a trigger, which forces the flop to alternate its state. Once the flop changes state it remains in that state until another trigger is received. A flop may be used to store data. A flop that provides a set of inputs to a dynamic circuit is referred to as an input flop, while a flop that stores a set of outputs from a dynamic circuit is referred to as an output flop.
FIG. 2A is a diagram illustrating a dynamic circuit 204 in conjunction with an input flop 202 and an output flop 206. As shown in FIG. 2A, at the rising edge of the clock signal, the input flop 202 provides a set of input to the dynamic circuit 204. At the rising edge of the clock signal, the dynamic circuit 204 is in evaluation mode. When the dynamic circuit 204 is in evaluation mode, the logic of the dynamic circuit 204 is evaluated, using the input from the input flop 202, to produce a set of output. Also at the next rising edge of the clock, the output flop 206 reads and stores the output from the dynamic circuit 204.
Dynamic circuits may be arranged in a series of two or more dynamic circuits. When multiple dynamic circuits are arranged in a series, the output of one dynamic circuit is the input to the next dynamic circuit in sequence. FIG. 2B is a diagram illustrating a circuit 210 that comprises series of three dynamic circuits (named A, B, and C) in conjunction with an input flop and an output flop. As FIG. 2B illustrates, the output of the input flop is the input to dynamic circuit A, the output of dynamic circuit A is the input to dynamic circuit B, and so on.
FIG. 2B also illustrates a timing diagram 212 of the signals of circuit 210. The rising edge of the clock signal triggers each dynamic circuit of circuit 210 to enter evaluation mode contemporaneously. For example, as the timing diagram 212 shows, the rising edge of the clock causes: (1) the input flop to produce data on signal d as output, (2) dynamic circuit A to evaluate its logic using the data signal d as input to produce data on signal q1 as output, (3) dynamic circuit B to evaluate its logic using data on signal q1 as input to produce data on signal q2 as output, and (4) dynamic circuit C to evaluate its logic using data on signal q2 as input to produce data on signal q3 as output.
A problem with storing data, produced by dynamic circuit C, in the output flop may be encountered. The output flop reads the value of signal q3 at the rising edge of the clock. As the timing diagram 212 shows, because of the delays in evaluating the logic of dynamic circuits A, B, and C, when the output flop reads the value of q3, dynamic circuit C has not yet generated an output on signal q3. Also, shortly after the time that dynamic circuit C does produce an output on signal q3, the falling edge of the clock causes dynamic circuit C to enter pre-charge mode, which, in turn, causes dynamic circuit C to output a logical low value on signal q3.
As a result, when the output flop reads the value of signal q3, the value of signal q3 has been driven to a logical low by the prior falling edge of the clock. In effect, the data produced by dynamic circuit C is passing by the output flop without the output flop being able to read the data. Thus, the output flop will never be able to read the output value of dynamic circuit C, and the value of signal q produced by the output flop will always be a logical low, as shown in timing diagram 212.
To solve this problem, a one-shot clock signal may be applied to the last dynamic circuit in the series, e.g., in this case, a one-shot clock signal is applied to dynamic circuit C. A one-shot clock signal is a clock signal that extends the period of time in which the dynamic circuit receiving the one-shot clock signal stays in evaluation mode. In this way, the length of time that the output of dynamic circuit C is available to be read on signal q3 is extended. Thus, the output flop may read the output produced by dynamic circuit C on signal q3 at the next rising edge of the clock signal.
To illustrate this technique, consider FIG. 2C, which is a diagram illustrating a circuit 220, similar to that shown in FIG. 2B, except that a one-shot clock signal is applied to dynamic circuit C in FIG. 2C. FIG. 2C also shows a timing diagram 222 of the circuit 220 shown in FIG. 2C. As shown in the timing diagram 222, the length of time that the data produced by dynamic circuit C on signal q3 is available to be read by the output flop is extended since the one-shot clock signal is applied to dynamic circuit C. Thus, the output flop may read the output produced by dynamic circuit C in signal q3 at the next rising edge of the clock. In this way, signal q produced by the output flop reflects the evaluation of the series of dynamic circuits A, B, and C, instead of always being driven to a logical low value as is the case in FIG. 2B.
On occasion, it has been observed that a set of circuits containing a dynamic circuit receiving a one-shot clock signal may not behave as intended. It is desirable to ensure that circuits behave as intended. Consequently, an approach for ensuring the proper behavior of circuits is desirable.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
USPTO Backgrounds
USPTO Backgrounds