1. Field of the Invention
The present invention relates to a method of layout of pattern.
Priority is claimed on Japanese Patent Application No. 2009-120291, filed May 18, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
For manufacturing a semiconductor device including wirings, a CMP (Chemical Mechanical Polishing) method is generally used to planarize the upper surface of an interlayer insulating film, the interlayer insulating film being formed over the wirings.
When the CMP method is performed to planarize the interlayer insulating layer, the flatness of the upper surface of the interlayer insulating film depends on the density of wiring layers underlying the interlayer insulating film. Therefore, in an area having a low density of wiring, a phenomenon such as dishing is likely to be caused. The upper surface of the interlayer insulating film is over-polished and a concave is formed on the upper surface of the interlayer insulating film. Japanese Unexamined Patent Applications, First Publications, Nos. JP-A-2002-158278 and JP-A-2002-208676 each disclose a technique of adjusting the density of wiring layers by laying out dummy patterns. The dummy patterns are formed by the same layer as the wiring layer which is necessary to operate circuits in the semiconductor device. The dummy patterns are not used for operations of circuits of the semiconductor device.
A scribed area (dicing area) is provided on the periphery of each semiconductor chip. The semiconductor chips are arranged over a semiconductor wafer. The scribed area (dicing area) has a width in the range of approximately 50 μm to approximately 100 μm. The dicing process is carried out to dice the semiconductor wafer into plural semiconductor chips. In the scribed area, various kinds of marks such as an alignment mark are usually disposed. The various kinds of marks such as an alignment mark can be used for alignments of wirings in a previous manufacturing process including diffusion processes for the semiconductor chip. In the scribed area, check patterns are also disposed. The check patterns are laid out to check the states during the manufacturing process of the semiconductor chip. When the aforementioned marks or patterns are optically measured, it is preferable not to lay out the aforementioned marks or patterns near the dummy patterns, in order to prevent malfunction due to interference with dummy patterns. The scribed area has a lower density of wiring than the density of wirings laid out in the semiconductor chip area. The scribed area is lower in wiring density than the semiconductor chip area. Therefore, when the polishing is performed by the CMP method, an over-polishing is likely to be caused. The affection of the over-polishing in the scribed area influences the semiconductor chip forming area, the semiconductor chip forming area being adjacent to the scribed area. The interlayer insulating film will generally be thin in the semiconductor chip forming area. Therefore, the reliability of the semiconductor chip is likely to decreases, and predetermined patterns are likely to be difficult to form during a manufacturing process after an interlayer insulating film is formed.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2002-208676 discloses that to prevent the interlayer insulating film from being thin near the scribed area, CMP dummy patterns are laid out such that the density of the CMP dummy patterns is over 50 percents, and enlarged dummy patterns are laid out.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2002-208676 discloses that dummy patterns are changed in size and the size-changed dummy patterns are then placed such that the density of wirings is over 50 percents in a predetermined area. Therefore, the process for laying out of the dummy patterns will be complicated.
USPTO Backgrounds
USPTO Backgrounds