The present invention pertains to integrated circuit designs providing features which reduce the capacitance on input lines to certain circuit elements such as charge amplifiers.
Parasitic input capacitance is of great importance in charge readout performance. In many integrated circuits containing arrays of data elements (e.g., memory devices having arrays of memory cells and imagers having arrays of pixels), amplifiers read out charge stored on the individual elements of the array. Ideally, the readout should be performed rapidly and accurately. Unfortunately, a large input line capacitance requires that some of the charge initially injected to the amplifier be used to charge the "input line capacitor." This of course slows the readout time and reduces or increases that amount of charge provided to the amplifier.
From the perspective of a charge amplifier, the main effects of input capacitance are (1) time response, (2) gain, and (3) output linearity. If C.sub.L, C.sub.R A, and .delta.Q are the input capacitance, the feedback capacitance, the voltage gain, and the injected charge respectively, the output of the charge amplifier is inversely proportional to C.sub.R according to the relation .DELTA.V.sub.o =.delta.Q/(C.sub.L /A)+(1+(1/A))C.sub.R) and the time response is proportional to the loop gain, C.sub.R /(C.sub.R +C.sub.L). From the previous analysis, two observations can be drawn: (i) the output linearity is seriously affected by the input capacitance for low amplifier gain, and (ii) gain and speed of the amplifier are traded off as in a generic negative feedback system. Thus, the speed of the system benefits greatly from a reduction on the input line capacitance.
For applications as in the field of CMOS optical sensors, the input line capacitance, Cr, is composed of the diffusion and metal capacitances of the line as shown in FIG. 1. There, a photodiode 8 is connected to a charge amplifier input line 10 via a switch 12. Photodiode 8 may be provided in a single pixel of a photodiode array of a CMOS imager, for example. When switch 12 is closed, charge stored on photodiode 8 is provided over input line 10 to a capacitor 16. Charge accumulated on capacitor 16 provides a voltage across the plates of the capacitor, which voltage may be read by an amplifier 14. The detected voltage should represent the charge stored on photodiode 8. A switch 18 is provided to allow reset of photodiode 8. During reset (after readout), switch 18 is closed so that the output of charge integrate toward it is provided to line 10, thereby resetting photodiode 8 while switch 12 is closed. This procedure resets photodiode 8 to reference voltage, V.sub.R.
Input line 10 includes two sources of parasitic capacitance: a metal capacitance illustrated as an idealized capacitor 20 and a diffusion capacitance illustrated as an idealized capacitor 22. The metal capacitance is created by the dielectric between the metal input line and the grounded substrate or other conductive features insulated from but proximate to line 10. Its effect is manifested when a potential change is applied to line 10, thereby changing the charge stored on the capacitor electrodes (i.e., the metal line and the substrate). The diffusion capacitance is created by a p-n junction at the interface of a diffusion (e.g., a photodiode diffusion) and a surrounding well or bulk region. When the diffusion is charged or discharged (as by injecting charge onto line 10), the capacitor defined by a p-n junction depletion region is charged or discharged. For most of integrated circuit designs in production today, about one half of the input line capacitance is due to the metal line (with the other half provided by the diffusion(s)).
In view of the above, it is clear that device performance could be significantly improved by designs that reduce input line capacitance from the diffusion and/or metal line components.
USPTO Backgrounds
USPTO Backgrounds