With the increased demand for computer functionality and speed, improvements are always being made in technologies that affect the ability of an IC board to deliver power to components that reside on the IC board. Because of manufacturing concerns, package stress factors, cost of materials, etc., each generation of technological advances provide some benefit to the existing state of technology capability and provides a segue into the next generation of technological innovation. With the advent of Surface Mount Technology (“SMT”), certain ICs that may be modified, coded or evolve in later generations, so that boards containing these ICs could be easily upgraded, created a practical upgrade and replacement problem.
The solution to this problem resulted in sockets as place-holders and carriages for these evolving ICs. The sockets are surface mounted onto the IC board during the solder re-flow and then the chips requiring socket placement are easily placed and removed from the board when required. As technologies have improved, the traces that connect the power and ground sources of the IC board to the chip have become a limitation because ICs require increasingly more power delivered through the socket. For instance, present SMT socket sizes limit the number of pins to about 800 pins. Of these 800 pins, many will be designated for I/O type signals and the rest are connected to either power or ground planes. As technologies improved for development of the IC and more computational power is attained for any given IC, bottlenecks are created by pin limitations for supplying the power from the IC board to these ever increasingly power hungry IC chips. The problem arises because even though more pins are designated for power transfer, the pin number limitation and the pin and trace size limitation impose natural restrictions on the amount of current that can be transferred across a set of multiple pins designated to a power plane. One of the primary bottleneck limitations is generated by the chip pins and the corresponding socket traces providing the power to those pins. Each pin limits the current going through the pins to between one half of an amp to one amp. Additionally, the electrical power delivery performance is limited by the area where the package pin and socket trace make contact. Because of the limited size of each pin and its corresponding contact area, the resulting resistance and inductance of the contact reduces the current delivery for each pin or provides inconsistent power transfer between one pin and another pin because of irregularities in the contact.
FIG. 12 demonstrates a prior art socket 1210 engaging an IC package 1211. All of the package pins 1201 are inserted into and engage a socket's pin receptacles 1202. A lever 1203 is used for locking the socket pins into place and forcing contact between the pins and their corresponding receptacles. Because of the small size of the pins, limited force can be applied to the pins resulting in inconsistent power transfer results. Additionally, each package pin and socket trace limits the amount of current that can be passed through the pin.
USPTO Backgrounds
USPTO Backgrounds