The present invention relates generally to circuit wiring boards and, more particularly, to ceramic composite circuit wiring boards and/or multichip modules and methods to construct the same.
Semiconductor integrated circuits ("SIC") or semiconductor chips are being developed to operate at increasingly higher speeds and to handle larger volumes of data. This trend has caused the density of electrical interconnections required between the semiconductor chip and the larger electronic system to increase dramatically. Conversely, this ultra-large scale integration restricts the physical dimensions of the SIC. The drive to implement more sophisticated SIC's which require much larger numbers of electrical interconnections to be crammed into smaller physical dimensions creates a technical bottleneck, wherein SIC performance is increasingly limited by the circuit board/package connecting the chip to the larger electronic system.
The industry convention has been to use a lead frame that electrically interconnects the SIC to a printed circuit board ("PCB"), and to envelop the chip and lead frame in a ceramic laminate package. The packaged SIC is socketed to the PCB, which electrically connects the SIC to the larger electronic system. The modern, more sophisticated SIC's generate greater amounts of heat than their predecessors. This heat, if not dissipated from the SIC, reduces circuit performance. Robust lead frames have been able to function as both electrical connection and heat sink, however, as the density of leads per unit area has increased, the physical dimension of the individual lead must be shrunk. Smaller lead sizes sharply limit their function as a heat sink. This has forced system manufacturers to dissipate thermal loads through unmanageably large heat sinks attached to the SICs, which hampers the drive towards smaller, mobile platforms.
Furthermore, the operating speed of the more sophisticated SICs is increasingly limited by the printed circuit board. Conventional PCBs have routed electrical signals between system and SIC through an electrode network patterned on the PCB surface on which the semiconductor chip is mounted. To allow the SIC to operate at higher speed the interconnections between the semiconductor chip and the electronic system must be low-resistance. Lower resistance electrical contact is achieved by shortening electrode length and by decreasing electrode resistivity. Shorter electrode lengths are engineered by embedding an electrical interconnection network within the circuit board rather than one patterned on the surface. The prior art discloses methods to construct multilayer ceramic composite printed circuit boards with electrical interconnection networks embedded within the circuit boards. However, these methods are performance-limited because the embedded electrode network is composed of metallic films, conducting pastes, or both, which have much higher electrical resistance than the wire form of the same conducting metal. Lower-resistance at higher signal frequency is also enhanced by forming the wiring board from low dielectric constant materials. Therefore, circuit wiring board and multichip module designs that comprise electrode networks of conducting metal wire embedded within a low dielectric ceramic, such as silica or alumina, and simultaneously contain heat sinks, embedded within the ceramic to dissipate heat generated by the SIC would be highly desirable.
Relevant prior art includes the following patents. Fujita et al., U.S. Pat. No. 5,396,034, discloses methods to construct a thin film ceramic multilayer wiring hybrid board. Bonham et al., U.S. Pat. No. 5,396,032, discloses the construction of a multi-chip module ("MCM") with two sets of lead frames, one set supplying input/output bond pads, and another independent set to provide electrical contact to test pins that can be used to isolate and examine the performance of one or multiple devices mounted on a substrate within a cavity of said MCM, wherein the device(s) is (are) wire bonded to said pads. The material comprising the MCM package body can be ceramic, plastic, laminate, or metal, but the substrate on which the devices are mounted does not contain internal electrical interconnects and/or heat sinks. Wiesa, U.S. Pat. No. 5,375,039, discloses the construction of a printed circuit board with internal heat dissipation means channeling heat from power units mounted on the board to heat sinks, wherein the core of the printed circuit board comprises glass cloth. Chobot et al., U.S. Pat. No. 5,363,280, discloses methods to construct a multilayer ceramic circuit board in which some metal film layers function as electrode networks, and are separated from other metal film layers which function as heat sinks. Ohtaki et al., U.S. Pat. No. 5,300,163, discloses a process to fabricate a multilayer ceramic circuit board comprising a ceramic substrate, multiple layers of green tape with conductive paste patterns therein, and via holes with conductive paste to electrically interconnect the assembled layers. Cherukuri et al., U.S. Pat. No. 5,256,469, discloses a multilayered co-fired ceramic-on-metal circuit board prepared using ceramic green tapes and a system of low-temperature, high expansion glass ceramics. Capp et al., U.S. Pat. No. 5,113,315, discloses the construction of ceramic circuit board structures in which heat dissipation extensions are embedded in the ceramic member by laser drilling holes into the ceramic member and filling the holes with conductive metal using well-known metal deposition techniques. Plonski, U.S. Pat. No. 4,679,321, discloses a method of making interconnection boards with coaxial wire interconnects on the external major surface of the board substrate that opposes the major surface upon which integrated circuits are mounted. Ushifusa et al., U.S. Pat. No. 4,598,167, discloses the construction of multilayered ceramic circuit board that comprises a plurality of integrally bonded ceramic layers, each having a patterned electrically conducting paste layer and through holes filled with electrical conductors for connecting the patterned electrically conducting layers on respective ceramic layers to form a predetermined wiring circuit. Takeuchi, U.S. Pat. No. 4,551,357, discloses a manufacturing process for ceramic circuit boards that comprises firing a circuit pattern formed from an organic-laden conductive paste on the surface of a green-state ceramic with an organic binder.
It is therefore an object of the present invention to provide a composite wiring structure which enhances SIC performance.
It is another object of this invention to provide a composite circuit wiring structure which increases the allowable operating speeds of SICs.
It is a further object of this invention to reduce compressive and shear stresses within the composite structure.
It is another further object of this invention to provide a composite circuit wiring board structure wherein the structure's dielectric member is either a ceramic or an organo-ceramic composite.
It is still another object of this invention to provide a highly efficient and effective ceramic composite wiring structure for SICs and the method of manufacture thereof.
USPTO Backgrounds
USPTO Backgrounds