In many general purpose input/output interfaces, such as USB Multimedia Card I/O (MMCIO), it is required to provide, via CMOS circuitry, a signal that varies between 0 volts and 3.3 volts and has a controlled rise/fall time to reduce electromagnetic interference (EMI) and supply/ground noise. However, deep submicron technology scales transistor voltages, for example by scaling down threshold voltage, VT, and increasing drive to have a lower gate-to-source voltage (“VGS”), supporting lower supply voltages. This creates a challenge for high-speed I/O circuit designs that require a high output voltage swing.
FIG. 1(a) shows basic driver structures and the voltage level the driver transistors need to tolerate. FIG. 1(a) shows a simple driver with single PMOS transistor device MP1 and NMOS transistor device MN1 as driver transistors. The gate of device MP1 in this case should be driven by a voltage that varies between a low of 3.3 volts minus the maximum VGS for which the device is rated (“VGSmax”), and a high of 3.3 volts, and should support a gate-to-drain maximum voltage (“VGDmax”) and drain-to-source maximum voltage (“VDSmax”) of 3.3V. The gate of device MN1 should be driven by levels that vary from 0 to VGSmax. Device MN1 also needs to support a gate-to-drain voltage (“VGD”), VDS, and a drain substrate reverse voltage VDB of 3.3V. A 3.3V supply usually has a variation of +/−10%, and therefore the junctions may need to tolerate 10% higher voltage than the nominal supply condition, depending on the application.
FIG. 1(b) shows a cascoded driver circuit, where devices MP1′ and MN1′ are protected by cascade PMOS and NMOS devices MP1C and MN1C, respectively. Therefore, in this circuit we can use low voltage transistors, henceforth referred as core transistors, as devices MP1′ and MN1′. Devices MP1C and MN1C should be biased according to their voltage ratings, but in this case also MP1C and MN1C should not be core transistors. In present day CMOS processes, one can have I/O transistor devices with higher VDS, VGD and VDB support by extending the drain region, hereinafter referred to as drain extended transistors (“DETs”), but the limiting voltage for such devices is VGSmax, as it is dependent on the gate oxide thickness. Accordingly, it would be desirable to use the simple architecture shown in FIG. 1(a), if it were possible to limit the VGS and have a simple slew control mechanism.
USPTO Backgrounds
USPTO Backgrounds