With respect to various applications (e.g., integrated circuit applications), it is known to employ driver circuits for driving at least two gated switches, for example, at least two gated power switches and/or power MOSgated devices (e.g., MOSFETs, IGBTs, GTO Thyristors, etc.). Referring now to FIG. 1, there is seen an exemplary MOS-gated circuit 100 according to the prior art. MOS-gated circuit 100 includes first and second gated switches 115, 120 electrically coupled to one another in series, as well as a driver circuit 105 configured to control the conduction states of gated switches 115, 120 via respective gate output signals 125, 130, such that only one of gated switches_115, 120 conducts at any given time. Such circuits are commonly used, for example, in bridge legs for motor drives and the like.
Referring now to FIG. 2, there is seen an exemplary timing diagram showing the turn-on and turn-off times of respective gate output signals 125, 130 for the conventional MOS-gate driver circuit of FIG. 1. Respective output signals 125, 130 are controlled in anti-phase, such that only one of gated switches 115, 120 conducts at any given time.
In actual applications, however, gated switches 115, 120 may be incapable of immediately switching from a conductive state to a non-conductive state in response to respective output signals 125, 130. That is, inherent gate capacitances may result in associated turn-off delay times, during which gated switches 115, 120 remain conductive after receiving turn-off commands from driver circuit 105. Thus, the ideal “anti-phase” control may not prevent simultaneous conduction of gated switches 115, 120. As such, it is known to intentionally provide a “dead-time” after turning off either of gated switches 115, 120, the dead-time being larger than the longest turn off delay of gated switches 115, 120 (e.g., between 1 and 3 μS). During this dead-time, neither of gated switches 115, 120 is controlled to conduct, as shown in FIG. 2.
Although these measures may prevent simultaneous conduction of gated switches 115, 120, the additional dead-time reduces the maximum duty cycle and the modulation depth of the Pulse Width Modulated (PWM) control of gated switches 115, 120. For example, with respect to a carrier frequency of 20 khz (Period=50 μS) and a 3 μS dead-time, the maximum duty cycle is:1−3/50=94%.
USPTO Backgrounds
USPTO Backgrounds