The present invention relates to a logic LSI in which input data are sampled in synchronization with a clock signal.
A conventional logic LSI includes a logic circuit, a register and a PLL (Phase Locked Loop) circuit. The register is connected to a clock input terminal to an output terminal of the PLL circuit. The register receives input data and generates an output signal Q in synchronization with a clock signal generated in the PLL circuit to have a constant phase. In other words, the logic circuit samples the input data in synchronization with the constant clock signal.
According to the conventional logic LSI, if the input data is shifted in phase, the logic circuit could not sample the input data properly and mistakenly generates an unexpected output data.
Accordingly, an object of the present invention is to provide a data sampling circuit in which input data are sampled at appropriate timings to provide reliability of data sampling even if the input data are phase-shifted.
Another object of the present invention is to provide a method in which input data are sampled at appropriate timings to provide reliability of data sampling even if the input data are phase-shifted.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock. The input data can be sampled at an appropriate point or timing, because the sampling clock is generated in response to the level-turning point of the input data. A level-turning point means a point where the level of a signal changes to the opposite sate, for example, the point can be called xe2x80x9csignal rising pointxe2x80x9d or xe2x80x9csignal falling pointxe2x80x9d. A sampling point means a point where the input data are sampled.
Preferably, the sampling clock has a sampling point provided in the middle of a normal cycle of the input data. The sampling clock may be generated in response to the base clock having a frequency that is eight times greater than the normal frequency of the input data.
In an embodiment, a plurality of source clocks is generated to have different phases shifted one by one, and one of the source clocks is selected as the sampling clock.
In another embodiment, an average phase signal representing the average of phase of plural source clocks, provided in the past, is generated. One from the average phase signal and currently generated sampling clock is selected to provide a sampling clock to be actually used for sampling process. Preferably, a previous sampling clock and currently generated sampling clock are compared to detect a phase difference between them; and the sampling operation is prohibited when the phase difference between the previous sampling clock and currently generated sampling clock is larger than a predetermined threshold value. According to this embodiment, it is not necessary to generate a sampling clock for each cycle of the input data. As a result, power consumption of the circuit can be reduced.
In another embodiment, the sampling clock has a first level-turning point synchronizing with a level-turning point of the input data and a second level-turning point provided right in the middle of a normal cycle of the input data. More precisely, a source clock, which is to be a source of the sampling clock, is generated. The source clock is compared with a predetermined reference signal, and the phase of the source clock is controlled in response to a result of the comparison. According to this embodiment, the sampling point can be provided at the same timing from the level-turning point of the input data regardless the frequency of the base clock. For instance, the sampling point is provided after four cycles of base clock from the detected level-turning point of the input data.
According to a second aspect of the present invention, a data sampling circuit includes an edge detecting circuit which detects level-turning points of input data; a sampling clock generating circuit which generates a sampling clock in response to the level-turning point of the input data; and a logic circuit which samples the input data in synchronization with the sampling clock.
Preferably, according to an embodiment, a data sampling circuit includes a PLL (Phase Locked Loop) circuit which generates a base clock having a frequency that is greater than a normal frequency of input data; an edge detecting circuit which detects level-turning points of the input data in response to the base clock; a source clock generating circuit which generates, in response to the base clock, a plurality of source clocks having different phases shifted by one cycle of the base clock one by one; a clock selecting circuit which selects one from the plural source clocks as the sampling clock so that the sampling clock has a first level-turning point synchronizing with a first level-turning point of the input data and a second level-turning point generated right in the middle of the normal cycle of the input data; and a logic circuit sampling the input data in synchronization with the sampling clock.
Preferably according to another embodiment, a data sampling circuit includes a PLL (Phase Locked Loop) circuit which generates a base clock having a frequency that is greater than a normal frequency of input data; an edge detecting circuit which detects level-turning points of the input data in response to the base clock; a source clock generating circuit which generates a source clock in response to the base clock; a sampling clock generating circuit which generates a sampling clock having a sampling point provided in the middle of a normal cycle of the input data; and a logic circuit sampling the input data in synchronization with the sampling clock. The sampling clock generating circuit includes a source clock generating circuit which generates a source clock, which is to be a source of the sampling clock; and a frequency register which provides a reference signal. The source clock generating circuit compares the source clock with the reference signal; and controls the phase of the source clock in response to a result of the comparison.
USPTO Backgrounds
USPTO Backgrounds