1. Field of the Invention
Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
A semiconductor device (e.g., a dynamic random access memory (DRAM) device) is generally used to memorize information (e.g., data or commands of a program). Information may be inputted into the semiconductor device and/or outputted from the semiconductor device. A unit memory device may include one transistor and one capacitor. The capacitor may include a lower electrode, a dielectric layer and an upper electrode. In order to improve the efficiency of the semiconductor memory device, a capacitance of the capacitor may be increased.
As an integration degree of the semiconductor device is increased, an area per the unit memory cell may be decreased. In order to gain a high capacitance, a structure of the capacitor may have been changed from flat structures to more complex structures (e.g., a box structure and/or a cylindrical structure). In the semiconductor device having a line width of less than about 0.1 μm, an aspect ratio of the capacitor may be increased in order to gain a higher capacitance.
FIGS. 1A and 1B are diagrams illustrating a conventional method of manufacturing a capacitor. Referring to FIG. 1A, an insulating interlayer 10 may be formed on a semiconductor substrate (not shown). A contact hole (not shown) may be formed in the insulating interlayer 10. The contact hole (not shown) may expose a contact region (not shown) in the semiconductor substrate. A pad 15 may be formed in the contact hole (not shown). An etch stop layer 20 may be formed on the pad 15 and the insulating interlayer 10. The etch stop layer 20 may be formed using a nitride.
A mold layer 25 may be formed on the etch stop layer 20. The mold layer 25 may be formed using an oxide (e.g., boro phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), undoped silicate glass (USG), tetra ethyl ortho silicate (TEOS), plasma enhanced-TEOS (PE-TEOS), high density plasma-chemical vapor deposition (HDP-CVD) oxide and/or any other suitable oxide). A mask layer (not shown) may be formed on the mold layer 25.
Referring to FIG. 1B, the mask layer, the mold layer 25 and the etch stop layer 20 may be successively patterned by a photolithography process. An opening 30 exposing the pad 15 may be formed. Before forming a lower electrode of a capacitor, a pre-cleaning process may be performed. The pre-cleaning process may be performed in order to remove contaminants (e.g., a native oxide layer) formed on the exposed pad 15, thereby increasing a capacitance. The precleaning process may be performed by a wet etching process using an etching solution (e.g., a hydrogen fluoride (HF) solution). The mold layer 25 also may include silicon oxide, so that the mold layer 25 may be partially removed in the pre-cleaning process. The etch stop layer 20 including silicon nitride may not be removed.
Because of the difference in etching rates between the mold layer 25 and the etch stop layer 20, an upper portion 30a of the opening 30 may be wider than a lower portion 30b of the opening 30. The opening 30 may have a step-shaped sidewall. A leaning defect may occur because the distance between the adjacent openings 30 may be shortened. The leaning defect may be a phenomenon that lowers electrodes of the capacitor, so that adjacent lower electrodes make contact with each other.
Considering the pre-cleaning process enlarges the width of the opening 30, a method to narrow the width of the opening 30 more than a given width of the opening 30 may reduce the leaning defect. The lower portion 30b of the opening 30 may not be etched in the pre-cleaning process. The lower portion 30b of the opening 30 in the etch stop layer 20 may sustain an original size, thereby not securing sufficient space to form a lower electrode, an upper electrode and a dielectric layer in the lower portion 30b of the opening 30 during the subsequent processes.
USPTO Backgrounds
USPTO Backgrounds