TFT (thin film transistor) backplanes in which TFTs are arranged like an array on the substrates are the backbone parts for various kinds of active matrix displays such as a liquid crystal display, an organic light emitting diode (OLED) display and the like. In the active matrix display, the TFT drives an electro-optic device corresponding to each pixel to display a desired content. As the TFT for such a purpose, a low-temperature polycrystalline silicon (LTPS) TFT, a hydrogenated amorphous silicon (a-Si:H) TFT, and the like are considered.
Further, a technique for simultaneously manufacturing TFTs respectively having different functions on the same substrate as the TFT backplane is considered. More specifically, in this technique, the TFT (pixel circuit) for driving the electro-optic device of each pixel and the peripheral circuits such as a gate driver, a source driver and the like constituted by TFTs are simultaneously manufactured on the same substrate. In this case, since the function of the TFT is different with respect to each of the circuit blocks such as the pixel circuit, the peripheral circuit and the like, it is desirable to adjust the threshold voltage of the TFT for each circuit block. For example, it should be noted that a large threshold voltage suitable for an inverting threshold of the electro-optic device is desired in the pixel circuit, and a small threshold voltage is desired for suppressing power consumption in the peripheral circuit. With this background, Japanese Patent Application Laid-Open No. 2005-072461 discloses a method of adjusting threshold voltages of the TFTs according to pixel blocks in LIPS TFT circuits fabricated using excimer laser annealing (ELA).
The peripheral circuits include digital circuits such as a shift register and the like. Here, it should be noted that, in case of manufacturing the digital circuit by TFTs, the following four constructions (1) to (4) can be employed as a NOT element (inverter): construction (1) is a resistive load, construction (2) is an enhancement-enhancement device (E/E), construction (3) is an enhancement-depletion device (E/D), and construction (4) is a complementary metal-oxide semiconductor (CMOS). Generally, the E/D construction or the CMOS construction is frequently applied with the objective of reducing layout area and achieving high-speed operation. Incidentally, to efficiently operate the E/D inverter, it is necessary to control the threshold voltage of the TFT so as to make the difference between the threshold voltages of the two TFTs constituting the inverter sufficiently large. On the other hand, since both an n-channel TFT and a p-channel TFT are necessary for the CMOS inverter, the respective doping processes for each TFT are required, resulting in a greater number of photolithography processes as compared with other constructions.
Incidentally, as candidates for high-performance TFTs to be used instead of the LIPS TFTs or the a-Si:Hs, TFTs (oxide TFTs) in which oxide semiconductor layers are used as the channel layer have been actively researched and developed. Here, a manufacturing method of an oxide TFT by using an RF-magnetron sputter thin film of amorphous In—Ga—Zn—O (IGZO) as the channel layer is disclosed in the document “Appl. Phys. Lett. 89, 112123 (2006)”. Many kinds of high-mobility oxide semiconductor such as the amorphous IGZO and the like have n-type (electron) conductivity, but do not come to have p-type (hole) conductivity even by doping, whereby the CMOS constitution cannot be used. However, the oxide TFT has the following two advantages. That is, (1) the mobility of the oxide TFT is extremely higher than the mobility of the a-Si:H TFT. For this reason, the document “IEEE Elec. Dev. Lett., 28, p. 273 (2007)”discloses that, even if a saturation load E/E constitution inverter which is inconvenient in the point of an operation speed is used, a high-speed operation which exceeds the a-Si:H TFT inverter can be achieved. Further, (2) sputter-deposition is available for the channel layer. Thus, since a mother glass substrate can be enlarged, the reduction in manufacturing cost according to the enlargement of the substrate can be expected.
Also, various methods of controlling the threshold voltage for the oxide TFT are disclosed in the following documents. First, U.S. Patent Application Publication No. US-2006-0113565 discloses a TFT which includes In, Ga, Zn and O as its constituent elements and uses, as the channel layer, a transparent amorphous oxide thin film of which the electron carrier density is less than 1018 cm−3, and an integrated circuit which uses the relevant TFTs. Further, this document mentions a use of a depletion (D) type TFT, but does not mention a concrete method of controlling Vth in the TFT.
U.S. Patent Application Publication No. US-2006-0244107 discloses a method of, in a TFT which uses zinc oxide (ZnO) as the channel layer, controlling Vth by doping into a channel layer deposition atmosphere.
Further, the document “BAROUINHA ET AL: “Influence of the semiconductor thickness on the electrical properties of transparent TFTs based on indium zinc oxide,” JOURNAL OF NON-CRYSTALLINE SOLIDS, NORTH-HOLLAND PHYSICS PUBLISHING. AMSTERDAM, NL, vol. 352, no. 9-20, 15 Jun. 2006 (2006-06-15), pages 1749-1752 XP005482522, ISSN: 0022-3093,” at FIG. 3 discloses that, in a TFT which uses ZnO as the material of the channel layer, Vth is controlled by the thickness of a deposited channel layer.
Furthermore, the document “Journal of Applied physics, 97, p. 064505 (2005)” discloses that, in a TFT which uses zinc indium oxide (Zn—In—O) as the material of the channel layer, Vth is controlled by a heat treatment temperature.
In any case, all of U.S. Patent Application Publication No. US-2006-0244107, the document “Solid State Electronics, 352 (9-20), p. 1749 (2006)” and the document “Journal of Applied physics, 97, p. 064505 (2005)” disclose that the characteristics of the TFTs respectively manufactured on the different substrates in different conditions are mutually different. However, none of these documents disclose a concrete method of manufacturing the TFTs each having different Vth are manufactured on the same substrate.
In the method disclosed in Japanese Patent Application Laid-Open No. 2005-072461, it is difficult to inexpensively manufacture a TFT digital circuit due to the following two reasons. First, the TFT disclosed in this document is an LIPS TFT. In other words, since the cost increases because the ELA device itself is enlarged even if the mother glass substrate is enlarged, the advantage of manufacturing cost according to the enlargement of the substrate is small. Second, it is impossible to obtain the E/D inverter that effectively operates, since the difference in the TFT threshold voltages acquired in the method disclosed in this document is too small. For this reason, the inverter disclosed in this document has the CMOS constitution, and the photolithography process is complicated as compared with other constitutions, whereby the cost increases.
USPTO Backgrounds
USPTO Backgrounds