The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device having a relaxed sense amplifier arrangement.
In semiconductor memory devices and integrated circuits, a typical example being a dynamic random access memory (DRAM), bit line pairs are disposed with ever decreasing mutual separation or pitch with the increase in the integration density. In relation to such a decrease in the pitch of the bit line pairs, there emerges a difficulty for laying out sense amplifiers with a pitch identical to the pitch of the bit line pairs.
In order to overcome the problem and to achieve a further increase of integration density, a so-called relaxed sense amplifier arrangement is proposed for the array of sense amplifiers.
FIG. 1 shows the overall construction of a DRAM that uses a relaxed sense amplifier arrangement.
Referring to FIG. 1, the DRAM includes a core area 1 that in turn includes arrays of memory cells referred to hereinafter as memory blocks, wherein each memory block includes an array of sense amplifiers. A part of the core area 1 is shown in detail in a plan view of FIG. 2. The memory blocks forming the core area 1 are selected by a block address signal such as block address signals BA0 and BA1.
Hereinafter, the construction of the core area 1 will be explained first with reference to FIG. 2.
Referring to FIG. 2, the core area 1 includes memory blocks A0 and A1, B0 and B1, C0 and C1, D0 and D1 each formed of a memory cell array, wherein the memory blocks A0 and A1 form together a memory block having a block address [00], the memory blocks B0 and B1 form together a memory block having a block address [01], the memory blocks C0 and C1 form together a memory block having a block address [01], and the memory blocks D0 and D1 form together a memory block having a block address [11].
Further, there is provided a sense amplifier array S00 in the core area 1, wherein the sense amplifier array S00 includes sense amplifiers corresponding to odd number bit line pairs extending in the memory block A0 such as the one formed of bit lines BL-A00 and /BL-A00.
Similarly, there is provided a sense amplifier array S01 including sense amplifiers that correspond to even number bit line pairs in the memory blocks A0 and B0, such as the bit line pair formed of bit lines BL-A01 and /BL-A01 or the bit line pair formed of bit lines BL-B01 and /BL-B01.
Further, there is provided a sense amplifier array S10 including sense amplifiers that correspond to odd number bit line pairs in the memory blocks B0 and C0, such as the bit line pair formed of bit lines BL-B00 and /BL-B00 or the bit line pair formed of bit lines BL-C00 and /BL-C00.
Further, there is provided a sense amplifier array S11 including sense amplifiers that correspond to even number bit line pairs in the memory blocks C0 and D0, such as the bit line pair formed of bit lines BL-C01 and /BL-C01 or the bit line pair formed of bit lines BL-D01 and /BL-D01.
Further, there is provided a sense amplifier array S20 including sense amplifiers that correspond to odd number bit line pairs in the memory blocks D0 and A1, such as the bit line pair formed of bit lines BL-D00 and /BL-D00 or the bit line pair formed of bit lines BL-A10 and /BL-A10.
Further, there is provided a sense amplifier array S21 including sense amplifiers that correspond to even number bit line pairs in the memory blocks A1 and B1, such as the bit line pair formed of bit lines BL-A11 and /BL-A11 or the bit line pair formed of bit lines BL-B11 and /BL-B11.
Further, there is provided a sense amplifier array S30 including sense amplifiers that correspond to odd number bit line pairs in the memory blocks B1 and C1, such as the bit line pair formed of bit lines BL-B10 and /BL-B10 or the bit line pair formed of bit lines BL-C10 and /BL-C10.
Further, there is provided a sense amplifier array S31 including sense amplifiers that correspond to even number bit line pairs in the memory blocks C1 and D1, such as the bit line pair formed of bit lines BL-C11 and /BL-C11, or the bit line pair formed of bit lines BL-D11 and /BL-D11.
Further, there is provided a sense amplifier array S40 including sense amplifiers that correspond to odd number bit line pairs in the memory blocks D1, such as the bit line pair formed of bit lines BL-D10 and /BL-D10.
As the sense amplifiers corresponding only to the odd number bit line pairs or only to the even number bit line pairs are thus aligned in each of the sense amplifier arrays S00, S01, S10, S11, S20, S21, S30, S31 and S40 in such a DRAM having the relaxed sense amplifier arrangement, a sufficient mutual separation is secured between adjacent sense amplifiers in each of the sense amplifier arrays.
Further, the core area 1 includes data lines LDB00 and /LDB00 referred to hereinafter as local data bus, wherein the local data bus (LDB00, /LDB00) corresponds to the sense amplifier array S00 and is connected commonly to the odd number bit line pairs included in the memory block A0 such as the bit line pair (BL-A00, /BL-A00).
Similarly, there is provided a local data bus (LDB01, /LDB01) in correspondence to the sense amplifier array Sol such that the local data bus (LDB01, /LDB01) is connected commonly to the even number bit line pairs included in the memory blocks A0 and B0 such as the bit line pair (BL-A01, /BL-A01) or (BL-B01, /BL-B01).
Further, there is provided a local data bus (LDB10, /LDB10) in correspondence to the sense amplifier array S10 such that the local data bus (LDB10, /LDB10) is connected commonly to the odd number bit line pairs included in the memory blocks B0 and C0 such as the bit line pair (BL-B00, /BL-B00) or (BL-C00, /BL-C00).
Further, there is provided a local data bus (LDB11, /LDB11) in correspondence to the sense amplifier array S11 such that the local data bus (LDB11, /LDB11) is connected commonly to the even number bit line pairs included in the memory blocks C0 and D0 such as the bit line pair (BL-C01, /BL-C01) or (BL-D01, /BL-D01).
Further, there is provided a local data bus (LDB20, /LDB20) in correspondence to the sense amplifier array S20 such that the local data bus (LDB20, /LDB20) is connected commonly to the odd number bit line pairs included in the memory blocks D0 and A10 such as the bit line pair (BL-D00, /BL-D00) or (BL-A10, /BL-A10).
Further, there is provided a local data bus (LDB21, /LDB21) in correspondence to the sense amplifier array S21 such that the local data bus (LDB21, /LDB21) is connected commonly to the even number bit line pairs included in the memory blocks A1 and B1 such as the bit line pair (BL-A11, /BL-A11) or (BL-B11, /BL-B11).
Further, there is provided a local data bus (LDB30, /LDB30) in correspondence to the sense amplifier array S30 such that the local data bus (LDB30, /LDB30) is connected commonly to the odd number bit line pairs included in the memory blocks B1 and C1 such as the bit line pair (BL-B10, /BL-B10) or (BL-C10, /BL-C10).
Further, there is provided a local data bus (LDB31, /LDB31) in correspondence to the sense amplifier array S31 such that the local data bus (LDB31, /LDB31) is connected commonly to the even number bit line pairs included in the memory blocks C1 and D1 such as the bit line pair (BL-C11, /BL-C11) or (BL-D11, /BL-D11).
Further, there is provided a local data bus (LDB40, /LDB40) in correspondence to the sense amplifier array S40 such that the local data bus (LDB40, /LDB40) is connected commonly to the odd number bit line pairs included in the memory block D1 such as the bit line pair (BL-D10, /BL-D10).
FIG. 3 shows a part of the memory blocks A0 and B0 as well as a part of the sense amplifier array S01, wherein it will be noted that the memory block A0 further includes word lines WL-A00 and WL-A01 extending perpendicularly to bit lines such as BL-A02 and /BL-A02, BL-A03 and /BL-A03, . . . , wherein the word lines are used for selecting a memory cell in the memory cell array as usual. Similarly, the memory block B0 includes word lines WL-B00 and WL-B01 extending perpendicularly to bit lines BL-B02 and /BL-B02, BL-B03 and /BL-B03, . . . . It should be noted that each of the bit lines BL-A02 and /BL-A02, BL-A03 and /BL-A03, . . or bit lines BL-B02 and /BL-B02, BL-B03 and /BL-B03, . . . are connected to a series of memory cells including memory cells 3-18 and forms a data transfer path.
FIG. 4 shows the construction of a memory cell such as the memory cell 3. As usual, the memory cell includes a cell capacitor 20 for storing information in the form of electric charges and a cell transistor for charging and discharging the cell capacitor 20, wherein a cell place voltage VCP is applied to the cell capacitor 20. The other memory cells 4-18 have the same construction.
FIG. 3 further shows bit line precharging circuits (PR) P-A02, P-A03, P-A04, P-A05, P-B02, P-B03, P-B04 and P-B05 connected respectively to the bit line pairs (BL-A02, /BL-A02), (BL-A03, /BL-A03), (BL-A04, /BL-A04), (BL-A05, /BL-A05), (BL-B02, /BL-B02), (BL-B03, /BL-B03), (BL-B04, /BL-B04) and (BL-B05, /BL-B05), wherein the detailed construction of the precharging circuit P-A02 is represented in FIG. 5. It should be noted that the other precharging circuits P-A03, P-A04, P-A05, P-B02, P-B03, P-B04 and P-B05 have the same construction.
Referring to FIG. 5, the bit line precharging circuit P-A02 includes a precharging line 23 carrying a bit line precharging voltage VPR, a signal line 24 carrying a bit line precharging signal xcfx86PR, and n-channel MOS transistors 25, 26 and 27 connected across the bit lines BL-A02 and /BL-A02, wherein the MOS transistors 25, 26 and 27 are turned ON and turned OFF in response to the bit line precharging signal xcfx86PR on the line 24.
FIG. 3 further shows a line 29 carrying a bit line transfer signal BT-A0 and transfer circuits B-A03 and B-A05 cooperating with the line 29, wherein the bit line transfer circuits B-A03 and B-A05 include n-channel MOS transistors 30-33 that are turned ON and turned OFF in response to the bit line transfer signal BT-A0 on the line 29.
Similarly, FIG. 3 further shows a line 34 carrying a bit line transfer signal BT-B0 and transfer circuits B-B03 and B-B05 cooperating with the line 34, wherein the bit line transfer circuits B-B03 and B-B05 include n-channel MOS transistors 35-38 that are turned ON and turned OFF in response to the bit line transfer signal BT-B0 on the line 34.
FIG. 3 further shows sense amplifiers 39 and 40 respectively cooperating with the transfer circuits B-A03 and B-A04 having a construction represented in detail in FIG. 6.
Referring to FIG. 6, the sense amplifier 39 or 40 includes a power line 42 for supplying a voltage Vii produced by decreasing the supply voltage Vcc of 5 volts to 3 volts, for example. The sense amplifier 39 further includes a signal line 43 for carrying a latch enable signal /LE and a p-channel MOS transistor 44 that is turned ON and turned OFF in response to the latch enable signal /LE.
Further, the sense amplifier 39 includes another power line 45 for supplying a supply voltage Vss typically of 0 volt, a signal line 46 for carrying a latch enable signal LE that is a logic inversion of the signal /LE, and a n-channel MOS transistor 47 that is turned ON and turned OFF in response to the latch enable signal LE.
Further, the sense amplifier 39 includes a flip-flop circuit 48 formed of p-channel MOS transistors 49 and 50 and n-channel MOS transistors 51 and 52, wherein the p-channel MOS transistors 49 and 50 act as a pull-up transistor while the n-channel MOS transistors 51 and 52 act as a pull-down transistor, as usual in a flip-flop circuit.
FIG. 3 further shows column gates 54 and 55 respectively cooperating with the sense amplifier 39 and 40, wherein the column gate 54 includes n-channel MOS transistors 56 and 57 that are turned ON and turned OFF in response to a column select signal CL3 supplied commonly to the gates of the transistors 56 and 57. Similarly, the column gate 55 includes n-channel MOS transistors 58 and 59 that are turned ON and OFF in response to a column select signal CL5 supplied commonly to the gates of the transistors 58 and 59.
Referring back now to FIG. 2, the core area 1 further includes data lines connected commonly to the local data buses (LDB00, /LDB00), (LDB10, /LDB10), (LDB40, /LDB40) and forming a global data bus (GDB00, /GDB00).
Similarly, the core area 1 includes data lines connected commonly to the local data buses (LDB01, /LDB01) and (LDB11, /LDB11) and forming a global data bus (GDB01, /GDB01).
Further, the core area 1 includes data lines connected commonly to the local data buses (LDB20, /LDB20) and (LDB30, /LDB30) and forming a global data bus (GDB10, /GDB10).
Further, the core area 1 includes data lines connected commonly to the local data buses (LDB21, /LDB21) and (LDB31, /LDB31) and forming a global data bus (GDB11, /GDB11).
In addition, the core area 1 of FIG. 2 shows a hierarchical data bus switch P00 connecting the local data bus LDB00 to the global data bus GDB00 and a hierarchical data bus switch Q00 connecting the local data bus /LDB00 to the global data bus /GDB00.
Further, the core area 1 includes a hierarchical data bus switch P01 connecting the local data bus LDB01 to the global data bus GDB01 and a hierarchical data bus switch Q01 connecting the local data bus /LDB01 to the global data bus /GDB01.
Further, the core area 1 includes a hierarchical data bus switch P10 connecting the local data bus LDB10 to the global data bus GDB00 and a hierarchical data bus switch Q10 connecting the local data bus /LDB10 to the global data bus /GDB00.
Further, the core area 1 includes a hierarchical data bus switch P11 connecting the local data bus LDB11 to the global data bus GDB01 and a hierarchical data bus switch Q11 connecting the local data bus /LDB11 to the global data bus /GDB01.
Further, the core area 1 includes a hierarchical data bus switch P20 connecting the local data bus LDB20 to the global data bus GDB10 and a hierarchical data bus switch Q20 connecting the local data bus /LDB20 to the global data bus /GDB10.
Further, the core area 1 includes a hierarchical data bus switch P21 connecting the local data bus LDB21 to the global data bus GDB11 and a hierarchical data bus switch Q21 connecting the local data bus /LDB21 to the global data bus /GDB11.
Further, the core area 1 includes a hierarchical data bus switch P30 connecting the local data bus LDB30 to the global data bus GDB10 and a hierarchical data bus switch Q30 connecting the local data bus /LDB30 to the global data bus /GDB10.
Further, the core area 1 includes a hierarchical data bus switch P31 connecting the local data bus LDB31 to the global data bus GDB11 and a hierarchical data bus switch Q31 connecting the local data bus /LDB31 to the global data bus /GDB11.
Further, the core area 1 includes a hierarchical data bus switch P40 connecting the local data bus LDB40 to the global data bus GDB00 and a hierarchical data bus switch Q40 connecting the local data bus /LDB40 to the global data bus /GDB00.
As represented in FIG. 7, the hierarchical data bus switches P00, Q00, P01, Q01. P10, Q10, P11, Q11, P20, Q20, P21, Q21, P30, Q30, P31, Q31, P40 and Q40 are formed of respective n-channel MOS transistors, wherein the MOS transistors forming the hierarchical bus switches P00 and Q00 are controlled by a control signal S00, the MOS transistors forming the hierarchical bus switches P01 and Q01 are controlled by a control signal S01, the MOS transistors forming the hierarchical bus switches P10 and Q10 are controlled by a control signal S10, the MOS transistors forming the hierarchical bus switches P11 and Q11 are controlled by a control signal S11, the MOS transistors forming the hierarchical bus switches P20 and Q20 are controlled by a control signal S20, the MOS transistors forming the hierarchical bus switches P21 and Q21 are controlled by a control signal S21, the MOS transistors forming the hierarchical bus switches P30 and Q30 are controlled by a control signal S30, the MOS transistors forming the hierarchical bus switches P31 and Q31 are controlled by a control signal S31, and the MOS transistors forming the hierarchical bus switches P40 and Q40 are controlled by a control signal S40.
Referring now back to FIG. 1, the DRAM further includes, in addition to the foregoing core area 1, a read/write circuit 61 that in turn includes an array of sense buffer circuits (SB) for reading the data by amplifying the voltage appearing across the data lines forming the global data bus and an array of write amplifiers (WA) for writing data by applying a voltage across the data lines forming the global data bus.
More specifically, the read/write circuit 61 includes a sense buffer 62 connected to the global data bus (GDB00, /GDB00), a sense buffer 63 connected to the global data bus (GDB01, /GDB01), a sense buffer 64 connected to the global data bus (GDB10, /GDB10), and a sense buffer 65 connected to the global data bus (GDB11, /GDB11). Further, the circuit 61 includes a write amplifier 66 connected to the global data bus (GDB00, /GDB00), a write buffer 67 connected to the global data bus (GDB01, /GDB01), a write amplifier 68 connected to the global data bus (GDB10, /GDB10), and a write buffer 69 connected to the global data bus (GDB11, /GDB11).
Further, the DRAM of FIG. 1 includes an input/output circuit 70 cooperating with the foregoing read/write circuit 61, wherein the input/output circuit 70 includes a data output buffer (DOB) 71 provided in correspondence to the sense buffer circuit 62, a data output buffer 72 provided in correspondence to the sense buffer circuit 63, a data output buffer 73 provided in correspondence to the sense buffer circuit 64, and a data output buffer 74 provided in correspondence to the sense buffer circuit 65.
Further, the input/output circuit 70 includes a data input buffer (DIB) 75 provided in correspondence to the write amplifier 66, a data input buffer 76 provided in correspondence to the write amplifier 67, a data input buffer 77 provided in correspondence to the write amplifier 68, and a data input buffer 78 provided in correspondence to the write amplifier 69.
Further, an input/output terminal 79 is provided in correspondence to the data output buffer 71 and the data input buffer 75, an input/output terminal 80 is provided in correspondence to the data output buffer 72 and the data input buffer 76, an input/output terminal 81 is provided in correspondence to the data output buffer 73 and the data input buffer 77, and an input/output terminal 82 is provided in correspondence to the data output buffer 74 and the data input buffer 78. In FIG. 1, DQ0, DQ1, DQ2 and DQ3 designate the write data or read data appearing at the foregoing terminals 79-82.
FIG. 8 shows the construction of the sense buffer 62, wherein it should be noted that the other sense buffers 63-65 have the same construction.
Referring to FIG. 8, it will be noted that the sense buffer 62 forms a differential amplifier amplifying the voltage appearing across the lines forming the global data bus (GDB00, /GDB00) and includes p-channel MOS transistors 85-96 and n-channel MOS transistors 97-106 forming together a current mirror circuit, wherein the transistors 101-106 are turned on in response to an enable signal SBE.
Further, the sense buffer 62 of FIG. 8 includes a flip-flop circuit 107 for latching the output of the differential amplifier 84, wherein the flip-flop circuit 107 includes p-channel MOS transistors 108 and 109, NAND gates 110 and 111 and an inverter 112.
Further, the sense buffer 62 cooperates with an output control circuit 113, wherein the circuit 113 in turn includes inverters 114 and 115 connected in series to a NAND gate 116, wherein the output of the sense buffer 62 is supplied to one of the input terminals of the NAND gate 116, while the other input terminal of the NAND gate 116 is supplied with a CAS (column address strobe) enable signal /CE. Thereby, the output of the sense buffer 62 is obtained at the output terminal of the inverter 115 as a signal D62.
When the circuits related to the CAS signal, or CAS system, is to be deactivated, the CAS enable signal /CE is set high (referred to hereinafter as xe2x80x9cHxe2x80x9d). Thereby, the output of the inverter 114 goes low (referred to hereinafter as xe2x80x9cLxe2x80x9d), and the output of the NAND circuit 116 is held at the level H. Thereby, the output data D62 of the sense buffer 62 is set to the level L.
When the CAS system is to be activated, on the other hand, the CAS enable signal /CE is set to the level L and the output of the inverter 114 goes high to the level H. Thereby, the NAND gate 116 acts as an inverter and inverts the output logic level of the flip-flop circuit 107.
When it is necessary to deactivate the sense buffer 62 in the state that the enable signal /CE is low, the level of the enable signal SBE is set to L. Thereby, the p-channel MOS transistors 89 and 90 are all turned on and the n-channel MOS transistors 101-106 are all turned OFF. As a result, the differential amplifier 84 is deactivated. Further, the p-channel MOS transistors 108 and 109 are turned ON, and the flip-flop circuit 107 does not change the output state thereof.
On the other hand, when it is necessary to activate the sense buffer 62 in the state that the /CE signal is low, the enable signal SBE is set to the level H. As a result, the p-channel MOS transistors 89 and 90 are turned OFF and the n-channel MOS transistors 101-106 are all turned ON. Thereby, the differential amplifier 84 is activated and the p-channel MOS transistors 108 and 109 are turned OFF. In this state, the flip-flop circuit 107 latches the output of the differential amplifier 84.
In the case in which the level of the global bus data line GDB00 is high and the level of the global data bus line /GDB00 is low, for example, it will be noted that a node N1 of FIG. 8 assumes a high level, a node N2 assumes a low level, a node N3 assumes a low level and a node N4 assumes a high level.
As a result of this, the NAND circuit 111 produces a low level output, while the low level output of the NAND circuit 111 causes the inverter 112 to produce a high level output. Thereby, the high level output of the inverter 112 is forwarded to the inverter 115 via the NAND gate 116, wherein the inverter 115 produces a high level output as the output data D62 of the sense buffer circuit 62.
When the level of the global bus data line GDB00 is low and the level of the global data bus line /GDB00 is high, on the other hand, the node N1 assumes a low level, the node N2 assumes a high level, a node N3 assumes a high level and a node N4 assumes a low level.
As a result of this, the NAND circuit 111 produces a high level output, while the high level output of the NAND circuit 111 causes the inverter 112 to produce a low level output. Thereby, the low level output of the inverter 112 is forwarded to the inverter 115 via the NAND gate 116, wherein the inverter 115 produces a low level output as the output data D62 of the sense buffer circuit 62.
FIG. 9 shows the construction of the data output buffer 71, wherein it should be noted that other buffer circuits 72-74 have the same construction.
Referring to FIG. 9, the data output buffer 71 includes inverters 118-121, NAND gates 122 and 123, p-channel MOS transistors 124-134, n-channel MOS transistors 135-143, and MOS capacitors 144 and 145, wherein a start-up control signal /STT is supplied to the inverter 121 at the time of starting up of the DRAM operation. Further, the data output buffer 71 is supplied with an output enable signal OE.
After the operation of the DRAM has started, the control signal /STT is set to have a low level, and the inverter 121 produces a high level output in response thereto. Thereby, the inverter 119 and the NAND circuit 122 form together a latch circuit once the operation of the DRAM has started. Similarly, the inverter 120 and the NAND circuit 123 form together a latch circuit.
In order to deactivate the data output buffer 71 in the operational state of the DRAM, the output enable signal OE is set to have a low level state such that the n-channel MOS transistors 135 and 139 are all turned OFF and the p-channel MOS transistors 125 and 131 are all turned ON.
As a result of this, the inverter 119 produces a low level output, and a node N5 assumes a low level state and a node N6 assumes a high level state in response thereto. Thereby, the p-channel MOS transistor 129 is turned OFF. Further, in response to the low level state of the output enable signal OE, a node N7 assumes a high level state and a node N8 assumes a low level state. Thereby, the n-channel MOS transistor 143 is turned OFF, and the data buffer circuit 71 assumes a high impedance state at the output terminal 79.
When to activate the data output buffer 71, on the other hand, the output enable signal OE is set to have a high level state such that the n-channel MOS transistors 135 and 139 are turned ON. At the same time, the p-channel MOS transistors 125 and 131 are turned OFF.
In the event the output D62 of the sense buffer 62 has a high level state, the inverter 118 produces a low level output and the inverter 119 assumes a high level state. Thereby, the node N5 assumes a high level state, the node N6 assumes a low level state, the p-channel MOS transistor 129 is turned ON, the inverter 120 produces a low level output, the node N7 assumes a high level output, and the node N8 assumes a low level output. Thus, the n-channel MOS transistor 143 is turned OFF and a high level state appears at the output terminal 79 as the output data DQ0.
When the output D62 of the sense buffer 62 has a low level state, on the other hand, the inverters 118 and 119 produces respectively a high level output and a low level output. Thereby, the node N5 assumes a low level state, the node N6 assumes a high level state , the p-channel MOS transistor 129 is turned OFF, the inverter 120 produces a high level output, the node N7 assumes a low level output, and the node N8 assumes a high level output. Thus, the n-channel MOS transistor 143 is turned ON and a low level state appears at the output terminal 79 as the output data DQ0.
FIG. 10 shows the construction of the data input buffer 75, wherein it should be noted that the other data input buffers 76-78 have the same construction.
Referring to FIG. 10, the data input buffer 75 includes an input circuit 146 that in turn includes p-channel MOS transistors 147-152, n-channel MOS transistors 153-158, inverters 159 and 160 and a NAND circuit 161. The data input buffer circuit 75 is thereby supplied with a write enable signal /WE and produces output data D75 at an output terminal.
In FIG. 10, it will be noted that the data input buffer 75 further includes an input control circuit 162 that controls the operation of the input circuit 146. It should be noted that the input control circuit 162 includes inverters 163 and 164, p-channel MOS transistors 165 and 166 and n-channel MOS transistors 167 and 168, and is controlled by an input control signal /ASW.
When the control signal /ASW has a high level state, for example, the inverter 163 produces a low level output, the inverter 164 produces a high level output, and the control circuit 162 produces a high level output.
As a result of this, the p-channel MOS transistor 147 and the n-channel MOS transistor 154 both forming the input circuit 146 are respectively turned OFF and turned ON, and the inverter circuit formed of the p-channel MOS transistors 147 and 148 and the n-channel MOS transistor 153 is deactivated. Further, the level of a node is set to a low level, and the transfer of the input data DQ0 at the node 79 to the NAND gate 161 is prohibited.
When the level of the input control signal /ASW is set to the low level state L, on the other hand, the inverter 163 produces a high level output, the inverter 164 produces a low level output, and the input control circuit 162 produces a low level output.
When the output of the control circuit 162 is low as such, the p-channel MOS transistor 147 is turned ON and the n-channel MOS transistor 154 is turned OFF. Thereby, the node N9 assumes a level that is a logic inversion of the input data DQ0.
When the write enable signal /WE goes high in this state, the n-channel MOS transistor 156 is turned ON and the p-channel MOS transistor 151 is turned OFF. Further, the output of the inverter 159 goes low, the p-channel MOS transistor 149 is turned ON, and the n-channel MOS transistor 158 is turned OFF. Thereby, the output of the NAND gate 161, in other words the output D75 of the buffer 75 is held at a high level state.
When the write enable signal /WE goes low in this state, the n-channel MOS transistor 156 is turned OFF, the p-channel MOS transistor 151 is turned ON, the inverter 159 produces a high level output, the p-channel MOS transistor 149 is turned OFF, and the n-channel MOS transistor 158 is turned ON.
As a result, an inverter circuit, formed of the inverter 160, the p-channel MOS transistors 151 and 152 and the n-channel MOS transistors 157 and 158, operates as a latch circuit and latches the data that is outputted by an inverter circuit formed of the p-channel MOS transistors 149 and 159 and the n-channel MOS transistors 155 and 156.
In this operation, it should be noted that the NAND circuit 161 operates, in view of the high level output of the inverter 159, as an inverter for inverting the logic level of the output of the inverter 160.
In the foregoing operation, it should also be noted that the inverter circuit formed of the inverter 160, the p-channel MOS transistors 151 and 152 and the n-channel MOS transistors 157 and 158, latches the data that is produced by the inverter circuit formed of the p-channel MOS transistors 149 and 150 and the n-channel MOS transistors 155 and 156.
Thus, in the case that the input data DQ0 has a high level state H, the node N9 assumes a low level state, the node N10 assumes a high level state and the inverter 160 produces a low level output. In this case, the output D75 of the data input buffer 75 assumes a high level state.
When the input data DQ0 has a low level state, on the other hand, the node N9 assumes a high level state, the node N10 assumes a low level state and the inverter 160 produces a high level output. Thereby, the output D75 of the data input buffer 75 assumes a low level state.
FIG. 11 shows the construction of the write amplifier 66, wherein it should be noted that the other write amplifiers 67-69 have the same construction.
Referring to FIG. 11, the write amplifier 66 includes inverters 171-176, analog switch circuits 177 and 178, p-channel MOS transistors 179 and 180, and n-channel MOS transistors 181 and 182.
In the case the write enable signal WE has a low level state L, the inverter 175 produces a high level output, the inverter 176 produces a low level output, and the analog switch circuits 177 and 178 are turned OFF.
When the write enable signal WE has a high level state H, the inverter 175 produces a low level output, the inverter 176 produces a high level output, and the analog switch circuits 177 and 178 are both turned ON.
Thus, when the output D75 of the data input buffer 75 has a high level state, it will be noted from FIG. 11 that the inverter 171 produces a low level output, the inverter 172 produces a high level output, the inverter 173 produces a low level output and the inverter 174 produces a high level output. Thereby, the data line GDB00 forming a global data bus assumes a high level state and the other data line /GDB00 also forming the same global data bus assumes a low level state.
When the output D75 of the data input buffer 75 has a low level state, on the other hand, the inverter 171 produces a high level output, the inverter 172 produces a low level output, the inverter 173 produces a high level output and the inverter 174 produces a low level output. Thereby, the data line GDB00 forming the global data bus has a low level state and the data line /GDB00 forming also the global data bus has a high level state.
In the conventional DRAM explained heretofore, it is assumed that the DRAM has a relaxed sense amplifier design as noted already.
In such a conventional DRAM having a relaxed sense amplifier arrangement, the control signals S00, S01, S20 and S21 are set to have a high level state and the control signals S10, S11, S30, S31 and S40 are set to have a low level state when selecting the memory blocks A0 and A1, see FIG. 2. In correspondence to this, the hierarchical data bus switches P00, Q00, P01, Q01, P20, Q20, P21 and Q21 are all turned ON and the hierarchical data bus switches P10, Q10, P11, Q11, P30, Q30, P31, Q31, P40 and Q40 are all turned OFF.
Thereby, the local data bus (LDB00, /LDB00) is connected to the global data bus (GDB00, /GDB00), the local data bus (LDB01, /LDB01) is connected to the global data bus (GDB01, /GDB01), the local data bus (LDB20, /LDB20) is connected to the global data bus (GDB10, /GDB10), and the local data bus (LDB21, /LDB21) is connected to the global data bus (GDB11, /GDB11).
In the reading operation, therefore, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block A0, is amplified by a corresponding sense amplifier included in the sense amplifier array S00 and is further transferred to the global data bus (GDB00, /GDB00) via the local data bus (LDB00, /LDB00).
Similarly, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block A0, is amplified by a corresponding sense amplifier included in the sense amplifier array S01 and is further transferred to the global data bus (GDB01, /GDB01) via the local data bus (LDB01, /LDB01).
Further, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block A1, is amplified by a corresponding sense amplifier included in the sense amplifier array S20 and is further transferred to the global data bus (GDB10, /GDB10) via the local data bus (LDB20, /LDB20).
Further, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block A1, is amplified by a corresponding sense amplifier included in the sense amplifier array S21 and is further transferred to the global data bus (GDB11, /GDB11) via the local data bus (LDB21, /LDB21).
TABLE I below summarizes, in the first row, the memory cell data obtained at the output terminals 79-82 for the case in which the memory blocks A0 and A1 are selected, wherein the data A0-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block A0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S00, the data A0-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block A0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S01, the data A1-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block A1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S20, and the data A1-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block A1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S21.
A similar relationship holds also between the input data DQ0-DQ3 supplied respectively to the input/output terminals 79-82 and the memory cell column into which the foregoing input data is written, as is represented in the first row of TABLE II below.
When selecting the memory blocks B0 and B1 in the foregoing conventional DRAM, the control signals S01, S10, S21 and S30 are set to have a high level state and the control signals S00, S11, S20, S31 and S40 are set to have a low level state. In correspondence to this, the hierarchical data bus switches P01, Q01, P10 Q10, P21, Q21, P30 and Q30 are all turned ON and the hierarchical data bus switches P00, Q00, P11, Q11, P20, Q20, P31, Q31, P40 and Q40 are all turned OFF.
Thereby, the local data bus (LDB01, /LDB01) is connected to the global data bus (GDB01, /GDB01), the local data bus (LDB10, /LDB10) is connected to the global data bus (GDB00, /GDB00), the local data bus (LDB21, /LDB21) is connected to the global data bus (GDB11, /GDB11), and the local data bus (LDB30, /LDB30) is connected to the global data bus (GDB10, /GDB10).
In the reading operation, therefore, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block B0, is amplified by a corresponding sense amplifier included in the sense amplifier array S10 and is further transferred to the global data bus (GDB00, /GDB00) via the local data bus (LDB10, /LDB10).
Similarly, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block BC, is amplified by a corresponding sense amplifier included in the sense amplifier array S01 and is further transferred to the global data bus (GDB01, /GDB01) via the local data bus (LDB01, /LDB0l).
Further, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block B1, is amplified by a corresponding sense amplifier included in the sense amplifier array S30 and is further transferred to the global data bus (GDB10, /GDB10) via the local data bus (LDB30, /LDB30).
Further, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block B1, is amplified by a corresponding sense amplifier included in the sense amplifier array S21 and is further transferred to the global data bus (GDB11, /GDB11) via the local data bus (LDB21, /LDB21).
TABLE I, second row, also summarizes the memory cell data obtained at the output terminals 79-82 when the memory blocks B0 and B1 are selected, wherein the data B0-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block B0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S10, the data B0-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block B0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S01, the data B1-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block B1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S30, and the data B1-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block B1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S21.
A similar relationship holds also between the input data DQ0-DQ3 supplied respectively to the input/output terminals 79-82 and the memory cell column into which the foregoing input data is written, as is represented in the second row of TABLE II.
When selecting the memory blocks C0 and C1 in the foregoing conventional DRAM, the control signals S10, S11, S30 and S31 are set to have a high level state and the control signals S00, S01, S20, S21 and S40 are set to have a low level state. In correspondence to this, the hierarchical data bus switches P10, Q10, P11, Q11, P30, Q30, P31 and Q31 are all turned ON and the hierarchical data bus switches P00, Q00, P01, Q01, P20, Q20, P21, Q21, P40 and Q40 are all turned OFF.
Thereby, the local data bus (LDB10, /LDB10) is connected to the global data bus (GDB00, /GDB00), the local data bus (LDB11, /LDB11) is connected to the global data bus (GDB01, /GDB01), the local data bus (LDB30, /LDB30) is connected to the global data bus (GDB10, /GDB10), and the local data bus (LDB31, /LDB31) is connected to the global data bus (GDB11, /GDB11).
In the reading operation, therefore, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block C0, is amplified by a corresponding sense amplifier included in the sense amplifier array S10 and is further transferred to the global data bus (GDB00, /GDB00) via the local data bus (LDB10, /LDB10.
Similarly, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block C0, is amplified by a corresponding sense amplifier included in the sense amplifier array S11 and is further transferred to the global data bus (GDB01, /GDB01) via the local data bus (LDB11, /LDB11).
Further, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block C1, is amplified by a corresponding sense amplifier included in the sense amplifier array S30 and is further transferred to the global data bus (GDB10, /GDB10) via the local data bus (LDB30, /LDB30).
Further, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block C1, is amplified by a corresponding sense amplifier included in the sense amplifier array S31 and is further transferred to the global data bus (GDB11, /GDB11) via the local data bus (LDB31, /LDB31).
TABLE I, third row, also summarizes the memory cell data obtained at the output terminals 79-82 when the memory blocks C0 and C1 are selected, wherein the data C0-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block C0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S10, the data C0-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block C0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S11, the data C1-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block C1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S30, and the data C1-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block C1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S31.
A similar relationship holds also between the input data DQ0-DQ3 supplied respectively to the input/output terminals 79-82 and the memory cell column into which the foregoing input data is written, as is represented in the third row of TABLE II.
When selecting the memory blocks D0 and D1 in the foregoing conventional DRAM, the control signals S11, S20, S31 and S40 are set to have a high level state and the control signals S00, S01, S10, S21 and S30 are set to have a low level state. In correspondence to this, the hierarchical data bus switches P11, Q11, P20, Q20, P31, Q31, P40 and Q40 are all turned ON and the hierarchical data bus switches P00, Q00, P01, Q01, P10, Q10, P21, Q21, P30 and Q30 are all turned OFF.
Thereby, the local data bus (LDB11, /LDB11) is connected to the global data bus (GDB01, /GDB01), the local data bus (LDB20, /LDB20) is connected to the global data bus (GDB10, /GDB10), the local data bus (LDB31, /LDB31) is connected to the global data bus (GDB11, /GDB11), and the local data bus (LDB40, /LDB40) is connected to the global data bus (GDB00, /GDB00).
In the reading operation, therefore, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block D0, is amplified by a corresponding sense amplifier included in the sense amplifier array S20 and is further transferred to the global data bus (GDB10, /GDB10) via the local data bus (LDB20, /LDB20).
Similarly, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block D0, is amplified by a corresponding sense amplifier included in the sense amplifier array S11 and is further transferred to the global data bus (GDB01, /GDB01) via the local data bus (LDB11, /LDB11).
Further, the data for a selected column, which is selected from the odd number memory cell columns of the memory cell block D1, is amplified by a corresponding sense amplifier included in the sense amplifier array S40 and is further transferred to the global data bus (GDB00, /GDB00) via the local data bus (LDB40, /LDB40).
Further, the data for a selected column, which is selected from the even number memory cell columns of the memory cell block D1, is amplified by a corresponding sense amplifier included in the sense amplifier array S31 and is further transferred to the global data bus (GDB11, /GDB11) via the local data bus (LDB31, /LDB31).
TABLE I, fourth row, also summarizes the memory cell data obtained at the output terminals 79-82 when the memory blocks D0 and D1 are selected, wherein the data D0-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block D0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S20, the data D0-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block D0 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S11, the data D1-0 represents the memory cell data read out from a memory cell column selected from odd number memory cell columns of the memory cell block D1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S40, and the data D1-1 represents the memory cell data read out from a memory cell column selected from even number memory cell columns of the memory cell block D1 and amplified subsequently by a corresponding sense amplifier included in the sense amplifier array S31.
A similar relationship holds also between the input data DQ0-DQ3 supplied respectively to the input/output terminals 79-82 and the memory cell column into which the foregoing input data is written, as is represented in the fourth row of TABLE II.
In the conventional DRAM of the foregoing type, it will thus be noted that the input/output terminals 79, 80, 81 and 82 produce respectively data X0-0, X0-1, X1-0 and X1-1 (X=A, B, C) when the memory blocks X0 and X1 are selected. As already noted, the data X0-0 represents the data read out from an odd number memory cell column of the memory block X0, the data X0-1 represents the data read out from an even number memory cell column of the memory block X0, the data X1-0 represents the data read out from an odd number memory cell column of the memory block X1, and the data X1-1 represents the data read out from an even number memory cell column of the memory block X1.
In other words, there appears a rule, when reading data from the memory blocks X0 and X1, in that the input/output terminals 79, 80, 81 and 82 respectively correspond to an odd number memory cell column of the memory block X0, an even number memory cell column of the memory block X0, an odd number memory cell column of the memory block X1 and an even number memory cell column of the memory block X1.
On the other hand, in the case the memory blocks D0 and D1 are selected for reading, the input/output terminals 79, 80, 81 and 82 respectively produce data D1-0, D0-1, D0-0 and D1-1, wherein the data D1-0 represents the data read out from an odd number memory cell column of the memory block D1, the data D0-1 represents the data read out from an even number memory cell column of the memory block D0, the data D0-0 represents the data read out from an odd number memory cell column of the memory block D0, and the data D1-1 represents the data read out from an even number memory cell column of the memory block D1.
Thus, the data obtained at the terminals 79 and 81 in such a case correspond respectively to the odd number memory cell column of the memory block D1 and the odd number memory cell column of the memory block D0. In such a case, therefore, the correspondence of the data obtained at the terminals 79 and 81 and the memory cell column in the selected memory blocks is different from the correspondence given by the aforementioned rule.
A similar problem occurs also when writing data into selected memory blocks X0 and X1.
In such a case, it will be noted that the data DQ0, DQ1, DQ2 and DQ3 supplied to the input/output terminals 79, 80, 81 and 82 are written respectively into an odd number memory cell column of the memory block X0, an even number memory cell column of the memory block X0, an odd number memory cell column of the memory block X1 and an even number memory cell column of the memory block X1 respectively, provided that X is selected from one of A, B and C, similarly as before.
In this case again, there exists a rule that the data on the data input/output terminals 79, 80, 81 and 82 are written respectively into an odd number memory cell column of the memory block X0, an even number memory cell column of the memory block X0, an odd number memory cell column of the memory block X1 and an even number memory cell column of the memory block X1.
When the memory blocks D0 and D1 are selected, however, the data DQ0, DQ1, DQ2 and DQ3 on the input/output terminals 79, 80, 81 and 82 are written respectively into an odd number memory cell column of the memory block D1, an even number memory cell column of the memory block D0, an odd number memory cell column of the memory block D0 and an even number memory cell column of the memory block D1.
In such a case, therefore, the data input/output terminals 79 and 81 correspond respectively to an odd number memory cell column of the memory block D1 and an odd number memory cell column of the memory block D0, wherein such a relationship contradicts with the foregoing rule for writing data into the memory blocks X0 and X1 for the case in which X is selected from A, B and C.
Such a discrepancy does not cause any problem at all as long as the user of the memory semiconductor device is concerned.
For the manufacturer of the semiconductor device, however, such a violation of the correspondence between the input/output terminals 79-80 and the physical location of the memory cell columns in the memory cell blocks, is important in relation to a test conducted for evaluating the interference between the memory cells. In such a test, it is necessary to identify the location of the tested memory cell that experiences an interference and the location of the memory cell that provides the interference to the tested memory cell. In the absence of the rule describing the correspondence between the input/output terminals 79-82 and the memory cell columns and hence the memory cells in the memory blocks A0 and A1, B0 and B1, C0 and C1 and D0 and D1. it is necessary to use a complicated program in such a test in order to guarantee the proper correspondence between the data on the terminals 79-82 and the memory cells in the selected memory blocks.
In order to eliminate the foregoing problems and to impose a generalized rule applicable to all of the memory blocks A0-D1, it is proposed to provide the hierarchical data bus switches shown in FIGS. 2 and 27 to all of the intersections between the local data buses and the global data buses, in addition to the hierarchical data bus switches P00, Q00-P31, Q31 described in FIGS. 2 and 27. Alternatively, it is propose to provide additional sense amplifier arrays to the memory blocks D0 and A1 (Y. Watanabe, et al., 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp.105-106).
However, the approach to use additional hierarchical bus switches raises a problem in that use of such additional bus switches substantially complicates the circuit layout of the core area 1. On the other hand, the approach to provide sense amplifiers to each of the memory blocks D0 and A1 raises the problem of increased chip area.
Accordingly, it is a general object of the present invention to provide a novel and useful memory semiconductor device wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a memory semiconductor device suitable for an interference test of memory cells, without complicating the layout process and without increasing the chip area.
Another object of the present invention is to provide a memory semiconductor device for storing parallel data formed of a plurality of data bits, comprising:
a memory block array including a plurality of memory blocks each having an address, said memory block array storing said parallel data;
first data transmission means for transmitting said parallel data therethrough, said first data transmission means including a plurality of data transmission paths;
a plurality of input/output terminals corresponding to said plurality of data bits of said parallel data; and
cross connection means provided in said first data transmission means for cross connecting a part of said data transmission paths.
According to the present invention, it is possible to achieve a correspondence between the input/output terminals and the physical location of a memory cell for all of the memory blocks. Thereby, the interference test of the memory cells can be achieved easily for all of the memory blocks, without using a complicated program or providing additional sense amplifier array.
Other objects and further features of the present invention will become apparent from the following description of preferred embodiments when read in conjunction with the attached drawings.
USPTO Backgrounds
USPTO Backgrounds