1. Technical Field
The present teaching relates to a method and system for clock driver and systems incorporating the same. More specifically, the present teaching relates to a method and system for a BiCMOS clock driver and systems incorporating the same.
2. Discussion of Technical Background
Modern signal processing systems frequently digitize and process high speed signals that have a wide dynamic range. Digitization includes both quantizing a signal into discrete levels, e.g., into 2n levels, in an n-bit Analog-to-Digital converter (ADC), as well as sampling a signal at discrete time intervals. Some high speed input signals are at a frequency higher than the sampling rate of the ADC used. This yields a condition called under-sampling, under which a precise repetitive time-based reference is needed. Otherwise, the uncertainty in the timing of the sampling operation may create errors that are larger than that created in a quantizing process. This well known problem is documented in the Background section of U.S. Pat. No. 7,345,528 (hereafter “the '528 patent”), entitled “Method and Apparatus for Improved Clock PreAmplifier with Low Jitter”.
An ideal clock signal for such a system is a repetitive waveform with a perfectly uniform period. Every single cycle should have exactly the same duration as that of all other cycles. The fluctuations in actual clock signals with respect to the durations of each period can be characterized, as jitter (in time domain) or phase noise (in frequency domain). The latter can be converted to the former with certain assumptions. It is commonly recognized that the lower the jitter or phase noise, the more desirable it is.
To achieve a lower phase noise, different attempts have been made. For example, low noise Bipolar Junction Transistor (BJT) circuits can be made in the form of, e.g., Emitter-Coupled Logic (ECL), to achieve sufficiently low phase noise. A BJT circuit preserves the signal speed and noise integrity at low amplitudes.
Conventional CMOS logic circuits may also be used to achieve low phase noise, despite the higher inherent noise in MOSFET devices, due to the fact that the logic swings are large (rail-to-rail) and phase noise is a Signal-to-Noise characteristic. That is, larger noises may be overcome by using higher rail-to-rail signal levels.
CMOS can preserve both speed and noise only if a rail to rail signal swing can be obtained. However, hardly any signal sources for low-phase noise signals, whether a quartz crystal oscillator, a resonant oscillator, or a carrier transmitting a signal through a medium, can deliver true rail-to-rail CMOS logic levels. Therefore, a problem arises when translating a low-phase noise signal from low-levels such as ECL or a small sinusoid waveform to CMOS logic levels.
There are various prior solutions for translating a low-phase noise signal from low levels to CMOS logic levels. Unfortunately, such prior solutions have generally yielded poor phase noise, limited speed, excessive usage of power, or combinations thereof. For instance, a conversion circuit disclosed in U.S. Pat. No. 5,019,726 (hereafter “the '726 patent”), entitled “BiCMOS ECL-TO-CMOS Conversion Circuit,” is driven, at the inputs, by differential ECL signals with a circuit load of three MOSFET gates. The capacitive loading of MOSFET gates in the '726 patent either limits the speed at which a circuit can operate, or requires substantial power to drive the gates. Depending on the implementation, the solution proposed by the '726 patent may increase the noise level. In addition, the base node of the upper BJTs has to cycle through a large voltage swing in each cycle. Thus, when combined with the inevitable slew-rate limitations, it creates timing uncertainties. When the current that is used to charge the capacitance of that base node, which is set either by the upper PMOS or the lowest NMOS, is noisy, the phase noise degrades proportionally with respect to the noise level. The time to produce a voltage swing from an idle state to a cross-over point is also inversely proportional to the slew rate.
Another prior solution is disclosed in U.S. Pat. No. 5,631,580 (hereafter “the '580 patent”), entitled “BiCMOS ECL-to-CMOS Level Converter,” which has low-level signal swings until a rail-to-rail CMOS signal is created. However, the performance of the circuit disclosed therein still can not produce desired phase noise performance because the noise level yielded from the PMOSFET (having its gate connected to its drain) is still too high. This limits the available voltage swing, which subsequently degrades the signal to noise ratio. Even without this limitation, the base of the complementary output BJTs is driven all the way to their emitters, to the rail, when that BJT is off. This represents a signal swing of many hundreds of milliVolts (as much as 900 mV at −55° C.) from an idle state to a cross-over point. Although the '580 patent represents an improvement over the '726 patent, the noise is still too large and leads to degradation of phase noise because of the current noise and the slew rate limiting that occurs.
In U.S. Pat. No. 5,900,746 (hereafter “the '746 patent), entitled “Ultra Low Jitter Differential to Fullswing BiCMOS Comparator with equal rise/fall time and Complementary Outputs,” the inputs to the first CMOS gate are held at a static level near the threshold of crossover using a dummy inverter and the dynamic drive signal is a low-level signal from BJT differential pairs. Thus, the first nodes with a significant change in voltage to be slewed are the first rail-to-rail CMOS signals. However, the signals that drive the gates of the first MOSFETs are inherently current driven signals. Because of that, the slew rate of the edges are set by the quiescent current levels in the driving circuitry as well as the capacitance looking into the gates of the MOSFETs in the inverters. Those capacitances include gate to source capacitance, gate to bulk capacitance, and gate to drain capacitance. Thus, the latter term is effectively multiplied several times in accordance with the well-known Miller effect, which drives up the effective capacitance because of the opposite plate being connected to the drain. That is, the inverter output has a large and opposing voltage swing.
Driving the gates with such current sources may result in acceptable speeds, but noise performance often suffers because of the noise present in the current sources. On-chip current sources are usually created with the well-known band-gap type reference, providing a current that can be largely independent of supply voltage and temperature, or proportional to the absolute temperature. Although the circuitry disclosed in the '746 patent provides some desirable features in some cases, the dynamic range of a current source based on a band-gap reference, which is defined as the quiescent current level divided by the current noise level, is often a limitation in achieving the most demanding phase noise performance.
Another prior art circuit is disclosed in U.S. Pat. No. 6,008,667 (hereafter “the '667 patent”), entitled “Emitter-Coupled Logic to CMOS Logic Converter and method of operation.” In the circuit described in the '667 patent, the gates of the N-MOS and P-MOS transistors that create the first rail-to-rail CMOS signal are independently driven with a small voltage swing centered around the threshold Vgs of each respective MOSFET. This improves the speed for a given level of quiescent current drain, as measured in terms of both propagation delay and the slew rate of the gate drive signals. One of the noise sources of the inverter MOSFETs is the input referred voltage noise. Thus, the faster the slew rate in volts per second, the less voltage noise is converted into phase noise.
The circuit disclosed in the '667 patent, however, also suffers from two shortcomings already identified in other prior art circuits. The first is that the gate driven signals are still limited by the quiescent currents in the stage. The gate-to-drain connected MOSFETs at the inverter gate nodes attempt to lower the impedance, making the driver more like a voltage source. Thus, as passive devices, such MOSFETs do not increase the current available to drive the inverter gate terminals. The second limitation is that the gate-to-drain connection of those MOSFETs inherently limits the signal to noise ratio, as previously discussed.
The circuit disclosed in U.S. Pat. No. 7,345,528 (hereafter “the '528 patent”) drives the gates of the first inverter with a common node held at the appropriate mid-supply level (which can be seen also in the circuit disclosed in the '746 patent). In the '528 patent, the driver circuitry includes complementary differential BJT pairs to improve the signal to noise ratio for a given quiescent current level. The circuit as disclosed in the '528 patent, drives the inverter inputs with signals that are high impedance but, by varying both the current sink and the current source driving those nodes, the signal to noise level is improved by a factor of two. In addition, the '528 patent discloses a bipolar clamp circuit that limits the voltage swing at the inverter inputs, which may improve the phase noise performance as mentioned above.
FIG. 1 (PRIOR ART) shows another prior art circuit for driving the gate terminals of a pair of P-MOSFETs (150 and 155) from a conventional ECL logic gate including transistors 115 and 120. When fabricated using an integrated circuit process with reasonable control of the Vbe level of an NPN transistor and the Vgs threshold level of a PMOS transistor (150 or 155), this circuit can be made, based on skills well known in the art, to function properly for all operating temperatures with appropriate setting of the voltage swing. The inputs to the circuit are ECL logic signals and the outputs are usable for creating CMOS logic signals, as will be explained below.
As a digital logic circuit, FIG. 1 has only two static states, with the transitions between the two states occurring in (hopefully) quick dynamic events. When the input state changes, one of the two PMOS devices (e.g., 150) is turned off by the NPN emitter follower (e.g., 130) connected to its gate. This usually happens quite quickly and with low noise, because the NPN emitter follower (e.g., 130) acts as a voltage source, increasing the current needed to pull the node up in tandem with the signal on its base due to the current gain of the device. However, in the other half of the circuit, the other PMOS device (e.g., 155) will be turned on, but this will not happen as quickly because the emitter follower (e.g., 135) will cut-off (drop to zero emitter current) unless the quiescent bias current (145) of the emitter follower is set to a very high level. The capacitance looking into the gate of the MOSFET, as noted above, includes gate to source capacitance, gate to bulk capacitance, and gate to drain capacitance, where the latter term is effectively multiplied several times by the well-known Miller effect.
Given such multiplied capacitance as well as the fast slew-rate that an ECL logic gate can create, a substantial quiescent current is needed to keep the NPN emitter follower (e.g., 135) actively biased during the falling edge of the signal. This substantial bias level has all the usual undesirable outcomes, including increased power consumption from the supply rails, increased heat generation on the chip. It also causes an increase of the noise in the circuit because the base current noise of the NPN works into the pull-up resistor, R4 (110) which is substantially larger than the reciprocal of the transconductance (gm). That is, the voltage noise level at the base terminal is not set by the usual voltage noise terms, but rather by the current noise times the value of the pull-up resistor.
With a typical quiescent current level, the noise can be kept quite reasonable on the edge that turns off the PMOS device. However, the time base noise is dominated by the noise of the current source on the edge that turns on the PMOS device.
An alternative to the Prior Art of FIG. 1 is to change transistors Q5 and Q6 to N-channel MOSFETs. These source followers will act the same as the emitter followers described above as they are both functionally a type of voltage follower. The use of NMOS could introduce problems associated with the Vgs(ON) variability, particularly due to the bulk effect whereby the Vgs(ON) changes as a function on bulk voltage. But the dominant noise term using emitter followers, base current shot noise, is eliminated since the gate current noise of a MOSFET is orders of magnitude less. So with NMOS based voltage followers, it may be possible to increase the currents from I2 & I3 without as much noise penalty for doing so as with an NPN based voltage follower.
FIG. 2 (PRIOR ART) shows one prior art solution 200 to create conventional CMOS logic signals for the circuit as shown in FIG. 1. In circuit 200, anti-parallel CMOS inverters 230 and 240 are placed on the drains of the PMOS transistors 210 and 220, forming a latch which is set and reset between two logic states in association with circuit 100 in FIG. 1. This is an appropriate implementation in a CMOS process that includes NPN but not PNP BJTs. However, circuit 200 will result in a slight skew of the duty cycle at both outputs. One of the PMOS devices 210 and 220 generally turns off faster than the speed that its counterpart PMOS turns on, as discussed above with reference to FIG. 1. This is desirable from the standpoint of contention in circuit 200 shown in FIG. 2. However, the skew occurs at the outputs due to the fact that the rising edge of either output is actively pulled by the PMOS devices and the falling edge will lag by approximately one inverter delay. In this manner, the duty cycle of both outputs shown in FIG. 2 will be skewed so that within a cycle, the high state is slightly longer than the low state, relative to the ECL inputs.
FIG. 3 (PRIOR ART) shows a fully differential and complementary implementation 300 of circuit 100 in FIG. 1. A complementary circuit is well known to those skilled in the art, and is one in which a second circuit is overlaid in a “mirror-image” fashion. The polarity of all the BJTs are flipped from NPN to PNP or vice versa, while the polarity of all MOSFETs are flipped from PMOS to NMOS or vice versa. In general, the signals and bias voltages will be of similar magnitude and opposite polarity mirrored about the half-way point between the two supply rails. Circuit 300 can only be implemented in a process that includes NPN and PNP BJTs, as well as CMOS devices. Such processes are needed for complementary circuits, and are often used in high speed, low-noise circuits. In FIG. 3, input transistors 310 and 315 are connected to two PNP voltage followers 360 and 375, which further drive the gate terminals of two N-MOSFET transistors 385 and 390. In addition, the complementary side includes two input transistors 320 and 325 that are connected to two NPN voltage followers 345 and 365, that drive the gate terminals of two P-MOSFET transistors 377 and 380.
The four voltage followers (345, 365, 360, and 375) drive four MOSFETs (377, 380, 385, and 390) that create the first CMOS rail-to-rail logic signals at the output. There is no need for a latch circuit similar to circuit 200 shown in FIG. 2. As circuit 300 is merely a complementary version of FIG. 1, it has the same properties and shortcomings with respect to how the MOSFET gates are driven. That is, the gate drive to the off state is quick, with the emitter followers acting as voltage sources. The gate drive to the on state will be current limited and therefore slower and noisier, unless the quiescent current sources are increased substantially. In that case, the noise level rises anyway due to base current noise flowing through the resistors which creates noise on the base nodes.
Although an alternative to FIG. 3 may be to change the four BJT voltage follower devices (345, 365, 360, and 375) to their respective polarity MOSFETs, it may introduce considerable variability to the DC levels. This is because the Vgs(ON) changes with bulk voltage and additional noise such as of the 1/f variety.
Therefore, an improve solution is needed to the circuit shown in FIG. 3 without an increase in the bias current levels of the voltage followers, irrespective of the particular class of transistors used to implement the voltage followers.
USPTO Backgrounds
USPTO Backgrounds