As for a method to carry out interlayer connection in a printed wiring board, vias are more often used than through-holes due to a demand that requires compact-type electronic devices. Furthermore, due to demand for fine pitch in a printed wiring board, a transfer method to form a conductive circuit, in which a conductive circuit formed on a transfer base is transferred to an insulative resin layer, is being put into practice. For example, U.S. Pat. No. 7,297,562 B1 and Japanese Laid-Open Patent Publication 2005-39233 disclose a method for manufacturing a printed wiring board using a transfer process. The entire contents of these patent publications are incorporated herein by reference. According to these patent Publications, conductive circuits are embedded in an insulative material through a transfer process, and via openings are formed at predetermined spots. Then, filled vias are formed in the via openings by bottom-up plating.
However, while plating, the speed of depositing a plating metal may easily become erratic. When performing bottom-up plating, the conductive circuit at the bottom portions of via openings is connected to electricity so that the metal will be deposited from their bottoms. If the deposited metal comes in contact with a conductive circuit adjacent to the top portion of a via opening, electric current starts flowing to that conductive circuit. Namely, when multiple filled vias are formed simultaneously, if the speed in depositing the plating metal is faster in some via openings and the deposited metal comes in contact with the conductive circuit adjacent to the top portions of such via openings, electric current starts flowing into that conductive circuit. Accordingly, electric current flows mainly in the conductive circuit adjacent to the top portions of the via openings, and the current flowing in the conductive circuit at the bottom portions of the via openings decreases. That is because the surface size of the conductive circuit at the bottom portions of the via openings is smaller than the surface size of the conductive circuit adjacent to the top portions of the via openings. As a result, in the via openings where the deposition speed of the plating metal is slow, the plated metal is suppressed from further deposition, thus making it difficult for the deposited plating metal to reach the conductive circuit adjacent to the top portions of such via openings. Therefore, at the via openings where deposition of the plating metal is slow, conduction may become incomplete, causing faulty connections.
USPTO Backgrounds
USPTO Backgrounds