1. Field of the Invention
The present invention relates to apparatus for protecting integrated circuits (ICs) against electrostatic discharge (ESD) damage. In particular, this invention relates to a simple multiple-component guarding device capable of diverting dangerous charge accumulations away from input nodes, output nodes, and power rails of ICs. More particularly, this invention relates to a simple multiple-bipolar transistor guarding device used to divert such charge accumulations. Most specifically, this invention relates to a single bipolar device which when coupled to the input pin and to the output pin provides ESD protection to those pins and to the high-potential and low-potential power rails of an IC.
2. Description of the Prior Art
The risks to ICs posed by accumulations of electrostatic charge are well known. Although they generally constitute but a small quantity of charge, such accumulations can result in quite high voltages and thus high risk to circuit elements through which they may be discharged.
ESD protection strategies have generally involved providing a voltage-sensitive switch through which the accumulated charge can be diverted and then drained harmlessly. Such a switch must be implemented so that legitimate data signals are not also diverted. Typical data signals range from a logic-high of five volts to a logic-low of 0 volts. The transient voltage spikes against which protection is sought are of varying magnitudes. Any ESD protection device must ensure that all voltages exceeding the circuit's damage-threshold level--which may be just a few volts above the logic-high level--are diverted, while voltages at the logic-high level and below are left unaffected. The other requirement, of course, is that the ESD protection work extremely fast; it will do no good to divert a 20-volt pulse after that pulse has permanently damaged the circuit. It will also hamper normal circuit performance if the protection device requires so long to discharge the spike that the circuit input is "pegged" at a fixed voltage for a prolonged time, even if that voltage does not cause permanent damage.
There are two generally-accepted models for analyzing the protection effectiveness of fabricated electrostatic protection devices. One, the Human Body Model (HBM), is designed to determine the ability of an ESD protection device to divert a charge delivered by an external source away from a circuit's input or output pin before that charge damages the circuit. The other, the Charge Device Model (CDM), is designed to determine the ability of an ESD protection device to divert a charge stored by a circuit before that charge is discharged from the circuit's input or output pin to external devices. The HBM has been the most widely-utilized analysis and accounts for the most common type of electrostatic discharge observed. However, discharges tracking the CDM also occur and may be unguarded against because of the emphasis on the HBM. The discharges observed under the HBM vary widely, and a "mid-range" ESD protection device will divert HBM discharges in the range of 2000 V-4000 V that normally last for tens of nanoseconds. CDM discharges are generally of lower potential, with the same type of ESD protection device expected to divert discharges in the range of about 1000 V-1500 V. The differences are in 1) the duration of the discharge, with the CDM type lasting for only tenths of nanoseconds, and 2) the current applied, with the CDM discharge providing more current than an HBM discharge Both differences are due to the difference in the RC time constant associated with each type of discharge. The CDM is related to charge-storing entities with lower capacitances than those identified by the HBM. Additionally, the CDM involves much lower resistances than observed for HBM elements. It has recently been observed that the CDM discharges are in fact more damaging to ICs--and gate oxides of transistors in particular--and thus more likely to cause IC failure. This is often the case when circuit boards are coupled together, as in the case of computer fabrication, for example. Therefore, in order to provide both HBM and CDM protection, an ESD protection device must be able to divert significant voltage spikes and relatively high currents quickly in order to protect internal circuitry and circuitry coupled to that internal circuitry.
FIG. 1 shows a typical prior-art ESD protection device. It protects the input pin against positive voltage spikes exceeding the voltage of the high-potential power rail by a certain threshold amount. The protection mechanism involves punch-through conduction through the bipolar transistor. Thus, the threshold protection voltage for the system of FIG. 1 is V.sub.df +VCEO, where V.sub.df is the drop across the forward-biased diode and VCEO is the collector-emitter voltage at which the bipolar transistor undergoes punch-through. Voltages in excess of V.sub.cc +(V.sub.df +VCEO) appearing on the input pin are diverted to the high-potential power rail. [Generally, when a circuit is powered down, the high-potential power rail is grounded; consequently during power-down, the input pin is protected against positive voltage spikes in excess of (V.sub.df +VCEO).] The role of the diode is obviously that of a blocker. The bipolar transistor must be designed so as to have a punch-through voltage that will ensure protection against spikes exceeding the circuit's damage threshold while at the same time not allowing logic-high data signals to be diverted.
Obviously, the circuit of FIG. 1 does not provide protection against negative voltage spikes applied to the input pin. Nevertheless, a solution is available, as shown in FIG. 2, wherein a second diode--typically a Schottky-clamped diode--forward-biased from ground to the input pin protects against negative voltage spikes, possibly in addition to other functions it serves in the circuit. Of course, similar protection must be provided for output pins and where CDM discharges are of concern. Such protection must also be provided to protect against spikes occurring between the high- and low-potential power rails. It can be seen, then, that the prior devices were directed to specific transients such that a multiple of devices was needed to protect a single pin and/or a single power rail. As a result, the space on a chip that must be reserved for ESD protection is considerable and the delay associated with the multiple components is increased. This is an undesirable occurrence when the goal is smaller and faster integrated circuitry.
The various prior-art approaches to the problem share a couple of significant drawbacks. One is that different circuits are required to protect the I/O pins against the two different polarities with which electrostatic accumulations may appear. As previously noted, another drawback is in the space that such prior devices take up on a chip. One continuing goal in IC fabrication is a reduction in size and an increase in speed. The prior devices such as those illustrated in FIGS. 1 and 2 take up a significant amount of space, particularly since multiple components are required for the various ESD situations. In addition, the number of ESD protection devices required at the size needed to divert typical HBM and CDM discharges slows the operation of the entire circuit. Still another drawback of the prior devices described is their relative unreliability in performing the desired function. In some instances discharge diversion is achieved while in similar but not exactly identical conditions circuit overload occurred. It is believed that the protection, when it occurred, was a function of the fabrication of the device, and variations in parasitic capacitance caused thereby, which incidentally provided protection, rather than the design and coupling of the device. Therefore, what is needed is a simple circuit which meets all ESD protection needs with the same form, a circuit which will protect input and output pins and each of the power rails, regardless of the polarity of the voltage to be diverted. What is further needed is such a circuit which does not rely upon the particular structure of the circuit being protected. What is also needed is an ESD protection device which takes up less space on a chip than prior devices did when used in the same application of complete ESD protection. A related goal is to provide for faster diversion of electrostatic discharges, corresponding with the faster speed of current devices.
USPTO Backgrounds
USPTO Backgrounds