Reducing operation supply voltage (Vmin) is an effective strategy to improve energy efficiency for integrated circuits. However, write operations for static random access memory (SRAM) storage cells may become unreliable at lower operation supply voltages due to variations in circuit characteristics, such as threshold voltages, resulting from fabrication technology and/or the age of the integrated circuit device.
To write a conventional 6-transitor storage cell, the data to be written is encoded as differential values on bitlines (BL and BLB). For example, data=0 is encoded as BL-0 and BLB=1 and data=1 is encoded as BL=1 and BLB=0, where 1 (TRUE) is a high voltage level and 0 (FALSE) is a low voltage level. When a word line is enabled, NMOS (N-type metal-oxide semiconductor) transistor pass gates that couple a pair of bitlines to the memory element within the storage cell are activated. The pass gates must overcome the strength of the cross-coupled inverters that form the memory element to change the contents of the storage cell to match the data encoded on the bitlines, thus completing the write operation. In particular, variation in the circuit characteristics can strengthen a PMOS (p-type metal-oxide semiconductor) pull-up transistor of the memory element and weaken an NMOS pass gate, preventing transfer of a 0 encoded on one of the bitlines to the memory element. As a result, the SRAM storage cell cannot be reliably written.
Thus, there is a need for addressing the issue of write reliability and/or other issues associated with the prior art.
USPTO Backgrounds
USPTO Backgrounds