1. Field of the Invention
The present invention relates to a synchronous semiconductor device, and more particularly, to a synchronous dynamic random access memory (DRAM) (hereinafter, ‘SCRAM’) whose bit organization can be changed.
2. Description of the Related Art
A SCRAM is a DRAM device for inputting or outputting at least one kind of data in synchronization with an external clock. The number of data bits that are input to or output from the SCRAM at once is called data input/output regulation or bit organization. For instance, the bit organization of a SCRAM in which 4-bit data is input or output in parallel is 4 and the bit organization of a SCRAM in which 8-bit data is input or output in parallel is 8. In general, the bit organization of a SCRAM is denoted as “×4”, “×8”, or “×16”, for example.
In general, the bit organization of an SCRAM is not determined during a design process but is determined after the SCRAM is designed and manufactured to operate with various bit organizations. That is, SDRAMs are designed to operate with various bit organizations and then their bit organizations are determined right before they are shipped.
In the case of an SCRAM that operates with various bit organizations, access time, however, varies according to its bit organization. Access time refers to time lost in outputting data from a reference edge of a clock and is indicated as tSAC in a single data rate (SDR) SCRAM and as tAC in a double data rate (DDR) SCRAM. In general, the access time is set to be within a predetermined range.
The reason why access time for a SCRAM depends on the bit organization of the SCRAM is that the larger the bit organization is, a greater number of output drivers is needed to drive the number of pins to which power is applied. For this reason, the smaller the bit organization is, the less the access time is, and the larger the bit organization is, the more the access time is. If the access time changes according to the bit organizations there is a high probability that the access time does not fall within the predetermined range.
FIG. 1 is a block diagram of a conventional SCRAM 100. The SCRAM 100 includes an internal clock generator 110 and a data output buffer 120. The internal clock generator 110 receives an external clock E_CLK and generates an internal clock I_CLK. In a single data rate (SDR) SCRAM, the internal clock generator 110 is just a buffer for converting the external clock E_CLK into an internal signal, whereas in a double data rate (DDR) SCRAM, the internal clock generator 110 is a delay-locked loop circuit or phase synchronization loop circuit for precisely controlling the phase of the internal clock I_CLK.
The data output buffer 120 is a circuit that outputs data read from a memory cell to the outside in response to the internal clock I_CLK, and includes an output driver (not shown) that drives an output node (or output pad) to a predetermined level in response to output data R_DATA.
Power consumed by the data output buffer 120 depends on the bit organization of the SCRAM 100. As previously mentioned, the larger the bit organization, the greater the number of operated output drivers (not shown). An increase in the bit organization of the SCRAM 100 results in an increase in access time TP1 in the data output buffer 120. Thus, time lost in outputting data depends on the bit organization.
In conclusion, time for accessing a conventional SCRAM depends on the bit organization, which causes access time for a particular bit organization to deviate from a predetermined range. Also, output data skew increases according to the bit organization.
USPTO Backgrounds
USPTO Backgrounds