The present disclosure relates to traffic scheduling and to the field of traffic management in telecommunication routers and switch systems, in particular when a high performance, flexible traffic scheduling is required.
One of the key building blocks of a network equipment modern router or switch system for packet switched networks is a hierarchical traffic management unit. A traffic management unit is used in the packet-processing data path to implement Service Level Agreements (SLAs) and associated Quality of Service (QoS) and bandwidth provisioning requirements. A Service Level Agreement is a negotiated agreement between two parties, e.g. a customer and a service provider. The SLA may specify the levels of availability, serviceability, performance, operation, or other attributes of the service, such as billing. Quality of Service is the ability to provide different priorities to different applications, users, or data flows, or to guarantee a certain level of performance to a data flow. For example, a required bit rate, delay, jitter, packet dropping probability and/or bit error rate may be guaranteed. Bandwidth provisioning is the process of measuring and controlling the communications, i.e. traffic and packets, on a network link, to avoid filling the link to capacity or overfilling the link, which would result in network congestion and poor performance of the network.
Traffic management is usually implemented as a standalone IC device or as a hardware block within a Network Processor IC or a Communications processor IC. The traffic management device is constructed from flow queue manager (FQM) that stores a plurality of flow queues and the traffic scheduler that controls the sequence of transmission of packets out of FQM. Prior art high performance traffic schedulers are using hardware configurable engines. The functionality of such hardware traffic scheduler is defined via configuration, it is limited by the finite set of all possible configuration combinations, and therefore hardware traffic schedulers are strongly deficient in flexibility. Frequently, the hardware traffic scheduler fails to address relentlessly emerging network operators' requirements when these exceed the set of all possible configurations. To overcome the shortcoming of the hardware traffic scheduler, a more flexible scheduler is required. Flexibility is achieved by software programmability. A software-based traffic scheduler can be programmed for various scheduling algorithms, unique features and can be further safe updated to support new scheduling algorithms. Unfortunately, prior art software-based traffic schedulers, while addressing the generic flexibility demand, so far are failing to achieve the high performance of hardware traffic schedulers.
In order to describe the disclosure in detail, the following terms, abbreviations and notations will be used:                ALU: Arithmetic Logic co-processor Unit        XALU, X-ALU: Extended Arithmetic Logic co-processor Unit;        MCU: Memory Cluster Unit;        SPE: Scheduling Processor Element;        FQM: Flow Queue Manager;        Mem: Memory;        Node-Cop, NCOP: Node Co-Processor;        Acc-Cop, ACOP: Accounting Co-Processor;        VLIW: Very Long Instruction Word;        RISC: Reduced Instruction Set;        CISC: Complex Instruction Set;        ISA: Instruction Set Architecture;        S/W: Software;        H/W: Hardware;        TMU: Traffic Management Unit;        NPU: Network Processor Unit;        SLA: Service Level Agreement;        QoS: Quality of Service;        IC: Integrated Circuit;        WFQ: weighted fair queuing;        WRR: weighted round robin;        MDRR: modified deficit round robin;        SRAM: static random access memory;        DRAM: dynamic random access memory;        GQ: group level;        SQ: subscriber level;        FQ: flow queues level;        DMA: direct memory access;        RX: Receive;        TX: Transmit;        VLAN: Virtual Local Area Network.        
USPTO Backgrounds
USPTO Backgrounds