An information processing system using a conventional mirror mode (duplexing) will now be described. The mirror mode is an information processing technique of allowing a system to operate, even when a trouble occurs on one system, with use of another line by performing processing while synchronizing the one line (synchronized unit) with the another line.
Now, a description will be made of a system configuration of a conventional information processing system using a mirror mode. FIG. 25 is a block diagram illustrating a configuration example of a conventional information processing system. The information processing system is constituted by two lines A and B which perform synchronous operation, and includes a control system 1, processing devices 2a0 and 2a1 on the line A, and processing devices 2b0 and 2b1 on the line B. The processing devices are, for example, CPUs. The processing devices 2a0, 2a1, 2b0, and 2b1 each has an error checker inside. The control system 1 includes an interface (A IF) 4a for the line A, an interface (B IF) 4b for the line B, error checkers 7a and 7b, a comparator 9, a selector generation unit 12, a selector 14, and a common unit 15. Of these components, the processing devices 2a0, 2a1, A IF 4a, and error checker 7a are on the line A while the processing devices 2b0, 2b1, B IF 4b, and error checker 7b are on the line B.
The control system 1 is connected to the processing devices 2a0 and 2a1 through a route 3a and the A IF 4a, and is also connected to the processing devices 2b0 and 2b1 through a route 3b and the B IF 4b. The lines A and B operate synchronously and each has three error checkers (wherein the line A includes the error checker 7a and the error checkers in the processing devices 2a0 and 2a1, and the line B includes the error checker 7b and the error checkers in the processing devices 2b0 and 2b1). The comparator 9 carries out a synchronization check between a signal 5a outputted from the line A and a signal 5b outputted from the line B.
Output of the common unit 15 is inputted to the processing devices 2a0 and 2a1 through the A IF 4a, and to the processing devices 2b0 and 2b1 through the B IF 4b. Accordingly, a UE (uncorrectable error) in the common unit 15 propagates to the lines A and B when the processing devices read from the common unit. The UE is therefore detected on both the lines A and B.
The selector generation unit 12 makes a determination based on a signal 10 outputted from the comparator 9, a signal 8a outputted from the error checker 7a, a signal 8b outputted from the error checker 7b, a signal 11a0 outputted from the error checker inside the processing device 2a0, a signal 11a1 outputted from the error checker inside the processing device 2a1, a signal 11b0 outputted from the error checker inside the processing device 2b0, and a signal 11b1 outputted from the error checker inside the processing device 2b1. In accordance with a signal 13 indicating a determination result from the selector generation unit 12, the selector 14 selects and outputs either the signal 5a or 5b to the common unit 15.
Described below is a case that an error checker detects a UE.
Next, operation of receiving an error signal by the selector generation unit 12 will be described. FIG. 26 is a table illustrating an operation example of receiving a UE signal by a conventional selector generation unit. This table represents content of the select signal 13 as outputted from the selector generation unit 12 in relation to content of line-A error signals (e.g., the signals 8a, 11a0, and 11a1), line-B error signals (e.g., the signals 8b, 11b0, and 11b1), and synchronization errors (comparison errors and the signal 10) inputted to the selector generation unit 12, for each case number.
The line-A error signals each indicates that a UE is detected by a line-A error checker, and the line-B error signals each indicates that a UE is detected by a line-B error checker. The synchronization error is an error of in synchronization between the lines A and B, and indicates that a comparison result from the comparator 9 indicates a disagreement (i.e., being out of synchronization). Content of the select signal 13 indicates one of signal 5a, signal 5b and an error stop (not selected and a system stop). If the content of the select signal 13 describes that “both of signal 5a and signal 5b are OK”, the selector generation unit 12 selects either the signal 5a or signal 5b in accordance with a predetermined determination method because the same operation is obtained regardless of whether the signal 5a or signal 5b is selected. The predetermined determination method is, for example, to select a preset line or a line selected in advance.
FIG. 27 is a flowchart illustrating an operation example when a conventional selector generation unit receives an error signal. The selector generation unit 12 firstly determines whether a notification about a UE has been received or not (S11).
If a notification about a UE has been received (S11, Yes), the selector generation unit 12 determines where the UE has been received from (S21). If the UE is an error from the line A (S21, line-A error), the selector generation unit 12 selects the signal 5b (S22), and this flow ends. Otherwise, if the UE is an error from the line B (S21, line-B error), the selector generation unit 12 selects the signal 5a (S23), and this flow ends. If the UE is an error which has been simultaneously notified of from both the lines A and B (S21, simultaneous), the selector generation unit 12 does not select any signal (S24, error stop), and this flow ends.
If any notification about an UE has not been received (S11, No), the selector generation unit 12 makes a determination on a synchronization check result of the comparator 9 (S61). If no synchronization error occurs (S61, no error), the selector generation unit 12 selects either the signal 5a or signal 5b in accordance with the determination method described previously (S62), and this flow ends. Otherwise, if a synchronization error occurs (S61, synchronization error), the selector generation unit 12 does not select any signal (S63, error stop), and this flow ends.
According to the operation of the selector generation unit 12, if a comparison error is detected or errors are detected on both lines (case number=2, or 5 to 11 as illustrated in FIG. 26), the information processing system stops.
Next, operation of each error checker (the error checkers 7a and 7b, and the error checkers inside the processing devices 2a0, 2a1, 2b0, and 2b1) will be described. FIG. 28 is a flowchart illustrating an operation example of a conventional error checker. The error checker firstly determines what type of error has occurred (S111). If no error has occurred (S111, No Error), the error checker does nothing, and this flow ends. If a UE has occurred (S111, UE), the error checker issues a notification about the UE to the selector generation unit 12 (S112), and this flow ends. If a CE has occurred (S111, CE), the error checker corrects the CE (S113), and this flow ends.
For example, if a UE is detected on the line B, the selector 14 selects the signal 5a in accordance with the operation of the selector generation unit 12 as described above, and separates the line B from which an error has been detected. In a similar manner, if a UE is detected on the line A, the selector 14 selects the signal 5b in accordance with the operation of the selector generation unit 12 as described above, and separates the line A from which an error has been detected. In this manner, the system is protected.
A further description will be made of a case that an error checker detects a CE (correctable error). If each of the lines is given a path for carrying out a CE processing in an interruptive manner, the line where a CE has been detected performs masking of an interruption processing.
Several of conventional techniques relevant to the present invention are fault-tolerant computer devices which shorten a pause of device operation, and a resynchronization method thereof.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-046599
However, there is a case that the mirror mode is weaker against errors than a single mode, in a system in which a UE from the common unit 15 propagates to the lines A and B and an error is recognized by the lines A and B, and which has the selector generation unit 12 performing operation as described above, like in the information processing system described previously.
USPTO Backgrounds
USPTO Backgrounds