1. Field of the Invention
The present invention relates in general to built-in self-repair (BISR) systems for integrated circuits employing embedded memories, and in particular to a BISR system employing an efficient spare row and column replacement analysis system.
2. Description of Related Art
Integrated circuit (IC) designers often incorporate one or more random access memories (RAMs) into application specific integrated circuits (ASICs) to avoid manufacturing and performance costs associated with interconnecting the ASICs to separate RAMs at the circuit board level. However a RAM embedded in an ASIC may include thousands or millions of memory cells, and if any one of those cells is defective when manufactured, the ASIC is unusable. Radiation can also damage RAM cells when an ASIC is in use.
One approach to decreasing the percentage of ASICS that are unusable due to defective memory cells has been to replace defective memory cells with spare cells that have been incorporated into the ASIC. The memory cells of a RAM are arrayed into rows and columns, and a memory address identifies a particular cell to be read or write accessed by identifying its row and column position within the cell array. An address decoder decodes a read or write address to send a row enable signal to all cells of the identified row and a column enable signal to all cells of the identified column. The particular memory cell receiving both the row and column enable signals is enabled to read or write data appearing on data lines linked to all cells of the array. ASICs usually provide spare cells in the form of one or more spare columns of memory cells. When a memory cell in any particular column is found to be defective, the memory is reconfigured to replace all cells of that column with a spare column.
There are various ways to reconfigure a memory to implement spare column replacement. Some systems reroute the defective column's column enable line to the spare column, for example by using a laser to alter routing paths within the ASIC. Other systems implement the column replacement by changing the way the address decoder decodes the address so that it sends a column enable signal to the spare column instead of the defective column whenever the defective column is addressed. This usually involves writing data into a register the address decoder consults when decoding addresses.
Spare column replacement systems are not very efficient in their use of spare memory cells because they replace an entire column of memory cells even when only one cell in the column is defective. In order to be able to replace at least N defective memory cells, an ASIC would have to incorporate at least N entire spare columns of cells. To improve cell replacement efficiency, some systems provide spare memory rows in addition to spare memory columns so that when a memory cell is found to be defective it can be replaced by replacing either its row or its column with a spare row or column. For example when a defective cell is the only defective cell of its row, but is one of two or more defective cells of its column, then it is more efficient to replace its column with a spare column than to replace its row with a spare row. Conversely, when a defective cell is the only defective cell of its column but is one of two or more defective cells of its row, it is preferable to replace its row.
When an ASIC memory includes only spare columns, then each column can be tested in turn and immediately replaced with a spare column when it is found to have a defective cell. On the other hand when an ASIC memory includes spare columns and spare rows, then we would like to test memory cells of all rows and columns before deciding how to best allocate the spare rows and columns. To do so a test and repair system must store data indicating the address of each cell found to be defective until the end of the test, and then analyze that data to determine how to best allocate the spare rows and columns. For example a test and repair system may store that data in the form of a bit map, wherein each bit indicates whether a corresponding memory cell is defective. Since such a bit map requires as many cells as the memory itself, it isn't practical to provide a circuit for storing and analyzing such a bit map on the ASIC itself. Therefore the portions of test and repair systems that store and analyze such bit map data are typically located outside the ASIC. The test results data for each memory cell is therefore transmitted off chip as it is generated so that there are no on-chip test result data storage requirements.
For many reasons it is desirable to provide an ASIC with a "built-in self-repair" (BISR) system that can test and repair a memory with little or no communication with devices external to the ASIC. For example radiation or other environmental factors can cause a memory cell in an ASIC to fail long after it has passed a test at the factory. When the ASIC includes a BISR system enabled, for example, on ASIC power up or in response to an externally generated enabling signal, the BISR system can automatically test for and replace damaged cells. Since the BISR system is wholly contained within the ASIC, it isn't necessary to remove the ASIC from its normal operating environment or to connect it to external test and repair equipment.
Self-contained BISR systems have not been able to take full advantage of the efficiencies provided by combined spare column and spare row replacement because it has not been practical for them to store test results for all cells so that they can be analyzed at the end of the test to determine the best way to allocate spare rows and columns. U.S. Pat. No. 5,764,878 issued Jun. 9, 1998 to Kablanian et al describes a BISR system that organizes memory columns into blocks of several columns each and tests and repairs each block in turn. If a block of columns has one or more defective cells, a built-in repair analysis (BIRA) subsystem of the BISR system decides whether to repair the block by replacing memory rows with spare rows or by replacing the entire block with a spare block. Since the BISR system only tests and repairs one memory block at a time, it doesn't have to store and analyze test results data for the entire memory array at once. However since the BIRA subsystem makes its row and column replacement selections without having fully mapped the defective cells of the memory, the BISR System will not always optimize its allocation of spare rows and column blocks. Since the described BIRA system tests first on a row-by-row basis and then on a column-by-column basis, the system may impact test flexibility insofar as blocks must be tested individually and will have an effect on test time.
U.S. Pat. No. 5,577,050 also describes a BISR system employing both spare row and spare column replacement. The BISR system first checks each column in turn to determine whether the column has a "global" fault (such as column line stuck or open faults) that can affect more than one cell of a column. However it does not individually test each cell of a column. When it finds such a global error in a column, the BISR system replaces the defective column with a spare column before moving on to test the next column. After it has tested and replaced defective columns, the BISR system then individually tests each memory cell on a row-by-row basis, replacing any row having a defective cell with a spare row. Since it tests and repairs on a column-by-column and row-by-row basis, the BISR system doesn't have to store a large amount of result data, but the system will not optimize spare row and column allocation for, example, when a column has two or more defective cells that are not due to a global column fault.
What is needed is a BIRA subsystem for a BISR system for substantially optimizing spare row and column replacement allocation based on system test results without having to concurrently store large amounts of test results data upon which to base its allocation decisions and which does not limit test flexibility or significantly increase test time.
USPTO Backgrounds
USPTO Backgrounds