The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for a split-layer design for double patterning lithography.
Double patterning lithography (DPL) is a natural extension to single patterning lithography that uses two separate patterning processes to form two coarser patterns which are combined to form a single finer pattern. DPL is currently the forerunner for technology nodes beyond the 22 nm node. The paradigm of double patterning could be further extended to triple patterning lithography, and even quadruple patterning lithography.
There are different DPL process technologies being developed, e.g., double exposure (DE), DP with intermediate etch (a.k.a. litho-etch-litho-etch—LELE), and self-aligned spacer processing. All of the DPL processes have more processing steps/cost and lower throughput than the single patterning lithography. These DPL processes also have different costs and requirements on material/process as well as design/patterning constraints. DE is the simplest in terms of the process with two exposures and one etch, but provides limited design shrink benefits. LELE and spacer technologies can generate finer pitches than DE, but they require more processing steps. For example, LELE needs two exposures, two masks, two etches; and spacer needs even more steps. LELE can generate flexible patterns, but it puts more burdens on overlay control. For the self-aligned spacer processing, the overlay can be better controlled. But since the spacers are formed on the perimeter of a sacrificial first pattern, only very regular patterns can be generated.
No matter what DPL processes are used, they all pose new challenges to nanometer circuit design and electronic design automation (EDA) tools. A major challenge is the overlay errors, including shifting, rotation, and magnification errors. These overlay errors will cause both back end of line (BEOL) (interconnect) as well as front end of line (FEOL) (transistor critical dimension) variations. Circuit analysis tools also have to take into consideration these DPL-induced variations.
DPL requires layout decomposition, which is post-design, that decomposes the original layout into two separate masks (or colors), subject to minimum spacing constraints on each mask. The decomposition first needs to make sure that the design is decomposable, i.e., the design can be decomposed without any coloring conflict. Meanwhile, the number of stitches (where a layout feature is split into two masks) shall be minimized during layout decomposition for printed image robustness. Intelligent layout decomposition can also play a proactive role in mitigating the overlay-induced variations.
USPTO Backgrounds
USPTO Backgrounds