1. Field of the Invention
The present invention relates to a method for isolating a semiconductor device, and in particular to an improved method for isolating a semiconductor device which is well applicable to a shallow trench isolation for filling an insulation layer into a shallow trench.
2. Description of the Background Art
FIGS. 1A through 1F are views illustrating a known semiconductor device isolation method. As shown in FIG. 1A, an oxide film, which is a first insulation film 2, is formed on a semiconductor substrate 1 to a thickness of 500.about.100 .ANG., and a nitride film, which is a second insulation film 3, is formed on the first insulation film 2 to a thickness of 2000 .ANG.. In addition, a photoresist film 4 is formed on the second insulation film 3.
As shown in FIG. 1B, the photoresist film 4 is patterned through a conventional exposing and developing processes for exposing the surface of the second insulation film 3, and then the first insulation film 2 and the second insulation film 3 are sequentially etched using the resultant structure as a mask.
As shown in FIG. 1C, the substrate 1 is etched using the first insulation film 2 and the second insulation film 3 as a mask for thereby forming a trench 5. A shallow third insulation film 6, which is an oxide film, is formed in the trench 5 based on the thermal oxidation process. Thereafter, a fourth insulation film 7 is formed on the second insulation film 3. As a result, the trench 5 is filled by the fourth insulation film 7.
Here, the fourth insulation film 7 is formed as an oxide film based on a high density plasma chemical vapor deposition method, and then a heat treatment is performed for forming a good quality device isolation film for thereby densifying the fourth insulation film 7.
As shown in FIG. 1D, the fourth insulation film 7 is etched by a chemical-mechanical polishing (CMP) method until the surface of the second insulation film 3 is exposed. At this time, the second insulation film 3 acts as an etching stop film.
As shown in FIG. 1E, the first insulation film 2 and the second insulation film 3 are removed from the substrate 1 for thereby completing a known semiconductor device isolation process. The second insulation film 3 is removed based on a wet etching method in which H.sub.3 PO.sub.4 solution is used.
The known semiconductor device isolation method has the following problems.
First, the polishing process for forming an oxide film for filling the trench and etching the oxide film is implemented by an expensive semiconductor apparatus. In addition, a large amount of slurry which is a polishing material used during the CMP process is used for thereby increasing the fabrication cost.
Second, the surface of the semiconductor substrate may be damaged due to the stress of a thick silicon nitride film during the high temperature heat treatment after the HDP CVD oxide film, which is the fourth insulation film, is deposited.
Third, when chemically and mechanically polishing the HDP CVD oxide film, which is the fourth insulation film, it is difficult to control the uniformity of the surface of the oxide film.
Fourth, when etching the fourth insulation film using the CMP process, the third and fourth insulation films at the corner portions of the trench are etched to a predetermined thickness lower than the surface of the semiconductor substrate (refer to a dotted line in FIG. 1E). Therefore, when depositing and etching the polysilicon for forming a gate electrode in the following process, which is not illustrated in FIG. 1, the polysilicon deposited at the corner portions of the trench may not be etched for thereby causing a short circuit.
USPTO Backgrounds
USPTO Backgrounds