LCD panels, especially small and middle LCD panels, S/M LCD panels, for mobile and multimedia applications, are being developed ambitiously. To meet the demands of high-end mobile devices including functions such as cellular phone, digital camera, music player, GPS, mobile TV and so on, the development of S/M LCD panels with higher resolution, higher image quality, low power consumption and cost competitiveness is inevitable.
Please refer to FIG. 1(a), Vcom modulation is widely applied in S/M LCD panels. The driving of Vcom modulation can reduce the output voltage range of a source driver so as to save the source driver cost. However, it still causes the gray level inconsistent and then leads to the flick and the low transmittance when the TFT of a pixel unit is turned off and common voltage changes. This problem is attributed to the charge distribution on the pixel unit, which is disturbed by the voltage change of Vcom. To avoid the gray level being inconsistent, a storage capacitor Cst is configured in the common structure. That is, the Cst of the pixel unit on common structure is comprised of a common line and a pixel electrode disposed on a array substrate, wherein the common line and the common electrode are connected to the same voltage source, so that both the voltages of the common line and the common electrode are modulated to balance the charge distribution in the pixel unit.
Please refer to FIG. 1(b), which illustrates the layout of the storage capacitor Cst on common structure. The pixel unit 1 includes data lines 11 & 12, gate lines 13 & 14, a TFT 15, a common line 16, and a pixel electrode 17. The pixel electrode 17 covers the common line 16 to form the Cst, as shown the cross-section view along the dotted line a to a′. The Vcom modulation requires the Cst on common structure to avoid the gray level inconsistency when the TFT turns off and common voltage changes.
However, if a pixel includes some significant parasitic capacitances, although it has the Cst on common structure, the gray level also appears to be inconsistent. On the other word, the storage capacitor Cst in the common structure doesn't solve this problem completely. In many high-end applications such as HAR design, In-Cell Touch panel and so on, the significant parasitic capacitance is indispensable.
Please refer to FIG. 2, which is a circuit diagram showing a pixel unit of an In-Cell Touch panel according to the prior art. Touch sensors or photo sensors (not shown) are regularly disposed in the cell of the In-Cell touch panel. Moreover, readout lines connected to the sensors transmit the touch signals to a readout circuit. The pixel unit 2 includes a TFT 20, a liquid crystal capacitor CLC, and a storage capacitor CST. The G(Gate) electrode of TFT 10 is electrically connected to the gate line Gaten, the D(Drain) electrode is electrically connected to the data line Datam, and the S(Source) electrode is electrically connected to one end of respective the liquid crystal capacitor CLC and the storage capacitor CST. The other ends of respective the liquid crystal capacitor CLC and the storage capacitor CST are connected to the common voltage source. Owing to the existence of the read-out line of an In-Cell touch panel for In-Cell touch signal, a parasitic capacitor Cread-out is formed in the pixel unit as FIG. 2 shows. For example, the parasitic capacitor Cread-out formed between the pixel electrode and the readout line leads to the inconsistent gray level when the TFT 20 is turned off and Vcom changes.
Either the In-Cell touch panel or the HAR designed panel meet significant parasitic capacitance causing gray level inconsistent. Please refer to FIG. 3, which is a schematic diagram showing the structure of a high aperture ratio (HAR) pixel unit according to the prior art. The HAR pixel unit 3 includes a pixel electrode 30, a first data line 31, a second data line 32, a first gate line 33, and a second gate line 24. The pixel electrode 30 is designed to partially cover the adjacent data lines 31 & 32 and gate lines 33 & 34 so that the black matrix (BM)(not shown) widths are shrunk, therefore the high aperture ratio is increased, as FIG. 3 shows. It is noted that the capacitance formed between the pixel electrode 20 and the data line 31 is Cd1, the capacitance formed between the pixel electrode 30 and the data line 32 is Cd2, the capacitance formed between the pixel electrode 30 and the gate line 33 is Cg1, and the capacitance formed between the pixel electrode 30 and the gate line 34 is Cg2. The cross-section view along the dotted line a to a′ is, for example, also shown in FIG. 3.
As FIG. 3 shows, the capacitance formed between the pixel electrode 30 and the gate line 33 due to the partial covering thereof is Cg1. The area generated from the pixel electrode 30 covering the gate line 33 leads to one of the aforementioned parasitic capacitance, which causes the inconsistent gray level when the TFT 35 (shown in FIG. 2) of the pixel unit 3 is turned off and Vcom changes.
Please refer to FIG. 3(a), which is an equivalent circuit diagram showing the structure of the HAR pixel unit according to FIG. 3. The HAR pixel unit 3 includes a TFT 30, a liquid crystal capacitor Clc, a storage capacitor Cst, a Gate line 1, a Gate line 2, a Data line 1, and a Data line 2. The G(gate) electrode of the TFT 30 is electrically connected to the Gate line 1, the D(drain) electrode of the TFT 30 is electrically connected to the Data line 1, and the S(source) electrode of the TFT 30 is electrically connected to one end of the liquid crystal capacitor Clc and one end of the storage capacitor Cst. The other end of the storage capacitor Cst is connected to the common line and that of the liquid crystal capacitor Clc is connected to the common electrode of a color filter (CF) (not shown). Both the common line and the common electrode are electrically connected to a common voltage source. Similarly, the capacitance formed between the pixel electrode and the Data line 1 is Cd1, the capacitance formed between the pixel electrode and the Data line 2 is Cd2, the capacitance formed between the pixel electrode and the Gate line 1 is Cg1, and the capacitance formed between the pixel electrode and the Gate line 2 is Cg2. One ends of Cd2, Cd1, Cg2, Cg1, Cst, and CLC are all electrically connected to a node P, and the node P electrode connected to the S(source) electrode of the TFT 30. That is, the total parasitic capacitance, Cb, of the HAR pixel unit 3 is comprised of Cd1, Cd2, Cg1, and Cg2. That is,Cb=Cg1+Cg2+Cd1+Cd2 
Please refer to FIG. 3(b), which is a waveform diagram showing the waveforms of the Vcom signal and the Gate signal of the HAR pixel unit in FIG. 3(a) according to the prior art. The waveform above shows the waveforms of the Vcom signal and the Gate signal in the even frame and the waveform below shows those in the odd frame. During the periods of gate signal impulses, the TFT becomes conductive between S(source) terminal and D(drain) terminal because of the inversion layer in the amorphous silicon layer induced by gate signal impulses, and the voltage at node P in FIG. 3(a) is charged and discharged to the data signal voltages in the even frame and in the odd frame respectively. After the gate signal impulses, the TFT becomes isolated between S(source) terminal and D(drain) terminal because the low gate voltage dispels the inversion layer in the amorphous silicon layer. Therefore, the pixel electrode becomes floating and the voltage at the node P is synchronously varied with the Vcom signal. Because the parasitic capacitances exist, the change quantity (ΔVp) of node P voltage shown in the black horizontal line is smaller than that (ΔVcom) of Vcom modulated voltage, which causes the voltage difference between the node P and common voltage source is not fixed, leading to the transmittance loss and gray level inconsistent. That is, with the existence of the total parasitic capacitance Cb, the peak ΔVp is always smaller than the ΔVcom. Since the total parasitic capacitance Cb shares the charge pumped by the Vcom voltage in the pixel electrode, the gray level of the HAR pixel unit 3 thus becomes inconsistent. The traditional method to solve this problem is to enlarge the size of the storage capacitor Cst. However, the aperture ratio will be decreased undesirably.
Similarly, FIG. 3(b) also showing the waveform of the In-Cell touch panel, and please refer to FIG. 2 which is an equivalent circuit diagram showing the pixel structure of the In-Cell touch panel. The In-Cell touch panel pixel 2 includes a TFT 20, a liquid crystal capacitor Clc, a storage capacitor Cst, a Gate line n, a Gate line n−1, a Data line n, and a readout line. The G(gate) electrode of the TFT 20 is electrically connected to the Gate line n, the D(drain) electrode of the TFT 20 is electrically connected to the Data line n, and the S((source) electrode of the TFT 20 is electrically connected to one end of liquid crystal capacitor Clc and that of the storage capacitor Cst. The other end of the storage capacitor Cst is connected to the common line and that of the crystal capacitor Clc is connected to the common electrode of a color filter (CF) (not shown). Both the common line and the common electrode are electrically connected to a common voltage source. In the In-Cell touch panel, there is a readout capacitor Cread-out, a parasitic capacitance caused by readout line, of which one end is electrically connected to the S(source) electrode of the TFT 20, and the other end of the Cread-out is connected to the readout line. The one end of Cread-out, Cst, and CLC are all electrically connected to a node P, and the node P electrode connected to the S(source) electrode of the TFT 20. Therefore, the main parasitic capacitance in the pixel structure of the In-Cell touch panel is Cread-out.
Please refer to FIG. 3(b), which is a waveform diagram showing the waveforms of the Vcom signal and the Gate signal of the In-Cell touch panel pixel unit in FIG. 2 according to the prior art. The waveform above shows the waveforms of the Vcom signal and the Gate signal in the even frame and the waveform below shows those in the odd frame. During the periods of gate signal impulses, the TFT 20 becomes conductive between S(source) terminal and D(drain) terminal because of the inversion layer in the amorphous silicon layer induced by gate signal impulses, and the node P in FIG. 2 is charged and discharged to the data signal voltages in the even frame and in the odd frame respectively.
After the gate signal impulses, the TFT 20 becomes isolated between S(source) terminal and D(drain) terminal because the low gate voltage dispels the inversion layer in the amorphous silicon layer. Therefore, the pixel electrode becomes floating and the voltage at the node P is synchronously varied With the Vcom signal. Because the parasitic capacitances exist, the change quantity (ΔVp) of node P voltage shown in the black horizontal line is smaller than that (ΔVcom) of Vcom modulated voltage, which causes the voltage difference between the node P and common voltage source is not fixed, leading to the transmittance loss and gray level inconsistent. That is, with the existence of the total parasitic capacitance Cread-out, the peak ΔVp is always smaller than the ΔVcom. Since the total parasitic capacitance Cread-out shares the charge pumped by the Vcom voltage in the pixel electrode, the gray level of the In-Cell touch panel thus becomes inconsistent.
USPTO Backgrounds
USPTO Backgrounds