In a large capacity semiconductor memory, a memory cell array is divided into several blocks and non-selected blocks are deactivated, to reduce power consumption. Namely, only a block to be read or written is activated, and thus the sense amplifiers of the other blocks do not consume electric power. This power saving effect is particularly conspicuous in a large capacity semiconductor memory.
FIG. 6 shows an essential part of a block of a conventional semiconductor memory. Reference symbols A1 to An denote sense amplifiers each comprising a pair of bipolar-emitter-follower-type differential transistors, and numeral 1 denotes a bias voltage generator circuit. Each of the sense amplifiers A1 to An amplifies the potential difference of a pair of bit lines (not shown), and supplies the amplified difference as, for example, memory cell data.
FIG. 7 shows a differential amplifier circuit in the conventional sense amplifier (for example, A1). The sense amplifier A1 comprises transistors T1 and T2. The collectors of the transistors T1 and T2 are connected to an H-level power source Vcc through resistors R1 and R2, respectively, and the emitters thereof are commonly connected to an L-level power source line Vss through a current control element T3 and a switching element T4. IN and IN denote input signals, and OUT and OUT denote output signals.
In FIG. 8, the bias voltage generator circuit 1 comprises, for example, resistors R3 and R4 connected in series between Vcc and Vss, and a bipolar transistor T3 and a MOS transistor T6 also connected in series. The voltage Vcc is divided by the resistors R3 and R4 to provide a base potential for the transistors R3 and R4 to provide a base potential for the transistor T5, and the emitter of the transistor T5 provides a reference voltage VB having a constant potential.
In FIG. 7, when the transistor T4 is ON, emitter currents IE1 and IE2 of a pair of the bipolar transistors T1 and T2 flow (as a constant current IO) through the transistors T3 and T4, and when a predetermined activating/deactivating signal CONT is externally set to a level L, the transistor T4 is turned OFF to stop the flow of the current IO and deactivate the differential amplifier A1.
Namely, to deactivate the sense amplifiers of the semiconductor memory block by block, the signal CONT is set to the level L and commonly supplied to each of the sense amplifiers A1 to An of FIG. 6.
According to this prior art, each of the sense amplifiers A1 to An must have the switching element T4, which is turned ON and OFF according to the signal CONT, and as a result, this prior art has the following problems:
(i) The transistor T4 causes a channel resistance that slightly increases a node potential (VN in FIG. 7) between transistors T3 and T4, and this increases the reference potential of the transistor T3 to thereby reduce the current IO and lower the operation speed of the differential pair of transistors of the sense amplifier.
(ii) To deal with the above problem (i), the area of the transistor T4 can be increased to thus reduce the channel resistance. In practice, the area is increased four times in each differential amplifier, and therefore, each transistor T4 needs four times as large an area as required by a normal transistor, and thus an integrated circuit involving n differential amplifiers may require an area increase of "4.times.n" transistors, which will hinder circuit integration.
USPTO Backgrounds
USPTO Backgrounds