The invention relates generally to transmission circuits and more particularly to a circuit for driving a power amplifier (PA).
One class of power amplifiers that is known to perform with high efficiency are those that operate in a saturation mode. Efficiency being defined as the ratio of power emitted, in the form of radio frequency signal, to the electrical power used by the amplifier in order to produce said radio frequency signal. In many communication systems using frequency modulation (e.g. FSK), amplifiers are operated at or near their most efficient point of operation since minimal amplitude variation in the output signal occurs. Unfortunately, as demand grows for increased transmitted data bandwidth within each transmission channel, amplitude modulation is introduced into transmitted signals. With both frequency and amplitude modulation, distortion impairing data transmission rates becomes a more important figure of merit in respect of power amplifier performance. First, varying the signal power causes efficiency variations with which a varying output power signal is amplified. Second, because there is amplitude modulation, any variation in the ratio between input amplitude and output amplitude of a P A results in distortion, known to create data transmission errors more likely. Furthermore, is can be appreciated that there are legislative requirements that govern how much signal power is allowed within adjacent transmission channels in a wireless communication system. Signal power in adjacent transmission channels can arise with increasing distortion applied to the original signal submitted for amplification.
It is desirable to produce an amplitude varying transmit signal in an efficient fashion thereby preserving power and, in the context of battery powered terminals, maximizing the time interval between terminal charging. Typically, most transmitter applications utilize linear amplifiers that are transmitting at a power level considerably reduced from the power level at which the amplifier saturates. This reduction is often called the back-off. For example, a PA might be designed and biased to supply 30 dBm of amplification at the point of gain compression (1 dB compression point) but is operated 6 dBm below that power level so that the power amplifier is a regime of operation where the gain is relatively invariant. Clearly, if the gain is invariant then distortion arising from amplitude modulation is minimized. While distortion performance is thereby improved, efficiency is compromised since the amplifier is still biased for operation at a much higher level of output power. Thus a need exists to amplify an amplitude-varying signal for transmission in a more efficient manner.
One known method of increasing the efficiency in such an amplifier is by increasing the control circuitry complexity to vary more amplifier parameters in order to maintain near optimal efficiency for any and all amplification requirements. The disadvantage of such a scheme is that if the control system for controlling the PA is too complicated then it might consume more power than it recovers through efficiency. Moreover, additional control circuitry will commensurately increase the size of circuit board or, in the context of monolithic integration, the semiconductor die area. It is also well appreciated by the semiconductor power amplifier designers that power amplifier control schemes can lead to problems with the stability of the amplifier. Often an amplifier using a control loop will oscillate at some frequencies. Generally speaking, control systems for controlling various operation parameters of the power amplifier will add cost and, as the complexity of the control circuit increases, the power savings diminish.
Another known approach utilizes a plurality of PAs driven in parallel wherein the phase of the input signal provided to each of the PAs is controlled. A power combiner is coupled to the output ports of each of the PAs to combine output signals therefrom using a vector sum. Under this scheme, amplitude modulation is provided by controlling the phase angle of the input. However, efficiency of such an amplifier is often impaired by losses in the combiner circuit and therefore output power is wasted even though in principle each PA is operated close to the saturated output power level.
In typical transmitter systems, transmitter signal generators generate a modulated signal at a known carrier frequency for transmission at a known power level using two separate circuits, a modulation circuit and a power amplifier circuit (PA). The modulation circuit is for generating of a modulated signal, or RF signal, and then the PA is used to amplify the modulated signal to the known power level. Typically it is the PA that consumes a majority of power for the signal generator and, as such, PA efficiency is of significant concern. The PA circuit is typically implemented using any of a number of different transistor manufacturing technologies, such as GaAs, Si bipolar, SiGe bipolar, LDMOS and CMOS FET. Though the CMOS FET technology enables implementation of reasonable nonlinear PA circuits, it has yet to demonstrate competitive efficiency when used for implementing of linear power amplifier circuits. The GaAs, SiGe and Si bipolar devices produce excellent linear PAs, but they are not always available as device options combined with a state-of-the-art CMOS process. Moreover, conventional CMOS technology remains one of the most cost effective semiconductor electronics technology platforms available today. It is available from a number of foundry suppliers, particularly to satisfy the market for digital CMOS circuits that' are extensively utilized in modem telecommunication and computing systems.
GaAs and other group III-V materials have yet to be integrated into a high density CMOS process so that a single chip solution incorporating both the signal processing elements, primarily digital in nature, and amplifying elements are not yet practical. Rather, one often finds systems implemented using a mix of semiconductor technology elements. Unfortunately, state of the art CMOS linear power amplifiers do not have high efficiency operation, primarily due to the CMOS transistor saturation voltage. This drawback, inherent to known architectural approaches for a linear amplifier, prevents linear CMOS PAs from being accepted in the market for many common RF applications because they result in significantly reduced battery life for portable devices.
On the other hand, a non-linear architecture using CMOS switch-class PAs, can operate with constant amplitude envelope signals quite efficiently for some applications. Unfortunately, CMOS transistors operating in a switched mode, do not have effective power control much less sufficient dynamic range in said power control for CDMA applications or other modulation scheme wherein amplitude control is an important part of the signal transmission scheme. One known way of achieving power control in the context of a switch class CMOS PA, is by reducing the drain to source terminal voltage (Vds) for the FET therein. This reduction in Vds can provide approximately 30 dB of power control. Unfortunately, it is known to those skilled-in-the-art that CDMA and WCDMA applications require in excess of 60 dB power control.
For efficient operation in transmitter circuits, polar transmitter circuits can be utilized, where the amplitude modulation is applied directly to the PA through collector/drain voltage control and or bias control. Primarily this approach relies on predictable amplitude and phase response through the PA over a wide range of output signal powers. Alternatively, this approach relies on amplitude and phase compensation circuits being used to compensate for imperfections. Unfortunately, it is well appreciated by those skilled-in-the-art that the known compensation circuits consume power and increase the cost of the transmitter. Furthermore, there is significant demand to integrate signal generator circuits into a single IC, which is difficult with the above architectures. For example, Polar transmitter circuits are generally not integrated within the PA because the amplifying transistors used within the PA are constructed in a different semiconductor or manufacturing platform than that which is used for the Polar transmitter circuit and associated compensation circuitry. Effectively, integration of both the signal conditioning circuitry, wherein the circuitry generates the modulation, and the power amplifier into one semiconductor technology platform compromises the overall circuit performance with the existing architectures described above. Such a compromise in performance is often not acceptable to the marketplace.
It is conceivable that a P A circuit could be integrated with the modulation circuit using a SiGe technology, but this has yet to be achieved in a market acceptable form and is considered difficult with CMOS devices. A need therefore exists to integrate the signal generator including the modulation circuit and the PA circuit in a single semiconductor die using a CMOS process. This allows for the benefit of advances in CMOS process technology and reduced costs due to high volume for CMOS wafers.
It is therefore an object of the invention to provide a relatively efficient and relatively linear CMOS power amplifier that can be integrated with a modulation circuit to form a complete integrated signal generator circuit.
USPTO Backgrounds
USPTO Backgrounds