1. Field of the Invention
The present invention relates to switched capacitor circuits, and more particularly, to a switched capacitor circuit having low phase noise used in a voltage controlled oscillator (VCO) for minimizing the clock feedthrough effect and thereby preventing a VCO frequency drift phenomenon during the calibration and the synthesizer phase locking periods.
2. Description of the Prior Art
A voltage controlled oscillator (VCO) is commonly used for frequency synthesis in wireless communication circuits. As indicated by Welland, et al. in U.S. Pat. No. 6,226,506, a wireless communication system typically requires frequency synthesis in both its receiving and transmitting path circuitries.
FIG. 1 shows a prior art VCO circuit. An LC type VCO used in a frequency synthesizer contains a resonator 10 with a basic resonant structure including an inductor 12 connected between a first oscillator node OSC_P and a second oscillator node OSC_N. Connected in parallel with the inductor 12 is a continuously variable capacitor 14 and a plurality of discretely variable capacitors 16. The continuously variable capacitor 14 is used for fine-tuning a desired capacitance while the plurality of discretely variable capacitors 16 is used for coarse tuning. The resistive loss of the parallel combination of the inductor 12 and the capacitors 14, 16 is compensated by a negative resistance generator 18 for sustaining the oscillation.
Each discretely variable capacitor in the plurality of discretely variable capacitors 16 is made up of a switched capacitor circuit 20 and each switched capacitor circuit is controlled by an independent control signal (SW_1 to SW_N). Based on the control signal SW_N, the switched capacitor circuit 20 selectively connects or disconnects a capacitor 24 to the resonator 10 of the VCO. Different on/off combinations of the switched capacitor circuits 20 result in a wider capacitance range of the LC type resonator 10 and hence providing a wider VCO oscillation frequency coverage.
FIG. 2 shows a switched capacitor circuit 20a according to the prior art. A capacitor 30 is connected between the first oscillator node OSC_P and a node A. A switch element 32 selectively connects node A to ground, and the switch element 32 is controlled by a control signal SW. When the switch element 32 is turned on, the capacitance associated with the capacitor 30 is added to the overall capacitance in the VCO resonator 10. When the switch element 32 is turned off, the capacitance looking into the first oscillator node OSC_P is the serially combined capacitor 30 and the off state capacitance associated with the switch element 32.
FIG. 3 shows a differential type switched capacitor circuit 20b according to the prior art. The differential type switched capacitor circuit has a much greater common-mode noise rejection ratio and is thus widely used in high-speed integrated circuit environments. In the differential switched capacitor circuit 20b, a positive side capacitor 40 is connected between the first oscillator node OSC_P and a node A. A positive side switch element 42 selectively connects node A to ground. A negative side capacitor 44 is connected between the second oscillator node OSC_N and a node B. A negative side switch element 46 selectively connects node B to ground. The two switch elements 42, 46 are controlled by the same control signal SW. When the switch elements 42, 46 are turned on, the capacitance associated with the serially combined positive and negative side capacitors 40, 44 is added to the overall capacitance in the VCO resonator 10. When the switch elements 42, 46 are turned off, the differential input capacitance is the serial combination of the positive and negative side capacitors 40, 44 and the parasitic capacitances of the switch elements 42 and 46. The overall input capacitance when both switch elements 42, 46 are turned off is much lower than that when both switch elements 42, 46 are turned on.
FIG. 4 shows a second differential type switched capacitor circuit 20c according to the prior art. The second differential switched capacitor circuit 20c includes the same components as shown in the first differential switched capacitor circuit 20b except an additional center switch element 48 is used to lower the overall turn-on switch resistance connected between the nodes A and B. All three switch elements 42, 46, 48 are controlled by the same control signal SW. When the switch elements 42, 46, 48 are turned on, the capacitance associated with the serially combined positive and negative side capacitors 40, 44 is added to the overall capacitance in the VCO resonator 10. When the switch elements 42, 46, 48 are turned off, the differential input capacitance is the serially combined positive and negative side capacitors 40, 44 and the parasitic capacitances of the switch elements 42, 46 and 48. The overall input capacitance when all switch elements 42, 46, 48 are turned off is much lower than that when all switch elements 42, 46, 48 are turned on.
Regardless of whether the single ended implementation shown in FIG. 2 or one of the differential implementations shown in FIG. 3 and FIG. 4 is used, when the switched capacitor circuit 20a, 20b, 20c is turned off, a momentary voltage step change occurs at node A (and, in the case of the differential implementations, also at node B). The momentary voltage step causes an undesired change in the overall capacitance, and ultimately, an undesired change in the VCO frequency. Because NMOS switches are used in the examples shown in FIG. 2, FIG. 3, and FIG. 4, the momentary voltage step change is a voltage drop when the switch elements 32, 42, 46, 48 are turned off. In other p-type transistor based implementations, the momentary voltage step could also be a voltage spike.
Using the single ended case shown in FIG. 2 as an example, when the switch element 32 is turned off, charge carriers are injected into the junction capacitance connected between the source and drain terminals of the switch element 32. The injection produces an undesired voltage step change across the capacitive impedance and appears as a voltage drop at node A. This effect is known as the clock feedthrough effect and appears as a feedthrough of the control signal SW from the gate terminal of the switch element 32 to the source and drain terminals of the switch element 32. When the switch element 32 is turned on, node A is connected to ground so the feedthrough of the control signal SW is of no consequence. However, when the switch element 32 is turned off, the feedthrough of the control signal SW causes a voltage step, in the form a voltage drop in the implementation shown in FIG. 2, to appear at node A. Because of the dropped voltage at node A, the diode formed by the N+ diffusion of the switch element 32 and the P type substrate in the off state will be slightly forward biased. The voltage level at node A will spike low and then recover to ground potential as the slightly forward biased junction diode formed by the switch element 32 in the off state allows subthreshold and leakage currents to flow. The voltage drop and recovery at node A changes the loaded capacitance of the VCO resonator 10 and causes an undesired momentarily drift in the VCO frequency.
Similarly, when the differential switched capacitor circuit 20c shown in FIG. 4 switches off, it suffers from the same clock feedthrough effect problem at node A and at node B. The positive side node A has an undesired voltage step change caused by the clock feedthrough effect of both the positive side switch element 42 and the center switch element 48. Similarly, the negative side node B has an undesired voltage step change caused by the clock feedthrough effect of both the negative side switch element 46 and the center switch element 48. The voltage step change and recovery at node A and node B changes the loaded capacitance of the VCO resonator 10 and causes an undesired momentary drift in the VCO frequency.
USPTO Backgrounds
USPTO Backgrounds