1. Field of the Invention
The present invention relates to power regulators or converters, and more particularly to a power controller implemented with dual-edge modulation using dual ramp signals for fast response.
2. Description of the Related Art
The load current of a modern central processing unit (CPU) is highly dynamic and changes very quickly from low to high and from high to low. A CPU current transient may occur within 1 microsecond (μs), for example, which is less than the typical switching period of conventional voltage regulators. It is desired to provide a DC-DC power regulator with a control loop that has sufficient response time to fast load transitions whenever they occur.
In the conventional pulse-width modulation (PWM) scheme, the compensation (COMP) output of the error amplifier is typically compared to a fixed ramp signal by a PWM comparator, which generates a PWM signal used to control switching of a DC-DC power regulator. To provide switching noise immunity, a reset-set (R-S) flip-flop is often coupled to the output of the comparator to ensure that there is only one pulse for each switching cycle. A leading-edge modulation scheme is good for the load-adding transient event but not always responsive to a load-releasing transient, while a trailing-edge modulation scheme is good for the load-releasing transient event but not always responsive to a load-adding transient event. Each of these conventional schemes, therefore, insert clock signal delays under certain load varying situations. The conventional dual-edge modulation scheme also exhibits turn-on or turn-off delays since the ramp is fixed and since the leading-edge of the PWM pulse occurs only in the first half cycle while the trailing-edge only occurs in the second half cycle.
USPTO Backgrounds
USPTO Backgrounds