1. Field of the Invention
This invention relates generally to masking techniques for semiconductor fabrication, and more particularly to masking techniques including pitch multiplication.
2. Description of the Related Art
As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being reduced in size. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are also constantly being decreased to facilitate this size reduction.
The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. DRAM memory cells typically include two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. By decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices. Other examples of integrated circuit memories include MRAM (including magneto resistive elements), programmable fuse memories, programmable conductor memories (including metal-doped chalcogenide glass elements), SRAM, SDRAM, EEPROM and other volatile and non-volatile memory schemes.
Photolithography is commonly used to pattern features, such as conductive lines. The concept of pitch can be used to describe the sizes of these features. Pitch is defined as the distance between an identical point in two neighboring features. These features are typically defined by spaces between adjacent features. Spaces are typically filled by a material, such as an insulator. As a result, for regular patterns (e.g., in arrays) pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as optics and light or radiation wavelength, photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Consequently, the minimum pitch of a photolithographic technique is an impediment to further feature size reduction.
“Pitch multiplication” or “pitch doubling” is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. A pitch multiplication method is illustrated in FIGS. 1A-1F and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, a pattern of lines 10 is photolithographically formed in a photoresist layer, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30. As shown in FIG. 1B, the pattern is then transferred using an etch (preferably an anisotropic etch) to the layer 20, thereby forming placeholders, or mandrels, 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of spacer material is subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40. The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in FIG. 1F. Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased.
While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. Pitch can thus be used in two converse senses: the distance between identical elements in a regular pattern and the number of features in a fixed linear distance. The conventional terminology is retained herein.
Because the layer 50 of spacer material typically has a single thickness 90 (see FIGS. 1D and 1E) and because the sizes of the features formed by the spacers 60 usually correspond to that thickness 90, pitch doubling typically produces features of only one width. Circuits, however, generally employ features of different sizes. For example, random access memory circuits typically contain arrays of memory cells located in one part of the circuits and logic circuits located in the so-called “periphery.” In the arrays, the memory cells are typically connected by conductive lines and, in the periphery, the conductive lines typically contact landing pads for connecting arrays to logic. Peripheral features such as landing pads, however, should be larger than the conductive lines to facilitate contact with subsequently produced patterns (e.g., contacts from higher levels). In addition, periphery electrical devices, including peripheral transistors, can be larger and/or less dense than the electrical devices in the array. Moreover, even if peripheral features can be formed with the same pitch as features in the array, because mask patterns formed by pitch multiplication may be limited to those that are formed along the sidewalls of patterned photoresist, the flexibility, e.g., geometric flexibility, desirable to define some features is more difficult to achieve with pitch multiplication.
The reduction in feature sizes through pitch doubling and the concomitant increase in the complexity of device features may be met with an increase in the number of processing steps in semiconductor fabrication, which may in turn effect an increase in the processing time. Thus, the reduction of features sizes may increase the costs associated with semiconductor fabrication. Accordingly, there is a need for methods of forming features of different sizes, especially where some features are formed below the minimum pitch of a photolithographic technique, while minimizing the number of processing steps and/or processing time, in addition to the costs associated with semiconductor fabrication.
USPTO Backgrounds
USPTO Backgrounds