The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
BOX buried oxide
DT deep trench
DT capacitor deep trench capacitor
DRAM dynamic random access memory
eDRAM embedded dynamic random access memory
eSRAM embedded static random access memory
FET field effect transistor
Epi epitaxial growth
FiN fin-type
FinFET fin-type FET
IC integrated circuit
MOSFET metal-oxide-semiconductor FET
RF radio frequency
RIE reactive ion etching
SOI semiconductor on insulator
SRAM static random access memory
TTO trench top oxide
TTN trench top nitride
PWL passing word line
WL word line
HM hard mask
DTMO deep trench mask open
DT RIE deep trench reactive ion etching
It is a common practice to integrate memory and logic functions on a common semiconductor substrate. In such a configuration, when the memory function is performed by a dynamic random access memory (DRAM) cell, the circuitry is referred to as embedded DRAM (eDRAM).
The use of undoped channel devices such as fin-field effect transistors (FinFETs) for memory (both static random access memory (SRAM) and DRAM) has been proposed for this reason. However, the integration of FinFETs with planar logic is difficult due to vertical topography, especially since DRAM processes generally rely on bulk silicon wafer substrates. Various problems in extrapolating planar DRAM technology to FinFETs lie in the fact that there is no unprocessed side to the body of the transistor where the capacitor can be strapped to. Also, the thin body of the Fin allows for very little overlap area for intimate electrical contact.
Dual-gate non-planar FETs are FETs in which a channel region is formed in the center of a thin semiconductor fin. The source and drain regions are formed in the opposing ends of the fin on either side of the channel region. Gates are formed on each side of the thin semiconductor fin, and in some cases, on the top or bottom of the fin as well, in an area corresponding to the channel region. FinFETs specifically are dual-gate non-planar FETs in which the fin is so thin as to be fully depleted. The effective fin width is determined by the fin height (e.g., short wide fins can cause partial depletion of a channel). For a FinFET, a fin thickness of approximately one-fourth the length of the gate (or less) can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. FinFETs are discussed at length in U.S. Pat. No. 6,413,802 to Hu et al., which is incorporated herein by reference Deep trenches, typically having a depth exceeding one micron in contrast to shallow trenches having a depth less than one micron, are employed in the semiconductor industry to provide a variety of useful devices including a deep trench capacitor. The deep trenches may be utilized in a stand-alone semiconductor circuit such as a dynamic random access memory (DRAM) circuit to provide deep trench capacitors, or may be utilized as an embedded circuit component of a semiconductor chip that also includes other semiconductor circuits such as a processor core or other logic circuits. Particularly, embedded capacitors employing a deep trench are employed to enable an embedded memory device, e.g., an embedded dynamic random access memory (eDRAM) cell, a passive component of a radio frequency (RF) circuit, and decoupling capacitors that provide a stable voltage supply in a semiconductor circuit.
Semiconductor-on-insulator (SOI) substrates are employed in the semiconductor industry for performance benefits due to reduced capacitive coupling between semiconductor devices and the bulk portion of the substrate provided by a buried insulator layer. High performance logic chips are frequently manufactured on an SOI substrate to provide enhanced performance over devices having comparable dimensions and manufactured on a bulk substrate.
USPTO Backgrounds
USPTO Backgrounds