FIG. 1 shows an internal scan chain test structure for testing combinational logic matrices included in an integrated circuit on a semiconductor chip. In the scan chain test structure, multiplexed flip-flops MF1 102, MF2 106, MF3 108, MF4 110 and MF5 104 may receive test input data values in sequence while clocked by a scan clock signal. For example, when a first scan clock pulse is received, input terminal SI of multiplexed flip-flop MF1 102 may receive a first test input data value. When a second scan clock pulse is received, input terminal SI of second multiplexed flip-flop MF2 106 may receive the first test input data value from output terminal SO of multiplexed flip-flop MF1 102, and input terminal SI of multiplexed flip-flop MF1 102 may receive a second test input data value.
Accordingly, when a fifth scan clock pulse is received, multiplexed flip-flop MF5 104 may receive the first test input data value from output terminal SO of multiplexed flip-flop MF4 110. Meanwhile, input terminal SI of multiplexed flip-flop MF4 110 may receive the second test input data value from output SO of multiplexed flip-flop MF3 108. Input terminal SI of multiplexed flip-flop MF3 108 may receive the third test input data value from output SO of multiplexed flip-flop MF2 106. Input terminal SI of multiplexed flip-flop MF2 106 may receive the fourth test input data value from output SO of multiplexed flip-flop MF1 102. Input terminal SI of multiplexed flip-flop MF1 102 may receive the fifth test input data value.
When a pulse from the system clock is received, combinational logic 112 may receive test input data from multiplexed flip flops not shown in FIG. 1. Further, combinational logic 114 may receive the fifth test input data value from output terminal Q of multiplexed flip-flop MF1 102 and the fourth test input data value from output terminal Q of multiplexed flip-flop MF2 106, and combinational logic 116 may receive the third test input data value from output terminal Q of multiplexed flip-flop MF3 108, the second test input data value from output terminal Q of multiplexed flip-flop MF4 110, and the first test input data value from output terminal Q of multiplexed flip-flop MF5 104 so that combinational logic matrices 112, 114, 116 may be tested.
As a result of passing the test input data to the respective combinational logic matrices, test output data generated by combinational logic 112 may be output to input terminals D of multiplexed flip-flop MF1 102 and multiplexed flip-flop MF2 106, and test output data generated by combinational logic 114 may be output to input terminals D of multiplexed flips flops MF3 108, MF4 110 and MF5 104.
Therefore, when the next scan clock is activated, output terminal SO of multiplexed flip-flop MF5 104 may output a first test result; output terminal SO of multiplexed flip-flop MF4 110 may output a second test result to input terminal SI of multiplexed flip-flop MF5 104; output terminal SO of multiplexed flip-flop MF3 108 may output a third test result to input terminal SI of multiplexed flip-flop MF4 110; output terminal SO of multiplexed flip-flop MF2 106 may output a fourth test result to input terminal SI of multiplexed flip-flop MF3 108; and output terminal SO of multiplexed flip-flop MF1 102 may output a fifth test result to input terminal SI of multiplexed flip-flop MF2 106. Accordingly, in response to the fifth scan clock, output terminal SO of multiplexed flip-flop MF5 104 may output the fifth test result.
Thus, the combinational logic matrices included on an integrated circuit semiconductor chip may be tested with an internal scan chain. The above steps may be used to determine whether the combinational logic modules in the integrated circuit function normally prior to packaging the circuit for operational use.
Although the circuit described above with respect to FIG. 1 may be used to support internal scan testing of a combinational logic circuit, an internal scan chain testing based on the insertion a multiplexed flip-flop along each data line in the combinational logic circuit requires additional chip space, thereby reducing the space available for implementing functional circuits. Further, due to the complexity of a multiplexed flip-flop based approach, the chance of introducing faults within the scan chain circuitry itself is greatly increased.
USPTO Backgrounds
USPTO Backgrounds