1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device of precharge/discharge type for driving word lines by use of a voltage raising circuit to read out data and used for a memory device which is required to be operated at a high speed with a low voltage.
2. Description of the Related Art
Conventionally, a non-volatile semiconductor memory device of precharge/discharge type such as an EPROM for reading out data by a raised word line voltage is known. In such a non-volatile semiconductor memory device, as shown in FIGS. 6A to 6E, the voltage raising (pump-up) operation of a voltage raising (charge pump) circuit shown in FIG. 3 is effected only in a precharge period (in which PR is set at an "L" level) so as to reduce the number of voltage raising operations and reduce unnecessary current consumption in the voltage raising circuit.
Further, since a drop or lowering in the raised potential caused by a through current in the level shifter at the time of address change can be efficiently compensated by pump-up operation in the later stage, a low-voltage operation in which the power supply voltage of approx. 2 V or less is used is realized.
However, if the power supply voltage is further lowered, the charging speed for voltage raising capacitors C1, C2 is abruptly lowered, and the effective charging time of the voltage raising capacitors C1, C2 is reduced by the dull portion of a voltage raising clock, and therefore, the current supplying ability of the voltage raising circuit is extremely lowered. This becomes significant in the high-speed operation, a drop or lowering in the raised potential by an address change is large and the restoring operation in the later stage is delayed. That is, since the data readout operation is started before a raised voltage level which permits the high-speed readout operation is obtained, it is difficult to effect the high-speed readout operation with a power supply voltage of 2 V or less.
The readout speed in the precharge/discharge type using a flip-flop sense amplifier of FIG. 2 depends on the current driving ability of a group of transistor (transistors serially connected to the bit line, that is, column selectors, memory cells and the like) for discharging the input (F/F-IN) of the precharged flip-flop sense amplifier, that is, the threshold voltages and gate voltages of the transistors. More specifically, in order to make it possible to effect the high-speed readout operation with a voltage of 2 V or less, the level change in the input (F/F-IN) voltage of the flip-flop sense amplifier of FIG. 2 is made sharp so as to permit the threshold voltage of the flip-flop sense amplifier to be rapidly exceeded. In order to rapidly lower the F/F-In level from VDD to GND, it is necessary to enhance the current driving ability of a memory cell having the highest threshold voltage among a group of transistors serially connected to the bit line, and the raised voltage level may be set as high as possible to meet the above requirement. Thus, since an output of the flip-flop sense amplifier can be obtained at an earlier time by .DELTA.s shown in FIGS. 9B, 9C, a still higher speed operation can be effected.
However, there is a limitation to the degree by which the raised voltage level is raised by operating the voltage raising circuit of FIG. 3 as indicated by FIGS. 6A to 6E and a sufficiently high voltage raising ability cannot be attained under the circumstance in which the high-speed readout operation with a low voltage is required.
Further, since the dull portion of the voltage raising clock largely depends on the threshold voltage of MOS transistors constructing a clock creating circuit, there occurs a problem that the current supplying ability of the voltage raising circuit is influenced by a fluctuation in the process condition and it is difficult to stably attain the low-voltage operation ensuring margin.
Further, in a level shifter which consumes charges charged by the voltage raising operation, a problem occurs at the time of low-voltage operation or when variations in the threshold values of transistors constructing the same are large. For example, in the level shifter shown in FIG. 4, assuming that the threshold voltage of PTR1 is low and the threshold voltage of NTR1 is high, it is necessary to turn 0N NTR1 and turn OFF PTR1 when the potential level of the word line is changed from "H" to "L".
However, since the threshold voltage of NTR1 is high, it is difficult to turn ON NTR1 so that the GND level will be difficult to be transmitted to the word line, and as a result, PTR2 which permits the potential level of the word line to act as a feedback voltage becomes difficult to be turned ON, and therefore, PTR1 whose threshold voltage is originally low becomes more difficult to be turned OFF. For this reason, as shown in FIGS. 10A, 10B, since .DELTA.t becomes longer with a reduction in the operation voltage and a through current is permitted to flow during this period, a voltage output to the word line at the readout time is further lowered.
USPTO Backgrounds
USPTO Backgrounds