1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor, and particularly to a method of manufacturing a thin film transistor having a low concentration impurity region represented by an LDD region.
2. Description of the Related Art
There is known a technique in which a thin film semiconductor formed on a glass substrate or a quartz substrate is used to make a thin film transistor. Such a thin film transistor is used in, for example, an active matrix type liquid crystal display device or an active matrix type EL display device.
As a technical problem involved in such a thin film transistor, there is given that an OFF-state current value is large. The OFF-state current is a current flowing from or to an output side when the thin film transistor is in an OFF-state operation.
For example, in the active matrix type liquid crystal display device, a pixel electrode is required to have a characteristic of keeping electric charges for a predetermined time. Thus, a value of a current flowing through an element in an OFF-state operation, that is, a value of an OFF-state current is required to be made as small as possible.
As a technique for lowering an OFF-state current value of a thin film transistor, there is known a technique disclosed in Japanese Examined Patent Publication No. Hei 3-38755. Further, as structures capable of obtaining an effect similar to the above technique, there are known techniques disclosed in Japanese Patent Unexamined Publication Nos. Hei 4-360580 and Hei 5-166837.
The techniques disclosed in the latter two publications are methods in which an offset gate region is formed in a self-alignment manner by using an anodic oxidation film formed around a gate electrode. This method is capable of forming the offset gate region with high precision without complicating manufacturing steps so much.
However, in the techniques disclosed in Japanese Patent Unexamined Publication Nos. Hei 4-360580 and Hei 5-166837, an LDD (lightly doped drain) region, which is one of the optimum structures to obtain a low OFF-state current characteristic, can not be formed in a self-alignment manner.
USPTO Backgrounds
USPTO Backgrounds