When initializing a computer system bus, it is typically necessary to allocate memory address resources to devices present on the bus. For instance, the Peripheral Component Interconnect (“PCI”) bus standard defines two types of memory address resources that must be allocated to each bus device upon initialization: the PCI input/output (“I/O”) address space and the PCI memory address space. The PCI I/O address space may be utilized, for instance, to map the internal registers of the bus device into the address space of the host computer. The PCI memory address space is typically utilized to map memory resources utilized by a PCI device. For instance, PCI video cards typically utilize relatively large amounts of the PCI memory address space for storing video information. In the PCI bus standard each device also has a configuration memory address space utilized for configuring the device.
Allocating memory address resources to a bus with only root bus devices in an efficient manner is a relatively straightforward task. Each bus device makes requests for PCI I/O and PCI memory address resources that are powers of two. The requested values are also alignment requirements for the bus device's address decoder. Since all of the resource requests are powers of two, the resource requests are naturally aligned and can therefore be allocated without the need to pad the resource requests with unused memory addresses to align the resource requests.
When one or more bridge devices are present on a bus (PCI-to-PCI bridges, for instance), however, the task of allocating memory address resources to the devices on the bus in an efficient manner becomes much more complex. This is primarily because bridges typically have only one set of registers for storing the address range to be decoded, and therefore memory address resource requests for all of the bus devices on the secondary interface of a bridge must be grouped and allocated as a single continuous memory region. The memory address resource requirements for a bridge may, therefore, not be a power of two. As a result, it can be extremely difficult to efficiently allocate memory address resources when one or more bridges are present on a bus. Previous mechanisms for allocating memory address resources typically insert “padding” in the form of unused memory addresses in order to properly align the resource requests. The inefficient insertion of padding by previous solutions, however, often results in a significant loss of already scarce memory address resources.
It is with respect to these and other considerations that the disclosure presented herein has been made.
USPTO Backgrounds
USPTO Backgrounds