The invention relates to a method for generating a clock signal by means of a phase locked loop, a divided clock signal generated from the clock signal being compared with a reference clock, and a frequency and a phase angle of the clock signal to be generated being set as a function of said comparison.
The invention also relates to an arrangement for generating a clock signal, composed of a phase locked loop comprising a digitally controlled oscillator for generating the clock signal, a frequency divider, a phase frequency detector, which has an input for a reference clock, and a digital filter.
Phase locked loops (PLLs) are widely used arrangements for generating clock signals in integrated circuits. To this end, these loops can be used as frequency multipliers, a high-frequency clock signal with a defined integral or rational multiple of the reference frequency being generated on the basis of a reference clock signal with a typically low frequency. Use is made, to this end, of a phase frequency detector (PFD) which compares the signal edges of the reference clock with the signal edges of the divided clock of the oscillator.
In a so-called locked-in state, the time difference of the signal edges at the PFD input is zero. In this case, the period length of the clock signal TDCO to be generated corresponds to the period length of a reference clock signal TREF divided by a divider factor N, owing to the inverse proportionality between frequency and period and to the frequency division of the oscillator signal upstream of the PFD input, it being the case that TDCO=TREF/N.
After the activation of the phase locked loop circuit, this state is produced by the regulation loop. The time required for this is termed the settling time. Frequency and phase of the output signal are not defined during this settling time. Consequently, the generated clock signal cannot be used for the functional operation of a module to be supplied with this clock. It is therefore necessary to strive to shorten said settling time. After the settling of the phase locked loop, the phase error at the PFD is zero and the oscillator settles at its target frequency.
The PLL is locked.
Separate procedures are known from the prior art for determining frequency and phase for phase locked loops. For example, counters can be used for frequency determination which determine the target frequency in combination with a search algorithm. Such a binary search is known, for example, from H. Eisenreich, C. Mayr, S. Henker, M. Wickert, and R. Schüffny, A novel ADPLL design using successive approximation frequency control, Microelectron. J., vol. 40, pp. 1613-1622, November 2009.
The publication C.-T. Wu, W.-C. Shen, W. Wang, and A.-Y. Wu, A two-cycle lockin time ADPLL design based on a frequency estimation algorithm, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 57, no. 6, pp. 430-434, June 2010 presents a further method for this in the case of which the control characteristic of the digitally controlled oscillator is measured and the target frequency for the settling is determined. In this case, the phase angle upon starting of the oscillator is achieved by synchronizing the start signal with the reference clock.
After a so-called lockin according to a prescribed desired frequency with the aid of a frequency detector, the phase angle of the clock signal is adjusted following this step. If no additional phase synchronization is performed, this happens through the closed regulation loop of the phase locked loop. Owing to the loop filter, this requires a significant time, which is extended by the settling time of the PLL.
The phase synchronization proposed in C.-T. Wu, W.-C. Shen, W. Wang, and A.-Y. Wu, A two-cycle lockin time ADPLL design based on a frequency estimation algorithm, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 57, no. 6, pp. 430-434, June 2010 requires a special complicated oscillator architecture. Moreover, an additional phase error can result between divided oscillator clock and reference clock owing to asynchronous frequency dividers and cannot be compensated by using this technique.
A further disadvantage of this prior art resides in the fact that it is necessary to use separate circuit blocks for frequency and phase detection, and this increases the outlay on hardware, and thus also the need for chip surface.
USPTO Backgrounds
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