This invention relates generally to memory systems and more particularly to error detection and correction (EDAC) used in memory systems.
As is known in the art, in many applications a memory board is arranged as shown in FIG. 1. Thus, such memory board includes a plurality of memory banks 10.sub.1 -10.sub.n. Each one of the memory banks 10.sub.1 -10.sub.n has a plurality of random access memories (RAMs), here for example, dynamic RAMs (DRAMs) 12.sub.0 -12.sub.m. Each bit of a data word on a corresponding one of lines D.sub.0 -D.sub.m is coupled to the data bit terminal, D, of a corresponding one of the DRAMs 12.sub.1 -12.sub.n in each one of the memory banks 10.sub.1 -10.sub.n. Thus, for example, data bit D.sub.0 of the data word is coupled to the data bit terminal, D, of the DRAMs 12.sub.0 in each of the memory banks 10.sub.1 -10.sub.n. Each data word includes, in addition to data, a plurality of bits for error detection and correction. For example, a Solomon-Reed code. Thus, for example, if the data portion of the data word includes 64 bits (i.e., 8 bytes), an additional byte (i.e.,8 bits) is included in the data word for error correction and detection. Thus, in this example m=71 and there are 72 DRAMs 12.sub.0 -12.sub.71 in each one of the memory banks 10.sub.1 -10.sub.n.
Each DRAM is addressable by an r bit address, A.sub.0 -A.sub.(r-1). Consider, for example the case where r=12. Thus, a 12 bit row address and a 12 bit column address are fed sequentially to the address terminals, A, of the DRAMs. More particularly, when the 12 bit row address is fed to the DRAM, a control signal is also fed to a column address select line (CAS) of the DRAM. Likewise, when the 12 bit row address is fed to the DRAM, a control signal is fed to the row address select line (RAS) for the DRAM. The read/write mode of the DRAMs is selected by a control signal on write line (WR). Thus, here each DRAM has 16 megabits of addressable locations and, therefore, each memory bank is able to store 16 megs of 9 byte digital words; 8 bytes of data and a byte for error detection and correction.
It is noted that the address signals are fed to the memory board by a logic network, not shown. In order to provide adequate power to address large numbers of DRAMs, drivers 14 are included. Typically, each driver 14 is adapted to drive about 18-36 DRAMS. Thus, assuming here that each driver 14 is used to drive 36 DRAMs, there are 2 drivers 14 for each one of the memory banks 10.sub.1 -10.sub.n.
Finally, as mentioned above, the EDAC may be performed on the data by checking the data read from the memory using a Solomon-Reed code, for example. However, a failure in one of the drivers 14 results in the 36 bits of data being written to an incorrect memory location. While parity checking of the address may be used to detect the presence of an error in the address, an EDAC will not be able to readily correct 36 bits of data which have become stored in the incorrect address location.
USPTO Backgrounds
USPTO Backgrounds