When information is transferred across a bi-directional bus, there is a required delay in the transfer of information. This latency requirement can decrease the efficiency of a computing system. Specifically, there is a required delay of one full clock cycle between when data is transferred in a first direction across the bi-directional bus and then transferred in a second direction across the bi-directional bus.
In a conventional memory access system, as illustrated in FIG. 1, information is transferred between a memory controller 100 and a memory device 102, such as a dynamic random access memory (“DRAM”). The memory controller 100 contains a memory 104 and a first register, register A, 106. Moreover, the memory controller 100 contains a clock 108, which provides a timing signal to a second register, register B, 110 disposed within the memory 102 and the first register 106, along connection 112.
Further within the memory device 102, the second register 110 is operably coupled to a storage array 114. The first register 106 and the second register 110 are coupled to each other across a bi-directional bus 112 for the transfer of information to and from the memory controller 100 and the memory device 102. The bi-directional bus 116 of FIG. 1 requires a latency period of at least one full clock cycle between transferring information from the first register 106 to the second register 110 and then from the second register 110 to the first register 106, and vice versa.
FIG. 2 provides further illustration of the memory 102 of FIG. 1. The memory device 102 receives a command input via bus 120 from a memory controller (not shown) similar to the memory controller 100 of FIG. 1, wherein the command is referred to as command A (CMD A). CMD A is provided to register R 122, also referred to as a first register for the discussion relating to FIG. 2. The first register 122 is coupled to the storage array 114 via bus 126, wherein a command previously stored in the first register 122 is provided to the storage array 114, referred to as command Ab (CMD Ab).
The memory device 102 further contains a second register 128 and a third register 130. The second register 128 and third register 130 represent the second register 110 of FIG. 1 coupled to the storage array 114 via a bi-directional bus Db 118. Also, the second register 128 and the third register 130 are coupled to the memory controller (not shown) across the bi-directional bus 116, referred to as bi-directional bus DQ.
FIG. 3 illustrates a table 140 representing the timing of the delay associated with a typical bi-directional bus. As recognized by one skilled in the art, table FIG. 3 can further be represented as a timing diagram showing timing pulses as generated by the clock (not shown in FIG. 2). In the table, for each clock cycle, as represented across the first row, each column entry represents the location of a write command (W), a read command (Rd), a packet of write information (W#), and a packet of read information (R#), if present.
FIG. 3 illustrates the timing of multiple read and write operations of the memory device of FIG. 2. At a first clock cycle, a first write command (W) is provided to the first register 122 as CMD A across the bus 120. Within the same clock cycle, a first write information (W1), such as a packet of data, is provided to the second register 128 across the bi-directional bus DQ 116.
At a second clock cycle, a second write command (W) is provided to the first register 122 via bus 120 as CMD A, and the first write command is provided from the first register 122 to the storage array 114 along bus 126 as CMD Ab. As the first write command, CMD Ab, is provided to the storage array 114, the first write information (W1) is transferred from the second register 128, across the bi-directional bus Db 118 to the storage array 114. Furthermore, in the second clock cycle, a second write information (W2) is provided from the memory controller (not shown) to the second register 128, across the bi-directional bus DQ 116.
In a third clock cycle, the storage array 114 writes the first write information (W1), a third write command (W) is provided to the first register 120 along bus 120 as CMD Ab, and a third write information (W3) is provided to the second register 128 along the bi-directional bus DQ 116. Within the memory 102 in the third clock cycle, the second write command is provided from the first register 122 to the storage array 114 along bus 126 as CMD Ab and the second write information (W2) is provided to the storage array 114 across the bi-directional bus Db 118.
In a fourth clock cycle, the storage array 114 writes the second write information. The third write command is provided from the first register 122 to the storage array 114 along bus 126 as CMD Ab and the third write information (W3) is transferred to the storage array 114 across the bi-directional bus Db 118. Also, in the fourth clock cycle, no CMD A is provided along bus 120 and no write information is provided along the bi-directional bus DQ 116.
In the fifth clock cycle, a first read command (Rd) is provided to the first register 122 across bus 120 as CMD A and the storage array writes the third write information (W3) therein. As no command was provided to the first register 122 in the fourth clock cycle and no write information was provided along the first bi-directional bus DQ 116, in the fifth clock cycle there is no CMD Ab transferred to the storage array across bus 126 and no information is transferred along the bi-directional bus Db 118. Moreover, as the command A in the fifth clock cycle is a read command, wherein the read information is provided by the storage array 114, no information (read or write information) is provided along either bi-directional bus, DQ 116 or Db 118.
In a sixth clock cycle, a second read command (Rd) is provided across bus 120 to the first register 122 as CMD A and the first read command is provided to the storage array across bus 128 as CMD Ab. The storage array does not execute a read operation or a write operation during this clock cycle and the bi-directional buses 116 and 118 are inactive.
In a seventh clock cycle a third read command (Rd) is provided to the first register 122 via bus 120 as CMD A. The second read command is provided to the storage array along bus 126 as CMD Ab and the first read command is executed by the storage array 114. Once again during this clock cycle, the bi-directional buses 116 and 118 are inactive.
In an eighth clock cycle, a new CMD A is not provided from the memory controller, but the third read command is provided to the storage array along bus 126 as CMD Ab. The storage array 114 executes the second read command and the first read information (Rd1) is provided to the third register 130 along the bi-directional bus, Db 118. Moreover, during this clock cycle, the bi-directional bus DQ is inactive.
In the ninth clock cycle, a new CMD A is not provided along bus 120 and due to the lack of a CMD A in the previous clock cycle, there is no CMD Ab to be provided to the storage array 114 across bus 126. The storage array 114 executes the third read command, the second read information (Rd2) is provided to the third register 130 along the bi-directional bus Db 118 and the first read information (Rd1) is provided to the memory controller (not shown) along the bi-directional bus DQ 116.
In the tenth clock cycle, a new CMD A is not provided along bus 120 and due to the lack of a CMD A in the previous clock cycle, there is no CMD Ab to be provided to the storage array 114 across bus 126, and the storage array 114 is inactive. The third read information (Rd3) is provided to the third register 130 along the bi-directional bus Db 118 and the second read information (Rd2) is provided to the memory controller along the bi-directional bus DQ 116.
In the eleventh clock cycle, the third read information (Rd3) is provided across the first bi-directional bus, DQ 116. In the twelfth clock cycle, the memory is inactive, providing the requisite latent clock cycle across the first bi-directional bus, DQ 116.
Therefore, in the thirteenth clock cycle, a fourth write command may be provided along bus 120 to the first register 122 and a fourth write information (W4) may be provided to the second register 128 along the bi-directional bus DQ 116. Furthermore, similar to clock cycles 2-4, clock cycles 14-16 provide for more write commands and more write information to be provided to the memory device and the storage array.
As illustrated in FIG. 3, due to latency requirements along a bi-directional bus, no information is transferred across the bi-directional bus DQ 116 during clock cycles 4-8, and 12. As recognized by one skilled in the art, the bi-directional bus DQ 116, must maintain a single clock cycle latency period, therefore clock cycle 12 and either 4 or 8 must remain inactive. Furthermore, the storage array does not receive any commands, either read or write commands, during clock cycles 4 and 8-12. As buses 120 and 126 are not bi-directional buses, there are no latency requirements. As such, during multiple clock cycles, the memory 102 cannot receive new commands nor can it write data to the storage array 114 or read data from the storage array 114, thereby creating inefficient information transfer.
One solution to overcome this limitation is the application of a plurality of memory devices having a plurality of bi-directional buses with a single memory controller. Thereupon, during the latency period of a first memory device, a second or third bi-directional bus coupled to the second or third memory device is activated. This system requires multiple memories coupled to a single memory controller and a module for controlling the timing of the multiple memories and the multiple bi-directional buses.
Consequently, there exists a need for an improved apparatus and method for data transfer between a memory controller and a single memory across a bi-directional bus.
USPTO Backgrounds
USPTO Backgrounds