The present invention relates generally to testing a power island interface in a circuit, and more specifically, to a two-state logic power island interface test methodology.
Increasing power consumption in semiconductor chips requires that entire portions of the chips be turned off to save power, when the system does not require the use of the portions of the chip. The portions that can be turned on and off while other portions of the chip remain on and operational are referred to as “power islands.”
For example, U.S. Pat. No. 7,305,639 entitled “Method And Apparatus For Specifying Multiple Voltage Domains and Validating Physical Implementation And Interconnections In A Processor Chip” filed Feb. 12, 2005 teaches that a processor chip may include multiple power domains, each including multiple components that share a same power level, and that each power domain may be powered on or off at different times. The entire disclosure of U.S. Pat. No. 7,305,639 is hereby incorporated by reference.
When a power island is turned off, an adjacent “on” portion of the chip may receive an unintended logic input from the power island. While logical simulation may be used to test for the problem using multi-state logic, this increases the amount of data that needs to be processed and as a consequence slows down simulation significantly.
USPTO Backgrounds
USPTO Backgrounds