Microprocessors may utilize multi-level cache designs in order to reduce the latency of memory accesses. The cache levels closer to the processor cores (level one (L1) caches) may have a design emphasis on low latency, while the cache levels farthest from the processor cores (last-level caches (LLC)) may have a design emphasis on larger capacity. Intermediate cache levels, if present, may be designed for performance with a tradeoff being made between low latency and large capacity.
When a memory access (e.g. read or write) is made to a cache, a determination is made whether the requested memory location is present in the cache (a cache “hit”) or not (a cache “miss”). If a miss occurs, then room in the cache must be made for the requested line to be loaded from an upper-level cache or from system memory. Caches generally have a replacement method for determining which existing cache line should be evicted to make room for this new cache line. This process may often be referred to as “victimization”. Replacement methods may include well-known methods such as the least-recently-used (LRU) method, the random selection method, and the first-in-first-out (FIFO) method. Each of these and other methods may have advantages and drawbacks.
To preserve cache coherency in a multi-processor core system, snooping for requested cache lines is often performed. In a multi-level cache system, this would in general mean that snoop messages would need to be propagated downward, starting at the last-level caches and continuing all the way down to the L1 caches. Partially in order to reduce the latency produced by these snoop messages, many caches are designed to be inclusive. An inclusive cache maintains the property that any cache line present in a lower-level cache is also present in that inclusive cache. Therefore, snooping may in many circumstances need only be performed to the last-level caches: if a particular cache line is not present in the last-level cache, then by the inclusive property it will not be present in any lower-level caches either. However, the inclusive property may produce performance-reducing artifacts of its own.
USPTO Backgrounds
USPTO Backgrounds