As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the use of a metal gate structure with a high-k (dielectric constant) material. The metal gate structure is often manufactured by using gate replacement technologies, and source and drain are formed in a recessed fin by using an epitaxial growth method. One of the challenges, however, in the present technologies is reducing current crowding at the source and drain and increasing the transistor's current drive ability.
USPTO Backgrounds
USPTO Backgrounds