The Integrated Circuit (IC) design industry is facing unprecedented challenges as CMOS technology approaches its fundamental physics limit. Process viability, leakage power and device reliability issues have emerged as serious concerns that nullify the performance benefits gained by traditional device scaling. In particular, the parametric shifts or circuit failures caused by device reliability issues such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) have become more severe with shrinking device sizes and voltage margins. Aging-related circuit degradation has emerged as a new challenge to chip designers recently, because its impact was not significant in previous systems where the heat dissipation was moderate and operating margins were sufficient. The higher voltage stress and elevated temperatures in modern chips, however, are elevating circuit aging to become an increasingly important design consideration in high performance systems. Moreover, process improvements such as high-k/metal gate devices have introduced new degradation issues including positive-BTI (PBTI) in N-type devices, adding to the already complex aging behavior.
A major concern in IC designs (e.g., three-dimensional (3D) IC designs) is ensuring reliability and quality. Failure caused by aging and degradation affects the reliability and quality of IC components. Examples of known failure mechanisms include: (1) Electromigration (EM): a directional transport of electrons and metal atoms in interconnect wires leads to degradation and eventual failure; (2) Time-dependent dielectric breakdown (TDDB): wear-out of gate oxide caused by continued application of electric fields, which can lead to an electric short between the gate oxide and substrate; (3) Hot carrier injection (HCI): electrons that capture sufficient kinetic energy overcome the barrier to gate oxide layer and cause a threshold voltage shift and performance degradation; (4) Negative bias temperature instability (NBTI): holes trapped in the gate oxide layer cause the threshold voltage to shift. The switching between negative and positive gate voltages cause performance degradation and recovery from the NBTI degradation; (5) Stress migration (SM): mechanical stress due to the differences between the expansion rates of metals causes the failure; and (6) Thermal cycling (TC): fatigue accumulates in the silicon oxide layer with temperature cycles with respect to the ambient temperature. A ring oscillator is a device that includes an odd number of logic gates whose output oscillates between two voltage levels, representing true and false. The logic gates are typically attached in a chain and the output of the last logic gate is fed back into the first logic gate in the chain. High temperature is one cause of premature transistor aging and degradation. Ring oscillators are used as temperature sensors at the wafer level to monitor transistor aging by exploiting the linear relationship between oscillation frequency and temperature. In addition, aging and degradation resulting from various AC stress and DC stresses, such as PMOS HCI, PMOS BTI, NMOS HCI and NMOS BTI, can be tested and measured using ring oscillators.
USPTO Backgrounds
USPTO Backgrounds