Semiconductor device geometries (i.e., integrated circuit design rules) have decreased dramatically in size since integrated circuit (IC) devices were first introduced several decades ago. ICs have generally followed “Moore's Law,” which means that the number of devices fabricated on a single integrated circuit chip doubles every two years. Today's IC fabrication facilities (i.e., “fabs”) are routinely producing 65 nm (0.065 μm) feature size devices, and future fabs will soon be producing devices having even smaller feature sizes.
In most IC fabrication facilities, part of the fabrication process involves employing plasma in process equipment to either react or facilitate a reaction with a substrate such as a semiconductor wafer. Plasma processing is used for a wide variety of applications including etching of materials from substrates, deposition of materials onto substrates, cleaning of substrate surfaces, and modification of substrate surfaces.
As feature sizes have become smaller, the aspect ratio, or the ratio between the depth and the width of the feature has steadily increased. Fabrication facilities are currently etching materials into features having aspect ratios of from about 50:1 to 100:1 or greater. Traditionally, features having aspect ratios of about 10:1 were produced by anisotropic etching dielectric layers to a predetermined depth and width. However, when forming higher aspect ratio features, anisotropic etching using conventional sidewall passivation techniques has become increasingly difficult to control. Resulting features have non-uniform spacing or non-uniform profiles, thus losing designed critical dimensions (CDs) of the features.
Etching deeply-recessed features is a principal technology used to fabricate capacitive storage nodes, contact vias, and trench features into semiconductor structures. Strict control of etch profiles is needed to provide deeply etched features having required CDs.
Due to the ever-decreasing size of device structures, the thickness of a photoresist layer must be carefully controlled to meet critical feature dimensions. The thickness of the photoresist is often in the range of about 250 nm or less. A hard masking material is used under the photoresist to provide sufficient time for deep-etching of an underlying substrate without etching through the patterned mask.
A carbon-containing gas is frequently used as at least one of the etchant gases during plasma deep-etching into a substrate underlying the photoresist mask and the hard mask. The carbon-containing gas contributes polymer-forming materials onto various exposed surfaces fabricated on the substrate. The polymer-forming materials can frequently plug openings in features being etched and have deleterious effects on parameters such as top CD and CD bias uniformity. In the worst case, openings to smaller CD features which are to be etched may become completely plugged if a resulting polymeric residue is sufficiently thick. Once plugged, the etching stops. Using increased power to drive the etch plasma, for purposes of increasing etch rate, typically leads to an increase in the amount of hard, silicon-containing polymeric residues that are re-deposited on various surfaces. Thus, concerns about formation of the residues affects an ability to increase the etch rate during etching of a deeply recessed structure.
Yet another challenge associated with etching features with high aspect ratios is controlling the etch rate in features formed through multiple layers and having different feature densities. In such a case, each layer may etch at a different rate depending on feature density.
With reference to FIG. 1, a substrate 101 includes a dielectric film layer 103 with a plurality of high density features 109 and an isolated feature 111 formed from an underlying film 105 or bulk material (not shown). Each of the features 109, 111 is capped with a combination photoresist layer/hard mask 107. Faster etch rates occur proximate to the isolated feature 111 and often result in selectively over etching the dielectric film layer 103. In contrast, slower etch rates occurring proximate to the high density features 105 frequently have unetched portions 113.
As features move toward even higher aspect ratios and densities, maintaining efficient etching rates over the low and high feature density regions without either under-etching the upper layers or over-etching into the lower layers has become increasingly difficult to control. The failure to form the features or patterns on the substrate as designed may result in unwanted defects. Further, subsequent process steps are adversely affected, ultimately degrading or disabling the performance of the final integrated circuit structure.
Another problem in etching features with high aspect ratios is the occurrence of a micro-loading effect. Micro-loading is also known as “aspect ratio dependent etch” or “RIE lag” and is a measure of the variation in etch dimensions between regions of high and low feature densities. Low feature density regions (e.g., isolated regions) receive more reactive etchants per surface area compared with high feature density regions (i.e., dense regions) due to larger total openings of the surface areas, thereby resulting in a higher etching rate in the low density regions. Sidewall passivation layers generated from etch by-products exhibit similar pattern density dependence where thicker passivation layers are formed for the isolated features due to more by-products being generated in the region. The difference in reactants and the passivation per surface area between these two regions increases as feature density differences increase.
Referring now to FIG. 2A, differences in etch rates and formation of by-products between high and low feature density regions cause various differences in sidewall etch. An isolated or low feature-density region 203 typically etches with a desired shape and controlled lateral dimensions. In contrast, a high feature-density region 201 has sidewall regions 205 which are frequently bowed or undercut by the lateral etching due to insufficient sidewall passivation.
The bowing of the device feature can cause various deleterious effects including increased difficulty in performing subsequent process steps after the plasma etch. For example, if features in a shallow trench isolation (STI) are bowed due to a damage caused by the plasma etch process, a subsequent chemical vapor deposition (CVD) process used to fill the space between the STI features with an electrically insulating layer will leave a seam or void in the layer.
To avoid the lateral etching of sidewalls, an oxidation step (e.g., thermally formed or deposited silicon dioxide, SiO2) is typically used to avoid insufficient sidewall passivation and a resulting lateral sidewall etch. However, the SiO2 layer is formed by combining oxygen with silicon. In a thermal oxidation process, 44% of the SiO2 layer is consumed silicon. Thus, the oxidizing step comes at the expense of the remaining silicon resulting in additional bowing and CD enlargement once the oxidized layer is removed.
As indicated by FIG. 2B, other process techniques result in a low feature-density region 253 etching at a faster rate with more passivation than a high feature-density region 251. The higher etch rate results in a tapered top portion 255 on etched sidewalls. Therefore, insufficient sidewall protection associated with the different etch rates in high and low feature-density regions with high aspect ratios often results in an inability to hold critical dimensions of the etch features and a resulting poor pattern transfer.
The tapered top portion 255 eventually leads to an etch depth micro-loading problem at a location where a multitude of features are closely populated thus affecting an overall CD of the features. Thus, it is becoming increasingly more difficult to etch closely populated features with small space CDs using contemporary continuous plasma etch processes.
Therefore, what is needed is an improved method to simultaneously etch high aspect ratio features of high and low feature-density regions while maintaining uniform CDs of the features.
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