In a half bridge circuit, or the like, in which switching elements are connected in series and which is driven by a high potential power supply, a level shift circuit is used in order that a high potential side switching element is driven by a low potential signal.
FIG. 1 shows a configuration diagram of a half bridge circuit 100 using a heretofore known level shift circuit. The half bridge circuit 100 shown in FIG. 1 is configured of an output circuit 110, a high potential side drive circuit 120, and a low potential side drive circuit 130. The output circuit 110 is connected to the high potential side drive circuit 120 and low potential side drive circuit 130. Also, synchronized signals are input from the exterior into each of the high potential side drive circuit 120 and low potential side drive circuit 130.
The output circuit 110 is configured of a switching element XD1, a switching element XD2, a power source E, and a load L1. In the output circuit 110, the switching element XD1 is connected in series to the switching element XD2, to which the load L1 is connected in parallel, and the high voltage power source E supplies power to the load L1 via the switching element XD 1. The switching element XD 1 is a high potential side switching element, and can be, for example, an n-channel or p-channel MOS transistor, a p-type or n-type IGBT (Insulated Gate Bipolar Transistor), or the like. The switching element XD2 is a low potential side switching element, and can be, for example, an n-channel MOS transistor, an n-type IGBT, or the like. Hereafter, the switching element XD1 and switching element XD2 will be assumed to be n-channel MOS transistors.
The high potential side drive circuit 120 is configured of a level shift circuit, a high side driver 123, and a power source E1 (hereafter, the output voltage thereof will also be expressed as E1). The level shift circuit is a portion of the high potential side drive circuit 120 excluding the high side driver 123 and power source E1, and is configured of a latch malfunction protection circuit 121, a latch circuit 122, a first series circuit 124, a second series circuit 125, feedback resistors R3, R4, R5, and R6 (the resistance values thereof are also taken to be R3, R4, R5, and R6 respectively), p-channel MOS transistors (hereafter expressed as PM) 1 and PM2, a diode D1 and diode D2, and an inverter INV.
The first series circuit 124 is configured of a level shift resistor R1 (the resistance value thereof is also taken to be R1) and a high breakdown voltage n-channel MOSFET (hereafter expressed as HVN) 1 connected in series, and outputs a level shift output signal setdrn (hereafter expressed as a setdrn signal) to the latch malfunction protection circuit 121 via a first connection point Vsetb (the potential thereof is also taken to be Vsetb). Herein, the first series circuit 124 includes a first level shift output terminal (corresponding to the first connection point Vsetb) for outputting the setdrn signal to the latch malfunction protection circuit 121, and the first level shift terminal is connected to the latch malfunction protection circuit 121.
The second series circuit 125 is configured of a level shift resistor R2 (the resistance value thereof is also taken to be R2) and an HVN2 connected in series, and outputs a level shift output signal resdrn (hereafter expressed as a resdrn signal) to the latch malfunction protection circuit 121 via the HVN2 and a second connection point Vrstb (the potential thereof is also taken to be Vrstb). Herein, the second series circuit 125 includes a second level shift output terminal (corresponding to the second connection point Vrstb) for outputting the resdrn signal to the latch malfunction protection circuit 121, and the second level shift terminal is connected to the latch malfunction protection circuit 121.
The PM1 is connected in parallel to the resistor R1 configuring the first series circuit 124. The PM2 is connected in parallel to the resistor R2 configuring the second series circuit 125.
A connection point of the feedback resistors R3 and R5 is connected to the gate terminal of the PM2, and a connection point of the feedback resistors R4 and R6 is connected to the gate terminal of the PM1. A feedback circuit is configured of the inverter INV, the feedback resistors R3, R4, R5, and R6, the PM1, and the PM2. Also, regarding the resistance values of the level shift resistors R1 and R2 and the feedback resistors R3, R4, R5, and R6, it is taken that R1=R2, R3=R4, and R5=R6.
The setdrn signal and resdrn signal are input into the latch malfunction protection circuit 121. The latch malfunction protection circuit 121 is a circuit that, when a false signal called dv/dt noise occurs because of source-to-drain parasitic capacitors Cds1 and Cds2 of the HVN1 and HVN2, that is, when the potential Vsetb and the potential Vrstb are both at an L (low) level, outputs at a high impedance so that the latch circuit 122 is not affected.
The latch circuit 122 is connected to the latch malfunction protection circuit 121 and high side driver 123. The latch circuit 122 is a circuit into which the output from the latch malfunction protection circuit 121 is input that stores and outputs the value of the input when the input is at an L or H level and, when the input is of a high impedance, holds and outputs the value stored immediately before the input reaches the high impedance.
The output terminal of the latch circuit 122 is connected via the feedback resistors R4 and R6 to the second connection point Vrstb, which is a connection point of the level shift resistor R2 and HVN2 configuring the second series circuit 125. Also, by inverting the output of the latch circuit 122 using the inverter INV, an output the inverse of the output of the latch circuit 122 is obtained. The output terminal of the inverter INV that outputs the inverted output is connected via the feedback resistors R3 and R5 to the first connection point Vsetb, which is a connection point of the level shift resistor R1 and HVN1 configuring the first series circuit 124.
The high side driver 123 is connected to the high potential side switching element XD1 and latch circuit 122, and outputs a signal HO in accordance with the output of the latch circuit 122, thereby controlling the turning on and off of the switching element XD1.
The output terminal of the high side driver 123 is connected to the gate terminal of the switching element XD1. The latch malfunction protection circuit 121, the latch circuit 122, the high side driver 123, and the low potential side power source terminal of the power source E1 are connected to a connection point vs (hereafter, the potential thereof will also be expressed as vs) of the switching elements XD1 and XD2. Also, the latch malfunction protection circuit 121, latch circuit 122, and high side driver 123 receive a supply of power from the power source E1. In the same way, although not shown, the low potential side power source terminal of the inverter INV is also connected to the connection point vs, and receives a supply of power from the power source E1.
One end of each of the first series circuit 124 and second series circuit 125 is connected to a power source line vb (hereafter, the potential thereof will also be expressed as vb) connected to the high potential side terminal of the power source E1, while the other end of each is connected to a ground potential (GND). A set signal, which is a signal input into the level shift circuit of the high potential side drive circuit 120, is input into the gate of the HVN1, while a reset signal, which is a signal input into the level shift circuit of the high potential side drive circuit 120, is input into the gate of the HVN2.
The anodes of the diodes D1 and D2 are connected to the connection point vs of the switching elements XD1 and XD2, the cathode of the diode D2 is connected to the first connection point Vsetb, and the cathode of the diode D1 is connected to the second connection point Vrstb. The diodes D1 and D2 are for clamping the voltages Vsetb and Vrstb so that they do not drop to or below the potential vs, thus protecting the latch malfunction protection circuit 121 by ensuring that no overvoltage is input.
The feedback resistors R5 and R6 are connected to the vb potential or vs potential via a PMOS or NMOS of a CMOS circuit or logic inversion CMOS circuit (INV) used in the latch circuit 122, but for the sake of simplicity, the PMOS and NMOS are not shown in the latch circuit 122, and in the same way, will not be shown hereafter.
The low potential side drive circuit 130 is configured of a low side driver 131 that controls the turning on and off of the low potential side switching element XD2, and a power source E2 (hereafter, the potential thereof will also be expressed as E2) that supplies power to the low side driver 131.
The low side driver 131 is supplied with power from the power source E2, amplifies a signal S input into the low side driver 131, and inputs it into the gate terminal of the switching element XD2. According to this configuration, the switching element XD2 is turned on (energized) when the signal S is at an H (high) level, and the switching element XD2 is turned off (cut off) when the signal S is at an L (low) level. That is, the signal S is a signal that directly commands the turning on or off of the switching element XD2.
Of the set signal and reset signal input into the high potential side drive circuit 120, the set signal is a signal that indicates the timing of the start of an on-state period (the end of an off-state period) of the switching element XD1, while the reset signal is a signal that indicates the timing of the start of an off-state period (the end of an on-state period) of the switching element XD2.
The switching elements XD1 and XD2 are turned on and off in a complementary way such that when one is in an on-state the other is in an off-state, except during a dead time to be described hereafter, with the potential vs of the connection point vs reaching the ground potential when the switching element XD2 is in an on-state, and the potential vs of the connection point vs reaching the output voltage E of the power source E when the switching element XD1 is in an on-state. Also, the load L1 is a load that receives a supply of power from the half bridge circuit 100, and is connected between the connection point vs and the ground potential.
In the kind of heretofore known half bridge circuit 100 shown in FIG. 1, it is often the case that there is a large difference in potential of in the region of several hundred volts between the low potential side power source voltage E2 and high potential side power source voltage E1. Because of this, it may happen that the difference in potential occurs between wiring linking the high potential side circuit and low potential side circuit and a semiconductor forming an underlay of the wiring. In particular, when the wiring potential is a high voltage due to the high potential side circuit and a subsequent stage is a low potential side circuit region, voltage generation and the effect thereof are marked. When simply applying metal wiring of a semiconductor as the wiring linking the high potential side circuit and low potential side circuit, a high electric field is generated between the wiring and the semiconductor immediately below, and various problems occur in the level shift circuit. In order to solve the heretofore described kind of problem, it is possible to apply a wire bonding method in the level shift circuit. A wire bonding method is a method whereby the drain of the HVN1 and the first connection point Vsetb, and the drain of the HVN2 and the second connection point Vrstb, are connected by wiring in, for example, FIG. 1. As the wiring is point-to-point wiring distanced from the semiconductor when using a wire bonding method, it is possible to prevent a high electric field from being generated in the semiconductor region forming the underlay.
However, the application of a wire bonding method has a detrimental effect on the cost of the level shift circuit and on downsizing the product due to, for example, an increase in man-hours, the need for wiring space, and the like. Consequently, there is a demand for a level shift circuit that does not use a wire bonding method. The technologies shown in PTL 1 and PTL 2 (identified below) exist as level shift circuits that do not use a wire bonding method.
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