1. Field of the invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory device (DRAM).
2. Description of the prior art
FIG. 5 illustrates schematically a DRAM comprising memory cells. A memory cell which is indicated by a broken-line circle 10 in FIG. 5 is composed of an MOS transistor and a capacitor. The configuration of a conventional DRAM will be described by illustrating the operation of the DRAM. When a row decoder 20 selects one of word lines (e.g., a word line 40), according to an address signal input from outside the semiconductor chip, the signal charges written into memory cells are read out to bit lines /BIT.sub.l -/BIT.sub.N, respectively, and slight differences in potential occur between bit lines /BIT.sub.l and BIT.sub.l, . . . and /BIT.sub.N and BIT.sub.N. These slight differences in potential are amplified by sense amplifiers SA.sub.l to SA.sub.N to be output, while their respective signal charges are written back into the same memory cells. In FIG. 5, numeral 70 indicates a pull-up wire for driving the sense amplifiers SA.sub.l to SA.sub.N, and 60 is a pull-down wire. The DRAM of FIG. 5 has a memory cell array of the so-called "folded-bit" type in which there are memory cells at half of the word line and bit line intersections. The coupling capacitances between the word line 30 and bit lines (BIT.sub.i and /BIT.sub.i) are C.sub.i on the side where a memory cell is connected, and /C.sub.i on the side where a memory cell is not connected.
When data of the memory cells connected to the word line 40 are read out, amplified and rewritten, depending on the read-out data pattern, coupling noises from the bit lines may enter the unselected word line 30, thus destroying the data in memory cells M3.sub.l, . . . , M3.sub.i, . . . M3.sub.N connected to the unselected word line 30. Below is a detailed description of this phenomenon.
FIG. 6 shows the structure of the part enclosed by a broken line 50 in FIG. 5. In FIG. 6, numeral 500 is a silicon substrate. The word lines 30 and 40 are formed from polysilicon, and the bit line /BIT.sub.N is formed from aluminum or other material. 501 and 502 are SiO.sub.2 films, and 503 is a gate oxide film. 504 is an oxide film constituting the cell capacitance, 53 is a cell plate, 52 is a cell capacitance node, 51 is the source area to which the bit line /BIT.sub.N and the MOS transistor M4.sub./N are connected, and 54 is a field oxide film. The coupling capacitances C.sub.i and /C.sub.i can be expressed by EQU C.sub.i =C.sub.GS +C.sub.CW +C.sub.O EQU /C.sub.i =C.sub.O
where C.sub.GS is the capacitance between the gate and source of the switching transistor in the memory cell, C.sub.CW is the coupling capacitance between the bit line /BIT.sub.N and the word line 40 in the contact part of the bit line /BIT.sub.N, and C.sub.O is the coupling capacitance between the bit line /BIT.sub.N and the word line 30 or 40. Form the above expressions, the relation C.sub.i &gt;/C.sub.i can be easily seen.
As the degree of integration of semiconductor devices has increased in recent years, the gate oxide film of MOS transistors has tended to become thinner. Therefore, the capacitance C.sub.GS has tended to increase. On the other hand, the introduction of self-aligned contacts due to decreased planar surface areas has brought bit lines and word lines closer and closer together in the contact areas, and as a result, the capacitance C.sub.CW also has tended to increase in recent years, resulting in C.sub.i &gt;&gt;/C.sub.i. In other words, among the coupling capacitances between word lines and bit lines, the capacitance at the side on which the memory cell is connected is tending to become excessively large.
With reference to FIG. 7, the operation of the memory device shown in FIG. 5 will be described. In FIG. 7, curve a depicts the change in potential in the selected word line 40. It is assumed that "1" or "0" has been written in all the memory cells M4.sub./l -M4.sub./N connected to the selected word line. When "1" is written in all the selected memory cells M4.sub./l -M4.sub./N, the change in potential in the bit lines /BIT.sub.l -/BIT.sub.N connected to the selected memory cells is illustrated by the waveform indicated by c in FIG. 7, and the change in potential in the complementary bit lines BIT.sub.l -BIT.sub.N by the waveform b in FIG. 7. In other words, in FIG. 7, the bit line pairs (BIT.sub.l and /BIT.sub.l -BIT.sub.N and /BIT.sub.N) are precharged from time 0 to time T1. At time T1, the word line potential begins to rise, and the signal charges stored in the memory cells generate a slight potential difference, .DELTA.V.sub.l or .DELTA.V.sub.O (shown in FIG. 7), corresponding to "1" or "0". At time T2, the signals are amplified by the sense amplifiers SA.sub.l -SA.sub.N, as shown in FIG. 7. At time T3, the potential in the word line begins to drop, completing the rewriting of the data in the memory cells. Precharge then begins at time T4 in preparation for the next read-out cycle. In contrast, when "0" is written in all the selected memory cells M4.sub./l -M4.sub./N connected to the selected word line 40, the change in potential in the bit lines /BIT.sub.l -/BIT.sub.N connected to the selected memory cells is as indicated by waveform b in FIG. 7, and the change in potential in the complementary bit lines BIT.sub.l -BIT.sub.N as indicated by the waveform c in FIG. 7.
Since the coupling capacitance on the side where the memory cell is connected is larger (i.e., C.sub.i &gt;&gt;/C.sub.i) as described above, the difference, .DELTA.C=C.sub.i-/ C.sub.i, becomes a capacitance contributing to the generation of noises entering the word lines from the bit line. The noise entering the unselected word line 30 are indicated by broken lines d and d' in FIG. 7. These noises correspond respectively to the portions Nc and Nb of the waveforms c and b in FIG. 7. That is, when rewriting or precharging a memory cell (e.g., the cell M4.sub./l), noises are generated in the unselected word line 30. These noises cause the destruction of the data in the memory cells (e.g., the cell M3.sub.l) connected to the unselected word line 30. This will be discussed in more detail below.
FIG. 8A shows the equivalent circuit of a memory cell, and FIG. 8B is a graph illustrating the cutoff characteristic of a switching transistor, i.e., a so-called Vg - logI.sub.D graph. The current characteristic in an area below the threshold voltage V.sub.T in the Vg - logI.sub.D graph (area S in FIG. 8B) is referred to as the sub-threshold area, and has a significant effect on the holding characteristic of the memory cell. This is because, when the word line potential (i.e., the gate potential) rises transiently due to the above-mentioned noise, and even if this increased potential does not reach the threshold voltage V.sub.T, the current flowing through the transistor increases logarithmically, resulting in an outflow of the signal charge. This causes the degradation of the holding characteristic.
In the prior art, this problem is dealt by designing a memory device so that the slope of the subthreshold area S of the switching transistor is steeper, and that the number of memory cells connected to a word line is reduced to decrease the coupling capacitance between the bit lines and word lines. However, these measures have become more difficult as the degree of integration of memory chips increases. That is, as the degree of integration increases, the structure of transistors becomes more complex and the number of design parameters to be controlled increases markedly. As a result, optimizing only the subthreshold area becomes difficult. Further, reducing the number of memory cells connected to a word line and increasing the number of array divisions in a memory chip require that the area of the chip be increased.
As described above, noises caused by the coupling between bit lines and unselected word lines in a prior art semiconductor memory device produce a serious problem that data stored in memory cells connected to the unselected word lines are destroyed.
USPTO Backgrounds
USPTO Backgrounds