1. Field of the Invention
The present invention is related to a data transceiving system, and more particularly, to a method and a data transceiving system for generating a reference clock signal.
2. Description of Related Art
FIG. 1 illustrates a structure of a data transceiver of a conventional integrated chip. The data transceiver 100 comprises a phase lock loop (PLL) unit 110, a data transmitter (TX) 120, and a data receiver (RX) 130 having a function of clock data recovery (CDR). The integrated chip generates a clock signal having an accurate frequency (i.e. less than tens ppm deviating from a target frequency) by using a crystal device 140, and uses the same as a reference clock for transceiving data. In detail, the PLL unit 110 uses the reference clock as an input to generate a PLL clock output which has a frequency equal to a multiple of the clock frequency of the reference clock. The PLL clock is used as a reference clock for clock data recovery and used for generating a retimed data stream. The clock output generated during the clock data recovery is generated based on a base frequency of the received input data stream. Further, the PLL clock may also be used as a clock signal source and used for transmitting a data stream that is originally not accompanied by a clock signal.
The accuracy of the reference frequency of the PLL clock is essential in serial data transmission and can only tolerate considerably small frequency error. In detail, the frequency error is required to comply with a given standard specification, which is usually the allowable maximum of the bit error rate (BER). For example, in the high-speed (HS) mode of universal serial bus (USB) 2.0 specification, the accuracy of the PLL clock frequency is about 500 ppm deviating from a base frequency of the received data stream. Although a commercial crystal device may provide a clock signal with the frequency error less than 100 ppm and can serve as an ideal clock signal source, this kind of crystal device usually costs a lot and occupies a larger space of the circuit board.
USPTO Backgrounds
USPTO Backgrounds