The present invention relates to a nonvolatile memory array.
For NVRAMs using tunnelling to store charge in dielectric traps, there is a trade-off between write speed and storage time, because the same potential barriers which retard leakage of trapped charge into the channel also impede fast writing. (Avalanche-assisted write mechanisms partly avoid this dilemma, but only at the expense of greatly reduced device lifetime. The lifetime of an avalanche-write cell will typically be on the order of 10.sup.5 cycles, as opposed to 10.sup.14 cycles for the cell of the present invention.) Thus if a nonvolatile memory is to attain write speeds remotely comparable to those of a DRAM, relatively short nonvolatile storage times must be tolerated. For example, a memory having a 200 nsec write time will have a nonvolatile storage time down around 3 days.
However, nonvolatile memory arrays having such storage lifetimes retain most of the advantages of nonvolatile memory. That is, for many applications the trade off between storage time and write speed can desirably be exploited, if the result is a memory array which appears to have read and write characteristics closer to those of a conventional SRAM.
It is thus an object of the present invention to provide a nonvolatile memory array optimally incorporating memory cells which have good write speed and reduced nonvolatile storage time.
A particular difficulty in reading multi-dielectric type nonvolatile storage transistors which are well along in their storage lifetime is that the degradation of the two states of stored information is not symmetrical. That is, a transistor having trapped holes in its dielectric will degrade at a different rate than a transistor having trapped electrons in its dielectric. Thus, the provision of a reference voltage which will optimally discriminate between +V.sub.TH program states and -V.sub.TH program states is critical.
It is a further object of the present invention to provide a reference voltage generator for nonvolatile memories which will accurately provide a reference voltage which varies during the storage lifetime of nonvolatile transistors to provide a constantly optimized reference voltage for discrimination between +VTH and -VTH program states.
USPTO Backgrounds
USPTO Backgrounds