With the increasing down scaling of integrated circuits and increasingly higher requirements for integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFET) were thus developed. FIGS. 1 and 2 illustrate perspective views of conventional FinFETs. Fins 4 are formed as vertical silicon fins extending above substrate 2, and are used to form source and drain regions 6 and channel regions therebetween (not shown). Vertical gates 8 intersect the channel regions of fins 4. While not shown in FIGS. 1 and 2, gate dielectrics are formed to separate the channel regions from the respective vertical gates 8. The ends of fins 4 receive source and drain doping implants that make these portions of fins 4 conductive.
The structure shown in FIG. 1 is a silicon-on-insulator (SOI) FinFET structure, which is formed using an SOI substrate including semiconductor substrate 2, buried oxide layer (BOX) 10, and an overlying silicon layer. The overlying silicon layer is patterned to form fin 4, on which the FinFET device is based. SOI FinFET devices have excellent electrical performance. However, the manufacturing cost is high.
The structure shown in FIG. 2 is a bulk FinFET structure, which is formed starting from a bulk silicon substrate. The manufacturing cost of the bulk FinFETs is lower compared to SOI FinFETs. However, punch-through currents (leakage currents) may flow in a region not controlled by gate 8, as shown as the region 12 in FIG. 3, which is a cross-sectional view of the structure shown in FIG. 2. The cross-sectional view is made through a plane crossing line A-A′ in FIG. 2. Conventionally, to reduce the punch-through currents, an impurity implantation is performed using a high energy to dope region 12 to a high impurity concentration, for example, about 1019/cm3, wherein the impurity has a conductivity type opposite to that of source/drain regions 6. The implantation is performed after the formation of fin 4, but before the formation of gate 8. The entire fin 4 is thus implanted. By using this method with a high impurity concentration, although the punch-through currents are reduced, the carrier mobility is adversely reduced. Additionally, in this structure the fin height is affected by the position of the top surface of STI 10, which is varied in the multiple cleaning processes performed in subsequent manufacturing processes. The fin height variation is thus high, resulting in a device performance variation.
FIGS. 4 through 6 illustrate the formation of another conventional FinFET device. In FIG. 4, silicon substrate 16 is provided. Nitride strip 18 is formed on silicon substrate 16, and is used to recess silicon substrate 16, forming fin 20. In FIG. 5, nitride spacers 24 are formed to cover sidewalls of fin 20. An oxidation is then performed to form field oxide 26, as is shown in FIG. 6. The top portion of fin 20 is protected from the oxidation, and is electrically isolated from substrate 16 by field oxide 26. Advantageously, the FinFET formed based on fin 20 has substantially no punch-through currents, similar to the SOI FinFETs. Additionally, the fin height of fin 20 is not affected by the subsequent process, even if the top surface of field oxide 26 may be lowered in subsequent processes. However, the planar transistor formed on the same semiconductor chip does not have good isolation performance.
What are needed in the art, therefore, are formation methods and structures thereof that incorporate FinFETs to take advantage of the benefits associated with the increased drive currents while at the same time overcoming the deficiencies of the prior art.
USPTO Backgrounds
USPTO Backgrounds