Circuit devices which are fabricated on or over semiconductor wafers typically undergo one or more photolithographic steps during formation. During such photolithographic steps, device features can be etched using conventional techniques. The spacing between such devices is important because often times adjacent devices must be electrically isolated from one another to avoid undesirable shorting conditions.
One of the limitations on device spacing stems from limitations inherent in the photolithographic process itself. In the prior art, devices are generally spaced only as close as the photolithographic limit will permit.
By way of example and referring to FIGS. 1 and 2, a semiconductor wafer fragment is indicated generally by reference numeral 25. Fragment 25 includes a substrate 29 atop which a material 28 is provided. A plurality of patterned masking layers 26 are formed atop material 28.
Referring to FIG. 3, material 28 is anisotropically etched to form lines 30 atop substrate 29. As shown, individual lines have respective widths L.sub.1 which constitute the minimum photolithographic feature size available for a line. Typically, a separation S.sub.1 separates adjacent lines across the substrate as shown. Such dimension is typically only slightly larger than L.sub.1 but could be the same as L.sub.1. The term "pitch" as used in this document is intended to be in its conventional usage, and is defined as the distance between one edge of a device and the corresponding same edge of the next adjacent device. Accordingly and in the illustrated example, the pitch between adjacent lines P.sub.1 (i.e., from the left illustrated edge of one line to the left illustrated edge of the next immediately adjacent line) is equal to the sum of L.sub.1 and S.sub.1.
As integrated circuitry gets smaller and denser, the need to reduce spacing dimensions or pitch, such as S.sub.1 and P.sub.1, becomes increasingly important. This invention grew out of the need to reduce the size of integrated circuits, and particularly the need to reduce spacing dimensions and pitches between adjacent devices over a semiconductor wafer.
USPTO Backgrounds
USPTO Backgrounds