1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor substrate. In particular, the present invention relates to a manufacturing method of a semiconductor substrate that is effective in gaining a high quality silicon substrate wherein distortion of silicon is utilized.
2. Description of Related Art
In recent years extensive research has been carried out concerning the manufacture of a high mobility transistor wherein a hetero structure is fabricated using a material having a lattice constant that is different from that of Si, that is to say, a film of a material having a lattice constant different from that of silicon substrate is grown on a silicon substrate in an epitaxial manner and, thereby, distortion due to compression or stretching in the horizontal direction is provided in the film so that the distortion is utilized in order to achieve an increase in the speed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in place of a conventional technology wherein a MOS interface of Si—SiO2 is used as a channel.
The technology shown in FIGS. 3(a) to 3(e) is cited as an example of a manufacturing technology for a MOSFET wherein distortion is utilized.
First, as shown in FIG. 3(a), a SiGe layer 2 is grown in an epitaxial manner to have a thickness of approximately 300 nm and to have a concentration of Ge of 20 atom % on a silicon substrate 1 and a Si layer 3 is sequentially grown in an epitaxial manner to have a thickness of approximately 20 nm on the SiGe layer.
Next, as shown in FIG. 3(b), hydrogen ions are implanted into the entirety of the surface of the gained silicon substrate 1 and, after that, a heat treatment is carried out at approximately 800° C. As a result of this heat treatment, stacking faults 5 extending from micro voids 4 of hydrogen that have occurred in the vicinity of the hydrogen implantation peak reach to the interface between SiGe layer 2 and silicon substrate 1 and, furthermore, cause threading dislocations 6 in the direction of the interface. Distortion in SiGe layer 2 is relaxed due to the occurrence of these threading dislocations 6 in the direction of the interface. At this time, distortion due to stretching is generated in Si layer 3 on SiGe layer 2, wherein the distortion is relaxed and the mobility is increased in Si layer 3.
After that, as shown in FIGS. 3(c) and 3(d), the procedure passes through a conventional STI (Shallow Trench Isolation) process so that element isolation regions 11 are formed and, furthermore, as shown in FIG. 3(e), a gate insulating film 12, a gate electrode 13 and source/drain regions 14 are formed according to a general manufacturing process so that a MOSFET is completed.
According to the above described manufacturing method, however, in the case wherein the amount of implantation of hydrogen ions is sufficient to complete the relaxation of SiGe layer 2 in the step of implantation of hydrogen ions as shown in FIG. 3(b), excessive micro voids 4 of hydrogen are formed due to the subsequent heat treatment and excessive stacking faults are formed. These excessive stacking faults do not stop at the interface between SiGe layer 2 and silicon substrate 1 but cause threading dislocations 6 that reach to the surface of Si layer 3. These threading dislocations 6 caused by micro voids 4 of hydrogen are fixed by micro voids 4 of hydrogen and, therefore, it is difficult to remove threading dislocations 6 in the subsequent steps.
Thus, the amount of implantation of hydrogen ions is set at an amount of implantation lower than the amount that completely relaxes SiGe layer 2 and, thereby, prevention of the occurrence of threading dislocations 6 due to micro voids 4 of hydrogen in the subsequent heat treatment is attempted.
However, even in the case wherein the amount of implantation of hydrogen ions is set at an amount of implantation lower than the amount that completely relaxes SiGe layer 2, new occurrences of threading dislocations 6 from the interface between SiGe layer 2 and silicon substrate 1 in the subsequent heat treatment as shown in FIG. 3(b) cannot be avoided. Accordingly, the procedure passes through a conventional STI process as shown in FIGS. 3(c) and 3(d) under such conditions so that a MOSFET is fabricated and, then, many threading dislocations 6 are found beneath source/drain regions 14 as shown in FIG. 3(e) wherein the leakage current increases at the time when a reverse voltage is applied to these junctions and, therefore, there is a problem wherein a manufacturing technology for a high quality MOSFET cannot be established.
USPTO Backgrounds
USPTO Backgrounds