1. Field of the Invention
The present invention relates to a P-channel non-volatile semiconductor memory device capable of electrical writing and reading.
2. Description of the Related Art
In recent years, there is known a semiconductor integrated circuit including a bleeder resistor circuit capable of being trimmed by a memory. Conventionally, the bleeder resistance is adjusted by a method of mechanically cutting a fuse formed in parallel to the bleeder resistor with the use of laser light or the like.
The trimming of the bleeder resistor can therefore be performed only before the package assembly. The use of a semiconductor memory for trimming the bleeder resistor, on the other hand, enables electrical trimming even after the assembly. The following two typical benefits are obtained.
1. Quick delivery can be obtained because trimming is carried out in the packaged state before shipment.
2. High precision can be achieved because trimming covers package shift that occurs during package assembly.
In general, once the bleeder resistor is trimmed, there is no need to rewrite information. Accordingly as a memory for trimming, an ultraviolet-light-erasable programmable read only memory (EPROM) is used as a one-time programmable (OTP) memory. Further, unlike a memory IC, the memory for trimming the bleeder resistor requires small memory capacity. As compared to the memory IC, high integration and high-speed operation of a memory cell are not required. Consequently, the typical challenges required for the memory for trimming include downsizing a peripheral circuit for controlling the memory, achieving lower voltage operation, and utilizing the existing manufacturing process.
As a conventional ultraviolet-light-erasable EPROM, a non-volatile EPROM for writing information with the use of hot carriers is known.
At present, the mainstream of the non-volatile memory for writing information with the use of hot carriers is an N-channel non-volatile EPROM. One of the reasons is that the N-channel non-volatile EPROM has a higher operating speed than a P-channel EPROM.
However, as described above, the memory for trimming the bleeder resistor has small capacity and is not required to rewrite information once the information is written in trimming, and hence there is no problem even if the operating speed is lower than that of the memory IC. Further, in the P-channel EPROM, without applying such a high potential that causes avalanche breakdown between the substrate and the drain, drain avalanche hot electrons (DAHEs) are generated by applying a relatively low voltage and are injected into a floating gate, to thereby change a threshold voltage and perform writing. Thus, it is considered that the P-channel non-volatile EPROM is suitable for the memory for trimming the bleeder resistor.
The structure of a conventional P-channel non-volatile EPROM for writing information with the use of hot carriers is described below with reference to a cross-sectional view illustrated in FIG. 3.
In FIG. 3, an N-type well 11 is formed along one principal surface of a P-type semiconductor substrate 10 in which element isolation regions 12 are selectively formed. Impurities having P-type conductivity are heavily diffused in the N-type well 11, thereby forming a source region 13 and a drain region 14. On a gate oxide film 15, a floating gate 16 is formed above the substrate in which the source region 13 and the drain region 14 are formed.
A control gate 18 is formed above the floating gate 16 through the intermediation of a second insulating film 17, thereby constituting a conventional non-volatile EPROM.
The structure of electrode wiring and other members in subsequent processes (metal wiring and protective film) is similar to that of a general semiconductor device. The detailed description thereof is therefore omitted.
Next, a method of operating the conventional P-channel non-volatile EPROM is described.
In writing data, a voltage is applied between the source and the drain and to the control gate so as to generate hot carriers, and hot electrons are injected into the floating gate, to thereby fluctuate a threshold voltage. Data before and after the threshold voltage fluctuation is associated with “0” or “1”.
In reading data, a potential is applied between the source and the drain, and a current corresponding to a threshold which differs depending on the presence or absence of writing is monitored, to thereby perform determination of “0” or “1”.
FIG. 4 schematically illustrates the state of each of a source potential Vs, a drain potential Vd, a control gate potential Vcg, a floating gate potential Vfg, a threshold voltage variation ΔVth, and a difference Vfg−Vth(0) between the floating gate potential Vfg and an initial threshold voltage Vth(0) at the time of data writing in the conventional P-channel EPROM.
As illustrated in FIG. 4, the threshold voltage variation ΔVth caused by writing tends to be less written and saturated with time.
The reason is described below. In the case of a P-channel non-volatile EPROM, the floating gate potential Vfg decreases when hot electrons are injected into the floating gate in writing, and thus the threshold to be monitored fluctuates. When the capacitance of a capacitor formed by the gate oxide film 15 is represented by C1, the capacitance of a capacitor formed by the second insulating film 17 is represented by C2, and the quantity of electric charge of the injected hot electrons is represented by Q, the potential of the floating gate is expressed by expression 1 below.
                    Vfg        =                                                            C                ⁢                                                                  ⁢                1                                                              C                  ⁢                                                                          ⁢                  1                                +                                  C                  ⁢                                                                          ⁢                  2                                                      ⁢            Vcg                    +                      Q                                          C                ⁢                                                                  ⁢                1                            +                              C                ⁢                                                                  ⁢                2                                                                        (                  Ex          .                                          ⁢          1                )            
In the expression 1 above, it is understood that Q<0 is established because hot electrons are injected into the floating gate in writing and hence the potential of the floating gate decreases in writing. Next, FIG. 5 schematically shows the dependence of DAHEs on the floating gate potential Vfg. DAHEs, which are used for writing in a P-channel EPROM, are generated by avalanche breakdown caused by an electric field between a pinch-off point and the drain at the time of saturated operation. The amount of generated DAHEs therefore depends on the electric field between the pinch-off point and the drain. When the initial threshold voltage Vth(0), the control gate potential Vcg, and the drain voltage Vd are constant, as shown in FIG. 5, the electric field between the pinch-off point and the drain becomes larger as the floating gate potential Vfg becomes closer to the initial threshold voltage Vth(0), and hence the amount of generated DAHEs becomes larger. However, as illustrated in FIG. 4, the floating gate potential Vfg decreases with time to increase the difference Vfg−Vth(0) between the floating gate potential Vfg and the initial threshold voltage Vth(0). When the difference Vfg−Vth(0) increases, the pinch-off point moves in a direction of weakening the electric field between the pinch-off point and the drain as shown in FIG. 5. Thus, the amount of generated DAHEs becomes smaller to deteriorate write characteristics.
Because of the above-mentioned reason, the amount of generated DAHEs becomes smaller with time, and the amount of writing is saturated.
At present, one of the problems inherent in the conventional non-volatile EPROM is erroneous writing, where data is rewritten because the threshold fluctuates when reading is repeatedly performed.
One method for preventing rewriting of data caused by such erroneous writing is a method for preventing rewriting of data by setting a deep threshold before writing so as to enlarge a memory window. In the case of preventing rewriting of data by this method, it is necessary to increase the amount of writing in order to enlarge the memory window. In the conventional non-volatile EPROM, however, the amount of writing decreases with time because of the above-mentioned reason. Thus, it has been demanded to increase the amount of writing.
Further, Japanese Patent Application Laid-open No. 2001-257324 proposes a method of preventing rewriting of data caused by erroneous writing without increasing the amount of writing. FIG. 6 is a schematic diagram illustrating the outline of the invention described in Japanese Published Patent Application 2001-257324. In Japanese Published Patent Application 2001-257324, a semiconductor integrated circuit includes non-volatile memories (PM1 and PM2 of FIG. 6) having different threshold voltages, and two read transistors (DM1 and DM2 of FIG. 6) whose gate voltages correspond to respective floating gates of the two non-volatile memories and which are designed to detect the switch state based on the state of electric charges of the non-volatile memories. The use of the two read transistors can prevent a current from flowing through the non-volatile memories in reading, to thereby prevent rewriting of data caused by erroneous writing.
Each memory cell, however, needs to have two non-volatile semiconductor memories having different thresholds as well as two read transistors in Japanese Published Patent Application 2001-257324 although the method can prevent the threshold fluctuation caused by erroneous writing. The area of the memory cell thus becomes larger, which is disadvantageous in terms of cost. Accordingly it is beneficial to provide a non-volatile semiconductor memory device capable of improving the amount of writing as a method for preventing rewriting of data caused by erroneous writing without the need of a complicated memory cell.
USPTO Backgrounds
USPTO Backgrounds