1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a multi-chip package.
2. Description of the Related Art
The demand for high performance and miniaturization of electronic products has led to the development of various technologies for stacked packages. The term ‘stack’ in the semiconductor industry means piling up two or more semiconductor chips or packages vertically. For example, semiconductor memory device stacked packages may have two or more times the memory capacity as those realized through traditional semiconductor integration processes. In addition, since the stacked package has advantages in terms of packaging density, packaging efficiency, packaging area, as well as increased memory capacity, research and development on stacked packages continues to accelerate.
Stacked packages may be seen as the result of the practical application of three-dimensional (3D) structure technology, in which a plurality of memory chips are stacked to improve integration density. Due to the demand for highly integrated, high performance, high capacity semiconductor devices, multi-channel semiconductor memory devices have been developed in a stacked package form.
Since multi-channel semiconductor memory devices have a plurality of stacked memory chips (or channel memories), a through chip via (e.g., a through silicon via) may be used for conductive lines between the memory chips. When a multiple channels are formed by stacking the memory chips, each of the memory chips may include a data transmission/reception circuit to transmit/receive data, wherein each memory chip has its own channel. In other words, one data transmission/reception circuit is required for each of the memory chips to transmit/receive data. However, when a plurality of memory chips are designed to include a single data transmission/reception circuit for each channel, it is not efficient because they have to be designed differently from each other. Thus, the memory chips must have a plurality of data transmission/reception circuits for each channel. For example, when four channels and four memory chips are included, each of the memory chips may include four data transmission/reception circuits. For this reason, a number of transmission/reception circuits may be unnecessarily coupled with a single transmission line. FIG. 1 shows the concerns described above.
Referring to FIG. 1, the conventional multi-chip package may include a single master chip 110 and a plurality of slave chips 120, 130, 140 and 150.
The multi-chip package includes four channels. The master chip 110 includes four data transmission/reception circuits corresponding to the four channels to transmit data to a plurality of slave chips. Each of the slave chips 120, 130, 140 and 150 includes four data transmission/reception circuits. Although each of the slave chips 120, 130, 140 and 150 includes four data transmission/reception circuits, only one data transmission/reception circuit is to be enabled and used for each slave chip under actual conditions. Each of the slave chips 120, 130, 140 and 150 may select and use one transmission/reception circuit among the four data transmission/reception circuits based on a slice (or chip) identification (ID, not shown). In other words, although each of the slave chips 120, 130, 140 and 150 includes four data transmission/reception circuits, and the total number of the data transmission/reception circuits is 16, four data transmission/reception circuits are to be used under actual conditions. Therefore, the amount of circuit area unnecessarily occupied by the data transmission/reception circuits increases, and the amount of power consumption also increases. In addition, the loading of signal lines for transmitting data, which are coupled with each other by through-silicon-vias (TSVs) may be increased. The loading of signal lines may cause delays in transmitting data or voltage drops in the internal voltage supply.
USPTO Backgrounds
USPTO Backgrounds