Computing systems have increasingly required faster computing memory to transmit billions of instructions to and from a central processing unit (“CPU”) promptly for execution. These CPUs have dramatically become faster and more complex in the computing industry. To reduce access times by the CPU to data stored in computer memory, some conventional approaches have implemented the use of processor registers to provide quick access to commonly used values within the CPU. At least one approach implements an array of processor registers to meet the demand of increasing memory requirements.
In some conventional approaches, computing systems have become more complex and costly with the increasing need for multiple ports to share data across multiple processors. In some other conventional approaches, direct memory access (“DMA”) controllers have been implemented to ameliorate computing memory traffic independent of the CPU. This approach, however, does not provide optimal system performance since conventional approaches use multiple integrated circuits, which therefore might increase system latency. Alternatively, computing memory is used for a number of electronic devices using offline applications during which power is often absent. As electronic devices and CPUs become increasingly smaller and faster, requirements for computing memories with reduced cost, size, and power demands are also desirable. However, conventional approaches fail to fulfill these requirements, and data is often loss when power is removed. Typically, when power is lost, data is also lost in volatile systems.
Thus, a solution is needed to provide for a nonvolatile memory having multiple ports in which to access memory locations, without the limitations of conventional techniques.
USPTO Backgrounds
USPTO Backgrounds