In JP-A-H9-172187 discloses a structure of a silicon carbide (SiC) substrate 200 having a trench 201, wherein a silicon carbide epitaxial layer 202 is formed on an inside surface of the trench 200. Here, in order that electric field is inhibited from being concentrated on side walls of the trench 201, the substrate 200 has a main surface of a (0001) plane and the trench 201 has side walls of a (1-100) plane, as shown in FIG. 28.
In actual manufacturing, as shown in FIGS. 29A, 29B, when the epitaxial layer 202 grows from the (1-100) planes within the trench 201, a facet is formed in a vicinity of the surface. A defect cannot thereby be prevented. Namely, imbedded epitaxial growth on a wafer having an off-axis of a <1-100> direction develops the (0001) facet downstream of the <1-100> direction. This exhibits an asymmetric cross sectional shape of the epitaxial layer 202 that is deposited within the trench 201, and causes the facet to have a rugged surface, resulting in being apt to develop a defect on the facet.
When the above substrate is applied to a trench JFET, or a trench MOSFET, a facet is formed on a channel layer. This increases on-resistance due to lowered mobility and leak electric current, or varies a threshold value.
Incidentally, (1-100) or <1-100> is equivalent to (0 1 00) or <0 1 00> that is usually described in an expression method for a crystallographic plane or direction. Namely, “−n” in an index reads “ n.”
USPTO Backgrounds
USPTO Backgrounds