1. Field of Invention
Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device and a method of manufacturing the same.
2. Description of Related Art
A non-volatile memory device may retain data stored therein without a power supply. As two-dimensional memory devices having memory cells fabricated in the form of a single layer on silicon substrates reaches a limit in increasing the degree of integration, there are proposals of three-dimensional (3D) structured non-volatile memory devices that have memory cells vertically stacked on silicon substrates.
The structure of a conventional 3-D non-volatile memory device is described hereinafter in detail with reference to FIG. 1.
FIG. 1 is a cross-sectional view of a conventional 3-D non-volatile memory device. FIG. 1 illustrates a region in which memory cells are stacked.
As show in FIG. 1, the conventional 3-D non-volatile memory device may include vertical channel layers CH that protrude from a substrate (not shown) and a plurality of memory cells that are stacked along the vertical channel layers CH.
A method of forming the memory cells is described briefly hereinafter. First, sacrificial layers and interlayer insulating layers 11 are alternately formed and etched to form channel holes. Subsequently, the vertical channel layers CH are formed in the channel holes, and the sacrificial layers and the interlayer insulating layers 11 are etched to form slits between the vertical channel layers CH. Subsequently, the sacrificial layers exposed on inner walls of the slits are removed to form open regions, and a memory layer 12 is formed along the surface of the open regions. Here, the memory layer 12 comprises a charge blocking layer, a charge trap layer and a tunnel insulating layer, each of which is formed by a deposition process. Subsequently, the open regions in which the memory layer 12 is formed are filled with conductive layers 13. As a result, a plurality of memory cells are stacked over the substrate.
However, according to the known method of forming the memory cells as described above, since the open regions are filled with the conductive layers 13 after the memory layer 12 is formed along the inner surfaces of the open regions, the open regions are to be formed with ample spaces and thus the height of stacked layers may be increased, which may make it difficult to improve an integration degree of a memory device. In addition, since an insulating layer deposited by chemical vapor deposition is used as a charge blocking layer, the charge blocking layer may have low quality, thus deteriorating characteristics of the memory device.
USPTO Backgrounds
USPTO Backgrounds