The present invention is directed to semiconductor integrated circuits and, more particularly, to a semiconductor die having on-die decoupling capacitors.
Semiconductor processor devices include a variety of types of high-speed (high frequency) interfaces such as Serializer/Deserializer (SerDes) lanes, Peripheral Component Interconnect Express (PCIe) buses, Media Independent Interfaces (MII), and input/output (I/O) interfaces such as RapidIO. Many of these high-speed interfaces are provided with on-die decoupling capacitors (bypass capacitors) to reduce noise on signal lines and power supply lines. Often, a separate, dedicated decoupling capacitor is provided for each high-speed interface of the design in order to avoid incompatibility of connecting the interfaces to a common decoupling capacitor.
While there may be many high-speed interfaces in a semiconductor processor device, in variants (i.e., different device personalities) of the device, several different interfaces may be unused. For example, when packaging one variant of the device, a first interface may be used but a second is unused, while in another variant, the first interface is unused but the second is used. The provision of unused decoupling capacitors represents a waste of die area and unnecessary cost, which it is desirable to avoid.
USPTO Backgrounds
USPTO Backgrounds