1. Field of the Invention
The present invention relates to solid-state imaging devices, and more particularly, to a solid-state imaging device, such as a complementary metal-oxide semiconductor (CMOS) image sensor including amplifying elements for respective pixels.
2. Description of the Related Art
Solid-state imaging devices need a great number of pixels arranged in a two-dimensional array fashion in a pixel array area. For example, in known CMOS image sensors, each element of a pixel is disposed in a well and the well is electrically fixed to the periphery of the pixel array area.
FIG. 12 is a circuit diagram showing an example of the arrangement of a unit pixel 100. As shown in FIG. 12, the unit pixel 100 includes a photoelectric conversion portion 101, a transfer transistor 102, an amplifying transistor 103, a reset transistor 104, and a selection transistor 105. The anode of the photoelectric conversion portion 101 is grounded. The photoelectric conversion portion 101 photo-electrically converts incident light into an electric charge of an electron (or a positive hole) corresponding to the amount of the incident light to be accumulated. The source of the transfer transistor 102 is connected to the cathode of the photoelectric conversion portion 101, and the gate of the transfer transistor 102 is connected to a transfer signal wire 106. Also, the drain of the transfer transistor 102 is connected to a gate input 107 of the amplifying transistor 103. When the potential of the transfer signal wire 106 becomes the potential of a power supply wire 108 (hereinafter, referred to as an “H” level), the transfer transistor 102 transfers the electric charge accumulated in the photoelectric conversion portion 101 to the gate input 107 of the amplifying transistor 103.
The gate of the amplifying transistor 103 is connected to the gate input 107, and the drain of the amplifying transistor 103 is connected to the power supply wire 108. Also, the source of the amplifying transistor 103 is connected to the drain of the selection transistor 105. The amplifying transistor 103 outputs a voltage corresponding to the electric charge that is transferred by the transfer transistor 102 from the photoelectric conversion portion 101 to the gate input 107 to the source side. The source of the reset transistor 104 is connected to the gate input 107 of the amplifying transistor 103, and the drain of the reset transistor 104 is connected to the power supply wire 108. Also, the gate of the reset transistor 104 is connected to a reset signal wire 109. When the potential of the reset signal wire 109 becomes the “H” level, the potential of the gate input 107 is reset to the potential of the power supply wire 108, which is a power supply voltage.
The drain of the selection transistor 105 is connected to the source of the amplifying transistor 103, and the gate of the selection transistor 105 is connected to a selection signal wire 110. Also, the source of the selection transistor 105 is connected to a pixel output line 111. When the potential of the selection signal wire 110 becomes the “H” level, the selection transistor 105 is turned on and allows conduction between the source of the amplifying transistor 103 and the pixel output line 111. Pixels for respective rows are connected to the pixel output line 111 in parallel. The gate of a transistor 112 connected at an end of the pixel output line 111 is biased at a constant voltage by a bias power supply 113, and the transistor 112 operates as a constant current source. When the selection transistor 105 of a pixel is turned on, the amplifying transistor 103 and the constant-current transistor 102 function as a source follower. Thus, a voltage that has a predetermined potential difference from the potential of the gate input 107 of the amplifying transistor 103 is output to the pixel output line 111.
FIG. 13 is a plan pattern view showing a pixel structure of the unit pixel 100. Referring to FIG. 13, a gate electrode 201 is disposed between a photoelectric conversion region (activation region) 202 of the photoelectric conversion portion 101 and an activation region 203, and constitutes the transfer transistor 102. The Activation region 203 is a drain region of the transfer transistor 102, a source region of the reset transistor 104, and the gate input 107 of the amplifying transistor 103. A gate electrode 204 is disposed between the activation region 203 and an activation region 205, and constitutes the reset transistor 104. The activation region 205 is a drain region of the reset transistor 104 and a drain region of the amplifying transistor 103.
A gate electrode 206 is disposed between the activation region 205 and an activation region 207, and constitutes the amplifying transistor 103. The activation region 207 is a source region of the amplifying transistor 103 and a drain region of the selection transistor 105. A gate electrode 208 is disposed between the activation region 207 and an activation region 209, and constitutes the selection transistor 105. The activation region 209 is a source region of the selection transistor 105, and is electrically connected to the pixel output line 111, which is a metallic wire, at a contact part 210.
The gate electrodes 201, 204, 206, and 208 are, for example, polysilicon electrodes. The activation region 203 and the gate electrode 206 are electrically connected to each other via a metallic wire 213 at contact parts 211 and 212. The activation region 205 is connected to a power supply via a metallic line (not shown) at a contact part 214. Although wires extending in the row direction (the lateral direction in the drawing), that is, the transfer signal wire 106, the reset signal wire 109, and the selection signal wire 110 are not illustrated in FIG. 13, the gate electrodes 201, 204, and 208 are electrically connected to the transfer signal wire 106, the reset signal wire 109, and the selection signal wire 110, respectively.
Although not illustrated in FIG. 13, with the pixel structure of the unit pixel 100 as described above, the base of each of the transistors 102, 103, 104, and 105 is connected to a P-well. Also, the photoelectric conversion portion 101 has an arrangement in which an N-type impurity-doped region is covered by a P-type impurity region formed above thereof and a P-well. Such P-regions have the same potential and are at a ground level. A well contact part and a ground wire for fixing the P-well at the ground level have been disposed at the periphery of the pixel array area. This is because that a well contact part is not disposed inside a pixel array area in order to extremely reduce the size of a pixel although a well contact part is normally disposed near each transistor.
However, for the structure in which a well contact part is disposed only at the periphery of the pixel array area, if an increase in the number of pixels increases the dimensions of P-wells of a pixel array area, it is difficult to fix the intermediate portion of the P-wells at a ground potential. Thus, the following problems occur.                A transistor has a different threshold between the center and periphery of a pixel array area.        Since a photoelectric conversion portion of a type in which an N-type impurity region is covered by a P-type impurity region exhibits a different potential level of the P-type impurity region between the center and periphery of the pixel array area, a difference between the center and periphery of the pixel array area also appears in the saturation level.        When each pixel is driven, a variation in the potential of a doped layer connected to a pixel output line and the like in the pixel being driven causes a variation in a potential itself of a well due to a coupling capacitance of the doped layer and the well. Thus, when all the pixels are driven at the same time or when the number of pixels is large, the variation in the well potential due to the coupling capacitance is not negligible at a portion near the center of the pixel array area where pressure of the well potential is electrically weak.        
In order to electrically fix the well potential further firmly and to solve the above problems, a solid-state imaging device enabling well contact for each pixel has been suggested (for example, see Japanese Unexamined Patent Application Publication No. 2001-332714). FIG. 14 is a plan pattern view showing a pixel structure providing a well contact part for each pixel. In FIG. 14, parts equivalent to those in FIG. 13 are represented by the same reference numerals.
As shown in FIG. 14, cutting off part of the activation region 202, which is a photoelectric conversion region, of the unit pixel 100 ensures an activation region 221 for achieving well contact. The activation region 221, which is a well contact part, is electrically connected to a metallic wire 222 that supplies a ground potential and that extends in the vertical direction (the longitudinal direction in the drawing) at a contact part 223. The other parts are similar to those in FIG. 13.
FIG. 15 is a sectional view taken along the line XV-XV of FIG. 14. In FIG. 15, parts equivalent to those in FIG. 14 are represented by the same reference numerals. In the example shown in FIG. 15, a P-well 302 is disposed in an N-substrate 301, and the photoelectric conversion portion 101 and the transistors 102 to 105 of the pixel are disposed in the P-well 302. An N-region 303 is an activation region (the activation region 203 in FIG. 14) connected to the gate electrode 206 of the amplifying transistor 103 via the metallic wire 213 at the contact part 211.
The activation region 202 includes an N-type impurity region 304, a P+ region 305 near the surface of the N-type impurity region 304, and a P-well 302 peripheral to the N-type impurity region 304. A P+ region 306 is connected to the metallic wire 222 via the doped layer and the contact part 223 in that order, and fixes the potential of the P-well 302 at the ground potential via the metallic wire 222. Element separation regions 307 are disposed between a photoelectric conversion portion, transistors, and the well contact part (activation region) 221 so as to electrically separate the elements from each other.
However, as described above, in order to provide the activation region 221 and the element separation regions 307 for achieving well contact for every pixel without changing the size of a pixel, the dimensions of an activation region used for a photoelectric conversion portion and transistors must be reduced. Thus, the characteristics, more specifically, the saturation level and the sensitivity of a pixel are reduced by a reduction in the dimensions of the activation region. In contrast, if the activation region 221 and the element separation regions 307 are provided without changing the dimensions of an activation region, the size of a pixel is increased due to the dimensions of the activation region.
Although a solid-state imaging device having an arrangement in which the P-well 302 is disposed in the N-substrate 301 and each element is disposed in the P-well 302 has been described above, a similar problem occurs in a solid-state imaging device having an impurity having an opposite conductivity type.
USPTO Backgrounds
USPTO Backgrounds