Electronic devices, such as telephone equipment and computer equipment, that transceive information via a wireline source include line drivers. Line drivers allow the electronic devices to source information on relatively low impedance wirelines, such as twisted pair copper wire. Typically, line drivers of the electronic devices are connected to a shared bus as shown in FIG. 4. As shown, a plurality of line drivers are coupled to a shared bus. Each of the line drivers, as shown in FIG. 1, includes a p-channel field effect transistor (FET) and an n-channel FET. The p-channel FET includes a gate node (G), a source node (S), a drain node (D), and an intrinsic diode. The n-channel FET also includes a gate node (G), a source node (S), a drain node (D), and an intrinsic diode.
Referring back to FIG. 4, any one of the plurality of line drivers may provide, at a given time, information on the shared bus. For example, if line driver 1 is providing a logic "1" to the share bus, the p-channel FET is "on", while the n-channel FET is "off", thus the shared bus will be pulled to the supply voltage (V.sub.DD). Conversely, when line driver 1 is providing a logic "0", the n-channel FET is "on" while the p-channel FET is "off", thus the shared bus will be pulled to the return supply (V.sub.SS). While line driver 1 is providing information on to the shared bus, the other line drivers will be inactivated until their turn to provide information on to the shared bus.
The sharing of the bus works well until one of the line drivers fail or has the supply voltage V.sub.DD removed. When this happens, the intrinsic diode of the P-channel FET will be forward biased whenever one of the other line drivers is attempting to pull up the shared bus. Thus, clamping the shared bus to a maximum voltage of approximately 0.7 volts (typical forward bias voltage of a diode). For example, assume that line driver 1 has V.sub.DD removed, or shorted to V.sub.SS, the intrinsic diode of the p-channel FET will be forward biased when either line driver 2 or 3 attempts to provide a logic "1" on the shared bus.
FIGS. 2 and 3 each illustrate a line driver that prevents the above problem. FIG. 2 illustrates a two n-channel FET inverter. The top FET is driven by the inverse signal that drives the bottom FET. This embodiment prevents the above mentioned forward biasing of the p-channel's intrinsic diode when the supply voltage is shorted, or removed, however, it limits the output voltage swing from approximately V.sub.SS to approximately (V.sub.DD -V.sub.GS). The V.sub.GS term is introduced because the top n-channel FET must have a gate-source voltage (V.sub.GS) in order for it to be "on", thus pulling the output up only to V.sub.DD -V.sub.GS.
FIG. 3 illustrates a three FET line driver that includes a P-channel FET coupled in series with two n-channel transistors. When V.sub.DD is removed, or shorted to ground, an intrinsic diode of the second n-channel FET prevents the intrinsic diode of p-channel FET from being forward biased. As with the solution of FIG. 2, this embodiment limits its output voltage swing from approximately V.sub.SS to approximately (V.sub.DD -V.sub.GS) for the same reason.
In many applications, the less than maximum voltage swing produced by the solutions shown in FIG. 2 and FIG. 3 is not of great concern when supply voltages are relatively high, i.e., greater than 5 volts. As supply voltages are being reduced to meet the demand for reduced power consumption, limiting the output swing of line drivers is becoming of greater importance. For example, if the supply voltage V.sub.DD is 3 volts, a 1 volt V.sub.GS drop limits the maximum output voltage to 2 volts, which may be insufficient in many circuits to represent a logic "1". Therefore, a need exists for a line driver which provides a maximum output voltage swing while preventing reverse biasing of intrinsic diodes under failure mode, power removal, conditions.
USPTO Backgrounds
USPTO Backgrounds