1. Technical Field
The present invention relates to a signal amplifier, a bridge connection signal amplifier, a signal output device, a latch-up prevention method, and a program storage medium storing a latch-up prevention program.
2. Related Art
FIG. 5 shows an example of a conventional amplifier 100 used for connecting to a speaker. As shown in FIG. 5, the amplifier 100 is configured including an inverting amplification circuit 102, an overcurrent detection circuit 104 and a controller 106. The inverting amplification circuit 102 includes a power supply terminal 102A serving as a first voltage terminal connected to a power supply line VDD applied with a positive driving voltage, a ground terminal 102B serving as a second voltage terminal connected to a ground line GND applied with ground voltage, an inverting input terminal 102C to which a signal line 103 is connected, a non-inverting input terminal 102D to which a reference voltage (ground voltage in this example) is applied, an output terminal 102E, and a control terminal 102F. A resistance element R2 is provided at the signal line 103, and the inverting input terminal 102C is connected through the resistance element R2 to an input terminal 100A of the amplifier 100. The output terminal 102E is connected to the inverting input terminal 102C though a resistance element R1, and is also connected to the positive input terminal of a speaker 108 through a cable 109 leading from an output terminal 100B of the amplifier 100. The negative input terminal of the speaker 108 is grounded.
The overcurrent detection circuit 104 includes an input terminal 104A and an output terminal 104B. The input terminal 104A is connected to the output terminal 102E, and the overcurrent detection circuit 104 detects overcurrent when overcurrent has been input from the inverting amplification circuit 102, and outputs an overcurrent detection signal from the output terminal 104B. In the following explanation, situations in which power is introduced to the amplifier 100 and no overcurrent is generated are referred to as a “normal operation”.
The controller 106 is a computer including a central processing unit (CPU) that controls the amplifier 100 overall by executing processing of a specific program, a read only memory (ROM) that is a storage medium pre-stored with a control program for controlling operation of the amplifier 100 and with various parameters, and a random access memory (RAM) that is a storage medium employed for example as a work area used during execution of the various programs.
The controller 106 includes an input terminal 106A and an output terminal 106B. The input terminal 106A is connected to the output terminal 104B of the overcurrent detection circuit 104, and the output terminal 106B is connected to a control terminal 102F of the inverting amplification circuit 102.
FIG. 6 is a diagram showing main configuration of the inverting amplification circuit 102. As shown in FIG. 6, the inverting amplification circuit 102 includes a differential stage 110, an off-set stage 112, and an output stage 114. The differential stage 110 includes a power supply terminal 110A connected to the power supply line VDD through the power supply terminal 102A shown in FIG. 5, and a ground terminal 110B connected to the ground line GND through the ground terminal 102B shown in FIG. 5, the inverting input terminal 102C, and the non-inverting input terminal 102D. The inverting amplification circuit 102 generates and outputs to the following stage of the off-set stage 112 a differential signal indicating the potential difference between the signal input to the inverting input terminal 102C and the signal input to the non-inverting input terminal 102D.
The off-set stage 112 includes a power supply terminal 112A connected to the power supply line VDD through the power supply terminal 102A shown in FIG. 5, a ground terminal 112B connected to the ground line GND through the ground terminal 102B shown in FIG. 5, and is connected to the differential stage 110 so as to receive the differential signal. The off-set stage 112 generates a differential signal of the input differential signal from which an off-set voltage component occurring in the inverting amplification circuit 102 has been removed. The off-set stage 112 is equipped with an output terminal 112A that is a negative output terminal when in normal operation and outputs a positive differential signal obtained by removing the off-set voltage component from the input differential signal, and an output terminal 112B that is a positive output terminal when in normal operation and outputs a negative differential signal obtained by removing the off-set voltage component from the input differential signal.
The output stage 114 includes the output terminal 102E, P channel MOS field effect transistors (referred to below as PMOS transistors) 116, 118 and N channel MOS field effect transistors (referred to below as NMOS transistors) 120, 122.
The PMOS transistor 116 is a first switching element to be protected (protected first switching element), and is equipped with a gate terminal connected to the output terminal 112A, a drain terminal connected to the output terminal 102E, and a source terminal connected to the power supply line VDD through the power supply terminal 102A. The PMOS transistor 116 is configured such that when a voltage of the magnitude of the power supply voltage or greater has been applied to the gate terminal, the conducting state between the source terminal and the drain terminal in normal operation changes to a non-conducting state.
The PMOS transistor 118 is a switching element for changing the conducting state between the source terminal and the drain terminal of the PMOS transistor 116 to the non-conducting state when an overcurrent has been detected by the overcurrent detection circuit 104. The PMOS transistor 118 is equipped with a source terminal connected to the power supply line VDD through the power supply terminal 102A, a drain terminal connected to the gate terminal of the PMOS transistor 116, and a gate terminal connected to the output terminal 106B of the controller 106 through the control terminal 102F.
The NMOS transistor 120 is a second switching element to be protected (protected second switching element), and is equipped with a gate terminal connected to the ground terminal 112B, a drain terminal connected to the output terminal 102E, and a source terminal connected to ground line GND through the ground terminal 102B. The NMOS transistor 120 is configured such that the conducting state between the source terminal and the drain terminal of the NMOS transistor 120 in the normal operation changes to a non-conducting state when a voltage of the magnitude of the ground voltage or lower has been applied to the gate terminal.
The NMOS transistor 122 is a switching element for changing the conducting state between the source terminal and the drain terminal of the NMOS transistor 120 to the non-conducting state when an overcurrent has been detected by the overcurrent detection circuit 104. The NMOS transistor 122 is equipped with a source terminal connected ground line GND through the ground terminal 102B, a drain terminal connected to the gate terminal of the NMOS transistor 122, and a gate terminal connected to the output terminal 106B of the controller 106 through the control terminal 102F.
When an overcurrent has been output from the inverting amplification circuit 102 in the amplifier 100 configured as described above, the overcurrent is detected by the overcurrent detection circuit 104 and an overcurrent detection signal is output to the controller 106. The amplifier is thereby powered down (driving of the amplifier is halted) and damage due to the overcurrent to the PMOS transistor 116 or the NMOS transistor 120 is prevented (see for example the Japanese Patent Application Laid-Open (JP-A) No. 2000-174565).
However, in the amplifier 100 configured as described above, when the inductance component of the equipment connected to the output terminal 100B (in FIG. 5 this refers to the parasitic inductance component of the cable 109) is a specific magnitude or greater and overcurrent flowing in the inverting amplification circuit 102 is instantly interrupted (powered down), a surge current caused by an electromagnetic inductance effect due to the interruption occurs. This surge current sometimes causes the PMOS transistor 116 and the NMOS transistor 120 to latch-up, resulting in damage to the PMOS transistor 116 and the NMOS transistor 120. Namely, a minus surge current (overcurrent in the power supply line VDD) may occur when the power supply line VDD has been shorted to the ground side, or a plus surge current (overcurrent in the ground line GND) may occur when the ground line GND has been shorted to the power supply side, both thereby causing the PMOS transistor 116 and the NMOS transistor 120 to latch-up, and causing damage to the PMOS transistor 116 and the NMOS transistor 120.
USPTO Backgrounds
USPTO Backgrounds