1. Field of the Invention
The present invention relates to debug and testing of computer systems, specifically, for observing and exposing values for link interconnect technology.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances and demand for increased processor and memory performance, the debugging and testing integrated devices have significantly become more complex. Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip. As the complexity of the ICs increase, so does the cost and complexity of verifying/debugging functionality and electrically testing the individual IC and the systems in which they are employed. Testing and manufacturing costs and design complexity increase dramatically because of new manufacturing processes and new interconnect technologies.
Present solutions to debug consist of requiring additional component pins, are pre-emptive and disruptive to the dynamic operation of the integrated devices and system since they require interruption of normal data traffic or operation mode changes of the integrated devices.
USPTO Backgrounds
USPTO Backgrounds