The present invention relates to a prescaler for use in a PLL (Phase Locked Loop) circuit, which allows the frequency of an output signal to coincide with a preset frequency.
PLL circuits are commonly used in mobile communication devices such as automobile telephones and portable telephones. The operational frequency of such a PLL circuit is continually increasing. The rise in the operational frequency increases the power dissipation of the PLL circuit. One way to reduce the power dissipation of a PLL circuit is to decrease the power dissipation of a prescaler used in the PLL circuit.
FIG. 1 shows a conventional prescaler 50 used in a PLL circuit. A voltage controlled oscillator (not shown) is provided at a preceding stage of the prescaler 50. A buffer circuit 51 sends a pulse signal f.sub.VCO from the oscillator to individual flip-flop circuits FF1 to FF3 as a clock signal CK. An output signal XQ of the flip-flop circuit FF1 is input as data D to the flip-flop circuit FF2. The output signal Q of the flip-flop circuit FF2 is input as data D to the flip-flop circuit FF3. The output signals Q of the flip-flop circuits FF2 and FF3 are both input to an OR gate 52a. The output signal of the OR gate 52a is input as data D to the flip-flop circuit FF1.
The output signal XQ of the flip-flop circuit FF1 is also input as the clock signal CK to a flip-flop circuit FFL2. The output signal XQ of the flip-flop circuit FFL2 is fed back as data D to FFL1. The output signal Q of the flip-flop circuit FFL1 is input as the clock signal CK to a flip-flop circuit FFL2. The output signal XQ of the flip-flop circuit FFL2 is fed back as data D to FFL2. The signal Q from the flip-flop circuit FFL2 is sent out as a frequency-divided signal P.sub.out.
The signals Q from the flip-flop circuits FFL1 and FFL2 are both input to an OR gate 52b. The OR gate 52b also receives an externally supplied module control signal MD for controlling the operation of the prescaler 50. The output signal of the OR gate 52b is input as a control signal M to the flip-flop circuit FF3. When the control signal M has an L level, the flip-flop circuit FF3 functions normally, whereas when the control signal M has an H level, the flip-flop circuit FF3 fixes the output signal Q to an L level.
The operation of the prescaler 50 will be discussed below with reference to FIG. 2.
While the pulse signal f.sub.VCO from the oscillator is input to the prescaler 50, the flip-flop circuits FF1 and FF2 operate so that the output signal XQ, which is the pulse signal f.sub.VCO frequency-divided by four, is output from the flip-flop circuit FF1. The output signal Q of the flip-flop circuit FF2 is delayed in phase by a 1/4 period of the output signal XQ of the flip-flop circuit FF1 or by one period of the pulse signal f.sub.VCO.
The output signal Q of the flip-flop circuit FFL1 is set to a signal which is the output signal XQ of the flip-flop circuit FF1 frequency-divided by two or the pulse signal f.sub.VCO frequency-divided by 8. The output signal Q of the flip-flop circuit FFL2 is set to a signal which is the pulse signal f.sub.VCO frequency-divided by 16.
When the module control signal MD is at an L level, the control signal M of the OR gate 52b is determined based on the output signals Q of the flip-flop circuits FFL1 and FFL2. One of the output signals Q from the flip-flop circuits FFL1 and FFL2 is set to an H level since the prescaler 50 has started counting the pulse signal f.sub.VCO and until the prescaler 50 counts twelve pulses of the pulse signal f.sub.VCO. Having one of the Q outputs of FFL1 and FFL2 high sets the control signal M to the H level. With the control signal M set to the H level, the signal Q from the flip-flop circuit FF3 is fixed to the L level.
When twelve pulses of the pulse signal f.sub.VCO are counted, the output signals Q from both flip-flop circuits FFL1 and FFL2 are set to the L levels, which sets the control signal M to the L level. When the control signal M is set to the L level, the flip-flop circuit FF3 is activated. As a result, the FF3 output signal Q, which is delayed from the signal Q from the flip-flop circuit FF2 by one period of the pulse signal f.sub.VCO, is output from the flip-flop circuit FF3.
Then, the output signal XQ of the flip-flop circuit FF1 rises with a delay of one period of the pulse signal f.sub.VCO from the falling of the FF3 output signal Q.
In synchronism with the rising of the output signal XQ of the flip-flop circuit FF1, the output signals Q of the flip-flop circuits FFL1 and FFL2 rise to the H levels and the control signal M rises to the H level simultaneously. Then, the prescaler 50 starts a new counting operation.
When the module control signal MD is at the L level, as discussed above, the signal P.sub.out which is the pulse signal f.sub.VCO frequency-divided by M+1 (M=16) is output. When the module control signal MD is at the H level, on the other hand, the control signal M from the OR gate 52b is fixed to the H level, which disables the flip-flop circuit FF3 and fixes the output signal Q of the flip-flop circuit FF3 to the L level. When the module control signal MD has the H level, therefore, the signal P.sub.out which is the pulse signal f.sub.VCO frequency-divided by M (M=16) is output.
As the operational frequency of a PLL circuit is increased, the flip-flop circuits FF1-FF3 in the prescaler 50 are constructed with an ECL (Emitter Coupled Logic) circuit or the like, comprised of bipolar transistors.
As the number of stages of the flip-flop circuits FF1-FF3 connected to the buffer circuit 51 increases, therefore, the number of transistors which are driven by the buffer circuit 51 increases. The increased number of stages of the flip-flop circuits FF1-FF3 increases the line capacitances between the flip-flop circuits FF1-FF3 and the buffer circuit 51. This increased line capacitance increases the load on the buffer circuit 51 and results in increased power dissipation of the prescaler 50.
As the operational frequencies of the flip-flop circuits FF1-FF3 are high, the charge or discharge on the lines between the circuits FF1-FF3 and the buffer circuit 51 are carried out fast. Therefore, the multi-stages of the flip-flop circuits FF1-FF3 likewise raise the problems of increased power dissipation.
Accordingly, it is an object of the present invention to provide a prescaler capable of reducing power dissipation, a frequency divider which uses the prescaler, and a PLL circuit which uses the frequency divider.
USPTO Backgrounds
USPTO Backgrounds