1. Field of the Invention
The present invention relates to a rewritable nonvolatile semiconductor memory device. In particular, the present invention relates to a semiconductor memory device, which detects the number of cells having no write completion.
2. Description of the Related Art
A NAND flash memory has been developed as a nonvolatile semiconductor memory device. In the NAND flash memory, data is written in page units. Specifically, data is collectively written to a plurality of memory cells connected to a selected word line. The data write operation of the NAND flash memory is largely classified into two. One is an operation of applying a write voltage to the memory cells of a page unit, and programming the memory cells. The other is a write completion verification operation of verifying whether the write operation of the memory cells is all completed. After the write completion verification operation, it is judged whether the write operation ends. If the judgment result is pass, the write operation ends.
There has been known the following operations as a method of detecting whether write of the memory cells is completed (e.g., see Jpn. Pat. Appln. KOKAI Publications No. 2006-277786 and 2007-102942). One is a batch detection operation, and the other is a bad bit detection operation of detecting the number of bad bits. The batch detection operation presumes that all sense amplifier circuits detect a write operation completion. For this reason, long time is taken to detect the write completion. The bad bit detection operation is a detection method of permitting several bits having write incompletion (hereinafter, referred to as fail bit). Recently, an error correction code (ECC) technique is employed, and thereby, a bit error is saved; therefore, several fail bits are permitted. According to the bad bit detection operation, there is no need to wait write completion of all bits. Therefore, detection time is shortened compared with the batch detection operation. Thus, the bad bit detection operation is effective as the write completion detection method.
However, the bad bit detection operation has a need to accurately count the number of fail bits. For this reason, the bad bit detection operation has a problem of requiring time to count the fail bits. Therefore, it is desired to provide a semiconductor memory device, which can detect fail bits at high speed.
USPTO Backgrounds
USPTO Backgrounds