Due to the high costs associated with developing an integrated circuit (IC), first-pass success in IC fabrication can be critical to business success and profit margins. Therefore, it can be beneficial for engineers to verify the functionality of an IC design before semiconductor fabrication or manufacturing. For example, many ICs may include complex circuit components, signal routings and logic blocks that should be debugged or verified to function substantially as expected prior to fabrication of the IC. Functional verification of the IC design may include verifying that the design conforms to certain specification parameters as well as certain functional parameters. Functional verification may include generating Register Transfer Level (RTL) representations of various circuit elements of the IC design that represent the functionality of the circuit element for several clock cycles of operation of the IC. Generating and verifying the RTL representations can be a difficult and time consuming task.
Further, many modern ICs may include multiple communication interfaces (e.g., Ethernet, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), or other interfaces that are not easily decoded from viewing a signal timing waveform. Thus, it can be difficult to verify that correct stimulus signals have been received (e.g., via the communication interfaces) by a design under test (DUT) and that correct responses signals have been sent from the DUT (e.g., via the communication interfaces).
USPTO Backgrounds
USPTO Backgrounds