1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to preventing data loss of a nonvolatile memory device, and more particularly, to a nonvolatile memory that can represent bit information of multiple pages using one memory cell.
2. Description of the Related Art
In general, nonvolatile memories are widely used as a storage device to store and process data in embedded systems, including appliance devices, communication devices, and set-top boxes.
Flash memory, a commonly used nonvolatile memory, can delete and rewrite data electrically, and can be easily adapted to portable devices since it has a lower power consumption compared to magnetic disk storage devices, a fast access time similar to that of a hard disk, and a small footprint.
The basic mechanism to store data bits in such a nonvolatile memory is a memory cell. Such a memory cell is composed of a unit field effect transistor including a control gate, a floating gate, a source, and a drain. In this case, a data bit can be stored by changing the capacitance of the floating gate to change the threshold voltage of the memory cell. Also, the memory cell is decoded by applying a selection voltage through the word line of the control gate.
A typical memory cell provides storage capacity by storing two states using one bit. Specifically, “1” denotes deletion and “0” denotes written.
A technique to significantly reduce the price per bit for nonvolatile memories was published in the article “A Multilevel-Cell 32 Mb Flash Memory” by M. Bauer in ISSCC Digest of Technical Papers, pp. 132-133, February, 1995. This publication includes a technique storing four states using two bits per memory cell.
As described above, a nonvolatile memory having capacity for storing four states using two bits per memory cell is typically called an MLC (Multi-Level Cell), and data bits for two pages are stored using one memory cell. Also, each of the two pages corresponding to one memory cell is called an LSB (Least Significant Bit) page and an MSB (Most Significant Bit) page respectively, and data bits are stored starting from the LSB page. For example, a two level MLC flash memory implements four states including 00, 01, 10, and 11 using 2 bits.
FIG. 1 is a graph illustrating states of a related art two level MLC nonvolatile memory.
As shown in FIG. 1, the typical 2 level MLC flash memory has an initial state of 11 and the state changes 10 to 00 to 10 in order as the voltage is increased. Thus, in order to make a state of 01 from a state of 11, state sequence 11 to 10 to 00 has to be followed. Also, in each state an upper bit indicates the MSB page and a lower bit indicates the LSB page.
In order to make a state transition from 11 to 01 as previously described in FIG. 1, while data is written into the MSB page, an error can occur in the MSB page as shown by FIGS. 2 and 3, and one state of the LSB page can still be changed to 0. Although data is correctly written into the LSB page, the data loss of the LSB page can occur due to the error that occurred when data is written to the MSB page.
In the flash memory management method disclosed by Korean Patent 2002-0092487A, when a write to a page which stores valid data is requested, the write occurs in the log block corresponding the data block including the page. When another write is requested, the write is written to a free page in the log block. However, this patent does not provide a method to prevent data loss in the LSB page which shares memory cells due to an error occurring during data write to the MSB page in an MLC flash memory.
USPTO Backgrounds
USPTO Backgrounds