1. Field of the Invention
The present invention relates to a substrate processing method, a substrate processing system, and a computer-readable recording medium recording a program thereon.
2. Description of the Related Art
In a process of manufacturing a semiconductor device, for example, patterning processing is performed for forming a predetermined pattern in a specific film to be processed above a wafer. In the patterning processing of the film to be processed, for example, a resist coating treatment of applying a resist solution onto a top of the film to be processed above the wafer to form a resist film, exposure processing of applying light in a predetermined pattern to the resist film above the wafer surface to expose the resist film, heating processing of heating the wafer to accelerate the chemical reaction in the exposed resist film (post-exposure baking), developing treatment of developing the heated resist film, heating processing of heating the wafer after developing treatment (post-baking) and so on are performed in sequence using the photolithography technique, so that a predetermined resist pattern is formed in the resist film above the wafer surface. Thereafter, the film to be processed is etched using the resist pattern as a mask, and the resist pattern is then removed, whereby a predetermined pattern is formed in the film to be processed.
To form a finer pattern to further miniaturize the semiconductor device, conventionally the wavelength of light for use in the exposure processing in the above-described patterning processing has been increasingly reduced. Only by the method of increasing the reduction in the wavelength for exposure, however, it is difficult to form a fine semiconductor device at a level of, for example, 32 nm or 45 nm.
Hence, it is proposed to perform a plurality of rounds of patterning on the film to be processed at the same layer above the wafer surface to form a finer pattern, so as to miniaturize the semiconductor device (Japanese Patent Application Laid-open No. H7-147219).
The heating processing in the above-described patterning processing, for example, the post-exposure baking is normally performed in a post-exposure baking unit and by mounting the wafer on a thermal plate which is adjusted to a predetermined temperature.
Incidentally, since the heating temperature in the post-exposure baking greatly affects the dimension of a final pattern, the temperature of the thermal plate in the post-exposure baking unit is controlled to be uniform within the mounting surface. However, slight unevenness of temperature having a certain tendency within the thermal plate actually occurs due to the performance of the thermal plate itself, the ambient environment or the like. Therefore, certain unevenness of dimension within the wafer according to the tendency of the unevenness of temperature of the thermal plate will occur in the pattern of the wafer processed by the thermal plate. In other words, according to the temperature tendency of the thermal plate, a portion Rw where the line width is relatively large and a portion Rn where the line width is relatively small are created in the pattern within the wafer, for example, as shown at (I) in FIG. 14.
When a plurality of rounds of performing are performed on the film to be processed at the same layer as described above, the post-exposure baking is performed for each of the rounds of patterning and the wafer is transferred to the post-exposure baking unit every time, so that the mount position of the wafer with respect to the thermal plate may be deviated, for example, in the rotation direction between the rounds of patterning. Along with deviation of the mount position of the wafer, the above-described unevenness of dimension of the pattern within the wafer also deviates, and a final pattern is formed having unevenness of dimension different in each of the rounds of patterning added in a plurality of rounds of patterning. This results in a failure to form a pattern with a desired dimension above the wafer and in a non-uniform dimension of the pattern within the wafer.
If the portion where the line width is relatively small in the second round of patterning is overlapped on the portion Rw where the line width is relatively large in the first round of patterning like the wafer W shown at (I) in FIG. 14, the line width of the final pattern becomes large as shown at (II) in FIG. 14. On the other hand, if the portion where the line width is relatively large in the second round of patterning is overlapped on the portion Rn where the line width is relatively small in the first round of patterning like a wafer W shown at (I) in FIG. 14, the line width of the final pattern becomes small as shown at (II) in FIG. 14. Thus, a pattern with a desired line width is not formed finally, and the line width within the wafer varies.
Accordingly, it is difficult to finally form a pattern with a desired dimension and ensure the uniformity of the pattern dimension within the wafer by the conventional method of performing a plurality of rounds of patterning.
USPTO Backgrounds
USPTO Backgrounds