1. Field of the Invention
This invention relates to the field of memory circuits. More particularly, this invention relates to the control of the word line voltage used to trigger the read of a bit cell within a memory circuit.
2. Description of the Prior Art
It is known to provide memory circuits comprising an array of bit cells with each bit cell having a node storing a data value. This node is coupled to a bit line for reading the stored data value via a word line transistor. The word line transistor has a conductance which is dependent upon a word line voltage of a word line signal upon a word line coupled to the bit cell being read.
As the size of the circuit elements within a memory circuit has become smaller, due to the user of smaller integrated circuit geometries, and the operating voltages of the memories have reduced in an effort to reduce power consumption, an increasing problem is the access disturb margin associated with a memory. When a read access is made to a bit cell the data value being stored may be incorrectly read due to effects such as charge sharing between the bit lines and the internal node resulting in stability issues within the bit cell.
USPTO Backgrounds
USPTO Backgrounds