Layers of semiconductor devices are patterned using lithography and etch processes. Both of these processes distort the pattern that is being transferred from a photomask to a layer on a semiconductor wafer.
The pattern to be formed on the wafer will be called the target pattern for the purposes of this application. The target pattern is produced by design steps that include considerations of circuit function, electrical parameters of devices, placement of components on an integrated circuit, routing of connections, parasitic electrical parameters of interconnections, and timing analysis of the circuit. The target pattern comprises a set of polygons. It is usually stored and transmitted in a file that is in GDS-II or OASIS format.
A photomask is manufactured according to a photomask data set, which comprises a set of polygons. The photomask data set is what is sent to a mask shop when a photomask is ordered. The photomask data is derived from the target pattern. The process that starts with the target pattern, and that yields the photomask data, can include: insertion of assist features, assigning phase-shifts to transparent apertures on the photomask, applying rule-based or model-based optical proximity correction (OPC), or process proximity compensation (PPC; See: Apo Sezginer, Franz X. Zach, Bayram Yenikaya, Jesus Carrero, Hsu-Ting Huang, Proc. SPIE Vol. 6156, March 2006, SPIE Press, Bellingham, Wash.)
The goal of OPC is to render the pattern formed on a wafer similar to a target pattern. In the prior art, OPC algorithms have not always met this goal. OPC users therefore resorted to verifying the OPC output by a model-based simulation. Verification is the art of checking, using a mathematical model of a manufacturing process, whether a given photomask data set will result in a sufficiently close approximation of the target pattern on the wafer. Prior art of verification includes these documents:
U.S. Pat. No. 7,117,477, Ye et al.
U.S. Pat. No. 7,114,145, Ye et al.
U.S. Pat. No. 7,111,277, Ye et al.
U.S. Pat. No. 7,003,758, Ye et al.
U.S. Pat. No. 7,191,428, Tang et al.
U.S. Pat. No. 7,155,689, Pierrat et al.
U.S. Pat. No. 6,944,844, Liu et al.
Mason et al., Proc. SPIE Vol. 6349, p. 63491X-1, SPIE, Bellingham, Wash., 2006
Kang et al., Proc. SPIE Vol. 6154, p. 61543J-1, SPIE, Bellingham, Wash., 2006
Ogino et al., Proc. SPIE Vol. 6151, p. 615129-1, SPIE, Bellingham, Wash., 2006
Hung et al., Proc. SPIE Vol. 5992, p. 59922Z-1, SPIE, Bellingham, Wash., 2005
Kim et al., Proc. SPIE Vol. 5853, p. 599, SPIE, Bellingham, Wash., 2005
Kim et al., Proc. SPIE Vol. 5992, p. 599922U-1, SPIE, Bellingham, Wash., 2005
Tones et al., Proc. SPIE Vol. 5992, p. 59923L-1, SPIE, Bellingham, Wash., 2005
Graur et al., Proc. SPIE Vol. 5379, p. 202, SPIE, Bellingham, Wash., 2004
Belledent et al., Proc. SPIE Vol. 5377, p. 1184, SPIE, Bellingham, Wash., 2004
Shang et al., Proc. SPIE Vol. 5040, p. 431, SPIE, Bellingham, Wash., 2003
van Adrichem et al., SPIE Vol. 5038, p. 1019, SPIE, Bellingham, Wash., 2003
Beale et al., SPIE Vol. 4889, p. 896, SPIE, Bellingham, Wash., 2002
A deficiency in the prior art is that verification has been performed using an optical model. Plasma etching imparts a proximity effect to the pattern formed on the wafer because the access of plasma to the side-wall of the pattern that is being etched, depends on the pattern. The access of the plasma to the side wall has not been taken into account in the prior art of verification.
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USPTO Backgrounds