The phase locked loop (PLL) is a common method of frequency synthesis in modern communications. Conventional PLLs are integral components in wireless communication transceivers and are also used for FM and AM modulation and demodulation, data and tape synchronization, frequency shift keying, tone decoding, frequency multiplication and division, signal regeneration, and control mechanisms in robotics, radio and satellite. A PLL normally includes a phase detector and a voltage controlled oscillator (VCO). A PLL can also include a divider, loop filter, or a number of other devices depending on the intended output frequency of the PLL.
PLLs are commonly used as frequency determining circuit components. The PLL is normally configured to receive a produce a desired output frequency that is an integer or fractional multiple of a reference frequency. Specifically, in a conventional PLL, the reference frequency is coupled to a phase detector. The phase detector is coupled to a VCO. The phase detector is configured to receive the reference frequency and also the output frequency generated by the VCO. The phase detector transmits, and the VCO is configured to receive, a voltage control signal based on a phase difference between the reference frequency and the output frequency. The voltage control signal adjusts the oscillation of the VCO until the phase of the output frequency matches the phase of the reference frequency. This feedback loop causes the output frequency to phase lock on the reference frequency.
If a higher or lower output frequency is desired, a frequency divider or multiplier can be introduced between the output frequency of the VCO and the phase detector to manipulate the frequency to be smaller or larger. To simplify this discussion, only a divider will be considered though a multiplier can be substituted for the divider. A divider can be configured to receive the output frequency and transmit a manipulated frequency to the phase detector based on the value of the divider. The phase detector generates a voltage control signal to the VCO in response to differences between the reference frequency and the manipulated frequency. The voltage control signal is provided until the phase of the reference frequency matches the phase of the manipulated frequency. The PLL thereby phase locks on a fraction or multiple of the reference frequency. Thus, a variety of frequencies can be produced from a single reference frequency by changing the value of the divider.
In current generation circuit design of transceivers, the output of the PLL is coupled to a mixer. The mixer typically uses the frequency output from the PLL to modulate or demodulate an input signal to form a modulated signal. In transmitters, the mixer is usually coupled to a power amplifier (PA). The PA is configured to receive and amplify the modulated signal to transmit an output signal. The PA in particular uses a large amount of power to amplify the voltage and current of the modulated signal to produce the desired output signal.
Difficulties have been encountered which prevent the integration of the PLL and the PA on a single integrated circuit chip. One common problem is cross-talk between the components because the PLL and PA normally operate at similar frequencies.
Cross-talk can manifest itself in various highly undesirable fashions such as injection locking, increased phase noise, greater error vector magnitude in the transmitter and reduction in adjacent channel power rejection in the transmitter. Normally these problems are a direct result of a limited isolation between layout traces, bondwires, and supplies.
Injection locking is particularly troublesome for integrated transceivers. There, the unwanted feedback from the PA is the primary cause. The PA generates unwanted feedback because of the high power drawn to amplify the modulated signal. Frequently, harmonics are generated at the operating frequency of the PA. The unwanted feedback is parasitically coupled to the PLL and degrades its performance. The unwanted feedback alters the voltage control signal of VCO which causes the VCO to phase lock on the power and/or unwanted feedback of the PA rather than the desired multiple of the reference frequency.
Like all other amplifiers, stability is of major concern because PAs can have significant power gains (e.g. as high as 30 dB). Consequently any parasitic feedback between stages can severely jeopardize the stability of the power. For transceivers where the amplifier is working in Class-C, the Power Added Efficiency (PAE) is another major concern. Traditionally, to increase PAE by decreasing the resistance of the transistor ports in the power amplifier, the traces coupled to the transistor ports are made thicker. However, the frequencies at which integrated circuits for wireless applications operate, generally known as microwave frequencies, a phenomenon known as the “skin depth effect” causes a significant portion the current to be concentrated around small areas around the corners of the traces. Increasing the width of traces to compensate does not give the current a wider path to travel past corners. As such, any increase in width of a trace typically does not change the current distribution inside a trace, and therefore the parasitic inductance of a trace remains substantially unchanged. Additionally, the increase in width in traces increases parasitic capacitance. To compete with traditional discrete PAs made in GaAs or other compound semiconductor technology, any integrated silicon-based PA must exhibit a PAE better than 35%. For an integrated transceiver, the aforementioned requirement must be met when all parasitic elements such as parasitic inductors and parasitic capacitors created unintentionally by the IC layout process are accounted for. For microwave applications, there will be no clear-cut border between schematic and layout. That is, non-intentional parasitic elements formed during layout can have comparable values to the intentional circuit elements used for matching and coupling. The influence of these parasitic elements, however, is mostly detrimental. Thus, a layout technique is needed to reduce parasitic inductance as well as inductive coupling.
Electrostatic discharge protection problems have also caused difficulties which prevent integration of a PLL and PA on a single chip. Subcircuits on a conventional integrated circuit share a common voltage supply and a common ground connection. This allows noise generated in one circuit to be provided to another circuit. Further, if one subcircuit has an ESD event, the charge flows into the common voltage supply or common ground and can affect the negatively performance of other subcircuits.
In addition, bandgap references and voltage regulators and their corresponding bypass capacitors are commonly found in integrated transceivers. They provide the biasing for the PA and PLL but also provide and potential feedback path for unwanted coupling between the PA and PLL.
The current demand for lower cost and better performance hardware creates a need for the integration of a PLL and PA on a single chip. In addition, this integration would eliminate the need for special drivers and an external PA reducing overall power consumption. Moreover, this integration would increase the yield of the circuit board due to the reduced number of components. Before this invention, no successful integration of a PLL and PA on a single chip has been achieved.
USPTO Backgrounds
USPTO Backgrounds