The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which enters a test mode in accordance with a test command.
In a product test, before shipment of a semiconductor device, there is a method which makes a semiconductor memory unit enter a test mode by applying a higher voltage (the so-called super-high voltage) than usual to an input pin. In the test mode, various commands and data are input to the unit and a test is executed. This method is called the super-high voltage impression method. This method requires a circuit for detecting the super-high voltage. The circuit impedes high density integration and reduction of the total circuit area. Another method sets a test mode using a special address not used by the user. For example, a command (the so-called illegal command), whose use is prohibited by the user is used as the test mode entry command.
A semiconductor memory unit, such as a synchronous dynamic random access memory (SDRAM) and a fast cycle dynamic random access memory, detects a command using a chip selection signal, a row address strobe signal, a column address strobe signal and a write enable signal, which are supplied from an external device synchronously with an external clock signal. The memory unit operates in accordance with the command. In the SDRAM, for example, a mode register set command (MRS) is indicated by the chip selection signal. Various test modes, such as a counter test and a high load test for a cell plate, are set in a mode register by the mode register set command and memory address signals A0 to An.
The memory address signals A0 to An used for specifying various test modes do not include the memory address signals A0 to An used for setting the operation mode of a mode register set command, such as burst length and CAS latency. That is, address patterns (illegal patterns) whose use is prohibited by the user are used as the memory address signals A0 to An which specify the various test modes. For example, when both a memory address signal A7 and a memory address signal A8 are high, a test mode is set, and the type of test is specified by an address signal excepting the memory address signals A7 and A8.
However, in an SDRAM, an illegal command may be accidentally generated and the test mode erroneously set in the mode register. For example, when a power supply is turned on, an illegal command may accidentally be generated because the input terminal of the SDRAM is in an indeterminate state. When a test mode is accidentally entered, if the external memory address signals A0 to An cannot be accepted in the test mode, the user immediately becomes aware of an abnormality and can stop use of the memory. For example, in the address counter test mode, the memory address signals A0 to An are input and read data is output. Therefore, the user becomes aware of an abnormality due to the output of the read data. The test mode can then be reset by resetting the mode register.
However, a test may include a test mode which is no different from the normal operation mode. For example, in the high load test mode of a cell plate, the internal voltage is changed to a high voltage, but an address input from an external device, access and the input/output of cell data are performed in the same manner as the normal operation mode. That is, the cell plate high load test corresponds to a burn-in test, and while the counter electrodes of a memory cell are being held at a high voltage, normal operations (write operation and read operation) are performed.
Accordingly, if a high load test mode is accidentally entered, the user may perform the high load test mode without being aware that it is a test mode. Continuous use in this test mode causes a continuous high voltage to be applied to the counter electrodes of a memory cell, thereby shortening the life of the SDRAM.
In recent years, chip size packages (CSP) have been used to increase the device board mounting efficiency. When the CSP is used, a continuity test mode may incorrectly be entered. For example, a grid array type CSP has terminals (solder balls) arranged on one side in a grid pattern. The terminals are connected to fine wiring patterns on the board.
After the device is mounted on the board, a connection test (continuity test) is performed between the terminals of the semiconductor device and the wirings on the board. However, for a CSP, because the terminals are hidden between the CSP and the board, a continuity test cannot be performed by placing a probe against the terminals. Accordingly, the CSP terminals connections to the board wiring are checked by sending a test signal from the wiring on the board to the CSP and then confirming a response from the CSP.
Because the test after a semiconductor device has been mounted differs from the performance and durability tests performed before mounting, it is desirable that the test mode entry method be changed. In the test mode entry before mounting, a test mode is prevented from being incorrectly entered in normal use by using an illegal command comprising many (for example, 15) signal patterns. On the other hand, in the test mode entry after mounting, it is desirable that fewer signals than those for the test mode entry before mounting be used because the non-connected state between terminals and board wiring may exist. Specifically, in the continuity test after mounting, the connection between the terminals of the semiconductor device and the board wirings is checked because there may be a terminal which is not connected to board wiring. Accordingly, if an illegal command is formed by many (for example, 15) signals, there is a possibility that one or more of the terminals to which the signals are input may not be connected to the board wirings. The probability of occurrence of this non-connected state increases as the number of signals of the illegal command increases. Thus, if the illegal command formed by many signals is used, the case where a test mode is not entered occurs more readily. On the other hand, if the number of signals is reduced, the probability of the continuity test mode being accidentally entered in normal use increases.
An object of the present invention is to provide a semiconductor device which prevents a test mode from being entered incorrectly.
In a first aspect of the present invention, a semiconductor device having a normal operation mode and a test mode is provided. The device includes a decision circuit for determining whether the test mode has been entered. A control circuit changes information related to a normal operation of the semiconductor device when the test mode has been entered.
In a second aspect of the present invention, a semiconductor device having a test mode is provided. The device includes a decision circuit for determining whether the test mode has been entered to output a test mode entry signal. A timer circuit performs a timing operation in response to the test mode entry signal and produces a time-up signal after a predetermined time has elapsed. The decision circuit invalidates the test mode entry signal in response to the time-up signal.
In a third aspect of the present invention, a semiconductor device having a test mode is provided. The device includes a decision circuit for determining whether the test mode has been entered based on a receipt of a plurality set of test mode command signals to output a decision signal.
In a fourth aspect of the present invention, a semiconductor device is provided. The device includes a first operation mode entry circuit for producing a first operation mode signal in response to an external signal after a power-on. The first operation mode entry circuit invalidates the first operation mode signal in response to a transition on a logic value of the external signal until a power-off.
In a fifth aspect of the present invention, a semiconductor device is provided. The device includes a first operation mode entry circuit for producing a first operation mode signal in response to a first combination on a logic value of a plurality of external signals after a power-on. The first operation mode entry circuit invalidates the first operation mode signal in response to a transition from the first combination to a second combination o the external signal until a power-off.
In a six aspect of the present invention, a semiconductor device is provided. The device includes a first operation mode recognition circuit for producing a first operation mode signal in response to an external signal. A second operation mode recognition circuit produces a second operation mode signal in accordance with a command signal. A first operation mode decision circuit invalidates the first operation mode signal in response to the second operation mode signal until a power-off.
In a seventh aspect of the present invention, a semiconductor device is provided. The device including a first operation mode recognition circuit for producing a first operation mode signal when a plurality of external signals have the predetermined logic combination. A second operation mode recognition circuit produces a second operation mode signal in accordance with a command signal. A first operation mode decision circuit invalidates the first operation mode signal in response to the second operation mode signal until a power-off.
In a eighth aspect of the present invention, a semiconductor device is provided. The device includes a test mode recognition circuit for detecting a test mode based on an external command and producing a test mode signal. A normal operation mode recognition circuit detects a normal operation mode based on the external command and produces a normal operation mode signal. A test mode decision circuit validates the test mode signal when the normal operation signal is not produced and invalidates the test mode signal when the normal operation mode signal has been produced.
In a ninth aspect of the present invention, a semiconductor device with a function which masks a plurality of I/O data groups including a first I/O data group and a second I/O data group in accordance with a plurality of mask signals including first and second mask signals is provided. The device includes a plurality of data I/O terminal groups including a first data I/O terminal group and a second data I/O terminal group. The semiconductor device masks the second I/O data group corresponding to the second data I/O terminal group in accordance with the second mask signal. A first data compression circuit compresses a first output data group and supplies the compressed first output data group to one terminal of the first data I/O terminal group.
USPTO Backgrounds
USPTO Backgrounds