1. Technical Field
The present invention generally relates to a method of etching oxide layer and nitride layer and, particularly to a method of forming an oxide-nitride-oxide (ONO) structure.
2. Description of the Related Art
Usually, there are many applications of nitride and oxide within integrated circuits (ICs), for example, an isolating structure between adjacent transistors, a gate sidewall spacer, an etch stop layer, a protection layer for outermost layer of IC chip, an ONO structure, etc.
A non-volatile static random access memory (nvSRAM) is taken as an example. The nvSRAM generally includes a static random access unit and a non-volatile memory unit of two parts. The static random access unit is for temporarily accessing data when a power is supplied. The non-volatile memory unit is for storing data in the circumstance of the power being cut off and then providing the stored data to the static random access unit for use when the power is retrieved. The nvSRAM can use a silicon-oxide-nitride-oxide-silicon (SONOS) structure formed therein as a memory cell. In operation of the nvSRAM, data signals (e.g., digital signals “0” and “1”) are performed with an action such as write (or termed as programming), erase or read in the SONOS structure.
However, during a conventional process for manufacturing the SONOS structure, it is found that after dry etching a top oxide layer and a nitride layer, sidewalls of a shallow trench isolation (STI) structure protruding from a wafer surface usually have unwanted residual material layer existed thereat and whereby forming a redundant fence (or termed as sidewall residual material or redundant sidewall spacer). Such redundant fence would change a surface profile of the STI structure and increase a width of the STI structure. Moreover, the redundant fence would become shielding masks of subsequent etching process and implantation process, even if adjusting the position or direction of mask for the implantation process, the influence caused by the redundant fence still could not be eliminated. As a result, dimensions of an effective area of doped region and an effective etching window are decreased. In other words, the redundant fence would cause the decrease of the effective area of active region, especially for a narrow width device. Even more, the redundant fence would cause a drop of current of the narrow width device and thus influence the operation of the narrow width device.
In order to get rid of the redundant fence, if attempting to add an additional isotropic etching process or an additional anisotropic etching process, a bottom oxide layer of the SONOS structure would suffer from twice over-etching, which would easily cause a substrate material (e.g., silicon) underneath the bottom oxide layer to be damaged, especially at the situation of the bottom oxide layer being extremely thin, electrical properties of device such as electric current are adversely affected consequently.
USPTO Backgrounds
USPTO Backgrounds