1. Field of the Invention
The present invention relates to a solid state imaging device and particularly to a solid state imaging device that achieves reduced mixed color, residual images, dark current, and noise, high sensitivity, and high pixel density.
2. Description of the Related Art
Currently, CCD and CMOS solid state imaging devices are extensively used in video cameras and still cameras. Improvement in the performance of solid state imaging devices, such as higher resolutions and higher sensitivity, is always required. Technical innovations for higher pixel densities have been made to realize higher resolution solid state imaging devices. Furthermore, technical innovations for improved light collection efficiency and reduced noise, dark current, and residual images have been made to realize highly sensitive solid state imaging devices.
The operation of a related art solid state imaging device is described hereafter (for example, see Sunetra K. Mendis, Sabrina E. Kemeny and Eric R. Fossum: “A 128×128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems,” IEDM93, Digest Papers, 22.6.1. pp. 583-586 (1993)). FIG. 18A shows the pixel structure of the above CMOS solid state imaging device and FIG. 18B shows the potential profile along the line A-A′ in FIG. 18A when signal charge 50 is accumulated. In FIG. 18B, accumulated charge is shown by hatching for distinction. The pixel comprises a signal charge accumulation area consisting of a P-type semiconductor substrate 53 for accumulating signal charges 50 generated by emitted light 52, a silicon oxide film (SiO2 film) 54a, and a photogate PG conductor layer, a transfer gate TG joined to the signal charge accumulation area, a floating diode FD joined to a channel 55 below an electrode of the transfer gate TG, an amplifying MOS transistor 56 having a gate AG connected to the floating diode FD, a selection gate (SG) MOS transistor 57 joined to the amplifying MOS transistor 56, and a reset MOS transistor 58 having a reset gate RG provided on a SiO2 film 54b connected to the floating diode FD and a rest drain RD diode. The reset drain RD of the reset MOS transistor 58 and the drain of the amplifying MOS transistor 56 are connected to a power supply line of a voltage Vdd. The source of the selection gate (SG) MOS transistor 57 is connected to a signal line 59.
Emitted light (irradiation light) 52 enters the P-type semiconductor substrate 53 through the photogate PG. Then, generated signal charges 50 (electrons in this case) are accumulated in a potential well 51 formed in the surface region of the P-type semiconductor substrate 53 by applying a suitable voltage to the photogate PG. The accumulated signal charges 50 are transferred to the floating diode FD when an ON voltage is applied to the transfer gate TG electrode. Then, the potential of the floating diode FD changes according to the quantity of signal charges 50. At the same time, the gate voltage of the amplifying MOS transistor 56 joined to the floating diode FD changes according to the quantity of signal charges 50. When an ON voltage is applied to the selection gate SG of the selection gate (SG) MOS transistor 57, a signal current according to the gate AG voltage of the amplifying MOS transistor 56 runs through the signal line 59. This current is read as output.
Another solid state imaging device utilizes a photodiode structure in which signal charges are accumulated in a photodiode PD unlike the signal charge accumulation structure using a photogate PG as shown in FIGS. 18A and 18B (for example, see the specification of Unexamined Japanese Patent Application KOKAI Publication No. 2000-244818 and R. M. Guidash, T. H. Lee, P. P. K. Lee, D. H. Sackett, C. I. Drowley, M. S. Swenson, L. Arbaugh, R. Hollstein, F. Shapiro, and S. Domer: “A 0.6 um CMOS Pinned Photodiode Color Imager Technology,” IEDM Digest Papers, pp. 927-929 (1997)). Such photodiode structures include a structure (pinned photodiode) having a P+ layer provided on the surface of a photodiode PD and a channel stopper P+ layer connected to the P+ layer and fixed (pinned) to the ground potential for electrically separating pixels from each other.
In the related art CMOS solid state imaging device shown in FIG. 18A, light 52 enters the photogate PG conductor layer from above. The photogate PG conductor layer is, for example, a thin, impurity-doped polysilicon (polycrystalline Si) layer. In such a structure, blue-wavelength light in the incident light 52 is inevitably partly absorbed by the polycrystalline Si layer. Furthermore, since the photogate PG covers the signal charge accumulation area in the surface region of the P-type semiconductor substrate 53, the signal charge accumulation area cannot directly be connected to the gate AG of the amplifying MOS transistor 56. For this reason, the transfer gate TG electrode and floating diode FD are provided. The signal charges 50 accumulated in the potential well 51 of the signal accumulation area are once transferred to the floating diode FD and the potential of the floating diode FD is given to the gate AG of the amplifying MOS transistor 56. Therefore, the transfer gate TG electrode and floating diode FD are necessary in the pixel region. Such additional regions hamper increase in the pixel density in related art CMOS solid state imaging devices.
On the other hand, for example, the solid state imaging device having a pinned photodiode structure described in the specification of Unexamined Japanese Patent Application KOKAI Publication No. 2000-244818 does not have the aforementioned problem of deterioration in sensitivity to blue-wavelength light in the photogate PG structure. With the surface of the photodiode PD being fixed to the ground potential, residual images resulting from incomplete transfer of signal charges to the floating diode FD and noise called kTC noise can be prevented. Furthermore, holes are accumulated in the P+ layer at the surface of the photodiode PD. The holes are recombined with electrons thermally excited from the SiO2—Si interface states and thereby the electrons are prevented from being injected into the signal charges 50. Then, dark current can be reduced. However, as in the aforementioned photogate PG structure, since the surface of the photodiode PD in which signal charges are accumulated is covered with the P+ layer, the potential of the photodiode in which signal charges are accumulated cannot directly be connected to the gate of the amplifying MOS transistor. Therefore, as in the signal charge accumulation structure using a photogate PG, the transfer gate TG electrode and floating diode TD regions are necessary and such additional regions hamper increase in the pixel density in CMOS solid state imaging devices.
Other problems of related art CMOS solid state imaging devices include deteriorated resolution and mixed color in color imaging.
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