1. Field
This disclosure relates generally to memories, and more specifically, to programmable bias for a memory array.
2. Related Art
Traditional dual supply memories include a voltage supply for the memory array and another voltage supply for the peripheral circuits, including row decoders and column multiplexers. Typically, in low power applications to reduce power consumption, the peripheral voltage supply is maintained at a lower voltage level than the memory array voltage. As the peripheral voltage supply is lowered, however, the memory cells in the memory array can develop various problems. For example, a lowered peripheral voltage supply, which is used to precharge the memory cells, can result in read disturb problem. In particular, when the precharge voltage is lower than the array voltage then the read disturb problem becomes worse. Specifically, as the precharge voltage is lowered compared with the array voltage a voltage differential develops between the bitline and the stored value in the bitcell. Read disturb relates to a situation when the stored value in the bitcell may change because of the additional current path from high storage node to the bitline because of the lower periphery voltage than the array voltage.
Accordingly, there is a need for programmable bias for a memory array that may be used to eliminate read disturb or at least lower the chances of read disturb.
USPTO Backgrounds
USPTO Backgrounds