1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display (LCD) device, and more particularly, to a data driving circuit for an LCD device. Embodiments of the present invention are suitable for a wide scope of applications. In particular, embodiments of the present invention are suitable for providing a simpler controller to generate a polarity control signal for the LCD device.
2. Description of the Related Art
In general, an LCD device includes a liquid crystal panel. The liquid crystal panel includes a first substrate including a pixel electrode, a second substrate including a common electrode, and a liquid crystal layer placed between the first and second substrates. The liquid crystal molecules forming the liquid crystal layer have a dielectric anisotropy property.
A voltage is applied between the pixel electrode and the common electrode to form an electric field in the liquid crystal layer to control the arrangement of the liquid crystal molecules. Accordingly, the transmittance of light passing through the liquid crystal layer can be controlled with the electric field to display a desired image. However, an extended application of the electric field in one direction in the liquid crystal layer may lead to image quality deterioration. The polarity of the data voltage applied to the pixel electrode with respect to a common voltage applied to the common electrode is inverted frame-by-frame, line-by-line or dot-by-dot.
FIG. 1 shows a block diagram of a driving system of an LCD device according to the related art. Referring to FIG. 1, the LCD device includes an interface part 10 receiving red (R), green (G), and blue (B) data, and control signals from a drive system (not shown), such as a personal computer (PC), and supplies the R, G, and B data and the control signals to a timing controller 12. Here, the control signals may include an input clock, a horizontal synchronizing signal (Hsync), a vertical synchronizing signal (Vsync), and a data enable signal (DE), etc. A low voltage differential signal (LVDS) interface and a transistor-transistor logic (TTL) interface are widely used for data and control signal transmission to the drive system. Also, such interfaces may be integrated into a single chip together with the timing controller 12.
The timing controller 12 uses the control signal from the interface part 10 to generate control signals for driving a data driver 18 including a plurality of drive ICs (not shown) and a gate driver 20 including a plurality of gate drive ICs (not shown). Also, input data from the interface part 10 is transmitted to the data driver 18.
A reference voltage generator 16 generates reference voltages for a digital-to-analog converter (DAC) within the data driver 18. The reference voltages are established by a producer on the basis of a transmittance-to-voltage characteristic of the LCD panel.
The data driver 18 selects reference voltages from the reference voltage generator 16 in accordance with the input data in response to the control signals from the timing controller 12. The data driver 18 performs conversion of the input data into analog image signals, and supplies the converted analog image signals to a liquid crystal panel 22.
The gate driver 20 switches ON/OFF the gate terminals of thin film transistors (TFT) arranged on the liquid crystal panel 22 line-by-line in response to the control signals input from the timing controller 12. Also, the gate driver 20 transfers the analog image signals from the data driver 18 to pixels connected to the thin film transistors, respectively.
A power voltage generator 14 supplies operating power for each of components, generates a common electrode voltage of the liquid crystal panel 22, and supplies the common electrode voltage.
In the configuration described above, the timing controller 12 generates predetermined control signals for driving of the LCD device, in response to the input control signals. That is, the timing controller 12 generates a control signal in accordance with a clock based on the edge of a horizontal synchronizing signal (Hsync) or a data enable signal (DE). The output signals from the timing controller 12 may differ from each other according to types of data drive ICs and gate drive ICs.
Types and timing of control signals used in common will now be described. Control signals for the data driver include a source sampling clock (SSC), a source output enable (SOE), a source start pulse (SSP), a polarity reverse (POL), a data reverse (REV), and an odd/even data signals, etc. The SSC signal is used as a sampling clock to latch data in the data driver 18 and determines a driving frequency of a data drive IC. The SOE signal transfers data latched by the SSC signal to the liquid crystal panel. The SSP signal is a signal that notifies a latch and sampling initiation of data during one horizontal synchronous period. The POL signal indicates the positive/negative polarity of the liquid crystals to make an inversion driving of the liquid crystals. The REV signal is a signal that selects the polarity of the transferred data. The odd/even data signal distinguishes between an odd data corresponding to an odd-numbered pixel, and an even data corresponding to an even-numbered pixel.
FIG. 2 shows a timing diagram of the operation of the data driver of FIG. 1 in response to a control signal. Referring to FIG. 2, if the data driver recognizes a “high” input of the SSP signal at the rising and falling edges of the SSC signal, then the data driver latches input data in response to the SSC signal. Thereafter, the latched data is decoded into an analog output voltage in response to the SOE signal and supplies the analog output voltage to the liquid crystal panel. Here, a positive decoder output voltage higher than a common electrode voltage is selected when the POL signal is a “high” state, while a negative decoder output voltage lower than the common electrode voltage is selected when the POL signal is a “low” state. Accordingly, the driving of the liquid crystal panel is inverted between positive and negative polarities.
Control signals for the gate driver include a gate shift clock (GSC), a gate output enable (GOE), and a gate start pulse (GSP) signals, etc. The GSC signal determines a time when a gate of the TFT is turned on or off. The GOE signal controls output of the gate driver. The GSP signal indicates a first drive line of the field in one vertical synchronizing signal.
FIG. 3 is shows a timing diagram of the operation of the gate driver of FIG. 1 in response to a control signal. First, the gate driver recognizes a “high” state of the GSP signal at the rising or falling edge of the GSC signal to output a gate signal maintaining a “high” state during about one period of the GSC signal. Here, the GOE signal is combined with the output gate signal to disable an output correspond to a “high” width of the GOE signal.
The aforementioned related art configuration has the following problems. First, the purpose of the inversion driving of the liquid crystal panel between positive and negative polarities is to prevent deterioration of the liquid crystal material. However, this periodic polarity inversion of the data voltage causes an asymmetry in a pixel voltage of a liquid crystal capacitor, which results in severe flickering.
Also, the size of the timing controller is increased to allow the timing controller to generate various control signals and rearrange externally provided data, and transfer signals between the timing controller and the plurality of drive ICs become complicated. Accordingly, the number of signal lines increases.
USPTO Backgrounds
USPTO Backgrounds