1. Field of the Invention
The present invention generally relates to flash memory structures within the field of semiconductor manufacturing. More particularly, the invention relates to flash memory structures with enhanced performance within the field of semiconductor manufacturing.
2. Description of the Related Art
A conventional flash memory structure includes a control gate located at least in-part over a floating gate that in-turn is located over a semiconductor substrate. The floating gate is separated from the semiconductor substrate by a tunneling dielectric. In addition, the control gate is separated from the floating gate by an intergate dielectric. Tunneling dielectrics and intergate dielectrics often comprise oxide dielectric materials, such as but not limited to silicon oxide dielectric materials.
Digital data storage within a flash memory structure is typically achieved by applying a programming voltage between the control gate and the semiconductor substrate to thereby inject charge carriers into, or discharge charge carriers from, the floating gate with respect to the semiconductor substrate. The intergate dielectric electrically isolates the control gate from the floating gate, but nonetheless allows for transfer of at least part of a control voltage from the control gate to the floating gate. An amount of control voltage transferred from the control gate to the floating gate is proportional to a capacitive coupling coefficient ratio (CCCR) of a particular flash memory structure. In general, higher values of a capacitive coupling coefficient ratio provide for lower programming voltages (i.e., either write programming voltages or erase programming voltages) within a particular flash memory structure. As a simple approximation, a capacitive coupling coefficient ratio is defined as a ratio of Cid to (Cid+Ctd), where Cid is the capacitance related to the intergate dielectric and Ctd is the capacitance related to the tunneling dielectric.
Flash memory structures and flash memory devices that exhibit an enhanced capacitive coupling coefficient ratio are known in the semiconductor fabrication art.
For example, Kao, in U.S. Pat. No. 6,602,750, teaches a particular flash memory memory structure that provides an enhanced capacitive coupling coeffieient ratio. To achieve the enhanced capacitive coupling coefficient ratio, this particular flash memory structure uses a recess within a floating gate in the flash memory structure, where the recess is filled by a control gate within the flash memory structure.
In addition, Chung, in U.S. Pat. No. 6,914,013, teaches another particular flash memory structure that provides an enhanced capacitive coupling coefficient ratio. To achieve the enhanced capacitive coupling coeffieient ratio, this particular flash memory structure includes the use of designated geometric constraints for portions of an intergate dielectric that is located at a corner of a floating gate within the flash memory structure, in comparison with other portions of the intergate dielectric within the flash memory structure.
Flash memory structures are likely to continue to be prominent as semiconductor structure and semiconductor device fabrication technology continues to advance. Thus, desirable are flash memory structures, and methods for fabricating those flash memory structures, that provide the flash memory structures with enhanced performance, and/or manufacturability advantage.
USPTO Backgrounds
USPTO Backgrounds