1. Field of the Invention
The present invention relates to an output circuit, and more particularly, to an output circuit with overshoot-reducing function.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional output circuit 100. The output circuit 100 comprises an input end, an output end, an inverter INV1, delay circuits 110 and 120, PMOS QP1, and NMOS QN1.
The input end of the output circuit 100 receives an input signal DIN. The output end of the output circuit 100 outputs an output signal DOUT. It is assumed that the output end of the output circuit 100 is equivalently coupled to a capacitor CL.
The PMOS QP1 comprises a first end, a second end, and a control end. The NMOS QN1 comprises a first end, a second end, and a control end. The inverter INV1 is coupled between the input end of the output circuit 100, and the delay circuits 110 and 120. The delay circuit 110 is coupled between the inverter INV1 and the control end of the PMOS QP1. The delay circuit 120 is coupled between the inverter INV1 and the control end of the NMOS QN1. The first end of the PMOS QP1 is coupled to a voltage source VDD (supplying a voltage VDD), the second end of the PMOS QP1 is coupled to the output end of the output circuit 100, and the control end of the PMOS QP1 is coupled to the delay circuit 110. The first end of the NMOS QN1 is coupled to a voltage source VSS (supply a voltage VSS), the second of the NMOS QN1 is coupled to the output end of the output circuit 100, and the control end of the NMOS QN1 is coupled to the delay circuit 120.
The inverter INV1 is disposed for receiving the input signal DIN, inverting the received input signal DIN, and outputting the inverted input signal DIN.
The delay circuit 110 is coupled between the inverter INV1 and the control end of the PMOS QP1 for receiving the inverted input signal DIN, delaying the received inverted input signal DIN for a predetermined period DL1, and then inputting the delayed input signal DIN to the control end of the PMOS QP1 (the node DP). The delay circuit 110 can be realized with an even number of the inverters coupled in series (the even number is “2m” as shown in FIG. 1) for delaying the predetermined period DL1.
The delay circuit 120 is coupled between the inverter INV1 and the control end of the NMOS QN1 for receiving the inverted input signal DIN, delaying the received inverted input signal DIN for a predetermined period DL2, and then inputting the delayed input signal DIN to the control end of the NMOS QN1 (the node DN). The delay circuit 120 can be realized with an even number of the inverters coupled in series (the even number is “2n” as shown in FIG. 1) for delaying the predetermined period DL2.
The voltage VDD can be a high voltage, and the voltage VSS can be ground.
Additionally, the delay periods DL1 and DL2 are different, which means the numbers “2m” and “2n” of the inverters are different. The difference between the delay periods DL1 and DL2 avoids the PMOS QP1 and the NMOS QN1 being both turned on at the same time, which generates the current flows from the voltage source VDD directly to the voltage source VSS.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the conventional output circuit 100. As shown in FIG. 2, after the input signal DIN is inputted, on the node DP, the signal inverted from the input signal DIN and delayed for the predetermined period DL1 is generated and inputted to the PMOS QP1. Meanwhile, on the node DN, the signal inverted from the input signal DIN and delayed for the predetermined period DL2 is generated and inputted to the NMOS QN1. In this way, the output signal DOUT is generated by the PMOS QP1 and the NMOS QN1. When the input signal DIN is in a transient status (for example, in the period of the voltage of the signal DIN changing from a high voltage to a low voltage, or vice versa), the voltage of the output signal DOUT possibly rises over the voltage VDD or falls over the voltage VSS, which is so-called overshoot, and damages the components in the circuit.
A conventional method for reducing the overshoot problem is to couple a capacitor to the output end of the output circuit 100. However, the capacitor on the output end lowers the slew rate of the output signal DOUT, and consequently the access speed of the output circuit 100 is also lowered. As the speed of internal components of systems increases, the demand for the speed of the memory is also increased. It is not satisfying the demand with just purely raising the frequency of the clock signal of the memories, and therefore the technologies of the Synchronous Dynamic Random Access Memory (SRAM), the Double Data Rate (DDR), and the second generation of the DDR (DDR2) have to be utilized to meet the demand. The frequencies of dies of the conventional memories equal to the frequencies of the input/output buffers (I/O buffers. However, the frequencies of the I/O buffers of the memories of the DDR2 technology is doubled than the frequencies of the cores of the memories. The method with adding capacitors to the output ends for reducing overshoots lowers the speed of the output circuit of the memory.
Therefore, it is important to provide an innovative technology of Off-Chip Driver (OCD) with voltage-regulating circuits to reduce overshoots when the output circuit charges/discharges.
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