1. Field
Embodiments of the invention generally relate to a method for etching through-silicon vias (TSVs) with tunable profile angles while maintaining desired etching rates.
2. Description of the Related Art
Deep recessed structure etching is one of the principal technologies currently being used to fabricate semiconductor and microstructure devices. Strict control of the etch profile is required for complex devices to perform satisfactorily. Obtaining a controlled sidewall profile, where the taper angle range is from about 85 degrees to about 90 degrees in combination with a smooth sidewall surface has proved a difficult task in many instances.
Through-silicon vias (TSVs) with a sidewall taper angle ranging from about 85 degrees to about 90 degrees are particularly useful in various electronic packaging applications. The TSVs enable the attachment of various components to each other, frequently in manners which enable electrical connection from device to device. Different designs of the devices may require different sidewall taper angles to facilitate the bonding/packaging process. Inaccurate control of the sidewall taper angles may cause difficulty for the following wiring and/or packaging process, thereby resulting in device failure or poor electrical performance.
Furthermore, etching process control for forming deep trenches or deep vias in a substrate is often challenging. Improper etching process parameter control may result in defects formed in the resultant vias. For example, improper control of RF power generated during the etching process may result in insufficient depth down to the bottom of the vias or render grass type defects on the bottom of the vias. Additionally, sidewall profile management is highly associated with the process parameters and chemical precursors utilized during the etching process. Improper chemistry or process parameter control may result in an irregular profile, such as overly large side scallop 106, striation, non-smoothing or other different types of the defects formed on the via 104 formed in the substrate 102, as shown in FIG. 1.
Therefore, there requires an improved method for etching and forming TSVs in a substrate with desired sidewall management and profile control.
USPTO Backgrounds
USPTO Backgrounds