1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to a process flow that may reduce hole defects in P-active regions and reduce across-wafer threshold voltage scatter.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high-speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include so-called high-k materials (k value greater than 10) that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the typical polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also present an additional complex process step, which, however, may avoid complex processes in an advanced stage for adjusting the work function and, thus, the threshold voltages in a very advanced process stage.
It turns out, however, that the manufacturing sequence of forming the threshold adjusting semiconductor alloy may have a significant influence on threshold variability and other transistor characteristics, as will be described in more detail with reference to FIG. 1.
FIG. 1 depicts an illustrative prior art device 100 that is generally comprised of a partially formed NFET transistor 100N and a partially formed PFET transistor 100P formed in and above a semiconducting substrate 10. The illustrative transistors 100N, 100p are separated by an illustrative isolation structure 12, e.g., a shallow trench isolation structure, formed in the substrate 10. In one illustrative embodiment, the semiconducting substrate 10 is comprised of silicon. The substrate 10 may have a variety of configurations, such the depicted silicon-on-insulator (SOI) structure having a bulk silicon layer 10A, a buried insulation layer 10B and an active layer 10C. The substrate 10 may also have a simple bulk silicon configuration.
At the stage of manufacture depicted in FIG. 1, the transistors 100N, 100P are each comprised of a gate structure 20 and source/drain regions 30. The gate structure 20 may include a gate insulation layer 22, a high-k insulation layer 24, a gate electrode 26 and sidewall spacers 28. The gate electrode may be made of a variety of materials, such as aluminum (for the NFET transistor 100N) and lanthanum (for the PFET transistor 100P). In some cases, the PFET transistor 100P may have an additional work function layer 25, such as titanium nitride, that may not be present in the NFET transistor 100N. Typically, during the formation of the PFET transistor 100P, a layer of semiconductor material 32, e.g., silicon germanium, is selectively formed on the active layer 10C in the P-active region where the PFET transistor 100P will be formed to enhance the performance of the PFET transistor 100P. Typically, such a semiconductor layer is not formed for the NFET transistor 100N. Prior to selectively forming the layer of semiconductor material 32 for the PFET transistors 100P, one or more etching and masking process may be performed such that only the portions of the active layer 10C where PFET transistors 100P will be formed are exposes to the selective deposition process, e.g., a selective epitaxial deposition process. As a result of these various etching and masking steps, the thickness of portions of the isolation region 12 adjacent the P-active regions of the active layer 10C may be reduced as compared to the thickness of the portions of the isolation region adjunct the N-active regions of the active layer 10C. Additionally, although not depicted in FIG. 1, the layer of material that make gate electrode structure may not be the same for the PFET and NFET transistors, 100P, 100N, respectively. That is, in one example, the PFET transistor 100P may have additional work function adjusting materials as compared to the materials used for the NFET transistor 100N. The thickness of the layers of materials may vary as well for the NFET and PFET transistors 100N, 100P, even if the same material is employed.
One of more of the forgoing issues tends to make the total height of the NFET and PFET transistors 100N, 100P, different, and this height differential tends to exist across a wafer. In addition to making subsequent processing operation, like chemical mechanical polishing, more problematic, such across- wafer height differences can lead to relatively large variations in the threshold voltage of the resulting devices, thereby making control of the various devices difficult, at best. Additionally, such height differences may tend to make critical gate patterning operations less accurate as across-wafer height difference tends to make photolithography operations less accurate. Given that the gate length on modern transistor devices is 30-50 nm, and that further scaling is anticipated in the future, even very small errors in the gate patterning activities can significantly impact the performance of the resulting transistors. From an overall perspective, such threshold voltage variations may also lead to reduced yields and/or decreased performance capabilities of the resulting semiconductor device.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds