The present invention relates to a memory device, and relates in particular to a memory device having a circuit configuration that ensures an increase in the operating speed.
While memory devices have been highly integrated, interfaces have been developed that permit the memory devices to be operated at high speeds and with a low signal amplitude. To this end, SSTL (Stub Series Termination Logic) has been proposed as the standards for these interfaces. In order to increase the operating speeds of DRAM, which is one type of memory devices, a DDR (Double Data Rate) method has been also proposed. In the DDR method, the data rate can be doubled by inputting and outputting data in synchronism with the leading edge and the trailing edge of each clock.
These types of memory devices have a configuration wherein multiple memory modules are mounted on a motherboard in parallel and at predetermined distances or intervals. According to this configuration, when the memory modules are mounted on a motherboard, electrical contacts are established between the modules and their respective connectors. For this, the motherboard is provided with a slot for attachment of each memory module, and a plurality of terminals are arranged in each of the slots to make electrical connections to the corresponding memory modules. In addition, buffers, such as multiple memory units and registers, are mounted on the obverse and/or reverse faces of the memory modules, and are contacted with the connectors through the terminals formed at ends of the memory modules.
Among the memory devices, there is one where a controller called a chip set is mounted on the motherboard to control the memory units of the memory modules. According to this memory device, a data bus, a command bus and a clock bus (in the following explanation, these buses may be collectively referred to simply as buses) are wired on the motherboard. These buses provide electrical connections between the controller and the memory units and between the controller and the registers on the individual memory modules.
In an example configuration, the data and the clock buses among the above described buses are extended from the controller directly to the memory units of the memory modules while the command bus is extended to the registers through the connectors and is connected through the registers to the memory units of the memory modules.
Furthermore, a memory device conforming to the SSTL standards employs a configuration such that DRAMs (which serve as the memory units of the memory modules) and the connectors are connected through stubs.
In the above-mentioned memory device, it has been considered that the frequency of the clock provided for the clock bus is taken into account and is set equal to or higher than 100 MHz (e.g., 133 MHz). Therefore, by employing DDR, a data reading/writing rate can be attained that is equal to or higher than 200 MHz. Recent requests, however, have been made for memory modules that operate at clock frequencies of from 200 to 300 MHz, in which case data rates would rise to 400 to 600 MHz or more.
To respond to these requests, a stub structure and a wiring structure for a memory module have been proposed that would reduce signal reflection or signal distortion due to impedance mismatching (Japanese Unexamined Patent Publication No. 2001-257018A). However, according to a study performed by the present inventors, it was found that there are various factors that would prevent the operation at high speed of these types of memory device, and it was further found that neither improvements in the stub structure nor improvements in the memory module structure would provide a satisfactory operating speed increase.
For example, the following shortcoming was found as regards the data bus. When a readout operation is carried out through the data bus from the controller mounted on the motherboard to the memory unit of each memory module, the controller is put in a state that is not terminated. Accordingly, signal reflection occurs in the controller. Further, when a write-in operation is performed by the controller, it was also found out that signal reflection occurs at the connector, depending on the length of the data bus from the controller to the connector. Signal reflection was also observed when DRAMs were connected as the memory units for the memory modules and when data writing was performed for individual DRAMs.
Furthermore, the data bus has one end of the data connected to the controller and the other end connected to a non-reflecting terminating set, and a predetermined terminal potential is applied to the non-reflecting terminator from a terminal power source. This configuration is, however, disadvantageous in that the power sources increases in number. This is also applicable to the command address bus.
As for the clock bus, a memory device has been proposed wherein a pair of complementary clocks are supplied to the individual memory units of the memory module in order to accurately perform the clock operation. In this memory device, a controller and each of the memory units are connected through a pair of clock buses. No consideration has been given for the signal reflection that occurs in the memory units in this configuration.
USPTO Backgrounds
USPTO Backgrounds