1. Field of the Invention
The present invention relates to a memory device, and more particularly, to an EPROM encryption code decoding prevention circuit for a semiconductor memory device.
2. Background of the Related Art
As shown in FIG. 1, a data encrypting circuit of a semiconductor memory device, such as a conventional EPROM cell, includes an encryption code data cell 11A outputting encryption code data per bit line when an encryption word line signal EW/L is applied thereto by an external controller. A word line operator 12 generates a word line signal W/L according to an externally applied address signal ADD to select one of the column memory cells MC.sub.1 -MC.sub.m for reading data stored therein of a memory array 11B. An encryption processor 13 logically combines the output from the cell of the memory array 11B with the encryption data of encryption code data cell 11A and provides the encrypted data on the output terminal D.sub.out.
In FIG. 1, the data output circuit is drawn on the basis of a 1-bit line signal B/L, wherein a cell is selected from a plurality m of cells MC.sub.1 -MC.sub.n connected to one bit line. The data stored in the selected cell MC.sub.1 -MC.sub.n is logically combined with the encryption data stored in an encryption code data cell 11A, the transistor EC being connected to the corresponding bit line B/L. The resulting value is outputted in an encrypted type. The output timing steps will now be described.
At a first step, the word line operator 12 drives a designated word line W/L.sub.x selected from a plurality of word lines W/L.sub.1 -W/L.sub.n. Accordingly, a corresponding memory cell MC.sub.x selected from the multiple memory cells MC.sub.1 -MC.sub.n is enabled, whereby a 1-bit data read from the corresponding cell is outputted through the bit line B/L.sub.x.
At this time, a write signal W remains at a low level to maintain an off-state of NMOS transistor NM1. A data read signal R turns to a high level for enabling a second NMOS transistor NM2. An encryption data read signal ER turns to a high level to thereby enable a third NMOS transistor NM3. A read control signal RC turns to a low level to maintain a fourth NMOS transistor NM4 disabled. Accordingly, the output data from the bit line B/L.sub.x sequentially passes through the second NMOS transistor NM2, a first latch LAT1, and the third NMOS transistor NM3 and is latched in a second latch LAT 2.
At a second step, the encryption word line signal EW/L turns to a high level to enable an NMOS transistor EC of the encryption data cell 11A. Accordingly, an encrypted data is outputted through the bit line B/L.sub.x. At this time, the write signal W remains at a low level to disable the first NMOS transistor NM1, and the data read signal R turns to a high level to enable the second NMOS transistor NM2. Then, the encrypted data read signal ER remains at a low level to disable the third NMOS transistor NM3. As a result, the 1-bit encryption data via the bit line B/L is latched through the second NMOS transistor NM2 into the first latch LAT1.
At a third step, the encryption data read signal ER turns to a low level to disable the third NMOS transistor NM3. The read control signal RC turns to a high level to enable the on-state of fourth NMOS transistor NM4. Accordingly, the encrypted data latched in the first latch LAT1 and the cell data latched in the second latch LAT2 are NORed at a NOR gate NOR1 and XNORed at an exclusive NOR gate XOR1 sequentially. The resultant value is applied through the fourth transistor NM4 as an output signal Dout.
The above first to third steps are repeatedly performed to encrypt the output data Dout while the data stored in the memory array 11B is read and externally outputted. A truth table of FIG. 2 illustrates the encryption of the cell data. For instance, in the case in which an encryption code data is "0" and a data cell data is "0", the cell data is latched in the second latch LAT2 through the previously described steps. The the encryption data is inverted to "1" and stored in the first latch LAT1. At this time, since the encryption data read signal ER is "0", the encryption code data latched in the first latch LAT1 outputs the inverted "0" through the NOR gate NOR1, and a value of "0" is applied to each of the inputs of the exclusive NOR gate XNOR1 which in turn outputs a value "1". An encrypted cell data "0" is output as the data value.
Therefore, because the EPROM cell data is logically combined with the encryption code data and the resultant encrypted data is outputted, the data stored in the memory array 11B cannot be retrieved without knowledge of the encryption data. However, the conventional data encrypting circuit has several disadvantages as follows.
When every memory cell is employed to store data, the encrypted data is not exposed. When only a part of the memory cells are used to store data, the other unused data cells uniformly remain at a value "0". Further, the final output data is outputted as a uniformly inverted encryption code data whereby an unauthorized user may discern the encrypted data based upon the output data. The unauthorized user may be able to read the original cell data by XNORing the final output data stored in a cell and the discerned encryption data, thereby preventing the objectives of the encryption data cell adaptability.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
USPTO Backgrounds
USPTO Backgrounds