1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a gate array or an ECA (embedded cell array) and, more particularly, to a clock driver circuit furnished in that semiconductor integrated circuit device.
2. Background Art
In semiconductor integrated circuit devices including gate arrays and ECA's, the devices' core region has two kinds of macro cells formed therein: a plurality of macro cells acting as logic circuits such as AND or OR circuits, and a plurality of macro cells acting as circuits such as flip-flop circuits each requiring a clock signal. Clock driver circuits are furnished to supply clock signals to such multiple flip-flop circuits.
One way to form the clock driver circuit and to have the circuit included in a semiconductor integrated circuit is illustratively proposed in U.S. Pat. No. 5,444,276 (corresponding to Japanese Patent Laid-Open No. Hei 6-236923). As shown in FIG. 23, the clock driver circuit typically comprises a predriver PD and a plurality of main drivers MD1 through MDn. The input nodes of the main drivers MD1 through MDn are connected by a common line L1, and their output nodes are connected by a common line L2.
The clock driver circuit is arranged as shown in FIG. 24. Specifically, the plurality of main drivers MD1 through MDn are formed in macro cell layout regions MCR between a power supply line VDD1 and a ground line GND1 constituting a power supply line pair. The power supply line VDD1 is fed with a supply potential, and the ground line GND1 is arranged adjacent to and in parallel with the power supply line VDD1 and is supplied with a ground potential.
The common lines L1 and L2 are each formed between the power supply line VDD1 and ground line GND1 making up the power supply line pair and are arranged in parallel therewith. The common lines L1 and L2 are connected electrically via through holes TH1 and TH2 to the input and output nodes of the main drivers MD1 through MDn. The common line L1 is connected electrically to the output node of the predriver PD via a through hole TH3.
Flip-flop circuits FF formed in the macro cell layout regions MCR each need to be supplied with a clock signal. For that purpose, the clock input nodes of the flip-flop circuits FF are electrically connected via wiring LL to clock signal supply lines CL1 through CLm which in turn are connected electrically to the common line L2.
Each of the clock signal supply lines CL1 through CLm intersects perpendicularly the power supply line VDD1 and ground line GND1 in a wiring region WR, and is located along the corresponding macro cell layout region MCR. Each of the clock signal supply lines CL1 through CLm is electrically connected via a through hole TH4 to the common line L2 where the latter intersects the clock signal supply line.
Each macro cell layout region MCR is flanked by a power supply line VDD2 and a ground line GND2. The two lines VDD2 and GND2 perpendicularly intersect the power supply line VDD1 and ground line GND1 and are electrically connected thereto via through holes TH5 and TH6. A clock driver circuit of the above-described constitution incorporated in a semiconductor integrated circuit device proves to be a clock driver circuit that is easy to lay out and provides high driving ability without increasing the area of the semiconductor substrate.
A semiconductor integrated circuit fed with clock signals having a plurality of frequencies in normal operation may be tested for failure in a so-called scan test. The test in part involves connecting flip-flop circuits inside the circuit by means of scan paths. One way to establish clock signal wiring for the scan test is proposed illustratively in Japanese Patent Laid-Open No. Hei 7-168735.
In normal operation, as shown in FIG. 25, a clock signal A input to a clock A terminal 101 passes through a clock driver A 103, clock A wiring 120 and a switch 111 of a switch circuit 114 to enter a flip-flop circuit 108 in a block 107. A clock signal B input to a clock B terminal 102 passes through a clock driver B 104 of a driving ability change circuit 106, clock B wiring 121 and a switch 112 of the switch circuit 114 to enter a flip-flop circuit 109 in the block 107.
In a scan test, the clock A terminal 101 is not fed with any clock signal. Only the clock B terminal 102 is supplied with the clock signal B, so that a semiconductor integrated circuit 119 is given a single frequency. At this point, the switch 111 is turned off and the switches 112 and 113 are turned on in the switch circuit 114. As a result, the flip-flop circuits 108 and 109 admitting clock signals of a plurality of frequencies in normal operation are switched and connected to the single clock B wiring 121. In this setup, the driving ability change circuit 106 is supplied with a driving ability change signal 105 so as to enhance driving ability to counter new increases in the clock signal wiring load.
The result is that the flip-flop circuits 108 and 109 are fed with the clock signal B having entered the clock B terminal 102 by way of the driving ability change circuit 106, clock B wiring 121, and the switches 112 and 113 of the switch circuit 114. In the semiconductor integrated circuit of the above constitution, clock skews are reduced during the scan test.
The first example shown in FIGS. 23 and 24 is a semiconductor integrated circuit device that receives a single clock signal (gate array, ECA, etc.). The second example in FIG. 25, on the other hand, is merely a generically presented semiconductor integrated circuit and has nothing to show regarding such devices as gate arrays and ECA's. The second example has no mention of any specific constitution of the clock driver A 103 or the driving ability change circuit 106 including the clock driver B 104.
USPTO Backgrounds
USPTO Backgrounds