1. Field of the Invention
The present invention relates to asynchronous or synchronous circuit, and in particular to an asynchronous sensing differential logic (ASDL) circuit employing a charge-recycling technique.
2. Background of the Related Art
In general, in designing a semiconductor circuit, an asynchronous design technique has advantages in that a clock skew is not generated and a clock signal distribution overhead is not incurred because a global clock signal is not employed, power consumption may be reduced because a signal transition is generated only when there is an event, and latency is decreased because the processing time is determined not by a worst-case delay but by an average delay.
In order to embody an asynchronous system, a smooth communication is required between local function blocks. Here, a 2-phase handshaking protocol or 4-phase handshaking protocol is mainly used. Especially, the 4-phase handshaking protocol is easily embodied in a circuit, and thus is popularly used.
FIG. 1 is a schematic block diagram illustrating a conventional asynchronous pipeline configuration including a functional block 102 performing each logic operation, a completion detector 103 communicating operation completion of the functional block 102, a control block 101 controlling handshaking of the functional block 102, and a latch block 104 outputting data according to the operation of the functional block 102.
A differential cascode voltage switch (DCVS) logic can easily carry out a completion detection from a preceding stage, are mainly utilized as the functional block 102. A circuit diagram thereof is illustrated in FIG. 2.
FIG. 2 is a schematic circuit diagram illustrating a differential cascode voltage switch (DCVS) logic circuit. As shown therein, a clock signal CK is applied to gates of two PMOS transistors PM1, PM2 to the sources of which is applied a power supply voltage Vdd. The clock signal CK is applied to the gate of an NMOS transistor NM1 having its source grounded. The drains of the PMOS transistors PM1, PM2 are commonly connected to the drain of the NMOS transistor NM1 through a cascode logic 102-1 that is turned on/off pursuant to input data. The output drain terminals of the PMOS transistors PM1, PM2 and the cascode logic 102-1 are each respectively connected to the input terminals of two inverters X1, X2. The inverters X1, X2 output respective output signals OUT, OUT.
On the other hand, a Muller C-element is often employed as a handshaking circuit in the asynchronous system because of its delay-insensitive property. When two input values are the same, an output value is identical to the input value. In case the two input values are different, an operation of holding a preceding value is carried out.
The control block 101 in the configuration of FIG. 1 is embodied mainly with the Muller C-element for handshaking control.
In addition, the latch block 104 may use a traditional flow-latch type or Muller C-element. However, the flow-latch does not have the delay-insensitive property, and thus the Muller C-element is mostly employed.
As illustrated in FIG. 3, in the latch block 104, an acknowledge signal Ack from the succeeding stage is commonly applied to a gate of a PMOS transistor PM22 to the source of which is applied the power supply voltage Vdd, and to the gate of an NMOS transistor NM22 having its source grounded, and the input signal (Din, namely OUT or OUT) is commonly applied to the gate of a PMOS transistor PM21 having its source connected to the drain of the PMOS transistor PM22, and to a gate of an NMOS transistor NM21 with its source connected to the drain of the NMOS transistor NM22. The latch block 104 includes two circuits with a latch 104-1 consisting of two inverters X4, X5 connected in reverse parallel to latch a signal outputted from a node of the PMOS transistor PM21 and the NMOS transistor NM21, and to output the latched signal DATAOUT.
In general, the completion detector 103 in the configuration in FIG. 1 includes a NAND gate or NOR gate to carry out a logic operation on the two output signals OUT, OUT from the functional block 102 and to generate the operation completion signal.
The operation of the conventional asynchronous system will now be described.
When an acknowledge signal ACKOUT from the succeeding stage is low, if a request signal REQIN from the preceding stage is low, the clock signal CK outputted from the control block 101 becomes high, the functional block 102 provides the output value OUT, OUT, and the completion detector 103 performing a logic operation on the output value OUT, OUT generates a high output value.
In the case that the output value from the completion detector 103 is high, the output value is transmitted as the request signal REQOUT for the succeeding stage, and as the acknowledge signal ACKIN for the preceding stage.
Then, when the request signal REQIN from the preceding stage is high, the output signal from the control block 101 maintains its preceding output state. When the acknowledge signal ACKOUT from the succeeding stage is high, the clock signal CK outputted from the control block 101 becomes low.
Accordingly, the output signal from the completion detector 103 is generated low, thus rendering low the values of the acknowledge signal ACKIN transmitted to the preceding stage and the request signal REQOUT transmitted to the succeeding stage.
That is, the logic operation of the functional block 102 is carried out by repeating the above-described process.
If functional block 102 is implemented by FIG. 2, when the clock signal CK is low, the PMOS transistors PM1, PM2 are turned on, and thus the internal output terminal, namely the input terminals of the inverters X1, X2 are charged at a high level. The inverters X1, X2 receiving the high signals from the internal output terminals respectively discharge the external output terminals OUT, OUT to a low level.
Thereafter, when the clock signal is changed from low to high, the NMOS transistor NM1 is turned on, and thus the cascode logic 102-1 is put into an operational state.
Here, the cascode logic 102-1 discharges the internal output terminal, namely one of the input terminals of the inverters X1, X2 to a low level according to the input value DATAIN. Here, it is presumed for example that the input terminal of the inverter X1 is discharged.
As a result, the output terminal OUT of the inverter X1 whose input terminal is discharged to a low level becomes high, and the output terminal OUT of the inverter X2 whose input terminal is charged to a high level is maintained at a low level.
Then, when the clock signal CK is changed from high to low, the data operation is carried out by repeating the above-described process.
When outputted from the functional block 102 constituted as illustrated in FIG. 2, the data OUT, OUT are transmitted into the succeeding stage through the latch block 104 including the two circuits consisting of the plurality of transistors PM21, PM22, NM21, NM22 and the latch 104-1 as depicted in FIG. 3.
The operation will now be explained by exemplifying the output data signal OUT from the function block 102. When the acknowledge signal ACKOUT from the succeeding stage is at a low level, if the output data signal OUT from the functional block 102 is at a low level, only the PMOS transistors PM21, PM22 are turned on, the power supply voltage is applied to the latch 104-1, and thus the latch 104-1 outputs the low level data signal DATAOUT. When the acknowledge signal ACKOUT is at a high level, only the NMOS transistors NM21, NM22 are turned on, and thus the input terminal of the latch 104-1 is grounded. As a result, the latch 104-1 outputs the high level data signal DATAOUT.
When the acknowledge signal ACKOUT is at a low level, if the output data signed OUT from the functional block 102 is at a high level, or when the acknowledge signal ACKOUT is at a high level, if the output data signal OUT from the functional block 102 is at a low level, the latch 104-1 maintains a preceding output level until the two input signal levels become identical.
The conventional technique guarantees the low power consumption and high-speed operation in theory. Actually, there is a disadvantage in that performance is not remarkably improved, as compared with a synchronous system, due to a control circuit overhead required for the handshaking protocol and excessive power consumption of the DCVS logic used as the functional block.
USPTO Backgrounds
USPTO Backgrounds