1. Field of the Present Invention
The present invention relates to a semiconductor device including insulated gate field effect transistors, referred to as xe2x80x9cMIS transistorsxe2x80x9d hereinafter, as it components, and particularly to a configuration for reducing power consumption in a semiconductor device having miniaturized CMOS transistors (P- and N-channel MIS transistors). More particularly, the present invention relates to a structure for suppressing a gate tunnel current of a miniaturized MIS transistor.
2. Description of the Background Art
In a CMOS semiconductor device, as the size of MIS transistors is reduced, an operation power supply voltage is lowered for ensuring reliability of the transistors and reducing power consumption. For reducing the sizes of MIS transistors in accordance with lowering of the operation power supply voltage, values of various transistor parameters are reduced according to a certain scaling rule. According to the scaling rule, it is necessary to reduce a thickness Tox of a gate insulating film of the MIS transistor, and it is also necessary to reduce an absolute value Vth of a threshold voltage. However, it is difficult to reduce the absolute value of the threshold voltage according to the scaling rule. The threshold voltage is defined as a gate-source voltage, which causes a predetermined drain current under application of a predetermined drain voltage. If absolute value Vth of the threshold voltage is small, a weak inversion layer is formed in a channel region even with a gate-source voltage Vgs being 0 V, and a sub-threshold leak current, referred to as an xe2x80x9coff-leak currentxe2x80x9d hereinafter, flows through this inversion layer.
Therefore, such a problem occurs that the off-leak current increases to increase the standby current in a standby cycle during which MIS transistors are off. Particularly, in a semiconductor device for use in a battery-powered equipment such as a portable equipment, it is greatly required to reduce the off-leak current in view of a lifetime of the battery.
For reducing the off-leak current, absolute value Vth of the threshold voltage can simply be increased. In this case, however, reduction of the operation power supply voltage cannot achieve an intended effect, and fast operation cannot be ensured. Thus, an MT-CMOS (Multi-Threshold CMOS) structure has been proposed for reducing the off-leak current in the standby cycle and for ensuring fast operation.
FIG. 104 shows, by way of example, a structure of an MT-CMOS circuit in the prior art. In the structure shown in FIG. 104, five inverter circuits IV0-IV4 are cascaded. For these inverter circuits IV0-IV4, there are arranged a main power supply line MVL coupled to a power supply node, a sub-power supply line SVL coupled to main power supply line MVL via a switching transistor SWP, a main ground line MGL coupled to a ground node, and a sub-ground line SGL coupled to main ground line MGL via a switching transistor SWN.
Inverter circuits IV0-IV4 each have a structure of a CMOS inverter, and include P-channel MIS transistors P0-P4 and N-channel MIS transistors N0-N4, respectively. This MT-CMOS circuit has a standby cycle in a standby state and an active cycle in which an input signal changes actually. In the standby cycle, input signal IN is fixed to L-level, and switching transistors SWP and SWN are kept in the off state in response to control signals /xcfx86 and xcfx86, respectively. Each of switching transistors SWP and SWN has a threshold voltage relatively large (medium) in absolute value, M-Th. Each of MIS transistors P0-P4 and N0-N4 of inverter circuits IV0-IV4 has a threshold voltage of a small absolute value, L-Th.
Depending on a logical level of an input signal IN in the standby cycle, a source of each MIS transistor, which is on in the standby cycle, is connected to main power supply line MVL or main ground line MGL. More specifically, sources of MIS transistors P0, P2 and P4 are connected to main power supply line MVL, and sources of MIS transistors N1 and N3 are connected to main ground line MGL. A source of each MIS transistor, which is off in the standby cycle, is connected to sub-power supply line SVL or sub-ground line SGL. More specifically, sources of MIS transistors P1 and P3 are connected to sub-power supply line SVL, and sources of MIS transistors N0, N2 and N4 are connected to sub-ground line SGL. Now, an operation of the MT-CMOS circuit shown in FIG. 104 will now be described with reference to a signal waveform diagram of FIG. 105.
During the standby cycle, input signal IN is at L-level, and control signals xcfx86 and /xcfx86 are at L- and H-levels, respectively. In this state, switching transistors SWP and SWN are off. Switching transistor SWP is an M-Vth transistor, and the off-leak current thereof in the standby state cycle is small.
In inverter circuits IV0-IV4, MIS transistors P0, P2 and P4 are on, and therefore do not cause a sub-threshold leak (off-leak) current. Meanwhile, MIS transistors P1 and P3 are off, and cause an off-leak current from sub-power supply line SVL. The off-leak currents flowing through MIS transistors P1 and P3 flow to main ground line MGL through MIS transistors N1 and N3 in the on state, respectively. However, the off-leak current flowing through MIS transistors P1 and P3 depends in magnitude on the off-leak current flowing through switching transistor SWP. Therefore, the voltage level of sub-power supply line SVL reaches an equilibrium state where the off-leak current flowing through switching transistor SWP is balanced with the sum of off-leak currents flowing through MIS transistors P1 and P3. Due to the current flow, the voltage level of sub-power supply line SVL is lower than power supply voltage VCC, and MIS transistors P1 and P3 enters such a state that the gate to source thereof is reverse-biased, and therefore enters a deeper off state. Accordingly, MIS transistors P1 and P3 can have the off-leak currents sufficiently reduced.
Likewise, off-leak currents flow through MIS transistors N0, N2 and N4. These off-leak currents flowing through MIS transistors N0, N2 and N4 depend in magnitude on the off-leak current flowing through switching transistor SWN. Switching transistor SWN is an M-Vth transistor, and has a sufficiently small off-leak current so that the off-leak currents of MIS transistors N0, N2 and N4 can be sufficiently suppressed.
In the above case, the voltage level of sub-ground line SGL reaches an equilibrium state where the sum of off-leak currents flowing through MIS transistors N0, N2 and N4 are balanced with the off-leak current flowing through switching transistor SWN, and therefore is higher than ground voltage GND. In this case, each of MIS transistors N0, N2 and N4 enters such a state that the gate to source thereof is reverse-biased, and therefore enters a deeper off state. Accordingly, MIS transistors N0, N2 and N4 can have the off-leak current sufficiently suppressed.
In the active cycle for actually performing an operation, control signals xcfx86 and /xcfx86 are set to H- and L-levels, respectively, and switching transistors SWP and SWN are turned off. Responsively, sub-power supply line SVL is connected to main power supply line MVL, and sub-ground line SGL is connected to main ground line MGL. Inverter circuits IV0-IV4 include L-Vth transistors as components, and therefore, rapidly change their output signals in accordance with input signal IN.
As shown in FIG. 104, the power supply line differs in impedance value depending on the standby cycle and the active cycle. Thereby, even with the L-Vth transistors employed as its components, the off-leak current can be sufficiently suppressed in the standby cycle, while ensuring fast operation performance in the active cycle. Accordingly, a CMOS circuit capable of fast operation with low power consumption can be implemented.
Various parameters such as sizes of the MIS transistors are reduced according to a certain scaling rule. The scaling rule stands on the premise that the gate length of the MIS transistor and the thickness of the gate insulating film thereof are reduced at the same scaling ratio. For example, an MIS transistor having a gate length of 0.25 xcexcm (micrometers) generally has a gate insulating film of 5 nm (nanometers) in thickness, and therefore an MIS transistor having a gate length of about 0.1 xcexcm has a gate insulating film from about 2.0 to about 2.5 nm in thickness. In the case where the thickness of gate insulating film is reduced in accordance with lowering of the operation power supply voltage and is reduced to about 3 nm in accordance with the condition that the power supply voltage is 1.5 V or lower, for example, a tunnel current flows through the gate insulating film of MIS transistor in the on state, resulting in a problem of increase in power supply current of the transistor in the on state.
FIGS. 106A-106C schematically show energy bands of the MIS transistor, with the gate being a metal gate. Normally, in the MIS structure, a gate is formed of polycrystalline silicon doped with impurities and has properties as a semiconductor. For simplicity reason, however, it is here assumed that the gate is made of a metal. The semiconductor substrate region is of the P-type substrate (layer).
As shown in FIG. 106A, it is now assumed that a negative voltage is applied on the gate. In this state, holes present in the P-type substrate are pulled toward the interface between the substrate and the insulating film. Thereby, the energy band of the P-type substrate is bent upward at the interface between the insulating film and the P-type substrate, and a valence band Ev approaches a Fermi level EF. A conduction band Ec is bent upward at the vicinity of this interface. In this case of application of the negative voltage, Fermi level EF of the gate (corresponding to conduction band Ec in the case of a polycrystalline silicon gate) also rises. In this state, the density of majority carriers (holes) on the interface is higher than that in the inner portion. This state is called an accumulated state. In this state, the conduction band Ec is bent upward, and a barrier against electrons is high so that the tunneling current through the gate insulating film does not flow.
Where a low positive voltage is applied to the gate as shown in FIG. 106B, the Fermi level (conduction band) of the gate lowers so that conduction band Ec and valence band Ev are bent downward in the P-type substrate region at the interface with the insulating film. In this state, holes have been located away from the interface to the gate insulating film so that depletion of majority carriers occurs, and Fermi level EF on the interface is located substantially in the center of the band. This state, where a majority carrier is not present, is called a depletion state. In this depletion state, a carrier is not present on the interface, and a tunnel current does not occur.
When a further high positive voltage is applied as shown in FIG. 106C, Fermi level EF of the gate further lowers, and the band bending at the vicinity of the interface occurs to a larger extent. Consequently, Fermi level EF of the gate exceeds the intermediate value of energy gap Eg at the vicinity of the interface, and electrons which are minority carries are accumulated. This state is called an inverted state because the conduction type of the interface is inverted with respect to that of the interior. This state corresponds to the state where a channel is formed in the MIS transistor. If the gate insulating film has a thickness xcex4 of, e.g., 3 nm in this state, electrons which are minority carriers flow into the gate through a tunneling phenomenon. Thus, the tunnel current directly flows into the gate from the channel region in the MIS transistor having the channel formed and thus conductive. This tunnel current is called a (direct) gate tunnel current. Similar behaviors occur in a structure having an N-type substrate region, except for that a voltage applied to the gate has the opposite polarity and that the energy band bends in the opposite direction.
In MIS transistor, if the thickness of the gate insulating film is reduced, e.g., to 3 nm, a direct gate current flows from the channel region to the gate. Consequently, the MT-CMOS circuit such as that shown in FIG. 104 accompanies the following problem. In the standby cycle, a tunnel current flows from the channel region to the gate in an on state MIS transistor, and through-current finally flows from the power supply node to the ground node so that the current consumption in the standby cycle increases.
FIG. 107 shows a path of a tunnel current in the MT-CMOS circuit shown in FIG. 104 in the standby cycle.
FIG. 107 shows a structure of a portion including inverter circuits IV1 and IV2. In inverter circuit IV1, MIS transistor N1 has a source and a back gate connected together to main ground line MGL, and MIS transistor P1 has a source connected to a sub-power supply line (not shown). In inverter circuit IV2, MIS transistor P2 has a back gate and a source connected together to main power supply line MVL, and MIS transistor N2 has a source connected to a sub-ground line (not shown).
In the standby cycle, inverter circuit IV1 is supplied with a signal at H-level. Therefore, the output signal of inverter circuit IV1 is at L-level or the level of ground voltage GND in the standby cycle, and MIS transistor P2 in inverter circuit IV2 is on. In MIS transistor P2, a tunneling current It flows from the substrate region to the gate, and further flows to main ground line MGL through MIS transistor N1. As indicated by broken line in FIG. 107, the gate tunnel current of MIS transistor P2 causes a through current flowing from main power supply line MVL to main ground line MGL.
FIG. 108 shows a structure of a portion including inverter circuits IV2 and IV3 of the MT-CMOS circuit shown in FIG. 104. In the standby cycle, inverter circuit IV2 is supplied with a signal at L-level. The sources of MIS transistors P2 and N3 are connected to main power supply line MVL and main ground line MGL, respectively, while the sources of MIS transistors N2 and P3 are connected to the sub-ground line and sub-power supply line (both not shown in FIG. 108), respectively. In this state in the standby cycle, MIS transistor P2 is on, and supplies a current to the gate of MIS transistor N3 from main power supply line MVL.
MIS transistor N3 is on, and therefore gate tunnel current It flows through MIS transistor N3 (through the source region and the back gate region) to main ground line MGL. When the back gate of MIS transistor N3 is biased to a voltage level different from ground voltage GND, gate tunnel current It of MIS transistor N3 flows from this channel region through the source region. In this case, therefore, gate tunnel current It likewise causes a though current flowing from main power supply line MVL to main ground line MGL.
This gate tunnel current is nearly equal to the off-leak current when the gate oxide film has a thickness of about 3 nm or less. If the gate oxide film has a thickness smaller than about 3 nm, the gate tunnel current exceeds the off-leak current. Therefore, in the case where the operating power supply voltage is lowered and the thickness of gate insulating film is reduced according to the scaling rule, this gate tunnel current cannot be neglected and causes a problem of increase in current consumption in the standby cycle.
A gate tunnel current J approximately satisfies the relationship expressed by the following formula:
Jxcx9cExc2x7exp[xe2x88x92Toxxc2x7Axc2x7xcfx86], 
where xcfx86 represents a height of a barrier at the interface with the gate insulating film, and is approximately expressed by a difference between the Fermi level and the surface potential xcfx86s at the interface, A is a constant depending on an impurity concentration (an effective mass of an electron) of the semiconductor substrate in the channel region, and E represents an electric field applied to the gate insulating film. The barrier Height xcfx86 is a function of a dielectric constant xcex5i and thickness Tox of the gate insulating film. Therefore, if a tunnel current starts to flow at the gate oxide film thickness of 3 nm with the gate insulating film formed of silicon oxide, a gate tunnel current likewise flows through the gate insulating film, which provides a barrier equal to that by the silicon oxide film of 3 nm in thickness. As the gate insulating film, there is a silicon nitride oxide film, other than the silicon oxide film (silicon dioxide film).
As described above, with the miniaturized transistors as components, there arises a problem that the gate tunnel current of the MIS transistor becomes substantially equal to or larger than the off-leak current in the standby, and the current consumption in the standby cycle cannot be reduced.
An object of the present invention is to provide a semiconductor device, which can sufficiently suppress current consumption in the standby state, and is suitable to a high integration.
Another object of the present invention is to provide a semiconductor device, in which a gate tunnel current of an MIS transistor can be sufficiently suppressed in the standby state.
A semiconductor device according to the present invention includes: a first power supply node, a logic gate receiving a voltage on a first power supply line as one operation power supply voltage, for performing a predetermined operation, and a first switching transistor connected between the first power supply node and the first power supply line, and being selectively turned on in response to an operation mode instructing signal instructing an operation mode of the logic gate. The logic gate includes, as its components, an MIS transistor having a first gate tunnel barrier, and the first switching transistor has a gate tunnel barrier greater than the gate tunnel barrier of the MIS transistor of the logic gate.
According to a second aspect of the present invention, a semiconductor device includes a first MIS transistor connected between a first power supply node and a first output node and receiving an input signal on a gate thereof, and a second MIS transistor connected between the output node and a second power supply node and receiving the input signal on a gate thereof The first MIS transistor is turned on in accordance with the input signal in a standby cycle, and has a first gate tunnel barrier. The second MIS transistor is turned off in accordance with the input signal in the standby cycle, and has a gate tunnel barrier smaller than the first gate tunnel barrier.
According to a third aspect of the present invention, a semiconductor device includes a first MIS transistor connected between a first power supply node and a first output node and receiving an input signal on a gate thereof, a second MIS transistor connected between the first output node and a second power supply node and receiving the input signal on a gate thereof, and a control circuit for reducing leakage amounts of gate tunnel currents of the first and second MIS transistors in the standby cycle below those in an active cycle.
According to a fourth aspect of the present invention, a semiconductor device includes a first MIS transistor connected between a first power supply node and a first output node, having a first gate tunnel barrier and receiving an input signal on a gate thereof, a second MIS transistor connected between the first output node and a sub-power supply node, receiving the input signal on a gate thereof to be turned on complementarily to the first MIS transistor, and a first switching transistor connected between the sub-power supply node and a second power supply node and being selectively turned on in response to an operation cycle instructing signal. The second MIS transistor has a second gate tunnel barrier smaller than the first gate tunnel barrier.
According to a fifth aspect of the present invention, a semiconductor device includes a first switching transistor connected between a power supply node and a power supply line and being selectively turned on in response to an operation cycle instructing signal, a gate circuit receiving a voltage on the power supply line as one operation power supply voltage, for performing a predetermined processing, a replica circuit including elements formed by proportionally scaling down the gate circuit and the first switching transistor, and a transmitting circuit for transmitting an output voltage of the replica circuit to the power supply line in accordance with the operation cycle instructing signal. The scaled down gate circuit of the replica circuit receives the voltage on the output node as one operation power supply voltage, and the scaled down transistor of the first switching transistor supplies a voltage from the power supply node to the output node.
According to a sixth aspect of the present invention, a semiconductor device includes a first switching transistor connected between a first power supply node and a first power supply line and being selectively turned on in response to an operation cycle instructing signal, a first gate circuit receiving a voltage on the first power supply line as one operation power supply voltage, a second switching transistor connected between a second power supply node and a second power supply line, and being selectively turned on in response to the operation cycle instructing signal, and a second gate circuit receiving a voltage on the second power supply line as one operation power supply voltage. The first and second gate circuits include MIS transistors as their components, and have the same structure.
According to a seventh aspect of the present invention, a semiconductor device includes a gate circuit including first and second transistors each having an SOI (Silicon On Insulator) structure, and effecting predetermined processing on an input signal for outputting, and a bias voltage applying circuit for applying a bias voltage to body regions of the first and second transistors of the gate circuit. The input signal applied to the gate circuit is at a predetermined logical level in a standby cycle, and each of first and second transistors has a gate insulating film having a thickness not exceeding 3 nanometers. The bias voltage applying circuit sets a bias of the body region of at least the transistor in the off state out of the first and second transistors in the standby cycle to be deeper than that in an active cycle.
According to an eighth aspect of the present invention, a semiconductor device includes a gate circuit including first and second MIS transistors each having an SOI (Silicon On Insulator) structure, and effecting a predetermined logical processing on an input signal for outputting, and a bias voltage applying circuit for applying a bias voltage to body regions of the first and second MIS transistors. The bias voltage applying circuit sets biases of the body regions of the first and second transistors to be deeper in the standby cycle than those in an active cycle.
According to a ninth aspect of the present invention, a semiconductor device includes a first MIS transistor connected between a first power supply node and an output node and receiving an input signal on a gate thereof, and a second MIS transistor connected between the output node and a second power supply node and receiving the input signal on a gate thereof. A logical level of the input signal in a standby cycle is predetermined, and the first MIS transistor is turned on in accordance with the input signal in the standby cycle, and is formed of an MIS transistor of a buried channel type.
According to a tenth aspect of the present invention, a semiconductor device includes a first MIS transistor connected between a first power supply node and an output node and receiving an input signal on a gate thereof, and a second MIS transistor connected between an output node and a second power supply node and receiving the input signal on a gate thereof. The logical level of the input signal in a standby cycle is predetermined, and the first MIS transistor is turned on in response to the input signal in the standby cycle, and is an MIS transistor of a depleted gate type.
According to an eleventh aspect of the present invention, a semiconductor device includes a latch circuit for latching an applied signal, and a gate circuit for effecting a predetermined processing on a latch output signal of the latch circuit. The latch circuit is formed of an MIS transistor having a first gate tunnel barrier. The gate circuit is formed of an MIS transistor having a gate tunnel barrier smaller than the first gate tunnel barrier.
According to a twelfth aspect of the present invention, a semiconductor device includes a first latch circuit for latching an applied signal in an active cycle, a second latch circuit for latching an applied signal in a standby cycle, and a transfer circuit transferring a latching signal of the first latch circuit to the second latch circuit in response to transition of an operation cycle instructing signal from an active cycle instruction to a standby cycle instruction, and transferring a latching signal of the second latch circuit to the first latch circuit in response to transition of the operation cycle instructing signal from the standby instruction to the active cycle instruction. The first latch circuit has a first gate tunnel barrier, and the second latch circuit has a gate tunnel barrier larger than the first gate tunnel barrier.
According to a thirteenth aspect of the present invention, a semiconductor device includes a precharge transistor for precharging a precharge node to a predetermined voltage level in response to activation of a precharge instructing signal, and a gate circuit coupled to the precharge node, being in a standby state in an active state of the precharge instructing signal, and driving the precharge node in accordance with an applied signal in an inactive state of the precharge instructing signal. The precharge transistor has a first gate tunnel barrier, and an MIS transistor of the gate circuit has a second gate tunnel barrier greater than the first gate tunnel barrier.
According to a fourteenth aspect of the present invention, a semiconductor device has a precharge transistor being activated to precharge a precharge node to a predetermined voltage for a predetermined time upon transition from a standby cycle to an active cycle, and a gate circuit for driving the precharge node in accordance with an applied signal in the active cycle. The gate circuit has the same, first gate tunnel barrier as the precharge transistor. The first gate tunnel barrier has a height equal to or greater than that of a gate tunnel barrier provided by a silicon oxide film of 3 nm in thickness.
According to a fifteenth aspect of the present invention, a semiconductor device includes a plurality of memory cells requiring refresh of storage data, a timer circuit being activated in a refresh mode to generate a refresh request instructing refreshing of the stored data of the plurality of memory cells at predetermined intervals, a refresh address counter for generating a refresh address specifying a memory cell row of the plurality of memory cells to be refreshed, and refresh-related circuitry for refreshing the stored data of the memory cells specified by the refresh address among the plurality of memory cells. The timer circuit and the refresh address counter include MIS transistors having a first gate tunnel barrier as components, and the refresh-related circuitry includes, as a component, an MIS transistor having a second gate tunnel barrier of a height not exceeding that of the first gate tunnel barrier.
According to a sixteenth aspect of the present invention, a semiconductor device includes a logic circuit including an insulated gate field effect transistor as its component, a latch circuit provided corresponding to an internal node of the logic circuit for latching a signal on the corresponding internal node, and a transfer path coupled to the latch circuit for transferring the signal of the latch circuit. At least the logic circuit is set to a state of having a gate tunnel current reduced in a standby state.
According to a seventeenth aspect of the present invention, a semiconductor device includes a plurality of internal circuits formed of MIS transistors, and performing predetermined operations when made active, an activation control circuit responsive to an internal circuit designating signal designating an internal circuit to be activated among the plurality of internal circuits for generating an internal circuit activating signal for activating the designated internal circuit, and a current control circuit responsive to an operation mode instructing signal and the internal circuit activating signal for holding a gate tunnel current of the MIS transistor of the internal circuit in the inactive state among the plurality of internal circuits to be smaller than that of the MIS transistor of the internal circuit in the active state. The operation mode instructing signal designates an active cycle of enabling the plurality of internal circuits and a standby cycle of disabling the plurality of internal circuits.
According to an eighteenth aspect of the present invention, a semiconductor device includes a normal array having a plurality of normal memory cells, a redundant array having spare memory cells for repairing a defective normal memory cell having a defect in the normal array, a normal access circuit for accessing a selected memory cell in the normal array, a spare access circuit for accessing a spare memory cell in the redundant array, and a power supply control circuit for determining a gate tunnel current of an MIS transistor of the inactive circuit out of the spare access circuit and the normal access circuit to be smaller than the gate tunnel circuit of the MIS transistor of the active circuit.
If a gate tunnel current may occur in an MIS transistor, measures are taken for the MIS transistor, e.g., of increasing the height of the gate tunnel barrier or cutting off the current flowing path. For the MIS transistors through which the gate tunnel current may not occur, MIS transistors having sizes reduced according to a scaling rule is used. Owing to these measures, the semiconductor device which can operate fast with low current consumption can be implemented.
When the circuit is to be disabled, the gate tunnel current of the MIS transistor forming the circuit is reduced, or the power supply voltage is powered down. Thereby, the current consumption of the disabled circuit can be reduced, and the semiconductor device operating with low current consumption can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds