As is well known in the art, an electronic semiconductor power device, such as power supply, amplifier and similar devices, includes an output stage which is used for driving an electric load. The load is often an inductive one, and is connected to the output terminal of the power device.
Typically, the power output stage is monolithically integrated in a portion of a semiconductor material which is isolated by a peripheral "barrier" well. This barrier well functions to block or restrict electric current that flows between wells adjacent to or contiguous with the barrier well, under certain critical conditions of the circuit operation.
An output stage of this kind would usually include an isolated vertical final transistor of the PNP type.
Shown in FIG. 1 is a vertical section view, not drawn to scale, of a semiconductor material chip, usually of monocrystalline silicon, having an output stage integrated therein which includes a vertical PNP transistor as is known in the art. The semiconductor material substrate of the P type is denoted by 1. The epitaxial layer of the N type is there denoted by 2 as a whole. This epitaxial layer 2 includes a predetermined number of wells, with three such wells, 2', 2" and 2'", separated by isolation regions 3 of the P type shown by way of example. Well 2" is divided into two sides, 2"a and 2"b, as shown. The wells 2', 2" and 2'" extend from the substrate to a surface 4 of the chip. The vertical transistor of the PNP type is integrated in one of the wells, specifically well 2'. This PNP transistor forms the final transistor of the output stage. Indicated outside the well 2', on the left-hand side thereof in FIG. 1, are circuit portions that are formed in the layer 2 and are external to the output stage.
The structure of the PNP transistor includes a buried layer 5 of the N+ type formed at the interface between the substrate 1 and the epitaxial layer 2, and contained within the well 2'. Formed over the buried layer 5 is a first buried collector region 6, of the P type, which is connected to the surface 4 by a second collector region 7, also of the P type, which is annular in shape and extends vertically in FIG. 1 from the region 6 to the surface 4. The perimeter formed by the collector region 7 may have any shape, such as a circle, square, rectangle, triangle, etc. The collector regions 6 and 7 bound and enclose a base region 8 of the N type which is, therefore, isolated both laterally and downwardly. Within this base region 8, an emitter region 9 of the P type is provided. FIG. 1 also shows collector, base and emitter contacts, respectively denoted by C, B and E. The well 2' containing the transistor is also connected to that collector through a contact C1. The transistor collector C is connected, within the output stage, to an output terminal OUT; emitter E is connected to a supply terminal Vcc being applied thereto a constant supply voltage, typically +V; and base B to a driver terminal D of the transistor itself, being connected to a driver circuit not shown in FIG. 1.
Also shown in FIG. 1 is a barrier well 10 of the kind conventionally employed in the art. The barrier well 10 comprises, in particular, a region of the N+ type which is heavily doped and, accordingly, has a low resistance value. As can be seen in FIG. 1, the barrier well is formed inside N-type well 2", between the two sides 2"a and 2"b, and adjacent to the well 2', which contains the PNP transistor.
Region 10 includes an N+ region 110, that is formed as part of the layer 5. Also, the well 2'" includes an N+ contact region 112 that is typically coupled to either ground or the Vcc terminal.
To make the geometric arrangement of the barrier well 10 more clearly understood, FIG. 2 shows a top plan view of a chip portion which contains the output stage. The output stage is generally and schematically represented by a block 11. The barrier well 10 surrounds the output stage 11 and is enclosed by the sides 2"a and 2"b of the well 2". The barrier well 10 is schematically depicted as an uninterrupted square for simplicity, although as stated above, the barrier well 10 may have another shape.
The barrier well 10 would usually be connected to the supply terminal Vcc, as shown in FIGS. 1 and 2, by contacts S. A single contact S is shown in FIG. 2 for simplicity.
The barrier well 10 provided is quite effective under critical conditions of operation, especially where the voltage at the output terminal OUT drops below ground potential. This may happen, for instance, where the load is an inductive one, and during the circuit operation, transient conditions are established on the load. These being conditions of the potential which can trigger parasitic currents between the output stage and outside regions, the connection of the barrier well 10 to a constant supply voltage +V via terminal Vcc is effective to create a preferential current flow path. That is, the barrier well 10 allows current to be drawn from the supply terminal Vcc but not from parts of the integrated circuit which are external of the output stage 11.
For such arrangements, a trend in the art presently favors the manufacturing of devices that are substantially indestructible even when their terminals are incorrectly connected by a user.
The most frequently occurring mistakes, in the context of devices used in audio and industrial power applications, for example, are shown in FIGS. 3a and 3b. Shown schematically in FIGS. 3a and 3b is a power output stage of the kind discussed above, which comprises a PNP transistor, designated T. The block DRIVER generally represents a driver circuit for the transistor T, and is connected to a control terminal, specifically the base terminal D, of the transistor T. Respectively designated OUT and Vcc are the output and supply terminals, like in FIGS. 1 and 2.
In FIG. 3a, the output terminal OUT has been mistakenly connected to the supply voltage +V, and the supply terminal Vcc to ground. FIG. 3b differs from FIG. 3a by the supply terminal Vcc being left unconnected. More precisely, Vcc is connected to a capacitor C1 in FIG. 3b. This is the filter capacitor that would anyhow be present at the supply terminal Vcc. Prior to using the device, i.e. at the time of connecting its terminals, this capacitor is still uncharged, and has been schematically depicted as connected to ground.
In these two typical instances of wrong connection of the device, for an output stage having a barrier well as described above, the barrier well itself may be instrumental to trigger a destructive latch-up phenomena within the output stage.
With reference to FIGS. 3a and 3b, it can be seen that the circuit DRIVER, being connected between the base and the emitter of the transistor T and having an amount of impedance, in the arrangement shown would drive the transistor into a reverse configuration, that is with the collector exchanged for the emitter. In addition, when the voltage applied by mistake between the base and the emitter exceeds the breakdown voltage value of the base/emitter junction, the transistor T is also turned on in reverse.
What can happen to the integrated output stage of the type shown in FIG. 1 is depicted in FIG. 4. FIG. 4 illustrates incorrect connections of the output stage terminals. Also, a first parasitic transistor of the PNP type is shown at T1. The base of T1 is represented by the well 2', whereas the potential +V is present; its emitter is coincident with the collector 6 and 7 of the final PNP transistor of the output stage; and its collector is the substrate 1, and has an associated resistance collector. A second parasitic transistor T2 of the NPN type is linked to the first into a configuration commonly referred to as an SCR (Silicon Controlled Rectifier). Its base is connected to the collector of the first transistor T1, its collector to the base of T1, and its emitter is the barrier well 10. The base resistance R.sub.base of transistor T2, and the substrate resistance R.sub.substrate, are also shown. The other parasitic resistances are omitted for clarity.
In the case of the wrong connection shown in FIG. 4, with the final transistor being operated in the reverse mode as mentioned, the parasitic transistor T1 may be turned on to inject a current into the substrate 1 and raise its potential. Thus, the barrier well 10 becomes the emitter of the second parasitic transistor T2, thereby allowing it to be turned on. The transistor T1, in turn, continues to be active due to the current from the collector of T2. The process is a self-supporting one, and may result in large currents being conducted through the output stage, and in the phenomenon known as latch-up, with likely destruction of the device.
USPTO Backgrounds
USPTO Backgrounds