The present invention relates to frequency synthesizers and direct modulation, more particularly to phase locked loops, and even more particularly to phase detectors for use in a phase locked loop and exposed to interfering signals placed close to frequencies which are multiples of the reference frequency of the phase locked loop (“PLL”).
PLLs are well known and are useful for generating oscillating signals in many types of circuits, including but not limited to radio circuitry. In digital communication systems, for example in mobile telephone communications operating under the Global System for Mobile Communications (GSM) or Digital Communication Systems (DCS) systems, PLLs may be employed to effect continuous phase modulation (CPM) of a carrier signal. One example of such a PLL system is found in U.S. patent application Ser. No. 09/580,632, entitled “Linear Dead-Band-Free Digital Phase Detection,” the contents of which are hereby incorporated herein by reference in their entirety.
FIG. 1 is a block diagram of a conventional integer-divide PLL 100. A phase detector 101 compares the phase of a signal supplied by a reference oscillator 103 with the phase of a feedback signal supplied by a frequency divider 105. The output of the phase detector, which represents the phase difference between the two input signals, is filtered by a filter 107. The filtered output is then used to control the frequency of an output signal generated by a voltage controlled oscillator (VCO) 109. The output signal from the VCO 109, in addition to being supplied as an output from the PLL, is also supplied as an input to the frequency divider 105, and is thus the source of the feedback signal. The PLL 100 is governed by the following equations:                                           i            e                    =                                    K              P                        ⁡                          (                                                φ                  R                                -                                                      φ                    o                                    N                                            )                                      ⁢                                  ⁢                                            φ              o                        =                                          i                e                            ⁢                              Z                ⁡                                  (                  s                  )                                            ⁢                                                           ⁢                                                K                  V                                s                                              ,                                    (        1        )            where s, KP, Z(s), and KV are the complex frequency, phase detector gain, loop-filter trans-impedance, and VCO gain, respectively, and φR, φ0, and ie, are the reference phase (or frequency as 2πf=s*φ), the VCO phase, and the phase-detector error current, respectively.
Solving the above equations for φ0 yields the well-known result that fo=N·fR, that is, the VCO frequency is an integer multiple of the reference frequency.
Since the loop response time to a change in N (e.g., when a new channel is selected) is proportional to 1/fR (i.e., it takes a certain number of reference cycles to settle) and the minimum channel spacing equals fR, there is a conflict in the choice of reference frequency. That is, it would be desirable to set a low value for fR to reduce the minimum channel spacing. However, such a setting would result in a larger loop response time, which is undesirable.
To get around the above restriction on channel spacing, fractional-N PLLs have been devised. By employing a variable-modulus divider, rather than an integer divider, it is possible to achieve more flexible divide ratios. For example, performing three successive divisions by 20 followed by one division by 21 results in an average division factor of (3·20+21)/4=20.25 and a channel spacing of fR/4. Due to the repetitive nature of this variable modulus division, however, spurious tones will be generated (here at fo±n·fR) that will modulate the VCO.
A transmitter structure called a “Direct Modulation architecture” (transmitter and Local Oscillator synthesizer) is based on the concept of using a Sigma-Delta controlled fractional-N PLL for generating a modulated GSM spectrum at radio-frequency (RF). The output RF signal of the PLL in a highly integrated Direct Modulation architecture has a tendency to leak back to the reference parts of the PLL, such as the phase detector. When this leaking RF signal is mixed with the original wanted baseband signal in the phase detector, a problem arises in that the signal generated at the output of the PLL includes spurious spectral components at N times the reference frequency, where N equals an integer. Furthermore, any PLL exposed to an unwanted RF interferer placed at frequencies close to multiples of the reference frequency will experience problems with spurious spectral components at N times the reference frequency.
Consequently, it is desirable to provide a PLL that will reduce the problem of having N times the reference frequency spurious spectral components around the RF spectrum when using a Sigma-Delta controlled fractional-N PLL as a modulator or frequency synthesizer.
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