This invention relates to calculators and more particularly to calculators having a power consumption controller. Power consumption control is a twofold advancement over the integrated on switch of the calculators described in U.S. Pat. No. 4,115,705, which is assigned to the assignee of the present invention. In such calculators, live power is provided only to the logic necessary to detect a predetermined voltage level on a selected input line, that would then turn on a large device that would switch power to the remainder of the chip.
The integrated circuit chip provided in the calculator of the present invention is an improvement over the calculator integrated circuit chip of U.S. Pat. No. 4,115,705 utilizing a CMOS metal gate process to produce a low power chip capable of operation in a LCD calculator, for example, the Texas Instruments TI 50 Calculator, for at least 1000 hours per battery. Additionally, the present chip is an improvement over the calculator integrated chip of the co-pending application Ser. No. 252,096, now U.S. Pat. No. 4,361,873, filed Apr. 8, 1981, which is a continuation of Ser. No. 47,431, filed June 11, 1979, now abandoned, by Harper et al, for "Calculator with Constant Memory", assigned to the assignee of the present invention. The constant memory chip of that application has the capability of communicating with an external standard off the shelf CMOS RAM chip so as to implement an LCD INSTANT REPLAY calculator. Because of the low stand-by power required to keep the external CMOS RAM on live power, it would be acceptable to leave it on live power and not switch its power. On-chip static CMOS RAM and associated circuitry is also connected to live power to achieve a semi-non-volatile on-chip constant memory.
To maintain live power on the external RAM chip and the on-chip static RAM, live power can be run to the digit latches and R-line drivers (I/O lines), Chip Select, and Read/Write lines which control the external semi-non-volatile constant memory. Data maintained for the length of the battery life.
In effect, by running a switched negative voltage (SV.sub.SS) and a non-switched (or live) negative voltage (LV.sub.SS) to the appropriate P (-) wells of the CMOS chip, the power consumptive clocked logic (for example, ROM Page Register, ROM, ALU, oscillator, clock, etc.) may be turned off while power is maintained on the internal static RAM, RAM Write Logic, Digit latches, and R-lines. In this embodiment an internal and external semi-non-volatile CMOS memory (constant memory) and a display interface such as described in U.S. Pat. No. 4,264,963, granted Apr. 28, 1981 to J. G. Leach for "Static Latches For Storing Display Segment Information" assigned to the assignee of the present invention may be achieved without exceeding a specified OFF (or standby) current.
USPTO Backgrounds
USPTO Backgrounds