1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an improved interconnection fabricating method for a semiconductor device.
2. Discussion of the Related Art
In general, a multi-layer photoresist forming technique for an interconnection fabricating method for a semiconductor device is concerned with fine interconnection patterns of less than 0.25 .mu.m in thickness. In particular, an irregular surface of a lower layer is prevented by forming a first photoresist layer for planarization of a thick layer to facilitate an exposure process and improve its margin by forming a second photoresist layer.
FIGS. 1A through 1D are cross-sectional views illustrating a conventional interconnection fabricating method for a semiconductor device using a multi-layer photoresist technique.
As shown in FIG. 1A, an interconnection layer 13 is formed on a semiconductor substrate 11. A first photoresist layer 15 is formed on the interconnection layer 13 for planarization, and a hard bake step is carried out.
In FIG. 1B, an insulation layer 17 serving as an intermediate mask is formed on the first photoresist layer 15. A second photoresist pattern 19a is formed having a thickness of less than 0.4 .mu.m on the insulation layer 17.
As shown in FIG. 1C, using the photoresist pattern 19a as a mask, the insulation layer 17 and the first photoresist layer 15 are dry-etched to form an insulation layer pattern 17a and a first photoresist layer pattern 15a. A hard bake step is then carried out. The photoresist layer pattern 19a is removed while the insulation layer 17 and the first photoresist layer 15 are etched. The hard bake step is performed to reinforce adhesion between the first photoresist layer 15 and the interconnection layer 13.
Referring to FIG. 1D, the insulation layer pattern 17a is removed using a wet etching method with a buffered oxide etchant (BOE), and the interconnection layer 13 is etched using the first photoresist layer pattern 15a as a mask to form a fine interconnection layer pattern 13a. The first photoresist layer pattern 15a is then removed.
However, the conventional method using a multi-layer photoresist structure has several disadvantages.
First, when the intermediate insulation layer pattern 17a is removed using a wet etching method, an additional buffered oxide etchant (BOE) container, such as a bath or a chamber, is required, increasing production cost.
Second, when the insulation layer pattern 17a is wet-etched, a lifting of the first photoresist layer pattern 15a occurs, and an additional hard bake step needs to be done prior to the wet etching step, complicating the manufacturing process.
Third, the wet etching method applied to the insulation layer pattern 17a requires a multi-step process including a BOE application, a DI-rinse (de-ionized water rinse) and a spin dry, requiring a longer processing time.
USPTO Backgrounds
USPTO Backgrounds