1. Field of the Invention
The present invention relates to a variable length decoding method and device operable to decode variable-length-encoded image data.
2. Description of the Related Art
As a system which performs encoding and decoding for motion picture data using a bandwidth compression technology, there are MPEG-2 and MPEG-4 systems standardized by MPEG (Moving Picture Experts Group) of ISO, and H.263 system recommended by ITU-T (International Telecommunication Union-Telecommunication Standardization Sector).
These systems are based on use of intra-picture correlation and inter-picture correlation of the motion picture. A picture is divided into blocks each of which is composed of several pixels, and data in the blocks are transformed by discrete cosine transformation (abbreviated as DCT), which is one of the orthogonal transformation methods. Then, quantization and variable-length-code encoding (abbreviated as VLC encoding) is performed, thereby, attaining highly-compressed encoding of the picture data.
The VLC encoding performs coding by assigning a unique code to a combination (Last, Run, Level) of the DCT coefficients obtained as a result of DCT, where “Run” means the number of preceding zero coefficients, “Level” means the value of a non-zero coefficient, and “Last” means whether the non-zero coefficient is the last one or not. In assigning codes, shorter codes are assigned to combinations (Last, Run, Level) with high frequency of appearance, thereby coding of a high compressibility is realized. In these coding systems, variable length code tables are specified in order to assign unique codes to all of the combinations (Last, Run, Level).
The VLC encoded data is decoded at high speed using a variable-length-code decoding table which is reversely generated from the variable length code table. What is posed as a problem in the decoding is how to store the variable-length-code decoding table.
Document 1 (Published Japanese patent application No. H09-185548) discloses a memory controlling method including storing a variable-length-code decoding table to a cache memory in variable length decoding processing.
FIG. 21 is a block diagram illustrating the conventional cache memory controller, which the Document 1 discloses. The cache memory controller shown in FIG. 21 comprises a control circuit (CONTROL) 1, an instruction memory (IMEM) 2, CPU 3, a data bus 6, a data memory (DMEM) 7, a first data cache (DCACHE) 8, a second data cache (DCACHE) 9, a selector 10, and a selector 11. CPU 3 includes a part of a register file (REG) 4, an arithmetic-logic circuit (ALU) 5, and a control circuit 1. The first data cache 8 and the second data cache 9 are memories operable to read/write data at high speed, and perform an exchange of data from and to the register file 4 and the arithmetic-logic circuit 5, via the selector 11 and the data bus 6. In the conventional cache memory controller shown in FIG. 21, a variable-length-code decoding table is stored in the first data cache 8 and the second data cache 9, thereby performing the decoding processing.
In the conventional cache memory controller, the decoding processing is performed using the variable-length-code decoding table stored in the cache memories. Therefore, each time when decoding data with different variable length coding standards, it is necessary to replace the contents of the cache memory with the variable-length-code decoding table of the standard concerned. Cache memory is a memory of a small capacity and cannot store all the variable-length-code decoding tables. Therefore, when there are no data needed at the time of decoding on the cache memory, the so-called cache error occurs and replacement processing becomes necessary for newly storing other portions of the variable-length-code decoding table to the cache memory.
Thus, the conventional cache memory controller has to solve subjects such as the increase in the processing amount resulting from the replacement processing of the variable-length-code decoding table, and the accompanying increase in the power consumption thereof.
USPTO Backgrounds
USPTO Backgrounds