1. Technical Field
This patent application relates generally to integrated circuit (IC) packaging technology and, in particular, but not by way of limitation, to leadless IC packages having high density contacts and related methods of manufacture.
2. Background
IC packaging is one of the final stages involved in the fabrication of IC devices. During IC packaging, one or more IC chips are mounted on a package substrate, connected to electrical contacts, and then coated with an encapsulation material comprising an electrical insulator such as epoxy or silicone molding compound. The resulting structure, commonly known as an “IC package,” may then be mounted onto a printed circuit board (PCB) and/or connected to other electrical components.
In most IC packages, the IC chip is completely covered by the encapsulation material, while the electrical contacts are at least partially exposed so that they can be connected to other electrical components. In other words, the electrical contacts are designed to form electrical connections between the IC chip inside the package and electrical components outside the IC package. Oftentimes, using a metal leadframe (LF) to form part of the IC package may be more cost effective than using a laminated board or tape material because, for example, more cost effective materials may be used, such as copper, nickel, or other metals or metal alloys, and use of such materials may allow more cost effective manufacturing processes to be employed, such as stamping or etching rather than multi-step laminate processes. One of the most common designs for these electrical contacts is one in which they form “leads” extending out from the sides of the encapsulating material. The leads typically are bent downward to form connections with electrical components on a PCB.
Oftentimes, the presence of external leads tends to significantly increase the size of IC packages. For instance, it may increase the length and width across the IC packages due to the horizontal extension of the leads. This increased size can be disadvantageous in systems where PCB space is limited. In addition, because the external leads are typically arranged along the sides of the IC packages, the pin count of the IC packages is limited by the linear distance around the IC packages. Another disadvantage is that these leads require an additional inspection step for straightness, co-planarity, and other required mechanical dimensions (and rework or scrap if they fail the specification). Finally, the leads (starting from the bonding fingers down to the tip of the external portions) add to the total electrical signal length (bond wires+leads), which may affect the electrical performance of the IC package.
Recognizing these and other problems with conventional IC packages, researchers have developed IC packages in which the external leads are replaced by electrical contacts that are covered on top by the encapsulating material but exposed on the bottom of the IC package so they can be connected to electrical components located beneath the IC package. These IC packages, referred to as “leadless” IC packages, tend to occupy less space compared with conventional IC packages due to the absence of the external leads. In addition, these IC packages eliminate the need to bend the leads to form connections. Some examples of conventional leadless IC packages are disclosed in U.S. Pat. Nos. 6,498,099 and 7,049,177, the respective disclosures of which are hereby incorporated by reference. Among other things, these patents describe and illustrate design variations for leadless IC packages and various techniques for manufacturing and using the leadless IC packages.
An example of a leadless IC package can be seen in FIGS. 1A and 1B. FIG. 1A is a bottom view of an IC package 100 having a die attach pad (DAP) 102 with an IC chip 104 mounted on a top surface thereof (shown as a dashed line in FIG. 1A). A plurality of contact points 106 can be seen disposed around an outside perimeter of the DAP 102. The contact points 106 may be utilized to provide contact points for electrically connecting the IC chip 104 and a PCB when the IC package 100 is mounted onto the PCB. An encapsulation compound 108 may be interposed between the DAP 102 and the plurality of contact points 106, for example, to isolate the contact points 106 from the DAP 102. FIG. 1B is a side view of a cross-section of the IC package 100 of FIG. 1A along line A-A. The IC chip 104 may be attached to the DAP 102 using a conductive epoxy 110. Wire bonds 112 may be utilized to form electrical connections from the IC chip 104 to a plurality of bonding points 116 on terminals which are electrically isolated from the DAP 102. Wire bonds 114 may be utilized to form electrical connections from the IC chip 104 to a plurality of bonding points 118 which may not be electrically isolated from the DAP 102. Because the contact points 106 are isolated from the DAP 102, the contact points 106 may be utilized to pass signals to and from the PCB (not shown) and the Input/Output (I/O) ports on the IC chip 104. Because the DAP bonding points 118 are not electrically isolated from the DAP 102 or from other DAP bonding points 118, these electrical connections can be used only to ground the IC chip 104.
One limitation of this type of leadless IC package is that the maximum number of terminals that can be utilized to pass electrical signals to and from the I/O ports of the IC chip is limited to the number of terminals that can be located around the perimeter of the DAP. As can be seen in FIG. 2, attempts have been made to increase the number of terminals available for electrical connection with the I/O ports of the IC chip, including decreasing the distance between the terminals in order to fit more terminals around the perimeter of the DAP and increasing the number of rows of terminals disposed around the perimeter of the DAP. However, increasing the number of rows of terminals requires either decreasing the size of the IC chip or increasing the size of the IC package. Additionally, the amount the distance between the terminals can be reduced is limited to the minimum distance between connection points on the PCB, which is relatively large.
USPTO Backgrounds
USPTO Backgrounds