A memory device having a three-dimensional structure has been proposed in which memory holes are made in a stacked body in which insulating layers are multiply stacked alternately with conductive layers that function as control gates of memory cells, and silicon bodies used to form channels are provided on the side walls of the memory holes with a charge storage film interposed between the silicon bodies and the side walls. In such a device, a peripheral circuit also is formed in the same chip as the memory cell array. There are various proposals for the resistance element structure of the peripheral circuit.
USPTO Backgrounds
USPTO Backgrounds