1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a divided bit line structure.
2. Description of the Related Art
A semiconductor memory device of large memory capacity contains a correspondingly large number of memory cells connected to bit lines. However, using a large number of memory cells has the effect of causing a large stray capacitance around the bit lines, which impedes the data read operation to the memory cells.
To cope with such data read retardation, there has recently been developed a semiconductor memory device having a divided bit line structure as shown in FIG. 1. In the memory device of FIG. 1, sense amplifier 11 is connected at both ends to a pair of main bit lines B11 and B12. The paired main bit lines are respectively connected through transfer switches S11 and S12 to paired divided bit lines BS11 and BS12, and through transfer switches S13 and S14 to paired divided bit lines BS13 and BS14. Transfer control line T11 is connected to switches S11 and S12, which are for controlling data transfer between paired main bit lines B11 and B12 and paired divided bit lines BS11 and BS12, and transfer control line T12 is connected to switches S13 and S14, which are for controlling data transfer between paired main bit lines B11 and B12 and paired divided bit lines BS13 and BS14. When transfer control line T11 is energized, switches S11 and S12 are turned on to electrically connect main bit lines B11 and B12 to paired divided bit lines BS11 and BS12, respectively. When transfer control line T12 is energized, switches S13 and S14 are turned on to electrically connect main bit lines B11 and B12 to paired divided bit lines BS13 and BS14, respectively.
Paired divided bit lines BS11 and BS12 are coupled with memory cells C11 and C12, while paired divided bit lines BS13 and BS14 are coupled with memory cells C13 and C14.
When one of word lines W11 to W14 is selected, the memory cells connected to the selected word line are driven so that data stored in the driven memory cells is transferred to the divided bit line. When the control line of a switch connecting a divided bit line to a related main bit line is selected, the data on the divided bit line is transferred to the main bit line. The data of the selected memory cell appears in the form of a minute potential difference between the paired main bit lines B11 and B12, and by amplifying the potential difference, by means of sense amplifier 11, the logical state of the data, viz., "1" or "0", can be determined.
Since the memory cells in a column of such a divided bit line system ar allotted to a plurality
e of divided bit line pairs, the number of memory cells connected to one pair of divided bit lines can be reduced, to cause a corresponding reduction in the stray capacitance around main bit line pair B11, B12, and an increase in the rate at which data can be read.
In the divided bit line system, however, a minute amount of charge from the memory cell is distributed among the divided bit line and the main bit line, so that an amount of charge transferred from the memory cell to the main bit line is extremely small. Therefore, if main bit lines are too long, a desired data transfer rate cannot be obtained. Thus, the divided bit line system can not use a long main bit lines and consequently the number of divided bit line pairs which can be connected to the paired main bit lines is limited.
An additional disadvantage of the conventional divided bit line system is that a large chip area is required for the bit line wiring, because the divided bit line pair and the main bit line pair must be provided for the memory cells in one column of the memory cell array.
USPTO Backgrounds
USPTO Backgrounds