1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor chips, and more particularly to a structure and novel methodology for fabricating a reliable, dimensionally accurate, high-integrity Ball Limiting Metallurgy (BLM) without undercut in Back-End-Of-Line (BEOL) semiconductor chip processing.
2. Description of the Prior Art
Controlled Collapse Chip Connection (C4) processes are well known in forming solder bumps in back-end-of line semiconductor fabrication, e.g., when chips are connected to their packaging. Typically, the formation of a C4 solder bump includes the conventional formation of a metallurgical system that includes the underlying final metal layer (pad), an under “bump” or Ball Limiting Metallurgy (BLM) and the solder ball. The BLM ideally should provide good adhesion to a wafer passivation and to the IC final metal pad, and, function as an effective solder diffusion barrier.
The drive to Lead-reduced and lead-free C4 processing together with reduced-pitch requirements limit the extendibility of current electroetch BLM technology, which routinely produces a final structure in which the baselayer BLM films (Ti, Cu) are dimensionally inset or “undercut” with respect to the outer dimension of the C4 solder ball. A typical process BLM structure for leaded C4 is comprised of an approximate ˜0.15 μm TiW base layer which underlies a film of CrCu of similar thickness over which resides a copper layer that is approximately ˜0.45 μm thick. A resist solder mask is used to electroplate the C4, and following a resist strip operation, the Cu/CrCu/TiW BLM is typically wet-etched using an electroetch process, with the C4 solder ball serving as the etch mask. This BLM technology can be used successfully with Pb-reduced (97/3 Pb/Sn) solder and C4 pitch that is no less than 4 on 8 mil (about 100 μm×200 μm). However, in current 65 nm technology, there is a requirement for C4 designs that are laid out on 3 on 6 mil pitch and which use both Pb-Reduced and Pb-Free C4 technology. The simple reduction in pitch from 4on8 to 3on6 minimizes contact area of the BLM to the final passivation film around the via such that undercut of the baselayer BLM films is no longer acceptable. The final via is set at ˜47 μm by electrical considerations, and there is a reliability constraint that the BLM must never be reduced in dimension sufficiently to expose the via sidewall. With an electroetch undercut that is typically 10-15 μm per edge, this constraint can no longer be met with 3on6 pitch. FIG. 1 illustrates the current BLM process and the wet etch undercut problem.
Particularly, FIGS. 1A-1D depict the BLM process steps according to the prior art.
As shown in FIG. 1A, there is depicted an underlying insulating layer 10, e.g., a fluorine-doped silicon oxide layer (FSG layer) having the final copper metallization layer 19 formed therein. Formed on top of the FSG layer 10 is the further insulator stack 11 comprising, for example, SiN, SiO2 and SiN layers. Formed thereabove and contacting the underlying Cu metallization 19 by a contact via is a metal bonding pad, e.g., Aluminum, and final passivation layer 12, e.g., polyimide. In FIG. 1A, there is depicted the process step of etching a final via 15 in the polyimide passivation layer 12. Then, as shown in FIG. 1B, current fabrication techniques implement Pb-free C4's using plating of the solder in a photoresist pattern, followed by wet etching of the BLM 20. In the prior art solder bump plating process, the BLM 20 includes the deposition of an adhesion layer 21, e.g., a titanium-tungsten alloy (TiW), followed by wetting layers 22 of, e.g., Cr—Cu (chromium-copper alloy) and copper (Cu). The wetting layers ensure the solder completely covers the patterned Ti—W adhesion layer (thereby ensuring a large contact area between the solder ball and the chip, and providing high mechanical strength. In the solder bump plating process, the wafer is cleaned to remove oxides or organic residue prior to metal deposition and to roughen the wafer passivation and bond pad surface to promote better adhesion of the BLM. The BLM barrier layer metals such as TiW, Cr—Cu, and Cu may then be sequentially sputtered or evaporated over the entire wafer so that the BLM 20 adheres to the wafer and passivation in addition to the bond pads. Next, a photoresist layer 30 is applied and then metal layers 40 (e.g., a Ni barrier layer followed by a C4 Sn-based solder) are electroplated over the bond pad to a height as determined by the patterned photoresist 30.
Then, as shown in FIG. 1C, after the solder bump is formed, the photoresist is stripped, leaving the BLM exposed on the wafer. The BLM 20 is subsequently etched from the wafer whereby the CrCu layer 22 is removed by electroetching, and the TiW layer 21 removed by using a wet etch process (e.g., an H2O2-based wet etch). FIG. 1C depicts the undercut 50 of approximately 10 μm-15 μm that results at each edge of the BLM due to the applied electroetch. Finally, as shown in FIG. 1D, the solder bump 40 is reflowed to form the Pb-free or Pb-reduced solder ball 40′.
For Pb-free and Pb-reduced technology, the BLM itself must normally include a top barrier layer to prevent consumption of the copper in the BLM layer by tin in the solder. Nickel is commonly used for this, in a thickness of 1-3 um. Pb-Free BLM technology is still being developed in the industry, but one Pb-Free BLM that is available comprises a stack of TiW—Cu—Ni, with the TiW layer about 0.15 μm in thickness, Cu layer from about 0.5 μm-2.0 μm in thickness, and the Ni layer about 1 μm in thickness. The TiW and Cu films are typically deposited by PVD, and the Ni is normally electroplated.
It is the case though, that problems associated with undercut of the BLM during wet electroetching of the Cu and TiW base layers exist. For example, the final structure such as shown in FIG. 1D, is at risk for reliability failure due to the minimal effective contact attach area of the remaining TiW base layer to the final passivation (polyimide) film 12, and/or with respect to the voids created by undercut 50 at each edge of the structure, which can act to entrap contaminants that act as stress nucleation sites for failure during thermal cycling.
While a partial prior solution to this problem that might include wet etch of the copper by electroetch, followed by TiW RIE to pattern the TiW base layer without undercut beneath the Cu layer is theoretically possible, in practice it does not work because of incomplete cleaning of the electroetched Cu layer in the field areas over the TiW film. The electroetch process invariably leaves minute residues which act to micromask the TiW film during the RIE, resulting in metallic residues between C4s that are of sufficient density to cause electrical shorting. This problem has proven to be unavoidable when Cu electroetch or wet-etching is used for BLM patterning.
It would be highly desirable to provide a C4 fabrication technique that results in an improved C4 pitch by eliminating the BLM undercut by a novel fabrication process that consequently increases the mechanical stability of the formed solder bump.
USPTO Backgrounds
USPTO Backgrounds