The need for portable personal electronics, such as cell phones, digital cameras, music players, personal digital assistants (PDA's), and location-based devices, is driving the necessity for increased integrated circuit (“IC”) density. To interface an IC with other circuitry, it is common to mount it on a leadframe or substrate. Each IC has bonding pads that are individually connected to the substrate's contact or terminal pads using extremely fine gold or aluminum wires or conductive balls, such as solder balls. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies to create an IC package.
IC packaging technology has seen an increase in the number of ICs mounted on a single circuit board or substrate. The new packaging designs have more compact form factors, such as the physical size and shape of a packaged IC, and provide a significant increase in overall IC density.
However, IC density continues to be limited by the “real estate” available for mounting individual ICs on a substrate. Even larger form factor systems, such as personal computers (PC's), computer servers, and storage servers, need to accommodate more ICs in the same or smaller “real estate”.
This increased IC density has led to the development of multi-chip packages in which more than one IC can be packaged. Each package provides mechanical support for the individual ICs and one or more layers of interconnect lines that enable the ICs to be connected electrically to surrounding circuitry.
Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of a printed circuit board (PCB) substrate onto which a set of separate IC components are directly attached. Such multi-chip packages have been found to increase IC density and miniaturization, improve signal propagation speed, reduce overall IC size and weight, improve performance, and lower costs, all of which are primary goals of the computer and electronics industry.
Multi-chip packages whether vertically or horizontally arranged, can also present problems because they usually must be pre-assembled before the IC and IC connections can be tested. Thus, when ICs are mounted and connected in a multi-chip module, individual ICs and connections cannot be tested individually, and it is not possible to identify known-good-die (“KGD”) before the multi-chip is assembled. Consequently, conventional multi-chip packages lead to assembly process yield problems. This fabrication process, which does not identify KGD, is therefore less reliable and more prone to assembly defects.
Moreover, vertically stacked ICs in typical multi-chip packages can present problems beyond those of horizontally arranged IC packages, further complicating the manufacturing process. It is more difficult to test and thus determine the actual failure mode of the individual ICs. Moreover, the substrate IC are often damaged during assembly or testing, complicating the manufacturing process and increasing costs.
For both vertical and horizontal multi-chip packages, assembly of the multi-chip packages must have reliable electrical and mechanical attachments between the multiple ICs, the stacked packaged ICs, or a combination thereof. For example, the encapsulating process for forming the packaged IC may cause problems because of the loss of adhesion between lead pads and package encapsulation leading to delamination and damage to the IC package. Also, exposed lead pads on the IC packages may lead to mechanical damage during handling and assembly.
Thus, a need still remains for an IC package system providing low cost manufacturing, improved yield, improved reliability, and greater flexibility to offer more functionality and fewer footprints on the PCB. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
USPTO Backgrounds
USPTO Backgrounds