The present invention relates to a method of fabricating a semiconductor device on a wafer, and more particularly, to a method that provides a simplified die release technique of the semiconductor device from the wafer.
Modern technology has enabled microelectromechanical systems (MEMS) to be fabricated on semiconductor substrates, typically silicon wafers. MEMS structures typically have sizes on the order of microns and may be integrated with electrical circuits on a common substrate. As a result, MEMS have found their way into numerous applications across numerous industries. Exemplary MEMS applications include optical switching, inertial or pressure sensors, and biomedical devices for example.
MEMS components are typically built at the wafer level and must be freed from the wafer after the fabrication process, which is referred to as xe2x80x9cdie release.xe2x80x9d The term xe2x80x9cdiexe2x80x9d is typically defined as the piece of wafer containing the semiconductor or MEMS structure. Typically a wafer will have tens to hundreds of die located thereon. Currently, products, such as MEMS-based fiber optic switches, are processed at the wafer level using a composite structure known as an SOI wafer that is generally formed by three layers of materials. The top layer is silicon (Si) and ultimately forms the MEMS device, and is often referred to as a device layer. The middle layer is an oxide and is used as an etch-stop layer. The bottom layer is also silicon (Si) and is used as a handle or support and is often referred to as a handle layer.
The SOI wafer is processed using conventional semiconductor processing techniques to create the device. Generally, semiconductor fabrication processing steps are performed from the top side of the wafer down into the wafer, i.e., at the device layer level. To define individual die on the wafer, trenches are formed in the device layer of the wafer.
Once processing is complete, the trenches between die must completely extend through the etch-stop and handle layer to separate the wafer into individual die. Dicing or sawing is often performed to accomplish this die releasing operation. However, problems with dicing or sawing include debris generation, rough edge creation, and yield loss due to process conditions, such as vibrations, etc. Furthermore, dicing may not be cost effective in comparison to an etching solution depending on the number of cuts per wafer.
Therefore, it is desirable to have an improved techniques for both releasing the structures on the die itself, and releasing the die from the wafer, or using a single technique to simultaneously accomplish both release operations.
In accordance with this invention, the above and other problems were solved by creating a die release trench in a handle layer as one of the initial steps.
According to a first aspect of the invention, there is provided a method of fabricating a semiconductor die on a wafer having a device layer, an etch-stop layer, and a primary handle layer, wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer. The method includes the steps of:
(a) etching a die release trench in the primary handle layer;
(b) etching a moving parts trench and die release trench in the device layer where the die trench in the device layer is aligned with the die release trench formed in the primary handle layer;
(c) affixing an additional handle layer to the primary handle layer;
(d) removing the etch-stop layer located between the die release trenches on the device and primary handle layers; and
(e) removing the additional handle layer to release the die.
According to a second aspect of the present invention there is provided a method of fabricating a semiconductor die on a wafer having a device layer, an etch-stop layer, and a primary handle layer, wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer. The method includes the steps of:
(a) creating a die release trench in the primary handle layer;
(b) creating a die release trench in the device layer where the die trench in the device layer is aligned with the die release trench formed in the primary handle layer;
(c) affixing an additional handle layer to the primary handle layer;
(d) removing the etch-stop layer located between the die release trenches on the device and primary handle layers; and
(e) removing the additional handle layer to release the die.
According to a third aspect of the invention, there is provided a MEMS device formed in a wafer having a device layer, an etch-stop layer and a primary handle layer wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer by the above-described processes.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.
USPTO Backgrounds
USPTO Backgrounds