1. Field of the Invention
The present invention relates to a positioning (aligning) method between a reticle and a wafer in an exposure apparatus for manufacturing semiconductor devices and liquid crystal display elements.
2. Related Background Art
In recent years, a step-and-repeat reduction projection type exposure apparatus (stepper) has become very popular as an apparatus for transferring a reticle pattern to a wafer with a high resolution in a lithographic process in the manufacture of semiconductor elements. In such a stepper, wavelengths of exposure beams have been shortened, and projection lenses having high numerical apertures (N.A.) have been developed along with the development of semiconductor elements having higher integration. Most recently, a resolution line width on a wafer has reached a submicron (about 0.5 to 0.7 .mu.m) order. In order to transfer such a high-resolution pattern, alignment (superposing) precision corresponding to its resolution is required. In view of this, it has been proposed to improve alignment precision by increasing, e.g., a resolution of an alignment sensor.
A high-resolution alignment sensor is disclosed in, e.g., U.S. Pat. No. 4,710,026. A one-dimensional diffraction grating mark formed on a wafer is irradiated with coherent parallel beams from two directions to form a one-dimensional interference fringe pattern on the diffraction grating mark. An intensity of a diffracted beam (interference beam) generated by the diffraction grating mark upon radiation of the interference fringe pattern is photoelectrically detected.
According to this method disclosed in the above U.S. Patent, a heterodyne technique for providing a predetermined frequency difference to two parallel beams incident from two directions, and a homodyne technique without providing a frequency difference are available. For example, according to the heterodyne technique, an interference beam from the diffraction grating mark is intensity-modulated with a beat frequency, thereby photoelectrically detecting the intensity of the interference beam.
A heterodyne alignment sensor (to be referred to as a laser interferometric alignment system (LIA system) hereinafter) obtains a phase difference (within .+-.180.degree.) between a photoelectric signal (optical beat signal) of an interference beam from a diffraction grating mark on a wafer and an optical beat signal of a reference interference beam separately prepared by two other beams. The LIA then detects a positional error within .+-.P/4 (where P is the grating pitch).
If the grating pitch is 2 .mu.m (1-.mu.m line and 1-.mu.m space) and a resolution of a phase difference meter is about 0.5.degree., a resolution of positional error measurement is given as (P/4).multidot.(0.5/180)=0.0014 .mu.m. As described above, the LIA system has an extremely high resolution as an alignment sensor. It is thus expected the alignment precision can be improved by 10 times or more as compared with a conventional alignment system.
Extended wafer global alignment (to be referred to as enhanced global alignment (EGA) hereinafter) is most popular as an existing stepper alignment scheme, as disclosed in U.S. Pat. No. 4,780,617.
According to the EGA scheme, in order to expose one wafer, after the position of an alignment mark formed on a pattern (chip) formed on a wafer is measured (sample alignment), six parameters, i.e., offset values (X and Y directions) of the central position of the wafer, elongation/contraction values (X and Y directions) of the wafer, a remaining rotation amount of the wafer, and the orthogonality degree between wafer stages (or the orthogonality degree between chips of a chip array), are determined according to a statistical scheme in accordance with a difference between the designed and measured values of the mark position. The position of a second (2nd) chip to be superposed and exposed is corrected in accordance with design values, thereby sequentially stepping the wafer stages.
This EGA scheme has the following advantage. After a smaller number of mark positions (about 3 to 16 positions) than the total number of chips on the wafer is measured prior to wafer exposure, other marks need not be detected or measured, so that a throughput can be increased. In addition, when a sufficient number of marks are sampled and aligned, individual mark detection errors can be averaged on the basis of statistical calculations. Therefore, alignment precision equal to or higher than alignment in units of chips (die-by-die or site-by-site scheme) can be expected for all the chips on the entire wafer surface.
The EGA scheme using the LIA system is most promising as a future stepper alignment scheme from the viewpoints of alignment precision, the throughput, and the like.
In the conventional technique described above, however, when two parallel beams are radiated on a wafer, part of a return beam (0th-order beam) from the wafer is undesirably detected by a photoelectric detector although a diffraction grating mark is not present. Therefore, an optical beat signal is output from the photoelectric detector. In particular, on a wafer having a metal layer made of aluminum, an optical beat signal is generated by a speckle or the like due to grains of the metal layer.
When the two parallel beams are radiated on the diffraction grating mark to measure a wafer position, an optical beat signal as a noise component by a speckle or the like is contained in an optical beat signal output from the photoelectric detector. When alignment is to be performed by the EGA scheme using the LIA system, chips that lead to reduced detection precision of alignment marks due to the above noise component, i.e., chips that lead to poor reliability (accuracy) of measured values of the alignment marks, are equally processed with others. Therefore, alignment (EGA measurement) precision may be degraded by values of poor reliability.
In this case, in order to compensate for the measured values of poor reliability, the number of chips subjected to sampling and alignment is increased or the measured values of poor reliability are eliminated from sampling and alignment to perform positioning without degrading alignment precision.
In the former case, upon an increase in the number of chips to be measured, a time required for measuring the mark positions and performing alignment is undesirably prolonged. In the latter case, the measured values excluded from EGA measurement are not used at all, so that the number of chips used for EGA measurement is decreased thus, each method has significant disadvantages.
USPTO Backgrounds
USPTO Backgrounds