The semiconductor-related industry currently typified by DRAM and flash memory has developed successfully through miniaturization and integration based on the fact that the principles of operation can be maintained even when the size of the devices is decreased. However, with the recent rapid development of the information and communications technology, the performance and complexity of the devices are increasing and high speed, high integration and power saving are required for the memory devices. But, the DRAM is problematic in that it is volatile and is limited in data processing speed. And, the flash memory has the problem that it requires a high threshold voltage (>5 V) in addition to the problems of increased complexity after the sub-30 nm process, electrical degradation and slow operation speed. Accordingly, development of next-generation memory devices overcoming the problems of the existing memory devices is necessary.
As next-generation nonvolatile memory devices for solving these problems, phase-change RAM, magnetic RAM (MRAM), resistance switchable RAM (RRAM), etc. are available. Among these next-generation memory devices, the RRAM records the data 1 and 0 as low resistance state (LRS) and high resistance state (HRS) are switched reversibly depending on the applied voltage conditions. In addition, the RRAM is the most promising candidate for commercialization because it can satisfy the data nonvolatility of flash memory, the fast operation speed of SRAM and, above all, the low power consumption of DRAM. In particular, it is drawing a lot of attentions because high integration density can be achieved through a simple 3-dimensional vertical crossbar array structure including a resistance switching layer made of an oxide thin film between top and bottom electrodes.
However, parasitic current resulting from interference between adjacent non-target cells of low resistance state located on the same bit line or word line in the crossbar array is known as the biggest problem in reliable operation of the RRAM. Sneak current passing through the cells located on the same row or column as the target cell may result in errors when reading and recording cell state. For example, sneak current through adjacent non-target cells may cause errors in reading by affecting the total current of the target cell.
The one-transistor one-resistor (1T1R) structure proposed to solve the problem caused by the parasitic current has superior selectivity but the memory integration density is significantly limited. The 1S1R structure using one selector and one resistor, which was proposed as another solution, makes the structure of the crossbar array complicated. In addition, the nonlinear element of the selector is significantly dependent on the array size and enough current may not pass to the target cell.
Accordingly, a complementary resistance switchable (CRS) random access memory which exhibits memory function and selectivity at the same was proposed recently. The CRS memory has an insulator/conductor/insulator structure between top and bottom electrodes as if two resistance switchable memories face each other. The CRS memory records “0” when the top element is in high resistance state and the bottom element is in low resistance state. On the contrary, it records “1” when the top element is in low resistance state and the bottom element is in high resistance state. Because the entire device is in high resistance state whether “0” or “1” is recorded, sneak current resulting from the interference of adjacent non-target cells is excluded. In addition, because it exhibits self-compliance current behavior not requiring an external resistor for current compliance, it is not affected by RC delay.
However, because the CRS memory is driven based on the filamentary phenomena of formation and extinction of conductive filaments, it shows the problems occurring in the existing resistance switchable memory based on the filamentary phenomena, such as indefinite and random formation of many filaments. As a result, the CRS memory driven by the complementary behavior of two filaments may suffer from severe device instability (poor endurance/retention). In addition, the CRS memory is problematic in that it is difficult to ensure mechanical stability for a highly integrated crossbar array structure because a process of depositing multiple thin films is necessary for the resistance switchable memory and it is difficult to ensure physical properties required for wearable devices, such as transparency or bendability, due to the presence of multiple intermediate layers.
USPTO Backgrounds
USPTO Backgrounds