1. Field of the Invention
Embodiments of the invention relate to integrated circuits, and more particularly, in one or more embodiments, to 3-D integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs) may include many devices and circuit members that are formed on a single semiconductor wafer or die. The current trends in IC technology are towards faster and more complicated circuits. However, as more complex ICs are manufactured, various speed-related problems become more challenging. This is especially true when ICs having different functions are used to create electronic systems, for example, computing systems including processor and memory ICs, where different ICs are electrically connected by a network of global interconnects. As global interconnects become longer and more numerous in electronic systems, RC delay and power consumption, as well as low system performance, become limiting factors.
One proposed solution to these problems is three-dimensional (3-D) integration or packaging technology. 3-D integration refers to the vertical stacking of multiple die, packaged die, wafers, or chips including ICs within a package. In recent 3-D integration technology, multiple die or wafers are electrically connected using vertical connectors or 3-D conductive structures. Vertical connectors extend through one or more of the die and are aligned when the die are stacked to provide electrical communication among the ICs in the stack. Such vertical connectors are often formed of a conductive material, such as copper. 3-D integration typically results in a reduction of the packaged IC's footprint as well as a reduction in power consumption, and a simultaneous increase in performance.
Referring to FIGS. 1 and 2, a conventional 3-D IC device will be described below. The illustrated 3-D IC device 100 includes first to fourth die 110a-110d stacked over one another. The first die 110a is the uppermost die, and the fourth die 110d is the lowermost die. The second and third die 110b, 110c are interposed between the first and fourth die 110a, 110d. In other examples, a 3-D IC device can include a greater or fewer number of die than the device of FIG. 1.
Each of the first to fourth die 110a-110d includes an IC array 112, a transceiver 114, first interconnect lines 116, second interconnect lines 118 and landing pads 130a-130d. Each of the die 110a-110c, except for the lowermost die (the fourth die 110d in the illustrated example), also includes vertical connectors 120a-120c (FIG. 2). In the context of this document, such vertical connectors may also be referred to as “3-D interconnects” or “3-D conductive structures.” In an example where the die are formed of silicon, such vertical connectors may be referred to as “through-silicon vias” (TSVs).
The IC array 112 may include one or more integrated circuits, including, but not limited to, one or more memories (for example, volatile and/or non-volatile memories) and one or more processors. The first interconnect lines 116 provide data paths between the IC array 112 and the transceiver 114 on a respective one of the die 110a-110d. The second interconnect lines 118 provide data paths between the transceiver 114 and the landing pads 130a-130d of a respective one of the die 110a-110d. 
The vertical connectors 120a-120c provide electrical paths between the landing pads 130a-130d of two die 110a-110d that are stacked immediately next to each other, thereby completing parts of data paths between the IC arrays 112 on the two die. In certain cases, the vertical connectors 120a-120c of two or more die 110a-110d that are stacked over one another are aligned in series, and can together provide serial data paths among the two or more die.
Referring to FIGS. 3A and 3B, a conventional scheme for data transfer between two ICs on different die via vertical connectors will be described below. The illustrated portion of a 3-D IC device 300 includes a die 310, a first re-routing logic circuit 301, a second re-routing logic circuit 302, transmission drivers 331a-331d, 341a-341d, 331r, 341r, and comparators 332a-332d, 342a-342d, 332r, 342r. 
The die 310 includes first to fourth nominal vertical connectors 320a-320d and a repair vertical connector 325. The repair vertical connector 325 may also be referred to as “redundant vertical connector” in the context of this document. In other examples, a die may include a greater or fewer number of nominal and/or repair vertical connectors than the die 310 of FIG. 3A.
The first and second re-routing logic circuits 301, 302 are configured to route data signals between the two ICs on the different die. One of the two ICs may be on the die 310, and the other IC may be on a die immediately below the die 310. The transmission drivers 331a-331d, 341a-341d, 331r, 341r are configured to buffer the data signals for transfer through the vertical connectors 320a-320d, 325. The comparators 332a-332d, 342a-342d, 332r, 342r are configured to detect the levels of the data signals that have been transferred through the vertical connectors 320a-320d, 325.
When there is no defect in the nominal vertical connectors 320a-320d, the first and second re-routing logic circuits 301, 302 can route data signals between the ICs on the different die, using the nominal vertical connectors 320a-320d, as shown in FIG. 3A. Statistically, however, it is improbable that 100% of the vertical connectors are functional, following the stress of fabrication and testing.
Thus, 3-D IC devices are typically tested during fabrication to determine if there are any defective vertical connectors. For example, if any one (for example, the fourth vertical connector 320d, as shown in FIG. 3B) of the nominal vertical connectors 320a-320d is found to be defective during the fabrication/testing of the 3-D IC device, the first and second re-routing logic circuits 301, 302 are configured to replace the defective vertical connector 320d with the repair vertical connector 325. Thus, data signals are routed via the repair vertical connector 325 and the remaining non-defective nominal vertical connectors (for example, the first to third vertical connector 320a-320c, as shown in FIG. 3B).
FIG. 4 illustrates the layout of a conventional 3-D IC device 400 employing the scheme described above in connection with FIGS. 3A and 3B. The illustrated portion of the 3-D IC device 400 includes IC arrays 412a-412c on a die, and first to fourth columns 415a-415d of vertical connectors 420, 425.
Each of the first to fourth columns 415a-415d includes nominal vertical connectors 420 and a repair vertical connector 425. In the illustrated example, each of the first to fourth columns 415a-415d includes nine (9) nominal vertical connectors 420 and one (1) repair vertical connector 425. Any one of the nine nominal vertical connectors 420 in a column 415a-415d may be replaced with the repair vertical connector 425 in the column, when it is found to be defective.
USPTO Backgrounds
USPTO Backgrounds