1. Field of the Invention
The present invention relates to a method for solid phase diffusion of zinc into an InP-based photodiode and an InP-based photodiode made with the method.
2. Description of the Background Art
InP-based photodiodes are p-i-n photodiodes and avalanche photodiodes for sensing near-infrared light (wavelength: 1.3 to 1.6 μm) in optical communication applications. The absorption layer is a compound crystal of InxGa1-xAs (where 0<x<1) or a compound crystal of InxGa1-xAs1-yPy (where 0<x, y<1). Hereinafter, the mixture ratios “x” and “y” are omitted for the sake of brevity. InGaAs compounds are used more often although InGaAsP absorption layers are sometimes used depending on the wavelength of the light to be absorbed
These photodiodes are called InP-based photodiodes because the substrate is made of InP and the absorption layer contains InP. In the subsequent explanation, the absorption layer is described as an InGaAs absorption layer because the explanation would become complicated if InGaAs and InGaAsP were both mentioned simultaneously. However, the term InGaAs absorption layer includes both InGaAs absorption layers and InGaAsP absorption layers, and description of the InGaAs absorption layer is applicable to both of InGaAs absorption layers and InGaAsP absorption layers.
When an InP photodiode is manufactured, an n-InP buffer layer, an InGaAs absorption layer, an n-InP window layer, and the like are epitaxially grown onto an n-type substrate. The perimeter of the top surface is then covered with a mask and zinc is selectively diffused through the opening of the mask to form a dish-shaped p-region.
Group IIb elements such as Zn and Cd are used as the p-type dopant for forming the p-region of the InP photodiode. Zn is used most frequently. The epitaxial method, the ion implantation method, or the thermal diffusion method can be used to form a pn junction in a semiconductor layer.
When the epitaxial method is used, a p-type layer is epitaxially grown on an n-type layer or an i-type layer, such that the boundary layer therebetween forms the pn junction. With this method, a p-region having a dish-shaped cross section cannot be made.
When the ion implantation method is used, ions of a p-type dopant are accelerated and shot into an n-type layer or an i-type layer. Since the ions can be implanted selectively by attaching a mask, a p-region can be formed on a limited area. The impact of high-speed ions disturbs the crystalline structure. Therefore, the regularity of the crystal is restored by annealing.
Neither the ion implantation method nor the epitaxial growth method is particularly well suited to forming the p-region of a photodiode. The p-regions of photodiodes are made almost exclusively by the thermal diffusion method. Thermal diffusion is a process in which a p-type impurity is put in physical contact with a semiconductor layer and heat is applied such that particles of the impurity are drawn to inside the semiconductor layer due to a concentration gradient. Thermal diffusion is categorized into vapor phase diffusion, liquid phase diffusion, and solid phase diffusion, based on the physical state of the p-type impurity. Liquid phase diffusion is difficult to employ in the case of InP photodiodes because there are not any suitable substances in which Zn can be dissolved to make a liquid solution.
Consequently, the p-regions of InP photodiodes have been formed almost exclusively by vapor phase diffusion. The vapor phase diffusion methods include the closed tube method and the open tube method.
The closed tube method of the vapor phase diffusion has been used conventionally. Today, the closed tube method is the most commonly employed method. The closed tube method involves covering an n-type InP wafer with an SiO2 mask having a window, and then placing the n-type InP wafer, together with solid phosphorous (P) and a Zn compound that serves as a dopant, into a quartz tube that has been pulled to a vacuum. The Zn compound is heated to a vapor and the gaseous Zn compound is put into contact with the InP wafer through the window of the mask. The Zn diffuses into the epitaxial wafer in the vapor phase. ZnCl2 or other compound that sublimates readily is used as the Zn compound. The solid phosphorous (P) is maintained at a lower temperature in order to balance against the disassociation pressure of the phosphorous from the InP wafer and prevent phosphorous from escaping from the surface of the InP wafer. When semiconductors made of elements in Groups 3 to 5 are raised to high temperatures, the disassociation pressure of Group 5 elements becomes high and the escape of Group 5 elements becomes particularly prominent. Therefore, a high vapor pressure of the Group 5 element is created inside the quartz tube so that the vapor pressure and the disassociation pressure of the Group 5 element are in balance. A closed tube is particularly well suited for maintaining such a balance.
The amount of Zn to be diffused (diffusion depth) can be controlled based on the temperature and the amount of time. Once a prescribed amount of time elapses, the quartz tube is broken and the wafer is removed. The wafer thus removed has a p-region and a pn junction formed thereon. The process is called “vapor phase diffusion” because the Zn is in the vapor phase. The method is called the “closed tube method” because the process is conducted inside a closed quartz tube. This method has a long history of success, is an excellent method, and is still used almost exclusively today.
The closed tube method can be employed to manufacture 2-inch diameter InP wafers. However, when the diameter of the InP wafer is larger, such as 3 or 4 inches, it becomes difficult to conduct Zn diffusion with the closed tube method. This is because as the wafer diameter becomes larger, a larger quartz tube becomes is necessary. Thus, even though it is possible to employ the closed tube method, the cost of a quartz tube increases. Therefore, a less expensive method is desired.
The open tube method was developed as a vapor phase diffusion method for diffusing Zn into an InP epitaxial wafer having a diameter of 3 inches or 4 inches. The open tube method involves placing an n-type InP wafer inside a quartz tube that is open at both ends, and introducing a flow of a heated Zn compound into the tube such that Zn contacts the wafer and diffuses into the wafer from the surface thereof. This method uses a large quartz tube. A gas of a Group V element and a gas containing an impurity are introduced into the tube in a flowing fashion, with both ends of the tube being open, such that the wafer can be inserted into and removed from the tube through the opening. The Group V gas is for preventing disassociation of the Group V element contained in the wafer and is made to flow into the tube constantly in such a manner as to maintain an appropriate vapor pressure. Since the open method does not require the quartz tube to be broken after each diffusion process, the same apparatus can be used over and over again. It is also possible to manufacture a large apparatus. Thus, the open tube method is well suited to the vapor phase diffusion of larger diameter wafers. This open tube method, too, is an old method. In actual practice, however, it is difficult to control the diffusion conditions while maintaining the pressure balance of the Group V elements. Consequently, the open tube method is still not widely employed for p-type doping of InP wafers.
Another possibility is the solid phase diffusion method, which is also well suited to large wafers. The method is called “solid phase diffusion” because the diffusion source is a solid instead of a gas. The concept of solid phase diffusion has been around for a long time. Solid phase diffusion has a track record with Si, GaAs, and other semiconductors, but it still has hardly any track record at all with InP.
An example of how solid phase diffusion might be conducted with an InP photodiode will now be described. An SiN mask is attached to an InP epitaxial wafer, openings are formed in the mask, and a thin film of ZnO is formed over the mask with the openings. A layer is then provided on top of the ZnO for sealing, and the wafer is heated. As a result, the zinc atoms separate from the ZnO and thermally diffuse into the n-InP window layer and the n-InGaAs absorption layer of the wafer through the openings. The speed of the diffusion can be controlled by adjusting the temperature. When the desired degree of Zn diffusion is achieved, the wafer is removed from the furnace, and the ZnO layer that served as the solid diffusion source is removed with hydrofluoric acid. As a result, the ZnO and the SiN layers are removed and the InP window layer is exposed. When the wafer is viewed from above, the p-region appears as dots in a sea of n-type window layer. The p-region is allowed to remain, and an SiN layer is formed so as to cover the pn junction. Afterwards, a p-electrode is provided on the p-region and an n-electrode is provided on the n-type InP substrate.
[Patent Document 1] Japanese Patent Application Publication No. 2002-299679, “Photodiode Manufacturing Method”
Patent Document 1 addresses the issue of dislocations and defects that occur due to the difference in the thermal expansion rates of the solid diffusion layer (ZnO) and the epitaxial layers.
More specifically, when the p-region of an InP device is made using the solid phase diffusion method, a solid diffusion layer (ZnO) is formed directly on an epitaxial growth layer by vapor deposition, and heat is applied to cause the p-type dopant to diffuse from the diffusion layer to the epitaxial layers. The magnitudes of the thermal expansion rate and other physical constants of the solid diffusion layer (ZnO) containing the p-type impurities are substantially different from those of the epitaxial layer (InP, InGaAs), which contacts the solid diffusion layer from below. Consequently, dislocations and defects occur at the boundary between the two layers. If the defects and dislocations are large and numerous, the semiconductor device will incur such drawbacks as a large amount of leakage current. Patent Document 1 addresses this problem.
In the process disclosed in Patent Document 1, an n−-InP cap layer and an n−-InGaAs cap layer are epitaxially grown onto the uppermost layer (InGaAs contact layer) of the InP epitaxial growth layers. A mask is applied and the mask is partially etched to form openings. A ZnO diffusion source and an SiO2 cap layer are then formed over the mask with the openings by sputtering. The resulting wafer is heat-treated such that the Zn diffuses from the ZnO diffusion source to the epitaxial layers through the n−-InP cap layer and the n−-InGaAs cap layer. After the diffusion is completed, the SiO cap layer, the ZnO cap layer, the p-InP cap layer, and the p-InGaAs cap layer are removed by etching.
In short, an n−-InP cap layer and an n−-InGaAs cap layer are formed thinly on the InP epitaxial layers (n-InP window layer/n-InGaAs/n-InP buffer/n-InP) and Zn is thermally diffused through the cap layers. Then, the ZnO, the p-InP, and the InGaAs cap layers are removed.
Here the difference between the lattice parameters of the n−-InP cap layer and the InGaAs contact layer, which is directly below the n−-InP cap layer, is small. On the other hand, the difference between the physical constants of the InP cap layer and the ZnO layer is large. Consequently, dislocations and defects occur between the InP cap layer and the ZnO layer, but do not reach the n-InGaAs contact layer below. Since the InP cap layer and the InGaAs cap layer are removed, the defects and dislocations are also removed. As a result, the defects do not remain in the device itself and a high-quality device can be obtained.
The cap layers (InP, InGaAs) are dummy layers that contact the ZnO layer and have lattice parameters and thermal expansion rates that are greatly different from those of the ZnO layer. Consequently, dislocations and defects occur between the ZnO layer and the cap layers (InP, InGaAs), and the defects and the dislocations multiply in the cap layers. However, the defects and dislocations are limited within the cap layers and do not extend to the epitaxial layers therebelow. Thus, the epitaxial layers have only a small amount of defects and dislocations. As a result, almost no leakage current occurs even if a large reverse bias is applied to the photodiode.
The object of the present invention is different from the object of Patent Document 1 and the two inventions are not closely related. The author has cited Patent Document 1 as a publicly known technology only because any more closely related document regarding the solid phase diffusion of Zn in the manufacture of an InP photodiode could not be found.
In a diffusion process in which Zn is diffused by the solid phase diffusion in order to manufacture an InP photodiode, an SiN or SiO2 mask is formed on the epitaxial layers and a window is formed on a portion of the film. A ZnO film is formed over the mask with openings and an SiO2 film is formed over the ZnO film. The wafer is then heated and Zn is allowed to diffuse from the ZnO into the epitaxial layers. The Zn is stopped and not allowed to diffuse into the epitaxial layers at the portions where the SiN or SiO2 mask is formed. Meanwhile, the ZnO contacts the InP at the window portion of the mask. The heat causes the Zn to pass through the contact plane and move into the InP layer, such that Zn is diffused into the InP layer by heat. As a result, a p-region and a pn junction are formed in desired portions of the wafer surface corresponding to the window of the mask.
The diffusion of Zn with the solid phase diffusion works well thus far. However, unlike the vapor phase diffusion, the solid phase diffusion requires that the diffusion source (ZnO layer) be removed after the diffusion is completed. Since ZnO is an oxide film, it cannot be removed with such substances as sulfuric acid, hydrochloric acid, or caustic soda (sodium hydroxide). Hydrofluoric acid is used to remove the ZnO. However, although hydrofluoric acid can remove the ZnO, it also removes the SiN or SiO2 of the mask and causes the pn junction to be temporarily exposed.
In both solid phase diffusion and vapor phase diffusion, the diffusion of Zn proceeds in an isotropic fashion through the crystal. Thus, the diffusion also advances laterally from the edge of the mask underneath the mask. Consequently, the portion of the pn junction on the uppermost surface is expanded from the pattern edge of the diffusion mask by several microns. The edge of the pn junction is directly underneath the mask and would remain protected by the mask if the mask was not removed. In the case of the vapor phase diffusion, the SiN or SiO2 mask remains as a protective film. Thus, there is no concern regarding degradation of the pn junction because the pn junction is always protected. Also, in the case of the vapor phase diffusion, the mask remains and the spread of the p-region exists slightly beyond the mask opening. The vapor phase diffusion process results in self alignment, and all else that is required is to attach a p-electrode to the p-region.
Conversely, the solid phase diffusion method requires that the ZnO be removed with hydrofluoric acid. When the solid diffusion source is removed with hydrofluoric acid, the diffusion mask (SiO2 or SiN) is also removed simultaneously. Thus, the protection of the mask is lost and the pn junction is completely exposed at the surface of the wafer. Since the wafer is outputted to the atmosphere after the etching, the gases and contaminants in the atmosphere contaminate the edge of the pn junction and cause the pn junction to become damaged.
The solid phase diffusion process will now be explained with reference to FIGS. 11 to 17. FIG. 11 is a cross sectional view showing a portion of an epitaxial InP wafer corresponding to a single device. An n-InP buffer layer 2, an n−-InGaAs absorption layer 3, an n-InP window layer 4 are epitaxially grown onto an n-InP substrate 1. Here, “n−-InGaAs” means the layer is n-type but its concentration is low. Since the InGaAs is n-type even if it is undoped, “n−-InGaAs” includes undoped InGaAs. In some cases, the uppermost n-InP window layer 4 is not provided. In actual practice a multitude of chips are formed vertically and horizontally in a single wafer. Here, however, only the portion corresponding to a single device is depicted.
An SiN film 6 is formed on the epitaxial wafer as shown in FIG. 12. The SiN film 6 serves as a cover that will prevent the Zn from diffusing into the epitaxial layers. A photoresist is coated, exposed through a mask, and developed. In this manner, a window is formed in the photoresist. The SiN film 6 in the window portion of the photoresist is removed by etching, more specifically, by wet etching with hydrofluoric acid. As a result, an opening 10 is formed in a central portion of the device as shown in FIG. 13.
A thin ZnO film 8 serving as the Zn source is formed over the opening 10 and the SiN film cover 18. A thin SiO2 film 9 is formed over the ZnO film 8. The SiO2 film 9 on the ZnO film 8 prevents the Zn from escaping upward.
FIG. 14 shows the state of a single device of the wafer after the SiO2 film 9 is formed. In the opening 10 area, the ZnO film 8 and the InP window layer are in contact. The sections where the cover exists, the ZnO film 8 and the InP window layer 4 are separated by the SiN film 6. The InP wafer is then heated and held at an appropriate temperature such that the Zn diffuses by thermal diffusion. The Zn atoms of the ZnO film 8 diffuse into the epitaxial layers of the wafer from the surface of the n-InP window layer 4 due to the concentration difference.
The Zn cannot diffuse into the SiN layer 6 and, thus, only diffuse into the InP window layer 4. The Zn atoms move not only directly downward but also laterally under the SiN mask 6. Once the Zn atoms pass through the n-InP window layer 4, they enter the n−-InGaAs absorption layer 3 underneath. The Zn atoms then penetrate farther into the n−-InGaAs absorption layer 3. This is the solid phase diffusion of Zn. After an appropriate amount of time has elapsed, the temperature is reduced and the diffusion is terminated. A pn junction 20 is thereby formed at a middle portion of the InGaAs absorption layer 3. The materials above the pn junction 20 turn into p-InP and p-InGaAs, while the material below the pn junction 20 is n-InGaAs. FIG. 15 is a cross sectional view showing a portion of the wafer corresponding to a single device when the diffusion is terminated.
A pn junction is a portion where the donor concentration and the acceptor concentration are the same. At the pn junction, free electrons and holes do not exist and the donors and acceptors are in an ionic state. Depletion layers form above and below the pn junction. The n-type depletion layer located directly below the pn junction is thick and is the more important of the two. When light incident on the device reaches the absorption layer 3, the light is absorbed because the band gap is small and electron-hole pairs are created. Due to the effect of the electric field, holes move toward the pn junction and pass the pn junction. When the holes enter the p-region, it means an electric current is generated and, thus, a photocurrent is generated.
The pn junction 20 is formed so as to be horizontal within the absorption layer 3. The portion of the pn junction 20 underneath the mask has a pn junction side wall 22. The edge 23 of the pn junction 20 is exposed in a portion of the n-InP window layer. When the vapor phase diffusion is used, the pn junction edge 23 is not exposed to the outside because the SiN mask is not removed. Conversely, with the solid phase diffusion, the pn junction edge 23 is temporarily exposed because the hydrofluoric acid etching used to remove the SiO2/ZnO thin films also removes the SiN. Herein lies the problem with the solid phase diffusion method.
FIG. 16 shows the state of a single device of the wafer after the ZnO and SiN have been removed and the pn junction edge 23 is exposed. The pn junction edge 23 is vulnerable to contamination, since water vapor, oxygen, and the like tend to adhere to the pn junction edge 23. Defects 27 such as dislocations may result. When localized defects 27 occur, the pn junction is degraded and incomplete. It is a drawback of the solid phase diffusion that the state shown in FIG. 16 tends to occur. This state does not occur when the vapor phase diffusion is employed because the SiN is always attached.
With the solid phase diffusion, it is necessary to remove the SiO2 and the ZnO diffusion source by etching. Since ZnO is strong oxide, it cannot be dissolved with sulfuric acid, phosphoric acid, hydrochloric acid, or caustic soda. Hydrofluoric acid must be used to remove ZnO. Although ZnO can be dissolved with hydrofluoric acid, the SiN is also removed simultaneously. In short, there is no etching liquid that can dissolve the ZnO without dissolving the SiN.
Thereafter, an SiN protective layer 36 is formed to cover the edge 23 of the pn junction 20. Since this SiN protective layer 36 is formed afterwards, the edge thereof is generally misaligned in the lateral and longitudinal directions relative to the pn junction edge 23. Due to the misalignment 29, the width by which the pn junction edge 23 is covered differs at different portions of the pn junction edge 23. Thereafter, a p-electrode and an n-electrode are formed. If the protective layer 36 is misaligned, the positioning of the p-electrode with respect to the p-region may also become misaligned.
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