As time progresses, semiconductor packaging structures become smaller and smaller and the concentration of the structures keeps increasing. In addition, semiconductor packaging structures have been made in a variety of shapes. Based on the connection method, semiconductor packaging structure has been typically classified as a metal wire bonding type and a flip-chip bonding type. The packaging structure of the metal wire bonding type connects electrodes of a semiconductor chip to a leadframe by using conducting bonding metal wires while for a packaging structure of the flip-chip type, the semiconductor chip is directly connected to the electric leads or connected to connecting terminals of a circuit board through conductive protrusions placed on solder joints of the electrodes of the semiconductor chip. The packaging structure of the flip-chip bonding type has shorter electrical connection paths as compared to the packaging structure of the metal wire bonding type, thus it provides not only excellent thermal and electrical properties but also a smaller size for the packaging structure. Therefore, the flip-chip packaging structure becomes an advanced selection for the modern wireless communication applications in the GHz frequency range.
Currently, during the process of forming a flip-chip on leadframe (FCOL) semiconductor packaging structure, low melting point solder material is usually deposited on the interconnection sites and solder protrusions are formed on the semiconductor chip. The protrusions may also include metal pillars sticking out from solder pads of the semiconductor chip. Each solder pad of the semiconductor chip has a solder ball formed on a free end of the metal pillar. The solder balls are usually made of a high-lead solder material. Further, the solder balls on the chip are flipped together with the semiconductor chip and are placed upside down on the leadframe with the solder balls adjacent to the deposited solder material on interconnection sites.
Then, the temperature is raised. When the temperature reaches a certain point, the deposited solder material melts and flows back. As a result, the solder material adheres to both the interconnection sites on the leadframe and the high-lead solder balls on the copper pillars, thus forming solder connections between the high-lead solder balls on the free ends of the copper pillars and the interconnection sites on the leadframe. Finally, the structure is packaged to an FCOL semiconductor packaging structure.
During the back-flow process, the melt solder is flowable and may be lost from the connection points, leading to poor contacts between the high-lead solder balls on copper pillars and the interconnection sites on the leadframe or undesired contacts between the solder and the neighboring leads, causing short circuits.
In addition, during the packaging process of the FCOL semiconductor packaging structure, the chip will be sealed, thus the heat in the chip may not be conducted out. Traditionally, most FCOL semiconductor packaging structures release the heat in the chip through a carrier board. However, there are still some problems as follows.
First, the chip in a traditional FCOL semiconductor packaging structure is suspended on the carrier board. However, heat cannot be efficiently dissipated from such a suspended chip, thus the electrical and thermal performance and the reliability of the final product may be affected.
Second, most of the traditional semiconductor leadframe-type packages use a metal board in the package component to conduct the heat generated in the chip, thus increasing the area of the carrier board may improve the cooling efficiency. However, due to the difference in the thermal expansion coefficients of different materials, increasing the area of the carrier board to meet the high heat dissipation demands may induce reliability issues such as residual stress, layer segregation, etc. In addition, increasing the area of the carrier board does not meet the requirements of the development trend for increasingly slim and light semiconductor packaging components.
Third, some traditional semiconductor packaging structures also choose to use highly conductive and thermal molding material to improve the cooling efficiency. However, in addition to the cost price of the highly conductive and thermal molding material, using such a material not only has higher requirements for the control of the molding process of the product, but also shows no obvious improvement on the cooling effect. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.
USPTO Backgrounds
USPTO Backgrounds