1. Field of the Invention
The invention relates to a chip package, and in particular relates to a chip package formed by a wafer-level packaging process.
2. Description of the Related Art
In a conventional chip packaging process, semiconductor dies diced from a wafer is one by one packaged, which requires a lot of time and process steps. In a wafer-level packaging process, before the dies are one by one diced, process steps needed to be performed have already been completed on the wafer. After a dicing process is subsequently performed, a plurality of chip packages formed under substantially the same process conditions may be simultaneously obtained. Adopting a wafer-level packaging process may reduce the fabrication cost and time.
However, because a wafer has a larger surface area, packaging processes or fabrication processes of the wafer sometimes needs to be accordingly adjusted. For example, process conditions of portions at the central and periphery portions of the wafer may need to be adjusted.
Thus, it is desired to have relative position information of a single specific chip package in a wafer before being diced, so that the fabrication conditions may be adjusted accordingly thereto.
USPTO Backgrounds
USPTO Backgrounds