For data communication between semiconductor devices, various methods have been proposed to provide an interface circuit which transmits and receives data using an internally generated clock signal for synchronization among different processing units.
For example, one conventional technique provides an interface circuit for testing a dual-port memory, wherein a transmitter device outputs data with a strobe signal for transmission to a receiver device, which loads the incoming data using the strobe signal for synchronization. Another conventional technique provides an interface circuit with phase adjustment capability, wherein data is transmitted and received among multiple devices in synchronization with a single, phase-adjusted clock signal. This technique is employed by various interface standards, such as Peripheral Component Interconnect (PCI), as well as those for commercially available memory cards, such as PC Card, Secure Digital (SD), and Memory Stick.
FIG. 1 is a circuit diagram of a conventional interface circuit 110 included in a host device 100 to communicate data with an external device 200 in synchronization with a phase-adjusted clock signal.
As shown in FIG. 1, the interface circuit 110 includes a pair of input-output (IO) cells 101 and 102, a pair of first and second, D-type flip-flops 103 and 104, and a delay element 105.
In the interface circuit 110, the IO cell 101 receives a basic clock signal CLK_BASE from a signal source to output a clock signal CLK_IO to the external device 200. The IO cell 102 outputs data for transmission to the device 200, and receives data output from the device 200 for output to the flip-flop 103. The first flip-flop 103 receives the incoming data in synchronization with a delayed clock signal, generated by the delay element 105 adding a delay to the basic clock signal CLK_BASE, and outputs the received data to the second flip-flop 104. The second flip-flop 104 loads the data output from the first flip-flop 103 in synchronization with the basic clock signal CLK_BASE for forwarding to a given destination.
In the circuit of FIG. 1, it is not difficult for the host device 100 to satisfy timing requirements specific to AC characteristics of the data line when transmitting data to the external device 200, since the data and clock signals output from the host device 100 flow in the same direction (i.e., output) through the interface circuit 110. However, this is not the case during data reception, wherein the interface circuit 110 receives data being input from the external device 200 while outputting the clock signal from the host device 100.
Hence, to ensure a sufficient setup time and hold time to meet the specific timing requirements, the host device 100 has the delay element 105 located upstream of the clock terminal of the first loading D-type flip-flop 103, which compensates for a wiring delay caused by wiring between the host device 100 and the external device 200, as well as a delay caused by passing through the IO cell 102.
For such an interface circuit 110 to work properly, it is necessary to accurately estimate the wiring delay and the IO cell delay during the development stage of the semiconductor device, which is, however, difficult to perform due to various factors influencing the delay time. For example, the delay occurring at the IO cell depends on the capacity of the circuit board as well as on the environmental temperature, and typically increases at higher temperatures to cause a reduced timing margin of the conventional interface circuit 110.
FIG. 2 is a circuit diagram of another, modified interface circuit 100a proposed to overcome the problem of the conventional configuration. As shown in FIG. 2, the interface circuit 100a is similar to that depicted in FIG. 1, except that the modified circuit 100a has the delay element 105 connected to the output of the basic clock signal CLK_BASE through the IO cell 101, so that the clock signal is input to the clock terminal of the first loading D-type flip-flop 103 after passing through the IO cell 101. This arrangement makes it easier for the interface circuit 100a to satisfy timing requirements, since unlike the configuration depicted in FIG. 1, the delay occurring at the IO cell 101 is not required to be taken into account in the estimation of the overall delay time of the semiconductor circuit.
However, the improved interface circuit 100a has several drawbacks. One drawback is that the clock signal transmitted between multiple devices on the circuit board is susceptible to reflection and causes erroneous operation of the semiconductor circuit where the impedance of its transmission line is not properly controlled. This presents difficulties in providing the interface circuit 100a with a sufficient timing margin in applications where the basic clock signal CLK_BASE has a relatively high frequency.
Another drawback, which is common to both of the conventional interface circuits 100 and 100a, is that timing violation occurs between the first and second D-type flip-flops 103 and 104 when the sum of the wiring delay on the circuit board and the delay at the IO cell exceeds one cycle of the clock signal.
USPTO Backgrounds
USPTO Backgrounds