In serial based communication systems, data is transmitted serially between network nodes in a bit stream, comprising a sequences of separate bits, evenly spaced by a bit period. The speed at which a node can process a bit stream in order to operate upon the information contained therein is determined by, among other factors, the data rate of the bit stream and the bit stream processing latency. The data rate of a bit stream is the inverse of the bit period, and the bit stream processing latency is the delay from the time the bit stream arrives at the node to the time the individual bits are available for computation.
In many cases, a bit stream may be formatted to improve various aspects of transmission. For instance, a bit stream may be encoded via an mBnB block code for reducing baseline wander problems by eliminating long strings of 1s and 0s in a serial transmission. Another approach for eliminating long sequences of the same bit is to scramble the serial data with a known polynomial. A different form of scrambling is encryption of a bit stream to improve the security of the transmission of data.
In many such cases, bits of an incoming bit stream must be detected and substituted before the information in the bit stream can be used by a user application. For example, one FDDI standard for fiber-optic networks specifies that transmitted bits are encoded with a 4B5B block code. Consequently, a receiving node of the fiber-optic network must detect every five bits and substitute the five bits with a corresponding four-bit value.
In conventional systems, the data rate of such formatted incoming bit streams is limited for a variety of reasons. For example, the incoming bit stream is usually stored for processing in a random access memory (RAM) buffer, such as a dynamic RAM (DRAM) buffer and static RAM (SRAM) buffer. Thus, the data rate of a bit stream can be limited by the speed of these memories.
Furthermore, the entire bit stream is typically stored in the RAM buffer, before bits of the bit stream may be operated upon. Accordingly, the processing latency depends on the size of the incoming bit stream and the rate at which the bit stream can be handled.
As another example, processor intervention may be required to handle the incoming bit stream. The speed of the processor, therefore, can further limit the data rate of the bit stream. Processors can also be relatively costly and require substantial additional hardware and software resources for functions unnecessary to detecting and substituting bits in a bit stream. If, however, a processor already dedicated for another task is shared, then processing the bit stream reduces the performance of the shared processor.
USPTO Backgrounds
USPTO Backgrounds