The present invention relates to a current sensing circuit and a current sensing method, and particularly to a current sensing circuit and a current sensing method for sensing a current flowing through a power device.
In general, a current mode direct current-to-direct current (DC-DC) converter includes a power metal-oxide semiconductor field-effect transistor (MOSFET) to induce a current in an inductor. The power MOSFET switches in response to a control voltage having a pulse waveform. To generate a stable output voltage, a switching current flowing through a power MOSFET is sensed. The sensed switching current is converted into a voltage that is fed back to a control terminal of the power MOSFET. A switching current flowing through the power MOSFET may be sensed by a sense MOSFET coupled to the power MOSFET.
When the drain-source voltage of a power MOSFET is changed, the ratio of a current flowing through the power MOSFET to a current flowing through the sense MOSFET may change.
FIG. 1 is a circuit diagram illustrating a conventional current mirror circuit, and FIG. 2 is a graph illustrating a relationship between a drain-source voltage (VDS) and a drain current (ID) of a conventional MOS transistor.
Referring to FIG. 1, a current generated by a current source IS flows through an NMOS transistor MN1, and an NMOS transistor MN2 is coupled in a current-mirror configuration to the NMOS transistor MN1. For transistors MN1 and MN2 being of equal size, a current flowing through the NMOS transistor MN2, which is a current flowing through a resistor R1, is equal to the current flowing through the NMOS transistor MN1 when the NMOS transistor MN2 is operated in a saturation region. Referring to FIG. 2, in a saturation region REG2, when the effect of channel-length-modulation is ignored, a drain current ID of NMOS transistor is constant regardless of a drain-source voltage VDS. However, in triode region REG1, the drain current ID of NMOS transistor changes with the drain-source voltage VDS. Thus, when operating in triode region REG1, the drain currents of NMOS transistors MN1 and MN2 would be equal only if both the gate-source voltage VGS and drain-source voltage VDS of transistors MN1 and MN2 are equal.
FIG. 3 is a circuit diagram illustrating a conventional voltage-to-current converter as disclosed in U.S. Pat. No. 5,519,310, wherein a voltage sensing technique is used to force the drain-source voltage VDS of two NMOS transistors MN12 and MN11 to be equal.
Referring to FIG. 3, the voltage-to-current converter includes PMOS transistors MP11 and MP12, NMOS transistors MN11, MN12 and MN13, operational amplifiers OA1 and OA2 and a resistor R11. In FIG. 3, an output current IOUT flowing through the NMOS transistor MN11 is sensed by the NMOS transistor MN12 that has its gate coupled to the gate of the NMOS transistor MN11. A current flowing through the NMOS transistor MN12 is provided to a current-mirror circuit comprised of PMOS transistors MP11 and MP12, and a current flowing through the PMOS transistor MP12 is converted into a voltage by the resistor R11. The operational amplifier OA1 amplifies a difference between an input voltage signal VIN and a feedback voltage signal VF and provides the amplified signal to the gates of NMOS transistors MN12 and MN11. The operational amplifier OA2 and the NMOS transistor MN13 operate to force a drain-source voltage of the NMOS transistor MN12 to be equal to a drain-source voltage of the NMOS transistor MN11. As a result, the current flowing through the NMOS transistor MN12 is proportional to the current flowing through the NMOS transistor MN11.
However, the voltage-to-current converter of FIG. 3 has drawbacks as described below.
The operational amplifier OA2 included in FIG. 3 has a common mode input signal that is near ground voltage GND. Therefore, an amplifier such as a folded cascode amplifier that includes PMOS transistors need to be used. A transient response of the folded cascode amplifier is slow when a quiescent current, i.e., a maximum output current, is limited. In order to make the transient response of the circuit of FIG. 3 fast, the quiescent current needs to be increased which increases the power consumption. In general, the maximum output current is limited in applications with low power requirements.
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