Memory stacks are built by stacking memory dies on top of each other. Each memory die contains a memory array and associated control logic or data buses for distributing the data received from the array. In some single-rank implementations, all different dies belong to a single logical memory device, called a rank. To this end, the memory arrays of the dies are electrically coupled to each other in order to be accessible by common control data lines and word lines (data paths). This interconnection may be achieved by through silicon vias or bonding, i.e., by bonding associated pins of the memory dies to one common terminal. In other implementations, dual or multi-rank devices are constructed, in which multiple memory dies stacked on top of each other correspond to two or more different ranks. To this end, only the control data lines of those dies corresponding to a single-rank are electrically coupled.
Furthermore, the memory dies may support different I/O modes, such as, for example, a ×4 I/O and an ×8 I/O mode. In order to manufacture the different stacks required by the market, multiple configurations of memory dies are produced, such as, for example, one ×4 I/O mode for single-rank implementations and one ×4 I/O die for dual-rank implementations. Of course, for ×8 I/O configurations, the same distinction between the memory dies has to be made in order to provide memory dies comprising interconnection circuitry suited for single-rank as well as for dual-rank implementations. That is, multiple different memory dies are developed and separately put on stock. Furthermore, if one memory die or the memory array of the die fails in a quality test, the complete hard-wired memory stack may be rendered unusable, only due to the defect of one memory die of, for example, eight memory dies in a common dual-rank implementation. As a consequence, the remaining seven layers of the stack would be sorted out together with one failing layer, which may result in yield numbers below 20%.
USPTO Backgrounds
USPTO Backgrounds