Electronic devices and systems such as printers, copiers, electronic storage devices (memories) high definition television, enhanced definition television and computational devices (e.g. calculators and computers including personal computers, minicomputers, personal computers and microcomputers) requiring electronic storage devices, often provide data storage on an integrated circuit chip. Because these devices often require large amounts of storage space for many applications, these storage devices are embodied in memory, for instance, a dynamic random access memory (DRAM). Memory cells sometimes contain or are associated with defects. It is therefore necessary to replace this defect memory or defect associated memory with memory from alternate memory cells commonly referred to as redundant memory. Once defective memory is detected the address corresponding to this memory is noted and before the memory is used, the mechanism for implementing the redundant memory cells is usually embodied in a system based on blowing fuses. The scheme for producing a signal indicative of the desire to use the redundant memory or rather to match the address of the defective memory is of extreme importance. The redundancy scheme, particularly the address match scheme, forms an integral part of the dynamic random access memory. The address match scheme is also an integral part of the above described devices and systems, supplying substantial value to these and other devices and systems in which it is used.
Address match schemes in the past have been used wherein a fuse associated with a given bit position of an address is blown located in the path between a selected transistor from a plurality of transistors and a common node between the transistors. The fuse blown corresponds to a particular logic state of the address. For instance, fuses can be blown corresponding to the logic ones in an address. Alternatively, but not interchangeably within the scheme, fuses can be blown corresponding to the logic zeros in an address. FIG. 1 illustrates a prior art address match scheme for a 4 megabit (4 meg) DRAM. A plurality of n-channel transistors 2 is illustrated with each transistor connected at its drain to a fuse 4. A plurality of inverters 6 are illustrated with each inverter connected to an associated gate of a transistor from the plurality of transistors 2. The input to each inverter 6 is denoted by labeling address factors F0 through F23 and nodes for receiving address bits A12 and A.sub.-- 12. The character .sub.-- used throughout in connection with a label herein indicates a node which receives the complement of a signal going to or coming from the node without such a character. Consequently, bit A12 receives the complement of the signal going to bit A.sub.-- 12 and vice versa. Each fuse 4 is connected to the input of inverter 8 whose output is capable of transmitting a signal in connection with the activation of a redundant row of memory. Pull-up p-channel transistor 10 is connected by its gate to the output of inverter 12 whose input is connected to each fuse 4 and the input of inverter 8.
The left half of FIG. 1 illustrates a schematic drawing of the logic circuit used in determining the signals used at nodes representing address factors F0 through F23. Complemented address signals from address bits A.sub.-- 0 through A11 are received by NAND gates 14 as shown. Every address bit from a set of two address bits and the complements of those address bits are NANDed together as shown resulting in 4 address factors for input into inverters 6.
Since every address and its complement from a set are NANDed together, only one such combination (the one with logic high inputs to a NAND gate) of NANDed addresses produces a logic low output as an address factor. The inverter from the plurality of inverters 6, which receives the logic low address factor signal will energize the gate of the associated transistor from the plurality of transistors 2. In order to activate a redundant row of memory cells the input of inverter 8 must remain at around roughly one transistor 10 threshold voltage drop below voltage Vdd, or rather at a voltage corresponding to a logic high. Output OUT at inverter 8 will output a logic low signal in connection with activating a redundant row of memory. Therefore, fuse 4 associated with the energized gate of a transistor from the plurality of transistors 2, must be blown to keep the input to inverter 8 a logic high. Thus, as shown in FIG. 1 one fuse 4 associated with a set of four address factors must be blown in order to ensure that the redundancy row is activated. For the 4 megabit memory address scheme, there are 6 sets of four address factors, thus 6 fuses must be blown in order to activate the redundancy row. Additionally, in order to activate any redundancy row, fuses 4 for address bits A12 or A.sub.-- 12 must be blown as dictated by the most significant bit of the address in which redundancy is sought. Consequently if the most significant bit of the address is a logic 1, then fuse 4 corresponding to address bit A12 must be blown. Likewise, if the most significant bit of the address is a logic 0, then fuse 4 corresponding to address bit A.sub.-- 12 must be blown. As a result, a total of 7 fuses must be blown in the 4 megabit address match scheme illustrated in FIG. 1.
FIG. 2 illustrates a prior 16 megabit (16 meg) DRAM type address match scheme. This scheme is similar to the 4 meg scheme discussed above. However, the scheme shown in FIG. 2 uses the plurality of fuse circuits illustrated. In the fuse circuits shown in FIG. 2, field effect transistor 14 is connected to field effect transistors 16, 18, and 20. Additionally, the fuse circuits comprise inverter 22 connected to fuse 24. Transistor 20 receives an address bit signal at one of its terminals while transistor 18 receives the complement of this address bit signal at one of its terminals. Transistors 18 and 20 generally have a lower threshold voltage than the other transistors shown in FIG. 2. In an effort to activate a redundancy memory cell corresponding to a selected address, fuse 24 is blown when the selected address bit corresponding to the signal sent to transistor 20 is a logic 1 or rather a logic high value. However, fuse 24 is not blown when the address bit corresponding to the signal sent to transistor 20 is a logic 0 or rather a logic low value. Note that when fuse 24 is not blown, the gate of transistor 18 is energized and the A.sub.-- signal at the terminal of transistor 18 is transferred to the address factor. Otherwise, when fuse 24 is blown, the gate of transistor 20 is energized and the A signal is transferred to the address factor. After receiving a start up pulse, at the gate of transistor 14, signals are produced as address factors RA0 through RA11 which are each input into the inverters from the plurality of inverters 6. In order to activate a redundant memory cell, address factors RA0 through RA11 are all at a logic 0 level such that a logic low signal results at the output of inverter 8. Address bit signals A12 and A.sub.-- 12 with fuses 4 function as discussed with respect to the 4 meg scheme. The minimum number of fuses blown in the 16 meg scheme is one. The maximum number of fuses blown is thirteen, while the average number of fuses blown is seven. In the drawing of FIGS. 2 there are fourteen fuses.
The main problem with the foregoing address redundancy match schemes is that the process of blown fuses takes a considerable amount of process time. Therefore, an address redundancy match scheme is needed that minimizes the number of blown fuses needed.
USPTO Backgrounds
USPTO Backgrounds