The referenced applications describe the high density packaging of integrated circuits which is common in modern electronic equipment, particularly data processors. The need exists for convenient and reliable methods for testing integrated circuit chips both separately and mounted in-place in a working configuration.
In connection with the testing of integrated circuit chips, it is known that depending upon the logic function of a given chip, a digital reference pattern or signature exists on all of its input and output pins at the end of a test routine. More specifically, in the case of a chip bearing sequential logic in the form of gates, a pseudo-random test sequence may be employed to exercise the logic function. At the conclusion of a predetermined number of interactive iterations of the test sequence, a unique signature for the chip will be present. Assuming that the chip is satisfactory, all similar chips will have the identical signature. In practice, a computer may be programmed to simulate the pseudo-random test and to define the proper signature for the chip as a function of its logic. Deviation of the signature present after an actual test sequence with that defined by the computer analysis, is indicative of a defective chip.
It is present-day practice to make the known signature available to the test technician through the use of tables, annotated schematics, etc. Various visual forms of documenting signatures are depicted in FIGS. 4, 5, 6 and 8 of a technical article entitled "Signature Analysis--Concepts, Examples, and Guidelines" by Hans J. Nadig, appearing in the May 1977 issue of the "Hewlett-Packard Journal". In another related publication of the Hewlett-Packard Company, dated April 1977, and entitled "Application Note 222, A Designer's Guide to Signature Analysis", Section VI, "Documentation", mentions "annunciating schematics", "signature tables", "signature maps" and "troubleshooting trees" or "flow diagrams" for documenting signatures in a service manual. The updating of such documentation is difficult to implement and is costly. Furthermore, the loss of such documentation may render the tester useless.
The ideal solution to the signature documentation problem is the inclusion of the final signature within the chip itself during its manufacture, such that it can be read by the tester without human intervention. The present invention offers such a solution.
USPTO Backgrounds
USPTO Backgrounds