1. Field of the Invention
The present invention relates to integrated data processing systems and, in particular, to a processor system that integrates the functions of both a general purpose CPU core and a parallel, independently operating digital signal processor (DSP) module, and wherein the system is capable of implementing glitchless switching between different asynchronous frequencies.
2. Discussion of the Prior Art
Commonly assigned and co-pending U.S. patent application Ser. No. 467,148, filed Jan. 18, 1990, by Intrater et al. for INTEGRATED DIGITAL SIGNAL PROCESSOR/GENERAL PURPOSE CPU WITH SHARED INTERNAL MEMORY, now U.S. Pat. No. 5,630,153, discloses a data processing system that utilizes integrated general purpose processor (i.e., the National Semiconductor Corp. 32FX16 embedded processor) and digital signal processor (DSP) functions that are connected for common access to an internal shared memory array. The shared memory array stores the operands for a set of basic DSP operations that can be executed by the DSP function. The sequence of DSP operations to be executed by the DSP function is selectively configurable by the general purpose processor function; that is, the general purpose processor can define a variety of DSP algorithms that can be executed by the DSP function for processing different digital input signal formats.
In addition to storing the operands required by the DSP function for execution of a DSP algorithm, the internal shared memory array also stores selected instructions and data required by the general purpose processor function for execution of general purpose tasks. The operands, instructions and data may be selectively loaded to the internal shared memory array from system memory. After execution of a DSP algorithm, the corresponding information set may be down-loaded from the internal memory array to system memory and a new information set retrieved for execution of a subsequent DSP algorithm or a new general purpose processor task.
Thus, the general purpose processor selects a DSP algorithm for conditioning and recovering digital data from the incoming signal. That is, the general purpose processor selects from the set of basic DSP operations to define a specific sequence of DSP operations appropriate for processing the incoming signal. The general purpose processor then retrieves operands required for execution of the selected DSP algorithm and/or instructions and data critical to the general purpose processor for controlling the DSP function or for performing general purpose tasks and loads them into the internal shared memory array. Next, the general purpose processor invokes the first DSP operation in the selected sequence and the DSP function performs the DSP operation utilizing operands retrieved by the DSP function from both the shared memory array and system memory. Upon completion of the DSP operation by the DSP function, the general purpose processor function either reads the result of the DSP operation, invokes the next DSP operation in the selected sequence or performs a general purpose task.
While the input signal to the data processing system may be received directly from a digital source, the system described in the above-identified application includes an analog front end that converts a modulated input signal received on an analog channel to corresponding digital signal for processing by the data processing system.
Thus, the above-described data processing system provides unique system partitioning by integrating a small DSP module and a general purpose processor. This unique partitioning provides a single processor solution for both DSP and general purpose computations that can utilize the same programming model and the same system development tools for both functions. The DSP module provides the capability necessary to handle a variety of DSP requirements. The internal shared memory allows the DSP algorithms to be tuned or changed or new algorithms to be added to meet changing, expanding system requirements. General purpose, computation intensive tasks can also be executed directly from the internal shared memory.
While the above-described system provides a unique and innovative architecture for many DSP applications, it lacks the DSP computing capability that could be provided by a solution that integrates the general purpose function and a parallel, independently-operable DSP function on the same integrated circuit chip.
(U.S. patent application Ser. No. 467,148, including its Appendix A, are hereby incorporated by reference to provide additional background information regarding the invention disclosed herein.)
USPTO Backgrounds
USPTO Backgrounds