1. Field of the Invention
The present invention relates to high density memory devices based on phase change memory materials, including chalcogenide based materials and on other programmable resistance materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistance material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the molten phase change material and allowing at least a portion of the phase change material to stabilize in the amorphous state.
The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material.
One approach to reducing the size of the phase change element in a memory cell is to form small phase change elements by etching a layer of phase change material. However, reducing the size of the phase change element by etching can result in damage to the phase change material due to non-uniform reactivity with the etchants which can cause the formation of voids, compositional and bonding variations, and the formation of nonvolatile by-products. This damage can result in variations in shape and uniformity of the phase change elements across an array of memory cells, resulting in electrical and mechanical performance issues for the cell.
Additionally, it is desirable to reduce the cross-sectional area or footprint of individual memory cells in an array of memory cells in order to achieve higher density memory devices. However, traditional field effect transistor access devices are horizontal structures having a horizontally oriented gate overlying a horizontally oriented channel region, resulting in the field effect transistors having a relatively large cross-sectional area which limits the density of the array. Attempts at reducing the cross-sectional area of horizontally oriented field effect transistors can result in issues in obtaining the current needed to induce phase change because of the relatively low current drive of field effect transistors.
Thus, memory devices including both vertically and horizontally oriented field effect transistors have been proposed. See, for example, U.S. Pat. No. 7,116,593. However, the integration of both vertically and horizontally oriented field effect transistors can be difficult and increase the complexity of designs and manufacturing processes. Thus, issues that devices having both vertically and horizontally oriented field effect transistors need to address include cost and simplicity of manufacturing.
Although bipolar junction transistors and diodes can provide a larger current drive than field effect transistors, it can be difficult to control the current in the memory cell using a bipolar junction transistor or a diode adequately enough to allow for multi-bit operation. Additionally, the integration of bipolar junction transistors with CMOS periphery circuitry is difficult and may result in highly complex designs and manufacturing processes.
It is therefore desirable to provide both vertically and horizontally oriented field effect transistors on the same substrate that are readily manufactured for use in high-density memory devices, as well as in other devices that may have a need for both types of transistors on one chip. It is also desirable to provide memory devices providing the current necessary to induce phase change, as well as addressing the etching damage problems described above.
USPTO Backgrounds
USPTO Backgrounds