1. Field of the Invention
The present invention relates to an image sensor for outputting pixel data imaged by an X-Y address scanning system in chronological order from each of pixel elements arranged in matrix.
2. Description of the Related Art
As a system in which pixel data is sequentially read from each of pixel elements in an image sensor, there has been generally employed an X-Y address scanning system in which positions in an X-direction and a Y-direction are sequentially designated on a pixel element basis by address scanning circuits for the X-direction and the Y-direction to read the pixel data from each of the pixel elements in chronological order (for example, refer to JP 2003-87660 A).
As a basic operation, while a Y address is set, an X address is sequentially incremented. When image data of all the X addresses for the set Y address has been read, the Y address is incremented to sequentially read the image data from the pixel elements.
However, in the conventional image sensor disclosed in JP 2003-87660 A and so on, the X address is incremented when a clock is input, where the Y address is read from is set, and therefore it is necessary to set the Y address according to a write signal. When the Y address is set, it is necessary to enable writing into the Y address and to disenable the writing into the Y address upon completion of the writing.
Conventional examples of the image sensor using the X-Y address scanning system include a circuit configuration illustrated in FIG. 4. FIG. 5 is a timing chart illustrating an operation of an image sensor of FIG. 4.
When the write signal RE is input to the image sensor during a disenable period (period of “L” level) where no Y address scanning enable signal is input to the image sensor from an external terminal, a Y address is written into a register latch 100 from a data bus. Then, Y address signals YA1 to YA4 resulting from decoding the Y addresses are set in a Y address register 101 according to the write signal RE, but none of those signals are output at this time.
Then, the Y address register 101 outputs, to a pixel element matrix 103, any one of the Y address signals YA1 to YA4, that is, a Y address signal corresponding to the Y address at, for example, “H” level during an enable period (period of “H” level) where the Y address scanning enable signal is input. The Y address does not change even if the write signal RE is input to the image sensor during the period during which the Y address scanning enable signal is input thereto.
The Y address scanning enable signal is input to the image sensor, and an X address control unit 102 increments the X address, and outputs, to the pixel element matrix 103, any one of X address signals XA1 to XA4, that is, an X address signal corresponding to the X address at, for example, “H” level at timing at which the X address scanning enable signal synchronous with an internal clock is sequentially input thereto.
Then, pixel data is read from a pixel element selected from an X pixel element matrix according to the Y address signal and the X address signal.
However, in the case of the image sensor illustrated in FIG. 4, the external terminal for inputting the Y address scanning enable signal is required, and provision of the external terminal inhibits a reduction in the size of an image sensor chip.
On the other hand, another conventional example of the image sensor using the X-Y address scanning system is a circuit configuration illustrated in FIG. 6. FIG. 7 is a timing chart illustrating an operation of an image sensor of FIG. 6. A circuit of FIG. 6 is configured to generate the Y address scanning enable signal with the aid of an internal circuit according to the write signal RE, without provision of the external terminal for inputting the Y address scanning enable signal. A register latch 200 brings the Y address scanning enable signal that is output to a Y address register 201 into a disenable state at a falling edge of a first write signal RE1.
As a result, the Y address register 201 does not output any one of Y address signals YA1 to YA4 obtained by decoding the Y addresses input from the register latch 200.
Subsequently, the register latch 200 holds the Y address input from the data bus in response to a falling edge of a second write signal RE2, and outputs the held Y address to the Y address register 201.
Then, the register latch 200 brings the Y address scanning enable signal into an enable state at a falling edge of a third write signal RE3.
As a result, the Y address register 201 decodes the Y address input from the register latch 200, and resultantly outputs any one of the Y address signals YA1 to YA4, and selects any one of rows of the pixel elements in a pixel element matrix 203. Further, an X address control unit 202 selects any one of columns of the pixel elements in the pixel element matrix 203 as in the circuit of FIG. 4. As a result, any one of the pixel elements in the pixel element matrix 203 is selected to read pixel data therefrom.
However, in the case of the image sensor illustrated in FIG. 6, no external terminal for inputting the Y address scanning enable signal is required, but it is necessary to generate the write signals RE by three pulses (a plurality of pulses) with respect to one writing of Y address. As a result, the image sensor suffers from a defect that an external circuit for generating the write signal RE is complicated in configuration, and the circuit scale becomes larger.
USPTO Backgrounds
USPTO Backgrounds