The active matrix panel display elements possess many merits of thin frame, power saving, no radiation, etc. and have been widely used. The Organic Light Emitting Diode (OLED) display technology is a flat panel display technology which has great prospects for development. It possesses extremely excellent display performance, and particularly the properties of self-illumination, simple structure, ultra thin, fast response speed, wide view angle, low power consumption and capability of realizing flexible display, and therefore is considered as the “dream display”. Meanwhile, the investment for the production equipments is far smaller than the TFT-LCD (Thin Film Transistor-Liquid Crystal Display). It has been favored by respective big display makers and has become the main selection of the third generation display element of the display technology field. At present, the OLED has reached the point before mass production. With the further research and development, the new technologies constantly appear, and someday, there will be a breakthrough for the development of the OLED display elements.
The Oxide Semiconductor possesses higher electron mobility and non crystalline structure, and has higher compatibility with the amorphous silicon process. Therefore, the Oxide Semiconductor has been widely utilized in the skill field of large scale Organic Light Emitting Display.
At present, the common structure of the oxide semiconductor TFT substrate is the ESL (Etching Stop Layer) structure. However, the structure itself has some problems. For example, the uniformity of the etching is difficult to control, and the additional mask and photolithographic process are required, and the gate overlaps with the source/the drain, and the storage capacitor is larger, and it is difficult to reach high resolution.
In comparison with the Etching Stop Layer structure, the Coplanar oxide semiconductor TFT substrate structure is more reasonable and has the production prospect which is more possible. As shown from FIG. 1 to FIG. 5, disclosed is a manufacture method of a co-planar oxide semiconductor TFT substrate structure according to prior art, comprising steps of:
step 1, providing a substrate 100, and deposing a first metal layer on the substrate 100, and patterning the first metal layer with a photolithographic process to form a first gate 210 and a second gate 220 which are separately positioned;
step 2, deposing a gate isolation layer 300 on the first gate 210, the second gate 220 and the substrate 100, and patterning the same with a photolithographic process to form a first via 310 in the gate isolation layer 300 correspondingly above the second gate 220;
step 3, deposing a second metal layer on the gate isolation layer 300, and patterning the second metal layer with a photolithographic process to form a source 410, a drain 420, which are separately positioned, and forming a second via 425 on the drain 420;
Specifically, the drain 420 is connected with the second gate 220 through the first via 310.
step 4, deposing an oxide semiconductor layer on the source 410, the drain 420 and the gate isolation layer 300, and patterning the same with a photolithographic process to form an active layer 500, and the active layer 500 comprises a main body 520 and a channel 510 connected to the main body 520 between the source 410 and the drain 420;
step 5, deposing a passivation layer 600 on the active layer 500, the source 410 and the drain 420, and patterning the same with a photolithographic process to form a third via 610 in the passivation layer 600 correspondingly above the drain 420.
Specifically, the passivation layer 600 fills in the second via 425 on the drain 420.
In the co-planar oxide semiconductor TFT substrate structure manufactured by the aforesaid method, the channel 510 of the active layer 500 is a long channel. The active layer 500 possesses lower mobility and higher leak current. The performance of the TFT element is worse.
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