1. Field of the Invention
This invention is a digital multiplexer and demultiplexer circuit having a data transmission line and a synchronization line suitable e.g., for system control multiplexing.
2. Description of the Prior Art
U.S. Pat. No. 3,804,982 shows a serial data transmission system wherein one line is used for data and synchronization, unlike the present invention wherein a separate synchronization line is employed.
U.S. Pat. No. 4,054,754 is a data transmission system wherein the synchronization information is interleaved with data and goes out on line SDOUT (see FIG. 5). TSWOUT is not a synchronizer.
U.S. Pat. No. 4,050,062 is an analog to digital multiplexer employing parallel data transmission. The present invention is a digital multiplexer employing serial transmission.
U.S. Pat. No. 2,962,552 is an analog, not a digital, multiplexer which does not discuss synchronization in detail. The synchronization circuitry 15, 16, 17, 18 and 19 comprises extraneous boxes which are not relevant to the present invention.
U.S. Pat. No. 3,980,820 is a repeater, not a multiplexer. It resends data at a new phase. It reclocks the data with new clock 10. It employs separate clock and synchronization inputs. The present invention combines a clock function and word synchronization on a single line.
Secondary references, in which data information and synchronizing information are interleaved, are: U.S. Pat. Nos. 2,548,345, 2,495,168, 3,162,838, 3,353,158, 3,404,231 and 4,031,316.
USPTO Backgrounds
USPTO Backgrounds