1. Field of the Invention
The present invention relates to digital-to-analog converted data accessing in an automatic alignment monitor test system used for video monitor display testing under a specific display mode.
2. Description of the Prior Art
At present, video monitors used in personal computers must be capable of displaying various display modes required by various applications of customers, such as EGA mode, VGA mode, or 780*1024 mode, etc. However, conventional monitors when switching between distinct display modes can not typically display one standard screen frame due to the changes of the horizontal/vertical size/phase (H.sub.-- size, H.sub.-- phase, V.sub.--4 size, V.sub.-- phase) and other parameters. As a result, users would then need to manually adjust knobs associated with these parameters (usually in front of the monitors) to appropriately display the monitor frames for various display modes.
To address the framing problem associated with having various display modes, an automatic alignment system can be employed during monitor manufacturing testing to determine optimal parameters of the monitor for the various display modes. The optimal parameters are then stored in memory devices (e.g., EEPROMs in the monitor's control board). When a computer user then wants to use a specific monitor display mode, the optimal parameters stored in the EEPROMs for the specific mode can be fetched and transmitted to the monitor after a digital-to-analog conversion. This will enable the user to achieve the best viewing state for the various display modes.
The configuration of a typical automatic alignment system is shown in FIG. 1 and includes monitor 5, microcontroller 1 mounted on a monitor controlling board (not shown), camera 7, and auto-alignment adapter 3. The method of automatic alignment operates as follows. When the testing begins, microcontroller 1 will transmit predefined display parameters of a specific display mode to monitor 5 over control lines 4 and also to auto-alignment adapter 3 over signal lines 6. Meanwhile, camera 7 visually captures frame information of monitor 5 and also transmits related frame data to auto-alignment adapter 3 over signal lines 8. According to the frame data transmitted from camera 7 and the pre-defined display parameters from microcrontroller 1, auto-alignment adapter 3 will decide whether monitor 5 is in its best state, and if it's not, how much deviation exists between the parameters received from the microcontroller and the data received from the camera. Auto-alignment adapter 3 thens inform microcontroller 1 of the needed display parameter modifications. This process is performed recursively until the optimal parameters of the specific display mode are obtained. Finally, microcontroller 1 stores the code of the display modes under test and their optimal parameters into the monitor control board EEPROMs.
Conventional microcontroller 1 is shown in FIG. 2 and includes CPU 11 connected to communication interface 12 over lines 15 and to memory mapping registers 13 over lines 17. Communication interface 12 is also connected to auto-alignment adapter 3 over signal lines 6. DACs 14 are coupled to monitor 5 over signal lines 4. There are a plurality of DACs in microcontroller 1, some corresponding to every parameter of a display mode and the others reserved for future need. The parameters of the display mode are transmitted between microcontroller 1 and auto-alignment adapter 3 by means of communication interface 12. When auto-alignment adapter 3 needs to access contents of one of the DACs 14 (e.g., when the parameters are to be written into the DAC) CPU 11 addresses corresponding memory mapping registers 13. For example, consider that there are six factors serving as the display mode parameters, including H-size, V-size, H-phase, V-center, Pincusion, Trapzoid. Thus, six corresponding DACs will receive the six factors from corresponding memory mapping registers, respectively. The factor data is in turn converted to analog form and transmitted to the monitor.
The hardware configuration for such a conventional DAC data accessing scheme has disadvantages. First, communication interface 12 must be prepared and stand between auto-alignment adapter 3 and CPU 11 to relay the DAC data accessing request. Such dedicated hardware logic circuitry adds to the overall complexity and cost of the design.
Secondly, communication firmware must be provided for communication interface 12 to commence the communication procedure between CPU 11 and auto-alignment adapter 3 for the transfer of the data. The complexity of the overall system firmware is thereby increased, as well as having an added storage requirement to accomodate this added communication firmware.
And, finally, the task of auto-alignment adapter 3 accessing the DAC data becomes complicated since auto-alignment adapter 3 must issue its request via communication interface 12 to CPU 11. Thereupon, CPU 11 writes the requested data into memory-mapped register 13. This is typically accomplished under control of a software service routine that introduces timing delays in obtaining the data, thereby reducing the overall data acquisition throughput and the production speed.
USPTO Backgrounds
USPTO Backgrounds