FIG. 7 shows a simplified semiconductor device disposed in a three-dimensional (3D) package arrangement including two silicon chips 10-1 and 10-2 that are stacked vertically and separated by an insulating layer 13. Silicon chip 10-1 and 10-2 respectively include integrated circuits (ICs) 20-1 and 20-2 fabricated thereon using conventional (e.g., CMOS) fabrication processes, with IC 20-1 being connected by conventional metal wiring structures to contact pads 17 and to a conductor 18-1, and IC 20-2 being connected to a conductor 18-2. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. To avoid these edge-wiring issues, the 3D package arrangement shown in FIG. 7 utilizes a through-silicon via (TSV) 30, which is a vertical electrical connection (Vertical Interconnect Access, or “via”) structure passing completely through silicon chip 10-1. Conventional methods for producing TSV 30 typically involve drilling a hole partially through upper surface 11 of the silicon wafer material from which chip 10-1 is diced, then filling the hole with an electrically conductive material (e.g., Copper or Tungsten), and then grinding the back side of the silicon wafer to expose a lower end portion 32 of TSV 30. During subsequent processing, an upper end portion 31 of TSV 30 is connected by conductor 18-1 to IC 20-1, and lower end portion 32 is connected during package assembly by a solder structure 40 to conductor 18-2. TSV 30 thus forms a vertical interconnect between IC 20-1 and IC 20-2 that minimizes timing delays due to shorter signal paths lengths, and provides a smaller 3D package arrangement over conventional edge-wired 3D package arrangements (i.e., because the package width is effectively defined by the peripheral edge of chips 10-1 and 10-2, and because the absence of an interposer allows for a flatter/thinner profile). In addition, because chip-to-chip connections are disposed between opposing surfaces of chips 10-1 and 10-2 (e.g., by solder structure 40), the TSV 3D package arrangement facilitates a substantially higher number of chip-to-chip connections than is possible using edge-wired 3D package arrangements.
Although TSVs facilitate superior 3D package arrangements, the development of methodologies for testing TSVs has proven to be a challenge. Conventional IC testing is typically conducted during process known as “wafer sort” to verify that the circuitry functions properly before the wafer is diced and the resulting chips are assembled into packages. The TSV production process leads to defects within the TSV which can include voids that produce improper (i.e., high impedance) connections to adjacent devices or interposer layers, thereby requiring that the integrity of each TSV also be tested during wafer sort. Because conventional IC fabrication involves forming the IC on only one side of a silicon wafer, conventional IC testing is typically performed entirely from one side of the silicon wafer using a single probe assembly that applies and detects test signals to/from the IC's contact pads (e.g., contact pads 17 in FIG. 7). In contrast, TSV testing requires verifying that signals are properly passed from one side of the chip to the other, which requires simultaneously accessing both ends the TSVs (e.g., both upper end portion 31 and lower end portion 32 of TSV 30, shown in FIG. 7). Although it is possible to modify existing IC test equipment to configure two test probe arrays that respectively contact both sides of the wafer, this modification is problematic due to the complexity of simultaneously accessing a large number of contact pads disposed on both sides of a wafer.
What is needed is a cost-effective method for testing TSVs that requires minimal modifications to existing IC test equipment.
USPTO Backgrounds
USPTO Backgrounds