The present invention relates to a package structure for a semiconductor device, particularly a mark structure for recognizing the location of a chip cavity provided in a ceramic package for a semiconductor device.
Recently, there has been a tendency to increase the integration of semiconductor integrated circuits, and, consequently, it has become necessary to enlarge the size of the semiconductor chip.
A semiconductor chip is mounted in a chip cavity of a ceramic package for the semiconductor device. The size of the chip cavity, in turn, is limited by the size of the package. Consequently, it is necessary that the clearance between the chip and the chip cavity be extraordinarily small in a case in which a large scale integrated circuit chip is mounted on a conventional package.
In order to exactly recognize the location of a chip cavity, e.g., by means of a TV camera, marks are generally provided on the ceramic sheet of the package.
Two types of mark structures are known for recognizing the location of a cavity provided in a semiconductor package.
In FIG. 1, marks M are formed within a metallized chip stage 1 on a first sheet S.sub.1, in a chip cavity C. This structure can be explained in more detail by referring to FIG. 2. A first window 4 is opened in a second sheet S.sub.2, on which an internal conductor pattern 3 is metallized so as to form a wire-bonding area WB. A second window 7 is opened in a third sheet S.sub.3. The first window 4 and the second window 7 constitute the chip cavity C. These three ceramic sheets are laminated as green sheets and are fired to form a package for a semiconductor device.
The terms "alignment" and "mal-alignment" described hereinafter refer to the locational relationship between the chip cavity and the marks for recognizing the chip cavity; in other words, to the relationship between the location of the produced marks and the designated location of the marks in respect to the location of the chip cavity, i.e., the window.
In the prior art mark structure, two kinds of mal-alignment are apt to take place. One is due to inappropriate registration in metallizing the chip stage. The other is due to the inappropriate lamination of the second sheet on the first sheet. The amount of mal-alignment of the marks in respect to the first window 4 amounts to .+-.0.2 mm.
In the second type of mark structure, the marks M are formed within the wire-bonding area WB on the second sheet S.sub.2, in the chip cavity C (FIG. 3). The marks M and the internal conductor pattern 3 are printed simultaneously on the second sheet S.sub.2. Then, the first window 4 is punched through the second sheet S.sub.2. Therefore, due to inappropriate registration between the printing and the punching, the mal-alignment of the marks in respect to the first window 4 amounts to .+-.0.1 mm.
Thus, the clearance between the chip and the chip cavity is inevitably limited by the amount of mal-alignment, i.e., .+-.0.1.about.0.2 mm.
USPTO Backgrounds
USPTO Backgrounds