1. Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly to large arrays of high-speed, high-density memory cells on semiconductor substrates. Specifically, the present invention relates to cache or associative memories that are addressed by virtual or translated addresses.
2. Background of the Invention
Advances in semiconductor processing techniques and improved memory cell designs have permitted semiconductor random access memory chips to be manufactured with an ever-increasing memory capacity in excess of one million bits. In general, the preferred construction of such a memory is a square array of rows and columns of memory cells. To address a bit of information, a row address is first transmitted to the memory chip along with a row address strobe signal. The row address is decoded to assert a signal on a "word line" extending across a selected row of memory cells. In response, each cell in the row asserts a stored information signal on a respective bit line extending along the cell's column in the array. During this time, a column address indicating an addressed bit line is transmitted to the memory chip along with a read or write signal. For a read operation, the information signal is read from the addressed bit line and asserted on an input/output line. For a write operation, an information signal from the input/output line is asserted on the addressed bit line and is written into the addressed memory cell.
For some special applications, such as associative or cache memories, a square array of memory cells does not match the required data organization. In these instances, rectangular memory arrays have been used, despite the natural preference for a square array.
USPTO Backgrounds
USPTO Backgrounds