The present invention relates to a storage media reading system which can extract a sync clock signal for information reproduction and reproduced data from information recorded in the form of combinations of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in a digital versatile disc (DVD), a compact disc-read only memory (CD-ROM) or the like with use of such a phase-locked loop circuit as a phaselocked loop (PLL).
Recorded on an optical disc such as a DVD or CD-ROM are information or data in the form of combinations of logical values of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. For example, when the sync clock signal has a period of T, data is recorded in combinations of signal periods of 3T to 11T. Such data recorded on the optical disc is read out by a pickup and waveform-equalized by a preamplifier and digitized to generate a binary signal. In order to reproduce recorded data from the binary signal, the PLL circuit reproduces a sync clock signal on the basis of the binary signal, and the binary signal is used as reproduced data synchronized with the reproduced sync clock signal. At this time, synchronization is achieved in the PLL circuit so that an edge of the binary signal and a falling edge of the sync click signal (when the sync clock signal has a duty of 50%, the falling edge of the sync clock signal corresponds to a middle point between adjacent rising edges of the sync clock signal) are made to be coincided. Under this condition, when the binary signal is latched at a rising edge of the sync clock signal, a highest quality of reproduced data can be acquired.
The aforementioned technique is conventionally known and is valid when the duty of the sync clock signal is 50%. However, when the duty of 50% cannot be secured, the timing of rising or falling (level change) in the binary signal goes out of the middle point between adjacent edges of the sync clock signal. Under such a condition, a small jitter takes place in the sync clock signal or binary signal, the normal value of the binary signal cannot be latched, thus resulting possibly in that erroneous reproduced data is output. In order to realize a sync clock signal having a duty of 50%, it is usual to generate a clock signal of a frequency twice as high as a required frequency and frequency divide the generated clock signal. However, nowadays, it has become difficult to generate such a high frequency signal as a transfer rate is increased. A disc such as a DVD or CD-ROM is rotated at a high speed for the purpose of enabling high-speed access, and a data transfer rate tends to also be increased correspondingly.
It is also substantially difficult to forcibly make the timing of level change in the binary signal coincide with the timing of a middle point between adjacent edges of the sync clock signal, including logical gate delay or changes in the characteristics of circuit elements. It is difficult to predict fluctuations in the duty of a clock generated in the interior of an LSI or variations in the logical gate delay upon manufacturing it.
Disclosed in JP-A-7-221800 (laid-open on Aug. 18, 1995) is a technique for automatically adjusting the phase of an edge of a clock signal to be input to a data discriminating/reproducing circuit at a already-determined phase, wherein the values of input data for phases leading or lagging with respect to a reproduced clock signal are compared with the value of the input data for the phase of the reproduced clock signal, land the phase of the reproduced clock signal in a phase synchronization loop is automatically adjusted so that these data values become equal to each other. Since this technique is directed to adjustment of the phase of the reproduced clock signal per se. separately from the phase synchronization loop, however, a result of the phase adjustment does not accurately reflect even another clock signal having a phase difference given for the aforementioned comparison, and thus it is expected that, when a data transfer rate is high, it becomes difficult to perform the phase adjustment.
It is therefore an object of the present invention to provide a storage media reading system which can generate a sync clock signal from a signal read out from a recording medium, can use the clock signal to reduce an error generated at the time of reproducing data, and can achieve a high quality of reproduction of digital data.
In accordance with an aspect of the present invention, there is provided a storage media reading system which comprises:
a phase detector having first and second input terminals, a binary signal obtained from data recorded on a recording medium and carrying the data being supplied to said first terminal;
a voltage controlled oscillator for generating (2m+1) multi-phase clock signals (m being a positive integer) which are changed in oscillation frequency according to an output of the phase detector and which are mutually shifted in phase by an integral multiple of 2xcfx80/(2m+1) and for extracting one of these multi-phase clock signals as a sync clock signal for data reproduction and for supplying part of the sync clock signal to the second input terminal of the phase detector;
a variable delay circuit for delaying the binary signal by a controllable delay time to generate a binary delayed signal; and
a delay control circuit including first circuits for determining a value of the binary delayed signal from the variable delay circuit in synchronism with the sync clock signal to generate a reproduced data signal and also including a second circuit for comparing a phase of the binary delayed signal from the variable delay circuit with phases of the multi-phase clock signals from the voltage controlled oscillator to generate a delay control signal to be supplied to the variable delay circuit for control of the delay time, and
wherein the reproduced data signal and sync clock signal are used to reproduce the data recorded in the recording medium.
In accordance with another aspect of the present invention, there is provided a storage media reading system which comprises a data reproducing circuit for reproducing a sync clock signal in a phase-locked loop circuit on the basis of a digital binary signal read out from a recording medium and for generating reproduced data through synchronization of the binary signal with the sync clock signal. The phase-locked loop circuit has a ring type voltage-controlled oscillator in its phase-locked loop which includes an odd number of delay gate stages whose delay times are determined by the phase comparison result. One of outputs of the delay gate stages is used as a sync clock signal fed back in the phase-locked loop. The data reproducing circuit further has a variable delay circuit for variably delaying the binary signal to generate a binary delayed signal and also has a delay control circuit for comparing the phase of the binary delayed signal from the variable delay circuit with phases of clock signals generated in the plurality of delay gate stages and for supplying the delay control signal to the variable delay circuit in such a manner that the binary delayed signal has a predetermined phase difference with respect to the sync clock signal.
In the aforementioned aspect of the present invention, the phase of the binary delayed signal to the sync clock signal is optimumly controlled on the basis of a phase relationship between the output clock signals from the delay gate stages present in the voltage controlled oscillator and the binary delayed signal. For example, the delay of the delayed signal from the variable delay circuit is controlled so that the timing of a level change in the delayed signal is away from a rising edge of the sync clock signal. As a result, when the duty of the sync clock signal is shifted from 50% as an increased data transfer rate causes n increased frequency of the sync clock signal, even generation of a jitter in the sync clock signal or binary signal enables a normal signal value to be latched by a latch circuit and thus accurate reproduced data corresponding to the binary signal to be obtained.
Further, the phase discrimination is carried out with use of the multi-phase clock signals within the voltage controlled oscillator. Thus even when a change in the transfer rate of the input signal causes a change in the oscillation frequency of the voltage controlled oscillator, a phase discrimination sensitivity can be kept constant.
Furthermore, because of the delay control of the binary signal, control can be easily realized with a reliability higher than that of the case of performing delay control of the multi-phase clock signals equally.
The delay control circuit has, as an example, a plurality of latch circuits provided to correspond in number to the output clock signals of the delay gate stages in the voltage controlled oscillator for latching the value of the binary delayed signal in synchronism with a change in a first level in the output clock signals, a phase discriminating circuit for generating a advance/delay detection signal indicative of a time relationship of the binary delayed signal with respect the respective outputs of the delay gate stages on the basis of outputs of the plurality of latch circuits, and a signal producing circuit for supplying a delay control signal to the variable delay circuit to change the timing of a level change in the binary delayed signal to such a direction as away from the timing of the first level change of the sync clock signal on the basis of the advance/delay detection signal from the phase discriminating circuit.
With the aforementioned arrangement, the entire latched state of the latch circuits is sequentially determined for each one period of the clock signal outputted from each one of the delay gate stages. The latched state is discriminated for each one period and the delay control signal is sequentially updated on the basis of the discriminated result.
The delay control circuit may, as another example, include a plurality of sets of latch circuits for each of the output clock signals from the delay gate stages in the voltage controlled oscillator. In each set of latch circuits, a plurality of latch circuits are connected in series, their latch clock terminals are commonly connected, so that latching operation is carried out in synchronism with the first level change of the clock signals to supply the binary delayed signal to a latch data input terminal of the first stage. The delay control circuit further has a phase discriminating circuit for generating a advance/delay detection signal indicative of a time relationship of the phase of the binary delayed signal with respect to the phases of the clock signals on the basis of outputs of the latch circuits, and a signal producing circuit for supplying the delay control signal to the variable delay circuit to change the timing of the level change of the binary delayed signal to such a direction as away from the timing of the first level change of the sync clock signal on the basis of the advance/delay detection signal from the phase discriminating circuit.
The phase discriminating circuit is only required to output a detection signal at a rate of once for a plurality of cycles of the output clock signals from the delay gate stages. Or the signal producing circuit is only required to receive a delayed signal from the phase discriminating circuit at a rate of once for a plurality of cycles of the output clock signals from the delay gate stages.
With the aforementioned arrangement, when n stages of latch circuits connected in series are provided for example, the latched state of the entire latch circuits is sequentially determined for each n periods of the output clock signal of one of the delay gate stages in the voltage controlled oscillator. When a signal of, e.g., 3T to 11T is reproduced from a disc, however, pulses of T and 2T may be included into a read binary signal. When such binary signal is subjected to detection of the phase state with the sync clock signal, a phase control error will be large. In order to avoid this, after the latch state of the entire latch circuits is determined for each n periods of the clock signals, its latched data is discriminated and the delay control signal is updated. For example, when a pulse of 1T is mixed, such a state that the binary delayed signal has level changes during consecutive two periods of the sync clock signal, it is designed so that this will not be detected. In short, it is only required to detect by pattern matching or the like whether or not the latched state of the entire latch circuits corresponds to any one of a plurality of states to be detected for each n periods of the clock signal. Such a state as caused by the noise of 1T is previously excluded from the states to be discriminated. For example, when such a shift register arrangement that latch circuits are connected in series is employed to detect a level change point in the binary delayed signal with respect to a unit of latch data corresponding to a plurality of periods of the sync clock signal, such an abnormality as to discriminate two consecutive level change points, e.g., an erroneous level change in the binary delayed signal caused by la damage or the like on the disc, can be discriminated and thus delay control to the variable delay circuit can be realized with use of only reliable signal changes.
As a method for realizing the above phase discrimination and the generation of the delay control signal, two methods which follow may be employed. Both of the two methods are based on averaging or sensitivity lowering, to thereby suppress a state in which, when the phase of the sync clock signal or binary signal is disturbed in a one-shot manner or irregularly, this is reflected directly on the phase control to lead to a difficulty in convergence of the phase control.
In first one of the above methods, the phase discriminating circuit detects outputs of the plurality of latch circuits concurrently to detect whether the timing of a level change in the binary delayed signal is advanced or delayed with respect to the timing of the first level change in the sync clock signal. At this time, the signal producing circuit includes a first operational circuit which updates a count value in a first direction in response to the discriminated result of the phase-advanced state by the phase discriminating circuit and updates the count value in a second direction in response to the discriminated result of phase-delayed state by the phase discriminating circuit. Further included in the signal producing circuit is an arrival detecting circuit which detects whether the count value of the first operational circuit arrived at a first threshold value in the first direction or at a second threshold value in the second direction. And also included in the signal producing circuit is a second operational circuit which updates the value of the delay control signal in a third direction in response to the detection of arrival at the first threshold value thereby and which updates the value of the delay control signal in a fourth direction in response to the detection of arrival at the second threshold value thereby. As a result, the variable delay circuit advances the timing of the level change of the binary delayed signal and locates the timing away from/the first level change of the sync clock signal due to the updating of the value of the delay control signal in the third direction; and delays the timing of the level change of the binary delayed signal and locates the timing away from the timing of the first level change of the sync clock signal due to the updating of the value of the delay control signal in the fourth direction.
With the above arrangement, when it is judged on the basis of the phase discrimination of the sync clock signal and binary delayed signal that the phase state is out of a control target, the count value of the second operational circuit for generating the delay control signal to the variable delay circuit is incremented or decremented. For the purpose of modifying a control sensitivity, the first operational circuit integrates the phase state of the binary delayed signal delayed or advanced with respect to the sync clock signal, and, when its integrated value reached its threshold value, updates the count value (delay control signal) of the second operational circuit, thereby updating a delay to the variable delay circuit. Accordingly a phase relationship between the sync clock signal and binary delayed signal is stably converged into a control target.
In the second method, the phase discriminating circuit detects outputs a plurality of latch circuits concurrently to detect how much the timing of the level change of the binary delayed signal is advanced or delayed with respect to the timing of the first level change of the sync clock signal. At this time, the signal reproducing circuit includes a first operational circuit which updates a count value in the first direction in response to the degree (time length) of advance detected by the phase discriminating circuit and which updates the count value in the second direction in response to the degree (time length) of delay detected by the phase discriminating circuit. Further included in the signal producing circuit is an arrival detecting circuit which detects whether the count value of the first operational circuit arrived at a first threshold value in the first direction or arrived at a second threshold value in the second direction. Also included in the signal producing circuit is a second operational circuit which updates the value of the delay control signal in the third direction in response to detection of the arrival at the first threshold value by the arrival detecting circuit and which updates the values of the delay control signal in the fourth direction in response to detection of the arrival at the second threshold value thereby. As a result, the updating of the value of the delay control signal in the third direction causes the variable delay circuit to advance the timing of the level change of the binary delayed signal to locate the timing away from the timing of the first level change of the sync clock signal; while the updating of the value of the delay control signal in the fourth direction causes the variable delay circuit to delay the timing of the level change of the binary delayed signal to locate the timing away from the timing of the first level change of the sync clock signal.
In this case, since the judgement including the size of an error to the control target is carried out, convergence to the control target is made fast.
With respect to the first operational circuit, its count value is initialized in response to the updating operation of the delay control signal by the second operational circuit. The initialization means to reset the first operational circuit or to preset a prescribed value therein.
When the variable delay circuit is made up of a D/A converter for converting the delay control signal to an analog signal and a delay circuit for variably controlling its delay time by controlling its mutual conductance in response to a signal outputted from the D/A converter, a part of the arrangement of the voltage controlled oscillator may also serve as a part of the variable delay circuit in common.
The above and other objects and novel features of the present invention will become clear as the following description of the invention advances as detailed with reference to preferred embodiments of the invention as shown in accompanying drawings.
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