(a) Field of the Invention
The present invention relates to integrated circuit transistors and manufacturing methods thereof, in particular, to bipolar transistors, integrated injection logic devices (I.sup.2 L), capacitors, polysilicon resistors and isolation regions which separate the above devices and manufacturing methods thereof.
(b) Description of the Related Art
Many semiconductor devices are integrated in a chip in various fields. In order to integrate these devices on a chip, many complicated processes are used, and thus many problems may occur. For example, the resistivity in the polysilicon resistors are not uniform, that is, the distribution of the impurities in the resistors are not uniform. This because there are many ion implantation steps and drive-in steps once doping of the polysilicon resistors are completed. During the successive ion implantation steps and drive-in steps, the impurities in the polysilicon resistors may be are redistributed nonuniformly. In addition, since a separate polysilicon layer is deposited and patterned to form polysilicon electrodes after forming the polysilicon resistors, two polysilicon layers are used for resistors and electrodes respectively. The manufacturing method thus may be complicated. Furthermore, the characteristics of the I.sup.2 L may not be good, and the description thereof is now described with reference to FIG. 1A which illustrates a conventional I.sup.2 L.
An n+ type buried layer 2 is formed on a p type substrate 1, and an n type epitaxial layer 3 is formed thereon. The epitaxial layer 3 has a plurality of diffusion regions such as n type regions 4, 8, 9,10 and 24 and p type regions 5, 31 and 34 which extend downwards from the surface of the epitaxial layer 3. An n+ type sink region 4 is formed on the edges of the buried layer 2. A LOCOS oxide layer 13 is formed on the central region of the portion of the epitaxial layer 3 enclosed by the sink region 4. P type regions 5 and 31 and 34 are formed at both sides of the LOCOS oxide layer 13, respectively. The p type region 34 includes two p- type regions 36 and 37 and a central p+ type region 35 therebetween. The p type region 31 has a p- type region 33 adjacent to the LOCOS oxide layer 13 and a p+ type region 34 adjacent thereto, and the p type region 5 is formed to be separated from the p type region 31. Multiple n+ type regions 8, 9 and 10 are formed in the p- type regions 33, 36 and 37. Another n+ type region 24 is formed in one side of the sink region 4, and a LOCOS layer 14 is formed on the other side of the sink region 4. A LOCOS oxide layer 11 and 12 surrounding the n+ type region 24 is formed on the epitaxial layer 3. An oxide layer 15 is formed on the epitaxial layer 3 and on the LOCOS oxide layers 11, 12, 13 and 14, and it has contact holes on the n+ type regions 8, 9, 10 and 24 and on the p+ type regions 5, 32 and 35. In the contact holes on the n+ type regions 8, 9, 10 and 24, polysilicon electrodes 17, 18, 19 and 16 are formed to be in contact with the n+ type regions 8, 9, 10 and 24, and silicide layers 30 are formed on the respective polysilicon electrodes 17, 18, 19 and 24. An interlayer insulating film 23 is formed thereon and it has contact holes exposing the polysilicon electrodes 17, 18, 19 and 24 and contact holes in the oxide layer 15. Finally, metal electrodes 21, 22 and 25 which are respectively in contact with the p+ type regions 5, 32 and 35, and metal electrodes 20, C1, C2 and C3 which are respectively in contact with the polysilicon electrodes 16, 17, 18 and 19 are formed in the contact holes.
In this conventional I.sup.2 L, a punch through phenomenon occurs among the n+ type region 10, the p- type region and the epitaxial layer 3 in the region as shown by A in FIG. 1A, and this yields leakage current which degrades the characteristics of the device.
Next, a conventional lateral pnp bipolar transistor is described with reference to FIG. 1B.
An n+ buried layer 40 is formed on a p type substrate 1, and an n type epitaxial layer 3 with is formed thereon. A p+ isolation region 44 formed in the epitaxial layer 3 extends downward from the surface of the epitaxial layer 3, and a p+ type region 42 is formed to extend from the p+ isolation region 44 to the substrate 1. The isolation region 44 and the p+ type region 42 surround the buried layer 40, and LOCOS oxide layers 61 and 63 are formed on the isolation region 44. The portion of the epitaxial layer 3 surrounded by the isolation region 44 has a plurality of diffusion regions such as n type regions 46 and 48 and p type regions 51 and 52 which extend downwards from the surface of the epitaxial layer 3. An n+ type sink region 46 is formed to be connected to the edges of the buried layer 40. A p+ type emitter region 52 and a p+ type collector region 51 which surrounds the emitter region 52 and is separated from the emitter region 52 are formed in the epitaxial region 3. An n+ type region 42 is formed in the sink region 4, and it provides currents to the epitaxial layer 3 which serves as a base through the sink region 46 and the buried layer 40. A LOCOS oxide layer 62 is formed on the portion of the epitaxial layer 3 between the sink region 46 and the portion of the collector region 51 adjacent to the sink region 46. An oxide layer 15 is formed on the epitaxial layer 3 and the LOCOS oxide layers 61, 62 and 63, and it has contact holes on the n+ type region 48 and the collector and the emitter regions 51 and 52. In the contact hole on the n+ type region 48, a polysilicon electrode 70 is formed to be in contact with the n+ type regions 48. An interlayer insulating film 23 is formed thereon and the interlayer insulating film 23 has contact holes exposing the polysilicon electrode 70 and contact holes in the oxide layer 15. Finally, an emitter and a collector metal electrodes 81 and 82 which are respectively in contact with the emitter and collector regions 52 and 51 and a base metal electrode 83 which is in contact with the polysilicon electrode 48 is formed in the contact holes.
In this conventional lateral pnp bipolar transistor, since the concentration of the epitaxial layer 3 which function as the base is very low, sufficient distance may be required between the emitter region 52 and the collector region 51 for maintaining the breakdown voltage. However, the large distance between them may cause the current gain to become small.
USPTO Backgrounds
USPTO Backgrounds