1. Field of the Invention
This invention relates to a semiconductor safer therein pad electrodes necessary for a burn-in test of all semiconductor chips on the semiconductor safer are electrically connected to external terminal pad electrodes formed on a peripheral portion of the semiconductor wafer.
2. Description of the Prior Art
In recent years, high integration and miniaturization of semiconductor elements have proceeded dramatically. As a result of this high integration and miniaturization, the film thickness of semiconductor elements and the thickness of metal film wiring lines have become greatly reduced. This gives rise to a serious problem with respect to the reliability of the semiconductor elements and also to the removal of latent defects which appear during initial use in order to resolve these problems, it is a common practice to perform a so-called burn-in test wherein a stress such wherein a voltage is applied to the semiconductor elements under elevated temperature conditions to accelerate the conversion of latent defect into an actual existence.
Such burn-in tests are normally performed in accordance either with a first testing form Viz., a condition wherein a test is performed by inserting a single semiconductor device in a completed condition, wherein semiconductor chips are separated from one another and individually enclosed in a resin material into a socket mounted on a printed circuit board especially designed for use in burn-in tests. Alternatively, the completed chips are subjected to a second testing format wherein tests are performed using a burn-in testing pattern formed on a TAB (Tape Automated Bonding) tape. This latter-mentioned testing is used in order to perform a burn-in test on semiconductor chips mounted on a TCP (Tape Carrier Package).
The first testing technique described above suffers from drawbacks of the nature described below. First as the production of semiconductor devices increases, the cost of burning boards each having a socket mounted on a printed circuit board increases remarkably. Further, a great number of man-hours is required for mounting and dismounting of a semiconductor device on the burn-in board, and in many cases, a new apparatus exclusively for such mounting and dismounting is required Further, when a semiconductor device is mounted or dismounted, deformation of the external terminal leads is invited. This tends to bring about a nonsoldered condition and is a principal cause of onto defects when the semiconductor devices are soldered onto printed circuit boards using a surface mounting solder reflow technique
Additionally, since the separate semiconductor chips on a semiconductor wafer are tested as individual semiconductor devices, the ability to ascertain the existence of burn-in defects which existed when semiconductor chips and the like were still on the semiconductor wafer is greatly reduced. This inhibits the accumulation of data which are useful in improving in semiconductor wafer manufacturing techniques. Consequently, it has been difficult to enhance the yield and the reliability of semiconductor wafers.
The second testing form wherein a burning test is performed for semiconductor chips mounted on a TCP has also suffered from drawbacks of the nature described below. In particular, a TAB tape used in this test has a length of up to about 20 m, and a burn-in apparatus is required to have a sufficient size to allow such long TAB tape to be accommodated therein. Consequently, the burn-in apparatus has a very large size. In order to reduce the size of the burn-in apparatus. it is necessary to out such TAB3 tape for several semiconductor chips. However, if a TAB3 tape is cut in this manner, then automation of the mounting step, which is a characteristic of the TAB technique, cannot be achieved.
Further, when a socket for a TCP is used, since there are many various outer profiles of custom specifications for such TCP, the socket cannot be used commonly, and if expansion of a TAB tape in a heated condition during a burn-in test is taken into consideration, it is very difficult to achieve accurate positioning between terminals of the socket and TAB leads over the length of about 20 m.
In addition, even if a burn-in power source pattern is provided on a TAB tape so as to allow a burn-in test to be performed. Input clocks cannot be supplied for dynamic burn-in wherein specimens of a semiconductor device are operated dynamically. Consequently the burn-in test is limited only to static burn-in. Accordingly, an optimal burn-in cannot be achieved.
USPTO Backgrounds
USPTO Backgrounds