1. Field of the Invention
The present invention relates to a nonvolatile memory with hierarchical row decoding, and more in particular to a control circuit of a variable-voltage regulator forming part of said nonvolatile memory.
2. Description of the Related Art
As is known, nonvolatile memory devices are typically organized as an array, in which word lines connect gate terminals of the memory cells arranged on the same row, and bit lines connect drain terminals of the memory cells arranged on the same column.
The rows of the memory array are addressed by means of a row decoder, which receives at an input a coded address, and has the purpose of biasing the word line of the row each time addressed at a stable and precise voltage, the value of which depends upon the type of operation carried out on the memory cells of that particular row (reading, programming, verifying, erasing).
Furthermore, in certain nonvolatile memories the memory array is organized in global word lines and local word lines. In particular, the memory array comprises global word lines and a plurality of local word lines for each global word line, the local word lines being connected to the corresponding global word line via respective switching stages having the purpose of enabling, when they are on, transfer of the voltage present on the global word line to the respective local word line, and to which the memory cells are then physically connected.
A global row decoder addresses the global word lines, and a local row decoder addresses the local word lines. In particular, the global row decoder is directly connected to the global word lines and each time biases the line or lines selected, whilst the local row decoder controls the switching stages in such a way as to enable selective connection between the local word lines and the respective global word line.
For proper operation, each of the switching stages needs to receive a biasing voltage that is stable, precise and variable according to discrete values within a certain range, in which the lower end of the range is less than the supply voltage.
In particular, the switching stages typically have a CMOS-type structure and are formed by a PMOS transistor and an NMOS transistor having their respective source and drain terminals connected together and to the global word line, their respective drain and source terminals connected together and to the local word line, and gate terminals receiving respective control signals that are complementary to one another.
The NMOS transistor moreover has a bulk terminal which must be biased at a voltage that is equal to ground voltage during the steps of reading and programming of the memory cells, and is equal to a negative erasure voltage, for example xe2x88x928 V, during the erasure step, whilst the PMOS transistor has a bulk terminal which must be biased at a voltage that typically assumes a value of approximately 6 V during the reading step, a voltage of approximately 1.5 V during the erasure step, and presents a staircase waveform with pre-set steps during the programming step, in which the initial and final values of the staircase depend upon the type of memory cells used; for example, for four-level memory cells (i.e., memory cells able to store 2 bits per cell) the programming voltage varies between 1.5 and 9 V with steps of approximately 300 mV.
It is, however, known that nonvolatile memories are typically of the single-supply-voltage type; i.e., they receive from outside a single supply voltage having a value of, for instance, between 2.5 and 3.8 V.
Consequently, the aforesaid voltage variable between 1.5 and 9 V, as in general all voltages that present staircase waveforms, is generated inside the nonvolatile memory in the way illustrated in FIG. 1, namely, by means of a supply stage formed by a voltage-boosting circuit 2 and a voltage regulator 3 cascade-connected.
In particular, the voltage-boosting circuit 2, generally known as xe2x80x9cvoltage boosterxe2x80x9d or xe2x80x9ccharge pumpxe2x80x9d, is fed with the supply voltage VCC supplied from outside to the nonvolatile memory and supplies at output a boosted voltage VHV higher than the supply voltage VCC. Since the boosted voltage VHV is not very voltage-stable, it is then supplied at input to the voltage regulator 3, which supplies at output a regulated voltage VREG, which is voltage-stable and presents the staircase waveform with the values referred to above.
In particular, the voltage regulator 3 typically has a circuit structure of the variable-gain feedback operational amplifier type shown in FIG. 2; i.e., it basically comprises an operational amplifier 4 and a resistive-type feedback network 8.
In detail, the operational amplifier 4 has a supply terminal receiving the boosted voltage VHV generated by the voltage-boosting circuit 2, a non-inverting terminal receiving a reference voltage VREF, an inverting terminal connected to a node 6, and an output terminal supplying the regulated voltage VREG, whilst the feedback network 8 consists of a resistive divider formed by a first feedback resistor 10 of a variable type connected between the output terminal of the operational amplifier 4 and the node 6 and having a resistance RA, and a second feedback resistor 12 connected between the node 6 and the inverting terminal of the operational amplifier 4 and having a resistance RB.
With the circuit structure shown in FIG. 2, the regulated voltage VREG is therefore linked to the reference voltage VREF by the known relation:       V    REG    =            V      REF        ·          (              1        +                              R            A                                R            B                              )      
Given that the second feedback resistor 12 has a constant resistance RB, by varying the resistance RA of the first feedback resistor 10, the regulated voltage VREG is accordingly made to vary as a function of the ratio between the feedback resistances RA and RB.
The first feedback resistor 10 is generally made in the way shown in Figure namely, it is formed by N resistors, designated by 14.1, 14.2, . . . , 14.N, connected in series and identical to one another, and a plurality of switches, designated by 16.1, 16.2, . . . , 16.N, each of which is connected in parallel to a respective resistor 14.1-14.N, and by means of which it is possible to short-circuit each of the resistors 14.1-14.N independently of one another.
The switches 16.1-16.N are typically pass-gate CMOS switches, and each of them receives, on a first control terminal and a second control terminal, respectively a first control signal and a second control signal, which are complementary to one another and are designated, in FIG. 3, by xcfx861, {overscore (xcfx86)}1 for the first switch 16.1, xcfx862, {overscore (xcfx86)}2 for the second switch 16.2, and so forth.
In particular, through the appropriate opening or closing command of the switches 16.1-16.N it is possible to obtain a resistance that varies between a minimum value of zero, when all the switches 16.1-16.N receive a closing command and short-circuit the respective resistors 14.1-14.N, and a maximum value equal to the sum of the resistances of all the resistors 14.1-14.N, when all the switches 16.1-16.N receive an opening command and do not short-circuit the respective resistors.
The smaller the resistance of the switches 16.1-16.N that are closed, the greater the precision obtained on the regulated voltage VREG,.
In fact, if it is assumed that of the N resistors 14.1-14.N that form the first feedback resistor 10, K are not short-circuited, i.e., that is K switches are open and N-K switches are closed, then the ideal regulated voltage VREG, i.e., the voltage that would be obtained if all the switches were ideal and hence did not have a resistance of their own, would be:       V    REG    =            V      REF        ·          (              1        +                              K            ·                          R              S                                            R            B                              )      
where RS is the resistance of each of the resistors 14.1-14.N, whereas the actual regulated voltage VREG, i.e., the voltage that is obtained if the resistance of the switches is taken into account is:       V    REG    =            V      REF        ·          (              1        +                                            K              ·                              R                S                                      +                                          (                                  N                  -                  K                                )                            ·                              R                1                                                          R            B                              )      
where RI is the resistance of each of the switches 14.1-14.N when they are closed.
Consequently, the absolute error E made on the value of the regulated voltage VREG is:   E  =            V      REF        ·                            (                      N            -            K                    )                ·                  R          1                            R        B            
As may be noted, the absolute error E made on the value of the regulated voltage VREG is directly proportional to the resistance of the switches 16.1-16.N and to their number, so that it is evident how the minimization of said absolute error E can be obtained by minimizing the resistance of said switches, i.e., by rendering the NMOS and PMOS transistors forming said switches sufficiently conductive.
FIG. 4 shows the circuit diagram of one of the switches 16.1-16.N, namely the switch 16.1, which is formed by a PMOS transistor 18.1 and an NMOS transistor 20.1 having their respective source and drain terminals connected together and defining a first node A, which is in turn connected to a first terminal of the corresponding resistor 14.1, their respective drain and source terminals connected together and defining a second node B, which is in turn connected to a second terminal of the corresponding resistor 14.1, and gate terminals respectively receiving the control signals xcfx861 and {overscore (xcfx86)}1.
The control signals xcfx861, and {overscore (xcfx86)}1 are generated by a control circuit, designated by 22 in FIG. 4, having a supply input receiving a supply voltage VPG, a signal input receiving control signals S generated by an appropriate control circuit (not shown), and a plurality of pairs of outputs, one for each of the switches 16.1-16.N, which supply the control signals xcfx861, {overscore (xcfx86)}1, . . . , xcfx86N, {overscore (xcfx86)}N for the switches 16.1-16.N.
In order to minimize the resistance of the switch 16.1 when the latter is closed, namely the resistance xe2x80x9cseenxe2x80x9d between the nodes A and B, the amplitudes of the control signals xcfx861 and {overscore (xcfx86)}1 supplied to the gate terminals of the PMOS transistor 18.1 and NMOS transistor 20.1 must be sufficiently high. In fact, if the nodes A and B are at a relatively low potential, the PMOS transistor 18.1 will conduct little current, whereas it will be the NMOS transistor 20.1 that will conduct most of the current, thus causing a short circuit which will be all the more effective the greater the amplitude of the control signal {overscore (xcfx86)}1 supplied to the gate terminal of the NMOS transistor 20.1.
If, instead, the nodes A and B are at a relatively high potential, the NMOS transistor 20.1 will make only a small contribution to conducting current, which will prevalently flow in the PMOS transistor 18.1, and it will be therefore the latter that will bring about an effective short circuit. In this condition of biasing of the nodes A and B, moreover, turning-off of the PMOS transistor 18.1 may be obtained effectively simply by supplying, to its gate terminal, a control signal xcfx861 having a high amplitude, namely, a control signal at least equal to the voltage of the node A.
In order to bias the gate terminals of the PMOS and NMOS transistors of the switches 16.1-16.N in such a way as to guarantee good conductivity of the latter, its has been proposed in the past to supply, to the control circuit 22, as supply voltage VPG, the boosted voltage VHV generated by the voltage-boosting circuit 2. In this way, in fact, since the boosted voltage VHV is higher than the regulated voltage VREG generated by the voltage regulator 3, the control signals supplied to the switches 16.1-16.N have amplitudes that are as high as possible.
Since, however, the boosted voltage VHV is characterized by a very marked pulse waveform, by means of the capacitive coupling constituted by the gate-source and gate-drain capacitances of the PMOS transistors 18 and NMOS transistors 20 of the switches 16.1-16.N, the said pulse waveform is brought onto the output of the voltage regulator 3 and constitutes an undesirable disturbance present on the regulated voltage VREG generated by the voltage regulator 3.
Consequently, the above solution is satisfactory as regards the conductivity of the PMOS transistors 18 and NMOS transistors 20, but is unsatisfactory as regards noise rejection.
To overcome the aforesaid problem, an alternative solution has been proposed, which consists in supplying to the control circuit 22, as its supply voltage VPG, the regulated voltage VREG supplied by the voltage regulator 3. This solution is satisfactory both from the standpoint of the conductivity of the PMOS transistors 18 and NMOS transistors 20 and from the standpoint of noise rejection as long as the regulated voltage VREG supplied by the voltage regulator 3 is sufficiently high, whereas it loses efficacy at the moment when the voltage regulator 3 is required to supply a relatively low regulated voltage VREG, i.e., even lower than the supply voltage VCC supplied from outside to the nonvolatile memory.
In this condition, in fact, the PMOS transistors 18 and NMOS transistors 20 of the switches 16.1-16.N, which are intended to behave as short circuits, would in effect be equivalent to resistors the resistances of which are a function of the regulated voltage VREG supplied by the voltage regulator 3, and would thus directly contribute to determining the resistance of the first feedback resistor 10, and hence the value of the regulated voltage VREG itself, with an evident loss of precision, or in the extreme case, of the control of the desired value of the regulated voltage VREG.
An Embodiment of the present invention obtains a nonvolatile memory provided with a voltage regulator controlled by a control circuit which enables the drawbacks of the control circuits described above to be, at least partially, overcome.
According to an embodiment of the present invention, a nonvolatile memory is provided, comprising a memory array organized according to global word lines and local word lines. The memory includes a global row decoder, a local row decoder, a first supply stage for supplying the global row decoder; a second supply stage for supplying the local row decoder, and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array.
Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.
A method of operation is also provided, according to an embodiment of the invention.
USPTO Backgrounds
USPTO Backgrounds