The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device including a two-stage input buffer for stably ensuring a setup time margin and a hold time margin under pressure, voltage and temperature (PVT) variation.
A semiconductor device is fabricated using a variety of semiconductor technology including a silicon wafer processing technology and a logic design technology. In the semiconductor fabricating process, a final product is a plastic package type chip. The plastic package type chip has different logics and functions according to its use. Most of the semiconductor chips are mounted on a printed circuit board (PCB) that is an important component in a system configuration. Appropriate driving voltages are applied to the chips. Semiconductor devices including a semiconductor memory device operate according to the input/output of particular signals. That is, an operation and an operation method of the semiconductor device are determined by combination of input signals, and the semiconductor device outputs different signals according to the combination of the input signals. Further, an output signal of the semiconductor device can be used as an input signal of another semiconductor device within the same system.
An input buffer buffers an external signal and inputs the buffered signal to an internal circuit of the semiconductor device. A simple input buffer is a static input buffer. The static input buffer is an inverter configured with a PMOS transistor and an NMOS transistor serially connected between a power supply terminal and a ground terminal. The static input buffer has a simple structure but is weak against noise. Therefore, a swing width between a logic high level and a logic low level must be large. Consequently, the static input buffer is inappropriate to devices in which an input signal has a large swing width or which requires a high operating frequency.
In order to meet such a demand, a differential amplifier type input buffer has been proposed. The differential amplifier type input buffer is also called a dynamic input buffer.
FIG. 1 is a block diagram of a conventional semiconductor memory device including a two-stage input buffer.
Referring to FIG. 1, the conventional semiconductor memory device includes a pre-amplifying unit 10 and a main amplifying unit 20. The pre-amplifying unit 10 detects a voltage difference between an input signal IN and a reference voltage VREF to output positive and negative pre-output signals OUT_PRE and OUT_PREB. The main amplifying unit 20 receives the positive and negative pre-output signals OUT_PRE and OUT_PREB as differential inputs to output an output signal OUT. The positive and negative pre-output signals OUT_PRE and OUT_PREB have opposite phases to each other.
FIG. 2 is a waveform diagram of the signals in the semiconductor memory device illustrated in FIG. 1.
Referring to FIG. 2, when the input signal IN has a voltage level higher than that of the reference voltage VREF, the pre-amplifying unit 10 outputs the positive pre-output signal OUT_PRE of a logic high level and the negative pre-output signal OUT_PREB of a logic low level. The main amplifying unit 20 outputs the output signal OUT of a logic low level in response to the positive and negative pre-output signals OUT_PRE and OUT_PREB.
If a pulse signal of a logic low level is applied as the input signal IN, the input signal IN has a voltage level lower than that of the reference voltage VREF. At this time, the pre-amplifying unit 10 outputs the positive pre-output signal OUT_PRE of a logic low level and the negative pre-output signal OUT_PREB of a logic high level. The main amplifying unit 20 outputs a pulse signal of a logic high level as the output signal OUT.
As described above, the conventional semiconductor memory device allows the output signal OUT to swing fully between 0 V and a power supply voltage VDD by performing two-stage amplification process through the pre-amplifying unit 10 and the main amplifying unit 20.
In the conventional semiconductor memory device, when the reference voltage VREF varies with external environments, activation timing and activation duration of the output signal OUT are influenced.
FIG. 3 is a waveform diagram of the signals in the semiconductor memory device illustrated in FIG. 1 when a voltage level of the reference voltage VREF decreases.
As shown, when a voltage level of the reference voltage VREF decreases, the pre-amplifying unit 10 cannot detect, in time, a pulse signal of a logic low level being applied as the input signal IN. Thus, the activation timings of the positive and negative pre-output signals OUT_PRE and OUT_PREB are delayed and their activation durations are shortened. Consequently, the activation timing of the output signal OUT from the main amplifying unit 20 is delayed and its activation duration is shortened.
In this case, setup/hold time requirements are not met in a block (not shown) receiving the delayed output signal. Hence, the signals are not correctly recognized.
Although not illustrated, when a voltage level of the reference voltage VREF increases, the output signal OUT is activated earlier and its activation duration is lengthened. In this case, a block receiving the output signal may not recognize the signals due to the reduction of the setup time margin.
Moreover, since the positive and negative pre-output signals OUT_PRE and OUT_PREB have opposite phases to each other and are influenced by variation of the reference voltage VREF, the main amplifying unit 20 receiving the positive and negative pre-output signals OUT_PRE and OUT_PREB is further influenced by the variation of the reference voltage VREF.
Therefore, the conventional semiconductor memory device generates signals that do not meet the setup/hold time requirements when the voltage level of the reference voltage VREF varies with PVT variation, thus causing malfunction of the semiconductor memory device.
USPTO Backgrounds
USPTO Backgrounds