Microchip fabrication processes are largely a matter of surfaces. Processing techniques are concerned with modifying properties less than a few microns below or above the surface of a substrate material. Present complex electronic integrated circuits are formed by using planar processes in which an ultra-clean, flat wafer of silicon is used as a substrate upon which a large number of identical devices are built by various oxidation, photolithography, removal, ion bombardment, deposition and other processes.
It is well known that device performance, reliability and product yield of silicon circuits are critically affected by the presence of chemical contaminants and particulate impurities on the wafer surface of the device. An ultra-clean surface preparation before and after the processes used for the patterning of microelectronics devices is now more important than ever before, as the surface diameter extends toward 300 mm and the structure dimensions shrink below sub-microns.
Existing methods for ultra-clean surface preparation can be divided into two main categories: wet processes such as immersion and spray techniques, and dry processes such as chemical vapor and plasma based techniques. Wet processing typically consists of a series of steps of immersing or spraying the wafers with appropriate chemical solutions. The wet processes for ultra-clean wafer surface preparation have been successfully used for the past thirty years and are still the predominant methods used in present integrated circuits manufacturing. However, the complexity of 90- and 65-nm semiconductor processes, that call for new materials and structures, such as copper interconnects, low-k dielectrics, high-k capacitors and more metal levels, has demanded creating new ways of measuring and removing contamination and other fatal defects, as well as the design of process steps that are not defect-sensitive. In addition, the economic realities of modern semiconductor manufacturing that dictate that devices must yield in the mid- to high- 90% range reflect the volatility and cyclical nature of the semiconductor business. As such, advanced process control and in situ process monitoring will be much more important than the traditional approach of longer-loop feedback based on final test and inspection data. There is a need to have a reliable in-line monitoring system to ensure critical equipment performance and process quality.
Thus, there is a need for the ability to clean and process semiconductor wafers efficiently in terms of materials, time, and labor required, as well as the ability to analyze and monitor the cleaning and/or processing of semiconductor wafers accurately and on a real-time basis. The present invention seeks to address these needs.
USPTO Backgrounds
USPTO Backgrounds