The present invention relates to a method of forming patterns of a semiconductor device and, more particularly, to a method of forming micro patterns of a semiconductor device which have a pitch lower than resolutions of an exposure apparatus.
A minimum pitch of patterns of semiconductor devices, which are formed in a photolithography process, is determined according to a wavelength of exposure light used in an exposure apparatus. To form patterns having a smaller pitch in highly integrated semiconductor devices, light having a short wavelength is used. Processes employing X-ray or E-beam may be used for forming semiconductor devices having a small pitch, but these procedures remain in the experimental stage. A Double Exposure and Etch Technology (DEET) has been proposed to address the limitations of X-ray and E-beam procedures.
FIGS. 1A to 1C are sectional views illustrating the DEET process. Referring to FIG. 1A, a first photoresist PR1 is coated over a semiconductor substrate 10 including a to-be-etched layer 11. The first photoresist PR1 is patterned using exposure and development processes. The to-be-etched layer 11 is etched using the patterned first photoresist PR1 as a mask. A line width and a space width of the etched to-be-etched layer 11 are 150 nm and 50 nm, respectively.
The first photoresist PR1 is removed. A second photoresist PR2 is coated on the entire surface. The second photoresist PR2 is patterned using exposure and development processes so that a part of the to-be-etched layer 11 is exposed, as shown in FIG. 1B.
Referring to FIG. 1C, the to-be-etched layer 11 is etched again using the patterned second photoresist PR2 as a mask, thereby forming final patterns having a line and space width of 50 nm. The second photoresist PR2 is then removed.
During the exposure process of the second photoresist PR2, overlay accuracy is directly concerned with the Critical Dimension (CD) variation of the final patterns. The overlay accuracy of an exposure apparatus is difficult to control within 10 nm, which makes it difficult to decrease the CD variation of the final patterns. There is another difficulty in controlling the Optical Proximity Correction (OPC) due to circuit isolation according to dual exposure.
USPTO Backgrounds
USPTO Backgrounds