1. Field of the Invention
This invention relates to integrated-circuit (IC) chips carrying thin film resistors. More particularly, this invention relates to improved techniques for developing thin film resistors on IC chips, and to IC chips made by such improved techniques.
2. Description of the Prior Art
IC chips have been manufactured for many years by various processes. Resistors for the circuits can be formed by diffusions into the substrate, but for many applications the resistors must be formed from thin film material, such as Silicon Chromium (Si Cr), deposited on the substrate. The present invention concerns only thin film resistors.
Interconnect material, usually Aluminum or one of its alloys, is applied by photolithographic procedures to make connections to all circuit elements including thin film resistors. A barrier layer such as Titanium-Tungsten (TiW) may be placed between the thin film material and the Aluminum. The configurations of all of these materials are controllable by conventional photolithographic processes employing photoresist and etching to remove selected portions of a deposited layer.
In one early process, thin film material is deposited over the entire substrate. (Note normally the substrate is a circular wafer, to be subdivided after processing into separate chips.) The optional barrier layer, if used, is laid down over the layer of thin film material. Photolithography then is employed to etch away all portions of the thin film and barrier layer except selected regions where resistors are to be developed. In those regions, the thin film material (and the optional barrier layer) remaining after the etching serves as the resistors for the circuit on the chip.
The entire substrate then is covered with Aluminum, which thereafter is etched away selectively to establish the interconnect pattern. This pattern includes portions which make contact with the various transistor elements, and other components, and also includes portions making contact with the ends of the thin film resistors developed on the substrate described above.
In an alternative procedure, the substrate receives, in sequence, covering layers of thin film material, barrier layer (if required) and interconnect material (e.g. Aluminum). Next, the interconnect pattern is established by the usual photoresist masking and etching. The barrier layer (if used) then is etched away in the areas where the interconnect had previously been etched away (the barrier material however still remaining under the non-etched interconnect). Thus the thin film material is exposed in the etched areas (i.e. all areas except where the interconnect is established). Photoresist then is used to mask out the thin film material where resistors are to be formed, and all the other (non-masked) thin film material is etched away, leaving only thin film to serve as resistors.
In both of the above-described techniques, chemical etchant solutions (i.e. so-called "wet-etching") were employed for removal of the interconnect material (Aluminum) in those regions identified by the photolithographic masking. This produces "isotropic" etching, where the etching action takes place equally in all directions. Such etching results in undercuts of the material being etched. Wet-etching is satisfactory for processes using relatively wide conductors, such as 5 microns or larger. However, for smaller-width conductors, and wherein close spacing is required between conductors, it is necessary for the etching to be substantially "anisotropic". Such etching avoids undercutting of the layer being etched, and permits close spacing of the conductors.
Plasma etching (or so-called "dry etching") has been introduced to perform anisotropic etching for Aluminum and its alloys. Plasma etching however also attacks barrier and thin film materials, and cannot be used with the prior processes as described above without injuring the thin film material to be used as resistors.
Accordingly, there has developed a strong need for new processing techniques which can make use of plasma or dry-etching, to permit use of narrow interconnect conductors, to allow closer spacing of such interconnect conductors, and which yet is compatible with the development of resistors formed from deposited thin film material.
USPTO Backgrounds
USPTO Backgrounds