As processing and packaging technologies continue to advance to support smaller geometries and higher speed input/output (I/O) signal applications, simultaneous switching output (SSO) noise is becoming a significant issue for electronic devices such as programmable logic devices (PLDs) designs. While various techniques may be used by a PLD manufacturer to reduce SSO noise, such as by employing a more expensive package (e.g., a flip chip package), SSO noise is generally still perceived as a PLD design issue, with the PLD design engineer typically tasked with dealing with SSO noise design problems.
Conventional approaches generally fail to provide adequate design tools that address SSO noise (also referred to as ground bounce voltage) for a given PLD design. For example, a conventional approach may fail to adequately predict or estimate the SSO noise and/or adequately address SSO noise during the PLD design process (e.g., for design optimization, map, place, and route). Consequently, the PLD design engineer may employ a SSO design check tool (e.g., provided by a vendor), after the I/O signal assignments (e.g., after the design fitting process), to determine if SSO noise may be an issue for the PLD design. However, this conventional approach typically results in a tedious and time-consuming trial-and-error process.
As a result, there is a need for improved techniques directed to simultaneous switching output noise, such as for the PLD design process.
USPTO Backgrounds
USPTO Backgrounds