Those techniques as will be explained in brief below have been taken into consideration by the inventors as named herein during studying for reduction to practice of the present invention as disclosed and claimed herein.
The quest for further miniaturization or “downsizing” of modern electronic equipment results in shrinkage of dimension and weight reduction and tends to grow rapidly in the markets of electronics and semiconductor industries. Under such circumstances, it is becoming more important in the manufacture of small size electronic equipment to further improve the large-scale integrated circuit (LSI) chip mount architectures—that is, to develop an improved LSI chip packaging technique with ultra-high integration densities.
In addition, as the markets of electronics grow, improvements in productivity have been more strictly required while simultaneously reducing manufacturing costs.
A first prior known approach to satisfying the above technological requirements is to employ a resin sealed or hermetic surface-mount semiconductor device structure as disclosed in, for example, Published Unexamined Japanese Patent Application (“PUJPA”) No. 5-129473. The prior art device as taught thereby is such that as shown in FIG. 29, this device employs a lead frame 35 with a pattern of electrical leads 33 and a chip support paddle or die pad 34, also known as a “tab” among those skilled in the art, being located on the same surface, wherein the prior art is featured in that the leads 33 are electrically connected at lower surfaces to a semiconductor chip 36 via bonding wires 37, wherein the lower surfaces are for use as external electrodes each functioning as an electrical connector portion with external circuitry operatively associated with the semiconductor device.
Unfortunately the first prior art shown in FIG. 29 is associated with a problem which follows. As this is structurally designed so that the tab 34's parts-mount surface side is exposed from the lower surface of the semiconductor device, the tab 34 will possibly come into direct contact with leads on the parts mount substrate when mounting the semiconductor device on the mount substrate, which in turn makes it impossible to form any leads at corresponding portions of the mount substrate, resulting in a noticeable decrease in the degree of freedom of substrate design schemes. Another problem is that since the device is structurally arranged so that the tab 34 is sealed only at its one surface, the resulting contact area between the tab 34 and a sealing material 38 used decreases causing the tight contact or adhesiveness to degrade accordingly, which would result in a decrease in reliability of the semiconductor device.
A second prior art resin sealed semiconductor device is found in PUJPA No. 10-189830 (JP-A-10189830). This device is shown in FIG. 30, which includes a semiconductor element 42 as mounted on a tab 41 that in turn is supported by a hanging or “suspending” lead 40 of a lead frame 39, metal fine leads 45 for electrical interconnection between electrodes 43 on the upper surface of said semiconductor element 42 and associative inner leads 44, a sealing resin material 46 for use in sealing an outer surrounding region of the semiconductor element 42 containing metal fine lead regions over the upper surface of semiconductor element 42, and external connect terminals 47 that are laid out in a bottom surface region of said sealing resin 46 for connection with said inner leads 44, wherein said suspension lead 40 has been subjected to the so-called “up-set” processing thus having step-like differences 48, called “stepped portions,” and wherein the sealing resin 46 is also formed at part underlying said tab 41 to a thickness corresponding to the amount of said upset processing.
The second prior art shown herein is such that since the suspension lead 40 of the lead frame 39 has been subject to the up-set processing to have the stepped portions 48, it becomes possible to permit the sealing resin 46 to be present at the part underlying the tab 41, which in turn makes it possible to provide substantially the double-face sealed semiconductor device structure with respect to the lead frame 39, thereby offering increased reliability when compared to said first prior art discussed above.
Another advantage of the prior art is that in view of the fact that this is structurally designed to prevent exposure of the tab 41's parts-mount substrate side from the lower surface of the semiconductor device, the tab 41 will no longer come into contact with those leads on the mount substrate, thereby increasing the degree of freedom in parts mount design schemes.
Other examples of the semiconductor device with its tab subjected to the up-set processing (tab finishing treatment) are known among those skilled in the art, one of which is disclosed in JP-A-11-74440.
Regrettably said first prior art is faced with a problem in that a decrease in seal material-to-tab contact area can be lower the resultant adhesiveness thus reducing the reliability of the semiconductor device because of the fact that this device is structured so that the tab is sealed solely at its one surface in order to improve the thickness reducibility.
Additionally, although said second prior art and the one as taught by the above-identified Japanese document JP-A-11-74440 are drawn to the double-face resin-sealed semiconductor device with respect to the lead frame used therein, which offers an advantage as to an increase in reliability when compared to said first prior art, stepped portions included are to be formed through the up-set processing whereby each of them suffers from a problem in that it is impossible to improve the thickness reducibility to the extent that is equivalent to the first art and also a “tab dislocation” problem including displacement or strain of the tab occurring during execution of such up-set Processing.
In short, it has been affirmed by the inventors that even the first and second prior art devices stated supra have met with limited success as to the capability of solving the conflicting or “trade-off” problems—i.e. the thickness reducibility and increased reliability required.
It is therefore a primary objective of the present invention to provide a new and improved semiconductor device capable of achieving both the thickness reducibility and high reliability at a time and also methodology of manufacturing the semiconductor device along with a parts mount structure of the same.
Another object of this invention is to provide an improved semiconductor device capable of increasing productivities while reducing production costs and a method of manufacturing the device as well as a parts mount structure of same.
A further object of the invention is to provide a semiconductor device capable of-preventing any accidental electrical short circuiting and unwanted lead dropdown detachment otherwise occurring during parts mounting processes and a method of manufacturing the device as well as a parts mount structure of same.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds