1. Field of the Invention
The present invention is in the field of digital logic circuits.
2. Description of the Related Art
Generally, digital computer systems operate on a synchronous basis. That is, the logic circuits within the computer system are clocked logic circuits that are responsive to a common clock signal so that output signals generated by a first logic circuit within the computer system change at predictable times with respect to the common clock signal. Thus, a second logic circuit receiving an output signal from the first logic circuit can gate the output signal at a particular time with respect to the common clock signal when it can be assured that the output signal is stable (e.g., has reached one of two binary states, for example, and has been at that state for a sufficient amount of time that the second logic circuit will detect the correct logic level).
Clocked logic circuits are particularly advantageous for testing purposes. Since the signals into and out of a clocked logic circuit change with respect to a clock signal, the circuit can be tested by applying input signals to it with varying times with respect to the clock signal to determine the setup and hold requirements for the input signals, i.e., how long an input signal has to be stable prior to a change in the clock signal (setup time), and how long an input signal has to remain stable after a clock signal (hold time). In addition, propagation delay through the clocked logic signal can be determined by measuring when an output signal changes with respect to the clock signal that caused the change. These parameters and other parameters can be measured under various operating conditions (e.g., voltage levels, temperatures, etc.) to characterize the clocked logic circuits so that a designer will have knowledge of the parameters when designing systems utilizing the clocked logic circuits. Further, during production, the clocked logic circuits can be readily tested to determine whether the circuits operate in accordance with the known characteristics, or whether the circuits are defective.
There are many advantages to clocked logic circuits that operate in synchronism with a clock; however, there are a number of circumstances where a clocked logic circuit cannot be used and logic circuits must be utilized which operate asynchronously with respect to each other. An input signal to an asynchronous circuit may change at unpredictable times with respect to other logic functions within the asynchronous circuit. For example, a clocked logic component in a computer system may initiate an asynchronous command to an asynchronous circuit and then wait for the asynchronous circuit to respond to the command. The asynchronous circuit may respond with an output signal that is asynchronous to the command from the clocked logic component. Such asynchronous communications are necessary for many applications and serve a number of useful purposes; however, because of the asynchronous nature of the asynchronous circuit, it is difficult to test the asynchronous circuit and characterize its operating parameters since there is no common system clock to which the input signals and output signals can be compared. This is particularly true if the asynchronous circuit is incorporated into a large scale integrated circuit (LSI) such as an application specific integrated circuit (ASIC) which are presently used in a substantial number of new computer systems. Although it is possible to test such asynchronous circuits using specially devised testers or manual techniques, the thorough testing of asynchronous circuits using conventional parametric testing systems has not been readily available. Thus, a need exists for a logic circuit that provides the benefits of an asynchronous circuit (e.g., the ability to operate without a common clock) and that also provides the testability characteristics of a clocked logic circuit.
USPTO Backgrounds
USPTO Backgrounds