1. Field of the Disclosure
This disclosure relates to a sensor and a method of efficiently reducing power consumption associated with analog to digital converters of an image sensor.
2. Description of the Related Art
Low power consumption is a primary concern in many CMOS image sensor applications. As the resolution of these sensors has increased while maintaining or increasing their frame rate, the analog to digital conversion (A/D) associated with the sensors has become a dominant component of power consumption. Typical image compression techniques reduce the readout rate (and hence the I/O power consumption), but cannot reduce the power consumption associated with the A/D conversions.
A naïve solution to reduce the power consumption is to skip a readout, wherein the number of pixels accessed for composing an output image is reduced so that the bandwidth of the A/D conversion decreases. In doing so a high frame rate of imaging (or reduction of power consumption) per frame is obtained, but the detailed information of the image is lost as the spatial sampling frequency (Nyquist frequency) degrades.
Another technique is to implement an on-chip image compression using a well known transform basis such as a discrete cosine transform or a wavelet transform. This approach compresses the output bandwidth and keeps the features of the image object, but it cannot reduce the bandwidth of the A/D conversion. Hence the frame rate is limited by the A/D conversion and the impact of power reduction is also insufficient.
Accordingly there is a requirement to lower the power consumption of the A/D converters in order to utilize the device in an efficient manner.
USPTO Backgrounds
USPTO Backgrounds