In semiconductor memories, such as NAND-type flash memories, capacitors are used in various types of peripheral circuits such as charge pump circuits, sense amplifiers and the like. These capacitors are formed as MOS capacitors or well capacitors above a semiconductor substrate by the same process as that of transistors used in other circuits.
A conventional NAND device comprises a memory array having rows and columns of memory cells. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge and is separated from source and drain regions within a substrate by a dielectric material. Each of the memory cells can be electrically programmed (or charged) by injecting electrons from the drain region through an oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the dielectric material during an erase operation. Thus, the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. In order to continue to reduce the decreased reliability becomes increasingly problematic as the thickness of the dielectric material is further scaled down to facilitate increased device density. Decreasing the thickness of the dielectric material used in “high-stress” circuits may result in dielectric breakdown.
Conventional NAND memory devices have an operating voltage (Vcc) in the range of from about 20 volts to about 29 volts. A high voltage, otherwise referred to as a “programming voltage,” of about 8 volts or greater is conventionally required for programming and erase operations in NAND memory devices. For example, if the thickness of the dielectric material for a NAND device is 55 nm, a capacitor having an area of 10 mm2 may sustain a voltage of about 2.2 volts without reliability concerns. The smaller the over-all device area, the higher sustainable stress voltage is allowed for the device.
For example, a charge pump, which may be used to generate the programming voltage pulses, conventionally includes a plurality of series-connected pump stages that are driven by two non-overlapping clock signals. The series-connected pump stages multiply the amplitude of the clock signals. The actual voltage obtained at the charge pump output terminal depends on the number of pump stages and on the charge transfer efficiency of the pump stages. In addition to providing a programming voltage pulse to the memory cells, the charge pump may also be used to support decoding. Therefore, the charge pump is subjected to varying load conditions that may affect the ramp-up rate of the programming voltage pulse. Under heavy loading, the ramp-up rate may be relatively slow. If the load is suddenly reduced, the ramp-up rate may increase dramatically, overstressing the dielectric material of the floating-gate transistor.
On the other hand, the thinner the dielectric material, the lower the stress it can sustain for a given surface area. In a NAND device, many different kinds of charge pump circuits are required to provide different internally generated voltage levels. These pump circuits usually are equipped with several different sized charge pump circuit capacitors made by planar capacitors having a fixed size. When the number of the pump circuits is increased, and the size of the charge pump circuit capacitors used in the charge pump circuits decreases, the reliability of the capacitor dielectric becomes a concern, especially for those capacitors operated at high voltage levels.
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