1. Field of the Invention
The present invention relates to a power-on reset circuit in a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a conventional typical power-on reset circuit. When power is turned on in the power-on reset circuit of FIG. 1 and a potential VDD of a power supply terminal 94 rises, a potential V1 of a node N1 rises more slowly than the potential VDD, through the use of an integration circuit which includes a resistor 91 and a capacitor 92. At this time, the potential VDD is also supplied to a PMOS transistor in an inverter 93, and so a threshold voltage VT (e.g., VDD/2) of the inverter 93 increases in proportion to the potential VDD. Immediately after the power is turned on, when the potential V1 of the node N1 is lower than the threshold voltage VT of the inverter 93, an output of the inverter 93 is high (H) level, and a potential V2 of a node N2 nearly equals the potential VDD. Then, when the potential V1 of the node N1 exceeds the threshold voltage VT, the inverter 93 changes to low (L) level, the potential V2 of the node N2 drops and approaches a GND potential, and thus a reset signal RESET is outputted.
However, the conventional power-on reset circuit has problems as follows: when the potential VDD of the power supply terminal 94 rises slowly immediately after the power is turned on in the circuit, the potential V1 of the node N1 which rises more slowly than the potential VDD cannot reach the threshold voltage VT of the inverter 93 which increases in proportion to the potential VDD, and thus the reset signal RESET may not be outputted to the node N2 which is an output of the inverter 93. Moreover, after the potential VDD of the power supply terminal 94 normally rises, when the potential VDD drops for an instant and then immediately recovers, i.e., a momentary power outage occurs, the potential V1 of the node N1 approximately remains the potential before the momentary power outage, and thus the reset signal RESET is not outputted to the node N2.
There is a proposal of a power-on reset circuit capable of generating a reset signal stably at a rising of a power supply potential and preventing the problems described above, for example, in Patent Document 1: Japanese Patent Kokai Publication No. 5-183416 (FIG. 1, FIG. 2, and paragraphs 0009 to 0014, for example). In the power-on reset circuit proposed in Patent Document 1, when the power supply potential (reference numeral 11 in FIG. 1) starts to rise and a current starts to flow through a bias circuit (a PMOS 12 and an NMOS 13 in FIG. 1), a current flows to an NMOS (reference numeral 15 in FIG. 1) through a resistor (reference numeral 14 in FIG. 1). When a potential of a connection node of these elements (reference symbol f in FIG. 1) incerases, the current which flows through the NMOS (reference numeral 15 in FIG. 1) increases, the potential of the connection node (reference symbol f in FIG. 1) accordingly drops to a GND potential, and the reset signal is outputted from an output terminal of an SR flip-flop circuit (reference numeral 21 in FIG. 1).
However, the circuit of Patent Document 1 requires the resistor of an extremely large resistance value (several megaohms to tens of megaohms, for example) for reducing consumption power, and so the resistor has a large area on a semiconductor integrated circuit. Consequently, it is difficult to reduce a size of the circuit.
Moreover, the circuit of Patent Document 1 requires a structure that an output potential of the bias circuit depends on the power supply potential, and so the bias circuit cannot be independently used. Consequently, it is not easy to control a current for reducing consumption power.
USPTO Backgrounds
USPTO Backgrounds