The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body having a surface adjoined by a semiconductor region and a field oxide region surrounding said region, this surface being provided with a metal layer, in which a conductor track is formed, after which an isolating layer of silicon oxide is deposited over the semiconductor track on the surface.
The conductor track can be provided so that it extends both above the semiconductor region and above the field oxide region and contacts the semiconductor region. The conductor track then contacts, for example, a source or drain zone of a field effect transistor, which is provided in the semiconductor region. The conductor track can then be further connected through a contact window in the isolating layer of silicon oxide deposited over the conductor track to a metallization layer, which is provided on the isolating layer of silicon oxide. The conductor track may also be further connected to a conductor track of polycrystalline silicon, which may also be provided on the surface of the semiconductor body. Both conductor tracks may then be covered by the isolating body. Both conductor tracks may then be covered by the isolating layer of silicon oxide. Thus, for example, a source or drain zone of a field effect transistor provided in the semiconductor region may be connected to a gate electrode of another field effect transistor to be provided in the semiconductor body. The conductor track may also be arranged, however, so that it extends only above the field oxide or only above the semiconductor region. Also in these cases, it may be used to establish different interconnections.
European Patent Application No. 190 070 discloses a method of the kind mentioned in the opening paragraph, in which the conductor track is formed in a layer of titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum or tungsten. The isolating layer of silicon oxide may be deposited over the conductor track on the surface of the semiconductor body by means of one of the methods known for depositing silicon oxide.
In practice, it has been found that with the use of the known method problems may arise. For example, the conductor track covered by silicon oxide may have an electrical resistance which is much larger than that which could be expected of such a metal track on account of its properties. In certain cases, it has also been found that the conductor track is then entirely interrupted. These problems especially arise if the layer of silicon oxide is deposited by means of a deposition process by which a good step coverage can be obtained. During the manufacture of semiconductor devices with current elements, such as field effect transistors having submicron dimensions, such a deposition process is very necessary, however.
USPTO Backgrounds
USPTO Backgrounds