The present invention relates to integrated circuit dynamic memories, and more specifically to methods of tracking errors in a memory system having detection and correction of errors in a memory.
Systems containing digital electronic components are designed to function correctly over a variety of system parameters and conditions, such as voltage, temperature, etc. System parameters such as bias voltages are typically adjusted by open loop control methods through the use of sensors, such as temperature sensing diodes, and voltage sensors. Similarly, sensors have been used to monitor conditions which initiate a sleep-mode or idle-mode operation. These methods prevent incorrect operation of or damage to many components, particularly memory devices. Many means have been developed to correct xe2x80x9chardxe2x80x9d component failures and/or xe2x80x9csoftxe2x80x9d noise induced loss of data.
Various methods have been developed to detect and correct errors in memory. In a Dynamic Random Access Memory (DRAM) redundant columns and rows are added to avoid the use of memory cells exhibiting poor performance. An Error Detection And Correction unit (EDAC) is used to detect errors in stored data, and if possible, correct errors in the data. EDACs greatly improve data integrity. The operation of one type of EDAC is based on a code word. Data to be stored in the memory is provided to the EDAC. The EDAC then generates check bits based on the data value. The check bits are then combined with the data to form a code word. The code word is then stored in the memory. To check the data, the EDAC reads the code word from the memory and recalculates the check bits based on the data portion of the code word. The recalculated check bits are then compared to the check bits in the code word. If there is a match, the data is correct. If there is a difference and the error is correctable, the EDAC provides the correct data and check bits as an output. If there is a difference and the error is uncorrectable, the EDAC reports the occurrence of a catastrophic failure.
A variety of EDAC techniques and circuits are available, as are a variety of methods for generating code words and performing bit checks. Some methods are discussed in U.S. Pat. No. 5,598,422, by Longwell, et al., entitled xe2x80x9cDigital computer having an error correction code (ECC) system with comparator integrated into re-encoder,xe2x80x9d and in Error-Correction Codes, by W. W. Peterson, 2d edition, MIT Press (1972). The information from the EDAC unit is typically used as it is generated. Information such as the address of data that has been corrupted, or the location of failed bits in data are not retained after an EDAC has returned correct data.
A need exists to obtain information over time regarding the errors experienced in the memory. There is a need to retain error address and error frequency information to improve hardware reliability and/or data integrity. There is further a need to analyze error information to determine a connection between such failures and parameters of the system.
USPTO Backgrounds
USPTO Backgrounds