This invention relates to an oscillator circuit and, more particularly, to a system for electrically establishing and maintaining the output frequency of an oscillator circuit at a prescribed value.
It is known that low-power-dissipation operation of a conventional complementary metal-oxide-semiconductor (CMOS) circuit fabricated in integrated-circuit form can be achieved if the power supply lead of the circuit is ramped repetitively between VDD and VSS. During the so-called power-down phase of each ramped cycle, the state of the circuit is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (pulsed power supply) CMOS and is characterized by a power dissipation property that is typically approximately an order of magnitude less than that of conventional CMOS. The technique is described in "Pulsed Power Supply CMOS--PPS CMOS" by T. J. Gabara, Proceedings of 1994 IEEE Symposium on Low Power Electronics, San Diego, Calif., Oct. 10-12, 1994, pages 98-99. Further, the technique is described in T. J. Gabara's copending commonly assigned U.S. patent application Ser. No. 08/225,950, filed Apr. 8, 1994, now U.S. Pat. No. 5,450,027.
In practice, an oscillator circuit designed to generate a sinusoidal waveform can be utilized to power PPS CMOS circuits. Ideally, such an oscillator circuit should be relatively simple and should itself exhibit a relatively low-power-dissipation characteristic.
A relatively simple low-power-dissipation oscillator circuit suitable for generating sine-wave signals for driving PPS CMOS circuits includes an inductor connected in series with a capacitor. In practice, the capacitor of such a series-resonant path typically comprises the effective capacitance of the CMOS circuits to be driven. [A specific illustrative oscillator circuit comprising such a series-resonant path is described in a copending commonly assigned U.S. patent application of T. J. Gabara, Ser. No. 08/355,124, filed Dec. 13, 1994.]
In a variety of important practical applications, data flow in an information processing system is designed to occur at a prescribed rate. This may be accomplished, for example, under control of signals provided by a master timing source such as a crystal oscillator. The signals generated by the crystal oscillator serve as a standard against which all operations in the system are timed.
Thus, in such an information processing system that includes PPS circuits, it is necessary that the output of the oscillator circuit that drives the PPS circuits be established and maintained in a synchronous relationship with respect to the output of the master timing source. Maintaining such a relationship is necessary to assure reliable interfacing and data flow between the PPS circuits and conventional CMOS circuits included in the system.
Establishing and maintaining a synchronous relationship between the output of a master timing source and the output of the oscillator circuit that drives PPS circuits is often in practice a difficult and challenging task. This is so for several reasons. For example, manufacturing variations inevitably occur in the value of the inductor included in the series-resonant path of the oscillator circuit. Because of this, the actual output frequency of each assembled oscillator circuit will typically vary from its prescribed value. Also, the value of the capacitor included in the series-resonant path depends on the effective capacitance of the particular chip or chips driven by the oscillator circuit. As the number and type of these driven chips changes, so too of course does the effective capacitance included in the path, whereby the output frequency of the oscillator circuit again is caused to vary from the prescribed value.
USPTO Backgrounds
USPTO Backgrounds