1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a test pattern which allows a cause of a failure in a borderless via hole to be precisely understood.
2. Description of the Prior Art
As known in the art, a semiconductor device is manufactured in a laminated layered structure. Accordingly, in metal wiring for electrical connection between upper wiring and lower wiring, a multi-layer metal wiring structure is employed, which allows wiring design to be easy and setting for wiring resistance and electric current capacity to be freely performed.
In such a multi-layer metal wiring structure, electric contact between lower metal wiring and upper metal wiring is generally performed by via contacts. In order to form such via contacts, an interlayer dielectric layer formed so as to cover the lower metal wiring is etched, via holes for exposing portions of the lower metal wiring is formed, and plugs are formed in the via holes. Therefore, the lower metal wiring is contacted with the upper metal wiring through the plugs.
Meanwhile, when the multi-layer metal wiring is formed, it is very important to check alignment state between the upper metal wiring and the lower metal wiring and to allow precise alignment to be performed between the upper metal wiring and the lower metal wiring through the checking, in view of device reliability and manufacturing yield.
Accordingly, in a typical semiconductor manufacturing process, a test pattern is inserted into a separate space in order to check the alignment state between the upper metal wiring and the lower metal wiring. A structure of a typical bordered via test pattern formed in a conventional semiconductor device is as shown in FIGS. 1a and 1b. 
In FIGS. 1a and 1b, a reference numeral 2 represents lower metal patterns, a reference numeral 4 represents hole patterns, and a reference numeral 6 represents upper metal patterns.
Referring to FIG. 1a, each lower metal pattern 2 and each upper metal pattern 6 are shaped like a bar, each hole pattern 4 is formed to expose one end and the other end of each lower metal pattern 2, and each upper metal pattern 6 is formed so that its one end and the other end are disposed on each hole pattern 4.
Herein, as shown in FIG. 1b, when it is assumed that each hole pattern 4 has a size of 0.22 μm, a side margin A and an end margin B between each hole pattern 4 and each lower metal pattern 2 are respectively 0.04 μm and 0.04 μm, and a hole pitch C to an X axis is 0.66 μm, a line width W in a Y axis direction of the lower metal pattern 2 is 0.30 μm and a length L in an X axis of the lower metal pattern 2 is 0.96 μm. Also, the hole pitch C becomes a pitch of the lower metal pattern 2 with respect to the X axis.
Meanwhile, each upper metal pattern 6 formed on an upper side of each hole pattern 4 may be patterned in consideration of a side margin and an end margin with each hole pattern 4, or may have margins larger than the side margin and the end margin.
FIGS. 2a and 2b are views of a conventional borderless via test pattern. As shown in FIGS. 2a and 2b, the test pattern shows a structure in which a borderless via has hole patterns 4a shifted with an angle of 45° in comparison with the structure shown in FIGS. 1a and 1b, so as to prevent the hole patterns 4a from being exactly landed to the lower metal pattern 2s. 
Herein, a side margin a and an end margin b between each lower metal pattern 2 and each hole pattern 4a are respectively −0.04 μm and −0.04 μm.
As described above, in the conventional test pattern shown in FIGS. 1a and 1b, alignment state between each lower metal pattern and each hole pattern can be easily understood. However, when a bordered via occurs due to occurrence of alignment failure, it cannot be precisely understood whether the alignment failure has been caused by a misalignment of the hole pattern or line shortening of the lower metal pattern because the hole pattern is shifted in only one direction.
Especially, since the conventional test pattern is very different from those of metal wiring of an SRAM cell block in shapes, the conventional test pattern cannot precisely reflect a cell.
USPTO Backgrounds
USPTO Backgrounds