1. Technical Field of the Invention
The present invention relates to integrated circuits and more particularly to the protection of a component of such a circuit against the formation of a metal silicide.
2. Description of Related Art
At the present time, there is need in the microelectronics field to obtain components having different resistance values. When the components of an integrated circuit undergo a siciliding operation, that is to say the formation of a metal silicide on areas made of silicon, the silicon/metal alloy obtained results in a very low resistance of these areas. On the other hand, when this component has not been silicided, this resistance is high. An example of the component that usually has to have a high resistance is an input/output transistor of a circuit. To obtain components having high resistance values, it is therefore envisaged to protect these components from the siliciding.
At the present time, a method allowing certain elements of an integrated circuit to be protected against the formation of a metal sicilide is known.
More precisely, the method conventionally used involves the deposition of a bilayer comprising a tetraethyl orthosilicate (more widely known as TEOS) layer surmounted by a silicon nitride layer. Those areas of the integrated circuit on which it is desired to form a metal silicide are exposed by removing the bilayer locally. This removal comprises, after the silicon nitride has been etched away, a chemical treatment so as to strip off the TEOS from the areas to be silicided. This chemical treatment uses hydrofluoric acid.
However, this method has drawbacks. A first drawback stems from the high thermal budget used in depositing the bilayer, and this proves difficult to make compatible with a CMOS technology.
Another drawback stems from the fact that the chemical treatment using hydrofluoric acid partly etches the STI (Shallow Trench Isolation) material that separates the various components of the integrated circuit, and this may cause junction losses during siliciding of transistors that are not protected by the bilayer.
There is accordingly a need to provide a solution which does not suffer from the foregoing drawbacks.
USPTO Backgrounds
USPTO Backgrounds