One stage differential amplifiers are commonly used as buffers. However, such a buffer has a settling time which is slope-limited by the capacitance being driver. A common one of such buffers is a source follower. A typical source follower is shown in FIG. 1. The input signal 100 is applied to the gate 102 of an FET 104. Drain 106 and source 108 are appropriately biased. The source is also connected to a constant current source 112. The signal out 110 drive a capacitive load 114.
This device is capable of quickly charging the capacitor through the FET 104. However, the device only provides quick operation in one direction, herein changing direction. The discharge of the capacitor is provided across the high resistance load of the source follower. The load is usually a current sink, which limits the settling time for the falling edge.
Putting this another way, the settling time is slope limited by the charge of the load capacitance with the amplifier reference current.
It is often desirable to limit the amount of power which is used by the circuit. However, a source follower such as FIG. 1 would require charging a 25 pF capacitance by dv=2 volts for 25 nanoseconds. This would require a current typically higher than 2 milliamps.
A two-stage op amp configured as a unity gain buffer could be used to solve such a problem. However, the circuit can become complicated. Moreover, unless the value of the load capacitance is very accurately known, it becomes difficult to stabilize the op amp using standard compensation capacitor techniques.
USPTO Backgrounds
USPTO Backgrounds