1. Field of the Invention
The invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a power metal-oxide-semiconductor field effect transistor (MOSFET).
2. Description of Related Art
Power MOSFETs are widely applied to power switching devices, for example, power supplies, converters, or low-voltage motor controller, and the like. In general, a conventional power MOSFET adopts a vertical structural design to enhance the device density. For each power MOSFET, each drain region is formed on the back-side of a chip, and each source region and each gate are formed on the front-side of the chip. The drain regions of the transistors are connected in parallel so as to endure a considerable large current.
As the level of integration of power MOSFETs increases, the dimension of the same is reduced as well. Therefore, misalignments between contact plugs and trenches in power MOSFETs easily occur so as to affect the performance of the device. For example, misalignments between contact plugs and trenches affect the variations of channel on resistance (Ron) and threshold voltage (Vth), and thus, the reduction of the cell pitch is limited.
Moreover, the working loss of power MOSFETs is categorized into a switching loss and a conducting loss. The switching loss caused by input capacitance Ciss increases with the increase in operating frequency. The input capacitance Ciss includes a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd. Thus, one of the most important tasks is to lower the gate-to-drain capacitance Cgd for effectively reducing the switching loss.
USPTO Backgrounds
USPTO Backgrounds