An electric double-layer capacitor can perform an extremely quick charging in comparison with a storage battery and yet has a storage capacity advantage over the storage battery. The electric double-layer capacitor, however, has a relatively low voltage rating such as a value on the order of 3 volts and therefore, a plurality of electric double-layer capacitors are commonly connected in series in order to generate a desirable voltage.
In charging the capacitors with relatively large capacities, connected in series as described above, there are issues concerning the differences in capacity among the capacitors and an unevenness of charges varied by self-charging and self-discharging. To overcome these issues, a circuit for uniformalizing the charging is commonly used. Such circuit may be referred to as a parallel monitor circuit.
Referring to FIG. 1, a parallel monitor circuit is now explained. As illustrated in FIG. 1, capacitors C1 and C2 are connected in series and are provided with a parallel monitor circuit. For example, the capacitor C1 is provided with a parallel monitor circuit which includes a reference voltage Vr1, a comparator CMP1, a bypass switching element Tr1, and a zener diode D1. The capacitor C2 is provided with another parallel monitor circuit which includes a reference voltage Vr2, a comparator CMP2, a bypass switching element Tr2, and a zener diode D2.
The capacitor C1 is charged by a direct current power source (not shown) and, as the charge is increased, a voltage of the capacitor C1 is increased. When the voltage of the capacitor C1 exceeds the reference voltage Vr1, the comparator CMP1 outputs a high voltage which turns on the bypass switching element Tr1. As a result, a charge current of the capacitor C1 is allowed to flow through the bypass switching element Tr1 and consequently the voltage of the capacitor C1 is clamped at the same voltage as the reference voltage Vr1.
The above-described operation is performed by each one of the capacitors connected in series. This may prevent deterioration and/or damage of the capacitors due to uneven charging. If the capacitor is rapidly charged to a high voltage, the zener diode D1 may be damaged and a relatively large current may flow through the zener diode D1.
The above-described operation is needed to control a plurality of reference voltages predetermined per each capacitor and changes them in accordance with the use conditions. However, it may be difficult to control and change each of the reference voltages for the capacitors when using a huge number of capacitors such as an electric automobile, an electric power reserve system, etc.
In one attempt for the above circuit, an operational voltage is controlled by applying a voltage setting signal to a plurality of the capacitors from a common signal source through a joint circuit. With this structure, a remote control can be carried out in a simple structure.
To charge a large number of capacitors using this circuit structure, the number of parallel monitor circuits is increased and accordingly a space shared by the circuit increases, resulting in a high manufacturing cost.
Integration of the parallel monitor circuits involves various issues. When the power source for the comparator is supplied from the terminal voltage of the corresponding capacitor, as shown in FIG. 1, an isolated area for forming each comparator circuit is needed on the semiconductor substrate.
There are three isolation methods to isolate each of the comparators on the semiconductor substrate; a PN junction method; a method using an isolation material; and a beam lead method. The PN junction method uses a characteristic that a PN junction applied with a reverse bias has an isolation region. The PN junction method has drawbacks of a relatively low resistance to pressure, a relatively large stray capacitance in the circuit, and a high frequency signal due to its large capacity. One example of using an isolation material implants a silicon oxide layer to a silicon substrate. The beam lead method dissolves the substrate between the elements by way of a chemical method to isolate the elements. Among these three methods, the second and third methods require a huge cost.
In using the first method having an N-type semiconductor substrate, an issue is a formation of an independent isolation region (i.e., Pwell region) which is needed to be formed for each of a plurality of comparators. In the same way, when the first method uses a P-type semiconductor substrate, an isolation region (i.e., an Nwell region) is needed to be formed, resulting in a large chip area which also causes a problem of a high manufacturing cost.
Further, if the source power for the comparators is supplied from a direct-current power source which charges the serially-connected capacitors, the necessity for forming the isolation region (i.e., the Pwell or the Nwell) for each comparator is eliminated and therefore the chip area can be made smaller. However, in this case, an amplitude of the output voltage from the comparator expands approximately to that of the source power voltage, resulting in damage to a bypass switching element used therein.
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