1. Field of the Invention
The present invention relates to a microprocessor having a cache memory, and particularly to a pipeline processor and pipeline processing method for the microprocessor.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional pipeline processor. An instruction reading part 1 reads a machine language instruction. A decoding part 3 decodes the instruction. An address generating part 5 provides an operand address. Based on the operand data, an executing part 9 executes the instruction. A writing part 11 writes a result of the execution.
The data reading and writing processes mentioned above are carried out with respect to a cache memory 13. When data are read out of the cache memory 13, an address tag area of the cache memory 13 is simultaneously searched for an address tag of the read data to judge the validity of the read data. This reading operation needs, therefore, only one machine cycle.
When data are written into the cache memory 13, there is a risk of writing the data into an incorrect location of the cache memory 13 if the data writing operation and address tag searching operation are simultaneously carried out and if a cache miss is judged by the address tag searching operation. To avoid the risk, the address tag searching operation must be done first, and then the data writing operation. The data writing process requires, therefore, two machine cycles.
FIG. 2 shows a flow of pipeline processes carried out in the conventional pipeline processor of FIG. 1. Respective processing stages are vertically arranged in FIG. 2 with the same reference marks seen in FIG. 1. In FIG. 2, time elapses from the left to the right, and an interval between adjacent dotted lines corresponds to one machine cycle.
In FIG. 2, a read instruction A, write instructions B and C, and a read instruction D are pipeline-processed in parallel. The fifth and sixth machine cycles of an operand reading stage OF carried out in the operand reading part 7 are blank, because the write instructions B and C do not involve an operand reading operation. Each of the write instructions B and C requires, however, two machine cycles in a writing stage OS carried out in the writing part 11. The first one of the two machine cycles is used to search the cache memory 13 for an address tag of data to be written, and the second one is used to write the data into the cache memory 13.
In this way, the conventional pipeline processor involves a processing stage where blanks occur and a processing stage where two machine cycles are consumed. These are disadvantages in achieving an effective parallel processing.
USPTO Backgrounds
USPTO Backgrounds