Processing systems may employ different bus architectures for transport of data between different components. Depending on particular applications and implementations, the bus architectures may include topologies such as a ring, mesh, star, etc. as known in the art, and various protocols and standards may be followed for sending and receiving data on the buses.
One or more agents such as processors, caches, etc. may be coupled to a data bus. In some implementations, one or more agents may be connected to the data bus through a bus interface unit such as a switch unit. The bus interface units may include arbiters to manage data traffic sent on to the data bus from the one or more agents and the data traffic received from the data bus for consumption by the one or more agents. For instance, a bus interface unit may employ one or more queues, also referred to as virtual channels, for storing requests from the one or more agents. When more than one request is pending, arbitration techniques are employed to select requests to be sent out.
One consideration for the arbitration techniques is to reduce power consumption. As will be recognized for processing applications involving servers, mobile systems on chips (SoCs), battery powered and handheld devices, etc., there is an ever increasing need to reduce power consumption. In the case of data buses for such processing applications, e.g., high performance bus networks traversing long distances, wide wire bundles between different switch units, etc., dynamic power contributes a significant portion of the overall power consumption. Thus, there are techniques employed in the art for reducing dynamic power consumption of data buses.
One such technique is referred to as bus invert coding, wherein either an outstanding word from a virtual channel or the inverse of the word, whichever one of the two would result in the least amount of switching activity on the data bus, is selected by a bus interface unit connected to the virtual channel, to be transmitted on to the data bus. Bus invert coding seeks to minimize switching activity and thus reduce power consumption. In implementations of these techniques, a state bit or similar information is also sent along with the transmission from the bus interface unit, to indicate whether the transmission is of the originally intended word from the virtual channel or the inverse of the word. Accordingly, such techniques involve adding wires for the state bit and additional control signaling, and in cases where the wires cross chip or package boundaries, adding additional pins and input/output ports.
Furthermore, techniques such as bus invert coding do not take into account the switching power of more than one word. Thus, if there are multiple outstanding words for transmission from multiple virtual channels connected to the bus interface unit, a conventional arbiter may resort to a work-conserving round robin approach in selecting words from the multiple virtual channels, which does not take into account switching power considerations across the multiple words. For example, two consecutive words transmitted from the bus interface unit based on the round robin approach may be apart from each other by a high switching distance, referred to as a Hamming distance in the art. The high Hamming distance can lead to a high switching power, thus increasing the dynamic power consumption of the transmission of the words on the data bus.
Accordingly, there is a need in the art for improved arbitration techniques for reducing dynamic power consumption of data buses, while avoiding the aforementioned limitations of the known approaches discussed above.
USPTO Backgrounds
USPTO Backgrounds