The present invention relates to a memory device, and more particularly to a memory device basically identical to that of a shift register having a depth of variable stage.
Shift registers comprising a plurality of registers cascade-connected to shift their contents in sequence play an important role in computational processings or image processings, etc. Products having various capacities of 4, 8, 16, 1024 and 64K bits, etc. have been available.
Referring to FIG. 1, there is shown an example of a commonly used conventional shift register 10 of 8 bit configuration. This shift register 10 comprises eight stages of flip-flops 1 to 8 wherein Q outputs of the flip-flops are respectively connected to D inputs of the next stages thereof and a clock line is commonly connected to the respective flip-flops.
With the shift register thus configured, when a clock pulse signal is input from the clock line CLK, data input to the leftmost flip-flop 1 is transferred to the right per each clock pulse and output data is fetched from an output terminal OUT 1 of the rightmost flip-flop 8.
To change the number of stages in the shift register 10 of the eight stages, as shown in FIG. 1, a method has been employed to provide lead-out or draw-out lines on the output sides of the respective stages of the flip-flops to switch the lead-out lines by using a changeover switch 9 to fetch an output delivered through the selected lead-out line from an output terminal OUT 2 to the external.
When the shift register has a small number of stages as in the above-mentioned example, this method is satisfactory, but when the shift register has a large number of stages, its realization is impossible in an actual sense.
For instance, when characters or figures (graphic pattern) are displayed on a CRT using a display device, there is employed a method to store display information in a storage unit to use the information read for a required display. When there is no change in information corresponding to one frame (frame information), it is convenient to repeatedly read the display information at a rate of 60 per second. Generally, a volume of such an information corresponding to one frame is not necessarily expressed by the second power (power of 2) and the frame information requires a large capacity. Hitherto, for storing such a frame information, it was necessary to specially provide a storage unit having a required memory capacity, resulting in high cost of the device. In addition, in the case of the above-mentioned example, since all of the memory capacity of the second power are not used, there occurs a wasteful memory capacity and an operation for combining valid or effective informations with each other is required.
USPTO Backgrounds
USPTO Backgrounds