To satisfy the ever increasing need for bandwidth, the external I/O interfaces of Central Processing Units (CPU's) and other semiconductor components have increased significantly both in frequency and data width. The increase in frequency has resulted in system designs that must carefully match the electrical length of signal traces between a CPU and a memory controller such that synchronous signals can be received with a common clock and a common phase. This design requirement is sometimes known as “length matching” or “delay matching.” Length matching can be difficult given the serpentine routing required for many signal traces. While the following discussion concerns the parallel transmission of data and clock signals, the same considerations also apply to systems using source synchronous strobing, where a strobe signal is transmitted in parallel with a data signal.
Length matching, however, has a number of undesirable consequences, including increased Electro-Magnetic Interference (EMI) from the increased routing area, increased power consumption from the larger total trace capacitance and resistance, increased board area, and increased board layer count. Length matching also increases coupling between signals, thus reducing their Signal-to-Noise Ratio (SNR). In other words, length matching increases system costs and power consumption and lowers overall system performance. In addition, carefully aligning data transitions increases the simultaneous switching output (SSO) noise of the transmitting device and increases the “ground bounce” associated with turning on many output drive transistors simultaneously. SSO and ground bounce can, in some devices, limit the switching frequency at which a device will function both properly and within regulatory noise limits.
Several techniques to free a system designer from the need to length match are known. One such technique is known as CDR, where the clock signal is carried on the same wire (or differential pair of wires) as the data. However, in order to use CDR, both the CPU and the memory controller must be equipped with special CDR circuitry. Most CPU's, however, do not have such circuitry. Also, using CDR to recover data introduces additional latency and power consumption.
Another technique involves performing a timing sweep to determine the optimal transmit or receive timing. This technique, while applicable to many integrated circuits, is not ideal for calibrating the CPU-memory controller interface because it requires the active participation of the CPU and the memory controller and suffers from a “live lock” problem. That is, the CPU and the memory cannot communicate timing information reliably in either direction before they are synchronized by a software algorithm. But the software algorithm cannot be reliably executed by the CPU prior to the establishment of proper transmit and receive timing.
Accordingly, what is needed is an alternative to length matching that enables high speed data communication between one integrated circuit (e.g., a CPU) and another integrated circuit (e.g., a memory controller) without requiring special circuitry for at least one of the devices.
USPTO Backgrounds
USPTO Backgrounds