This invention relates to memory access in a processing system. More particularly, this invention relates to a method, a system and a device for a processor to access memory devices of different speeds using a standard memory bus.
A product, such as a printer, typically includes a specially designed part, such as a print head, for which an accompanying application specific integrated circuit (ASIC) is usually designed. The specially designed print head, which may account for a large proportion of product design cost, is thus leveraged and used in a range of products. For example, a printer family that uses the print head may include a basic printer, a printer with a network functionality, a printer having a network hard disk, a photo printer supporting various types of photo media, and a multi-functional printer including scanner and facsimile functionalities. It would be ideal to build a single ASIC including the different functionalities that can be used across all printers. However, the cost of such an ASIC will be prohibitively high since an ASIC that includes a large number of functionalities is complex to design and produce. The design cycle is proportionately longer than would be required for designing a less complex ASIC. As there are more components in such a complex ASIC, production yield for the ASIC may be lower. Furthermore, building functionalities that are not utilized in an ASIC is also wasteful and adds unnecessary cost to a product.
One solution is to have a basic ASIC for the basic printer and additional function-specific add-on ASICs that can be connected to the basic ASIC. These add-on ASICs are typically connected to the basic ASIC using a Peripheral Component Interconnect (PCI) bus. Such a PCI bus includes sixty or more signal lines, usually more when power and ground signal lines are counted. The basic ASIC and the add-on ASICs supporting such an interface will need to include a corresponding number of ports or pins for interfacing with the PCI bus. These ASICs will cost more than one with a lesser number of pins.
To reduce the number of pins on the basic ASIC, a standard host bus used for accessing an SDRAM has been used to also interface with a bridge device to which a PCI device is connected. Such a design has been disclosed in U.S. Pat. Nos. 5,632,021 and 6,247,088. However, the design suffers a notable disadvantage. To accommodate the bus speeds of slower PCI devices, the standard host bus is operated at only a clock speed of 33 MHz. With some of these PCI devices having relatively long access latency, the sustainable standard bus throughput seldom exceeds 50 Mbytes per second. Operating the SDRAM at such a throughput is not efficient considering that an SDRAM throughput of about 400 Mbytes per second is achievable.
To overcome this disadvantage, another method that is common with standard PC chipsets has been used. According to this method, the bridge ASIC is also connected to the basic ASIC using a host bus. However, the SDRAM, IDE and PCI interfaces are provided by the bridge ASIC. Such a design results in a bridge ASIC that is more complicated and thus costly, especially for low cost printing and imaging products.
USPTO Backgrounds
USPTO Backgrounds