Host devices such as computers, laptops, personal video recorders (PVRs), MP3 players, game consoles, servers, set-top boxes, digital cameras, and/or other electronic devices often need to store a large amount of data. Storage devices such as hard disk drives (HDDs) may be used to meet these storage requirements.
A hard disk controller (HDC) communicates with the storage device and the host system. The HDC manages interaction between the storage device and the host system. Communication between the host system and the HDC is usually provided using one of a variety of standard I/O bus interfaces. Typically, when data is read from a storage device, a host system sends a read command to the HDC, which stores the read command into a buffer memory. Data is read from the storage device and stored in a buffer memory.
The buffer memory typically includes volatile memory having low latency. The buffer memory may be a synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR SDRAM) (referred to herein as “DDR”). Typically, SDRAM transfers data at the positive edge of a clock signal at the HDC. In contrast, DDR memory transfers data on a rising and falling edge of a clock signal of the HDC. Hence, SDRAM is a single data rate memory device and DDR memory has double the transfer rate of SDRAM.
In DDR systems, address and commands are managed similarly to SDRAM systems. However, DDR systems manage data further based on a separate clock signal such as a data strobe signal (DQS). For example, the DDR memory generates the DQS during read operations. DDR systems transfer data to and/or from the DDR memory based on the DQS. Typically, DQS signals are delayed with respect to the data that is read from a DDR-based buffer memory.
USPTO Backgrounds
USPTO Backgrounds