A flip flop is a very common and well-known element in the field of electronics and integrated circuits. A common use and functionality for a flip flop is to store a single bit value, and thus a flip flop is a single bit storage element. FIG. 1 illustrates a standard flip flop 100, as is known in the art. Standard flip flop 100 may comprise two latches 104 and 106. Latches 104 and 106 each have inputs D and outputs Q and are coupled in series with an inversion in the level sensitivity through inputs E to provide single-bit storage. A scan multiplexer 102 may be coupled to an input D of each of multiple flip flops 100 in an integrated circuit so that the various flip flops 100 within the integrated circuit design may be scan testable. Scan multiplexer 102 may receive control signal SE and may have data inputs D and SI.
FIG. 2 illustrates an example timing diagram 200 for standard flip flop 100, as is known in the art. Timing diagram 200 shows an example input signal for input D and an example output signal for output Q for flip flop 100 timed in accordance with a clock signal CLK received at inputs E of latches 104 and 106. Timing diagram 200 for flip flop 100 further illustrates an example set-up time tsu, an example hold time th, and an example clock-to-output time tcq. A set-up time tsu may define a minimum amount of time a data signal on input D of flip flop 100 should be held steady before a clock event (e.g., rising edge of clock signal CLK) so that data is reliably sampled by flip flop 100. A hold time th may define a minimum amount of time a data signal should be held steady after the clock event (e.g., rising edge of clock signal CLK) so that the data is reliably sampled by flip flop 100. A clock-to-output time tcq (also sometimes referred to as a clock-to-output delay or propagation delay) may define a time in which flip flop 100 takes to change an output signal on output Q after the clock event (e.g., rising edge of clock signal CLK).
As with any circuit element, standard flip flop 100 may take up area within an integrated circuit and consume power in operation. In most integrated circuit designs, it is often desirable to reduce area and power consumption of integrated circuit components, including standard flip flops. In addition, it is often desirable to minimize the various timing parameters of a flip flop of a storage element, including set-up time tsu, hold time th, and clock-to-output time tcq 
USPTO Backgrounds
USPTO Backgrounds