1. Field of the Invention
The invention relates generally to the field of power converters controlled through digital pulse-width modulation (PWM). More particularly, the invention relates to a digital control scheme for PWM converters that enables a fast transient response to be achieved while maintaining very low steady-state jittering.
2. Description of Related Art
The use of pulse-width modulation (PWM) to control the output voltage of a power converter is well known. FIG. 1 illustrates a simplified PWM control circuit for a buck-type power converter that is typical of the prior art. A primary voltage 106 is selectively applied to an inductor 114 by a switch 108. When the switch 108 is closed, the diode 110 is reverse biased, and the current through the inductor 114 rises linearly as it stores magnetic energy. When the switch 108 is opened, the inductor energy is discharged to the output 112 as the inductor's magnetic field collapses. As the switching cycle is repeated, the output voltage thus achieves a level that is related to the input voltage 106 and is dependent on the duty cycle of the switch 108. For a buck conversion circuit such as that shown in FIG. 1, the output voltage, Vout, is related to the input voltage Vin by the expression Vout=Vin×D, where D is the duty cycle, or the fraction of the switching period during which the switch is closed. In other words, the output voltage level is set by controlling the duty cycle of the switch 108.
Controlling the duty cycle of switch 108 can be performed by an analog PWM control loop as illustrated in FIG. 1. The output voltage 112 is scaled and compared to a desired reference voltage 102, and an error voltage signal 116 is produced, reflecting the deviation of the output voltage 112 from the desired regulation point 102. The error voltage is then compared with a periodic ramp waveform 104, and the resulting PWM voltage is used to drive the switch 108.
FIG. 2 depicts the voltage ramp waveform 202, an error voltage 204, and the resulting PWM waveform 206 plotted as a function of time 208. In this example, the error voltage 204 is relatively low compared to the center of the ramp voltage 202, resulting in a PWM waveform 206 exhibiting a relatively large duty cycle that will cause the output voltage to rise, reducing the error voltage. While this example is described with respect to a particular buck converter topology, the same principles are employed for other types of switched power converters.
Moving from analog to digital PWM control systems provides a number of advantages including in situ programmability to fit a wide variety of applications, expanded control functionality, and adaptive control algorithms, among others. FIG. 3 is a simplified block diagram, typical of the prior art, of a power converter employing a digital PWM control loop. A switching converter 304 operates in a manner similar to the circuit of FIG. 1 to convert an input voltage 302 to an output voltage 306. The output voltage 306 is then digitized by an analog-to-digital converter (ADC) 308 to produce a digital output voltage sample 324. This digital output voltage sample is subtracted from a digital reference sample 312 to create a digital error sample 314. The error sample is processed by a digital compensator filter 316, which generally has a proportional-integral-differential (PID) character, to produce a digital control signal 318 that drives a digital PWM circuit, generally implemented as a digital counter or as a mixed-signal device. The PWM output waveform 322 is then used to drive the switching element of the switching converter 304 to provide closed-loop control of the output voltage 306. The digital nature of the compensator 316 provides flexibility in the filtering operation that cannot be achieved in a purely analog system. In addition, the digital PWM circuit 320 is programmable and allows the converter to be used in a variety of applications.
However, digital control systems also raise certain performance issues that stem from the quantization of time and voltage amplitude. In particular, the resolution of output voltage control depends on the ratio of the PWM switching frequency to the sampling clock of the system. Measured in number of bits, the resolution is given by Log2(TSW/TDPWM), where TSW is the switching period of the digital PWM circuit and TDPWM is the clock period used to implement the digital PWM. In typical point-of-load applications, the switching frequency can be as high as one megahertz, and the input-to-output voltage ratio can be ten, as in a typical 12 V-to-1.2 V conversion system. Given 1% regulation requirements, the PWM clock frequency is thus required to be in the range of several gigahertz. Implementing such a high-frequency clock adds complexity, power consumption, and cost and is thus undesirable.
An additional performance issue raised by digital PWM systems is a phenomenon known as limit cycling. When a digital PWM circuit does not have sufficient resolution, periodic low-frequency oscillation can be observed at the output. This low-frequency oscillation can result in excessive output voltage ripple, often in the range of a few percent, which is unacceptable for many applications.
A lack of sufficient resolution in the digital PWM can result in another phenomenon called jittering. Without sufficient DPWM resolution, the output error voltage cannot remain within the zero-error bin. When the error voltage is not inside the zero-error bin, a duty-cycle correction command will be initiated, resulting in a duty-cycle change. This duty-cycle change, observed at the phase node, is the jittering of the system. This measure is used by many customers to decide whether or not the power stage is in a good state of regulation. High jittering means the controller needs to employ frequent, large duty-cycle corrections, suggesting that the system is not in a very stable condition. In a system with lower jittering, the controller must make only small duty-cycle corrections, keeping the output voltage in a state of tight regulation.
Accordingly, it would be desirable to provide a digital PWM control system and method that addresses the issues discussed above. In particular, it would be desirable to provide a method of reducing phase-node jittering and output voltage ripple without requiring a very-high-resolution digital PWM circuit and very high clock rates. And it would be useful to decouple the transient response of the system from the jittering such that a fast transient response could be achieved without increasing the phase-node jittering. Finally, it would be useful to reduce the susceptibility of the digital PWM control system to noise within the regulation bin surrounding the operating point at which the output voltage is very close to its control value.
USPTO Backgrounds
USPTO Backgrounds