1. Field of the Invention
This invention generally relates to a high order sigma delta analog-to-digital converter and, more particularly, to a high order sigma delta oversampled analog-to-digital converter integrated circuit network which is economical in both power dissipation and chip area requirements.
2. General Description of the Prior Art
High resolution, analog-to-digital (or A/D) signal conversion can be achieved with lower resolution components through use of high order oversampled interpolative (or sigma delta) modulation followed by digital low pass filtering and decimation. Oversampling refers to operation of the modulator at a rate many times above the signal Nyquist rate, whereas decimation refers to reduction of the clock rate down to the Nyquist rate.
In the above type of analog-to-digital converters, resolution is predominantly governed by two factors: (1) the ratio of the modulator clock to the Nyquist rate, henceforth referred to as the oversampling ratio, and (2) the "order" of the modulator. Order in this context is analogous to the order of a frequency selective filter and indicates the relative degree of spectral shaping that is provided by the modulator. A "high order" analog-to-digital converter a third or higher order network.
As with a filter, higher selectivity is obtainable with a higher order at the expense of increased hardware complexity. In recognition of the aforementioned two factors governing resolution of oversampled analog-to-digital converter networks, recent implementations of high resolution oversampled analog-to-digital converters have employed both large oversampling ratios and high modulator order. However, practical considerations can limit the extent to which oversampling rate and modulator order can be taken. For instance, for a given modulator clock rate, the oversampling ratio is inversely proportional to the Nyquist rate after decimation and thus cannot be made arbitrarily high without sacrificing conversion rate. Different considerations set bounds on the modulator order. Implementation of order greater than two, using a single quantizer, can be shown to be only conditionally stable and are therefore not viable.
An alternative approach can be used to effectively provide high order noise shaping with cascaded low order modulators to ensure stable operation. Unfortunately, the matching of the modulators in such structure is crucial, and the degree of mismatch governs accuracy of the overall converter. Requirements of close component matching and high operational amplifier (or "op amp") gains imply that such circuit can only be manufactured with a low yield, and possibly will require trimming, thereby being expensive to produce.
Early work in this field has been directed at implementation of modulators of first and second order, due to the stability concerns connected with orders of three or greater. T. Hayashi et al., in "A Multistage Delta-Sigma Modulator Without Double Integrator Loop", Proc. IEEE 1986 Int. Solid-State Circuits Conf., pp. 182-183, Feb. 1986, describe an approach in which second order performance is obtained using a cascade connection of two first order stages. The quantization error of the first stage is supplied to the second stage so that the second output signal, after a digital differentiation, contains a replica of the frequency-shaped quantization noise. Finally, a subtraction of the second stage output signal from that of the first stage yields a signal that contains only the quantization noise of the second stage with second order noise-shaping. However, this method requires tight matching of the characteristics of the two first order modulators and high op amp gains.
An extension of the above approach to third order analog-to-digital converter networks using a triple cascade connection of first order modulators is described by Y. Matsuya et al. in "A 16-Bit Oversampling A-D Conversion Technology Using Triple Integration Noise Shaping", IEEE J. Solid-State Circuits, Vol. SC-22, No. 6, pp. 921-929, Dec. 1987. However, this approach requires even tighter component matching and also requires high op amp gains in order to achieve the theoretically obtainable resolution.
A slightly different approach is disclosed by L. Longo and M. A. Copeland in "A 13-Bit ISDN-Band ADC Using Two-Stage Third Order Noise Shaping", Proc. 1988 Custom Integrated Circuit Conf., pp. 21.2.1-4, June 1988, wherein a second order modulator is connected in cascade with a first order modulator to implement third order noise-shaping. This approach has the advantage of reducing the component matching requirements somewhat from the other implementations.
The aforementioned U.S. patent application of David B. Ribner, entitled "Third Order Sigma Delta Oversampled Analog-To-Digital Converter Network With Low Component Sensitivity", Ser. No. 07/505,384, now abandoned in favor of continuation-in-part application Ser. No. 07/550,763, filed July 10, 1990, describes an improved third order sigma delta analog-to-digital converter network which achieves third order noise shaping with reduced sensitivity to component mismatching and other nonidealities. An improved architecture for a third order sigma delta analog-to-digital converter network which can be implemented as a sampled-data switched-capacitor circuit is therein described. For enhanced accuracy and economical operation, it is desirable to minimize internal noise and reduce power requirements of such circuits.
If a high order oversampled analog-to-digital converter (or ADC) is to achieve accuracy beyond the 12 bit level, it must be designed so that its internal noise sources are suitably low. Such design requires use of large-valued capacitors to minimize kT/C noise (where T is circuit absolute temperature (.degree.K.), C is the sampling capacitance (farads), and k is Boltzmann's constant), and often requires chopper stabilization to reduce low frequency op amp flicker (or 1/f) noise. A discussion of 1/f noise is presented in R. Gregorian, "Analog MOS Integrated Circuits for Signal Processing", pp. 500-504, Wiley, New York, 1986, incorporated herein by reference. A major disadvantage of using these options is the requirement for increased area on the integrated circuit (IC) chip to be occupied by the larger capacitors, for the corresponding larger op amps required to drive the capacitors, and the chopper circuitry. Another resulting problem is a much increased power dissipation accompanying operation with large capacitances.
Previous ADC implementations employ identical circuitry at each stage in high order modulators, operate at high power levels, and require large portions of IC chip area. See, for example, S. R. Norsworthy and I. G. Post, "A 13 Bit Sigma-Delta A/D Convertor For ISDN", Proc. IEEE Custom Integrated Circuits Conf., pp. 21.3.1-4, May 1988, and the aforementioned Y. Matsuya et al. and L. Longo et al. papers.
USPTO Backgrounds
USPTO Backgrounds