The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for layout retargeting for electrical yield enhancement.
Optical lithography is a crucial step in semiconductor manufacturing. The basic principle of optical lithography is quite similar to that of chemistry-based photography. The images of the patterned photo-mask are projected through the high-precision optical system onto the wafer surface, which is coated with a layer of light-sensitive chemical compound, e.g. photo-resist. The patterns are then formed on the wafer surface after complex chemical reactions and follow-on manufacturing steps, such as development, post-exposure bake, and wet or dry etching.
The resolution of the photo-lithography system (R) can be described by the well-known Rayleigh's equation:
  R  =                    k        1            ⁢      λ        NA  in which λ is the wavelength of the light source, NA is the numerical aperture, and k1 is the factor describing the complexity of resolution enhancement techniques. As the very-large-scale integration (VLSI) technology pushes further into nanometer region, the feasible wavelength of the photo-lithographic system remains unchanged at 193 nm. Although there is anticipation that extreme ultraviolet lithography (EUVL) with the wavelength of 13 nm will replace traditional optical lithography, the availability of EUVL remains uncertain due to technical challenges and cost issues. On the other hand, the physical limit of dry lithography of NA is 1.0. The recently introduced immersion lithography has bigger NA (1.2), but it is harder to further increase NA to even higher values. Thus it is commonly recognized that k1 remains a cost effective knob to achieve finer resolution.
Due to the unavoidable diffraction, the optical lithography system is lossy in the sense that only low frequency components of the electromagnetic field can pass the optical system. As the gap between the required feature size and lithography wavelength gets bigger, the final wafer images are quite different from the patterns on the mask. In the past few years, resolution enhancement techniques (RETs) have become necessary in order to achieve the required pattern density. One well-known RET is the optical proximity correction (OPC), in which the mask patterns are intentionally “distorted” so that the desired image can be formed on the wafer. Other commonly used RETs are sub-wavelength resolution assist features (SRAF) and phase-shift masks (PSM). Nowadays, considerable amount of computing power has to be dedicated to these post-layout processes (often referred as data prep). Large computer farms have to spend weeks of central processing unit (CPU) time to perform data prep after a design is completed. As the technology is further pushed, manufacturing variations (e.g., dose and focus variations during the lithograph steps) have to be considered.
Lithographic variation in parameters such as exposure dose, focus, mask error, overlay, etc. may cause significant deviation in the printed wafer image from the desired target layout. The response of a layout feature to lithographic sources of variation is typically represented by process variability band (PV-band). PV-bands represent the geometric variation in the printed wafer image contours over desired process window. These bands are generated by aerial image simulations on post Optical Proximity Correction (OPC) mask pattern at different process window corners. The resulting aerial image contours for different corners are combined together to generate inner (minimum) and outer (maximum) limits on the printed wafer contours. PV-bands represent the geometric region between these outer and inner contours indicating that the printed wafer image can lie anywhere between these two physical extremes due to lithographic variability. Besides impacting manufacturing yield, PV-bands may also degrade parametric yield by impacting the electrical behavior of a circuit.
USPTO Backgrounds
USPTO Backgrounds