As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory device (DRAM) or static-random-access-memory device (SRAM), the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components.
One technique to reduce SRAM memory cell dimensions is to split the wordline over the cell. The wordline controls read and write functions to the cell by turning the access transistors on and off. By splitting the word line into two separate lines, a more symmetrical cell layout is possible. However, even with a split wordline memory cell design, a need remains to further reduce the overall cell dimensions. Although split wordline designs reduce the area of the cell, fundamental manufacturing limitations remain. Active surface regions of the cell must be made available for the interconnection of leads providing supply and ground voltages to the cell. In addition, active surface area must be available for the formation of driver transistors and pass transistors providing read and write functions for the cell. Simple downsizing of components can only be pursued to the limit of the line-width definition capability of the manufacturing process. Once the line-width definition limits are reached, new design methodology must be employed if further reduction in memory cell area is to be achieved.
Another technique for fabricating a memory cell having a small surface area is to stack MOS transistors in a vertical arrangement. Typically, a driver transistor is formed in the substrate having source, drain, and channel regions in the substrate and a gate electrode overlying the substrate surface. Then, a second transistor is formed in a thin-film layer overlying the first transistor. By adding an additional electrical component to the device, the thin-film transistor increases the functional capacity of a device while not consuming additional surface area or requiring further downsizing of components.
While thin-film transistors remain a useful design alternative for the formation of compact devices, they usually exhibit poor performance. Thin-film transistors are most often formed in an amorphous or polycrystalline material which does not conduct charge as well as a single-crystal silicon substrate. Therefore, the use of thin-film transistors in memory devices has been limited to either load resistor functions, or to asymmetrical SRAM cells. Because each driver transistor in the asymmetric SRAM cell has a different current handling capability, the the asymmetric SRAM has unmatched inverter characteristics. However, in either the conventional SRAM cell or the asymmetric SRAM cell, valuable substrate surface area is used for the formation of high-performance driver transistors, and the like. The prior art practice of placing at least one driver transistor in the substrate limits the further downsizing of semiconductor memory cells.
USPTO Backgrounds
USPTO Backgrounds