1. Field of the Invention
The present invention relates to a logical simulation device for performing logical simulation of a semiconductor integrated circuit in large scale integration (LSI).
2. Description of the Prior Art
This kind of conventional logical simulation device inputs test patterns as operational descriptions for logical circuit verification and circuit information, including delay characteristic factors between circuit blocks, in a semiconductor integrated circuit as a target of the logical simulation operation, then compares results of the logical simulation operation with expected designed values, and decides the correctness of the logical circuits in the target semiconductor integrated circuit.
In this conventional case, each delay value is calculated using data stored in a library in which delay characteristic factors of each circuit block forming the target semiconductor integrated circuit in the logical simulation are stored. In this conventional method, this calculation of each delay value is performed separately from the logical simulation operation.
FIGS. 1A and 1B are diagram showing the conventional delay value calculation device and the logical simulation device. In FIG. 1A, the reference number 101 designates the conventional delay value calculation device. This conventional delay value calculation device 101 inputs information stored in the memory 102 storing circuit diagrams, information stored in the library 103 storing delay values and timing check values, and back annotation information 104, and then calculates information for the circuit diagrams in the target semiconductor integrated circuit in the logical simulation, delay values required during the logical simulation operation, and the timing check values, and stores calculation results in the file 105. The library 103 stores information of the each of macro cells in the target semiconductor integrated circuit such as minimum units in the circuit, for example, a flip/flop, an OR gate, a AND gate, a NOR gate, a NOT gate, and the like that are provided by ASIC vendor. The reference number 106 designates the logical simulation device. The logical simulation device 106 inputs the circuit diagram information 102 for the target semiconductor integrated circuit in the logical simulation, test patterns as test information, the delay values stored in the file 105 and the timing check values as the calculation results, and then performs the logical simulation using that information, and outputs test results of the logical simulation operation into a test result file 108.
Next, a description will be given of the operation of the conventional delay value calculation device 101.
FIG. 2 is a flow chart showing the operation of the conventional delay value calculation device 101.
In the delay value calculation, first, the delay value calculation device 101 checks delay characteristic factors in circuit blocks such as delay value, wiring capacitance, wiring resistance, and input capacitance of each circuit element in each logical circuit block that affect a signal delay characteristic of each circuit element (Step ST101), and then calculates the basic delay value of each circuit element (Step ST102).
Next, the device 101 compensates the basic delay value by using compensation values of temperature condition, and then calculates the delay value and the timing check value (this timing check value is used only for each of circuits of memory elements such as a latch circuit, a flip flop circuit, and the like) (Step ST103). Then, the delay value calculation device 101 checks whether the calculation has been performed for all macro cells. If YES, the device 101 stops the delay value calculation operation and if NO, the operation of the device 101 returns to the Step ST101 to repeat the above delay value calculation operation.
In this case, it is required to perform the delay value calculation operation for all combinations among input signals. If a macro cell as a target for the delay value calculation operation is a logical sum circuit (an OR gate), delay values for sixteenth combinations of input signals must be calculated as shown in FIG. 3.
That is, when there are ten logical sum circuits in the circuit diagram information that has been given, the delay values must be calculated 160 times (one hundred sixty times, 16.times.10=160) for all combinations. The delay values for other macro cells such as logical product circuits (AND circuits), flip flops, and the like must also be calculated.
FIG. 4 is a flow chart showing the operation of the delay value calculation executed by the logical simulation device 106 by using the delay values and the timing check values that have been calculated the above calculation operation.
First, the logical simulation device 106 selects macro cells corresponding to inputted test patterns in the circuit diagram information 102, and then obtains input signals through input pins of each selected macro cell (Step ST105).
Next, the logical simulation device 106 performs the timing check operation for those input signals by referring to the delay values and the timing check values at the output pin based on the calculated delay value calculation results (Step ST106) and then outputs the output signal (Step ST107).
For example, in the test pattern of the circuit comprising the logical circuits A, B, and C, as shown in FIG. 5, there are four input signals, input signals a1 and a2 are input to the logical sum circuit A, an output signal from the logical sum circuit A and an input signal a3 are input to the logical sum circuit B, and an output signal from the logical sum circuit B and an input signal a4 are input to the logical sum circuit C.
First, the delay value "01" of the logical sum circuit A is obtained by performing the steps ST101 to 103. After this operation, the operation flow returns to the Step ST101, and the delay value "02" is calculated using the delay result of the logical sum circuit A and the delay value of the logical circuit B.
As the result of the above calculation operations, the total delay value obtained by the logical simulation for the test pattern becomes "01"+"02"+"03".
Because the conventional logical simulation device has the above configuration, the operations of the conventional delay value calculation device and the conventional logical simulation device are performed independently in the development of semiconductor integrated circuits.
For example, because the conventional delay value calculation device calculates delay values of all of elements in the semiconductor integrated circuit without referring to any operational descriptions (as input test patterns) for use in circuit test to be given to the logical simulation operation, there is a waste of operation time and waste of information for the semiconductor integrated circuit.
In addition, more detailed timing check operation requires a tremendous volume of information. Furthermore, because the timing check values stored in a conventional cell library are worst cases for the timing check operation (for example, the same timing check value is stored in the cell library for all macro cells of the same type), an adequate timing margin is required during circuit design of semiconductor integrated circuits. Therefore, it is difficult to perform a high-accuracy timing check operation.
In the conventional logical simulation device, coefficients of the states of logical circuits are designated only for the entire circuit. In addition, because the conventional delay value calculation device 101 performs the delay value calculation using the circuit information stored in the circuit diagram information 102 at the start of the calculation operation, it is difficult to compensate for an error in a delay value caused by a specific operation of the target circuit. That is, an error of the delay value caused by a temperature condition when the logical simulation is executed using the test patterns.
USPTO Backgrounds
USPTO Backgrounds