This invention relates to integrated circuit capacitors, and more particularly, to metal-insulator-metal capacitors that are formed in the dielectric stack of an integrated circuit.
The dielectric stack of an integrated circuit commonly contains alternating metal interconnect layers and “via” layers that together provide electrical connection to devices on the semiconductor substrate. Capacitors in the dielectric stack can be formed from the same metal and dielectric materials that are used in forming the interconnects. Forming capacitors in the dielectric stack conserves valuable integrated circuit surface area, as capacitors can be formed directly over semiconductor devices in the substrate.
Capacitors in the dielectric stack can be constructed across multiple metal interconnect layers, and can have geometries that utilize both vertical (interlayer) and horizontal (intralayer) electric field components. For example, metal-comb-woven capacitors may be implemented in metal interconnect layers as a series of metal lines that alternate in voltage both horizontally (within a layer) and vertically (between layers). Such capacitors have electric field lines with both horizontal and vertical components. Metal-comb-woven capacitors can also be implemented so that metal lines in one metal interconnect layer are oriented at right angles to metal lines in adjacent metal interconnect layers. This type of arrangement exhibits reduced interlayer capacitance but is less susceptible to parasitic inductive coupling effects.
The precise geometry that would be optimal to use for capacitors on a given integrated circuit is sensitive to the parameters and capabilities of the current semiconductor technology. For example, as technology advances to enable the formation of smaller devices, and as dielectric materials with lower dielectric constants are used, it might be desirable to use capacitor geometries that take advantage of these changes. It would be desirable to use a capacitor geometry that exhibits a satisfactory capacitance per unit of surface area and limited parasitic inductive coupling effects.
USPTO Backgrounds
USPTO Backgrounds