1. Technical Field
The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a resistance variable memory device having a three-dimensional (3D) structure and a method of manufacturing the same.
2. Related Art
With the rapid development of mobile and digital information communication and consumer-electronic industry, studies on existing electronic charge controlled-devices may encounter limitations. Thus, new functional memory devices other than the existing electronic charge devices need to be developed. In particular, next-generation memory devices with large capacity, ultra-high speed, and ultra-low power need to be developed.
Currently, resistance variable memory devices using a resistance device as a memory medium have been suggested as the next-generation memory devices. Typical examples of the resistance variable memory devices are phase-change random access memories (PCRAMs), resistance RAMs (ReRAMs), and magentoresistive RAMs (MRAMs).
Each of the resistance variable memory devices may be formed of a switching device and a resistance device and store data “0” or “1” according to a state of the resistance device.
Even in the variable resistive memory devices, the first priority is to improve integration density and to integrate memory cells in a limited and small area as many as possible.
Currently, methods of forming resistance variable memory devices in 3D structures are suggested, and demands on methods of stably stacking a plurality of memory cells with a narrow critical dimension are growing.
As a manufacturing method of a typical 3D structure resistance variable memory device, there is a method of manufacturing a switching device using a vertical pillar. However, the method of manufacturing a switching device using the vertical pillar may have a concern in that a fabrication process of the switching device is complex, and an aspect ratio is increased due to a height of the vertical pillar.
To overcome this concern of the 3D vertical pillar structure, a 3D horizontal channel structure is proposed. The 3D horizontal channel structure is a structure in which an active region having a horizontal channel is supported by a common source region unlike an existing buried type.
However, a manufacturing process of the 3D horizontal channel semiconductor device may be accompanied with a process of aligning a channel of the active region with the common source node, and a process of aligning a gate (a word line) with the channel of the active region. Therefore, a process defect such as misalignment may occur in the manufacturing process.
USPTO Backgrounds
USPTO Backgrounds