The present invention relates generally to analog-to-digital code converters and in particular to such code converters implemented by means of charge coupled device technology.
An analog-to-digital converter encodes an analog signal, S, as a sum of powers of 1/2: ##EQU1## WHERE B.sub.N 'S ARE 1 OR 0, AND THE FULL SCALE REFERENCE IS TAKEN TO BE 1.0. The conventional successive approximation algorithm for determining the b.sub.n 's is to compare S with ##EQU2## FOR THE KTH BIT CONVERSION. If S exceeds R.sub.k, b.sub.k =1 and if S is less than R.sub.k, b.sub.k =0. The k+l reference then becomes: ##EQU3## WHERE A SUBTRACTION IS INVOLVED. (B.sub.K, 0, 1 FOR B.sub.K =1, 0 RESPECTIVELY).
Stating the above nonmathematically, the signal S is progressively compared with ##EQU4## As soon as R exceeds S, the last added fraction (1/8) must be subtracted and the next in the series of (1/2.sup.n) (e.g. 1/16) added. The approximations then continue by successively adding progressively smaller members of the series (1/2.sup.n) to R until it again exceeds S, at which time the member of the series (say 1/32) which caused R to exceed S is subtracted from R and, prior to the next comparison, the next member in the series (1/64) is added to R. The process continues through a series of approximations depending in number on the desired precision of the system.
Charge subtraction is not as readily performed in charge coupled devices as is the addition of charge. The only known prior attempt to perform analog-to-digital conversion by means of a CCD device without using charge subtraction is that described in U.S. Pat. No. 3,930,255. It involves a succession of stages for performing respective ones of the successive approximations, resulting in a larger than desirable device.
It is therefore an object of the present invention to create an improved analog-to-digital converter which is particularly suitable for CCD implementation, resulting in a high speed, and highly compact, device.
A further object of the present invention is to provide a CCD analog-to-digital converter wherein charge is always added between successive approximations.
A related object of the present invention is to provide a method of analog-to-digital conversion through successive approximation which permits a signal to be successively compared with a progressively greater reference without requiring the reference to be reduced as a result of exceeding the signal.
These and other objects of the invention are attained through a method for converting an analog signal into its binary equivalent comprising the following steps:
(1) store at a reference input location in a semiconductor charge storage medium a charge proportional to a reference signal; PA1 (2) transfer half of the charge which is at the reference input location to a reference sensing location in the charge storage medium and store at a signal sensing location in the medium a charge proportional to the analog signal; PA1 (3) compare the charges stored at the signal sensing and reference sensing locations and register the results of the comparison; PA1 (4) if the charge at the signal sensing location exceeds the charge at the reference sensing location, transfer half of the charge remaining at the reference input location to the signal sensing location; if not, transfer half of the charge remaining at the reference input location to the reference sensing location; and PA1 (5) repeat the last two of the above steps a predetermined number of times.
Implemented as an analog-to-digital converter, the present invention may be characterized by a combination which includes means for generating a reference charge Q.sub.R and an analog signal charge Q.sub.S. During successive iterations a fractional reference charge (Q.sub.R /2.sup.n) is progressively derived by charge splitting means from the reference charge Q.sub.R. First and second charge summing means are provided, the first of them receiving the charge Q.sub.S. The fractional reference (Q.sub.R /2.sup.n) is entered into a selected one of the first and second charge summing means in response to a control signal which may have either a first or a second state representative of the relative magnitudes of the charges in the first and second charge summing means. This control signal is generated by a circuit which compares, and responds to, the contents of the first and second summing means. The means which respond to the control signal is operative to enter the fractional reference charge (Q.sub.R /2.sup.n) into that one of the first and second charge summing means whose stored charge is indicated to be the lesser by the control signal generating circuit.
By virtue of the invention as described briefly above, each step of the successive approximation process used to generate the binary equivalent of a signal involves the addition of a charge either to the signal or to the reference with which it is compared. Consequently, the successive approximations progress through a series of steps during which one or the other of the compared quantities is increased, this being in contrast to the conventional method of successive approximation during which only one of two compared quantities is changed, either by adding to it or subtracting from it, depending upon whether it exceeds or falls short of the signal with which it is compared.
USPTO Backgrounds
USPTO Backgrounds