1. Technical Field
The present subject matter relates generally to integrated circuits (ICs). More particularly, the present subject matter relates to an interconnect protocol for use in an IC package comprising at least two stacked dies.
2. Background Information
In some applications, it is desirable to include more than one semiconductor die in a single semiconductor package. For example, two dies can be stacked in a single package. As such, one die resides on top of another die. One or more issues arise regarding the interconnection protocol between stacked dies. If the dies have different “footprints” (i.e., are of different sizes), electrically interconnecting the dies may be problematic. In general, the electrical connectivity to/from a die is generally from “pins” formed or attached to the sides of the die. If the die has four sides (most dies are rectangular and thus have four sides), then all four sides of the die may be used for interconnection pins. Pins of one die can be connected to a corresponding pin of another die if the sides of the dies align vertically. For example, if two stacked dies have the same footprint, then the four sides of the dies are in vertical align and the pins on all four sides of each die can be connected with pins of the other die. However, if the dies have different footprints, then, in general, the dies can be stacked only in such a way that one or two sides (not all four) of the dies vertically align. In this case, only the one or two aligned sides can be used for die-to-die interconnection pins. As a result, fewer pins are available to interconnect stacked dies of different sizes than stacked dies of the same size.
Despite different size stacked dies being inter-connectable with fewer pins than same size stacked dies, it still may be desirable for the smaller die to have shared access to resources coupled to the larger die. These resources may have a large number of signals, well in excess of the number of interconnect pins available to the smaller die. Further, it may be desirable to share such resources without causing substantially higher power consumption of the system despite the desire for higher performance and lower latency in the face of fewer interconnecting pins.
USPTO Backgrounds
USPTO Backgrounds