This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-288329, filed Sep. 22, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device comprising a voltage boosting circuit for boosting the power supply voltage, particularly, to a semiconductor device comprising a voltage boosting circuit that is boost-driven by a plurality of phase shifted clock signals generated from an oscillation circuit, the semiconductor device being used in, for example, a semiconductor memory device in which a high voltage used in erasing, writing and reading data in and from the memory cell is generated from a voltage boosting circuit.
2. Description of the Related Art
FIG. 1 is a cross sectional view showing the construction of one memory cell included in a flash memory, which is one of semiconductor memory devices. As shown in FIG. 1, an N-well 2 is formed in a P-type semiconductor substrate 1. Further, a P-well 3 is formed in the N-well 2. Source and drain regions 4, 5 each consisting of an N+ region are formed apart from each other in the P-well 3. A floating gate 6 is formed on the channel region between the source and drain regions 4 and 5 with an insulating film (not shown) interposed between the floating gate 6 and the channel region. Further, a control gate 7 is formed on the floating gate 6 with an insulating film (not shown) interposed therebetween.
A contact region 8 consisting of a P+ region is formed on the P-type semiconductor substrate 1. A contact region 9 consisting of an N+ region is formed in the N-well 2. Further, a contact region 10 consisting of a P+ region is formed in the P-well 3.
During the operation, a gate voltage Vg is supplied to the control gate 7 of the memory cell, a drain voltage Vd is supplied to the drain region 5, and a source voltage Vs is supplied to the source region 4. Also, a voltage equal to the source voltage Vs is supplied to each of the contact regions 9 and 10, and a ground voltage of 0V is supplied to the contact region 8.
The memory cell shown in FIG. 1 stores xe2x80x9c1xe2x80x9d level and xe2x80x9c0xe2x80x9d level of the data depending on the amount of electrons stored in the floating gate 6. Also, the threshold voltage as viewed from the control gate 7 is changed in accordance with the level of the stored data. A memory cell array is formed by arranging a plurality of memory cells of the particular construction.
FIG. 2 exemplifies a circuit of a memory cell array of a NOR type flash memory. A plurality of memory cells MC are arranged in rows and columns. The control gates of the memory cells MC arranged in the same row are commonly connected to the corresponding single word line selected from a plurality of word lines WL0 to WLn. Also, the drain regions of the memory cells MC arranged in the same column are commonly connected to the corresponding single bit line selected from a plurality of bit lines BL0 to BLm. In general, the memory cell is divided into a plurality of blocks, and the source regions of the memory cells MC in the same block are commonly connected to the source line of the corresponding block selected from a plurality of source lines SLi.
FIG. 3 is a graph showing the relationship between the gate voltage supplied to the control gate of the memory cell during operation of the flash memory shown in FIG. 2 and the drain current flowing into the drain region of the memory cell during operation of the flash memory shown in FIG. 2. In this case, the state that a relatively large amount of electrons are stored in the floating gate, i.e., the state that the threshold voltage Vth of the memory cell is high, represents xe2x80x9c0xe2x80x9d data, and the memory cell storing the xe2x80x9c0xe2x80x9d data is called xe2x80x9c0xe2x80x9d cell. On the other hand, the state that a relatively small amount of electrons are stored in the floating gate, i.e., the state that the threshold voltage Vth is low, represents xe2x80x9c1xe2x80x9d data, and the memory cell storing the xe2x80x9c1xe2x80x9d data is called xe2x80x9c1xe2x80x9d cell.
FIG. 4 exemplifies the values (bias conditions) of the gate voltage Vg, the drain voltage Vd and the source voltage Vs supplied to the memory cell during operation, i.e., during reading, writing and erasing of data, of the flash memory shown in FIG. 2.
When data is read, the gate voltage Vg, the drain voltage Vd and the source voltage Vs are set at 5V, 1V and 0V, respectively. During the data writing (during the programming), the gate voltage Vg and the source voltage Vs are set at 9V and 0V, respectively. On the other hand, the drain voltage Vd is set at 5V when it comes to the memory cell in which the xe2x80x9c0xe2x80x9d data is written, and is set at 0V when it comes to the other memory cell, i.e., the memory cell in which the original xe2x80x9c1xe2x80x9d data is stored. Further, in the erasing step, the gate voltage Vg and the source voltage Vs are set at xe2x88x927V and 10V, respectively, and the drain voltage Vd is put in the floating state.
The reading of data is judged depending on the state as to whether or not a cell current flows at the time when a gate voltage Vread (5V in this case) is supplied to the control gate under the state that a predetermined voltage (1V in this case) is supplied to the drain region. The judgment is performed by the comparison with the reference current Iref flowing into the reference cell, the comparison being performed by a sense amplifier (not shown).
The erasure is collectively performed in a plurality of memory cells sharing the P-well 3 shown in FIG. 1. In the erasing step, electrons flow from the floating gate 6 into the P-well region 3 by the Fowler-Nordheim (Fxc2x7N) tunneling phenomenon, with the result that all the memory cells to be erased are put in the conditions of xe2x80x9c1xe2x80x9d cell.
The writing is performed for each memory cell. The bit line of the memory cell in which the xe2x80x9c0xe2x80x9d data is written is biased to 5V so as to inject the high energy electrons generated by the channel hot electron phenomenon into the floating gate 6. In this case, the bit line of the xe2x80x9c1xe2x80x9d cell, in which the original xe2x80x9c1xe2x80x9d data is desired to be maintained, is set at 0V. As a result, the electron injection into the floating gate 6 does not take place in the memory cell in which the data is not written, with the result that the threshold voltage Vth is not changed.
Also, a write verify operation and an erase verify operation are performed in the flash memory in the writing step and the erasing step in order to confirm the degree of writing and erasing. In the write verify operation, the voltage of the control gate 7 is set at a high voltage Vpv, e.g., 7V, compared with the voltage Vread in the reading step (5V in this case), so as to perform the xe2x80x9c0xe2x80x9d read operation. The write operation and the write verify operation are alternately performed repeatedly, and the write operation is finished when all the data of the memory cells in which the data is written have become xe2x80x9c0xe2x80x9d.
In the erasing step, the voltage of the control gate 7 is set at a voltage Vev, e.g., 3.5V, which is lower than the voltage Vread in the reading step, so as to perform the xe2x80x9c1xe2x80x9d read operation. The erase operation and the erase verify operation are alternately performed repeatedly, and the erase operation is finished when all the data of the memory cells to be erased have become xe2x80x9c1xe2x80x9d. As a result, the cell current Icell is secured sufficiently.
As described above, the voltage supplied to the control gate of the memory cell is changed variously in accordance with the operation mode. For example, the voltage noted above is changed to 9V, 7V, 5V, and 3.5V. The voltages of 9V, 7V and 5V are higher than the power supply voltage supplied from the outside.
In order to form various voltages such as 9V, 7V and 5V, which are higher than the power supply voltage supplied from the outside, a required number of boosting circuits for boosting the power supply voltage are arranged, and the outputs of these plural boosting circuits are selected appropriately by a switch so as to be supplied to the control gate of the memory cell.
A boosting circuit for boosting the power supply voltage is used in a memory for reading and rewriting the data by forming various voltages higher than the power supply voltage supplied from the outside within the chip such as the flash memory described above.
FIG. 5 exemplifies the construction of the system of the conventional boost voltage generation circuit, and FIG. 6 shows the wave forms of the main signals or voltage for describing the operation of the boost voltage generation circuit shown in FIG. 5.
The construction of the boost voltage generating circuit shown in FIG. 5 is known to the art. Specifically, as shown in FIG. 5, the boost voltage generating circuit comprises an oscillation circuit (OSC) 11, a plurality of boost circuits, e.g., four boosting circuits (PUMP) 12 to 15 each using a charge pump circuit, and a voltage detection circuit (DETECT) 16, which are electrically connected to each other.
The oscillation circuit 11 is formed of, for example, a ring oscillation circuit constructed as shown in FIG. 7. The oscillation/oscillation-stop of the oscillation circuit 11 is controlled in accordance with the logic level of the input of the oscillation activation signal (OSCE) such that the oscillation circuit 11 is oscillated during the xe2x80x9cHxe2x80x9d period of the OSCE so as to form four phase shifted clock signals CLK0 to CLK3, which are supplied to the boosting circuits 12 to 15.
As shown in, for example, FIG. 8, each of the boosting circuits 12 to 15 comprises two systems of a charge pump circuit in which a plurality of sets of an NMOS transistor Q of an I-type (intrinsic type: Vth being close to 0V) and a capacitor C are connected to each other, and the output nodes of these two systems of the charge pump circuits are connected to each other. In this case, a driving clock DRV input is supplied to one system of the charge pump circuit through an inverter IV1 so as to boost-drive the particular system of the charge pump circuit, with the result that a voltage formed by boosting the power supply voltage Vcc is outputted to the output node OUT. On the other hand, a driving clock DRV input is supplied to the other system of the charge pump circuit through two stage inverters IC2, IV3 so as to boost-drive the other system of the charge pump circuit, with the result that a voltage formed by boosting the power supply voltage is outputted to the output node OUT.
The voltage detection circuit 16 comprises a level shift circuit 17, a voltage dividing resistor circuit 18, and a voltage comparing circuit 100, which are electrically connected to each other, as shown in, for example, FIG. 9. The voltage detection circuit 16 of the particular construction detects whether the dividing voltage Vdiv of the boosted voltage VPP is higher or lower than the reference voltage Vref during the xe2x80x9cHxe2x80x9d period of the voltage boost activation signal (VPPE) so as to set the oscillation activation signal OSCE output at xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d in accordance with the result of the detection.
The level shift circuit 17 comprises PMOS transistors QP1, QP2 having the sources connected to the boosted voltage VPP, NMOS transistors QN1, QN2 connected between the drains of the transistors QP1, QP2 and the ground node, an inverter IV4 supplied with the voltage boost activation signal VPPE and inverting the supplied voltage boost activation signal VPPE so as to supply the inverted signal to the gate of the transistor QN1, and an inverter IV5 for inverting the output of the inverter IV4 so as to supply the inverted signal to the gate of the transistor QN2.
The voltage dividing resistor circuit 18 comprises a PMOS transistor QP3 having the source connected to the boosted voltage VPP and supplying the output of the level shift circuit 17 to the gate, voltage dividing two resistors R1, R2 connected in series between the drain of the transistor QP3 and the ground node, and an NMOS transistor QN3 for the activation control for supplying the voltage boost activation signal VPPE to the gate.
The voltage comparing circuit 100 compares the divided voltage Vd divided by the resistors R1, R2 of the voltage dividing resistor circuit 18 with the reference voltage Vref so as to generate the oscillation activation signal OSCE.
The operation of the boost voltage generating circuit of the construction described above will now be described.
If the boost activation signal VPPE input becomes xe2x80x9cHxe2x80x9d in the voltage detection circuit 16, the output of the inverter IV4 becomes xe2x80x9cLxe2x80x9d, the output of the inverter IV5 becomes xe2x80x9cHxe2x80x9d, and the output of the level shift circuit 17 becomes xe2x80x9cLxe2x80x9d. As a result, the PMOS transistor QP3 is turned on, the boost voltage VPP is divided by the two resistors R1, R2, and the divided voltage Vdiv is compared with the reference voltage Vref by the voltage comparing circuit 100. Since the value of the boost voltage VPP is low immediately after operation of the boosting circuits 12 to 15, the relationship of Vref greater than Vdiv is established so as to allow the oscillation activation signal OSCE, which is the output of the voltage comparing circuit 100, to become xe2x80x9cHxe2x80x9d.
If the oscillation activation signal OSCE becomes xe2x80x9cHxe2x80x9d, the oscillation circuit 11 performs the oscillating operation so as to form phase shifted clock signals CLK0 to CLK3. The clock signal CLK0 to CLK3 thus formed are supplied as the driving clock DRV to the four voltage boosting circuits 12 to 15 to allow these voltage boosting circuits 12 to 15 to perform the voltage boosting operation, and the voltages of the output nodes of these voltage boosting circuits 12 to 15 are combined so as to form the boosted voltage VPP. In this case, since the voltage boosting operations of these four voltage boosting circuits 12 to 15 are controlled by the phase shifted clock signals CLK0 to CLK3, it is possible to suppress the peak current of the entire system.
If the boosted voltage VPP is inputted and the time when the boosted voltage VPP is rendered higher than the reference value during the period xe2x80x9cHxe2x80x9d of the boost activation signal VPPE (Vref less than Vdiv) is detected, the voltage detection circuit 16 sets the oscillation activation signal OSCE at xe2x80x9cLxe2x80x9d, stops the oscillation of the ring oscillation circuit 11 and stops the voltage boosting operation of the voltage boosting circuits 12 to 15.
If the boosted voltage VPP is rendered lower than the reference value under this state, the oscillation activation signal OSCE is set again at xe2x80x9cHxe2x80x9d and the oscillating operation is started again so as to start again the charge transfer operation in the voltage boosting circuits 12 to 15. The particular operation is repeated during the period xe2x80x9cHxe2x80x9d of the voltage boost activation signal VPPE so as to output the boosted voltage VPP.
However, in the conventional ring oscillation circuit 11 shown in FIG. 7, the clock signals CLK0 to CLK3 are not stopped immediately after the oscillation activation signal OSCE is set at xe2x80x9cLxe2x80x9d, and the ring oscillation circuit 11 is stopped after operated until the clock signal CLK3 is outputted. Therefore, even if the reference value of the boosted voltage VPP is set at VPP2 as shown in FIG. 6, the clock signals CLK0 to CLK3 continue to be generated even after the level of the reference value VPP2 is detected by the voltage detection circuit 16. It follows that the boosted voltage VPP is actually boosted to the level of the reference-over value VPP1 ( greater than VPP2).
In this case, the output current of the voltage boosting circuits 12 to 15 during the one clock operation is increased with increase in the power supply voltage Vcc of the voltage boosting circuits 12 to 15. In other words, the level of the reference-over value VPP1 is dependent on the power supply voltage Vcc such that the level of VPP1 is increased with increase in the power supply voltage Vcc. On the other hand, it is desirable for the boosted voltage VPP to be low in its dependence on the power supply voltage Vcc. Therefore, the dependence of the boosted voltage VPP on the power supply voltage Vcc is of high importance in, particularly, guaranteeing the operation over a wide range of the power supply voltage Vcc.
As described above, the conventional voltage boosting circuit is driven by a plurality of phase shifted clock signals generated during the period when the oscillation circuit is activated. The conventional voltage boosting circuit of the particular construction continues to perform its voltage boosting operation for some period, which is derived from the inputting of the clock signal, even after the voltage detection circuit detects that the boosted voltage reaches the reference value so as to inactivate the oscillation activation signal. As a result, the output current of the voltage boosting circuit is increased so as to give rise to the problem that the dependence of the boosted voltage VPP on the power supply voltage Vcc is increased.
According to one embodiment of the present invention, there is provided a semiconductor device, comprising an oscillator configured to output a plurality of phase shifted clocks; a voltage boosting circuit configured to input a plurality of driving clocks and outputting a boosted voltage higher than a power supply voltage; a voltage detection circuit configured to detect whether the boosted voltage is higher than a predetermined voltage or not and to output a detection signal, wherein the detection signal is in a first logic state when the boosted voltage is lower than the predetermined voltage and the detection signal is in a second logic state when the boosted voltage is higher than the predetermined voltage; and a clock signal control circuit configured to input a plurality of the phase shifted clocks and the detection signal, and to output a plurality of the driving clocks, wherein the clock signal control circuit transfers a plurality of the phase shifted clocks to output a plurality of the driving clocks when the detection signal is in the first logic state, the clock signal control circuit stops transferring a plurality of the phase shifted clocks when the detection signal changes from the first logic state to the second logic state, the clock signal control circuit holds the first and second logic states of a plurality of the driving clocks when the detection signal is in the second logic state, and the clock signal control circuit restarts transferring one of a plurality of the phase shifted clocks to output the corresponding one of the plurality of driving clocks when the logic state of one of a plurality of the phase shifted clocks is identical to the first logic state or the second logic state of the corresponding one of a plurality of the driving clocks after the detection signal changes from the second logic state to the first logic state.
USPTO Backgrounds
USPTO Backgrounds