Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Multicore processors have emerged as a mainstream computing platform in major market segments. As the number of processor cores on a given multicore processor increase, so too does the potential demand on that multicore processor's local memory. When the processor executes an instruction, for example, the processor first looks at its on-chip cache to find the data associated with that instruction to avoid performing a more time-consuming search for the data elsewhere (e.g., off-chip or on a main memory chip).
The present disclosure contemplates that systems with multiple cores may be required to handle multiple incoming application streams that may interfere with each other while seeking shared cache space. These multiple incoming application streams may cause a shared cache in the multicore processor system to operate inefficiently, resulting in poor overall performance. Conflict among processor cores for the use of a shared cache can be expensive in terms of both latency and power as a result of additional requests to off-chip memory. Other factors relating to multiple cores can also reduce efficiency.
The present disclosure also contemplates that multicore processors may experience both higher cache miss rates and much higher penalties for cache misses. Further, as core counts improve bus congestion and cache miss penalties may rise at exponential rates. Cache calls, data exchange, and I/O may all be impacted in cases where cache-misses or other events lead to bus congestion that may further degrade performance.
USPTO Backgrounds
USPTO Backgrounds