This invention pertains to the field of semiconductor devices, and in particular, pertains to a method for coupling to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors.
Manufacturers of semiconductor memory devices continually strive to reduce the size of individual memory cells. By reducing the size of individual memory cells, faster and higher capacity memory devices can be constructed. Conventional memory cells typically comprise a substrate, a transistor formed in the substrate, a storage capacitor coupled to the transistor, and a word line and a bit line for accessing the memory cell. One limiting factor in reducing the size of the memory cell is the size of the access lines of the memory device. In order to resolve this limitation, manufacturers have developed memory devices with word line conductors that extend normal to the substrate. Furthermore, the word lines are narrower than the gate regions of the transistors to which they are coupled. This type of word line is known in the art as an edge-defined word line.
The typical fabrication process of semiconductor memory device comprises a series of lithographic steps where material is either deposited on the device or removed from the device. The minimum dimension of the material which can be deposited or removed is known in the art as the minimum lithographic dimension. In a further attempt to reduce the size of a memory cell, manufacturers have developed word lines which are narrower than the minimum lithographic dimension. The development of sub-lithographic word lines which extend normal to the surface of the substrate has eliminated the size of a word line as a limiting factor in the reduction of the memory cell size. The development, however, has introduced complexities in the other areas of the memory cell.
Traditionally, there are two ways of implementing the capacitor region of a memory cell. A memory cell may contain a trench capacitor or a stacked capacitor. A trench capacitor is formed by etching a hole in the substrate. The storage electrode of the trench capacitor is inside the hole and the plate electrode is the substrate. Because a trench capacitor is located in the substrate of the semiconductor device, it is formed before the word lines of the memory device are formed. Thus, with a trench capacitor, the semiconductor manufacturer can easily form edge-defined word lines on top of the substrate and the trench capacitor.
Trench capacitors have several disadvantages. One disadvantage is the difficulty of fabricating them without introducing silicon crystal defects which result in leakage currents from the storage nodes. In contrast, stacked capacitor are formed on top of the cell transistor and therefore do not significantly affect leakage currents within the silicon. Because of their location, however, spacial interference with the cell wiring may limit the fraction of the cell area available for the capacitor.
For the above reasons, it is advantageous to build the storage capacitor of a memory cell on a plane above that of the wiring and to provide a method to connect the stacked capacitor, located above the sub-lithographic word lines, to the transistor, located, below the sub-lithographic word lines. The present invention allows the active regions of the substrate to be accessed through and above the complex, sub-lithographic word lines so that the active regions can be connected to a semiconductor device, such as a stacked capacitor, which is formed outwardly from the word lines.
One aspect of the invention is a method for forming an integrated circuit using a lithographic process having a minimum lithographic dimension. The method comprises the steps of forming a semiconductor device in a semiconductor substrate, forming a first conductor outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension, forming a second conductor outwardly from the semiconductor device, the second conductor adjacent to the first conductor, and coupling a circuit component to the semiconductor device by the second conductor.
According to another feature of the invention, the step of coupling a circuit component to the semiconductor comprises the step of coupling a storage capacitor to the semiconductor and the step of forming a semiconductor device comprises the step of forming a transistor for accessing the storage capacitor.
According to another feature of the invention, the step of forming a first conductor comprises the step of forming a word line for activating the transistor.
According to another feature of the invention, the second conductor is aligned with the circuit component by using a single mask image.
According to another feature of the invention, the second conductor is bounded by the first conductor.
Another aspect of the invention is a method for forming a semiconductor memory device using a lithographic process having a minimum lithographic dimension. The method comprising the steps of forming a transistor in a semiconductor substrate, forming a word line outwardly from the transistor, the word line having a width less than the minimum lithographic dimension, the word line for activating the transistor, forming a bit line and a conductor outwardly from the transistor that couple to the transistor, said bit line and said conductor adjacent to the word line, and forming a storage capacitor outwardly from the bit line and the conductor, said storage capacitor coupled to the transistor by the conductor.
Another aspect of the invention is a method for forming two memory cells having a shared bit line using a lithographic process having a minimum lithographic dimension. The method comprising the steps of forming two transistors in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate extending outwardly from the semiconductor substrate, forming two word lines outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor for activating the transistor, forming a bit line and two conductors outwardly from the transistors that couple to the transistor, the bit line coupled to the shared drain of the transistors, each conductor coupled to a source of a different transistor, the bit line and the conductors adjacent to the word line, and forming two storage capacitors outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor.
Another aspect of the invention is an integrated circuit formed using a lithographic process having a minimum lithographic dimension. The integrated circuit comprising a semiconductor device formed in a semiconductor substrate, a first conductor formed outwardly from the first semiconductor device, the first conductor having a width less than the minimum lithographic dimension, a second conductor formed outwardly from the first semiconductor device, the second conductor adjacent to the first conductor, and a circuit element coupled to the semiconductor device by the second conductor.
Another aspect of the present invention is a memory device formed by a lithographic process having a minimum lithographic dimension. The memory device comprising a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate, a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor, a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines, and a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor.
Another aspect of the invention is a pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension. The pair of memory cells comprising two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate, two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors, a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the two conductors adjacent to the word line, and two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors.
USPTO Backgrounds
USPTO Backgrounds