The disclosed subject matter relates generally to memory systems, and, more particularly, to reducing power consumption of a memory system.
Memory in a processor system commonly includes a temporary storage system that includes both dynamic random access memory (DRAM) and one or more caches formed from static random access memory (SRAM). Generally, DRAM is relatively inexpensive, and thus, is commonly employed in large blocks to store large volumes of data, but is relatively slow when retrieving the data. Caches, on the other hand, are constructed from high-speed SRAM cells that are substantially faster than DRAM, but are relatively more expensive.
Many processor systems employ a relatively small cache and a relatively large DRAM. Commonly, this type of processor system is designed such that the cache is loaded with a subset of the data found in the DRAM that is likely to be used by the processor system. Thus, the processor system normally accesses the high-speed cache, and only occasionally accesses the lower-speed DRAM. By carefully selecting the subset of data loaded into the cache, the processor system can operate at a relatively high speed without the expensive of including a large block of high-speed cache.
Since the cache is holding only a subset of the data that may be accessed by the processor system, “misses” will occasionally occur when the processor system requests data that has not been loaded into the cache. When such a miss occurs, the memory system will access DRAM to retrieve the desired data, and the retrieved data will be loaded or “filled” into the cache. Of course, if the cache is full, then the cache will need to eject or otherwise remove some old data from the cache to make room for the newly retrieved data.
In some applications, caches generally treat all data fills the same way: store the new data in a most recently used (MRU) location in the cache because the new data is assumed to be “useful,” in that it will be accessed or “touched” again. The general presumption that all data, because it have been touched once will be touched again in the near future, has been extremely useful in the past and generated good performance benefits, and the pain of being wrong has been generally bearable. Thus, caches have typically erred on the side of caution and the set of data in a cache generally significantly exceeds the set of data that will be touched again. However, increasing pressure on caches from multiple directions makes it increasingly important to be able to use cache space more efficiently by having its space taken up by more useful data, i.e. data that will be reused.
USPTO Backgrounds
USPTO Backgrounds