The present invention relates to a programmable function block that is a logic unit for logic devices for implementing various functions with programs.
Logic devices such as PLDs or field programmable gate arrays (FPGAs) have been developed rapidly in recent years that can provide various functions with programs. By improvement in degree of integration and speed, it is expected to use the logic devices for reconfigurable computer systems with different hardware design depending on application programs used, not only for emulation in designing conventional application specific integrated circuits (ASICs) or as a mere alternative to simple peripheral circuits. In the conventional PLDs or FPGAs, a programmable function block comprises the circuit combined with multiplexers or comprises a look-up table (LUT) for implementing a plurality of functions. The programmable function block with the multiplexers or the look-up table provides lower performance in arithmetic operation that is frequently used in computers. On the other hand, arithmetic logic units (ALUs) based on a full adder, which are typically used for conventional general-purpose processors, provide good arithmetic operation performance but less functions as a logic circuit. Accordingly, the conventional ALUs are not suitable for the programmable function block in the PLDs or FPGAs.
USPTO Backgrounds
USPTO Backgrounds