1. Field of the Invention
This invention relates generally to the field of circuits for controlling the duty cycles of signals and, in particular, circuits for providing a signal with a 50 percent duty cycle from a signal with an arbitrary duty cycle.
2. Background Art
A number of parameters may be used to describe the characteristics of an electrical signal. These include voltage, amplitude, frequency, period, duty cycle, on-time and off-time. Duty cycle is particularly relevant to signals having a digital or rectangular waveform. Digital or rectangular waveforms alternate between a low level and a high level, with the transition between levels occurring substantially instantaneously. The term "period" refers to the duration of a single cycle. For each cycle, a digital or rectangular waveform remains at the low level for a portion of the period and at the high level for the remainder of the period. "On time" refers to the amount of time spent at the high level, while "off time" refers to the amount of time spent at the low level. "Duty cycle" refers to the ratio of on time to period, and is often specified as a percentage. A signal may have a duty cycle from zero to 100 percent. In some cases, the duty cycle of a signal may be unpredictable. To make the characteristics of a signal more predictable, it is often desirable to adjust the duty cycle of the signal to be a known value, e.g. 50 percent. A 50 percent duty cycle provides equal on time and off time.
In the past, methods for controlling duty cycles have required a closed loop circuit. One circuit of the prior art is described in U.S. Patent No. 4,479,216, issued to Krambeck, et al. Krambeck describes a circuit in which the average voltage of a clock out pulse is compared to a reference voltage to produce a control signal which is fed back to adjust the timing of the clock out pulses.
Another method used for controlling the duty cycle of a signal is described in U.S. Pat. No. 4,277,697 issued to Hall, et al. Hall, et al. describes a circuit in which a generator initiates a rectangular output signal in synchronism with the input signal. A comparator compares the relative amplitudes of the output signal and another reference voltage to produce a signal which is fed back to the generator to terminate the output signal after the appropriate on time needed to produce the desired duty cycle.
Both of these methods rely on circuits of the closed loop type and require that a signal be fed back to control the output signal. Closed loop circuits must be designed carefully to avoid instability, which is inherent in such circuits. Also, some of the prior art circuits require components which are difficult or costly to fabricate as an integrated circuit. Additionally, some of the prior art circuits are difficult to adjust to achieve a 50 percent duty cycle.
USPTO Backgrounds
USPTO Backgrounds