As the physical dimensions of semiconductor devices continue to decrease, these ever smaller dimensions pose new challenges which must be overcome in order to make the devices functional. In the field of MOSFETs (metallic oxide semiconductor field effect transistors), the decrease in size, and the commensurate decrease in operating current, have resulted in current leakage when the transistor is in its off state. This leakage is often attributed to the formation of parasitic features which are formed in the substrate beneath the gate of the FET. Generally, such parasitic features create alternate and undesirable pathways for current flow. These parasitic features may be caused by imperfections or physical limitations inherent in the fabrication process. In conventional planar CMOS technology wherein FETs are formed on a bulk substrate, parasitic features often form in the channel between the source and drain and beneath the gate at certain depths where the gate field is no longer effective.
One approach known to the art for compensating for the current leakage problem in planar FETs is through the provision of a second gate disposed beneath the channel region. In such dual gate FETs, the second gate provides a lower boundary for the channel, and also provides a second field for regulating the current flow through the channel region.
While dual gate MOSFETs have certain advantages over single gate MOSFETs, they also have some notable drawbacks. In particular, the formation of a lower gate is challenging from a fabrication standpoint, and it is also difficult to properly align the two gates with each other.
The aforementioned difficulties have led to the development of FinFETs, an example of which is depicted in FIGS. 1-2. As seen therein, a FinFET 10 is essentially a dual gate MOSFET in which the gates 46 of the device are formed vertically rather than horizontally, and in which the channel regions 42 are disposed within a series of vertical fins 12 which contain source 14 and drain 18 regions on opposing sides thereof. The FinFET 10 is fabricated from an SOI (semiconductor-on-oxide) wafer 22 which contains an SOI layer 34 disposed on a BOX (buried oxide) layer 26 which, in turn, is disposed on a semiconductor substrate 30. The gate 46, source 14 and drain 18 regions are formed in the SOI layer 34.
After fins 12 have been formed, subsequent processing steps include forming a gate oxide (not shown) on fins 12, and forming the gate 46 which is common to both fins 12. After formation of the gate 46, the source 14 and drain 18 regions are doped, as illustrated by arrows 50, to achieve a doping profile 58. Doping is typically accomplished using ion implantation from the front side of the wafer 22, and typically at an angle of about 30 degrees relative to a normal from the wafer 22 so that ions can enter each fin 12 along its entire height without interference from any adjacent fin 12.
As seen in FIG. 1, FinFET 10 avoids the problem encountered with planar CMOS devices of having to form a second gate beneath the channel of the FET. FinFET 10 also overcomes the problem in planar CMOS technology of having to align gates above and below the channel region. Since the fins 12 in a FinFET device are free-standing structures prior to the formation of the gate 46, the portions of the gate 46 on either side of each channel 42 (see FIG. 2) are largely self-aligned as a result of forming the gate 46 perpendicular to the fins 12.
USPTO Backgrounds
USPTO Backgrounds