1. Field of the Invention
The present invention relates to Moving Picture Expert Group-2 (MPEG-2) technology, and more particularly, to a method and device for controlling a System Time Clock (STC) of an MPEG decoder, in which the STC being used as a standard for synchronization during multi-decoding is effectively controlled.
2. Background of the Related Art
Generally, digital video technology is used in various fields, such as computers and home appliances, as well as in communications technology, such as video conferencing and video telephones. Particularly, various apparatuses for recording and reproducing digital video signals, such as digital video cassette recorders and digital video cassettes, adopt MPEG standards of media (such as MPEG-2) for storing digital video signals.
The MPEG standards provide for the transmission of digital information by dividing digital data into packets forming data bit streams, which are multiplexed onto a single data channel. One standard for the multiplexing of bit streams from several audio, video, and/or auxiliary data sources has been developed by the ISO MPEG and set forth in draft form in a document entitled, “Coding of Moving Pictures and Associated Audio” (ISO/IEC JTC1/SC29/WG11N 0801, published on Nov. 13, 1994, by the ISO/IEC Copyright Office, Geneva, Switzerland, hereby incorporated by reference).
Appropriate encoding and decoding are required to ensure proper transmission and reproduction of digital data. When a digital signal is encoded into data packets for transmission as system bit streams, clock reference values which represent values of an encoder counter clocked by a stable clock having a frequency that is proportional to the sampling frequency of the digital signal to be transmitted, are encoded together with the digital signal. Upon receiving digital signals, decoding of the data packets in the digital signal needs to be performed by producing a decoder clock using the clock reference values contained in the data packets. Using a clock recovery system in an MPEG decoder minimizes the differences between an encoder clock and a decoder clock so that the decoder clock is maintained at approximately the same frequency as the encoder clock, allowing proper presentation of digital signals.
According to the MPEG-2 standards, a system bit stream includes a program stream and a transport stream. The program stream is comprised of elementary streams for respective bit columns of video data, audio data and user data. The elementary streams are packeted in Packetized Elementary Streams (PES). Program streams are used in optical discs and multimedia applications having relatively small error rates. Transport streams are used for media, such as broadcasting media, having relatively large error rates.
To decode a system bit stream, an MPEG-2 decoder includes a transport stream decoder and a program stream decoder. A Program Clock Reference (PCR) is used for the transport stream decoder, while a System Clock Reference (SCR) is used for the program stream decoder. The PCR and SCR are used for clock synchronization of a decoder and an input bit stream, and for Presentation Synchronization (PS) of audio and video data. Although the PCR and the SCR are respectively used for different decoders, they have the same function. As such, only the clock timing synchronization aspects of a transport stream decoder using the PCR values in a transport stream will be explained for the sake of brevity.
A related art MPEG-2 decoder having a clock recovery system therein will be described with reference to the accompanying drawings. FIG. 1 is a schematic view of a clock recovery system according to the related art.
As shown in FIG. 1, the related art clock recovery system includes a subtractor 1, a Low Pass Filter (LPF)/gain controller 2, an STC counter 3, and a Voltage Controlled Oscillator (VCO) 4. A PCR extractor (not shown) obtains, from a bit stream received through an input terminal of the MPEG-2 decoder, a PCR value representing a count value generated by an encoder counter when that PCR value was generated. A plurality of PCR values from a plurality of bit streams are obtained by the PCR extractor during the decoding process. Each of the obtained PCR values is provided to both the subtractor 1 and the STC counter 3.
Initially, the first PCR value obtained by the PCR extractor is provided to the STC counter 3. The initial count value of the STC counter 3 is set as the first PCR value extracted by the PCR extractor, and the STC counter 3 counts at an initial system clock frequency obtained from the VCO 4. Thereafter, upon receipt of each subsequent PCR value during the decoding process, the current count value of the STC counter 3 is provided to the subtractor 1.
The subtractor 1 calculates the difference between the PCR value obtained from the PCR extractor and a current STC value received from the STC counter 3, and outputs the results thereof. The LPF/gain controller 2 outputs a control signal to the VCO 4 by low pass filtering the output from the subtractor 1 and controlling the gain thereof. The VCO 4 varies a local clock frequency and then outputs a control signal so that the STC counter 3 counts at a system clock frequency of 27-MHz. The VCO 4 also outputs a 27-MHz decoder clock signal to an output terminal. The above process is repeated accordingly, so that the decoder clock is continuously synchronized with the encoder clock having a frequency of 27-MHz.
FIG. 2 is a schematic view of another clock recovery system according to the related art. The clock recovery system of FIG. 2 includes an STC counter 21, a PCR register 22, an STC register 23, a Pulse Width Modulator (PWM) 24, a Micro-Controller Unit (MCU) 27, an LPF/gain controller 25, and a VCO 26.
The processing involved is similar to that of the related art clock recovery system shown in FIG. 1, except that a PCR value and an STC value at the time when that PCR value is input are both provided to the MCU 27 for calculating the difference between the PCR value and the STC value. Also, the PCR register 22 temporarily stores the PCR values extracted from the PCR extractor, while the STC register 23 temporarily stores the STC values output from the STC counter 21. Instead of a subtractor, the MCU 27 receives and calculates the difference between a PCR value temporarily stored in the PCR register 22 and a STC value temporarily stored in the STC register 23. The PWM 24 generates a PWM signal in response to the difference value calculated by the MCU 27, and outputs a PWM signal to the LPF/gain controller 25.
The LPF/gain controller 25 outputs an analog voltage signal obtained by low pass filtering the PWM signal and controlling the gain thereof, so that the VCO 26 is driven. As the VCO 4 shown in FIG. 1, the VCO 26 varies a local clock frequency and then outputs a control signal so that the STC counter 3 counts at a system clock frequency of 27-MHz. The VCO 26 also outputs the system clock frequency of 27-MHz to an output terminal. The above process is repeated accordingly, so that the decoder clock is continuously synchronized with the encoder clock having a frequency of 27-MHz.
In addition to synchronizing the decoder clock frequency with the encoder clock frequency, audio and video synchronization (e.g., lip synchronization for matching a person's lip movements displayed visually with the person's audible voice to be generated) are also required for proper presentation of digital data to the user. The various aspects of lip synchronization can be understood by considering the transport stream syntax depicted in FIGS. 3 and 4.
FIG. 3 is a diagram of a transport stream syntax according to the related art. The MPEG-2 standard provides for the transmission of digital information from multiple signal sources by dividing the digital data into a number of packets. In the transport stream syntax required by the MPEG-2 standard, as shown in FIG. 3, all audio, video, and auxiliary information are transmitted in packet types. Respectively different Program Identifiers (PIDs) are used in accordance with different types of audio, video, and auxiliary information.
FIG. 4 is a diagram of a PES packet syntax according to the related art. The audio and video information, as shown in FIG. 4, are formed in PES packet types, and transmitted after being transformed into the transport packet types shown in FIG. 3.
Here, problems related to lip synchronization occurs when processing and outputting audio and video data. To solve such problems, the matching of lip synchronization between the PCR in the transport packet header, and a Decode Time Stamp (DTS) and a Presentation Time Stamp (PTS) in the PES header has been proposed in the MPEG-2 standard. The DTS indicates when a picture must be decoded, while a PTS indicates when the picture must be presented to the decoder output.
To achieve lip synchronization, an encoder inserts a counter value being clocked at a clock frequency of 27-MHz into a PCR location of the transport packet header. Also, an encoder counter value being successively increased is inserted into the PES header as a DTS value or PTS value for audio or video data. This type of processing can be referred to as time stamping.
Subsequently, the decoder uses the first received PCR value to set and initialize the STC counter, and the STC counter begins counting at an initial system clock frequency. Thereafter, upon receipt of each subsequent PCR value during the decoding process, the current count value of the STC counter is provided to a subtractor and further processed so that the count value of the STC counter is adjusted. During this process, the DTS value in the PES header is detected, and the detected DTS value is compared with the adjusted STC value. If the compared value is within an acceptable error range, decoding of the received data is performed. Also, when the PTS value in the PES header is detected, the PTS value is compared with the STC value of that time. If the compared value is within an acceptable error range, presentation of the received data is performed. Here, the PCR value consists of a PCR-base value of 33 bits and a PCR-extension value of 9 bits.
However, if a clock signal of 27-MHz used in the decoder is not accurately synchronized with the clock signal in the encoder, problems may occur. For example, if the actual decoder clock frequency is a little slower than an ideal clock frequency of 27-MHz, a buffer empty state may be erroneously achieved when the DTS or PTS detected in the decoder is compared with the STC value, and found to be greater than the acceptable error range, resulting in the erroneous skipping of the DTS or PTS. Conversely, the DTS or PTS compared with the STC may be found to be smaller than the acceptable error range if the actual decoder clock frequency is a little faster than an ideal clock frequency of 27-MHz, and a buffer full state may be erroneously achieved.
The related art clock recovery system of the MPEG-2 decoder suffers from another problem. In a digital television system adapted to the MPEG-2 standard, a maximum of five to six programs can be provided for one broadcasting channel. If the MPEG-2 decoder receives a transmitted broadcasting signal to decode all five or six programs therein, each of the programs has an individual STC, and thus a counter, a low pass filter, subtractor, and a VCO are respectively required for each type of program. This increases the overall complexity and cost of hardware components.
USPTO Backgrounds
USPTO Backgrounds