1. Field of Invention
The present invention relates to a chip package structure. More particularly, the present invention relates to a stack chip package structure.
2. Description of Related Art
As techniques for fabricating a smaller integrated circuit (IC) progresses, the level of integration inside an IC chip also increases. Moreover, the number of transistors inside the IC chip increases and the cross-sectional area of internal conductive lines are reduced. In general, heat is produced in each transistor and conductive line. Hence, a compact IC chip will produce a lot of heat during operation leading to an increase in temperature. As temperature of the IC chip rises to a level above the normal operating temperature, computational errors, temporary malfunction or permanent damages may occur. Therefore, aside from providing suitable output signals via an interface, the IC chip must be physically protected and have good heat dissipation capacity so that the IC is maintained at a suitable operating temperature, and be prevented from exceeding the normal operating temperature range.
For most wire-bonding type of chip packages, a dummy die or a heat conductive metal block is stacked on top of a functional die to serve as a thermal conductive block. In this manner, the thermal impedance along the conductive path of the functional die is lowered. As a result, the heat generated by the chip is rapidly transferred to the outer surface of the chip package and dissipated away to the surrounding air.
FIG. 1 is a schematic cross-sectional view of a conventional stack chip package structure. The package in FIG. 1 has a wire bonding (W/B) chip package structure 100. The chip package structure 100 mainly comprises a carrier 110, a die 120, a thermal conductive block 130, an adhesive layer 140, a plurality of conductive wires 150 and a molding compound 160. The carrier 110 is, for example, a substrate or a lead frame (here, the carrier 110 is a substrate). The carrier 110 has a carrier surface 112 and a plurality of bonding pads 114. The bonding pads 114 are positioned on the carrier surface 112 of the carrier 110. In addition, the die 120 has an active surface 122 and a back surface 124. The back surface 124 of the die 120 is attached to the carrier surface 112 of the carrier 110 via the adhesive layer 142. The die 120 has a plurality of metal pads 126 on the active surface 122. The thermal conductive block 130 is, for example, a dummy die or a metallic block with high thermal conductivity. The thermal conductive block 130 has a bonding surface 132 that attaches to the active surface 122 of the die 120 through another adhesive layer 140. The metallic wires 150 connect each metal pad 126 on the die 120 with a corresponding bonding pad 114 on the carrier 110 electrically. The molding compound 160 encloses the die 120, the thermal conductive block 130 and the conductive wires 150.
As shown in FIG. 1, the thermal conductive block 130 has a rectangular structure, for example. In other words, the bonding surface 132 (or the bottom surface) and a side surface 134 of the thermal conductive block 130 form a right angle (the bonding surface 132 and the side surface 134 form a 90° angle). This often leads to a problem of concentrating stress at the bottom peripheral sections of the thermal conductive block 130. When the chip package 100 is subjected to a thermal stress testing, for example, a temperature cycle test (TCT) or a thermal shock test (TST), repeated heat expansion and cool contraction bends the thermal conductive block 130 and results a stress ring at its bottom peripheral sections that is particularly hard. As a result, a passivation layer (not shown) that covers the actives surface 122 of the die 120 may crack and damage some of the underlying wiring circuits (not shown).
In order to increase the elastic buffer between the die 120 and the thermal conductive block 130, the thickness of the adhesive layer 140 may be increased. However, the thermal impedance of the adhesive material is much greater than the thermal impedance of the thermal conductive block material. Hence, the overall thermal impedance of the die 120 is increased if thickness of the adhesive layer 140 is increased. Therefore, to meet the thermal requirement of a particular package, there must be a maximal limitation for the thickness of the adhesive layer 140. Yet, the adhesive layer 140 may not be too thick to buffer the passivation layer over the die 120 against repetitive stress.
USPTO Backgrounds
USPTO Backgrounds