High-speed networks are continually evolving. The evolution includes a continuing advancement in the operational speed of the networks. The network implementation of choice that has emerged is Ethernet networks physically connected over twisted pair wiring. One of the most prevalent high speed LANs (local area network) for providing connectivity between personal computers, workstations and servers is Ethernet in its 10BASE-T form.
High-speed LAN technologies include 100BASE-T (Fast Ethernet) and 1000BASE-T (Gigabit Ethernet). Fast Ethernet technology has provided a smooth evolution from the 10 megabits per second (Mbps) performance of 10BASE-T to the 100 Mbps performance of 100BASE-T. Gigabit Ethernet provides 1 Gigabit per second (Gbps) data rate with essentially the simplicity of Ethernet. There is a desire to push operating performance to even greater data rates.
Ethernet is the high speed LAN technology of choice. FIG. 1 shows a block diagram of an Ethernet transceiver pair communicating over a bi-directional transmission channel 135, according to the prior art. The transceiver pair includes a first transceiver 100 and a second transceiver 105. The first transceiver 100 includes a transmitter section 110 that receives digital data for transmission over a transmission channel 135. The first transceiver 100 also includes a receiver section 120 that receives analog data.
A hybrid circuit 130 is an electrical bridge circuit that is designed to provide some isolation between a receiver and a transmitter. Without a hybrid circuit 130, the transmitter section 110 and the receiver section 120 are directly connected to a twisted pair of the transmission channel 135. The direct connection between the transmitter and the receiver typically causes at least a portion of transmitter signals to be received by the receiver. The transmitter signal received by the receiver can be referred to as an “echo” signal. The hybrid circuit 130 is designed to mitigate the effects of the echo signal.
The hybrid circuit 140 of the second transceiver 105 operates in the same manner as the hybrid circuit 130 of the first transceiver 100. The transmitter section 150 and the receiver section 160 of the second transceiver 105 operate in the same manner as the transmitter section 110 and receiver section 120 of the first transceiver 100.
An implementation of high speed Ethernet networks includes simultaneous, full bandwidth transmission, in both directions (termed full duplex), within a selected frequency band. When configured to transmit in full duplex mode, Ethernet line cards are generally required to have transmitter and receiver sections of an Ethernet transceiver connected to a common twisted wiring pair.
FIG. 2 shows diagram of a hybrid receiver circuit of a full duplex communication receiver, according to the prior art. The hybrid receiver 200 includes a hybrid circuit 210 that receives a received signal (RX) and a replica signal (REPLICA). The replica signal represents a signal being transmitted (generally, a scaled and processed representation). Additionally, the replica signal can include processed versions of the cross-talk signals. The cross-talk signals generally include far-end cross-talk (FEXT) signals and near-end cross-talk (NEXT) signals. The FEXT and NEXT signals are generally interference signals from neighboring twisted pair connection within an Ethernet bundle. The received signal includes an echo signal, cross-talk signals and a desired receive signal (also referred to as a far end signal). The hybrid is designed to minimize the effects of the echo signal, and the cross-talk signals by subtracting at least a portion of the replica signal from the received signal. Additionally, the hybrid circuit can minimize cross-talk signals.
The analog to digital conversion functionality is generally implemented with sample and hold (S/H) circuit functionality as shown by block 220, and an analog to digital converter (ADC) 230 of FIG. 2. The block 220 can also include a programmable gain adjust. The S/H 220 reduces the bandwidth requirements of electronic circuitry located after the S/H 220. The S/H 220 provides constant sampled and held waveforms that are well behaved. The S/H 220 and the ADC 230 include clock frequencies that are high enough to provide enough resolution to receive the transmitted signals.
It is desirable to have a high data rate transceiver that provides separation of transmit signals from receive signals while operating in full duplex mode.
USPTO Backgrounds
USPTO Backgrounds