1. Technical Field
This invention relates to digital signal processors, and has particular relation to multiply-accumulate (MAC) units.
2. Background Art
Digital Signal Processors (DSPs) are specialized types of microprocessors that are specifically tailored to execute mathematical computations very rapidly. DSPs can be found in a variety of applications including compact disk players, PC disk drives, telecommunication modem banks, and cellular telephones.
In the cellular telephone context, the demand for DSP computation capability continues to grow, driven by the increasing needs of applications such as GPS position location, voice recognition, low-bit rate speech and audio coding, image and video processing, and 3G cellular modem processing. To meet these processing demands, there is a need for improved digital signal processor architectures that can process computations more efficiently.
Considerable work has been done in these areas. Applicant Sih is also an applicant in the following applications for United States patents:
xe2x80x9cMultiple Bus Architecture in a Digital Signal Processorxe2x80x9d, Ser. No. 09/044,087, filed Mar. 18, 1998 now abandoned;
xe2x80x9cDigital Signal Processor Having Multiple Access Registerxe2x80x9d, Ser. No. 09/044,088, filed Mar. 18, 1998 U.S. Pat. No. 6,496,920;
xe2x80x9cMemory Efficient Instruction Storagexe2x80x9d, Ser. No. 09/044,089, filed Mar. 18, 1998 now abandoned;
xe2x80x9cHighly Parallel Variable Length Instructions for Controlling a Digital Signal Processorxe2x80x9d, Ser. No. 09/044,104, filed Mar. 18,1998 now abandoned ;
xe2x80x9cVariable Length Instruction Decoderxe2x80x9d, Ser. No. 09/044,086, filed Mar. 18,1998 now U.S. Pat. No. 6,425,070;
xe2x80x9cDigital Signal Processor with Shiftable Multiply Accumulate Unitxe2x80x9d, Ser. No. 09/044,108, filed Mar. 18,1998 now abandoned.
The disclosure of these applications is incorporated herein by reference.
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture and attaches a dual-MAC coprocessor onto it in a unique way to achieve a significant increase in processing capability.
USPTO Backgrounds
USPTO Backgrounds