Free-angle wiring is based on circular arcs and lines with Euclid distance and can utilize a wiring region more effectively than conventional rectilinear wiring or octilinear wiring. Where semiconductor chips are mounted on a printed-circuit board with high density, free-angle wiring will be very useful if it can be performed at high speed and automatically. A method of perfect free-angle wiring is described, for example, in Shaodi Gao, Mark Jerrum, Michael Kaufman, Kurt Mehlhorn, Wolfgang Rueling, and Christopher Storb, "On continuous homotopic one layer routing," in Proceedings of the 4th annual ACM Symposium on Computational Geometry, pages 392-402, ACM, 1988. However, there is no practical free-angle wiring method.
Techniques for even-spacing and wire-width enlargement are important in order to enhance the yield and the stability in electrical characteristics of pin-grid array (PGA) packages, ball-grid array (BGA) packages, and multi-chip modules (MCMs) in addition to printed-circuit boards which utilize very fine wires. For PGA packages, a method for automatically realizing even-spacing and wire-width enlargement has been reported (in Changsheng Ying and Jun Gu, "Automated pin-grid array package routing on multilayer ceramic substrates," IEEE Transaction on Very Large Scale Integration (VLSI) SYSTEMS, 1(4), pages 571-575, 1993). However, in this method, wires are only line segments which extend radially from the center, there is also a grid-shaped array of pins, which is characteristic of PGA packages. Consequently, this method lacks extensibility. As a matter of course, there is no product which carries out even-spacing and wire-width enlargement by general free-angle wiring.
A general object of the present invention is to provide a practical method and apparatus for routing wires between terminals on a printed circuit-board or other substrate.
Another object of the present invention is to provide a practical free-angle wiring method and apparatus which also enlarges wire spacings and wire widths to fully utilize the available surface area of the board.
USPTO Backgrounds
USPTO Backgrounds