1. Field of the Invention
The present invention relates to a power management architecture scheme in a computer system. More specifically, the present invention relates to power management of DMA slaves through DMA traps.
2. Art Background
It is a becoming a necessity for many companies to use portable and laptop computers. Due to an increased demand for portable and laptop computers, their respective markets are becoming quite profitable and highly competitive. In order for the computer industry to provide a more affordable portable and laptop computer, there exists a crucial need for efficient power management architecture schemes in view of the fact that these computers are generally supplied by limited power sources such as batteries. Thus, power should be conserved wherever possible for reliability and economic reasons.
It is commonly known that most portable and laptop computer systems are based on Industry Standard Architecture ("ISA"), which is basically an IBM PC architecture employing a multi-master bus system which can support several bus slaves, but can only be controlled by one bus master at a time. A bus master is a device which controls a system bus, and initiates bus cycles. A bus slave, such as any input/output ("I/O") device, only receives bus cycles without having a capability of initiating them.
Conventional power management schemes are generally accomplished by monitoring and controlling power to certain I/O devices, such as a keyboard, a floppy disk drive and a hard disk drive. The I/O devices were generally monitored in lieu of memory devices since I/O devices usually require more power to operate. For example, when a software application is being executed by the CPU, there exist many I/O devices which are unnecessarily running and thereby wasting power. To eliminate such waste, the computer industry has devised conventional computer systems which could "power-off" the unnecessary I/O devices. However, there existed one major flaw with such conventional computer systems; specifically, if the CPU attempted to read data from or write data into any one of a "powered-off" I/O device, the software application would fail unnecessarily. Such unnecessary failures greatly increases the run-time of the software application and, thus, decreases its performance capabilities.
In response to these software application failures, Intel.RTM. Corporation of Santa Clara, Calif. developed the 386.TM.SL superset 1 which is the first superset to employ a power management architecture scheme designed to manage power use within the computer system. Such scheme was based on the operation of a Power Management Macro ("PMM") 6. As shown in FIG. 1, the SL superset 1 utilizes a system bus 2, which commonly an 8-bit bus, coupled to a plurality of bus masters, such as a CPU 3 and a DMA Controller 4. The system bus 2 is further coupled to a plurality of bus slaves 5a-5n, (e.g., I/O devices) and the PMM 6.
The PMM 6 is a programmable power manager comprising a plurality of storage elements, such as registers, used to maintain a list of bus slaves 5a-5n which are powered-on or powered-off; a list of physical addresses of such bus slaves; and a circuit to monitor the system bus 2 for access requests directed toward the bus slaves 5a-5n. The PMM 6 is programmed in accordance with the number of bus slaves 5a-5n coupled to the system bus 2. The operation of the conventional power management system within the SL superset 1 is illustrated in FIG. 2 as follows.
The CPU 3 places an access request on the system bus 2 to request access to a specific bus slave. For illustration purposes, let us presume that an I/O cycle is directed toward the bus slave 5a. The PMM 6 monitors the I/O cycle and determines whether the bus slave 5a is "powered off". If so, the PMM 6 signals the CPU 3 to halt execution of a main software application and to enter into a System Management Mode ("SMM"). SMM is a mode which allows the CPU 3 to operate within a special environment completely isolated from the main software application. This SMM mode is enabled when the PMM 6 generates a System Management Interrupt ("SMI") to the CPU 3 by activating a SMI control signal line 7 as shown in FIG. 1. This, in turn, would prompt a software service routine stored in memory to service the SMI. After the software service routine has serviced the SMI (i.e., the device is "powered-on"), the SMM would be exited thereby allowing the main software application to continue. All these operations being transparent to the user and the main software application.
However, one problem associated with the conventional power management system is that there exists no equivalent "SMI" mechanism to interrupt an alternative bus master, such as the DMA Controller 4, when it controls the system bus 2. Instead, as shown in FIG. 1, the conventional SL superset 1 utilized simple bus monitoring through I/O programmable traps to manage power status of the bus slaves 5a-5n when the DMA Controller 4 is in control of the system bus 2. More particularly, DMA was controlled by implementing a register 8 within the DMA Controller 4 so that DMA transfers could be requested by writing to this register 8. The PMM 6 would continuously monitor the register 8 so that once the DMA request was detected, all of the bus slaves susceptible to DMA transfer (i.e., DMA slaves) 5a-5n would be re-powered to allow the DMA to occur. Re-powering every DMA slave 5a-5n, however, does not efficiently optimize power usage. Hence, it would be desirable to implement a power management system capable of re-powering only a selected DMA slave which is accessed by the DMA Controller 4 in order to minimize power consumption.
Another problem is that even if the computer system was designed so that the PMM 6 could manage the DMA Controller 4 through interrupts such as SMI, the PMM 6 would still not be able to detect the beginning of a I/O cycle until after it had already begun. Since the PMM 6 is monitoring the system bus 2, the I/O cycle would be detected after external memory 9 had been accessed. Accordingly, it would be a great advantage and is therefore an object of the present invention to provide earlier power management of the DMA slaves transparent to the main software application.
USPTO Backgrounds
USPTO Backgrounds