In signal processing, various timing information, such as frequency, phase, or skew, is often gathered from a signal or series of signals having a sampling frequency higher than the bandwidth or frequency of the sampled signal(s) when oversampling.
By oversampling the incoming data stream, transition locations may be determined, valid data bits extracted and analyzed from the oversampled data, and bit boundaries identified for selecting preferred samples for bit recovery. Operationally, in oversampling, one method is recognized to first provide a common data stream to a plurality of flip-flops, generate multiple phases of a base clock, and provide each of the clock phases to a different flip-flop of the plurality of flip-flops. Oversampling improves the frequency at which the base clock alone would have sampled the data signal as the frequency of the data signal sampled is increased over the base clock frequency alone by the approach. In some oversampling approaches, an oversampling factor is applied which is the number of clock phases used to initiate the oversampling.
However, oversampling, particularly at higher oversampling rates, typically requires the use of multiple clock phases that often consume several digital clock managers (DCMs) and global clock resources. The approach may result in an inefficient use of resources such as where using multiple DCMs may create jitter in output thereby decreasing the precision of the sampling points, for instance. The approach may also create the need for additional clocks thereby creating a complex system requiring complicated data routing and additional system resource demands. Similarly, there are disadvantages such as increase of chip size, increase of current consumption and increase of cost in such traditional approaches.
Similarly, when attempting to increase the number of samples during a signal period for an available input signal, often an approach may include adding more flip-flops and more clock signals. A circuit comprised as such would then oversample an incoming serial data stream (i.e., input signal), evaluating data transition locations such as rising and falling waveforms, and extract data bits from the oversampled data following processing. After which, the oversampled data can then be analyzed to locate bit boundaries. However, while the addition of such may increase the number of samples, it also additionally provides for most cost, complexity and routing in order to maintain timed spacing, where such complexity does not necessarily ensure improved accuracy in all cases.
What is desired is an approach that increases the granularity of sampling within a single clock cycle without increasing the complexity of the addition of complicated resources and routings, thereby traversing the shortcomings of the typical approach and reducing error.
As used herein the terms device, apparatus, system, etc. are intended to be inclusive, interchangeable, and/or synonymous with one another and other similar arrangements and equipment for purposes of the present invention though one will recognize that functionally each may have unique characteristics, functions and/or operations which may be specific to its individual capabilities and/or deployment.
Accordingly, there is a need for an improved method of and circuit for oversampling a signal in an integrated circuit without added complexity.
USPTO Backgrounds
USPTO Backgrounds