1) Field of the Invention
The present invention relates to a data receiver which includes equalizers, receives data signals, and performs waveform shaping of the data signals with the equalizers. In addition, the present invention also relates to an equalizer adapter used in the data receiver for adapting the equalizers.
2) Description of the Related Art
When loss in a transmission line is great in transmission of data signals between LSIs, between elements or circuit blocks in a chip, between circuit boards, or between chassis, the data signals are deformed. Therefore, in such cases, adaptive equalizers are used. The adaptive equalizers detect deformation in data signals received by a receiver, and perform waveform shaping of the data signals into appropriate waveforms.
FIG. 18 is a diagram illustrating an example of a configuration of a data receiver. In FIG. 18, LSI (Large Scale Integration) chips 141 and 142 are indicated. The LSI chip 141 includes transmission circuits 141a to 141d, and the LSI chip 142 includes a data receiver constituted by reception circuits 142a to 142d and equalizer adapters 143a to 143d. The transmission circuits 141a to 141d and the reception circuits 142a to 142d are point-to-point connected through transmission lines, respectively. In addition, in FIG. 18, the dotted frames indicate the boundaries of clock domains. That is, the circuits indicated in each of the dotted frames operate in synchronization with each other.
The reception circuits 142a to 142d respectively receive data signals DT0 to DT3 through the transmission lines, and respectively comprise equalizers (not shown). The equalizer adapters 143a to 143d each receive from the reception circuits 142a to 142d N-bit data, and control the equalization coefficients EQ0 to EQ3 of the equalizers so as to correct deformation of the signals.
That is, the waveforms of the data signals DT0 to DT3 are shaped while controlling the equalization coefficients EQ0 to EQ3 of the equalizers in the reception circuits 142a to 142d by using the equalizer adapters 143a to 143d, respectively. Thereby, for example, the reception circuits 142a to 142d can correctly decide the values represented by the data signals DT0 to DT3 to be 0 or 1.
Further, in a wireless communication system (which is disclosed, for example, in Japanese Unexamined Patent Publication No. 7-66739), equalizers for compensating for intersymbol interference occurring in a digital communication system and deterioration caused by noise are arranged in two stages preceding reception circuits.
However, when equalizer adapters are respectively arranged in correspondence with the reception circuits, the size of the circuitry and power consumption increase.
USPTO Backgrounds
USPTO Backgrounds