1. Field of the Invention
The invention relates to a computer system with power management and the method thereof, and more particularly to a computer system with power management for a peripheral supporting the PCI express, and the method thereof.
2. Description of the Related Art
The power management is to optimize the power in a most efficiency way and thus save the power consumption. FIG. 1 is a schematic illustration showing a computer system. The computer 100 includes a CPU (Central Processing Unit) 110, a north bridge 120, a south bridge 130, and a power supply 140. The CPU 110 communicates with the power supply 140 and other peripherals (not shown in the drawing) via the north bridge 120 and the south bridge 130. The power supply 140 supplies a main power and an auxiliary power for powering the computer 100 to operate. The power supply modes typically include C2, C3, S3, S4, S5 modes, and the like. The modes C2 and C3 are used to save the power consumption of the CPU 110, while the modes S3, S4 and S5 are used to suspend the main power.
FIG. 2 is a flow chart showing a power management method in a typical computer system. First, in step 210, when the computer wants to enter a power-saving mode, such as a sleep mode S3, S4 or S5, the CPU 110 passes a power management signal to a power management unit of the south bridge 130 via the north bridge 120 by accessing a PMIO register of the south bridge 130 according to the indication from the operation system. Then, in step 220, the south bridge 130 receives the power management signal and immediately responds with a stop clock cycle STPCLK to inform the CPU 110 that the requested power supply mode will be entered. In step 230, the CPU 110 receives the stop clock cycle STPCLK and immediately responds with a stop grant cycle STPGNT to represent that the sleep mode is ready to be entered. The north bridge 120 receives the stop grant cycle STPGNT and immediately passes it to the south bridge 130, as shown in step 240. Next, the south bridge 130 receives the stop grant cycle STPGNT and immediately outputs a power control signal to the power supply 140. For example, the south bridge 130 outputs a power control signal SUSB to the power supply when the mode S3 is to be entered, or the south bridge 130 outputs a power control signal SUSC to the power supply when the mode S4 or S5 is to be entered. Finally, the power supply 140 receives the power control signal and immediately suspends the corresponding power, as shown in step 260.
Serially connected peripherals, such as PCI express peripherals that are electrically connected to the north bridge by PCI express link, have been gradually developed in order to meet the demands on the high-speed peripherals. FIG. 3 is a schematic illustration showing power management state transitions for a PCI express link. The PCI express link operates at a full speed under the normal condition referred to as the state L0. The PCI express link has to enter the state L2 or L3 for saving power. At this time, the power supply stops supplying the main power to the PCI express device. However, before entering the state L2 or L3, the link has to first enter the state of L2/L3 ready. However, because the conventional power management method is only controlled by the CPU and the south bridge, and the north bridge cannot identify the change of the power supply mode, the PCI express peripheral cannot be informed in advance. Under the condition that the PCI express link cannot identify the change of the power supply mode of the computer, the PCI express peripheral cannot be transited to the state of L2/L3 ready. Instead, the PCI express link jumps from the state L0 to the state L2 or L3, and abnormal conditions will be caused during the initialization of the next rebooting process.
USPTO Backgrounds
USPTO Backgrounds