1. Field of the Invention
The present invention relates to a plasma display device for providing gray-scale display by controlling the number of sub pixels to be turned ON out of sub pixels forming a pixel.
2. Description of the Related Art
Recently, information to be displayed is increasingly diversified and also a greater screen size and higher definition are increasingly implemented in equipments such as computer displays and televisions. In response to such trends, improved display quality is in high demand in the field of display devices used in those equipments (such as plasma display devices, LCDs (Liquid Crystal Displays), electroluminescence, fluorescent display tubes, and light emitting diodes).
Of the above display devices, the plasma display devices are actively developed in recent years because of their characteristics such as no flickering, easy to increase the screen size, high brightness, and long life time.
The plasma display devices are roughly divided into two types: a two-electrode plasma display device and a three-electrode plasma display device. The two-electrode plasma display device uses two electrodes to generate selective discharge (address discharge) for selecting cells to be turned ON from a plurality of light-emitting cells forming a display surface and sustain discharge for sustaining light emission of the selected light-emitting cells. The three-electrode plasma display device uses a third electrode to generate address discharge and uses the above two electrodes to generate sustain discharge.
Recently, plasma display devices capable of providing color display are also actively developed. Of such plasma display devices, a plasma display device capable of providing gray-scale display causes light emission by exciting a fluorescent material (which is formed in each light-emitting cell) having a luminescent color corresponding to one of the three primary colors of light by ultraviolet (UV) rays generated by discharge between the electrodes. However, the fluorescent material is susceptible to impact caused by bombardment of positively charged ions generated together with UV rays by discharge.
In the two-electrode plasma display device, ions directly bombard a fluorescent material. Therefore, the fluorescent material has a short life time.
In view of the above, a surface-discharge-type three-electrode plasma display device is becoming common in the art. In this plasma display device, ions generated by discharge do not bombard a fluorescent material.
The surface-discharge-type three-electrode plasma display device is divided into two types: a plasma display device in which a third electrode for generating address discharge is disposed on a substrate on which first and second electrodes for generating sustain discharge are disposed; and a plasma display device in which the third electrode is disposed on another substrate which faces the substrate on which the first and second electrodes are disposed.
In the plasma display device having the first to third electrodes on the same substrate, the third electrode may either be disposed above or below the two electrodes for generating sustain discharge.
There are also a transmission-type plasma display device and a reflection-type plasma display device. In the transmission-type plasma display device, light (visible light) emitted from a fluorescent material is transmitted through the fluorescent material to the outside. In the reflection-type plasma display device, light emitted from a fluorescent material is guided to the outside as reflected light from the fluorescent material.
A light-emitting cell for generating discharge is spatially separated from an adjacent light-emitting cell by a partition wall (which is also referred to as rib or barrier). The plasma display devices having this partition-wall structure are divided into two types. In one of the two types of plasma display devices, the partition wall entirely surrounds the four sides of each light-emitting cell in order to completely seal within the light-emitting cell a gas to be supplied for light emission. In the other type of plasma display device, the partition wall extends only in one direction, and adjacent light-emitting cells are separated from each other in the direction perpendicular to the one direction by providing an appropriate gap (distance) between electrodes.
Of the above three-electrode plasma display devices, a surface-discharge-type three-electrode AC (alternating current) plasma display device which has been commonly used in the art will now be described with reference to FIGS. 9 to 13. This plasma display device is disclosed in Japanese Laid-Open Publication No. 9-6283.
The following description will be given for a reflection-type surface-discharge three-electrode AC plasma display device (hereinafter, simply referred to as PDP (Plasma Display Panel)). In this PDP, first and second electrodes for generating sustain discharge are disposed in parallel on a substrate, and a third electrode for conducting address discharge is disposed in the direction perpendicular to the first and second electrodes on a substrate facing the above substrate. Moreover, the partition wall is disposed only in the direction perpendicular to the first and second electrodes for generating sustain discharge and parallel to the third electrode for generating address discharge. Each of the first and second electrodes is partially formed by a transparent electrode.
First, the schematic structure of the conventional PDP will be described with reference to FIGS. 9 to 11. FIG. 9 is a plan view of the conventional PDP 100.
Referring to FIG. 9, the PDP 100 includes address electrodes A1 to AM for generating address discharge and X-electrodes X1 to XN and Y-electrodes Y1 to YN for generating sustain discharge. The X-electrodes X1 to XN are connected to a common electrode, and the Y-electrodes Y1 to YN are independent of each other.
A fluorescent material corresponding to one of the three primary colors of light (red (R), green (G) and blue (B)) is applied in each light-emitting cell C. The Y-electrodes Y1 to YN are separated by partition walls 129 in the address-electrode direction.
A fluorescent material of the same color is applied in a space between adjacent two partition walls 129 so that the PDP 100 has repeated stripe patterns of fluorescent material having the colors of R, G, B.
Adjacent light-emitting cells C are separated from each other in the direction of the address electrodes A1 to AM by providing an appropriate gap (distance) between an X-electrode and a Y-electrode between the adjacent light-emitting cells C (e.g., X-electrode XN and Y-electrode YN-1).
In the PDP 100 having the above structure, address discharge is generated between the address electrode A1 to AM and the Y-electrode Y1 to YN, and sustain discharge is generated between each X-electrode X1 to XN and a corresponding adjacent Y-electrode Y1 to YN (e.g., X-electrode X1 and Y-electrode Y1, X-electrode X2 and Y-electrode Y2, and the like).
Hereinafter, the cross-sectional structure of the PDP 100 will be described with reference to FIGS. 10A and 10B. FIG. 10A is a partial cross-sectional view taken along line α–α′ in FIG. 9 (a region associated with the address electrodes A4 to A6), and FIG. 10B is a partial cross-sectional view taken along line β–β′ in FIG. 9 (a region associated with the Y-electrode Y1, the X-electrode X2 and the Y-electrode Y2).
As shown in FIGS. 10A and 10B, the PDP 100 is a reflection-type PDP. The address electrodes A1 to AM, the X-electrodes X1 to XN, the Y-electrodes Y1 to YN, the light-emitting cells C and the partition walls 129 are formed between a rear glass substrate 131 and a front grass substrate 106. The X-electrodes X1 to XN and the Y-electrodes Y1 to YN serve as sustain electrodes. As shown in FIG. 10A, the PDP 100 includes the following elements sequentially from its rear surface: the rear glass substrate 131; the address electrodes A1 to AM; the partition walls 129; a fluorescent material F; an MgO layer 102; a dielectric layer 103 such as glass; the X-electrodes X1 to XN; the Y-electrodes Y1 to YN; and the front glass substrate 106. The rear glass substrate 131 serves as a body of the PDP 100. The partition walls 129 separate the light-emitting cells C from each other. The fluorescent material F covers the address electrodes A1 to AM. The fluorescent material F has a luminescent color (R, G or B) corresponding to each light-emitting cell C, and emits light when being excited by UV rays generated by address discharge and sustain discharge. The MgO layer 102 serves as a protection layer for protecting a discharge surface from positive ions bombardment produced by address discharge and sustain discharge. The dielectric layer 103 insulates the X electrodes and the Y-electrodes from each other and forms a discharge surface. The front glass substrate 106 forms a display surface.
The rear glass substrate 131 and the front glass substrate 106 are laminated each other so that the top of the partition walls 129 closely contact the MgO layer 102.
As shown in FIG. 10B, each of the X-electrodes X1 to XN and the Y-electrodes Y1 to YN is formed by a transparent electrode 105 and a bus electrode 104.
The transparent electrode 105 is formed from ITO (Indium Tin Oxide, a transparent conductive film mainly containing indium oxide) in order to allow emitted light from the fluorescent material F to transmit therethrough. The bus electrode 104 is formed from a low-resistance material such as Cu (copper) or Cr (chromium) in order to prevent a voltage drop from being caused by an electric resistance.
In the above structure, emitted light from the fluorescent material F transmits through the transparent electrodes 105 and the front glass substrate 106 as reflected light and is discharged from the display surface to the outside. In display data to be displayed using the conventional PDP 100, each frame is formed by a plurality of sub frames (images), and each sub frame is divided into a reset period, an address period, and a sustain discharge period in a time-sharing manner.
The reset period is a period for resetting all light-emitting cells C of the PDP 100 in order to remove unnecessary charges. The address period is a period for generating address discharge (selective discharge; see FIGS. 10A and 10B) by applying an address pulse and a scan pulse along an address line to an address electrode A1 to AM and a Y-electrode Y1 to YN which correspond to light-emitting cells C to be turned ON, based on the data to be displayed.
The sustain discharge period is a period for applying a sustain pulse to the X-electrode X1 to XN and the Y-electrode Y1 to YN in order to enhance light emission of the light-emitting cells C turned ON by address discharge. The sustain pulse generates sustain discharge, whereby the light-emitting cells C emit light. As a greater number of sustain pulses is applied, brightness of the light-emitting cells C is increased.
Hereinafter, the structure of a conventional plasma display device including the PDP 100 will be described with reference to FIG. 11. In the plasma display device 200 of FIG. 11, the address electrodes A1 to AM are individually connected to an address driver 111. The address driver 111 applies an address pulse PAW and the like for generating address discharge. The Y-electrodes Y1 to YN are individually connected to a Y-scan driver 113.
The Y-scan driver 113 is connected to a Y-common driver 114. The Y-scan driver 113 generates a scan pulse PAY for generating address discharge. The Y-common driver 114 generates a sustain pulse PYS and the like in a sustain discharge period, and applies the sustain pulse PYS and the like to the Y-electrodes Y1 to YN through the Y-scan driver 113. The X-electrodes X1 to XN are connected to a common potential across all display lines of the PDP 100 and extended to the outside.
An X-common driver 112 generates a write pulse PXW in a reset period and generates a sustain pulse PXS in a sustain discharge period, and the like. These drivers are controlled by a control circuit 110.
The control circuit 110 includes a display data control section 120 and a panel drive control section 121. The display data control section 120 includes a frame memory 130 for storing data corresponding to a single frame of display data. The panel drive control section 121 includes a scan-driver control section 140 and a common-driver control section 141 for controlling a corresponding driver. The control circuit 110 outputs control signals for controlling each driver, based on external signals (a dot clock CLK, synchronization  signals HSYNC, VSYNC and display data DATA).
Hereinafter, operation of the plasma display device 200 in a sub-frame period (a period corresponding to a single sub frame) will be described with reference to the timing chart of FIG. 12 and FIG. 11. FIG. 12 shows the timing of generating each pulse in a sub-frame period.
As shown in FIG. 12, all Y-electrodes Y1 to YN are set to 0 V and a write pulse PXW (about 330 V, 10 μsec) is applied to all X-electrodes X1 to XN in a reset period (which consists of an overall write period and a self-eraser discharge).
A write pulse PAW is applied to all address electrodes A1 to AM in synchronization with the write pulse PXW. These write pulses PXW, PAW generate discharge between all X-electrodes X1 to XN and all address electrodes A1 to AM (in all light-emitting cells C) regardless of the previous display state. After discharge is generated by the write pulses PXW, PAW, all X-electrodes X1 to XN and all address electrodes A1 to AM fall to 0 V. In all light-emitting cells C, a voltage of wall charges themselves exceeds a starting discharge voltage, whereby discharge is started. Since there is no potential difference between the electrodes, no wall charge is generated by the discharge, and the discharge is completed as a result of self-neutralization of space charges. This is so-called self-erase discharge.
A period from completion of application of the write pulse PXW to the X-electrodes X1 to XN until starting application of a voltage to the X-electrodes X1 to XN in the following address period is referred to as a self-eraser discharge TSE.
This self-erase discharge renders all light-emitting cells C in a uniform potential state having no wall charge, whereby reset operation is conducted. In the reset period, all light-emitting cells C are rendered in the same potential state regardless of their ON/OFF states in the previous sub-frame period. This ensures stable address discharge in the address period following the reset period.
In the address period, address discharge is generated in order to select light-emitting cells C to be turned ON based on sub-frame data. The address discharge is divided into priming address discharge and main address discharge. The priming address discharge is discharge for designating light-emitting cells, and the main address discharge is discharge for accumulating wall charges.
More specifically, in the priming address discharge, an address pulse PAA is applied to address electrodes corresponding to light-emitting cells C to be turned ON. In parallel with this, a scan pulse PAY is applied to Y-electrodes corresponding to the light-emitting cells C to be turned ON sequentially from the Y-electrode Y1 in a time-sharing manner (along an address line). The priming address discharge is thus generated by the address pulse PAA and the scan pulse PAY.
The address pulse PAA is applied to all address electrodes corresponding to the light-emitting cells C designated by sub-frame data corresponding to a single sub frame shown in the timing chart of FIG. 12.
As a result, the priming address discharge occurs simultaneously in the required ones of the light-emitting cells C corresponding to the Y-electrode. Since the scan pulse PAY is sequentially applied to the Y-electrodes, this operation is repeated in the light-emitting cells C corresponding to a Y-electrode of interest in response to the scan pulse PAY applied to each Y-electrode.
The priming address discharge and the main address discharge will now be described in more detail. First, a scan pulse PAY of −VY level (about −150 V) is applied to a Y-electrode of interest (e.g., Y-electrode Y1). At the same time, an address pulse PAA of a voltage Va (about 50 V) is applied to an address electrode corresponding to a light-emitting cell C to be turned ON. All X-electrodes X1 to XN are held at a predetermined X-address voltage (“VX” in FIG. 12). As a result, priming address discharge occurs between the Y-electrode Y1 and the address electrode A1. This priming address discharge serves as priming of main address discharge. Main address discharge thus occurs between the corresponding X-electrode X1 and the Y-electrode Y1 as discharge for accumulating wall charges.
The priming address discharge and the main address discharge accumulate wall charges on the MgO film 102 (see FIGS. 10A, 10B) covering the X-electrode and the Y-electrode corresponding to the light-emitting cell C to be turned ON (X-electrode X1 and Y-electrode Y1) in an amount which allows sustain discharge to be generated in the following sustain discharge period.
The above address discharge occurs sequentially in all Y-electrodes in response to every address pulse PAY, whereby data is written to the light-emitting cells C corresponding to the sub-frame data of a single sub frame.
Finally, in the sustain discharge period, sustain pulses PXS, PYS (about 180 V) are alternately applied to all X-electrodes and all Y-electrodes in order to enhance light emission of the light-emitting cells designated in the address period. As a result, sustain discharge exceeding a threshold value occurs in the designated light-emitting cells C (the light-emitting cells C having wall charges accumulated therein), whereby an image having a brightness corresponding to the sub-frame data is displayed. As described above, the brightness in the sub-frame period is increased as a greater number of sustain pulses PXS, PYS is applied.
Hereinafter, multi-gray-scale display of the plasma display device 200 including the above PDP 100 will be described. It is herein assumed that the plasma display device 200 provides display of 256 gray levels.
For display of 256 gray levels, each frame of display data is divided into eight sub frames (SF1 to SF8) in a time-sharing manner, as shown in FIG. 13. Wherein, the time-sharing manner and the time dither method have the same meaning.
Each sub frame has a reset period, an address period and a sustain discharge period. The reset period and the address period have respective constant lengths in every sub frame. The eight sub frames have the sustain discharge period at a length ratio of 1:2:4:8:16:32:64:128. Accordingly, selecting a sub frame to be turned ON enables the difference in brightness of to be displayed with 256 gray levels (i.e., 0 to 255).
For example, it is now assumed that 7/256 gray levels are to be displayed. Since 7 (gray level)=1 (gray level)+2 (gray level) and 4 (gray level), light is emitted only during a period corresponding to the sub frames SF1 to SF3, and no light is emitted in the remaining sub frames. Similarly, when 20/256 gray levels are to be displayed, 20 (gray level)=16 (gray level)+4 (gray level). Therefore, light is emitted only during a period corresponding to the sub frames SF3, SF5. The brightness of each sub frame is determined by the length of the sustain discharge period, that is, the number of sustain pulses.
An example of actual time allocation in each frame is as follows: provided that the display is rewritten at 60 Hz, each frame is 16.6 ms (1/60 Hz). If the number of sustain discharge cycles (hereinafter, sometimes referred to as “sustain cycles”) per frame is 510, the number of sustain cycles of each sub frame is 2 for the sub frame SF1, 4 for the sub frame SF2, 8 for the sub frame SF3, 16 for the sub frame SF4, 32 for the sub frame SF5, 64 for the sub frame SF6, 128 for the sub frame SF7, and 256 for the sub frame SF8.
Provided that each sustain cycle is 8 μs, the total time of sustain cycles in each frame is 4.08 ms. Eight reset periods and eight address periods are allocated in the remaining period (about 12 ms). The reset period of each sub frame is 50 μs, and the time required for an address cycle (scanning per line) is 3 μs. Therefore, in the case of the PDP 100 having 480 display lines (Y-electrodes) in the vertical direction, 1.44 ms (3×480) is required for the address cycles.
Accordingly, in order to display 256 gray levels by display data of a single frame (sub frames SF1 to SF8), about 16 ms is required in total for the reset periods, the address periods and the sustain discharge periods.
Japanese Laid-Open Publication No. 2000-66637 describes a method for improving gray-scale display by using in combination a gray-scale display means for dividing each frame of display data into a plurality of sub frames in a time sharing manner and a gray-scale display means for forming a unit pixel by a plurality of pixels. This method will now be described.
In this method, each pixel is formed by minimum unit pixels of R, G, B, and each minimum unit pixel is formed by a plurality of pixels. In this case, each unit pixel can be formed by two, three or more pixels. In the case where each minimum unit pixel is formed by a multiplicity of pixels, resolution is necessarily reduced due to the limitation of reduction in pixel size. Accordingly, each unit pixel is desirably formed by about two pixels.
Provided that each unit pixel is formed by two pixels and a time dither method is not used, the following three gray levels are possible: “both pixels are turned ON (very bright)”; “one of the pixels is turned ON (bright)”; and “both pixels are turned OFF (dark)”.
Conventionally, however, each of the minimum unit pixels of R, G, B is normally formed by a single pixel. Therefore, if the time dither method is not used, only the following two gray levels are possible: “the pixel is turned ON (bright)”; and “the pixel is turned OFF (dark)”.
According to the technology described in Japanese Laid-Open Publication No. 2000-66637, the number of unit pixels to be turned ON is controlled in a stepwise manner. This enables a greater number of gray levels to be displayed as compared to the conventional examples.
The above gray-scale display method can be used in combination with a gray-scale display method based on the time dither method in which each field is divided into a plurality of sub frames and a desired pixel is turned ON during a period of a desired sub frame.
Hereinafter, the above technology will be described in more detail with reference to the figures.
FIG. 14 shows the structure of the conventional plasma display device. This plasma display device 100 includes an AC-type PDP 100 and a drive unit 85. The PDP 100 is a matrix-type color display device. The drive unit 85 selectively turns ON the light-emitting cells C forming a screen SC. The light-emitting cells C are arranged in a matrix.
The PDP 100 is a surface-discharge type three-electrode PDP. More specifically, in the PDP 100, two pairs of first and second main-discharge electrodes (e.g., X-electrode X2N-1, Y-electrode Y2N-1 and X-electrode X2N, Y-electrode Y2N) are provided in parallel in every row. In each cell C, the X-electrode and the Y-electrode cross a corresponding address electrode AM (third electrode). Each unit pixel is formed by two pixels.
The X-electrode X2N-1, the Y-electrode Y2N-1, the X-electrode X2N and the Y-electrode Y2N extend in the row direction (horizontal direction) of the screen. The Y-electrodes Y2N-1, Y2N are used as scan electrodes for selecting light-emitting cells C on a row-by-row basis in an address period. The address electrodes AM extend in the column direction (vertical direction), and are used as data electrodes for selecting light-emitting cells C on a column-by-column basis. The region where the X-electrode group XN and the Y-electrode group YN cross the address electrode group AM is a display region, that is, the screen SC.
The drive unit 85 has a controller 110, a frame memory 122, a data processing circuit 120, a sub-field memory 124, a power supply circuit 46, an X-driver 112, a Y-driver 113 and an address driver 111. Field data and various synchronization signals are applied from an external device (such as a television (TV) tuner and a computer) to the drive unit 85. The field data indicates the brightness level (gray level) of each color (R, G, B) on a pixel-by-pixel basis.
The field data is first stored in the frame memory 122 and then transmitted to the data processing circuit 120. The data processing circuit 120 is a data conversion means for dividing each field into a predetermined number of sub frames in order to provide gray-scale display and determining a combination of sub frames to be turned ON. The data processing circuit 120 outputs sub-frame data Dsf corresponding to the field data. The sub-frame data Dsf is stored in the sub-field memory 124. The value of each bit of the sub-frame data Dsf represents information indicating whether a cell is to be turned ON or not in a sub frame. To be exact, the value of each bit of the sub-frame data Dsf represents information indicating whether address discharge is required or not.
The X-driver 112 applies a drive voltage to the X-electrode group XN, and the Y-driver 113 applies a drive voltage to the Y-electrode group YN. The address driver 111 applies a drive voltage to the address electrodes AM according to the sub-frame data Dsf. The power supply circuit 46 supplies predetermined power to these drivers.
FIG. 15 is a perspective view showing the internal structure of the PDP 100. On the inner surface of a front glass substrate 106 of the PDP 100, two pairs of first and second electrodes (e.g., X-electrode X2N-1, Y-electrode Y2N-1 and X-electrode X2N, Y-electrode Y2N) are provided in every row L. Each row L is a cell train in the horizontal direction of the screen. The X-electrodes X and the Y-electrodes Y are formed by a transparent conductive film 105 and a metal film (bus conductor) 104, and are covered with a dielectric layer 103 having a thickness of about 30 μm. The transparent conductive film 105 is formed from ITO, the metal film 104 is formed from Cr—Cu—Cr, and the dielectric layer 103 is formed from low melting-point glass.
A protection film 102 having a thickness of several thousands of angstroms is provided on the surface of the dielectric film 103. The protection film 102 is formed from magnesia (MgO). The address electrodes A are provided on an underlying layer 132 which covers the inner surface of a rear glass substrate 131, and are covered with a dielectric layer 134 having a thickness of about 10 μm.
A partition wall 129 having a height of 150 μm is provided on the dielectric layer 134 at a position between the address electrodes A. Each partition wall 129 has a linear band shape when viewed two-dimensionally. These partition walls 129 define individual discharge spaces 135 in the row direction on a sub-pixel-by-sub-pixel basis, and also define the dimension of the gap between the discharge spaces 135. Note that the sub pixel is a unit light-emitting region.
For color display, fluorescent material layers 128R, 128G, 128B of three colors (R, G, B) cover the inner surface of the rear glass substrate 131 (including the side surfaces of the partition walls 129 and the portions above the address electrodes A). Each of the fluorescent material layers 128R, 128B, 128B has a stripe pattern so that the cells in the same column have the same luminescent color and the cells in adjacent columns have different luminescent colors.
For improved contrast, it is desirable to color the top portions of the partition walls 129 with a dark color and to color the other portions thereof with white so as to increase the reflectance of visible light. The partition walls 129 are colored by adding a pigment of a predetermined color to glass paste, a material of the partition walls 129.
The discharge spaces 135 are filled with a discharge gas (charged pressure: 500 Torr). The discharge gas is a mixture of neon (a main component) and xenon. When discharge occurs, UV rays are generated by xenon. As a result, the fluorescent material layers 128R, 128G, 128B are locally excited by the UV rays and emit light. Each pixel for display is formed by a total of six sub pixels arranged in two rows. More specifically, each pixel for display is formed by three sub pixels arranged in a row and three sub pixels arranged in an adjacent row. The structural element in each sub pixel is a light-emitting cell (display element) C. Since the partition walls 129 are arranged with a stripe pattern, every discharge space 135 continuously extends in the column direction over all rows L.
Therefore, the dimension of the electrode gap between adjacent rows L (which is called “reverse slit”) is sufficiently larger than the surface discharge gap of each row L (e.g., in the range of 80 to 140 μm). The electrode gap has a value that prevents discharge coupling in the column direction (e.g., in the range of 200 to 500 μm).
Note that a not-shown light-shielding film is provided on the outer surface or inner surface of the glass substrate 106 along each reverse slit in order to hide a non-luminous whitish fluorescent material layer.
FIG. 16 specifically illustrates the structure of the PDP 100. As shown in FIG. 16, each unit pixel is formed by fluorescent material layers 128R, 128G, 128B of three colors (R, G, B) in the horizontal direction, and is formed by two electrode pairs (i.e., a first electrode pair X1, Y1 and a second electrode pair X2, Y2) in the vertical direction. Therefore, each unit pixel is formed by six sub pixels (i.e., two R-sub pixels, two G-sub pixels, and two B-sub pixels).
In the illustrated example, each unit pixel is formed by two display electrode pairs. However, each unit pixel may alternatively be formed by three, four or more display electrode pairs.
The above electrode arrangement enables reduction in individual discharge, thereby improving luminous efficiency over the conventional PDP in which each unit pixel is formed by a single display electrode pair.
FIGS. 17A to 17C illustrate the ON/OFF state of two sub pixels of each color (R, G, B). As shown in FIGS. 17A to 17C, the following three brightness levels are possible for two sub pixels of each color (R, G, B): both cells are turned ON (brightness level 2) (see FIG. 17A); one of the two cells is turned ON (brightness level 1) (see FIG. 17B); and both cells are turned OFF (brightness level 0) (see FIG. 17C).
Since the three brightness levels are possible, display of a greater number of gray levels can be provided as compared to the case where a PDP having unit pixels each formed by three sub pixels of R, G, B is driven by the time dither method.
More specifically, when the time dither method is applied to the PDP having unit pixels each formed by three sub pixels R, G, B, each field is divided into a plurality of sub frames, and the sub frames have a length ratio of 1:2:4:8:16 . . . . Therefore, if each frame is divided into n sub frames, 2n gray levels are obtained.
On the other hand, when the time dither method is applied to the conventional PDP, each field is divided into a plurality of sub frames, and the sub frames have a length ratio of 1:3:9:27:81 . . . . Therefore, if each frame is divided into n sub frames, 3n gray levels are obtained.
For example, if each field is divided into four sub frames, five sub frames and six sub frames, display of 81 gray levels, 243 gray levels and 729 gray levels is possible, respectively.
In this case, the same effects as those obtained by a dither method are obtained. In the dither method, however, gray-scale display is provided by a plurality of pixels, thereby reducing the resolution of the screen. On the other hand, in the above conventional method, gray-scale display is provided by a single pixel. Therefore, the resolution of the screen is not reduced.
If the number of discharge electrodes is increased, the write time of each sub field is increased as compared to the PDP having unit pixels each formed by three sub pixels of R, G, B. Therefore, when the time dither method is used, the number of sub frames must be reduced as compared to the conventional example, whereby the number of gray levels is reduced. In the above conventional method, however, gray-scale display is provided by a single pixel. Therefore, the number of gray levels is not reduced even if the number of sub frames is reduced. Moreover, since the density of points whose ON/OFF state is controlled is increased, the spatial frequency of the image is increased, which contributes to improvement in apparent image quality.
In the illustrated example, each unit pixel is formed by two display electrode pairs. However, each unit pixel may alternatively be formed by three, four or more display electrode pairs, as described above.
Greater screen size and higher definition are highly expected for the plasma display devices.
However, 256 gray levels are the limit of gray-scale display even in a VGA (Video Graphics Array)-standard plasma display device having 480 display lines (Y-electrodes) in the vertical direction as disclosed in Japanese Laid-Open Publication No. 9-6283.
Japanese Laid-Open Publication No. 11-133912 describes a plasma display device capable of implementing a greater number of gray levels and higher definition. In this plasma display device, the display screen is divided into upper and lower display screens, and these upper and lower display screens are simultaneously scanned by using two independent scan-pulse generating means.
However, since the display screen is divided into the upper and lower display screens, a difference is produced between a voltage applied to an upper anode driving section and a voltage applied to a lower anode driving section. This causes a difference in a discharge current for gray-scale display between the upper and lower display screens. Therefore, the resultant gray-scale display becomes non-uniform along the boundary between the upper and lower display screens.
The gray-scale display means disclosed in Japanese Laid-Open Publication No. 2000-66637 has a plurality of sub pixels (k sub pixels) in the column direction. Therefore, the number of scanning lines required to scan all sub pixels in the column direction is increased to N (scanning lines)×k (sub pixels), thereby increasing the total address period. As a result, there is a limit in improvement in definition and the number of gray levels.
It is now assumed that video signal data according to the VGA standard (480 display lines (480 pixels) in the vertical direction) is displayed with a total of 243 gray levels by using both a gray-scale display means of three gray levels and a gray-scale display means based on the time dither method. In the former gray-scale display means, each of the pixels of R, G, B in the column direction is formed by two sub pixels. In the latter gray-scale display means, each frame is formed by five sub frames and the sub frames have a length ratio of 1:3:9:27:81.
Each sustain cycle period:8μsNumber of sustain cycles pergray level:2cyclesEach reset period:50μsEach address cycle period:3μs
In this case, the total period required to provide 8-bit gray-scale display of VGA-standard video signal data of a single frame is given by the following equation (4):Reset period=0.25 ms  (1)Address cycle period=14.4 ms  (2)Sustain cycle period=1.94 ms  (3)A frame period required for 243 gray-level display=16.59 ms  (4)It can be appreciated from the equation (4) that the plasma display device having 480 pixels in the column direction cannot provide more than 243 gray-level display. In other words, higher definition and a greater number of gray levels are not implemented.
It is now assumed that video signal data according to VGA standard (480 display lines (480 pixels) in the vertical direction) is displayed with a total of 729 gray levels by using both a gray-scale display means of three gray levels and a gray-scale display means based on the time dither method. In the former gray-scale display means, each of the pixels of R, G, B in the vertical direction is formed by two sub pixels. In the latter gray-scale display means, each frame is formed by six sub frames, and the sub frames have a length ratio of 1:3:9:27:81:243.Reset period=0.3 ms  (5)Address cycle period=17.28 ms  (6)Sustain cycle period=5.82 ms  (7)A frame period required for 729 gray-level display=23.40 ms  (8)In this case, the frame period required for 729 gray-level display (23.40 ms) exceeds a standard one-field period (about 16.6 ms) of a video signal.
In other words, the gray-scale display means disclosed in Japanese Laid-Open Publication No. 2000-66637 do not provide a solution to implement higher definition and a greater number of gray levels in the PDP, and can implement the number of gray levels and definition at most as the same level as that in the existing technologies.
USPTO Backgrounds
USPTO Backgrounds