1. Field of the Invention
The present invention relates to a semiconductor device decreased in thickness by a backgrinding process of a semiconductor substrate, and a method of manufacturing the device.
2. Description of Related Art
As a method of manufacturing a power semiconductor device such as a diode or an insulated gate bipolar transistor (hereinafter, referred to as IGBT), the following method is known. First, a semiconductor device is manufactured using a wafer such as silicon wafer while it has a large thickness. Then, the wafer is decreased in thickness to have a final thickness by grinding and etching, and then subjected to ion implantation and activation heat treatment (for example, refer to JP-T-2002-520885, where the term “JP-T” as used herein means a published Japanese translation of a PCT patent application). Such a manufacturing method is becoming mainstream in recent years.
However, in this manufacturing method, since an electrode has already been formed on a surface of the wafer at a side opposite to a side of a surface that was ground, heat treatment must be performed at low temperature, at or below a melting point of the material of the electrodes, for example, at a temperature of 450° C. or less if the electrode material is aluminum, in the activation heat treatment after grinding. Therefore, it is hard to sufficiently activate impurities.
Thus, the applicant has proposed a method of activating an ion-implanted impurity by irradiating high-energy laser light such as YAG second harmonic (YAG2ω) upon an ion implantation surface instead of heat treatment in this manufacturing method (for example, refer to JP-A-2005-223301 and JP-A-2005-64429). According to this method, since energy can be applied only to a region in an appropriate depth from a laser irradiation surface, the impurity can be activated without adversely affecting the previously formed electrode.
For example, a diode in a withstand voltage class of 1200 V is fabricated as follows. First, a P-type anode layer or an aluminum electrode to be an anode electrode is formed on a right face of an N-type FZ (floating zone) silicon wafer having a thickness of about 500 μm and resistivity of about 60 Ωcm. Then, the wafer is subjected to grinding from a back face, so that the thickness of the wafer is made to be 140 μm. Then, the ground surface is chemically polished by wet etching using nitro-hydrofluoric acid. Then, phosphorous is ion-implanted into the polished surface.
Then, such an ion-implanted surface is irradiated with YAG 2ω laser light by a double pulse method setting an energy density of 4 J/cm2 and a delay time of 300 nanoseconds, so that the phosphorous is electrically activated, thereby forming an N+ cathode layer. Here, the double pulse method is a method where a plurality of pulse laser beams are continuously irradiated from a plurality of laser irradiation devices with irradiation timing being staggered by predetermined delay times for each irradiation area of laser light. The double pulse method is described in detail in the JP-A-2005-223301.
Moreover, a diode in which an impurity concentration of a drift layer has a profile that the concentration gradually decreases from the neighborhood of the center of the drift layer to the anode and cathode layers, and an IGBT in which the impurity concentration of a drift layer has a profile such that the concentration gradually decreases from the neighborhood of the center of the drift layer to emitter and collector layers are known (for example, refer to JP-A-2005-64429 and JP-A-2003-318412). A diode or IGBT having such an impurity concentration profile has properties of both a high-speed and low-dissipation and exhibits a soft recovery property.
Furthermore, a semiconductor element is known, in which a P-type anode layer is formed at one end of an N-type semiconductor substrate in low concentration, and an N-type cathode layer in comparatively high concentration is formed at the other end; an i layer is formed between the anode and cathode layers; and an N-type impurity layer in low concentration compared with the cathode layer is provided between the cathode layer and the i layer (for example, refer to JP-A-2000-223720). Moreover, a power diode is known, in which an N-type internal region, and an N-type cathode region following the internal region and having high doping concentration compared with the internal region, and a P-type anode region following the internal region and having high doping concentration compared with the internal region are provided, and an N-type floating region having high doping concentration compared with the internal region is provided in the internal region (for example, refer to JP-A-11-26779).
However, such a diode or IGBT, which is fabricated by the method in which one surface of a semiconductor substrate is ground, and a cathode layer of the diode or a collector layer of the IGBT is formed on such a ground surface, exhibits a problem in that the probability of defective articles is high in measurement of electric characteristics in a wafer state before being cut into individual chips, that is, production yield is low. For example, when a leakage current of an element at a reverse bias voltage of 1200 V of a diode (hereinafter, referred to as reverse leakage current) was measured in the wafer state, many elements showed a leakage current of 10 μA/cm2 or more with respect to a criterion of 1 μA/cm2 or less, and the production yield was 60% or less.
The problem of generation of such a reverse leakage current has not been noticed in the past. Therefore, it should be appreciated that the patent references referred to above do not suppose generation of the reverse leakage current at all. Therefore, there is no description of the reverse leakage current or description of a measure for the reverse leakage current therein.
It is desirable to provide a semiconductor device showing a small reverse leakage current, the device being fabricated by decreasing the thickness of a semiconductor substrate by grinding, then performing ion implantation to such a ground surface and thermal activation of an implanted element. Moreover, it is desirable to provide a method of manufacturing a semiconductor device, in which a semiconductor device showing a small reverse leakage current is fabricated by decreasing thickness of a semiconductor substrate by grinding, then performing ion implantation to such a ground surface and thermal activation of an implanted element.
As a result of earnest study, the inventor discovered the following. When a scratch is formed on a ground surface (ion implantation surface) of a semiconductor substrate, or a particle caused by grinding remains thereon, since phosphorous as an N-type impurity is not normally ion-implanted into the ground surface, a cathode layer in high concentration may not be uniformly formed.
That is, when the particle remains, the particle blocks the phosphor, and the phosphor is not sufficiently implanted into the substrate, therefore a cathode layer in high concentration is not formed. Moreover, when a scratch having a size of a trajectory of an ion or more is formed on an implanted surface after ion implantation, an N+ high-concentration layer is not formed in a portion of the scratch and therefore an exposed portion of the substrate is formed. When a high reverse bias voltage is applied to an element having such a defect, a depletion layer expands into an N− drift layer, and reaches an electrode at the site of the defect, therefore the reverse leakage current is increased. The present invention overcomes these problems.
USPTO Backgrounds
USPTO Backgrounds