One-time programmable non-volatile memories (OTP) have been widely used in read only memories (ROMs) for circuit trimming, and can be realized using a circuit containing fuse or antifuse element structures. When a fuse element is utilized, the device is programmed by blowing fusible links at selected nodes to create an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data that a user wishes to store in OTP. A high power is normally required (e.g. ˜50 mA for a poly fuse link in a 0.25 um CMOS flow) to blow the link. In addition, a large area with supporting circuits is required. If the resultant opening formed in the circuit is not large enough, the disconnected blown links may become reconnected during long-term operation of the links, resulting in a circuit malfunction and reliability issues.
When an antifuse element is utilized, the programming mechanism is opposite the process of causing an open circuit in the fuse structure to be formed. Instead, the antifuse element programming mechanism creates a short circuit or a low resistance path. The antifuse element includes an insulating dielectric layer, such as a gate oxide, between two conducting layers. The unprogrammed state of an antifuse element is an open circuit with intact dielectric. The programmed state is a shorting path at a damaged point, known as the rupture point, in the dielectric/gate oxide formed by applying a voltage higher than the dielectric rupture voltage. It is known that, as the gate oxide in complementary metal oxide semiconductor (CMOS) flows becomes thinner (below 50 Å), many NMOS or PMOS types of structures are useful as antifuses, because the gate oxide rupture voltage/current becomes lower with thinner oxides resulting in a smaller trim circuit. Furthermore, spontaneous healing of a ruptured gate oxide is very unlikely, resulting in improved device reliability.
Typically, previous approaches to the inclusion of antifuse elements using CMOS type devices tie the source, drain, and body together as the bottom electrode, and the polysilicon gate as the top electrode. During programming, the rupture points can occur on the source side, drain side, or any point in a channel region formed under the polysilicon gate. This results in a relatively large resistance variation. In addition, when the rupture is located in the channel region under the gate, undesirable diode behavior may be measured between the polysilicon gate and silicon body, due to the opposite doping types. In general, previous antifuse elements are characterized by: (1) a program voltage higher than a low voltage CMOS transistor operation voltage; (2) long programming time (the charge-to-breakdown (QBD) is a function of gate oxide thickness, area and defects); and (3) large post program resistance and variation due to random rupture locations in the gate oxide.
Accordingly, it would be desirable to provide an antifuse element and a method of forming an antifuse element in which the rupture location is controlled and the local rupture electric fields are enhanced. Other desirable features and characteristics of the present embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
USPTO Backgrounds
USPTO Backgrounds