The present invention relates to a structure and a process for fabrication of a semiconductor device including a high-K dielectric material for a tunnel dielectric and in a modified ONO structure, in particular to a structure and process for fabrication of a floating gate flash memory device.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions.
An important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. The ONO structure has been used as the interpoly dielectric layer in a floating gate flash memory device. In such a device, the ONO structure separates the floating gate electrode from the control gate electrode.
A floating gate flash memory device includes a floating gate electrode upon which electrical charge is stored. The floating gate electrode is formed on a tunnel oxide layer which overlies a channel region residing between the source and drain regions in a semiconductor substrate. The floating gate electrode together with the source and drain regions form an enhancement transistor. Typically, the floating gate electrode may be formed of polysilicon.
In a floating gate flash memory device, electrons are transferred to the floating gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating gate electrode by an overlying control gate electrode. The control gate electrode is capacitively coupled to the floating gate electrode, such that a voltage applied on the control gate electrode is coupled to the floating gate electrode through a dielectric layer, which is often referred to as the interpoly dielectric. The floating gate flash memory device is programmed by applying a high positive voltage to the control gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating gate electrode.
The control gate electrode is separated from the floating gate electrode by the interpoly dielectric layer which, as noted above, may be an ONO structure or layer. However, as device dimensions continue to be reduced, the electrical thickness of the interpoly dielectric layer between the control gate electrode and the floating gate electrode need to be reduced accordingly. Previously, this has been accomplished by scaling down the physical thickness of the ONO layer. However, as the ONO layer is made physically thinner, leakage current through the ONO layer may increase, which limits the scaling down of the total physical thickness of the ONO layer.
Some of the improvements in devices can be addressed through development of materials and processes for fabricating the ONO layer. Recently, development efforts have focused on novel processes and materials for use in fabrication of dielectric materials, such as for use in the ONO layer. Numerous challenges remain in the fabrication of material layers within these devices. In particular, the ONO layer must be carefully fabricated to avoid an increase in the leakage current, while obtaining an electrically thin layer. Accordingly, advances in ONO fabrication and materials technology are needed to ensure proper charge isolation in ONO structures in floating gate flash memory devices.
In one embodiment, the present invention relates to a floating gate flash memory device including a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.
In another embodiment, the present invention relates to a floating gate flash memory device including a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein each of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a high-K dielectric material.
In one embodiment, the present invention relates to a process for fabrication of a floating gate flash memory device by steps including providing a semiconductor substrate; forming a tunnel dielectric layer overlying the substrate; forming a floating gate electrode overlying the tunnel dielectric layer; forming a bottom dielectric material layer overlying the floating gate electrode; depositing a nitride layer overlying the tunnel dielectric material layer; and depositing a top dielectric material layer overlying the nitride layer, wherein each of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a high-K dielectric material.
Thus, in the present invention, by use of a high-K dielectric material instead of silicon dioxide for the tunnel oxide layer, and at least one of the bottom oxide layer and the top oxide layer, a floating gate flash memory device may be fabricated having reduced dimensions without creation of interface states coming from contamination which could provide charge leakage paths within the modified ONO structure in the device. The present invention provides advantages such as (1) improved coupling between the control gate electrode and the floating gate electrode; (2) reduction of equivalent oxide thickness of the ONO structure; (3) improved data retention and reliability; and (4) the high-K dielectric material layer replacing the silicon dioxide layers allows fabrication of an ONO layer and a tunnel dielectric layer which are physically thicker, resulting in fewer charge leakage paths within these dielectric material layers. A variety of high-K or composite dielectric materials may be used for replacement of silicon dioxide in the in the tunnel dielectric layer and in the bottom and top oxide layers of a modified ONO structure. These dielectric materials may be formed in a nano-laminate, allowing for exact selection of composition, thickness and K value of the dielectric material layers. Thus, the present invention provides an advance in dielectric material layer fabrication technology for floating gate flash memory devices, and ensures proper dielectric separation of the control gate electrode from the floating gate electrode, and proper dielectric separation of the floating gate electrode from the channel, source and drain, while at the same time providing distinct process and economic advantages.
Although described herein in terms of a floating gate flash memory device, the present invention is broadly applicable to fabrication of any semiconductor device that includes an ONO structure and additional dielectric layers in which the equivalent oxide thickness needs to be reduced, while maintaining a physically thick dielectric material layer.
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