1. Field of Invention
The present invention relates to an integrated circuit, and more particularly to a semiconductor device.
2. Description of Related Art
In the semiconductor manufacturing process, a metal interconnect layer is used to electronically couple one device to another device. In general, a dielectric layer is formed as electronic isolation after a semiconductor device is formed, and then a metal interconnect layer including a metal layer and a plurality of contact plugs are formed. For a general device, in order for the subsequent patterning process to be more accurate, a thicker dielectric layer is deposited and then a planarization process is performed thereon. However, for some special devices, the thickness of the dielectric layer has to be thin enough in order to reduce the distance between a device and a metal layer to meet certain special requirements. The dielectric layer is so thin that a planarization process cannot be performed thereon. Ultimately, the rough topography of the un-planarized dielectric layer generates some problems.
FIG. 1 is a schematic top view illustrating a conventional power MOS (metal-oxide-semiconductor) device. FIG. 1A is a schematic cross-sectional view taken along the line I-I of FIG. 1.
Referring to FIGS. 1 and 1A, in the manufacturing process of the power MOS device 10, in order to reduce the thickness of the dielectric layer, the conformal and un-planarized dielectric layer 20 is applied to increase the parasitic capacity between the gate metal pattern 12 and the gate pattern 14; and thus the sustainable load feedback voltage is increased. After the un-planarized dielectric layer 20 is formed, in order to increase the current, the subsequent metal layer used to form the gate metal pattern 12 and the source metal pattern 16 is usually very thick. Due to the very thick metal layer and the rough topography over the substrate, the process window becomes very narrow when the photolithography-and-etching process is performed on the metal layer to form the gate metal pattern 12 and the source metal pattern 16. After the etching process, a portion of the metal 18 (i.e. metal residue) remains on the dielectric layer 20 around the sidewall of the gate pattern 14 and a metal bridge issue is resulted.
USPTO Backgrounds
USPTO Backgrounds