1. Field of the Invention
The present invention relates to a data receiving device provided on a transmission line transmitting a data-base signal, for reproducing a received symbol from a data signal received at the data receiving device, in particular, the present invention relates to a timing recovery circuit provided to the data receiving device and masking circuits associated with the timing recovery circuit.
At the present time, a data receiving device for reproducing a received symbol from a received data signal transferred through a transmission line such as a subscriber line is developed by virtue of remarkable progress in LSI and digital signal processing technique.
When the data receiving device receives the data signal, an analog-to-digital circuit in the data receiving device performs sampling of the received data signal, and a phase of the sampling is shifted so as to produce the received symbol properly. The shift of the sampling phase is performed by using a pre-cursor tap coefficient of an impulse response provided in consideration of characteristics of the data signal to be received and the transmission line for transmitting the data signal. A timing recovery circuit is provided to the data receiving device for producing information, which will be called "sampling phase control information" hereinafter, on control of the sampling phase. Receiving the sampling phase control information, the sampling phase is shifted forward or backward at the analog-to-digital circuit so that the received symbol is reproduced from the received data signal properly. The sampling phase has been required to be controlled correctly and at a high speed as much as possible.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a data receiving device (101) of the related art. As shown in FIG. 1, the data receiving device 101 consists of an analog-to-digital converter (A/D) (1), a feed-forward equalizer (FFE) (2), an impulse response estimating unit (IRE) (3) and a timing recovery circuit (TIM) 4.
When a data signal (Dt) arrives at the data receiving device 101 through a transmission line not depicted in FIG. 1 at a time "t", Dt is fed to A/D 1 for converting Dt to a numerated sampled digital signal with a period (T) of symbols in Dt. The period T will be called a "sampling period" hereinafter. The sampled digital signal is sent to FFE 2 in which the sampled digital signal is equalized in consideration of compensating characteristics of the transmission line and an impulse response to the data signal Dt and the transmission line so that a pre-cursor of the impulse response crosses a zero-cross point of the impulse response. Wherein, the compensating characteristics for the transmission line are considered to compensate signal distortion due to, for example, frequency characteristics of the transmission line, and the impulse response is considered to eliminate intersymbol interference occurring in the data signal transferred through the transmission line. The impulse response will be detailed later in reference to FIG. 2 . The FFE 2 produces an equalized output Xt which is sent to IRE 3. In IRE 3, an intersymbol interference component of Dt is removed from the equalized output Xt and a received symbol a is produced under a decision made in accordance with a main cursor of the impulse response. A pre-cursor signal exhibiting the pre-cursor is also output from IRE 3 to TIM 4 as timing information. Receiving the pre-cursor signal, TIM 4 produces sampling phase control information and sends the information to TIM 4. Receiving the sampling phase control information, the sampling phase is shifted at A/D 1 with the sampling period T repeatedly until at is produced properly.
FIG. 2 shows the impulse response provided in consideration of the transmission line and apparatus connected with the transmission line. As shown in FIG. 2, the impulse response is represented by a train of fractional impulse responses h.sub.-1, h.sub.0, h.sub.1, h.sub.2, h.sub.3, h.sub.4, h.sub.5 . . . separated with the sampling period T.
Generally, when a symbol in a data signal is composed of, for example, square wave signals and transmitted through a transmission line, the data signal is distorted in wave shape, due to characteristics of the transmission line and intersymbol interference. In the data receiving device 101, the former distortion is equalized by FFE 2, however, the latter distortion is equalized by using the impulse response.
In the data receiving device 101, since the received data signal Dt includes the symbols having the sampling period T, it can be considered that the received data signal Dt is equal to convolution of the symbol and the fractional impulse responses h.sub.-1, h.sub.0, h.sub.1, h.sub.2, h.sub.3, h.sub.4, h.sub.5 . . . shown in FIG. 2. In FIG. 2, the fractional impulse response h.sub.0 is called a main cursor which substantially corresponds to a peak response of the impulse response, h.sub.-1 is called a "pre-cursor" which appears just before the main cursor h.sub.0, and h.sub.1, h.sub.2, h.sub.3, h.sub.4, h.sub.5, . . . are called "post-cursors" which appear after the main cursor h.sub.0.
When the impulse response shown in FIG. 2 is provided for the received data signal Dt and the transmission line through which the received data signal Dt is transmitted, it is well known that when the pre-cursor h.sub.-1 is used as a timing information and the sampling phase is controlled by using the timing information until the pre-cursor h.sub.-1 coincides with the zero-cross point, the received data signal Dt can be sampled with an optimum sampling phase.
FIG. 3 is a block diagram of a decision feedback equalizer (DFE) (3A) which is a first example of IRE 3. In FIG. 3, receiving the equalized output Xt from FFE 2, DFE 3A produces the received symbol a and a pre-cursor signal (C.sub.-1 signal) as the timing information.
When DFE 3A receives the equalized output Xt from FFE 2, a subtracter (11) subtracts Rt, which is an intersymbol interference component obtained by using the post-cursors, from the equalized output Xt, producing an equalized output Yt. Receiving the equalized output Yt, a deciding circuit (DECIDE) (12) produces the received symbol at under decision made by using a threshold value obtained from the main cursor.
The equalized output Yt is also sent to a subtracter (13) at which an error component et is produced by subtracting a multiplying result obtained at a multiplier (21.sub.1) by multiplying at by a tap coefficient C.sub.0 of the main cursor, from Yt. After delaying the error component et at a register (14) as much as the sampling period T, a residual error e.sub.T-1 is produced at a subtracter (15) by subtracting an intersymbol interference component due to the pre-cursor, from the delayed et. Wherein, the intersymbol interference component due to the pre-cursor is produced at a multiplier (21) by multiplying at by a tap coefficient C.sub.-1 of the pre-cursor. It can be realized from the above description that the residual error e.sub.T-1 , is an error obtained by subtracting the intersymbol interference components due to the pre-cursor and the post-cursors, from the equalized output Xt.
On the other hand, in DFE 3A shown in FIG. 3, tap coefficients C.sub.-1, C.sub.0, C.sub.1, C.sub.2, . . . are updated in accordance with the following steps: at a register (16.sub.1, 16.sub.2,16.sub.3 . . . ), received symbols a .sub.T-1, a.sub.T-2, a.sub.T-3, . . . are obtained by delaying the received symbol at, a.sub.T-1, a.sub.T-2 . . . as much as a timing period T, respectively; at multipliers (17, 17.sub.1, 17.sub.2 . . . ), multiplied results are obtained by multiplying the residual error e.sub.T-1 by at, a.sub.T-1, a.sub.T-2, . . . respectively; at amplifiers (18, 18.sub.1, 18.sub.2, . . . ), tap coefficient renewal quantity to be used for respective timing is obtained by multiplying respectively the multiplied results by a step size .alpha. which is a parameter for updating the tap coefficients; and at adders (20, 20.sub.1, 20.sub.2, . . . ), the tap coefficients C .sub.-1, C.sub.0, C.sub.1, C.sub.2, . . . are updated by adding the tap coefficient renewal quantity to tap coefficients delayed as much as the sampling timing period T at resistors (19, 19.sub.1, 19.sub.2, 19.sub.3, . . . ), respectively.
Then, at the multiplier 21, the intersymbol interference component due to pre-cursor is obtained by multiplying the tap coefficient C.sub.-1 by the received symbol at, and at a multiplier (21.sub.1), an intersymbol interference component due to the main cursor is obtained by multiplying the tap coefficient C.sub.0 by the received symbol at.
Furthermore, at multipliers (21.sub.2, 21.sub.3,21.sub.4, . . . ), the intersymbol interference components due to the post-cursors are obtained by multiplying the tap coefficients C.sub.1, C.sub.2, C.sub.3, . . . by the received symbols a.sub.T-1, a.sub.T-2, a.sub.T-3, . . . respectively; and at an accumulator (.SIGMA.) (22), the intersymbol interference component Rt is obtained by totaling the intersymbol interference components due to the post-cursors.
The above steps for obtaining intersymbol interference component Rt is based on convolution expressed by ##EQU1## Where Rt is the intersymbol interference component at time t, due to the post-cursors, and other Cn (t) and at are also treated as a function of time t respectively.
On the other hand, the equivalent output Yt can be represented as EQU YtXt-Rt,
the error component et can be represented as EQU et=e.sub.t-1 -at.multidot.C.sub.0 (t),
the residual error e.sub.t-1 can be represented as EQU e.sub.t-1 =e.sub.t-1 -at.multidot.C.sub.-1 (t), and
the step size a can be obtained as EQU Cn(t+1)=Cn(t)+.alpha..multidot.a.sub.T-n-1 .multidot.e.sub.T-1
where n=1.about.N.
The DFE 3A shown in FIG. 3 composes an adaptive FIR (Finite Impulse Response) digital filter which is non-recursive. When adaptive operation of DFE 3A is over, the values of the tap coefficients C.sub.-1, C.sub.0, C.sub.1, C.sub.2, . . . coincide with the fractional impulse responses h.sub.-1, h.sub.0, h.sub.1, h.sub.2, . . . respectively. Therefore, the values of the tap coefficients C.sub.-1, C.sub.0, C.sub.1, C.sub.2, . . . can be used as the fractional impulse responses h.sub.-1, h.sub.0, h.sub.1, H.sub.2, . . . shown in FIG. 2, and the tap coefficient C.sub.-1 can be used as the timing information.
FIG. 4 is a block diagram of a timing estimator (3B) which is a second example of IRE 3 and composed of operation circuits such as a decision circuit (DEC) (26), a delay circuit (DELAY) (27), a multiplier (X) (28) and a mean value producer (MEAN) (29).
When the timing estimator 3B receives the equalized output Xt from FFE 2 (see FIG. 1) at a time "t", DEC 26 decides to produce a received symbol at and sends at to the multiplier 28; the equalized output Xt is also sent to DELAY 27 at which Xt is delayed as much as the sampling period T, producing X.sub.T-1, which is sent to the multiplier 28; the multiplier 28 multiplies at by X.sub.T-1 and produces a signal at.multidot.X.sub.T-1 which is sent to MEAN 29; and receiving at.multidot.X.sub.T-1 MEAN 29 produces a mean value E [at.multidot.X.sub.T-1 ] of the signal at.multidot.X.sub.T-1.
Since the equalized output Xt is expressed by convolution of received symbols and fractional impulse responses, Xt can be expressed similarly to equation (1), as follows: ##EQU2## Where CK such as C.sub.-1, C.sub.0, C.sub.1, C.sub.2, . . . , C.sub.N-1 or CN is a fractional impulse responses. Therefore, the received symbol at can be decided by virtue of C.sub.0 in the same manner as in the description on DFE 3A in reference to FIG. 3.
Substituting the convolution result shown in expression (2) for the mean value E [at.multidot.X.sub.T-1 ], the mean value E [at.multidot.X.sub.T-1 ] is expressed as follows: ##EQU3##
Since the received symbols at, a.sub.T-1, a.sub.T-2, . . . , aT-N and a.sub.T-N-1 are random signals having no auto-correlation, the following mean values in the above expression (3) become zero as: ##EQU4##
Therefore, equation (3) is simplified as follows: EQU E[at.multidot.X.sub.T-1 ]=E[at.multidot.at].about.C.sub.-1
From the above equation, the pre-cursor coefficient C.sub.-1 is given as follows: EQU C.sub.-1 =E[at.multidot.X.sub.t-1 ]/E[at.sup.2 ]. (4)
Since the denominator of the right-hand side of equation (4) is not zero, the numerator of equation (4) should be zero for making the pro-cursor coefficient C.sub.-1 zero. Therefore, as the numerator E [at.multidot.X.sub.T-1 ] becomes zero, the pre-cursor coefficient C.sub.-1 becomes zero. This teaches that the means value E [at.multidot.X.sub.T-1 ] can be used as the timing information. Receiving the mean value E [at.multidot.X.sub.T-1 ], TIM 4 in FIG. 1 performs feedback control to A/D 1 for controlling the sampling phase properly so as to make the mean value zero.
Receiving the pro-cursor tap coefficient C.sub.-1 from DFE 3A or the mean value E [at.multidot.X.sub.T-1 ] from the timing estimator 3B as the timing information, the timing recovery circuit starts to operate so as to produce the sampling phase control information.
FIG. 5 is a block diagram of TIM 4 of the prior art. The TIM 4 consists of a comparator (COMP) (23), an up-down counter (UP-DWN COUNT) (24) and an OR circuit (OR) (25). When the timing information produced from DFE 3A or the timing estimator 3B is sent to TIM 4, COMP 23 compares the timing information with "0" in value. As a result of the comparison, if the value of the timing information is larger than "0", UP-DWN COUNT 24 makes one step increment in counting, and if the value of the timing information is less than "0", UP-DWN COUNT 24 makes one step decrement in counting. When UP-DWN COUNT 24 continues the increment and a counted value exceeds a positive overflow value previously designated, UP-DWN COUNT 24 outputs a forward phase shift signal from a positive overflow terminal (POF), and when UP-DWN COUNT 24 continues the decrement and the counted value falls below a negative overflow value previously designated, UP-DWN COUNT 24 outputs a backward phase shift signal from a negative overflow terminal (NOF). The forward or the backward phase shift signal is sent to A/D 1 as the sampling phase control information.
Since the one step increment or decrement is performed by increasing or decreasing a constant value step by step every the sampling period, TIM 4 continues to send the sampling phase control information to A/D 1, taking a time. The forward and backyard phase shift signals are also sent to OR 25 at which a clear signal is produced and sent back to UP-DWN COUNT 24 every time the phase forward or backward shift signal is sent to A/D 1. In FIG. 5, a terminal named "CLR" is provided to UP-OWN COUNT 24 for receiving the clear signal from OR 25.
In the impulse response in FIG. 2, it can be seen that the sampling phase lags because the fractional impulse response h.sub.-1 has a positive value. In order to control the sampling phase properly, UP-DWN COUNT 24 must produce the forward phase shift signal until the output from COMP 23 becomes less than the positive threshold value.
In TIM 4 of the prior art, the timing information is counted up or down with constant magnitude, between the positive and negative overflow values. This means that TIM 4 performs integrating operation. Since the timing information C.sub.-1 is an estimating value including error, the integrating operation is effective in increasing accuracy of the phase control. Therefore, if attention is focused only on increase of the phase control accuracy, the TIM 4 should have a large time constant in the integration by widening an interval between the positive and negative overflow value. However, at UP-DWN COUNT 24, the counting is performed step by step by counting the constant magnitude regardless of magnitude of the timing information and the shift amount is also limited to constant magnitude. Therefore, when the sampling phase is deviated far from the correct phase, it takes a long time to follow up the deviation by counting up or down. In other words, a frequency tolerance capable of phase tracking through the data receiving device is narrow. Thus, there is contradiction that when the interval between the positive and the negative threshold is widen, the accuracy in the timing recovery increases, however, the frequency tolerance capable of phase tracking becomes narrow. This contradiction has been a problem in the timing recovery circuit of the prior art.
Furthermore, there have been other problems regarding stability of the data receiving device. Since the data receiving device forms a PLL (Phase Locked loop) in regard to the timing recovery for the sampling, the data receiving device becomes unstable when the data receiving device receives no data signal in a long time or a frame for informing that the data receiving device is in a transmitting mode of a time compression multiplex system.
USPTO Backgrounds
USPTO Backgrounds