1. Field of the Invention
The present invention is generally directed to the field of manufacturing semiconductor devices, and, more particularly, to methods for dynamically controlling etch endpoint time, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, FIG. 1 depicts an illustrative semiconductor device, i.e., a transistor 10, that is formed above a semiconducting substrate 12. The transistor 10 is comprised of a gate insulation layer 14, a gate electrode 16, sidewall spacers 18, and doped source/drain regions 20. The transistor 10 is electrically isolated from other similar devices formed above the substrate 12 by the trench isolation region 22. The various structures and components of the transistor 10, as well as the manner in which they are made, are well-known to those skilled in the art and will not be described in any greater detail herein. In a typical integrated circuit device, millions of transistors, such as the transistor 10 shown in FIG. 1, are formed above a semiconducting substrate, thereby resulting in a very densely-packed structure. A typical integrated circuit device includes multiple layers of conductive interconnections, i.e., conductive lines 15 and conductive contacts or vias 17, formed in multiple layers of insulating material 13, e.g., silicon dioxide, etc. The multiple layers of conductive interconnections are the means by which electrical signals propagate throughout the integrated circuit device, thereby allowing the various semiconductor devices, or groups of devices, to perform their intended functions.
The conductive interconnections may be formed from a variety of materials, e.g., aluminum, copper, etc. Recently, copper has become more popular as the choice for these conductive interconnections in high performance integrated circuits due to its lower electrical resistivity as compared to other potential materials, e.g., aluminum. All other things being equal, the lower resistivity of copper interconnections allows an integrated circuit device to operate at faster speeds.
Typically, conductive interconnections comprised of copper are formed in accordance with the following process flow. First, a layer of insulating material, e.g., silicon dioxide, an oxide, an oxynitride, or a material having a dielectric constant less than 5, is formed by a deposition process. Next, openings are formed in the insulating layer using known photo-lithography and etching steps. Thereafter, a thin barrier metal layer, e.g., tantalum, is conformally deposited above the insulating layer and in the openings in the insulating layer. Then, a relatively thin copper seed layer is conformally deposited above the barrier metal layer. A bulk copper layer is then formed across the surface of the insulating layer, and in the openings formed therein, using known electroplating techniques. Lastly, one or more chemical mechanical polishing operations are reformed to remove the excess copper material above the surface of the layer of insulating material.
The process of forming the openings in the layer of insulating material typically involves a two-step etching process, an endpoint etch process followed by a timed, over-etch process. Ideally, the endpoint etch process removes all, or substantially all, of the insulating material within the opening in the layer of insulating material. The endpoint etch process is typically endpointed using an optical technique, e.g., optical spectroscopy, wherein the outgases of the process are optically analyzed to detect for the presence of the underlying copper interconnect, e.g., line, over which the opening is formed. In theory, the optical endpoint detection system indicates when all, or substantially all, of the insulating material is removed from the opening thereby exposing the underlying conductive interconnection. In practice, it is recognized that this initial endpoint process may not completely remove or clear the insulating material from all of the openings in the layer of insulating material. Accordingly, a timed over-etch process is performed, typically for a duration ranging from approximately 15-60 seconds, in an attempt to insure that the openings are all completely clear of the insulating material.
However, the effectiveness of the above-described etching protocol varies across the wafer lots. Such variations may exist for a variety of reasons, e.g., thickness variations in the layer of insulating material, underlying topographical differences, equipment cleanliness, quality of supply gases, etc. Moreover, such across-lot variations in clearing the openings in the layer of insulating material may adversely impact device performance. In some integrated circuit devices, after the devise is substantially complete, it is subjected to an electrical test, a so-called xe2x80x9cvia chain resistance test,xe2x80x9d to determine the overall resistance of the integrated circuit device. The lower this overall resistance, the faster the integrated circuit device will perform. Thus, failure to clear openings in the layer of insulating material, which tends to decrease the area of the opening, tends to increase the resistance of the resulting conductive interconnection, and this increased resistance may be cumulative from the perspective of the overall integrated circuit device.
The present invention is directed to an integrated circuit device that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally direct to methods for dynamically controlling etch endpoint time, and a system for accomplishing sane. In one illustrative embodiment, the method comprises providing a first plurality of semiconducting substrates, each of the substrates having a layer of insulating material formed thereabove, and performing an etch process recipe comprised of an endpoint etch process and a timed over-etch process on each of the first plurality of substrates to form at least one opening in each layer of insulating material. The method further comprises determining a duration of the endpoint etch process performed on the first plurality of substrates, determining a duration of the timed over-etch process of the etch process recipe to be performed on a second plurality of substrates based upon the determined duration of the endpoint etch process performed on the first plurality of substrates, and performing the etch process recipe comprised of the endpoint etch process and the timed over-etch process of the determined duration on the second plurality of semiconducting substrates.
In one illustrative embodiment, the system comprises an etch tool for forming at least one opening in a layer of insulating material formed above each of a first plurality of semiconducting substrates by performing an etch recipe comprised of an endpoint etch process and a timed over-etch process on each of the substrates, and a controller that determines a duration of the endpoint etch process performed on the first plurality of substrates and determines a duration of the timed over-etch process of the etch recipe to be performed on a second plurality of semiconducting substrates based upon the determined duration of the endpoint etch process performed on the first plurality of substrates.
USPTO Backgrounds
USPTO Backgrounds