The present invention relates to a nonvolatile memory device, and to a technique effective if applied to a nonvolatile memory device of a multichip package (MCP) structure comprising, for example, a flash memory chip and a controller chip.
As examples each illustrative of a semiconductor device in which a plurality of semiconductor chips are laminated and sealed with a resin, there have been known those disclosed in Japanese Unexamined Patent Publication No. 2001-102515 (patent document 1) and Japanese Unexamined Patent Publication No. 2001-217383 (patent document 2). Japanese Unexamined Patent Publication No. 2001-102515 is directed to the invention wherein two semiconductor chips identical in size and bonding pads are laminated two or more and wire-bonded between the same and electrodes of a substrate. The present configuration has the problem that wires overlap each other as viewed from above to make it difficult to judge the presence or absence of shorts between the upper and lower wires in a visual inspective process or make it easy to develop a short circuit therebetween. In order to avoid it, the two chips are laid out with being shifted. In the invention of Japanese Unexamined Patent Publication No. 2001-217383, pads of an upper layer chip are provided on one side thereof or adjoining two sides thereof in integrated form to prevent a short circuit between adjoining wires in the upper layer chip, a short circuit with respect to a lower layer chip due to dangling, or a wire break or the like. In the upper layer chip, the corner comprising the one side or two sides such that the length of each of the wires becomes shorter is set so as to adjoin one side or the corner where corresponding pads of a lower layer chip are provided.
USPTO Backgrounds
USPTO Backgrounds