The present invention is directed to packaging for electronic devices, and is particularly directed to an improved package for semiconductor devices. Some commonly available semiconductor devices, such as the TO-220 are ill suited for high voltage circuit applications, such as a switching transistor in the primary side of a switch-mode power supply. A principal shortcoming is in the lead-to-lead spacing. In the TO-220 device, the lead spacing is not sufficiently great to allow adequate creepage on the package of the device itself. Creepage is defined as the shortest distance between two conductive parts as it is measured along an insulated surface. Thus, creepage in a device having two leads extending from an insulating package is the shortest distance between the two leads, as measured along the face of the package. Failures due to insufficient creepage may be caused by the presence of environmental contaminants, such as dust. Such conditions may lead to a short circuit between leads. Such high impedance shorts may cause catastrophic failure of the device and, indeed, may cause failure of the entire circuit in which the device is employed. Generally, shorting is a function of several factors: the working voltage employed in the circuit, the dielectric constant of the insulating medium, and the presence or absence of environmental contaminants.
Insufficient creepage and the potential for high impedance shorts are known. Previously, the solution to the problem has simply been to incorporate a physically larger part in the circuit design for higher voltage or essential circuits. Such larger parts have wider lead-to-lead spacing and, therefore, greater creepage. In today""s market the pressure is for ever smaller, more compact products. In view of this pressure to produce smaller products requiring smaller component circuitry, the previous expedient solution of simply specifying and employing a larger part to obviate creepage problems is no longer a good solution.
Another attempt to solve the creepage problem has been to encase the leads of devices in silicone materials. However, this is not a reliable solution because of the difficulty of handling silicone during manufacturing and assembly operations. Adequate coverage of the leads cannot be guaranteed as silicone has a tendency to migrate. This use of silicone can be deleterious, as silicone tends to contaminate other operations in a manufacturing plant. For example, the printing of labels on components for a product may be seriously negatively impacted by silicone contamination. Further, once silicone contamination has occurred across processes in a manufacturing plant, it is difficult to eliminate.
There is a need for a package which will establish acceptable creepage for high-voltage applications without requiring larger components occupying excessive board area in circuit implementations.
The preferred embodiment of the present invention is an improved package for an electronic device, and especially for a semiconductor device. The semiconductor device includes an apparatus having at least two access leads to facilitate electrical connection of the apparatus within an electrical circuit. The package has generally a closed polyhedral shape presenting a plurality of faces and substantially insulatingly surrounding the apparatus in a manner leaving the at least two access leads uninsulatedly exposed for effecting electrical connection with the apparatus. The at least two access leads extend a distance from at least two exit loci from the package. The at least two exit loci are situated on an exit face of the package and lie generally in a common plane. An intraplanar distance within a common plane is established intermediate each adjacent pair of the at least two exit loci. The improvement comprises configuring the exit face to establish an on-surface path greater than the intraplanar distance intermediate selected adjacent pairs of the exit loci.
The invention provides an improved high-voltage power semiconductor package. By including structure on the face of the package intermediate selected electrical leads of the semiconductor device to increase the on-surface distance between the selected leads, creepage is increased. Increasing creepage increases the potential necessary to short the selected leads. The result is a higher voltage capacity for the semiconductor device without having to use a larger, bulkier device to achieve greater creepage.
The preferred embodiment of the present invention involves providing walls intermediate leads. The provision of walls intermediate leads is an especially attractive embodiment since it would not require adding material to an existing package mold for a part to effect the change. To add the desired walls between leads, one would merely need to appropriately remove some material from the package mold. The removed area would then fill with packaging material during molding, and the result would be manifested in the form of the desired walls.
Alternate embodiments of the present invention may be configured using depressions, or trenches, or grooves intermediate leads. Such alternate embodiments require that material be added to an existing package mold to construct the desired depressions in a finished molded package. Thus, this alternate construction would require the construction of a wholly new mold.
Other alternate embodiments of the present invention may be configured by forming insulating wraps on selected leads during the molding of the package by over-molding package material on the selected leads. The overmolding may be effected on the two outboard leads adjacent the center lead on a three-lead semiconductor device, such as a power transistor. Another construction would have the overmolding being effected only on the center lead of a three-lead device.
It is, therefore, an object of the present invention to provide an improved package for an electronic device which increases creepage in the finished packaged device.
Further objects and features of the present invention will be apparent from the following specification and claims when considered in connection with the accompanying drawings, in which like elements are labeled using like reference numerals in the various figures, illustrating the preferred embodiments of the invention.
USPTO Backgrounds
USPTO Backgrounds