1. Field of the Invention
The disclosed embodiments of the present invention relate to impedance adjustment and delay capacitance adjustment, and more particularly, to an impedance adjustment method and a delay capacitance adjustment method utilizing a predetermined algorithm, and associated apparatus.
2. Description of the Prior Art
Differential impedance of a cable may differ from target impedance due to manufacturing processes, environmental factors or aging. This causes impedance mismatches to emerge between the chip and the cable, which could introduce reflection of transmission data (i.e. echo), affecting the reception in the full duplex mode. In the prior art, an impedance adjustment function is employed to deal with the issue. Different impedance paths may be prepared in advance for selection, wherein all impedance paths may be tested under various situations—for example, when a link sequence is restarted after disconnection—to find out the most appropriate.
Echo cancellers are also popular in the prior art. The echo canceller includes a delay capacitance, which may also vary due to changes in environment. Different delay capacitance paths may be prepared in advance for selection, wherein all delay capacitance paths may be tested under various situations—for example, when a link sequence is restarted after disconnection—to find out the most appropriate.
These exhaustive prior art search methods need to test all built-in impedance paths and delay capacitance paths, which is time consuming and makes it difficult to realize fast connection in applications such as Automotive Ethernet. How to obtain the optimized selection of impedance paths and delay capacitance paths has therefore become an urgent issue in the field.
USPTO Backgrounds
USPTO Backgrounds