The present invention relates to a method of fabricating a thin-film transistor, and more particularly to an improvement in the fabrication method of a thin-film transistor which can simplify the fabrication process, and can produce transistors with little variation of the on-current and off-current.
As the thin-film transistor of the above kind, there has been known one that are equipped, as shown in FIG. 2 to FIG. 4, with a glass substrate (a), a gate electrode (b) formed on the glass substrate (a), a gate insulating layer (c) that covers the gate electrode (b), a first amorphous semiconductor layer (d) deposited on the gate insulating layer (c), a protective layer (e), as needed, provided on the first amorphous semiconductor layer (d) and at the area corresponding to the gate electrode (b) for protecting the first amorphous semiconductor layer (d), a second amorphous semiconductor layer (f) for ohmic contact formed on the first amorphous semiconductor layer (d) and containing trivalent or pentavalent impurity atoms, source/drain electrodes (g), (h) electrically connected to the second amorphous semiconductor layer (f), and a diffusion preventive layer (j) disposed between each of the source/drain electrodes (g), (h) and the second amorphous semiconductor layer (f) for preventing diffusion of the metal constituting the source/drain electrodes (g), (h) into the second amorphous semiconductor layer (f). This thin-film transistor is used for driving, for example, an image sensor, electroluminescence display and liquid crystal display.
The conventional method of fabricating such a thin-film transistor has the processes shown in FIG. 5(A) to FIG. 5(J).
Namely, as shown in FIGS. 5(A) and 5(B), on the glass substrate (a) having the gate electrode (b) formed thereon, there are deposited sequentially an SiN.sub.x insulating coating (c') which is to become the gate insulating layer (c), an amorphous silicon (a-Si) semiconductor coating (d') which is to become the first amorphous semiconductor layer (d), and an SiN.sub.x protective coating (e') which is to become the protective layer (e). Then the protective layer (e) is formed as shown in FIG. 5(C) by selectively removing the protective coating (e').
Next, as shown in FIG. 5(D), an amorphous silicon (a-Si) second amorphous semiconductor layer forming film (f') and a chromium (Cr) diffusion preventive layer forming film (j') are deposited sequentially. Then, after forming a resist film (k.sub.1) in patterned form on the diffusion preventive layer forming film (j') as shown in FIG. 5(E), an etching is performed using an etchant which is a mixture of ammonium cerium nitrate (IV) and perchloric acid to form the diffusion preventive layer (j) by removing the portion of the diffusion preventive layer forming film (j') not being covered by the resist film (k.sub.1). Then, the resist film (k.sub.1) is removed to assume the structure shown in FIG. 5(F).
Then, after forming a patterned resist film (k.sub.2) again on the diffusion preventive layer (j) as shown in FIG. 5(G), the second amorphous semiconductor layer (f) and the first amorphous semiconductor layer (d) are formed as shown in FIG. 5(H) by removing the portion of the second amorphous semiconductor layer forming film (f') not being covered by the resist film (k.sub.2) and the outer portion of the underlying amorphous silicon (a-Si) semiconductor coating (d') by means of an etching that uses a hydrofluoric/nitric acid based etchant.
Further, as shown in FIG. 5(I), the gate insulating layer (c) is formed by selectively removing the SiN.sub.x insulating coating (c') by means of photoetching. Then, as shown in FIG. 5(j), the source/drain electrodes (g), (h) are formed, thereby obtaining the thin-film transistor.
Now, in the conventional method described above, as the etchant for the second amorphous semiconductor layer forming film (f') and the underlying amorphous silicon (a-Si) semiconductor coating (d'), a hydrofluoric/nitric acid based agent is used which can also dissolve chromium and the like used for the diffusion preventive layer (j), so that there is a drawback that if a portion of the diffusion preventive layer (j) is exposed, this portion is also etched at the time of the above-mentioned etching process. Moreover, the resist film that once made a contact with an etchant tends to suffer from the side etching, and therefore, it is necessary to form again the new resist film (k.sub.2) on the diffusion preventive layer (j) as shown in FIG. 5(G).
Therefore, there occurs a problem that the number of fabrication processes must be increased owing to the necessity of two times of the resist film formation processes. Moreover, there is another problem that the operability is diminished due to the requirement that the resist film must be formed on the diffusion preventive layer (j) with high accuracy.
Further, when the position of formation of the resist films (k.sub.2) is deviated to one side due to misalignment as shown in FIG. 6(A), the second amorphous semiconductor layer (f) is formed such that its one end portion extends toward the center of the protective layer (e), with a result that one of the source/drain electrodes (g), (h) and the second amorphous semiconductor layer (f) are connected directly in one portion without an intermediary of the diffusion preventive layer (j). This causes a problem that the on-current and off-current of thin-film transistors obtained have variations depending on an area of the direct connection.
The inventor considers based on his analysis that the above variations are due to the following reasons.
First, when the source/drain electrodes (g), (h) and the second amorphous semiconductor layer (f) are connected directly, the resistance of the second amorphous semiconductor layer (f) is reduced if the metal constituting the electrodes (g), (h) diffuses into the second amorphous semiconductor layer (f). On the contrary, if a portion of the second amorphous semiconductor layer (f) is exposed and is oxidized during the etching process, then its resistance will be increased. In this manner, the condition of electrical connection between the source/drain electrodes (g), (h) and the second amorphous semiconductor layer (f) becomes unstable, so that the electrical connection condition is likely to change even with a slight variation in fabrication conditions.
Further, in the thin-film transistor with the protective layer (e) as shown in FIG. 7, when a voltage is applied between the source/drain electrodes (g) and (h), there is formed an additional channel which serves as a current path in the boundary between the protective layer (e) and the first amorphous semiconductor layer (d) depending upon the kind of material forming the protective layer (e), with a result that the protective layer (e) sometimes traps electrons. Under these circumstances, if there exists a variation in the condition of electrical connection between the source/drain electrodes (g), (h) and the second amorphous semiconductor layer (f) among individual transistors fabricated, then quantity of the electrons trapped by the protective layer (e) will be varied accordingly, causing a variation of current flowing through the first amorphous semiconductor layer (d). This is also considered to contribute to the dispersion of the on-current and off-current among individual thin-film transistors that are fabricated.
On the other hand, in the thin-film transistor with no protective layer as shown in FIG. 8, if there is a variation among individual transistors in the condition of electrical connection between the source/drain electrodes (g), (h) and the second amorphous semiconductor layer (f), then quantity of the electrons trapped in the first amorphous semiconductor layer (d) varies in accordance with a variation in the effective gate length (.alpha.), causing a variation of current flowing through the first amorphous semiconductor layer (d). This is also considered to be responsible for the dispersion of the on-current and off-current.
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USPTO Backgrounds