In general, memory devices are typically designed with no more than two bit error correction. However, during manufacturing some number of memory devices typically experience a higher failure rate than may be correctable with two bit error correction or even three bit error correction. These memory devices are typically discarded and result in lower device yields. Therefore, increasing the number of bits that may be corrected while ensuring accurate functionality of the memory devices may result in increased yields when manufacturing memory devices.
USPTO Backgrounds
USPTO Backgrounds