1. Field of the Invention
This invention relates to a CMOS (Complementary Metal-Oxide Semiconductor) output circuit in a CMOS integrated circuit device having an improved property for preventing latch-up.
2. Description of Related Art
All CMOS circuits have potentially troublesome parasitic elements such as parasitic bipolar transistors and parasitic resistors in its bulk semiconductor body. For example, a pnp parasitic transistor is possible where an n-type substrate, as its base, is formed with a p-well, as its collector, and with a source or a drain of a pMOS transistor, as its emitter. At the same time, an npn parasitic transistor is possible where the p-well as its base is formed with the n-type substrate, as its collector, and with a source or a drain of nMOS transistor, as its emitter. When such a CMOS structure forms an output circuit of an the integrated circuit device, a ground voltage Vss and a power supply voltage Vcc are typically supplied to the sources of the nMOS transistor and the pMOS transistor, respectively, and the drains of the nMOS and pMOS transistors are used for an output terminal of the output circuit. If the output terminal incidentally receives a triggering voltage, which is generally higher than the power supply voltage Vcc or lower than the ground voltage Vss, the parasitic transistors begin to conduct since their junctions between base and emitter are forward-biased. Once both parasitic transistors become conducting, a current continues to flow in a direction from the power supply voltage Vcc to the ground voltage Vss without any further triggering voltage to the output terminal. This phenomenon is known as latch-up, and the CMOS circuits are often permanently damaged by the resulting high currents.
USPTO Backgrounds
USPTO Backgrounds