As the speed and complexity of processors and other integrated circuit (IC) components has increased, the need for high-speed input/output (I/O) and clean power delivery has also increased. Conventional packaging technologies are running into physical limitations, making them unable to meet all the requirements.
Moreover, due to the increasing trends of higher current and high I/O count, using the present techniques drives a substantial increase in pin count, hence an increase in body size and package cost. Also, most central processing units (CPU) currently have about 2.5–6.2 square inches required connector footprint on the CPU substrate, which is limiting and expensive.
One current solution is to have multiple connectors in the logic and power circuitry. This solution, however, introduces a high level of inductance and resistance, which in turn can degrade the signals and lose power.
FIGS. 1a–1c illustrate the state of the current art. FIG. 1a shows a typical land grid array (LGA) socket where both the power and signal contacts areas are homogeneous in contact design and placement. The socket of FIG. 1a includes formed metal contacts 102 to engage a component and a frame 104. FIG. 1b shows a cross-sectional view of the socket shown in FIG. 1a. 
FIG. 1c shows a top view of a standard pin grid array (PGA) zero insertion force (ZIF) socket. The socket of FIG. 1c includes an actuation lever 106 to lock an inserted device in place and a socket grid 108 to receive pins from the inserted component.
Generally, current technology has all I/O and power going through the pins or pads on the CPU package. In some high-end implementations, such as in server computers, an additional power connector on the edge of the CPU substrate may be utilized. This approach also raises inductance, which in turn can degrade the signals significantly.
USPTO Backgrounds
USPTO Backgrounds