It is more and more common to use integrated-circuit chips having through-holes to produce electrical connections from one side to the other and to integrate such chips in complex assemblies of superposed chips. To do this, it has been proposed to produce, on the active sides of the chips of a wafer comprising a plurality of chips, blind holes that are filled with and electrical conductor; to mount this chip-bearing wafer on a thick support wafer by placing the active sides of the chips against this support wafer; to thin the chip-bearing wafer until the conductor that forms then electrical-connection vias is exposed; to assemble other chips on the backside of the thinned chip-bearing wafer, optionally by way of a layer integrating electrical-connection networks and by encapsulating these other chips; to remove the support wafer; to produce an electrical-connection layer on the frontside of the chip-bearing wafer; and finally to dice the resulting wafer so as to singulate the semiconductor devices.
It will be immediately noticed that such a procedure requires many operations and requires the use of a support wafer as a tool on which the semiconductor devices are fabricated.
USPTO Backgrounds
USPTO Backgrounds