1. Field of the Invention
This invention relates to noncontact dynamic operational monitoring testing of integrated circuits, and more particularly relates to a full chip testing procedure by which instantaneous operational voltages at a number of nodes on an integrated circuit are interrogated by pulsed laser induced photoemission at specific times during the chip clock cycle, for result interpretation through voltage discriminated luminescence.
2. Description of the Prior Art
Known techniques for testing internal nodes of integrated circuits, whether carried out by mechanical contact probing or contactless techniques, suffer from the inherently slow speed of any point-by-point measurement. In addition, most of these do not give as reliable a picture of the circuit operation as would a real-time measurement.
The following are representative of the prior art and scientific background:
Copending U.S. patent application of Beha, Dreyfus and Rubloff, Ser. No. 667,506 filed Nov. 1, 1984, entitled NON-CONTACT DYNAMIC TESTER FOR INTEGRATED CIRCUITS, shows a tester which allows testing in vacuum of the dynamic operation and performance of high-speed very large scale integration (VLSI) circuits, including on-chip contactless measurement of AC switching waveforms (picosecond time scales) as well as logic state evaluation (nanosecond time scales) using high energy photons (about 5-6 eV). This technique is based on the phenomenon of photon-induced electron emission (photoelectron emission) from a solid surface into vacuum. In this technique, the voltage of a single circuit node is measured as a function of time during the chip clock cycle.
Copending U.S. patent application of Beha, Dreyfus, Hartstein and Rubloff, Ser. No. 717,409, filed Mar. 29, 1985, now U.S. Pat. No. 4,644,264, entitled PHOTON ASSISTED TUNNELING TESTING FOR PASSIVATED INTEGRATED CIRCUITS, shows a tester which allows testing in air of the dynamic operation and performance of high-speed very large scale integration (VLSI) circuits. This technique employs a transparent insulating passivation layer, often present over the circuit's internal nodes, together with a metal overlayer on top of the insulating layer in order to detect the monitoring signal, based on the phenomenon of photon-assisted tunneling from a metal into an oxide. The voltage of a single circuit node is measured as a function of time during the chip clock cycle.
Copending U.S. patent application of Beha, Dreyfus and Rubloff, Ser. No. 717,407, filed Mar. 29, 1985, now U.S. Pat. No. 4,670,710, entitled NONCONTACT FULL-LINE DYNAMIC AC TESTER FOR INTEGRATED CIRCUITS, shows a tester which allows testing in vacuum of the dynamic operation and performance of high-speed very large scale integration (VLSI) circuits. By producing a line focus with the incident laser light and employing high-speed electron deflection optics for the photoemitted electrons (as exploited in a streak camera), this technique achieves simultaneous measurement of the voltage of a one-dimensional array of internal nodes on a circuit.
These real-time measurements of internal node voltages on a chip fall short of the high testing speed attainable by simultaneous measurement of a two-dimensional array of circuit nodes, which is the object of the present invention.
U.S. Pat. No. 1,957,249, Dantscher, ELECTRON DISCHARGE APPARATUS, May 1, 1934, merely shows electron discharge from electron beam excitation. Electron beam testing methods are known as means for contactless measurement of internal circuit nodes. However, they carry several important limitations. First, they require surface availability of metal conductor test points and are therefore inadequate for testing of passivated circuits. Second, the electron beam causes damage to passivating layer materials such as oxides and must therefore be carefully directed away from such areas. Third, and most crucial, they do not permit simultaneous measurement of an array of circuit nodes.
In our copending patent applications listed above, we described techniques for testing of the dynamic operation and performance of high-speed VLSI circuits. Besides the measurement of AC switching waveforms (picosecond time scales) as part of the verification of hardware design, it is also important and helpful to be able to check that the logic operation of the chip is functionally correct. The ability to test the logic states and AC switching waveforms at internal nodes on the chip becomes increasingly important with high chip complexity and wafer scale integration. This can be accomplished with the laser test methods of our copending U.S. patent applications (Ser. Nos. 667,506, 717,409, and 717,407) with scanning, or with available metal test points at the chip surface, with electron beam methods of by scanning the probe over the chip. Such scanning is time-consuming, making on-line product testing inconvenient, and does not provide a simultaneous test of the circuits on the chip.
The prior art does not teach nor suggest the invention, which permits dynamic real-time testing of a large two-dimensional array of internal circuit node voltages, i.e. "full-chip" testing of logic states and AC switching waveforms, to provide rapid and accurate evaluation of circuit operation.
USPTO Backgrounds
USPTO Backgrounds