1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining process layer thickness using scatterometry measurements.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semi-conductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines that connect the various interconnect structures are commonly formed in trenches defined in the dielectric layers.
A contact is generally used to define an interconnect structure (e.g., comprising polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a via denotes a metal to metal interconnect structure. For contacts and vias, a contact opening is formed in an insulating layer overlying the conductive member. A second conductive layer is then formed over the contact opening and electrical communication is established with the conductive member.
An exemplary semiconductor device 100 is shown in FIG. 1. The semiconductor device 100 includes trenches 110, 120 used to form conductive line interconnect structures and a contact opening 130 used to form a conductive plug interconnect structure defined in a base insulating layer 135. The contact opening 130 communicates with an underlying conductive feature 137 (e.g., polysilicon line) formed in a previous layer of the semiconductor device 100. Prior to filling the trenches 110, 120 and contact opening 130 with a conductive metal (e.g., by electroplating a copper fill layer), the trenches 110, 120 and contact opening 130 are lined with one or more barrier layers 140 and/or seed layers 150. A stop layer 160 is provided for protecting the base insulating layer 135 during a subsequent polishing process used to remove portions of the layers 140, 150 and copper fill layer extending beyond the trenches 110, 120 and contact opening 130. The barrier layer 140 functions to inhibit electromigration in the copper fill layer. Electromigration is the displacement of metal ions in the copper layer due to the current flow in the line. The force of the propagating electrons is commonly referred to as xe2x80x9celectron wind.xe2x80x9d Over long periods of time, voids left behind by displaced ions accumulate. Eventually, an open circuit may occur, causing the semiconductor device to irreparably fail. Commonly used barrier layer materials include tantalum and tantalum nitride. An exemplary barrier layer 140 configuration includes a tantalum nitride layer lining the trenches 110 and contact opening 120 and a tantalum layer overlying the tantalum nitride layer.
The seed layer 150, typically comprising a deposited layer of copper or a copper alloy, is formed over the barrier layer 140 by a physical vapor deposition process (i.e., sputtering). The seed layer 150 is coupled to a voltage source during the subsequent plating of the copper layer to fill the trenches 110, 120 and contact opening 130 to complete the interconnect structures.
Controlling the thicknesses of the barrier and/or seed layers 140, 150 is important for controlling the performance of the completed devices. If the barrier layer 140 has insufficient thickness the protection provided against electromigration is compromised. If the seed layer 150 thickness is not sufficient, the subsequent plating process will leave gaps or voids in the interconnect structure compromising its integrity. If the barrier and/or seed layers 140, 150 are too thick, the aspect ratio of the structure may be increased to a point where the plating process is ineffective and voids or seams form in the copper fill material.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for determining thickness of a process layer. The method includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer and the grating structure with a light source; measuring light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile; and determining a thickness of the process layer based on the reflection profile.
Another aspect of the present invention is seen in a processing line including a metrology tool. The metrology tool includes a light source, a detector, and a data processing unit. The metrology tool is adapted to receive a wafer having a grating structure and a process layer formed over the grating structure. The light source is adapted to illuminate at least a portion of the process layer and the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile. The data processing unit is adapted to determine a thickness of the process layer based on the generated reflection profile.
USPTO Backgrounds
USPTO Backgrounds