(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process for integrating the processes needed to fabricate a capacitor structure, and a transfer gate transistor, on the same semiconductor chip
(2) Description of Prior Art
To reduce processing costs of memory and logic semiconductor devices, comprised with both polysilicon capacitor structures, and transfer gate transistor, polysilicon gate structures, integration of as many process steps, or process sequences, used for both the capacitor and transfer gate transistor is desirable. However although some process sequences allow the desired process integration, deleterious effects, due to the sharing of process steps and sequences can occur. For example if the capacitor bottom plate, and gate structure, of the transfer gate transistor, are formed during the same process sequence, in addition to the formation of source/drain regions, formed self-aligned to the polysilicon gate structure of the transfer gate transistor, the temperature needed for formation of a capacitor dielectric layer, on the surface of the polysilicon bottom plate, of the capacitor, can result in unwanted movement of dopants in the transfer gate transistor region. If the polysilicon gate structure is formed after formation of the polysilicon bottom plate, the topography created by the bottom plate structure may result in difficulties when patterning the polysilicon gate structure, using anisotropic reactive ion etching procedures, resulting in unremoved polysilicon ribbons and residues, possibly resulting in a conductive path allowing leakage or shorts, between specific devices to occur.
This invention will describe a novel process sequence allowing integration of many process steps, and sequences, used for both the capacitor structure and a transfer gate transistor, to be shared. Featured in this invention is the creation of a polysilicon bottom plate, embedded in insulator, formed by a chemical mechanical polishing, (CMP), procedure, prior to formation of a polysilicon gate structure, of a transfer gate transistor. Also featured in this invention is the formation of the well regions, and the source/drain regions, in a epitaxial silicon layer, selectively grown on the semiconductor substrate, in an opening in the same insulator layers that the capacitor bottom plate resides on. This allows, after the growth of a gate insulator layer, on the epitaxial silicon layer, in the transfer gate transistor region, as well as the formation of an capacitor dielectric layer, on the capacitor bottom plate, the simultaneous formation of a polysilicon gate structure, on the gate insulator layer, and of a upper polysilicon plate structure, on the capacitor dielectric layer. Prior art, such as Huang, in U.S. Pat. No. 5,924,011, as well as Chen et al, in U.S. Pat. No. 5,607,873, describe processes for forming a capacitor structure, over a field oxide region, however these prior arts do not describe the key features of this present invention, which include: a polysilicon bottom plate, embedded in an insulator layer, via a CMP procedure; the simultaneous formation of a top polysilicon plate, and a polysilicon gate structure; and the use of a selectively grown epitaxial silicon, for the channel region of the transfer gate transistor.
USPTO Backgrounds
USPTO Backgrounds