1. Field of the Invention
The present invention generally relates to a non-volatile memory and a method of manufacturing the non-volatile memory, and more particularly, to a non-volatile memory having an ONO (Oxide Nitride Oxide) film and a method of manufacturing such non-volatile memory.
2. Description of the Related Art
In recent years, data-rewritable semiconductor devices, such as non-volatile memories, have been generally used. In the field of non-volatile memory technology, development effort is being focused to produce smaller memory cells for use in high-capacity memories.
Among non-volatile memories, floating gate flash memories that accumulate charges in the floating gates have been widely used. However, with smaller memory cells being employed to achieve a higher memory capacity, it is difficult to design such floating gate flash memory devices. As the memory cells in a floating gate flash memory become smaller, the tunnel oxide film must necessarily become thinner. With a thinner tunnel oxide film, the leakage current flowing through the tunnel oxide film increases, causing defects in the tunnel oxide film. As a result, the charges accumulated in the floating gate are lost and the reliability of the flash memory device is decreased.
To counter this problem, flash memories having ONO films of such types as MONOS (Metal Oxide Nitride Oxide Silicon) type and SONOS (Silicon Oxide Nitride Oxide Silicon) type have been developed. In such flash memories, charges are accumulated in a silicon nitride film called a trap layer that is interposed between silicon oxide films, the silicon nitride film being an insulating film. Accordingly, even if there are defects in the tunnel oxide film, charge loss is not caused as easily as in a conventional floating gate flash memory. Furthermore, it is possible to store multi-value bits in the trap layer of a single memory cell, which is advantageous for manufacturing a high-capacity non-volatile memory. Such a flash memory of the prior art having such an ONO film is disclosed in U.S. Pat. No. 6,011,725, for example.
The conventional flash memory having an ONO film (hereinafter referred to as the “prior art”) is now described. FIG. 1 is a top view of a memory cell region of the prior art (excluding a protection film 32, a line 34, an interlayer insulating film 30, and an ONO film 16a). FIG. 2 is an enlarged view of a part of FIG. 1. FIG. 3A is a cross-sectional view of the memory cell region, taken along the line A-A′ of FIG. 2. FIG. 3B is a cross-sectional view of the memory cell region, taken along the line B-B′ of FIG. 2.
As shown in FIGS. 1 and 2, the memory cell region includes source/drain diffusion regions 14 that are formed in a semiconductor substrate 10a and also serve as bit lines extending in the vertical direction, and control gates 20a that are formed on the semiconductor substrate 10a and also serve as word lines extending in the transverse direction. As shown in FIGS. 3A and 3B, the source/drain diffusion regions 14 are diffused regions that are formed through impurity ion implantation to the p-type silicon semiconductor substrate 10a followed by thermal treatment performed on the semiconductor substrate 10a. The source/drain diffusion regions 14 are embedded in the semiconductor substrate 10a. The ONO film 16a is formed on the semiconductor substrate 10a, and the control gates 20a are formed on the ONO film 16a. The portions of the semiconductor substrate 10a that are located below the control gates 20a and are interposed between the source/drain diffusion regions 14 are channels 15a. 
A silicon oxide film such as BoroPhospho Silicated Glass (BPSG) is formed as the interlayer insulating film 30 on the transistors. The line 34 is formed on the interlayer insulating film 30 and is in contact with the source/drain diffusion regions 14 via a contact hole 40. The protection film 32 is formed on the line 34.
The ONO film 16a includes a silicon oxide layer that is a tunnel oxide film, a silicon nitride layer that is a trap layer, and a silicon oxide layer that is a top oxide film. Data writing is performed by inducing a high electric field in the channels 15a, injecting hot electrons to the trap layer on the channels 15a, and accumulating the hot electrons in the trap layer. Since the trap layer is interposed between the silicon oxide films, the charges accumulated in the trap layer are retained. Data erasing may be performed by injecting hot holes generated from the channels 15a to the trap layer or by applying a Fowler-Nordheim (F-N) tunnel current to the tunnel oxide film.
Also, as shown in FIG. 15 of U.S. Pat. No. 6,011,725, charges can be accumulated at two locations in one transistor and, accordingly, two-value data can be stored in one memory cell. Thus, a higher memory capacity can be achieved.
Since the source/drain diffusion regions 14 serve also as bit lines, the memory cells can be miniaturized. However, being formed with diffused regions, the source/drain diffusion regions 14 have a higher resistance than metal. As a result, with the source/drain diffusion regions 14 serving also as bit lines, the data writing and reading characteristics deteriorate. To counter this problem, a bit-line/contact region 42 is provided for each predetermined number of word lines (control gates) 20a, as shown in FIG. 1. In the bit-line/contact regions 42, the source/drain diffusion regions 14 serving also as bit lines are connected to the metal line 34 via the contact hole 40. In this manner, the resistance of the bit lines is lowered to improve the data writing and reading characteristics.
In the prior art, however, it is difficult to make the memory cells smaller. This problem is described in greater detail hereinbelow. In the prior art, the source/drain diffusion regions 14 are formed with diffused regions. Functioning also as bit lines, the source/drain diffusion regions 14 need to extend below the control gates 20a which also function as word lines. Therefore, the source/drain diffusion regions 14 are formed prior to the formation of the control gates 20a. After the formation of the source/drain diffusion regions 14, thermal treatment is carried out during the procedures for forming the control gates 20a and the line 34. Through the thermal treatment, impurities in the source/drain diffusion regions 14 are dispersed in the transverse direction, and each source/drain diffusion region 14 thereby becomes wider. As a result, the channel length becomes smaller. With a smaller channel length, a sufficient area for accumulating charges cannot be secured in the ONO film 16a. To avoid the inconvenience, the distance between each two adjacent source/drain diffusion regions 14 is lengthened, so as to secure a sufficient channel length. In doing so, however, miniaturization of the memory cells becomes difficult.
Meanwhile, when the source/drain diffusion regions 14 are formed, the dose amount and the ion energy for ion implantation are reduced, so as to restrict the impurity dispersion in the transverse direction and increase the channel length. However, the bit line resistance becomes higher, as the source/drain diffusion regions 14 function also as the bit lines. So as not to degrade the data writing and reading characteristics, connecting to the line 34 via the contact hole 40 needs to be performed frequently. To do so, however, a large number of bit-line/contact regions 42 are required, and miniaturization of the memory cells becomes even more difficult.
USPTO Backgrounds
USPTO Backgrounds