1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus having an output driver.
2. Related Art
FIG. 1 is a circuit diagram of an output driver according to the conventional art. The conventional output driver includes a pull-up signal generation unit 10, a pull-down signal generation unit 20, a pull-up pre-driver unit 30, a pull-down pre-driver unit 40, a pull-up main driver unit 50a, and a pull-down main driver unit 60a. 
The pull-up signal generation unit 10 may be configured to receive first data rdata and generate a pull-up pre-drive signal pup, and may include an inverter.
The pull-down signal generation unit 20 may be configured to receive second data fdata and generate a pull-down pre-drive signal pdn, and may include an inverter.
The pull-up pre-driver unit 30 is configured to receive the pull-up pre-drive signal pup and generate a pull-up main drive signal up. The pull-up main drive signal up generated by the pull-up pre-driver unit 30 is a signal which is controlled in slew rate and driving force to drive the pull-up main driver unit 50a. The pull-up pre-driver unit 30 may be configured to include an inverter which can change a driving force through a fuse option, etc.
The pull-down pre-driver unit 40 is configured to receive the pull-down pre-drive signal pdn and generate a pull-down main drive signal dn. The pull-down main drive signal dn generated by the pull-down pre-driver unit 40 is a signal which is controlled in slew rate and driving force to drive the pull-down main driver unit 60a. The pull-down pre-driver unit 40 may be configured to include an inverter which can change a driving force through a fuse option, etc.
The pull-up main driver unit 50a is configured to charge an output node no in response to the pull-up main drive signal up. The pull-up main driver unit 50a may be configured to include a PMOS transistor P.
The pull-down main driver unit 60a is configured to discharge the output node no in response to the pull-down main drive signal dn. The pull-down main driver unit 60a may be configured to include an NMOS transistor N.
The conventional output driver adopts a scheme of controlling slew rates of the pull-up main drive signal up and the pull-down main drive signal dn to control a slew rate of an output signal out. The slew rates of the pull-up main drive signal up and the pull-down main drive signal dn are controlled by configuring the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 to include the inverters which can change driving forces through fuse options, etc. By checking the slew rate of the output signal out and changing the driving forces of the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 depending upon a checking result, the slew rates of the pull-up and pull-down main drive signals up and dn can be controlled.
As stated above, the conventional scheme is to control the slew rates of the pull-up and pull-down main drive signals up and dn to control the slew rate of the output signal out. However, a disadvantage is that changes in the slew rates of the pull-up and pull-down main drive signals up and dn are greater than a change in the slew rate of the output signal out. This means that the changes should be made to sufficiently lengthen the rising times and the falling times of the pull-up and pull-down main drive signals up and dn so as to make a sufficient change in the slew rate of the output signal out.
In the extreme, there may be a case in which the pull-up and pull-down main drive signals up and dn do not make full swings from a power supply voltage level to a ground voltage level, and a jitter may be caused depending upon a data pattern, due to ISI (inter-symbol interference). This problem may lead to deterioration of a timing characteristic of the output signal out and occurrence of a skew between data pads DQs.
FIG. 2 is a block diagram of a semiconductor apparatus including an output driver according to the conventional art. The semiconductor apparatus shown in FIG. 2 includes a pull-up signal generation unit 10, a pull-down signal generation unit 20, a pull-up pre-driver unit 30, a pull-down pre-driver unit 40, a pull-up driver unit 50b, a pull-down driver unit 60b, a data determination unit 70, and an impedance calibration signal generation unit 80.
The semiconductor apparatus shown in FIG. 2 can output data by having a configuration similar to the conventional output driver shown in FIG. 1, and can perform an on-die termination operation by including the data determination unit 70 and the impedance calibration signal generation unit 80.
The pull-up signal generation unit 10 is configured to receive first data rdata and generate a pull-up pre-drive signal pup, and may include an inverter, like the pull-up signal generation unit 10 shown in FIG. 1.
The pull-down signal generation unit 20 is configured to receive second data fdata and generate a pull-down pre-drive signal pdn, and may include an inverter, like the pull-down signal generation unit 20 shown in FIG. 1.
The pull-up pre-driver unit 30 is configured to receive the pull-up pre-drive signal pup and generate a pull-up main drive signal up. The pull-up main drive signal up generated by the pull-up pre-driver unit 30 is a signal which is controlled in slew rate and driving force to drive the pull-up driver unit 50b. Like the pull-up pre-driver unit 30 shown in FIG. 1, the pull-up pre-driver unit 30 may be configured to include a plurality of inverters coupled in parallel and can change a driving force through fuse options, etc.
The pull-down pre-driver unit 40 is configured to receive the pull-down pre-drive signal pdn and generate a pull-down main drive signal dn. The pull-down main drive signal dn generated by the pull-down pre-driver unit 40 is a signal which is controlled in slew rate and driving force to drive the pull-down driver unit 60b. Like the pull-down pre-driver unit 40 shown in FIG. 1, the pull-down pre-driver unit 40 may be configured to include a plurality of inverters coupled in parallel and can change a driving force through fuse options, etc.
The pull-up driver unit 50b is configured to charge an output node no in response to the pull-up main drive signal up. The pull-up driver unit 50b is controlled in the driving force and the internal impedance value thereof in response to a first impedance calibration signal pcode.
The pull-down driver unit 60b is configured to discharge the output node no in response to the pull-down main drive signal dn. The pull-down driver unit 60b is controlled in the driving force and the internal impedance value thereof in response to a second impedance calibration signal ncode.
The data determination unit 70 is configured to generate the first data rdata and the second data fdata in response to an ODT enable signal odten, a first source signal RDO and a second source signal FDO. The data determination unit 70 and the ODT enable signal odten can control the first data rdata and the second data fdata such that the semiconductor apparatus shown in FIG. 2 can perform the on-die termination operation. The detailed configuration of the data determination unit 70 and the on-die termination operation according to the ODT enable signal odten will be described later with reference to FIG. 4.
The impedance calibration signal generation unit 80 is configured to check an impedance value of an external resistor Rz coupled to a ZQ pad and serving as a resistor element with a very small error, and generate the first impedance calibration signal pcode and the second impedance calibration signal ncode depending upon the checking result. The first impedance calibration signal pcode and the second impedance calibration signal ncode are signals which are respectively inputted to the pull-up driver unit 50b and the pull-down driver unit 60b and control driving forces and internal impedances of the pull-up driver unit 50b and the pull-down driver unit 60b. 
Impedance calibration (ZQ calibration) indicates a procedure of generating pull-up and pull-down codes which are changed according to a process-voltage-temperature (PVT) variation. A resistance value of an on-die termination device (a termination resistance value of an output driver side or a termination resistance value of an input driver side in the case of a memory apparatus) is controlled using the pull-up and pull-down codes generated as a result of the impedance calibration, that is, the first and second impedance calibration signals pcode and ncode. The first and second impedance calibration signals pcode and ncode are signals which can have different number of bits depending upon a semiconductor apparatus.
In general, each of the first and second impedance calibration signals pcode and ncode comprises 3 to 6 bits in the case of a semiconductor memory apparatus (6 bits in the case of a DDR3 DRAM). For the sake of convenience in explanation, it will be exemplified in the present specification that each of the first and second impedance calibration signals pcode and ncode has 3 bits.
The conventional semiconductor apparatus shown in FIG. 2 operates in a data output mode or an on-die termination mode in response to the ODT enable signal odten. The data output mode is a mode in which the semiconductor apparatus performs an operation of outputting data, and the on-die termination mode is a mode in which the semiconductor apparatus simultaneously charge and discharge the output node no in such a way as to fix a voltage of the output node no in a high impedance (Hi-Z) state to a specified level and prevent occurrence of a far end reflection phenomenon in a signal when an input driver sharing a data pad DQ receives data through the data pad DQ.
If the ODT enable signal odten is deactivated, or deasserted, the semiconductor apparatus operates in the data output mode, and charges or discharges the output node no in response to the first source signal RDO and the second source signal FDO and outputs the output signal out through the data pad DQ. At this time, the data determination unit 70 generates the first source signal RDO and the second source signal FDO as the first data rdata and the second data fdata.
If the ODT enable signal odten is activated, or asserted, the semiconductor apparatus operates in the on-die termination mode, and simultaneously charges and discharges the output node no regardless of the first source signal RDO and the second source signal FDO. Accordingly, an on-die termination effect for the output node no is produced.
At this time, the data determination unit 70 sets and outputs the first data rdata and the second data fdata such that the pull-up driver unit 50b and the pull-down driver unit 60b can simultaneously charge and discharge the output node no. In order to maximize the on-die termination effect for the output node no, a pull-up current of the pull-up driver unit 50b and a pull-down current of the pull-down driver unit 60b should match each other. To this end, the pull-up driver unit 50b and the pull-down driver unit 60b receive the first impedance calibration signal pcode<0:2> and the second impedance calibration signal ncode<0:2> outputted from the impedance calibration signal generation unit 80 and are controlled such that their driving forces match each other.
FIG. 3 is a circuit diagram illustrating the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG. 2. The pull-up driver unit 50b is configured such that three PMOS transistor groups, each group comprising a pair of PMOS transistors coupled in series, are coupled in parallel. In the pull-up driver unit 50b shown in FIG. 3, three PMOS transistors 51, 53, and 55 are turned on in response to the pull-up main drive signal up. Three PMOS transistors 52, 54, and 56 are respectively coupled in series to the three PMOS transistors 51, 53, and 55, are turned on in response to respective bits of the first impedance calibration signal pcode<0:2>.
The three PMOS transistor groups, which are coupled in parallel, are coupled to the output node no through a resistor 57. The pull-up driver unit 50b configured as shown in FIG. 3 charges the output node no according to the pull-up main drive signal up, and the driving force of the pull-up driver unit 50b, that is, a charging current for the output node no is changed depending upon the first impedance calibration signal pcode<0:2>.
The pull-down driver unit 60b may be configured to include a plurality of NMOS transistors such that the pull-down driver unit 60b has a configuration similar to that of the pull-up driver unit 50b. The pull-down driver unit 60b is configured such that three NMOS transistor groups, each group comprising a pair of NMOS transistors coupled in series, are coupled in parallel. In the pull-down driver unit 60b shown in FIG. 3, three NMOS transistors 63, 65, and 67 are turned on in response to the pull-down main drive signal dn. Three NMOS transistors 62, 64, and 66, which are respectively coupled in series to the three NMOS transistors 63, 65, and 67, are turned on in response to respective bits of the second impedance calibration signal ncode <0:2>.
The three NMOS transistor groups, which are coupled in parallel, are coupled to the output node no through a resistor 61. The pull-down driver unit 60b configured as shown in FIG. 3 discharges the output node no according to the pull-down main drive signal dn, and the driving force of the pull-down driver unit 60b is changed depending upon the second impedance calibration signal ncode<0:2>.
In this way, the termination resistance values, that is, the driving forces of the pull-up driver unit 50b and the pull-down driver unit 60b, are controlled according to the first impedance calibration signal pcode<0:2> and the second impedance calibration signal ncode<0:2> in such a manner that the driving forces match each other.
FIG. 4 is a circuit diagram illustrating the data determination unit 70 shown in FIG. 2. The data determination unit 70 includes a first data generation section 71 and a second data generation section 72.
The first data generation section 71 includes a PMOS transistor 71-2 and an NMOS transistor 71-3 which are configured as an inverter and are turned on by the first source signal RDO. The PMOS transistor 71-2 is coupled in series with a PMOS transistor 71-1 which is coupled to a power supply voltage Vcc and is activated by the ODT enable signal odten such that a current path from the power supply voltage Vcc is formed through the PMOS transistor 71-1.
The NMOS transistor 71-3 is coupled in series with an NMOS transistor 71-4 which is coupled to a ground voltage Vss and is activated by an inverted signal odtenb of the ODT enable signal odten such that a current path to the ground voltage Vss is formed through the NMOS transistor 71-4. A PMOS transistor 71-5 is activated by the inverted signal odtenb of the ODT enable signal odten such that a current path is formed from the power supply voltage Vcc to a node nt to which the PMOS transistor 71-2 and the NMOS transistor 71-3 are commonly coupled.
An inverter 71-6 inverts a voltage of the node nt and outputs the first data rdata. If the ODT enable signal odten is deactivated to a low level, the PMOS transistor 71-5 is turned off and the PMOS transistor 71-1 and the NMOS transistor 71-4 are turned on such that the PMOS transistor 71-2 and the NMOS transistor 71-3 perform an inverter operation for the first source signal RDO. Accordingly, if the ODT enable signal odten is deactivated to the low level, the first data generation section 71 outputs the first source signal RDO as the first data rdata.
Conversely, if the ODT enable signal odten is activated to a high level, the PMOS transistor 71-5 is turned on and the PMOS transistor 71-1 and the NMOS transistor 71-4 are turned off such that the PMOS transistor 71-2 and the NMOS transistor 71-3 cannot form a current path to the node nt. A charging operation from the power supply voltage Vcc to the node nt is performed through the PMOS transistor 71-5. Accordingly, if the ODT enable signal odten is activated to the high level, the first data generation section 71 outputs the first data rdata to a low level.
If the ODT enable signal odten is deactivated to the low level, the second data generation section 72 outputs the second source signal FDO as the second data fdata, and if the ODT enable signal odten is activated to the high level, the second data generation section 72 outputs the second data fdata to a high level. Since the second data generation section 72 may be configured similarly to the first data generation section 71 shown in FIG. 4, detailed description thereof will be omitted herein.
In the data output mode, if the ODT enable signal odten is deactivated to the low level, the first source signal RDO is outputted as the first data rdata as described above, and the second source signal FDO is outputted as the second data fdata. Accordingly, the pull-up signal generation unit 10, the pull-down signal generation unit 20, the pull-up pre-driver unit 30, and the pull-down pre-driver unit 40 shown in FIG. 2 generate the pull-up main drive signal up by controlling the driving force of the first data rdata and generate the pull-down main drive signal dn by controlling the driving force of the second data fdata.
Further, the pull-up driver unit 50b or the pull-down driver unit 60b shown in FIG. 3 charges or discharges the output node no in response to the pull-up main drive signal up or the pull-down main drive signal dn. The driving forces of the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG. 3 are changed by virtue of the PMOS transistors 52, 54 and 56 and the NMOS transistors 62, 64 and 66 which are turned on, respectively, in response to the first impedance calibration signal pcode<0:2> and the second impedance calibration signal ncode<0:2>. The charging and discharging operations for the output node no are alternately performed.
Therefore, while the pull-up driver unit 50b is activated in response to the pull-up main drive signal up and charges the output node no, the pull-down driver unit 60b is deactivated in response to the pull-down main drive signal dn and does not discharge the output node no. Conversely, while the pull-down driver unit 60b is activated in response to the pull-down main drive signal dn and discharges the output node no, the pull-up driver unit 50b is deactivated in response to the pull-up main drive signal up and does not charge the output node no.
In the on-die termination mode, if the ODT enable signal odten is activated to the high level, the first data rdata is outputted to the low level and the second data fdata is outputted to the high level as described above. Accordingly, the pull-up signal generation unit 10, the pull-down signal generation unit 20, the pull-up pre-driver unit 30, and the pull-down pre-driver unit 40 shown in FIG. 2 generate the pull-up main drive signal up to the low level and the pull-down main drive signal dn to the high level.
Accordingly, the PMOS transistors 51, 53, and 55 and the NMOS transistors 63, 65, and 67 of the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG. 3 are turned on. Therefore, the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG. 3 are changed in driving forces by virtue of the PMOS transistors 52, 54 and 56 and the NMOS transistors 62, 64 and 66 which are turned on, respectively, according to the first impedance calibration signal pcode<0:2> and the second impedance calibration signal ncode<0:2>, and simultaneously charge and discharge the output node no, thereby performing the on-die termination operation. In general, such an on-die termination operation is performed while the input driver sharing the DQ pad receives data.
The conventional semiconductor apparatus shown in FIGS. 2 through 4 adopts the scheme of controlling the slew rates of the pull-up and pull-down main drive signals up and dn so as to control the slew rate of the output signal out in the data output mode, similarly to the conventional output driver shown in FIG. 1. The slew rates of the pull-up and pull-down main drive signals up and dn are controlled by configuring the pull-up pre driver unit 30 and the pull-down pre-driver unit 40 to include a plurality of inverters coupled in parallel and which can change driving forces through fuse options, etc.
In the conventional semiconductor apparatus, by checking the slew rate of the output signal out and controlling the driving forces of the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 through fuse cutting, etc. according to a checking result, the slew rates of the pull-up and pull-down main drive signals up and dn are controlled.
The plurality of inverters for constituting the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 include a plurality of transistors for performing a pull-up operation and a plurality of transistors for performing a pull-down operation. According to this fact, in the conventional semiconductor apparatus, the slew rate characteristic of the output signal out is markedly changed depending upon the characteristics of the plurality of transistors for performing the pull-up operation and the plurality of transistors for performing the pull-down operation which constitute the pull-up pre-driver unit and the pull-down pre-driver unit 40. The conventional semiconductor apparatus has a disadvantage in that characteristics markedly change depending upon a PVT variation (process, voltage, temperature variation).
Also, in the case where the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 are configured to include the plurality of inverters coupled in parallel and which can change driving forces through fuse options, etc., since the fuse options are component elements which occupy a relatively large area, integration of the semiconductor apparatus may be adversely influenced.
Further, in the conventional semiconductor apparatus, a disadvantage is caused in that degrees to which the slew rates of the pull-up and pull-down main drive signals up and do should be changed to control the slew rate of the output signal out in the data output mode are greater than a degree to which the slew rate of the output signal out to be controlled should be changed.
This means that rising times and falling times of the pull-up and pull-down main drive signals up and dn should be changed to be sufficiently lengthened so as to calibrate the slew rate of the output signal out in conformity with a PVT variation. In the extreme, there may be a case in which the pull-up and pull-down main drive signals up and dn do not make full swings from a power supply voltage level to a ground voltage level, and a jitter may be caused depending upon a data pattern, due to ISI (inter-symbol interference). This problem may lead to the deterioration of a timing characteristic of the output signal and the occurrence of a skew between data pads DQs.
USPTO Backgrounds
USPTO Backgrounds