(1) Field of the Invention
The present invention relates to an apparatus and a method for memory management, and especially to technology for leveling degrees of degradation of a memory device at locations resulting from accesses made to the locations.
(2) Description of the Related Art
Memory devices of a certain type have a characteristic that a location in a memory area degrades as a result of a data erase operation performed to the location. Such memory devices include flash memory devices. When a number of erase operations are performed intensively to a specific location of a flash memory, the specific location degrades outstandingly and eventually fails to store data. As a result, the memory device comes to the end of its usable life earlier than expected.
For this reason, a flash memory device requires memory management for distributing erase operations over the entire memory area of the flash memory device to maximize its usable life.
Due to its structure, a flash memory device has access constraints that bits may be set on an individual basis, but the bits once set need to be reset collectively in units called physical blocks.
For this reason, an access to a flash memory device is often made in units of physical blocks. Typically, the flash memory device writes data into an empty physical block in which all the bits are reset, by setting individual bits in the physical block as required. When the data is no longer needed, the flash memory device erases the data by resetting all the bits in the physical block collectively at the same time. Consequently, the physical block is available again for a next write operation.
In the above process, each bit constituting a physical block of the flash memory device degrades all at once every time the bits are reset to erase data.
JP Unexamined Patent, Application Publication No. 08-016482, for example, discloses a memory management technique made in view of the above-noted access constraints and degradation characteristics of a flash memory device.
FIG. 24 illustrates mapping according to the above conventional memory management technique between logical blocks, which are units of access from a super ordinate device, and physical blocks of a flash memory device.
According to the above technique, the flash memory device keeps counts of write operations and erase operations separately for each logical block.
When instructed to write data to a logical block having a large write count (i.e., frequently accessed), the flash memory device maps the logical block to an empty physical block having a small erase count (i.e., less degraded), and writes the data to the empty physical block.
As a result of this write operation, the number of empty physical blocks having a small write count decreases by one. Therefore, the flash memory device selects one currently used physical block having a small erase count, copies data stored in the selected physical block to another empty physical block, and subsequently erases the data in the selected physical block all at once. Consequently, there is another empty physical block having a small erase count.
Through the series of the above operations, all the physical blocks are made to have substantially even write counts, thereby avoiding a specific physical block degrading intensively. This leads to maximize the usable life of the flash memory.
In recent years, FeRAM (Ferroelectric Random Access Memory) devices, which are a future alternative to flash memory devices, are proceeding toward commercialization.
FeRAM devices are so structured to allow individual bits to be set or reset both on a bit-by-bit basis. Thus, an FeRAM device may be accessed on a bit-by-bit basis (practically, in units of a few bytes, which are the width of a bus).
In an FeRAM device, each bit degrades individually every time when the bit is set or reset as well as when the bit is referenced.
Therefore, in order to maximize its usable life, an FeRAM device also requires memory management to distribute write operations and read operations over an entire memory area of the memory device.
Unfortunately, however, the above conventional memory management for a flash memory is not applied to an FeRAM device without causing the following problems.
First of all, the conventional technique is made on the understanding that the data write operations are the only cause of degradation, and thus insufficient to correctly evaluate degradation of an FeRAM device because the degradation is caused also by a data read operation.
Second of all, the conventional technique is made based on the understanding that degradation takes place in units of a physical block and thus without consideration that degradation degrees may be nonuniform within one physical block. For this reason, the conventional technique is insufficient to suppress local degradation that may take place within one physical block of an FeRAM device due to its random access capability.
Lastly, although it is preferable to take some measures to reduce the absolute number of accesses especially in the case of an FeRAM, which is capable of fast access, the conventional technique fails to address the need.
USPTO Backgrounds
USPTO Backgrounds