This invention relates to dual port memory circuits, and more particularly, to dual port memory circuits that have shared write drivers and sense amplifiers.
A configurable memory block in field programmable gate array (FPGA) is usually built to support various read and write operation modes, such as true dual port (TDP), simple dual port (SDP), and single port (SP) modes. The operation mode is configured depending on the user application. A TDP memory supports two write operations, one read and one write operation, or two read operations at one time.
A typical dual port memory has two independent input and output data paths and address decoders. A dual port memory block also has two independent write bitline drivers and two independent sense amplifiers that support two simultaneous write or two simultaneous read operations on a single column of memory cells. A SDP memory supports one read and one write operation at the same time. A SDP memory can be built from a TDP memory by using one port to write and the other port to read.
The number of input and output paths of a configurable memory block in a FPGA fabric is fixed. The maximum data width that can be supported in different operation mode varies. For example, if the number of the input and output paths for a memory block is 36 each, the maximum data width that can be supported in TDP mode is 18 bits, and the maximum data width that can be supported in SDP mode is 36 bits. Hence, a configurable memory in a FPGA fabric often supports an N-bit data width for TDP mode, and 2N-bit data width for SDP mode to fully utilize the available input/output path resources.
A typical configurable memory block that supports N-bit TDP and 2N-bit SDP modes includes an input/output path with input and output registers, and other logics to control the input and output data path. Two independent column decoders, called Port A and Port B column decoders, are used for TDP and SDP mode operation. The Port A column decoder controls which column of memory cells to access through Port A decoded from the Port A column address. The Port B column decoder controls which column of memory cells to access through Port B decoded from the Port B column address.
A width decoder decodes the configurable input and output data width to the memory array. Together with the column decoder, the input and output data is mapped to the correct memory column. A sense amplifier block includes precharge circuitry and the actual sense amplifiers. The differential bitlines are pre-charged to a high value before read. During evaluation, one of the differential bitlines starts to discharge. The sense amplifier senses and amplifies the differential voltage.
Write driver circuitry includes the tri-state write drivers with other write control logic. Two independent row decoders (for Port A and Port B) are used to control which row of memory cells to access for each port. The memory array is organized as M rows×36 columns of dual port RAM cells.
Each column of the RAM cells is accessible through a Port A write driver, a Port B write driver, a Port A sense amplifier, a Port B sense amplifier, and the Port A and Port B column and row decoder. Each port has 36 write drivers and 36 sense amplifiers to access 36 bitlines associated with each port. Hence, there are total of 72 write drivers and 72 sense amplifiers in one memory block.
When the memory block is configured in TDP, the maximum data width is 18 bits for each port. 18 out of the 36 input paths are used for the Port A input data, and the other 18 input paths are used for the Port B input data. The 18-bit input data for each port is fed to 18 of the 36 write drivers for each port. Only 18 out of the 36 write drivers for each port are enabled at one time during a write operation. For the output path, 18 out of the 36 outputs are used for Port A output data, and the other 18 outputs are used for Port B output data. Only 18 out of the 36 sense amplifiers are enabled for each port during read.
When the memory block is configured in SDP mode, the maximum data width is 36 bits. Port A is always used as the write port, and Port B is always used as the read port. A maximum of 36 bits of data is written to the RAM array through the 36 Port A write drivers. Writing in SDP is only done through the Port A bitlines. Port B write drivers are always disabled in this mode. 36-bit data is read from the array through the 36 Port B sense amplifiers. Reading in SDP is only done through Port B bitlines. Port A sense amplifiers are always disabled in this mode.
There are total 72 write drivers and 72 sense amplifiers in this design. The write drivers and sense amplifiers are usually large devices that occupy large layout area that make the bit per area density number larger. The overhead becomes more significant for a chip that is area or cost sensitive. Although there are 72 write drivers and 72 sense amplifiers in this design, only as many as 36 write drivers and 36 sense amplifiers are active at any time during a read or write operation. In TDP mode, up to 18 Port A write drivers, 18 Port B write drivers, 18 Port A sense amplifiers, and 18 Port B sense amplifiers are active. In SDP mode, up to 36 Port A write drivers and 36 Port B sense amplifiers are active.
Therefore, there is a need to provide dual port memory blocks that provide TDP and SDP operation that has a reduced layout area overhead.
USPTO Backgrounds
USPTO Backgrounds