Microelectronic devices are used in computers, communications equipment, televisions and many other products. Typical microelectronic devices include processors, memory devices, field emission displays and other devices that have circuits with small, complex components. In current manufacturing processes, the components of such circuits are generally formed on a microelectronic substrate or wafer with conductive, insulative and semiconductive materials. Fifty to several hundred microelectronic devices are typically formed on each microelectronic substrate, and each microelectronic device may have several million components.
Because fabricating microelectronic devices generally involves forming electrical components at a number of layers and locations, microelectronic devices generally have many conductive features to couple the various components together.
The method by which the components of an integrated circuit are interconnected involves the fabrication of metal strips that run across an oxide layer in the regions between rows of transistors. However, the strips, together with the oxide beneath the strips, form gates of parasitic MOS transistors and diffused regions adjacent the strips form sources and drain regions, respectively, of the parasitic MOS transistors. The threshold voltage of such parasitic transistors must be kept higher than any possible operating voltage so that spurious channels will not be inadvertently formed between the devices. In order to isolate MOS transistors, then, it is necessary to prevent the formation of channels in the field regions, implying that a large value of V.sub.T is needed in the field regions.
Implementing electronic circuits involves connecting isolated devices through specific electrical paths. When fabricating silicon integrated circuits it must therefore be possible to isolate devices built into the silicon from one another. These devices can subsequently be interconnected to create the specific circuit configurations desired. Isolation technology is one of the most critical aspects of fabricating integrated circuits. Hence, a variety of techniques have been developed to isolate devices in integrated circuits. These techniques balance competing requirements, such as minimum isolation spacing, area of footprint, surface planarity, process complexity, and density of defects generated during fabrication of the isolation structure.
One of the most important techniques developed is termed LOCOS isolation (for LOCal Oxidation of Silicon), which involves the formation of a semi-recessed oxide in the nonactive (or field) areas of the substrate for use with PMOS and NMOS integrated circuits. Conventional LOCOS isolation technologies reach the limits of their effectiveness as device geometries reach submicron size. Modified LOCOS processes such as trench isolation have had to be developed to deal with these smaller geometries.
Refilled trench structures have been used as a replacement for conventional LOCOS isolation techniques. Trench/refill approaches for isolation applications generally fall into the following three categories: shallow trenches (less than 1 micron); moderate depth trenches (1-3 micron); and deep, narrow trenches (greater than 3 micron deep, less than 2 micron wide). Shallow, refilled trenches are used primarily for isolating devices of the same type, and hence they can be considered as replacements for LOCOS isolation. An example of a shallow trench isolation structure is shown in FIG. 1.
The conventional shallow trench isolation structure 10 shown in FIG. 1 is fabricated on a microelectronic substrate 20. Gate structures 100 and 300 are formed on the substrate 20 from a pad/gate oxide layer 30, a first gate layer 40, a second gate layer 70 and a silicide layer 80. A trench 22 formed in the substrate 20 is filled with a silicon oxide 60, to form the shallow trench isolation structure or isolation pad 400. An isolated component 200 is fabricated on the isolation pad 400, the isolated component 200 comprising the second gate layer 70 and the silicide layer 80. Oxide spacers 91-94 are then formed about the gate structures 100 and 300, the isolated component 200 and the isolation pad 400. The oxide spacers 91-94 protect the components from contact with other conductive components, as well as, providing gentle slopes to improve step coverage when applying additional layers. Generally, the less severe the slope, the better the coverage.
Due to the need to define gentle slopes from the relatively tall gate structures 100, 300, the isolated component 200, and the isolation pad 400, the spacers 91-94 take up a large amount of area on the microelectronic substrate 20. Continued progress in microelectronic fabrication requires that isolation structures be as small as possible and take up a minimum of area on the microelectronic substrate. Any reduction in the size of the isolation structures will provide great benefits in semiconductor manufacture.
USPTO Backgrounds
USPTO Backgrounds