The invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a clock divider circuit with duty cycle correction that adds only a minimal delay to the clock path.
Digital circuits such as board level systems and integrated circuit (IC) devices, including programmable logic devices (PLDs) and microprocessors, use clocking signals for a variety of reasons. For example, synchronous systems use global clock signals to synchronize various circuits across the board or IC device.
However, as the complexity of digital circuits increases, clocking schemes for synchronous systems become more complicated. Many complex digital circuits such as PLDs and microprocessors use multiple clock signals at different frequencies. For example, in some PLDs, some of the programmable logic blocks can be operated at a first clock frequency while other logic blocks are operated at a second clock frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals. However, clock generating circuits typically consume a large amount of device or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are often used to generate clock signals of lower frequency from an input clock signal.
FIG. 1 shows a conventional clock divider 100 that receives an input clock signal ICLK and generates a divided-by-two clock signal CLKD2, a divided-by-four clock signal CLKD4, and a divided-by-eight clock signal CLKD8. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Clock divider 100 comprises a 3-bit counter 110. Input clock signal ICLK is applied to the clock terminal of 3-bit counter 110. Counter 110 drives clock signals CLKD2, CLKD4, and CLKD8 on output terminals O0, O1, and O2, respectively. Output terminals O0 through O2 provide the least significant bit through the most significant bit of 3-bit counter 110, respectively.
FIG. 1A is a timing diagram for clock divider 100 of FIG. 1. As can easily be seen from FIG. 1A, if input clock signal ICLK has a clock period P, then divide-by-two clock signal CLKD2 has a clock period of 2P. Similarly, divide-by-four clock signal CLKD4 has a period of 4P, and so forth. Thus, the frequency of clock signal CLKD2 is half the frequency of input clock signal ICLK, the frequency of clock signal CLKD4 is one-fourth the frequency of signal ICLK, and so forth.
As illustrated by FIGS. 2 and 3, including a clock divider in an IC device typically carries a timing penalty, even when the clock divider is disabled. FIG. 2 shows a clock driver circuit 200 in an IC where a clock divider is not included. Clock driver circuit 200 includes a driver 202 that accepts an input clock signal from clock pad 201, and applies the signal to clock tree 203. FIG. 3 shows a second clock driver circuit 300 that includes an optional clock divider 303. The designer can either include clock divider 303 in the circuit, or bypass the clock divider, under the control of multiplexer 304.
FIG. 3 clearly shows that whether or not the clock divider is included in the clock path, there is an additional delay D310 in the circuit of FIG. 3 compared to that of FIG. 2. When clock divider 303 is bypassed, there is additional delay through signal line BYPASS and a propagation delay through multiplexer 304. When clock divider 303 is included in the circuit, the propagation delays of both clock divider 303 and multiplexer 304 are added to the clock path.
If a clock divider such as that shown in FIG. 1 is placed into the clock driver circuit of FIG. 3, the result is a clock tree driven by a flip-flop (from 3-bit counter 110 of FIG. 1) through a multiplexer (e.g., multiplexer 304 of FIG. 3). Clearly, neither a flip-flop nor an unbuffered multiplexer have the drive capability to drive a large clock treexe2x80x94the resulting clock signal would be unacceptably slow and have a very high skew. Therefore, multiplexer 304 is typically buffered. The delay through the clock buffer is also added to the clock path.
FIG. 4 shows another optional capability that is often included in clock driver circuits, that of optionally inverting the input clock signal. Clock driver circuit 400 includes inverters 402, 405 and CMOS passgates 403, 404. A clock signal on clock pad 401 is provided to passgate 404, and also to passgate 403 through inverter 402. When select signal TRUE is high, the true (non-inverted) clock signal passes through passgate 404 to clock tree 406. When select signal TRUE is low, the complement (inverted) clock signal passes through passgate 403 to clock tree 406.
FIG. 5 shows a first known clock divider circuit 500 that has the capabilities of both FIGS. 3 and 4. Input clock signal CLKIN drives internal node INT either through passgate 503 (when select signal TRUE is high), or through inverter 501 and passgate 502 (when select signal TRUE is low). Thus, either the true or the complement version of input signal CLKIN is selected by select signal TRUE. Internal node INT then passes the selected signal to clock divider 505 and multiplexer 506. Multiplexer 506 selects the output of clock divider 505 when select signal DIV is high, and internal signal INT when select signal DIV is low.
As can be seen from FIG. 5, the fastest path through clock divider circuit 500 still includes the delay through passgate 503, internal node INT, and multiplexer 506.
FIG. 6 shows a second known clock divider circuit 600. Circuit 600 does not allow the inversion and division circuits to be used at the same time. There are three paths through clock divider circuit 600. A first, non-inverting path passes input clock signal CLKIN through passgate 605 when select signal SELTRUE is high. A second, inverting path passes input clock signal CLKIN through inverter 602 and passgate 604 when select signal SELCOMP is high. A third, non-inverting but divided path provides input clock signal CLKIN to clock divider 601, the output of which passes through passgate 603 when select signal SELDIV is high. At most one of select signals SELTRUE, SELCOMP, and SELDIV can be high at any given time.
The minimum path delay through clock divider circuit 600 is less than that of circuit 500 of FIG. 5, because only one passgate (605) is included in the fastest clock path. However, the delay through the fastest clock path is not necessarily as important as the delay through the slowest clock path, as is now explained.
Delay through a clock driver circuit can be an important parameter for IC designers. When known circuits are used, the additional delay due to the presence of a clock divider can be significant, e.g., about 500 picoseconds. Like most timing parameters, this delay is typically specified as a worst-case value, to ensure operation of the device under worst-case conditions. Therefore, even when the clock divider is bypassed, the specifications for the device are based on the worst case scenario, i.e., the delay when the clock divider is included. Therefore, the additional delay on the clock path due to the presence of a clock divider not only delays the clock signal, it also makes the IC device appear to be slower than it really is.
For these and other reasons, it is advantageous to provide a clock divider circuit having a shorter delay on the clock path than is achievable using known clock divider circuits.
The invention provides a novel clock divider circuit that adds little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are also provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.
According to one embodiment of the invention, every Nth rising edge on the true clock signal is passed to the output terminal, where N is an even integer. Every Nth falling edge on the complement clock signal is also passed to the output terminal. This embodiment provides a divide-by-N output signal. In one embodiment, the selected edges are separated by N/2 rising edges. Thus, this embodiment provides a duty-cycle-corrected output clock signal.
The clock divider circuit of the invention provides the capability to divide by any even integer, rather than being limited to powers of two as are many clock dividers. The delay through the clock divider circuit is the same, regardless of which even number is selected as the divisor.
In one embodiment of the invention, the control circuit is implemented as a counter followed by a decoder circuit. In other embodiments, the control circuit is a state machine having at least four states. In a first state, the state machine enables the xe2x80x9ctruexe2x80x9d path through the multiplexer circuit and disables the xe2x80x9ccomplementxe2x80x9d path. In a second state, the state machine disables both paths through the multiplexer, and the next transition is to a third state. In the third state, the state machine enables the xe2x80x9ccomplementxe2x80x9d path through the multiplexer circuit and disables the xe2x80x9ctruexe2x80x9d path. In the fourth state, the state machine disables both paths through the multiplexer, and the next transition is to the first state. In the second and fourth states, the keeper circuit maintains the existing value on the output terminal of the clock divider circuit.
An advantage of this circuit is that many of the delays typical of prior art clock dividers (D-flip-flop delays, combinational logic delays, and so forth) are shifted from the clock path to the path through the control circuit. Therefore, these delays are not on the clock path, i.e., not on the critical path for the clock divider circuit.
Another advantage is that by controlling the functionality of the control circuit, any even number (up to the capacity built into the control circuit) can be selected as the divisor for the clock divider circuit. Therefore, the clock divider circuit of the invention provides additional flexibility compared to many known clock dividers.
In one embodiment, the described clock divider circuit is included in a programmable logic device (PLD). In some such embodiments, the control circuit is programmable to select a divisor from a group of supported divisors. The divisor selection can be controlled, for example, using configuration data stored in static RAM (SRAM) cells included in the control circuit.
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