Voltage sensing and regulation become more complicated in a gated system. Power gating effectively closes off the leakage current path for CPU cores which are not active. In a power gated configuration, current travels into the CPU silicon at the power gate Controlled Collapse Chip Connection bumps (C4 bumps) on the ungated side, through power gating transistors, and into a gated power domain on the chip and package substrate. If the core's power gates are on, a conducting path exists between the ungated voltage domain and the gated domain. If the power gates are off, the gated CPU is isolated from the ungated supply.
Multi core systems make use of power gating to reduce leakage power on inactive cores, and utilize that power for faster and more efficient operation of the active cores. Any core may go into an inactive state and be gated, in which its voltage supply is cut off by the power gates, and the on core voltage will decay to 0V. In that state, the remaining active cores must be supplied with an appropriate voltage level.
Voltage sensing may be conducted through on die structures located in a variety of locations throughout the cores. An integrated on die regulator senses these locations and uses a digital algorithm to determine the correct regulation voltage. Power gating does not present a problem for this configuration, since the on die voltage regulator controller is able to logically determine the voltages to sense and those to ignore if power gating is enabled for some of the cores.
However, in most instances external VR11 operation may be desired. In this case, a voltage sense line from the die is routed to the regulator to monitor the voltage and use it for regulatory feedback. Complications arise when the voltage at any gated core could fall to 0V, while other cores need a stable voltage supply. The voltage regulator needs to somehow ignore the voltage at cores with power gates turned off, while continuing to monitor and adjust to voltage changes at the active cores.
Sensing the voltage upstream in the package ungated region is undesirable because the gated voltage is separated from this domain by package power routing, the power gates themselves, and any other parasitic impedance between the power gates and the core transistors. These series elements in the power path could account for up to 20-30 mV of voltage difference between the regulation point and the true core voltage. The loss in sensing accuracy of 2-4 MHz per mV is a problem which calls for an as yet unavailable means for voltage sensing at each core, which is able to comprehend the gating states to disable sensing at the gated cores.
Although the following Detailed Description will proceed with reference being made to these illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.
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