CDMA communication systems are well known in the art. Generally, such systems comprise communication stations which transmit and receive wireless communication signals between each other, commonly generically referred to as wireless transmit receive units (WTRUs). Typically, base station WTRUs are provided which are capable of conducting wireless concurrent communications with a plurality of subscriber station WTRUs. In CDMA systems specified by the Third Generation Partnership Project (3GPP), base stations are called Node Bs, subscriber stations are called User Equipments (UEs) and the wireless interface between the Node Bs and UEs is known as the Uu interface. FIG. 2 illustrates a typical 3GPP CDMA system.
Turbo codes are a form of error correcting codes that yield performance near the Shannon limit for performance in an Additive While Gaussian Noise (AWGN) channel in a wireless communication system, such as 3GPP time division duplex using code division multiple access (TDD/CDMA). Decoders for these codes utilize an iterative algorithm which gives an improved estimate of the transmitted data at each iteration.
A significant design parameter for decoders is the number of iterations to be used. Decoders can be implemented in hardware or software, but in either case the number of iterations used drives the requirement for processing resources, including the processing throughput required to achieve the desired data rate, power consumed in decoding, and the amount of hardware needed in a hardware implementation.
Two general strategies are known in the art for determining the number of iterations in a decoder implementation. First, a fixed number of iterations can be determined as part of the design. This simplifies the implementation, but requires excessive processing resources since the fixed number must be set high enough to give the desired performance, i.e. bit error rate for the expected range of signal to noise levels, for nearly all cases where many decodings would require less than the fixed number of iterations.
Another strategy is to use a stopping rule to dynamically determine when decoding can be terminated without significantly effecting performance. The simplest stopping rule is the hard-decision-aided (HDA) criteria. When using this stopping rule, decoding is terminated when two successive iterations yield the same results. There are no changes in the hard decisions between iterations. Implementation of this rule for a coded block of N bits requires N memory locations to store the results of the previous implementation, as well as comparison of the previous N bit result to the current N bit result.
Conventional stopping criteria are disclosed in Shao, Rose Y., and Fossorier, Marc P.C., “Two Simple Stopping Criteria for Turbo Decoding”, IEEE Transactions on Communications, Vol. 47, No. 8, August 1999. That paper presents two simple criteria for stopping the iteration process in turbo decoding. EP 1 017 176 and EP 1 009 098 describe the general state-of-the-art of turbo code error detection. EP 1 009 098 discloses use of cyclic redundancy checksum implemented by appending checksum bits to each frame.
A typical turbo decoder may produce turbo decoder estimate data having in excess of 5,000 bits of information for each iteration. Accordingly, the implementation of a conventional stopping rule requires an additional memory allocation in excess of 5,000 bits to store a first code iteration for comparison with a next code iteration in order to determine whether the same results have been produced.
The inventor has recognized that it would be desirable to provide an improved turbo decoder which can more efficiently implement a stopping rule with a lesser requirement for additional memory.
USPTO Backgrounds
USPTO Backgrounds