The present invention relates to a capacitor and a method for manufacturing the same wherein a dielectric layer is made of ferroelectric material or a material of high dielectric constant and which is formed on an insulating film on a surface of a substrate. More particularly, it relates to a capacitor capable of preventing dispersion of the metallic component(s) of the dielectric material into the insulating film or a semiconductor layer or preventing occurrence of cracks in the dielectric material, by patterning a lower electrode and by making the dielectric layer of the capacitor directly contact with the insulating film, and which is further capable of preventing influences of adhesion of the electrode or interdiffusion also in case the electrode is electrically connected to the semiconductor layer via the plug within the contact hole formed in the insulating film.
In forming a plurality of dielectric capacitors on a same substrate such as a semiconductor substrate, it is necessary to perform patterning of a formed electrode or a dielectric layer. It is possible to employ a method as illustrated in FIG. 8(a) in which an upper electrode 6, a dielectric layer 5 and a lower electrode 4 are processed in a lump. The example as illustrated in FIG. 8(a) is a sectional explanatory view of an example in which an insulating film 2 is formed on a semiconductor substrate 1, and electric connection is achieved with a semiconductor layer formed below the insulating film 2 via a plug 7 formed within a contact hole 11 formed in the insulating film 2, the plug being made of conductive layer of, for instance, poly-silicon. In this method, it is required to sequentially perform etching of the three layers by using the same mask while processing thereof is difficult in view of selection of etching conditions and others, and etching damages may be formed at side wall portions that undergo etching that will cause degradations in capacitor characteristics.
It is known for a method to perform separate patterning of the three layers of the lower electrode 4, the dielectric layer 5 and the upper electrode 6 as illustrated in FIG. 8(b) in order to avoid such etching damages. However, in performing separate patterning of the three layers, it will be required for mask alignments for each of the layers, and alignment margins A and B, which depend on alignment accuracies for forming the etching pattern, will further be required. It is therefore necessary to secure a larger area than an actual area of the capacitor and will cause an increase in cell area (chip area).
In order to solve such problems, it would be possible to employ a method as illustrated in FIG. 8(c) in which the lower electrode 4 is patterned prior to forming the dielectric layer 5, and in which the dielectric layer 5 is either refrained from etching of the dielectric layer 5 or etching thereof is performed for an area that is larger than the lower electrode 4, whereupon the upper electrode 6 is formed. Such a method will be effective in achieving smaller etching margin and less etching damages. However, since SiO2 is usually used as the insulating film 2 formed on the substrate to form a base for the capacitor, the dielectric film 5 will directly contact the SiO2 film in this method. This method is further disadvantaged in that a weak point (see point C) is formed on an edge portion of the lower electrode 4 at which the dielectric layer 5 is thin. In such a case, though troubles can be eliminated if patterning would be performed to make the upper electrode 6 face the lower electrode 4 to be identical in size, it may also be the case that it is used as a common plate (wiring) so that short deficiencies of both electrodes 4, 6 are apt to occur.
In case the dielectric layer of the capacitor is made of ferroelectric material or a material of high dielectric constant, Pb or Ti of the ferroelectric layer may be diffused into the SiO2 film and may further be diffused into the semiconductor layer formed downward thereof upon direct contact of the ferroelectric layer with SiO2 to thus cause degradations not only of the capacitor but also of element characteristics of the semiconductor elements, and it may, in some cases, cause to crack in the dielectric layer.
On the other hand, it is suggested in Japanese Patent Application Unexamined Publication No. 7-99290 (1995) that for the purpose of preventing interactive reaction, which may be caused upon contact of a ferroelectric layer of a ferroelectric capacitor with a silicon-containing layer, a titanium dioxide layer or an oxide layer of magnesium zirconium, tantalum or the like shall be formed at portions that come in contact with the ferroelectric layer. However, oxides of titanium, magnesium, zirconium, tantalum or the like exhibit extremely poor workability and thus lead to a drawback that it is difficult to perform precise patterning owing to time-consuming processing through dry etching or adhesion of liberated heavy metal, which is a constitutive element thereof, on the surface exposed by etching. It is thus of disadvantage that they cannot be used particularly for the case as illustrated in FIG. 8(a) in which a contact hole is formed in the insulating film on which the capacitor is to be formed for electric connection with a plug formed therein.
When manufacturing a ferroelectric capacitor in which the lower electrode is connected to the semiconductor layer via the plug formed in the contact hole of the insulating film, interactive reaction may be caused between the ferroelectric layer and poly-silicon, which is a material usually used for forming the plug, to cause degradations in capacitor characteristics or degradations in element characteristics of semiconductor elements in case the lower electrode is made of Pt, which exhibits superior orientation for the ferroelectric layer, and thus makes constitutive elements such as Pb, Zr or O of the ferroelectric layer easily pass through. Moreover, adhesion between the lower electrode made of Pt, which is suitable for forming the ferroelectric film, and the plug is not necessarily favorable and may cause in worsened ohmic contact.
The present invention has been made for the purpose of solving such problems, and it is an object thereof to provide a capacitor and a method for manufacturing the same which is capable of improving workability through dry etching while preventing diffusion and immersion of constitutive elements of the ferroelectric material or material of high dielectric constant such as Ti or Pb into the SiO2 film or the semiconductor layer.
It is another object of the present invention to provide a capacitor and a method for manufacturing the same that is of a structure in which weak points are hardly occurring in the dielectric layer.
It is still another object of the present invention to provide a capacitor of a structure in which preventing the interaction between the dielectric layer and the SiO2 film or the semiconductor layer may be achieved while improving adhesion between the lower electrode of the capacitor and the plug formed within a contact hole of the insulating film and preventing the interaction between the dielectric layer and the plug through the lower electrode.
It is still another object of the present invention to provide a method for manufacturing a capacitor in which the oxide of high melting point metal such as Ti, Ta or Zr exhibiting high barrier effects with respect to the ferroelectric layer may be interposed between the dielectric layer made of ferroelectric or the like and the insulating film made of SiO2 film or the like as a barrier layer without the necessity of patterning, also in case the lower electrode is electrically connected to the underlying layer through the contact hole.
The capacitor according to the present invention comprises; a lower electrode formed on a silicon oxide film, a dielectric layer formed on the lower electrode and made of ferroelectric material or a material of high dielectric constant (permittivity), and an upper electrode formed on the dielectric layer, wherein the lower electrode is patterned such that the dielectric layer is formed to extend off the lower electrode, and wherein an insulating barrier layer made of a composite metallic oxide including at least two metals containing a Si or a silicon nitride compound is interposed between a portion of the dielectric layer at which it extends off the lower electrode and the silicon oxide film.
In the description, the term xe2x80x9ccapacitorxe2x80x9d includes, in addition to an ordinary capacitor in which a dielectric layer is sandwiched by metallic electrodes from both sides, one of a FET type structure such as a ferroelectric memory (FRAM) of MFMIS structure in which a gate electrode of a MOS transistor and the lower electrode of the capacitor are used in common. Further, the term xe2x80x9csilicon nitride based compoundxe2x80x9d includes, besides silicon nitride, SiOuNx (0xe2x89xa6u, 0 less than x, wherein u and x indicate content ratios when Si is set to be 1) in which oxygen may be contained in the silicon nitride.
With this arrangement, the insulating barrier layer will exhibit a smaller diffusion constant of elements constituting the ferroelectric such as Ti or Pb when compared to SiO2 (in case of SiOuNx), or will function as a barrier for the metal of the same sort (in case of a composite metallic oxide including at least two metals), and diffusion thereof will be prevented. On the other hand, since it contains Si, it is easy to be etched and also exhibits superior workability.
It is especially preferable that the insulating barrier layer includes the above constitutive elements of the dielectric layer to function as a barrier and for preventing diffusion of the element from the dielectric layer.
It is preferable that the composite metallic oxide of the insulating barrier layer is SiZryOz (0 less than y, 0 less than z, wherein y and z indicate content ratios when Si is set to be 1), SiTiyOz (0 less than y, 0 less than z, wherein y and z indicate content ratios when Si is set to be 1), or SiTayOz (0 less than y, 0 less than z, wherein y and z indicate content ratios when Si is set to be 1), since it is possible to improve workability of dry etching while preventing diffusion of Ti or Zr of the ferroelectric.
It is preferable to form the insulating barrier layer to be substantially on the same plane as the lower electrode, since weak points will be hardly formed on the dielectric layer thereby.
According to another aspect of the capacitor of the present invention, the capacitor is comprises; a plug for connection formed in a contact hole formed in an insulating film, a lower electrode formed to be in electric connection with the plug, a dielectric layer formed on the lower electrode, an upper electrode formed on the dielectric layer, an adhesion layer made of a high melting point metal or a nitride of a high melting point metal that is interposed between the plug and the lower electrode, and an insulating barrier layer made of an oxide of the identical material to that of the adhesion layer that is interposed between a portion of the dielectric layer, which extends off the lower electrode to extend on the insulating film, and the insulating film.
With this arrangement, the adhesion layer will be interposed between the plug and the lower electrode and the insulating barrier layer will be interposed between the portion of the dielectric layer, which extends off the lower electrode to extend on the insulating film, and the insulating film, so that it is possible through both of these to prevent diffusion of constitutive element of the dielectric layer into the insulating film or the semiconductor layer. Moreover, since the insulating barrier layer is formed of an oxide of a high melting point metal, it may be formed by selective oxidation treatment of the simultaneously formed layer, and although the oxide of high melting point metal or the like is hard to be processed through etching or the like, it may be employed as an insulating barrier layer without the necessity of patterning. It will consequently act as an extremely favorable insulating barrier layer, while the adhesion layer will act as a junction layer to maintain the electric connection between the lower electrode and the plug in an extremely favorable manner.
Such effects are especially remarkable in case the dielectric layer is formed of a ferroelectric or a dielectric of high dielectric constant. The adhesion layer may be formed of the high melting point metal, a nitride of the high melting point metal or a conductor which contains further a Si in the nitride.
A method for manufacturing the capacitor of the present invention includes the steps of; (a) forming a contact hole in an insulating film on a semiconductor substrate for electric connection with an underlying layer, (b) forming a plug by filling a conductive material into the contact hole, (c) forming a conductive layer containing a high melting point metal on the plug and the insulating film, (d) forming a lower electrode by depositing an electrode material on the conductive layer and patterning the same, (e) making an adhesion layer under the lower electrode and an insulating barrier layer on an outer periphery thereof from the conductive layer, upon selective oxidation treatment of the conductive layer at the portion exposed from the lower electrode by utilizing the lower electrode as a mask, (f) forming a dielectric layer on the lower electrode to extend on the insulating barrier layer, and (g) forming an upper electrode on the dielectric layer.
By employing this method, an insulating barrier layer exhibiting superior characteristics for barricading heavy metal owing to oxide of a high melting point metal may be extremely easily be formed without patterning the contact hole portion.
The selective oxidation treatment of the conductive layer may be either performed through heat treatment in an oxygen atmosphere or through implantation of oxygen ion.
According to another aspect of a method for manufacturing the capacitor, the method includes the steps of; (a) forming an insulating barrier layer by depositing a composite metallic oxide including at least two metals containing a Si on an insulating film on a semiconductor substrate, (b) forming a contact hole through the insulating barrier layer to make the insulating film expose, (c) forming a plug by filling a conductive material into the contact hole, (d) forming a lower electrode to contact with the plug, and (e) forming a dielectric layer and an upper electrode on the lower electrode.
According to this method, etching may be easily performed, even though the capacitor is formed to contact with the plug while interposing the insulating barrier layer between the dielectric layer and the insulating film, since the insulating barrier layer contains Si, and the contact hole may be easily formed.
It is preferable to perform flattening of the surface of the dielectric layer prior to forming the upper electrode to thereby eliminate generation of weak points on the dielectric layer.
USPTO Backgrounds
USPTO Backgrounds