Metal Oxide Semiconductor (MOS) transistors are used in a wide variety of ways in switched capacitor circuits. For example, they can be used as switches, current sources, amplifiers, etc. These MOS transistors have inherent parasitic components, which may lead to limitations to circuit speed, signal distortion, and noise. The drain (or source) to bulk parasitics are of special concern because of the large parasitic capacitance component and its non-linearity. The parasitic capacitance is related to the P-N junctions formed between the drain to bulk and drain to source respectively. The capacitance of a P-N junction is non-linear in that it is voltage dependent and may, therefore, contribute to signal distortion and noise.
It is a goal of an embodiment of the present invention to provide a circuit and method to reduce the influence of the parasitic capacitance at the drain and source of a MOS transistor and its non-linearity, thereby increasing its operating speed, reduce signal distortion, and reduce noise.
USPTO Backgrounds
USPTO Backgrounds