As memory in computers, servers, and other computational, communication, storage, and electronic devices has evolved toward increased speed and performance, memory power consumption has also increased. Although new generations of memory technology implement lower voltages with the goal of decreasing power, device developments and techniques are sought to reduce power draw in future systems.
The simplest traditional approach for reducing power draw from dynamic random access memory (DRAM) generation to DRAM generation has been to lower voltage. For example, memory class double data rate 1 (DDR1) uses 2.5V for the VDD positive power voltage supply rail, class DDR 2 uses 1.8V, and class DDR3 uses 1.5V. Even within the same technology, sometimes a lower voltage grade is introduced. For example, the DDR2 standard was originally 1.8V at introduction. Joint Electron Device Engineering Council (JEDEC) is currently developing a DDR2 1.5V specification. Although supply voltage reduction can be an effective way to reduce power consumption, sometimes suppliers have to compensate with higher current requirements. Lowering the voltage within a technology can require controller changes that are not simply backwards compatible, thus requiring a new subsystem design to exploit lower voltage parts.
Traditional DRAMs and memory controllers use internal pull-up and pull-down resistors to terminate all data and strobe lines. Typical values are 100 ohm up and 100 ohm down although other values are available. The termination rails are VDD and GND. FIG. 4 shows an example of on-die single-ended termination (ODT) circuitry.
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