1. Field of the Invention
The present invention relates to a Field Effect Transistor (FET) for a semiconductor memory device or the like and a method of manufacturing the FET, and more particularly, the present invention relates to an FET having a conductive nano tube as a gate and a method of manufacturing the FET.
2. Description of the Related Art
As the integration of semiconductor devices has remarkably increased, the miniaturization of CMOS semiconductor devices having a conventional structure, that is, scaling, has reached the limits in the current technology. Scaling has been performed to reduce the width and the length of a gate, minimize an isolation area between unit elements, and reduce the thickness and the junction depth of a gate insulating layer in order to achieve high integration, high performance, and low power consumption. However, since gate controllability is basically required in this respect, an on-current off-current ratio (Ion/Ioff) of a transistor must be substantially maximized. According to a road map of international technology road maps for semiconductors (ITRS, 2001), research has been recently conducted on a ultra-thin body fully depleted (UTB-FD) SOI transistor having a silicon-on-insulator (SOI) substrate and a band-engineered transistor {K. Rim, et al., VLSI 2002 page 12} which has improved electron mobility by using a strained Si channel in order to increase a drive current. In addition, research has been conducted on silicon transistors having various three dimensional structures, such as a vertical transistor {Oh, et al., IEDM-2000, page 65}, Fin-FET {Hisamoto, et al., IEEE Trans. On Electron Device 47, 2320 (2000)}, and double-gate transistor {Denton, et al., IEEE Electron Device Letters 17, 509 (1996)}. However, in a silicon transistor having a three dimensional gate structure, it is difficult to change the structure of a gate when manufacturing the silicon transistor in order to maximize a field effect of the gate. In particular, since silicon used for forming a channel is also used for forming a substrate or a silicon substrate with a three dimensional structure in deposition and patterning processes, a method of manufacturing a three dimensional gate structure is complicated.
A transistor having a carbon nano tube as a channel has been recently suggested for overcoming the problems of a silicon device that has reached the scaling limits. Tans and Dekker, et al. reported a carbon nano tube transistor which can be operated at a normal temperature {Tans, et al., Nature 393, 49 (1998)}. In particular, since a horizontal growth technique for a carbon nano tube {Hongjie Dai, et al., Appl. Phys. Lett. 79, 3155 (2001)} and techniques in which a carbon nano tube is vertically grown from a nano hole {Choi, et al., Adv. Mater. 14, 27 (2002); Duesberg, et al., Nano Letters} have been developed, research has been widely conducted for applying these techniques to semiconductor devices.
USPTO Backgrounds
USPTO Backgrounds