Semiconductor chip manufacturers often perform electrical testing of the semiconductor chips at various stages of production, including final testing prior to shipment. This electrical testing may consist of testing chips in package form, in wafer form, or in individual die form. In package form, the semiconductor chips may be encapsulated in an encapsulating resin, with only conductive balls, pads, or leads exposed outside of the package for electrical contact. In wafer and individual die form, the semiconductor chips may have conductive balls or pads available for electrical contact. Typically, the electrical contacts are arranged into an array. Two common types of contact arrays are land grid array and ball grid array. The electrical testing may consist of electrical functionality tests lasting several minutes or it may consist of burn-in or reliability tests lasting many hours. To maximize the efficiency of the testing process, numerous semiconductor chips may be loaded onto a load board and multiple load boards may be rotated through a single piece of test equipment. This allows some load boards to be populated/de-populated with semiconductor chips while other load boards are in the testing area of the test equipment. The semiconductor chips need to be non-permanently affixed to the load board in such a way that the chips can be easily loaded and unloaded from the board while still ensuring good electrical contact to the load board throughout the potentially lengthy testing process. Typically, an interconnect assembly is used to interface the semiconductor chips to the load board. The actual electrical connections between the semiconductor chip and the load board are usually accomplished by compressible pin-type structures within the interconnect assembly. The compressible pins allow for small variations in the structure of the semiconductor chips while still ensuring good electrical contact between the contact arrays on the chip and the load board. The compressible pin structures, sometimes referred to as ‘spring pins’ or ‘pogo pins’ can be quite complicated and expensive, consisting of several discrete components, due to the tight tolerances associated with the interconnect assembly and the high reliability demands of the testing process. As an example, a single compressible pin failure can cause many semiconductor chips to be identified as non-functional before the pin failure is identified. Consequently, an interconnect assembly that includes simpler, more reliable, and less expensive electrical contact components is desired. The invention addresses these and other disadvantages of the conventional art.
USPTO Backgrounds
USPTO Backgrounds