Although the current invention will work with any type of multi-bank or segmented array architecture, this specification focuses on synchronous dynamic random access memories (SDRAMs) for purposes of explaining the current invention. Nevertheless, it should be understood that the current invention applies to memory architectures such as video random access memories (VRAMs) synchronous graphic random access memories (SGRAMs), Rambus memory systems, and Synchlink memory systems.
Synchronous memories such SDRAMs are designed to operate in a synchronous memory system, where input and output signals are synchronized to an active edge of a system clock (one exception in an SDRAM being a clock enable signal as used during power-down and self-refresh modes).
The address operations of an SDRAM are somewhat different from those of an asynchronous DRAM. In an asynchronous DRAM, once row and column addresses are issued to the DRAM and the row and column address strobe signals are deactivated, the DRAM's memory is automatically precharged and available for another access. An SDRAM, on the other hand, requires a separate command to precharge a row of storage cells within a memory array. Assuming an SDRAM has multiple banks and a memory cell in one of those banks has been addressed, that bank remains active even after the cell has been accessed. This occurs because an internal row address strobe is generated and maintains the active state of the addressed row. As a result, the last row accessed in a bank remains open until a PRECHARGE command is used to deactivate the open tow and put the bank into a standby mode.
Thus, to accomplish an SDRAM transfer operation, an ACTIVE command is issued to register a row address, and a memory bank is selected to be accessed. Data is then transferred to or from the memory bank by registering the column address through a WRITE or READ command, respectively. Other memory banks may be subsequently accessed, but a PRECHARGE command directed to a bank is needed before registering another row on that bank. During a time tRP required to precharge a row in a bank, commands to other banks may be issued. As a result, the precharge time tRP is considered to be “hidden” by the commands to other banks.
Testing of SDRAM as well as other memories involves writing sample data to the banks, reading data from the banks, and comparing the output to the input. This can be a time-consuming process. Consequently, there is a continuing need to shorten test time. One such method in the prior art involves compressing row addresses, which allows more than one open row and therefore allows writing to more than one memory cell at a time. Similarly, column addresses may also be compressed. However, as more rows and columns are activated simultaneously, there is an increase in he current load on busses used to transmit the input and output data. The additional line noise on the busses caused by the increased current load can change the output. As a result, the test mode conditions may actually create errors that would not appear in a non-test mode. Thus, there is an additional need in the art for a faster test mode that will not contribute error-producing factors to the testing process. Moreover, concerning faster writing to multi-bank architectures, prior art teaches treating all banks as one large bank, wherein a row address accesses that row in all of the banks. It would be a benefit to the art to have the option to simultaneously write to any number of banks, including not only writing to one bank or all banks, but also to writing to more than one bank but less than all banks. It would be a further benefit to maintain the discrete nature of each bank by being able to write to one row of one bank and a different row of another bank with a single command.
USPTO Backgrounds
USPTO Backgrounds