1. Field of the Invention
The invention relates to testing digital modules and more particularly to a test set therefor that does not require a programmed computer.
2. Description of the Prior Art
Logic circuits consist of discrete semiconductor devices and integrated circuits of small scale, medium scale and large scale integration. A single logic board incorporates a multiplicity of such circuits and as packaging densities increase, fewer test points are available resulting in an ever increasing complexity of data streams at available test points. As a result, logic board testing has been accomplished by applying a data stream at various test points and noting the response thereto at other test points on the board. Applied data streams are tailored to the board under test and are generated by an actively participating computer which also evaluates the resulting responses. Each board type to be tested requires a corresponding computer program which must be generated, debugged and verified; generally, an expensive time consuming procedure.
Passive devices for testing logic circuits with a minimum of software support exist in the prior art. These devices employ a cyclic redundancy check code produced by a pseudorandom number generator. Pseudorandom numbers have random statistical properties for finite sequence of codes after which the sequence repeats. Data at the output terminals of the circuit under test, responsive to an external or self-applied stimulus at the input or test terminals thereof, are overlayed with the random codes produced by the pseudorandom number generator, disturbing its internal sequence. At the conclusion of the test sequence, a code appears at the output terminals of the tester which is unique to the circuit under test. Since these devices require either external or self-stimulus for the circuit under test, they do not eliminate the programmed computer and they are limited with respect to the logic circuits that may be tested.
Appreciable simplification to logic board testing, over that achievable by the prior art, may be realized with the application of pseudorandom numbers as the input data. Applying a pseudorandom sequence of sufficient length to the input terminals of the board under test, and applying clock and reset pulses on a pseudorandom basis, causes all logic circuits therewithin to be thoroughly exercised and the effect of all internal faults will propagate to the output terminals of the board. Thus, by noting the data at the output terminals of the board under test at the conclusion of each sequence and comparing it with data similarly obtained on a known good board, it is possible to determine whether faults exist within the board. It is to such a system that the present invention applies.
USPTO Backgrounds
USPTO Backgrounds