Dynamic random access memory (DRAM) integrated circuit devices have existed for more than thirty years and have undergone tremendous increases in both storage capacity as well as speed. These advances have been achieved through advances in semiconductor fabrication technology and circuit design technology. The quest to increase memory speeds has lead to several changes in DRAM devices. In recent years, DRAM devices have transitioned towards synchronous operation. That is, synchronous DRAM (SDRAM) devices accept commands and transfers data synchronized to a clock signal. A recent variation on SDRAM is the introduction of double data rate (DDR) SDRAM devices. DDR devices still accept commands aligned on the rising clock edge, but transfer data on both the rising and falling clock edges.
Internally, SDRAM devices store data in memory cells. Each memory cell stores one bit of data and is organized into an array which can be addressed by a row address and a column address. Each device outputs or accepts a n-bit word of data, where n is an integer, for each read or write, respectively. Thus, each SDRAM device typically includes a plurality of arrays which are read simultaneously using the same row and column address in order to output or accept n-bits of data simultaneously. Alternatively, some SDRAM memory device may accept a column address which maps to multiple column lines, and thus a plurality of memory cells. One limitation on increasing memory device speed is the rate at which column lines can be switched within a memory array. That is, the clock cycle time supplied to an SDRAM is ordinarily limited by the maximum speed which the memory arrays can switch column lines.
A solution to increasing data transfer rates beyond the limitations imposed by the maximum speed at which column lines can be switched is to employ prefetching, which allows the internal column cycle time to be spread across multiple external data transfer periods. Essentially, a single read or write transaction in a prefetching memory device effectively consists of a single wider data transfer over one internal data transfer period (at the SDRAM core) and a corresponding number of consecutive n-bit wide external data transfers over the corresponding number of external data transfer periods. For example, one common prefetch mode is known as 2n prefetch. If each word is 32-bits (n), each read causes 64-bits (2n) to be read from the internal arrays over a single internal data transfer period, and 32-bits are output from the SDRAM device over each of two consecutive external data transfer periods. Another common prefetch mode is known as 4n prefetch, in which the internal read is four times the width of the SDRAM's external interface, and data is output over four consecutive external data transfer periods. In a SDRAM, an external data transfer period is one clock cycle, while in DDR SDRAM, an external data transfer period is one half of a clock cycle.
Thus, prefetching permits increasing the data transfer rate of a SDRAM device beyond the limitation imposed by the column line switching speed. The cost of using prefetching is the increased granularity of the data size being read or written simultaneously. For example, in a memory device having 4n prefetch, at least four words of data are output for each read transaction. For burst reads, the minimum burst size would correspond to the size of the prefetch. Burst reads larger than the minimum burst size would be equal to multiples of the prefetch size, unless the burst read is terminated prematurely. Thus, for a 4n prefetch SDRAM device, burst reads are limited to, for example, 4, 8, or 12 words. Many conventional SDRAM devices are designed to operate with a single prefetch level, since each prefetch level requires a differing number of data lines.
One problem introduced by the use of prefetching memory devices relates to compatibility and efficiency. For example, some systems may only be compatible with a particular type of prefetching (e.g., 2n prefetch only). Additionally, other systems may be compatible with a range of prefetching (e.g., 2n- or 4n-prefetch) but may operate more effectively at one of the prefetch modes. Server computers, for example, may favor smaller prefetches such as a 2n prefetch, while workstations may favor larger prefetches, such as a 4n prefetch. Accordingly, there is a need and desire for a method and apparatus to permit a synchronous memory device to operate at a plurality of prefetch levels.
USPTO Backgrounds
USPTO Backgrounds