1. Field of the Invention
The present invention relates to a switching circuit having two P-channel MOS-FETs connected in series.
2. Description of Related Art
A switching circuit for switching a low current under a high voltage can be constituted by MOS-FETs (Metal Oxide Semiconductor Field Effect Transistors). It is often preferable to form such a switching circuit by using only. P-channel MOS-FETs or N-channel MOS-FETs to simplify the manufacturing process.
FIG. 3 shows a conventional switching circuit 6 in which two P-channel MOS-FETs are used. A first P-channel MOS-FET 1 and a second P-channel MOS-FET 2 are connected in series. Sources of both MOS-FETs are connected to a common source junction Js, and gates of both MOS-FETs are connected to a common gate junction Jg. In this case, cathodes of parasitic diodes 3, 4 formed between a drain and a source of each MOS-FET are commonly connected to the source junction Js. Namely, both parasitic diodes 3, 4 are connected in a reverse direction to each other, in order to prevent a reverse current that flows from an OUTPUT side to an INPUT side through the parasitic diode 4 when only the second MOS-FET 2 is used. An example of an analog switch which is similar to the switching circuit shown in FIG. 3 is disclosed in JP-A-2002-43434.
When a switching circuit such as the circuit shown in FIG. 3 is used in an electronic control unit (ECU) mounted on an automotive vehicle, a maximum signal level given to an input side will be 12-14 volts corresponding to a battery voltage. Assuming that a gate voltage of the EFT 1 and EFT 2 is controlled in a range of 5-0 volts and that a withstanding gate voltage is 8 volts, it is proper to set a Zener voltage to 8 volts.
However, in the switching circuit shown in FIG. 3 following problems are involved. When the gate becomes open, due to disconnection of a lead wire controlling the gate voltage, for example, and the On-Off control of the switching circuit 6 becomes impossible to be performed, it is preferable to keep the circuit in an Off state from a safety standpoint. If the input side is at zero volt and a voltage such as 16 volts is imposed on the output side, a voltage is imposed on a source of FET 2 through the parasitic diode 4. Assuming that a forward voltage of the parasitic diode 4 is 0.8 volts, the source voltage of the FET 2 becomes 15.2 volts. The gate voltage at the gate junction Jg is set to 7.2 volts (15.2−8) through the Zener diode 5. Accordingly, both of the FETs 1 and 2 are turned on by a potential difference between the gate and the source, and the switching circuit 6 is brought to a conductive state. JP-A-2002-43434 mentioned above does not touch upon this problem at all because the structure of the switching circuit is different from that shown in FIG. 3 though MOS-FETs are used.
USPTO Backgrounds
USPTO Backgrounds