The present invention relates generally to semiconductor memory devices and their manufacture, and more particularly to capacitor under bitline DRAM memory cells and methods for fabricating such structures and cells providing benefits relating to increased circuit density and processing simplicity.
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continually getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a memory device, which has memory and logic functions integrated onto the same semiconductor chip.
One type of fast data storage device that has been used consistently to address the memory portion of this demand is the high density of the standard DRAM device. High density DRAM devices have been enabled by advances in photolithography and expensive dielectric materials. However, as the cell area decreases, process margins such as alignment tolerance have become limiting factors for developing a simple cost effective high density DRAM memory cell.
Several types of DRAM memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The 1T1C (one transistor and one capacitor) memory cell type requires less silicon area than the dual capacitor type, but is less immune to noise and process variations. Additionally, the 1T1C cell requires a voltage reference for determining a stored memory state.
The dual capacitor memory cell (referred to as a 2T2C memory cell) requires more silicon area, but stores complementary signals allowing differential sampling of the stored information. The 2T2C memory cell typically is more stable than a 1T1C memory cell. As illustrated in prior art FIG. 1, a 1T1C DRAM cell 105 includes one access transistor 108 and one memory storage capacitor 110. A storage node capacitor plate (storage plate) 112 of the storage capacitor 110 is connected to a source terminal (source node) 114 of the transistor 108. The 1T1C cell 105 is read from, or written into by applying a signal via the word line WL 115 to the gate 116 of the transistor, thereby coupling the storage plate 112 of the capacitor 110 to the drain 117 of the transistor and the bit line BL 118. A ground node (ground plate) 120 of the storage capacitor 110 is connected to a common ground of the memory array. A sense amplifier (not shown) is connected to the bitline 118 and detects the voltage associated with a logic value of either 1 or 0 associated with the charge of the DRAM capacitor 110. In this manner, the memory cell data is retrieved.
A characteristic of a DRAM memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. The sense amplifier usually rewrites or restores (onto that cell) the same logical state as the bit just read from the cell. If the applied read voltage was small enough not to destroy this logical state, then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art FIG. 2, a 2T2C memory cell 130 in a memory array couples to a bit line (xe2x80x9cbitlinexe2x80x9d) 132 and an inverse of the bit line (xe2x80x9cbitline-barxe2x80x9d) 134 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The 2T2C DRAM memory cell comprises two transistors 136 and 138 and two capacitors 140 and 142, respectively. The first transistor 136 couples between the bitline 132 and a first capacitor 140, and the second transistor 138 couples between the bitline-bar 134 and the second capacitor 142. The first and second capacitors 140 and 142 have a common ground terminal.
By contrast to the expensive DRAM process, standard logic processes are simple and very cost effective. Thus, simply adding the standard DRAM process to the simpler standard logic process would be too expensive, both in terms of development and production.
Additionally, as memory cell density increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. One way of increasing cell capacitance is through three-dimensional cell capacitor structures, such as trenched or stacked capacitors.
Deep trench capacitors have been implemented in prior art DRAM cells below the substrate surface in what is referred to as capacitor under the bit line (CUB) type DRAM cells. Several trench capacitor cells have had process problems, particularly where increases in cell density has pressed the access transistor alongside the trench capacitor. Attempts to use short-channel lengths for the access transistor have run up against the effects of drain-induced barrier lowering. Some of the process problems presented by these prior art approaches include: the epi process from the contact hole being barely controllable; the gate dielectric grown from the gate (rather than the channel) causing a potential reliability problem; alignment tolerances between contact holes; and word lines that are patterned before the contact process. In addition, these approaches have the tendency of decreasing process margins more than conventional processes.
Prior art capacitor over bit line (COB) type DRAM memory cells have also used various configurations of planar, trenched or stacked capacitors in the metal layers and other layers over the bit line. Generally, these implementations resort to processes requiring a number of additional masking, deposition, etching, or other production process steps. These additional process steps have a great impact on manufacturing costs and capitol equipment costs particularly where they are associated with added photolithographic equipment and more complex photo processing. Defect density inevitably increases with each additional photomasking layer and compromises yield and reliability.
Thus, conventional combinations of a standard DRAM process with the simpler standard logic process have been too expensive for the applications considered.
Also, conventional prior art COB type DRAM cells integrated into the standard logic process are generally limited to the relatively thin IMD (inter-metal dielectric) layers, by comparison to some other layers under the bit line such as the PMD (poly-metal dielectric) layer or the substrate. This may not be a problem when planar capacitors are used in the DRAM, consuming large areas of semiconductor but when three-dimensional capacitors are to be integrated into the IMD layers, depth issues become paramount.
Accordingly, there is a need in the industry to provide a simple high density memory device, which has memory and logic functions integrated onto the same semiconductor chip, permits the use of the simpler standard logic process with a minimum of process steps, yet has the high density benefits of the DRAM structure and process formed within the thicker PMD layer.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a capacitor under bitline type DRAM memory cell and method for its fabrication. In particular, the memory cell provides a high density CUB type DRAM cell with a three-dimensional capacitor formed substantially within the relatively thick PMD layer. The memory cell utilizes several variations of storage contact pillar structures as a first capacitor plate of the memory cell capacitor formed within a trench in the PMD layer. In one aspect of the present invention, a capacitor dielectric layer such as Ta2O5, TiO2, or BST is deposited over the first capacitor plate (e.g., the storage contact pillar structures). To form the other or second capacitor plate, the capacitor dielectric layer is then covered with another conductive layer, for example, the first metal (M1) layer or another plate material. An access transistor formed between substrate (e.g., semiconductor substrate) active regions and a word line is in electrical communication with a bit line contact, the first capacitor plate, and the word line, respectively. The memory cell effectively integrates (embeds) into the simple standard logic process the high density benefits of the DRAM process, in effect forming an embedded DRAM (eDRAM), without the usual added development and manufacturing cost issues of the more complex standard DRAM process. In one embodiment of the present invention, this integrated eDRAM process requires only one additional masking step.
In one aspect of the present invention the capacitor plate that includes the contact pillars (or contact plugs) can be either the ground plate (reference plate), or the storage plate.
The term xe2x80x9cgroundxe2x80x9d herein, shall be understood in one or more aspects of the present invention to represent any specific, or preset voltage (e.g., reference voltage) which may include a ground voltage. For example, a preset voltage, which may include the ground voltage, may be applied to a ground plate, a ground plane, a ground plate contact structure, or a ground plate region as discussed herein.
In another example, the capacitor plate that includes, for example, the M1 layer, can be either separate from the ground plate, or the ground plate can comprise the M1 layer.
In still another variation of the present invention, the contact pillar structures may have corrugated or fluted shapes, long thin aspect ratio shapes, or they may include multiple or dummy contact pillars to enhance the effective surface area of the capacitor.
According to another aspect of the invention, one of the conductive capacitor plates may comprise a copper layer with a tantalum nitride barrier layer to prevent migration of the copper.
In another aspect of the present invention, the top conductor layer (reference plate) of the eDRAM capacitor provides a structure which can be continuous across adjoining cells.
In yet another aspect of the present invention, one plate of the capacitor may comprise multiple contact pillars. Contact pillars used as a capacitor plate, may be comprised of conductive materials, for example, tungsten, aluminum, or copper with a tantalum nitride migration barrier layer.
In some variations of the present invention, the cells have a portion of the contact pillar structure of the capacitor plate which extends into a region of the PMD that is not removed. This improves structural strength of the cell during processing. Of these variations, the cell with contact pillars in the storage plate has the greatest capacitance density (capacitance per unit foot-print area).
Single-event upsets (SEUs) are random errors in semiconductor memory devices, which can cause a loss of data. SEUs are caused by passage of energetic charged particles through sensitive regions of a chip. Beneficially, the single-event upset cross-section is reduced by having the contact pillar structures extend over field, effectively shielding the active areas of the substrate, thus reducing random errors and the loss of data.
A further object of the present invention is to provide a method for fabricating a capacitor under bit line memory cell within the PMD layer utilizing several self-aligning steps, while performing these steps within the simple standard logic process.
Yet a further object of the present invention is to provide a DRAM cell with a three-dimensional capacitor structure utilizing contact pillar structures embedded within the PMD layer having reduced complexity and thus reduced defect rate, increased ease of manufacture, and reduced manufacturing cost.
A simple memory structure and method utilizing a three-dimensional capacitor formed substantially within the thick PMD layer provides a high density CUB type DRAM memory cell, which has memory and logic functions integrated onto the same semiconductor chip, thereby permitting the use of the simpler standard logic process with a minimum of process steps, yet has the high density benefits of the DRAM process.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
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