1. Field of the Invention
The present invention relates to a bus system and a command delivering method thereof, and more particularly, to a bus system including a plurality of slave devices, at least one slave device having a latency time for data input/output, and a command delivering method thereof.
2. Description of the Related Art
A bus system, including a plurality of master devices and a plurality of slave devices, generally adopts an arbiter for the purpose of sharing a common bus. The arbiter grants the control of a bus to a master device according to a predetermined arbitration algorithm, and the master device exclusively takes control of the bus until transfer of corresponding data is complete. Here, the bus includes an address/control bus and a data bus.
If a slave device is a memory, the slave device includes a memory device for storing data and a memory controller for controlling the memory device. If a command is output from a master device to the memory controller, the memory controller outputs a corresponding control signal to the memory device after having completed preparation for access to the memory device.
FIG. 6 is a timing block diagram for explaining a conventional process of delivering a command to a memory which is a slave device. A master execution cycle, a memory controller execution cycle, and a memory device execution cycle are shown in FIG. 6. The master execution cycle refers to the time beginning with the instant a master device outputs a command to a memory controller until the instant the master device is informed of execution completion of the output command and data transfer completion by the memory controller. The memory controller execution cycle means the time between the instant a control signal is output to a memory device after the latency time of the memory controller has lapsed upon receipt of the command output from the master device, and the instant data transfer is completed. The memory device execution cycle refers to the time beginning with a point when data transfer starts after the latency time of the memory device has lapsed until a point when the data transfer is completed. The latency time is the time required for executing a predetermined preparation process in the memory device or in the memory controller.
Referring to FIG. 6, a process of delivering a command for a memory such as a synchronous DRAM (SDRAM) recently adopted in a bus system will now be described in detail. If a command containing information necessary for data transfer, such as an address, a read/write flag, and a burst length, is input from a master device to an SDRAM controller which is a memory controller, the SDRAM controller extracts information necessary for data transfer from the command and outputs a corresponding control signal to the SDRAM. The SDRAM to which the control signal is input from the SDRAM controller accesses a memory cell of a predetermined memory bank after having completed a predetermined preparation process such as address decoding. As the SDRAM controller accesses the memory cell, data is output or input through a data bus. That is, to access the SDRAM, the preparation by the SDRAM controller is necessarily required. While preparation by the SDRAM controller is made, actual transfer of data is delayed, which is called a latency time. Referring to FIG. 6, the latency time is classified into two parts; a slave controller latency beginning with the instant a command is output from a master device until the instant a control signal is output from a slave controller, and a memory device latency beginning with the instant the control signal is output from the slave controller until the instant data is output from a memory device.
Meanwhile, when data transfer is complete, the SDRAM controller informs the master device of completion of execution of the command. The master device outputs a new command after having been informed of the execution completion by the SDRAM controller. Data transfer intended by the new command is made after a latency time for the preparation process described above has passed.
As a consequence, in the case of a slave device such as SDRAM, as shown in FIG. 6, there is an idle clock cycle on a data bus beginning with a point when a command is output from a master device before transfer of corresponding data, which thereby degrades the efficiency of data bus access as well as system performance.
USPTO Backgrounds
USPTO Backgrounds