1. Field of the Invention
The invention relates to a hub chip for connection to an address bus and for connecting one or more memory modules.
2. Description of the Related Art
Memory modules are frequently used in personal computers in order to store data which can be processed in the personal computer. In order to use the storage capacity of a plurality of memory modules, an address and databus is usually provided which has the memory modules connected to it, i.e., each of the memory modules is connected to the joint address and databus. The line and input capacitances of the corresponding inputs for the address and databus on the memory modules and also reflection of the, signals at branch points mean that the maximum clock frequency at which address data and user data can be transferred is limited.
Particularly when double data rate (DDR) technology is used, the frequencies at which data are transferred via the address and databus can be very high. For future DDR-III technology, it is therefore appropriate for the memory modules not to be operated on a joint address and databus.
One possible alternative address and databus concept involves the provision of a “hub chip” between memory modules and memory controller, which is used to actuate one or more memory modules. The hub chip is connected to the memory controller, which controls the storage and retrieval of data. The hub chip has an input for the address and databus in order to receive address data and user data and to transfer any user data to the memory controller. The hub chip also has an output which can be used to output address and user data. The output for the address data and user data can be connected to an input on a further hub chip downstream.
Normally, address data in the currently used DDR-II and the future DDR-III technology are transferred not in parallel, but rather in blocks, e.g., four blocks, which means that the full address data are available in the appropriately connected hub chip only after four clock cycles. So that the hub chip detects whether one of the memory modules connected to it is being addressed by the address data item, it is first necessary to receive all portions of the address data before a decision can be made regarding whether one of the memory modules connected to the hub chip is being addressed by the address.
To date, provision has been made for the address data to be forwarded to the next connected hub chip only after the address data have been received in full. This is usually done using a shift register to which the portions of the address data are successively written, the portions being pushed into the shift register and being forwarded at the end of the shift register via the output of the hub chip to the input of the next hub chip (if present). With a plurality of hub chips connected in succession, this results in the address data being applied to the input of the respective hub chip with a delay. The delay in the address data becomes greater for a hub chip the more hub chips there are in the array upstream of the hub chip in question. This results in an unwanted delay in the addressing of one of the memory modules on hub chips situated further back in the array when there are a plurality of hub chips connected in succession.
USPTO Backgrounds
USPTO Backgrounds