The present invention relates, in general, to the field of integrated circuit memory arrays or other integrated circuit devices having circuit elements capable of being selectively disabled. More particularly, the present invention relates to a technique for reducing element disable fuse pitch requirements in an integrated circuit memory device incorporating replaceable and/or redundant memory elements.
In highly integrated memory arrays, an "element" (e.g. a word line) may be designed to be replaceable in the event one or more memory cells on the word line is non-functional due to processing defects and the like. As such, a defective element can be disabled and a redundant element then enabled to take its place. Most commonly, the defective element is disabled by blowing a fuse. Historically, this means that there must be one fuse for every replaceable element on the device.
Nevertheless, when redundant elements are used to improve the yield of memory devices, as in the example above, it is also highly desirable to minimize the width of such elements to reduce the overall impact such redundant elements have on device die size. Moreover, it is also advantageous to fashion the fusible link used to disable the defective elements as integral to the "real" element. Unfortunately, these design constraints frequently conflict because a replaceable element containing a disable fuse can be narrower than the fuse pitch, which is frequently relatively quite large in comparison.
In light of this, various means have heretofore been employed to obviate the need for element disable fuses in order to avoid this problem. However, such techniques are usually costly in terms of the speed penalty incurred when the memory array row decoder is activated.
USPTO Backgrounds
USPTO Backgrounds