Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to a method and apparatus for reverse memory sparing.
Description of the Related Art
Dynamic Random Access Memory (DRAM) is organized into rows and columns, and is accessed by electrical signals called “strobes” which are transmitted along the rows to the columns. To access memory, the memory controller activates the Row Access Strobe line to indicate the row where data is to be found (high bits) and the Column Access Strobe specifies the column (low bits). The data is then provided to the output line and to its destination on the next clock cycle.
DRAM devices have a high failure rate. Current memory architectures solutions use “Sparing” techniques to reduce the annual service rate (ASR) of the memory subsystem by physically mapping out failed regions. Memory starts in a non-failed state. Hardware and/or firmware identify a hard DRAM failure and invoke a sparing resource to map out the failure, moving the memory to the n failure state. Subsequent hard failures may invoke additional sparing, if available, which moves memory to the n+1 failure state. This is referred to as “Forward Sparing” in this description, or more generally in the industry as simply “Sparing.” After all forward sparing resources are used, a service call must be initiated.
USPTO Backgrounds
USPTO Backgrounds