Conventionally, logic circuit designs of large-scale integrated (LSI) circuits have been made by using the designs of a register transfer level (RTL) description, and by performing data flow controls using state transition diagrams. The RTL expresses the level of abstraction of the logic circuit design, and the RTL description is a kind of a description method by a hardware description language (HDL) with the low level of abstraction that describes the structure and the operation of hardware. In the RTL, a flow of data is described at the register level. A source code of the HDL that is described in the RTL is converted into a logic-gate level circuit description using software, which is called a logic synthesis tool.
When a logic circuit design is made using a state transition diagram, the state transition diagram is firstly created, and thereafter a flow of the state transition needs to be manually verified. Accordingly, in the case of designing a logic circuit that needs a complicated data flow control, for example, a high-performance LSI for image processing applications, there are problems, such as a failure of full verification to verify the flow of the state transition, and the easy degradation in the design quality due to inclusion of a bug or the like.
Therefore, a high-level synthesis technique illustrated below has been introduced in recent years.
As a technique of designing a logic circuit in a short period, a high-level synthesis technique as indicated in Non-patent Literature 1 is known. The high-level synthesis technique is a design automation technique in which an operation description (hereinafter, called “software description”) of a logic circuit that is represented using a procedural software programming language such as the C language is automatically converted into an RTL description by the HDL. Steps of automatically synthesizing the RTL description from the software description using such a high-level synthesis technique are as follows:
(1) An allocation step: the type and the number of pieces of computing elements, memories, and the like that are mounted on a logic circuit to be synthesized are decided;
(2) A scheduling step: the execution time for each operation in the software description is decided. This step is based on a “parallelism analysis” function used in a parallelization compiler technique for a very long instruction word (VLIW) processor in which parallel operations by multiple operation devices are possible;(3) A binding step: allocation of operation to each computing element, allocation of intermediate processing data to a register, and the like are decided; and(4) An FSMD generation step: a control unit for executing a processing operation equivalent to the software description in the logic circuit is implemented with a finite state machine (FSM), and this control unit generates a finite state machine with datapath (FSMD) that drives an operation processing circuit (Datapath) configured to include a computing element, a register, a memory, and a bus. The FSMD that is eventually generated serves as an RTL description to be outputted.
Among these steps, the “operation scheduling and binding step” that includes a step of multiplexing each operation process inside the software in the time direction by the “scheduling”, and a step of multiplexing each operation process in the space direction (allocation to the computing element) by the “binding”, is an important step as a core for the high-level synthesis technique.
The details of the high-level synthesis technique and the steps thereof are described in, for example, Patent Literature 1, Patent Literature 2, and Non-patent Literature 1.
As another technique of designing a logic circuit in a short period, a method that uses a SystemC as indicated in Non-patent Literature 2 is also known. The SystemC is a kind of the HDL provided as a class definition and a macro definition of a C++ language that provides an interface for event driven simulation of a hardware system. In the SystemC, the description of a “tier description”, a “parallel operation process description and process startup condition (sensitivity list)”, and a “signal connection” that are necessary for the hardware description is possible, and thus, it is possible to describe a logic circuit in the RTL using the SystemC. Moreover, it is possible to abstractly represent a function of a system in a software description by the C++ language, by a description method called transaction level modeling (TLM) on the SystemC in which a communication description and an operation processing description are separated, and execute a large-scale system-level simulation.
The details of the SystemC are described in, for example, Non-patent Literature 2.
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