1. Technical Field
The present invention relates to a field effect transistor structure, in particular to a field effect transistor structure integrated with a RRAM and a manufacturing method thereof, belonging to the technical field of semiconductor memories.
2. Description of Related Art
Information reading and writing of the RRAM is realized by reading or changing the resistance of the resistance-variable material. By the action of an external voltage, the resistance of the RRAM has a high state and a low state, which are represented by “0” and “1”. With different voltages, the resistance of the RRAM can be switched between the high state and the low state to realize information storage. The RRAM has advantages of simple preparation, high storage density, low operation voltage, quick speed of reading and writing, long service time, nondestructive access, low power, and in comparison with CMOS (complementary metal-oxide-semiconductor) high process compatibility, and therefore is regarded as one of the most powerful candidates of the next generation of “universal” memories.
At present, MOS transistor structures (metal-oxide-semiconductors, namely field effect transistors) are usually adopted as the driving device of the RRAM, and the RRAM is usually formed in the subsequent interconnection procedure of the MOS transistor. The integration structure of the RRAM and the MOS transistor in the prior art can be seen in FIG. 1, comprising a MOS transistor structure, a metal interconnection structure and a RRAM structure formed on a semiconductor substrate 100, wherein the MOS transistor structure comprises a source region 101, a drain region 102, a gate dielectric layer 103, a gate electrode 104, and an insulating layer 105 which isolates the gate region from other conductive layers of this unit; the metal interconnection structure comprises an interlayer isolating layer 106 in a primary layer interconnection, a diffusion blocking layer 107 and a copper interconnection line 108 in a contact hole, an etching blocking layer 109 and an interlayer isolating layer 110 in a second layer interconnection, and a diffusion blocking layer 111 and a copper interconnection line 112 in a contact hole of the second layer interconnection; the resistance random access structure comprises a resistance-variable material layer 113 and a conductive material layer 114, and the insulating layer 115 isolates the RRAM from other conductor layers of this unit.
As mentioned above, the integration structure of said resistance random accessory memory and said MOS transistor structure is complicated, is unfavorable for the integration of this unit and the development of this unit in the miniaturization direction.
USPTO Backgrounds
USPTO Backgrounds