1. Field of the Invention
The present invention relates to a process of manufacturing an interdigitated back-contact solar cell and the device manufactured thereby. Particularly, it relates to a process of manufacturing an interdigitated back-contact solar cell, in which a semiconductor material is used as a substrate to form an electrode with P-N junction on the back of the substrate by means of printing or spraying and chemical etching without any time-consuming photolithographic processes.
2. Description of Related Art
Traditionally, an interdigitated back-contact solar cell is based on crystalline silicon as a substrate material. A positive electrode and a negative electrode and a PN junction are formed on the back of a device in a manner that the P and N electrodes are interdigitated and a shallow front surface field (FSF) layer is formed on the front of the device so as to reduce the lateral resistance and enhance the rate of carrier collection.
Common interdigitated back-contact solar cells use N-type semiconductor material as substrates. The surface of the substrate is etched by a chemical etching solution to form a pyramid microstructure for the majority of solar light to enter the substrate. FIG. 2A partially shows a P-type metal electrode 15 and an N-type metal electrode 17 on a back surface of an interdigitated back-contact solar cell. In a large-area interdigitated back-contact solar cell, the back electrode consists of the fork-shaped P-type and N-type metal electrodes. The light receiving side of the N-type semiconductor substrate is disposed to form a micro-structure 10. FIG. 2B shows a cross-sectional structure of FIG. 2A cut along a broken line AB. In FIG. 2B, a N+ semiconductor layer 12 is grown on the light receiving side of a N-type semiconductor substrate 11 to form the front surface field for attracting those electrons close to the front of the N-type semiconductor substrate 11 and the P-type semiconductor layer 14. Those electrons then flow to the region of a back surface field, i.e. the N++ semiconductor layer 13. The advantage of the front surface field is to reduce the recombination of electrons and holes, and thus to enhance the fill factor and the photocurrent.
In addition, to reduce the recombination of electron-hole pairs, one important way is to increase emitter area on the back of the substrate, i.e. to increase the width of the P-type semiconductor layer 14 so as to improve the rate of collecting holes at the P-type metal electrode 15 and therefore to improve transport of electrons to the N++ semiconductor layer 13.
Conventionally, the above N+ semiconductor layer and the N++ semiconductor layer are individually subject to phosphorus doping. Alternatively, on the light receiving side of the semiconductor substrate 11 is first formed a buffer layer which is then subject to one-step phosphorus doping to produce a lightly doped layer on the light receiving side and a heavily doped layer, i.e. the N++ semiconductor layer 13, on the back. Subsequently, one photolithographic process is used to form a separated P-type semiconductor layer 14 which is positioned apart from the N++ semiconductor layer 13 in a staggered manner. FIG. 2C is a schematic view of an interleaved distribution of the P-type semiconductor layer 14 and the N++ semiconductor layer 13 according to the conventional invention. Thicker lines, respectively, correspond to the locations of wide area of P-type semiconductor layer 14 and the N++ semiconductor layer 13.
The antireflection layer 16 on the light receiving side of the semiconductor substrate 11 is used to reduce the energy reflected from the semiconductor substrate 11 and thus to generate more power. After the P-type semiconductor layer 14 and an N++ semiconductor layer 13 have been formed on the back of the semiconductor substrate 11, the oxide layer 18 is grown on the back of the substrate to repair defects on back surface of the substrate. Finally, the oxide layer is subject to a photolithographic process to form a trench in the oxide layer so as to partially expose the P-type semiconductor layer 14 and the N++ semiconductor layer 13 to form, respectively, the P-type metal electrode 15 and the N-type metal electrode 17 in the exposed areas. The P-type metal electrode 15 and the N-type metal electrode 17 are then subject to sintering for them to be in good contact with the back surface of the substrate. In the whole manufacturing process, the high-temperature diffusion process is performed at least twice, and multiple photolithographic processes are performed. The conventional process results in not only an increase in time and cost, but also a decrease in production rate, thus being unable to fulfill the demand of mass production. Therefore the method cannot be applied to the actual need for use.
In addition, U.S. Patent No. US20110070681 discloses the use of wet etching. However, the wet etching is used to process the surface micro-structure, rather than produce the trenches for the electrode. Its trenches are formed by laser and therefore is different from the present technique. U.S. Pat. No. 4,478,879 discloses the use of screen printing. However, the screen printing is not used to form trenches of electrodes, but instead used for doping and is therefore different from the present technique. Japanese Patent No. JP2012004565 discloses the screen printing and wet etching processes. However, the wet etching is used for processing surface microstructure, rather than to produce the trenches of electrodes. The screen printing is used to coat an etch paste for selectively etching a dielectric layer, rather than to form trenches of electrodes.
For this reason, the inventors has studied the related technology for many years based on the experiences of related manufacturing practice. After long-term research and efforts in development, the inventors has at last successfully developed this invention ‘a process of manufacturing an interdigitated back-contact solar cell’, which overcomes the shortages in the prior art.
USPTO Backgrounds
USPTO Backgrounds