Recent years have seen many more systems connecting a processor as an extension-side device on an extension bus as typified by PCIe (Peripheral Component Interconnect Express) or the like. In such a case, a synchronization processing mechanism is often required between a host-side processor and an extension-side processor or between a plurality of extension-side processors. Thus, in general, a method of performing synchronization processing by using host-side memory is known. For example, in PCIe, synchronization processing is performed by using memory in a root complex that is an element serving as a hierarchical root of a PCIe connection. Atomic operation defined by PCIe, flush operation to host-side memory by using a traffic class, and the like are mechanisms suitable to perform synchronization processing by using host-side memory.
One example of techniques relating to such synchronization processing between a plurality of processors is disclosed in Japanese Unexamined Patent Application Publication No. 2014-182795. The related technique disclosed in the patent literature performs synchronization processing between a plurality of logic processors in a processor by using shared memory.
In addition, another example of the techniques relating to synchronization processing between a plurality of processors is disclosed in Japanese Translation of PCT International Application Publication No. 2013-546035. The related technique disclosed in the patent literature performs synchronization processing between a host device and a graphics processing unit by using shared memory.
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