1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus receives data from outside, stores the data and outputs the stored data. Such a semiconductor memory apparatus receives data and a data strobe signal from outside, latches data inputted from outside, and stores the latched data.
FIG. 1 is a configuration diagram illustrating a typical semiconductor memory apparatus. Referring to FIG. 1, a typical semiconductor memory apparatus includes a first delay unit 10, a second delay unit 20, a data input enable signal generation unit 30, a latch control signal generation unit 40, and a data latch unit 50.
The first delay unit 10 delays data DATA inputted from outside to generate delayed data DATA_d.
The second delay unit 20 delays a data strobe signal DQS inputted from outside to generate a delayed data strobe signal DQS_d.
The data input enable signal generation unit 30 generates a data strobe enable signal DQS_en which is activated when a CAS write signal CASWT, which is generated upon receiving a write command, is activated. The data input enable signal generation unit 30 deactivates the data strobe enable signal DQS_en when a CAS write latency signal CASWT+4, which is activated after preset write latency upon receiving the write command, is activated.
The latch control signal generation unit 40 outputs the delayed data strobe signal DQS_d as a latch control signal latch_ctrl during the enable period of the data strobe enable signal DQS_en.
The data latch unit 50 latches the delayed data DATA_d in is response to the latch control signal latch_ctrl and provides latched data DATA_latch to the semiconductor memory apparatus. At this time, a delay time of the first delay unit 10 should be substantially equal to a delay time of the second delay unit 20.
The operation of the typical semiconductor memory apparatus configured as above will be described in detail with reference to FIG. 2 below.
When the write command WT is inputted to the semiconductor memory apparatus, the CAS write signal CASWT is activated. When two cycles of a clock CLK pass after the write command WT is inputted, write latency WL is counted. FIG. 2 illustrates an example in which write latency is 4. Referring to FIG. 2, the CAS write latency signal CASWT+4 should be activated at the time point WL+4 at which the write latency is 4, but the CAS write latency signal CASWT+4 is activated after a delay time A passes from the time point WL+4 due to internal delay.
The semiconductor memory apparatus delays the data strobe signal DQS by a delay time substantially equal to the delay time A to generate the delayed data strobe signal DQS_d.
The data strobe enable signal DQS_en is activated when the CAS write signal CASWT is activated, and is deactivated when the CAS write latency signal CASWT+4 is activated.
The semiconductor memory apparatus outputs the delayed data strobe signal DQS_d as the latch control signal latch_ctrl during the enable period of the data strobe enable signal DQS_en.
Referring to FIG. 1, the second delay unit 20 has the delay time A. Since the data strobe signal DQS has the delay time A, the delayed data DATA_d inputted to the data latch unit 50 should also be inputted to the data latch unit 50 after the delay time A passes. Thus, the first delay unit 10 is designed to have a delay time substantially equal to that of the second delay unit 20.
The data strobe signal DQS is toggled with the same phase as the clock CLK or has a high impedance state high-z (an intermediate level between a low level and a high level). If the data strobe signal DQS is toggled and enters the high impedance state, a ring back phenomenon may occur in which a voltage level unstably increases and decreases. Since the ring back phenomenon may cause a serious data error in the semiconductor memory apparatus, it is designed that the latch control signal latch_ctrl is generated by delaying the data strobe signal DQS by the delay time A.
However, since the typical semiconductor memory apparatus latches the data DATA through the first delay unit 10 and the second delay unit 20, a data storage speed of the semiconductor memory apparatus is lowered, area efficiency is reduced due to the addition of the delay logic, and power consumption is also increased.
USPTO Backgrounds
USPTO Backgrounds