1. Field of the Invention
The present invention relates to a technique for forming an oxide film on a wafer having an SOI (Silicon on Insulator) structure and to a technique for fabricating a bonded wafer having an SOI structure in which two mirror-polished silicon wafers are bonded together without use of adhesive, one of the wafers subsequently being made very thin.
2. Description of the Related Art
Two methods have been widely noticed as methods for fabricating wafers having an SOI structure. One method is a SIMOX (separation by implanted oxygen) method in which oxygen ions are implanted into a silicon monocrystal at a high concentration, and heat treatment is then performed at a high temperature in order to form an oxide film. The other method is a bonding method in which two mirror-polished silicon wafers are bonded together without use of adhesive, one of the wafers subsequently being made very thin.
In the SIMOX method, the thickness of an SOI layer that becomes a device active region can be determined and controlled through adjustment of an acceleration voltage at the time of oxygen ion implantation. Therefore, the SIMOX method has an advantage of enabling easy formation of a thin SOI layer having a high uniformity of thickness (hereinafter called "thickness uniformity"). However, the SIMOX method has many problems in relation to the reliability of a buried oxide film, the crystallinity of the SOI layer, and necessity of heat treatment at a temperature of 1300.degree. C. or higher.
Meanwhile, in the wafer bonding method, an oxide film is formed on at least one of two mirror-polished silicon monocrystalline wafers, which are bonded together without use of adhesive and then subjected to heat treatment (typically, at 1100-1200.degree. C.) in order to strengthen the bonding; subsequently, one of the wafers is subjected to grinding or wet etching such that the wafer becomes a thin film, the surface of which is then mirror-polished to form an SOI layer. Therefore, the reliability of the buried oxide film is high, and the crystallinity of the SOI layer is good. However, since the thin film is formed by means of mechanical machining, there are limits in relation to the thickness and the thickness uniformity of the resultant SOI layer.
However, a further reduction of the thickness of an SOI layer has been demanded in order to cope with an increased degree of integration and an increased speed of semiconductor devices, and there has arisen demand for a very thin SOI layer having a thickness of 1 .mu.m or less. Therefore, in order to enable such a very thin SOI layer to be fabricated through use of a bonded wafer and to decrease the thickness of the SOI layer to a level equal to or less than that obtained according to the SIMOX method, thereby enabling the bonded wafer to be used as a future CMOS substrate, the SOI layer must be machined to a thickness and accuracy of 0.1 .mu.m.+-.0.01 .mu.m at least.
In order to realize a thickness and accuracy of 0.1 .mu.m.+-.0.01 .mu.m in a bonded wafer, a so-called PACE (plasma assisted chemical etching) method has been developed, and is disclosed in Japanese Patent Application Laid-Open (kokai) No. 5-160074. In the PACE method, the thickness of a thin film is made uniform through vapor-phase etching. The distribution of thickness of a silicon layer whose thickness is to be made uniform is measured to form a map of thickness distribution; and the vapor-phase etching is numerically controlled in accordance with the map in order to locally remove thicker portions, thereby fabricating a very thin film having a very high thickness uniformity.
However, in the above-described PACE method, since the surface of a thin film is removed through use of RF plasma, slight damage is generated at the surface of an SOI layer. Also, when an SOI layer is treated under the PACE method, periodic fine roughness having a period of 0.01-5 .mu.m, so-called haze, may be newly generated on the surface of the SOI layer. Therefore, in order to eliminate the haze, polishing for removing a very small amount of stock, called touch polishing, must be performed after completion of the process according to the PACE method. However, when an SOI layer that had undergone touch polishing was evaluated in accordance with a four-step Secco-etching disclosed by H. Gassel et al. (J. Electrochem. Soc., 140, pp 1713, 1993), it was found that high density crystal defects existed at the surface of the SOI layer. That is, use of touch polishing does not eliminate damage and crystal defects generated during the process according to the PACE method, or the touch polishing itself generates damage and crystal defects. These residual damage and crystal defects adversely affect the electrical characteristics of devices.
In order to remove damage and crystal defects generated during the process according to the PACE method, the applicant of the present application has proposed a method disclosed in Japanese Patent Application No. 8-94855, in which an SOI layer is subjected to thermal oxidation after touch polishing in order to form an oxide film, which is then removed by an amount corresponding to the thickness of damage and crystal defects. However, a satisfactory result has not been obtained, and therefore a further decrease in damage and crystal defects has been demanded.
The reason for failure to obtain a satisfactory result has been investigated through use of four-step Secco-etching. From the evaluation through use of four-step Secco-etching, it was found that when an SOI wafer is subjected to a thermal oxidation process after touch polishing, crystal defects may be newly introduced due to thermal oxidation, depending on the conditions therefor.
USPTO Backgrounds
USPTO Backgrounds