This invention relates generally to storage devices and more particularly, it relates to a selectable multi-input CMOS data register.
Prior art CMOS data registers typically requires the use of a plurality of inverters and transmission gates connected in series for clocking in and holding data in both a master section and a slave section. The data is refreshed by feedback loops which are activated during a non-active clock cycle. Each inverter and each transmission gate is formed of a P-channel MOS transistor and an N-channel MOS transistor. Due to the differences in conductivity type, either the P-channel transistor or the N-channel transistor must be in a separate well. For instance, the P-channel transistor may be formed in an N-well. As a result, the two transistors which form the inverter or transmission gate must be physically separated. Therefore, the interconnection between the P-channel and N-channel transistor is typically longer than the conventional connection between transistors of like conductivity. Further, the interconnection of the transistors of different conductivity increases the layout complexity and thus utilizes more chip area.
In addition, the design of the prior art CMOS data register suffers from the disadvantage of requiring a high number of transistors circuit components. This tended to cause a rather heavy loading on a clock generator which provides the clock signal. It would therefore be desirable to provide a CMOS data register which is formed mainly of transistors of one conductivity type. Further, it would be expedient to reduce the transistor count so as to minimize the amount of chip area used and thus provide a less heavier load to be driven by a clock generator.
USPTO Backgrounds
USPTO Backgrounds