For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits.
Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing the appropriate stress/strain into the semiconductor lattice.
The application of stress changes the lattice dimensions of the semiconductor substrate. By changing the lattice dimensions, the electronic band structure of the material is changed as well. This results in changes in carrier transport properties such as carrier scattering rates and effective mass, which can be dramatic in certain cases. The application of physical stress (tensile or compressive) can be further used to enhance the performance of devices fabricated on the semiconductor substrates.
Compressive strain along the device channel increases drive current in p-type field effect transistors (pFETs) and decreases drive current in n-type field effect transistors (nFETs). Tensile strain along the device channel increases drive current in nFETs and decreases drive current in pFETs.
Stress can be introduced into a single crystal oriented substrate by several methods including, for example, forming a stress liner on top of the substrate and around the gate region. Depending on the conductivity type of the FET (i.e., p or n), the stress liner is optimally under tensile stress (preferred for nFETs) or compressive stress (preferred for pFETs). When nFETs and pFETs are integrated onto the same semiconductor substrate, dual stress liner technology is typically used in which a first stress liner under tensile stress is formed around each nFET, while a second stress liner under compressive stress is formed around each pFET. It is noted that the order of forming the stress liners may be variable. For example, the compressive stress liner may be formed prior to the tensile stress liner or visa versa.
However, the boundary between tensile and compressive stress liners in dual stress liner (DSL) technology also induces stress in the substrate, which can influence transistor performance as well. When the DSL boundary is in close proximity (with a lateral distance of about 5 microns or less) from an FET, and oriented parallel to the gate region, a degradation of the devices in proximity to the boundary has been observed. Degradation of 25% pFET and 18% nFET (saturation current at a fixed overdrive) have been demonstrated on recent CMOS structures, which is solely attributed to the DSL boundary influence mentioned above.
Reference is now made to FIGS. 1A-1D which illustrates the DSL boundary influence in greater detail for the case in which the tensile stress liner is formed prior to the formation of the compressive stress liner; in this case the compressive stress liner overlaps a portion of the tensile stress liner. FIG. 1A illustrates a portion of a non-stressed semiconductor substrate 100 that has a tensile stress liner 102 formed on a surface thereof. It is noted that no FET structures are shown in FIG. 1A since they lay to the periphery of the portion of the substrate 100 shown in FIG. 1A. The FETs are formed prior to disposing the tensile stress liner 102 on the substrate.
FIG. 1B illustrates the structure of FIG. 1A after patterning the tensile stress liner 102 by lithography and etching. As shown, an edge force 106 is created on the substrate 100. Moreover, the tensile stress liner 102 creates local stress in the substrate that decays with distance from the etched edge of the liner 102. In FIG. 1B, reference numeral 108 denotes a region of the substrate 100 under compression, while reference numeral 110 denotes a region of the substrate under tension. The dotted line (designated as 112) denotes a zero stress line.
FIG. 1C illustrates the structure of FIG. 1B after forming a compressive stress liner 114 thereon. The overlap region (i.e., boundary) 119 of the dual liners magnifies the edge force 106. Depending on the relative strengths of the tensile and compressive liners, the zero stress contour can take the form of 112, or either of the two other contours indicated by 112′.
FIG. 1D is an expanded view of FIG. 1C showing the presence of an FET 120 on a surface of the substrate 100. In this drawing, the substrate is under the following stresses (i) compression (c) under the FET 120 (from left spacer outer edge to right spacer outer edge), (ii) tension (t) beneath the compressive liner 114, and (iii) compression (c) under the tensile liner 102.
The problem with such a structure is that the dual stress liner boundary 119 is in longitudinal proximity to the FET 120 which results in substantial degradation of the performance of the FET. The term “longitudinal proximity” is used in the present application to denote that the dual stress liner boundary 119 is located at a distance lengthwise from the FET that is about 5 microns or less. This degradation is observed for both nFETs and pFETs. In particular, it was been found that the longitudinal stress, which is related to the dual stress liner boundary 119, reduces the stress in the FET channel.
One solution to this dual stress liner boundary problem is to design an integrated circuit in which the longitudinal boundaries are placed far away (a longitudinal distance of greater than 5 microns) from the FET devices. Although such a solution is feasible, it does come with an area penalty that increases the overall size of the integrated circuit. Such an increase in size contradicts the current trend in shrinking integrated circuits.
As such, a method is needed which overcomes the dual stress liner boundary problem without significantly increasing the overall size of the integrated circuit.
USPTO Backgrounds
USPTO Backgrounds