1. Field of the Invention
This invention relates to integrated circuit structures with reduced capacitance. More particularly, this invention relates to the formation of an integrated circuit structure with a layer of low dielectric constant dielectric material formed between horizontally closely spaced apart metal lines of an integrated circuit structure to reduce horizontal capacitance between closely spaced apart metal lines, while via poisoning in vias formed through a second layer of standard k dielectric material down to the metal lines is mitigated due to the presence of silicon nitride caps on the metal lines.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled xe2x80x9cPursuing the Perfect Low-K Dielectricxe2x80x9d, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH3xe2x80x94SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400xc2x0 C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Trikon process.
The use of this type of low k material has been found to result in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the horizontal capacitance between such adjacent metal lines on the same metal wiring level.
However, the substitution of such low k dielectric materials for conventional silicon oxide insulation has not been without its own problems. It has been found that the subsequent formation of vias, or contact openings, through such low k dielectric material to the underlying conductive portions (such as metal lines, or contacts on an active device), can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces, resulting in unfilled vias. Apparently the presence of carbon in the low k dielectric material formed by the Trikon process renders the material more susceptible to damage during subsequent processing of the structure. For example, contact openings or vias are usually etched in the low k dielectric layer through a resist mask. When the resist mask is subsequently removed by an ashing process, damage can occur to the newly formed via surfaces of the low k material resulting in such via poisoning.
Copending U.S. patent application Ser. No. 09/426,061, entitled xe2x80x9cLOW DIELECTRIC CONSTANT SILICON OXIDE-BASED DIELECTRIC LAYER FOR INTEGRATED CIRCUIT STRUCTURES HAVING IMPROVED COMPATIBILITY WITH VIA FILLER MATERIALS, AND METHOD OF MAKING SAMExe2x80x9d, was filed Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of Ser. No. 09/426,061 is hereby incorporated by reference. In one embodiment in that application, low k silicon oxide dielectric material having a high carbon doping level is formed in the high aspect ratio regions between closely spaced apart metal lines and then a second layer comprising a low k silicon oxide dielectric material having a lower carbon content is then deposited over the first layer and the metal lines.
U.S. Pat. No. 6,391,795, issued May 21, 2002, entitled xe2x80x9cLOW K DIELECTRIC COMPOSITE LAYER FOR INTEGRATED CIRCUIT STRUCTURE WHICH PROVIDES VOID-FREE LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE MITIGATING VIA POISONINGxe2x80x9d, was also filed on Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of U.S. Pat. No. 6,391,795 is also hereby incorporated by reference. In one embodiment in that application, a void-free low k silicon oxide dielectric material is formed in the high aspect regions between closely spaced apart metal lines by one of several processes, including the process used to form the first low k silicon oxide dielectric material described in the previously cited Ser. No. 09/426,061 patent application. A second layer of low k silicon oxide dielectric material is then deposited over the first layer and the metal lines by a process which deposits at a rate higher than the deposition rate of the void-free dielectric material. In a preferred embodiment, both of the layers are formed in the same vacuum chamber without an intervening planarization step.
U.S. Pat. No. 6,423,628, issued Jul. 23, 2002, entitled INTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINES, was also filed on Oct. 22, 1999 and assigned to the assignee of this application. The subject matter of U.S. Pat. No. 6,423,628 is also hereby incorporated by reference. In that application the use of a silicon oxynitride capping layer over metal lines was suggested to provide an antireflective coating which could also function as a etch stop layer for a CMP planarizing process used to remove from over the metal lines portions of low k dielectric material used to fill the space between the metal lines. A second layer of standard k dielectric material was then formed over the silicon oxynitride capping layer and the low k dielectric material between the metal lines. Vias formed through the second dielectric layer and the silicon oxynitride capping layer down to the metal lines do not intersect the low k dielectric material and via poisoning is thereby prevented.
Thus, it is highly desirable to provide an integrated circuit structure having a low k dielectric layer, and a process for making same, wherein a dielectric layer is formed comprising low k silicon oxide dielectric material for high aspect ratio regions between closely spaced apart metal lines while mitigating the poisoning of vias subsequently formed in a dielectric layer down to the metal lines.
In accordance with the invention, a sacrificial chemical mechanical polishing layer of silicon nitride is formed over a metal layer on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Both the sacrificial polishing layer and the metal layer are then patterned to form horizontally closely spaced apart metal lines, each having a silicon nitride cap.
Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between closely spaced apart metal lines is then deposited over and between the closely spaced apart metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material. This second silicon nitride layer acts a protective layer over portions of the layer of low k silicon oxide dielectric material between the metal lines which may be lower that the top surface of the silicon nitride caps on the metal lines to prevent further etching or dishing of those portions of the layer of low k silicon oxide dielectric material during the planarizing step.
The structure is then planarized by a process such as a CMP process to remove all low k dielectric material on the top surface of the silicon nitride caps over the metal lines and to bring the level of the low k material between the metal lines (and the second layer of silicon nitride thereon) down to the level of the tops of the silicon nitride caps on the metal lines. A second layer of standard k dielectric material is then formed over the planarized low k dielectric layer and the silicon nitride caps. Vias are then formed through the further dielectric layer and the silicon nitride caps down to the metal lines. Since the vias are not formed through the low k dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.
USPTO Backgrounds
USPTO Backgrounds