There is an increasing demand for semiconductor memories that can be electrically erased and programmed without the need for refreshing data stored in the memory. Also, there is a trend toward enhancing the storage capacity and the density of integration in memory devices. NAND-type flash memory is one example of a nonvolatile semiconductor memory that provides high capacity and integration density without the need for refreshing stored data.
FIG. 1 contains a block diagram of an array of memory cells and conventional page buffers assigned to the array in a NAND-type flash memory. The memory includes a memory cell array 10, a page buffer circuit 20 and a Y-pass gate circuit 30 (or referred to as "a switch circuit"). The memory cell array 10 is formed of a plurality of strings 12 (a "string" is a cell unit corresponding to one bit of data) arranged in columns. Each string 12 includes a string selection transistor SSTi (i=0, 1, . . . , m), the gate of which is coupled to a string selection line SSL. Each string 12 also includes a ground selection transistor GSTi (i=0, 1, . . . , m), the gate of which is coupled to a ground selection line GSL. Memory cells MCj (j=0, 1, . . . , n) are connected in series between each string selection transistor SSTi and its associated ground selection transistor GSTi. Control gates of the memory cells are coupled to word lines WLj (j=0, 1, . . . , n). The drain of each string selection transistor SSTi is connected to its corresponding bit line Bli (i=0, 1, . . . , m), and the source of each ground selection transistor GSTi is connected to a common source line CSL.
The page buffer circuit 20 includes page buffers 20_i (i=0, 1, . . . , m) corresponding to the bit lines BLi, respectively. During a read operation, a page buffer senses data from a selected memory cell and then transfers the data to a data bus DB through the Y-pass gate circuit 30. Hereinafter, even page buffer 20_0, corresponding to bit line BL0, is referred to in describing its constructions. Other page buffers 20_1 to 20_m, corresponding to other bit lines BL1 to BLm, have the same constructions and functions as those of the page buffer 20_0.
The page buffer 20_0 includes PMOS transistor M2, six NMOS transistors M1 and M3 to M7, a latch 40 formed of a pair of inverters INV1 and INV2, and tri-state inverter INV3. The NMOS transistor M1, whose gate is coupled to signal BLSHF, is connected between a sensing node N1 and a corresponding bit line BL0 to adjust a voltage level of the bit line BL0 which is developed while being activated and to prevent the page buffer 20_0 from being influenced by a high voltage when the high voltage is applied to BL0. The gate and source of the PMOS transistor M2, the drain of which is connected to the sensing node N1 (at the drain of M1), are connected to a signal CURMIR and a power supply voltage Vcc, respectively. The PMOS transistor M2 supplies current to the bit line BL0 in response to the signal CURMIR.
As seen from FIG. 2, the inverter INV1 of the latch 40 is formed of two PMOS transistors M12 and M13 and one NMOS transistor M14 connected as illustrated in FIG. 2, and the inverter INV2 of the latch 40 is formed of CMOS inverter well known in the art. The PMOS transistor M12 is controlled by a signal PBset, which from FIG. 1 will be understood to be inactivated only when the NMOS transistor M3 is turned on (i.e. only during a discharge period of the read operation when DCB is active (high)). This is to prevent power noise from being generated when the page buffers are reset and the bit lines are discharged.
Referring again to FIG. 1, the NMOS transistor M3 has its source and gate connected to a ground voltage Vss and a signal DCB, respectively, and is connected between the sensing node N1 and the ground voltage Vss. The transistor M3 discharges a voltage of the bit line BL0 and resets the page buffer 20_0 output to a ground level. The NMOS transistor M4, the gate of which is coupled to a signal SBL, is connected between a node N2 of latch 40 and the sensing node N1. The drain of the transistor M4 is connected to the Y-pass gate circuit 30 through tri-state inverter INV3, the state of which is controlled by signals Osac and nOsac (the complement of Osac). Data in the latch 40 is transferred to the data bus DB through the tri-state inverter INV3 and the Y-pass gate circuit 30. Data to be programmed is transferred to the node N2 of the latch 40 through the NMOS transistor M7, the gate of which is coupled to a signal SPB. Node N3 (a complementary node of N2) of latch 40 is connected to Vss through the NMOS transistor M5, whose gate is coupled to the sensing node N1, and the NMOS transistor M6, whose gate is coupled to a signal Olatch. The NMOS transistors M5 and M6 thus set the state of data stored in the latch in response to a voltage level on the bit line BL0.
According to the conventional page buffer as described above, when data held in the latch 40 is transferred to the data bus DB during read and program operation, the tri-state inverter INV3 not only drives the data bus DB in response to a voltage level of the node N2, but also prevents charges on the node N2 from being discharged to the data bus DB. However, the data path of the conventional page buffer is divided into an input path formed of the NMOS transistor M7 and an output path formed of the tri-state inverter INV3. And, the tri-state inverter INV3 is formed by use of multiple MOS transistors and power lines as well known to ones skilled in the art. For this reason, the conventional page buffer has a high component count that renders it difficult to lay out the tri-state inverters in the page buffers 20_i within a page buffer region of the flash memory device in which higher capacity and integration density are required.
USPTO Backgrounds
USPTO Backgrounds