1. Technical Field
This invention relates in general to managing translations using a translation lookaside buffer (TLB) and more particularly to managing translations across multiple contexts using a TLB including entries directed to multiple privilege levels and to multiple types of address spaces.
2. Description of the Related Art
Modern computer systems typically utilize a virtual memory system to address very large amounts of memory in one or more virtual address spaces, even though the main memory of the system populates a much smaller portion of physical memory address space. To map a virtual address to an address within the virtual address space to a physical memory address space, an operating system (OS) maps the virtual address space for each process to the actual physical address space for the system. The OS may maintain page tables to use for mapping a virtual address to a physical address.
Some virtual memory systems implement a specialized cache to store the last translation of a virtual address to physical address accessed from a page table. For example, a translation lookaside buffer (TLB), within a small section of memory in a processor pipeline, easily accessible to the processor, caches part of the system's virtual address to physical address translation. By storing recently mapped virtual address to physical address translations in a TLB, upon a next request for the same virtual address, a processor can quickly access a translation of the virtual address into a physical address from a previously stored entry in the TLB. If a translation for a particular virtual address is not present in the TLB, a “translation miss” occurs and the address translation is resolved from page tables.
Many computer systems implement a virtualization layer, such as a hypervisor, which manages one or more logical partitions (LPARs) on a server system, each LPAR functioning as self-contained platforms and each LPAR running its own instance of an operating system and other software. In one example, the operating system run by an LPAR is referred to as a guest operating system (OS) and the software run by an LPAR is referred to as guest software. The virtualization layer manages control over events and hardware resources on the underlying platform to interface between LPARs and the resources for protection from and between guest software running on different LPARs.
Within a system that supports multiple processes, operating on multiple LPARs, context switches may occur when a multi-tasking guest OS on an LPAR stops running one process and begins running another. Similarly, in a system that supports multiple LPARs, context switches occur when a processor shifts a control level of a hypervisor on or off.
USPTO Backgrounds
USPTO Backgrounds