Photolithography is commonly utilized during integrated circuit fabrication. Photolithography comprises patterning of photoresist by exposing the photoresist to a pattern of actinic energy, and subsequently developing the photoresist. The patterned photoresist may then be used as a mask, and a pattern may be transferred from the photolithographically-patterned photoresist to underlying materials.
A continuing goal in semiconductor processing is to reduce the size of individual electronic components, and to thereby enable smaller and denser integrated circuitry. A concept commonly referred to as “pitch” can be used to quantify the density of an integrated circuit pattern. A photolithographic technique will tend to be constrained by a minimum pitch below which the particular photolithographic technique cannot reliably form features. The minimum pitches associated with photolithographic techniques present obstacles to continued feature size reduction in integrated circuit fabrication.
Pitch multiplication, such as pitch doubling, is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch.
In some applications, it is desired to form different levels of pitch multiplication across different regions of a semiconductor substrate. For instance, it may be desired to perform pitch-doubling along one region of a semiconductor substrate, and to perform pitch-quadrupling along another region of a semiconductor substrate. It can be advantageous to utilize common process steps when forming the different levels of pitch multiplication in that such may improve economy associated with a fabrication process. However, it can be difficult to develop appropriate processing to combine steps of the different levels of pitch multiplication without also introducing other complexities into the fabrication process which offset the gains achieved from the combined steps.
It is desirable to develop new methodologies for pitch multiplication, and to develop processes for applying such methodologies to integrated circuit fabrication. It is further desirable to develop methodologies for pitch multiplication which may efficiently enable multiple common steps to be performed while achieving different levels of pitch multiplication across different regions of a semiconductor substrate.
USPTO Backgrounds
USPTO Backgrounds