1. Field of the Invention
The instant disclosure relates to a high-voltage level conversion circuit; in particular, to a high-voltage level conversion circuit that needs less circuit area.
2. Description of Related Art
Please refer to FIG. 1 showing a schematic of a conventional high-voltage level conversion circuit. The conventional high-voltage level conversion circuit 1 has a first stage circuit 110 and a second stage circuit 120. The input voltage of the first stage circuit 110 is the first voltage level VSS or the second voltage level VDD, wherein VDD>VSS. The first stage circuit 110 comprises NMOS transistors 111, 112 and PMOS transistors 113, 114. The second stage circuit 120 comprises NMOS transistors 121, 122 and PMOS transistors 123, 124. The circuit of the first stage circuit 110 and the second stage circuit 120 are depicted in FIG. 1.
The first stage circuit 110 converts VDD or VSS of the input signal to the third voltage level VGH or VSS for output, wherein VGH is corresponding to VDD. In other words, the first stage circuit 110 maintains VSS (that VSS is not changed), and converts the high-voltage level (which is VDD) of the input signal to VGH.
Further, the second stage circuit 120 respectively converts VSS and the VGH of the input signal (coming from the first stage circuit 110) to the fourth voltage level VGL and the VGH, wherein VGL is corresponding to VSS. In other words, the second stage circuit 120 maintains VGH and converts the low voltage level (which is VSS) of the input signal to VGL.
However, in order to meet the required transition ability and response speed, the NMOS transistors 111, 112 and the PMOS transistor 123, 124 usually need to provide wider channel width for providing larger current, therefore the circuit area is dominated by the NMOS transistors 111, 112 and the PMOS transistors 123, 124. Accordingly, the larger circuit area causes more manufacturing cost of the circuit.
USPTO Backgrounds
USPTO Backgrounds