Microelectronic devices are fabricated on semiconductor wafers using a variety of techniques, e.g. including deposition techniques (CVD, PECVD, PVD, etc.) and removal techniques (e.g. chemical etching, CMP, etc.). Semiconductor e.g. silicon wafers may be further treated in ways that alter their mass e.g. by cleaning, ion implantation, lithography and the like.
Depending on the device being manufactured, each wafer may be passed sequentially through hundreds of different processing steps to build up and/or to remove the layers and materials necessary for its ultimate operation. In effect, each wafer is passed down a production line. The nature of semiconductor manufacturing means that certain processing steps or sequences of steps in the production flow may be repeated in a similar or identical fashion. For example, this may be to build up similar layers of metal conductors to interconnect different parts of the active circuitry.
The cost and complexity of the processing steps required to produce a completed silicon wafer together with the time that it takes to reach the end of the production line where its operation can be properly assessed has led to a desire to monitor the operation of the equipment on the production line and the quality of the wafers being processed throughout processing so that confidence in the performance and yield of the final wafers may be assured.
A single semiconductor wafer may include many different devices manufactured by many different techniques. For example, logic and memory device may be created using CMOS fabrication methods, whilst other bipolar and compound semiconductor devices may be created using a different type of planar transistor fabrication technology. In future, several devices may be regularly fabricated together on a single chip or made separately and mounted on a common platform and connected together. Future devices may also use 3D integration techniques, where the devices are connected through the complete wafer.
It is known to use Statistical Process Control (SPC) to monitor variability in the many processes involved in fabricating a typical semiconductor device. This may involve, for any given process step, setting upper and lower limits for one or more measurable parameters which are indicative of the result of the process step based on a normal distribution and mean and measuring those parameters at one or one measurement sites on a sample (or on each) of the semiconductor wafers subject to the process step to ensure that they fall within the set limits. Ellipsometry measurements can be used for SPC purposes.
A development of SPC that is used in some process steps is Advanced Process Control (APC), which is able to use measurements to adjust the process. SPC measurements may be used as feedback to adjust a given process for subsequent wafers. Alternatively, SPC measurements may be used to feed forward information e.g. to adjust later process steps for a given wafer to compensate for variations in an earlier process step.
However, many existing metrology techniques used for SPC are limited by their ability to measure certain types of material or indeed certain processes. For example, ellipsometry can only measure optically transmissive films; it is not possible to use it with opaque films. Similarly, resistivity probes can only measure metals (not dielectrics). Furthermore, both of these techniques are limited to use with deposited layers; they cannot measure etched or recessed structures.
Another typical limitation of known SPC measurement techniques is the difficulty of measuring product wafers. In some cases, special areas (test sites) are built into the design of a wafer to check the performance of a process step. One problem with such areas is that they are not necessarily representative of what happens on real device structures and are therefore of limited value. Test wafers are an alternative solution, wherein similar processes are carried out on the test wafer structures and measured with the premise that if the process meets specification on the test wafer, then the process will meet specification on the product wafer. However, the increasing cost and complexity of wafer fabrication means that scrapped product wafers and test wafers are becoming uneconomical. Furthermore, test sites on wafers are undesirable as they use up value space, i.e. reduce the number of devices that may be fabricated, hence impacting on productivity.
In WO 02/03449 the present inventors disclosed a way to measure changes in mass very accurately when semiconductor wafers are processed. A common feature of many semiconductor device fabrication steps is that material will be added or removed. In WO 02/03449, it was suggested that SPC could be applied to deposition process steps using the accurate mass measurement method.
USPTO Backgrounds
USPTO Backgrounds