1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a process of forming small transistors with low leakage and acceptable threshold voltages.
2. Description of Related Art
In the field of semiconductor devices, transistors must simultaneously exhibit high performance and low power characteristics. These two parameters typically compete with one another. As transistor channel lengths decrease, for example, to improve the speed of a device, other parameters such as the subthreshold leakage and the threshold voltage can become more difficult to control. Conventionally, doped transistor channels are employed to control threshold voltages within a desired range. These doped channels are frequently achieved using ion implantation.
Recently, silicon on insulator (SOI) technology has been used to achieve lower power consumption. In addition, gate lengths are being scaled down with each new process technology. The shallow channels needed for SOI and deep sub-micron devices are difficult to achieve consistently with conventional channel doping implants. Without these doped channels, however, it is difficult to fabricate deep sub-micron devices that exhibit sufficiently low leakage current, adequate threshold voltages, and acceptably low threshold voltage variation. It would be desirable, therefore, to implement a process and resulting transistor having a short channel length, adequate threshold voltage, and low subthreshold leakage without significantly increasing the cost or complexity of the process.
USPTO Backgrounds
USPTO Backgrounds