The invention relates to a computer in accordance with the preamble of claim 1, which comprises a plurality of plug-in cards.
The like computers are used in manifold designs and may particularly be employed when it is a matter of flexibly solving various tasks through several system plug-in cards and peripheral plug-in cards. As system plug-in cards it is, e.g., possible to use plug-in cards acting as bus masters. As peripheral plug-in cards it is possible to employ plug-in cards providing most variegated functions, for example performing input/output to cache memories, acquisition and processing of signals, outputting correspondingly processed signals for controlling, e.g., control elements intervening in industrial processes, but also communication components for transferring the data flow in a processed manner from and to the computer, for example via digital telephone lines.
In modern computers it is also possible to apply several system plug-in cards in order to increase computing speed and data throughput depending on the user""s requirements, or on the other hand to be able to simultaneously solve various tasks by using one computer.
One problem of such plural master or system plug-in cards resides in the fact that their clock signals must be synchronized. In low-cost bus systems one frequently reverts to providing a bus clock signal which is many times slower than the local system clock. The PCI bus, for example, is designed for a maximum clock frequency of 66 MHZ.
It has therefore already been suggested to fundamentally define one plug-in place, or slot, as a clock or master slot and supply the clock signal thereof to the other plug-in places, thus also to those plug-in places provided for system plug-in cards.
In this proposal it is, however, particularly disadvantageous that a constant precondition is to at least also mount the system plug-in card in the master plug-in place of the bus; in a case where the respective plug-in card is missing if only for testing purposes, the computer will be blocked altogether as it will then not be possible to generate slave clocks.
This system of a master plug-in place, for example in slot 1, fundamentally is in contradiction with the concept of a universal bus.
A universal bus should be functional independent of whether or not a particular plug-in place is provided with a particular card, at least when the bus is designed as a genuine bus, i.e. with mutually corresponding signals at the respective plug-in jacks.
Moreover it is known from U.S. Pat. No. 5,524,237 to synchronize clock signals between two microprocessors with each other. To this end, the clock lines of the two microprocessors are mutually connected with each other. Depending on whether a respective microprocessor receives or transmits data, clock input and clock output are toggled, so that the associated clock will correspondingly be active for data supplied by a microprocessor.
Herein the particular expenditure for the software-side synchronization constitutes a drawback. In addition, when the transmission direction is switched over by means of a kind of safety circuit, it must be made sure that the respective other microprocessor will generate the clock following completion of data transmission by a microprocessor. It is disadvantageous that this circuit permits not a genuine bus operation but merely the coordination of two microprocessors capable of mutually supplying data.
From DE 42 40 145 a system bus with a plurality of boards is known. If a master board fails, there will be no clock signal on the system bus and means are provided to generate clock signals locally on each board. The disadvantage of this system is, however, that the local clock signals are not synchronized to each other.
Furthermore it has already been suggested to split clock signals in genuine bus systems between system plug-in cards and peripheral plug-in cards, whereby it is possible to provide several clock signals through the bus. A proposed specification permits a maximum deviation of 2 ns between the clock signals of two bus plug-in cards.
Particularly when buffered slave clocks are additionally provided, it is difficult to observe this time frame.
In order to improve signal quality, it has become known in this context to terminate the bus lines. Nevertheless this does not take into account those problems possibly resulting from the use of several system plug-in cards.
The invention is therefore based on the object of furnishing a computer in accordance with the preamble of claim 1, which permits a flexible configuration despite the realization of fast clock signals through the bus.
This object is attained in accordance with the invention by claim 1. Advantageous developments result from the appended claims.
In accordance with the invention it is particularly favorable that a fast system clock is generated under the condition that a universal plug-in card is inserted in any place whatsoever of the bus, either in peripheral or system plug-in places.
It is furthermore particularly favorable in accordance with the invention that automatically, by insertion in the corresponding location, a universal plug-in, card will or will not output a clock signal as a basic system clock. This function is fulfilled in accordance with the invention by a tristate buffer circuit wherein as a result of inserting the card at a system plug-in place, the internally generated clock signal is looped through, whereas this very feed-through is suppressed upon insertion in a peripheral plug-in place; as a result, there is no danger of a system plug-in card inserted there outputting a clock signal on a same bus line concurrently with another system plug-in card, in which case the operation of two logic circuits would be in mutual conflict.
In accordance with an advantageous design it is provided to form only one plug-in place as a system plug-in place independently of how the bus or the backplane is equipped, a clock collision may accordingly be automatically prevented from occurring in this embodiment. It is nevertheless possible to readily use several universal plug-in cards, so that flexible and mixed mounting may be used depending on the customer""s profile of requirements.
In accordance with a particularly favorable design it is provided to form the clock terminal for the clock plug-in contact as a bi-directional path. Depending on the application case, the line path may then be used for inputting the clock signal into the bus or for supplying the clock signal from the bus to the plug-in card.
In accordance with a particularly favorable aspect of the invention it is possible to use an ASIC for realization of a bus bridge circuit. When the system bus has the form of a CompactPCI bus, the ASIC may operate as a PCI-to-PCI bridge, and a local PCI bus serving as a local bus, for example of a peripheral plug-in card, may additionally be provided.
In accordance with another advantageous design of this aspect, the ASIC may then also be mounted in a rotated position so as to provide the clock control function depending on the application case, also with respect to the local PCI bus. To this end, a symmetrical pin design of the ASIC is necessary.
According to an advantageous development of the invention, means are provided to reduce the skew between clock lines, e.g., the bus slave clock lines or when switching between the two different conditions of the universal plug-in card.
Different line lengths for propagating the clock lead to different propagation times. Also, buffers and all other asynchronous logic circuits vary in delay time. Yet, it would be desirous to have all clock signals synchronized. With an important aspect of the invention, both internal and external skew is reduced such that the clock handling of the plug-in card according to the invention is independent from production parameters when producing gates or buffers. Moreover, the influence from voltage and temperature deviations is reduced. With the internal skew optimization circuit, the skew is reduced to 20 ps, and the overall skew is reduced to 100 ps.
According to a specifically advantageous aspect of the invention, there is a skew optimization arrangement on the plug-in card which delays the clock signal exactly by the same time when acting as system plug-in card as the propagation time via the bus clock line when acting a peripheral plug-in card
USPTO Backgrounds
USPTO Backgrounds