1. Technical Field
The present invention relates to limited switch dynamic logic circuits, and more particularly to high-speed time division multiplexed limited switch dynamic logic circuits to enable high-speed double pumping.
2. Description of the Related Art
Whether by frequency scaling or parallelism, as microprocessor performance increases, the demand for high-speed memory grows dramatically. To sustain system performance trends, increasing memory capacity requirements is critical. However, memory capacity is generally a tradeoff with memory performance. Double pumping may be able to satisfy these tradeoff requirements, particularly with a multi-port register file (RF) or content addressable memory (CAM). Double pumping transfers data on both the rising and falling edge of the clock signal. By using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate. In order to apply double pumping, a high-speed time division multiplexing circuit is needed.
USPTO Backgrounds
USPTO Backgrounds