The advent of high-density circuits has spurred the development and implementation of high-layer-count (HLC) printed wiring boards (PWBs) having multilayer substrates. While multilayer substrates typically offer the advantage of more efficient use of space in a circuit board design, multilayer substrates typically require more complex connection capabilities and circuit modularity. These complexities give rise to several problems. For one, relatively large drills often are required to form via holes, or “vias,” for connecting two or more HLC substrates to one another. Further, the alignment of layers and the potential for wander by the drill bit present serious obstacles to correct registration and connections between and among HLC substrates. Substrates with high aspect ratios introduce additional complications, as it generally is difficult to plate a via hole to connect multiple substrates without disturbing adjacent circuit features. Further, the interconnection between substrates typically cannot be easily repaired. As a result, the failure of a single connection may cause an entire multilayer package of substrates to be discarded as incurably defective.
In view of the problems presented in the use of HLC substrates (also known as large-layer-count substrates or LLC substrates) in multilayer packages, improved techniques for HLC lamination have been developed. For example, U.S. Pat. Nos. 5,786,238 and 5,986,339, both issued to Pai, et al., disclose techniques for HLC lamination based on plating copper and solder posts. While eliminating some of the problems discussed above, these techniques have a number of limitations. One such limitation includes the possibility of an electrical disconnect. It will be appreciated that the heights of plated posts on a large board often vary significantly from the edges to the center of the board despite the use of pulse plating processes and “thieving” features to enhance uniformity. Because of this height variation, some posts may fail to electrically connect with the counterpart on the opposing HLC substrate. These conventional techniques are also limited by the expense and time-requirements of the plating process, especially in small-batch production. It also will be appreciated that printed wiring boards (PWBs) with plated solder bumps typically are difficult to handle as solder slivers may separate from the plated bumps and cause problems in subsequent manufacturing operations unless the boards are reflowed to melt and secure the bumps.
Accordingly, an improved HLC laminating process would be advantageous.
USPTO Backgrounds
USPTO Backgrounds