The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to an insulated gate field effect transistor of a thin film type formed on an insulating surface which may be a surface of an insulating substrate such as glass or an insulating film such as silicon oxide formed on a silicon wafer. Specifically, the present invention is applicable to a manufacture of a TFT (thin film transistor) formed on a glass substrate of which glass distortion temperature is 750xc2x0 C. or lower. The present invention further relates to a semiconductor integrated circuit which utilizes TFTs on an insulating surface which are formed through a process at a process temperature 650xc2x0 C. or lower. The semiconductor integrate circuit of the present invention is suitable as an active matrix of a liquid crystal display, a driving circuit of an image sensor, three dimensional integrated circuit, or SOI integrated circuit or a conventional semiconductor integrated circuit such as microprocessor, microcomputer, micro-controller, or semiconductor memory etc. In particular, the present invention is advantageous for a monolithic type active matrix device in which an active matrix circuit and a peripheral driving circuit are formed on a substrate.
Recently, formations of insulated gate field effect semiconductor devices (MOSFET) on insulating substrates have been well studied. The formation of a semiconductor integrated circuit on an insulating substrate is advantageous for improving the operational speed of the circuit because there is no stray capacitor between the insulating substrate and wirings thereon while it exists in the case of a conventional semiconductor integrated circuit which employs a semiconductor substrate. The MOSFET which is formed on an insulating substrate and has an active region in a thin film form is called a thin film transistor (TFT).
Also, there is known a device in which a semiconductor integrated circuit is formed on a transparent substrate, for example, an optical device such as a liquid crystal display or an image sensor. Since these devices needs to be formed on a large area the TFT producing process needs to be done at a lower temperature. Further, since a device having a number of external terminals on a substrate has a difficulty in connecting said external terminals to external circuits, it has been suggested that the circuits corresponding those external circuits are monolithically formed on the same insulating substrate. FIG. 7 shows a block diagram of an example of such a monolithic type integrated circuit. In the figure, a monolithic type active matrix circuit is shown. On one substrate 7, an active matrix circuit 3, peripheral driving circuits 1 and 2 and bus lines 5 and 6 for connecting the active matrix circuit and the peripheral driving circuit. The active matrix circuit 3 includes a number of pixels 4 each of which comprises a TFT 8, pixel electrode 9 connected to an optical modulating medium 10 such as liquid crystal. In this structure, the above mentioned problem reducing the connection is avoided.
However, the electrical characteristics needed for TFTs of the driving circuit is generally different from that needed for TFTs of the active matrix circuit. For example, the active matrix circuit needs to have a sufficiently low leak current (off current) property when a reverse bias voltage is applied to a gate electrode. On the other hand, the peripheral driving circuit is required to have a sufficiently high mobility. If a monolithic active matrix device having more than 1000 scanning lines is to be formed, those TFTs in the peripheral driving circuit must have a mobility higher than 150 cm2/V s and an ON/OFF ratio of a drain current in the active matrix circuit must be 7 digits or more. It was almost impossible to achieve these properties simultaneously in the case of using a non-single crystalline semiconductor for the TFTs.
Crystalline TFTs have been proposed to be used for an active matrix liquid crystal device or an image sensor device. FIGS. 3A-3F are cross sectional views showing an example of a manufacturing method of a TFT in accordance with a prior art.
Referring to FIG. 3A, a base film 302 and an active layer 303 of crystalline silicon are formed on a substrate 301. An insulating film 304 is formed on the active layer using silicon oxide or the like.
Then, a gate electrode 305 is formed of phosphorous doped polysilicon, tantalum, titanium, or aluminum, etc. With this gate electrode used as a mask, an impurity element (e.g. phosphorous or boron) is doped into the active layer 303 by an appropriate method such as ion-doping in a self-aligning manner, thereby, forming impurity regions 306 and 307 containing the impurity at a relatively lower concentration and therefore having a relatively high resistance. These regions 306 and 307 are called a high resistance region (HRD: High Resistivity Drain) by the present inventors hereinafter. The portion of the active layer below the gate electrode which is not doped with the impurity will be a channel region. After that, the doped impurity is activated using laser or a heat source such as a flush lamp. (FIG. 3B)
Referring to FIG. 3C, an insulating film 308 of silicon oxide is formed through a plasma CVD or APCVD (atmospheric pressure CVD), following which an anisotropic etching is performed to leave an insulating material 309 (side spacer) adjacent to the side surfaces of the gate electrode as shown in FIG. 3D.
Referring to FIG. 3E, using the gate electrode 305 and the side spacer 309 as a mask, an impurity is introduced by ion doping or the like in order to form impurity regions 310 and 311 having a higher impurity concentration within the active layer 303. The impurity regions 310 and 311 have a low resistivity and are to become source and drain regions. Accordingly, there are two independent steps of introducing an impurity to the active layer and a step of an anisotropic etching between the two impurity introducing steps.
Then, the doped impurity is activated by means of a laser or a flush lump. Finally, as shown in FIG. 3F, an interlayer insulating film 312 is formed following which contact holes are formed on the source and drain regions through the interlayer insulating film. Further, through the contact holes, electrode/wirings 313 and 314 are formed from a metallic material such as aluminum.
The foregoing process was achieved pursuant to the known LDD technique for a conventional semiconductor integrate circuit and this method has some disadvantages for a thin film process on a glass substrate as discussed below.
Initially, it is necessary to activate the added impurity element with laser or flush lamp two times. Moreover, there exists a step of an anisotropic etching between these steps so that it is necessary to take out a substrate from a vacuum chamber. For this reason, the productivity is lowered. In the case of a conventional semiconductor circuit using a semiconductor substrate, the activation of an impurity can be carried out by a heat annealing at one time after completely finishing the introduction of the impurity (namely, after a step corresponding to FIG. 3F.)
However, in the case of forming TFTs on a glass substrate, the high temperature of the heat annealing tends to damage the glass substrate. Therefore, the use of laser annealing or flush lamp annealing is necessary. However, these annealing is effected on the active layer selectively, that is, the portion of the active layer below the insulating material (side spacer) 309 is not annealed, for example. Accordingly, the annealing step should be carried out at each time after an impurity doping is done.
Also, it is difficult to form the insulating material 309 accurately. Generally, the insulating film 308 is as thick as 0.5 to 2 xcexcm while the base film 302 on the substrate is 1000-3000 xc3x85 thick. Accordingly, there is a danger that the base layer 302 is unintentionally etched and the substrate is exposed when etching the insulating film 308. As a result, a production yield can not be increased because substrates for TFTs contain a lot of elements harmful for silicon semiconductors.
Further, it is difficult to control the thickness of the insulating material 309 accurately. The anisotropic etching is performed by a plasma dry etching such as a reactive ion etching (RIE). However, because of the use of a substrate having an insulating surface as is different from the use of a silicon substrate, the delicate control of the plasma is difficult. Therefore, the formation of the insulating material 309 is difficult.
Since the above HRD should be made as thin as possible, the foregoing difficulty in precisely controlling the formation of the insulating material 309 makes it difficult to mass produce the TFT with a uniform quality.
It is an object of the present invention to provide a TFT having a high resistance region (HRD) through a simplified process instead of the foregoing complicated process. Here, the HRD includes not only a region which contains an impurity at a relatively low concentration and has a relatively high resistivity, but also includes a region which has a relatively high resistivity because of an addition of an element for preventing the activation of the dopant impurity even though the concentration of the dopant impurity is relatively high. Examples of such element are carbon, oxygen and nitrogen. By the provision of the HRD regions adjacent to a channel region, it is possible to suppress the occurrence of hot carriers, and reduce degradation, resulting in an increase of a reliability.
It is a further object of the present invention to manufacture of both high speed type TFTs and low leak current type TFTs on one substrate through a relatively simple manufacturing process.
In accordance with a first aspect of the present invention, a surface of a gate electrode is oxidized and this oxide layer is used to define the high resistivity region. The oxide layer is formed, preferably, by anodic oxidation. The use of the anodic oxidation to form the oxide layer is advantageous as compared with the step employing the anisotropic etching mentioned above because the thickness of the anodic oxide layer can be precisely controlled and can be formed as thin as 1000 xc3x85 or less or as thick as 5000 xc3x85 or more with an excellent uniformity.
Further, it is another feature of the present invention that there are two kinds of anodic oxide in the above mentioned anodic oxide layer. One is called a barrier type anodic oxide and the other is called a porous type anodic oxide. The porous anodic oxide layer can be formed when using an acid electrolyte. A pH of the electrolyte is lower than 2.0, for example, 0.8-1.1 in the case of using an oxalic acid aqueous solution. The resistance of such a film is very low so that the thickness of the film can be easily increased. On the other hand, the barrier type anodic oxide is formed using a weaker acid or approximately neutral electrolyte. Since the metal is not dissolved by the electrolyte, the resultant anodic oxide becomes dense and highly insulating. An appropriate range of pH of the electrolyte for forming the barrier type anodic oxide is higher than 2.0, preferably, higher than 3, more preferably, between 6.8 and 7.1.
While the barrier type anodic oxide can not be etched unless a hydrofluoric acid containing etchant is used, the porous type anodic oxide can be relatively easily etched with a phosphoric acid etchant, which can be used without damaging other materials constructing a TFT, for example, silicon or silicon oxide. Also, both of the barrier type anodic oxide and the porous type anodic oxide are hardly etched by dry etching. In particular, both types of the anodic oxides have a sufficiently high selection ratio of etching with respect to silicon oxide.
By using the anodic oxide film around the gate electrode, it is possible to determine the HRD region in the active layer.
As a material for the gate electrode which can be anodic oxidized, aluminum, tantalum, titanium, or silicon can be used. These materials are combined in a multilayer structure. For example, a titanium silicide may be laminated on an aluminum film, or vice versa.
In accordance with another feature of the present invention, the introduction of an impurity into the active layer is carried out through an insulating film formed on a portion of the active layer and this introduction is carried out twice at different conditions as shown in FIG. 4A or 4B. That is, in a configuration shown in FIG. 1E, phosphorous ions are introduced into the active layer 103 through an insulating film 104xe2x80x2 at a relatively lower acceleration energy. At this time, the impurity can not pass through the insulating film 104xe2x80x2 so that the phosphorous ions are mainly added to the regions 110 and 113. Subsequently, phosphorous ions are introduced at a higher acceleration energy so that the accelerated ions can be introduced into the regions 111 and 112 through the insulating film. Thus, it is possible to form source and drain regions 110 and 113 having a higher impurity concentration and high resistivity regions 111 and 112 having a lower impurity concentration. The order of these steps may be reversed. Also, it is possible to change the condition of introducing impurity ion such as acceleration voltage monotonously or in a stepwise manner.
In accordance with a second aspect of the present invention, crystallinity of a semiconductor film formed on a substrate is selectively improved by means of an intense light such as a pulsed laser, visible light ray or infrared ray in order to form a plurality of TFTs having various electrical characteristics on one substrate.
For example, TFTs comprising crystalline silicon obtained by an intense light have a high speed and a high mobility, however, the off current thereof is relatively larger and are not suitable for an active matrix circuit. On the other hand, TFTs comprising amorphous silicon can not be used for a driving circuit but a leak current thereof is sufficiently low. Therefore, the second aspect of the present invention is characterized by the use of crystalline TFTs for a driving circuit and amorphous TFTs for an active matrix circuit. Further, it is preferable that the crystalline TFTs are provided with a silicide layer or a low resistance layer within the regions corresponding to the source and drain regions in order to reduce the sheet resistance.
Further, by constituting a peripheral driving circuit with TFTs of a top-gate structure, the ion doping of the active layer can be made in a self-aligning manner so that a parasitic capacitance can be reduced, resulting in increase of an operational speed.
In the case of using a pulsed laser, a UV light laser such as an excimer laser of KrF, ArF, XeCl or XeF is suitable. Also, the characteristics of a TFT can be changed by changing the irradiation condition of the laser. Generally, the larger the energy density of the laser is, the larger the mobility of the TFT is.
However, this depends upon the material of the semiconductor and the wavelength of the laser. If the energy density is too high, there is a possibility that the characteristics for the TFT is degraded. The same applies to a shot number of the laser irradiation. In accordance with the present inventors"" knowledge, when a KrF excimer laser (wavelength 248 nm, pulse width 10 nsec) is used, the preferred shot number is 1-50 times and the preferred energy density is 200-350 mJ/cm2.
In this case, if a laser irradiation overlaps, the characteristics of the TFT of this portion tends to be determined by the condition of the first laser irradiation. Generally, the characteristics of a portion on which laser irradiations overlap tends to deteriorate. In the present invention, since only a peripheral circuit is crystallized by a laser irradiation, it is advantageous if the laser beam is shaped in a same form as the shape of the peripheral circuit region. However, in the case that a peripheral circuit portion and an active matrix portion are formed on a same plane and they are located near with each other (as is the case in Example 4 described later), it is necessary to use an appropriate mask because even a small amount of light leak would cause a large influence on the surrounding semiconductor. On the other hand, when the peripheral circuit and the active matrix circuit are formed within different layers, such a care is not necessary.
The foregoing and other features of the invention will be further clarified in preferred embodiments of the invention with reference to the attached drawings.
USPTO Backgrounds
USPTO Backgrounds