Referring to FIG. 1, one type of conventional clock recovery phase locked loop circuit 10 is shown. The circuit 10 generally comprises a phase detector 12, a filter 14, and oscillator 16 and a decoding device 17. This type of phase locked loop is used to synchronize a clock frequency 26 with serial data 33 such that the data can be recovered correctly.
Serial data is presented to an input 24 of the phase detector 12. The phase detector 12 is generally coupled to the oscillator 16 through the filter 14. An output 26 of the oscillator 16 is presented to an input 30 of the phase detector 12 as well as to an input 31 of the decoding device 17. The decoding device 17 also has an input 33 that receives the serial data input. The circuit 10 is generally used to provide a properly timed clock (i.e., a clock at the same rate as the serial data, and with proper phase alignment to insure adequate time margins) to the decoding device 17.
A typical voltage controlled oscillator (VCO) has the capability to operate over a wide frequency range to (i) provide a flexible frequency of operation and (ii) accommodate process and environmental variations. A phase detector (PD) only corrects for a phase error and is insensitive to the frequency of operation of the PLL. This insensitivity is required since serial data consists of variable width pulses and variable width spaces. The transitions, when they occur, are at predictable intervals, but the data stream has no intrinsic operating frequency because of the nature of the serial data stream. It is difficult for a conventional PLL to correct for frequency error when decoding serial data. Edges generally occur at specific intervals of an input clock (i.e., the intrinsic operating frequency), but errors in clock rate can be misinterpreted as data running at another frequency.
One problem associated with the circuit 10 may occur when the VCO 16 operates at a harmonic (e.g., one half, twice, or other multiples) of the data rate of the serial data input. In such a case, the phase detector 12 will not try to correct the error, but will instead provide an out of tolerance clock to the decoder device 17. Another problem occurs when the frequency of oscillation of the signal at the output 26 is out of tolerance by a large amount.
One approach to remedying the problem associated with the VCO 16 operating at a harmonic of the serial data input is to limit the operating range of the VCO, as closely as possible to a small percentage around an expected data rate. In such a system a trimmed oscillator, or tuneable oscillator, may be used to provide such a correction. However, this solution is not desirable since it may introduce other problems, including manufacturing complexity and degrade product performance.
Referring to FIG. 2, another conventional phase locked loop circuit 10' is shown. This type of phase locked loop is generally used to multiply a reference frequency by some multiple set by a feedback divider. The circuit 10' generally substitutes a phase frequency detector 20 for the phase detector 12. The phase frequency detector 20 is generally coupled to the oscillator 16 through the filter 14. A divider circuit 18 has an input 28 that receives the output of the oscillator 16. The divider 18 generally presents a signal to the input 30 of the phase frequency detector 20. The phase frequency detector 20 is capable of indicating both phase error and frequency error. Errors coupled through the filter 14 cause the VCO 16 to change its frequency to minimize the error. VCO frequency errors are easily managed by the circuit 10'. The nominal frequency of operation will be the reference frequency multiplied by a divider ratio. A typical phase frequency detector 20 as used in phase locked loop 10' cannot tolerate irregular input data streams that may be found in a serial data input. As a result, the circuit 10' is not an adequate solution for the VCO frequency error problem.
Referring to FIG. 3, a circuit 40 is shown implementing phase locked loop circuit 10 with a "use local clock" input. The circuit 40 can be used for clock recovery in the same way as the circuit 10, and can correct for frequency errors in the same way as circuit 10'. The circuit 40 generally comprises a PLL 10 (which includes a phase detector (PD) 12, a filter 14, and an oscillator (VCO) 16), a VCO frequency divider 18, a phase frequency detector (PFD) 20 and a switch 22. Serial data is presented to an input 24 of the phase detector 12. The phase detector 12 is coupled to the oscillator 16 through the filter 14. An output 26 of the oscillator 16 is presented to an input 28 of the VCO frequency divider 18 as well as to a feedback received at an input 30 of the phase detector 12.
The VCO frequency divider 18 has an output 30 that presents a signal to an input 32 of the phase frequency detector (PFD) 20. An external reference frequency is presented to an input 34 of the phase frequency detector 20. An output 36 of the phase frequency detector 20 is presented to an input 38 of the switch 22, which also has an input 40 that receives the use local clock signal. The switch 22 presents a signal at an output 42 that is received at an input 44 of the filter 14. The filter 14 is constructed in such a way that when errors are coupled through the frequency error input 44, they will dominate the signal connected to the VCO 16. When the frequency of oscillation of the signal at the output 26 has a very large frequency error when compared with the external reference frequency, logic external to the PLL will assert the use local clock signal received at the input 40. This turns on the switch 22 which causes VCO corrections to be generated by the PFD 20, and to be presented to the input 44 of the filter 14. The use-local clock input 40 may be an internal or an external signal. The phase frequency detector 20 and other control logic can be powered down when not in use.
FIG. 4, illustrates a circuit 50 for triggering the input 44 causing the circuit of FIG. 3 to lock to a local clock. The circuit 50 includes a reference clock divider block (or circuit) 52, an out-of-lock indicator block (or circuit) 54, a terminal count block (or circuit) 56, and a VCO cycle counter 58. The circuit 50 continuously monitors the ratio of the VCO frequency to the reference frequency to switch in (or select) a phase frequency detector (i.e., PFD 20 of FIG. 3) when necessary to correct the VCO frequency during an out-of-range condition. The reference clock divider circuit 52 divides the reference clock frequency by a fixed number (i.e., 256) to produce a low frequency sampling rate. The VCO cycle counter 58 counts the VCO oscillator cycles for a predetermined time (e.g., a sampling period) to measure the exact frequency of oscillation of the signal received from the receive clock divider circuit 52. In one example, the VCO cycle counter 58 may be implemented as a counter 60 and a counter 62, which may present a number related to the ratio of the reference clock divider. During a particular sampling period while the output of the reference clock divider 52 is low, a predetermined number of VCO cycles may occur, indicating the VCO would be operating at the proper frequency. Otherwise, an error signal (e.g., MAX or MIN) is presented at the output 64 or 66 that indicates an over count or under count condition has occurred and the operating frequency is out of tolerance. The signal MAX is received at an input 68 of the terminal count circuit 56 and the signal MIN is received at the input 70 of the terminal count circuit 56. If either the input 68 or the input 70 receives the signal MAX or signal MIN, an out-of-range indication signal is presented at an output 72 to an input 74 of the out-of-lock indicator circuit 54.
The counter 58 is shown implemented as a two part counter. A low speed counter 60 is implemented for the high order bits and a high speed synchronous counter 62 (which is easily decoded) is implemented for the low order bits which may run at the VCO rate. The high order counter 60 provides a carry output to the low order counter 62 to produce a single counter 58. The counters 60 and 62 may be viewed as a single counter or as two counters operating in series.
During operation of the circuit 50, the reference clock divider circuit 52 is high for 128 cycles and low for a 128 cycles to produce a divide by 256 counter. The reference clock divider circuit 52 presents a signal (e.g., REFDIVOUT) that, when high, causes the counter 58 to be held to a preset value (e.g., 1021). When the signal REFDIVOUT is low, the VCO cycle counter 58 begins to count down from the preset value. An ideal value indicating a locked signal may be selected (e.g., 0003). When the counted value reaches at least 0006, and not less than 0000, before the signal REFDIVOUT rises, proper operation of the circuit occurs (i.e., operation within 0.3% of the correct frequency or +/-3/1024). In such a case the terminal count circuit does not present the out-of-range indication signal to the input 74 of the out-of-lock indicator circuit 54. If the counter 58 is not decremented to be at least 0006, or has reached 0000, then the VCO is "out-of-range" and the terminal count circuit 56 will present the out-of-lock indication signal at the input 74 of the out-of-lock indicator circuit 54.
The terminal count is set using the VCO as a clock so that the circuit 50 will be able to record the error in real time. The state of the overall out-of-lock indicator circuit 54 is preserved and can be used, when the circuit 56 (along with the VCO cycle counter) is reset. When the signal REFDIVOUT is high the VCO cycle counter 58 and the terminal count circuit 56 are reset and prepared for the next cycle of frequency comparison.
The out-of-lock indicator 54 is a clocked device that operates on the rising edge of the signal REFDIVOUT. If an error has been recorded, the out-of-lock indicator 54 causes the PLL to lock to the local clock. An arbitrary time later, the out-of-lock indicator 54 is cleared, which may allow the PLL to reacquire an incoming data stream. While the solution in FIG. 4 may provide internal range control for a single PLL system, in multiple PLL chips, a significant power and size burden may result by duplicating the various components of the circuit 50.
USPTO Backgrounds
USPTO Backgrounds