1. Field of the Invention
This invention relates to a test circuit capable of a multi-chip package type semiconductor device (MCP semiconductor device) and an MCP semiconductor device having the test circuit.
2. Description of the Related Art
In the related art, there are several types of multi-chip packages in which more than one IC chip can be packaged. One typical multi-chip package is a stack-type multi-chip package that packages at least two IC chips in a stacked manner as shown in FIG. 7. Another typical multi-chip package is a parallel-type multi-chip package that packages at least two IC chips in the same plane as shown in FIG. 8.
As shown in FIGS. 7 and 8, Each of the MCP semiconductor devices 1, 2 includes a first semiconductor chip (hereinafter “first chip”) C101 and a second semiconductor chip (hereinafter “second chip”) C102. The first chip C101 includes terminal pads P101 for internal connections (hereinafter “internal pads”), and terminal pads P111 for external connection (hereinafter “external pads”). The second chip C102 shown in FIG. 7 includes internal pads P102, and the second chip C102 shown in FIG. 8 includes internal pads P102 and external pad P112. Each of the internal pads P101 is connected to one of the internal pads P102 by a bonding wire BW. Each of the external terminal pads P111 and of the external terminal pads P112 are connected to one of external terminal 121 by a bonding wire BW.
A process of forming the MCP semiconductor device 2 shown in FIG. 8 includes a step for conveying the first chip C101 and second chip C102, and a step for mounting the first and second chips on a printed board. A process of forming the MCP semiconductor device 1 shown in FIG. 7 includes a step for conveying a first chip C101 and the second chip C102, and a step for mounting the second chip C102 on the first chip C101. In these steps, static electricity may be charged on the first and second chips C101, C102. While the static electricity may be charged on the first and second chips C101, C102, if the bonding wires BW are contacted with the internal and external pads P101, P102, P111, P112, surges may occur between the internal and external pads P101, P102, P111, P112 and the bonding wires BW. As a result, a peripheral circuit, which is formed near the pads, may be damaged by the surges. When the damage is critical to the peripheral circuit, it is possible to find an MCP semiconductor device having a damaged chip by a function test. However, when the damage is not so critical to a peripheral circuit, an MCP semiconductor device having a damaged chip may not be found by the function test because the damaged circuit operates normally. Since it is difficult to find an MCP semiconductor device having a damaged chip by a function test, an MCP semiconductor device having a damaged chip is found by measuring a leakage current. According to this measurement, a judgement as to whether an MCP semiconductor device has a damaged chip, can be made.
In an MCP semiconductor device having a single chip, since a terminal pad formed on the chip is connected directly to an external terminal of a lead flame placed outside of the MCP semiconductor device, it is easy to measure a leakage current at the terminal pad by applying a voltage having an H level (ex. power supply voltage) or applying a voltage having an L level (ex. ground voltage) to the external pad. However, in an MCP semiconductor device, at least two chips are formed, and these chips are connected to each other at some of their internal pads P101, P102 by the bonding wires BW, as shown in FIGS. 7 and 8. In other word, these internal pad P101, P102 are used for connecting the first chip C101 to the second chips C101, C102, and are not used for connecting the first and second chips C101, C102 to the external terminals 121. Therefore, it is impossible to measure leakage current on these internal pads P101, P102 by applying the predetermined voltage from the outside because these internal pads P101, P102 are not connected directly to the external terminal on which the predetermined voltage is applied.
Since it is impossible to measure a leakage current on these internal pads P101, P102 by the method described above, the judgement as to whether an MCP semiconductor device having a damaged chip, must rely on the function test. However, as described above, the function test may not be able to find a damaged chip when the damage is not critical. As a result, the MCP semiconductor device having the damaged chip may be manufactured, and then, incorporated in a system. In the worst case, the MCP semiconductor device having the damaged chip malfunctions, and it causes the system to malfunction.
To resolve this problem, it is proposed for an MCP semiconductor device that a consuming current (IDDS) be measured under the condition that an operation of all chips is halted. However, there are some problems with this measurement.
For example, if one of two chips is a programmable memory, it takes a long time to fix the highest bit in an address to “0” or “1”. As a result, a long time is required for measuring the consuming current (IDDS) under the conduction that an operation of all chips is halted.
Further, if one of two chips is a memory, an electric current of a few mA flows in the chip when a chip select terminal is enabled. That is, when MCP semiconductor device includes a chip such as a memory chip or similar kinds, it may be impossible to set the value of the electric current to be caused to flow in the chip to zero (“0”), depending on the voltage level that is applied to each terminal. As a result, it is difficult to obtain accurate measurement results.
Moreover, if one of the two chips is an analog circuit such as an A/D converter, it is difficult to fix the internal pad P101, P102 to the predetermined voltage level.
As described above, it is not easy to test the internal terminal pads and their peripheral circuits formed on each chip, according to the structure of the MCP semiconductor device.
USPTO Backgrounds
USPTO Backgrounds