1. Field of the Invention
This invention relates generally to the field of clock synchronization. More particularly, this invention relates to a method and apparatus for providing clock synchronization in communication systems which are relatively insensitive to absolute timing such as digitized voice systems.
2. Background
In a communication system including a transmitter and a receiver, it is frequently desirable for a transmitter clock to be synchronized to a receiver clock. In some instances, this synchronization may prove inconvenient or costly. For example, consider the system shown in FIG. 1 wherein digitized compressed speech is transmitted from a first location over a communication medium to a second location. In the system shown in FIG. 1, analog speech is applied to the input of an analog to digital (A/D) converter 12 which is clocked by a first clock 14. Clock 14 operates typically at eight (8.0) Khz for sampling speech and produces an 8.0 Khz clock signal referred to herein as CLK1. The digitized samples from analog to digital converter 12 are passed to a compressor 16 which is also clocked by signal CLK1. Compressor 16 operates on the digitized speech signal to reduce its bandwidth by any of a number of known speech compression algorithms. Such speed compression algorithms may include silence detection and deletion and other known bandwidth reduction techniques. The output of compressor 16 is a compressed digital representation of the original analog speech signal which is fed to the data communications equipment (DCE) 18 for transmission over communications medium 20. DCE 18 may be a modem or other communications equipment and provides its own clock signal shown as CLKA back to compressor 16 so that compressor 16 is able to provide the compressed samples in a synchronous manner to DCE 18.
On the receiving end of the data communications medium 20 a similar DCE 22 is provided which receives the transmission from DCE 18 and derives clock signal CLKA from the transmitted data. This clock signal CLKA is delivered to a phase locked loop frequency synthesizer 24 which uses known techniques for synthesizing signal CLK1 from the derived clock signal CLKA. The derived CLKA is used to clock an expander 26 which receives the output of DCE 22 and expands the signal back into a string of digital signals which is then clocked by CLK1 and converted by digital to analog (D/A) converter 28. Digital to analog converter 28 converts the string of digital characters to an analog speech signal which closely resembles the analog speech signal input.
The approach described above, utilizes phase locked loop frequency synthesis to synthesize CLK1 from the derived CLKA from DCE 22. Phase locked loop frequency synthesis, while a relatively mature technology, is not without drawbacks and is somewhat costly in many instances. For example, in many sampled speech systems, it is standard and desirable to have the speech sampling clock operate at 8 Khz. Data communications clock rates are typically a multiple of 2400 hz and at the higher communication rates, which are presently required to support high quality compressed voice, it may be difficult to synthesize 8 Khz from the wide variety of data communication frequencies in common use without requiring a different circuit for each frequency. For example, assume DCE 18 and 22 are high speed modems operating at 14.4 kbps. The clock rate needed for the PCM codec is 1.536 Mhz (the T1 rate) which is a standard PCM clock rate for voice from which 8.0 Khz may be readily derived. However, to derive both 8.0 Khz and 14.4 Khz is somewhat more complex. In one approach, the T1 clock must be multiplied by 3 to obtain a multiple of 14.4 Khz. The multiple of 14.4 Khz is 320, so to derive 14.4 Khz from the T1 rate requires that the T1 clock be multiplied by 3 and divided by 320. While this is certainly possible to do, it requires that either a rather elaborate phase locked loop be used or that a different phase locked loop circuit be used for each data rate. Therefore, a different set of hardware is needed for 19.2 Kbps than for the 14.4 Kbps system described above. Thus, the economy of scale is not fully realized by using conventional phase-locked loop technology.
In addition to the expense required for providing this frequency synthesis, as well as the additional circuit complexity required, the generation of such high frequencies makes electromagnetic emissions more difficult to control and subjects the receiver to the problems associated with lock time, jitter and noise associated with the use of phase-locked loops. The present invention addresses the problem of synchronization of two clocks in certain environments such as digital voice in a manner which avoids such problems and which is easily implemented at very low cost. The circuit operates over a wide range of frequencies without hardware modification by simply supplying a new set of constants to be stored in memory.
USPTO Backgrounds
USPTO Backgrounds