The present invention relates generally to a semiconductor device and method of making the semiconductor device and, more particularly, to a semiconductor device which includes first and second vertical field effect transistors (VFETs) connected in parallel and third and fourth VFETs connected in series.
Related art devices such as NAND and NOR devices are formed using complementary metal oxide semiconductor (CMOS) technology. These CMOS devices may be formed, for example, by using a traditional (e.g., horizontal) transistor configuration.
For example, in forming a CMOS NAND device, an n-well is formed in a p-type substrate, and a pair of p-type field effect transistors (pFETs) is formed in the n-well, and connected in parallel. A pair of n-type FETs (nFETs) is then formed on the substrate adjacent to the pair of nFETs, and connected in series.
Thus, the related art CMOS NAND device has a physical layout that covers a large area of the substrate.
USPTO Backgrounds
USPTO Backgrounds