A severe limitation for large scale integration is the lack of adequate registration from layer to layer during the fabrication process. These mis-registrations result in the introduction of guards/protections which enlarge the real estate area needed for a particular circuit layout.
In addition to registration problems, there is difficulty in preserving dimensional control when etching contacts or vias.
Another problem is caused by the steep walls generated during the making of conventional contacts/vias. Etching steps result in discontinuities of metal lines. Furthermore, metal has the propensity for spiking through shallow junctions forming sources and drains. As dimensions reach the submicron sizes, the problems mentioned above exacerbate exponentially.
USPTO Backgrounds
USPTO Backgrounds