1. Field of the Invention
The present invention relates to a symmetric integrated amplifier with controlled DC offset voltage and, more particularly, to such an amplifier which is insensitive to variations in either the power supply voltages or transistor threshold voltage.
2. Description of the Prior Art
Optical communication systems currently under development are beginning to utilize opto-electronic integrated circuits (OEICs)as fully integrated lightwave transmitters, repeaters, receivers, etc. A clear advantage of such OEICs is their small size relative to the bulk devices in use today. A problem being currently addressed in the art is providing a substrate material, and corresponding fabrication techniques, which is compatible with both the optical and electronic components. Most electronic integrated circuits is use today are formed on a silicon substrate, where silicon is not a preferred substrate material for lightwave devices, including lasers, LEDs, or photodiodes. In contrast, the GaAs substrate material utilized in lightwave fabrication is suitable only for short wavelength (0.8-0.9 .mu.m) communications, whereas long haul and/or high bit rate systems require wavelengths beyond the range of GaAs (.apprxeq.1.3-1.5 .mu.m). A reasonable compromise has emerged where OEICs are formed on indium phosphide (InP) substrates, with lattice-matched GaInAsP material grown on the InP substrate for lightwave device formation. For a large variety of OEICs, some sort of electronic amplifier is required. Unlike silicon and GaAs, however, InP does not have a well-established field effect transistor (FET) technology. Due to gate-semiconductor interfacial problems, the metal-insulator-semiconductor (MIS) and metal-semiconductor (MES) FETs do not appear to be practical InP.
One recent attempt to fabricate an integrated photoreceiver on an InP substrate is discussed in the article "InGaAs Monolithic Photoreceiver Integrated PIN/JFET With Diffused Junctions and a Resistor" by J. C. Renaud appearing as paper WF3 in the Optical Fiber Communication Technical Digest, 1988. In particular, Renaud describes the formation of a PIN/JFET structure based on a three-layer InGaAs structure grown on a semi-insulating InP substrate. A problem remains with the JFET structure of this particular arrangement in that the DC offset voltage of the JFET may vary as a function of changes in the power supply. Further, similar JFETs included in separate photoreceivers may exhibit vastly different threshold voltages, due to the relatively complex InP-based JFET fabrication process. The latter problem creates a significant impediment to the formation of multi-stage amplifiers, since the output voltages from the cascaded stages will be unknown and thus uncontrollable.
Therefore, a need remains in the prior art for a transistor amplifier structure which is compatible with the advances in OEICs and may be configured in a cascaded form without suffering the problems described above.
USPTO Backgrounds
USPTO Backgrounds