Conventional complementary-metal-oxide-semiconductor (CMOS) logic gates, such as NAND-gates, NOR-gates, and inverters, are typically used in applications where the speed of the signal transmission through a particular gate is not necessarily critical.
For speed critical paths, an alternate approach to conventional CMOS logic gates can be transmission gate logic circuits. A typical conventional transmission gate logic circuit includes an NMOS (i.e., n-channel) transistor and a PMOS (i.e., p-channel) transistor configured with source/drain regions connected together to form a CMOS transmission gate (i.e., passgate). The propagation of a “primary” signal through the passgate can be controlled according to other logic signals, thus establishing a desired response.
Transmission gate logic circuits can offer a distinct speed advantage over corresponding conventional CMOS logic gates. Transmission gate logic circuits can be used to implement basic logical functions, but with a critical signal path optimized for signal propagation. This can be realized by reducing the levels or number of stages of logic gates required to achieve the same logic function with similar or better circuit input/output capabilities.
A CMOS transmission gate equivalent can also eliminate buffering in some applications by isolating an input from a large driving inverter using a passgate gate. This capability makes the transmission gate logic approach suitable for certain decoding signals, such as address decode signals in a memory device. In such applications, lower input capacitance seen at each local decoder circuit can reduces the overall capacitance of the select line, and hence the overall delay of the decode logic is reduced.
Despite the speed advantages of transmission gate logic implementations, there are limitations with such conventional approaches. To better understand features of the various embodiments of the present invention, conventional transmission logic gate arrangements will first be described.
FIG. 7A shows a schematic diagram of a conventional transmission gate NAND logic circuit. FIG. 7B is a timing diagram showing the operation of the circuit set forth in FIG. 7A. The conventional circuit of FIG. 7A is designated by the general reference character 700 and includes a passgate gate 702, NAND logic gate 704, an inverter 706, a setting device 708, and a buffer inverter 710.
Logic gate 704 can receive input signals A and B. When input signals A and B transition high, logic gate 704 provides a low output, which enables passgate gate 702. That is, the output of logic gate 704 can enable the p-channel portion of passgate 702, while the output of inverter 706 can enable an n-channel portion of passgate 702. In this way, when signals A and B are both high, a “primary” input signal C can propagate through transmission gate 702 to node XB. When signal A or B or both A and B are low, passgate 702 is turned off, and node XB is set to default low value by operation of setting device 708.
A logic value at node XB can be inverted (e.g., buffered) by buffer inverter 710 to provide output signal X.
A drawback to the conventional arrangement of FIG. 7A can be that a resulting slew rate of a signal at node XB is tied to that of primary input signal C. Consequently, assuming the signals A and B are both high prior to a change in the signal at node C, if a slew rate for signal C is undesirably slow, a resulting response at node XB will likewise be even slower.
Another drawback to the conventional arrangement set forth in FIG. 7A can be the effectiveness of the n-channel device within passgate 702. In particular, as operating voltages are lowered, the impedance presented by such an n-channel device is limited by its threshold voltage (Vtn). That is, when an input signal at node C transitions from low to high, once the potential at node XB is greater than VPWR-Vtn, signal transmission is provided solely by the p-channel device of transmission gate 702, as the n-channel device will be turned off due to its gate-source voltage that becomes equal or smaller than the threshold voltage. Such an effect is illustrated by FIG. 7B.
FIG. 7B is a timing diagram showing input signals A, B, and C, as well as node XB and output X.
An equivalent logic circuit representation for the conventional circuit of FIG. 7A is shown in FIG. 7C. Also, a truth table result for the circuit of FIG. 7A is shown in FIG. 7D.
A second conventional example of a transmission gate logic circuit is shown in FIGS. 8A to 8C, and sets forth an example of a NOR gate. FIG. 8A is a schematic diagram and shows the same general components as FIG. 7A, with like sections being identified by the same reference character but with a first digit being a “8” instead of a “7”. As shown in FIG. 8A, unlike FIG. 7A, in circuit 800 logic gate 804 is a NOR gate, and transistor 808 is a pull up transistor.
FIG. 8B shows an equivalent logic circuit representation for the conventional circuit of FIG. 8A. FIG. 8C shows a truth table result for the circuit of FIG. 8A which shows the NOR logic function.
As noted briefly above, one application for high speed logic circuits can be in decoder circuits for memory devices and the like. More particularly, very high speed memory devices, such as quad data rate (QDR) random access memories (RAMs), can benefit from faster decoding operations, as such results can allow for faster selection of a memory array portion (e.g., quadrant, section, block, row group, row, column group, column), and hence faster reading and/or writing of data values.
In light of the above, it would be desirable to arrive at some way of providing high speed transmission gate logic that does not suffer from the drawbacks of conventional approaches, like that shown in FIGS. 7A to 8C.
USPTO Backgrounds
USPTO Backgrounds