In recent years, there has been proposed a ferroelectric memory device having a memory cell provided with a capacitor in which a capacitive film made of a ferroelectric material is disposed, resulting in a non-volatile memory device. As shown in FIG. 19, the ferroelectric material is such a material that, as an electric field applied thereto is increased gradually from 0, the amount of polarization caused therein also increases to reach a maximum value at point A but, as the electric field is reduced in reverse, the amount of polarization decreases slowly without retracing the previous transition process and does not reach 0 even when the electric field is reduced to 0, which causes a residual polarization indicated at point B. If a negative electric field is applied to the ferroelectric material and reduced gradually to 0, a residual polarization indicated at the point D is observed. One characteristic of the ferroelectric material is a so-called hysteresis curve or loop which causes a residual polarization responsive to the intensity and polarity of the electric field applied previously to the ferroelectric material.
By internally providing a memory cell with a ferroelectric capacitor composed of a ferroelectric film sandwiched between two conductor films and using, as stored data, the residual polarization of the ferroelectric film responsive to the polarity and magnitude of a signal voltage, the stored data can be preserved without being volatilized so that a so-called non-volatile memory device is implemented.
For example, U.S. Pat. No. 4,873,664 discloses the following two types of ferroelectric memory devices.
In the non-volatile memory device of the first type, each memory cell for storing 1 bit is composed of one transistor and one ferroelectric capacitor (1T1C). In this case, one dummy memory cell (reference cell) is provided for every 256 main memory cells (normal cells).
In the non-volatile memory device of the second type, each memory cell for storing 1 bit is composed of two transistors and two ferroelectric capacitors (2T2C) without using a dummy memory cell.
There is also a non-volatile memory device in which each memory cell for storing 1 bit is composed of two transistors and one ferroelectric capacitor (2T1C), as disclosed for example in U.S. Pat. No. 4,888,733.
Known examples of the ferroelectric material used in the ferroelectric capacitor include KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3. There is also disclosed a ferroelectric material with extremely reduced fatigue compared with PbTiO.sub.3 --PbZrO.sub.3 in PCT International Publication WO 93/12542.
A description will be given to the operation of a conventional 2T2C ferroelectric memory device with reference to FIGS. 17 and 18.
FIG. 17 is an electric circuit diagram showing the structure of the conventional 2T2C ferroelectric memory device, in which a reference numeral 1 denotes a memory cell; 2 denotes a bit-line voltage control circuit; 3 denotes a sense amp circuit; BL, /BL denote bit lines; SN, /SN denote data accumulation nodes; WL denotes a word line; CP denotes a cell plate line; BP2 denotes a bit-line voltage control signal line; and SAE denotes a sense-amp control signal line.
In the memory cell circuit 1, memory cell transistors 11, 12 have respective drains connected to the bit lines BL, /BL, respective sources connected to the data accumulation nodes SN, /SN, and respective gates connected to the word line W1. Memory cell capacitors 13, 14 each having a ferroelectric film are interposed between the respective data accumulation nodes SN, /SN and the cell plate line CP.
In the bit-line voltage control circuit 2, respective NMOS transistors 21 and 22 for voltage control are interposed between the bit lines BL, /BL and the ground. The bit-line voltage control signal line BP2 is connected to each of the gates of the NMOS transistors 21 and 22.
In the sense amp circuit 3, first and second inverters 31, 32 are connected in series to the sense amp signal line SAE. The first inverter 31 has an output connected to the gate of a PMOS transistor 34 for applying a drive pulse. Two PMOS transistors 35 and 36 constituting a differential sense amplifier are disposed between the bit lines BL, /BL. The PMOS transistor 34 has a source connected to the common drain of the PMOS transistors 35, 36, while having a drain connected to a power-source voltage supply terminal. The second inverter 32 has an output connected to the gate of an NMOS transistor 39 for applying a drive pulse. Two NMOS transistors 37, 38 constituting another differential sense amplifier are disposed between the bit lines BL, /BL. The NMOS transistor 39 has a drain connected to the common source of the NMOS transistors 37, 38, while having a source connected to the ground. Briefly, the MOS transistors 34 and 39 are operated in response to a control signal from the sense amp signal line SAE to apply an activation pulse to the two differential sense amplifiers which amplify a voltage difference (data) between the bit lines BL, /BL.
FIG. 18 is a timing chart illustrating a write operation performed in the aforesaid 2T2C ferroelectric memory device.
First, when a logic signal L is supplied to the bit-line voltage control signal line BP2 at a time t201, the NMOS transistors 21, 22 are turned OFF in the bit-line voltage control circuit 2 to stop the precharging of the bit lines BL, /BL to the ground voltage VSS. On the other hand, data to be written from the outside is transferred to the bit lines BL, /BL and a logic signal H is supplied to the sense-amp control signal line SAE to operate the sense amp circuit 3, so that the data on the bit lines BL, /BL is latched thereby. By way of example, data on the bit lines BL, /BL is defined to be "1" when a voltage on the bit line BL is H and a voltage on the bit line /BL is L, while it is defined to be "0" when the voltage on the bit line BL is L and the voltage on the bit line /BL is H. When data "1" is transferred, therefore, the voltage on the bit line BL becomes equal to the power-source voltage VDD by turning ON the PMOS transistor 35 and turning OFF the PMOS transistor 36. By contrast, the voltage on the bit line /BL becomes the ground voltage VSS by turning ON the NMOS transistor 38 and turning OFF the NMOS transistor 37. When data "0" is transferred to the bit lines BL, /BL, on the other hand, the voltage on the bit line BL becomes equal to the ground voltage VSS, while the voltage on the bit line /BL becomes equal to the power-source voltage VDD.
Next, when the logic signal H is supplied to the word line WL at a time t202, the memory cell transistors 11, 12 are turned ON so that respective voltages at the data accumulation nodes SN, /SN become equal to respective voltages on the bit lines BL, /BL. When the logic signal H is supplied simultaneously to the cell plate line CP, the L data is written in one of the memory cell capacitors 13, 14 each having the ferroelectric film (e.g., the state indicated at point C in FIG. 19).
Next, when the logic signal L is supplied to the cell plate line CP with the logic signal H supplied to the word line WL at a time t203, H data is written in the other of the memory cell capacitors 13, 14 (the state indicated at point A in FIG. 19). As a result, the L data has a residual polarization indicated at point D in FIG. 19.
At that time, for example, the data "1" is stored in the memory cell with the H data written in the memory cell capacitor 13 and with the L data written in the memory cell capacitor 14, while the data "0" is stored in the memory cell with the L data written in the memory cell capacitor 13 and with the H data written in the memory cell capacitor 14. In other words, complementary data is stored.
Next, when the logic signal L is supplied to the sense-amp control signal line SAE at a time t204, the operation of the sense amp circuit 3 is stopped so that the voltage difference between the bit lines BL, /BL becomes approximately zero. When the logic signal H is supplied to the bit-line voltage control signal line BP2, the respective voltages on the bit lines BL, /BL become equal to the ground voltage VSS, while the respective voltages at the data accumulation nodes SN, /SN also become equal to the ground voltage VSS. In this state, no charge remains in the two conductor films of the memory cell capacitor with the ferroelectric film sandwiched therebetween, since the voltage on the cell plate line CP is also the ground voltage VSS. At that time, the L data has a residual polarization indicated at point D in FIG. 19, while the H data has the residual polarization indicated at point B in FIG. 19.
Next, when the logic signal L is supplied to the word line WL at a time t205, the memory cell transistors 11, 12 are turned OFF, whereby the write operation is completed.
In the foregoing write operation, the period between the times t202 and t203 is the period for the writing of L data in the memory cell capacitor and the period between the times t203 and t204 is the period for the writing of H data in the memory cell capacitor.
USPTO Backgrounds
USPTO Backgrounds