The invention relates to a charge transfer device comprising a semiconductor layer and a charge transfer channel belonging to the semiconductor layer and having first and second longitudinal sides and an electrode system comprising electrodes which are separated by a barrier layer from the charge transfer channel and which extend transversely across the charge transfer channel from one longitudinal side to the other, at least one of these electrodes being a first electrode which is associated with a first storage site present in the charge transfer channel, while there is present outside the charge transfer channel a second storage site which belongs to the semiconductor layer and has an associated second electrode separated by a barrier layer from this second storage site. The first and second storage sites each have a substantially rectangular periphery with a length and a width, which periphery is defined at least inter alia by the relevant associated first or second electode, the semiconductor layer comprising a connection channel which extends from the first to the second storage site and can be controlled by a transfer electrode which is separated by a barrier layer from the connection channel, said connection channel joining the first storage site on the first longitudinal side of the charge transfer channel, and the transfer electrode being strip-shaped and being arranged substantially parallel to the first longitudinal side beside the charge transfer channel charge carriers can be transferred through the connection channel between the first and the second storage sites from one storage site to the other, the connection channel having at an end adjoining the one storage site a width which is smaller than the length and smaller than the width of this one storage site, and the transfer electrode being separated from the first or second electrode associated with the one storage site.
Such a charge transfer device is known from U.S. Pat. No. 4,376,897. This known device is a series/parallel/series storage device composed of CCD shift registers. The input register is coupled to several parallel registers. Each parallel register is connected through a connection channel to a first storage site of the series register present beneath a first electrode, the connection channels being narrower than the width of the charge transfer channel of the series register. The series register is a 2-phase register, in which the first electrodes are located at a first level above the semiconductor body, while the intervals between these first electrodes are each bridged by a further electrode system. The further electrodes are located at a second level which is separated from the first level by an insulating layer. Each first electrode is connected to the adjacent further electrode and the electrode pairs thus formed are alternately connected to the different clock voltages. The first and the further electrodes extend transversely across the charge transfer channel of the series register, the first electrodes being longer than the further electrodes. These longer first electrodes extend not only across the said charge transfer channel, but also above the adjoining part of the respective connection channels and as far as underneath the edge of the strip-shaped transfer electrode. Other known charge transfer devices are shown in Japanese Kokai No. 54-150983 and Netherlands Pat. No. 7904406.
The present invention is based inter alia on the recognition of the fact that in the known structure described problems can readily arise during the transfer of information representing charge packets from the first to the second storage sites, so from the series register to the parallel registers, which problems become more serious as the connection channels are made narrower. Due to the proximity of the lateral boundary of the connection channels, at the entrance of these channels the potential well to be formed underneath the first electrode will be less deep than in the central part of the first storage site which is arranged centrally in the wider charge transfer channel of the series register. This effect becomes manifest during the transfer of charge carriers as a threshold, as a result of which charge carriers of the charge packet to be transferred can remain in the first storage site.
USPTO Backgrounds
USPTO Backgrounds