This invention pertains to apparatus and processes for conducting chemical depositions, and may find particular use in depositing a conformal film of dielectric material with a high degree of surface smoothness particularly suited to high aspect ratio gap fill applications in semiconductor device fabrication.
Conformal, uniform dielectric films have many applications in semiconductor manufacturing. In the fabrication of sub-micron integrated circuits (ICs) several layers of dielectric film are deposited. Four such layers are shallow trench isolation (STI), premetal dielectric (PMD), inter-metal dielectric (IMD) and interlayer dielectric (ILD). Other applications of conformal dielectric films may be as sacrificial or permanent spacer layers, sacrificial or permanent storage node separation layers, or as dielectric liners for through-wafer vias. All of these layers require silicon dioxide or other low dielectric constant films that fill features of various sizes and have uniform film thicknesses across the wafer.
In particular, it is often necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. As device dimensions shrink and thermal budgets are reduced, void-free filling of high aspect ratio (AR) spaces (AR>3.0:1) becomes increasingly difficult due to limitations of existing deposition processes. The deposition of doped or undoped silicon dioxide assisted by high density plasma CVD, a directional (bottom-up) CVD process, is the method currently preferred for high aspect ratio (AR) gap-fill in semiconductor fabrication production processes. Evolving semiconductor device designs and dramatically reduced feature sizes have resulted in several applications where HDP processes are challenged in filling the high aspect ratio structures (AR>7:1) using existing technology (see, for example, U.S. Pat. No. 6,030,881). For structures representative of the 65 nm and 45 nm technology nodes and beyond, engineering the gap-fill process becomes structure dependent, hence the process requires re-optimization, a task of considerable complexity, every time a new structure needs to be filled.
An alternative to CVD is atomic layer deposition (ALD). ALD methods involve self-limiting adsorption of reactant gases and can provide thin, conformal dielectric films within high aspect ratio features. The ALD process involves exposing a substrate to alternating doses of, usually two, reactant gases. As an example, if reactants A and B are first and second reactant gases for an ALD process, after A is adsorbed onto the substrate surface to form a saturated layer, B is introduced and reacts only with adsorbed A. In this manner, a very thin and conformal film can be deposited. One drawback, however, to ALD is that the deposition rates are very low. Films produced by ALD are also very thin (i.e., about one monolayer); therefore, numerous ALD cycles must be repeated to adequately fill a gap feature. These processes are unacceptably slow in some applications in the manufacturing environment.
Another more recently developed technique useful in gap fill and other dielectric deposition applications in semiconductor processing is referred to as pulsed deposition layer (PDL) processing, sometimes also referred to as rapid surface-catalyzed vapor deposition (RVD). PDL is similar to ALD in that reactant gases are introduced alternately over the substrate surface, but in PDL the first reactant A acts as a catalyst, promoting the conversion of the second reactant B to a film. In ALD the reaction between A and B is approximately stoichiometric, meaning that a monolayer of A can only react with a similar amount of B before the film-forming reaction is complete. The catalytic nature of A in PDL allows a larger amount of B to be added, resulting in a thicker film. Thus, PDL methods allow for rapid film growth similar to using CVD methods but with the film conformality of ALD methods.
PDL-type processes for forming silicon-based dielectrics can use as reactant A a metal or metalloid catalyst (e.g., trimethylaluminum (TMA)) or metal and metalloid-free catalysts (e.g., an organic acid such as acetic acid (CH3COOH) or an inorganic acid such as phosphoric acid (H3PO4); and as reactant B, a silicon-containing dielectric precursor. As an example of the use of PDL to deposit silicon dioxide on silicon, the first (catalytic) reagent can be trimethylaluminum (TMA) and the second (silicon-containing) reagent can be tris t(pentoxy)silanol (TPOSL). A heated silicon substrate is first exposed to a dose of TMA, which is thought to react with the silicon surface to form a thin layer of surface-bound aluminum complex. Excess TMA is pumped or flushed from the deposition chamber. A large dose of TPOSL is then introduced. The aluminum complex catalyzes the conversion of the silanol to silicon oxide until the silanol is consumed, or the growing film covers or otherwise inactivates the catalytic complex. When excess silanol is used, the film growth is usually self-limiting and a thick and uniform film results. Unreacted silanol is then removed from the chamber and the growth cycle repeated.
The most significant difference between CVD and PDL or ALD is that in the latter case the catalyst and silicon-containing precursors are not present in the reactor at the same time. Instead, they are introduced sequentially, generally with a purging step in between to minimize gas-phase reactions and to improve step coverage and uniformity of the film.
In CVD, ALD, or PDL systems, a film is often deposited on the chamber walls in addition to the desired location, on the substrate (e.g., silicon wafer) surface. In ALD and PDL reactors, this unwanted deposition can occur as the precursors adsorb to the walls of the reactor in addition to the wafer surface and subsequently react to form film in later PDL/ALD steps. This film can build up on the chamber walls and can act as a source of chemical contaminants and particulates. It has been well documented for many CVD and ALD/PDL systems that a periodic cleaning of the chamber walls to remove these deposits is beneficial. If these chamber cleans are not performed, the film stresses may be so large that the film delaminates from the chamber wall, leading to particle deposition on the wafer surface. However, these chamber cleans reduce chamber productivity.
It is therefore desirable to develop a method and apparatus for minimizing unwanted film growth on reaction chamber walls, thus minimizing or eliminating altogether the need to perform chamber cleans in order to keep the particle performance of the chamber within acceptable limits and thereby improving the availability of the tool for processing wafers.
USPTO Backgrounds
USPTO Backgrounds