The present invention generally relates to a header for a wafer scale assembly and, in particular, relates to such a header having a plurality of pins disposed such that the end portions thereof to be connected to the wafer scale assembly lie in a plane substantially parallel to a plane of the wafer scale assembly.
In general, a wafer scale assembly is an electronic device that includes a substrate, usually silicon, having a plurality of active semiconductor chips affixed to one surface thereof. The substrate usually includes conductive paths for interconnecting the active semiconductor chips affixed thereto. This type of assembly allows many active chips to be interconnected into a single operative device in a reliable fashion. Such an assembly is considerably more reliable than a functionally identical element wherein the devices are formed in a semiconductor substrate by semiconductor integrated circuit fabrication techniques. One reason for the increased reliability is that the individual chips can be tested prior to affixing them to the substrate to ensure that each is operable.
Such wafer scale assembly devices have numerous advantages in addition to the reliablity thereof. For example, wafer scale assemblies generally have an excellent thermal matching between the substrate chips affixed thereto and consequently, thermally related expansions and contractions are less destructive. Further, the wafer scale assemblies offer high chip density arrangements similar to that of wafer sized integrated devices. In addition, wafer scale assemblies including both the substrate and the individual chips can each be made by conventional integrated circuit fabrication processes thereby providing a relatively low cost per function as well as the ability to mix different integrated circuit technologies on the same substrate, such as, for example, MOS and BIPOLAR device chips can be mounted on the same silicon substrate.
However, conventional wafer scale assemblies do have a drawback, to wit, as part of the packaging procedure, the silicon substrate of the wafer scale assembly is bonded to a ceramic substrate and the connections from the silicon substrate are wire-bonded to bonding pads along the periphery of the ceramic substrate. The ceramic substrate includes a plurality of pins that extend through the ceramic material to contact the bonding pads. These pins then extend substantially perpendicular to the major surface of the ceramic substrate opposite the bonding surface of the silicon substrate. The overall ceramic substrate is then hermetically sealed either by use of a cover or by a non-conductive sealant epoxy. Such a pin arrangement weakens the ceramic substrate and increases the potential for fracture thereof. Any fracture of the ceramic substrate renders the entire wafer assembly useless as an entity and consequently, that entire package must be replaced.
Consequently, a header for use with a wafer scale assembly that avoids through-holes in a brittle material is quite desireable to avoid the potential fracturing of the wafer scale assembly.
USPTO Backgrounds
USPTO Backgrounds