1. Field of the Invention
The present invention relates to a technique for estimating the quality of a photomask used for manufacturing a semiconductor device, and more specifically to a photomask quality estimation system and method, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
In accordance with the progress of microfabrication of semiconductor devices, there is a demand for further enhancement in the accuracy of lithography. To meet the demand, much stricter dimensional accuracy is now being required for the photomasks used for lithography. For instance, there is a demand for reducing the tolerance in mask planar dimensions to 10 nm or less, and more desirably, to 5 nm or less. Photomasks are manufactured by forming a resist pattern on a mask blank, and etching the shade film of the mask blank into a plurality of chip patterns. When, for example, a halftone phase-shift mask as a kind of photomask is produced, estimations concerning a number of check items, such as dimensional variation, phase difference, transmittance, and existence/non-existence of a defect, are performed to estimate the quality of the mask.
However, in the prior art, since all mask patterns included in the chip patterns of a photomask are regarded as a population for quality estimation, even if only some of the chip patterns are non-compliant and the other chip patterns are compliant, the photomask is considered defective. This makes the yield of photomasks extremely low, regardless of the progress in the accuracy of the photomask manufacturing technique (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-72440).
USPTO Backgrounds
USPTO Backgrounds