1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device.
2. Description of the Related Art
In a semiconductor integrated circuit, some locations (such as input/output terminals) are not provided with protective film for protecting circuits from the discharge of static electricity, the metal wiring layer being exposed in these locations.
Static electrical discharge can easily occur during the assembly process of a semiconductor integrated circuit. After completion of assembly, the reduced number of input/output terminals in which the metal wiring layer is exposed and the increased electrostatic capacitance of the semiconductor substrate decrease the necessity for protecting input/output terminals.
Semiconductor integrated circuits that include electrostatic discharge protection circuits (hereinbelow abbreviated as “ESD protection circuits”) are known as one method of protecting locations in which the metal wiring layer of the semiconductor integrated circuits is exposed.
Connection between an ESD protection circuit and a main circuit causes delays in the operation of the main circuit, and ESD protection circuits are therefore cut off from main circuits after assembly has been completed.
Document 1 (JP-A-2001-244338) and Document 2 (JP-A-2003-518745) disclose protection function release methods for cutting fuses that connect main circuits with ESD protection circuits after completion of assembly.
In memory devices such as DRAM (Dynamic Random Access Memory), memory cells included in the memory device are connected to main circuits by way of fuses. When a memory cell has been damaged, the fuse that connects the damaged memory cell to the main circuits is cut, following which a normal memory cell is connected to the main circuits.
In order to cut the connection between a damaged memory cell and the main circuits, the fuse is irradiated by a laser. The cut surface of a fuse that has been cut by means of laser irradiation is left exposed without being covered by a protective film, and as a result, the cut surface of the fuse is prone to the occurrence of electrostatic discharge.
For example, in the step of mounting a semiconductor package in a ball grid array (BGA) packaging method, there is a potential for the occurrence of electrostatic discharge at the cut surfaces of fuses that are under the suction portion when a semiconductor chip is adhered to a vacuum collet.
In addition, in the step of assembling a multi-chip semiconductor device, there is a potential for the occurrence of electrostatic discharge in the cut surfaces of fuses provided on lower-layer chips that are formed immediately below an upper layer chip.
FIG. 1 is a circuit diagram showing a circuit in which a fuse and a MOS field-effect transistor are connected. In FIG. 1, this circuit includes MOSFET 501 and fuse 502.
When an electric charge resulting from electrostatic discharge is applied to the cut surface of fuse 502, the applied charge is discharged in MOSFET 501.
When the electric charge is discharged in MOSFET 501, the potential exists for damage to the MOSFET 501.
FIG. 2 is a sectional view of the circuit shown in FIG. 1.
In FIG. 2, semiconductor substrate 601 includes N+ diffusion layers 606 and 607 and gate 608. In addition, N+ diffusion layer 606 N+ diffusion layer 607 and gate 608 form MOSFET 602.
When an electric charge is applied to the cut surface of fuse 604 by an electrostatic discharge, the applied electric charge is discharged in N+ diffusion layer 607 by way of first metal wiring layer 603 and second metal wiring layer 605. The electric charge that is discharged in N+ diffusion layer 607 can potentially damage MOSFET 602.
Documents 1 and 2 disclose no methods of protecting circuits from electrostatic discharge that occurs in the cut surfaces of fuses.
USPTO Backgrounds
USPTO Backgrounds