High-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical devices, such as input/output (I/O) circuits, CPU power supplies, power management systems, analog/digital converters, etc. There are a variety of types of HVMOS devices. Lateral diffused MOS (LDMOS) devices are among the most commonly used HVMOS devices. LDMOS devices typically include laterally diffused drain regions, which enclose drain regions. Laterally diffused drain regions typically have lower doping concentrations than the drain regions, thus have high breakdown electrical fields.
FIG. 1 illustrates a conventional LDPMOS device 2, which includes gate oxide 10, gate electrode 12 on gate oxide 10, drain region 6 in low-voltage p-well (LVPW) region 4, and source region 8 in low-voltage n-well (LVNW) region 7. Shallow trench isolation (STI) region 14 spaces drain region 6 and gate electrode 12 apart so that a high drain-to-gate voltage can be applied. LDPMOS device 2 may be encircled by an isolation ring, which includes an LVNW regions 7, 16 and the corresponding pick-up regions 18. Deep n-well (DNW) region 20 is typically formed underlying LVPW region 4 and LVNW regions 7 and 16 for isolation purposes.
Typically, the isolation ring is applied with a voltage of zero volts. Therefore, when a high voltage is applied on drain region 6, the same high voltage is applied between drain region 6 and LVNW region 16. In region 22, which is an interface region between LVPW region 4, LVNW region 16 and DNW region 20, a high electrical field is generated. The formation of the high electrical field causes the reduction in breakdown voltage of LDPMOS 2. Typically, LDPMOS devices, as shown in FIG. 1, can be operated under high voltages of up to about 12 volts without being broken down. However, LDPMOS devices are often required to be operated under voltages of 16 volts or higher. Therefore, the structure of LDPMOS devices needs to be improved.
USPTO Backgrounds
USPTO Backgrounds