1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly to methods, structures and masks associated with programming an identification code into an integrated circuit.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuit manufacturers often find it useful to include an identification code, or xe2x80x9cdevice ID,xe2x80x9d within a manufactured integrated circuit. The code is generally contained within a set of memory cells, such as a register, which is externally readable, often during test of the integrated circuit (IC). The circuit identification code may provide information on, for example, the manufacturer, the particular circuit design, and/or the process used to fabricate the circuit. Identifying an integrated circuit using a device ID may allow close synchronization of the integrated circuit device design with back-end processing steps. Such back-end processing steps may include, for example, testing individual devices or attachment of individual devices to printed circuit boards. Identification codes may be particularly useful for manufacturers producing many diverse ICs, such as manufacturers of custom-designed application-specific integrated circuits (ASICs). Identification may also provide an opportunity for the end users of a product to resolve certain inventory problems in an unambiguous way.
In some cases, an identification code is externally programmed into a programmable, read-only register dedicated for that purpose. It is generally desired that the register be read-only in order to minimize the possibility that its contents will be altered during subsequent processing. The programming may take place during, for example, an initial wafer sort test. Although such external programming may allow additional information to be represented by an identification code, such as die-specific test performance information, there are disadvantages to this approach. In particular, external programming may be error-prone in that the possibility exists for the wrong code to be inadvertently programmed into a particular circuit""s identification register, which then renders that particular device useless to the extent that the device must be properly identified using the code. Also, non-volatile registers require the availability of special processing steps, which in themselves represent an added cost element.
An alternative approach is to design the metallization of the integrated circuit to directly wire the memory cells to on-chip programming voltages. The programming voltages are typically power supply voltages for the chip, so that the identification code is programmed into the identification register upon any power-up of the device (during testing, for example). Such internal programming of the circuit identification code may involve multiple mask levels of the integrated circuit, which are discussed briefly below.
Integrated circuit fabrication typically requires the use of multiple photolithography masks. Each mask is used to transfer a pattern to an upper layer of the semiconductor topography from which the circuit is formed, where the semiconductor topography includes a semiconductor wafer and the various layers and structures formed upon and within the wafer during the IC fabrication process. Multiple photolithographic masking steps are performed at various stages of the process, with patterning of one layer often followed by formation of and patterning of an additional layer. Generally, photolithography begins with formation of a layer of a photosensitive material called photoresist over the semiconductor topography. The photoresist is exposed to radiation through an appropriately patterned mask, so that properties of the photoresist are altered by the radiation in a pattern corresponding to the mask pattern. Depending on the particular type of the photoresist, either exposed or unexposed portions of the photoresist are then preferentially removed. The resulting photoresist pattern may be transferred to the underlying semiconductor topography, by processes such as etching or implantation of dopant impurities, as appropriate for the particular layer of the IC being formed.
During the product life cycle of an IC, various revisions may be made to its design and/or fabrication process. In fact, such revisions are often made during initial testing of a circuit design before the first devices are sold. Such revisions often involve changes to the mask used for patterning of a particular layer within the circuit. It is desirable in such cases to change the circuit identification code of a circuit undergoing a revision. Different codes can be used to distinguish one revision of the device from another, for example, or to later identify a particular mask or sequence of masks used to form a device.
In the case described above of a circuit identification register having its memory cells internally wired to programming voltages, however, changing the circuit identification code may require modification of multiple masks used to fabricate the integrated circuit. This can result in excessive time and expense, particularly in a case for which the revision of the circuit design requires changing of only one or two masks. It would therefore be desirable to develop a method of altering the circuit identification code of an IC when a mask pattern change is implemented. The code alteration should require changes to a minimal number of masks, and should not require excessive area on the circuit to implement.
The problems outlined above may be in large part addressed by a structure described herein for programming a memory cell on an integrated circuit. The structure provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In a preferred embodiment, there are two programming voltages used: the upper polarity of the circuit""s power supply (typically called xe2x80x9cVDDxe2x80x9d or xe2x80x9cVCCxe2x80x9d), and the lower polarity of the power supply (typically called xe2x80x9cVSS,xe2x80x9d and usually at ground potential). Application of VDD to the input of the memory cell would typically program a logical xe2x80x9c1xe2x80x9d into the cell, while application of VSS would program a xe2x80x9c0.xe2x80x9d In such an embodiment, both VDD and VSS are available at multiple mask levels, so that modification of a single mask can be used to change the value programmed into the memory cell. Preferably, all of the programming voltages are accessible at each mask level within the circuit involving either patterning of a conductor or formation of contacts or vias between conductor layers.
In an embodiment, the structure includes a conductive signal path extending through multiple horizontally conductive layers of the integrated circuit from a programming voltage pad (or node) to an input of the memory cell. The multiple horizontally conductive layers may be stacked above one another, such that the conductive signal path is in a generally vertical direction. A xe2x80x9chorizontally conductive layerxe2x80x9d as used herein is a layer having conductive structures arranged in a primarily horizontal direction (parallel to a polished surface of the semiconductor substrate on which the circuit is formed). A horizontally conductive layer may therefore be an interconnect layer, including patterned conductive interconnect lines. Such interconnect lines may be formed from metal, or other conductive materials such as polysilicon, which might be used in a local interconnect level. Patterned doped regions within the semiconductor substrate could also form a horizontally conductive layer. The horizontally conductive layers typically have via or contact layers interposed between them, where the via/contact layer is a dielectric layer having conductive vias or contacts formed therethrough. xe2x80x9cViaxe2x80x9d is typically used to describe vertical connections between metal lines, while xe2x80x9ccontactxe2x80x9d may be used to describe a vertical connection made to a semiconductor regions.
The above-described conductive signal path includes portions selected from multiple alternate path portions formed within the multiple horizontally conductive layers through which the signal path extends. In a preferred embodiment, the multiple alternate path portions are formed within each of the horizontally conductive layers. Each alternate path portion within a layer may correspond to one of the programming voltages available for programming the memory cell. In an embodiment for which the available programming voltages are VDD and VSS, for example, two corresponding alternate path portions may be available within a horizontally conductive layer. Each alternate path portion may further be connected to a pad or node for a respective programming voltage. Selection of the alternate path portions included within the conductive signal path may be done through the positions of conductive vias or contacts formed within via or contact layers interposed between the horizontally conductive layers. For example, one set of via positions may result in connection of VDD to the memory cell input, while a different set of via positions may cause VSS to be connected.
Selection of the alternate path portions included in a signal path such as that described above may be done as part of making the masks used in fabrication of the integrated circuit. The masks used to fabricate the integrate circuit may also include patterns to form portions of the above-described programming structure. A programming structure portion may be adapted to pass multiple programming voltages from one layer of the integrated circuit to an adjacent layer, where the programming voltages are adapted to program a memory cell on the integrated circuit.
An embodiment of a method for making a mask includes selecting one of multiple configurations of the programming structure portion to be formed using the mask. If the mask is for patterning of a horizontally conductive layer, the programming structure portion may include an alternate path portion for each of the multiple programming voltages, and the configurations to be selected from may include alternative arrangements (layouts) of these alternate path portions. One of the layouts to be selected from may be arranged such that the relative lateral positions of the programming voltages carried by contacts to the alternate path portions from below are unchanged with respect to relative lateral positions of the programming voltages carried by contacts to the alternate path portions from above. As an example, a configuration of two path portions may be selected such that if VDD and VSS are passed down to the path portions from above with VDD on the left and VSS on the right, VDD and VSS are also passed down from the path portions to the next underlying layer with VDD on the left and VSS on the right. The layouts to be selected from in making a mask may also include layouts arranged such that the relative lateral positions of the programming voltages carried by contacts to the alternate path portions from below are altered with respect to relative lateral positions of the programming voltages carried by contacts to the alternate path portions from above. To illustrate using the above example, a configuration could instead be selected such that VDD and VSS are passed down to the path portions from above with VDD on the left and VSS on the right, but the voltages are passed down from the path portions to the next underlying layer with VDD on the right and VSS on the left. In a method for making a mask to pattern a via or contact layer, the programming structure portion may include multiple conductive vias or contacts, and the configurations to be selected from in making the mask may include different positions of the vias.
A computer-usable carrier medium may include digital representations of the alternative configurations for a programming structure portion from which a programming structure pattern may be selected. The carrier medium may be a storage medium, such as a semiconductor memory or a magnetic or optical disk. The carrier medium could also include a transmission medium, such as a wire, cable, or wireless link, or a signal traveling along such a wire, cable or link. The digital representations may take the form of, for example, program instructions executable to generate the alternative patterns, or data points representing the patterns. The alternative patterns may include alternative arrangements of a set of multiple conductive path portions, where each conductive path portion is adapted to pass a respective programming voltage. The alternative configurations may also include alternative positions of a set of contact or via openings.
Use of a programming structure as may be defined by the above-described masks may allow masks used in fabrication of an integrated circuit to be identified after the circuit is made. A method for identifying a mask used in the manufacture of an integrated circuit may include reading a circuit identification code stored in a circuit identification register on the integrated circuit, and comparing a read value of one or more bits within the code to a design value of the bit(s). The design value is the value expected based on the configuration of a programming structure formed using the mask (typically along with other masks). In an embodiment, the method includes comparing a read circuit identification code from one revision of the integrated circuit to that from another revision, and comparing a difference between the codes to an expected alteration of the code based on the change in the programming structure caused by any mask changes associated with the revision.
The memory cell programmed by the above-described programming structure may be within a circuit identification register on the integrated circuit, and may be adapted to store a bit of a circuit identification code stored within the register. In addition to programming of a circuit identification code into a set of memory locations, the programming structure may be used to program memory locations for other purposes. The structure, methods, and carrier medium described herein are believed to be useful for any application for which the ability is desired to use a number of masks as low as one to change the value stored in a memory cell on an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds