1. Field of the Invention
The present invention relates to semiconductor device having a plurality of vertical metal oxide semiconductor field effect transistor (MOSFET) unit cells.
2. Description of the Related Art
A vertical MOSFET is used in power electronics field. A commonly used vertical MOSFET is a trench gate MOSFET.
The vertical MOSFET includes first and second source electrode regions and a base region. When viewed from above, the three regions are arranged in the order of the first source region, the base region, and the second source region. The first and second source regions are a first conductivity type (for example, N+ source regions), and the base region is a second conductivity type opposite to the first conductivity type (for example, a P+ base region).
An example of the semiconductor device having a plurality of vertical MOSFET unit cells is described in Japanese Unexamined Patent Publication No. 2000-031484. The semiconductor device aims at increasing cell density and decreasing on-resistance. FIG. 20 shows the semiconductor device. An N+ source region 102 is formed on a P+ base region 101. The N+ source region 102 has openings where the P+ base region 101 is exposed. FIG. 21 is a top view of this device. Three regions of a first N+ source region 103, a P+ base region 104, and a second N+ source region 105 are sequentially arranged in the surface part of the device.
The semiconductor device shown in FIGS. 20 and 21 has a plurality of unit cells arranged in a row. Thus, the P+ base regions 101 of two adjacent unit cells are continuous. Further, the N+ source region 102 is common to two adjacent unit cells. In other words, the N+ source regions 102 of adjacent unit cells are continuous.
In this semiconductor device, a channel region 106 is formed only in both sides of the N+ source region 102. This device thus fails to obtain a high channel density, which impedes the achievement of higher power MOSFET.
In addition, the semiconductor device shown in FIGS. 20 and 21 has a connecting portion 107 that connects the first and second N+ source regions 103 and 105 in both sides of the P+ base region 104. The minimum width required for the formation of the connecting portion 107 and the P+ base region 104 restricts the increase in integration density. The entire channel width is thereby restricted, making it difficult to reduce the on-resistance.
Normally in the vertical MOSFET, an avalanche current flows through the base region when a high reverse bias voltage that exceeds the withstand voltage is applied. Thus, if a reverse bias voltage increases, the avalanche current flows due to avalanche breakdown.
Hence, if base regions of a plurality of vertical MOSFETs are close to each other, a large current flow is concentrated to cause gate oxide layer breakdown and the like.
USPTO Backgrounds
USPTO Backgrounds