1. Field of the Invention
The present invention relates to a semiconductor device and to methods of operating and fabricating the same. More specifically, the present invention is directed to a non-volatile memory device and to methods of operating and fabricating the same.
2. Description of Related Art
Non-volatile memory devices store data in an electrically insulated manner. Typically, non-volatile memory devices include stack-gate memory devices, split-gate memory devices, and Electrically Erasable Programmable Read Only Memory (EEPROMs) devices.
FIG. 1 is an equivalent circuit diagram of a cell array of a conventional split-gate memory device, and FIG. 2 is a cross-sectional view of a conventional split-gate memory device.
FIG. 1 and FIG. 2, illustrate a cell array of a conventional split-gate memory device which adopts an NOR type cell array to randomly access memory cells. Memory cells are arranged in row and column directions to share a source region 22 or a drain region 24 with adjacent memory cells. Each of the memory cells includes a channel region defined between a source region 22 and a drain region 24, a gate insulation layer 12 formed on the channel region, a floating gate 14 formed on the gate insulation layer 12, a control gate electrode 16 formed on the gate insulation layer 12 and the floating gate 14, and a tunnel insulation layer 20 interposed between the control gate electrode 16 and the floating gate 14. An insulation layer having an elliptical section is formed on the floating gate 14, so that a tip is formed to enhance a tunneling efficiency.
As illustrated in FIG. 1, control gate electrodes 16 of memory cells arranged in a column direction are connected to constitute a wordline WLn, and source regions are connected to constitute a common source line CSL. A drain region of memory cells arranged in a column direction is connected to a bitline BLn. A NOR-type cell array of a stack-gate memory device has an over-erase problem, while a NOR-type cell array of a split-gate memory device does not have an over-erase problem because the control gate electrode formed on the gate insulation layer corresponds to a gate electrode of a select transistor.
In a split-gate memory device, a control gate voltage is applied to a control gate electrode 16 for forming a channel below the control gate electrode 16 and a program voltage of about 10 volts is applied to a source region 22 to inject charges into a floating gate 14 through a gate insulation layer 12. The program voltage is coupled to the floating gate 14 by an overlap capacitance of a source region 22 and the floating gate 14. Thus, a high program voltage is required for inducing a sufficient vertical field to a channel region. For this reason, the source region 22 must be configured to have a high junction breakdown voltage.
Unlike a split-gate memory device, an EEPROM is not required for a junction structure for applying a high junction breakdown voltage because a relatively lower voltage is applied to a source region or a drain region.
FIG. 3 is an equivalent circuit diagram of a cell array of a conventional EEPROM, and FIG. 4 is a cross-sectional view of the conventional EEPROM.
Referring to FIG. 3 and FIG. 4, unlike a split-gate memory device, an EEPROM has a configuration where a select gate electrode and a control gate electrode are isolated from each other. Memory cells of the EEPROM are arranged in row and column directions and share a source region 68 and a drain region 66 with adjacent memory cells. Each of the memory cells includes a channel region defined between a source region 68 and a drain region 66, a tunnel insulation layer 52 and a gate insulation layer 54 which are formed on the channel region, a floating gate 56 formed on the tunnel insulation layer 52 and the gate insulation layer 54, and a control gate electrode 60 formed on the gate insulation layer 54 to be spaced apart from the floating gate electrode 56. A select gate electrode 58 is formed on the floating gate 56 with an intergate dielectric 62 interposed therebetween. A floating diffusion layer 64 is formed in a substrate between the floating gate 56 and the control gate electrode 60 to extend to the bottom of the tunnel insulation layer 52.
As illustrated in FIG. 3, select gate electrodes of memory cells arranged in a column direction are connected to constitute a sensing line SL. Control gate electrodes of memory cells arranged in a column direction are connected to constitute a wordline WL, and source regions in a column direction connected to a common source line CSL. A sensing line SL is divided into a plurality of cell units to selectively erase memory cells connected to a wordline WL. Since an EEPROM requires a wider cell area than a split-gate memory device, there is a limit to an integration density of the EEPROM.
As previously stated, a split-gate memory device has a control gate electrode acting as a gate electrode of a select transistor. Thus, the split-gate memory device is advantageous in high integration density. However, with split-gate memory devices, a high breakdown voltage is required because a program operation is performed by source junction coupling of a low coupling ratio. Meanwhile, an EEPROM device, in which a program operation is performed by gate coupling, does not require a high junction breakdown voltage. Nevertheless, EEPROM devices have certain disadvantages such as a large cell area and a limited integration density because a select gate electrode and a control gate electrode are spaced apart from each other.
USPTO Backgrounds
USPTO Backgrounds