1. Field of the Invention
The present invention relates to a memory cell capacitor and method for forming said memory cell capacitor. More particularly, the present invention relates to a method of forming memory cell capacitors by efficiently utilizing the area over the surface of a semiconductor substrate.
2. State of the Art
A widely-utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes CMOS (Complimentary Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor. In the most common circuit designs, one side of the transistor is connected to one side of the capacitor, the other side of the transistor and the transistor gate are connected to external circuit lines called the bit line and the work line, and the other side of the capacitor is connected to a reference voltage that is typically one-half the internal circuit voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor that charges and discharges the circuit lines of the capacitor.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, DRAM chips have been continually redesigned to achieve ever higher degrees of integration. However, as the dimensions of the DRAM chips are reduced, the occupation area of each unit memory cell of the DRAM chips must be reduced. This reduction in occupied area necessarily results in a reduction of the dimensions of the capacitor, which, in turn, makes it difficult to ensure required storage capacitance for transmitting a desired signal without malfunction. However, the ability to densely pack the unit memory cells, while maintaining required capacitance levels, is a crucial requirement of semiconductor manufacturing if future generations of DRAM chips are to be successfully manufactured. This drive to produce smaller DRAM circuits has given rise to a great deal of capacitor development.
In order to minimize such a decrease in storage capacitance caused by the reduced occupied area of the capacitor, the capacitor should have a relatively large surface area within the limited region defined on a semiconductor substrate. However, for reasons of available capacitance, reliability, and ease of fabrication, most capacitors are stacked capacitors in which the capacitor covers nearly the entire area of a cell and in which vertical portions of the capacitor contribute significantly to the total charge storage capacity. In such designs, the side of the capacitor connected to the transistor is generally called the "storage node" or "storage poly" (since the material out of which it is formed is doped polysilicon) while the polysilicon layer defining the side of the capacitor connected to the reference voltage, mentioned above, is called the "cell poly".
U.S. Pat. No. 5,292,677 issued Mar. 8, 1994 to Dennison and U.S. Pat. No. 5,459,094 issued Oct. 17, 1995 to Jun each teach methods for fabricating capacitors for memory cells. However, as with other known fabrication methods, these methods require numerous complex steps in forming the capacitors and do not maximize the size of the capacitor by efficient use of the space above the semiconductor substrate.
Therefore, it would be advantageous to develop a technique for forming a high surface area capacitor and a memory cell employing same, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and apparatus without requiring complex processing steps.
USPTO Backgrounds
USPTO Backgrounds