The present disclosure generally relates to a method of providing direct mapped (DM) cache access and direct mapped-associative index extended (DM-AIX) cache access in a memory circuit employing a self-reconfigurable decoder, and a semiconductor circuit for implementing the same employing a new cache replacement scheme for (DM-AIX) caches.
To overcome the central processing unit (CPU) to main memory performance gap, a cache hierarchy exploiting locality is needed. System performance is heavily dependent upon average memory address time (AMAT). Most L1 and L2 caches currently in use employ either direct mapped (DM) caches, set associative (SA) caches, or fully associative (FA) caches.
Direct-mapped caches and, to an extent, set associative caches suffer from conflict misses. Average memory address times at L1 cache level is the sum of the L1 hit time and the product of L1 miss rate and L1 miss penalty in time. L1 miss penalty is the sum of L2 hit time and the product of L2 miss rate and L2 miss penalty in time.
In general, hit time reduction can be provided by technology scaling improvements because the delay time Δt is given by the product of the capacitance and the voltage of the circuit device divided by the current of the circuit. Further, hit time reduction can be effected by astute circuit design, which tends to provide incremental benefits with each technology generation. Miss rates can be reduced by enhanced cache organization and/or increased cache capacity. In general, increased capacity of the cache decreases the miss rate asymptotically. The miss rate is affected by the type of the cache. Specifically, direct-mapped caches tend to have a larger miss rate than set associative caches at the same capacity level.
The various types of caches known in the art require tradeoffs between design and miss rate. For example, direct-mapped caches are fast and easy to design and verify, but suffer from conflict misses and high miss rates. Set associative caches are slower because more comparators are employed during tag match, and replacement policies get complicated. Fully associative caches are slowest and hardest to design, do not have conflict misses, and provide the least miss rate. Further, even simple line replacement policies become impractical in fully associative caches.
USPTO Backgrounds
USPTO Backgrounds