Field of the Invention
The invention relates to a method for fabricating field-effect transistors, in particular MOS transistors, in integrated semiconductor circuits, in which mutually spaced-apart source and drain regions of a first conductivity type are produced in a semiconductor substrate of an opposite conductivity type. A plurality of strip-type gate regions are produced in each case between mutually assigned adjacent source and drain regions, and the gate regions respectively associated with a field-effect transistor are interconnected. The invention likewise relates to a field-effect transistor that is provided within an integrated semiconductor circuit and has at least two gate regions that in each case extend between a source region and a drain region in or on a substrate and are interconnected by an electrical connection. Furthermore, the invention relates to an integrated semiconductor circuit having at least one field-effect transistor of this type.
MOS field-effect transistors are very often used for driver transistors in integrated semiconductor circuits. Larger field-effect transistors of this type, i.e. higher-power field-effect transistors, have hitherto been fabricated in such a way that a plurality of parallel gate strips are disposed in finger form in/on a substrate between respectively assigned source and drain regions. In this case, such a field-effect transistor configured for a higher power could easily have a lateral dimension measuring ten times its width dimension, which is e.g. 50 xcexcm, the lateral dimension measuring e.g. 500 xcexcm.
In the course of large scale integration of integrated semiconductor circuits, such a large area of the driver transistors is unacceptable and a method is desired for reducing the space requirements of such driver transistors.
Consequently, it is an object of the invention to realize, in an integrated semiconductor circuit, larger field-effect transistors, i.e. higher-power field-effect transistors, with a reduced space requirement.
It is accordingly an object of the invention to provide a method for fabricating field-effect transistors in integrated semiconductor circuits and an integrated semiconductor circuit fabricated with a field-effect transistor of this type that overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which a higher-power field effect transistor with a reduced space requirement is produced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a field-effect transistor in an integrated semiconductor circuit. The method includes producing mutually spaced-apart source and drain regions of a first conductivity type in or on a semiconductor substrate of a second conductivity type opposite the first conductivity type. A section of a main area of the semiconductor substrate is etched-out between the source and drain regions resulting in an etched substrate section. A first gate region is formed in the etched substrate section, with a result that the first gate region lies between the source and drain regions. A semiconductor material is deposited above the first gate region in the etched substrate section. At least one second gate region is produced above the first gate region with an interposition of the semiconductor material. The first gate region is connected to the second gate region on at least one side free of the source and drain regions with an electrically conductive material. The source and drain regions being common to the first gate region and the second gate region lying one above the other.
In order to achieve the object, the invention proposes a generic method for fabricating field-effect transistors, in particular MOS transistors, in integrated semiconductor circuits, which is characterized in that the plurality of gate regions respectively associated with a field-effect transistor are disposed in layers one above the other in and/or on the substrate in the thickness direction thereof. In other words, the way into the third dimension is taken instead of extending the transistor in the plane of the main area of the integrated semiconductor circuit. Situated between the gate regions disposed one above the other there is in each case a semiconductor layer, in particular a silicon layer, and a source region on one side of the gate regions and a drain region on the other side are common to all the gate regions lying one above the other. A fabrication method of this type can be implemented using process steps that are known in detail. First, a section is etched out within a substrate section, defining a field-effect transistor, in each case between a source region and an associated drain region from a main area of the substrate. Afterward, a first gate region is produced in the substrate within the etched section, with the result that the first gate region lies between the two associated source and drain regions. Afterward, the first gate region within the etched substrate section is covered with a semiconductor material, e.g. silicon. Finally, a second gate region is formed above the first gate region, i.e. above that region of the same which is covered by the semiconductor material. It goes without saying that not only two but more than two gate regions can be disposed one above the other in this way. To that end, the depth of the mutually associated source and drain regions and the etching depth in between must be correspondingly greater in the thickness direction of the substrate. The assigned gate regions are subsequently conductively connected to one another.
Preferably, a field-effect transistor fabricated in this way is a MOS transistor, the substrate region defining the transistor is a p-doped silicon substrate region, and the drain and source regions are composed of n-type silicon.
The gate regions lying one above the other can be connected in a simple manner on at least one side thereof which is free of the drain and source region by a readily electrically conductive material.
The above features according to the invention show that a field-effect transistor according to the invention not only has the advantage of the reduced space requirement on the semiconductor chip but also saves electrical contacts, since there is only one source region and one drain region, so that there is no need to connect mutually associated source regions or drain regions to one another, as have been necessary hitherto in the prior art.
The space saving through a field-effect transistor realized by the method according to the invention in an integrated semiconductor circuit is greater, the more gate regions that are disposed such that they lie one above the other.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating field-effect transistors in integrated semiconductor circuits and an integrated semiconductor circuit fabricated with a field-effect transistor of this type, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds