1. Field of the Invention
The present invention relates to a bus bridges and, more particularly, it relates to a primary-to-secondary bus bridge supported by an existing BIOS (Basic Input/Output Standard) and allowing controlling of a plurality of devices on the secondary bus including a VGA (Video Graphics Array) device through the primary bus.
2. Description of Background Art
A PCI (Peripheral Component Interconnect) bus is now widely used in personal computers. PCI is a bus standard advocated by Intel Corporation, of which specification is determined and published by PCI Special Interest Group (PCI SIG) of the United States. According to the PCI bus standard, a device participating in PCI data transfer is referred to as an “agent.” According to PCI standard, agents are controlled by BIOS executed by a CPU (Central Processing Unit), by a device driver and so on. PCI bus standard provides automatic configuration capability of automatically sensing a device connected to the bus at the time of power-on and preparing system environment such as memory mapping for each system.
Recently, as personal computers come to have ever improved performance, it comes to be a common practice to execute, by a personal computer, image processing programs and the like, which have conventionally been executed by a workstation. For this purpose, an LSI (semiconductor Large Scale Integrated circuit) for performing such a specific processing is often connected to a host CPU through a PCI bus in the personal computer. Implementation of a plurality of PCI devices in the integrated circuit is desirable in some cases. At that time, it is necessary to interface the PCI bus of the host with a PCI bus of an added device. Here, the PCI bus in the host CPU is called a primary PCI bus, and the PCI bus of a circuit (add-in board) connected to the primary PCI bus is called a secondary PCI bus.
If a secondary PCI bus is connected to the primary PCI bus and a plurality of PCI agents are connected to the secondary PCI bus, it is necessary for the host to control PCI agents independent from each other. For this purpose, PCI standard employs data called a PCI configuration header. The header includes two types, i.e., “Type 0” and “Type 1”. “Type 0” header is recognized by the host CPU as one PCI agent, and “Type 1” header is prepared for the PCI-to-PCI bridge.
The “PCI-to-PCI Bridge Architecture Specification” (Rev. 1.1) specifies in detail the implementation of a configuration “Type 1” header into a PCI-to-PCI bridge device. The configuration address format of the “Type 1” is shown in FIG. 4 and will be described in detail later in the detailed description of the embodiments of the present invention. The specification provides a universal configuration methodology for all systems, given the BIOS supports the “Type 1” format.
Referring to FIG. 1, a typical PCI-to-PCI bridge 250 of the prior art includes a primary port connected to a primary bus 42, and a secondary port 254 connected to a secondary bus 44. The PCI-to-PCI bridge 250 further includes a bridge core 252, provided between primary port 60 and secondary port 254, for interfacing the primary bus 42 and the agents connected to secondary bus 44 such as agents 260, 262, 264.
As shown in FIG. 4, one of the restrictions of the PCI-to-PCI bus bridge according to the specification is that only a single secondary port 254 is defined that is shared by all PCI agents (agents 260, 262, 264), located on the secondary bus 44. If one tries to build an AGP (Accelerated Graphics Port)-to-AGP bridge upon this specification, a major problem emerges.
AGP is an interface targeted to 3D graphical display applications advocated by Intel Corporation, operating upon a PCI bus architecture. AGP standard includes electrical specification of the hardware, specification of the signals used, and the specification of the protocols.
Operational modes of AGP includes a normal operational mode in a normal transfer rate (1× transfer mode) as well as 2× transfer mode or 2× mode wherein data are transferred at twice the normal rate, and 4× transfer mode or 4× mode wherein data are transferred at four times the normal rate. Since AGP 2× and especially AGP 4× introduce very strict electrical and timing constraints, a shared port as shown in FIG. 1 is not a feasible option. Thus, two or more dedicated secondary ports have to be implemented as shown in FIG. 2.
Referring to FIG. 2, the PCI-to-PCI bridge 270 will include a primary port 60, first secondary port (Port A) 64 and a second secondary port (Port B) 66. The PCI-to-PCI bridge 270 will further include a bridge core, provided between primary port 60 and secondary ports 64 and 66 for interfacing the primary bus 42 connected to primary port 60 and the secondary buses 44A and 44B connected to port A 64 and port B 66, respectively.
This way, an AGP device, e.g. device 260, does not have to share a port with other agents, but can own a port, e.g., port A 64, exclusively. The other port can be populated with a plurality of PCI devices. Of course, the bridge should also be usable as a pure PCI bridge, i.e., it should operate with only PCI devices hooked to the secondary ports.
Finally, if an AGP device is operated in a lower data rate, such as AGP 1× or AGP 2×, a shared port is feasible if special care is taken during the system design.
A problem with a plurality of secondary ports is that the bridge has to know to which port to route configuration accesses during configuration cycles after boot-up. In contrast to memory access, where the dispatching is governed by the memory maps, the only information provided with configuration accesses is the Device Number in the “Type 1” address format. The Bios starts reading from device number 0 and increments its way upwards until it encounters a master abort error (MAE) where the secondary port response indicates that no device is responding.
Since the AGP-to-AGP bridge will have two decoupled ports, it will have to start on one port, i.e., port A. If the bridge does not know when it exceeds the number on devices on port A, the device number will be too high resulting in a master abort error and the BIOS will conclude its screening.
However, the devices on port B have not been scanned yet. Thus, they will not be configured by the BIOS and the system resources only will be allocated for port A. The problem will be also encountered if the bridge includes two or more secondary ports. The problem is not restricted to a PCI-to-PCI bridge. Still further, if a bridge has two or more secondary ports, two or more VGA devices may be connected to the secondary ports. At the present, a VGA device that first responds is used as a display during the boot-up. There is no way for the user to preselect a VGA device that the user prefers to use during the boot-up.
USPTO Backgrounds
USPTO Backgrounds