1. Field of the Invention
The present invention relates to the field of power electronics. It relates in particular to a controlled-turn-off high-power semiconductor component for a maximum turn-off current of more than 100 A, comprising
(a) a semiconductor device having an active semiconductor area which is substantially greater than 1 cm.sup.2 ; PA1 (b) a fine structure composed of a multiplicity of parallel-connected individual elements inside the semiconductor device; PA1 (c) the individual elements being combined in groups.
Such a component is known, for example, from the publication EP-A3-0 064 231 in the form of a transistor or gate-turn-off thyristor (GTO).
2. Discussion of Background
Because of the continuously increasing requirements imposed by circuit engineers, future power semiconductor components will also be finely structured in the high-power range, i.e. will have structures in the .mu.m range. In this connection, both purely bipolar and mixed bipolar and MOS technologies (BiMOS) are suitable for the implementation. An example of the medium power range, where these structures are already established, is the IGBT (Insulated Gate Bipolar Transistor).
On the one hand it is now generally known that, as current loading increases, the active areas and, consequently, the chip size of such components also increase. Thus, in the high-power range, currents (from a few 100 A up to a few 1000 A) are controlled or switched, and these can only be handled with chip areas which are substantially greater than 1 cm.sup.2.
On the other hand, unavoidable defects which limit the so-called chip yield occur in the production of semiconductor components. In this connection, the density of these defects is essentially determined by the available clean-room class and the number of process steps. Naturally, the yield decreases with increasing chip area and also with increasing miniaturization of component structures. In practice, it is currently assumed that finely structured components having chip areas which are substantially greater than 1 cm.sup.2 cannot be manufactured economically. This also manifests itself, for example, in the chip prices: 5 MOSFETs each carrying 10 A taken together are cheaper than 1 chip carrying 50 A.
So-called "repair techniques" which are intended to enable the defects to be eliminated or to be passivated and acceptable yields consequently to be achieved, nevertheless, on large areas are therefore being intensively investigated for the high-power components mentioned. Thus, in a large-area semiconductor component (GTO or power transistor) which comprises several 1000 individual elements, the publication mentioned in the introduction proposes to combine the individual elements in groups (for example, of 100 each) and to make common contact for each group. In this way, defective individual elements can be more easily detected inside a group and rendered harmless.
Such repair concepts have, however, the following disadvantages:
The decommissioning of particular individual elements or of entire subareas results in an inhomogeneous current distribution over the component area, which may possibly impair the electrical operation, in particular the turn-off power in the case of thyristors; and
the repair itself (including the identification of the defective individual elements) requires a substantial metrological and time expenditure.
USPTO Backgrounds
USPTO Backgrounds