1. Technical Field
The present disclosure relates to a Delay Locked Loop (DLL) circuit and, more particularly, to a multi-phase generating method and apparatus for generating a plurality of clock signals having equal phase differences between each other, regardless of the frequency of an external clock signal.
2. Discussion of Related Art
As the bandwidth of systems increases, Phase Locked Loop (PLL) circuits and Delay Locked Loop (DLL) circuits are used more and more. DLL circuits are especially widely used due to their excellent stability and favorable jitter characteristics.
FIG. 1 is a block diagram of a conventional DLL circuit 100.
Referring to FIG. 1, the conventional DLL circuit 100 includes a buffer 110, a delay cell block 120, a multiplexer 130, a phase detector 140, a controller 150, and an interpolator 160.
The delay cell block 120 includes N delay cells D1 through Dn. The first delay cell 121 delays the phase of an external clock signal ext_CLK received through the buffer 110 by a predetermined delay time, and generates a first delayed clock signal CLK1. The second delay cell 122 delays the phase of the first delayed clock signal CLK1 by a predetermined delay time and generates a second delayed clock signal CLK2. The third delay cell 123 delays the phase of clock signal CLK2 by a predetermined delay and generates a third delayed clock signal CLK3. Likewise, the N-th delay cell 12N delays the phase of an (N-1)-th delayed clock signal CLKN-1 by a predetermined delay time, and generates an N-th delayed clock signal CLKN.
The multiplexer 130 selects two delayed clock signals from among the plurality of delayed clock signals CLK1 through CLKN generated by the delay cell block 120, in response to a control signal C1 received from the controller 150, and outputs the selected delayed clock signals to the interpolator 150. The multiplexer 130 includes two multiplexer units that respectively output different delayed clock signals to the interpolator 150.
The phase detector 140 compares the phase of the external clock signal ext_CLK with the phase of the delayed clock signal received from the multiplexer 130 and outputs an UP signal or a DOWN signal to the controller 150, according to the result of the comparison. That is, the phase of an external clock signal ext_CLK is compared with the phase of a delayed clock signal from the delay cell block 120 at the output of the multiplexer 130, and a signal corresponding to the difference between the phases is output.
The controller 150 outputs the first control signal C1 for causing the multiplexer 130 to select delayed clock signals, according to the UP or DOWN signal received from the phase detector 140, and a second control signal C2 for controlling the interpolator 160. That is, the controller 150 outputs control signals C1 and C2 to select desired delay cells from among the delay cells 121 through 12N, thereby performing a series of processes for frequency locking.
The interpolator 160 performs interpolation on the two delayed clock signals received from the multiplexer 130, and generates an internal clock signal int_CLK that is suitable for use in a system that includes the DLL. That is, by performing interpolation on the two delay clock signals having different delay times, the interpolator 160 performs a frequency locking process with the correct phase.
When the system operates at a high frequency, because electrical characteristics required to operate the system normally are loose, jitter increases if the unit delay time of each delay cell included in the delay cell block 120 is too long. On the other hand, when the system operates at a low operating frequency, although electrical characteristics required to operate the system normally are comparatively loose, frequency locking is difficult if the total delay time of the delay cells is too short. Accordingly, a multi-phase generating apparatus that can be applied to a wide frequency range is needed.
FIG. 2 is a block diagram of a conventional multi-phase generating apparatus 200.
Referring to FIG. 2, the conventional multi-phase generating apparatus 200 includes a reference phase generator 210 and a delay cell matrix 220. The reference phase generator 210 includes a plurality of main delay cells 211 through 215, and the delay cell matrix 220 includes a plurality of sub delay cells 211_1 through 225_N.
The first main delay cell 211 delays the phase of an external clock signal ext_CLK by a first predetermined time, and generates a first delayed clock signal CLK1. The second main delay cell 212 delays the phase of the external clock signal ext_CLK by a second predetermined time, and generates a second delayed clock signal. The third main delay cell 213 delays the phase of the external clock signal ext_CLK by a third predetermined time and generates a third delayed clock signal CLK3. The fourth main delay cell 214 delays the phase of the external clock signal ext_CLK by a fourth predetermined time and generates a fourth delayed clock signal CLK4. Likewise, a fifth main delay cell 215 delays the phase of the external clock signal ext_CLK by a fifth predetermined time, and generates a fifth delayed clock signal CLK5.
The respective delayed clock signals CLK1 through CLK5 generated by the reference phase generator 210 have equal phase differences between each other, and are reference clock signals for causing the delay cell matrix 220 to generate multi-phase clock signals. The respective clock signals CLK1 through CLK5 are input to the delay cell matrix 220 through different channels. The delay cell matrix 220 includes N stages.
Because the number of main delay cells included in the reference phase generator 210 can vary, the number of channels required for connecting the reference phase generator 210 with the delay cell matrix 220 can also increase or decrease. Accordingly, the number of multi-phase clock signals that will be generated by the delay cell block 200 can also change.
If the reference phase generator 210 generates the reference clock signals CLK1 through CLK5, the delay cell matrix 220 receives the reference clock signals CLK1 through CLK5 through the corresponding channels, and sequentially generates multi-phase clock signals through N stages. For example, if the delay cell matrix 220 includes 40 sub delay cells, the delay cell matrix 220 can generate 40 clock signals having phase differences of 90 (360/40) between each other.
Because the delay cell matrix 220 generates the multi-phase clock signals on the basis of the reference clock signals CLK1 through CLK5 received from the reference phase generator 210, the delay cell matrix 220 cannot generate multi-phase clock signals having equal phase intervals to each other if there are offsets generated in the phases of the reference clock signals CLK1 through CLK5.
FIG. 3 is a table illustrating the phases of the multi-phase clock signals output from the multi-phase generating apparatus 200 illustrated in FIG. 2. In FIG. 3, the phases of five reference clock signals and the phases of 40 multi-phase clock signals generated using the reference clock signals are illustrated.
Referring to FIGS. 2 and 3, the reference phase generator 210 generates five reference clock signals having respective delay phases of 9°, 18°, 27°, 36° and 45°, through the main delay cells 211 through 215. The delay cell matrix 220 generates eight multi-phase clock signals having different phases for each reference clock signal, through five delay lines.
Accordingly, if offsets exist in the phases of the reference clock signals generated by the reference phase generator 210, the delay cell matrix 220 will generate multi-phase clock signals that will reflect or amplify the offsets. This reduces the stability of a system requiring clock signals having equal phase intervals relative to each other.
FIG. 4 is a graph showing the non-linearity of a multi-phase clock signal, and FIG. 5 is an illustration for explaining a change in a reference clock signal with respect to a change in frequency.
Referring to FIG. 4, multi-phase clock signals having normal phase differences between each other are denoted by a solid line, and multi-phase clock signals having abnormal phase differences between each other are denoted by dotted lines. Since the multi-phase clock signals having the normal phase differences between each other have equal phase intervals between each other, the multi-phase clock signals have linearity. On the other hand, because the multi-phase clock signals having the abnormal phase differences between each other have unequal phase intervals between each other, the multi-phase clock signals are non-linear.
Referring to FIG. 5, the left part of FIG. 5 represents reference clock signals generated by the reference phase generator 210 when a high-frequency clock signal is received, and the right part of FIG. 5 represents reference clock signals generated by the reference phase generator 210 when a low-frequency clock signal is received.
If the linearity of phase delays is adjusted based on a high-frequency clock signal, non-linearity of phase delays occurs in a low-frequency clock signal. On the contrary, if the linearity of phase delays is adjusted based on a low-frequency clock signal, non-linearity of phase delays occurs in a high-frequency clock signal. That is, if the frequency of an external clock signal changes, the stability of the reference phase generator 210, shown in FIG. 2, cannot be ensured.
More specifically, in next-generation Digital Versatile Disk (DVD) and Blue-ray Disk (BD) systems, the importance of multi-phase clock signals is increasing. In the conventional technologies, however, because the possibility of phase offsets increases as the number of multi-phase signals increases, a problem can occur when data is read to or written from a storage medium such as optical discs.
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