The present disclosure is generally directed to polyacenes and uses thereof. More specifically, the present disclosure in embodiments is directed to a class of polyacenes selected as solution processable and substantially stable channel semiconductors in organic electronic devices, such as thin film transistors.
There are desired electronic devices, such as thin film transistors (TFT) fabricated with polyacenes, with excellent solvent solubility, which can be solution processed, and which devices possess mechanical durability and structural flexibility, characteristics which are selected for fabricating flexible TFTs on plastic substrates. Flexible TFTs enable the design of electronic devices with structural flexibility and mechanical durability characteristics. The use of plastic substrates together with the polyacene components can transform the traditionally rigid silicon TFT into a mechanically more durable and structurally flexible TFT design. Thus, can be of particular value to large area devices, such as large-area image sensors, electronic paper and other display media. Also, the selection of polyacene TFTs for integrated circuit logic elements for low end microelectronics, such as smart cards, radio frequency identification (RFID) tags, and memory/storage devices, may enhance their mechanical durability, and thus their useful life span.
A number of semiconductor materials are not, it is believed, stable when exposed to air as they become oxidatively doped by ambient oxygen, resulting in increased conductivity. The result is large off-current and thus low current on/off ratio for the devices fabricated from these materials. Accordingly, with many of these materials, rigorous precautions are usually undertaken during materials processing and device fabrication to exclude environmental oxygen to avoid or minimize oxidative doping. These precautionary measures increase the cost of manufacturing therefore offsetting the appeal of certain semiconductor TFTs as an economical alternative to amorphous silicon technology, particularly for large area devices. These and other disadvantages are avoided or minimized in embodiments of the present disclosure.
USPTO Backgrounds
USPTO Backgrounds