1. Field of the Invention
The invention relates to magnetic annealing of fabricated magnetic random access memory (MRAM) elements, and more specifically to single substrate magnetic annealing of magnetic random access memory elements.
2. Description of the Related Art
Various types of electronic devices utilize ferromagnetic materials with defined magnetic properties. Among these are magnetic random access memory (MRAM) devices which contain arrays of magnetic memory elements formed using magnetic tunnel junction (MTJ) or giant magnetoresistance (GMR) principals. Operation of the memory elements depends in part on a pinned magnetic layer having a specific orientation of the magnetic field. The pinned magnetic layer is typically pinned by an antiferromagnetic (AF) layer having a specific magnetic field orientation. In a typical application, the pinning is effected by a thin layer (˜100 Å) of AF material, such as IrMn, adjacent a ferromagnetic (FM) material, such as NiFe.
An example of a layered structure 30 for a magnetic tunnel junction formed on a wafer is illustrated in FIG. 3. Structure 30 includes two outer lead layers 32, 44 made of tantalum (Ta). Sandwiched between the lead layers are a free ferromagnetic layer 34 and a pinned ferromagnetic layer 40 made of nickel-iron (NiFe). A tunneling barrier layer 36 of aluminum oxide (Al2O3) is provided between the two ferromagnetic layers, and a magnetic pinning (anti-ferromagnetic) layer 42 of iridium manganese fixes the orientation of the adjacent pinned ferromagnetic layer 40. The layers shown in FIG. 3 are representative: for example, the layers may be arranged differently, may use different materials, and are not necessarily equal in thickness.
Annealing is performed to fix the magnetic orientation of the pinned layer 40. By heating the material to its Néel temperature and applying a magnetic field until the material cools below the Néel temperature, the magnetic field of the iridium manganese is fixed in a particular orientation. The anti-ferromagnetic (AF) layer 42 adjacent the ferromagnetic layer 40 holds or “pins” the magnetic field of the ferromagnetic layer in a fixed orientation.
Known manufacturing processes for annealing the anti-ferromagnetic layer, for example, include a bulk process in which a batch of wafers is heated in a large oven to the Néel temperature and a strong magnetic field is applied while the wafers cool. As a result, anti-ferromagnetic layers formed on the wafers will have a fixed magnetic field orientation.
According to the known bulk processes, the applied magnetic field is generated either by a large electromagnet or a large permanent magnet. Either way, a powerful magnet is necessary to provide the required uniform magnetic field over the large volume of wafers. Consequently, the known bulk processes have several disadvantages, including the need for long heating cycles (greater than an hour, and up to five hours, for 25 wafers, for example) and large, bulky structures for magnetic field generation.
One difficulty of a prolonged annealing process, such as the bulk process described above, is interdiffusion of the ultra-thin layers of the layered structure 30. During heating, manganese ions, for example, tend to migrate through the layered structure from layer 42 through layer 40, and can build up against layer 36, forming a high-manganese concentration area as represented by the narrow layer 38. The build-up of manganese degrades the performance of the structure, for example, by disadvantageously diminishing the tunneling magnetoresistive (TMR) signal that otherwise would be generated by the device structure.
Referring to FIG. 4, a time vs. temperature plot 50 for one bulk anneal process is shown. A load of devices is heated in an oven which is held at an annealing temperature TA. As can be seen from the graph, before and after reaching the Néel temperature TN, the devices being annealed undergo heating for a significant period of time. During the extra heating time, unwanted changes can occur in the MRAM devices being annealed, such as manganese ion migration noted above.
In addition, when entire devices are being heated during the annealing process, high annealing temperatures may have adverse effects on other materials in the devices. Low temperature plasma enhanced chemical vapor deposition (PECVD) films may undergo densification or modification of stress levels, for example. Accordingly, prior art processing requirements can limit the types of materials to be used in fabrication of a magnetic memory element.
Further, in bulk processing, uniform magnetic field and heating parameters on individual wafers may be difficult to control. For example, the amount and duration of heating experienced by each device will vary with the device's position in the bulk processing chamber.
One attempt to avoid a bulk anneal process is disclosed in U.S. Pat. No. 6,027,948 to Jensen et al. In this patent, annealing is applied to a packaged die. The packaged die, containing magnetic memory elements, is placed in a fixture positioned between the poles of a magnet. The self-contained assembly of the combined die, fixture, and magnet is subjected to elevated temperatures. This process unnecessarily subjects the entire packaged device to heating, such that only limited, heat-resistant materials can be used in the package.
A method of annealing MRAM devices which does not damage the devices or any associated packaging would be desirable.
USPTO Backgrounds
USPTO Backgrounds