Very often, data processing devices, such as microprocessors, microcontrollers, digital signal processors, coprocessors and the like, need a temporary data storage area for data processing. Conventionally, one or more memory blocks are provided, which can be instantiated by the IC designer.
Integrated circuit (IC) designers are normally faced with the problem of deciding whether to implement the memory block or blocks as First-In, First-Out (FIFO) memories, or to instantiate a Random Access Memory (RAM).
FIFO memories and RAMs have respective pros and cons.
As known, a FIFO memory includes a monodimensional array of memory elements, and can only be accessed sequentially in a first-in, first-out manner; in other words, in a FIFO memory it is not possible to access randomly a generic memory element within the array. This may be a significant limitation. However, FIFO memories are capable of operating at high speeds (low access time), and are used as large data buffers.
On the contrary, a RAM is a bidimensional array of memory elements that can be accessed randomly, both in writing and in reading. However, RAMs often feature operating speeds slower than that of the FIFO memories.
In many cases, application constraints set a clear cut choice between a FIFO memory or a RAM. For example, if a block of memory elements is needed that are randomly accessible either in writing or in reading, and the operating speed requirements are not very strict, the IC designer can choose to instantiate a RAM; conversely, if the operating speed requirements cannot be satisfied by the available RAMs, and the applicative context does not compel randomly accessible memory elements, a FIFO memory is chosen.
Nevertheless, there are cases in which the choice is not straightforward. For example, it may be necessary to have a memory that is randomly accessible and at the same time features a high operating speed, higher than that achievable by the available RAM technology.
It has been found that in some applications a fully randomly accessible memory block is not really required. For example, it has been found that there are applications in which while the retrieval of data from the memory block needs to be random, the storage of data in the memory block may be sequential, or vice versa.
USPTO Backgrounds
USPTO Backgrounds