1. Field Of The Invention
The present invention relates to digital computers and specifically, to the apparatus used to connect memory units that store shared information to the functional elements of a digital computer, including units for central processing and Input/Output. The present invention applies to multiprocessor, multicomputer or network systems operating across a parallel or serial bus structure for distribution of information in a common environment. The invention facilitates software control of the storage and retrieval of data in a distributed architecture.
2. Description Of The Prior Art
Computer memory architecture conventionally has been organized for shared use, wherein a central processing unit (CPU) uses the memory for storage of programs and data and shares a common memory read/write path, typically a bus with Input/Output (I/O) devices. The read/write format employed in such architecture typically consists of a first group of binary bits which represent a specific memory location and second group of binary bits which represent information. The bits representing a specific memory location are called the "memory address". The bits representing the information are called "data". Both groups of bits are transmitted during a "write cycle" to the memory unit which decodes the address bits to determine a physical location and stores the information bits at that location. During a "read cycle" the address bits are transmitted by a requesting unit, along with a control bit representing a read request, to the memory unit. The memory control logic retrieves the data from the specified address and returns the data over the data bus to the requesting unit. The transmission of both address and data on a common bus during a single bus cycle is conventionally designated as a "value" transfer.
Early computer designs typically had a limited memory addressing capability (represented by the number of address bits the CPU could generate) and addressed the memory in a direct addressing mode. The address generated by the CPU was the same as the real physical address decoding a specific memory location. The size of the program processed by the CPU was limited to the size of the memory.
Later system designs increased the size of the address field generated by the CPU in order to increase program and data storage capacity. This type of system still required a generation of the real physical address of the memory.
Some designs allowed multiple programs to exist in system memory simultaneously, requiring that two levels of addressing be maintained. These two levels were the address space of the program e.g. the physical address of the program within physical memory and the logical addressing with the program done. All logical addresses started at address zero. The addressing scheme was facilitated through the use of mapping units that resolved the address differences.
The direct addressing of memory in a multiprogram machine created a problem called "memory fragmentation." This problem was caused when programs of different sizes were being loaded, executed and deleted. As a result, gaps in memory utilization were created since a large program could not be loaded into an area vacated by a small program. The solution to the fragmentation problem was an address translator which converted the CPU-generated addresses into "memory addresses." In this process, referred to as "memory mapping," the CPU generates a contiguous logical memory address which is converted into a real physical memory address. Memory mapping also permits program code to be stored in physical memory locations that are not contiguous.
Recent developments in CPU technology permit execution cycles which exceed the speed of memory cycles. This was achieved by the implementation of special high speed static RAMs (Random Access Memories) located adjacent to the CPU. These RAMs (called "cache memory") duplicated portions of the contents of main memory, but were smaller in storage capacity due to both their smaller physical size and their high cost. Cache memory allowed the CPU to execute at speeds faster than the main memory cycle time when the referenced instruction or operand was located in the cache memory. The cache memory is typically addressed with a physical address which has been translated by a memory map unit. The data referenced by the physical address is supplied by the cache when the block of memory containing that data is present in cache however, the address is rerouted to the main memory for fulfillment when that data is not present. When using cache memory, the same address will describe two separate physical locations in duplicated memory blocks, one in cache and one in main memory. In this case, the faster memory (cache) determines if the slower memory (main) is to be accessed. However, when cache memory is shared by several processors, the advantages of caching shared memory regions ordinarily is lost.
Another recent addressing technique permits the program(s) being executed to be larger than available memory. This technique employs a "virtual memory" and can be viewed as utilizing main memory as a cache memory for the system disk. Using a virtual memory, the program size can exceed the size of the main memory since only a portion of the executing program physically resides in main memory. In addition, multiple programs whose total size exceeds main memory capacity can be executed concurrently since only a small portion of each executing program is resident in the main memory at any given instant Operationally, the memory addresses may be grouped into "pages" of N bytes and assigned for program usage by the operating system software. The CPU generates logical addresses which are mapped into main memory physical addresses and used to access the content of main memory for program execution. However, when the virtual address circuitry detects a fault (i.e.. the CPU generated logical address is not contained in a valid page located in main memory), the logical address is converted into a disk address, and a page that contains the referenced address is loaded into main memory for program execution. Current virtual memory machines are implemented using memory mapping and cache designs for efficient use of memory.
A detailed explanation of current memory address structures is provided in "Computer Storage Systems & Technology", Richard E. Matick, 1977 and in the "Encyclopedia of Computer Science and Engineering", Anthony Ralston, Editor, 1983.
The information path employed in the system architecture also is relevant to the efficient use of memory. For example IEEE standard P1014 teaches the use of multiple paths between functional units through its definition of the VMEbus, the VSB sub-bus, and the VMS serial sub-bus.
The Motorola VMEbus Products Selector Guide 1988 (BR606/D). lists a model MVME 132DOF processor module as containing both a VME and a VSB bus interface. The Guide also lists memories which are dual ported between the VME and VSB buses (e.g., MVME224-2 Dual Ported Memory) These products embody the use of the VME bus as a transmit/write or receive/read bus and the VSB bus as a receive/read bus. The selection of a particular bus for a given communication is performed by bits external to a 32 bit address field. These additional bits enable the same physical address to select different paths to a common data location. Two dual ported memories are used, each operating in a slave mode with the same physical address, and are connected in common to a VME bus and are connected to separate VSB buses. This bus and memory structure demonstrates the use of a single write function for storing information into two physical locations which have two separate read paths.
Another example of a single transmit/write function selecting multiple duplicated locations is the system developed by the Gould Computer Systems Division and marketed as "Reflective Memory". This system defines a memory address "block" with a starting address and an ending address. The block encompasses all inclusive addresses and may reside in one of several dual-ported system memories. Transmit/write transactions to this address space are routed to a secondary bus that is connected to all participating functional units through one of the two ports for each memory. The port interface has the capability to convert the secondary bus address to a different address for an address block in the functional unit memories through a set of physical jumpers which perform a one-to-one conversion based on the placement of the jumpers. A start jumper and an end jumper define the boundaries for addresses in each block of memory.
All of the described prior art memory schemes, including those that employ both a VME and VSB bus with dual-ported memories concern computing systems in which plural functional units are connected by common bus structures that operate to transmit values using a transaction process. Such busses have several lines dedicated to the transmission of an address field and other lines dedicated to the transmission of data. The address information generated by CPU's in the system identifies local logical addresses and system physical addresses that have a predefined static relationship to system memories having a static configuration. The system memory may be a remote resource that is shared among several other functional units. However, the system memory is not dynamically configurable in such a way as to allow allocation of memory capacity to individual units based on need. No means of communicating the information needed to perform the requisite memory allocation and commitment at the start of each task is available, because a bus employing a transaction process cannot support the underlying communication. Memory allocations in such architectures necessarily are fixed, although the mechanical allocation of memory can occur through the use of jumpers. Accordingly, those prior art memory structures are ineffective in providing efficient use of global or shared memories in a multicomputer environment.
A unique bus structure that permits the use of both a transaction process and a message process is disclosed in U.S. patent application Ser. No. 07/232,155, filed Aug. 15, 1988 and entitled "Broadcast Bus with Multi-Level Arbitration" (Parrish et al), whose teachings are incorporated herein by reference. The bus' dual mode design supports point-to-point and point-to-multipoint transactions (the latter permits a single transmit/write to several physical locations). The message process permits the sharing of control information (e.g.. parameters) among two or more functional units such information being useable for several operational purposes, including the dynamic configuration of memory. The unique arbitration scheme described in that application assures the priority transmission of single cycle unmasked requests and the effective transmission of multiple cycle masked requests that may control the configuration process. The disclosed bus architecture is particularly useful in supporting a high-speed, multicomputer, multiprocessor or network interconnect systems having a distributed processing capability.
A primary object of the present invention is to provide a memory structure which supports a high speed multicomputer, multiprocessor or network interconnect system with distributed computational capabilities.
A further object of the present invention is to provide a memory structure which supports a multicomputer, multiprocessor or network system capable of being used on diverse applications.
A further object of the present invention is to provide a reliable high speed memory structure for storing and retrieving bi-directional communications in a common address space environment.
A further object of the present invention is to provide a method for the transfer of information between two or more functional units connected to a secondary bus.
A further object of the present invention is to provide a method for cache memory to be used on shared information, i.e.. to cache any data in distributed memory space.
A further object of the present invention is to support a memory structure which will allow multiple functional units to operate on a common body of data.
A further object of the present invention is to support a memory structure that will allow memory to be dynamically allocated as a system resource.
USPTO Backgrounds
USPTO Backgrounds