The present invention relates to an image display apparatus, and more particularly, to a light emission type image display apparatus suitable for displaying an image using current driven display elements, specifically, organic light emitting diodes (LED).
An organic EL-based flat image display apparatus has been known as one type of image display apparatus. This type of image display apparatus employs a driving method using low temperature polysilicon TFTs (thin film transistors) in order to implement a high luminance active matrix display, for example, as described in SID 99 technical digest, pages 372-375. For employing this driving method, the image display apparatus takes a pixel structure in which scanning wires, signal wires, EL power supply wires and capacitance reference voltage wires are intersected with one another, and has a signal voltage holding circuit formed of an n-type scanning TFT and a storage capacitor for driving each EL. A signal voltage held in the holding circuit is applied to a gate of a p-channel driving TFT arranged in a pixel to control the conductance of a main circuit of the driving TFT, i.e., the resistance value between its source and drain. In this structure, the main circuit of the driving TFT and an organic EL element are connected in series with each other from an EL power supply wire, and also connected to an LED common wire.
For driving a pixel configured as described above, a pixel selection pulse is applied from an associated scanning wire to write a signal voltage into the storage capacitor through a scanning TFT for holding the signal voltage. The held signal voltage is applied to the driving TFT as a gate voltage to control a drain current in accordance with the conductance of the driving TFT determined from a source voltage connected to a power supply wire, and a drain voltage. As a result, a driving current of the EL element is controlled to control a display luminance. In this event, in the pixel, a source electrode of the driving transistor is connected to the power supply wire, which causes a voltage drop. The driving transistor has a drain electrode connected to one end of the organic LED element, the other end of which is connected to a common electrode shared by all pixels. The driving transistor is applied with the signal voltage at its gate, such that the operating point of the transistor is controlled by a differential voltage between the signal voltage and source voltage to realize a gradation display.
However, when the foregoing configuration is applied to implement a large-sized panel, voltages for driving pixels in a central region of the panel are lower than voltages for driving pixels in a peripheral region of the panel. Specifically, the organic LED element is current driven, so that if a current is supplied to a pixel in a central region of the panel from a power supply through a LED common wire, a voltage drop is caused by the wire resistance, thereby reducing the voltage for driving the pixel in the central region of the panel. Since this voltage drop is affected by the length of the wire and a display state of pixels connected to the wire, the voltage drop also varies depending on displayed contents.
Further, the operating point of a driving transistor for a pixel largely varies in response to a varying source voltage of the driving transistor connected to the LED common wire, so that a current for driving LEDs largely varies. The variations in current cause variations in the luminance of display, i.e., uneven display and non-uniform luminance, as well as cause a defective display in the form of non-uniform color balance in the screen when a color display is concerned.
To solve these problems, JP-A-2001-100655, for example, has proposed an improvement on a voltage drop caused by a wire by reducing a wiring resistance. In a system described in JP-A-2001-100655, a conductive light shielding film having an opening for each pixel is disposed over the entire surface of a panel and connected to a common power supply wire to reduce the wire resistance and accordingly improve the uniformity of display.
However, in the system described in JP-A-2001-100655, since a source electrode, acting as a reference voltage for a transistor for driving an organic LED in a pixel is connected to an LED common electrode shared by the panel, some voltage drop is produced between the source electrode and common electrode. For this reason, even if the same signal voltage is applied, the gate-source voltage, which determines the operating point of the transistor, varies in response to variations in the source voltage, thereby encountering difficulties in removing the non-uniformity of display.
Also, the foregoing system has such a nature that variations in a threshold value, i.e., the on-resistance of a driving TFT for driving an EL cause a change in an EL driving current even if the same signal voltage is applied for controlling the current, so that TFTs which exhibit few variations and uniform characteristics are required for implementing the system. However, transistors for use in realizing such a driving circuit are obliged to be low temperature polysilicon TFTs which are manufactured using a laser anneal process and are high in mobility and applicable to a large-sized substrate. However, the low temperature polysilicon TFTs are known to suffer quite a few variations in element characteristics. Thus, due to the variations in the characteristics of TFTs used in an organic EL driving circuit, the luminance varies pixel by pixel, even if the same signal voltage is applied, so that the low temperature polysilicon TFT is not suitable for displaying a highly accurate gradation image.
As a driving method for solving the foregoing problems, JP-A-10-232649, for example, proposes a driving method for providing a gradation display which divides a one-frame time into eight sub-frames which are different in display time, and changes a light emitting time within the one-frame time to control an average luminance. This driving method drives a pixel to display digital binary values representing a lit and an unlit state to eliminate the need for using the operating point near a threshold value at which variations in the characteristics of TFTs are notably reflected to a display, thereby making it possible to reduce variations in luminance.
Any of the foregoing prior art techniques does not sufficiently consider the non-uniformity in luminance due to a voltage drop on a power supply wire of organic LEDs, and fails to solve a degraded image quality due to the voltage drop on the power supply wire, particularly in a large-sized panel.
In addition, the prior art techniques may reduce the conductance of the transistors to set a high LED power supply voltage for preventing a varying voltage on the LED common wire, thereby reducing variations in luminance. However, this leads to a lower power efficiency and increased power consumption of a resulting image display apparatus. Also, since a transistor presenting a low conductance has a longer gate length, the transistor has a larger size which is a disadvantage in regard to the trend of higher definition.
It is an object of the present invention to provide an image display apparatus which is capable of suppressing a degraded image quality even if a voltage drop is caused by a power supply wire.
To solve the foregoing problems, the present invention provides an image display apparatus which includes a plurality of scanning wires distributively arranged in an image display region for transmitting a scanning signal, a plurality of signal wires arranged to intersect with the plurality of scanning wires in the image display region for transmitting a signal voltage, a plurality of current driven electro-optical display elements each arranged in a pixel region surrounded by each of the scanning wires and each of the signal wires and connected to a common power supply, a plurality of driving elements each connected in series with each of the electro-optical display elements, connected to the common power supply, and applied with a bias voltage to drive each of the electro-optical display elements for display, and a plurality of memory control circuits each for holding the signal voltage in response to the scanning signal to control driving of each of the driving elements based on the held signal voltage, wherein each of the memory control circuit samples and holds the signal voltage while blocking a bias voltage from being applied to each of the driving elements, and subsequently applies each of the driving elements with the held signal voltage as the bias voltage.
For implementing the image display apparatus, the plurality of memory control circuits may be configured to have the following functions.
(1) Each memory control circuit samples and holds the signal voltage while blocking a connection with each of the driving elements, and subsequently releases the blocked state to apply each of the driving elements with the held signal voltage as the bias voltage.
(2) Each memory control circuit executes a sampling operation for sampling the signal voltage in response to the scanning signal and holding the sampled signal voltage, a floating operation, following the sampling operation, for holding the signal voltage in an electrically insulated state from each of the signal wires and driving elements, and a bias voltage applying operation, following the floating operation, for applying each of the driving elements with the held signal voltage as a bias voltage.
For implementing each of the image display apparatus, the following elements may be added.
(1) Each of the memory control circuits includes a main sampling switch element responsive to the scanning signal to conduct for sampling the signal voltage, a sampling capacitor for holding the signal voltage sampled by the main sampling switch element, an auxiliary sampling switch element responsive to the scanning signal to conduct for connecting one end of the sampling capacitor to a common electrode, a main driving switch element connected to the one end of the sampling capacitor and to one bias voltage applying electrode of the driving element, and conducting when the polarity of the scanning signal is inverted, and an auxiliary driving switch element connected to the other end of the sampling capacitor and to the other bias voltage applying electrode of the driving element, and conducting when the polarity of the scanning signal is inverted.
(2) Each of the driving elements includes a p-type thin film transistor, each of the main sampling switch elements and auxiliary sampling switch elements includes an n-type thin film transistor, and each of the main driving switch elements and auxiliary driving switch elements includes a p-type thin film transistor.
(3) A plurality of inverted scanning wires are each arranged in parallel with each of the scanning wires for transmitting an inverted scanning signal having a polarity opposite to that of the scanning signal. Each of the memory control circuits includes a main sampling switch element responsive to the scanning signal to conduct for sampling the signal voltage, a sampling capacitor for holding the signal voltage sampled by the main sampling switch element, an auxiliary sampling switch element responsive to the scanning signal to conduct for connecting one end of the sampling capacitor to a common electrode, a main driving switch element connected to the one end of the sampling capacitor and to one bias voltage applying electrode of the driving element, and responsive to the inverted scanning signal to conduct, and an auxiliary driving switch element connected to the other end of the sampling capacitor and to the other bias voltage applying electrode of the driving element, and responsive to the inverted scanning signal to conduct.
(4) Each of the driving elements includes an n-type thin film transistor, each of the main sampling switch elements and auxiliary sampling switch elements includes an n-type thin film transistor, and each of the main driving switch elements and auxiliary driving switch elements includes an n-type thin film transistor.
(5) A plurality of inverted scanning wires are each arranged in parallel with each of the scanning wires for transmitting an inverted scanning signal having a polarity opposite to that of the scanning signal. Each of the memory control circuits includes a main sampling switch element responsive to the scanning signal to conduct for sampling the signal voltage, a sampling capacitor for holding the signal voltage sampled by the main sampling switch element, an auxiliary sampling switch element responsive to the scanning signal to conduct for connecting one end of the sampling capacitor to a common electrode, and a main driving switch element connected to the one end of the sampling capacitor and to one bias voltage applying electrode of the driving element, and responsive to the inverted scanning signal to conduct. Each of the sampling capacitors has the other end connected to the other bias voltage applying electrode of each of the driving elements.
(6) Each of the driving elements includes an n-type thin film transistor, each of the main sampling switch elements and auxiliary sampling switch elements includes an n-type thin film transistor, and each of the main driving switch elements and auxiliary driving switch elements includes an n-type thin film transistor.
According to the foregoing configurations, for writing a signal voltage from the signal wire into a pixel in each pixel region, the signal voltage is sampled and held while a bias voltage is blocked from being applied to each driving element, and the held signal voltage is then applied to the driving element as a bias voltage, so that after a sampling operation for sampling the signal voltage, the signal voltage is held in a floating state, in which the sampling capacitor is electrically insulated from the signal wire and driving element, and the held signal voltage is subsequently applied to the driving element as a bias voltage. Thus, the held signal voltage can be applied as it is to the driving element as the bias voltage without being affected by a voltage drop, if any, on a power supply wire connected to the driving element, thereby making it possible to drive the driving element for providing a display at a specified display luminance, and accordingly to display an image of high quality. As a result, an image can be displayed in a high quality even when the image is displayed on a large-sized panel.
Also, since a good image can be displayed without increasing the power supply voltage or using low conductance transistors, a high definition image can be displayed with low power consumption.
The present invention also provides an image display apparatus which includes a plurality of scanning wires distributively arranged in an image display region for transmitting a scanning signal, a plurality of signal wires arranged to intersect with the plurality of scanning wires in the image display region for transmitting a signal voltage, a plurality of memory circuits each arranged in a pixel region surrounded by each of the scanning wires and each of the signal wires for holding the signal voltage in response to the scanning signal, a plurality of current driven electro-optical display elements each arranged in each of the pixel regions and connected to a common power supply, and a plurality of driving elements each connected in series with each of the electro-optical display elements, connected to the common power supply, and applied with a bias voltage to drive each of the electro-optical display elements for display. Each of the memory circuits includes a sampling switch element responsive to the scanning signal to conduct for sampling the signal voltage, and a sampling capacitor for holding a signal voltage sampled by the sampling switch element. Each of the sampling capacitors has one end connected to the common power supply through each of the driving elements or a power supply wire, and the other end connected to a gate electrode of each of the driving elements. In a sampling period in which the sampling switch element of each of the memory circuits holds the signal voltage, each of the driving elements is brought into a non-driving state by changing a voltage of the common power supply or maintaining a potential on a common electrode shared by the driving elements in the common power supply at a ground potential. Each of the driving elements is applied with a bias voltage after the sampling period has passed.
For implementing the foregoing image display apparatus, a plurality of power supply control elements may be provided for controlling electric power supplied from the common power supply to each of the driving elements. Each of the power supply control elements and memory circuits may be configured to have the following functions.
(1) Each of the memory circuits may include a sampling switch element responsive to the scanning signal to conduct for sampling the signal voltage, and a sampling capacitor for holding a signal voltage sampled by the sampling switch element, wherein each of the sampling capacitors has one end connected to the common power supply through each driving element or a power supply wire, and each of the sampling capacitors has the other end connected to a gate electrode of each driving element. In a sampling period in which the sampling switch element of each memory circuit holds the signal voltage, each of the power control element stops supplying the electric power to each of the driving elements, and supplies the electric power to each driving element after the sampling period has passed.
For implementing each of the foregoing image display apparatuses, the following elements may be added.
(1) Each of the sampling switch elements, driving elements and power control elements may include an n-type thin film transistor, and each of the power supply control elements may be responsive to a reference control signal to conduct when the reference control signal changes to a high level in a period out of the sampling period.
(2) Each of the sampling switch elements and driving elements may include an n-type thin film transistor, and each of the power supply control elements may include a p-type thin film transistor, and be responsive to the scanning signal to conduct when the scanning signal changes to a low level in a period out of the sampling period.
(3) Each of the sampling switch elements, driving elements and power supply control elements may include an p-type thin film transistor, and each of the power supply control elements may be responsive to a reference control signal to conduct when the reference control signal changes to a low level in a period out of the sampling period.
(4) The plurality of current driven electro-optical display elements may include organic LEDs, respectively.
According to the foregoing configurations, for writing a signal voltage from the signal wire into a pixel in each pixel region, in a sampling period in which a signal voltage is held in the sampling switch element, a voltage of a common power supply is changed or a potential on a common electrode shared by the driving elements of the common power supply is held substantially at a ground potential to bring one line or all of driving elements into a non-driving state. After the sampling period has passed, each of the driving elements is applied with a bias voltage. Alternatively, in the sampling period in which a signal voltage is held in the sampling switch element, the power supplied to each driving element is stopped, and after the sampling period has passed, each driving element is supplied with the power, so that a bias voltage to each driving element can be substantially the same bias voltage as a signal voltage applied to sampling capacitance for all the driving element considering ground voltage as the substantial reference. It is therefore possible to display an image of high quality on a large sized panel even if a power supply voltage varies, or a voltage drop for each pixel is caused by a power supply wire.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds