The present disclosure relates to a semiconductor memory device. More particularly, the present disclosure relates to a skew signal generator capable of generating a skew signal from a fuse signal that is set according to skew states of a wafer such that the skew signal can be used for determining a delay interval of a delay circuit included in a semiconductor memory device.
As a semiconductor device is gradually scaled down, property variation in performance of a transistor is increased according to a skew and the temperature. This is because it is difficult to control a process and a device variable determining the properties of a transistor as a semiconductor device is gradually scaled down. For example, a manufacturing process and a device variable may comprise the width and length of a transistor gate, the thickness of a gate oxide, a sheet resistance and the like. As such variables have lower target values, errors in the target value are increased in respective processes. Thus, property variation in performance of a transistor is increased.
A skew is classified into SLOW, TYPICAL and FAST. The SLOW denotes a state in which a transistor has a low current driving force, and the FAST denotes a state in which a transistor has a high current driving force. The TYPICAL denotes a state in which a transistor has a current driving force higher than that in the SLOW, and has a current driving force lower than that in the FAST. It is preferred to design a circuit in a semiconductor device such that the circuit can operate regardless of property variation in performance of a transistor caused by such a skew.
FIG. 1 is a block diagram illustrating a Vref generating unit 1 according to the prior art.
As illustrated in FIG. 1, the Vref generating unit 1 is connected to external voltage terminals VDDs through a plurality of fuses F1 to FN to adjust the level of reference voltage Vref. That is, the Vref generating unit 1 receives external voltage through the N external voltage supply terminals VDDs to generate the reference voltage Vref. The number of the external voltage supply terminals VDDs is adjusted by cutting a part of the fuses F1 to FN, so that the driving force of the Vref generating unit 1 can be adjusted. Whether to cut the fuses F1 to FN is adjusted by a skew. For example, when a skew is determined as SLOW according to a test result of a wafer, voltage is sufficiently supplied to the Vref generating unit 1 without cutting all the fuses F1 to FN because transistors included in the Vref generating unit 1 have a low current driving force. Further, when the skew is determined as FAST, external voltage supplied to the Vref generating unit 1 is decreased by partially or completely cutting the fuses F1 to FN because transistors included in the Vref generating unit 1 have a high current driving force. As described above, the level of the reference voltage Vref is adjusted according to whether to cut the fuses F1 to FN, so that the reference voltage Vref having a predetermined level can be generated regardless of the skew.
In general, an internal circuit of a semiconductor memory device is designed without paying thoughtful attention to the skew. That is, if a wafer is output, product development parts test the wafer under various conditions to determine the skew, and adjust the level of an output signal output from the internal circuit by cutting fuses based on information regarding the determined skew.
However, since cutting the fuses according to the skew is individually performed relative to respective internal circuits, limitations exist in applying skew property to all internal circuits.
USPTO Backgrounds
USPTO Backgrounds