1. Field of the Invention
The invention generally relates to integrated circuit chips and corresponding methods and devices, and in particular to interfaces that can be used to place requests that require responses.
2. Description of the Related Art
Integrated circuit chips are often used for data processing and are known to comprise a number of different circuit units. Generally, each circuit unit is for performing a specific function and of course, there may be different circuit units provided on one chip for performing the same function, or performing different functions. The circuit units may operate sequentially in time or simultaneously, and they may function independently from each other, or dependent on the operation of other circuit units.
In the latter case, the circuit units are usually interconnected via an interface to allow the circuit units to interchange data needed for making the operation of one circuit unit dependent on the operation of the other circuit unit. The data exchange is often done by sending transactions from one circuit unit to the other circuit unit. A transaction is a sequence of packets that are exchanged between the circuit units and that result in a transfer of information. The circuit unit initiating a transaction is called the source (or master), and the circuit unit that ultimately services the transaction on behalf of the source is called target. It is to be noted that there may also be intermediary units between the source and the target.
Transactions may be used to place a request, or to respond to a received request. Taking the requests, there may be distinguished posted request from non-posted requests, dependent on whether the request requires a response. Specifically, a non-posted request is a request that requires a response while a posted request does not require a response.
When focusing on the functions which are performed by the interconnected circuit units, the circuit units can often be divided into hosts and devices. The term host then means a circuit unit that provides services to the dependent device. A transaction from the host to the device is said to be downstream while a transaction in the other direction is said to be upstream. In bi-directional configurations, both the host and the device may send and receive requests and responses so that a device may be source as well as target, and also the host may function as source as well as device.
A field where such integrated circuit chips are widely used are personal computers. Referring to FIG. 1, the hardware components of a common motherboard layout are depicted. It is to be noted that this figures shows only one example of a motherboard layout, and other configurations exist as well. The basic elements found on the motherboard of FIG. 1 may include the CPU (Central Processing Unit) 100, a northbridge 105, a southbridge 110, and system memory 115.
The northbridge 105 is usually a single chip in a core-logic chipset that connects the processor 100 to the system memory 115 and, e.g., to the AGP (Accelerated Graphic Port) and PCI (Peripheral Component Interface) buses. The PCI bus is commonly used in personal computers for providing a data path between the processor 100 and peripheral devices like video cards, sound cards, network interface cards and modems. The AGP bus is a high-speed graphic expansion bus that directly connects the display adapter and system memory 115. AGP operates independently of the PCI bus. It is to be noted that other motherboard layouts exist that have no northbridge in it, or that have a northbridge without AGP or PCI options.
The southbridge 110 is usually the chip in a system core-logic chipset that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus, controls a USB (Universal Serial Bus) bus that provides plug-and-play support, controls a PCI-ISA (Industry Standard Architecture) bridge, manages the keyboard/mouse controller, provides power management features, and controls other peripherals.
Thus, common personal computers include southbridges 110 which are southbridge 110 and the northbridge 105 are interconnected by the PCI bus acting as system bus so that the northbridge 105 works as host-to-PCI bridge forming a link between the host bus that connects to the processor 100, and the PCI bus whereas the southbridge 110 works as, e.g., PCI-to-ISA bus where the ISA (Industry Standard Architecture) bus is the I/O bus. However, other chipset arrangements exist in which the northbridge 105 operates as memory controller hub and the southbridge 110 as I/O controller hub. In such structures, the northbridge 105 and the southbridge 110 are no longer interconnected by a system bus but by a specific hub interface.
To satisfy the demands for high-speed chip-to-chip communication in such hub interfaces, the HyperTransportTM technology was developed which provides a high-speed, high-performance point-to-point on-board link for interconnecting integrated circuits on a motherboard. It can be significantly faster than a PCI bus for an equivalent number of pins. The HyperTransport technology is designed to provide significantly more bandwidth than current technologies, to use low-latency responses, to provide low pin count, to be compatible with legacy computer buses, to be extensible to new system network architecture buses, to be transparent to operating systems, and to offer little impact on peripheral drivers.
In particular in systems where a high-speed communication is made possible by interfaces such as those according to the HyperTransport technology, a problem may arise when driving low-speed devices. For instance, it may be the task of a HyperTransport-to-PCI bridge to interconnect a PCI compliant interface and a HyperTransport compliant interface. The PCI compliant interface is a low-speed interface that may be blocked by individual PCI devices. Whenever a PCI device places a request, it may assert a request signal on a specific signal line. The HyperTransport-to-PCI bridge will then send a respective request upstream. If the request requires a response, the response data will arrive at the bridge and will be sent to the PCI device. The PCI device then deasserts the request signal when it receives the response.
In such systems, there can be no other request placed in PCI interface unless the response is delivered to the requesting PCI device. That is, the PCI device blocks the PCI interface so that no data transfer takes place in the time between placing the request and sending back the response. Moreover, even the high-speed upstream interface is blocked with respect to any data traffic relating to PCI devices since there can be no PCI related data traffic in the HyperTransport link before receiving the response. This is disadvantageous since the high-speed capabilities of the upstream interface cannot be used efficiently.
USPTO Backgrounds
USPTO Backgrounds