1. Technical Field
Embodiments of the present invention are related to the field of electronic devices, and in particular, to scan cells.
2. Description of Related Art
A typical integrated circuit (IC) chip has combination logic circuits which are coupled by flip-flops or latches controlled by a plurality of clock signals, with the combination logic circuits and latches utilizing a particular clock signal defining one of a plurality of functional clock domains. For example, in one illustrative IC chip, there are more than 30 different internal functional clock domains with frequency ranging from 1 KHz to 312 MHz.
Referring to FIG. 1, Design-For-Testability (DFT) mechanisms for an IC chip 10 include utilizing a plurality of scan cells 12 to perform manufacturing tests on the IC chip 10. In one scan cell design, sometimes referred to as a “mux flip-flop”, each scan cell 12 has a flip-flop 14, such as a D-flip-flop, and a multiplexer 16. Each scan cell 12 has a normal mode of operation and scan mode of operation, which is selected by the select signal SE coupled to the multiplexers 16. During the normal mode, data signals D are provided from the multiplexers 16 to the flip-flops 14 and during the scan mode, a test pattern or scan-in signal SI is provided from the multiplexers 16 to the flip-flops 14. In this simplified example, four flip-flops 14A, 14B, 14C, and 14D are illustrated.
During the scan mode, well-known sequential-test problems may be avoided by turning flip-flops 14 of a Device-Under-Test (DUT) at input and output nodes of combination logic circuits 18 into externally loadable and readable elements. These flip-flops 14 are chained together as a single serial shift register to form a scan chain 20, with an output SO of one flip-flop 14 being coupled to an input SI of the next flip-flip 14. With respect to a given combination logic circuit 18, a portion of a serial data of an appropriate the scan-in signal SI, in the form of a test pattern or vector, is loaded into flip-flop 14 at an input node to set it to a predetermined state. The combination logic circuit 18 then functions in a normal manner, with the test pattern being launched from the flip-flop 14 at the first node to propagate through the logic circuit 18 so as to generate a system response. The system response to the test pattern is latched by the flip-flop 14 at an output node on the other side of the logic circuit 18 and then is shifted out of the DUT in a scan-out operation and analyzed for improper operation.
During the normal mode, each functional clock domain has its own system clock, as illustrated by a simplified example having two clock domains 22 and 24 with system clocks CLK1 and CLK2, respectively, coupled to the flip-flops 14. The two clocks have a different frequency and the interface between the two clock domains 22 and 24 defines a clock crossing 26. The flip-flops 14 in the first clock domain 22 are labeled “F1” and in the second clock domain 24 are labeled “F2”. During a normal mode of operation, the data signal D is passed along via the flip-flops 14, which are synchronized using system clocks CLK1 and CLK2. During the scan mode, the test pattern is shifted in and the system response is shifted out using scan clocks CLKT1 and CLKT2 in the clock domains 22 and 24, which are driven from different external scan clock input pins (not shown). In one embodiment, the systems clocks are frozen during the scan-in and scan-out operations which use the scan clocks. In one prior art implementation, the scan clock CLKT1 may be driven by a Power Management Unit (PMU) and the scan clock CLKT2 may be driven by another scan clock pin, although the paths for the system and scan clocks are coupled together as shown in FIG. 1. Between these operations, the flip-flops 14 apply the test pattern to the input of the corresponding combination logic circuit 18 on a first pulse of the system clocks. Then the flip-flops 14 capture or latch the system response from the combination logic circuits 18 on a second pulse of the system clocks.
The scan clocks CLKT1 and CLKT2 are “in-phase” at the scan clock input pins, but by the time they arrive at the flip-flops 14, there may be clock skew. This clock skew is caused by the scan clocks CLKT1 and CLKT2 propagating by different clock distribution paths having different propagation delays. To compensate for the clock skew at the interface of the two clock domains 22 and 24, a lockup latch (LU) 28 is interposed into the scan chain 20 between at SO output of one flip-flop 14 and the SI input of the next flip-flop 14 at the clock crossing 26. During scan data shifting, the lockup latch 28 holds the data from the flip-flop 14B for a half clock cycle before it propagates to the next flip-flop 14C. With respect to flip-flops 14B and 14C, when both are positive edge-triggered flips or both are negative edge-triggered flip-flops, then the lockup latch 28 is interposed between them, with the scan clocks being in-phase. Referring to FIG. 2, the solid arrows illustrate the triggering edges of the scan clocks CLKT1 and CLKT2 for two positive edge-triggered flip-flops and the dashed arrows illustrates the triggering edges of the scan clocks CLKT1 and CLKT2 for two negative edge-triggered flip-flops. In FIG. 2 the scan clocks are “in-phase” with an original clock (not shown). When one clock domain has positive edge-triggered flip-flops and the other clock domain has negative edge-triggered flip-flop, the negative edge-triggered flip-flops are placed first in the scan chain (become flip-flops F1) followed by the positive edge-triggered flip-flops (become flip-flops F2) and the lockup latch 28 is not used.
With more than 30 different internal clock domains with frequency ranging from 1 KHz to 312 MHz in the illustrative chip 10, it is a challenge to test all the scan chains 20 that reside in so many different clock domains with these varying clock frequencies and complex clock tree structures, all of which need careful scan timing balancing. Presently, this challenge is addressed by providing extra external scan clock inputs to drive the clock distribution networks (not shown) to the scan cells 12, which may increase the total scan pin count and pattern size or/and may add large numbers of buffers to balance the clock distribution networks. This in turn may increase DFT implementation overhead and may increase die and testing costs.
USPTO Backgrounds
USPTO Backgrounds