The present invention relates to integrated circuits and to processes for fabrication of integrated circuits.
In a wide variety of integrated circuit processes, a contact etch step is necessary. For example, polysilicon-gate MOS transistors, separated by field oxide regions, would be covered up by a planarizing insulator or "MLO" layer, which could be any one of a number of dielectrics, such as BPSG (borophosphosilicate glass), OCD (spin-on silicate glass), PSG (phosphosilicate glass), or TEOS oxide (silicon oxides vapor deposited from a tetraethylorthosilane gas flow). To usefully interconnect the poly-gate active devices, it is necessary to cut through the MLO to make contact to selected locations in the polysilicon gate level and to selected locations in the source/drain diffusions of the MOS transistors. The contact holes thus opened will be interconnected by a patterned layer of a conductor such as aluminum to configure the desired electric circuit.
Each contact will impose a series resistance in the circuits which include it, and excessive series resistance in the contacts may cause the circuits to be slow or defunct. This danger of excessive contact resistance imposes processing constraints on the contact etch. First, the contact hole must be cleared: if the bottom of the hole is partly covered by remnants of the MLO or by residues from etching the MLO, the electrically effective area of the contact will be reduced, and, for a given specific contact resistance, the series resistance through the contact will obviously increase. Second, the silicon exposed at the bottom of the contact hole should not be damaged too much by overetching: if silicon at the bottom of some contact holes is exposed to a prolonged overetch it is likely to be pitted, even if the etch is nominally selective to silicon. Moreover, during prolonged overetching it is also possible to redeposit on the exposed silicon small quantities of dielectric which have been sputtered off of the contact hole's sidewalls. Third, no etch is infinitely selective, and, if the overetching period is very much prolonged, even a reasonably selective etch may erode enough silicon from the exposed areas to cause problems (such as excessive spreading resistance under the contact, or even cutting right through the source/drain junctions to short-circuit to the substrate). This is a particular problem where siliciding is used (as is now common), since a substantial fraction of the silicide layer over the poly gate level or over the source/drain regions may be removed by prolonged overetching.
Obtaining a reliable contact etch process has been a major problem in fabricating VLSI circuits. Processing control of this step is impeded by three sources of difficulty: (1) the plasma etch rate in small openings is inherently uncertain, (2) the contact etch must cut through various MLO thicknesses across the wafer, and (3) normal endpoint detection techniques do not work, so overetch must be added onto an endpoint estimated (imprecisely) by timing, rather than onto a measured endpoint, so the additional overetch must be used to allow for this imprecision. For all these reasons, substantial overetch (i.e. etching for more than the time required to clear from a flat surface the thickness of MLO which overlies the contact hole location) is necessary to assure that the contact is clear.
Normal endpoint detection techniques are of no use in contact etching, simply because of insufficient signal due to small total area exposed to plasma. The oxide thickness left in the bottom of contact holes cannot be detected by instruments such as Nanospace (.TM.), because the holes are much smaller than the minimum size (of detection) for Nanospace. In general, there is no efficient way to tell whether the contacts (in integrated circuits using micron dimensions) are clear and without oxide resistance.
Engineer inspection of the results of a contact etching step is also not easy because of the limitations of inspection tools. Contact resistance is very sensitive to the residual oxide in the contact. Resistance can increase several orders of magnitude even when the oxide thickness is only a few nanometers. However, no commercially available equipment can detect this residual oxide layer in a micron-sized contact. Microscopes (such as an SEM) may provide the contact profiles, but cannot resolve oxide layers which may be only a few nanometers thick. Nanospec machines (.TM.) and ellipsometers are commonly used in the industry to measure thin oxide thickness, yet they cannot pinpoint the characteristics of a small geometry such as the contact holes.
Another reason why substantial overetch is normally necessary is because of the variation of plasma etch rate in small areas. Plasma etching rates tend to be reduced when the geometry of the openings is small, due to gas transfer rate limitations, and therefore the etch rate will be pattern-dependent. (This becomes even more of a problem when very steep-walled contact holes are used, as is increasingly preferable.) As a result, a substantial amount of overetching (typically up to about 70%) is needed to assure that the contact is clear.
The amount of required overetching is further increased by the thickness variation of the MLO layer. The variation not only comes from the nature of deposition, but also because of the steps (such as poly gate) created in structures which are later smoothed out by oxide planarization for metal step coverage and lithography purposes. That is, the MLO layer preferably has a nearly flat surface, but the structure is covers is not flat, and therefore the MLO layer is thicker in some places than in others. This thickness variation can easily be as much as 5000 A. When a single contact etch is used to make the contacts both to source/drain and to gate, as is usual, the gate contact holes will be greatly overetched by the time the source/drain contact holes are cleared. FIG. 1 shows a sample prior art structure illustrating this: the contact etch, which cuts through MLO layer 16, must simultaneously etch through a thickness t1 to permit contact to the source/drain diffusions 13, while etching through only thickness t2 over the poly gate 15. Moreover, the contact etch should preferably not etch through the silicide layers 11, and certainly not through the source/drain junctions 10. This can be a particular problem at the edge of field oxide 17, where implantation of the source/drain diffusion 13 may have been partially masked by the edge of the field oxide 13 and/or partially counterdoped by the channel stop doping under the field oxide. Thus, if the contact hole mask slightly overlaps the edge of the field oxide 17, as it easily may, it is particularly easy for overetching to cut through diffusion 13 and short-circuit to substrate.
The overetching of contacts can result in an excessive loss of the underlying layers. This is a very serious problem since the "crater" formed in silicon source/drain areas may cause a short circuit between the junction and the substrate after the metal is deposited. This mischance becomes more likely as the junction depth is scaled down, which is to be expected as VLSI gets more compact. Furthermore, if silicide is used to reduce series resistance in both gate and source/drain regions, the chances of etching through this silicide layer (which might be, for example, 1000 Angstroms thick) are even higher. This is likely to cause excessive spreading resistance around the contact and degrade circuit performance.
Thus, the prior art presents the crucial problem that, for various reasons, a tremendous amount of overetching is normally needed when etching contact holes, but this overetching degrades the underlying circuit elements.
The present invention solves these shortcomings of the prior art, and also provides other advantages, by providing a reliable contact etch process which is more tolerant to overetching. One basic idea of the present invention is to transfer the etch nonuniformity to a conformal (not planar) intermediate layer which serves as an etch stop.
In one class of embodiments of the present invention, a conductive layer is used as the intermediate layer. This layer not only provides important processing advantages, but also can be used to provide field-plate assisted isolation over the whole integrated circuit structure. This is not lateral field-plate isolation, as is common, but vertical field-plate isolation, which reduces cross-talk between poly and metal levels, and between metal and moat. Such a global field plate also provides improved radiation hardness.
This global field-plate isolation is particularly advantageous in high-voltage circuits, where the voltage present in power lines or other metal lines may be enough to cause anomalous transistor turnon or turnoff, even through a normal thickness of PSG or other MLO dielectric intervenes.
Thus, in general, the present invention teaches a process wherein a thin dielectric interface layer, such as good quality oxide, is first conformally deposited or grown. Next, the intermediate layer (e.g. doped polysilicon) is conformally deposited. Next, the bulk of the MLO is deposited and planarized. The contact holes are patterned, e.g. with photoresist, and the MLO is etched using the required overetch, using an etch which stops on the material of the intermediate layer. The intermediate layer portions which are exposed at the bottoms of partially etched contact holes are then etched away, and a short final etch removes the thin conformal oxide layer.
Although a thin layer (or layers) of additional materials is provided underneath the planarizing MLO layer, the gettering advantages of a heavily phosphorus-doped MLO are preserved. That is, the phosphorus doping in PSG or BPSG serves to getter metal-ion contamination, but this gettering will still occur when the PSG or BPSG is separated from the underlying active device structures by 2000 Angstroms or so of oxide, polysilicon, etc.
The conformal oxide layer provides optimal interface to the active device regions, and is preferably made thick enough (e.g. 500-1500 Angstroms) to minimize charge-up. Thus, the required overetching of the MLO may damage the intermediate layer, but does not damage the underlying structures. The only overetching to which the underlying structures are exposed is the amount of overetching necessary to clear the thin conformal oxide layer which underlies the intermediate layer; however, this will be much less (typically by a factor of 10 or more) than the amount of overetching which would be required to clear the whole MLO.
Thus the present invention provides the advantage that contact holes are etched through thick MLO of varying thickness without exposing the underlying structures to extensive overetch.
A further advantage of the present invention is that it can be used in combination with a wide variety of contact etching processes. That is, various etch processes (cantilever etch mask, high pressure plasma etching, BPSG reflow, etc.) can be used to provide a controlled sidewall slope for the contact hole, and the present invention can be used in combination with most of these processes, as long as the etch used to cut through the MLO planarizing layer is selective with respect to the intermediate layer.
A further advantage of the present invention is that it does not entail much additional process complexity.
According to the present invention there is provided: A method for fabricating integrated circuits, comprising the steps of: providing a substrate having thereon a partially fabricated integrated circuit structure; providing upon said partially fabricated integrated circuit structure a conformal dielectric layer, conformally depositing over said conformal dielectric layer an intermediate layer consisting essentially of a material which can be etched selectively with respect to said conformal dielectric layer, depositing over said intermediate layer an MLO layer comprising a thick planarizing layer of a dielectric material which can be etched selectively with respect to said intermediate layer, and providing a masking layer above said MLO layer to define contact holes in predetermined locations; etching said MLO layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof, etching away said exposed portions of said intermediate layer from said bottoms of said contact holes, to expose said conformal dielectric at said bottoms of said holes, and etching away said exposed portions of said conformal dielectric from said bottoms of said holes, to expose underlying portions of said partially formed integrated circuit structures; and providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
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