1. Field of the Invention
The present invention specifically relates to an element-isolating construct of a semiconductor integrated circuit for isolating a plurality of element regions formed on a semiconductor substrate. The present invention also related to a process for manufacturing the element-isolating construct.
2. Description of the Related Art
When an integrated circuit is conventionally formed by incorporating bipolar-transistors, each of the bipolar transistors must be electrically separated to ensure a reliable operation. The electrical isolation of bipolar transistors can be attained by surrounding each of the bipolar transistors with the region doped with impurities of the opposite conductive type to those of the collector region.
Hereinbelow, we will explain a process for forming an element-isolating region, taking an NPN transistor as an example, with reference to the accompanying drawings.
First, as shown in FIG. 1, a large amount of N-type impurities is introduced into a predetermined buried collector region of a bipolar transistor provided on a P-type silicon substrate 1, forming an N+ type region 2. As the N.sup.+ type impurities, As (arsenic) or Sb (antimony) is generally introduced by means of solid-phase diffusion. After an opening having distance L1 is formed between the N.sup.+ type regions 2 of adjacent bipolar transistors, by using a resist 4, impurity ions are implanted through the opening to form a P-type region 3 responsible for isolating adjacent bipolar transistors. Then, an N-epitaxial layer 5 is grown, as shown in FIG. 2. In the epitaxial layer 5 immediately above the buried P-type region 3, a P-type region 6 is formed, as shown in FIG. 3. The isolating region of bipolar transistors is thereby accomplished.
FIG. 4 is a cross sectional view of a bipolar transistor region obtained after the construct shown in FIG. 3 is treated in subsequent processing steps, and more specifically, shows the isolation profile of adjacent bipolar transistors. As is apparent from FIG. 4, the element regions are separated by an oxide film 9. To decrease the collector resistance, a deep N-type region 7 is formed extending to the buried collector region. In a predetermined base contact region of a bipolar transistor, a P-type region 8-1 is selectively formed by ion implantation. Also, using ion implantation, another P-type region 8-2, shallow and lightly doped is formed extending to the P-type region 8-1. The region 8-2 acts as the base region. In the surface of the P-type base region 8-2, an N-type region 10 is formed as the emitter.
In the manufacturing process thus constituted, the temperature for epitaxial layer growth is as high as 1,000.degree. C. or more. As a result, impurities of the heavily-doped N+-type region 2 and the P-type region 3 are diffused vertically and laterally in the epitaxial layer 5. In this case, if the offset distance L2 (indicated in FIG. 1) between the buried N.sup.+ type region 2 and P-type region 3 is designed to be shorter than the sum of the distances of impurity laterally diffused from the regions 2 and 3, the region 2 will be in contact with the region 3 as shown in FIG. 2.
In practice, the impurities in the buried P-type region 3 are tend to be diffused easier than those in the buried N.sup.+ type region 2. Since the impurity concentration of the P-type region 3 is generally higher than that of the substrate 1, if the buried layers 2 and 3 come in contact with each other, capacitive coupling of the N.sup.+ type region 2 will be increased. In other words, a collector/substrate capacitance of a transistor will be larger.
However, to ensure a high-speed operation of a bipolar transistor, it is important to reduce the collector/substrate capacitance. Therefore, each of the impurity concentrations of the N+-type region 2 and P-type region 3 must be maintained as low as possible. To satisfy the requirement, it is considered that the P+ type region 3 is formed at a certain distance (offset distance) apart from the N.sup.+ type region 2 sufficiently to avoid the contact of both regions even if heating is applied thereto during epitaxial growth. In this method, however, the offset distance L2 will be inevitably long, offering a disadvantage to high integration of the semiconductor circuit.
To suppress the lateral diffusion, it is conceivable that the epitaxial growth is carried out at reduced temperature. However, if the temperature is reduced during the epitaxial growth, the quality of the epitaxial layer 5 and the epitaxial growth rate will decrease, resulting in a low productivity. It is also conceivable that the impurity concentration of the P-type region 3 is reduced. However, to ensure reliability, the impurity concentration of the P-type region 3 and the isolation distance L3 (indicated in FIG. 3) must be inversely proportional. Therefore, in the case where the impurity concentration of the P-type region 3 is reduced, the isolation distance L3 must be increased, making it difficult to attain the high integration density.
In the case where an element isolating construct is formed in accordance with any one of manufacturing processes mentioned above, it is impossible to form a semiconductor circuit having a reduced distance between adjacent transistors and a low collector/substrate capacitance.
As an alternative way to reduce the isolation distance between the adjacent bipolar transistors, a trench as deep as 4-6 .mu.m may be employed. Since adjacent transistors are physically isolated in the trench isolation method, the buried P-type region 3 is not required. The deep-trench isolation technique is employed usually in very high-speed bipolar transistor integrated circuits. The adjacent bipolar transistors are isolated by a trench which is deeper than the buried P-type region 3. If such a trench isolation construct is applied to the semiconductor circuit, it will be possible to reduce isolation distance L3 (shown in FIG. 3) and lower the collector/substrate capacitance, realizing the semiconductor circuit with high performance. However, the trench isolation has the following disadvantages: (1) manufacturing process is complicated and (2) another method such as a shallow trench isolation or a LOCOS process must be used together in the case where a wide element-isolating region is formed. Many steps are therefore required to manufacture the semiconductor circuit, increasing a manufacturing cost.
As mentioned above, it has been hitherto impossible to construct a semiconductor circuit having a reduced isolation distance between transistors and a low collector/substrate capacitance, without an increase in manufacturing steps and cost.
USPTO Backgrounds
USPTO Backgrounds