FinFET source/drain regions are made by growing epitaxial material on portions of fin structures, extending beyond the gate structures. The size of these epitaxial regions is critical for optimization of yield and performance. At present, physical analysis is required to track the nature of this growth for feedback to process control. This physical analysis includes destructive testing.
By way of example, it is known that growing epitaxial material on fin structures is much more difficult than in planar applications. For example, planar fabrication processes include filling a defined cavity. In these fabrication processes, overfill is the main concern which is very controllable. Also, there is a relatively defined relationship between planar SIMS pad and nominal device fill height which can be used as a monitor. Fin geometry shape, on the other hand, is very poorly related to SIMS pad monitor and the relationship varies strongly with Ge % and B %, fin pitch, etc. The only dependable way to characterize the process variations, e.g., epitaxial size, is through a cross section of the structure using destructive testing.
USPTO Backgrounds
USPTO Backgrounds