In the design of a clock-distribution network, or “clock tree,” for an integrated circuit (IC) such as application specific integrated circuit (ASIC) or a Programmable Logic Device (PLD) some of the major considerations are skew, jitter, delay, duty cycle distortion and power consumption. Various clock tree geometries such as the balanced tree (e.g., the H clock tree) and grid have been used. The H clock tree, in some cases, can provide low clock skew.
In addition to clock tree geometry, a clock tree may be differential, i.e., provide a differential clock signal using differential circuits, or may be single-ended, i.e., a single clock signal using the conventional Complementary Metal Oxide Semiconductor (CMOS) circuits. A single-ended clock tree is typically noisy and prone to duty cycle distortion at high frequencies, but has only dynamic power consumption. On the other hand, while a differential clock tree has good noise immunity and low duty cycle distortion, it consumes static power due to a common mode.
Traditionally, a PLD has used a single ended clock tree. A PLD, for example, a Field Programmable Gate Array (FPGA) such as the Virtex™-II from Xilinx Inc. of San Jose, Calif, receives a single ended clock or differential signal via the ring of IOBs on the perimeter of the FPGA and transfers this clock signal to configurable logic blocks (CLBs) via the single ended clock tree.
As clock speeds for ICs increase, there is a need for a low noise clock such as a differential clock; however, the single ended clock still has advantages, such as lower static power consumption. Therefore, there is a need for a better clock-distribution network for ICs and in particular PLDs that better balances low noise and low power consumption.
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