1. Field of the Invention
The present invention relates generally to the handling of semiconductor devices during processing. More particularly, the present invention relates to a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to allow testing the dice with standard contact technology. The present invention further relates to materials and methods for temporarily attaching the dice to the die carrier.
2. State of the Art
In semiconductor manufacturing, it is highly desirable to test semiconductor devices for functionality prior to packaging or mounting of the devices to higher-level assemblies. By doing so, defective devices can be identified and eliminated without unnecessarily providing them with further processing.
A common method for testing semiconductor devices during processing comprises forming temporary electrical connections to the device I/O elements with pin-type contact probes. Probe testing has been conventionally carried out, for example, while a plurality of semiconductor devices are still contained within a wafer. With this process, a matrix of contact probes carried by a test contactor substrate is forced against the I/O elements (e.g., bond pads or conductive bumps) of the semiconductor devices in the wafer, and a brief test is conducted to determine the functionality of each device. The wafer is subsequently singulated to provide individual semiconductor dice. Any dice containing nonfunctional integrated circuits are scrapped, routed for rework if possible, or binned into a category not requiring full functionality for less demanding applications. The remaining dice are passed on to further processing for packaging or attaching the dice to higher-level assemblies. By using this method, semiconductor devices may be tested without substantially slowing down the manufacturing process.
Probe testing of semiconductor devices at the wafer level, however, is typically capable of providing only a minimal measure of functionality and does not ensure that the devices will operate suitably after final processing in die form. Further, defective devices may induce undetectable failures in adjacent devices by testing them while coexistent on a wafer, or devices may be damaged during wafer singulation. Accordingly, the dice must be tested again after being packaged or otherwise incorporated into higher-level assemblies. Processing unusable semiconductor dice to this point, only to scrap them after testing, results in a waste of production time and materials. Furthermore, as semiconductor device geometries shrink, the I/O elements of a die become more difficult to contact and test due to tighter alignment tolerances and the need to use smaller, more fragile contact probes.
In order to address the problems associated with testing semiconductor devices at the wafer level, manufacturers have developed methods for testing of individual, unpackaged semiconductor dice. The methods often employ temporary die carriers to hold one or more individual dice and prevent damage during testing. A prior art die carrier typically comprises a base portion with a cavity for housing a die and providing an electrical connection to external test circuitry. A die is placed in the cavity circuit side down, and the die I/O elements are biased against an array of interconnects in communication with conductive elements on the exterior of the carrier. The interconnects may take the form of bumps, pins or simple pads forming a land-grid array (LGA), depending on whether the die I/O elements are bond pads, or include structures such as conductive bumps added for subsequent flip-chip or TAB (tape-automated-bonding) type circuit connection. Biasing the I/O elements against the interconnects is achieved through the use of lids, clips or springs that are attached to the base portion and press on the die. Once the die is secured, the carrier is pressed into a test socket to connect the carrier conductive elements to the external test circuitry.
Prior art die carriers of the type discussed above are disclosed in U.S. Pat. No. 5,367,253 to Wood et al., U.S. Pat. No. 5,517,125 to Posedel et al., U.S. Pat. No. 5,767,689 to Tokuno et al. and U.S. Pat. No. 6,278,286 to Farnworth et al. Although these die carriers overcome some of the problems associated with testing at the wafer level, they raise other issues which are undesirable in the context of semiconductor processing. Due to their complex structure, existing die carriers may be expensive to fabricate and include features susceptible to damage during use. Interconnects in the form of bumps or pins, for instance, may be damaged or worn down by repetitive biasing against die I/O elements, especially when the interconnects are of a small size suitable for interfacing with very fine pitch I/O elements. Likewise, the carrier conductive elements, which may comprise pins or lead-like structures, may be damaged during insertion into a test socket and do not offer the efficiency of probe-type testing. Furthermore, the lids, clips and springs used to press on a die add cumbersome manual operations to the manufacturing process.
In view of the present state of the art, there exists a need for a die carrier having a durable, yet simple construction and that uses an improved method for temporarily attaching one or more semiconductor dice to its interconnects.
USPTO Backgrounds
USPTO Backgrounds