Along the trend of multifunction and miniaturization of various electronic devices, a semiconductor device such as an integrated circuit device having a multilayer structure may be provided in an electronic device. Such a multilayer semiconductor device may have a plurality of circuit devices and structured having a small size with an increased integration density of a semiconductor device is increasing. For example, there are proposed a high-integration semiconductor device having a structure of stacking and fixing LSI chips having a through electrode over a plurality of layers and a three-dimensional (3D) semiconductor device having a structure of stacking a plurality of semiconductor substrates having integrated circuits.
As one of key technologies for realizing compact, light and thin electronic equipment, various packaging technologies have been developed in the semiconductor devices to realize high density mounting of semiconductor chips. As a technology related to a package structure of semiconductor devices for reducing an area required for mounting the semiconductor devices on a mother board, there have been developed a pin insertion-type package such as a dual inline package (DIP), a surface mount package such as a small outline package (SOP) by a peripheral lead, and a package having external output terminals in a grid shape on the lower surface of the package such as a ball grid array (BGA). Furthermore, as a technology for realizing high density mounting by reducing an area ratio of a package to semiconductor chips, the pitch of the external output terminals becomes small and the reduction in the size of the package become promoted according to miniaturization of lines of the substrate.
A technology of a multichip package for mounting a plurality of semiconductor chips in a single package has been developed. In the multichip package, a technology of a chip stacked package for stacking a plurality of semiconductor chips has been developed in order to realize higher density mounting. Furthermore, a multichip package systematized by sealing a plurality of semiconductor chips having different functions in a single package is referred to as a system-in-package (SIP) and the development of the SIP has been conducted.
Meanwhile, a separate method from high-density packaging and mounting of semiconductor chips has been given attention as a method for realizing compact, light and thin electronic equipment. The separate method employs a system-on-chip (SOC) such that memory, logic and analog circuits and the like, which are different semiconductor chips, are mixedly loaded to integrate system functions in a single chip.
However, in a case of integrating memory, logic circuits and the like in a single chip, it is difficult to obtain a low-voltage memory circuit, and thus, necessary to control noise generated in the logic circuit. Further, in a case of mixedly loading a bipolar analog circuit, it is difficult to manufacture the analog circuit in a CMOS circuit equal to memory and logic circuits. Accordingly, instead of the SOC, an SIP capable of being developed for a short period of time at low cost to have the same functions as the system on chip has been given attention.
As a technology required to manufacture 3D multilayer LSI and SIP, there is a technology for forming a through electrode in a semiconductor substrate. A current process for forming a through electrode in a silicon (Si) wafer still has many process steps. Moreover, there is difficulty in forming a through electrode having a large depth. A through electrode capable of connecting devices should be formed to package various devices into one body. In order to form the through electrode, metal is filled in the through hole formed by etching in the previous step to form a conductor through which electricity flows. The SIP includes a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. As a total thickness of the multilayer semiconductor device having a plurality of layers, the through hole has a very large depth compared to an opening area. Accordingly, there is a problem that it is difficult to closely form a through electrode by filling tungsten in a through hole by a general chemical vapor deposition (CVD) process.
USPTO Backgrounds
USPTO Backgrounds