The present invention relates to a selector circuit employed in a semiconductor integrated circuit device and, more particularly, to a selector circuit employed in a semiconductor memory device having a power circuit responding to an external power supply voltage applied to the device and generating an internal power voltage lower than the external power supply voltage.
The increase in memory capacity of a semiconductor memory device has been accelerated more and more. In accordance with the increase in the memory capacity, an internal circuit of the memory deice is required to operate on a voltage lower than an external power supply voltage applied to the device in order to lower power consumption and enhance reliability thereof. For this purpose, the recent memory device incorporates therein a power circuit which responds to the external power supply voltage and generates an internal power voltage lower than the external power supply voltage.
The power circuit incorporated into the memory device is in turn required to generate the internal power voltage stabilized against the variation of the external power supply voltage. For this purpose, the power circuit includes a reference voltage generator generating a reference voltage by utilizing threshold voltages of MOS transistors. Although the threshold voltage of the MOS transistor is stabilized against the variation of the external power supply voltage, it is influenced by the manufacturing process of the transistor and thus deviated from the designed value. Accordingly, the power circuit further includes a voltage regulator coupled to the reference voltage generator to regulate the reference voltage therefrom.
Referring to FIG. 1, a reference voltage generator 40 according to the prior art employed in a power circuit of a memory device includes a reference circuit 39 and a voltage regulator 30. The reference circuit 39 generates a reference voltage by utilizing the threshold voltages of MOS transistors (not shown), as described above, and supplies it to an input node 32 of the regulator 30 which includes an operational amplifier 31, a P-channel MOS transistor Q5 and resistors R2 and R3 connected as shown. As each of the resistors R2 and R3 is denoted as a variable resistor in FIG. 1, accordingly, a regulated reference voltage is derived from an output node 33 of the regulator 30 by adjusting the resistance values of the resistors R2 and/or R3.
It is of course impossible to form the variable resistor on the semiconductor chip. Accordingly, each of the resistors R2 and R3 is in fact constructed by a plurality of unit resistors and fuses each connected in parallel to an associated one of the unit resistors. The selected one or ones of the fuses are blown to adjust the resistance value of each of the resistors R2 and R3. Blowing a fuse is carried out by a raiser trimming apparatus, as is well known in the art. In order to select the fuses to be blown and determine the number thereof, the voltage from the output node 33 is required to be measured. For this purpose, the generator 40 further includes a voltage measurement circuit 38. This circuit 38 includes a comparator 35 having a non-inverting input terminal connected to the output node 33 of the regulator 30, an inverting input terminal connected to a terminal pad P1 and an output terminal connected to another terminal pad P2, each of pads P1 and P2 being formed on the semiconductor chip. The comparator 35 is activated in a test mode. In the test mode, accordingly, the pad P1 is supplied with a variable reference test voltage from a test apparatus. The potential level of the test voltage applied to the Pad P1, at which the level at the pad P2 is inverted from the high level to the low level, represents the reference voltage which is not yet properly regulated. From that potential level, the deviation from the desired potential level of the reference voltage is obtained. One or more fuses are then blown by the trimming apparatus by use of the deviation thus obtained. The voltage regulator 30 thus generates the regulated and desired reference voltage at the output node 33 in a normal operation mode.
As is well known in the art, the memory device includes in general a memory cell array having a plurality of memory cells and further includes a redundant memory cell array including a plurality of redundant memory cells for defective memory cells. The defective memory cell or cells in the memory cell array are thus replaced with one or more redundant memory cells in the redundant memory cell array. Specifically, when a set of address signals designating the defective memory cell is supplied to the device, the redundant memory cell array is selected in place of the memory cell array having the defective memory cell, and data is written into or read form the selected redundant memory cell. In order to replace the defective memory cell with the redundant memory cell, the address designating the defective memory cell has to be memorized. For this purpose, a fuse circuit is employed to memorize that address, as is also well known in the art. The fuse circuit includes a plurality of fuses, and selected one or ones thereof are blown by the trimming apparatus to store the defective address.
Thus, it is required to blow the selected fuse or fuses in the voltage regulator 30 as well as those in the fuse circuit for the defective address. It is needless to say that it is desirable to blow all the selected fuses at one time. However, it is impossible for the memory device having the reference voltage generator 40 to do that. Blowing the selected fuses in the regulator 30 and blowing those in the fuse circuit for the defective address has to be done in separated steps.
Specifically, the defective memory cell or cells are detected under the condition of supplying the desired internal power voltage to the memory cells. In order to supply the desired internal power voltage, the regulated reference voltage is required. For this reason, the selected fuses in the regulator 30 is first blown to generate the regulated reference voltage. As a result, the selected fuses for memorizing the defective address is blown after blowing the fuse or fuses in the regulator 30.
Therefore, it has been proposed to connect the terminal pad P1 directly to the output node 33 of the regulator 30, as shown in FIG. 2. In this circuit, the reference voltage at the output node 33 is first measured from the pad P1 to detect the deviation from the desired potential level and the desired reference voltage is then supplied from the pad P1 to the output node 33 to bring the memory cell array into a condition of receiving a desired internal power voltage to detect the defective cell or cells. The information necessary to blow fuses to be blown is thus derived, so that all the selected fuses can be blown at one time.
However, the voltage regulator 30 has a very high output impedance, as is apparent from the circuit construction thereof. For this reason, the potential level at the pad P1 easily fluctuates even by slight noises. The accurate potential level at the pad P1 is thus not derived. Moreover, the test apparatus is required to measure the potential level at the pad P1 and then supply the desired reference potential level to the pad P1. That is, the test apparatus needs two functions different from each other for the same pad P1. The cost of the test apparatus is thereby increased accordingly.
USPTO Backgrounds
USPTO Backgrounds