1. Technical Field
The inventive concept relates to a semiconductor integrated device, and more particularly, to an access device, a method of fabricating the same, and a semiconductor memory device having the same.
2. Related Art
Recently, resistive memory devices have received attention as nonvolatile memory devices that can replace flash memories. Typical resistive memory devices may include phase-change RAMs (PCRAMs) or resistive RAMs (ReRAMs) memory devices and may have a structure that selects an individual memory cell using an access device, such as a cell switching device.
With high integration of memory devices, a size of the access device is reduced and thus, resistances of a word line and a bit line and resistance of the access device itself are increased to cause shortage of an operation current. Therefore, an access device with high performance and high integration is needed.
In the conventional art, a MOS transistor or bipolar transistor may be used as the access device. However, a vertical diode is mainly used as the access device to meet high integration.
In the general PCRAMs, a word line is formed of an N+ type junction region that is used as one electrode of the diode and a single crystalline silicon region is formed on the word line by a selective epitaxial growth method that is used as the other electrode of the diode. However, with a reduction in size of the semiconductor memory device, resistance in the word line using the N+ type junction region is increased and a characteristic of the diode may be degraded. To solve this problem, a word line contact is formed in units of predetermined cells to reduce the resistance of the word line, but the word line contact hinders high integration.
A structure, in which a word line is formed of a metal layer and a polysilicon diode is formed on the metal layer, has been studied using an improved method.
FIG. 1 is a view showing a structure of a conventional access device and shows an example of a polysilicon diode.
An access device 100 illustrated in FIG. 1 includes a first-type semiconductor layer 101, a second-type semiconductor layer 103, and a third-type semiconductor layer 105. Here, the first-type semiconductor layer 101 may be an N+ type ion doped region and the second-type semiconductor layer 103 may be a P+ type ion doped region. The third-type semiconductor layer 105 may be a high resistance region, for example, an intrinsic semiconductor layer. Further, a heat treatment is performed to activate dopants after the second-type semiconductor layer 103 is formed.
Conventionally, a process of patterning the layers into a pillar-type has to be performed. However, the diode may collapse during an etching process or a cleaning process due to a high aspect ratio, thus reducing the yield. The aspect ratio has to be reduced to prevent the collapse of the diode and thus, a height of the polysilicon layer serving as the diode has to be lowered.
Referring to FIG. 1, ions doped into the first-type semiconductor layer 101 and the second-type semiconductor layer 103 are diffused into the third-type semiconductor layer 105 in a subsequent heat treatment process. It can be seen from the dopant diffusion profile that the first-type ions are deeply diffused into the third-type semiconductor layer 105, as shown by profile B1 and that the second-type ions are deeply diffused into the third-type semiconductor layer 105, as shown by profile A1.
An off-current characteristic of the diode tends to improve as the height of the third-type semiconductor layer 105 increases. However, when the dopants are deeply diffused, above a preset depth, from the first-type and the second-type semiconductor layers 101 and 103 into the third-type semiconductor layer 105, the actual height of the third-type semiconductor layer 105 is reduced not to ensure a desired diode characteristic.
Therefore, in the current PIN diode, the third-type semiconductor layer has to be formed to have a sufficient height and thus, the total height of the diode 100 is increases and the yield is degrades due to a collapse of the diode in a subsequent process.
However, when the height of the polysilicon layer is lowered to solve the issue of the high aspect ratio of the diode, the dopants may be diffused passing through the third-type semiconductor layer 105 due to a thermal effect caused in a subsequent process and the current leakage characteristic in a reverse bias may be degraded. Therefore, when the height of the diode is reduced, a concentration of the dopant injected to the diode has to be maintained blow a predetermined level to suppress the dopant diffusion due to the thermal effect in a subsequent process.
When the concentration of the dopant injected into the diode is low, an on-current characteristic of the diode may be degraded and a reliability of the access device may be affected.
USPTO Backgrounds
USPTO Backgrounds