The present invention relates generally to a semiconductor memory device, and more particularly, to a technology of removing parasitic coupling capacitance generated between word lines.
Recently, a vertical type cell transistor has been introduced to correspond to trend of technology miniaturization. When the vertical type cell transistor is used, the capacitance between word lines is increased resulting in defects in cell operation. The operation defects increase as the miniaturization of technology continues.
A cell transistor of over 100 nm has been used as a planar gate. In the cell transistor of over 100 nm operation of gate does not cause a fail in an adjacent gate. However, operation of an adjacent gate results in a fail in a conventional cell transistor of less than 100 nm using a recess gate.
The fail generated by the operation of an adjacent gate in the cell transistor of less than 100 nm using a recess gate can be sensed in a wafer level test. The frequency of the fail discussed above increases as the miniaturization of technology continues.
As the capacity and level of integration of semiconductor memory continue to increase, efforts to reduce chip size have also continued. Therefore, it is desirable to increase the number of net dies that can be produced in one wafer thereby improving cost competitiveness.
As such, it is important to develop a process technique and reduce the circuit critical dimension for this technology. Reduction of the critical dimension rapidly decreases the interval between signal lines. Capacitance between two conductive materials is inversely proportional to the interval, and therefore a reduction in the interval between signal lines results in an increase in the parasitic coupling capacitance between signals.
FIG. 1 is a diagram showing word line arrangement of a conventional semiconductor memory device. As shown in the FIG. 1, eight neighboring word lines are driven.
In general, a bank of a DRAM includes a cell mat, which is a group of cells for storing data of one bit. The whole capacity of a memory is determined depending on the arrangement and number of cell mats. The number of word lines and bit lines is determined by the whole capacity of memory.
The bank includes a plurality of sub word line driving units SWLD0˜SWLD7 for driving sub word lines SWL0˜SWL7. The sub word line driving units SWLD0_0˜SWLD7_0 are connected to a main word line MWLB0. The sub word line driving units SWLD0_1˜SWLD7_1 are connected to a main word line MWLB1.
The sub word line driving units SWLD0, SWLD2, SWLD4, and SWLD6 are arranged in an even column of the sub word line driving units SWLD0_0˜SWLD7_0 and are driven by word line driving signals FX0, FX2, FX4, and FX6. The sub word line driving units SWLD1, SWLD3, SWLD5, and SWLD7 are arranged in an odd column of the sub word line driving units SWLD0_0˜SWLD7_0 and are driven by word line driving signals FX1, FX3, FX5, and FX7.
The sub word lines SWL are driven in every active and precharge memory operation and are arranged in a narrow space in a cell mat. Due to this space restriction, coupling capacitance causes word lines to be inactivated by the activated neighboring word lines.
FIG. 2 is a circuit diagram illustrating the sub word line driving unit SWLD of FIG. 1.
The sub word line driving unit SWLD includes a PMOS transistor P1 and NMOS transistors N1, N2.
The PMOS transistor P1 is connected between a word line driving signal FX terminal and the sub word line SWL, and a gate of the PMOS transistor P1 is connected to the main word line MWLB. The NMOS transistor N1 is connected between the sub word line SWL and a ground voltage terminal, and a gate of the NMOS transistor N1 is connected to the main word line MWLB.
The NMOS transistor N2 is connected to the sub word line SWL and the ground voltage terminal, and a gate of the NMOS transistor N2 receives a word line driving signal FXB. The word line driving signal FXB is an inverted signal of the word line driving signal FX.
The PMOS transistor P1 and the NMOS transistor N1 have a common gate to receive a main word line MWLB signal having the same level. When the main word line MWLB signal is enabled to a low level, the PMOS transistor P1 is turned on. One sub word line SWL is activated according to the level of the word line driving signal FX, which is applied to the source of the PMOS transistor P1.
The adjacent word lines connected to the same main word line MWLB in the sub word line driving circuit increase a level of the sub word line by coupling capacitance. That is, when the PMOS transistor P1 is turned on in response to the main word line MWLB signal, a coupling capacitance is generated by the inactivation of the word line driving signal FX.
When one sub word line SWL is selected by the word line driving signal FX, the coupling capacitance affects a non-selected sub word line SWL in response to the main word line MWLB signal, enabled to the low level, because of the restricted space.
As a result, an undesired level increase may occur in a sub word line which should be inactivated. In this case, the amount of charges for preventing leakage current and securing data accuracy may be lost.
USPTO Backgrounds
USPTO Backgrounds