Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a column bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
For some applications, flash memory uses a single bit per cell. Each cell is characterized by a specific threshold voltage, which is sometimes referred to herein as a Vt level. Within each cell, two or more possible Vt levels exist. These Vt levels are controlled by the amount of charge that is stored on the floating gate. For some NAND architectures, for example, a memory cell might have a Vt level greater than zero in a programmed (or logic zero) state and a Vt level less than zero in an erase state. As used herein, a program Vt refers to a Vt level of a memory cell in a programmed state, and an erase Vt refers to a Vt level of a memory cell in an erase state.
Memory cells are typically programmed using program/erase cycles, e.g., where such a cycle might involve first erasing a memory cell and then programming the memory cell. For a NAND array, a block of memory cells is typically erased by grounding all of the word lines in the block and applying an erase voltage to a semiconductor substrate on which the memory cells are formed, and thus to the channels of the memory cells, to remove the charge from the floating gates. More specifically, the charge is removed through Fowler-Nordheim tunneling of electrons from the floating gate to the channel, resulting in an erase Vt typically less than zero.
Programming typically involves applying a programming voltage to one or more selected word lines and thus to the control gate of each memory cell in communication with (e.g., electrically coupled to) the one or more selected word lines, regardless of whether a memory cell is targeted or untargeted for programming. While the programming voltage is applied to the one or more selected word lines, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, to charge the floating gates. More specifically, the floating gates are charged through Fowler-Nordheim tunneling of electrons from the channel to the floating gate, resulting in a program Vt typically greater than zero.
For the reasons stated herein, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative program and erase schemes.
USPTO Backgrounds
USPTO Backgrounds