1. Field of the Invention
This invention relates to an emitter-coupled logic (ECL) circuit device provided in an integrated circuit semiconductor device. More specifically, the invention relates to the improvement of a high-speed ECL circuit which uses bipolar transistors.
2. Description of the Related Art
In recent years, high speed performances of an ECL circuit provided in an integrated circuit semiconductor device have been rapidly developed by scaling.
In order to increase the cut-off frequency of transistor and to efficiently decrease the delay time t.sub.pd of an ECL Circuit, it has been important subjects to improve self-alignment techniques enabling the forming of a shallow emitter/base region as well as optimization in transistor fabrication and ECL circuit design in accordance with the scaling.
When designing an ECL circuit, the common emitter current gain h.sub.FE is considered to be a very important parameter since it determines the operating point of the ECL circuit.
Two types of transistors are used for an ECL circuit, namely, transistors which constitute a current switch and a transistor which constitutes emitter follower. Research concerning how to use these two transistor types have been conducted from the view point of current distribution by considering total power dissipations (refer to, for example, The Transactions of The Institute of Electronics, Information and Communication Engineers '86/6 Vol. J69-C No. 6). However, as far as common emitter current gain and emitter area are concerned, usually a completely identical common emitter current gain and emitter area are used for these transistors. Especially, the common emitter current gain h.sub.FE is generally set to be 100 as its central value, although no clear reasons were provided to set the common emitter current gain h.sub.FE to this value.
In order to increase the operating speed of an ECL circuit, it is required to decrease the base transit time of the carrier, the parasitic capacitance and the parasitic resistance in the transistors constituting the ECL circuit.
It has been found that it is not always possible to minimize the delay time by setting the emitter areas of the current switch transistors and the emitter follower transistor to be identical, since the contributions of the emitter/base junction capacitance to the delay in the current switch stage and to the delay in the emitter follower stage are different.
Furthermore, it has been known from the studies using simulation that there exits a limit for the reduction of the delay time in conventional ECL circuits with h.sub.FE =100 and with a constant emitter area when devices are further reduced in size.
As described above, in conventional ECL circuits the emitter area of the current switch transistors and the emitter follower transistor is set to be completely identical. However, using transistors with a completely identical emitter area is an obstruction to achieve the high speed operation of the ECL circuit since the contributions of the emitter/base junction capacitance to the delay time of current switch transistors and emitter follower transistor are different.
Also, in conventional ECL circuits the common emitter current gain of the current switch transistors and the emitter follower transistor is set to be completely identical. However, using transistors with a completely identical common emitter current gain is an obstruction to achieve the high-speed operation of the ECL circuit since the contributions of the emitter base junction capacitance to the delay time of current switch transistors and the emitter follower transistor are different.
USPTO Backgrounds
USPTO Backgrounds