1. Field of the Invention
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.
The problem of soft errors generated by single event transients (and single event upsets) is expected to increase drastically in ultra-deep submicron (.ltoreq.90 nm) technologies. Of particular significance is that logic circuits are expected to become much more sensitive to radiation generated soft-errors and possibly surpass memory as the major source of single event errors. Furthermore, the generation rate of multiple errors, multiple bit upsets (MBU), single-event multiple upset (SEMU) increases.
The main reason for this is that, with a higher feature integration and higher frequencies, the spatial distribution and pulse length of a single event transient (SET) becomes relatively larger, increasing the probability that an SET pulse is latched-in as a (soft-) error, or that SET pulses are generated simultaneously on several circuit nodes by one single event.
The problem with increasing soft-error rates is further complicated by the escalating cost of semiconductor design and manufacturing. The high cost involved in developing and maintaining a semiconductor FAB makes it highly desirable to use standard commercial semiconductor manufacturing also for applications that require a high radiation tolerance. Hence, there is a strong drive to develop efficient and robust radhard-by-design (RHBD) techniques for these applications.
Furthermore, the design process is also becoming very complex and expensive, and it would be highly desirable to be able to re-use standard design IP and libraries as much as possible for radhard applications.
2. Prior Art
Current radhard-by-design technology for single event errors include triplication (triple mode redundancy, TMR) or duplication (e.g., built-in soft-error resilience, BiSER). These circuits carry two or more redundant copies of a signal, and use some form of voting, or filtering, circuitry to determine the correct signal among the redundant signals. Filtering preventing a signal to pass in the case that one of the redundant signals is wrong (by comparing the value of the redundant signals), and voting circuits selects the correct signal from the majority among several (3 or more) redundant signals.
These techniques generate undesirable power and area overhead, and current versions of these techniques cannot handle MBUs or SEMUs. Error correction codes, ECC, for memory, which also (loosely) could be classified as RHBD, is more efficient than duplication/triplication and can, with additional overhead, handle multiple errors in memory circuitry. However, the application of a corresponding error correction to logic circuits is very limited and application specific (e.g., selective parity check or insertion of specialized checking circuit IP).
State-of-the art for layout techniques for soft-error hard design mainly consist of simple spacing and sizing, and in adding additional contacts.
USPTO Backgrounds
USPTO Backgrounds