This disclosure relates to memory system architectures and, in particular, memory system architectures with error correction.
Memory controllers may be configured to perform error correction. For example, a memory controller may read 72 bits of data from a memory module where 64 bits are data and 8 bits are parity. The memory controller may perform other error correction techniques. Using such techniques, some errors in data read from the memory module may be identified and/or corrected. In addition, the memory controller may make information related to the errors available. A system including the memory controller may make operational decisions based on the error information, such as retiring a memory page, halting the system, or the like. Such a memory controller may be integrated with a processor. For example, Intel Xeon processors may include an integrated memory controller configured to perform error correction.
However, if error correction is performed before data is received by the memory controller, the error information related to the correction may not be available in the memory controller and hence, not available to the system for system management decisions.
USPTO Backgrounds
USPTO Backgrounds