The invention relates to microelectronic devices, and more particularly to a magnetic tunnel junction and method for patterning the same.
In a magneto-resistive random access memory (MRAM), information is stored in arrays of magnetic storage elements known as magnetic tunnel junctions (MTJs). One of the advantages of MRAM is the capability of the MTJ storage array to be placed in a level above the surface of a semiconductor substrate. In that way, the surface area of the semiconductor substrate is conserved for use by relatively few transistors used to control the MTJ array. In addition, the available substrate surface area does not constrain the density of the MRAM to the same extent as in other types of memory. MRAM technology potentially offers great benefits to the integration of processors and other system elements on a single integrated circuit (IC or “chip”), commonly referred to as “systems on a chip” (SOCs). The placement of the MTJ array in a layer above the semiconductor substrate surface increases the flexibility for fabricating the MRAM cell control transistors in the substrate. With such flexibility, MRAM cell control transistors can be fabricated using most, if not all of the same process steps as transistors used in logic circuitry, e.g. a microprocessor, of such chip.
Another advantage of MRAM compared to dynamic random access memory (DRAM) and static random access memory (SRAM), is that the stored information is non-volatile. In an MRAM, information is stored according to the orientation of magnetic dipoles within an MTJ storage element of each MRAM cell. The magnetic dipoles are re-orientable by application of a magnetic field to program the MTJ, that is, to write information to the MTJ. Once the MTJ is programmed by the magnetic field, the MTJ remains in either a first state or a second state until reprogrammed by a different magnetic field, even if power is removed from the MTJ in the meantime. An advantage of MRAM compared to other non-volatile rewriteable memory such as flash memory, is that the MTJ has longer life. Current technology suggests that MTJs are reprogrammable many billions of cycles. Flash memory, which utilizes thin dielectrics and is reprogrammed by applying relatively high voltage (10 V to 15 V) and current, typically fails within one million cycles.
A magnetic tunnel junction memory element includes a structure having ferromagnetic layers separated by a non-magnetic tunnel barrier. Digital information is stored and represented in the memory element as directions of magnetization vectors in the ferromagnetic layers. More specifically, the magnetic moment of one magnetic layer is fixed. Such layer is called the “pinned” or “reference” layer. The magnetic moment of the other magnetic layer may be switched to be either parallel or antiparallel to the pinned layer. This layer is called the “free” or “soft” layer. When the orientations in the pinned layer and the free layer are parallel, the MTJ is in a first state having a first electrical resistance. On the other hand, when the orientations in the pinned layer and the free layer are antiparallel, the MTJ is in a second state, in which its electrical resistance is significantly higher than in the first state. In general, the device state is determined by the orientation of the magnetic films in closest proximity to the tunnel barrier, even if the pinned and free layers are themselves comprised of multiple layers of materials. Such composite pinned and free layers are common, as they can enhance device operation and lifetime.
The patterning of the MTJ device is one of the most challenging aspects of fabrication. Conventional techniques used to pattern other structures of a chip, such as reactive ion etching (RIE) or ion milling, have been less than satisfactory when applied to the materials that compose magnetic stacks. In most cases utilizing such techniques, it is extremely difficult to cleanly remove etched material. Physical sputtering, often the dominant component of magnetic material RIE, usually results in the formation of re-deposited residues (called “fences” or “veils”) that can short circuit the junctions of the MTJ, as well as short circuit conductive patterns in different metal layers. Short circuiting may occur either immediately as a result of such fence residues, or after subsequent high temperature processing.
Another problem of conventional etch techniques is corrosion and degradation of the patterned free and pinned layers that form the MTJ, due to chemical residue remaining after etching. Exposure to reactive gases during deposition of dielectrics such as silicon nitride and silicon dioxide after the etching of the MTJ can also cause corrosion and degradation. For example, fluorine and/or chlorine species may be present when plasma-etching a stack of magnetic films. Chlorine and fluorine species can combine with conductive and photoresist material removed in the process to deposit a conductive residue along sidewalls of the stack. When subjected to high temperatures, the residue can migrate and cause corrosion, degradation and electrical shorting.
One way proposed for handling these problems is development of a process having better selective etch control to minimize exposure of sensitive interfaces to corrosive chemicals and conductive fences. Such etch process should have high selectivity, in order for etching to stop when the thin tunnel barrier layer of a magnetic film stack is reached. Such etch process is known as stop on alumina (SOA), named historically because many of the MTJ tunnel barriers are formed from alumina-type compounds. However, the tight process control and high selectivity required to maintain an acceptably controlled etch process across an entire wafer is difficult to achieve. Moreover, the SOA process does not necessarily protect the free layer from harmful corrosion and degradation.
Accordingly, it is desirable to provide an improved structure and method for patterning magnetic tunnel junctions of an MRAM.
USPTO Backgrounds
USPTO Backgrounds