1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having a circuit consisted of a thin film transistor (hereinafter, abbreviated as TFT), and particularly, relates to a method of forming a mask in an exposure step and a method of etching using the relevant mask.
2. Description of Related Art
In recent years, an active matrix type liquid crystal display utilizing a TFT has attracted a great deal of attention. An active matrix type liquid crystal display is provided with a TFT as a switching element at each pixel.
In general, in a TFT, a channel formation region is formed with an amorphous silicon or a polycrystalline silicon. Particularly, since a TFT using a polycrystalline silicon which is fabricated particularly at a temperature of being equal to 600° C. or less (referred to as low temperature process) (hereinafter, referred to as polycrystalline silicon TFT) is capable of being formed on a glass substrate, it becomes possible to lower the cost of a semiconductor device and make the area of it larger. Moreover, in the case of a polycrystalline silicon, since the mobility of it is large, it is possible to realize a liquid crystal display in which a pixel section and a driver are integrally formed on a glass substrate.
However, if a polycrystalline silicon TFT is continuously driven, the mobility may be changed, ON-state current (current flowing in the case where a TFT is in an ON-state) may be increased, and OFF-state current (current flowing in the case where a TFT is in an OFF-state) may be increased. It is considered that this may be caused by the deterioration due to a hot carrier occurred by a high electric field nearby a drain.
In order to relax the high electric field nearby the drain and suppress the hot carrier, in the case of a MOS transistor employing the design rule of 1.5 μm or less in a gate line width, it is useful to utilize a LDD (abbreviated from Lightly Doped Drain).
For example in the case of a NMOS (n-type MOSFET) transistor, a LDD structure can be formed by providing a low concentration n-type region (n− region) at the edge portion of the drain utilizing a side wall of the gate side wall. The electric field nearby the drain can be relaxed by employing a LDD structure in which a concentration of impurity of drain junction is made hold a gradient.
In a LDD structure, a drain breakdown voltage can be enhanced comparing to a single drain structure. However, since the resistance of the n− region is large, there is a difficulty that a drain current is reduced. Moreover, since a high electric field exists immediately under the side wall, where the ionization of collision becomes the maximum, and a hot electron is injected into a side wall, the n− region is depleted, and further the resistance is increased, and finally a TFT is made deteriorated.
Particularly, the above-described problem becomes significant according to the reduction of the length of a channel. In order to overcome this problem in the case of a MOS transistor whose design rule is 0.5 μm or less, a Gate Overlap LDD structure which forms the n− region by overlapping at the edge portion of a gate electrode is useful.
Then, the employment of a Gate Overlap LDD structure has been considered in order to relax the high electric field nearby the drain not only in a MOS transistor but also in a polycrystalline silicon TFT. As for a polycrystalline silicon TFT having a Gate Overlap LDD structure, in a polycrystalline silicon layer, a channel formation region, a source region and a drain region which are high concentration regions (n+ region), and a low concentration region (n region) which has been provided between the channel formation region and the source and drain regions and which is overlapped with a gate electrode are formed.
As a method of fabricating these structures, there have been reports described in the patent document 1, the patent document 2 and the like.    Patent document 1: Japanese Unexamined Patent Publication No.2000-349297 gazette, and    Patent document 2: Japanese Unexamined Patent Publication No. H07-202210 gazette.
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