1. Field of the Invention
The present invention relates generally to integrated circuit (IC) devices, and, more particularly, to IC device design.
2. Related Art
Traditionally, design of IC devices comprises a plurality of steps. Initially a schematic, or netlist, of elements of an IC device is generated. Subsequently, a layout scenario is determined based on the schematic. The layout scenario defines a physical representation of individual elements such as rectangles and polygons and their topology. Typically, identification of at least one satisfactory layout scenario in conformance with all constraints imposed is accomplished using complex and time consuming searches through numerous possible scenarios limited by a list of constraints impacting the physical cell level.
As complexity of integrated circuits increases and feature sizes shrink, capabilities of existing IC design systems can become a limiting factor in layouts of new integrated circuits. This is particularly true for design of analog and mixed signal IC devices, where layout is typically either performed manually or using automated layout tools. A typical automated layout tool searches through thousands, if not millions, of trial instantiations of the IC device at a basic primitive cell level in an attempt to perform a global optimization of the layout. Disadvantageously, the vast amount of searching requires significant computational resources. As complexity of IC devices to be designed and constraints imposed on their layouts evolve, it has become increasingly time consuming to identify a satisfactory and optimum layout scenario in conformance with all such constraints. Therefore, there is a need for improved systems and methods of designing integrated circuits.
USPTO Backgrounds
USPTO Backgrounds