1. Field of the Invention
This invention relates to electronic systems and more particularly relates to multiple output buffer drivers stages.
2. Description of the Related Art
An integrated circuit output buffer circuit typically charges and discharges an output impedance network that includes, for example, integrated circuit package leads and other large and small impedances connected to the leads. Rapid current changes associated with charging and discharging of the impedance network may produce power supply voltage noise when parasitic reactances and reactive loads are driven by the output buffer. This power supply voltage noise is undesirable because, if a large enough voltage swing occurs, it can be interpreted as an input signal state change by loads connected to the leads.
A network formed by the output buffer, a load connected to integrated circuit package leads, and a conductive path between the power supply voltage source and the load can be represented by an RLC equivalent circuit When driving complimentary metal oxide semiconductor (CMOS) circuitry, the inductance, L, is generally due to the inherent parasitic self inductance of the leads and conductive path. The capacitance (C) is generally due to the capacitive load of circuitry connected to the leads, and the resistance, R, is generally the resistance of the conductive path.
As loads are driven to HIGH voltages, e.g., 2-3.3 volts (V), and to LOW voltages, e.g., 0-1 V, by the output buffer, current varies over time at a rate defined by dI/dt, the derivative of output current over time. Power supply voltage noise is a function of dI/dt and the network impedance and can cause unintentional logic level changes in logic devices connected to the leads if the output buffer output voltage amplitude exceeds a logical threshold of the logic device. Power supply voltage noise may be manifested on a line supplying power to the output buffer and other circuits. The power supply line is often distributed around an integrated circuit periphery, and other circuits, such as an input buffer circuit sharing the same power line, may experience voltage instability due to the supply voltage noise. A noisy supply voltage may also cause logic shifting of data driven to a voltage level by other bus drivers sharing the same power line as the output buffer circuit causing the large dI/dt.
Conventionally, attempts have been made to reduce dI/dt by introducing resistance into the current path of a driving transistor. However, this may not sufficiently reduce dI/dt induced noise appearing on supply voltage lines, Vsso and Vcco, especially for coincident switching output buffers. Another attempted solution increases the number of power supply pins to a circuit to distribute current paths and thus reduce aggregated dI/dt. However, the number of supply pins may be constrained by, for example, a need for backwards compatibility or a need to utilize available pins for other purposes.
Accordingly, a need exists for an output buffer that sufficiently reduces dI/dt induced noise, including power supply voltage noise, in all modes of operation
USPTO Backgrounds
USPTO Backgrounds