1. Field of the Invention
This invention relates to an integrated circuit including an inverter circuit constructed by an enhancement type (E type) MOSFET and a depletion type (D type) MOSFET, and a gate-protection circuit.
2. Description of the Prior Art
An inverter circuit used in a prior art integrated circuit device is shown in FIGS. 1 and 2. As shown in FIG. 1, D type MOSFET (1) and E type MOSFET (2) are connected in series between power supply Vcc, for example 5V, and reference potential Vss, for example ground potential. The gate electrode of MOSFET (1) is connected to a connecting point of MOSFET (1) and MOSFET (2). An input signal Vin is coupled to the gate electrode of MOSFET (2), and an output signal Vout is derived from the connecting point of MOSFET (1) and MOSFET (2). MOSFET (1) operates as a load and MOSFET (2) operates as a driver. A sectional view of the inverter circuit in FIG. 1 is shown in FIG. 2. N+ diffusion regions (3), (4) and (5) are formed in P type semiconductor substrate (6). E type MOSFET (2) is constructed from N+ source region (3), N+ drain region (4) and gate electrode (7) formed on gate insulation layer (8), and D type MOSFET (1) is constructed from N+ source region (4), N+ drain region (5) and gate electrode (9) formed on gate insulation layer (10). Arsenic ion is implanted in the channel region between the N+ source and drain regions (4) and (5), and the gate electrode (9) is connected to the N+ source region (4). This inverter circuit is a ratio circuit in which logic levels of "1" and "0" are distinguished from each other by establishing appropriately the ratio EQU .alpha.=.beta.d/.beta.l (1)
of the geometrical sizes of driver MOSFET (2) and load MOSFET (1). In formula (1), .beta.d is the ratio [W/L] of channel width W and channel length L of the driver MOSFET (2), and .beta.l is the ratio of these parameters of the load MOSFET (1).
Generally the value of the ratio .alpha. is established at three to five. This value is appropriate for an inverter circuit which operates as part of a circuit constructed of MOSFETs or whose signal level fully swings from Vss to Vcc, but is not preferable where the circuit is used as an input stage. It is desirable that the value of the ratio .alpha. is established at ten to twenty for use as an input stage, for the following reason. Input signals inverters internal to the usual integrated circuit are low level of about 0 V or high level of about 5 V, Vcc, but input signals to the input stage of the integrated circuit usually have TTL (transistor-transistor-logic) levels and are low level at about 0 to 0.8 V and high level at about 2.0 V. Generally, the drain current I.sub.D of a MOSFET is defined by the following formula: EQU I.sub.D .varies.(V.sub.GS -V.sub.th).multidot.gm (2)
where,
V.sub.GS : gate-source voltage PA1 V.sub.th : threshold voltage PA1 V.sub.D : source-drain voltage PA1 gm: mutual conductance
In formula (2), V.sub.th and gm are determined by the shape of the MOSFET, gm is in proportion to W/L of the MOSFET, and V.sub.th is about -0.6 V in the usual E type MOSFET. V.sub.GS is the voltage between the gate electrode and Vss, and corresponds to the input signal Vin. From formula (2), when V.sub.GS is increased from about 2 V to about 5 V, gm will have to be decreased with the same rate in order to derive the same current, too. So, the ratio .alpha. is three to five when input signal is Vss to 5 V, as with the usual circuit, but must be ten to twenty when the input signal is Vss to 2 V as the circuit of an input stage whose input signal has TTL levels.
But, the circuit of the input stage is not always used with TTL level input signals, and can be used with input signal levels of about Vss and Vcc in several life tests and some uses. In this case, an input signal of Vcc is provided to the gate of driver MOSFET (2), and the output level of the inverter circuit becomes about the Vss level. Excessive drain current flows in the load MOSFET (1) because gm (.varies. W/L) of the MOSFET (2) is greater than that of the MOSFET (1) and Vcc is provided between the gate and drain of the load MOSFET, (1). In the event of severe use like this, the gate of the MOSFET (1) may be destroyed by noise on the Vcc terminal which occasionally includes high voltage spikes or surge voltages. This has caused destruction of integrated circuit devices and reduces reliability.
USPTO Backgrounds
USPTO Backgrounds