The present invention relates generally to a reset circuit for a central processing unit (hereinafter, "CPU"), and more particularly, to a circuit for resetting a CPU upon detecting an instable state for the purpose of stabilizing operation of a system employing the CPU.
Generally, a CPU reset circuit is comprised of a level detector and a watch-dog circuit. The level detector senses swings in the magnitude of a voltage supplied to the CPU. Also, in cases where a hardware or software error occurs, the watch-dog circuit restarts the CPU. Since a CPU is a required component in many devices, a CPU reset circuit is necessarily required in all devices using a CPU; particularly, those devices in which a high degree of reliability is required.
One prior art reference that discusses this subject is U.S. Pat. No. 5,408,648 entitled Method And Apparatus For Diagnosing CPU For CPU-Runaway-Preventing Circuit issued to Gokan et al. In Gokan et al. '648, when abnormal operation of the CPU or an abnormal reduction in voltage to the CPU is detected, the CPU is reset and reset signals for the CPU are counted. When the number of reset signals for a predetermined time satisfies specified conditions, a determination is made as to whether the CPU is in a failure state. While conventional art, such as Gokan et al. '648, possesses merit in its own right, I note that it fails to address the problem that occurs when a CPU is unable to be reset due to an inadequate duration of a reset signal.
USPTO Backgrounds
USPTO Backgrounds