Integrated circuits in general, and CMOS devices in particular, have continued to gain wide spread usage as user demands for increased functionality and enhanced benefits continue to increase. In order to meet this demand, the integrated circuit industry continues to decrease the feature size of circuit structures in order to place more circuits in the same size integrated circuit area thereby continuously increasing the packing density for a given chip size. Over the last several years, structures have evolved from 1.2 micron gate lengths (1 Mbit capacity), down to gate feature sizes of 0.25 microns (1 Gbit capacity) and less.
For example, the ever-increasing demand for computer memory to facilitate calculations and data storage has fostered intense development efforts in the area of Dynamic Random Access Memory (DRAM), and especially embedded DRAM. The DRAM is generally a collection of transistor devices with each having an integrated circuit capacitor typically connected to its source electrode thereby forming a memory cell. This collection of memory cells is then arranged into a memory structure using a word line and a bit line to address each memory cell. This integrated capacitor may store an electrical charge to represent a binary "1" or store no electrical charge for a binary "0" as instructed by the word and bit control lines.
Construction of these memory capacitors consists of using typically a tungsten, copper or aluminum electrode structure, either parallel to the wafer surface, in a trench, or as a plug for 0.25 micron technology, connected to the source of the transistor, which then supports a dielectric material, such as tantalum pentoxide (Ta.sub.2 O.sub.5), and then a top electrode, in sequence.
As the size technology of CMOS devices continues to shrink, the structure for a given memory size or circuit capability also shrinks as noted above. For example, the bond pads, which allow the integrated circuit to connect to external circuitry, cannot continue to shrink indefinitely. Currently, an integrated circuit package may have about 200 bond pads that are 50 microns by 50 microns in size. Shrinking topology coupled with this bond pad lower size limitation results in an excess of empty space around the bond pads. This allows for the inclusion of additional embedded memory around the bond pads. The use of higher dielectric constant oxides such as tantalum pentoxide as substitutes for silicon dioxide have allowed smaller structures still.
Tantalum pentoxide is an illustrative high-K (high dilectric constant) material used in integrated circuit elements such as gate and capacitor dielectrics. The dielectric is sandwiched between two electrodes to form a capacitor or between the gate and channel in a field effect device. However, there is a drawback to tantalum pentoxide used on aluminum electrodes. With time and temperature, the aluminum acts as a reducing agent to the tantalum pentoxide, forming aluminum oxide and reducing the tantalum pentoxide to tantalum suboxide, which is less of an insulator, and even to tantalum metal, which is a conductor. This conversion impairs the dielectric properties of the tantalum pentoxide and reduces the performance of any capacitors made with it due to leakage currents associated with tantalum metal shorts. The problem is particularly severe in capacitors formed on semiconductor wafers as part of an integrated circuit, because processing temperatures subsequent to dielectric deposition can approach the melting point of aluminum.
One approach to reducing the reactivity of tantalum pentoxide with aluminum is to pre-dope the tantalum pentoxide with about 1 to about 50 mole % aluminum oxide, preferably 1 to 20% mole % aluminum oxide. The presence of the reaction product, aluminum oxide, in the tantalum oxide, reduces the thermodynamic tendency for the reaction to go forward. The greater the amount of aluminum oxide, the greater the inhibition of reduction, but the lower the dielectric constant. Tantalum pentoxide is normally deposited by chemical vapor deposition at elevated temperature when making integrated circuit capacitors, and is desirably amorphous as deposited. The presence of aluminum provides a benefit to capacitors with non-aluminum electrodes in that aluminum doping increases the crystal phase transformation temperature of tantalum pentoxide from 850 to 950.degree. C., allowing for higher temperature post-processing without crystallization of the tantalum pentoxide. Tantalum pentoxide powder may also be sintered to form monolithic ceramic capacitor dielectric pieces, which then have electrodes metallized thereon.
Accordingly, it would be desirable if mixed tantalum aluminum oxide could be made in a low temperature spin-on form for use in aluminum electrode capacitors. It would also be desirable if a porous tantalum aluminum oxide could be had, since such a structure could be infiltrated with yet another high-K metal oxide precursor.
USPTO Backgrounds
USPTO Backgrounds