Comparator circuits often are implemented with hysteresis from output to input to prevent noise on the input from causing multiple switches in output, or chatter. There have been many means devised to accomplish the hysteresis, such as using a resistor network from input to output dissipating power in at least one state. Examples of some are shown in U.S. Pat. No. 4,110,641 to Robert L. Payne entitled “CMOS Voltage Comparator with Internal Hysteresis” and U.S. Pat. No. 4,394,587 to McKenzie et al entitled “CMOS Differential Comparator with Hysteresis”. Such previous solutions have required the addition of several devices creating a more complex design and requiring additional power.
USPTO Backgrounds
USPTO Backgrounds