With the ever development of Thin Film Transistor (TFT) display technology, more and more novel technologies are proposed and employed, such as Gate on Array (GOA) technology with high resolution and high aperture ratio. Currently, with respect to TFT-LCD, the fabrication of a conventional Advanced-Super Dimensional Switching (ADS) array substrate generally requires seven patterning processes including a gate metal layer mask, a active layer mask, a gate insulation layer mask, a first electrode layer mask, a source/drain metal layer mask, a passivation layer mask and a second electrode layer mask, and each patterning process respectively comprises film formation, exposing, developing, etching and peeling etc.
However, too many patterning processes will directly increase the product cost while decreasing the production capacity. Therefore, there is a need to further reduce the number of patterning processes.
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