1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and in particular, to a data input circuit for a semiconductor memory apparatus and a control method thereof.
2. Related Art
FIG. 1 is a block diagram illustrating a conventional data input circuit for a semiconductor memory apparatus As shown in FIG. 1, the conventional data input circuit includes an input buffer 10 and a data latch unit 20.
The input buffer 10 receives and buffers data ‘DATA_IN’ and outputs the buffered data.
The data latch unit 20 includes a plurality of latches. The data latch unit 20 latches the data output from the input buffer 10 according to a first data strobe signal synchronous pulse ‘DQSRP4’ and a second data strobe signal synchronous pulse ‘DQSFP4’, and outputs aligned data ‘ALGN_R1’, ‘ALGN_R0’, ‘ALGN_F1’, and ‘ALGN_F0’.
The first data strobe signal synchronous pulse ‘DQSRP4’ is generated so as to be synchronized with the rising edge of a data strobe signal ‘DQS’, which is generated outside of the semiconductor memory apparatus. The second data strobe signal synchronous pulse ‘DQSFP4’ is generated so as to be synchronized with the falling edge of the data strobe signal ‘DQS’.
FIG. 2 is a timing diagram illustrating the operation of a conventional data input circuit when the data strobe signal ‘DQS’ is received under normal conditions.
The input data ‘DATA_IN’ is input subsequent to an external write command WT, and is sequentially shifted according to the second data strobe signal synchronous pulse ‘DQSFP4’.
A data clock signal ‘DCLK’ is generated for every two second data strobe signal synchronous pulses ‘DQSFP4’. The data clock signal ‘DCLK’ is a signal that is used to write the aligned data ‘ALGN_R1’, ‘ALGN_R0’, ‘ALGN_F1’, and ‘ALGN_F0’ into memory cells included in the semiconductor memory device.
When two cycles of the clock signal ‘CLK’ (2 tCK) elapses after the input data ‘DATA_IN’ is received, an internal write operation is performed according to the data clock signal ‘DCLK’. Here, (tCK) means one cycle of an external clock signal ‘CLK’.
With respect to the aligned data ‘ALGN_R1’, ‘ALGN_R0’, ‘ALGN_F1’, and ‘ALGN_F0’, the setup time of the data clock signal ‘DCLK’ is (tSETUP), and the hold time of the data clock signal ‘DCLK’ is (tHOLD). A data input operation occurs when the data strobe signal ‘DQS’ is received. When the data strobe signal ‘DQS’ is received normally, then there is sufficient setup time (tSETUP) and hold time (tHOLD), and thus the data write operation is carried out normally. However, when the data strobe signal ‘DQS’ is received later than the rising edge of the external clock signal ‘CLK’, then there will now be sufficient setup time (tSETUP). In addition, when the data strobe signal ‘DQS’ is input earlier than the rising edge of the external clock signal ‘CLK’, then there will not be a sufficient hold time (tHOLD). In this case, the stability of the data write operation may be compromised. In particular, when the data strobe signal ‘DQS’ is input earlier than the rising edge of the external clock signal ‘CLK’, the stability of the data write operation may be significantly compromised.
FIG. 3 is a timing diagram illustrating the operation of the data input circuit when the data strobe signal ‘DQS’ is input too early.
When the data strobe signal ‘DQS’ is input earlier than the external clock signal ‘CLK’, that is, a difference between the data strobe signal ‘DQS’ and the external clock signal ‘CLK’ is (−0.35 tCK), the setup time (tSETUP) and becomes (0.45 tCK), and the hold time (tHOLD) becomes (0.1 tCK).
There are many cases in which a semiconductor memory module needs to operate with the data strobe signal ‘DQS’ while maintaining a minimum margin in the setup time (tSETUP) and the hold time (tHOLD). As such, the potential for the data strobe signal ‘DQS’ to be input earlier than the external clock signal ‘CLK’ goes up, which makes a data write error more likely.
USPTO Backgrounds
USPTO Backgrounds