The present invention is directed to the manufacture of masks used in the lithographic production of integrated circuits and, in particular, to the manufacture of phase shifting masks (PSMs).
As an alternative to chrome on glass (COG) masks used in the lithographic production of integrated circuits, alternating phase shifting masks (altPSMs) have been employed in order to increase the resolution of the critical active area patterns projected. Such increased resolution enables smaller line widths to be exposed on the resist and consequently etched into or deposited on the wafer substrate. This is done by manipulating the electric field vector or phase of the energy beam, e.g., visible or ultra-violet light, used in the lithographic process. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material. By recessing the mask to an appropriate depth, light traversing the thinner portion of the mask and light traversing the thicker portion of the masks will be 180° out of phase, that is, their electric field vector will be of equal magnitude, but point in exactly the opposite direction, so that any interaction between these light beams results in perfect cancellation. However, since the recessed regions on the mask have to form closed polygons and not all edges of these polygons can be made to coincide with desired layout images, the light intensity decrease caused by these residual 180° phase steps leads to unwanted patterns on the wafer. These unwanted residual phase images are erased using a second exposure, commonly using a non-phase shifted mask.
An electronic design automation (EDA) tool converts circuit designs to altPSM layouts with minimal impact to layout design density or design complexity. One method of optimizing design of altPSMs is described in U.S. Pat. No. 6,338,922, the disclosure of which is incorporated herein by reference. Other altPSM design solutions are disclosed in U.S. Pat. Nos. 5,636,131, 5,537,648, 5,858,580 and 6,057,063. However, these approaches do not take full advantage of the introduction of gridded layouts for integrated circuit designs to optimize altPSM design sign efficiency and accuracy, and to improve lithographic performance of the resulting mask.
USPTO Backgrounds
USPTO Backgrounds