1. Field of the Invention
The present invention relates to an analog switch. The present invention also relates to an A/D converter with the analog switch.
2. Description of the Related Art
A plurality of analog switches are employed, for example, in a sample and hold circuit. The sample and hold circuit having a plurality of analog switches are used in such a structure where the circuit is connected, for example, to a successive approximation type A/D converter.
The sample and hold circuit samples a predetermined one of a plurality of analog input signals, and holds the signal for a predetermined period, and supplies the A/D converter with the signal.
Particularly, the plurality of input signals are sent to a plurality of analog switches, respectively. One of the plurality of analog switches operates in a mode wherein an input signal passes through the analog switch, thereby the input signal is sent to the A/D converter.
When the analog switch is in such a mode, the analog switch is said to be in a selective mode. On the contrary, when the analog switch operates in a mode wherein one input signal does not passes through the analog switch, the analog switch is said to be in a non-selective mode.
Likewise the structure of automobiles, in a structure where a source voltage largely varies and an input signal has substantially the same level as that of the source voltage, if the level of the input signal is larger than the level of the source voltage, the input signal may partially pass through the analog switch being in a non-selective mode. An injection current which may be caused by such an input signal partially passing through the switch has an effect on an input signal to be sent to the A/D converter, i.e., on an input voltage of the A/D converter.
In order to prevent occurrence of the injection current, an analog switch generally has two transfer gates in two stages of an input stage and an output stage. In addition, there is included a transistor switch for controlling a connection point of the transfer gates to be grounded when the analog switch is in a non-selective mode. Further, the potential of the back gate (substrate electrode) of an N-channel MOS transistor, included in one transfer gate as an input stage, is set to the same as that of an input signal.
Having thus formed the analog switch, the analog switch has the large circuitry structure for preventing the occurrence of an injection current.
FIG. 4 is a circuitry diagram showing a general analog switch wherein an injection current is prevented from occurring.
As illustrated in FIG. 4, the analog switch comprises transfer gates 100 and 200, inverters 4, 5 and 600, and a transistor (N-channel MOS transistor) N31.
The transfer gates 100 and 200 is cascade-connected with each other between an input terminal TI and an output terminal TO. A connection point of the transfer gates 100 and 200 is denoted by X1.
The transfer gate 100 includes transistors (N-channel MOS transistors) N101, N102, N103, N104 and transistors (P-channel MOS transistors) P101, P102 and P103.
The sources of the transistors N101 and P101 are connected with each other, the sources of the N102 and P102 are connected with each other, and the sources of the N103 and P103 are connected with each other. The drains of the transistors N101 and P101 are connected with each other, the drains of the N102 and P102 are connected with each other, and the drains of the N103 and P103 are connected with each other.
The sources of the transistors N101 and P101 are connected to the input terminal TI, and the drains thereof are connected to the connection point X1. The source of the transistors N102 and P102 are connected to the source of the transistors N103 and P103, and the drains thereof are connected to the input terminal TI. The sources of the transistors N103 and P103 are connected to the source of the transistors N102 and P102, and the drains thereof are connected to the connection point X1.
The gates of the transistors N101, N102 and N103 are connected with each other, and receive a sampling control signal C. The gates of the transistors P101, P102 and P103 are connected with each other, and receive a sampling control signal CB.
Furthermore, the back gates of the transistors N101, N102, N103 are connected to the sources of the transistors N102 and P102 (or the source of the transistors N103 and P103). The back gates of the transistors P101, P102 and P103 are connected to the power supply.
The gate of the transistor N104 is connected to the gates of the transistors P101, P102, P103, the source of the transistor N104 is grounded, and the drain thereof is connected to the source of the transistors N102 and P102 (or the source of the transistors N103 and P103).
The transfer gate 200 includes transistors (N-channel MOS transistors) N201, N202, N203, N204, and transistors (P-channel MOS transistors) P201, P202 and P203.
The sources of the transistors N201 and P201 are connected with each other. The sources of the transistors N202 and P202 are connected with each other. The sources of the transistors N203 and P203 are connected with each other. The drains of the transistors N201 and P201 are connected with each other. The drains of the transistors N202 and P202 are connected with each other. The drains of the transistors N203 and P203 are connected with each other.
The sources of the transistors N201 and P201 are connected to the connection point X1, whereas the drains thereof are connected to the output terminal TO. The sources of the transistors N202 and P202 are connected to the sources of the transistors N203 and P203, while the drains thereof are connected to the connection point X1. The sources of the transistors N203 and P203 are connected to the sources of the transistors N202 and P202, while the drains thereof are connected to the output terminal TO.
The gates of the transistors N201, N202 and N203 are connected with each other, and receive a sampling control signal C. The gates of the transistors P201, P202 and P203 are connected with each other, and receive a sampling control signal CB.
The back gates of the transistors N201, N202 and N203 are connected to the sources of the transistors N202 and P202 (or the sources of the transistors N203 and P203). The back gates of the transistors P201, P202 and P203 are connected to the power source.
The gate of the transistor N204 is connected to the gates of the transistors P201, P202 and P203, the source of the transistor N204 is grounded, and the drain thereof is connected to the sources of the transistors N202 and P202 (or the sources of the transistors N203 and P203).
The inverter 4 supplies the gate of the transistor N31 with a pull-down control signal PD for controlling the connection of the connection point X1 and the ground, in accordance with a select signal S. The inverter 4 includes a transistor (N-channel MOS transistor) N41 and a transistor (P-channel MOS transistor) P41.
The gates of the transistors N41 and P41 are connected with each other, and receive a select signal S. The drains of the transistors N41 and P41 are connected with each other, and connected to the gate of the transistor N31. The source of the transistor N41 is grounded, whereas the source of the transistor P41 is connected to the power source.
The inverters 5 and 600 supply the transfer gates 100 and 200 with complementary sampling control signals C and CB, in accordance with a sampling signal SA.
The inverter 5 includes a transistor (N-channel MOS transistor) N51 and a transistor (P-channel MOS transistor) P51. The gates of the transistors N51 and P51 are connected with each other, and receive a sampling signal SA. The drains of the transistors N51 and P51 are connected with each other, and connected to the transfer gates 100 and 200 and the inverter 600. The source of the transistor N51 is grounded, whereas the source of the transistor P51 is connected to the power source.
The inverter 600 includes a transistor (N-channel MOS transistor) N601 and a transistor (P-channel MOS transistor) P601.
The gates of the transistors N601 and P601 are connected with each other, and connected to the drains of the transistors N51 and P51. The drains of the transistors N601 and P601 are connected with each other, and connected to the transfer gates 100 and 200. The source of the transistor N601 is grounded, while the source of the transistor P601 is connected to the power source.
The transistor N31 includes a gate connected to the inverter 4, a grounded source and a drain connected to the connection point X1. Upon reception of a high level pull-down control signal PD from the inverter 4, the transistor N31 controls the connection point X1 to be grounded. Upon reception of a low level pull-down control signal PD, the transistor N31 disconnects the connection point X1 from the ground.
Operations of the analog switch illustrated in FIG. 4 will now be described.
When the select signal S is at a high level, the analog switch is in a selective mode.
In response to the high level select signal S, the inverter 4 supplies the gate of the transistor N31 with a low level pull-down control signal PD. Then, the transistor N31 is OFF, and the connection point X1 is disconnected from the ground.
In the state where the connection point X1 is disconnected from the ground, if the sampling signal SA is at a high level, the inverter 5 sends a low level sampling control signal CB to the transfer gates 100 and 200 and the inverter 600 sends a high level sampling control signal C thereto. After this, the transistors N101, P101, N201 and P201 are ON, and the transfer gates 100 and 200 are in conduction mode. Thus, an input signal IN to be sent to the input terminal TI is output as an output signal OUT from an output terminal TO via the transfer gates 100 and 200.
The transistors N104 and N204 are OFF, and the transistors N102, P102, N103, P103, N202, P202, N203 and P203 are ON. Then, the back gate of the transistor N101 is connected to the input terminal TI, whereas the back gate of the transistor N201 is connected to the connection point X1. Hence, the potential of the back gates of the transistors N101 and N201 is equal to the potential of the input signal IN.
On the contrary, when the select signal S is at a low level, the analog switch is in a non-selective mode.
In response to the low level select signal S, the inverter 4 supplies the gate of the transistor N31 with a high level pull-down control signal PD. Then, the transistor N31 is ON, and the connection point X1 is grounded. In this structure, even if the input signal IN passes through the transfer gate 100, it will not flow to the transfer gate 200. That is, any injection current has no effect on the output signal OUT.
As explained above, the transistors N102, P102, N103 and P103 of the transfer gate 100 and the transistors N202, P202 N203 and P203 of the transfer gate 200 are necessarily included in the switch gate, in order to prevent any injection current having an effect on a signal. However such transistors have nothing to do with the essential operations of the analog switch.
Accordingly, the general analog switch, wherein the occurrence of an injection current having an effect on the output signal is prevented, includes a number of transistors, thus have complicated circuitry structure.
It is accordingly an object of the present invention to provide an analog switch with the simple circuitry structure.
Another object thereof is to provide an A/D converter employing an analog switch with the simple circuitry structure.
In order to achieve the above objects, an analog switch according to the first aspect of the present invention may comprise:
a first transfer gate which has a first input terminal and a first output terminal and controls transmission of an input signal in accordance with a first control signal and a second control signal which is an inverse signal of the first control signal; and
a second transfer gate which has a second input terminal and a second output terminal, the second input terminal being connected to the first output terminal, and which controls transmission of an input signal which has passed the first transfer gate, in accordance with the first control signal and the second control signal, and
wherein the first transfer gate may include:
a first conductive-type first transistor which has a source connected to the first input terminal, a drain connected to the first output terminal, and a gate receiving the first control signal; and
a second conductive-type second transistor which has a source and a back gate both connected to the source of the first transistor, a drain connected to the drain of the first transistor, and a receiving the second control signal.
According to this invention, an analog switch with the simple circuitry structure can be realized.
The second transfer gate may comprise:
a first conductive-type third transistor which has a source connected to the second input terminal, a drain connected to the second output terminal, and a gate receiving the first control signal: and
a second conductive-type fourth transistor which has a source connected to the source of the third transistor, a drain connected to the drain of the third transistor, and a gate receiving the second control signal.
The analog switch may further comprise a switch circuit which controls connection of a ground and a connection point of the first transfer gate and the second transfer gate, in accordance with a predetermined switch control signal, and
wherein the switch circuit may control the connection point to be grounded for a predetermined period, so that the input signal which has passed the first transfer gate is prevented from flowing to the second transfer gate.
The switch circuit may include a second conductive-type fifth transistor which has a drain connected to the connection point, a grounded source, and a gate receiving the switch control signal.
The fourth transistor may include a back gate; and
the back gate of the fourth transistor may be connected to the drain of the fourth transistor.
Each of the first transistor and the third transistor may be a P-channel MOS transistor; and
each of the second transistor and the fourth transistor may be an N-channel MOS transistor.
An A/D converter according to the second aspect of the present invention may comprise:
a sample and hold unit which samples and holds one of an xe2x80x9cNxe2x80x9d (N is a positive integer) number of analog signals and outputs the signal as a sampled and held signal; and
a converter unit which converts the sampled and held signal into xe2x80x9cMxe2x80x9d bit (M is a positive integer) digital signals, and
wherein:
the sample and hold unit may include
an xe2x80x9cNxe2x80x9d number of analog switches, each having an output terminal connected with one another, for selecting a target analog signal to be sampled and held; and
a capacitor, one end of which is connected to output terminals of the xe2x80x9cNxe2x80x9d number of analog switches and other end of which is grounded, and which samples and holds an analog signal selected by the analog switches and outputs the analog signal as the sampled and held signal;
each of the analog switches may include
a first transfer gate which has a first input terminal and a first output terminal and controls transmission of the analog signal in accordance with a first control signal and a second control signal which is an inverse signal of the first control signal,
a second transfer gate which has a second input terminal and a second output terminal, the second input terminal being connected to the first output terminal, and which controls transmission of an analog signal which has passed the first transfer gate, in accordance with the first control signal and the second control signal, and
a switch circuit which controls connection of a ground and a connection point of the first transfer gate and the second transfer gate, in accordance with a predetermined switch control signal, and controls the connection pint to be grounded while the capacitor holds an analog signal, thereby to prevent the analog signal which has passed the first transfer gate from flowing to the second transfer gate; and
the first transfer gate may include
a first conductive-type first transistor which has a source connected to the first input terminal, a drain connected to the first output terminal, and a gate receiving the first control signal, and
a second conductive-type second transistor which has a source and a back gate both connected to the source of the first transistor, a drain connected to the drain of the transistor, and a gate receiving the second control signal.
The second transfer gate may include:
a first conductive-type third transistor which has a source connected to the second input terminal, a drain connected to the second output terminal, and a gate receiving the first control signal; and
a second conductive-type fourth transistor which has a source connected to the source of the third transistor, a drain connected to the drain of the third transistor, and a gate receiving the second control signal.
The fourth transistor may includes a back gate; and
the back gate of the fourth transistor may be connected to the drain of the fourth transistor.
Each of the first transistor and the third transistor may be a P-channel MOS transistor; and
each of the second transistor and the fourth transistor may be an N-channel MOS transistor.
USPTO Backgrounds
USPTO Backgrounds