The invention of the present application will be illustrated with respect to double data rate synchronous dynamic random access memory (DDR), however, as will be understood by those of ordinary skill in the art, the invention is also applicable to other types of random access memories, in particular, those that utilize one or more delay compensation circuits such as, for example, one or more delay locked loops (DLLs).
A DDR memory essentially doubles the speed capabilities of standard synchronous dynamic random access memory (SDRAM) without increasing the external clock frequency. It does so by enabling the transfer of data on both the rising and falling edges of the external clock. With the increase in speed, timing and synchronization tolerances are correspondingly tighter.
In a purely synchronous memory, data transfer is referenced directly to a free-running external clock. However, as transfer speeds increase data cannot be launched in time for the data outputs (DQs) to capture the data in the data valid window, i.e., the period of time during which the data lines are certain to be in the correct logic state. Although the clock can be offset for early data launch and/or late data capture by adding or subtracting delay elements, these techniques do not account for variable movement of the data valid window relative to a fixed clock signal due, for example, to changes in temperature, voltage, process variables, and loading conditions. A delay compensation circuit such as a delay locked loop (DLL) or calibrated delay line can effectively compensate for such variations and place the data valid window with greater precision with respect to the external clock. A delay compensation circuit typically includes a relatively large number of delay logic gates that toggle or transition with each transition of the external clock. Power is consumed when the gates transition. The delay compensation circuit is not needed when the memory is in a standby mode and data is not being transferred. Unfortunately, once the delay compensation circuit is powered down it takes a large number of clock cycles, as many as 200, for example, to resynchronize or recalibrate the delay. In some standby modes of operation, such as in the active power-down mode, the time it takes to resynchronize or recalibrate the delay compensation circuit after a power-down is not acceptable.
The above-mentioned concerns are addressed by the present invention and will be understood by reading and studying the following specification.
USPTO Backgrounds
USPTO Backgrounds