Non-volatile data storage devices have enabled increased portability of data and software applications. For example, multi-level cell (MLC) storage elements of a flash memory device may each store multiple bits of data, enhancing data storage density as compared to single-level cell (SLC) flash memory devices. Consequently, flash memory devices enable users to store and access a large amount of data. As a number of bits stored per cell increases, bit errors in stored data typically increase. A data storage device may encode and decode data using an error correcting code (ECC) technique to correct certain bit errors in data. The ECC technique may utilize parity information that decreases data storage capacity for other information, such as user data.
To further increase data storage capacity, a memory may have a three-dimensional memory configuration. A three-dimensional memory may include multiple layers of storage elements that are “stacked” relative to a semiconductor substrate. Depending on the particular implementation, each layer of a three-dimensional memory may operate similarly to a two-dimensional (or “planar”) memory. A three-dimensional memory fabrication process typically includes different fabrication steps than a two-dimensional memory fabrication process. For example, a three-dimensional memory fabrication process may connect layers of storage elements to form a column of storage elements.
USPTO Backgrounds
USPTO Backgrounds