The present invention relates to the manufacture of integrated circuits (ICs). More particularly, the present invention relates to improved techniques for removing a controlled amount of the photoresist layer while leaving the remaining thickness of the photoresist layer sufficiently protective of underlying layers during a subsequent etch step.
The use of photoresist is well known in the manufacture of semiconductor devices. In the fabrication of semiconductor devices, e.g., semiconductor integrated circuits (ICs) or flat panel displays, devices such as component transistors are typically formed on a substrate, e.g., a silicon wafer or a glass panel. The substrate typically includes a plurality of layers out of which semiconductor device components are formed, e.g., via etching, doping, or the like. To facilitate the etching of one or more layers of the layer stack, an overlaying photoresist layer is typically applied atop the blanket-deposited underlying layer to be etched. The applied photoresist layer may then be patterned (e.g., through a conventional photoresist technique) to facilitate the etching of the underlying layer or layers. By way of example, one such photoresist technique involves the patterning of the applied photoresist layer by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of the underlying layer to be etched that are unprotected by the photoresist mask are then etched away, leaving behind the desired pattern or features.
FIG. 1 illustrates an exemplary layer stack 100 having thereon a patterned photoresist layer 102. Area 104 in patterned photoresist layer 102 represents the area where etching of the underlying layer 106 may occur in a subsequent etch step.
Substrate 108, representing for example a silicon wafer, is shown disposed below underlying layer 106. It should be understood that underlying layer 106 may represent one or more component layers, the exact number and composition of which are somewhat irrelevant for the purposes of the present invention. The patterned photoresist layer may be employed to etch a single or multiple component layers within underlying layer 106 (through the use of appropriately formulated etch recipes).
After etching is completed, the protective mask in patterned photoresist layer 102 is typically stripped away in a process commonly known as strip ashing. Strip ashing involves oxidizing the protective photoresist mask to form volatile byproduct gasses, which may then be exhausted away.
In the prior art, strip ashing may be performed in a variable-gap plasma processing system using oxygen and helium as component ash source gasses. When the ash source gas mixture comprising helium and oxygen is introduced into the plasma processing chamber, RF energy excitation ignites a plasma out of the ash source gasses. Helium is employed as the bombardment agent to create more ionized oxygen species (O.sup.+) in the plasma. The increase in the number of ionized oxygen species increases the rate of photoresist oxidation, thereby increasing the rate at which the photoresist mask is ashed or removed. If the goal is to quickly remove the photoresist mask, the use of helium is highly advantageous as it reduces the time required for ashing, thereby improving substrate throughput and decreasing the cost of ownership of the plasma processing system.
To keep the ash rate high, prior art strip ashing techniques typically employ a fairly narrow gap between the upper surface of the substrate and the lower surface of the upper electrode of the variable-gap plasma processing chamber in order to increase ion density. To facilitate discussion, FIG. 2A depicts a typical plasma processing chamber 200, representing a plasma processing chamber typically employed in the prior art to strip the photoresist. In the present example, plasma processing chamber 200 represents a plasma processing chamber of a plasma processing system known as the Rainbow 4400.TM., which is available from Lam Research Corporation of Fremont, Calif. Although the Rainbow 4400.TM. is employed herein to facilitate discussion, it should be borne in mind that the techniques disclosed herein are not limited to this particular configuration; the inventive and disclosed ash techniques may be adapted, using knowledge commonly possessed by those skilled in the art, to other plasma processing chamber configurations.
Plasma processing chamber 200 typically includes a lower electrode or chuck 202, which is typically grounded. Substrate 204, representing a substrate having thereon a photoresist layer to be strip ashed, is typically disposed above lower electrode 202 during strip asking.
An upper electrode 206 is disposed above substrate 204 and is separated therefrom by a gap 208. Upper electrode 206 is mounted to a movable backing plate 210, typically in the form of a large circular metal disk. Movable backing plate 210 and upper electrode 206 may be moved along the direction of the z axis by a gap drive assembly which includes a plurality of lead screws 212, a chain 214, and a gap drive motor 216. By changing the direction of rotation of gap drive motor 216, movable backing plate 210 and upper electrode 206 may be moved toward or away from electrode 202, thereby varying the size of gap 208.
During the ash process, the pressure within plasma processing chamber 202 is typically maintained at a lower pressure than the ambient environment pressure. To maintain the pressure differential between the interior of plasma processing chamber 200 and the ambient pressure, seals 220 are typically provided around the periphery of movable backing plate 210. Seals 220, of which there are two in FIG. 2A, are typically formed of a relatively non-reactive sealing material such as a suitable rubber material, e.g., Viton.TM. rubber. To reduce friction between seals 220 and the interior surface of chamber wall 224 as backing plate 210 is moved toward or away from the substrate, seals 220 are typically lubricated with a suitable lubricant.
To facilitate strip ashing, an ash source gas, e.g., O.sub.2 /helium in the case of the prior art strip ash, is typically flowed into chamber interior 226. In the configuration of FIG. 2A, upper electrode 206 has a shower head configuration, i.e., upper electrode 206 is provided with a plurality of apertures for releasing ash source gases into chamber interior 226. However, the ash source gases may also be provided through other mechanisms, e.g., via apertures in chamber wall 224 or a gas ring surrounding lower electrode 202.
An RF power source 22b is then turned on to provide RF energy to upper electrode 206. RF power source 228 is typically coupled to upper electrode 206 via an RF tuning network 230 of a conventional design. RF tuning network 230 functions to minimize the impedance between RF power source 228 and plasma processing chamber 200, thereby maximizing power delivery. The supplied RF power ignites or strikes the plasma from the supplied ash source gases within chamber interior 226 to strip away the photoresist. Reaction byproduct gasses are then exhausted away through an exhaust port 240. Exhaust port 240 may be coupled to an automatic pressure control (APC) system 242, which automatically varies the rate of the gas exhausted through exhaust port 240 to maintain the desired chamber interior pressure.
As mentioned earlier, prior art strip ashing techniques have typically focused on optimizing the process to achieve a high rate of photoresist removal. It has been found, however, that the complete removal or stripping of the photoresist mask is not always desirable. For example, some etch processes demand consistency in the critical dimension of the unetched features, i.e., the width and shape of the areas in underlying layer 106 that remain after etching. While conducting these etch processes, it is advantageous to employ the same photoresist mask in consecutive etches. By way of example, it may be desirable to employ photoresist mask 252 of FIG. 2B to etch through both polysilicon layer 254 and oxide layer 256 to ensure that the unetched features in polysilicon layer 254 and oxide layer 256 have substantially the same critical dimension and are substantially aligned relative to one another. In these cases, the layer stack is typically first etched with an etch that is optimized for etching through polysilicon layer 254 and then etched again with another etch process that is optimized for oxide layer 256 before photoresist mask 252 is completely stripped or removed.
It has been found, however, that consecutive etches using the same photoresist mask, e.g., photoresist mask 252, result in a hardened photoresist upper crust that is difficult to remove after the etches through the underlying layers are completed. With reference to FIG. 2B, this hardened upper crust is shown as upper crust 258. In some etch processes, upper crust 258 may be so hardened after the consecutive etch processes (which are employed to etch through the underlying layers, e.g., polysilicon layer 254 and oxide layer 256) that it is difficult to remove upper crust 258 and photoresist mask 252 afterwards. In these cases, it may be desirable to remove the built up crust after each etch step so that upper crust 258 does not have the opportunity to build up to a thickness that renders photoresist mask 252 difficult to remove after the etches through the underlying layers are completed.
The removal of an upper layer of the photoresist mask, however, presents problems that are different from those encountered by designers of prior art strip ashing processes. For one, the removal of only a thin upper layer of the photoresist mask has not been heretofore the goal of prior art ashing processes. The removal of the thin upper layer of the photoresist mask requires a uniform and controlled ashing process so that only a small portion of the photoresist mask is removed while the remaining thickness of the photoresist mask is left undisturbed to protect the underlying features during subsequent etch step or steps. This is different from the goal of prior art strip ashing processes, which focus on the highest possible photoresist removal rate (which in turn leads to the complete removal of the photoresist mask in the shortest possible period of time).
It has been found, for example, that prior art strip ashing techniques are highly unsuitable for the uniform and controlled removal of the photoresist mask upper crust. For example, the fast rate of photoresist removal of prior art strip ashing processes (about 4,000 angstroms per minute, typically) renders the process unsuitable for removing, say, the top 100 angstroms of the photoresist mask. If one were to employ the prior art strip ashing technique and simply reduce the duration of the ashing step, the high ash rate of the prior art strip ashing technique requires that the ash step be performed in as short as a few seconds. As can be appreciated by those skilled in the art, such a short duration does not permit the plasma processing chamber to stabilize. If such a short strip ash duration is employed, the remaining thickness of the PR layer tends to be highly unreliable and unrepeatable from substrate to substrate. On the other hand, if one were to employ the prior art strip ashing technique and merely reduce the RF power supplied to the top electrode in an attempt to reduce the ion density and to slow down the ash rate to achieve more control, the RF power supply typically needs to be reduced to such a level that plasma reaction may not be sustainable within the plasma processing chamber.
In view of the foregoing, there are desired improved techniques for performing uniform, and controlled removal of an upper layer portion of the photoresist mask in a plasma processing chamber.
USPTO Backgrounds
USPTO Backgrounds