Multigate transistors have been implemented in integrated circuit chips for area efficiency. Examples of multigate transistors include fin-shaped field effect transistors (FinFETs) having multiple fins disposed on two sides of a gate stripe, with fins on one side of the gate stripe serving as sources and fins on the other side of the gate stripe serving as drains. Examples of typical FinFET devices include devices in which transistor arrays are formed by multiple gate stripes in parallel with one another, which are positioned perpendicular to multiple oxide diffusion stripes in parallel with one another. The oxide diffusion stripes are positioned like fins on two sides of each gate stripe. Each pair of source and drain and a portion of the gate stripe between such pair of source and drain may be implemented as an individual transistor.
FIG. 1A illustrates a conventional design for fabricating FinFETs. In this figure, two FinFET cells are illustrated as dashed boxes. Shapes for a gate cut 110 and an isolation cut 120 are also illustrated. The isolation cut 120 is an isolation structure within an active region where the dummy poly-silicon gates and the silicon underneath the gates are removed and filled with dielectrics. The isolation cut 120, which is oriented in the gate stripe direction, is the mask name on the location where a single diffusion break (SDB) process is performed. SDB is kind of isolation by digging trench at the gate region and deep into the silicon fin, and filling the trench with dielectrics. The gate cut is used to cut poly-silicon gates. The gate cut 110, which is oriented in the fin direction, is the mask name on the location where gate is cut. The gate and isolation cuts 110, 120 are locations of fabrication cuts along a gate of the FinFET. The gate cuts 110 are parallel with the fin stripes of the FinFET and the isolation cuts 120 are parallel with the gate stripes of the FinFET.
As illustrated in FIG. 1A, the gate and isolation cuts 110, 120 are separated from each other in the FinFET fabrication by design. But in practice, the conventional isolation cuts 120 are merged often due to lithography process limitations as illustrated in FIG. 1B. For example, the gate cut 110 can be very narrow (e.g., as small as 30 nm), such that the integrity of the conventional lithography process can be compromised.
FIG. 1C illustrate a simplified designed separation between the gate and the isolation cuts, 110, 120. As seen, the design is that one isolation cut 120 is above the gate cut 110 and another isolation cut 120 is below the gate cut 110, and the two isolation cuts 120 are separated from each other. But again, due to lithography processing integrity issues, a long isolation cut mask 125 is used conventionally for processing as illustrated in FIG. 1D. FIG. 1D also illustrates a gate cut mask 115 also used for processing.
When the long isolation cut mask 125 is used, the interlayer dielectric layer corresponding to the junction between the gate cut mask 115 and the isolation cut mask 125 is etched. This unfortunately has the effect of introducing stresses in later processing. The break of the active region and the surrounding inter-layer-dielectric (ILD) causes strain accumulation at the region. For example the PFET adjacent to the isolation cut is usually impacted by compressive strain, and causes threshold voltage Vt of the PFET to be lowered from a target Vt. Also, as the isolation cut length is increased, this has the effect of lowering the threshold voltage from the target even further. In other words, ΔVt, which is the deviation from the target, may increase as the isolation cut length increases. Such layout effects are generally undesirable.
USPTO Backgrounds
USPTO Backgrounds