1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device including a step of controlling a lifetime.
2. Description of the Background Art
Japanese Patent Laying-Open No. 62-055964 discloses a transistor formed on a semiconductor wafer. The transistor is independent of main chips in a power transistor to measure a current amplification factor. The publication describes that, by using the transistor measuring the current amplification factor, a main chip having a large variation in the current amplification factor can be selected from a plurality of main chips obtained from the semiconductor wafer.
Japanese Patent Laying-Open No. 2006-352101 describes that, when a plurality of semiconductor devices are prepared, concentrations of impurities originally contained in these semiconductor devices before fabrication thereof vary for each semiconductor device. The publication discloses a method of substantially equalizing such variations. In the method, a large amount of impurities are introduced into a semiconductor device when a semiconductor region is formed. The publication describes that the variations described above are substantially negligible by the introduction of a large amount of impurities.
Japanese Patent Laying-Open No. 2000-200792 discloses a method of manufacturing an IGBT (Insulated Gate Bipolar Transistor). In the method, electron beams of several MeV (Mega electron Volt) are emitted to the IGBT. Emission of the electron beams reduces the lifetime of the IGBT. Emission of the electron beams damages a gate oxide film and an interface between the gate oxide film and a channel region. The damage is recovered by an annealing treatment performed after the emission.
USPTO Backgrounds
USPTO Backgrounds