1. Field of the Invention
This invention relates to circuits and semiconductor devices that will receive light and convert the light to an electronic signal representing the amplitude of the light commonly referred to as photosensors or pixel sensors. More particularly this invention relates to the methods of operation photosensors or pixel sensors to provide electronic shuttering and to eliminate image-lag.
2. Description of Related Art
Imaging circuits typically include a two dimensional array of photosensors. Each photosensor will comprise one picture element (pixel) of the image. Light energy emitted or reflected from an object will impinge upon the array of photosensors. The light energy will be converted by the photosensors to an electrical signal. Imaging circuitry will scan the individual photosensors to readout the electrical signals. The electrical signals of the image will be processed by external circuitry for subsequent display.
The most common single chip imaging technology in use is the charge coupled device (CCD) camera. A CCD operates by accumulating charge generated within a photo sensor in potential wells in the semiconductor substrate. The depth of the potential wells is controlled by the voltage on a gate electrode located just above the surface of the semiconductor substrate. By manipulating the voltage on the gate electrodes, the charges can be moved along the surface of the semiconductor substrate to a sensing point. The charges will be amplified into the electronic signals of the image.
Modern metal oxide semiconductor (MOS) processing techniques have allowed the transport of charges within CCD structures to be accomplished with almost perfect efficiency at video rates. However, some fraction of the charge accumulated will be lost during the shifting of the charge along the surface. The charge accumulated within each potential well will be shifted and sensed once per frame time. Typically this time is on the order of 30-60 frames per second.
The CCD technology has limitations. The charge generated by the impinging light is shifted directly before being sensed and amplified. Because of the inefficiency of this process, the gain of the device (electrons out vs. photons in) is less than unity. The will impose limitations on the amount of charge to be stored in each well. The amount of minimum charge will be the amount that can be sensed in the sense amplifier above the noise of the sense amplifier. The amount of maximum charge will be limited by the amount that will physically be able to be generated and shifted from one well to the next.
To overcome these dynamic-range limitations of the CCD, a phototransistor has been used to sense the incoming light. High resolution imagers as described in U.S. Pat. No. 5,260,592 (Mead et al.), U.S. Pat. No. 5,324,958 (Mead et al.), and "A High Resolution CMOS Imager With Active Pixel Using Capacitively Coupled BiPolar Operation", Chi et al, paper #82, Proceedings of International Conference on VLSI-technology systems, and applications, Taipei, Taiwan, June 1997, have a simple structure as shown in FIGS. 1a, 1b, and 1c. These pixel structures employ standard processing techniques typical to CMOS logic technology.
An N-type impurity is implanted in a P-substrate 5 to form an N-well 10. A field oxide 20 is grown on the surface of the semiconductor substrate to define the boundaries of the pixel cell. Within the field oxide 20 a p-type impurity is implanted to form the P-base 15 of the phototransistor Q1 60. The N-well 10 will be connected to a power supply voltage source and act as the collector of the phototransistor Q1 60. Next a thin layer of gate oxide is grown on the surface of the P-base 15 to form the capacitor dielectric 30 of the capacitor C 65. A layer of polysilicon material 35 will be deposited over the P-base 15 to form the second plate of the capacitor C 65. After a short re-oxidation and formation of oxide spacer an n-type impurity is implanted to form the emitter 25 of the phototransistor Q1 60. The P-base 15 is left floating. Its potential is determined by the V.sub.row through the coupling of capacitor C 65. The layer of polysilicon material will also be connected to the row activation voltage circuit V.sub.row 62. The row activation circuit V.sub.row 62 will activate the phototransistor Q1 60 to transfer charges collected by the phototransistor Q1 60.
A second insulating material such as silicon dioxide is deposited on the surface of the semiconductor substrate to form the dielectric 40. A metal layer 45 is place in contact 50 with the emitter 25 of the bipolar transistor Q1 60. The metal layer 45 will provide the interconnection to the sense amplifier 70. It is apparent that the above described process flow can be used to form CMOS transistors. For instance the polysilicon material 35 can be used to form a gate of the CMOS transistor and the n-type implant that is used to form the emitter 25 can be used to form a source/drain region. The compatibility of fabricating bipolar pixels and CMOS transistors is a great advantage compared to the process used in CCD fabrication methods.
A quantum of light energy L1 105 will be reflected or emitted from an external object and impinge upon the P-base active region 17. The photons of the quantum of light energy 105 will be absorbed in the neighborhood of the collector-base junction 12 and the emitter base junction 22 and form electron-hole pairs. The nearest p-n junction will collect the electron-hole pairs. The minority carriers collected by either the collector-base junction 12 or the emitter-base junction 22 will as base current. The base current is multiplied by the current gain of the transistor to form the collector current. The signal current I.sub.sc 100 at the emitter 25 of the transistor Q1 60 is the sum of the base current created by the conversion of the quantum of light 105 to the electron-hole pairs and the collector current. The signal current I.sub.sc 100 will be transferred to the sense amplifier 70 for further conditioning.
Refer now additionally to FIG. 1d to understand the operation of the photo transistor pixel structure. During the integration period 102 the row activation circuit V.sub.row 62 is held at a fixed voltage to reverse bias the base-emitter junction 22 of the transistor Q1 60. Under this condition, the current created by the conversion of the quantum of light 105 to the electron-hole pairs will integrate on the capacitor C 65.
When it is desired to read the amount of charge created during the integration period 107, the row activation circuit V.sub.row 62 is brought to a high voltage level during the read time 104. The P-base potential is raised by Vrow 62 through capacitor C 65 coupling and becomes forward biased with respect to the emitter 25. The charge on capacitor C 65 will flow in the base 15 of the transistor Q1 60 and form the emitter current, which is the signal current I.sub.s 100.
Other structures incorporating photodiodes and MOS transistors are described in "Image Capture Circuits in CMOS" E. Fossum, Paper #B1, Proceedings of International Conference on VLSI-Technology, Systems, and Applications, Taipei, Taiwan, June 1997. A passive pixel circuit consists of a photodiode and a MOS pass transistors. The photodiode will convert light to electric charge. The MOS pass transistor will gate the electric charge to a charge integrating amplifier. An active pixel circuit will have a photodiode, a MOS pass transistor, and a source follower to act as a buffer amplifier to the charge integrating amplifier. A MOS transistor activated by a reset signal is added to the active pixel circuit to reset the photodiode to act as an electronic shutter. The time of the electronic shutter will be modified by adjusting the activation time of the MOS transistor activated by the reset signal. The varying of the reset time within a fixed frame time will adjust the exposure time of the photodiode to adjust the amount of time the photodiode will collect the electrons generated by the image photons.
The active bipolar pixel of FIGS. 1a, 1b, and 1c have the advantage of high sensitivity, simpler pixel layout, and lower manufacturing cost compared to CMOS pixels as described in Chi. However, the bipolar active pixels have the limitations of blooming and image lag. Further, the active bipolar pixels of FIGS. 1a, 1b, and 1c can not implement an electronic shutter without modifying the frame rate of the active bipolar pixel sensor.
Refer now to FIG. 2 to understand the phenomena of blooming. In an array of pixels (pixel A 80-pixel X 85), one row of pixels--pixel A 80 will be integrating the charge from the quantum of light L1 105 impinging on the phototransistor Q1 60a. That is the row activation circuit V.sub.rowa will be brought to a low level 75 to reverse bias the base emitter junction of the phototransistor Q1 60a and allow the charges to collect at the capacitor C 65a. At this same time another row of pixels--pixel X 85 will be read to sense the level of charge present on the capacitor C 65b.
If the quantum of light impinging L1 105 on the pixel A 80 is sufficiently large, the charges will begin to forward bias the base-emitter junction of the transistor Q1 60a. This will cause an overflow current I.sub.ofc 95 to flow in the column interconnection 90. The sense amplifier will now sense the total current I.sub.tot 110 which is the sum of the overflow current I.sub.ofc 95 and the intended signal current I.sub.sc 100. The pixel being read (pixel X 85) will to be brighter than is should be. This will cause a blooming of bright light sources within an image.
Refer now to FIG. 3 to understand the problem of image lag. In this diagram the pixel X--last frame 200 will have been read at the frame time previous to the current frame time. As the row activation circuit V.sub.rowx is brought from a high voltage to a low voltage 185, the p-base is reversed biased with respect to the emitter by the coupling of the capacitor C 165. The p-base potential may not be the same for all pixels with the row at the beginning of the image integration time. The amount of P-base potential drop after V.sub.row transitions from a high level to a low level (i.e. pulse height) at the beginning of a read operation is: EQU .DELTA.V.sub.B =(pulse height).times.(coupling ratio).
The coupling ratio of the capacitor C 165 is defined as: ##EQU1## where: C.sub.BE is the base-emitter junction capacitance of the transistor Q1 160.
C.sub.BC is the base-collector junction capacitance of the transistor Q1 160.
The P-base potential is controlled by the voltage V.sub.row and the coupling ratio (.gamma.). Thus the charge removal from the capacitor C 165 is not complete and will cause a component of a residue current 210 in the emitter of the transistor Q1 160.
A second component of the residue current 210 will be a remnant of minority carrier charges left in the p-base from the injection of electrons from the forward biased base-emitter junction of the transistor Q1 160 during the previous read operation. The residue charges in the p-base will continuously flow with current gain to the emitter of the transistor Q1 160 and will be added to the signal current 215 of the current read time. This will cause a ghosting of the image following moving objects or a tail following a bright object. The residual charge will eventually disappear some time later by either recombination or the minority carrier current flowing away from the P-base. The time for image-lag is approximately the minority carrier recombination lifetime (i.e. approximately 100 msec.) and can last for several frames.
An impurity could be added to the p-base to act as an "life-time killer" to reduce the recombination time. A difficulty with such "life-time killers" is increased junction leakage current, which degrades the imager sensitivity.
U.S. Pat. No. 5,097,305 (Mead et al.) discloses a photosensor having a phototransistor and a capacitor coupled to the base of the phototransistor. A pass transistor is placed in the emitter of the phototransistor to selectively couple the signal current to the sense amplifier.
U.S. Pat. No. 5,288,988 (Hashimoto et al.) describes a photosensor circuit similar to that described in FIGS. 1a, 1b, and 1c. The cell incorporates a MOS transistor in the photoconversion cell. When the MOS transistor is activated, the above described residue current will be prevented by eliminating the residue charges from the base of the phototransistor.
U.S. Pat. No. 5,576,763 (Ackland et al.) discloses a CMOS single polysilicon active pixel. The CMOS active pixel comprises a photo site located on a substrate for generating and storing charge carriers, the charge carriers being generated from photonic energy incident upon the photo site and semiconductor substrate, a photo gate, a transfer transistor and output and reset electronics. The gate of the transfer transistor and the photo gate are defined in a single layer of polysilicon disposed on the semiconductor substrate. The source of transfer transistor is a doped region of substrate, referred to as a coupling diffusion, which provides the electrical coupling between the photo gate and the transfer transistor. The coupling diffusion allows for the transfer of a signal stored in a photo site under the photo gate to the output electronics for processing. The single polysilicon active pixel may be operated by biasing the transfer transistor to the low operating voltage of the pixel for example, 0 volts. By virtue of the structure of the single polysilicon active pixel, this mode of operation results in the same timing as if the transfer transistor were clocked but neither a clock nor the associated driving circuitry are required. However, there is little or no tendency for image lag as occurs in double polysilicon active pixels when they are operated in a manner which avoids clocking the transfer gate.
U.S. Pat. No. 5,512,950 (Watanabe et al.) discloses a solid state CCD imager device and a method for driving the solid state CCD imager device in which an electronic shutter function is provided. The CCD imager will never have charge overflow in the light receiving portion even when the light with a high intensity. The electronic shutter operation is conducted by sweeping out the charges in the light receiving portion by applying a predetermined voltage to a substrate, and the voltage application period is within a horizontal blanking period.
U.S. Pat. No 5,619,049 (Kim) teaches a charge coupled device type solid state image pickup in which the overflow drain is formed at a high concentration on each photo-sensitive well. A high concentration impurity layer is formed in the top layer of a PNPN structure to act as a drain against overflow. The structure enables overflow and electronic shutter operation even under low voltage conditions and may be realized on chip.
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