This application claims the priority benefit of Taiwan application serial no. 87114053, filed Aug. 26, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to a clock generator, and more particularly to a phase lock loop (PLL) clock generator with programmable skew and frequency.
2. Description of the Related Art
With the advancement of semiconductor technologies, operating frequency of digital circuit systems is getting higher and higher. Therefore, the problem of clock synchronization becomes an important issue for designers. The clock synchronization involves not only a single clock signal, but also multiple clock signals. Generally, skew of a clock signal is determined by the clock generator and the loading based on an open-loop configuration. When trace length from the clock generator to the loading becomes longer, or the loading increases, the problem of signal skew of the clock signals becomes more serious. For example, many devices might share a single clock generator on a computer motherboard. Also, memory size can be dynamically changed depending on user requirements. Furthermore, there are many interface slots for connecting peripheral devices depending on practical requirements. Therefore, the change of memory size and quantity of peripheral devices will accordingly change the loading on the clock signal. It is no wonder that the open-loop configuration can not solve the problem of signal skew. On the other hand, there is a need to change the frequency of a clock signal. If all the clock signals are provided by external clock generators, it is difficult to arbitrarily change the clock frequency because the frequency of the clock signals has been fixed.
FIG. 1 is a schematic block diagram of a computer motherboard using a conventional clock generator, in which a single clock generator 150 provides clock signals CPU_CLK and SYS_CLK. The clock signal CPU_CLK provides signals to a CPU 110 and a chipset 120, while the clock signal SYS_CLK provides signals to the chipset 120 and devices 141 to 14N through a bus 130. Since the chipset 120 is responsible for controlling operations of the computer motherboard, it needs to reference both the clock signal SYS_CLK and the clock signal CPU_CLK. The devices 141 to 14N are peripheral devices. Since various numbers of peripheral devices can be connected to the computer motherboard, the loading on the clock signal SYS_CLK is therefore varied depending on the number of devices connected. The change of loading on the clock signal SYS_CLK affects the skew of the clock signal, and consequently the stability of the whole system.
If multiple clock signals can be provided from the chipset 120 to devices within the system, designers can better control the skew of clock signals to provide higher stability and durability to the system. Furthermore, frequency of the clock signals can be dynamically changed by a computer program.
As a summary, the conventional clock generator has the following sadvantages:
1. If clock signals are provided by external clock generators, the frequency of the clock signals can not be easily changed, particularly by a computer program.
2. The clock signal provided based on an open-loop configuration is affected by the change of loading, which imposes great difficulty to control the skew of the clock signal, and consequently the stability of the system.
It is therefore an objective of the present invention to provide a phase lock loop (PLL) clock generator with programmable frequency to dynamically change the clock frequency generated.
It is another objective of the present invention to provide a PLL clock generator with programmable skew so that the skew of the clock signal can be dynamically adjusted.
In accordance with the foregoing and other objectives of the present invention, a phase lock loop (PLL) clock generator with programmable frequency and skew is provided, in which a clock signal is generated based on a reference signal. The clock generator includes a plurality of first delay devices each having a first terminal and a second terminal, a first multiplexer, a plurality of second delay devices each having a first terminal and a second terminal, a second multiplexer, and a PLL signal generator.
The first delay devices are cascaded in series by connecting the second terminal of a first delay device to the first terminal of an adjacent first delay device. The first terminal of one of the first delay devices is coupled to the reference signal.
The first multiplexer comprises a plurality of input terminals, an output terminal, and a first selection input. The input terminals of the first multiplexer are connected to the reference signal and the second terminals of the first delay devices, respectively, so that one of the input signals to the first multiplexer is chosen by the first selection input to couple to the output terminal of the first multiplexer.
The second delay devices are cascaded in series by connecting the second terminal of a second delay device to the first terminal of an adjacent second delay device. The first terminal of one of the second delay devices is coupled to a feedback signal.
The second multiplexer comprises a plurality of input terminals, an output terminal, and a second selection input. The input terminals of the second multiplexer are connected to the feedback signal and the second terminals of the second delay devices, respectively, so that one of the input signals to the second multiplexer is chosen by the second selection input to couple to the output terminal of the second multiplexer.
The PLL signal generator comprises a first input terminal, a second input terminal, and an output terminal. The first input terminal of the PLL signal generator is coupled to the output terminal of the first multiplexer and the second input terminal of the PLL signal generator is coupled to the output terminal of the second multiplexer. The clock signal is generated from the output terminal of the PLL signal generator and fed back to serve as the feedback signal via a conductive line.
According to a preferred embodiment of the present invention, the clock signal, which is fed back at the midpoint of the conductive line to serve as the feedback signal, provides clock signals required by external devices.
The above-mentioned PLL signal generator in the PLL clock generator comprises a plurality of first dividers each having an input terminal and an output terminal, a third multiplexer, a plurality of second dividers each having an input terminal and an output terminal, a fourth multiplexer, a PLL core circuit, a plurality of third dividers each having an input terminal and an output terminal, and a fifth multiplexer.
The input terminals of the first dividers are connected to the output terminal of the first multiplexer.
The third multiplexer comprise a plurality of input terminals, an output terminal, and a third selection input. The input terminals of the third multiplexer are connected to the output terminals of the first dividers, respectively, so that one of the input signals to the third multiplexer is chosen by the third selection input to couple to the output terminal of the third multiplexer.
The input terminals of the second dividers are connected to the output terminal of the second multiplexer.
The fourth multiplexer comprises a plurality of input terminals, an output terminal, and a fourth selection input. The input terminals of the fourth multiplexer are connected to the output terminals of the second dividers, respectively, so that one of the input signals to the fourth multiplexer is chosen by the fourth selection input to couple to the output terminal of the fourth multiplexer.
The PLL core circuit comprises a reference input terminal, a feedback input terminal, and an output terminal. The PLL core circuit generates a signal at the output terminal based on the phase difference between signals at the reference input terminal and the feedback input terminal. The reference input terminal is coupled to the output terminal of the third multiplexer and the feedback input terminal is coupled to the output terminal of the fourth multiplexer.
The input terminals of the third dividers are connected to the output terminal of the PLL core circuit.
The fifth multiplexer comprises a plurality of input terminals and an output terminal. The input terminals of the fifth multiplexer are connected to the output terminals of the third dividers, respectively, and the clock signal is produced from the output terminal of the fifth multiplexer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
USPTO Backgrounds
USPTO Backgrounds