1. Field of the Invention
The present invention generally relates to an auto-tuning circuit for an active filter used in video signal processing. More particularly, it relates to a circuit for automatically tuning an active filter used in a color television (TV) receiver, such as a delay line for delaying video signals or a band-pass filter for limiting the band of chrominance signals.
2. Description of the Related Art
In recent years, the active filtering technology and the semiconductor manufacturing technology have advanced, making it possible to incorporate active filters of video band (0-10 Hz) into an integrated circuit (IC). To incorporate active filters of this type into an IC had been regarded as very difficult.
The resistance, capacitance, etc. of a filter of this type incorporated in an IC, which determine the transfer characteristic thereof, differ about 20% from the design values due to the inadequate control of the IC manufacturing process. Hence, it is necessary to adjust the resistance, capacitance, etc. of the filter built in the IC, e.g., a delay line for delaying Y (luminance) signals or a band-pass filter for filtering chrominance signals.
Additional IC manufacturing steps must be performed to adjust the resistance, capacitance, etc. of the filter incorporated in each IC. Further, these electrical properties of the filter cannot always be adjusted with sufficient accuracy, and may change due to temperature drift. In view of this, it is not necessarily advisable to adjust the resistance, capacitance, etc. of the filter.
Hence, various auto-tuning circuits have been invented which automatically adjust the resistance, capacitance, etc. of a filter built in an IC.
FIG. 6 illustrates one of these circuits, which is a phase-locked loop (PLL) including a conventional voltage-controlled filter.
In this auto-tuning circuit, a reference clock signal A is supplied from an input terminal 1 to a phase detector 2 and a voltage-controlled filter 3. The phase detector 2 compares the phase of the clock signal A with that of the signal B output by the filter 3, and generates a voltage corresponding to the phase difference between the signals A and B. This voltage is applied via a loop filter 4 and a DC amplifier 5 to the voltage-controlled filter 3. The voltage adjusts the transfer characteristic of the filter 3 such that the filter 3 can process an input video signal into a video signal having desired characteristics.
FIG. 7 illustrates the phase detector 2 and the loop filter 4 in detail. The detector 2 comprises a current source I.sub.0, a double-balanced differential amplifier comprised of transistors Q01 to Q06, and a current mirror comprised of transistors Q07 and Q08. The reference clock signal A is supplied between the common base of the transistors Q03 and A06 and the common base of the transistors Q04 and Q05. The signal B output by the voltage-controlled filter 3 is supplied between the bases of the transistors Q01 and Q02. An output I.sub.X, which corresponds to the phase difference between the signals A and B, is supplied from the collectors of the transistors Q04 and Q06. The output I.sub.X is supplied to the DC amplifier 5 through a capacitor C.sub.X which constitutes the loop filter 4.
The voltage-controlled filter 3 is a delay line or a low-pass filter having such a second-order transfer characteristic, either shifting the phase of the reference clock signal A by 90.degree..
The operation of the circuit shown in FIGS. 6 and 7 will now be briefly explained, with reference to the timing chart of FIG. 8.
The first signal A input to the phase detector 2 has the waveform A shown in FIG. 8, and the second signal B input to the detector 2 has the waveform B shown in FIG. 8. The second signal B has been generated by passing the first signal A through the voltage-controlled filter 3, thereby phase-shifting the signal A or delaying the same by 135.degree.. Both the first signal A and the second signal B have a sufficient amplitude. The phase detector 2 outputs a current I.sub.X which represents the phase difference between the signals A and B and has the waveform specifically shown at C in FIG. 8. This current I.sub.X is accumulated in and discharged from the capacitor C.sub.X forming the loop filter 4.
As is evident from C in FIG. 8, the electrical charge supplied out of the capacitor C.sub.X is greater than the charged accumulated therein. Hence, the output voltage of the loop filter 4 decreases with time. The output voltage of the loop filter 4 is amplified by the DC amplifier 5 and is then applied to the voltage-controlled filter 3. The filter 3 is designed to shift the phase of the first signal A by an amount proportional to the input voltage. Therefore, the PLL is stabilized when the charge supplied from the capacitor C.sub.X is equal to that accumulated therein, that is, when the signal B is out of phase from the signal A by 90.degree..
More precisely, the reference clock signal A is a 3.58 MHz signal output by an oscillator (not shown) which is used to demodulate a chrominance signal, and the voltage-controlled filter 3 is a delay line. The transfer characteristic of this delay line is adjusted automatically such that the delay line shifts the phase of the signal A by 90.degree. at the frequency of 3.58 MHz. In other words, the delay line outputs a video signal delayed by about 70 nsec with respect to the input video signal (i.e., a luminance signal).
As is shown in FIG. 6, the control voltage applied to the filter 3 is also applied to the other filters formed in the same IC, whereby these filters are automatically adjusted to have desired transfer characteristics. This is because the resistors and capacitors incorporated in the IC have characteristics different slightly from the design values by only .+-.1 to 3%. However, this auto-tuning circuit (FIG. 6) has a drawback which will be discussed below.
FIG. 9 illustrates a conventional delay line circuit which is used as a Biquad-type voltage-controlled filter and which is similar to the type disclosed in U.S. Pat. No. 4,748,422. As is shown in FIG. 9, this delay line circuit has transistors Q1 to Q31, resistors R1 to R14, capacitors C1 and C2, a voltage source V.sub.CC, and a bias source V1. An input signal A is supplied to the base of the transistor Q1, and an output signal B is supplied from the emitter of the transistor Q16. A control voltage V.sub.X is applied to the bases of the transistors Q3, Q11, and Q17. A reference voltage V.sub.ref is applied to the bases of the transistors Q4, Q12, and Q18.
Let us determine the transfer function of the filter shown in FIG. 9. Assuming that the resistor R1 has a resistance twice as much as the resistance .gamma. of the resistor R2, we obtain: ##EQU1## where .alpha. is the transfer coefficient of the control transistors Q3 and Q4 and also that of the control transistors Q11 and Q12, and is less than 1 (.alpha.&lt;1).
Obviously, this filter (FIG. 9) has a stable amplitude characteristic and can function as a delay line. It should be noted that the transfer function c, common to the transistors Q3, Q4, Q11, and Q12, is I.sub.out /I.sub.in as is illustrated in FIG. 10 illustrating a delay line. Also it is apparent that the transfer coefficient .alpha. can be adjusted by changing the control voltage V.sub.X, whereby the transfer function (i.e., the delay time) of the delay line is changed.
Let us now discuss the influence of the crosstalk component of the signal leaked through the control voltage line connected to the voltage-controlled filter 3, with reference to FIG. 11 which shows a circuit for controlling the transfer function of the filter illustrated in FIG. 9. The circuit shown in FIG. 11 has two lines connected to the control voltage source V.sub.X and the reference voltage source V.sub.ref and having output impedances R.sub.r and R.sub.x. It further comprises transistors Q.sub.A and Q.sub.B whose bases are connected to the lines, respectively, and a current source I.sub.C for these transistors Q.sub.A and Q.sub.B. When the current from the current source I.sub.C contains an AC component resulting from the input signal A, the emitter currents of the transistors component Q.sub.A and Q.sub.B connected to the voltage sources V.sub.X and V.sub.ref change, thereby changing the base currents I.sub.B of both transistors Q.sub.A and Q.sub.B. Consequently, the current I.sub.B and the impedances R.sub.r and R.sub.x cause a voltage drop, and the AC component is inevitably supplied through the control voltage lines.
Further, a signal component is supplied to the collector of the transistor Q.sub.B. As a result of this, a high-band component leaks into the bias line for applying the reference voltage V.sub.ref, due to the base-collector parasitic capacitance C.sub.CB of the transistor Q.sub.B. Hence, the reference clock signal for adjusting the transfer function of the delay line is a 3.58 MHz signal for demodulating chrominance signals, the 3.58 MHz component will leak into the delay lines for processing luminance signals. This 3.58 MHz component will result in slant stripes appearing on the CRT screen of a TV receiver, and should therefore be removed. The parasitic capacitance C.sub.CB will affect the other bias lines in the same manner.
The loop filter 4 is connected between the phase detector 2 and the AC amplifier 5. The transfer characteristic of this filter 4 can be altered by external means. Therefore, in most cases, the capacitor C.sub.X is provided outside the IC and connected to the IC. More precisely, as is shown in FIG. 12, the capacitor C.sub.X is connected by a terminal pin P to aluminum wire connecting the phase detector 2 and the DC amplifier 5. An impedance R.sub.Z is provided between the terminal pin P and the aluminum wire, because of the other aluminum wires formed in the IC, the bonding wires connecting the IC and the chip frame, and the chip frame itself. Hence, while the phase detector 2 is comparing the signals A and B, the clock component at the input of the DC amplifier is twice as much (2 fsc) and leaks to the delay line. This clock component will result in slant stripes appearing on the CRT screen of the TV receiver, too.
As has been mentioned, in the conventional circuit shown in FIG. 11, both the reference clock component and the clock component twice as much as the reference clock component leak to the filters processing the video signals. As a consequence, slant stripes appear on the CRT screen of the TV receiver.
When the conventional auto-tuning circuit 10 is connected to a band-pass filter (BPF) 6 for processing chrominance signals as is shown in FIG. 13, and a 3.58 MHz signal is used as a reference clock signal, the 3.58 MHz clock signal leaks all the time the circuit 10 is operating. The band-pass filter 6, which is an active filter, inevitably generates a crosstalk signal CW. The crosstalk signal CW is supplied to a color signal demodulating circuit (DEMO) 8 through an automatic color control circuit (ACC) 7. Hence, the DEMO 8 demodulates the signal CW, adversely influencing a color-difference signal DC and ultimately impairing the white balance on the CRT screen. Further, the crosstalk signal CW is supplied from the ACC 7 also to a color killer circuit 9, along with a burst signal, inevitably causing the color killer circuit 9 to make errors.
The above description is limited to the case where the conventional auto-tuning circuit is used to control a voltage-controlled filter. Nevertheless, the conventional auto-tuning circuit can be used to control a current-controlled filter, in which case, too, the circuit will make the same problems as mentioned above.
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