The back-end structures of integrated circuits typically comprise multiple layers of patterned metal layers that are interconnected by vias. The metal layers are formed by alternately depositing insulating layers and metal layers on a semiconductor substrate and patterning each metal layer to define electrical traces that interconnect the devices formed in the semiconductor substrate. The layers are interconnected by etching or drilling holes in the insulating layers between the metal layers and filling the holes with an electrically conducting material such as copper or tungsten.
The process of etching or drilling holes in the insulating material uses a relatively large amount of the space available in the various back-end layers and the need to allow for a certain amount of additional space around the via for pads and/or for isolation consumes even more space.
USPTO Backgrounds
USPTO Backgrounds