This invention relates in general to cascode amplifiers and in particular, to field-effect-transistor ("FET") cascode transconductance circuits, CMOS structures for implementing those FET cascode transconductance circuits, and methods of forming those CMOS structures.
Cascode amplifiers are useful in various circuits, because of their inherently wide bandwidths. In particular, by avoiding the Miller effect, cascode amplifiers provide superior high frequency performance over other conventional amplifier circuits that are subject to high frequency roll-off.
FIG. 1A illustrates, as an example, a conventional, cascode transconductance circuit 10 comprising n-mos FETs, 12 and 14, serially connected together such that the source of n-mos FET 14 (also referred to herein as the "cascoding transistor") is connected to the drain of n-mos FET 12 (also referred to herein as the "current sinking transistor"). A first voltage V1 is then connected at node D to the source of n-mos FET 12, a second voltage V2 is connected at node A to the drain of n-mos FET 14, a bias voltage Vcasc is connected at node B to the gate of n-mos FET 14, and an input voltage Vin is connected at node C to the gate of n-mos FET 12. The second voltage V2 is selected to be greater than the first voltage V1, and the bias voltage Vcasc is selected to be sufficient to ensure that n-mos FET 12 operates in its saturated region. Thereupon, when an input voltage Vin is applied to the gate of n-mos FET 12, a proportional output current Iout flows through n-mos FETs 12 and 14.
FIGS. 1B and 1C illustrate, as examples, two conventional CMOS structures, 20 and 40, respectively, for implementing the conventional cascode transconductance circuit 10 in an integrated circuit. CMOS structure 20 uses a shared n+ source/drain region 23 to provide a more compact structure (i.e., requiring less surface die area to implement) than if two complete n-mos FETs (i.e., each having its own n+ source and drain regions, for a total of four such regions) were formed to implement the conventional transconductance circuit 10 of FIG. 1A. CMOS structure 40 goes even further in providing a more compact structure by eliminating the shared n+ source/drain region 23 of CMOS structure 20. This structure 40, however, typically requires a double polysilicon process so that the two gate electrodes, 45 and 46, can be formed in separate polysilicon layers. Such a double polysilicon process adds to the overall integrated circuit cost. In addition, the overlapping portion of the two polysilicon gate electrodes, 45 and 46, form a capacitor with the gate oxide material (hatched area) separating the two gate electrodes.
When more current providing capability is required than what one pair of n-mos FETs can provide, additional pairs can be connected in parallel. FIG. 2A illustrates, for example, a cascode transconductance circuit 50 comprising two pairs of n-mos FETs, 52 and 54, wherein each pair is identically formed as the conventional cascode transconductance circuit 10 of FIG. 1A.
FIGS. 2B and 2C illustrate, as examples, two conventional CMOS structures, 60 and 80, respectively, for implementing the conventional cascode transconductance circuit 50 in an integrated circuit, wherein CMOS structure 60 of FIG. 2B corresponds to the CMOS structure 20 of FIG. 1B, and CMOS structure 80 of FIG. 2C corresponds to the CMOS structure 40 of FIG. 1C.
USPTO Backgrounds
USPTO Backgrounds