Electronic computer aided design (ECAD) software tools for static timing analysis (STA) may be used to estimate timing delays in an electronic circuit such as that found in an integrated circuit. However as process technology improves so that smaller transistor channels of 65 nano-meters (nm) and 45 nm become available, there is an increased need for even more accurate timing analysis. Additionally with the smaller geometries there may be a number of unknown effects to electronic signal propagation that may be considered, which may not have been as severe with more relaxed process technology nodes.
USPTO Backgrounds
USPTO Backgrounds