The present invention relates to a method of manufacture of a semiconductor device. Particularly, the present invention is concerned with a technique applicable in the manufacture of a semiconductor device wherein a semiconductor chip and a wiring substrate are connected together using wire.
For allowing an IC (Integrated Circuit) chip to function, it is necessary to draw out electrical signal input and output portions to the exterior. To meet this requirement, there is known a packaging method wherein bonding pads on an IC chip (a semiconductor chip) and terminals for external connection, which are formed on a wiring substrate, are connected together using gold wires (bonding wires) and thereafter the IC chip and the gold wires are sealed with resin.
In such a packaging method, it is important to ensure a sufficient bonding strength between the gold wires and the bonding pads.
For example, Patent Literature 1 (Japanese Unexamined Patent Publication No. Hei 8(1996)-127828) discloses a technique wherein, in order to obtain a predetermined shear strength even at a reduced bonding area (bonding diameter), a thin wire is formed using a master alloy containing high purity gold and Pd (palladium) or Pt (platinum).
Patent Literature 2 (Japanese Unexamined Patent Publication No. Hei 7(1995)-335686) discloses a technique wherein gold having a purity of 99.995% or more is used as a material of a thin gold alloy wire for wire bonding and a metal such as Ca or Be is incorporated therein to improve the Young's modulus, and further, in addition to silver and copper, Pd or Pt is incorporated therein, where required, to improve the bonding strength.
USPTO Backgrounds
USPTO Backgrounds