1. Field of the Invention
The invention is related to probe testing of integrated circuits.
2. Description of Related Art
Integrated circuits offer a large number of benefits, including miniaturization of electronic devices, improved reliability, and reduced power consumption. In recent years, the density of integrated circuits has increased greatly and the number of pins of the integrated circuit packages has also increased.
The decreasing price of integrated circuits has lead to testing integrated circuits during earlier stages of the manufacturing process. By rapidly eliminating inferior products, during the manufacturing process, manufacturing costs are reduced.
Probe testing is performed prior to dicing a semiconductor wafer into individual integrated circuit chips. Probe testing requires multiple probe pins to be attached to a probe card. The probe pins contact bonding pads which are connected to internal circuits of an integrated circuit. The operation of the integrated circuit is tested through the probe pins.
The probe card is positioned for each integrated circuit (test subject) on the semiconductor wafer and the probe pins are connected to the bonding pads of the test subject. An integrated circuit test device is electrically connected to the test subject through the bonding pads testing both the electrical characteristics and operational functions of the integrated circuit. Only those integrated circuits that pass the probe testing process are packaged into final products.
The number of pins of the integrated circuits is increasing because generally the number of pins increase as technology is able to increase the number of functions performed by each integrated circuit. When the number of pins increase, the number of bonding pads of the integrated circuit increases. Since the physical dimensions of the integrated circuit chips are limited to certain values, an increase in the number of bonding pads decreases the size of the bonding pads and reduces the spaces between the bonding pads.
As the number of bonding pads increases and the size and spacing of the bonding pads decrease, the number of probe pins increases. The probe pins and the positioning gaps between the probe pins become narrower. There is a limit to the number of probe pins that can be attached to a probe card and probe cards having a large number of probe pins are costly. When the number of probe pins attached to a probe card increases, positioning the probe pins onto the bonding pads requires an ever increasing level of precision. Thus, a high level of technology is required to connect the probe card to the test subject. The technology required for integrated circuit test device that includes the probe card is also increased. Thus, the cost of the integrated circuit test device is increased.
The probe card requires personalization for each type of integrated circuit chip to be tested. A cost is associated with the personalization process which includes the labor involved. Thus, an increase in the number of probe pins attached to the probe card increases the cost of the probe card and the cost of the labor associated with personalizing and maintaining the probe card.
Japanese Patent 2-229448 (unexamined) discloses connecting input signal pad(s) with flip-flop circuit groups and between input signal pads which reduce the number of test input terminals. Japanese Patent 4-333252 discloses a technology to reduce the number of utilized pads. However, neither disclosure resolve the problems discussed above.
USPTO Backgrounds
USPTO Backgrounds