1. Field of the Invention
The present invention generally relates to a method and apparatus for surface-mounting capacitors on electronic (organic) substrates, and more particularly to a method and apparatus for reducing strain in a surface-mounted component.
2. Description of the Related Art
Electronic components, such as capacitors, are typically mounted on a substrate. For example, as illustrated in FIG. 1A, a chip 102 is mounted on a surface of a substrate 104. A plurality of capacitors 106, or other discrete electronic devices, is mounted on the surface of the substrate 104, surrounding the chip 102.
FIG. 1B illustrates a detailed description of the electronic module 100, depicted in FIG. 1A.
Typically, the substrate 104 is formed by first forming the core 108. An entire thickness of the substrate 104 may typically be, approximately 1 mm thick. Next, build-up layers 110 are formed on each of a top surface and a bottom surface of the core 108. The build-up layers typically include polymer and copper layers.
A solder mask 112 is then formed on a surface of the substrate 104. The solder mask 112 covers the substrate, except areas where it is desired to make a solder connection.
The chip (e.g., silicon chip) 102 is mounted to the substrate 104 through solder joints 114. Similarly, the capacitor 106, or other surface mount component, is mounted to the substrate by solder joints 116 and pads 118.
Capacitors that are mounted on a substrate, in accordance with the above description, however, may undergo significant thermomechanical strain. Temperature cycling produces fatigue of the solder joints or cracks in the ceramic plates of the capacitor. Accordingly, the life of the electronic package is reduced.
The electronic module is subjected to thermal cycling to evaluate the robustness of the electronic joints. FIG. 2 illustrates the sources of strain on a surface-mounted component during the thermal cycling.
First, shear stress 208 is induced in the solder joints 202, which mount the capacitor 204 to the substrate 206. The shear stress on the solder joints 202 is caused by a mismatch in coefficient of thermal expansion of the capacitor 204 and the substrate 206. Typically, the coefficient of thermal expansion for the capacitor 204 may be on the order of approximately 3 ppm, while the coefficient of thermal expansion of the substrate 206 may be on the order of approximately 20 ppm.
FIG. 3 illustrates the degree of stress 208 on the solder joints 202, the capacitor 204 and the substrate 206. The stress may also produce cracks in the substrate 206.
FIG. 4 illustrates two types of strain induced on the solder joints during thermal cycling. Both Von Mises stress and shear strain are induced on the solder joints.
Returning to FIG. 2, the mismatch in coefficient of thermal expansion also causes the substrate 206 to bend. The bending of the substrate 206 produces a tension/compression stress 210 on the solder joints 202. Additionally, while the bending may reduce the shear stress 208 on the solder joints 202, it will cause an increase in the stress placed on the capacitor 204.
Furthermore, the solder joints 202 have a coefficient of thermal expansion, which may be different from the coefficient of thermal expansion of the capacitor 204 and/or the substrate 206. This mismatch in coefficient of thermal expansion causes a localized, complex stress state 212 on the solder joints 202.
Additionally, the stress at the solder joint areas permeates the body of the electronic components, which can produce cracks that may result in functional failure.
Accordingly, prior to the present invention, there has been no method of surface mounting an electronic component, such as a capacitor, onto a substrate while reducing the effects of stress on the joints, the capacitor and the substrate.
USPTO Backgrounds
USPTO Backgrounds