1. Field of the Invention
The present invention relates generally to a bus control apparatus for use in information processing apparatus such as a personal computer, a work station, an office computer, etc., and more particularly to a bus control apparatus for optimizing the connection positions of slots through which devices are connected to a bus.
2. Description of the Related Art
Recent information processing apparatus tends to include more and more devices in the form of peripheral units such as a storage unit and an input/output unit to be connected to buses, due to the increase in type of the devices. However, the number of devices connectable to a single bus is electrically restricted, so that the bus is divided so as to have a hierarchical structure. More specifically, an upper hierarchical device bus is connected via a host bridge to a host bus connecting to a host, with a lower hierarchical device bus being connected via a bus bridge to the upper hierarchical device bus, to thereby constitute a hierarchical bus allowing the devices such as the storage unit, the input/output unit, etc., to be connected to a plurality of slots provided on the upper and lower hierarchical buses. In the case of such a conventional hierarchical bus, the positions of the slots for connecting the peripheral units to the respective hierarchical buses are fixedly mapped. For this reason, in the case where the host accesses a device connected to a slot on the lower hierarchical bus, processing time will be elongated since the access is effected from the upper hierarchical bus through the bus bridge to the lower hierarchical bus. Thus, in the case of structuring a hierarchical bus, the devices are fixedly mapped taking into consideration the upper hierarchical bus having a short access time and the lower hierarchical bus having a long access time. However, the states of the access to the devices vary depending on the applications executed by the host. Some processing may incur a concentration of accesses to the device mapped to the lower hierarchical bus, with the result that elongation of the access time may possibly lead to a low processing performance.
On the contrary, even in the case of an ordinary bus having no hierarchical structure, an electrical characteristic, for instance, a delay time of the access from the host differs depending on the positions of connections of the slots to the bus. As a result of this, a plurality of devices connected to the same bus also have different access time depending on their bus connecting positions. For this reason, in case accesses are concentrated to the device connected to the position having an insufficient electrical characteristic, the access time may be increased or an error attributable to an electrical fault may occur, which requires a retry for recovery, resulting in a lower processing performance as a whole.
USPTO Backgrounds
USPTO Backgrounds