1. Field of the Invention
The present invention relates to a package structure having a semiconductor chip embedded therein and a method for fabricating the same and, more particularly, to a package structure having characteristics of low thickness, high rigidity and enduring tenacity with a semiconductor chip embedded therein and method for fabricating the same.
2. Description of Related Art
Customer demands of the electronics industry continue to evolve rapidly and the main trends are high integration and miniaturization. In order to satisfy those requirements, especially in the packaging of semiconductor devices, development of circuit boards with the maximum of active and passive components and conductive wires has progressed from single to multiple layer types. This means that a greater usable area is available due to interlayer connection technology.
First, semiconductor chip carriers suitable for semiconductor devices are manufactured through a common semiconductor chip carrier manufacturer. Then, the semiconductor chip carrier is processed by semiconductor chip attachment, wire bonding, molding, and implanting solder ball etc. for assembling semiconductor devices. Finally, the semiconductor devices having electronic functions required by clients are completed. Because the steps of the practical manufacture are minute and complex, interfaces are not integrated easily at the time when manufactured by different fabricating proprietors. Further, if the client wants to change the design of the function, efficiency and economic benefit suffer.
In the conventional semiconductor device structure, semiconductor chips are mounted on top of a substrate, and then processed in wire bonding, or connected the chip which having the solder bump thereon to the conductive pads on the substrate, followed by placing solder balls on the back of the substrate to provide electrical connections for printed circuit board. Although an objective of high quantity pin counts is achieved, this condition is limited by way of long pathways of conductive lines making electric characteristics unable to be improved in the more frequent and high-speed operating situations. Otherwise, the complexity of the manufacture is relatively increased because too many connective interfaces are required for conventional packages.
In many studies, semiconductor chips directly conducting to external electronic devices are embedded into a package substrate to shorten conductive pathways, decrease signal loss and distortion, and increase abilities of high-speed operation.
In a carrier having a semiconductor chip embedded therein, for preventing destruction of the chip in carrier by laser drilling, as shown in FIG. 1, metal layers are added on electrode pads of an active surface of the semiconductor chip. The structure of the carrier having a semiconductor chip embedded therein includes: a carrier 11, in which a cavity is formed; a semiconductor chip 12 which is set in the cavity, and a plurality of electrode pads 13 formed on an active surface of the semiconductor chip 12; a protective layer 14 formed on the carrier 11 having the semiconductor chip 12 embedded therein, and then the a plurality of electrode pads 13 are exposed; a plurality of metal layer 15 formed on surfaces of the electrode pads 13; and a build-up structure 16 formed on surfaces of the semiconductor chip 12 and the carrier 11. The build-up structure 16 is formed on the surfaces of the semiconductor chip 12 and the carrier 11, and conducts the electrode pads 13 of the semiconductor chip 12 .
Currently, in a package structure having the semiconductor chip embedded therein, stress between the build-up structure and the non-build-up structures is not the same. Because the build-up structure is asymmetric, the metal carrier becomes warp. Under this condition, production becomes complex, and excessively warped carriers cause low yield and low stability of products.
Therefore, in order to prevent semiconductor chip-embedded carriers becoming warp due to an asymmetric build-up structure and to improve the yield of the process, carriers made of copper or bismaleimide-triazine (BT) resin already have not satisfy needs of the utilization.
USPTO Backgrounds
USPTO Backgrounds