1. Technical Field
The present invention relates generally to processors and computing systems, and more particularly, to a simultaneous multi-threaded (SMT) processor.
2. Description of the Related Art
Present-day high-speed processors include the capability of simultaneous execution of instructions, speculative execution and loading of instructions and simultaneous operation of various resources within a processor. In particular, it has been found desirable to manage execution of one or more threads within a processor, so that more than one execution thread may use the processor resources more effectively than they are typically used by a single thread.
Prior processor designs have dealt with the problem of managing multiple threads via a hardware state switch from execution of one thread to execution of another thread. Such processors are known as hardware multi-threaded (HMT) processors, and as such, can provide a hardware switch between execution of one or the other thread. An HMT processor overcomes the limitations of waiting on an idle thread by permitting the hardware to switch execution to a non-idle thread. Execution of both threads can be performed not simultaneously, but by allocating execution slices to each thread when neither are idle. However, the execution management and resource switching (e.g., register swap out) in an HMT processor introduce overhead that makes the processor less efficient than running on two single-threaded processors. In addition HMT does not allow threads to take full advantage of instruction parallelism by using multiple execution engines that are usually not all busy at the same time, since only one thread is executing at a given time.
Simultaneous multi-threaded (SMT) processors provide an even more efficient use of processor resources, as multiple threads may simultaneously use processor resources. Multiple threads are concurrently executed in an SMT processor so that multiple processor execution units, such as floating point units, fixed point instruction units, load/store units and others can be performing tasks for one (or more depending on the execution units' capabilities) of multiple threads simultaneously. Storage and register resources may also be allocated on a per-thread basis so that the complete internal state switch of the HMT is avoided.
However, at times when threads are stalled, a single-threaded processor would otherwise operate more efficiently by comparison and there are conditions under which the predictability of single-threaded execution is preferred, such as when processing must complete for a single task within an allotted time span.
It is therefore desirable to provide an SMT processor that can provide the advantages of a single-threaded processor and a multi-threaded processor. It is further desirable to provide a method and logical apparatus for managing thread execution within such a processor.
USPTO Backgrounds
USPTO Backgrounds