The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a trench.
A Deep Trench Isolation (DTI) structure in which an insulating film is embedded in a trench with a high aspect ratio is disclosed in, e.g., Japanese Unexamined Patent Publication No. 2011-151121.
In accordance with the technique described in this publication, a high-breakdown-voltage MOS transistor having a source region and a drain region in a surface of a semiconductor substrate is completed. In the surface of the semiconductor substrate, a trench is formed to surround the transistor in plan view. Over the transistor and in the trench, an insulating film is formed so as to cover the transistor from above and form a hollow in the trench.
After the DTI structure is formed as described above, an electronic element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed in the semiconductor substrate.
USPTO Backgrounds
USPTO Backgrounds