1. Field of the Invention
The present invention relates to the monolithic forming of image sensors intended to be used in shooting devices such as, for example, cameras, camcorders, digital microscopes, or digital photographic cameras. More specifically, the present invention relates to image sensors formed in CMOS technology.
2. Discussion of the Related Art
An image sensor formed in CMOS technology generally includes a matrix of photodetectors arranged at the intersection of lines and columns.
FIG. 1 schematically shows a first example of a CMOS-type photodetector. A photodiode D has its anode connected to a reference supply rail or circuit ground GND. The cathode of photodiode D is connected to a detection node SN. Two N-channel MOS transistors T1 and T2 have their drain connected to a high supply rail VDD. The source of transistor T1 and the gate of transistor T2 are connected to detection node SN. The gate of transistor T1 receives a precharge control signal PR. An N-channel MOS transistor T3 has its drain connected to the source of transistor T2. The source of transistor T3 is connected by a read terminal OUT to a read block not shown. The gate of transistor T3 receives a read control signal RD.
FIG. 2 schematically shows a second example of a photodetector of CMOS type. In addition to the elements of the photodetector of FIG. 1, the photodetector of FIG. 2 includes an N-channel MOS transistor T4. The cathode of photodiode D is connected to the source of transistor T4. The drain of transistor T4 is connected to detection node SN. The gate of transistor T4 receives a charge transfer control signal TR. The operation and the respective advantages of the photodetectors of FIGS. 1 and 2, are known.
FIG. 3 schematically shows a top view of the regions which form photodiode D and transistor T4 of FIG. 2. Photodiode D and transistor T4 are formed in a same active area of a lightly-doped P-type semiconductor substrate. The active area is delimited by an insulating area 2 which can be formed, for example, by means of a silicon oxide (SiO2). An insulated gate structure 4 of predetermined width is formed across the active area. On either side of gate 4, in the substrate surface, are N-type source and drain regions of transistor T4. The source region is formed in a much larger surface than the drain region. This N-type source region also forms with the underlying P-type substrate the photodiode junction. The source region is covered with a heavily-doped P-type layer 7 in contact with the substrate. Photodiode D then is of the so-called filly depleted type. On the top view of FIG. 3, drain region 6 can be seen on the right-hand side of gate 4 and heavily-doped P-type layer 7 can be seen on the left-hand side of gate 4. The source region, designated hereafter by reference 5, is not visible in FIG. 3.
FIG. 4 illustrates the voltage levels along axis B—B of the insulating area brought to substrate voltage 8, of source region 5 corresponding to the photodiode, of a channel area 10 located under gate 4, and of drain region 6, in different operating steps.
In an initialization step, transistor T1 is turned on and drain 6 of transistor T4 is set to voltage VDD. The gate of transistor T4 is at a high voltage VTRH and transistor T4 is on. Channel area 10 is at a voltage VTRH-VT4, where VT4 is the threshold voltage of transistor T4. The voltage across photodiode D reaches a so-called depletion quiescent level VD set by the characteristics of the photodiode. Region 5, forming the cathode of diode D, is at voltage VD.
In a light-measurement or integration step, transistors T1 and T4 are off and drain 6 of transistor T4 and the photodiode are isolated. Stray capacitances (not shown) connected to drain 6 maintain the voltage of drain 6 at VDD. Region 5 of photodiode D, which forms a potential well, fills up (hatched area α) according to the photodiode lighting. This period corresponds to the signal integration in the photodetector.
In a step of reading of the light measured by the photodiode, transistor T4 is turned on (transistor T1 being maintained off). Channel area 10 is at voltage VTRH-VT4. The charges accumulated in region 5 then are transferred to region 6, the voltage of which varies (hatched area β). The voltage variation of region 6 causes a modification of the conduction of transistor T2, which corresponds to the amount of transferred charges.
The use of a photodiode D of fully depleted type enables, as known, eliminating the initialization or precharge noise introduced by MOS transistor T1. For the photodiode to be of fully depleted type, the doping profiles are chosen so that region 5, pinched between layer 7 and substrate 8, is depleted. In the absence of any radiation, region 5, forming the photodiode cathode, is maintained at a depletion state voltage VD. Voltage VD depends on the number of charges pushed out of N-type region 5 by the depletion of region 5. Voltage VD can be adjusted by the doping profiles of layer 7, of region 5, and of substrate 8. Voltage VD is chosen, as illustrated in FIG. 4, at a value smaller than voltage VTRH-VT4 of channel 10 of transistor T4 when transistor T4 is turned on, to enable full transfer of the charges from region 5 to drain 6.
For photodiode D to properly operate, layer 7 and substrate 8 must be maintained at the same voltage, that is, there must exist a good contact between these regions. In the state of the art, layer 7 is for example in lateral contact with substrate 8, but the quality of such a lateral contact is linked to a minute adjustment of the manufacturing process, especially upon creation of region 5 and of layer 7. A modification of the manufacturing process causing a reduction in the surface area of layer 7 with respect to the surface of region 5 may damage, or even cause the disappearing of the contact between substrate 8 and layer 7, and cause a malfunction of photodiode D.
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