1. Technical Field
The present invention relates to the handling of precision workpieces, such as semiconductor wafers. More particularly, the present invention relates to the transfer of semiconductor wafers between a sealed container and a sealed processing environment.
2. Description of the Prior Art
State of the art semiconductor fabrication processes require a highly refined and expensive clean room environment to prevent foreign body contamination of the semiconductor wafers on which devices are formed. As device geometry having features of less than 0.5 .mu.m become prevalent, a clean room environment of less than class 1, i.e. an environment having less than one contaminant particle which is less than or equal to 0.5 .mu.m per 0.3 m.sup.3 (ft.sup.3) of clean room volume, is generally required. Class 1 conditions additionally require that processed or partially processed wafers must be bagged when transported to subsequent processing facilities or to outside analysis or other systems.
Micro-environments, such as are provided by the standard mechanical interface (SMIF) box of the type manufactured by Asyst Technologies, Inc. of Milpitas, Calif., are an attractive alternative to the expense, excessive handling, and exposure to contaminant particles attendant with the bagging of semiconductor wafers for transport. In the SMIF-type box, semiconductor wafers are transported and handled in small sealed containers, which deliver good contaminant particle results, while providing an industry standard interface between the base of the box and an outboard box load/unload mechanism. Various sealed containers of this type as are known in the art include those taught by Bonora et al (U.S. Pat. No. 4,995,430) and Mortensen et al (U.S. Pat. Nos. 4,709,834 and 4,582,219).
A disadvantage of the SMIF-type box is the need to purchase a special outboard SMIF box load/unload mechanism for each piece of wafer processing equipment with which a SMIF box is to be used. The purpose of such mechanism is to remove the wafers from the SMIF box and to transfer the wafers to and from the processing equipment.
An example of a prior art transfer mechanism is taught by Iwasawa et al (U.S. Pat. No. 4,826,360), in which a transfer vehicle carrying a wafer pod is shuttled through a transfer tube by application of a negative pressure within the tube. Wafer transfer from a sealed environment is also taught by Bonora et al (U.S. Pat. No. 4,995,430) which is discussed above; and by Davis et al (U.S. Pat. No. 5,044,871) in which a nonstandard bell-shaped carrier is maintained under vacuum for wafer transport. In Davis the wafers are carried upside down, which requires that the wafers be processed using unconventional techniques. Both Bonora and Davis place a sealed wafer container in a first chamber which encloses the container. Once the first chamber is sealed and evacuated, the wafer container is opened and the wafer cassette contained therein is transferred to a second chamber. Each wafer is then transferred from the second chamber to a process chamber where the wafer is processed. The wafer is then returned to the wafer cassette and the next wafer is selected and processed, and so on until every wafer in the cassette has been processed.
Thus, typical prior art wafer handling schemes involve two sealed chambers, in addition to the process chamber, each of which contains a substantial volume that must be pumped down during wafer transfer; and they require the use of outboard robot assemblies to hand off a wafer from the unload station to a robot in the process chamber. Accordingly, the teachings of Bonora and Davis provide an outboard load/unload mechanism.
The requirement of an outboard load/unload mechanism means that a relatively large portion of the available clean room area must be provided in front of the associated wafer processing equipment to accommodate both the equipment operator and the load/unload mechanism. In such situation, it may be necessary to increase the total clean room area. Any increase in clean room area adds significant cost per wafer processed. For example, a class 100 installation, which is suitable for older processing technologies, costs about $350.00/0.3 m.sup.2 (ft.sup.2), while a class 1 installation, which is required for state of the art and emerging technologies, such as for fabricating devices having 0.5 .mu.m features, costs upwards of $1250.00/0.3 m.sup.2 (ft.sup.2).
The chamber volumes associated with the SMIF box, the load/unload mechanism, and the load lock chamber of the wafer processing equipment are quite large (in current practice, 60 liters of gas must be pumped and vented for the load lock alone). Such large volumes require considerable pump down time, i.e. the time it takes to physically evacuate gases from the various chambers. These pump down times extend the cycle time of each wafer processed, limiting wafer throughput. The foregoing systems, having large chamber volumes, are also wasteful of expensive processing gases. It is especially important to note that the need for a separate piece of equipment to load wafers between a SMIF-type box and a piece of wafer processing equipment is particularly undesirable because it introduces additional processing time delays associated with the physical movement of the wafers by the load/unload mechanism. Such equipment also requires two sealed surfaces (the SMIF box seal and the processing equipment seal) and therefore is subject to an increased likelihood of introducing contaminant particles into the processing equipment, reducing device yield per wafer; and it adds a complex wafer handling mechanism that is expensive, difficult to align and maintain in alignment, such that proper wafer orientation is not always reliably achieved, and subject to wear and the need for frequent servicing, with its associated equipment (and processing) downtime.
Thus, the present state of SMIF-type box art is not well suited for modern and emerging semiconductor processing technologies as it requires an expensive, complex SMIF box interface mechanism which both exacerbates the likelihood of wafer contamination and creates a wafer throughput bottle neck, while increasing the need for expensive clean room space.
USPTO Backgrounds
USPTO Backgrounds