1. Field of the Invention
The present invention generally relates to a chip package and the fabricating method thereof, and more particularly, to a stacked chip package, an embedded chip package and a fabricating method thereof.
2. Description of Related Art
In the semiconductor industry, a chip packaging process is intended to avoid a bare chip from being affected by moisture, heat and noise and provide the bare chip with an electrical connection medium between the chip and the external circuit. In recent years, along with the update in tremendous pace for the electronic technology and the continuous integrations and renovations of the high-tech electronic products, the conventional semiconductor packaging technology is incapable of meeting the requirements of the product functions and cost. Currently, the semiconductor packaging technology has been advancing towards integrating a chip into a circuit substrate, so as to largely downsize the area/volume of a whole package and to meet the design requirements of an electronic product, such as, having light, thin and smallish figure and characterizing high performance, high speed and high density.
The major process flow for a conventional embedded chip package is to load a chip on a substrate and then a dielectric material is used to embed the chip in the package. Usually, the dielectric material is formed on a chip by a spin spreading, printing or lamination process. However, the above-mentioned process methods are likely to make the surface of the dielectric material uneven to adversely affect the successive processes. In particular, for a thicker chip, the thickness difference caused by the above-mentioned process methods would result in a poor surface evenness thereof and affect the production yield. In order to solve the unevenness problem, it is very often to use a lapping process for thinning the chip or use more dielectric material to reduce the chip surface unevenness, and then the chip may be embedded, wherein the lapping processes may increase the fabrication cost and also may damage the chip during the chip embedded processes. Thus, the fabrication cost may be further increased.
Many different schemes of the embedded chip packaging technology have been proposed. For example, Freescale Semiconductor, Inc. proposed a semiconductor packaging scheme related to an embedded chip package. Besides, in U.S. Pat. No. 6,759,270, entitled “Semiconductor Chip Module and Method of Manufacture of Same”, proposes fabricating a cavity in a substrate for embedding a chip first. Next, the chip is placed in the cavity and then dielectric material spread over the chip. Next, metal circuits and solder bonding pads are formed to complete an embedded chip package. The disadvantage of the above scheme is that an additional filler is needed to fill the gaps between the chip and the substrate, the package thickness is mainly occupied by the thick substrate and the cavity depth is hard to control.
In another U.S. Pat. No. 6,469,374, entitled as “Superposed Printed Substrates and Insulating Substrates Having Semiconductor Elements Inside”, it disclosed an embedded chip packaging process including forming a cavity for embedding a chip by superposing a plurality of hollow substrates. The disadvantage of this scheme is almost the same as the above described scheme where the package thickness is mainly occupied by the thick substrate, an additional filler is needed to fill the gaps between the chip and the substrate. Thus, it is difficult to align the substrates.
Accordingly, how to embed a chip in a circuit substrate without encountering the problems described above is an important issue for the semiconductor manufacturers.
USPTO Backgrounds
USPTO Backgrounds