1. Field Of the Invention
This invention relates to an integrated circuit device and more particularly, to an integrated circuit device designed by a standard cell design method.
2. Description of the Related Art
The layout pattern design method called a "standard cell design method" is known as one of conventional design methods of an integrated circuit device. The standard cell design method is one by which first the patterns of basic circuits such as NAND gates and flip-flops are designed to provide basic cell patterns (simply, basic cells), and then such basic cells are laid out and interconnected as required to determine a desired layout of an integrated circuit device.
An integrated circuit device whose layout is designed by the standard cell design method is described below with reference to FIGS. 1 to 3.
FIG. 1 shows a layout pattern of a basic cell 100 of an inverter circuit of a CMOS (complementary metal oxide semiconductor) integrated circuit device. The basic cell 100 is made up of two transistors 4 and 6 arranged in the Y direction, each of which is of the same size as a predetermined basic insulated gate field effect transistor (hereinafter, referred to as an MOS transistor). Other basic cells 100' each having the same circuit function and the same driving capability as the basic cell 100 are contiguous to the basic cell 100 in the X direction. A large number of basic cells are thus disposed in the X direction.
The basic cell 100 includes a p-channel MOS transistor 4 and an n-channel MOS transistor 6 connected in series. T.sub.1 denotes the cell width of the basic cell 100 in the X direction and S.sub.1 denotes the cell length of the basic cell 100 in the Y direction.
The p-channel MOS transistor 4 is composed of p-type diffusion regions 2a and 2b which become source and drain regions, respectively, and a gate electrode 3. The n-channel MOS transistor 6 is composed of n-type diffusion regions 5a and 5b which become source and drain regions, respectively, and the gate electrode 3.
The p-type diffusion region 2a as the drain region of the p-channel MOS transistor 4 is connected through a contact 7a to a signal line 8 and through a contact 7b to the n-type diffusion region 5a which becomes the drain region of the n-channel MOS transistor 6.
The p-type diffusion region 2b as the source region of the p-channel MOS transistor 4 is connected through a contact 9 to a power line 12 which is common to the basic cells 100' contiguous to the basic cell 100. The n-type diffusion layer region 5b as the source region of the n-channel MOS transistor 6 is connected through a contact 13 to aground line 14 which is common to the basic cells 100'.
An input terminal 15 is connected to a signal line 18 for connecting through a contact 17 to the common gate electrode An output terminal 16 is connected to the signal line 8. One end of the line 8 is connected through the contact 7a to the p-type diffusion region 2a and the other end thereof through the contact 7b to the n-type diffusion layer region 5a. The input terminal 15 and output terminal 16 are located each at predetermined distances in the X and Y directions from a cell center 50 which is the intersection of center lines in the X and directions.
FIG. 2 shows a layout pattern of a basic cell 200 having a driving capacity twice that of the basic cell 100. The basic cell 200 is of the same cell length S.sub.1 as the basic cell 100, but is of cell width T.sub.2 wider than the cell width T.sub.1 of the basic cell 100. The basic cell 200 includes two transistor regions. 24 and 26 arranged in the Y direction. The basic cells 100' shown in FIG. 1 are contiguous to the basic cell 200 in the X direction.
In the transistor region 24, one p-channel MOS transistor is composed of a p-type diffusion region 22a which becomes a drain region, a p-type diffusion region 22b which becomes a source region, and a gate electrode 23a. The other p-channel MOS transistor is composed of the p-type diffusion region 22a which becomes a drain region, a p-type diffusion region 22c which becomes a source region, and a gate electrode 23b.
In the transistor region 25, one n-channel MOS transistor is composed of an n-type diffusion region 26a which becomes a drain region, an n-type diffusion region 25b which becomes a source region, and the gate electrode 23a. The other n-channel MOS transistor is composed of the n-type diffusion region 25a which becomes a drain region, an n-type diffusion region 25c which becomes a source region, and the Gate electrode 23b.
The p-type diffusion region 22a is connected through contact 7a to signal line 8 and through a contact 7b to the n-type diffusion region 25a.
The p-type diffusion regions 22b and 22c are respectively connected through contacts 9a and 9b to a power line 12 which is common to the basic cells 100' contiguous to the basic cell 200. The n-type diffusion regions 25b and 25c are respectively connected through contacts 13a and 13b to a ground line which is common to the basic cells 100'.
An input terminal 15 is connected to the signal line 18 for connecting through a contact 17 to the gate electrodes 23a and 23b. An output terminal 16 is connected to the signal line 8. One end of the line 8 is connected through the contact 7a to the p-type diffusion region 22a and the other end thereof through the contact 7b to the n-type diffusion region 25a.
To use the standard cell design method for laying out an integrated circuit device, if the basic transistor size is determined and a plurality of the basic transistors are aligned in one direction to form the basic cell, the height of the basic cell, layout of the power line for supplying power to the basic cells, and layout of an impurity-doped regions within the basic cell, or the like can be standardized and layout design of an integrated circuit device can be automated efficiently.
In this case, it is necessary to provide a large number of types of the basic cell not only by circuit function to cover any layout design of integrated circuit devices, but also by load driving capability to cover any timing design, such as the basic cells 100 and 200.
For layout design, the basic cell 100 having the same driving capability as a basic MOS transistor is selected for a part of light load to suppress power consumption of an integrated circuit device and the basic cell 200 having a driving capability higher than the basic MOS transistor is selected for a part of heavy load to prevent the maximum operation frequency of the integrated circuit device from deteriorating.
However, after layout of the integrated circuit device is designed, the basic cell 100 to which a larger wiring load is assigned due to the actual layout pattern is replaced with the basic cell 200 having the same circuit function and higher driving capability, and a part or the entirety of the wiring layout is modified according to the replacement.
Generally, the signal delay time and power consumption of integrated circuit device depend on the performance of the basic cells themselves constituting the integrated circuit device and the pads given to the output terminals of the basic cells. When the basic cells are allocated and wired automatically as described above, the locations and signal wiring length of the basic cells are not determined until pattern design is complete, thus the signal delay and power consumption which depend on the load given to the output terminals of the basic cells cannot accurately be known. As a result, even if the driving capability of the basic cells is optimized at the logical design stage, the target performance of the integrated circuit device at the beginning may often be unable to be guaranteed for the actual device.
Therefore, if after layout of an integrated circuit device is designed, wiring load depending on the actual layout pattern is also considered to evaluate the performance of the integrated circuit device, and the basic cells deteriorating the performance are specified for replacement with other basic cells having the same circuit functions and different load driving capabilities, optimum design of the integrated circuit device is enabled.
However, there are the following problems in the conventional layout design method.
FIG. 3A shows the state of the basic cell 101 to which larger wiring pad is assigned after completion of layout design using the basic cells 102 and 103. FIG. 3B shows a layout pattern after the basic cell 101 is replaced with the basic cell 101' having the high driving capability and same wiring is modified.
As shown in FIGS. 3A and 3B, the cell width of the basic cell 101 having the same driving capability as the basic transistor is two cell units, whereas the cell width of the basic cell 101' having the driving capability twice that of the basic transistor is three cell units. Therefore, a mismatch of cell width occurs between the basic cells 101 and 101'.
Besides, since the basic cells 101 and 101' which differ in relative positions of the input and output terminals within the cells are replaced, signal lines 27 between the basic cells are required to be moved from the first location shown in FIG. 3A to the location shown in FIG. 3B after replacement. The location of the signal lines 27 between the basic cells disposed in FIG. 3A is indicated by the dot lines in FIG. 3B.
Thus, if the basic cells 101 and 101' replaced differ in cell width and positions of the input and output terminals, reallocation and rewiring of the basic cells have an effect on not only the basic cells to be replaced, but also other basic cells 102 and 103 constituting the integrated circuit device.
Therefore, the basic cells are required to be again allocated and wired for the entire integrated circuit device from the beginning, and it takes long time to complete the final layout pattern.
USPTO Backgrounds
USPTO Backgrounds