The disclosed invention generally relates to hybrid microcircuit bonding structures and techniques, and is more particularly directed to a repairable hybrid substrate architecture that allows for removal and replacement of bump bonded integrated circuit chips or dies.
In the fabrication of microelectronic circuitry, bump bonding techniques are utilized, for example, to bond and conductively connect integrated circuit microelectronic chips (sometimes called flip-chips) to hybrid circuit substrates which typically include interconnecting conductors and may include circuit elements as well. The number of integrated circuit chips bonded to a given substrate may be 100 chips, for example.
Bump bonding techniques generally involve the deposition of conductive bonding bumps of an appropriate material, such as indium, on the chips and the substrate in mirror image patterns. The bumps are attached by cold weld or reflow techniques, and thus function to bond the chips to the substrate. The bumps further function as conductors for conductively connecting the integrated circuit chips to the substrate conductors.
Bump bonding techniques offer advantages over other bonding techniques such as wire bonding and reflow soldering techniques. These advantages include more efficient fabrication processes, increased circuit density, shorter conductive paths, and the flexibility of locating bonding pads at locations other than at the edges of an integrated circuit chip.
However, chips bonded by bump bonding techniques are not designed for ease of replacement. While a given chip can be pried from the substrate, conventional bonding sites on the substrate contacts cannot be reused to accommodate a replacement chip. As a result, if any chip of a bump bonded hybrid is faulty, then the entire hybrid must be discarded. Such chip failures can be very costly, particularly when failures occur in hybrids that have many chips. Of course, the integrated circuit chips can be tested prior to bonding, but such testing can be costly, inefficient, and cumbersome in comparison to testing the completed hybrid circuit. Moreover, pre-testing of the chips is no guarantee that all the tested chips will not fail at a later time.
For purposes of background reference, a conventional indium bump bonding system and method is described in U.S. Pat. No. 4,573,627, issued to Miller et al. U.S. Pat. No. 4,567,643, issued to Droguet et al., describes a method of replacing an electronic component connected to conducting tracks on a support substrate, wherein the replacement is performed by cutting the tracks and replacing them with new tracks while leaving the tip of the track in place. U.S. Pat. No. 3,735,911, issued to Ward, discloses a tool for repairing integrated circuit chips, but does not appear to address the repair of components fabricated with bump bonding techniques. U.S. Pat. No. 3,969,813, issued to Minetti et al., and U.S. Pat. No. 4,012,832, issued to Crane, relate to nondestructive removal of semiconductor devices or parts thereof, but do not address the repair of circuits fabricated using bump bonding technology.
USPTO Backgrounds
USPTO Backgrounds