In recent years, digital processing of an analog television broadcast receiving device is advancing simultaneously with the advance of semiconductor technology, and particularly, importance is placed on realization of digital processing of the receiving device by a common device independently of the broadcast system (NTSC, PAL, SECAM, etc.).
Hereinafter, a conventional burst lock circuit will be described with reference to FIGS. 4 to 8.
FIG. 4 is a block diagram illustrating the whole construction of a video demodulation apparatus.
With reference to FIG. 4, the video demodulation apparatus 401 comprises a video signal input terminal 402, an A/D converter 403, a YC separation apparatus 404, a chrominance signal demodulation apparatus 405, a luminous component signal output terminal 406, an R-Y signal output terminal 407, and a B-Y signal output terminal 408.
A video signal S402 inputted through the video signal input terminal 402 of the video demodulation apparatus 401 is input to the A/D converter 403 in the video demodulation apparatus 401. In the A/D converter 403, the video signal S402 as an analog signal is converted into a digital signal according to a timing of a clock signal S405 outputted from the chrominance signal demodulation apparatus 405. The clock signal S405 is synchronized with a burst signal that exists in a back porch of the video signal S402, and it has a frequency twice or more as high as that of the burst signal, according to the sampling theorem of Nyquist. It is assumed that a clock signal S405 having a frequency four times as high as that of the burst signal is generated.
Next, the digital signal obtained by digitizing the video signal outputted from the A/D converter 403 is input to the YC separation apparatus 404.
In the YC separation apparatus 404, the digital signal outputted from the A/D converter 403 is separated into a luminous component signal S404y and a chrominance component signal S404c which are multiplexed in the video signal. The luminous component signal S404y is output to the outside of the video demodulation apparatus 401 through the luminous component signal output terminal 406. On the other hand, the chrominance component signal S404c separated by the YC separation apparatus 404 is output to the chrominance signal demodulation apparatus 405. Generally, the YC separation circuit is composed of a comb filter or a notch filter, and a band-pass filter.
In the chrominance signal demodulation apparatus 405, a clock S405 synchronized with the burst signal is generated and supplied to the A/D converter 403 and the YC separation apparatus 404. Further, the chrominance component signal S404c outputted from the YC separation apparatus 404 is separated into an R-Y component signal and a B-Y component signal. Thereafter, the R-Y component signal S407 and the B-Y component signal S408, which are separated by the chrominance signal demodulation apparatus 405, are output to the outside of the video demodulation apparatus 401 through the R-Y signal output terminal 407 and the B-Y signal output terminal 408, respectively.
Next, the internal structure of the chrominance signal demodulation apparatus 405 shown in FIG. 4 will be described in more detail.
FIG. 5 is a block diagram illustrating the construction of the conventional chrominance signal demodulation apparatus. The chrominance signal demodulation apparatus is aimed at receiving an NTSC system video signal.
In FIG. 5, the chrominance signal demodulation apparatus 405 comprises a chrominance component signal input terminal 500, a burst gate pulse input terminal 503, a loop filter 51, a chrominance signal multiplexing circuit 52, an R-Y output circuit 53, a B-Y output circuit 54, a 4FSC clock output terminal 513, an R-Y signal output terminal 518, and a B-Y signal output terminal 519.
The chrominance signal demodulation apparatus 405 is provided with the chrominance component signal input terminal 500, and a multiple-bit digitized chrominance component signal S404c is output to the loop filter 51 through the chrominance component signal input terminal 500.
The loop filter 51 generates a clock signal which is synchronized with the burst signal and has a frequency N times (N: integer not less than 2) as high as that of the burst signal. It is assumed that a clock signal S405 having a frequency four times as high as that of the burst signal is generated. The loop filter 51 comprises, as shown in FIG. 5, a latch circuit 501 comprising a group of flip-flops, a gate circuit 502, an LPF 504, a constant generation circuit 505, an addition circuit 506, a ramp generation circuit 507, a sinusoidal ROM 508, a D/A converter 509, a LPF 510, a 4 frequency multiplying circuit 511, and a ¼ frequency-division circuit 512.
The L/H terminals of the flip-flops constituting the latch circuit 501 are supplied with a signal which is obtained by subjecting the clock signal S405 that is outputted from the 4 frequency multiplying circuit 511 and has a frequency four times as high as that of the burst signal, to ¼ frequency-division by the ¼ frequency-division circuit 512, i.e., a signal having the same frequency as that of the burst signal, through the gate circuit 502. The gate circuit 502 performs a logical operation on the burst gate pulse inputted through the burst gate pulse input terminal 503 and the signal having the same frequency as that of the burst signal, which is output from the ¼ frequency-division circuit 512, so that the signal is supplied to the L/H input terminals of the flip-flops at only the timing of the burst signal.
The latch circuit 501 latches only the burst signal portion of the chrominance component signal S404c with the same cycle as the burst signal at the timing in which the signal is supplied to the L/H inputs of the flip-flops constituting the latch circuit 501. This eventually leads to sampling of the phase errors during burst lock.
Thereafter, the phase error components during burst lock, which are sampled by the latch circuit 501, are sent to the LPF circuit 504.
The LPF circuit 504 is a cumulative integration circuit, and integrates the phase error components which are sampled at the burst portion of the chrominance component signal S404c. If no phase error has occurred, the output of the LPF circuit 504 is zero, and the burst signal and the signal having the same frequency as the burst signal, which is output from the ¼ frequency-division circuit 512, are in complete agreement with each other in frequency and phase, resulting in burst lock.
The constant generation circuit 505 determines a center frequency for PLL operation. The constant generation circuit 505 outputs the center frequency when the output of the LPF 504 is non-zero, and outputs a constant value in accordance with the frequency of the burst signal when the output of the LPF 504 is zero, i.e., burst lock is carried out.
Further, the addition circuit 506 generates a value which is the sum of the phase error-components accumulated in the LPF 504 and the output of the constant generation circuit 505, and outputs the value to the ramp generation circuit 507. The ramp generation circuit 507 changes the inclination of the ramp waveform according to the output value from the addition circuit 506. For example, the larger the output value from the addition circuit 506 is, the steeper the inclination of the ramp becomes. Conversely, the smaller the value is, the gentler the inclination of the ramp waveform becomes.
The output from the ramp generation circuit 507 is connected to the addresses of the sinusoidal ROM 508. For example, assuming that there are n (0, 1, 2, 3, . . . n) addresses of the sinusoidal ROM 508, the output from the ramp generation circuit 507 corresponds to a sinusoidal function. That is, assuming that the address input to the ramp generation circuit 507 is “x” that is an arbitrary integer from 0 to n and its output is “y”, the ramp generation circuit 507 outputs a value that is obtained by converting “y=sin(2πx/n)” to a digital value. The address inputted to the sinusoidal ROM 508 is reproduced with its sinusoidal wave being a digital value because the output of the ramp generation circuit 507 is a ramp. Further, when the output of the LPF 504 is non-zero, the phase can be varied to make the output zero by controlling the inclination of the ramp waveform, whereby the frequency of the output from the sinusoidal ROM 508 is varied.
Thereafter, the digital output from the sinusoidal ROM 508 is converted into an analog waveform by the D/A converter 509, and discrete noise components are removed by the LPF 510 from the output waveform of the D/A converter 509.
In the above-mentioned construction, it is possible to generate, as an output from the LPF 510, a burst lock clock having the same frequency and phase as those of the burst signal.
Then, the output from the LPF 510 is input to the frequency multiplying circuit 511, multiplied by four times, and output to the ¼ frequency-division circuit 512, the 4FSC clock output terminal 513, and the selector 515.
The ¼ frequency-division circuit 512 subjects the clock signal S405, which is output from the 4 frequency multiplying circuit 511 and has a frequency four times as high as that of the burst signal, to ¼ frequency-division to convert the signal into a signal having the same frequency as the burst signal, and thereafter, outputs the signal to the gate circuit 502.
Further, the 4FSC clock which is output from the multiplying circuit 511 and has a frequency four times as high as that of the burst clock is supplied from the 4FSC clock output terminal 513 to the A/D converter 403 and the YC separation apparatus 404, as shown in FIG. 4.
Next, the chrominance signal multiplexing circuit 52 separates the chrominance component signal supplied from the chrominance component signal input terminal 500 into an R-Y component signal and a B-Y component signal on the basis of the clock signal outputted from the loop filter 51, and outputs a signal in which the R-Y component signal and the B-Y component signal are multiplexed at alternate timings. The chrominance signal multiplexing circuit 52 is composed of a selector 515 and an inverter circuit 514 as shown in FIG. 5.
Hereinafter, the processings to be performed by the inverter circuit 514 and the selector 515 will be described in more detail.
In the NTSC or PAL broadcasting system, since the phase-modulated chrominance component signal S404c is transmitted, the carrier signal can be expressed as a sinusoidal wave as follows:Cin=R·sin{2πfsc*t+φ(t)}  (1)wherein fsc is the frequency of the burst signal (i.e., so-called sub-carrier frequency), and R is the amplitude. Further,ωsc=2πfscholds. Assuming that the sampling frequency in the A/D converter 403 shown in FIG. 4, i.e., the clock signal S405 is fs,4fsc=fsholds, and the sampling cycle T can be expressed byT=1/fs
Moreover, since the video modulation unit 401 operates at a frequency four times as high as that of the burst clock, the respective sample points can be expressed byt=4nT,(4n+1)T,(4n+2)T,(4n+3)T
When the data of the first sample point is substituted into formula (1),
      R    ⁢                  ⁢    sin    ⁢          {                                    ω            sc            *                    ⁡                      (                          4              ⁢              nT                        )                          +                  ϕ          ⁡                      (                          4              ⁢              nT                        )                              }        =            sin      ⁢              {                              2            ⁢            π            ⁢                                                  ⁢                          f              sc              *                        ⁢            4            ⁢                          n              /              4                        ⁢                          f              sc                                +                      ϕ            ⁡                          (                              4                ⁢                nT                            )                                      }              =                  sin        ⁢                  {                                    2              ⁢              n              ⁢                                                          ⁢              π                        +                          ϕ              ⁡                              (                                  4                  ⁢                  nT                                )                                              }                    =              R        ⁢                                  ⁢                  sin          ⁡                      (                          ϕ              ⁡                              (                                  4                  ⁢                  nT                                )                                      )                              holds, and the term “ωsc” disappears.
Likewise, when the data of the second sample point is substituted into formula (1),R sin{ωsc*(4n+1)T+φ((4n+1)T)}=R sin{ωsc*4nT+ωsc*T+φ((4n+1)T)}holds, and the first term in “Sin” becomes 2nπ, and the second term becomesωsc*T=2πfsc/4fsc=π/2and therefore,=R cos{φ((4n+1)T)}is obtained.
The above-mentioned formulae are summarized as follows:                the first sample point=R sin(φ(4nT))        the second sample point=R cos(φ((4n+1)T)) and the data at the first sample point changes to the same function format as the input signal (1), and the data at the second sample point changes to the cosine function.        
Likewise, the third and fourth sample points are expressed as follows:                the third sample point=−R sin(φ((4n+2)T))        the fourth sample point=−R cos(φ((4n+3)T))and the data at the third sample point has a sign opposite to that of the input signal (1). Further, the data at the fourth sample point has a sign opposite to that of the input signal (1), and changes to the cosine function.        
In summary, it is possible to obtain an output signal having the same format of trigonometric function as the input signal which is a sinusoidal function, and excluding the carrier signal, by employing only the first and third sample points for the input signal. On the other hand, it is possible to obtain an output signal having a format of cosine function the phase of which is shifted by 90 degrees with respect to the input signal of the sinusoidal function, and excluding the carrier signal, by employing the second and fourth sample points.
Since demodulation for the phase-modulated NTSC system signal is controlled so that the sample data value corresponding to the first sample point of the burst signal becomes zero in the loop filter 51, the selector 515 outputs the first and third sample data as the R-Y component signal, and the second and fourth sample data as the B-Y component signal. At this time, the inverter circuit 514 operates to invert the signs of the data values at the third sample point and the fourth sample point, i.e., the sign of the data value at the first sample point is matched to the sign of the data value at the third sample point, and the sign of the data value at the second sample point is matched to the sign of the data value at the fourth sample point.
Thereby, the R-Y component signal and the B-Y component signal are multiplexed at alternate timings and outputted from the selector 515.
Thereafter, the R-Y component signal and the B-Y component signal which are outputted from the selector 515 at alternate timings are output to the outside of the chrominance signal demodulation apparatus 405 from the R-Y signal output terminal 518 and the B-Y signal output terminal 519 through the R-Y output circuit 53 and the B-Y output circuit 54, respectively.
FIG. 6 is a diagram for supplementary description. In FIG. 6, the abscissa shows the phase of the B-Y signal, and the ordinate shows the phase of the R-Y signal. In the NTSC system, as shown in FIG. 6, the phase of the burst signal is perpendicular to the R-Y axis and parallel to the B-Y signal.
As described above, when the construction of the conventional chrominance signal demodulation apparatus is employed, the B-Y axis is parallel to the burst signal while the R-Y axis is perpendicular to the burst signal.
The above-described construction has the following problems.
The first problem is as follows. That is, although the conventional chrominance signal demodulation apparatus can burst-lock the NTSC system signal, it cannot burst lock the PAL system signal.
The reason will be explained with reference to the phase of the PAL burst signal shown in FIG. 7. In FIG. 7, the abscissa shows the phase of the B-Y signal, and the ordinate shows the phase of the R-Y signal.
As shown in FIG. 7, in the PAL system, the phase of the burst signal is shifted for each line when it is transmitted. Therefore, even if the input signal is burst locked to match its phase to the phase of the burst signal 601 in the first line, the phase of the burst signal in the next line is shifted in the direction 602. So, in the above-mentioned conventional chrominance signal demodulation apparatus, stable pull-in characteristics cannot be secured, and demodulation of the PAL system signal cannot be carried out.
Further, in order to realize reception and demodulation of a NTSC system signal and a PAL system signal using a common device, a special unit for the PAL system should be prepared independently of the conventional NTSC system demodulation unit. However, when such independent PAL unit is provided, the circuit scale of the unit is simply increased, and the purpose of realizing a reduced circuit scale using the common device cannot be achieved.
Further, the second problem is as follows. Even if the phase of the burst signal can be made parallel to the phase axis of the R-Y signal in some way like in the case of the NTSC system under the state where the PAL system signal is being received, since the phase axis of the PAL burst signal is shifted by 90° for each line, it becomes necessary to accurately detect the orientation of the phase of the burst signal which changes for each line.
To be specific, even under adverse environments such as weak electric field or level compression of the burst signal, since the NTSC system signal just holds the same phase information for every line, normal demodulation can be carried out by only holding the phase information of the previous-line even in an abnormal situation where burst lock is released in a specific line. On the other hand, in the PAL system, since the phase of the burst signal is shifted by 90° for every line as described above, the phase information must be accurately detected. Especially, the orientation of the phase of the burst signal, i.e., the phase information as to whether the R-Y component signal of the burst signal is in the positive direction or in the negative direction, must be accurately detected. If the signal polarity, which is called a line ident signal, cannot be accurately detected, chrominance horizontal noise or the like undesirably appears on a screen of a television receiver or the like.
Further, the third problem is derived from a copy guard pulse that is inserted in a vertical blanking period of a medium such as a video decoder or a DVD device in recent years.
To be specific, although demodulation of the chrominance signal is carried out with reference to the burst signal, if a copy guard pulse is inserted in the medium, the sync separation circuit might malfunction to miss the timing when the burst signal exists. Thereby, particularly the possibility of improper detection of the line ident information is increased. Therefore, a countermeasure circuit against the case where the copy guard pulse is inserted in the medium must be further provided in the apparatus.
USPTO Backgrounds
USPTO Backgrounds