1. Field of the Invention
The present invention relates to a flat pulse generator (FPG) which can be used as a reference signal source for high-speed pulses and also as a calibration signal source for a digitizing oscilloscope, a linear LSI test system, or the like.
2. Description of the Prior Art
In recent years, the demand has been growing for high-speed and accurate measurement systems for the testing of high-speed D/A converters and the like. Although D/A converters with settling times as low as 1 ns are known, there is currently no measuring instrument which can satisfactorily measure the signals that settle at such high speeds in such devices, especially the high-speed settling signals that settle in less than 1 ns, with an accuracy of more than 8 bits. In such a circumstance, a signal that can be used as a reference is needed to enhance the accuracy of the conventional high-speed measuring instrument. However, such a signal must rise or fall in an extremely short time and then settle extremely rapidly.
The rising time of conventional instruments for measuring high-speed signals is quite short, for example, as short as 300 ps for an oscilloscope and some tens of picoseconds for a sampling type oscilloscope. However, such prior art oscilloscopes have an accuracy of only 6-8 bits of resolution. Moreover, the accuracy for such high speed operation is usually not specified on such oscilloscopes.
A conventional high speed flat pulse reference generator in accordance with the NBS standard is described in IEEE Transactions on Instrumentation and Measurement, Vol. IM-32, No. 1, pp. 27-32 (March 1983). Such an FPG has a transition duration of 600 ps, and it dampens all perturbations to less than .+-.10 mV within 5 ns. Improved versions of this FPG are disclosed in Japanese Patent application Nos. Showa 61-205627 and Showa 62-20992, filed by Yokagawa-Hewlett-Packard, Ltd. In addition, logic circuits using GaAs MESFETs (MEtal Semiconductor Field Effect Transistors) such as those disclosed by Katsu et al. in Shingaku Gihou SSD 81-83, in a paper entitled "GaAs IC High-Speed Frequency Divider Using Low-Power Source Coupled FET Logic SCFL)", Matsushita Electronics Corp., pp. 29-36 (an English paper with similar contents is IEEE Transactions on Electron Devices, Vol. ED-32, No. 6, pp. 1114-1118 (June, 1985), entitled "A Source Coupled FET Logic--A New Current-Mode Approach to GaAs Logics", by Katsu et al.), have been used as high-speed pulse circuits. The SCFL logic circuit described in these papers has a source follower circuit that acts as a level shifter for the drain voltage of one of the FETs to provide the level-shifted drain voltage as the output of the logic circuit. However, because these circuits are intended only for high-speed operation, these circuits have not been designed to generate a waveform necessary for use as the aforementioned reference signal.
Prior art FPGs of the type disclosed in the above-mentioned papers employ a diode clamper to shorten the rise time and to flatten the waveform after it rises. For this reason, only one of the two output levels of the FPGs can be flattened. As a result, only this flattened level can be used as the pulse reference. However, since the rise time of the output pulse depends on the input signal to the diode clamper, any input signal with a very high rising or falling speed may produce a significant amount of leakage due to its steep portion through the capacitance of the clamp diode.
Methods of analyzing a system using the output from an FPG of this kind as a calibration signal are disclosed, for example, in Japanese Patent application Nos. Showa 61-239737 and Showa 62-140614. These methods, however, present a serious problem. In particular, although a fast Fourier transform is the most effective as well as necessary means for signal analysis in the frequency domain, a pulse signal having only one flat level cannot be directly used because of the nature of a fast Fourier transform. Therefore, the prior art provides some modifications such as splicing the pulse signal in a pseudo manner with a signal the other side of which is of a flat level. An example of such techniques can be found in an article by Shaarawi et al. in IEEE Transactions on Instrumentation and Measurement, Vol. IM-34, No. 4, pp. 537-540 (December 1985), and entitled "Spectrum Amplitude of Step-Like Waveforms Using the Complete-FFT Technique". However, this method can introduce some error due to the splicing technique.
USPTO Backgrounds
USPTO Backgrounds