1. Field of the Invention
The present invention relates to test pattern generation and execution by environment emulation. In particular, the present invention relates to emulation of an integrated circuit device and its intended operating environment to facilitate generation of test patterns having improved fault-detection coverage.
2. The Prior Art
Integrated circuit (IC) device fabrication prior to thorough design verification is no longer acceptable as the cost of first-article fabrication continues to climb. This problem was addressed in the last two decades by circuit-level simulators, then by switch-level simulation, then gate-level, then register-transfer-level, behavioral, and now mixed-mode simulators which combine the best features of all. But still the time required to create and explore a complex design remains the biggest development cost.
Simulations using best available technology run hours, even days, and only exercise these complex devices in a very rudimentary way. Device after device is released into the marketplace with performance :flaws not detected by simulation, not because the simulation was inaccurate but because it did not contain the conditions required to exhibit these flaws.
Test patterns derived from logic designs, particularly those which are created automatically from structure presented by the design file, in principle cannot discover such logic errors. Testability is addressed. Controllability and observability are enhanced. Even test coverage can be assessed accurately enough with weeks of ever less expensive CPU time. But the answer to the key question, whether the device does what it should, remains elusive.
The traditional approach answers this question by building the device and checking it out, in the system. All the costs of system prototype assembly are thus risked on unproven designs.
USPTO Backgrounds
USPTO Backgrounds