This invention relates to a semiconductor integrated circuit device (hereinbelow termed "IC") having a high density of integration and a method of manufacturing it.
New isolation techniques suited to render ICs high in the density of integration are being developed in large numbers. Many of them utilize the (isotropic) reactive ion etching in which side etching is scarcely involved (refer to "NIKKEI ELECTRONICS", Mar. 29, 1982, pp. 90-101).
Such isolation technique itself is applicable to not only bipolar ICs, but also MOSICs. It can have its merits exploited, especially in the bipolar ICs which require deep isolation regions. In the following, therefore, description will be centered on the bipolar ICs, but is not limited thereto.
As one of the isolation techniques of the specified type, there is a method in which the part of a semiconductor body to become an isolation region is cut to form a groove, whereupon the groove is filled up by employing an insulating material, such as SiO.sub.2, or polycrystalline silicon, as a burying material. A concrete expedient for filling up the groove part with the burying material is as stated below. On the whole surface of the semiconductor body formed with the groove, the burying material is deposited to be thick. Subsequently, the whole surface is etched and flattened, thereby to remove the excessive burying material.
In an IC, in laying out various elements such as transistors, a large isolation region for forming wiring is inevitably set in a selected part of a chip, particularly the peripheral part thereof. This poses the problem of the flattening of the surface of that part. The isolation region part which is narrow compared to its depth is not very serious because the groove is almost filled up. In contrast, regarding the isolation part which is wide compared to its depth, unavoidably a large hollow develops on the surface even after the deposition of the burying material. A process which is necessary for further flattening such surface is considerably complicated. Therefore, a process for forming the whole device becomes complicated and forms a serious difficulty in the aspect of production.
As a measure for solving such difficulty in the aspect of production, the inventors studied a method in which the width of the aforementioned groove is set at a substantially constant small value within a range of, e.g., about 1.0-2.5 .mu.m, in relation to the resolving power of photolithography, etc. The reason that this solves such difficulty is that, with the CVD (Chemical Vapor Deposition) for depositing the burying material, the narrow groove is readily filled up because the burying material is piled up also from the side surfaces of the groove.
On the other hand, however, in the case where the width of the groove for electric isolation is rendered constant, e.g., at a substantially small value, wiring must be formed on the inactive area of a semiconductor body (the area where no semiconductor element is formed). The inactive area is not covered thereon with a thick insulating film as obtained by the use of the isoplanar technique. With such wiring structure, accordingly, the wiring capacitance between the wiring and the semiconductor body becomes large, resulting in the problem that the electric characteristics of the device worsen, namely, that the signal propagation is delayed.
USPTO Backgrounds
USPTO Backgrounds