Memory cells are frequently used in integrated circuits. They often take a large fraction of integrated circuit area. Consequently, significant amount of effort is usually spent to minimize the area of a memory cell while meeting the required performance and yield targets of the memory cell. Typically, this involves not only the memory cell development but also the integrated circuit process development, since the area, performance, and yield of the memory cell strongly depend on the capability and variation of the integrated circuit process.
Memory cell characterization provides critical feedbacks regarding the health of the memory cell and associated integrated circuit process. It is essential for the development of memory cells in integrated circuits as well as for the development and monitoring of the integrated circuit process supporting the memory cells. A correct characterization of a memory cell is also essential for the optimum design of an integrated circuit comprising the memory cell.
A relatively complete characterization of a memory cell requires measuring a plurality of characteristics of (a) the memory cell and (b) the circuit elements of the memory cell. For example, a relatively complete characterization of a standard 6T static random access memory (SRAM) cell may require measuring more than ten characteristics including minimum write voltage, minimum and maximum read voltages, minimum data-retention voltage, read currents, trip voltages, active and standby static noise margins, and characteristics of each of the six transistors. As local variation becomes increasingly important with scaling, there will be asymmetry in nominally symmetric memory cells; therefore, each of the characteristics must be characterized for each state of the cell (store ‘1’ and store ‘0’).
Currently, a relatively complete characterization of a memory cell depends on several test structures, each for measuring one or a subset of the required plurality of characteristics. For example, a relatively complete characterization of a standard 6T SRAM cell may depend on nine different test structures including (a) a full-cell test structure for measuring minimum write voltage, minimum and maximum read voltages, minimum data-retention voltage, read currents, and trip voltages, (b) two half-cell test structures for measuring active and standby static noise margins, and (c) six transistor test structures for measuring the characteristics of the six transistors.
With current technologies, two similar transistors even in similar environments will have different characteristics due to random variation. Thus the use of different test structures to characterize the various characteristics of (a) a memory cell and (b) the circuit elements of the memory cell has inherent deficiencies. The characteristics measured in different test structures can not be correlated because of local random variation. Also, the local mismatch information of the circuit elements of the memory cell cannot be obtained.
Therefore, the current approach to memory cell characterization limits the usefulness of the measurements for memory cell development and for integrated circuit process development and monitoring.
USPTO Backgrounds
USPTO Backgrounds