The present invention relates generally to a CMOS (Complementary Metal-Oxide Semiconductor) dynamic logic structure, and more particularly to a high-speed four-phase CMOS dynamic logic structure which has an operation speed higher than the prior art, and can avoid the charge redistribution and clock-skew race problems.
Recently, CMOS dynamic logics have been widely applied to the high-performance VLSI (Very Large-Scale Integration) products, such as the pipelined multiplier, etc. In the VLSI, the most important subject is how to accelerate the operation speed. The operation speed of the VLSI depends on the operation speed of the processing element, i.e. the basic logic gate. In order to improve the operation speed, many CMOS dynamic logic structures usually suffer from some problems, e.g. the charge redistribution and clock-skew race. Also, there is still a strong desire existed in this art to further improve the operation speed of the CMOS dynamic logic.
Referring to FIG. 1, there is shown a conventional four-phase CMOS dynamic logic structure which includes a plurality of logic gates, for example four logic gates 10, 11, 12, and 13. Each logic gate is considered of a PMOS (P-type Metal-Oxide Semiconductor) transistor, two NMOS (N-type MOS) transistors, and a logic tree block N, all being stacked together. The logic tree blocks N are used to realize the logic function. All of the PMOS and NMOS transistors are respectively controlled by four kinds of clocks .phi.1, .phi.2, .phi.3, and .phi.34 as shown in FIG. 2. As clearly shown in FIG. 1, the control clocks of the logic gate 10 is identical to those of the logic gate 12 while the control clocks of the logic gate 11 is identical to those of the logic gate 13. In this art, the logic gates 10 and 12 are generally defined as the type-1 logic gate, and the logic gates 11 and 13 are defined as the type-3 logic gate. In this four-phase CMOS dynamic logic structure, the type-1 and type-3 logic gates are alternately connected in series, and the circuit has three operation phases, i.e. the precharge (or P), evaluate (or E), and hold (or H) phases. The operation phases of the type-1 and type-3 logic gates respectively in the clock intervals T1 to T4 and T1' to T4' of FIG. 2 are listed in Table I, and repeated every four clock intervals.
TABLE I ______________________________________ T1 T2 T3 T4 T1' T2' T3' T4' ______________________________________ Type-1 P E H H P E H H Type-3 H H P E H H P E ______________________________________
In this conventional CMOS dynamic logic structure, if the clock .phi.12 is skew (for example, the dashed lines shown in FIG. 2 illustrate the skew phenomenon of the clock .phi.12), a clock-skew race problem happens. Referring to FIGS. 1 to 3, the clock-skew race problem will be described in detail hereinafter. FIG. 3 is the transient simulation results of FIG. 1 wherein the circuit is a shift register, and shows the voltage variations of four control clocks .phi.1, .phi.12, .phi.3, and .phi.34, and five nodes V.sub.in, V.sub.2, V.sub.3, V.sub.4, and V.sub.out of FIG. 1. The clock .phi.12 of FIG. 3 is skew 3 ns (10.sup.-9 second), corresponding to the dashed area 15 within the clock interval T3 as shown in FIG. 2. As shown in Table I, the type-1 logic gate is in the hold phase, and the type-3 logic gate is in the precharge phase, during the clock interval T3. At this time, the clock .phi.3 turns to a low voltage level (or "O"), and the PMOS transistor Q1 of the type-3 logic gate 11 is turned on the precharge the node V.sub.3, as shown by an arrow 16 in FIG. 3. In normal situation, the NMOS transistor Q2 of the type-1 logic gate 12 is turned off to keep the voltage of the node V.sub.4 at the previous state. Unfortunately, the clock .phi.12 is skew, and thus the transistor Q2 is still "ON". At this time, if the high voltage of the node V.sub.3 turns on the logic tree block 14, the node V.sub.4 discharges improperly (as shown by an arrow 17 in FIG. 3) because the transistors Q2 and Q3 are all "ON". Consequently, the output is wrong, as shown by an arrow 18 in FIG. 3, and this is the so-called clock-skew race problem.
Referring to FIG. 4, there is shown a conventional logic gate wherein a capacitor C.sub.1 represents the parasitic capacitance of a logic tree block 19. When a clock .phi. is "0", a transistor Q4 is turned on to charge an output capacitive load C.sub.0 till a high voltage level. At this time, if the inputs of transistors Q6 and Q7 as well as the capacitor C.sub.1 are all in a low voltage state, the transistors Q6 and Q7 are turned off, and the voltage of the capacitor C.sub.1 is kept at the low voltage state. When the clock .phi. turns to high (or "1"), the voltage of the capacitor C.sub.0 should be kept at the previous state, i.e. the high voltage state. However, if the input state is changed at this time, resulting in that the transistor Q6 in the logic tree block 19 is turned on, the charge of the capacitor C.sub.0 will be redistributed between the capacitors C.sub.0 and C.sub.1. Consequently, the capacitor C.sub.0 has a voltage drop, and this is the so-called charge redistribution problem.
USPTO Backgrounds
USPTO Backgrounds