1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing it, and in particular to a method for producing a box mark for automatic overlay measurement used in a lithography process.
2. Description of the Related Art
In semiconductor device manufacture, the lithography process is required to form each of layers of a semiconductor device in a predetermined shape. In this process, it is needed when forming a resist pattern in a certain layer to align a mask pattern with its underlying layer according to a predetermined standard. The predetermined standard concerning the pattern overlay accuracy is becoming more stringent as the semiconductor devices become finer.
Hereafter, a box mark for automatic overlay measurement between a mask pattern and its underlying layer used in a conventional lithography process will be described.
FIGS. 1A through 1F are sectional views showing a conventional method for manufacturing a semiconductor device. FIG. 2 is a top view of a conventional semiconductor device. Word lines and bit lines are formed on a semiconductor substrate having devices formed thereon. Thereafter, a capacity contact pattern is formed between word lines and bit lines in a lithography process. Here, the lithography process is shown.
As shown in FIG. 1A, element isolation regions 102 are first formed on a semiconductor substrate 101.
Subsequently, as shown in FIG. 1B, word lines 105 each having a polycide structure are formed. At this time, an integral outside box mark 105a for automatic misalignment measurement is also formed on a scribe line simultaneously with formation of the word lines 105.
Subsequently, as shown in FIG. 1C, pad polysilicon regions 10 are formed on predetermined areas on the word lines 105. Thereafter, an oxide film 103 having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film 103 to planarize the oxide film 103.
As shown in FIG. 1D, a resist 107 is applied to the surface of the oxide film 103. By using a mask for forming a contact hole 109 having an inside box mark 11 for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, a misalignment value from the inside box mark 11 formed over the outside box mark 105a is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between the word line 105 and the contact hole 109 is measured.
In succession, the misalignment value is inputted as an offset value of an aligner. A resist 107 is applied on the surface of the oxide film 103 again, and exposure of the contact hole 109 is conducted.
Subsequently, as shown in FIG. 1E, a predetermined region of the oxide film 103 is removed, using the photoresist 107 formed in a predetermined pattern shape, as a mask, and by using anisotropic etching or the like. A contact hole 109 is thus formed. Furthermore, by way of a predetermined process, WSi is buried in the contact hole 109, and in addition, WSi serving as a bit line 111 is deposited.
Thereafter, in the same way as the word line 105, exposure and development are conducted by using a mask for forming the bit lines 111 having an integral outside box mark 111a for automatic overlay measurement added thereto. The bit lines 111 are thus formed, and the outside box mark 111a is newly formed. At this time, misalignment of the bit lines 111 is measured by using the box mark 111a formed at the time of contact described before.
Subsequently, as shown in FIG. 1F, an oxide film 150 having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film 150 to planarize the oxide film 150.
Thereafter, a photoresist film 113 is applied to the surface of the oxide film 150. By using a mask for forming capacity contacts 114 having an inside box mark 17 for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, by using the automatic overlay measuring instrument, a misalignment value in the X direction (the lateral direction of FIGS. 1A through 1F) is read from the outside box mark 105a formed in the process of FIG. 1B, and a misalignment value in the Y direction (the depth direction of FIGS. 1A through 1F) is read from the outside box mark 111a formed in the process of FIG. 1E. Between wiring lines formed in the shape of (#), the capacity contacts 114 are thus formed.
In the above described integral outside box mark for automatic overlay measurement, however, two box marks are required to measure the misalignment values in the X direction (word line) and Y direction (bit line) when forming capacity contacts between word lines and between bit lines. Therefore, there is a problem that it takes time to measure the misalignment values and analyze the measurement results.
USPTO Backgrounds
USPTO Backgrounds