FIG. 1 depicts a small portion of a conventional spin transfer torque magnetic random access memory (STT-MRAM) 1. The conventional STT-MRAM 1 utilizes spin transfer as a mechanism for switching the state of the magnetic storage cell. The conventional STT-MRAM 1 includes a conventional magnetic memory cell 10 including a magnetic element 12 and a selection device 14. The selection device 14 is generally a transistor such as a NMOS transistor and includes a drain 11, a source 13, and a gate 15. Also depicted are a word line 16, a bit line 18, and source line 20. The word line 16 is oriented perpendicular to the bit line 18. The source line 20 is typically either parallel or perpendicular to the bit line 18, depending on specific architecture used for the conventional STT-MRAM 1. However, in other STT-MRAMs, the orientations of bit lines, word lines, and source lines may differ. The bit line is connected to the magnetic element 12, while the source line 20 is connected to the source 13 of the selection device 14. The word line 16 is connected to the gate 15.
The conventional STT-MRAM 1 programs the magnetic memory cell 10 by current flowing through the cell. In particular, the magnetic element 12 is configured to be changeable between high and low resistance states by driving a current through the conventional magnetic element 12. The current is spin polarized when passing through the magnetic element 12 and changes the state of the magnetic element 12 by the spin transfer effect. For example, the magnetic element 12 may be a MTJ configured to be written using the spin transfer effect. Typically, this is achieved by ensuring that the magnetic element 12 has, for example, a sufficiently small cross-sectional area as well as other features desirable for switching using the spin transfer effect. When the current density is sufficiently large, the current carriers driven through the magnetic element 12 may impart sufficient torque to change the state of the magnetic element 12. When the write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is passes through the magnetic element 12 in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
During write operations, the word line 16 is high and turns on the selection device 14. The write current flows either from the bit line 18 to the source line 20, or vice versa, depending upon the state to be written to the magnetic memory cell 10. During read operations, the word line 86 is high, thereby enabling the selection device 14. Consequently, a read current flows from the bit line 18 to the source line 20.
Because the magnetic element 12 is programmed by a current driven through the magnetic element 12, the conventional STT-MRAM 1 has better cell scalability, lower current of writing memory cells 80, does not suffer from the problem of write disturbance to the neighboring memory cells and smaller cell size for high memory density.
FIG. 2 depicts the structure of another conventional STT-RAM memory array block 1′ that utilizes the conventional memory cell 10 (depicted in FIG. 2 as cell 10′). Portions of the conventional STT-RAM memory block 1′ are analogous to those depicted in FIG. 1 and are, therefore, labeled similarly. In addition, for clarity, only some of the components of the conventional STT-RAM memory block 1′ are numbered. Thus, the conventional STT-RAM memory block 1′ includes memory cells 10′, local word liens 16′, bit lines 18′, and source lines 20′ as well as global word lines 22, word line strap 24, reference generator 26, pre charge circuits 28, 29, and 30, read reference selector 32, bit line selectors 34, sense amplifiers precharge circuit 36, read sense amplifiers 38, and write control driver 40.
In the conventional STT-RAM memory block 1′, j bit-lines 18′ and m local word lines 16′ are shown. There are thus j×m memory cells 10′, each of which includes a magnetic element 12′ and a selection device 14′ that is typically a conventional NMOS transistor. The size of the conventional STT-RAM memory block 1′ may vary as j and m vary depending on the memory architecture. The selection transistor 14′ and magnetic element 12′ are connected to the bit line 18′, source line 20′, and LWL 16′ in an analogous manner to that depicted in FIG. 1. Referring back to FIG. 2, the gate 15′ of each selection transistor 14′ is connected to a LWL 16′, while the source of the selection transistor 14′ is tied to the source line 20′, which minimizes the area (cost) of the conventional STT-RAM block 1′.
In addition to the local word lines 16′, global word lines 22 are also utilized. The local word lines 16′ and global word lines 22 are connected by the vias or contacts 42 in the word line strap 24. The global word lines 22 are typically metal lines with low resistance, while the local word lines are typically polysilicon with a relatively high resistance. In addition to the vias/contacts 42, power supply lines (not shown) and the well contacts (not shown) are typically in the word line strap 24 to supply the power, Vdd, and ground to the cells 10′ in each block 1′. The use of global word lines 22 in conjunction with the local word lines 16′ is typically used to speed up the local word line rise/fall time by reducing the maximum high resistance delay of the local word lines 16′.
The logic including, for example, reference generator 26, pre charge circuits 28, 29, and 30, read reference selector 32, bit line selectors 34, sense amplifiers precharge circuit 36, read sense amplifiers 38, and write control driver 40 are used to control the STT-RAM memory block 1′.
During the write operations, the appropriate local word line 16′ is driven high and the selected one of the j bit lines 18′ is selected by the bit line selector 34. The data for the write operation is sent to the write control driver 40, which drives the data in current either through the selected bit line 18′ to the source line 20′ via the selected memory cell 10′ or through the source line 20′ to the bit line 18′, depending on the data. For the write operation, the R_WL line 44 is driven low to disable the reference line 46.
At the beginning of read operations, the pre-charge circuits 28, 29, and 30 pre-charge the bit lines 18′ to a pre-charge voltage which may be from Vdd to the Ground. Selected local word line(s) 16′ is/are driven high. In addition, selected bit line(s) 18′ is/are selected by the bit line selector controlled by the signals from the column address decoder (not specifically shown). The current flows through the selected memory cell 10′ from the bit line 18′ to the source line 20′, which is connected to the ground. The value of the current depends on the data stored in the memory cell 10′. In addition, the reference line 46 is selected by the R_WL line 44 and the read reference selector 32, which is driven by an Rsel signal. Thus, reference current flows through the reference generator.
In order to read the data, conventional read sense amplifiers 38 are used. The conventional read sense amplifier reads out the data according to the difference between the selected bit line current and the reference line current.
Although the STT-MRAM 1/1′ functions, one of ordinary skill in the art will readily recognize that the STT-MRAM 1/1′ is desired to be improved.
USPTO Backgrounds
USPTO Backgrounds