1. Field of the Invention
The present invention relates to programmable integrated circuits. More specifically, the present invention relates to layouts for non-volatile memory cells and arrays.
2. The Prior Art
Two-transistor non-volatile memory cells for use in programmable integrated circuits are known in the art. FIGS. 1A and 1B are, respectively, top and cross sectional views of an illustrative group of three pairs of two-transistor non-volatile memory cells. The cross sectional view of FIG. 1B is taken through the dashed line 1B-1B in FIG. 1A.
Each two-transistor non-volatile memory cell (one of which is shown in dashed rectangle 10) of FIG. 1A and is shown formed inside of a p-type well shown at reference numeral 12 formed within an n-type well 14. Each two-transistor non-volatile memory includes a memory transistor and a switch or pass transistor controlled by the memory transistor, disposed within the p-type well. The memory transistor is used to program and erase the cell. The switch transistor may be used, for example, to make interconnections in an FPGA. The memory transistors are formed from portions of active regions 16-1, 16-2, and 16-3, shown at the right side of each two-transistor non-volatile memory cell and the switch transistors are formed by portions of active regions 18-1, 18-2, and 18-3, shown at the left side of each two-transistor non-volatile memory cell.
Persons of ordinary skill in the art will observe that mirrored pairs of memory transistors and switch transistors are shown in p-type well 12 in FIGS. 1A and 1B. Contacts 20-1, 20-2, and 20-3 form the common source connections for each pair of memory transistors and contacts 22-1, 22-2, and 22-3 form the common source connections for each pair of switch transistors. Contacts 24-1, 24-2, and 24-3 connect to the drains of the first of the memory transistors in each pair of cells and contacts 26-1, 26-2, and 26-3 connect to the drains of the second of the memory transistors in each pair of cells. Contacts 28-1, 28-2, and 28-3 connect to the drains of the first of the switch transistors in each pair of cells and contacts 30-1, 30-2, and 30-3 connect to the drains of the second of the switch transistors in each pair of cells.
Common control gate 32 is associated with the first memory and switch transistors of all of the two-transistor non-volatile memory cells and common control gate 34 is associated with the second memory and switch transistors of all of the two-transistor non-volatile memory cells. Floating gate segments 36-1, 36-2, and 36-3, respectively, are common to the first memory and switch transistors in the three cell pairs shown and floating gate segments (hidden under control gate 32 and not shown in FIG. 1A) are common to the second memory and switch transistors in the three cell pairs shown in FIGS. 1A and 1B. As will be appreciated by persons of ordinary skill in the art, the floating gate segments are aligned with the control gates with which they are associated.
The programming, erasing, and normal-mode operating of the two-transistor, non-volatile memory cells shown in FIGS. 1A and 1B are all well known to persons of ordinary skill in the art. Briefly, the two-transistor non-volatile memory cell is programmed using the memory transistor. Because the memory transistor and the switch transistor share the same floating gate, the switch transistor is either turned off or turned on depending on the programmed or erased state of the memory transistor.
As can be seen from an examination of FIGS. 1A and 1B the memory transistors are smaller than the switch transistors. As will be appreciated by persons of ordinary skill in the art, this makes the memory transistors easier to program and also allows the switch transistors to have a low on resistance.
While the two-transistor memory cells shown in FIGS. 1A and 1B function satisfactorily for their intended purpose, there remains room for improvement in the technology.
USPTO Backgrounds
USPTO Backgrounds