The present invention relates to a semiconductor device and a manufacturing technique for the same. Particularly, the present invention is concerned with a technique effective in its application to the manufacture of plural semiconductor elements which are electrically isolated from one another by element isolation having a width of 0.3 μm or less for example.
As one of element isolation methods for isolating adjacent semiconductor elements electrically from each other there is known a shallow trench isolation (hereinafter referred to as “STI”). According to the structure of STI, a trench having a depth of about 0.4 μm for example is formed in an element isolation region of a substrate and an insulating film is embedded therein.
For example, in Japanese Unexamined Patent Publication No. 2001-15586 (Patent Literature 1) there is disclosed a semiconductor device having a trench structure region and an element region both formed adjacent to each other on a semiconductor substrate having {100} plane as a semiconductor substrate surface, at least a part of the boundary between the trench structure region and the element region as seen in a direction <100> perpendicular to the substrate being formed in the direction of <010> axis or the vicinity thereof.
[Patent Literature 1]                Japanese Unexamined Patent Publication No. 2001-15586        
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