In the manufacture of semiconductor devices, process chambers are frequently interfaced to permit transfer of wafers or substrates, for example, between the interfaced chambers. The transfer is typically performed via transfer modules that move the wafers, for example, through slots or ports that are provided in adjacent walls of the interfaced chambers. Transfer modules are generally used in conjunction with a variety of wafer processing modules (PMs), which may include semiconductor etching systems, material deposition systems, and flat panel display etching systems.
Semiconductor device geometries (i.e., integrated circuit design rules) have decreased dramatically in size since such devices were first introduced several decades ago. Integrated circuits (ICs) formed in the process chambers have generally followed “Moore's Law,” meaning that the number of devices that fit onto a single integrated circuit chip doubles every two years. Contemporary IC fabrication facilities (“fabs”) routinely produce 65 nm (0.065 μm) feature size devices and smaller. Future fabs will soon be producing devices having even smaller feature sizes. Commensurate with the reduced feature sizes are reduced contamination and particle budgets as even a single 30 nm particle can be a killer defect for a given IC.
Perhaps more importantly, from a yield and cost basis standpoint, the types of equipment (e.g., process tools) used in the fabrication process is becoming a primary technology driver. The fabrication process must be effective, but it must also be fast and not add to the total particle or contamination budget. Contemporary throughput demands for current generations of 300 mm wafers in many applications are 360 wafers per hour or higher. Currently, systems use only a single carrier linear wafer motion requiring a non-productive time period while the wafer carrier is returned to a starting point in a process tool. Thus, wafer handling is slow. Proposed solutions to increase throughput have focused on joining a plurality of process tools in parallel. While such solutions may increase wafer throughput, they do so at the expense of tool footprint, increased equipment costs, reduced reliability, and, in many cases, increased particle generation from wafer transport mechanisms within the tools. Accordingly, improvements are needed in the field of semiconductor processing with a special emphasis on equipment reliability, throughput, and efficiency.
USPTO Backgrounds
USPTO Backgrounds