1. Field of the Invention
The present invention generally relates to a semiconductor light-receiving device, and more particularly, to a PIN-type photodiode that can perform high-speed operations and can be used in large-capacity optical fiber communication systems.
2. Description of the Related Art
As optical communication systems have been rapidly increasing in capacity, transmission systems with 40 Gbps or higher have been developed in recent years. Semiconductor light-receiving devices to be used in such large-capacity transmission systems need to be capable of operating at high-speed of 40 GHz or higher, and therefore, need to exhibit higher performance and higher reliability than conventional semiconductor light-receiving devices.
Japanese Unexamined Patent Publication No. 2001-127333 discloses this type of semiconductor light-receiving device in the form of a PIN-type photodiode having a tapered optical waveguide structure integrated therein. FIG. 8 is a perspective view of an example structure of the PIN-type photodiode having a tapered optical waveguide structure integrated therein. In the circle denoted by A in FIG. 8, an enlarged section view of the light receiving unit of the photodiode is shown. As can be seen from FIG. 8, the photodiode 100 has a tapered optical waveguide structure 102 connected to a side surface of a light receiving element 103 on a semi-insulating InP substrate 101. The tapered optical waveguide structure 102 converts the size of light transmitted from optical fibers into a spot size, and then sends the converted light into the light receiving element 103 through a side surface of a light absorption layer 104.
A p-side electrode pad 105 of a predetermined shape is provided on the substrate 101, with an insulating film being interposed in between. Also, n-side electrode pads 106 are provided on the same plane as the p-side electrode pad 105. Accordingly, this photodiode 100 can be connected directly to a substrate of a coplanar strip line substrate. A P-type electrode 107 is formed on top of the light receiving element 103. The P-type electrode 107 is connected to the p-side electrode pad 105 by an air bridge 107a. 
An N-type electrode 108 is formed on the surface of an N-type semiconductor layer 109 that is exposed by etching performed on the light receiving element 103 to form a mesa structure. The N-type electrode 108 is connected to the n-side electrode pads 106 extending onto the semiconductor layer 109. The n-side electrode pads 106 occupy large areas to secure a connection region for a bypass capacitor (later described) and to securely provide a ground potential to the N-type electrode 108 in a high-frequency operation.
FIG. 9 illustrates an example structure of such a PIN-type photodiode. An N+-InP contact layer 112, an N−-InP buffer layer 113, an undoped InGaAs light absorption layer 114, P−-InGaAsP composition graded layers 115 and 116, a P+-InP layer 117, and a P+-InGaAsP contact layer 118, are stacked in this order on an InP semiconductor substrate 111, as shown in FIG. 9. Etching is then performed on these semiconductor layers to form a mesa structure.
An N-side electrode 119 is ohmically connected to the N-side contact layer 112 with a double-layered metal of Au and Ge, for example. Also, a P-side electrode 120 is ohmically connected to the P-side contact layer 118 with a double-layered metal of Au and Zn, for example.
When the photodiode is operating, the N-side electrode 119 has a positive potential, the P-side electrode 120 has a ground potential, and the P-type semiconductor layer 117 and the N-type buffer layer 113 are reverse-biased. When carriers are generated by light incidence into the light absorption layer 114, electrons are taken out by the N-side electrode 119, while holes are taken out by the P-side electrode 120.
The response speed of the above receiving element is basically determined by the CR time constant and the running time of the carriers (mostly holes) in the depletion layer. To restrain the hole trapping by the heterobarrier at the interface between the P-type semiconductor layer 117 and the light absorption layer 114, the semiconductor intermediate layers (or the graded layers) 115 and 116 of graded compositions are interposed in between. Meanwhile, to reduce the PN junction capacity of the light receiving unit without increasing the running time of the holes, the buffer layer 113 is provided under the light absorption layer 114. The impurity concentration in the buffer layer 113 is made as small as 1×1016 cm−3, so that the thickness of the depletion region formed in the buffer layer 113 is increased. Accordingly, the electrostatic capacity C is reduced, and the response speed is increased.
In the conventional PIN-type photodiode having the buffer layer 113 to reduce the electrostatic capacity, however, adverse influence of electron trapping cannot be avoided due to the heterobarrier formed at the interface between the light absorption layer 114 and the buffer layer 113. If the impurity concentration in the buffer layer 113 becomes lower than 1×1017 cm−3 in practice, the band discontinuity between the buffer layer 113 and the light absorption layer 114 becomes an obstacle to the running of electrons. Particularly, when a high-speed operation with high-intensity light incidence is performed at 40 GHz or higher, the trapping time of not only holes but also electrons, due to the band discontinuity, becomes so long as to cause the problem of poor frequency response characteristics.
USPTO Backgrounds
USPTO Backgrounds