1. Field of the Invention
The invention generally relates to microprocessor test interfaces and more particularly relates to a low cost, user oriented microprocessor test interface suitable for hardware development and testing of a computer system that includes a complex, single chip, general purpose central processing unit (CPU).
2. Description of the Related Art
Methods and apparatus are well known for testing processor units. The earliest approaches, when processors were relatively large, involved interfacing a test unit directly with system buses and critical registers of the processor. The registers and buses were accessible for both factory and end-user testing. As processor units have become smaller, in fact, down to the size where they can be fabricated on a single chip, the feasibility, particularly from a cost point of view, of providing the aforementioned accessibility to the key registers and system buses for test purposes has become a problem.
There are two well known approaches for testing single chip microprocessors. The first approach is Level Sensitive Scan Design (LSSD) testing. The second approach is testing the processor utilizing special purpose test logic added to the chip.
With LSSD testing, the processor state is modified and inspected via large, serial scan strings. A high degree of test coverage is possible, but the amount of time required to perform a test is excessive due to the serial nature of data transfer. Additionally, the implementation of scan strings affects the die size and cost of a chip.
Using the special test logic approach, experience dictates that the logic is difficult to design and maintain. In addition, the special purpose logic can be very sensitive to changes made in processor logic. This approach normally requires special chip bond-outs which are not available to customers for downstream processor testing, system development use, etc.
Methods and apparatus for testing multichip, bit-sliced microcode processors are known which feature parallel test interfaces. The parallel type interface allows for more rapid testing then LSSD type testing approaches and does not suffer from the aforementioned difficulties associated with using special test logic.
Heretofore the parallel test interfaces have not been used in the single chip context. When the processor is spread over several chips, the microinstruction bus and the microinstruction address bus are feasibly (from a cost point of view) accessible to the test unit over the parallel test interface. Control of sequencing can be easily effected over such an interface as well. However, as indicated hereinbefore, the same accessibility becomes a problem in the single chip processor context, explaining why parallel test interfaces have not previously been developed for these processors.
Reduced Instruction Set Computer (RISC) architectures, with their simplified instruction sets and simplified bus structures, lead themselves to the design of parallel test interfaces for single chip processors. Direct access by a test unit over the test interface to RISC data and instruction buses would allow for the direct "feeding" of the processor with test data and instruction sequences. Sequencing control signals can also be easily supplied to a processor in a RISC environment. This obviates the need for special purpose sequencing hardware or test logic, particularly where the RISC processor operates with a single cycle execution time.
The aforementioned features of a RISC architecture, make it ideal for implementing the desired parallel test interface for testing single chip microprocessors.
USPTO Backgrounds
USPTO Backgrounds