1. Field of the Invention
This invention relates to network systems, and more particularly, to a network switcher for data transfer between various nodes, which can serve as a virtual local area network (VLAN).
2. Description of Related Art
FIG. 1 is a schematic diagram of a conventional network system in which a network switcher 10 is connected between a network communication unit 20 and a plurality of nodes 30A, 30B, 30C, 30D. Each node can be a workstation or PC (personal computer). In the case of FIG. 1, the network switcher 10 includes four interface ports 12, 14, 16, 18 respectively linking the four nodes 30A, 30B, 30C, 30D to the network communication unit 20. Each of the interface ports 12, 14,16, 18 includes a reception interface unit 12A for transferring an outgoing node-information signal from the associated node (i.e., the source of the node-information signal) to the network communication unit 20, and an output interface unit 12B for transferring an incoming node-information signal from the network communication unit 20 to the associated node (i.e., the destination of the node-information signal).
In operation, the nodes 30A, 30B, 30C, 30D can forward and receive information via the interface ports 12, 14, 16, 18 and the network communication unit 20 to and from other various nodes at remote sites. The network communication unit 20 can be, for example, a fiber-optic system which can transmit information at high speeds and large volumes.
FIG. 2 is a schematic block diagram depicting a more detailed structure of the reception interface unit 12A used in the network system of FIG. 1. As shown, the reception interface unit 12A includes a package buffer 210, a Destination Address (DA) Latcher 220, an address generator 230, a decoder 240, a remoter 250, and a DMA (direct memory access) controller 260.
When a certain node, for example the node 30A wants to send information via the associated reception interface unit 12A to a certain destination, the node 30A issues and transfers a node-information signal via the signal line 202 to both of the package buffer 210 and the DA Latcher 220 in the reception interface unit 12A. The package buffer 210 stores the node-information temporarily therein, while the DA Latcher 220 generates a Destination Address (DA) signal and a Destination Address Latch (DA.sub.-- Latch) signal in response to the node-information signal. The DA signal is transferred respectively via the signal line 222 to the address generator 230, while the DA.sub.-- Latch signal is transferred via the signal line 224 to the decoder 240. The DA signal is, for example, a 12-bit binary signal. In response to the DA signal, the address generator 230 generates and transfers a Destination Address Control (DA.sub.-- Control) signal via the signal line 232 to the decoder 240, a Destination Address (DA) buffer signal via the signal line 234 to the decoder 240, and a Destination Port (DP) signal via the signal line 236 to both of the decoder 240 and the remoter 250. The contents of these signals indicate, for example, whether the access is still valid or expired, which interface port the MAC (media access control) address is associated with, and so on.
The decoder 240, in response to the DA.sub.-- Latch signal received from the signal line 224, the DA.sub.-- control signal received from the signal line 232, the DA signal from the signal line 234, and the DP signal received from the signal line 236, generates a Broadcast-pkt ("pkt": short for "packet") signal, a Remote-pkt signal, and a Local-pkt signal, which are respectively transferred via the signal lines 242, 244, 246 to the remoter 250. The Broadcast-pkt signal indicates whether the node-information signal is to be forwarded to all of the linked ports; the Remote-pkt signal indicates whether the node-information signal is to be forwarded to a single specified port; and the Local-pkt signal indicates whether the node-information signal is restricted for local transfer. To obtain the logic values of these signals, the decoder 240 performs a decoding procedure in accordance with the following algorithm:
Local-pkt=(DA control signal valid) & PA1 Remote-pkt=(DA.sub.-- Control signal valid) & PA1 Broadcast-pkt=an identification method other than the foregoing. PA1 (a) a plurality of reception interface units, each being coupled between the network communication unit and one of the nodes, for transferring data from the nodes to the network communication unit; when receiving a node-information signal from the associated node, each reception interface unit being capable of determining whether the node and the destination of the node-information signal belong to the same group; if yes, the reception interface unit allowing the transfer of the node-information signal to the network communication unit; and PA1 (b) a plurality of output interface units, each being coupled between the network communication unit and one of the nodes, for transferring data from the network communication unit to the nodes; when receiving an incoming node-information signal from the network communication unit that is to be transferred to a certain node connected to the network switcher, each output interface unit being capable of determining whether the destination and the source of the incoming node-information signal belong to the same group; if yes, the output interface unit allowing the transfer of the incoming node-information signal to the destination node. PA1 (a) a package buffer, connected to the associated node of the reception interface unit, for temporary storage of the packet of the node-information signal issued by the associated node; PA1 (b) a Destination Address Latcher, connected to receive the node-information signal from the, node, for generating a Destination Address signal and a Destination Address Latch signal; PA1 (c) a Source Address Latcher, connected to receive the node-information signal from the node, for generating a Source Address signal; PA1 (d) multiplexer means, connected to receive the Destination Address signal and the Source Address signal respectively from the Destination Address Latcher and the Source Address Latcher, for selectively outputting the Destination Address signal and the Source Address signal; PA1 (e) an address generator connected to receive the output of the multiplexer means, when the output of the multiplexer means is the Destination Address signal, the address generator generating a Destination Address Control signal, a Destination Port signal, a Destination Address Group signal, and a Destination Address buffer signal; and when the output of the multiplexer means is the Source Address signal, the address generator generating a Source Address Control signal, a Source Address Group signal, and a Source Address buffer signal; PA1 (f) a group decoder, coupled to receive the Destination Address Group signal and the Source Address Group signal from the address generator, for generating a Group check signal indicating whether the Destination Address and the Source Address belong to the same group; PA1 (g) a decoder, coupled to the Destination Address Latcher, the Source Address Latcher, the address generator, and the group decoder, for generating either a Remote-pkt signal, a Local-pkt signal, or a Broadcast-pkt signal in response to the Destination Address Latch signal, the Source Address Latch signal, the Destination Address Control signal, the Destination Port signal, the Destination Address buffer signal, the Source Address Control signal, the Source Address buffer signal, and the Group check signal; PA1 (h) a remoter, coupled to the address generator and the decoder, for generating a Remote Control signal and a Remote-Access Control signal in response to the Destination Port signal and either the Local-pkt signal, the Broadcast-pkt signal, or the Broadcast-pkt signal; and PA1 (i) a DMA controller, coupled to the remoter, for generating and transfers a DMA control signal to the package buffer in response to the Remote-Access Control signal from the remoter; the package buffer outputting and transferring the packet of the received node-information signal to the destination node in response to the DMA control signal. PA1 (a) a hasher, coupled to the multiplexer means, for processing the output of the multiplexer means to thereby generate a reset signal; PA1 (b) an address decoder coupled to the hasher, the address decoder having a builtin Address Table, the address decoder comparing the output of the multiplexer means with the Address Table. PA1 (a) a first buffer, coupled to the address decoder, for temporary storage of the Destination Address Control signal therein; PA1 (b) a second buffer, coupled to the address decoder, for temporary storage of the Destination Port signal therein; PA1 (c) a third buffer, coupled to the address decoder, for temporary storage of the Destination Address Group signal therein; PA1 (d) a fourth buffer, coupled to the address decoder, for temporary storage of the Destination Address buffer signal therein; PA1 (e) a fifth buffer, coupled to the address decoder, for temporary storage of the Source Address Control signal therein; PA1 (f) a sixth buffer, coupled to the address decoder, for temporary storage of the Source Address Group signal therein; and PA1 (g) a seventh buffer, coupled to the address decoder, for temporary storage of the Source Address buffer signal therein. PA1 (a) a package buffer, connected to the associated node of the reception interface unit, for temporary storage of the packet of the incoming node-information signal issued by the associated node; PA1 (b) a Destination Address Latcher, connected to receive the incoming node-information signal, for generating a Destination Address signal; PA1 (c) a Source Address Latcher, connected to receive the incoming node-information signal from the node, for generating a Source Address signal; PA1 (d) multiplexer means, connected to receive the Destination Address signal and the Source Address signal respectively from the Destination Address Latcher and the Source Address Latcher, for selectively outputting the Destination Address signal and the Source Address signal; PA1 (e) an address generator connected to receive the output of the multiplexer means, when the output of the multiplexer means is the Destination Address signal, the address generator generating a Destination Address Control signal, a Destination Port signal, a Destination Address Group signal, and a Destination Address buffer signal; and when the output of the multiplexer means is the Source Address signal, the address generator generating a Source Address Control signal, a Source Address Group signal, and a Source Address buffer signal; PA1 (f) a group decoder, coupled to receive the Destination Address Group signal and the Source Address Group signal from the address generator, for generating a Group check signal indicating whether the Destination Address and the Source Address belong to the same group; PA1 (g) a decoder, coupled to the Destination Address Latcher, the Source Address Latcher, the address generator, and the group decoder, for generating an Output Access Control signal in response to the Destination Address signal, the Source Address signal, the Destination Address Control signal, the Destination Port signal, the Destination Address buffer signal, the Source Address Control signal, the Source Address buffer signal, and the Group check signal; and PA1 (h) an output DMA controller, coupled to the decoder, for generating a DMA control signal in response to the Output Access Control signal from the decoder; the package buffer outputting and transferring the packet of the received incoming node-information signal to the destination node in response to the DMA control signal. PA1 (a) a hasher, coupled to the multiplexer means, for processing the output of the multiplexer means to thereby generate a reset signal; and PA1 (b) an address decoder coupled to the hasher, the address decoder having a builtin Address Table, the address decoder comparing the output of the multiplexer means with the Address Table. PA1 (a) a first buffer, coupled to the address decoder, for temporary storage of the Destination Address Control signal therein; PA1 (b) a second buffer, coupled to the address decoder, for temporary storage of the Destination Port signal therein; PA1 (c) a third buffer, coupled to the address decoder, for temporary storage of the Destination Address buffer signal therein; PA1 (d) a fourth buffer, coupled to the address decoder, for temporary storage of the Source Address Control signal therein; PA1 (e) a fifth buffer, coupled to the address decoder, for temporary storage of the Source Address Group signal therein; and PA1 (f) a sixth buffer, coupled to the address decoder, for temporary storage of the Source Address buffer signal therein.
(DP is the port ID code of this node) & PA2 (DA=DA.sub.-- Latch) PA2 (DP is not the port ID code of this node) & PA2 (DA=DA.sub.-- Latch)
Subsequently, the remoter 250, in response to the DP signal received from the signal line 236, the Broadcast-pkt signal received from the signal line 242, the Remote-pkt: signal received from the signal line 244, and the Local-pkt signal received from the signal line 246, generates a Remote Control signal and a Remote-Access Control signal, which are respectively transferred via the signal line 252 to the DMA controller 260 and via the signal line 254 to the network communication unit 20. In response to the Remote-Access Control signal, the DMA controller 260 generates and transfers a DMA control signal via the signal line 262 to the package buffer 210. In response to the DMA control signal, the package buffer 210 outputs and transfers the packet of the earlier received node-information via the data line 212 to the network communication unit 20. Meanwhile, the network communication unit 20, in response to the Remote Control signal, forwards the node-information signal received from the data line 212 to the prescribed destination. After the data transfer is completed, the network communication unit 20 will return a confirmation signal indicative of the success or failure of the data transfer via the signal line 254 to the remoter 250.
FIG. 3 is a schematic block diagram showing a more detailed structure of the address generator 230 used in the reception interface unit 12A shown in FIG. 2. As shown, the address generator 230 includes a signal processor 310, an address decoder 320, having a built-in Address Table 325, and three buffers 330, 340, 350. The signal processor 310 receives the DA signal from the DA Latcher 220 via the signal line 222 and then converts it into a 12-bit format. The output of the signal processor 310 is transferred via the signal line 312 to the address decoder 320 where it is compared with the Address Table 325 to thereby generate a Destination Address Control (DA.sub.-- Control) signal, a Destination Address (DA) buffer signal, and a Destination Port (DP) signal, which are respectively transferred via the signal lines 322, 324, 326 to the buffers 330, 340, 350 and temporarily stored therein before being transferred onwards via the signal lines 232, 234, 236 to the decoder 240 (FIG. 2).
FIG. 4 is a schematic block diagram showing a more detailed structure of the output interface unit 12B used in the network switcher shown in FIG. 1. As shown, the output interface unit 12B includes a DMA (direct memory access) controller 410 and a package buffer 420. The DMA controller 410 is used to control the data transfer from the network communication unit 20 through the package buffer 420 to the node 30A. The DMA controller 410 generates and transfers a DMA control signal via the signal line 412 to the network communication unit 20. In response to the DMA control signal, the network communication unit 20 forwards the incoming node-information signal, which was received from a remote node in the network system, via the data line 24 to the package buffer 420, and onwards via the data line 422 to the node 30A.
One drawback to the foregoing network switcher, however, is that, when a packet is to be transferred from a source port to a destination port, if the destination address is not yet acknowledged or the transfer is a multicast, the packet can be forwarded to other ports beside the destination one. This will cause a degradation in the performance of the overall network system.
USPTO Backgrounds
USPTO Backgrounds