1. Field of Invention
The invention relates to a gate driving circuit of a display panel, and more particularly, to a gate driving circuit of a display panel with the gate driving circuit adopted in gate in panel (GIP).
2. Description of Related Art
In recent years, along with development in semiconductor technology, portable electronic products and flat display products have become increasingly popular. In various types of flat displays, liquid crystal displays (LCDs) have gradually become the main stream of display products due to features such as low voltage operation, radiation-free scattering, light weight, compactness, and the like.
In order to reduce the manufacturing cost of LCDs, some manufacturers have proposed to manufacture multi-level shift registers directly on glass substrates by adopting thin film transistors (TFTs), thereby replacing conventional gate driving chips for reducing the manufacturing cost of LCDs.
FIG. 1A is a schematic block diagram illustrating a conventional multi-level shift register directly manufactured on a glass substrate. Referring to FIG. 1A, a plurality of shift registers SR1′, SR2′, SR3′, . . . , SRn-2′, SRn-1′, SRn′ are serially coupled to one another. The shift registers SR1′, SR2′, SR3′, . . . , SRn-2′, SRn-1′, SRn′ are flip-flops respectively, and therefore each include two outputs. One of the two outputs (marked as Cout′ in the figure) is used as a Set input of a next level shift register. Here, the Set input is marked as S in FIG. 1A. Moreover, the other output outputs gate driving signals Gout1′, Gout2′, Gout3′, . . . , Goutn-2′, Goutn-1′, Goutn and is used as a Reset input of a previous level shift register. Here, the Reset input is marked as R in FIG. 1A.
FIG. 1B is an equivalent circuit diagram of a single level shift register set in FIG. 1A. Referring to FIG. 1A and FIG. 1B simultaneously, the shift register sets SR1′, SR2′, SR3′, . . . , SRn-2′, SRn-1′, SRn′ respectively receive a gate timing signal CKV, an inverse of the gate timing signal CKVB, and a reference voltage VGL, and the first level shift register SR1′ further receives a threshold driving signal STVP. Therefore, the shift registers SR1′, SR2′, SR3′, . . . , SRn-2′, SRn-1′, SRn′ respectively output a plurality of gate driving signals Gout1′, Gout2′, Gout3′, . . . , Goutn-2′, Goutn-1′, Goutn′ sequentially according to the threshold driving signal STVP, the gate timing signal CKV, and the inverted gate timing signal CKVB, so as to drive scan lines in the display panel in sequence.
However, when the display is being turned off, every pixel in the display discharges. Since the speed of discharging each pixel is different, the display frame becomes irregular, and this phenomenon is generally referred as image sticking.
USPTO Backgrounds
USPTO Backgrounds