1. Field of the Invention
This invention relates generally to an apparatus for compensating a quantization error and more particularly is directed to such an apparatus for use with a servo system of a video tape recorder (VTR).
2. Description of the Prior Art
In the prior art, a time information detecting apparatus which detects time information, such as, a pulse width of a pulse signal, is employed in various kinds of apparatus which include a servo system for a motor of a video tape recorder (VTR).
In the VTR, as shown in FIG. 1, in order to rotate a DC motor 1, such as a drum motor, a capstan motor or the like at a constant rotational speed, the rotational speed of the motor 1 is detected by a frequency generator 2 and a control voltage signal corresponding to the detected rotational speed (time information) is generated by a time information detecting apparatus 3 and is supplied through a motor drive amplififying circuit 4 to the motor 1.
As the time information detecting apparatus 3 used in such speed servo system, it is known to employ one constructed as shown in FIG. 2.
Referring to FIG. 2, a time signal VEL (FIG. 3A) consisting of a pulse signal from the frequency generator 2 (FIG. 1) is supplied to a delay circuit 5 and to a sampling pulse generator circuit 8. The delay circuit 5 generates a timing delay signal DLY (FIG. 3B), which rises to a logic level "H" during a predetermined time T0 measured from every other rising-up time point t1 of the time signal VEL, and supplies the signal DLY to a slope generator circuit 6. The slope generator circuit 6 supplies to a sample and hold circuit 7 a voltage signal V which gradually and rectilinearly increases in voltage value from a time point t2 at which the timing delay signal DLY falls to a logic "L" as shown in FIG. 3C.
A sampling pulse generator circuit 8 receives the time signal VEL, detects a rising edge time t3 of the time signal VEL delayed by one period TX from the time t1 at which the timing delay signal DLY rises to the logic "H", produces a sampling pulse signal SMP shown in FIG. 3D and supplies the sampling pulse signal SMP to the sample and hold circuit 7.
The sample and hold circuit 7 is adapted to sample and to hold the value of the voltage signal V when the sampling pulse signal SMP is applied thereto and generates the value thereof as a control voltage signal VCON (FIG. 3C).
Consequently, with the time information detecting apparatus 3 of FIG. 2, when the motor 1 is rotated at a speed higher than a predetermined rotational speed, the period TX of the time signal VEL is shortened and hence the sampling pulse signal SMP is delivered at an earlier time, so that the sample and hold circuit 7 produces the control voltage signal VCON with a lower level. On the other hand, when the motor 1 is rotated at a rotational speed lower than the predetermined rotational speed, the period TX of the time signal VEL is increased so that the sample and hold circuit 7 produces the control voltage signal VCON with a higher level.
Therefore, the motor 1 is controlled so as to be rotated at a constant rotational speed.
However, if such time information detecting apparatus 3 is formed as an analogue circuit arrangement, it will be defective in that the output voltage signal VCON will fluctuate due to changes of ambient temperature, the fluctuation of a power supply source speed control and so on, and hence the voltage is unstable.
For this reason, it has been considered to form this time information detecting apparatus 3 as a digital circuit arrangement. In such digital time information detecting apparatus, since the time information of the analogue amount is digitized, a quantization error occurs so that the accuracy of the output signal is restricted by this quantization error. Accordingly, in order to effect stable control, for example, of a motor, a high clock frequency must be selected.
For example, if the period of the pulse signal VEL from the frequency generator 2 is 50 .mu.s and a drum motor is to be stably controlled at an accuracy of within 0.02%, it is necessary to detect each period at more than 5000 counts. This requires a clock frequency expressed by the following Eq. (1) EQU 1/50 (.mu.s).times.5000=100 (MHz) (1)
However, since the maximum operation frequency of a widely used digital IC lies in a range from about 10 to 20 MHz, if the clock frequency of 100 MHz is intended to be realized, there is the fear that a digital IC, will not be practically available for that purpose. Further, even if the clock frequency of 100 MHz may be realized, the apparatus becomes complicated in construction and large in size because many interface circuits are required by each circuit and also such apparatus comsumes a large amount of power. Therefore, the described apparatus is not suitable in practice.
USPTO Backgrounds
USPTO Backgrounds