The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device having a non-volatile memory cell array for storing data.
E.sup.2 PROMs (Electrically Erasable and Programmable ROM) are used extensively for a semiconductor memory device of microcomputers for storing programs.
An E.sup.2 PROM includes a non-volatile memory cell of the so-called FLOTOX (Floating Gate Tunnel Oxide) type or MNOS (Metal Nitride Oxide Semiconductor) type, wherein a FLOTOX type cell includes an electrically isolated floating gate and stores the logic data "0" or "1" in the form of electric charges.
It should be noted that such a writing of the data "0" or "1" into a memory cell is carried out by injecting or extracting electrons to or from the floating gate, wherein such an injection or extraction of the electrons is achieved by charging or discharging the floating gate by way of a tunnel current. It should be noted that the tunnel current is caused to flow by increasing the voltage applied to the floating gate.
In the state the floating gate is charged with electrons, the threshold voltage of the memory cell transistor is decreased. In the state the floating gate is discharged, on the other hand, the threshold voltage is increased. Thus, the memory cell produces a logic output indicative of the charging state of the floating gate as a result of the change of the threshold voltage.
FIG. 1 shows the block diagram of a conventional non-volatile semiconductor memory device 1.
Referring to FIG. 1, the semiconductor memory device 1 includes a non-volatile memory cell array 2, wherein the non-volatile memory cell array 2 includes a plurality of non-volatile memory cells therein. Further, there are provided a row decoder 3 in cooperation with the memory cell array 2 for selecting a row of the memory cell array 2 in response to a given address, a column decoder 4 selecting a column of the memory cell array 2 in response to a given address, a sense amplifier 5 in cooperation with the column decoder 4 for amplifying the data signal of the non-volatile memory cell that is selected by the row decoder 3 and the column decoder 4. The sense amplifier 5 is supplied with a reference signal from a reference cell 6 and there is provided an input/output buffer 7 for holding the output of the sense amplifier 5. The input/output buffer 7 further holds an external input data signal to be written into a selected memory cell.
In addition, there are provided an address buffer 8 supplied with external address data and for supplying the same to the row decoder 3 and to the column decoder 4, an erasing circuit 9 for flash-erasing the non-volatile memory cell array 2 when a rewriting of the data is to be made, a writing circuit 10 for writing data into the memory cell array 2, and a control circuit 11 for controlling the erasing circuit 9 and the writing circuit 10 when rewriting the data in the memory cell array 2.
FIG. 2 shows a typical conventional construction of the memory cell forming the memory cell array 2.
Referring to FIG. 2, the memory cell includes a memory cell transistor Q.sub.m and a select transistor Q.sub.s, wherein the memory cell transistor Q.sub.m includes a floating gate Gf between a control gate G.sub.cnt and a channel defined in a semiconductor substrate in the state that the floating gate G.sub.f is isolated from the surroundings. The non-volatile memory cell thereby produces a logic output in response to the electric charges held in the floating gate G.sub.f.
When reading data, a read address is supplied to an address terminal T.sub.add connected to the address buffer 8, wherein the address thus supplied is held in the address buffer 8 and is supplied further to the row decoder 3 and to the column decoder 4 from the address buffer 8. The row decoder 3 and the column decoder 4 thereby select the memory cell corresponding to the address given by the address buffer 8, wherein the memory cell thus selected is connected to the sense amplifier 5 via the column decoder 4.
In the sense amplifiers, the output signal of the selected memory cell is compared with a reference signal from the reference cell and is amplified according to the result of the comparison. The output signal thus amplified is then supplied to the input/output buffer 7. Thereby, the input/output buffer 7 holds the output signal thus supplied thereto and supplies the same further to an input/output terminal T.sub.in-out. During this operation, a data-read control signal is supplied to a control terminal T.sub.cnt, wherein the data-read control signal is supplied to a control circuit 11 via a control terminal T.sub.cnt. It should be noted that control circuit 11 controls the data hold timing of the address buffer 8 and the input/output buffer 7 in response to the data read control signal.
When rewriting data, a data-rewrite control signal is supplied to the control terminal T.sub.cnt, wherein the data rewrite control signal thus supplied to the control terminal T.sub.cnt is forwarded further to the control circuit 11. The control circuit 11 thereby controls the erase circuit 9 in response to the data-rewrite control signal.
FIG. 3 shows the block diagram of a conventional example of the erase circuit 9.
Referring to FIG. 3, the erase circuit 9 includes a pump circuit 12 for boosting the voltage of the control gate G.sub.cnt of the memory cell transistor Q.sub.m constituting the memory cell of the non-volatile memory cell array 2 to a level sufficient for erasing the electric charges of the floating gate G.sub.f, a pulse control circuit 13 controlling the timing of operation of the pump circuit 12, an erase block switch 14 selectively supplying the boosted voltage of the pump circuit 12 to the control gate G.sub.cnt of the memory cell transistor Q.sub.m of a selected block, from which the data is to be erased, and a gate voltage control circuit 15 controlling the gate voltage of the memory cell constituting the non-volatile memory cell array 2.
It should be noted that the erase circuit 9 carries out the erasing of data in each of the blocks by supplying the boosted erase voltage to each of the erasing blocks of the non-volatile memory cell array 2. Further, the control circuit 11 controls the writing circuit 10, after the completion of the erasing by the erase circuit 9, and carries out writing of the data supplied to the input/output buffer 7 into the non-volatile memory cell array in correspondence to the address data held by the address buffer 8.
On the other hand, such conventional non-volatile semiconductor memory devices have lacked the function of controlling or managing the number of the erasing operations or erase number conducted on the semiconductor memory device. Because of this, it was not possible for the user or designer of the non-volatile semiconductor memory device to recognize the actual number of erasing operations conducted on a given non-volatile semiconductor memory device. As a consequence, it was not possible to recognize the state of degradation even when a given non-volatile semiconductor device in use or a defective non-volatile semiconductor device is given for inspection.
USPTO Backgrounds
USPTO Backgrounds