Integrated circuits (ICs) formed on semiconductor substrates, typically silicon wafers, are typically comprised of a variety of basic electrical components, such as amplifiers, resistors and the like. It is desirable to verify that such integrated basic components are fabricated according to a design specification and have certain properties or values, e.g., a specified gain, resistance, etc. An individual component cannot readily be tested, however, once integrated into a circuit.
In lieu of testing the integrated components, "stand-alone" copies of such basic components are tested. The stand-alone copies are fabricated in either vertical or horizontal "streets" that separate various "dies," i.e., integrated circuits, formed on the wafer. Such copies have properties or values of gain, resistance, etc. that are representative of such properties of their "integrated" counterparts since they are fabricated using the same processes. As such, it is appropriate to apply the test results to the integrated components. The aforedescribed quality control methodology is referred to as "in-process electrical testing."
During in-process electrical testing, a signal source and measurement device, usually external, are electrically connected to the stand-alone component to be tested ("the target component"). Electrical connection is effected via microprobes, one of which is attached to an end of a coaxial cable carrying a signal from the signal source, the other of which probes is attached to an end of a coaxial cable leading to the measurement device. On the wafer, the target component is electrically connected to pads. The microprobes contact the pads thereby electrically connecting the signal source and the measurement device to the target component.
The pads and the target component collectively form a "process monitor" or "device monitor" or tester. Some of the wafer surface is reserved for such monitors. Such reserved surface cannot be utilized for devices forming part of the ICs, and, as such, reduces the amount of wafer surface available for the ICs. It is therefore desirable to reduce the amount of wafer surface sacrificed in conjunction with the use of such process monitors.
USPTO Backgrounds
USPTO Backgrounds