As the semiconductor industry pushes for more density and performance, IC stacking structures have become a prominent solution. However, the IC package in stacking structures tends to run much hotter.
A conventional chip stacking technique is disclosed in U.S. Patent Publication 2013/0280864, which stacks the IC chip on an interposer. To solve the thermal issues, a standalone heat sink is attached over the top of the package. Attaching a heat sink over the semiconductor package has been a standard solution used for IC cooling. However, this solution is bulky and is not viable for sensor packages because the sensor active area needs to be exposed to the environment (i.e. for receiving what is being sensed—e.g. incoming light). Placing a heat sink over the package would block and seal away the sensor active area preventing its proper operation.
There is a need for a low profile technique for stacking IC chips such as a sensor device over associated ASIC semiconductor wafer (e.g. the sensor's processor unit) which includes a cooling solution all within a single package.
USPTO Backgrounds
USPTO Backgrounds