A high reliability semiconductor package typically includes a semiconductor device which is hermetically sealed in a housing portion thereof. Typical semiconductor devices used in high reliability semiconductor packages are power MOSFETs, bipolar transistors, Schottky diodes, PN junction diodes, and IGBTs.
Hermetic surface mount packages, leadless chip carriers and ceramic leadless chip carriers (also known as LCC and CLCC respectively) have served as high reliability platforms for more than 20 years.
In the recent years, a vast array of electronic designs have been integrating new surface mount packages (also referred to as surface mounted devices or SMDs) which have surface mountable terminals on a common surface thereof. Such SMDs are desirable due to their smaller size and footprint, lighter weight, and excellent thermal performance. In addition, many high frequency circuit designs benefit from the inherently low inductance and low resistance of such SMDs.
The following are some more advantages of such SMDs:                1) very low profile when compared to TO- and MO-types of packages;        2) light weight;        2) ideal for single MOSFET, IGBT and BJT die;        3) capable of dissipating very high power due to low thermal resistance from junction to case and employing low electrical resistance material for terminal design;        4) extremely reliable at package level and when used on CCA and CIC type of boards;        5) when used as building blocks for high reliability power modules, they can be pre-screened to give high yield at module level.        
The following are some of the disadvantages of such SNDs:                1) thermal and reliability performance are largely nullified when they are used on organic printed circuit boards;        2) all connections are on the same plane which makes soldering, cleaning and inspection difficult;        3) problems with testing when multiple chips are packaged (e.g. synchronous rectifiers);        4) additional ceramic carriers are used to provide electrical isolation, stress relief to the leads, which may add many problems such as difficulty in inspection, significant increase of thermal resistance, and more cost;        5) cost is about four times higher than an ordinary TO-packages with comparable cavity size.        
It is desirable to have a package which exhibits the advantages, but not the disadvantages of the prior art SMDs.
USPTO Backgrounds
USPTO Backgrounds