1. Field of the Invention
The present invention relates to a system for and a method of verifying an electronic circuit design. In particular, the present invention relates to a technique of efficiently managing code coverage information on an electronic circuit design.
2. Description of the Related Art
Recent large-scale, sophisticated electronic circuits and their developing speeds are promoting the reuse of design resources of previous products. When developing a new circuit having given specifications by reusing design resources, an important thing is to thoroughly verify the reliability of the design resource. Code coverage information is widely used to verify the reliability of design resources. The code coverage information is a record of codes or descriptions contained in a circuit description and tested through logic simulations. Here, the “circuit description” is a form of expressing the connective relationships of a circuit and is composed of a plurality of descriptions such as RTL (register transfer level) descriptions, the “descriptions” being substantially synonymous with “codes.” The code coverage information is expressible in a value such as a percentage. The code coverage information of a given resource circuit is useful to understand how many descriptions contained in a circuit description of the resource circuit were tested in logic simulations and grasp the reliability of the resource circuit. There are other information pieces employable to verify the reliability of design resources, such as state coverage information indicating whether or not each line of a circuit description tested in logic simulations and branch coverage information indicating whether or not conditional expressions, such as conditional branch, of a circuit description tested in logic simulations. These pieces of information are useful to improve the reliability of circuit design verification.
There are some related arts that prepare code coverage information and use it for circuit design verification. Problems of the related arts will be explained. A first problem is that the related arts must prepare several kinds of code coverage information for each circuit, thereby increasing the amount of information in proportion to circuit size and complicating the management of gathered information pieces.
A second problem is that the related arts must prepare code coverage information for each test environment and each set of test patterns. When existing circuits are combined to form a new circuit and when an overall verification test is carried out on the new circuit under a new test environment with a new set of test patterns, there is no use, for the overall verification test, of code coverage information gathered through individual tests of the existing circuits. Even if the overall verification test finds a problem, the related arts are incapable of determining whether the problem has been caused by descriptions unverified in the individual tests of the existing circuits, or by an input signal string used for the overall verification test, or by peripheral circuits. The related arts, therefore, provide very low debugging efficiency.
USPTO Backgrounds
USPTO Backgrounds