The present invention relates generally to the field of integrated circuits. More particularly, the invention relates to circuits that will synchronize the internal timing or clock signals within an integrated circuit such as a synchronous dynamic random access memory (SDRAM) to external timing or clock signals.
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, and so forth, the processing, storage, and retrieval of information is coordinated with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high-speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
A continual demand exists for devices with higher data rates; consequently, circuit designers have begun to focus on ways to increase the frequency of the clock signal. In SDRAMs, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. The delay between a rising edge of the system clock (external to the SDRAM) and the appearance of valid data at the output of the memory circuit is known as the clock access time of the memory. A goal of memory circuit designers is to minimize clock access time as well as to increase clock frequency.
One of the obstacles to reducing clock access time has been clock skew, that is, the delay time between the externally supplied system clock signal and the signal that is routed to the memory""s output circuitry. An external system clock is generally received with an input buffer and then further shaped and redriven to the internal circuitry by an internal buffer. The time delay of the input buffer and the internal buffer will skew the internal clock from the external clock. This clock skew will cause signals that are to be transferred from the integrated circuit to be out of synchronization with the external system clock. This skew in the clock signal internal to the integrated circuit is furthered by the delays incurred in the signal passing through the clock input buffer and driver and through any associated resistive-capacitive circuit elements. One solution to the problem of clock skew is the use of a synchronous mirror delay, and another is the use of delay-locked loops.
Delay-locked loops (DLL) are feedback circuits used for synchronizing an external clock and an internal clock with each other. Typically, a DLL operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal.
A synchronous mirror delay circuit (SMD) is a circuit for synchronizing an external clock and an internal clock with each other. The SMD can acquire lock generally within two clock cycles. The SMD has a period of delay, known as a delay range. The delay range of the SMD determines the actual operating range, or clock frequency, within which the integrated circuits (ICs) can operate. In other words, it is desired to reduce the number of delay stages required in the SMD while maintaining the lock delay range. One goal is to improve the efficiency of the SMD to maintain the proper operating range and to reduce the required area and power consumption of the SMD.
For the conventional SMD implementations, two delay lines are required, one for delay measurement, one for variable mirrored delay. The effective delay length for both delay lines is defined as:
tdelay=tckxe2x88x92tmdl 
where tck is the clock period, tmdl is the delay of an input/output (xe2x80x9cI/Oxe2x80x9d) model, including clock input buffer, receiver, clock tree and driver logic. The delay stages required for each delay line is given by:   N  =                    t                  d          ⁢                      xe2x80x83                    ⁢          e          ⁢                      xe2x80x83                    ⁢          l          ⁢                      xe2x80x83                    ⁢          a          ⁢                      xe2x80x83                    ⁢          y                            t        d              =                            t                      c            ⁢                          xe2x80x83                        ⁢            k                          -                  t                      m            ⁢                          xe2x80x83                        ⁢            d            ⁢                          xe2x80x83                        ⁢            l                                      t        d            
where td is the delay per stage. The worst case number is given by:       N          w      ⁢              xe2x80x83            ⁢      o      ⁢              xe2x80x83            ⁢      r      ⁢              xe2x80x83            ⁢      s      ⁢              xe2x80x83            ⁢      t        =                              t                      c            ⁢                          xe2x80x83                        ⁢            k                          ⁡                  (                      l            ⁢                          xe2x80x83                        ⁢            o            ⁢                          xe2x80x83                        ⁢            n            ⁢                          xe2x80x83                        ⁢            g                    )                    -                        t                      m            ⁢                          xe2x80x83                        ⁢            d            ⁢                          xe2x80x83                        ⁢            l                          ⁡                  (                      f            ⁢                          xe2x80x83                        ⁢            a            ⁢                          xe2x80x83                        ⁢            s            ⁢                          xe2x80x83                        ⁢            t                    )                                    t        d            ⁡              (                  f          ⁢                      xe2x80x83                    ⁢          a          ⁢                      xe2x80x83                    ⁢          s          ⁢                      xe2x80x83                    ⁢          t                )            
For example, where tck (long)=15 ns (as in a 66 MHz bus), tmdl (fast)=1 ns and td (fast)=110 ps,       N          w      ⁢              xe2x80x83            ⁢      o      ⁢              xe2x80x83            ⁢      r      ⁢              xe2x80x83            ⁢      s      ⁢              xe2x80x83            ⁢      t        =                              15          ⁢                      xe2x80x83                    ⁢          ns                -                  1          ⁢                      xe2x80x83                    ⁢          ns                            110        ⁢                  xe2x80x83                ⁢        ps              ≈    128  
For two delay lines in an SMD, a total of 256 stages are needed to adjust the delay.
When locking, tlock=din+tmdl+(tckxe2x88x92tmdl) (measured)+(tckxe2x88x92tmdl) (variable)+dout. This is the conventional equation to calculate the lock time of the SMD, which is generally two clock cycles, based on sampling from one rising edge to the next rising edge of the internal clock signal.
Therefore, one goal of the present invention is to reduce the effective delay stages used in the SMD while maintaining the lock range.
The present invention solves the aforementioned problems, and improves the efficiency of the synchronous circuitry for the internal clock signal to lock with the external clock signal.
In one aspect of the invention, a phase detection and selection circuit includes a phase detector for receiving a clock input signal CIN and a clock delay signal CDLY. Each signal has is timing conditions and generates a plurality of output signal combinations, each combination corresponding to pre-defined phases of the signals based upon the timing characteristics. Logic is associated with the phase detector to select one of the output signal combinations corresponding to the timing conditions of the signals. The timing characteristics define a period of CIN as tck and also define a period from a rising edge in CIN to a rising edge in CDLY as tmdl, and wherein when tmdl greater than tck/2, CIN is input into the SMD, and when tmdl less than tck/2, an inverted clock signal CINxe2x80x2 is input into the SMD to reduce the number of delay stages in the SMD.
In another aspect of the invention, a method of improving the efficiency of a synchronous mirror delay circuit comprises the steps of providing a clock input signal CIN, an inverted clock signal (CINxe2x80x2) and a clock delay signal CDLY, each having timed characteristics. The method includes interposing a phase detector and selection system between an external clock signal and a synchronous mirror delay circuit, and determining which of a number of phases the signals are in based on the timing characteristics, and directing the signals based upon the phase of the signals.
In another aspect of the invention, a phase detection and selection circuit for a delay-locked loop (DLL) includes a phase detector for receiving a clock input signal CIN and a clock feedback signal CKFB. Each signal has timing conditions and generates a plurality of output signal combinations, each combination corresponding to pre-defined phases of the signals based upon the timing characteristics. Logic is associated with the phase detector to select one of the output signal combinations corresponding to the timing conditions of the signals. The timing characteristics define a period of CIN as tck and also define a period from a rising edge in CIN to a rising edge in CKFB as te, and wherein when te less than tck/2, the effective delay of the DLL is less than tck/2.
USPTO Backgrounds
USPTO Backgrounds