1. Field of the Invention
The present invention relates, in general, to integrated circuits and, more particularly, to integrated circuits having charge pump circuits generating a power supply voltage from an external power supply voltage.
2. Relevant Background
Electronic systems usually comprise ICs manufactured with a variety of technologies. This has created a need for multiple power supply voltages to be supplied on a single printed circuit board to support the various types of devices on that board. Standard IC voltages required by typical devices range from 5.0 volts to 3.3 volts, or lower voltage. However, there are a number of devices that require power at voltages in addition to the standard available voltages. These include data communications circuits that often require negative voltages, and interface circuitry such an the RS232 interface that specifies voltages ranging from +/-25V. Moreover, some ICs have different voltage requirements internally although they receive power from an industry standard power supply level. Being able to generate a range of voltage levels, including negative voltages and voltages larger in magnitude that the supplied voltage provides a great deal of flexibility to the circuit designer. Also, higher voltage levels often enable faster switching for better performance.
A practical solution to this disparity is to provide DC/DC converter circuitry that changes an input DC voltage into a higher or lower DC voltage required by another device. A negative charge pump operates to generate a negative voltage by charging a pump capacitor during a first half-cycle of a clock to the level of a source voltage. During a second half-cycle the pump capacitor is disconnected from the source and coupled, with its polarity switched, to a reservoir capacitor, thereby pumping charge to the reservoir capacitor and providing an output that is approximately the negative of the input voltage.
A positive charge pump may also operate to generate a higher voltage than the supply voltage (i.e., a "step-up" converter) by coupling the pump capacitor to the source voltage during the first half-cycle. During the second half-cycle, the pump capacitor's positive terminal is disconnected from the source voltage and the capacitors negative terminal is coupled to the source voltage in its place. The pump capacitor's positive terminal is then coupled to the reservoir capacitor to charge it to approximately twice the source voltage.
Larger high output charge pumps usually run at lower frequencies and therefore are not optimized for size. The size of a large, low frequency charge pump may be a limiting factor in obtaining the smallest IC chips as possible. It is desirable to make on-chip charge pumps as small as possible especially when the charge pumps occupy a significant area of the chip. For a target output current, the smaller the size of the charge pump, the higher proportionately the operating frequency must be. Typically, for high-current-output (e.g., greater than 5-10 milliamp) charge pumps, the operating frequency of the pump is dictated by the peak operating current and the rate of change in operating current (di/dt), as well as the size of driver and support circuitry.
One problem with a higher frequency charge pump is that regulation of the output voltage level becomes harder since it might take multiple cycles to turn on and off the charge pump which would result in an unwanted hysteresis. A charge pump whose output capacity per pump cycle is large relative to the load it is driving could change the voltage on the load an appreciable amount. In this case, waiting multiple pump cycles after a regulation point is reached to turn on or off the charge pump is not acceptable.
To remedy this problem, high speed and high power regulation methods utilizing direct current (d.c.) differential amplifiers are used. In this solution, a small portion of time at the beginning of a pump cycle is used to sense whether the voltage on the load is at or below a reference level. If the voltage is below, then a pump is initiated. If the voltage is above, then no pump occurs. With the operating frequency approaching 30 Mhz (33ns period), less than about 20% of each clock cycle (i.e., 7 ns) could be devoted to regulation. Although a fast regulation scheme can be accomplished, a large portion of the total allotted charge pump current is used for regulation in this circumstance. When using a high speed d.c. differential regulation scheme, power consumption is a problem.
If a high frequency charge pump is implemented in an IC that uses an active and standby mode, operation can become more complex. Even if power consumption during the active mode can be tolerated, power consumption by the charge pump might still be a problem during standby mode. Typically the standby mode requires much lower power consumption yet the charge pump must be operational at least some of the time. To conserve power, which is the purpose of the stand-by mode, it is desirable to turn off high powered regulation circuitry when not in use. While still in standby mode, the high powered regulation circuitry must be turned on and stabilized before entering a pump cycle requiring more complicated control and timing circuitry. This stabilization time consumes power and quite possibly increase the current consumption specification during standby.
Another method to decrease the current consumption during standby, is to totally shut-off the high powered regulator and instead use a very low power regulator that is always on. This method requires critical circuitry to ensure that multiple or partial pumps do not occur since the low power regulator takes some time for decisions to be made. In another variant, a low power, low output current pump is operational during standby mode so that a slow turn on or off would only produce a small hysteresis on the output voltage. These prior solutions all require more circuitry and complicated control logic.
USPTO Backgrounds
USPTO Backgrounds