1. Field of the Invention
The present invention relates to a method of forming a capacitor in a semiconductor device, and more particularly, to a method of forming a capacitor in a semiconductor device that is suitable for a SOC (Silicon On a Chip) device.
2. Background of the Related Art
In an exemplary conventional method of forming a memory capacitor in a DRAM device, a cylinder type capacitor is employed, as a shown in FIG. 1.
Referring to FIG. 1, the conventional method of forming the capacitor will be described roughly.
A word line 200 is formed on a semiconductor substrate 100. An interlayer insulating film 300 and a wet anti-etch film 400 are then formed on the entire structure including the word line 200. Next, a series of processes for forming portions of the wet anti-etch film 400 and the interlayer insulating film 300 are implemented to form a source contact 500. Thereafter, a bottom electrode 600 of a cylinder type connected to the source (not shown) through the source contact 500 is formed. A dielectric film 700 is then formed on the bottom electrode 600. A conductive layer 800 is deposited on the entire structure including the dielectric film 700 to form a plate electrode. Thereby, the capacitor of the cylinder type is completed.
In this capacitor of the cylinder type, it is a general trend that the height of the cylinder is increased in order to increase the area of the capacitor. In order to implement devices such as SOC, however, it is required that a smoothing process for mitigating the steps of the DRAM unit and the logic circuit unit be implemented. Due to this, there are disadvantages that there is a limit in increasing the height of the cylinder and it is difficult to implement a deep metal contact. Furthermore, at least four mask processes are required in order to implement the capacitor of the cylinder shape shown in FIG. 1. Therefore, there is a disadvantage that the process is complicated.
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art, and an object of the present invention is to provide a method of a method of forming a capacitor in a semiconductor device capable of implementing the capacitor by means of more simple process without affecting implementation of a logic device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method of forming a capacitor in a semiconductor device according to the present invention is characterized in that it comprises the steps of forming word lines on a semiconductor substrate in which semiconductor constitution elements are formed, sequentially forming a first interlayer insulating film, a first conductive layer and a second interlayer insulating film on the entire structure including the word lines, removing portions of the second interlayer insulating film, the first conductive layer and the first interlayer insulating film to form contact holes, forming a second conductive layer on the entire structure including the contact holes and then patterning the second conductive layer to connect the first and second conductive layers, removing the second interlayer insulating film without a mask process to form a bottom electrode consisting of the first and second conductive layers, etching the first conductive layer using the second conductive layer as an etch pattern without a mask process, and forming a dielectric film and a top electrode on the entire structure including the bottom electrode.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
USPTO Backgrounds
USPTO Backgrounds