1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a method and a gate structure for threshold voltage modulation in transistors.
2. Description of the Related Art
If a transistor is scaled down to improve the performance thereof, gate leakage may increase as a thickness of a gate dielectric layer is reduced. In order to cope with this concern, the material of a gate dielectric layer may be replaced with a high-k material having a dielectric constant that is larger than the dielectric constant of SiO2. The high-k material may include a metal oxide containing hafnium, zirconium, or the like. However, the use of the high-k material creates a concern of a Fermi level pinning effect. This concern is raised due to contact between the high-k material and a polysilicon gate electrode. Fermi level pinning is a basic characteristic of an interface between a polysilicon gate electrode and a metal oxide, and tends to increase the threshold voltage of a transistor.
Recently, in order to overcome Fermi level pinning, a gate stack including a high-k material and a metal gate electrode has been suggested. However, when fabricating a CMOS device, it is difficult to form metal gate electrodes with an N-type work function and a P-type work function that require threshold voltages (Vt) appropriate for respective transistors. Also, even when metal gate electrodes with work functions appropriate for respective transistors are formed, the effective work functions of gate stacks may be changed due to various factors that are based on the material of a gate dielectric layer, a gate stack forming process (for example, an etching process and a thermal process at a high temperature), and so forth.
USPTO Backgrounds
USPTO Backgrounds