1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device compatible with a SRAM and employing a ferroelectric memory or a DRAM for a memory core thereof.
2. Description of the Background Art
In recent years, cellular phones have gained popularity causing a high demand for a pseud-SRAM configured for the cellular phones. Such a pseud-SRAM includes: an asynchronous pseud-SRAM asynchronously operating with an external input signal; a synchronous pseud-SRAM synchronously operating with an external input signal such as an external chip enable signal, and internally generating a clock signal in chronological order for controlling an internal operation; and the like. In order to enhance the degree of integration, a DRAM or a ferroelectric memory (FeRAM: ferroelectric RAM) is used for a memory core of these pseud-SRAMs and they are mass-produced.
A pseud-SRAM configured as shown in FIG. 21 is an example of a conventionally used pseud-SRAM. The pseud-SRAM shown in FIG. 21 receives data to be written when an external write enable signal XWE rises, as illustrated in a timing chart of FIG. 22.
Other examples of the pseudo-SRAM are: a pseud-SRAM receiving data to be written in accordance with a falling transition of an external write enable signal, as shown in FIGS. 23 and 24 (see “Transistor Gijutsu SPECIAL” No. 25, CQ Publishing Co., Ltd., Jan. 1, 1991, p. 23); a pseud-SRAM of a late-write system (see Japanese Laid-Open Patent Publication No. 2003-308692); a pseud-SRAM receiving an address in accordance with a falling transition of an external chip enable signal XCE, and the received address may change its value after a certain period of time is passed (held) from the falling transition of the external chip enable signal XCE, as shown in FIGS. 25 and 26 (see Japanese Laid-Open Patent Publication No. 10-106275); and the like.
However, the conventional pseud-SRAM has following problems. In the conventional pseud-SRAM, one cycle completes when an address is received in synchronization with an external chip enable signal XCE, and then data to be written is received into a chip, as necessary, in accordance with transitions of the external write enable signal XWE. Under such a scheme, when a ferroelectric memory or a DRAM causing a data destruction as a result of a read-out is used for a memory core, a data rewrite operation becomes necessary. When a time period for the data rewrite operation is considered, a cycle time becomes long, and thus, the conventional pseud-SRAM is not suited for a high-speed input/output of data.
Further, a synchronous pseud-SRAM capable of successively transferring data at a high-speed has been proposed, but, to achieve such a high-speed transfer, a pin needs to be separately provided for an external reference clock signal, and therefore, a problem of compatibility with SRAM emerges.
Further, although a time period to perform the rewrite operation can be sufficiently provided by using a portion of a time period during which the external chip enable signal XCE is taking an “H” level (time period for precharging) or the like, if noise is generated in the external chip enable signal XCE while precharging, a sufficient precharge time required for the rewrite cannot be ensured. In addition, if a voltage drop due to a power cut occurs before a completion of one cycle, a sufficient precharge time cannot be ensured, thereby disabling a completion of the rewrite operation, in some cases.
As such, when a rewrite operation is performed during the precharge time for the external chip enable signal XCE, there is a problem that a sufficient time period required for the rewrite cannot always be ensured due to an external factor. When, particularly, a ferroelectric memory is used, data retention is essential, and therefore, ensuring a sufficient time period for a rewrite operation is important.
As described above, the conventional pseud-SRAM has problems in data reliability and performing a high-speed process. Also, in addition to the above problems, the pseud-SRAM employing a ferroelectric memory has a problem in noise tolerance and data retention in a case of a power cut.
USPTO Backgrounds
USPTO Backgrounds