The present invention is related to a semiconductor device having a non-volatile storage element capable of storing at least 4 values of information (namely, 2 bits of information) into a single memory cell, for example, an electrically reprogramable non-volatile semiconductor memory device such as a flash memory, and furthermore, is related to a technique effectively applicable to a data processing system such as a file memory system with using this non-volatile semiconductor memory device.
Conventionally, non-volatile semiconductor storage devices such as flash memories have been proposed. These storage devices are capable of storing information by injecting and/or extracting electrons with respect to floating gates. A flash memory owns a memory cell transistor having a floating gate, a control gate, a source, and a drain. In this memory cell transistor, when electrons are injected into the floating gate, a threshold voltage would be increased, whereas when electrons are extracted from the floating gate, the threshold voltage would be decreased. The memory cell transistor may store therein information in response to the higher/lower threshold voltages with respect to a word line voltage (namely, voltage applied to control gate) used to read out data. Although not having restriction intentions, the lower threshold voltage condition of the memory cell transistor will be referred to as an xe2x80x9cerasing statexe2x80x9d, and the higher threshold voltage condition thereof will be referred to as a xe2x80x9cwriting statexe2x80x9d in this specification.
Among these flash memories, such a flash memory is available that information having more than 4 values can be stored in a single memory transistor. For example, such multi-level memories are described in Japanese Publication xe2x80x9cNIKKEI MICRODEVICExe2x80x9d issued in November, 1994, pages 48 to 49, and further Japanese laid-opened Patent Application No.9-297996/1997 opened in 1997.
In a multi-level memory, for example, if a selection can be made of one state from an erasing state and first to third writing states whose threshold voltages are different from each other with respect to this erasing state, then information having four values can be stored in a single memory cell transistor. If an erasing operation is carried out before a writing operation, then information having four values can be stored by determining that all of the first to third writing states is not selectable, or any one of the first to third programing states is selected. In this programing operation, such program control information is required so as to determine as to whether or not the programing operations are selected in order to separately obtain the first programing state through the third programing state. To save such program control information, a sense latch circuit and a data latch circuit, provided on each of bit lines, may be employed.
A sense latch circuit is constructed of, for example, a static latch. One end of each of bit lines is connected to a pair of input/output terminals of this sense latch circuit, and a drain of the above-described memory cell transistor is connected to each of these bit lines. Moreover, a data latch circuit is connected to the other end of each of bit lines. When either a readout voltage or a verify (verification) voltage is applied to a control gate of the memory cell transistor, the above-described sense latch circuit senses as to whether or not a current may flow through the source-to-drain path. At this time, the bit line provided on one operation non-selected side of the sense latch circuit is precharged to a reference level. Also, when data is written by forming a high potential difference between the control gate of the memory cell transistor and the drain thereof, the drain voltage is increased, or decreased every memory cell, so that it is possible to discriminate the program selection to the memory cell from the program non-selection to the memory cell. In this case, the sense latch circuit latches the data in correspondence with the program selection, and the program non-selection. This latched data corresponds to the above-explained program control information.
Such program control information is produced via a data converting circuit every 2 bits of externally supplied program data, and then is latched by the sense latch circuit of the program-selected bit line and by each of the data latch circuits for the bit line pair which commonly use this sense latch circuit. In the case that the programing operation is carried out in unit of a word line, the program control information is previously latched into the above-described sense latch circuit and data latch circuit as to all of bit lines. Which commonly use the word line.
In the programing operation, a decision is first made as to whether or not the memory cell is brought into the first program state in accordance with the program control information latched by the sense latch circuit. Next, another decision is made as to whether or not the memory cell is brought into the second program state in accordance with the program control information which has been internally transferred from one data latch circuit to the sense latch circuit. Moreover, a further decision is made as to whether or not the memory cell is brought into the third program state in accordance with the program control information which has been internally transferred from the other data latch circuit to the sense latch circuit. In this manner, the information having the four values specified by the 2-bit data can be stored into a single memory cell. In the above-explained programing operations from the first programing state to the third programing state, such a verify operation is carried out as to whether or not the threshold voltage of the memory cell reaches the threshold voltage allocated to each of the first to third programing states.
At this time, there is such a memory cell which is brought into an overprograming state among these memory cells with respect to each of the first to third programing states. In this memory cell, the threshold voltages under preceding/succeeding programing states cannot be discriminated from each other. For instance, the threshold voltage of the memory cell of the first programing state becomes high, which cannot be discriminated from the threshold voltage of the second programing state. In such a case, in order to retry the programing operation from the beginning stage, after the erasing operation is carried out with respect to the memory cell to be written, the above-explained programing operation is retried.
However, when the programing operations from the first programing state to the third programing state are once carried out, the program control information which has been first latched into the sense latch circuit would be overwritten by another program control information internally transferred from the data latch circuit to thereby disappear. As a result, when the reprograming operation is performed due to the overprograming operation, the same program data must be again received from the external device. To this end, the control circuit for access-controlling the flash memory must save the program data in a work memory or the like for the time being after the programing operation is carried out with respect to the flash memory. Thus, the work load for access-controlling the flash memory would also be increased. The Inventors could reveal that this fact may lower the access efficiency of the flash memory, or the data processing efficiency.
Furthermore, in such a case that the programing operation itself will finally fail due to the failure operation of the reprograming operation caused by the overprograming operation, it is imaginable that the program data existed in this failure programing operation is stored into another storage area of this flash memory, or another flash memory. Similar to the previous case, the flash memory related to this failure programing operation can no longer save the program data at this time. As a consequence, also in this failure case, the control circuit for access-controlling the flash memory must save the program data in a work memory or the like for the time being after the programing operation for this flash memory. Thus, this fact may lower the access efficiency of the flash memory, or the data processing efficiency.
An object of the present invention is to provide a semiconductor device in which program data is not lost by a programing operation, and this program data is externally supplied to a data latch circuit in order to program information having multi-levels to the respective memory cells.
Another object of the present invention is to provide a semiconductor device which is no longer required to again receive the externally supplied program data in such a case that a programing operation of multi-level information is retried with respect to a memory cell.
A further object of the present invention is to provide such a semiconductor device that when a programing operation is accomplished under abnormal condition, the program data which has been internally saved at the end of this abnormal programing operation can be rewritten by designating another memory address.
A still further object of the present invention is to provide a semiconductor device that when a programing operation is accomplished under abnormal condition, the program data related to the end of this abnormal programing operation can be outputted outside this semiconductor device.
The above-described objects and other objects, and also novel features of the present invention may be apparent from a detailed description of the present specification and the accompanying drawings.
The typically disclosed invention will now be summarized as follows:
[1] A semiconductor device, according to a first aspect of the present invention, is featured by that in a semiconductor device capable of storing information having multi-levels into a single electrically erasable/programable non-volatile memory cell, in such a case that an overprogram state of the memory cell is detected by performing an overprogram detecting operation (either word disturb detection or erratic detection) in connection with a programing operation, even when the programing operation is retried by again performing the erasing operation, internal saving of the program data required for the programing operation can be guaranteed.
In other words, the semiconductor device is constituted by a sense latch circuit having one pair of input/output terminals; bit lines provided in correspondence with the respective input/output terminals of the sense latch circuit; a plurality of electrically erasable/programable non-volatile memory cells selectively connected to the bit lines; a data latch circuit coupled to each of the bit lines; input/output means capable of interfacing the data latch circuit with an external device; and control means for controlling data reading/erasing/programing operations with respect to the memory cell. The control means causes the data latch circuit to save externally supplied program data; produces program control information every time the data programing operation is carried out; and causes the latch circuit to latch the produced program control information for determining that the non-volatile memory cell is brought into any state of different threshold voltages, the non-volatile memory cell being selected to be connected to the bit line based upon the program data having plural bits saved in the data latch circuit.
In accordance with the above-explained control means, the externally supplied program data is latched into the data latch circuits, and a judgment is carried out as to whether or not the latched program data corresponds to which threshold value of the multi-levels every time the programing operation of the plural stages is performed. Then, the program control information control corresponding to this judgment result is latched into the sense latch circuit. In response to the program information latched in the sense latch circuit, the programing operation for setting the threshold voltages of the multi-levels to the memory cell is carried out in a stepwise manner. As a consequence, even when the programing operation is accomplished, the program data which has been originally and externally supplied is left in the data latch circuits. Accordingly, even when the programing operation of the multi-levels information with respect to the memory cell is carried out again based upon the detection result of the word disturb detecting operation, or the detection result of the erratic detecting operation, the program data is no longer again accepted from the external devices.
To detect the overprograming state, the following method may be employed. That is to say, the above-described control means furthermore judges as to whether or not a threshold voltage which should be set to a memory cell is equal to a threshold voltage corresponding to such a threshold voltage to be checked by an overprogram detection every time a verify reading operation required for the overprogram detection is performed by calculating the data latched by the data latch circuit; the control means causes the sense latch circuit to latch the judgment result; in the case that the judgment result data latched in the sense latch circuit means the corresponding threshold voltage, the control means precharges the bit line; and the control means checks as to whether or not the precharge state of the bit line is changed by the verify reading operation to thereby detect the overprograming state.
The above-explained control means can retry the programing operation after retrying the erasing operation when the overprograming state is detected.
[2] The present invention, according to a second aspect, is directed to a more concrete calculating/controlling means. The calculating/controlling means according to the first aspect is employed so as to latch the program information into the sense latch circuit. In accordance with this second aspect, another semiconductor device is conceived which is capable of storing information having four values into a single electrically erasable/programable non-volatile memory cell by controlling the non-volatile memory cell to be brought into any one of an erasing state, a first programing state, a second programing state, and a third programing state, the threshold voltages of which are different from each other. At this time, the control means causes the data latch circuit to save externally supplied program data; calculates program control information capable of determining that a non-volatile memory cell selectively connected to the bit line is brought into any one of the erasing state, the first programing state; the second programing state, and the third state while using 2-bit program data as a unit, the 2-bit program data being saved by two data latch circuits connected to the one pair of bit lines for commonly using the sense latch circuit; causes the sense latch circuit to latch the calculated control information every time a programing operation is performed; and controls the first programing state to the third programing state in accordance with the latched programing control information.
Concretely speaking, when the sense latch circuit latches program control information for setting as a first logic value, output data on the side of a memory cell connection selecting bit line, the control means causes the memory cell connected to the bit line set as the first logic value to execute the programing operation. The program control information is calculated by the control means in such a manner that with respect to a first program data bit latched in the data latch circuit provided on the side of one memory cell connection selecting bit line and also a second program data bit latched in the data latch circuit provided on the side of the other memory cell connection non-selecting bit line, both the memory cell connection selecting bit lines commonly using the sense latch circuit, an OR gating operation between logically inverted data of the first program data bit and the second program data bit; another OR gating operation between the first program data bit and the second program data bit; and another OR gating operation between the first program data bit and logically inverted data of the second program data bit are carried out based upon the bit line precharge operation by the data latched in the data latch circuits and also the sense operation by the sense latch circuit; and every time the programing operation is performed, the control means causes the sense latch circuit to latch the OR-gated values sequentially acquired by said OR-gating operations; and causes such a memory cell of the memory cell connection selecting bit line in which the latched OR-gated value becomes the first logic value to perform the programing operation.
The above-described means for judging the overprograming state may be realized by the following more concrete example. The control means furthermore judges as to whether or not a threshold voltage which should be set to a memory cell is equal to a threshold voltage corresponding to such a threshold voltage to be checked by an overprogram detection every time a verify reading operation required for the overprogram detection due to the programing operation is performed by calculating the data latched by the data latch circuit; the control means causes the sense latch circuit to latch the judgment result; in the case that the judgment result data latched in the sense latch circuit means the corresponding threshold voltage, the control means precharges the bit line; and the control means checks as to whether or not the precharge state of the bit line is changed by the verify reading operation to thereby detect the overprograming state. The judging calculation is performed by the control means in such a manner that with respect to a first program data bit latched in the data latch circuit provided on the side of one memory cell connection selecting bit line and also a second program data bit latched in the data latch circuit provided on the side of the other memory cell connection non-selecting bit line, both the memory cell connection selecting bit lines commonly using the sense latch circuit, a negative logic OR gating operation between the first program data bit and the second program data bit; an AND gating operation between the first program data bit and logically inverted data of the second program data bit; and another AND gating operation between the first program data bit and the second program data bit are carried out based upon the bit line precharge operation by the data latched in the data latch circuits and also the sense operation by the sense latch circuit. Every time the overprograming detection operation is performed, the control means causes the sense latch circuit to latch as the judgment result data the negative logic OR-gated value and the AND-gated values sequentially acquired from the calculations; and when the sense latch circuit latches such judging result data that the output data on the side of the memory cell connection selecting bit line is equal to a second logic value, the control means precharges the memory cell connection selecting bit line via the precharge circuit.
[3] Even when the programing operation fails, the program data at this time is saved inside the semiconductor device by the above means. While paying an attention to this fact, in the case that the retry program command is accepted after the failure programing operation has been accomplished, the control circuit can program the program data already saved in the data latch circuits at the address supplied in connection with this retry program command. Since the semiconductor device owns such a retry function, the memory controller, or the control apparatus for access-controlling this semiconductor device changes either the program address or the sector address with respect to the semiconductor device in which the programing operation has failed, so that the memory controller, or the control apparatus can perform the reprograming operation.
Also, after the programing operation has been accomplished under abnormal condition, the subject to be rewritten may be changed into another semiconductor device. In this case, when the control circuit receives the recovery read command after the programing operation has failed, the control circuit outputs the program data saved in the data latch circuits DLL and DLR via the input/output means to the external device. Due to this recovery function, the control apparatus can readily reprogram the same data into another semiconductor device other than such a semiconductor device where the programing operation has failed. This control apparatus access-controls either the memory controller of the memory card, or the memory card constituted by the plurality of semiconductor devices.
[4] The reprograming operation may be performed in such a manner that after the erasing operation is carried out by the erase command, the programing operation is performed with respect to the same area by the program command. Such a reprograming process operation may be realized by a single command, namely one reprogram command. The above-described control means is operated as follows. When the first reprogram command is supplied, the reprogram address is fetched, and also the program data is fetched by the data latch circuit. After the second reprogram command is supplied, the area designated by the reprogram address is erased. Subsequently, the programing operation is controlled based upon the data saved in the data latch circuits. As a result, all of the data of a sector can be rewritten by way of a single command.
Also, data reprograming for a portion of a sector may be realized by a single command. That is to say, when a first reprogram command is supplied, the control means fetches a reprogram address and saves data of the fetched address into the data latch circuit; the control means designates a reprogram address within a range of the reprogram address after saving the data of the fetched address so as to latch the program data into the data latch circuit; after a second reprogram command is supplied, the control means erases the program data of the sector area designated by the reprogram address; and subsequently, the control means controls the programing operation based upon the data saved in the data latch circuit and stored at the sector area designated by the reprogram address.
[5] In the case that a semiconductor device is utilized as a file memory, while a management area is allocated to a sector of this semiconductor device, the remaining portion thereof may be opened as a user area. For example, information related to reprograming times and failure/good sectors is stored into the management area. While data is erased in unit of a sector by a user, such a command for automatically setting the management area out of erasing operation is supported. As a result, the semiconductor device and furthermore the file memory can be made more convenient. In view of this point, a partial erasing command may be supported. In other words, when a first partial erasing command is supplied, the control means acquires a sector address; next, when a second partial erasing command is supplied, the control means saves data of a predetermined area into a data latch circuit corresponding to the predetermined area within an area designated by the sector address and also sets data indicative of an erasing state to a data latch circuit corresponding to other areas within the area designated by the sector address; and furthermore, after the control means performs the erasing operation with respect to the area designated by the sector address, the control means executes the program control operation in accordance with the data set to the data latch circuit.
[6] A memory card may be realized by packaging on a card board, the semiconductor device, a memory controller for access-controlling the semiconductor device, and an external interface circuit connected to the memory controller. Also, a data processing system may be arranged by comprising the semiconductor device, a memory controller for access-controlling the semiconductor device, and a processor for controlling the memory controller.
While paying an attention to a retry programing command, a data processing system may be arranged by comprising the semiconductor device, and a control apparatus for outputting both a retry program command and a program address to the semiconductor-device when the control apparatus detects that a programing operation by the semiconductor device is accomplished under failure state. Also, while paying an attention to a recovery read command, a data processing system is arranged by comprising the semiconductor device, and further a control apparatus for outputting a recovery read command to the semiconductor device when the control apparatus detects that a programing operation by the semiconductor device is accomplished under failure state, and also for capturing program data outputted from the semiconductor device to which the recovery read command is supplied, and further for controlling to program the fetched program data into another semiconductor device.
USPTO Backgrounds
USPTO Backgrounds