Electronic devices commonly include a number of chips to perform a set of functions. These multichip arrangements are subject to inter-chip signaling delays which increase the basic machine cycle time. Multichip modules can partially mitigate this problem. However, multichip modules are complex and expensive.
Efforts are ongoing to include more and more system functions on a single die. As device feature sizes shrink to 1.0 micrometer or less, and die sizes increase to over 1 cm2, it becomes possible to put an entire processor, including floating point unit, memory management, and cache memory, on a single CMOS (complementary metal-oxide semiconductor) die. Examples of this fully integrated approach include most of today's fastest microprocessors, including Digital's 21064 RISC microprocessor and Intel's i486. This fully integrated approach is slowly being applied to mainframe computers.
Modern mainframe computers typically rely upon emitter coupled logic (ECL) . ECL is a very fast logic family with superior load driving capabilities. However, in its usual gate array or standard cell form, ECL has a lower layout density than custom CMOS. In addition, ECL has high static power dissipation. For instance, a high performance ECL microprocessor will dissipate over 100 W. For proper performance, the package should uniformly distribute 30 amps and maintain the die at less than 100 deg C. The size and high watt density of such a chip precludes conventional power distribution strategies. Similarly, acoustic noise considerations preclude the use of conventional solid metal heatsinks. Thus, even single-chip packaging presents a considerable challenge, particularly in power distribution and cooling.
The cooling mechanisms for ECL dies must address a number of problems. As previously stated, conventional solid metal heatsinks are not feasible. However, one prior art technique which may be helpful in cooling an ECL die is a thermosiphon. A thermosiphon absorbs heat by vaporizing liquid on a boiling surface and transferring the vapor to a condenser where it cools and reliquefies. Gravity then returns the liquid to the boiler to repeat the cycle.
In order for a thermosiphon to successfully cool an ECL die, a number of problems with prior art devices must be solved. one shortcoming with prior art devices is that additional thermal interfaces are used between the die and the thermosiphon. The thermal interfaces add manufacturing complexity and compromise efficient heat transfer from the die.
The choice of operating fluid within the thermosiphon significantly affects the thermosiphon performance. Water is a desirable working fluid for a thermosiphon since it has such a high heat of vaporization, high thermal conductivity, and is nontoxic and nonflammable. However, at subatmospheric pressures and at high heat fluxes, the boiling behavior of water becomes sporadic. Thus, it would be desirable to improve the boiling behavior of the fluid within the thermosiphon while still employing a fluid which is non-toxic and non-flammable.
Thermosiphon performance is also compromised by contaminants which may migrate into the fluid. Contaminants typically enter the fluid from joint regions of the thermosiphon. It would be advantageous to eliminate this problem.
A final problem with prior art thermosiphons relates to the control of excess temperatures. A mechanism should be provided which prevents the thermosiphon from exploding if it is exposed to fire or some other high temperature fault condition.
There are numerous power distribution problems associated with ECL dies. ECL dies require large currents while maintaining tight voltage tolerances. In particular, a high performance ECL microprocessor will typically require 30 amps. The same chip will typically have a signal swing of approximately 600 mV. In contrast, a CMOS chip will have a signal swing of approximately 3.3 V.
Special design considerations are required to assure highly uniform voltages at all circuit locations. In addition, the packaging should accommodate power transients caused by switching activity in the circuits and signal wires. Power transients may significantly disrupt chip performance.
The power distribution problems for an ECL microprocessor are especially acute in relation to the bond wires coupling the chip to the package. Most microprocessors, and other VLSI devices, employ aluminum wires with a diameter of approximately 33 micrometers. Aluminum has a melting point of approximately 660 deg C. This melting point limits the current per wire to approximately 200 MA. Thus, to provide the 30 amps required for an ECL microprocessor die would require 300 aluminum bond wire for the power alone. This is unacceptably high because a microprocessor will require approximately 350 signal wires and approximately 150 power wires. Thus, a modified bond wire configuration is required.
The problem with the high number of bond wires is compounded by the fact that 33 micrometer diameter wires generally require a pitch (i.e. , distance between wire bond pads) of at least 100 micrometers. To increase bondwire density, other designers have tried staggering the pads around the edge of the die. While this approach can accommodate wider bonding tools and bonds, it increases wire-to-wire shorting risks. This problem is especially acute with multi-tier packages which have poor tier-to-tier registration. A multi-tier package is desirable for a high density chip such as a microprocessor. Wedge bonding is the technique typically employed in multi-tier packages. The problem with wedge bonding is that the shallow wire departure angle at the first row of bond pads requires a relatively large spacing to the next row of bond pads to alleviate the potential for shorting. This approach makes the wires longer and consumes valuable die space. It would be advantageous to develop a multi-tier package which employs relatively short bond wires which can carry relatively large currents, and simultaneously be space efficient.
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