A conventional computer system 10 shown in FIG. 1 includes a central processing unit (“CPU”) 12, such as a microprocessor, that is coupled to a bus bridge 16, memory controller or the like. The CPU 12 is also typically coupled to a cache memory 18 to allow instructions and data to be more frequently accessed by the CPU 12. The bus bridge 16 allows the CPU 12 to receive program instructions from a system memory 20. The CPU 12 can also write data to and read data from the system memory 20 through the bus bridge 16. The CPU 12 also preferably transfers video data from the system memory 20 to a display system including a graphics processor or graphics accelerator 24, a video RAM 26, and a conventional display 28, such as a cathode ray tube (“CRT”), liquid crystal display (“LCD”) or field emission display (“FED”). The graphics accelerator 24 processes graphics data to free up the CPU 12 from performing that function. The graphics accelerator 24 writes video data to and reads video data from the video RAM 26, and generates a video signal that is applied to the display 28. The bus bridge 16 also interfaces the CPU 12 to a peripheral bus 30, such as a peripheral component interconnect (“PCI”) bus. The peripheral bus 30 is, in turn, coupled to at least one mass storage device, such as a disk drive 32 and a CD ROM drive 34, and at least one user interface device, such as a keyboard 36 and a pointing device 38. The computer system 10 may, of course, contain a greater or lesser number of components.
As shown in FIG. 2, the system memory 20 is generally in the form of one or more memory modules 44 that includes several integrated circuit memory devices 40, such as dynamic random access memories (“DRAMs”) and which may be Advanced Technology (“AT”) Drams, such as RAMBUS DRAMs (“RDRAMs”) or synchronous link DRAMs (“SLDRAMs”), mounted on a printed circuit board 42. Typically, the memory modules 44 are removably plugged into a motherboard 46 of a computer system 10 (FIG. 1). The size of the computer system's memory can be increased by simply plugging additional memory modules 44 into the motherboard 46. Memory modules 44 are commercially available in standardized configurations, such as a single in-line memory module (“SIMM”) and a double in-line memory module (“DIMM”). The memory modules 44 are electrically coupled to a memory controller 50 or other device (not shown) mounted on the mother-board 46 using standardized memory interfaces 52. These standardized memory interfaces 52 generally include a data bus, an address bus, and a control/status bus.
Conventional DIMM's have two sides populated with memory devices with each side of the memory module 44 representing an independently addressable memory rank. In conventional memory modules 44, only one rank of memory will be transmitting data at a time, since the memory interface 52 is shared between the two ranks. The physical design for such modules typically consists of one rank on each side of the memory module 44. The printed circuit board (PCB) or module substrate of a conventional memory module 44 has power and ground reference planes that are shared for the entire rank, and in some cases, shared between both ranks of memory.
FIG. 3 shows a top schematic representation of a conventional memory module 44. In this example, each memory rank 62 consists of eight memory devices 40 (e.g. DRAMs). A driver chip 64 is attached to one side of the memory module 44 and is operatively coupled to the memory interface 52 (FIG. 2). The driver chip 64 receives control signals and address signals from the memory interface 52 and multiplexes and routes these signals to the appropriate memory devices 40 on the memory module 44 and receives and de-multiplexes data signals from the memory devices 40 and routes these signals back to the memory interface 52. The PCB typically includes a connector edge adapted for insertion into a corresponding socket of the computer system 10, as disclosed, for example, in U.S. Pat. Nos. 6,111,757 and 5,513,315 issued to Dell et al.
FIG. 3 also shows a PCB stackup 60 of the conventional memory module 44. The PCB stackup 60 includes top and bottom conductive layers S1, S4 which are used as signal routing layers. Ground layers G1, G2 are formed adjacent to the top and bottom signal routing layers S1, S4 which serve as ground planes to deliver the ground connection to the memory devices 40, and to provide a return path for data signals. Next, voltage layers V1, V2 are provided for delivering power to the memory devices 40. Finally, signal layers S2, S3 are provided for command/address and clock signals. The voltage layers V1, V2 may also provide a return path for the command/address and clock signals that may be contained on signal layers S2, S3. The ground layer G1 is a common reference plane for all of the memory modules 40 of rank A, and this ground layer G1 is electrically connected to ground layer G2 using plated through holes (not shown). In some memory modules, a six layer PCB stackup design is used, and the first voltage layer V1 and second ground layer G2 are eliminated, as disclosed, for example, in U.S. Pat. No. 5,973,951 issued to Bechtolsheim et al.
Although desirable results have been achieved using conventional memory module 44 of the type described above, some drawbacks exist. One drawback, for example, is that because the memory interface 52 is shared between the two ranks 62, the driver chip 64 accesses only one memory rank 62 at a time. For advanced data bus configurations having greater bandwidth than conventional 32-bit or 64-bit configurations, memory modules 44 that can only access the memory ranks 62 sequentially cannot fully utilize the capacity of such advanced data bus configurations. Thus, conventional memory modules 44 may hamper the speed at which advanced computer systems may operate.
USPTO Backgrounds
USPTO Backgrounds