The present invention relates generally to the use of electrodes in semiconductor devices, and more particularly relates to the formation of small electrodes having reduced contact areas which may be utilized, for example, in semiconductor memory devices. More specifically, the present invention relates to the manufacture of a small-sized electrode such as is useful to control the size of the active area of a chalcogenide resistive element in a memory cell of a chalcogenide memory device.
Electrodes are used in a variety of integrated circuit devices. In certain devices, such as memory devices, the ability to efficiently manufacture small electrodes is crucial in maximizing the performance and cost-efficiency of the device. A memory device can have a plurality of memory arrays, and each memory array can include hundreds of thousands of memory cells. Each memory cell generally includes a memory element and an access device (such as, for example, a diode) coupled to the memory element. Memory-storage materials, that is, materials that can be made to store information, such as by storing a charge or by changing resistivity, are used to fabricate the memory elements. Electrodes couple each memory element to a corresponding access device. The electrodes can be part of the access device and can also define the memory element.
In certain memory devices, such as memory devices having chalcogenide memory elements, the size of the electrode has a direct relationship to the speed, power requirements, and capacity of the memory device. Chalcogenides are materials which may be electrically stimulated to change states, from an amorphous state to a crystalline state, for example, or to exhibit different resistivities while in the crystalline state. Thus, chalcogenide memory elements can be utilized in memory devices for the storage of binary data, or of data represented in higher-based systems. Such memory cells will typically include a cell accessible, for example, by a potential applied to access lines, in a manner conventionally utilized in memory devices. Typically, the cell will include the chalcogenide element as a resistive element, and will include an access or isolation device coupled to the chalcogenide element. In one exemplary implementation suitable for use in a RAM, the access device may be a diode.
Many chalcogenide alloys may be contemplated for use with the present invention. For example, alloys of tellurium, antimony and germanium may be particularly desirable, and alloys having from approximately to 55-85 percent tellurium and on the order of 15-25 percent germanium are contemplated for use in accordance with the present invention. Preferably, the chalcogenide element will be generally homogeneous (although gradiented alloys may be utilized), and will be alloys formed from tellurium, selenium, germanium, antimony, bismuth, lead, strontium, arsenic, sulfur, silicon, phosphorus, oxygen and mixtures or alloys of such elements. The alloys will be selected so as to establish a material capable of assuming multiple, generally stable, states in response to a stimulus. It is contemplated that in most cases, the stimulus will represent an electrical signal, and that the multiple states will be states of differing electrical resistance. U.S. Pat. No. 5,335,219 is believed to be generally illustrative of the existing state of the art relative to chalcogenide materials, and is believed to provide explanations regarding the current theory of function and operation of chalcogenide elements and their use in memory cells. The specification of U.S. Pat. No. 5,335,219 to Ovshinski et al., issued Aug. 2, 1994, is incorporated herein by reference, for all purposes. An exemplary specific chalcogenide alloy suitable for use in the present invention is one consisting of Te.sub.56 Ge.sub.22 Sb.sub.22.
An observed property of a chalcogenide element in a memory cell is that the chalcogenide element will have an "active area" which may be less than the area of the entire chalcogenide element. The size of this active area can be controlled by controlling the size of the electrode contact with the chalcogenide element. A primary reason for limiting the active area of the chalcogenide element is that the size of the active area is directly related to the programming current and/or time required to achieve the desired state change. Thus, in the interest of optimally fast programming rates of a memory device, it is desirable to minimize the dimension of electrode contacting the chalcogenide element, to minimize the active area and to thereby facilitate optimally fast programming time and optimally low programming current.
Techniques for forming the electrode of a chalcogenide memory cell include forming a hole in a dielectric layer, and then depositing a conductive material in the hole. Conventional techniques of forming the hole in the insulative layer have included the application of a high current pulse to open a hole having a diameter of on the order of 0.1-0.2 microns. Additional attempts have been made to rely upon photolithography or etching to establish an opening through the insulative layer. All of these methods suffer from technological constraints upon the hole size, and offer less than optimal repeatability.
Accordingly, the present invention provides a new method and apparatus for creating small electrodes, so as, for example, to establish minimally-sized active areas in a chalcogenide layer disposed adjacent to such insulative layer. In a preferred implementation of the invention, the active area of the chalcogenide element can be generally controlled through selection of the electrode size in the insulative layer.
USPTO Backgrounds
USPTO Backgrounds