Static random-access memory (SRAM) is a type of semiconductor memory that does not need to be periodically refreshed. The SRAM is comprised of a plurality of NFET and PFET devices organized in such a way as to provide means of storing electrical data. SRAM cell design optimizes size, power, noise margin, performance, and yield. Generally, SRAM must live with the inherent soft error rates (SER), which is given by design and technology. For a large SRAM, usually the only option is the use of error correction circuitry (ECC); however, such circuitry adds chip area and cycle time.
In SOI technology, the SRAM tends to have a lower SER than in bulk technologies. This is because the SRAM devices are isolated from charge generated in the substrate. This isolation, however, decreases the cell node capacitance, making the cell more sensitive to upset such as from radiation events. Also, because of the floating body, charge injected into a device body will induce a bipolar multiplication effect, which increases the effective collected charge. These two effects limit the SER benefit of SOI. Body-ties reduce the bipolar effect; however, these add cell area.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds