1. Field of the Invention
This invention relates to an enhanced heat dissipating chip scale package method and devices, and particularly to a chip scale package method and device that employs Ball Grid Array Package (BGA package) structure and process to get enhanced heat dissipating effect and small size package.
2. Description of the Prior Art
In the Semiconductor integrated circuit (IC) industry, how to make IC package thin and small size, and get better heat dissipating efficiency in a simple and low cost production process is a heavily focused subject. Among the many known techniques, the chip Scale Package (CSP) technique is a popular method. It can attain the Package size/Chip size ratio below 1.2.
FIG. 1 illustrates a conventional BGA package member 1 which includes a substrate 2 with two metallic circuit layouts disposed respectively on an upper side and a lower side thereof (not shown in the figure). The two metallic circuit layouts are coupled with each other by means of a plurality of plugs (not shown in the figure) running through the substrate 2. The upper side of the substrate 2 adheres to a chip 4 by means of non-conductive resin 3. The lower side adheres to a plurality of solder balls 5. The chip 4 is coupled with the metallic circuit layouts on the upper side by means of gold wires 6. Then a filler 7 (such as EPOXY) is used to cover the top of the chip 4 and the coupling portion between the chip 4 and the substrate 2 to enhance the package reliability.
The BGA Package member 1 set forth above has the shortcomings of large package size and poor heat dissipating property resulting from the filler 7. As the gold wire 6 has to extend outward from the chip 4 to couple with the substrate 2, the substrate 2 should be larger than the chip 4. The Package size/chip size ratio usually is over 1.4 or even 1.6. It becomes a big design limitation.
At present, there is an Enhanced BGA (EBGA) package technique being developed. FIG. 2 illustrates an EBGA package member 10 which includes a chip 11, a Tape substrate 12 which has metallic circuits disposed at one side thereof, a plurality of solder balls 13 adhered to a lower side of the Tape substrate 12 and a metallic heat dissipating member 16. Between the solder balls 13 and the Tape substrate 12, there is a non-conductive solder ball mask 14 for preventing oversize solder balls from making a short circuit with the metallic circuits in the Tape substrate 12. The Tape substrate 12 and the chip 11 are adhered to the heat dissipating member 16 by means of Epoxy 18. The Tape substrate 12 has a center opening to contain the chip 11. The metallic circuits in the Tape substrate 12 are coupled with the chip 11 by means of gold wires 17. The active side of the chip 11 (i.e., where IC layouts are disposed), is molded with a filler 15 to cover the active side of the chip and the gold wire coupling portions. An annular dike ring 19 is disposed around the juncture of the gold wires 17 and the metallic circuits for preventing the filler 15 from overflowing.
Comparing with conventional BGA package, this EBGA package is thinner and has better heat dissipating property. The heat dissipating member 16 also provides support for the chip 11 and the relatively soft Tape substrate 12. However the gold wire 17 coupling is still formed from the chip 11 outward to the Tape substrate 12. The Package Size/Chip size ratio usually is larger than 1.4. It still does not totally meet CSP requirement.
USPTO Backgrounds
USPTO Backgrounds