1. Field of the Invention
The present invention relates to an operational amplifier having large output current, particularly to an amplifier for driving a headphone and an amplifier for driving a speaker utilized for acoustic apparatus and an amplifier suitable for other heavy load drive.
2. Description of the Related Art
In related arts, according to an amplifier for providing large output current, there are provided circuit constitutions as shown by FIG. 17, FIG. 18 and FIG. 19. For convenience, in the drawings, the same constituent elements are designated by the same notations. According to the circuit constitution shown in FIG. 17, a power buffer is constituted by connecting the sources of a P-channel MOS transistor Tr1 the drain of which is connected to a negative power source terminal VSS (for example, 0V) and an N-channel MOS transistor Tr2 the drain of which is connected to a positive power source terminal VDD (for example, 5V) and providing an output terminal OUT, a resistor RN1 and a constant voltage circuit VN are connected in series between an output terminal of an operational amplifier (hereinafter, simply referred to as OP amplifier) 1 and the positive power source terminal VDD from the side of the positive power source terminal VDD, a connection point connecting the resistor RN1 and the constant voltage circuit VN is connected to the gate of the N-channel MOS transistor Tr2, a resistor RP1 and a constant voltage circuit VP are connected in series between the output terminal of the OP amplifier 1 and the negative power source terminal VSS from the side of the negative power source terminal VSS, a connection point for connecting the resistor RP1 and the constant voltage circuit VP is connected to the gate of the P-channel MOS transistor Tr1 and although not illustrated, a feedback resistor is connected between the output terminal OUT and a negative phase input terminal VINN. Further, feedback resistors are similarly provided also in the circuit constitutions of FIG. 18 and FIG. 19. Although not particularly illustrated, the constant voltage circuits VP and VN are publicly-known constant voltage circuits which are arranged proximately to the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 and are constituted by transistors or diodes and resistors thermally coupled thereto. Thereby, temperature-compensated desired idling current is made to flow to the P-channel MOS transistor Tr1 and the N-channel transistor Tr2 and an alternating current signal applied to the negative phase input terminal VINN of the OP amplifier 1, is amplified with small distortion caused by temperature variation. In this case, the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 carry out only current amplification. FIG. 20 shows a relationship among voltages at respective terminals 11, 12 and 13 and FIG. 21 shows drain currents of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2, that is, idling currents II1 and II2, in idling time at which the input signal of the amplifier of FIG. 17 is brought into a no signal state. Voltage at the positive power source terminal VDD is designated by notation VDD and the voltage at the negative power source terminal VSS is designated by notation VSS (0V). A positive phase input terminal VINP of the OP amplifier 1 is fixed to potential VDD-(VDD-VSS)/2 at intermediary voltage of voltages of the positive power source terminal VDD and the negative power source terminal VSS and in the idling time, the intermediary potential is applied also to the negative phase input terminal VINN of the OP amplifier 1 and the terminal 11 is provided with the same voltage.
Further, according to an amplifier of FIG. 18, a power buffer is constituted by connecting the drains of the P-channel MOS transistor Tr1 the source of which is connected to the positive power source terminal VDD and the N-channel MOS transistor Tr2 the source of which is connected to the negative power source terminal VSS and providing the output terminal OUT, a resistor RP1 and a resistor RP2 are connected in series between the output terminal of the OP amplifier 1 and the positive power source terminal VDD, a connection point for connecting the resistors is connected to the gate of the P-channel MOS transistor Tr1, a resistor RN1 and a resistor RN2 are connected in series between the output terminal of the OP amplifier 1 and the negative power source terminal VSS and a connection point for connecting the resistors is connected to the gate of the N-channel MOS transistor Tr2. The P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 receive bias voltages produced at the connection points of the resistors and the output signal of the OP amplifier 1 and carry out current amplification and voltage amplification. FIG. 22 shows a relationship among voltages at respective terminals 21, 22 and 23 and the power source voltage in idling time of the amplifier of FIG. 18 and FIG. 23 shows drain currents Id1 and Id2 of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2.
According to an amplifier of FIG. 19, in the amplifier of FIG. 18, the resistors RP1 and RN1 are replaced by constant voltage circuits VP and VN and by the constant voltage circuits VP and VN, idling currents of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 are determined and by driving the transistors by low impedance, influence of gate capacitance is reduced. That is, according to the amplifier of FIG. 18, values of the respective resistors are reduced for constituting low impedance formation in order to maintain drivability of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2, load on the OP amplifier 1 is increased. According to the amplifier of FIG. 19, large output power is provided without increasing the burden on the OP amplifier 1.
According to the amplifier of FIG. 17, maximum amplitude is reduced by an amount of threshold voltages (hereinafter, simply referred to as xe2x80x9cVthxe2x80x9d) of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2. In other words, it is difficult to lower the power source voltage. Describing in reference to FIG. 20, in idling time, voltage between the terminal 11 and the terminal 12 coincides with Vth of the N-channel MOS transistor Tr2 and voltage between the terminal 11 and the terminal 13 coincides with Vth of the P-channel MOS transistor Tr1. The maximum amplitude, that is, the range of the output voltage becomes a sum of a voltage value produced by subtracting the voltage 12 from the voltage VDD shown in FIG. 20 and a voltage value produced by subtracting the voltage VSS from the voltage 13. Therefore, when the power source voltage is proximate to the sum of Vth""s of the respective transistors, the range of the output voltage is narrowed and amplifying operation becomes impossible at the power source voltage having a value smaller than a voltage value VO at which the voltage VDD intersects with the voltage 12 and the voltage 13 intersects with the voltage VSS.
Further, although connection of the N-channel MOS transistor Tr2 to the side of the positive power source terminal VDD and connection of the P-channel MOS transistor Tr1 to the side of the negative power source terminal VSS, can be carried out in the case of a discrete element, the connections are difficult to form on the same substrate in an integrated state. Therefore, temperature compensation by thermal coupling of the constant voltage circuits VP and VN and the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 which has been possible in the case of the discrete element, becomes insufficient For example, a timing of simultaneously making OFF the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 is widened by temperature variation and there poses a problem of distortion of the output voltage.
According to the amplifier of FIG. 18, the resistors are connected between the output terminal of the OP amplifier 1 and the positive power source terminal VDD and between the output terminal of the OP amplifier 1 and the negative power source terminal VSS and accordingly, the drivability of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 is sacrificed. Further, when low impedance drive of the gates of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 is intended to carry out, load is applied on the OP amplifier 1 and when the load on the OP amplifier 1 is intended to alleviate, an RC circuit formed by gate capacitances and the resistors produce low pass filtering operation and high frequency characteristic is deteriorated. Further, in order to provide respective desired idling currents II1 and II2 by drain currents Id1 and Id2 as shown by FIG. 23, the power source voltage is also limited. Further, temperature compensation of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 is also difficult.
The amplifier of FIG. 19 poses a problem of limiting the power source voltage similar to the amplifier of FIG. 18. In addition thereto, since there are provided the constant voltage circuits constituted by transistors, temperature dependencies of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2, are added with those of the transistors constituting the constant voltage circuits and the temperature dependencies are operated in a direction of further depending on temperature.
Hence, it is an object of the invention to aim at restraining of power source voltage dependencies of idling currents of respective transistors constituting a power buffer in an amplifier, promotion of low power source voltage formation, improvement in temperature dependencies of respective transistors and promotion of low impedance formation of signals for driving respective transistors to thereby improve frequency characteristic.
According to the invention, a first P-channel MOS transistor is arranged on a positive power source side, a first N-channel MOS transistor is arranged on a negative power source side, drains thereof are connected to each other to thereby constitute a power buffer, an output terminal of the power buffer is connected with a negative phase input terminal of a first operational amplifier receiving an input signal, an output signal is generated by a second operational amplifier receiving an output signal of the first operational amplifier at a negative phase input terminal thereof, the output signal is provided to the gate of the first P-channel MOS transistor, an output signal is generated by a third operational amplifier receiving the output signal of the first operational amplifier at a negative phase input terminal thereof and the output signal is provided to the gate of the first N-channel MOS transistor. Voltage values provided to positive phase input terminals of the second and the third amplifiers, are made to correspond to voltages between the sources and the drains of a second P-channel MOS transistor having a temperature characteristic similar to that of the first P-channel MOS transistor and a second N-channel MOS transistor having a temperature characteristic similar to that of the first N-channel MOS transistor, the second and the third amplifiers generate output signals each having a voltage waveform constituting a potential center by a potential lowered from a potential of the source of the first P-channel MOS transistor by an amount of voltage between the source and the drain of the second P-channel MOS transistor and output signals each having a voltage waveform constituting a potential center by a potential higher than the potential of the source of the first N-channel MOS transistor by an amount of a voltage between the source and the drain of the second N-channel MOS transistor, thereby, the power buffer is driven and therefore, idling currents independent from the power source voltage can be provided. Accordingly, low power source voltage formation can be carried out.
Further, temperature variations of the first P-channel MOS transistor and the second N-channel MOS transistor are canceled by each other and temperature dependency of the amplifier is improved.
Further, gates of transistors constituting the power buffer can be driven equivalently at low impedance while holding high impedance in view from sources thereof and frequency characteristic is promoted.
According to an aspect of the invention, there is provided an amplifier comprising a first operational amplifier for receiving an input signal, a power buffer connecting respective drains of a first P-channel MOS transistor and a first N-channel MOS transistor and providing an output terminal at a connection point for connecting the first P-channel MOS transistor and the first N-channel MOS transistor, a second P-channel MOS transistor having a temperature characteristic the same as a temperature characteristic of the first P-channel MOS transistor, a second N-channel MOS transistor having a temperature characteristic the same as a temperature characteristic of the first N-channel MOS transistor, a second operational amplifier for receiving a voltage based on a voltage between a source and a drain of the second P-channel MOS transistor at a positive phase input terminal thereof, receiving an output signal of the first operational amplifier at a negative input terminal thereof, generating an output signal constituting a potential center of a voltage waveform by a potential lowered from a potential of a source of the first P-channel MOS transistor by an amount in correspondence with the voltage between the source and the drain of the second P-channel MOS transistor and driving the first P-channel MOS transistor by the output signal, and a third operational amplifier receiving a voltage based on a voltage between a source and a drain of the second N-channel MOS transistor at a positive input terminal thereof, receiving the output signal from the first operational amplifier at a negative phase input terminal thereof, generating an output signal constituting a potential center of a voltage waveform higher than a potential of a source of the first N-channel MOS transistor by an amount in correspondence with the voltage between the source and the drain of the second N-channel MOS transistor and driving the first N-channel MOS transistor by the output signal.
Further, according to another aspect of the invention, there is provided an amplifier comprising a first operational amplifier for receiving an input signal, a power buffer connecting a source of a first P-channel MOS transistor to a first power source terminal at a first potential, connecting a source of a first N-channel MOS transistor to a second power source terminal at a potential lower than the first potential, connecting drains of the first P-channel MOS transistor and the first N-channel MOS transistor and providing an output terminal at a connection point connecting the drains, a second P-channel MOS transistor connecting a source thereof to the first power source terminal, connecting a drain thereof to the second power source terminal via a first resistor and connecting a gate thereof and the drain, a second N-channel MOS transistor connecting a source thereof to the second power source terminal, connecting a drain thereof to the first power source terminal via a second resistor and connecting a gate thereof and the drain, a second operational amplifier receiving a voltage provided by dividing by resistors, between a terminal at a specific potential between the first potential and the second potential and the drain of the second P-channel transistor at a positive phase input terminal thereof, receiving an output signal of the first operational amplifier at a negative phase input terminal thereof and driving the first P-channel MOS transistor by the output signal, and a third operational amplifier receiving a voltage provided by dividing by resistors, between the terminal at the specific potential and the drain of the second N-channel transistor at a positive phase input terminal thereof, receiving the output signal of the first operational amplifier at a negative phase input terminal thereof and driving the first N-channel MOS transistor by the output signal.
It is preferable that a feedback resistor is provided between a negative phase input terminal of the first operational amplifier and the output terminal of the power buffer.
It is preferable that the second operational amplifier and the third operational amplifier are provided with a unity gain.
It is preferable that the specific potential is an intermediary potential between the first potential and the second potential, a voltage produced at a connection point for connecting a pair of resistors connected between the terminal at the specific potential and the drain of the second P-channel MOS transistor, is provided to the positive phase input terminal of the second amplifier and a voltage produced at a connection point for connecting a pair of resistors connected between the terminal at the specific potential and the drain of the second N-channel MOS transistor, is provided to the positive phase input terminal of the third amplifier.
It is preferable that the first P-channel MOS transistor, the second P-channel MOS transistor, the first N-channel MOS transistor and the second N-channel MOS transistor are formed on a same substrate.
USPTO Backgrounds
USPTO Backgrounds