1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a capacitor of a highly integrated semiconductor memory device, which increases cell capacitance, using a polysilicon having hemispherical grains (HSG) formed on an oxide layer.
2. Description of the Related Art
Increasing cell capacitance enhances read-out ability and decreases soft error rate of memory cells greatly contributing to the enhancement of memory characteristics in dynamic random access memories (DRAMs). Along with the increase of the packing density in the memory cell, an area occupied by an individual unit cell of a single chip is decreased, which decreases the cell capacitor area and decrease of cell capacitance. Accordingly, increased capacitance secured in an individual unit cell is an important factor in increasing packing density.
Research papers on increasing cell capacitance have been recently published, wherein a fin-structured electrode of Fujitsu Co., a box-structured electrode and a spread-stacked capacitor structure electrode of Toshiba Co., and a cylindrical structured electrode of Mitsubishi Co., etc., relate to the structure of a storage electrode constituting a cell capacitor. However, the attempt to increase the cell capacitance by improving the structure of a storage electrode faces difficulties such as restricting the design rule and increasing the error rate due to the complicated process, which thus casts doubt whether the capacitor can be actually manufactured. Accordingly, the need for a manufacturing method of a novel cell capacitor which overcomes the foregoing problem is increasingly heightened.
A method has been proposed for increasing the cell capacitance by utilizing a property of a material constituting a storage electrode without depending on structural improvement. This method will be briefly described with reference to "A Capacitor-Over-Bit Line (COB) Cell with a Hemispherical-grain Storage Node for 64 Mb DRAMs," introduced by NEC., Japan, in IEDM (Ref., M. Sakao et al., IEDM Tech. Dig, 1990, pp. 655-658).
FIG. 1 is a diagram showing a layout for manufacturing a capacitor-over bit line (COB) cell presented in the above paper. A portion denoted by a single-dashed line which transversely extends is a mask pattern P1 for active region formation. Solid-lined symmetrical portions are a mask pattern P2 for gate electrode formation. Portions denoted by long-dotted lines and has two symmetrically extending arms and centers the layout are a mask pattern P3 for forming a local wiring which connects a source region to a storage electrode. A transversely extending portion denoted by a double-dashed line having a contact mark therein is a mask pattern P4 for bit line formation. Portions denoted by short-dotted lines which are drawn as matrices is a mask pattern P5 for storage electrode formation.
A cell capacitor is formed on a bit line in the COB cell. After forming a bit line to be connected to a drain region of a transistor, an insulating material is coated on the whole surface of a substrate, so that the bit line is electrically insulated. Successively, the insulating material is partially removed to expose a region which is electrically connected to a source region of a transistor. A storage electrode is formed on the insulating material, and is connected to the source region of the transistor through the partially removed portion of the insulating material. This structure is suitable for 64 Mb and 256 Mb DRAM cells, and which is introduced for preventing contact failure of the bit line.
FIGS. 2 through 5 are sectional views illustrating a method for manufacturing a capacitor of a conventional high integrated semiconductor memory device, taken along line A-A' of FIG. 1.
In the NEC paper, a polysilicon having hemispherical grains (hereinafter referred to as HSG polysilicon) is produced thanks to a specific physical phenomenon during state transition of an amorphous silicon to a polysilicon. In more detail, when an amorphous silicon is deposited on the substrate, and then is subjected to heat, the amorphous silicon forms microscopic hemispherical grains at a specific temperature and pressure, e.g., at 550.degree. C. and 1.0 torr. Therefore, the state of the amorphous silicon changes to an intermediary polysilicon having a rugged surface due to the grains. The rugged surface doubles or triples the surface area as compared with a smooth surface.
As shown in FIG. 2, after forming an insulating layer 22 (which is two or three stacked insulating layers) on the whole surface of a semiconductor substrate 10 on which a gate electrode 18 of a transistor, a bit line (not shown) in contact with a drain region of the transistor, and a local wiring 20 in contact with a source region of the transistor are formed, a contact hole 9 is formed via anisotropically etching partially exposing local wiring 20. Successively, after forming a first polysilicon having a predetermined thickness on the insulating layer along with filling contact hole 9 completely, an etching is carried out, using mask pattern P5, so that a central storage electrode 30 is formed by being defined into an individual unit cell.
Referring to FIG. 3, as HSG polysilicon layer 32 is formed on the whole surface of semiconductor substrate 10 having central storage electrode 30 thereon, which is formed via a common depositing method, e.g., low-pressure chemical vapor deposition (LPCVD), except a specific temperature and pressure is used, e.g., 550.degree. C. and 1.0 torr. Due to the microscopic hemispherical grains, the effective area of the HSG polysilicon layer is increased to approximately twice the conventional polysilicon layer (i.e., without the HSG). At this time, since the hemispherical grains have a diameter of about 80 nm, HSG polysilicon layer 32 must be thicker than 80 nm but yet thinner than half the distance between two adjacent central storage electrodes 30.
As shown in FIG. 4, HSG polysilicon layer 32 is etched-back through a reactive ion etching (RIE), using HBr gas without requiring an additional etch-mask. This etch-back is carried out until the surface of insulating layer 22 between each central storage electrode 30 is partially exposed in order to divide the storage electrode into an individual unit cell. HSG polysilicon layer 32 coated on the upper surface of the central storage electrode is thoroughly removed during the etch-back process. Thereafter, only the rugged surface shape is left on the surface of central storage electrode 30, and the roughness of the HSG polysilicon layer 32a on the side surface of the central storage electrode is eased. The storage electrode consists of central storage electrode 30a having the rugged surface and HSG polysilicon layer 32a left after the etching process.
Referring to FIG. 5, after forming a dielectric film 34 on the whole surface of the storage electrode, a second polysilicon layer is coated on the whole surface of semiconductor substrate 10 to form a plate electrode 36 completing a cell capacitor.
The above-described method for manufacturing a capacitor of a memory cell is advantageous in that, since a physical property of the material is used for enlarging the effective area of a cell capacitor without depending on the structural improvement of a storage electrode, the cell capacitor can be manufactured by a simple process without being restricted by design rule. However, this method has a drawback in that the increased effective area of the capacitor is limited to only twice per unit area.
USPTO Backgrounds
USPTO Backgrounds