The present invention relates to a semiconductor device, and a manufacturing method thereof.
As semiconductor integrated circuits have been rapidly made minuter in recent years, the density thereof has been becoming higher. Following this phenomenon, about cutting-edge integrated circuits, their element isolation regions have been required to be made minuter while their element isolating capability is kept in order to increase the integration degree per unit area.
In response to such requirements that the element isolation regions should be made minuter, the trench isolation method has been widely used as an element isolation method instead of a conventional LOCOS (local oxidation of silicon) method. The trench isolation method is a method of embedding an insulating film into a trench made between elements, thereby attaining electric isolation between the elements. According to this element isolation technique (or element isolating technique), the integration degree is easily made high.
However, on the basis of requirements that integrated circuits should made still minuter, the width of trenches is made equivalent to the thickness of conventional gate insulating films. As a result, element isolation based on embedment with insulating films has been approaching the limit thereof. In particular, a problem about a change in electric potential of neighboring nodes is caused. This problem is described in, for example, J. Sim et al., “The Impact of Isolation Pitch Scaling on Vth Fluctuation in DRAW Cell Transistors due to Neighboring Drain/Source Electric Field Penetration”, Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 32-33 (Non-Patent Document 1).
As a method for solving such a problem, there is known field shield STI (shallow trench isolation). The field shield STI is a method of embedding, into a trench between elements, not an insulating film but a conductive film, and then fixing the electric potential of the conductive film, thereby realizing isolation between the elements. As this conductive film, there is frequently used a polycrystal silicon film doped with an impurity, which will be referred to as a “doped polysilicon film” hereinafter, from the viewpoint of the simplicity of the production process, and others.
In the meantime, according to the trench isolation method, trenches are made by etching a silicon substrate anisotropically; thus, edges of the resultant element regions are each made into a shape having an angle. An electric field from a gate electrode is concentrated into such an angular portion. For this reason, a channel portion formed into the angular portion more easily turns on than other portions of the channel. In particular, as the width of the channel is made smaller, the property of the angular portion jointed to the tip of the channel becomes more preferential. Thus, the threshold value of the transistor becomes lower as the channel width is made smaller. This phenomenon is known as the reverse narrow channel effect, and deteriorates the performance of semiconductor devices.
As elements have been made minuter, a reduction in channel width has been rapidly advancing; thus, the decline in the threshold value has been increasingly becoming a more serious problem. The reverse narrow channel effect can be decreased by a matter that the above-mentioned field shield STI method is used to change the electric potential of an embedded conductive film and control the electric potential of angular portions of element region edges.
Field shield STI as described above is described in, for example, Japanese Unexamined Patent Publication Nos. Hei 10 (1998)-22462, Hei 1 (1989)-245538, Hei 2 (1990)-174140, and Hei 1 (1989)-260840 (Patent Documents 1, 2, 3, and 4, respectively). In the techniques described in these documents, a cap insulating layer for restraining a short circuit is formed on a conductive layer embedded in trenches by thermal oxidation.
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