Non-volatile memory (NVM) generally utilizes a charge trap layer to store charge and provide non-volatility. NVM is typically fabricated on a substrate into arrays of memory cells, each cell including a charge trap memory device. Along with a memory array, high and low voltage logic devices, such as complementary metal oxide semiconductor (CMOS) transistors, as well as thin film resistors and metal-insulator-metal (MIM) capacitors may be fabricated in peripheral regions of the substrate to form an integrated circuit (IC) device.
Integration of the various active and passive devices in an IC device is increasingly challenging as the NVM and logic devices independently scale to smaller dimensions and higher densities. In addition to the greater expense associated with patterning a feature with smaller dimensions, scaling may also entail new materials, such as high-k materials (i.e., materials with a dielectric constant ∈ greater than that of silicon nitride) and metal gate layers, that may necessitate more complex process flows, multiplying the number of patterning (lithography and etch) operations to further increase costs. Methods of fabricating IC devices having a reduced number of patterning operations are therefore desirable.
USPTO Backgrounds
USPTO Backgrounds