This invention relates to a test socket for an integrated circuit chips or device and will have specific application to small outline integrated circuit devices.
Recently, small outline (SO) type integrated circuits have been gaining popularity in the electronics field. The SO package is substantially smaller in size than a standard dual-in-line package (DIP) equivalent. Its ease of circuit board assembly and smallness of size are advantages over the other types of integrated circuit devices.
Integrated circuit devices must be statistically, and sometimes each individually, tested for electrical performance properties and ability to perform under extreme heat. For the SO, because of its smallness, this creates a handling problem. Previous test sockets included hinged tops or caps to secure the SO's within the sockets and required each SO to be individually inserted into a socket by hand, often using tweezers to align the leads of the SO within the socket. After SO insertion, the hinged top of the socket must be closed. This procedure is time consuming and not always accurate due to human error. Such sockets are large and take up a great amount of space upon the printed circuit board or other power source.
In the following, a new test socket will be described which efficiently accommodates integrated circuit devices such as the SO.
USPTO Backgrounds
USPTO Backgrounds