The present technology relates to non-volatile memory.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retaining its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device. Despite the higher cost, flash memory is increasingly being used in mass storage applications. More recently, flash memory in the form of solid-state disks (SSD) is beginning to replace hard disks in portable computers as well as in fixed location installations.
In flash memory devices, a memory cell can include a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate, in a two-dimensional (2D) NAND configuration. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (Vth) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate. A memory cell can have a floating gate that is used to store two or more ranges of charges, where each range represents a data state.
Moreover, ultra-high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure which is formed from an array of alternating conductive and dielectric layers. One example is the Bit Cost Scalable (BiCS) architecture. A memory hole is drilled in the layers, and a NAND string is formed by filling the memory hole with appropriate materials. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a bottom back gate. Control gates of the memory cells are provided by the conductive layers.
High performance integrated-circuit memory devices typically have multiple die or chips controlled by a memory controller. Each die contains a memory array with peripheral circuits. At any one time, many of these multiple die may be involved in various memory operations including input or output operations with the memory controller. For example, in enterprise SSD and Client SSD the input/output (I/O) requirements are demanding. In some instances, 8 to 16 die are stacked on the same I/O channel and they are operating at 200 MHz (DDR2) speed with reduced power.
One issue has to do with I/O interface circuits for memory devices. An important characteristics for memory devices, such as flash memory devices is the ability to achieve high speed read/write operation in semiconductor storage systems. However, improving I/O interface circuit speed while meeting standby current limits is technically challenging.
USPTO Backgrounds
USPTO Backgrounds