The design of a chip, a size of which is usually between 1 mm2 and 50 mm2, is defined by its layout. During manufacturing, the chip layout is patterned onto a wafer, a size of which is usually considerably larger than the size of the chip. This enables producing several chips in parallel by using one wafer. Therefore, several chip layouts are patterned side by side onto the wafer. As a result of this, a plurality of chip areas separated by a scribe line, also referred to as a dicing line, is generated. The wafer is cut or diced in order to singulate the chips for further manufacturing. This can, for example, be done by using a saw or by using stealth dicing.
USPTO Backgrounds
USPTO Backgrounds