Circuit designers frequently wish to have a given integrated circuit design be produced at more than one integrated circuit fabrication site (“foundry”). Unfortunately, due to differences in tooling and process specializations, process technologies used at different foundries are rarely identical. Typically, each process technology has at least its own minimum design rules and electrical parameters.
In order to assist the designer in creating designs capable of being produced at a specific foundry, most foundries allow an integrated circuit designer to access a foundry-specific “process design kit,” or PDK. The PDK, coupled with various other generic design software, usually constitutes the basic environment necessary to design an integrated circuit. A fully integrated PDK includes all the necessary components to design, simulate, layout and verify a chip design. Once the design is in acceptable form, a file, typically in a binary format called “Graphic Design System II” or “GDSII” is submitted to the foundry for reticle-build processing and eventual integrated circuit production.
Unfortunately, there is little standardization among process design kits from different foundries. Each provider typically has its own way of developing, delivering and describing the kits. This lack of standardization requires that the designer “migrate” or “port” a design to a given PDK environment in order to create a design capable of being produced at the corresponding foundry. Since each PDK is different, an unfamiliar PDK presents the user with a relatively steep learning curve. Moreover, the migration process is time consuming, error prone and requires the creation of multiple copies of the original design database. Once a design is migrated to more than one process technology, multiple copies of the design will need to be maintained. Future modifications to the design then need to be made independently in each separate design environment, often leading to mistakes and inconsistencies. These added tasks and their associated risks create a significant challenge to integrated circuit designers striving to meet time-to-market opportunities.
Because of these disadvantages, methods and apparatus that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single design environment would be extremely advantageous.
USPTO Backgrounds
USPTO Backgrounds