1. Field of the Invention
The invention relates to an interface driving technique capable of supporting multiple output specifications, and more particularly, to a display control device and an output driving device, and a control method using the same.
2. Description of the Prior Art
Liquid crystal display (LCD) panels are extensively applied in flat panel display or digital TV industries by being small in size and light in weight. A current LCD display is generally divided into two parts namely a panel module and a control module. Between the panel module and the control module is an interface, which may vary from transistor-transistor level (TTL) interface and low-voltage differential signaling (LVDS) to reduced swing differential signaling (RSDS). The control module is commonly provided with a display controller integrated circuit having integrated analog-digital-converter (ADC) and scaling engine. Wherein, the ADC is for converting analog image signals received by a display control unit to corresponding digital images signals. According to images resolutions required by the LCD display, the digital image signals are then processed with either down scaling or up scaling by the scaling engine.
FIG. 1 shows a schematic block diagram illustrating an LCD display utilizing a TTL interface as a transmission interface between a panel module and a display controller. Referring to FIG. 1, 100 represents a display controller, and 110 represents a panel module. The display controller 100 is coupled to the panel module 110 via a TTL interface 120. The display controller 100 has a scaling engine 102 that processes received image data with down-scaling or up-scaling according to an image resolution required. Signals sent by the TTL interface 120 include R/G/B pixel data, pixel clock CLK, horizontal synchronization HSYNC, vertical synchronization VSYNC and a display enable signal DE. The panel module 110 has a timing controller 112, a column driver 114, a row driver 116 and an LCD panel 118. Via the TTL interface 120, the panel module 110 receives the pixel data, horizontal synchronization HSYNC, vertical synchronization VSYNC and display enable signal DE, which are all processed by the timing controller 112 into column signals 113 and row signals 115 further connected to the column driver 114 and the row driver 116, respectively. The column driver 114 and the row driver 116 then proceed with column/row display control relative to the LCD panel 118, respectively.
Ordinary pixel data are 8-bit parallel data, and are transmitted by means of dual ports. Hence, 3×8×2=48 pins are needed for transmitting the R/G/B pixel data. Suppose four signals including the pixel clock CLK, horizontal synchronization HSYNC, vertical synchronization VSYNC and display enable signal DE are added, a number of pin count required by the TTL interface 120 sums up to about 52. Referring to FIG. 2 showing a timing diagram of individual signals of the TTL interface 120 shown in FIG. 1, RA[7:0] represent 8-bit parallel red pixel data transmitted via a port A, GA[7:0] represent 8-bit parallel green pixel data transmitted via the port A, BA[7:0] represent 8-bit parallel blue pixel data transmitted via the port A, RB[7:0] represent 8-bit parallel red pixel data transmitted via a port B, GB[7:0] represent 8-bit parallel green pixel data transmitted via the port B, and BB[7:0] represent 8-bit parallel blue pixel data transmitted via the port B.
FIG. 3 shows a schematic block diagram illustrating an LCD display utilizing a TTL/TCON interface as a transmission interface between a panel module and a display controller. Referring to FIG. 3, 300 represents a display controller, and 310 represents a panel module. The display controller 300 is coupled to the panel module 310 via a TTL/TCON interface 320. The display controller 300 has a scaling engine 302 and a timing controller 304. The scaling engine 302 processes received image data with down-scaling or up-scaling according to an image resolution required. For that the display controller 300 shown in FIG. 3 is provided with the timing controller 304, TTL signals outputted by the scaling engine 302 are converted into TTL/TCON signals. Therefore, signals sent by the TTL/TCON interface 320 include R/G/B pixel data, pixel clock CLK, start pulse signal and general-purpose outputs GPO. The panel module 310 has a column driver 312, a TTL row driver 314 and an LCD panel 316. Via the TTL/TCON interface 320, the panel module 310 receives the pixel data, pixel clock CLK, start pulse signal and general-purpose outputs GPO. The signals received are divided into column signals 311 and row signals 313 further connected to the column driver 312 and the TTL row driver 314, respectively. The column driver 312 and the TTL row driver 314 then proceed with column/row display control relative to the LCD panel 316, respectively.
Ordinary pixel data are 8-bit parallel data, and are transmitted by means of dual ports. Hence, 3×8×2=48 pins are needed for transmitting the R/G/B pixel data. Suppose signals including the pixel clock CLK, odd start pulse signal, even start pulse signal and general-purpose outputs GPO (generally requiring 5 to 7 signals) are added, a number of pin count required by the TTL/TCON interface 320 sums to about 56 to 58. Referring to FIG. 4 showing a timing diagram of individual signals of the TTL/TCON interface 320 shown in FIG. 3, RA[7:0] represent 8-bit parallel red pixel data transmitted via a port A, GA[7:0] represent 8-bit parallel green pixel data transmitted via the port A, BA[7:0] represent 8-bit parallel blue pixel data transmitted via the port A, RB[7:0] represent 8-bit parallel red pixel data transmitted via a port B, GB[7:0] represent 8-bit parallel green pixel data transmitted via the port B, and BB[7:0] represent 8-bit parallel blue pixel data transmitted via the port B.
FIG. 5 shows a schematic block diagram illustrating an LCD display utilizing an LVDS interface as a transmission interface between a panel module and a display controller. Referring to FIG. 5, 500 represents a display controller, and 510 represents a panel module. The display controller 500 is coupled to the panel module 510 via an LVDS interface 520. The display controller 500 has a scaling engine 502 and an LVDS transmitter 504. The scaling engine 502 processes received image data with down-scaling or up-scaling according to an image resolution required. The LVDS transmitter 504 is for converting TTL output signals 503 coming from the scaling engine 502 into LVDS signals, which are further sent to the panel module 510 via the LVDS interface 520. The panel module 510 also has an LVDS receiver 512, a timing controller 514, a column driver 516, a row driver 518 and an LCD panel 519. Via the LVDS interface 520, the panel module 510 receives LVDS signals and converts the received signals into TTL signals 513. The TTL signals 513 are processed into column signals 515 and row signals 517 further connected to the column driver 516 and the row driver 518, respectively. The column driver 515 and the row driver 517 then proceed with column/row display control relative to the LCD panel 519, respectively.
FIG. 6 shows a timing diagram of signals of the LVDS interface 520 shown in FIG. 5 in one format. Referring to FIG. 6, the LVDS interface 520 is divided into A and B links. The link A consists of LVACKP/N, LVA0P/N, LVA1P/N, LVA2P/N and LVA3P/N signal pairs. The link B consists of LVBCKP/N, LVB0P/N, LVB1P/N, LVB2P/N and LVB3P/N signal pairs. Because the LVDS interface 520 adopts differential signals, a suffix P/N indicates that each signal is composed of two signals. The signal pair LVACKP/N represents a clock signal pair sent via the link A. The signal pair LVBCKP/N represents a clock signal pair sent via the link B. In the link A, the signal pairs LVA0P/N, LVA1P/N, LVA2P/N and LVA3P/N serially transmit pixel data, horizontal synchronization HSYNC, vertical synchronization VSYNC and display enable signal DE. Within each clock cycle, each of the LVA0P/N, LVA1P/N, LVA2P/N and LVA3P/N signal pairs needs to transmit seven bit data. For instance, LVA0P/N is for transmitting bit data including GA2, RA7, RA6, RA5, RA4, RA3 and RA2. In link B, the signal pairs LVB0P/N, LVB1P/N, LVB2P/N and LVB3P/N serially transmit pixel data, horizontal synchronization HSYNC, vertical synchronization VSYNC and display enable signal DE. Within each clock cycle, each of the LVB0P/N, LVB1P/N, LVB2P/N and LVB3P/N signal pairs needs to transmit seven bit data. For instance, LVB0P/N is for transmitting bit data including GB2, RB7, RB6, RB5, RB4, RB3 and RB2. Referring to FIG. 6, those with a “*” symbol represent dummy bits. The LVDS interface 520 uses ten differential signals for transmission, and therefore better electromagnetic interference (EMI) immunity is obtained. In addition, a pin count required is reduced to as low as 20, which is not even half of that of a TTL interface or a TTL/TCON interface.
FIG. 7 shows a timing diagram of signals of the LVDS interface 520 shown in FIG. 5 in another format. A distinction is that the signals LVACKP/N, LVA0P/N, LVA1P/N, LVA2P/N, LVA3P/N, LVBCKP/N, LVB0P/N, LVB1P/N, LVB2P/N and LVB3P/N transmit different bit data. For instance, LVA0P/N is for transmitting serial bits including GA0, RA5, RA4, RA3, RA2, RA1 and RA0; and LVB0P/N is for transmitting serial bits including GB0, RB5, RB4, RB3, RB2, RB1 and RB0.
FIG. 8 shows a schematic block diagram illustrating an LCD display utilizing an RSDS/TCON interface as a transmission interface between a panel module and a display controller. Referring to FIG. 8, a symbol 800 represents a display controller, and a symbol 810 represents a panel module. The display controller 800 is coupled to the panel module 810 via an RSDS/TCON interface 820. The display controller 800 has a scaling engine 802, a timing controller 804 and an RSDS transmitter 806. The scaling engine 802 processes received pixel data with down-scaling or up-scaling according to an image resolution required. The timing controller 804 is for converting TTL signals 803 from the scaling engine 802 to TTL/TCON signals 805. The RSDS transmitter 806 is for converting the TTL/TCON signals 805 from the scaling engine 804 to RSDS/TCON signals, which are further sent to the panel module 810 via the RSDS/TCON interface 820. The panel module 810 also has a column driver 812, an RSDS row driver 814 and an LCD panel 816. Via the RSDS/TCON interface 820, the panel module 810 receives RSDS/TCON signals, which are processed into column signals 811 and row signals 813 further connected to the column driver 812 and the row driver 814, respectively. The column driver 812 and the row driver 814 then proceed with column/row display control relative to the LCD panel 816, respectively.
FIG. 9 shows a timing diagram illustrating the signals of the RSDS/TCON interface 820 shown in FIG. 8. Referring to FIG. 9, the RSDS/TCON interface 820 similarly transmits pixel data using ports A and B. RA[3:0]P/N represent four signal channels of red pixel data transmitted in parallel by the port A, GA[3:0]P/N represent four signal channels of green pixel data transmitted in parallel by the port A, and BA[3:0]P/N represent four signal channels of blue pixel data transmitted in parallel by the port A. RB[3:0]P/N represent four signal channels of red pixel data transmitted in parallel by the port B, GB[3:0]P/N represent four signal channels of green pixel data transmitted in parallel by the port B, and BB[3:0]P/N represent four signal channels of blue pixel data transmitted in parallel by the port B. For that the RSDS/TCON interface 820 adopts differential signals, a suffix P/N indicates that each signal is composed of two signals. Moreover, RSCKAP/N and RSCKBP/N represent two clock channels by the port A and the port B, each of which also adopts differential signals. In addition, the odd start pulse signals, the even start pulse signals and the general-purpose outputs (GPO) remain as TTL/TCON signals.
The signal channels RA[3:0]P/N, GA[3:0]P/N and BA[3:0]P/N send the pixel data RA[7:0]/GA[7:0]/BA[7:0] in serial transmission, and hence within each clock cycle, each of the signal channels RA[3:0]P/N, GA[3:0]P/N and BA[3:0]P/N needs to transmit two bit data. For instance, RA0P/N is for transmitting RA0 and RA1; RA1P/N is for transmitting RA2 and RA3; RA2P/N is for transmitting RA4 and RA5; and RA3P/N is for transmitting RA6 and RA7. The signal channels RB[3:0]P/N, GB[3:0]P/N and BB[3:0]P/N also send the pixel data RB[7:0]/GB[7:0]/BB[7:0] in serial transmission, and hence within each clock cycle, each of the signal channels RB[3:0]P/N, GB[3:0]P/N and BB[3:0]P/N needs to transmit two bit data. For instance, BB0P/N is for transmitting BB0 and BB1; BB1P/N is for transmitting BB2 and BB3; BB2P/N is for transmitting BB4 and BB5; and BB3P/N is for transmitting BB6 and BB7. Because the RSDS/TCON interface 820 uses 26 differential signal channels for transmission, better EMI immunity is obtained.
It is observed from the above descriptions that, in cases of different transmission interfaces utilized by panel modules, it is essential to design corresponding display controllers. As a result, costs of circuit designs and integrated circuit manufacturing are increased.
USPTO Backgrounds
USPTO Backgrounds