1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly to a circuit configuration of a sense amplifier which amplifies storage data in a memory cell.
2. Description of the Background Art
In recent years, a nonvolatile memory device enabling nonvolatile data storage is becoming mainstream. An example thereof includes a flash memory enabling high integration. Further, special attention is being given, as nonvolatile memory devices for the new generation, to an MRAM (Magnetic Random Access Memory) device for performing nonvolatile data storage with a thin film magnetic element, and an OUM(R) (Ovonic Unified Memories) device for performing data storage with a thin film material called chalcogenide.
Data stored in a memory cell used as a storage element of these nonvolatile memory devices is generally read by applying a predetermined voltage on the storage element and detecting a passing current at the moment. The data reading requires securing reading margin by increasing the amount of passing current; however, applying too much voltage may make it impossible to perform data reading.
For example, when a high voltage is applied to a tunneling magneto-resistance element (hereinafter, also referred to as a TMR element) which is a storage element of an MRAM device, there arises a problem in that the thin insulating film forming the TMR element is broken.
When a high voltage is applied to a chalcogenide layer used as a storage element of an OUM(R) device, there arises a problem in that the element is deformed, whereby the stored data is broken.
In addition, in a flash memory which performs data storage according to the level of a threshold voltage, when the amount of passing current which flows through the flash memory is increased too much by applying a high voltage, there arises a problem in that erroneous writing is caused, whereby stored data is broken. Therefore, it is necessary to carefully control the voltage applied to the memory cell. Japanese Patent Laying-Open No. 6-309883 discloses a configuration of performing data reading in accordance with the comparison of the voltage difference between a voltage obtained from resistance division into the electric resistance of the memory cell and the predetermined fixed resistance, and a reference voltage. In other words, it discloses a configuration of performing data reading by controlling the voltage to be applied to the memory cell by means of resistance division with fixed resistance.
However, in this configuration, it is necessary to set the operating voltage of a circuit at a comparatively high level in order to secure the difference with the reference voltage, that is, to secure data reading margin. Therefore, it is difficult to secure data reading margin with a low operating voltage.
An object of the present invention is to provide a nonvolatile memory device capable of securing sufficient reading margin under a comparatively low operating voltage and performing stable data reading.
A nonvolatile memory device according to the present invention includes a plurality of memory cells through which a passing current flows according to stored data at the time of data reading, a first and second data lines, a differential amplifying unit, and a reference voltage supply unit. The differential amplifying unit performs data reading in accordance with a passing current difference between the first and second data lines. The reference voltage supply unit generates a passing current to be used to compare with a selected memory cell out of the plurality of memory cells in one of the first and second data lines at the time of the data reading. At the time of the data reading, one of the first and second data lines is electrically connected to a first voltage trough the selected memory cell, and the other of the first and second data lines is electrically connected to the reference current supply unit. The differential amplifying unit includes a first and a second current mirror circuit, and an amplifying unit. The first current mirror circuit is arranged between the one data line and a second voltage so as to maintain the voltage of the one data line at a predetermined level at the time of the data reading, and also to supply a first mirror current according to the passing current of the one data line, to a first internal node. The second current mirror circuit is arranged between the other data line and the second voltage so as to maintain the voltage of the other data line at the predetermined level at the time of the data reading, and also to supply a second mirror current according to the passing current of the other data line to a second internal node. The amplifying unit outputs read data according to the difference between the mirror currents to be supplied to the first and second internal nodes.
According to the present invention, as described above, the differential amplifying unit adjusts the voltages of the first and second data lines by the first and second current mirror circuits. The first and second current mirror circuits supply mirror currents according to the passing currents which flow through the first and second data lines to the first and second internal nodes, and the amplifying unit outputs read data according to the mirror current difference. With the configuration, adjusting the voltage to be applied to the selected memory cell which is connected to one of the first and second data lines makes it possible to perform stable data reading and also perform a data read operation based on a small amount of passing current. It is therefore possible to operate at a low voltage and to reduce power consumption of the differential amplifying unit.
Further, a nonvolatile memory device according to the present invention includes a plurality of memory cells arranged in a matrix through which a passing current flows according to stored data at the time of data reading, a plurality of bit lines provided in correspondence with memory cell columns, respectively, X (X: an integer of equal to or more than 2) data lines, a reference data line used to compare with a selected memory cell out of the plurality of memory cells at the time of data reading, a reference current supply unit, X differential amplifying units, a plurality of column selection lines provided in correspondence with the plurality of groups, respectively, and a plurality of connection control units. The reference current supply unit generates a predetermined passing current to the reference data line at the time of the data reading. The X differential amplifying units are provided in correspondence with the X data lines, respectively so as to perform data reading according to the difference between the passing currents which flow through the corresponding data lines and the reference data line. The plurality of bit lines are divided into a plurality of groups each having X bit lines at the time of the data reading. The plurality of connection control units are provided in correspondence with the plurality of groups, respectively so as to electrically couple X bit lines belonging to the corresponding group to the X data lines, in response to the activation of the corresponding column selection line at the time of the data reading. At the time of the data reading, at least one of the X bit lines is electrically connected to a first voltage through the selected memory cell. Each of the X differential amplifying units includes a current mirror circuit and an amplifying unit. The current mirror circuit is arranged between the corresponding data line and a second voltage so as to maintain the voltage of the corresponding data line at a predetermined level at the time of the data reading, and also to supply a mirror current according to the passing current of the corresponding data line to an internal node. The amplifying unit outputs read data according to the current difference between the passing current which flows through the reference data line and the mirror current to be supplied to the internal node, at the time of data reading.
According to the present invention, X data lines are provided and a plurality of bit lines are divided into groups each consisting of X bit lines. Further, X connection control circuits are provided for electrically coupling the X bit lines in each group to the X data lines at the time of data reading, and the X connection control circuits are each provided with X differential amplification units which perform data reading in accordance with the difference in passing current between each data line and the reference current at the time of data reading. It is therefore possible to realize X-bit data reading from the X bit lines in one data read operation, and to perform efficient data reading.
USPTO Backgrounds
USPTO Backgrounds