1. Field of the Invention
The present invention relates to a self arc-extinguishing thyristor in which a current flow is MOS gate-controlled.
2. Description of the Background Arts
Existing IGBTs (Insulated Gate Bipolar Transistor) are known for their excellent gate-voltage controlled turning on and off of a main current. FIG. 1 shows a basic structure of an IGBT in cross section. An n-type base layer 2 is formed on a p-type anode layer 1. In a top center portion of the n-type base layer 2, a p-type base layer 3 is selectively formed. The p-type base layer 3 consists of a relatively heavily doped p+-type center region 3a and a p-type region 3b surrounding the p+-type region 3a.
An n-type emitter layer 4a is selectively formed in a top portion of the p-type base layer 3. A top surface portion of the n-type emitter layer 4a and the top surface of the p+-type region 3a contiguous thereto serve as a cathode surface 6 in direct contact with which a cathode electrode 10 is disposed. An anode electrode 12 is disposed in contact with an anode surface 11, or the bottom surface of the p-type anode layer 1.
A gate electrode 8 which is buried in a gate oxide film 7 lies over the p-type region 3b. By controlling a gate voltage applied to the gate electrode 8, a main current is allowed and prohibited between the cathode electrode 10 and the anode electrode 12.
The current control by the gate voltage, however, does not work if a cathode-anode current develops large, thereby causing thyristor effect which latches and turns on a four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the n-type emitter layer 4a. Once this has happened, the gate-voltage control of current becomes impossible, and hence, the four-layer structure would not turn off, eventually resulting in destruction of the device.
As an improved self arc-extinguishing thyristor in which such a problem facing IGBTs is solved, an EST (Emitter Switched Thyristor) was proposed. In an EST, even if thyristor effect latched the four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the n-type emitter layer 4a, it is possible to turn off the four-layer structure by removing the gate voltage. More importantly, an EST purposely causes the latching and utilizes it in an attempt to attain extended control of a main current. An example of the EST is disclosed by B. J. Baliga in "IEEE ELECTRON DEVICE LETTERS," Volume 11, page 75.
FIG. 2 shows a cross sectional structures of an EST unit cell 100. An n-type base layer 2 is formed on a p-type anode layer 1. The n-type layer 2 has at its interface with the p-type anode layer 1 a pn junction J.sub.1. A p-type base layer 3 is selectively formed in the n-type base layer 2 so as to occupy a top center portion of the cell 100. The p-type base layer 3 consists of a relatively heavily doped p+-type center region 3a and a p-type region 3b surrounding the p+-type region 3a. A pn junction J.sub.2 is created at an interface between the n-type base layer 2 and the p-type base layer 3.
A first n-type emitter layer 4 and a second n-type emitter layer 5 are selectively formed in a top portion of the p-type base layer 3. The first n-type emitter layer 4 corresponds to the n-type emitter layer 4a of the IGBT of FIG. 1. A cathode surface 6 is formed by a portion of the top surface of the first n-type emitter layer 4 and the top surface of the p+-type region 3a contiguous to the same. The second n-type emitter layer 5 surrounds the first n-type emitter layer 4. The p-type emitter layer 3 has at its interfaces with the first n-type emitter layer 4 and the second n-type emitter layer 5 pn junctions J.sub.3 and J.sub.4, respectively.
Two channel regions are formed in the vicinity of the top surface of the p-type region 3b, one between the first n-type emitter layer 4 and the second n-type emitter layer 5, namely a first channel region CH1, and the other between the second n-type emitter layer 5 and the n-type base layer 2, namely a second channel region CH2. The channel regions CH1 and CH2 are in a faced relation with gate electrodes 8a and 8b, respectively, which are buried in a gate oxide film 7 and which are electrically connected with an external gate electrode G.
The gate oxide film 7 and the cathode surface 6 are entirely covered with a cathode electrode 10. Hence, the gate oxide film 7 insulates the cathode electrode 10 from both the gate electrodes 8a and 8b and the second n-type emitter layer 5. The p-type base layer 3 and the first n-type emitter layer 4 are electrically connected with each other via the cathode electrode 10. The cathode electrode 10 is electrically connected with an external cathode electrode K.
An anode electrode 12 is disposed entirely across the bottom surface of the p-type anode layer 1, or an anode surface 11, so that the p-type anode layer 1 and the anode electrode 12 are electrically connected with each other. The anode electrode 12 is connected with an external anode electrode A.
EST cells having a geometry as that of the unit cell 100 are arranged in parallel to each other in a matrix to thereby form an EST pellet. The gate electrodes 8a, 8b and the anode electrodes 12 of the respective unit cells 100 are electrically connected with each other.
For example, the gate electrodes 8a, 8b of each cell 100 are connected with the gate electrodes 8a, 8b of a neighboring cell 100, and the gate electrodes 8a, 8b as a whole and the external gate electrode G are connected with each other by an aluminum or other suitable wire. The anode electrodes 12 are brazed to the external anode electrode A. The cathode electrodes 10 of the respective cells are also connected with each other, and further connected with the external cathode electrode K by an aluminum or other suitable wire.
In the following, behavior of the EST device will be explained focusing on one unit cell 100. First, assume that the gate electrodes 8a, 8b are kept at the same potential as the cathode electrode 10 and the anode electrode 12 is kept at a higher potential than the cathode electrode 10. In this case, the pn junction J.sub.2 is reverse-biased, thereby allowing no current between the anode electrode 12 and the cathode electrode 10.
Next, assume that the anode electrode 12 is maintained at a higher potential than the cathode electrode 10 and the gate electrodes 8a, 8b are also maintained at a higher potential than the cathode electrode 10. In this case, charge storage occurs in the gate electrodes 8a, 8b and the channel regions CH1 and CH2 since the p-type region 3b is electrically connected with the cathode electrode 10 through the p+-type region 3a while the gate electrodes 8a, 8b and the p-type region 3b are coupled through the gate oxide film 7. Thus, channels are created in the respective channel regions CH1 and CH2.
Since a channel at the channel region CH1 short circuits the first n-type emitter layer 4 and the second n-type emitter layer 5 while a channel at the channel region CH2 short circuits the second n-type emitter layer 5 and the n-type base layer 2, current is initiated between the anode electrode 12 and the cathode electrode 10.
The current (main current) is routed from the anode electrode 12 in sequence to the p-type anode layer 1, the n-type base layer 2, the channel region CH2, the second n-type emitter layer 5, the channel region CH1, the first n-type emitter layer 4 and the cathode electrode 10. Hence, a main current exceeding a certain current value gives rise to the thyristor effect which latches and turns on the four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5. As a result, the unit cell 100 turns on.
Once the turning on has occurred, most of the main current flows from the anode electrode 12 in sequence to the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3, the second n-type emitter layer 5, the channel region CH1, the first n-type emitter layer 4 and the cathode electrode 10, leaving a little current to flow through the channel region CH2.
If the gate voltage is removed during such ON-operation, the charge stored in the channel regions CH1 and CH2 is discharged. While the discharge take places, the potential around the gate oxide film 7 exhibits an exponential-like fall, thereby extinguishing the channel short circuiting the first n-type emitter layer 4 and the second n-type emitter layer 5 and the channel short circuiting the second n-type emitter layer 5 and the n-type base layer 2. This blocks the main current in the channel region CH1 and turns off the unit cell 100 since the channel region CH2 carries a little current whereas the channel region CH1 carries most of the current in the ON-operation.
As described above, no problem will be created even if the four-layer structure (i.e., main thyristor) latches which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5. However, this is not observed where the main current has further grown and latched another four-layer structure (i.e., parasitic thyristor) which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4. If the parasitic thyristor has latched, a current does not flow through not only the channel region CH2 but also the channel region CH1, thereby making it impossible to turn off the parasitic thyristor by removing the gate voltage. Thus, the EST of FIG. 2 is likely to be destroyed as much as the IGBT of FIG. 1 is.
USPTO Backgrounds
USPTO Backgrounds