In the prior art, the process of designing an integrated circuit on a typical CAD system is done in several discrete steps using different software tools and data bases. Once specifications for the IC are in place, the circuit for the product is designed, typically using a synthesis tool, followed with verification of the design using logic simulation tools and formal verification tools to ensure the resulting logical representation of the circuit is equivalent to the schematic and the original product design specifications for both performance criteria and logic correctness criteria.
The next stage for the circuit implementation is to convert the logical and schematic representation to a physical representation that will be produced on silicon. This physical representation is the placement of the various circuit elements in the manner in which they will appear on the silicon chip; this is commonly referred to as “laying out the device”. The physical layout is specified in terms of a multiplicity of layers used to fabricate the integrated circuit. The layout is a set of geometric polygons that is imprinted on silicon during the lithographic portion of the manufacturing process. A layout contains the different layers of polygons, each layer representing a different process step to form the logic gates, interconnects, and other circuit elements as described by the final schematic. A layout may also contain cells, which are structures of polygons grouped together in the same or different layers. A cell may be replicated many times within a layout but only one instance of it is stored, with the variance of it represented by the geometric orientation. The handling of cell arrangements and the methods of manipulating and storing them is called the hierarchy handling strategy.
At the lowest level, the most basic cells contain simple geometric shapes, rectangles and polygons. In order to generate a physical mask, the hierarchical data must first be flattened, enumerating every geometric figure described in the hierarchy. Flattening the hierarchy typically results in several orders of magnitude increase in the size of data storage required to represent the pattern.
After the physical representation, the layout is generated; many software tools are used to perform analysis to ensure correct mapping between logical and physical representation (Layout Versus Schematic, LVS tool), satisfaction of performance specifications such as timing (Timing analysis tool), power (Power analysis tool), and signal integrity (Signal integrity analysis tool), checking of design rules, vendor specific geometric rules such as minimum width rules to check the minimum size of a polygon, minimum spacing rules to check minimum spacing between polygons, overlap and extension rules to check overlapping and extensions of intersection polygons, and a Design rule checker, DRC), etc. Should the analyses performed identify violations of the design or performance specifications, the circuit designer has to make changes to either the logical representation or physical representation to correct the problems and to modify the layout such that the requirements are satisfied. When a designer decides that the layout satisfies all requirements, the desired layout, at this point referred to as the tape-out, is sent to the manufacturing group for fabrication of the photo masks required for integrated circuit production.
When the manufacturer receives the “taped-out layout”, a design rule check on the layout is performed first to ensure that the layout does not violate any design rules of the particular manufacturer. It is common for different manufacturers, or foundries, to have different design rules based upon the given production tools and processes employed at that site. After the design rule check, DRC, typically for advanced semiconductor manufacturing processes which employ feature sizes of 0.18 microns or smaller, a manufacturer will apply layout enhancement functions such as optical proximity correction, phase shifting, dummy fill generations, etc., to modify the layout in an attempt to produce patterning on the silicon as close to the optimal feature size as possible. After this process, the physical data required to represent the resulting layout is again expanded and may exceed ten times the data volume of the original taped-out layout. After this initial DRC, a manufacturer will perform additional design rule checking on the modified layout to verify that all design rules, including additional rules for the enhancement features introduced, are still satisfied. This checking for rule violations may require more than one iteration, occasionally three or four. After the final check, the manufacturer will use the “final” layout to generate a set of masks ready for integrated circuit production.
In the conventional scheme for proceeding from circuit design to mask production, the designer designs his layout without considering the enhancements or modifications required by the particular manufacturer who is going to perform the IC production. Similarly, a manufacturer applies his particular layout modifications without re-verifying the circuit characteristics. As illustrated in FIGS. 2A and 2B, it is well known that any layout modifications by a manufacturer will impact the electrical characteristics of the circuit, thus affecting the performance and functionalities of the circuit. Therefore, the current design to production process is flawed or suboptimal at best. Problems may not be detected until the integrated circuit is being manufactured or worse, when it is being final tested, resulting in wasted time and money.
As described herein, many software tools are utilized to verify and enhance the layouts. These tools come from many different vendors, such as Cadence, Synopsys, Mentor Graphics, Magma, etc. The design and verification tools frequently do not share a common database to facilitate the exchange of data and information. There is also no universal data format which encompasses the representation of data in this vast array of software tools. While there are many initiatives, such as Open Access from Cadence and MilkyWay from Synopsys, to encourage the use of a common database, it is not practical to expect all legacy and future tools to converge to a single standard, since each tool performs different functions and requires its own data model. Furthermore, a system which merely integrates design rule checkers, LVS, and layout enhancement operations, such as described in U.S. Pat. No. 6,415,421, does not help designers to consider layout enhancement effects at the design stage as it lacks the interface to various physical verification tools for performance criteria such as timing, power, signal integrity, etc., and does not help manufacturers to re-verify the electric circuit characteristics after layout enhancement as it does not carry the necessary performance and design criteria into the manufacturing stage.
FIG. 1 illustrates the prior art, a conventional process executed by computer system for creating circuit representations, verifying and predicting their performance on silicon, checking design rules for manufacturability, adding various layout enhancements to facilitate the manufacturing processes, and prepare final layout data for mask making. The process begins in this example at the placement and the routing of the circuit (step 11), where a set of complex circuit representations are being assembled. For example, one such complex layout may comprise nets, cells, functional blocks, various circuit layers, such as metal, polysilicon, diffusion, contact, via, transistor gates . . . , etc. Next, the process performs various verification operations (step˜12) to attempt to predict circuit performance on silicon and to identify a set of critical paths where circuit performance requirements may be in jeopardy. The next step (step 15) in the process is to check the layout against a set of pre-determined worst-case geometric rules (design rules) provided by the manufacturers to ensure manufacturability. Once all physical verifications are passed, the layout is taped-out from the design facility to the manufacturing facility. The first step in the manufacturing data preparation process (step 16) is another design-rule check and some manufacturing-specific layout pre-conditioning process, such as separating the layers and layer biasing/sizing. The next two steps (step˜17 and 18) in the process add to the layout various resolution enhancement features (see below). The layout is then prepared and translated into mask data format (step 10) in preparation for mask making.
FIGS. 2A and 2B illustrates an example of manufacturing-specific layout enhancements applied to metal interconnections. FIG. 2A shows the appearance of a layout portion defining five adjacent metal wires, where in region 21 the wires are densely packed and in region 22 there is only one isolated wire. According to prior practices, due to various proximity effects of the silicon manufacturing process, various layout enhancements may be applied to reduce these proximity effects hence ensure manufacturability and yield. FIG. 2B shows an example of such enhancement applications, where region 23 shows “additive” optical proximity correction, region 24 shows “dummy” fill patterns used to equalize the area pattern density, and region 25 shows “subtractive” optical proximity correction. It is well understood that these enhancement features create impacts not only on the manufactured silicon patterns but also on the circuit electric characteristics. In this example, enhancement 23, 24 and 25 slows down the signal propagation speed on the center wire hence causes longer delay than what designers can predict from the original layout shown in FIG. 2A.
The major dilemma presented in this conventional flow is that manufacturing-specific layout enhancements (FIG. 1, step 17 and 18) are required to ensure manufacturability; however, they do impact circuit electric characteristics hence should be considered early in physical verification (step 12). On the other hand, no design-related information is available to be used to optimally generate these enhancements and verify their correctness. This disconnect between the design and the manufacturing entities result in less-than-optimal yield and performance in the manufactured integrated circuit, especially for integrated circuits designed for and manufactured by advanced sub-0.20 micron technology. Therefore, an improved method of layout and verification is needed to resolve these issues.
U.S. Pat. No. 6,415,421 represents a partial solution in an attempt to solve the disconnect problem. By using one program encompassing DRC, OPC and other possible layout enhancement operations utilizing a common data-structure and database, the invention attempts to enhance the integration and communication in-between various geometric verification and enhancement operations. However, the invention cannot be extended to link the circuit design and verification tools to effectively close the communication disconnect between the design and the manufacturing groups. In addition, the proposed solution is handicapped by its own requirements for a common data-structure and database. Furthermore, the (421) approach is deficient because it does not include design-for-manufacturing tools; neither does it teach the concept of optimizing across all requirements, design and process, prior to mask making.
USPTO Backgrounds
USPTO Backgrounds