1. Field of the Invention
The present invention relates to controlling reading from and writing to a semiconductor memory device. The inventions claimed herein include, but are not limited to circuit arrangements and methods. More specifically, some of the inventions claimed herein feature an improved method and circuit for controlling read and write operations in a semiconductor memory device, which can reduce power consumption by controlling data read and write operations in a dynamic random access memory (DRAM) having an open drain output buffer structure.
2. General Background and Related Art
FIG. 1 (Prior Art) is block diagram of a Rambus DRAM system that helps to explain a conventional method for controlling reading from and writing to a semiconductor memory device. The Rambus DRAM system includes a controller 11, and a plurality of Rambus DRAMs 12xcx9c12n whose read and write operations are controlled by the controller 11. The controller 11 and Rambus DRAMs 12xcx9c12n transmit/receive a data DATA, an address ADD, a control signal CON and a parity bit Parity to/from each other through channels.
FIG. 2 (Prior Art) is a circuit diagram illustrating a conventional data input/output circuit for the semiconductor memory device having an open drain structure. As shown in the drawing, a conventional data input/output circuit for Rambus DRAM has an open drain structure, and consists of an input unit 22 and an output unit 24. Each of units 22 and 24 include one buffer 211 or 221 and one NMOS transistor 212 or 222.
The NMOS transistor 212 or 222 is turned on only when a logic xe2x80x9clowxe2x80x9d data value(0) is applied thereto. However, when the NMOS transistor 212 or 222 is turned on, a current path is formed to a ground voltage Vss, which results in large consumption of power. Moreover, the conventional data input/output circuit having the open drain structure writes data as it is, regardless of a structure of a data output buffer, thereby consuming much power.
Some of the inventions claimed herein feature methods and others feature circuits for controlling reading from and writing to a semiconductor memory device. The arrangements claimed herein can reduce power consumption by controlling data read and write operations in a dynamic random access memory (DRAM) having an open drain output buffer structure.
One exemplary embodiment of the invention features a method for a single controller to control writing write data to a plurality of DRAMs, or using a single controller to read read data from the plurality of DRAMs.
Also featured is a method for controlling read and write operations in a semiconductor memory device including:
detecting potential levels of bits of the write data,
converting the write data,
writing the converted data to a plurality of DRAMs as internal data with a flag bit having a first logic level, when a number of the bits having the first logic level is greater than a number of the bits having a second logic level, and
writing the write data as it is to the plurality of DRAMs as an internal data with a flag bit having the second logic level, when the number of the bits having the first logic level is equal to or smaller than the number of the bits having the second logic level; and
distinguishing a logic level of the flag bit written on the plurality of DRAMs,
converting an internal data from the plurality of DRAMs and reading the converted data as the read data, when the flag bit has the first logic level, and
reading the internal data from the plurality of DRAMs as the read data when the flag bit has the second logic level.
In the exemplary embodiments, the first logic level is xe2x80x9clowxe2x80x9d and the second logic level is xe2x80x9chighxe2x80x9d. However, different logic levels could be utilized without departing from the spirit of the invention. Also, in the exemplary embodiments the write data is 8 bit data. Of course, other types of data structures could be used.
Some of the claimed inventions feature a circuit for controlling reading from and writing to a semiconductor memory device.
The circuit includes a write unit for comparing potential states of bits of a write data according to a control signal, converting the write data into a first logic level and writing the converted data on DRAMs with a flag bit having a first logic level, when a number of the bits having the first logic level is greater than a number of the bits having a second logic level, and writing the write data on the DRAMs as an internal data with a flag bit having the second logic level, when the number of the bits having the first logic level is equal to or smaller than the number of the bits having the second logic level. A read unit reads a read data read from the DRAMs, or converts the read data and reads the converted data according to the potential state of the flag bit. In the exemplary embodiments, the first logic level is xe2x80x9clowxe2x80x9d and the second logic level is xe2x80x9chighxe2x80x9d. However, different logic levels could be utilized without departing from the spirit of the invention.
In accordance with some of the claimed inventions, the write unit includes an input conversion unit for comparing the potential states of the bits of the write data according to the control signal, setting the flag bit to a xe2x80x9clowxe2x80x9d level and converting the write data when a number of the logic xe2x80x9clowxe2x80x9d bits is greater than a number of the logic xe2x80x9chighxe2x80x9d bits, and setting the flag bit to a xe2x80x9chighxe2x80x9d level and outputting the write data when the number of the logic xe2x80x9clowxe2x80x9d bits is equal to or smaller than the number of the logic xe2x80x9chighxe2x80x9d bits; and an input buffer unit for transmitting the data and the flag bit from the input conversion unit to the DRAMs.
In accordance with some of the claimed inventions, the input conversion unit includes: a data comparison unit for comparing the potential states of the bits of the write data according to the control signal. A signal sense unit generates different flag bit signals according to the potential state of the output signal from the data comparison unit. A data conversion unit receives and inverts the write data. A data selector unit selectively outputs the data converted through the data conversion unit or the write data according to the flag signal from the signal sense unit.
In accordance with some of the claimed inventions, the data comparison unit includes first and second source voltage supplying units for respectively supplying a first source voltage and a second source voltage according to the control signal. A plurality of inverters connected in parallel between the first and second source voltage supplying units, respectively receive signals of the bits of the write data, and output output signals to one output terminal. A data conversion preventing unit connected between the output terminal and the second source voltage supplying unit, prevents data conversion of the output terminal when the respective bits of the write data have an identical potential level.
In the exemplary embodiments, the first source voltage is a supply voltage and the second source voltage is a ground voltage. Of course, other voltage levels could be used without departing from the spirit of the invention.
In the exemplary embodiments, the first source voltage supplying unit includes a PMOS transistor and the second source voltage supplying unit includes an NMOS transistor. However, alternative configurations are possible.
In the exemplary embodiments, the plurality of inverters respectively include PMOS and NMOS transistors. However, alternative configurations are possible.
In the exemplary embodiments, the data conversion-preventing unit includes an NMOS transistor having its gate connected to receive the supply voltage. However, alternative configurations are possible.
In the exemplary embodiments, the signal sense unit includes a sense amplifier for setting the flag bit to a xe2x80x9chighxe2x80x9d level when the output signal from the data comparison unit is at a xe2x80x9clowxe2x80x9d level, and setting the flag bit to a xe2x80x9clowxe2x80x9d level when it is at a xe2x80x9chighxe2x80x9d level. However, alternative configurations are possible.
In the exemplary embodiments the data conversion unit includes inverters as many as the number of the bits of the write data. However, alternative configurations are possible. Also, in the exemplary embodiments, the data selector unit includes a multiplexer. However, alternative configurations are possible.
In exemplary embodiments, the read unit includes an output receiver unit for transmitting the internal data and the flag bit from the DRAMs. An output conversion unit outputs the data from the output receiver unit as the read data, or converts the data and outputs the converted data as the read data, according to the flag bit from the output receiver unit.
In exemplary embodiments, the output conversion unit includes a data conversion unit for converting the internal data transmitted from the DRAMs through the output receiver unit. A data selector unit selectively outputs the internal data from the DRAMs as the read data, or converts the data and outputs the converted data as the read data, according to the flag bit transmitted from the DRAMs through the output receiver unit.
In exemplary embodiments, the data conversion unit includes inverters as many as the number of the bits of the write data, the inverters being connected in parallel. However, other configurations are possible. In exemplary embodiments, the data selector unit includes a multiplexer. However, other configurations are possible.
USPTO Backgrounds
USPTO Backgrounds