1. Technical Field
This disclosure relates to logic synthesis. More specifically, this disclosure relates to look-up based fast logic synthesis.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to design circuits.
Some circuit synthesis approaches use iterative trial-and-error approach to optimize circuit designs. Specifically, the approach begins with a given circuit design (e.g., a logical or physical design). Next, a cell is identified in the circuit design for optimization based on the metrics that are desired to be optimized. An optimal size for the identified cell is then determined by iteratively replacing the identified cell with functionally equivalent cells that have different sizes (this optimization process is also referred to as “sizing the cell,” “sizing the gate,” etc.). For each replacement cell size that is tried, the circuit synthesis approach updates timing information, and rejects cell sizes for which one or more timing constraints are violated. The iterative optimization process typically terminates after the optimization process has executed for a certain number of iterations or for a certain amount of time.
Unfortunately, such iterative trial-and-error based circuit synthesis approaches either take too long to complete and/or produce poor quality results for large circuit designs in which timing constraints are checked across many process corners and modes. Therefore, what are needed are systems and techniques for circuit synthesis that do not have the above-mentioned drawbacks.
USPTO Backgrounds
USPTO Backgrounds