1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a test mode of a semiconductor apparatus.
2. Related Art
When any one failed unit cell from among numerous unit cells of a semiconductor memory apparatus is detected during a fabrication process of the semiconductor memory apparatus, the semiconductor memory apparatus is typically discarded as a defective product. However, it is inefficient to discard the semiconductor memory apparatus as a defective product even though defects occur in only some unit cells thereof. The semiconductor memory apparatus may be restored by replacing the failed unit cells with redundancy cells prepared therein, which makes it possible to improve product yield.
At a package level, a repair operation is performed using an anti-fuse. In general, the anti-fuse may be formed of a thin dielectric material such as a complex in which a dielectric such as SiO2, silicon nitride, tantalum oxide, or ONO (silicon dioxide-silicon nitride-silicon dioxide) is interposed between two conductors. The anti-fuse is electrically open in a normal state. However, when a high voltage is applied to destroy the dielectric between the conductors, the anti-fuse is shorted. That is, when a failed cell is to be replaced at the package level, a programming operation of applying a high voltage to an anti-fuse circuit is performed. After the programming operation, the anti-fuse is shorted which results in the failed cell being replaced with a redundancy cell.
FIG. 1 is a block diagram of a conventional semiconductor apparatus.
FIG. 1 illustrates such a configuration that outputs data stored in a memory cell block including main memory cells and redundancy memory cells.
The semiconductor apparatus includes a decoder 1, a memory cell block 2, a fuse block 3, and an I/O driver 4.
The decoder 1 is configured to decode a received address ADD and to generate a cell select signal X_YADD when a command CMD is inputted.
The fuse block 3 includes a plurality of fuses, and is configured to receive the cell select signal X_YADD and output fuse information FUSE according to whether or not a corresponding fuse is programmed.
The memory cell block 2 includes a main memory cell block (not illustrated) and a redundancy memory cell block (not illustrated). When deactivated fuse information FUSE is inputted, data stored in a main memory cell selected according to the cell select signal X_YADD is outputted, but when activated fuse information FUSE is inputted, data stored in a redundancy memory cell substituted for the main memory cell is outputted.
The I/O driver 4 is configured to output the data transmitted through a global line GIO to a pad PAD.
That is, the data stored in the memory cell selected according to the inputted address ADD or the redundancy memory cell is outputted to the outside through the global line GIO and the I/O driver 4.
At this time, in order to monitor whether or not fuses included in the fuse block 3 were normally programmed according to the fail cell information, the data stored in the redundancy memory cell substituted by the fuse information FUSE is outputted and checked. In this method, however, the fuse information FUSE outputted from the fuse block 3 is not directly monitored, but measured through data transmitted from the memory cell block 2. Therefore, precision may be degraded.
FIG. 2 is a block diagram of a conventional multi-chip semiconductor apparatus.
In order to highly integrate a semiconductor apparatus, various types of multi-chip packaging methods have been proposed. In particular, a chip stack method is widely used, which stacks a plurality of semiconductor chips to form one semiconductor apparatus.
In general, a multi-chip semiconductor apparatus is divided into a homogeneous structure where the same semiconductor chips are stacked and a heterogeneous structure where semiconductor chips having different functions are stacked.
A semiconductor apparatus including a plurality of stacked slave chips and a master chips is one example of a heterogeneous structure. Each of the slave chips has a core area including a memory cell block, and the master chip serves to exchange signals between the slave chips and an external processor and control signal exchanges.
Referring to FIG. 2, the semiconductor apparatus includes a master chip MASTER CHIP and a plurality of slave chips SLAVE CHIP1 to SLAVE CHIPn. The semiconductor apparatus is connected to an external processor through a pad PAD formed in the master chip MASTER CHIP. FIG. 2 illustrates a multi-chip semiconductor apparatus in which a plurality of chips are electrically connected through a through-chip via TSV, for an example.
The plurality of slave chips SLAVE CHIP1, SLAVE CHIP2 include memory cell blocks 2_1, 2_2, respectively. Each of the memory cell blocks 2_1, 2_2 includes a main memory cell and a redundancy memory cell, and data stored in the memory cells are transmitted to the master chip MASTER CHIP through a global line.
The master chip MASTER CHIP may includes the decoder 1, the fuse block 3, and the I/O driver 4. The operations of the decoder 1, the fuse block 3, and the I/O driver 4 may be performed as described with reference to FIG. 1. That is, the decoder 1 generates a cell select signal, and the fuse block 3 generates a fuse signal. The memory cell blocks 2_1, 2_2 transmit corresponding data to the I/O driver 4 through the global line in response to the cell select signal and the fuse signal. The I/O driver 4 outputs the received data outside the semiconductor apparatus through the pad PAD.
In order to monitor whether or not fuses included in the fuse block 3 provided in the master chip MASTER CHIP were normally programmed according to fail cell information, data stored in the redundancy memory cell substituted by fuse information FUSE must be outputted and checked. Therefore, all of the slave chips SLAVE CHIP1, SLAVE CHIP2 must be stacked even during a test.
USPTO Backgrounds
USPTO Backgrounds