The present invention relates to writing bits into memory cells, and more particularly, to a data line control circuit using write-assist data line coupling and an associated data line control method.
Static random access memory (SRAM) and dynamic random access memory (DRAM) are classified as volatile memories. Compared to the DRAM which requires a periodic refresh operation, the SRAM is more suitable for a high speed and low power circuit design due to the fact that SRAM cells have the advantageous feature of holding data without requiring a periodic refresh operation. For example, embedded SRAM is particularly popular in high speed communication applications, image processing applications and system on chip (SoC) applications.
One SRAM cell may be implemented using a plurality of transistors. Taking a typical six-transistor (6T) SRAM cell for example, it includes two access transistors (or called pass-gate transistors) that may be N-channel metal-oxide semiconductor (NMOS) transistors. The gates of both access transistors are coupled to a word line (WL). The drain of one access transistor is coupled to a bit line (BL), and the source of the one access transistor is coupled to gates of transistors of cross-coupled inverters. The drain terminal of the other access transistor is coupled to a complementary bit line (BLB), and the source of the other access transistor is coupled to gates of transistors of the cross-coupled inverters. In deep sub-micron technology, the lowered word line voltage level affects the write capability of the SRAM cell. That is, the turn-on voltage Von (i.e., Vgs−Vth) of the access transistor is decreased, thus degrading the write capability of the SRAM cell. More specifically, as Moore's law moves to the FinFET technology, controlling the sizing of transistors to enhance the write capability of the SRAM cell is no longer feasible. Hence, a write-assist scheme becomes a must for the SRAM design. A negative-bit-line (NBL) scheme is one of the most popular write-assist schemes. During a write operation of the SRAM cell, a negative voltage is provided to a bit line (e.g., BL or BLB) to improve the turn-on voltage Von (i.e., Vgs−Vth) of an access transistor coupled to the bit line (e.g., BL or BLB). However, the traditional NBL scheme adopts a MOS capacitor (MOSCAP) as a charge-pumping capacitor, and is neither area-efficient nor power-efficient.
Thus, there is a need for an innovative write-assist scheme which is capable of providing a negative voltage to a bit line (e.g., BL or BLB) without using MOS capacitor(s).
USPTO Backgrounds
USPTO Backgrounds