1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device and a method of fabrication and more particularly to a semiconductor device with improved flicker noise characteristics.
This U.S. non-provisional patent application claims priority under 35 U.S.C §119 of Korean Patent Application 10-2006-0045709 filed on May 22, 2006 the entire contents of which are hereby incorporated by reference.
2. Discussion of Related Art
Device sizes are becoming smaller and smaller in today's semiconductor manufacturing processes. Because of these size reductions, methods of enhancing the mobility of electrons and holes are being developed. One such method induces strain in channel regions of the semiconductor device. However, strained analog MOS transistors tend to exhibit deteriorating flicker noise characteristics. Even though straining technology may have the ability to enhance the mutual conductance and cut-off frequency characteristics of analog MOS transistors, it may not be the most effective method to enhance the mobility of electrons and holes. In particular, in the case of large-scale integrated circuits (LSI) which comprise both digital and analog MOS transistors to provide completely integrated functions, it may be inappropriate to apply straining technology to both digital MOS transistors and analog MOS transistors at the same time. Accordingly, there is a need for a semiconductor device that can achieve synergies by improving both operating and noise characteristics.
USPTO Backgrounds
USPTO Backgrounds