1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a capacitor and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for preventing a contact between a plug and a lower electrode from being oxidized and for minimizing a contact resistance therein.
2. Discussion of the Related Art
As a density of semiconductor device becomes high, there has been an effort to fabricate a capacitor to keep a desired capacitance for a memory cell. One way to increase such capacitance is to utilize high dielectric materials such as Ta.sub.2 O.sub.5, PZT(Pb(Zr Ti)O.sub.3), BST((Ba Sr))TiO.sub.3, or the like as a dielectric layer for a capacitor. Another way to increase the capacitance is to form a storage electrode having a stacked structure or a three-dimensional shape by using a trench in order to increase the surface area thereof.
FIG. 1 is a layout of capacitors according to the background art, and FIG. 2 shows a cross-sectional view of capacitors along with the line II--II' of FIG. 1. Transistors having gate electrodes and heavily-doped impurity region 120 of sources/drains in an active region defined by a field oxide layer are fabricated in a semiconductor substrate 100 where capacitors are formed according to the background art.
Further, as shown in FIGS. 1 and 2, an insulating layer 102 which has a contact hole C1 exposing the heavily-doped impurity region is formed on a semiconductor substrate 100. A plug 104-1 filling the contact hole C1 contacts the heavily-doped impurity region 120. The plug 104-1 is made of a material having an excellent step coverage such as doped polysilicon, tungsten or the like. A lower electrode 106-1 of the capacitor is formed on the insulating layer 102. The plug 104-1 is covered with the lower electrode 106-1 which electrically contacts the heavily-doped impurity region 120 through the plug 104-1. Then, a dielectric layer 108 and an upper electrode 112 are formed on the lower electrode 106-1 in this order.
In FIG. 1, the dielectric layer 108 and the upper electrode 106-1 which cover the lower electrode 106-1 are omitted for convenience. A circled portion indicated by a dotted line shows the plug 104-1 covered with by the lower electrode 106-1.
FIGS. 3A to 3C are cross-sectional views illustrating the process steps of fabricating method of capacitors according to the background art. A fabricating method of a capacitor having the aforementioned structure will be described as follows.
Initially referring to FIG. 3A, an insulating layer 102 is formed on a semiconductor substrate 100 having a transistor therein by depositing silicon oxide using chemical vapor deposition (CVD). A contact hole Cl is formed by patterning the insulating layer 102 to expose a heavily-doped impurity region 120.
A first conductive layer 104 is formed on the insulating layer 102 including the heavily-doped impurity region 120 through the contact hole C1. A thickness of the first conductive layer 104 is thick enough to completely fill up the contact hole C1. A material having an excellent step coverage, such as doped polysilicon, tungsten, or the like, may be an example for the first conductive layer 104 and formed by CVD.
Referring to FIG. 3B, a plug 104-1 electrically connected to the heavily-doped impurity region 120 is formed by etch-back the first conductive layer 104 until the top surface of the insulating layer 102 is exposed so that only a portion of the conductive layer 104 remains in the contact hole C1. A second conductive layer 106 (for example, platinum) is then formed on the insulating layer 102 including the plug 104-1. Having a low reactivity and a desirable interfacial characteristic, platinum (Pt) is widely used for forming a lower electrode of a capacitor. Subsequently, a photoresist pattern 110 defining a lower electrode of a capacitor is formed on the second conductive layer 106.
Referring to FIG. 3C, a lower electrode 106-1 is formed by removing a portion of the second conductive layer 106 using the photoresist pattern 110 as a mask. After the photoresist pattern 110 is removed, a dielectric layer 108 is deposited on the insulating layer 102 including the lower electrode 106-1. For instance, a high dielectric constant material 108, such as Ta.sub.2 O.sub.5, PZT(Pb(Zr Ti)O.sub.3), BST((Ba Sr)TiO.sub.3, or the like, may be used for the dielectric layer. When the dielectric layer having a high dielectric material is formed, Rapid Thermal Processing (RTP) is accompanied under oxygen atmosphere in order to prevent the dielectric layer from being metalized by substituting oxygen with carbon. A background art capacitor is completed by forming an upper electrode 112 on the dielectric layer 108.
However, when a thermal treatment is performed on the dielectric layer in the background art, oxygen is diffused through the lower electrode due to an excessive heat, thereby oxidizing the surface of the plug in contact with the lower electrode. Consequently, a contact resistance becomes high and the capacitor may be short-circuited with the transistor.
USPTO Backgrounds
USPTO Backgrounds