This invention relates to a semiconductor device in which a semiconductor chip (hereinafter referred to as “chip”) is electrically solder bonded to a frame serving as an external terminal, and to its surface laminated electrode structure and a method of manufacturing the semiconductor device.
Schottky barrier diodes (SBD) and Zener diodes often have a junction near the metal surface. For such semiconductor device products, there is an existing technology in which an aluminum (Al) layer is sandwiched in a laminated electrode on the surface (Japanese Laid-Open Patent Applications 2000-114302 and 63-289956 (1988)). Such existing semiconductor devices have the following problems:
1. A Schottky barrier diode having the conventional metal structure (low VF-SBD and low IR-SBD) will be described.
With respect to this diode, when Schottky metal (in general, high melting point metal such as V and Ti is used) is formed on a silicon semiconductor substrate surface, its protecting film (typically high melting point metal such as Mo, like the Schottky metal) is consecutively formed at the same time. This is carried out in order to prevent the Schottky surface from being damaged during a heat treatment step (performed for the purpose of controlling the Schottky metal to have a prescribed work function, (φB) when the process is advanced from the metal film patterning step to the heat treatment step.
Next, oxide film on the protecting film formed during the heat treatment is removed and a solder bonding metal layer (composed of: two-layer bonding material made of a Ni layer and a V or Ti layer; bonding material made of a Ni layer to be contacted with assembly solder; and antioxidant film for Ni made of a Au or Ag (silver) layer) is formed. After its patterning, a chip having finally three to five layers of surface metal is completed. The top and rear of the chip are then bonded to upper and lower frames (conductive metal on the substrate or strip) with assembly solder to complete a diode.
In this structure, typically, if there is any thin portion of assembly solder, the chip surface is directly susceptible to rapid heating during assembly of upper and lower frames, rapid heating during installation on a customer site, and/or frame stress due to temperature difference in the commercial use environment. This causes stress on the surface junction, and junction breakdown may occur due to the stress.
2. Next, the case of pn junction chip products including shallow junction chip products (Xj being 3 μm or less, e.g., constant voltage diode having low withstand voltage) will be described.
In manufacturing this product, a solder bonding metal layer (composed of: bonding material made of a V or Ti layer to be contacted with silicon; bonding material made of a Ni layer to be contacted with assembly solder; and antioxidant film for Ni made of a Au or Ag layer) is formed on a surface junction of the silicon semiconductor substrate. After its patterning, a chip having finally three layers of surface metal is completed. Subsequently, during assembly, the top and rear of the chip are bonded to upper and lower frames (conductive metal on the substrate or strip) with assembly solder to complete a diode.
In this structure again, typically, if there is any thin portion of assembly solder, the chip surface is directly susceptible to rapid heating during assembly of upper and lower frames, rapid heating during installation on a customer site, and/or frame stress due to temperature difference in the commercial use environment. This causes stress on the surface junction, and junction breakdown may occur due to the stress.
USPTO Backgrounds
USPTO Backgrounds