1. Field
The present application relates generally to the operation and design of analog front ends, and more particularly, to the operation and design of amplifiers for use in analog front ends.
2. Background
Wireless devices have become increasingly more complex resulting in more circuitry being incorporated onto smaller chips and circuit boards. For example, a conventional receiver used in a wireless device may include an amplifier coupled to a buffer stage that provides multiple gain modes.
The linearity of a typical common gate buffer stage is set by the standing current in the buffer. At the same time, the current also sets the input impedance of the buffer stage, thus some additional on-chip matching circuits may be required to present a 50-ohm input impedance at the input of the buffer stage to provide a “matchless buffer”.
Typically, when the gain of the buffer is reduced, the linearity requirements do not go down. However, if an amplifier precedes the buffer, the linearity requirements may go down as gain provided by the buffer is reduced. Thus, for lower buffer gain modes, the current in the buffer can be decreased, since linearity requirements go down. However, this decrease in current results in a change in the input impedance of the buffer and thus the impedance presented at the buffer input changes, which is undesirable.
Therefore, it would be desirable to have a common gate buffer stage for use with an amplifier in a receiver that maintains constant input impedance as the standing current in the buffer changes thereby providing additional power savings and reduced circuitry.
USPTO Backgrounds
USPTO Backgrounds