The manufacturing of IC chips is a process intensive task. Specifically, many individual process steps are performed to a wafer of semiconductor material such that multiple IC chips are simultaneously formed from the wafer. After fabrication, the individual IC chips are separated from each other, packaged, and used in electronic circuits. Improving the overall IC chip fabrication process is achieved by improving the individual processes of which it is composed. Thus, any techniques which, for example, reduce costs, reduce processing time, and/or improve quality of the individual IC chip fabrication processes are desirable.
One IC chip fabrication process is Chemical-Mechanical Polishing ("CMP"). The CMP process is used to polish the surface of a wafer during IC chip fabrication such that structures of the IC chips being fabricated are planarized. Briefly summarized, CMP comprises polishing the wafer using a polishing pad having a polishing slurry disposed thereon. The CMP process further includes several system parameters which may be used to control the polishing process, including polishing time, polishing pad composition, polishing down pressure, wafer rotation speed, and slurry composition.
As an example of an application of CMP during IC chip fabrication, an insulating layer (e.g., an oxide) may be formed over a wiring level. The insulating layer, as deposited, conformally covers the wiring level such that the upper surface of the insulating layer is non-planar. Thus, CMP may be used to planarize the upper surface of the insulating layer. Of course, it is desirable to stop the CMP process once the desired level of planarity is achieved.
The determination of when to stop a CMP process, is problematic. In particular, many parameters affect the amount of CMP processing necessary, for example, the aforementioned CMP system parameters and the density pattern of the wiring level which the polished insulating layer overlays. Thus, as various insulation layers overlaying different wiring levels of IC chips are fabricated, different amounts of CMP processing are required.
The determination of the necessary amount of CMP processing is currently performed by, for example, performing multiple CMP test trials. This is very time consuming. Specifically, the test trials necessary to determine the CMP processing time for an insulating layer overlaying a single wiring level on an IC chip may take, for example, over a half of a day. This problem is compounded by the presence of multiple levels of wiring on the IC chip such that a CMP processing time must be determined for each of the levels of wiring. Thus, as an example, conventional methods may require two and one-half days of testing to determine the CMP processing times for a new IC chip with 5 levels of wiring. This detrimentally increases the amount of time needed to bring a new IC chip to production.
Another IC chip fabrication process comprises photolithographic creation of structures on the IC chips being manufactured from the wafer. For example, silicon and/or metal structures may be created using photolithography. In specific regard to the photolithography process, although photolithographic masks may be error free in design, certain distortions nonetheless arise during actual photolithographic processing. These distortions negatively impact resultant IC chip quality.
One type of distortion that arises during photolithographic processing is caused by variations in etch rate. Specifically, IC chip areas with a high pattern density are known to etch faster than IC chip areas with a low pattern density (note: the "pattern" refers to the defining photolithographic pattern for an etched structure). Thus, for a given etch time, a disproportionately greater amount of material will be etched from high density areas than low density areas. Problems therefore arise in etched areas that require precise dimensional tolerance, such as, for example, precisely controlled transistor channel lengths. As of this date, no automatic way to correct this problem is known.
The present invention is directed towards solving all of the above noted problems.
USPTO Backgrounds
USPTO Backgrounds