This invention relates generally to charge pumps for maintaining a constant voltage bias on the substrate of an integrated circuit, and, more particularly, to a substrate pump having reduced power requirements by eliminating the crossing-current in the gates of the ring oscillator used in conjunction with the charge pump.
A typical charge pump system 10 is shown in FIG. 1, including a ring oscillator 12 for providing a square-wave oscillating signal to a charge pump 14. The charge pump 14, which is coupled between a positive supply voltage and ground, usually includes two diodes and a capacitor for converting the square-wave oscillating signal into a negative voltage, although other more sophisticated circuits exist. The negative voltage is provided at output 16 for driving the substrate of an integrated circuit in the absence of an external source of negative supply voltage. In the alternative, substrate pump 14 is sometimes configured to provide a voltage higher than the most positive supply voltage for driving isolated wells on the integrated circuit. The ring oscillator 12 includes an odd number of inverter stages 101-113 arranged in a serially-connected ring fashion. Thirteen inverter stages are shown in FIG. 1, but the exact number can be any odd number depending upon the delay through each stage and the desired oscillating frequency. The "X" output of each inverter is coupled to the "A" input of a succeeding inverter in the ring. The output of the last inverter 113 is coupled to the input of the first inverter 101 to form the oscillating output, which is in turn coupled to the input of the charge pump 14.
A typical prior art inverter stage 100 is shown in the schematic diagram of FIG. 2. Inverter stage 100 includes a P-channel transistor Q1 and an N-channel transistor Q2. The gates of transistors Q1 and Q2 are coupled together to form the A input at node 20 and the drain of transistors Q1 and Q2 are coupled together to form the inverted X output at node 22. Power for the inverter is supplied by a source of positive voltage VDD, usually five volts, at node 24. Node 24 is also the source of transistor Q1. The source of transistor Q2 is coupled to ground or a second voltage source VSS at node 26. The exact values of the power supplies VDD and VSS are determined by the level of logic swings required and the physical dimensions of the transistors, among other factors.
Another prior art inverter stage 100' is shown in the schematic diagram of FIG. 3. Inverter stage 100' again includes P-channel transistor Q1 and an N-channel transistor Q2, and in the same configuration, except for the source connections. The source of transistor Q1 is coupled through an additional P-channel load transistor Q3 to VDD, while the source of transistor Q2 is coupled through an additional N-channel load transistor to VSS. The extra transistors of inverter stage 100' enable the designer to adjust channel dimensions for minimum parasitic output capacitance at node 22. For example, the channel length of transistors Q3 and Q4 can be made quite large, minimizing power requirements and decreasing inverter gain. The channel width and length of transistors Q1 and Q2 can be made quite small to minimize parasitic drain capacitance. Transistor Q3 is biased on with bias voltage VBIAS1 at node 27, while transistor Q4 is biased on with bias voltage VBIAS2 at node 29.
Inverters 100 and 100' both exhibit undesirable "crossing-current". This term refers to the characteristic of the inverter whereby current flows directly from VDD to VSS through the transistors Q1-Q2 or Q1-Q4 during an edge transition of the input signal. Referring now to FIG. 4, a portion of the square-wave oscillating signal is shown having GND and VDD logic levels. The oscillating signal and operation of the inverters are divided into three zones. If the input signal is less than the threshold voltage V.sub.TN of transistor Q2, current is directed from VDD through output node 22 into the load and transistor Q1 is off. If the input signal is greater than VDD minus the threshold voltage V.sub.TP of transistor Q1, current is directed from the load through output node 22 to VSS and transistor Q2 is off. If the input signal is between V.sub.TN and VDD-V.sub.TP, transistors Q1 and Q2 are both on, and an undesirable crossing-current component flows from VDD to VSS. The current, which can be made small in a single inverter, is nonetheless significant if multiplied by the number of inverters required in the ring oscillator 12. The total current, multiplied by the difference in voltage between the VDD and VSS power supplies, represents a significant amount of wasted power consumption in the charge pump system 10.
Accordingly, a need remains for a charge pump system in which the power consumption due to crossing-current in the inverter stages of the ring oscillator is minimized or even eliminated.
USPTO Backgrounds
USPTO Backgrounds