1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device and, more particularly, to a semiconductor memory device in which a word line arrangement in a memory cell array is improved.
2. Description of the Related Art
In recent years, with the development of fine processing technology, 4- or 16-Mbit DRAMs can be manufactured as high-density mass products, and 1-Gbit DRAMs can be manufactured in R & D. However, in submicron generation, due to slow development of lithography technique, processing of wiring or the like is difficult. In particular, processing of a metal wiring or the like formed on an upper layer is difficult due to the underlying step difference or the like.
FIG. 1A shows the arrangement of a cell array section of a conventional DRAM. Memory cells MC1 to MC8 are selectively arranged at the nodes between word lines W1 to W4 and bit lines BL1 and /BL2 and BL2 and /BL2, respectively. Memory cell data of a word line WL selected by the row decoders R/D1 to R/D4 is read through a bit line BL, and amplified by the sense amplifiers S/A1 and S/A2.
When the word line WL is constituted by a gate wiring serving as a wiring for a transistor of a memory cell MC, since the material of the gate wiring has a relatively high resistance, an RC delay of rising/falling in selection is large. For this reason, the following method is known. That is, as shown in FIG. 1B, metal wirings consisting of A1 or the like are parallelly arranged on the gate wiring, a cell array is divided, and the contact between a metal wiring and a gate wiring is established in the middle of each cell array. This contact portion is generally called shunt, snap, or stitch. The contact between a metal wiring and a gate wiring, as shown in FIG. 1C, may be established in such a manner that the metal wiring is connected to the gate wiring through an intermediate wiring.
However, this scheme has the following problem.
As shown in FIG. 1D, the pitch of gate wirings (L1=line, S1=space) must be equal to the pitch of metal wirings (L2=line, S2=space). However, since the upper layer has an underlying step difference, and the metal itself cannot be easily processed, the metal wirings cannot be easily processed.
In recent years, a hierarchy word line scheme which has been used in an SRAM or the like has been tried to be employed in a DRAM. FIG. 2A shows a hierarchy word line scheme in a conventional DRAM. FIG. 2B is a plan block diagram a chip from above.
One main word line (MWL) constituted by metal wirings to which an output from a main row decoder (M.cndot.R/D) is supplied is arranged for sub-word line (SWL) serving as gate wirings and consisting of polysilicon or the like. One memory cell array is divided into a plurality of parts, and sub-row decoders (S.cndot.R/D) are arranged therebetween. That is, one metal wiring is arranged for four gate wirings.
Each sub-row decoder is decoded in response to a main word line signal and an address signal WDRV output from a bit line direction (not shown) to drive a gate wiring. By decoding performed by the address signal from the bit line direction, the pitch of main row decoders and the pitches of main word lines (metal wirings) for outputs of the main row decoders can be made considerably relax, i.e., four times of the pitch of gate wirings as shown in FIG. 2C. Referring to FIG. 2C, L3+S3=4 (L1+S2) is established.
However, this conventional scheme has the following problem.
In the snap scheme, the number of contacts is only decreased. In contrast to this, in the hierarchy wire line scheme, since sub-row decoder circuits are arranged to be dispersed, an area larger than that required in the snap scheme is required. For this reason, unless the number of columns between S.cndot.R/D and S.cndot.R/D is larger than the number of columns between snap and snap, the chip size increases. In contrast to this, when the number of columns between S1.cndot.R/D and S.cndot.R/D in the hierarchy word line scheme is increased, RC delay caused by the resistance of the gate wiring in the subarray increases.
As shown in FIG. 3, in order to obtain a chip size equal to that obtained in the snap scheme, the following equation must be satisfied: EQU 2.times.(number of columns/snap)=number of columns/sub-row decoder
More specifically, the number of columns between S.cndot.R/D and S.cndot.R/D of the hierarchy word lines must be twice or more the number of columns between snap and snap. The area of the snap portion is twice or more of the area of sub-row decoders. In contrast to this, the number of arrays connected to a main decoder can be set to be larger in the hierarchy word line scheme than in the snap scheme. For this reason, the number of arrays in the hierarchy word line scheme is almost twice the number of arrays in the snap scheme, and the area in the hierarchy word line scheme is almost equal to the area in the snap scheme. At this time, a gate wiring delay RC is determined by the value related to twice the number of columns. For this reason, the following equation is established: EQU (2R).times.(2C)=4RC
and the delay increases to be four times. As a result, in order to keep a constant speed, development for making the resistance of a gate wiring lower than that in the snap scheme must be performed, and the cost of development is required.
The conventional hierarchy word line scheme also has the following problem. Although the rule of a metal wiring on a subarray can be relaxed as shown in FIG. 3, the pitches of the main row decoders and the pitch of the metal wirings of the sub-row decoders cannot be relaxed. As a result, the design rule of the metal wirings is limited to the rules of the main row decoders and sub-row decoders.
In the conventional snap scheme shown in FIGS. 1A to 1D, the rules of row decoders is relaxed compared with the rule on the cell array. However, in the hierarchy word line scheme shown in FIGS. 2A to 2C, since the rules on the subarray is considerably relaxed, the metal wirings are limited to the rules of the main row decoders and sub-row decoders.
For example, referring to FIG. 4, when a contact to the well of a main row decoder is to be formed, a second layer metal wiring (not shown) extending in a bit line direction is brought into contact with a first layer metal wiring (metal 1) to be brought into contact with the well. For this reason, as indicated by (A) in FIG. 4, the pitch of the first layer metal wirings reduces by half. The rule of the contact between the first layer metal wiring and the second layer metal wiring is large, the rule of the first layer metal in the portion (A) is smaller than a half of the rule of the subarray. As in a portion (B) in another word line power supply (VSV), or as in a portion (C), when a signal (S1) from another wiring, e.g., a lower circuit, in the main row decoder is connected to a main word line in parallel, the rule becomes more severe. In addition, as in a sub-row decoder section, a portion such as the portion (A) is present. When a sub-word line is formed by the first layer metal wiring as indicated by (D), the rule becomes more severe.
As described above, with respect to a conventional word line arrangement in a memory cell array, in the snap scheme, processing cannot be easily performed because a metal wiring pitch is severe. In the hierarchy word line scheme, although a pitch is relax, a delay increases unless the resistance of a gate wiring is reduced, and a chip size increases.
In the conventional hierarchy word line scheme, the pitch of the metal wirings on a subarray can be considerably relaxed, but the rules of the metal wirings of the main row decoders and sub-row decoders are constant. As a result, the rule of the metal wirings is limited to the rules of the metal wirings of the main row decoders and sub-row decoders.
USPTO Backgrounds
USPTO Backgrounds