Digital integrated circuits often include a number of storage elements such as latches and flip-flops that temporarily store logical states (e.g., HIGH or LOW) within the integrated circuit. In normal operation, data from a component of the integrated circuit is received by the storage elements and then outputted to the same and/or another component of the integrated circuit. Sometimes, it is useful to selectively set the data stored in the storage elements in order to operate the integrated circuit from a known logical state.
Similarly, it is also useful to shift an entire sequence of bits into the storage elements to test the integrated circuit. In the latter case, two or more storage elements are xe2x80x9cdaisy-chainedxe2x80x9d together so the output of one feeds the input of the next, and so on. To begin the xe2x80x9cshiftxe2x80x9d, one of the storage elements in the chain is tapped, that is, selected as the point at which to shift in the controlled test bits. Similarly, a sequence of bits can be shifted out from the integrated circuit and compared with an expected output. This technique of shifting data bits in is also referred to as xe2x80x9cscanningxe2x80x9d while the technique of shifting data bits out is called xe2x80x9ccapturexe2x80x9d. The chain of storage elements is referred to as a xe2x80x9cscan chain.xe2x80x9d A common software tool called an automatic test pattern generator (xe2x80x9cATPGxe2x80x9d) is used to generate the test patterns used to test the integrated circuit.
One common type of storage element is a Muxscan storage element 10, depicted in FIG. 1A as a multiplexer MUX connected to a flip-flop FF. The multiplexer MUX has two inputs 0 and 1 which are selectable via a select input SEL, and an output O. The 0 and 1 inputs are typically connected to a data signal DATA and a scan-in signal SI, respectively, and the select input SEL is typically connected to a scan-enable signal SE. The DATA signal carries logic states from a predefined component of the integrated circuit during normal operation.
The scan-in signal SI provides logic states from a tester for purposes of testing the integrated circuit. When the scan-enable signal SE is at logic LOW, the multiplexer MUX selects the DATA signal as the output. When the scan-enable signal SE is at logic HIGH, the multiplexer MUX selects the SI signal as the output. The output O is connected to an input D of the flip-flop FF, which also has a data output Q. In operation, upon assertion of a clock signal CLK, the flip-flop FF latches whatever data are at its input D (from either the DATA or SI signal) and outputs this data at the output Q.
FIG. 1B shows a simplified version of the Muxscan storage element 10 of FIG. 1A. The multiplexer MUX and the flip-flop FF of FIG. 1A have been combined into a single device that is functionally identical to the device shown in FIG. 1A.
Another type of storage element is the Level-Sensitive Scan Design, or LSSD. Generally, LSSD storage elements have an advantage over non-LSSD storage elements in that their operation does not depend on the exact timing of a clock signal. Instead, operation of an LSSD storage element depends solely on whether the clock signal has occurred (i.e., whether it has attained a certain, predefined voltage level, and not on when the clock signal has occurred). This insensitivity to exact timing avoids timing related problems such as clock skew and rise or fall times dependencies. However, LSSD storage elements have more stringent design requirements. For example, each latch in an LSSD storage element must have its own clock signal, and the clock signals may not overlap.
A popular type of LSSD storage element called an xe2x80x9cL2-Starxe2x80x9d is functionally depicted in FIG. 2. This storage element 20 has a master latch L1 and a slave latch L2 connected together. Both latches L1 and L2 have a set of inputs D1 and D2 which are latched by clock inputs CLK1 and CLK2, respectively. An output Q outputs the data from either the D1 or D2 input (whichever is latched last) on both latches L1 and L2. The master latch L1 outputs a master output signal QM and the slave latch L2 outputs a slave output signal QS. The input D1 of the master latch L1 is connected to a data signal DM carrying logic states from a predefined component of the integrated circuit, while the corresponding input D1 of the slave latch L2 is connected to another data signal DS. A write clock signal WCLK global to the integrated circuit is connected to the clock inputs CLK1 of both latches L1 and L2 for latching the data from the DM and DS signals. The input D2 of the master latch L1 is connected to a scan-in signal SI carrying logic states from, for example, a tester, for purposes of testing the integrated circuit. The corresponding input D2 of the slave latch L2 is connected to the master output signal QM from the master latch L1. A master scan clock ACLK latches the data from the scan-in signal SI and a slave scan clock BCLK latches the data from the QM signal.
Operation of the LSSD storage element 20 will now be described with reference to the timing diagram of FIG. 3. During normal operation, the master latch L1 and the slave latch L2 both function as independent storage elements. Upon assertion of the write clock WCLK, data carried by the signals DM and DS are latched by the two latches L1 and L2 and outputted as the output signals QM and QS, respectively. Note that the two scan clocks ACLK and BCLK are inactive at this time, and the scan-in signal SI is in a xe2x80x9cdon""t carexe2x80x9d state.
During testing, or scan operation, the master latch L1 and the slave latch L2 operate together to form a 2-position shift register. Upon assertion of the master scan clock ACLK, the data from the scan-in signal SI is latched by the master latch L1 and outputted as the master output signal QM. This same data will then be latched by the slave latch L2 upon assertion of the slave scan clock BCLK and outputted as the slave output signal QS. Note, for proper operation of the scan function, the two scan clocks ACLK and BCLK must not overlap each other. Also, note that at the end of the scan operation, these outputted signal bits stored in the latches are always equal (i.e., QM=QS).
As can be seen from the timing diagram, the L2-Star configuration uses both latches L1 and L2 as independent storage elements during normal operation. However, during scan operation, the master latch L1 feeds the slave latch L2 and the latches are no longer independent. As such, in a scan chain made of multiple L2-Star storage elements, asserting the master scan clock ACLK first at the start of the scan operation destroys the initial data bit going into the input D2 of the slave latch L2. Likewise, asserting the slave scan clock BCLK first destroys the initial data bit going into input D2 of the following master latch L1. By way of example, say the scan-in signal SI is HIGH at the start of the scan operation while the master output signal QM is LOW. Upon assertion of the master scan clock ACLK, the HIGH from the scan-in signal SI is latched by the master latch L1 and the master output signal QM becomes HIGH, thus displacing the previous LOW before it can be latched by the slave latch L2. A similar displacement occurs at the next master latch in the scan chain if the slave scan clock BCLK is asserted first. Therefore, each scan operation would have to be executed twice, once with the master scan clock ACLK asserted first, and once with the slave scan clock BCLK asserted first, in order to capture all the data.
In one embodiment, the invention relates to an apparatus for circuit modeling for use with an automatic test pattern generator of a level sensitive scan design storage element and a non-level sensitive scan design storage element comprising: a master element that receives a master input signal; a slave element that generates a slave output signal; and a master observe control module that alternatively selects the master input signal from the master element and the slave output signal from the slave element.
In another embodiment, the invention relates to an apparatus for circuit modeling for use with an automatic test pattern generator of a level sensitive scan design storage element and a non-level sensitive scan design storage element comprising: means for modeling a level sensitive scan design storage element; means for modeling a non-level sensitive scan design storage element; and means for modeling the interface between the level sensitive scan design storage element and the non-level sensitive scan design storage element.
In another embodiment, the invention relates to a method of modeling a level sensitive scan design storage element and a non-level sensitive scan design storage element for testing with an automatic test pattern generator comprising: generating a slave output signal from a slave element; generating a master input signal for a master element; and alternatively selecting the slave output signal and the master input signal with a master observe control module.
The advantages of the disclosed invention include an efficient test generation that avoids multiple passes of the scan operation for a LSSD storage element and a non-LSSD storage element.
USPTO Backgrounds
USPTO Backgrounds