1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor integrated circuit devices using plasma. More particularly, the present invention relates to a method of forming a PE-TEOS layer on a semiconductor wafer.
2. Description of the Related Art
In the fabrication of semiconductor integrated circuit devices, PE-TEOS (plasma enhanced tetra-ethyl ortho silicate) is widely used for inter-metal dielectric (IMD) layers because the PE-TEOS layer has good step coverage and a high dielectric characteristic. In general, TEOS is a silicon oxide grown by pyrolyzing liquid Si(OC2H5)4 under a vacuum. A PE-TEOS layer is a layer of silicon oxide deposited on a wafer by exciting TEOS gas using a radio frequency (RF) power while the gas is at a given temperature and under a given pressure, whereby plasma is formed. This process is thus known as a chemical vapor deposition (CVD) process or, more specifically, a plasma-enhanced chemical vapor deposition (PECVD) process.
A chemical vapor deposition (CVD) apparatus capable of batch processing is typically used to attain high yields for the PE-TEOS process. For example, the Sequel model of Novellus Systems, Inc. allows for six wafers to be processed at a time in a chamber. FIG. 1 schematically shows in plan such a conventional CVD apparatus for use in forming a PE-TEOS layer.
Referring to FIG. 1, the CVD apparatus 10 has a chamber 12 in which the PE-TEOS deposition process is performed. The CVD apparatus 10 further has a heater table 14, which is also referred to as a heater block, and several showerheads 16. The heater table 14 heats the inside of the chamber 12 and thus, the wafers 24 supported in the chamber 12. The showerheads 16 spray process gases, such as TEOS gas, onto the wafers 24 mounted on the heater table 14. In addition, the chamber 12 is equipped with two wafer cassettes 20 and 30. A loading wafer cassette 20 contains the wafers 24 to be supplied into the chamber 12. An unloading wafer cassette 30 receives wafers 26 discharged from the chamber 12 after the PE-TEOS deposition process.
The heater table 14 has a spindle 18 at its center and six wafer stages 17 disposed around the spindle 18. Each wafer stage 17 supports a wafer 24 supplied from the loading wafer cassette 20. The spindle 18 rotates so that the wafers 24 can be loaded from the loading cassette onto the respective wafer stages 17 and unloaded from the wafer stages 17. More specifically, the spindle 18 has a spindle body 13 capable of moving up-and-down and rotating, and pairs of transfer bars 15 connected to the spindle body 13. The transfer bars 15 extend to the wafer stages 17 and can be inserted into grooves formed on the wafer stages 17.
The wafer stages 17 include a first stage 17a located near the loading wafer cassette 20. The second through sixth stages 17b-17f are spaced from the first wafer stage 17a and from one another in the circumferential direction of the spindle body 13, i.e., are spaced from the first stage 17a in the clockwise direction in the figure. The sixth stage 17f is located near the unloading wafer cassette 30. The spindle 18 transfers each wafer 24 from one wafer stage to the next wafer stage in the clockwise direction. For example, in order to transfer the wafer 24 from the first stage 17a to the second stage 17b, the spindle body 13 moves upward so that the transfer bars 15 supporting the wafer 24 are raised above the top surface of the first stage 17a. Then the spindle body 13 rotates to move the transfer bars 15 supporting the wafer over the second stage 17b, whereupon the spindle body 13 moves downward. Therefore, the transfer bars 15 are inserted into the grooves in the second stage 17b, whereby the wafer 24 is mounted on the second stage 17b. 
FIG. 2 illustrates a flow 40 of a conventional method for forming the PE-TEOS layer by using the CVD apparatus described above. Referring to FIGS. 1 and 2, the conventional PE-TEOS method begins with a preparation step 41 in which the loading wafer cassette 20 provides the wafers 24 to be subjected to the PE-TEOS deposition process. Next, and before the actual deposition occurs, a process atmosphere is created in the chamber 12 (pre-creating step 42). The atmosphere is the same as the one in which the actual deposition will take place. Such a pre-creating step 42 is also referred as to a pre-coating step.
In a next step 43, the wafers 24 are supplied in sequence into the chamber 12 from the loading wafer cassette 20. The PE-TEOS layer is deposited to a target thickness (PE-TEOS deposition step 44) while the wafers 24 in the chamber 12 are sequentially transferred by the spindle 18 from the first wafer stage 17a to the sixth wafer stage 17f. 
In a next step 45, the wafer 26 on which the PE-TEOS layer has been formed to a target thickness is unloaded from the sixth stage 17f of the chamber 12 to the unloading wafer cassette 30. The PE-TEOS deposition (step 44) and the wafer unloading (step 45) are carried out continuously without interruption until an RF cleaning process (step 47) starts. More specifically, the PE-TEOS layer is deposited during the PE-TEOS deposition step 44 not only on the wafer(s) 24 but also on exposed portions of the inside of the chamber 12, namely, on inner walls of the chamber 12 and surfaces of the heater table 14. Therefore, the thickness of the PE-TEOS layer deposited on the exposed portions of the chamber 12 should be periodically checked and, if the thickness thereof exceeds a specific thickness, the inside of the chamber 12 should be cleaned. However, whether the cleaning process (step 47) can begin depends on the target thickness of the PE-TEOS layer. For example, if the target thickness is approximately 17000 Å, the RF cleaning step 47 can only be initiated once a PE-TEOS layer having the target thickness of approximately 17000 Å is formed on all twenty-five wafers 24 in the loading wafer cassette 20.
The RF cleaning step 47 is initiated after the PE-TEOS deposition step 44 once all of the wafers 26 are unloaded from the chamber 12. Then, oxygen gas and C2F6 gas are supplied together into the chamber 12 while excited by the RF power under a pressure of about 3 Torr and a temperature of about 390° C. The RF cleaning removes foreign particles as well as the PE-TEOS layer deposited on the exposed portions of the chamber 12. After the RF cleaning step 47, the CVD apparatus prepares for next PE-TEOS batch deposition process, i.e., the method returns to preparation step 41.
Unfortunately, the above-described conventional process for forming the PE-TEOS layer has drawbacks. As shown in FIG. 3, the thickness of the PE-TEOS layers deposited on the wafers decreases gradually and then becomes almost uniform after the RF cleaning process has been performed. For example, when the PE-TEOS layer has a target thickness of about 17000 Å, the thickness of the PE-TEOS layers formed on the first twelve wafers becomes smaller and smaller, and thereafter the thickness of the PE-TEOS layers formed on the following wafers is substantially uniform.
The thickness of the PTEOS layer becomes smaller in the first several wafers that are processed after the RF cleaning step because the shower heads and the inside of the chamber are heated during the cleaning step by the heater table 14 on which no wafers are mounted. Accordingly, the temperature of the shower heads and the inside of the chamber rises above the deposition process temperature, and this rise in temperature affects the deposition thickness of the PE-TEOS layer.
Under this condition, the PE-TEOS layers are formed on the wafers initially supplied into the chamber 12 to a thickness that is greater than the target thickness. On the other hand, as more and more wafers are supplied into the chamber 12, the heat produced by the heater table 12 is absorbed by the wafers. In addition, the TEOS gas sprayed through the showerheads reduces the temperature of the showerheads and the inside of the chamber. Therefore, the internal temperature of the chamber is eventually stabilized at about the desired process temperature whereupon the thickness of the PE-TEOS layers formed on the wafers becomes uniform.
When the PE-TEOS layers have different thicknesses for the reasons explained above, it is difficult to establish a suitable depth to which the PE-TEOS layers should be polished in a subsequent process. Furthermore, different thicknesses of the PE-TEOS layers cause serious differences to occur among the critical dimension of respective patterns subsequently formed on the wafers. It would therefore be desirable to prevent the temperature of the showerheads and the inside of the chamber from being excessively heated by the empty heater table. However, it is difficult to control the temperature of the heater table, and thereby control the temperature of the showerheads and the inside of the chamber.
USPTO Backgrounds
USPTO Backgrounds