1. Field of the Invention
The present invention relates to techniques for detecting a position of a mark from a mark signal obtained by capturing an image of the mark. The present invention is applicable, for example, to an exposure apparatus used in fabrication processing of a device, such as a semiconductor device.
2. Description of the Related Art
In recent years, projection exposure apparatuses used in fabrication processing of semiconductor devices have been miniaturized and have been made in high density, and therefore, are required to perform projection exposure of a circuit pattern arranged on a reticle surface onto a surface of a wafer with comparatively high resolution. Projection resolution of the circuit pattern depends on a numerical aperture (NA) and an exposure wavelength of a projection optical system. Accordingly, a method for increasing the NA and a method for making the exposure wavelength shorter have been employed to realize high projection resolution. As for the latter method, a g-line light source is replaced by an i-line light source, and further the i-line light source is replaced by an excimer laser. Furthermore, exposure apparatuses using excimer lasers having wavelengths of 248 nm and 193 nm have been put into practical use. Moreover, an EUV (extreme ultraviolet lithography) exposure method using a wavelength of 13 nm has been proposed as a next-generation exposure method.
Various fabrication processes of semiconductor devices have been proposed, and among the various fabrication processes, CMP (chemical mechanical polishing) processing has been attracting considerable attention as a planarization technique for solving a problem of the lack of a focal depth of an exposure apparatus. Furthermore, various configurations and materials of semiconductor devices have been proposed. For example, a P-HEMT (pseudomorphic high electron mobility transistor), an M-HEMT (metamorphic-HEMT) using a combination of chemical compounds such as GaAs and InP, and an HBT (heterojunction bipolar transistor) using SiGe or SiGeC have been proposed.
As described above, since the circuit pattern has been miniaturized, the reticle surface on which the circuit pattern is arranged and the wafer onto which the circuit pattern is projected are required to be aligned with each other with high accuracy. Required accuracy is considered to be one third of a circuit line width. Therefore, for example, in a case where a circuit line width of 90 nm is designed, the required accuracy is considered to be 30 nm, which is one third of 90 nm.
Japanese Patent No. 03347490 discloses an example of a wafer alignment method for the exposure apparatus. In this method, an alignment mark position is detected by template matching using a mark signal obtained by projecting an alignment mark captured using an area sensor, such as a CCD camera, in a longitudinal axis direction and using a mark signal obtained using a line sensor. In the template matching, calculations of the correlations between the mark signal captured using the line sensor and a template stored in a processing apparatus in advance are performed, and the highest correlation position is detected as an alignment mark center. The template matching is represented by the following expression.
                    Expression        ⁢                                  ⁢                  (          1          )                                                                              E          ⁡                      (            x            )                          =                              ∑                          i              =                              -                k                                      k                    ⁢                                    S              ⁡                              (                                  x                  +                  i                                )                                      ⁢                          T              ⁡                              (                i                )                                                                        (        1        )            Here, S denotes the mark signal obtained using the line sensor, T denotes the template, E denotes a result of the correlation calculation processing, x denotes an alignment mark position, and i denotes an alignment mark position in a window set in the correlation calculation processing.
In wafer alignment, a measuring error called a WIS (wafer induced shift) is caused due to processing. Examples of the WIS include asymmetry of a configuration of an alignment mark and asymmetry of a resist form to be applied to a wafer, which are caused by planarization processing such as CMP processing. Such asymmetry of a configuration of an alignment mark and uneven coating of resist cause asymmetry of a mark signal to be obtained using a sensor. The asymmetry of a mark signal further causes generation of a measuring error in wafer alignment employing template matching resulting in deterioration of capability of a semiconductor device and decreasing of fabrication yield of the semiconductor device.
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