1. Field of the Invention
This invention relates to analog-to-digital converters. More specifically, this invention relates to analog-to-digital converters employing sigma-delta modulation.
While the present invention is described herein with reference to a particular embodiment, it is understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional embodiments within the scope thereof.
2. Description of the Related Art
Recent developments in the field of digital signal processing, particularly within the areas of radar, digital radio, digital television, have accentuated the demand for fast accurate analog-to-digital (A/D) converters. Accuracy may gauged by measuring the signal-to-noise ratio of the output generated by the converter, with the result often being expressed in a particular bit resolution. Conventionally, either the successive approximation or dual-ramp conversion technique is used for high (i.e. 16-bit or greater) resolution A/D converters. One difficulty with the successive approximation approach is that trimming a weighting network associated therewith is necessary to achieve a conversion accuracy in excess of 15 bits. The requirement of trimming inhibits production efficiency and increases unit costs. High resolution is effected through the dual-ramp technique by utilizing, for example, precision high-speed integrator and sample-and-hold circuits. These circuits are generally realized only in certain specialized bipolar process technologies and then only with some difficulty.
Accordingly, A/D conversion techniques based on "oversampling" have been viewed favorably since this methodology obviates the need for trimming and for certain precision circuits. A/D converters utilizing oversampling operate at a clock rate much higher than the data rate of the sampled analog signal to be processed. The oversampling ratio of an A/D converter refers to the ratio of the clock rate of the A/D converter to the Nyquist sampling rate associated with the incident analog signal. As is well known, the value of the Nyquist rate is dependent upon the maximum frequency of interest included within the incident analog signal.
One class of oversampling A/D converters is based on a processing scheme known as sigma-delta modulation. Conventional sigma-delta modulators employ an internal 1-bit quantizer and output a bit stream whose pulse density is proportional to the amplitude of the applied input signal. Single bit internal quantizers are utilized, despite an inherent lack of resolution, in part because theoretically distortion-free quantization may be effected. Although both accuracy and stability of a sigma-delta converter may be enhanced through multi-bit internal quantization, multi-bit quantization also requires utilization of a multi-bit internal digital to analog converter (DAC). The internal DAC must be linear to the full accuracy of the overall sigma-delta converter so as to prevent nonlinearities in the DAC from negating any accuracy improvements achieved through multi-bit quantization. For high resolution A/D converters the requisite linearity in the DAC is typically achieved only by using ancillary (off-chip) compensation elements and/or by component trimming.
In a further effort to effectuate high resolution, conventional sigma-delta A/D converters have been operative at a sampling rate which gives rise to a high oversampling ratio. Unfortunately, a high oversampling ratio limits the analog signal bandwidth which may be accurately processed by a single converter. As a consequence, conventional sigma-delta A/D converters have been constrained to applications involving, for example, compact disks or audio systems. Moreover, the oversampling ratio is inversely proportional to the speed at which an analog signal may be converted to the digital domain. It follows that the high oversampling ratios of conventional sigma-delta A/D converters may preclude their inclusion in certain high speed processing applications. For example, it generally requires a cascade of three first order sigma-delta modulators employing 1-bit quantization and oversampling ratios in excess of 64 to achieve 15 to 16 bit resolution.
Matsuya, et. al. disclose an analog-to-digital converter having multiple cascaded sigma-delta stages of 1-bit internal quantization in "A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping", IEEE Journal of Solid-State Circuits, vol. SC-22, no. 6, p. 921, December 1987. The cascaded converter disclosed therein effected improvements in resolution by implementing a network disposed to cancel the quantization noise engendered by the first n-1 stages of an n-stage cascaded converter. Despite the advantages afforded by the noise cancellation network, the ultimate resolution of the Matsuya converter for a given oversampling ratio is limited due to the utilization of internal single bit quantization. In addition, each stage within the Matsuya converter is disposed to deliver a quantization error signal to the stage immediately subsequent thereto. Unfortunately, the small magnitude of the error signal relative to the dynamic range of each sigma-delta stage makes the degree of noise cancellation more sensitive to component variation. Further, since the relative magnitude of the error signal becomes smaller with each successive stage, extension of the Matsuya converter to multiple stages yields diminishing improvements in overall A/D conversion accuracy.
Hence, a need in the art exists for a precision sigma-delta A/D converter disposed to be extended to a desired number of cascaded stages, with each stage being operative at a sampling rate giving rise to a relatively low oversampling ratio.
USPTO Backgrounds
USPTO Backgrounds