1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (hereinafter designated “PDP”) which employs a matrix display scheme.
2. Description of Related Art
As a type of PDP employing such a matrix display scheme, known is an AC (alternating current discharge) type PDP.
The AC type PDP comprises a plurality of column electrodes (address electrodes) and a plurality of row electrodes that are orthogonal to the column electrodes, and a pair of row electrodes form a scan line. Each of these row and column electrodes is coated with a dielectric layer exposed to a discharge space, and the intersection of a row electrode and a column electrode defines a discharge cell corresponding to one pixel.
With this construction, PDP operates by discharge phenomenon and thus the aforementioned discharge cell has only two states, that is, a “light-emitting” state and a “non-light-emitting” state. Accordingly, in order to implement a brightness display of a halftone with such PDP, a sub-field method is employed. According to the sub-field method, the display period of one field is divided into N sub-fields. Then, each of the sub-fields is assigned with a light emitting period (the number of light emissions) having a length of time corresponding to the weight assigned to each bit digit of pixel data (N bits) for light-emission.
For example, as shown in FIG. 1, in the case where one field period is divided into 6 sub-fields, SF1 to SF6, light is emitted by the following ratio of light emission periods. That is,    SF1: 1    SF2: 2    SF3: 4    SF4: 8    SF5: 16    SF6: 32
As shown in FIG. 1, when the discharge cell is to emit light at brightness “32”, only SF6 of sub-fields SF1 to SF6 is allowed for emitting light. On the other hand, for light emission at brightness “31”, sub-fields SF1 to SF5, except for sub-field SF6, are caused to emit light. This enables an expression of brightness with 64 levels of halftone.
As is evident from the sequence in FIG. 1, the number of sub-fields may be increased to increase the number of levels of halftone.
However, a pixel data writing step is required for selecting light-emitting cells within one sub-field. Thus, an increase in the number of sub-fields would lead to an increase in the number of repetitions of the pixel data writing step that should be performed in one field. This causes the time assigned to the light-emission period (the length of time of the light-emission sustaining step) in one field period to become relatively short, thereby causing a decrease in brightness.
Therefore, it is necessary to perform multi-level gray scale processing in a specified manner for a video signal itself in order to implement a video display such as a television video image display by means of PDP. For example, as a scheme for multi-level gray scale processing, error diffusion processing is well known. The error diffusion processing is a method that adds an error between the pixel data corresponding to a pixel (a discharge cell) and a predetermined threshold value to the pixel data corresponding to a peripheral pixel in order to increase the number of levels of halftone in an apparent manner.
However, the fewer the number of levels of halftone, the greater the patterns of error diffusion become conspicuous, thereby presenting a problem in reducing the S/N ratio.
USPTO Backgrounds
USPTO Backgrounds