1. Field of the Invention
This invention relates to a counter using a frequency-divider in which a plurality of flip-flops are cascaded.
2. Description of the Prior Art
The conventional counter has a frequency-divider 1, a count detector 2 and a controller 3, as shown in FIG. 1. A clock signal to be counted is applied to the frequency-divider 1, having a series of flip-flops for counting the clock signal. A predetermined set of flip-flop states is detected by the count detector 2. The count detector 2 is composed of, for example, a NAND gate having a plurality of inputs each connected to the desired outputs of the flip-flops. The output from the count detector 2 is applied to the controller 3 to reset the flip-flops in the frequency-divider 1 in synchronism with the clock signal. The counter output is derived from the input or output of the controller 3.
A concrete example of the conventional counter is shown in FIG. 2. The frequency-divider 1 is composed of six flip-flops 11 to 16 so that an output Q of each flip-flop is applied to the succeeding flip-flop. The clock signal is applied to the first stage flip-flop 11. The count detector 2 includes a NAND gate 21 having six inputs, each connected to the output Q or the inverted output Q of the respective flip-flops 11 to 16. The selection of the output Q or the inverted output Q is selected from the binary form of the number to be counted. In order to detect, for example, "32", the respective inputs of the NAND gate 21 are connected to the inverted outputs Q of the flip-flops 11 to 15 and the output Q of the flip-flop 16. The controller 3 has a 2-input NOR gate 31 and an inverter 32. The output of the count detector 2, that is, the output of the NAND gate 21, is connected to one input of the 2-input NOR gate 31. To the other input of the 2-input NOR gate 31 is applied the inverted clock signal. The output of the 2-input NOR gate 21 is applied to the reset terminals R of the flip-flops 11 to 16. Due to the application of the inverted clock signal to the 2-input NOR gate 21, the reset of the flip-flops 11 to 16 is synchronized with the clock signal.
The output signals Q.sub.11 to Q.sub.16 obtained at the corresponding output terminals of the flip-flops 11 and the output of the NAND gate 21 are illustrated in FIG. 3. In the illustration the NAND gate 21 produces an output at a time when the outputs Q.sub.11 to Q.sub.15 are at a low level while the output Q.sub.16 is at a high level. When this output occurs, the flip-flops 11 to 16 are reset to an initial state.
The above operation represents an ideal condition where no time delay is observed in the output of the flip-flops 11 to 16, as shown in solid line in FIG. 3. However, in practical devices, some time delay appears in the outputs due to stray capacitances of transistors and wiring, as shown by dotted lines in FIG. 3. The delays in output in the first few stages are very small and cause no problem. The output time delays cumulate, however, and in the later stages become significant with respect to counter operation; that is, since the time delay of the final output Q.sub.16 becomes greater as the number of the stages cascaded is increased, the output timing and the reset timing are also delayed. For example, if the time delay of the final output becomes longer than the clock repetition period, the counter is no longer reset. The same drawback occurs in the case where the clock repetition period is made short to operate the counter in a high-frequency range. These delays also are a problem with respect to synchronization of the counter output with related circuit elements.
USPTO Backgrounds
USPTO Backgrounds