The present invention relates to a time-base error correction apparatus used in a video tape recorder, video disk player, or the like, for correcting time-base error in the reproduced video signal.
FIG. 1 is a block diagram showing a conventional time-base error correction apparatus. In this drawing, an A/D converter 1 converts to digital form an input reproduced analog video signal. The output of the A/D converter 1 is stored in a memory 3 and later read out and converted to analog form by a D/A converter 2. Address generator circuits 4 and 5 respectively generate addresses used in writing and reading operations of the memory 3. A reference signal generator circuit 6 produces a read clock (RCK) and a read H start pulse (RHS) on the basis of an output of a quartz oscillator or the like for reading operations. Separator circuits 7 and 8 separate a horizontal synchronizing signal from the video signal. The output of the separator circuit 7 is applied to a comparator circuit 9 and there compared with the output of frequency divider 11, which divides the output of a voltage-controlled oscillator (VCO) 10 by a predetermined factor, for example, by 1/910. The output of the comparator circuit 9 is applied to the voltage-controlled oscillator 10 through a low-pass filter 12 so as to control the oscillation frequency of the voltage-controlled oscillator 10. That is, the comparator circuit 9, the low-pass filter 12, the voltage-controlled oscillator 10, and the frequency divider 11 constitute a phase-locked loop (PLL) circuit 13.
The output of the voltage-controlled oscillator 10 is applied as a write clock (WCK) to the A/D converter 1 and the address generator circuit 4 through a phase shifter 16, and the output of the frequency divider 11 is applied as a write H start pulse (WHS) to the address generator circuit 4 through a phase shifter 17. The output of the voltage-controlled oscillator 10 is applied also to a frequency divider 14 to be divided by a predetermined value, for example, by 1/4. A comparator circuit 15 compares the output of the frequency divider 14 with the output of the separator circuit 8 to obtain an error signal used to control the amount of phase shifting imposed by each of the phase shifters 16 and 17.
The horizontal synchronizing signal separated by the separator circuit 7 is thus applied to the PLL circuit 13 to lock the PLL circuit 13 to the phase of the reproduced horizontal synchronizing signal. The phase of a signal of a predetermined frequency (for example, a frequency four times as high as that of the color subcarrier signal f.sub.c) and the phase of a signal frequency-divided by 1/910 by the frequency divider 11 are synchronized with the phase of the reproduced horizontal synchronizing signal.
On the other hand, after being divided by 1/4 by the frequency divider 14, the output of the voltage-controlled oscillator 10 is applied to the comparator circuit 15. The comparator circuit 15 compares the color burst signal produced by the separator circuit 8 with the output signal of the frequency divider circuit 14 to thereby produce a signal indicative of the phase difference between the color burst signal and the output signal of the frequency divider circuit 14. The output signal of the comparator circuit 15 corresponds to the amount of time-base error (residual time-base error) between the video signal and the write clock (and the write H start pulse), which can not be followed only by locking the PLL circuit 13 at the reproduced horizontal synchronizing signal, and the amount of phase shift imposed by the phase shifters 16 and 17. Accordingly, there is no relative time-base error between the video signal and either the write clock produced from the phase shifter 16 or the write H start pulse produced from the phase shifter 17 (both the absolute time-base errors are equal to each other).
The A/D convertor 1 samples the video signal corresponding to the write clock to digitize the video signal. The address generator circuit 4 generates an address at every write clock, and the memory 3 stores the sampled value at the indicated address at every write clock. The address generator circuit 4 is reset whenever the write H start pulse is applied to the address generator circuit 4. Thus, each sampled value is stored at a predetermined address for every line (H).
The address generator circuit 5 generates an address for each read clock pulse (having the same frequency as that of the write clock) produced by the reference signal generator circuit 6. The address generator circuit 5 is also reset whenever the read H start pulse is applied to the address generator circuit 5. Accordingly, a predetermined address is repeatedly generated for every line. The value read out of the specified address of the memory 3 at the timing of the read clock is converted into an analog signal by the D/A converter circuit 2. The read clock has no time-base error, and hence the time-base error of the video signal produced from the D/A conversion circuit 2 is corrected.
However, there is usually some residual time-base error, typically about several hundred nanoseconds, in the PLL circuit 13. The signal applied to the phase shifter 16 has a period of about 70 nsec (=1/4f.sub.c). Accordingly, in order to correct the residual time-base error of about several hundred nsec, the signal applied to the phase shifter 16 must be first frequency-divided by 1/N, then phase shifted, and thereafter frequency-multiplied by the same factor N. As a result, the circuitry becomes complicated.
Further, not only the write clock, but also the write H start pulse is essential to generate an address for every line, and therefore two phase shifters are required because the write clock and the write H start pulse must be synchronous with each other. Further, it is necessary to highly accurately adjust the shifters to make them coincident with each other in sensitivity, in operation point, and the like, and moreover a highly accurate compensation circuit is essential to compensate for changes in temperature and the like.
USPTO Backgrounds
USPTO Backgrounds