The present invention relates to a semiconductor device having bumps, a method for fabricating the same, and a method for forming bumps.
More specifically, the present invention relates to a semiconductor device having bumps able to ease thermal stress to prevent damage due to thermal stress and therefore of high reliability, a method for fabricating the same, and a method for forming bumps.
Along with the increasingly small size of electronic apparatuses, attempts have been made to use compact semiconductor packages of sizes similar to the size of a chip of a flip-chip structure. A large number of electronic circuits are integrated on such a small package, so many connection terminals are necessary. On the other hand, due to the reduced size, the problem arises that the space for arranging these connection terminals is insufficient. In such a small semiconductor package, DIPs or other connection terminals of the related art cannot be used.
As a solution to this problem, attempts have been made for flip chip mounting where a large number of small projecting electrodes (bumps) are formed on the bottom surface of a semiconductor integrated circuit chip, many electrodes are formed on a printed wiring board at positions corresponding to those bumps, and the electrodes on the wiring board and the bumps formed on the semiconductor integrated circuit chip are directly bonded. Such flip chip mounting has the advantage that many bumps can be formed even on the bottom surface of a semiconductor integrated circuit chip of a limited space.
As a method for connecting bumps and electrodes, attempts have been made to seal a semiconductor integrated circuit chip and a wiring board by a resin to connect and affix them.
Summarizing the problem to be solved by the invention, a large number of semiconductor integrated circuit chips are of a type using silicon for their semiconductor substrates. The linear thermal expansion coefficient of a silicon chip is much smaller than that of a wiring board. For example, the former is no more than 10% of the latter. As a result of the large difference of the linear thermal expansion coefficients, thermal stress appears when the temperature changes.
In most cases, the linear thermal expansion coefficient of the semiconductor integrated circuit chip is also largely different from that of the sealing resin. Similarly, the linear thermal expansion coefficient of the wiring board is often different from that of the sealing resin.
As a result of the difference of the linear thermal expansion coefficients, when the temperature rises during operation of the semiconductor integrated circuit chip, thermal stress appears between the semiconductor integrated circuit chip and the wiring board between which the sealing resin is interposed.
In a flip-chip structure designed for compactness, there is no mechanism for easing stress such as a lead frame. Therefore, if flip chip mounting is adopted, there could be deformation of the semiconductor integrated circuit chip, decline of bonding between bumps and electrodes, or even loss of the bonded state.
As shown here, although a reduced size is aimed at with flip chip mounting, sometimes the reliability of the semiconductor device could decline because of poor bonding or loss of bonding caused by thermal stress.
Accordingly, it is desirable to improve the reliability against thermal stress for a flip chip mounting semiconductor device which does not have a mechanism such as a lead frame for easing stresses.
USPTO Backgrounds
USPTO Backgrounds