1. Technical Field
The present invention relates to memory circuits in general, and in particular to memory circuits having chalcogenide cells. Still more particularly, the present invention relates to a read/write circuit for accessing chalcogenide memory cells.
2. Description of the Related Art
The use of electrically writable and erasable phase change materials for electronic memory applications is known in the art. Such phase change materials can be electrically switched between a first structural state where the material is generally amorphous and a second structural state where the material is generally crystalline. The phase change material exhibits different electrical characteristics depending upon its state. For example, in its amorphous state, the phase change material exhibits a lower electrical conductivity than it does in its crystalline state. The phase change material may also be electrically switched between different detectable states of local order across the entire spectrum ranging from the completely amorphous state to the completely crystalline state. In other words, the state switching of the phase change materials is not limited to either completely amorphous or completely crystalline states but rather in incremental steps to provide a “gray scale” represented by a multiplicity of conditions of local order spanning the spectrum from the completely amorphous state to the completely crystalline state.
General speaking, phase change material memory cells are monolithic, homogeneous, and formed of chalcogenide material containing chemical elements selected from the group of Tellurium (Te), Selenium (Se), Antimony (Sb), Nickel (Ni), and Germanium (Ge). Chalcogenide memory cells can be switched between two different electrically detectable states within nanoseconds in response to an input of picojoules of energy. Chalcogenide memory cells are truly non-volatile and can maintain the stored information without the need for periodic refreshing. Furthermore, the stored information remain intact even when power is removed from the chalcogenide memory cells.
The present disclosure describe a read/write circuit for accessing chalcogenide memory cells.
USPTO Backgrounds
USPTO Backgrounds