Memory devices are utilized as non-volatile memory for a wide range of electronic applications. Resistive memory devices may include an array of resistive memory cells and a corresponding array of switching transistors. Typically, a switching transistor and an associated resistive memory cell form a semiconductor memory control unit. A plurality of semiconductor memory control units complemented with other sub-circuits having a specific function may be configured to form an integrated circuit memory array. The switching transistor may be a field effect transistor, and in particular a metal oxide semiconductor field effect transistor (MOS FET). In a memory control unit or integrated circuit of a conventional semiconductor memory array, a switching transistor generally includes a source terminal, a drain terminal, and a gate terminal. The drain terminal is connected to the resistive memory cell. In addition, the source, drain, and gate of the switching transistor, their respective terminals, and the resistive memory cell are disposed on the same side of the semiconductor substrate.
With the increase in storage density and decrease in the semiconductor process technology node, the feature size of transistors, resistors and other semiconductor memory cell storage control units (alternatively referred to as storage units) has been continuously reduced. Accordingly, the distance (spacing) between gate and drain is becoming smaller, resulting in an increase of difficulty in manufacturing processes and coupling capacitance. Furthermore, because the contact holes and contacts of the source and drain electrodes are disposed on the same side of the substrate, the value of coupling capacitance between metal plugs of the gate and source and drain electrodes also increases.
The continuous increase in coupling capacitance between the gate and source/drain seriously affects the performance of the transistor, thereby affecting the performance of the integrated circuit. While a prior art fin-type field effect transistor (Fin FET) device can solve the problem of coupling capacitor to a certain extent, but as device dimensions continue to shrink, the performance of such Fin FET device may become adversely affected. The resistive memory cell array as a memory integrated circuit interconnected with row select and column select lines, source electrodes, drain electrodes, and gate electrodes of associated switching transistors and the corresponding connection terminals embedded in the same side of an interlayer dielectric layer are submitted to an thermal annealing process that may adversely affect the production yield. There are undoubtedly manufacturing difficulties in the integration process of the memory array circuit. For example, the quality of solid-state resistance change memory devices, such as thermal phase-change storage device (PCRAM), magnetoresistive memory device (Magnetic RAM) and variable resistor voltage sensitive device (ReRAM) are not suitable for post high temperature heat treatment processes.
Therefore, to solve the above problems, the present invention provides a novel semiconductor memory control unit, an integrated circuit using the semiconductor memory control unit, and method of manufacturing the integrated circuit.
USPTO Backgrounds
USPTO Backgrounds