Generally in electronics, a digital phase and frequency detector (“DPFD”) is a device which compares the phase and frequency of two input signals. The two inputs usually correspond to a voltage-controlled oscillator (“VCO”), as a feedback signal, and an external source as a reference signal. The DPFD can have two outputs for providing information to other circuitry for phase locking. To form a phase-locked loop (“PLL”), the DPFD's phase error output is fed to a loop filter which integrates the signal to smooth it. This smoothed signal is fed to a voltage-controlled oscillator which generates an output signal with a frequency that is proportional to the input voltage. The VCO output is also fed back to the DPFD to form the PLL circuit.
In traditional analog PLL techniques, a phase and frequency detector converts the phase and frequency differences between the reference clock and the feedback clock into an analog signal. Depending on the technology, this signal can either be a voltage which can be applied directly to the loop filter or a current generated by a charge pump. One disadvantage of the analog PLL structures is the silicon integration. Due to spur reduction requirements, the loop filter requires large resistors and capacitors, typically connected externally to an IC chip, to achieve a low PLL bandwidth. Another major disadvantage of conventional PLLs is lack of portability from one process technology to another. Therefore, more and more PLL designers are attempting to use digital architectures to implement a PLL. One of the key function blocks of a digital PLL is a digital phase and frequency detector.
Typically, a digital phase and frequency detector is implemented based on a time-to-digital converter (“TDC”). Various approaches for digital phase and frequency detectors have been attempted but have draw backs, such as increased hardware resources, slow locking time, or degradation in performance. For instance, it is difficult to achieve a DPFD that has both accuracy and low complexity. Furthermore, a bang-bang PLL technique is simpler since it uses a one-bit polarity output DPFD, but is not accurate in high performance applications. Thus, the need exists for a digital phase and frequency detector that can reliably produce phase error signals and has relatively low complexity.
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