The semiconductor device with a vertical transistor is described in, for example, Japanese Patent Laid-Open No. 05-110019. In this description, a structure is disclosed, in which a trench for forming a gate electrode is self-alignedly formed in a semiconductor region, in which a channel portion of a vertical MOS transistor is to be formed, by a bit line provided on the semiconductor region.
In addition, in U.S. Pat. No. 6,060,723, which corresponds to a gazette of Japanese Patent Laid-Open No. 11-87541, a semiconductor device having a PLED transistor is described. In this description, a structure is disclosed, in which a side gate structure is provided on a sidewall of a vertical pillar, and the vertical pillar has a relatively conductive material and a non-conductive material.
USPTO Backgrounds
USPTO Backgrounds