1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for utilizing a flash EEPROM memory array supplementing main memory to provide diagnostic functions.
2. History of the Prior Art
Recently, flash electrically-erasable programmable read-only memory (EEPROM) storage devices have been used in arrays as a new form of long term storage. A flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells into different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. A charge typically indicates a xe2x80x9czeroxe2x80x9d or programmed condition, while the absence of a charge indicates a xe2x80x9conexe2x80x9d or erased condition. The floating gate condition may be detected when the device is read.
These arrays may be designed to accomplish many of the operations previously accomplished by other forms of memory in digital systems. For example, flash memory is being used to replace various read-only memories such as the basic input/output system (BIOS) memory of a computer system. The ability to program flash memory in place offers substantial advantages over more conventional EPROM memory. More recently, flash memory has been used to provide a smaller lighter functional equivalent of an electromechanical hard disk drive. Flash memory is useful for this purpose because it may be read more rapidly and is not as sensitive to physical damage as an electro-mechanical hard disk drive. Flash hard drive memories are especially useful in portable computers where space is at a premium and weight is extremely important.
However, before flash memory can be used to store rapidly changing data, a number of difficult problems which are related to the design of flash memory must be solved. Typically, a flash memory array is divided into blocks which are connected so that all of the memory cells of an entire block are erased simultaneously. Thereafter, a cell may be individually programmed to store data. Since all of the memory transistors of a block of the array are joined to be erased together, a cell in a programmed condition cannot be switched to the erased state until the entire block of the array is erased. Thus, invalid information cannot be erased without erasing also all of the valid information that remains in the block. The result is that, unlike other memories in which changed data is written (essentially instantaneously) directly in place of the data it replaces, a flash EEPROM memory array requires a time consuming erasure process before it may be rewritten. When the information changes at a data entry in flash memory used to store changing information, the new information is written to a new memory area rather than over the old information; and the old information is marked as invalid. Then, after the block with the old information has filled and a sufficient portion of that block has been marked invalid, all valid information remaining in the block is written to a clean memory area; and the entire block may then be erased, often by a background process.
Intrinsically, flash memory may be read at the same rate as dynamic random access memory (DRAM) manufactured by the same processes so it would seem that flash memory might be used to replace or supplement main memory. However, because the level of charge required to write a flash device is much greater, writing to flash memory takes somewhat longer than writing to DRAM. Moreover, because changed data may not be directly written over invalid data in a block of flash memory but must be written to a new area, the old data invalidated, and the block with invalid data ultimately erased, the average time to write to flash memory is very much longer than to write to DRAM.
Thus, although flash memory has been used for many purposes in computer systems, it has not been used as main memory or a supplement to main memory. The write time for flash memory has been considered to be too long to allow the use of flash memory as a part of main memory.
There are a number of reasons to utilize flash memory at least as a supplement to main memory in a computer system. Data placed in flash EEPROM memory does not require a refresh cycle nor expend power for such a cycle. Since data placed in flash memory is not lost when power is removed from the system, processes which are normally stored in read only memory such as the basic input/output start-up (BIOS) processes could be placed in flash memory on the main memory bus to provide very rapid start-up. The BIOS processes are now typically stored in flash EEPROM or EPROM memory on what is referred to as the X bus, an adjunct to the Industry Standard Association (ISA) bus, in an Intel-processor-based system. When power is applied to a computer, the BIOS processes in the flash read-only memory on the X bus are read and transferred via the ISA bus (or other secondary bus), an ISA/PCI bridge, the PCI bus, and a PCI-to-processor/memory bridge to main memory. Eliminating the transfer of the BIOS processes to main memory would provide rapid system start-up. Moreover, there would be no need to shadow the BIOS processes in DRAM main memory so the portion of main memory typically used for that purpose would be unnecessary.
Placing BIOS processes in a flash EEPROM memory array which resides on the memory bus as a supplement to main memory would also offer another significant advantage. The BIOS includes various processes which test the condition of various components of the computer system. These BIOS processes are useful to one servicing a computer in the event of a failure. However, if the computer has problems which make it impossible to write the BIOS processes to main memory, the BIOS processes cannot be used in determining the nature of the problem. If these processes could somehow be made available in permanent memory on the memory bus, then even though the computer was otherwise inoperative, discovering the source of problems would be much easier.
The present invention is realized by a flash EEPROM memory array designed to be joined to a memory bus of a computer, diagnostic processes stored in the array for testing status of system to provide data indicating malfunctions in the computer, accessing processes stored in the array for calling the diagnostic processes even though the computer fails to boot, and communication processes stored in the array for transferring results produced by the diagnostic processes for use in servicing the computer.
One embodiment of the invention allows the transfer of data between hardware components of a computer and an external host computer so that a service technician at the host computer may diagnose and correct malfunctions within the computer which includes the flash EEPROM memory array.
The objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
USPTO Backgrounds
USPTO Backgrounds