1. Field of the Invention
The invention relates generally to digital memories and more specifically to memory systems utilizing a plurality of integrated circuit arrays with the memory system cycle time for selected blocks of memory being reduced by utilizing the array enable input signal to minimize the decoding time for address sequences assigned to these blocks of memory.
2. Description of the Prior Art
Typical integrated circuit digital memory arrays utilize a multi-bit address signal and a single bit array enable signal. In the prior art memory systems utilizing a plurality of these integrated circuit memory arrays have utilized an addressing scheme in which all of the storage locations in each array was considered as individual blocks of memory and addressed by a continuous group of address numbers. This addressing scheme required that the address input to the array be completely decoded by the address decoder forming a part of the array each time the storage location being addressed changed. Decoding the multi-bit address signal by the decoder forming a part of the array circuitry is relatively slow due to the fact that a relatively large number of bits are involved. In these prior art systems, the single bit array enable input signal to the individual arrays was utilized to switch between blocks of memory with all of the storage locations within an individual array considered as a block. For example, the first array might be assigned addresses from zero to 1024 while the second array would be assigned sequential addresses between 1024 and 2048. Thus for the first 1024 memory storage locations the array enable input signals would remain stable with at least one bit of the multi-bit address signal to the array changing for each new memory storage location addressed. This required a complete decoding of the address for each memory cycle. Utilizing this addressing method, the effective memory access time was determined by the time required to decode the multi-bit address signal to the array containing the storage location being addressed. This address arrangement would be continued for the remainder of the arrays comprising the memory system.
USPTO Backgrounds
USPTO Backgrounds