The present invention relates generally to an arrangement for and method of operating a computer system including a host computer having system Random Access Memory (RAM) and using a Basic Input/Output System (BIOS) to operate the host computer. More particularly the arrangement and method of the invention stores at least a portion of the BIOS used to operate the system within the mass memory storage of a mass memory storage peripheral computer device rather than in Read Only Memory (ROM). The BIOS stored in the mass storage media may be expansion BIOS associated with a particular peripheral computer device and/or system BIOS associated with the host computer. The ROM refers to either system ROM provided by the host computer or peripheral ROM provided by a peripheral device (either on a card or on the device itself).
The computer industry is continuously evolving, providing faster processors, larger memory capacities, and a variety of peripheral devices which may be interconnected with a host computer. Due to these increasing speeds and capacities, one of the developments in the industry is a peripheral bus implementation known as Peripheral Components Interface (PCI). This peripheral bus has been developed to provide an expansion mechanism between the host computer and peripheral computer devices or expansion boards.
The PCI peripheral bus is designed to be both processor and computer system architecture independent with the PCI electrical, protocol, and hardware interface requirements remaining the same regardless of the CPU or host system computer architecture being used. This allows the same peripheral computer device to be connected to a variety of different host systems without requiring different versions of the device for each type of host system with which the device is intended to be used. Because the PCI bus is independent of the processor and the computer architecture, each host system is required to provide a mechanism to map host I/O and memory space to the addressing mechanism used on the PCI bus. This is also true of the expansion ROM memory space of a peripheral computer device, which typically includes initializing information and operating information such as code and data for that peripheral computer device. Therefore, relocatable expansion ROM location addresses are allowed on a PCI device. This is not the case for earlier bus architectures such as the Industry Standard Architecture (ISA) Bus.
As shown in FIG. 1, which illustrates one example of a typical PCI-based computer system designated by reference numeral 10, system 10 includes a host computer 12 having a system BIOS 13 for operating host computer 12 and having system RAM memory 14 associate with host computer 12. System BIOS 13 is stored in system ROM 15 within host computer 12. A PCI peripheral bus 16 is connected to host computer 12 and system RAM 14 using a host bridge 17. The system also includes a peripheral computer device 18, for example a hard disk drive, which is connected to the PCI bus such that the host computer may communicate with the peripheral computer device using the PCI bus. Device 18 includes ROM 20 which contains any expansion BIOS 22 required in the host system in order to initialize and/or operate peripheral computer device 18. In a system using the PCI bus, the host system BIOS and/or operating system must provide a configuration manager that recognizes individual PCI devices, allocates resources, and enables those devices. It is the responsibility of the configuration manager to copy any expansion BIOS of the peripheral device into the host computer""s RAM and then execute any initialization routine provided within the expansion BIOS to provide proper peripheral device initialization.
Referring to FIG. 2A, which diagrammatically illustrates the expansion BIOS 22 contained in ROM 20, the PCI specification allows for multiple code images, for example 24a-24d, to be stored within the expansion BIOS 22 with each code image providing the appropriate information for a particular computer architecture. In this example, code image 24a might correspond to an Intel(copyright) based system, code image 24b might correspond to a Power PC(copyright) based system, and so on. These multiple code images 24a-24d increase the amount of information which is included in the expansion BIOS thereby increasing the amount of ROM required to store the expansion BIOS 22. As shown in FIG. 2B, code image 24a, and each of the other images, includes a header region 26. Depending on the requirements of device 18 to which the expansion BIOS 22 corresponds, each image may also include a data structure region 28, runtime code 30, initialization code 32, and a check sum 34. Referring to FIG. 2C, the PCI specification also requires that each PCI device includes a configuration space memory 35 which is 256 bytes in size and which conforms to the PCI format illustrated. The information provided by configuration space 35 includes a device ID register 36 containing the device identification and a configuration register 38 containing a requested amount of memory space. The configuration register 38 specifies the amount of memory space required within the host computer memory to map the expansion BIOS 22 associated with peripheral computer device 18.
As will be described in more detail immediately hereinafter, once expansion BIOS 22 has been copied into host system RAM 14, the initialization code 32 from the proper code image, for example code image 24a, is run. This initializes device 18 and provides the proper hooks into the system for operating device 18 using runtime code 30 from the proper code image, in this case, image 24a, as contrasted with image 24b, c, or d. Once the initialization code has been run, control is returned to the host system and only the code required for operating device 18 is left in host system RAM 14 where it remains throughout the operation of the system. The excess information of the proper code image 24a being only necessary for initialization of device 18 is no longer necessary. Therefore, the memory used to store this excess information is made available to be used again by host computer 12, thereby reducing the usage of RAM 14 to store the necessary portions of expansion BIOS 22.
Referring now to FIG. 3, a typical sequence for obtaining expansion BIOS from a PCI peripheral device and storing it within, system RAM will be described in detail using the example of system 10 described above. After computer system 10 is turned on, indicated in block 40 of FIG. 3, the processor of host computer 12 starts running system code typically called Power-On-Self-Test (POST) as indicated by block 42. The POST code performs unrelated system configurations (block 44) and then starts the configuration of the PCI bus add-on peripheral devices by checking for the presence of peripheral devices, such as peripheral device 18, as indicated by decision box 46. Once the POST code finds peripheral device 18 and as respectively indicated in blocks 48, 50, and 52 of FIG. 3, the POST code starts the configuration of device 18, allocates host I/O and RAM memory space as requested by device 18, and configures interrupt and allocates IRQs on host computer 12 as requested by device 18. At this point, the POST code determines if device 18 has an expansion BIOS that needs to be loaded and configured as indicated by decision block 54. If there is no expansion BIOS, as indicated by clock 56, the POST code goes on to the next peripheral device. If all the devices are configured, the POST code goes on to boot the operating system as shown in block 58. If, however, there is an expansion BIOS to be loaded from the device, as is the case for device 18, the expansion BIOS is loaded and configured as indicated by block 60. Once this loading of the expansion BIOS for device 18 is completed, the sequence proceeds to block 56 and the process continues for any other devices.
Referring now to FIG. 4, the typical process of loading and configuring the expansion BIOS of a peripheral device as indicated in block 54 and 60 of FIG. 3 will be described in more detail. Starting at decision block 54 in which the POST code determines if peripheral device 18 has an expansion BIOS, the POST code writes to and reads from the configuration register 38 of configuration space memory 35 of peripheral device 18 to determine if an expansion BIOS is present on the device and, if so, how much memory space is requested. Once it is determined that there is an expansion BIOS, the process of loading and configuring the expansion BIOS associated with device 18 generally indicated by block 60 of FIG. 3 proceeds as will now be described in detail.
As indicated by block 62 of FIG. 4, the POST code determines an acceptable address to map expansion BIOS 22 stored in ROM 20 of device 18 to and writes that address to the configuration register 38 of configuration space memory 35 on PCI peripheral device 18. In block 64, the POST code then enables expansion BIOS ROM decoding on the device. Next, peripheral device 18 maps its ROM memory starting at the address the POST code wrote to configuration register 38 in configuration space memory 35 on device 18 as indicated in block 66. The device sets up its internal address decoder to decode the memory address range to which the ROM memory is mapped. As indicated in block 68, the POST code reads through the expansion BIOS by reading the memory locations to which the expansion BIOS was mapped, searching for an appropriate expansion BIOS code image, in this case code image 24a of expansion BIOS 22. If an appropriate code image is not found, as shown in decision block 70, the sequence returns to block 56 to see if there are additional devices to be configured. However, if proper code image 24a is found, the sequence moves to block 72 in which the POST code determines a memory location within host system RAM 14 to copy the expansion BIOS code into from the device""s ROM 20. The POST code then in block 74 copies the appropriate code image 24a from the device""s ROM 20 into system RAM 14. As indicated in blocks 76 and 78, the POST code calls initialization code 32 of expansion BIOS 22 now in system RAM 14 and runs initialization code 32 further configuring peripheral device 18 and installing system level software support including interrupt handlers, device specific data, etc. Once initialization code 32 is finished, initialization code 32 returns control of the system to the POST code as shown in block 80. In block 82, the POST code performs any final initialization such as marking the portion of the system RAM 14 used to store the expansion BIOS remaining in system RAM after initialization code 32 has run as read only. And finally, at this point the sequence returns to decision block 56 to see if there are any more devices present to be configured.
As described above, the expansion BIOS 22 is typically stored in ROM 20 located on the peripheral computer device or an expansion card. However, this approach has the disadvantage of adding to the cost of the device by adding the cost of ROM 20 which in a system using a PCI bus is only used to store the expansion BIOS for loading into the system after system start-up. More particularly, in a system using a PCI bus and as mentioned above, the host computer is required to copy the expansion BIOS into the host system""s RAM. For purposes of efficiency, the system uses the copied expansion BIOS stored in its own memory rather than referring back to the ROM on the device when the expansion BIOS is required for the operation of the system. Therefore, once the necessary portions of the proper image 24a are stored in the host system""s RAM, ROM 20 is not accessed again until the system is turned off and on again at which time the proper image of the expansion BIOS is again loaded into the host system RAM. Also as mentioned above, because multiple images may be required in order to allow the same device to be connected to a variety of host systems having different computer architectures, the size of overall expansion BIOS 22 and therefore ROM 20 required to store the expansion BIOS can be rather large. This can cause the expansion BIOS ROM 20 to become a significant portion of the cost of device 18.
The cost of this expansion BIOS ROM varies depending on the specific type of ROM used. In a case in which high volumes of the devices are being produced, the ROM may be manufactured with the expansion BIOS programmed into the ROM at the time of manufacture of the ROM. This approach has the advantage of being less expensive; however, once this type of ROM is programmed, it may not be changed. If the device is modified in any way which requires a change in the expansion BIOS, or if a bug is found in the expansion BIOS, all of the ROM that have been produced with the old expansion BIOS must be scrapped. This approach does not provide much flexibility in updating and improving the operation of the device by updating the expansion BIOS.
In another approach, the expansion BIOS is programmed into the ROM after the ROM is manufactured. This allows the expansion BIOS to be updated without having to scrap the ROM which have been manufactured as would be the case for the above described approach. Although the programmable ROM provides more flexibility, it is more expensive than ROM which is programmed during its manufacture and further increases the cost of providing the expansion BIOS ROM. With the extremely competitive nature of the computer peripheral device market, for example in the area of hard disk drives, the ability to reduce or even eliminate the cost of the ROM for the expansion BIOS would provide a significant competitive advantage.
The present invention discloses a novel arrangement and method for operating a host computer having a system BIOS which is used to operate the host computer and having system RAM associated with the host computer. The arrangement and method allow at least a portion of the BIOS to be stored within the mass memory storage of a mass memory storage peripheral device which is connected to the host computer. The BIOS stored within the mass memory storage may be expansion BIOS associated with any particular peripheral computer device and/or expansion BIOS associated with the mass memory storage peripheral computer device itself. The BIOS stored within the mass memory storage may also be system BIOS associated with the host computer. This approach significantly reduces or even eliminates the need for and cost of the expansion BIOS ROM for the particular peripheral computer device and/or the expansion BIOS ROM for the mass memory storage peripheral computer device. This approach may also be used to significantly reduce the need for and cost of the system BIOS associated with the host computer. Since some or all of the expansion BIOS and/or some of the system BIOS is stored in the mass memory storage of a mass memory storage peripheral computer device, this approach also provides substantially improved flexibility in updating and improving the system or fixing bugs in the BIOS without having to use programmable ROM. Using this novel approach, the majority of the system BIOS and the majority of, or all of, the expansion BIOS associated with the peripheral devices connected to the system may be updated by simply reloading a revised BIOS into the mass memory storage of the mass memory storage device without having to scrap any BIOS ROM.
As will be described in more detail hereinafter, an arrangement for and method of operating a computer system is disclosed herein. The computer system includes a host computer having system RAM and a mass memory storage peripheral computer device such as a hard disk drive connected to the host computer. The host computer uses a BIOS to control the operation of the computer system. The arrangement and method allow at least a portion of the BIOS to be stored within the mass memory storage of the mass memory storage peripheral computer device rather than requiring all of the BIOS to be stored within BIOS ROM.
In one embodiment, the method of and arrangement for operating the computer system is a method of and arrangement for operating a particular peripheral computer device connected to the host computer using a peripheral bus in which relocatable expansion BIOS location addresses are allowed, such as a PCI bus. In this embodiment, the BIOS is expansion BIOS associated with the particular peripheral computer device. The operation of the peripheral computer device requires the host computer to obtain the expansion BIOS associated with the particular peripheral computer device and load the expansion BIOS into the system RAM. This embodiment includes ROM storage memory (peripheral ROM) for containing a first portion but not all of the expansion BIOS associated with the particular peripheral computer device. A second portion of the expansion BIOS associated with the particular peripheral computer device is stored within the mass memory storage of the mass memory storage peripheral computer device connected to the host computer. The particular peripheral computer device may or may not be the mass memory storage peripheral computer device. The arrangement further includes an operating mechanism for causing the host computer to access the peripheral ROM and obtain the first portion of the expansion BIOS associated with the particular peripheral computer device. Thereafter, by using the first portion of the expansion BIOS, the host computer is caused to (i) access the mass memory storage of the specific mass memory storage peripheral computer device, (ii) obtain the second portion of the expansion BIOS which is associated with the particular peripheral computer device and which is location within the mass memory storage of the mass memory storage peripheral computer device, and (iii) store the second portion of the expansion BIOS within the system RAM.
In this embodiment, the host computer may include system ROM memory storage containing system BIOS (system ROM). The peripheral ROM storage memory containing the first portion of the expansion BIOS may be separate and apart from the system ROM storage memory, or, alternatively, the peripheral ROM storage memory containing the first portion of the expansion BIOS may be part of the system ROM storage memory. In the case in which the ROM storage memory containing the first portion of the expansion BIOS is separate and apart from the system ROM storage memory, this peripheral ROM storage memory containing the first portion of the expansion BIOS associated with the particular peripheral computer device may be is located on the particular peripheral computer device.
In another embodiment in which the method and arrangement are a method and arrangement of operating a particular peripheral computer device, the entire expansion BIOS associated with the particular peripheral computer device is stored within the mass memory storage of the mass memory storage peripheral computer device. In this embodiment, the method and arrangement further include an operating mechanism for commencing the operation of the system,. Once the operation of the system is commenced, the operating mechanism causes the host computer to (i) access the mass memory storage of the mass memory storage peripheral computer device, (ii) obtain the expansion BIOS associated with the particular peripheral computer device, and (iii) store within the system RAM the expansion BIOS associated with the particular peripheral computer device.
In a specific version of the embodiment which stores the entire expansion BIOS within the mass memory storage of the mass memory storage peripheral computer device, the mass memory storage peripheral computer device includes a memory buffer on the mass memory storage peripheral computer device. In this version, the expansion BIOS associated with the particular peripheral computer device includes a first portion of the expansion BIOS and a second portion of the expansion BIOS. Also, the operating mechanism causes the host computer to perform a Power-On-Self-Test upon the commencing of operation of the, system. The mass memory storage peripheral computer device includes a mechanism for loading the first portion of the expansion BIOS associated with the particular peripheral computer device into the memory buffer of the mass memory storage peripheral computer device within the time frame of the Power-On-Self-Test. This allows the operating mechanism to access the memory buffer and obtain the first portion of expansion BIOS. Thereafter, by using the first portion of the expansion BIOS, the host computer is caused to (i) access the mass memory storage of the mass memory storage peripheral computer device, (ii) obtain the second portion of the expansion BIOS which is associated with the particular peripheral computer device and which is located within the mass memory storage of the mass memory storage peripheral computer device, and (iii) store the second portion of the expansion BIOS within the system RAM.
In each of the above described embodiments, the particular peripheral computer device associated with the expansion BIOS may actually be the mass memory storage peripheral computer device which provides the mass memory storage in which at least a portion of the expansion BIOS is stored. Alternatively, the particular peripheral computer device may be any other peripheral computer device such as a video card, a network card, or any other peripheral computer device or expansion card.
In another embodiment, the BIOS is system BIOS associated with the host computer. In this embodiment a first portion of the system BIOS is contained within a BIOS ROM located within the host computer. A second portion of the system BIOS is stored within the mass memory storage of the mass memory storage peripheral computer device. This second portion of system BIOS is retrieved and stored in system RAM in the same manner as the expansion BIOS stored within the mass memory storage as described previously.
In another aspect of the invention, a computer memory storage medium other than ROM for use in a computer system is disclosed. The computer system includes a host computer having system RAM associated with the host computer and a mass memory storage peripheral computer device which is connected to the host computer. The host computer uses a BIOS to control the operation of the system. At least a portion of the BIOS is stored within the mass memory storage of the mass memory storage peripheral computer device for use by the host computer after the host computer has loaded the BIOS stored in the mass memory storage into the system RAM of the host computer. The computer memory storage medium of the invention has a portion of the memory storage medium containing BIOS for controlling the operation of the host computer. In one embodiment of the computer memory storage medium, the medium is the mass memory storage of the mass memory storage peripheral computer device, such as a hard disk drive, which is connected to the host computer.
In another embodiment of the computer memory storage medium, the medium is a floppy disk or another such medium, and the BIOS contained on the medium is transferable to the mass memory storage peripheral computer device. In this embodiment, the BIOS contained on the medium may be updated and revised BIOS associated with at least a portion of the computer system such as expansion BIOS associated with a particular peripheral computer device connected to the system or system BIOS associated with the host computer. Alternatively, the BIOS contained on the medium may be expansion BIOS associated with a particular peripheral computer device being connected to the computer system.
USPTO Backgrounds
USPTO Backgrounds