1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, more particularly, to a complementary field-effect transistor (CMOSFET) which uses germanium (Ge) and silicon germanium (SiGe) as a material of its channel.
2. Description of the Related Art
Currently, MOSFETs using silicon (Si) as a channel material are widely in practical use. In recent years, designs to improve carrier mobility of the MOSFETs are attempted, such as giving strain in a channel region or the like (see, for example, the specification of U.S. Pat. No. 6,621,131). As another design to improve carrier mobility, MOSFETs and the like using Ge as their channel material have been developed.
A conventional Ge-channel CMOSFET using Ge as its channel material has a similar structure to that of an existing Si-channel MOSFET using Si as its channel material, and as its source/drain regions, diffusion layers doped with impurities are mainly used.
However, at present, the development of the Ge-channel MOSFET is targeted mostly at a p-channel type. To form a Ge-channel CMOSFET by using a Ge substrate or the like, used is a method to form source/drain regions by pn junctions in such a manner that diffusion layers are formed by doping a Ge substrate or the like with an n-type impurity atom. When this method is adopted, it is essentially difficult to form the source/drain junctions by an n-type impurity because the n-type impurity is generally large in diffusion coefficient and small in solubility limit. This is one of the reasons why it has been difficult to realize an extremely scaled Ge-channel CMOSFET of an n-channel type. Therefore, at present, a scaled and high-speed CMOSFET including Ge-channel CMOSFETs of both a p-channel type and an n-channel type has not been realized.
In a Ge-channel CMOSFET, a metal gate comprised of TaN, TiN, or the like is in the mainstream as a gate electrode, but etching for pattern formation of the metal gate is difficult and an aggressively scaled gate electrode is difficult to form. Further, a threshold voltage is determined depending on its work function, and therefore, it is essentially difficult to adjust the threshold voltage.
In this respect, if reactive ion etching (RIE) is used, a gate electrode is relatively easily formed and there is a possibility that the threshold voltage can be adjusted by doping, and in view of the above, the use of polycrystalline silicon as a material of the gate electrode is also conceivable. However, this method is not suitable for forming a Ge-channel CMOSFET because this method requires high-temperature heat treatment at about 700° C. when the polycrystalline silicon is deposited and when an impurity with which the inside of the polycrystalline silicon is activated. Moreover, no study has been made regarding the control of a threshold voltage in a case where the polycrystalline silicon is used as the material of the gate electrode.
As another method, the use of high Ge-concentration SiGe as a channel material to realize higher speed has conventionally been considered, but such a SiGe-channel CMOSFET has the same disadvantages as those of the Ge-channel CMOSFET.
USPTO Backgrounds
USPTO Backgrounds