Many semiconductor-memory products such as DRAMs use the so-called defect relieving method for improving the yield of memory products by using spare row lines and column lines (bit lines and word lines) and replacing these space row lines or column lines with row lines or column lines in which a defect occurs. A defect detection circuit is a circuit for comparing an accessed address with an address previously assigned to a spare row line and column line and determining whether to replace the former address with the latter address.
FIG. 1 is an illustration showing a conventional defect detection circuit. Circuit 1 is a circuit for holding an address determined to be a defect when testing a memory product as previously-programmed information (hereafter referred to as program information) by using a fuse or the like. Circuit 2 is a circuit for renewing and holding an address accessed (inputted) in read or write operation as address information. Though the number of pieces of address information to be inputted depends on a configuration of a memory, 10 to 14 pieces of the address information are required. Circuit 3 is a circuit for comparing program information outputted from Circuit 1 with address information outputted from Circuit 2 and determining whether to select a spare line.
FIG. 2 is an illustration showing a configuration of the comparing and detection Circuit 3 in FIG. 1. In FIG. 2, the program information (i.sup.th) outputted from the Circuit 1 is compared with the address information (i.sup.th) outputted from the Circuit 2 by an exclusive NOR Circuit 4. Then, comparison results are accumulated by a combinational Circuit 5 comprising a NAND circuit and a NOR circuit and when all the comparison results are matched, a result of replacement with spare lines is outputted.
The compare and detection Circuit 3 in FIG. 2 usually optimizes a combinational circuit comprising logical gates and the size of a transistor to be used. However, because of a large number of inputs such as 10 to 14, the combinational Circuit 5 requires logical gates of at least three stages as shown in FIG. 2. As a result, a problem occurs that it takes a lot of time to output a comparison and selection result.
USPTO Backgrounds
USPTO Backgrounds