Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
FIG. 1 shows a cross-section, along a wordline, of a typical prior art NAND flash memory array. The array is comprised of a silicon substrate 100 with a gate insulator layer 101 formed on top of the substrate 100. Shallow trench isolation (STI) areas 103 and 104 are formed between the bitlines. The floating gates 105 and 106 are formed between the oxide isolation areas 103 and 104. An interpoly insulator 107 is formed over the floating gates 105 and 106 prior to forming the control gate 110 on top. The memory array is comprised of multiple rows 120 and 121 of memory cell transistors.
FIG. 2 shows a cross-sectional view, along a bitline, of the typical prior art NAND flash memory array of FIG. 1. This view shows the source/drain regions 201 and 202 for each cell as well as the gate insulator 101, floating gate 105, interpoly insulator 107, and control gate 110 that is part of the wordline. One bit is typically stored on each floating gate in such a flash memory. If F describes the minimum feature size, then the density is one bit for each 4 F2 units of surface area. This is normally described as a density of 4 F2/bit.
The performance of flash memory transistors needs to increase as the performance of computer systems increases. To accomplish a performance increase, the transistors can be reduced in size. This has the effect of increased speed with decreased power requirements.
However, a problem with decreased flash memory size is that flash memory cell technologies have some scaling limitations due to the high voltage requirements for program and erase operations. As MOSFETs are scaled to deep sub-micron dimensions, it becomes more difficult to maintain an acceptable aspect ratio. Not only is the gate oxide thickness scaled to less than 10 nm as the channel length becomes sub-micron but the depletion region width and junction depth must be scaled to smaller dimensions.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a higher performance flash memory transistor.
USPTO Backgrounds
USPTO Backgrounds