1. Field of the Invention
The present invention relates to a semiconductor memory and more particularly to a semiconductor memory using a phase-change material.
2. Description of the Related Art
Conventionally, a phase-change memory using a phase-change material has been known. A memory element of a phase-change memory is formed of a chalcogenide material. The resistance of the chalcogenide material represents memory information. FIG. 1 illustrates the circuit diagram of a memory cell. A memory cell includes a variable resistor of a chalcogenide layer and an access transistor. In a memory cell illustrated in FIG. 1A, one end of a resistor is connected to a bit line. The other end of the resistor is connected to a drain of a transistor. A source of the transistor is connected to a constant potential. A gate of the transistor is connected to a word line. In a memory cell illustrated in FIG. 1B, a resistor and a transistor between a bit line and a constant potential are disposed in reverse. This memory cell can operate in the same way as the memory cell illustrated in FIG. 1A.
Reading in these memory cells is performed by reading out an electric current passing through a bit line when an access transistor connected to a selected word line is brought into conduction. “1” or “0” is determined by the electric current that passes through the bit line and varies with the resistance of a chalcogenide layer. Writing of memory information is performed when an access transistor connected to a selected word line is brought into conduction and the resulting Joule heat of the electric current passing through a chalcogenide layer changes the crystalline state of the chalcogenide layer.
Writing of memory information onto the chalcogenide layer is performed by the following two operations. In one operation referred to as “reset”, the chalcogenide layer is once melted by the supply of sufficient Joule heat and is then quenched to maintain an amorphous state of a high-resistivity layer. In the other operation referred to as “set”, a slightly smaller amount of Joule heat is supplied to cool the chalcogenide layer slowly and thereby a crystalline state having a face-centered cubic structure of low resistance is formed. The amount of supplied heat and the cooling rate are controlled by the current value and the length (time) of a pulse applied to the chalcogenide layer. Thus, different crystal structures of the chalcogenide layer and variations in resistance allow reading and writing of the memory.
The following prior documents disclose these phase-change memories. In Japanese Unexamined Patent Application Publication No. 04-045585, a chalcogenide layer formed on a lower heater electrode is patterned by an upper electrode to form a chalcogenide layer having a small diameter. Japanese Unexamined Patent Application Publication No. 2004-031953 discloses stacked phase-change memories. Japanese Unexamined Patent Application Publication No. 2004-153047 discloses a memory element including a chalcogenide layer between a lower heater electrode and an upper electrode both formed on the same plane. These documents disclose a structure in which an electric current from an electrode is converged into a memory element to improve the current efficiency during writing. Japanese Unexamined Patent Application Publication No. 2004-289029 discloses a phase-change memory that includes a memory element having a chalcogenide layer of a different composition and is thereby operable at elevated temperatures.
USPTO Backgrounds
USPTO Backgrounds