1. Field of the Invention
The present invention relates to read only memories (ROMs) and to ROM compilers.
2. State of the Art
A ROM is typically realized as transistors arranged in accordance with a Word-Line/Bit-Line organization. A timing unit, based on a ROM clock signal, generates pulses that control sequencing of the read operation. For example, the timing unit generates pulses to disable/enable bit line precharge, word line selection to enable/disable the sense amplifier and, finally, to register the read value. The proper timing of the foregoing signals depends on various factors including the process technology employed, the size and organization of the ROM, etc. Calibration of the duration of these internal pulses is key to optimizing the read cycle time and the power consumption of the ROM.
It is desirable for the realization of the timing unit to remain the same despite variations in the foregoing particulars. To achieve this end, self-timed synchronous ROMs have been developed. A self-timed synchronous ROM is described, for example, in Silburt et al. A 200 MHz 0.8 um BiCMOS Modular Memory Family of DRAM and Multi-port SRAM, IEEE 1992 Custom Integrated Circuits Conference, incorporated herein by reference.
In a self-timed synchronous ROM, critical path timing is physically modeled within the ROM itself. In general, prior timing unit systems mimic the ROM critical path (the discharge bit line) using "dummy paths", namely a dummy word line and a dummy bit line. These dummy paths model the worst case path delay of a read operation for a given ROM configuration. The worst case occurs in the instance of a word line and a bit line having all the transistors programmed. In some ROMs, only a dummy word line is used. Delay due to the discharge of the bit line is modeled using a programmable delay dependant on the number of word lines.
Referring more particularly to FIG. 1, a four-bit by eight-word ROM is shown, with word lines running in the X direction and bit lines running in the Y direction. (The memory may be organized into right and left memory maps, in which case the word lines may extend also toward the right for a right memory map, not shown.) Each intersection of a word line and a bit line defines one bit of information. If a transistor is formed at an intersection, then that bit is programmed with a logic zero value, for example. If no transistor is formed, then that bit is programmed with a logic one value. A dummy word line 101 is provided having loads at each intersection, thereby modeling the delay of a word line having a transistor at each intersection. Bit lines are paired and input to respective output circuitry blocks 103, each block including a multiplexer, a sense amplifier and an output buffer. A control unit 105 receives a clock signal, an X address and a Y address. The Y address is applied to a Y predecoder 107 that controls the multiplexers to select either bit line zero or bit line one. The X address is applied to an X predecoder 109. Output signals from the X predecoder are applied to respective X post decoders 111 in response to which exactly one of the post decoders is enabled to activate a particular word line.
The arrangement and operation of a conventional self-timed memory control circuit may be better understood with reference to FIGS. 2 and 3. The control circuit may be realized using a D flip-flop (Dff), for example. The Dff has its input tied high and is clocked by a clock signal from the memories timing unit. The Q output signal is coupled through dummy circuity that loads the output and through an inverter back to a (Clear) input of the Dff.
The following sequence of operations is performed:
1. In this case, a positive edge on the (Clk) Clock signal starts a read cycle operation. PA1 2. This positive edge activates a positive pulse on the (Q) output signal of the Dff. This activates for example the sense amplifier, enabling the correct Word Line to be selected, opening the output latches, etc. PA1 3. This pulse is then delayed using the dummy circuitry to reset itself (Clear). At this stage the read has been done, but the read cycle time is not completed. PA1 4. The reset mode is activated on the Dff, so the positive pulse on (Q) returns to low, disabling the sense amps and activating the bit line pre-charge for example. But at this stage the cycle time is not completed since a new positive edge on the clock could not start a new read cycle as the Dff still has its reset input activated. PA1 5. The reset is deactivated so a new read operation can start. This is generally counted as the cycle time (Tcyc). It should be noted that the cycle time is not dependant on the clock duty cycle.
The foregoing worst case approach, although it simplifies ROM design, unnecessarily limits ROM performance.
USPTO Backgrounds
USPTO Backgrounds