1. Field of the Invention
The present invention relates to a semiconductor device and more specifically to a semiconductor device ensuring the planarity of an interlayer insulating film and preventing displacement of an interconnection thereby achieving a high degree of integration.
2. Description of the Background Art
As one example of conventional semiconductor devices, a semiconductor device including an MOS transistor will be described with reference to the drawings. Referring to FIG. 47, a plurality of gate electrode portions 55 including a polycrystalline silicon film 55a, a tungsten silicide film 55b and a silicon oxide film 55c are formed on the surface of a silicon semiconductor substrate 51 with a gate insulating film 54 interposed therebetween. A pair of impurity diffusion layers 56a, 56b are formed at the surface of silicon semiconductor substrate 51 with one gate electrode portion 55 sandwiched therebetween. A pair of impurity diffusion layers 56c, 56d are formed at the surface of silicon semiconductor substrate 51 with another gate electrode portion 55 sandwiched therebetween. A sidewall insulating film 57 is formed on the both side surfaces of gate electrode portion 55. Gate electrode portion 55 and a pair of impurity diffusion layers 56a, 56b constitute one MOS transistor. Further, gate electrode portion 55 and a pair of impurity diffusion layers 56c, 56d constitute another MOS transistor. Gate electrode portion 55 of each MOS transistor serves as a first interconnection layer. MOS transistors are electrically insulated from one another by a separating oxide film 53 that is formed in an element separating trench 52 at the surface of silicon semiconductor substrate 51.
A silicon oxide film 58 is formed on silicon semiconductor substrate 51 to cover gate electrode portion 55. On silicon oxide film 58, a silicon oxide film doped with boron and phosphorous, that is, a BPSG (Boro-Phospho-Silicate-Glass) film 59 is formed. A silicon oxide film 60 is formed on BPSG film 59. A plurality of second interconnection layers 62 including a polycrystalline silicon film 62a, a tungsten silicide film 62b and a silicon oxide film 62c are formed on silicon oxide film 60. One second interconnection layer 62 is electrically connected to gate electrode portion 55 as a first interconnection layer by a polycrystalline silicon film filled in contact hole 61a that is formed in BPSG film 59 and silicon oxide films 60, 58. Another second interconnection layer 62 is electrically connected to impurity diffusion layer 56b by a polycrystalline silicon film filled in a contact hole 61b that is formed in BPSG film 59 and silicon oxide films 60, 58. A silicon oxide film 63 is formed on silicon oxide film 60 to cover second interconnection layer 62. A BPSG film 64 is also formed on silicon oxide film 63. A plurality of third interconnection layers 67 are formed on BPSG film 64.
Third interconnection layers 67 are electrically connected to gate electrode portion 55 and impurity diffusion layers 56c, 56d by plugs 66a, 66b, 66c e.g. of tungsten filled in contact holes 65a, 65b, 65c that are formed in BPSG films 59, 64 and silicon oxide films 63, 60, 58. Third interconnection layer 67 is also electrically connected to second interconnection layer 62 by a plug 66d filled in a contact hole 65d that is formed in BPSG film 64 and silicon oxide film 63. The conventional semiconductor device has such a configuration.
One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 48, element separating trench 52 is formed at the surface of silicon semiconductor substrate 51 by prescribed photolithography and RIE (Reactive Ion Etching) methods. To fill element separating trench 52, a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is then formed on silicon semiconductor substrate 51 by the CVD method. The silicon oxide film is polished by the CMP (Chemical Mechanical Polishing) method to form separating oxide film 53 in element separating trench 52. Gate oxide film 54 having a film thickness of 5 to 15 nm is then formed on the surface of silicon semiconductor substrate 51 by the thermal oxidation method. On gate oxide film 54, a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed. A plurality of gate electrode portions 55 as the first interconnection layers including polycrystalline silicon film 55a, tungsten silicide film 55b and silicon oxide film 55c are formed by the prescribed photolithography and RIE methods. By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate 51 using gate electrode portion 55 as a mask, a region (not shown) of a comparatively low impurity concentration is formed.
To cover gate electrode portion 55, a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is then formed on silicon semiconductor substrate 51 by the CVD method. The silicon oxide film is etched by the RIE method to form sidewall insulating film 57 on the both side surfaces of gate electrode portion 55. By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate 51 using sidewall insulating film 57 and gate electrode portion 55 as a mask, a region (not shown) of a comparatively high impurity concentration is formed. Thus, a pair of impurity diffusion layers 56a, 56b and a pair of impurity diffusion layers 56c, 56d. are respectively formed at the surface of silicon semiconductor substrate 51 with gate electrode potions 55 sandwiched therebetween. Thereafter, comparatively thin silicon oxide film 58 is formed on silicon semiconductor substrate 51 by the CVD method to cover gate electrode portion 55. BPSG film 59 is formed on silicon oxide film 58 by the CVD method.
Referring to FIG. 49, BPSG film 59 is heated at a temperature of approximately 850.degree. C. to locally planarize the surface of BPSG film 59. In other words, BPSG film 59 is reflowed. Locally planarizeed BPSG film 59 is etched by the RIE method or a hydrofluoric acid solution to make BPSG film 59 thinner.
Referring to FIG. 50, comparatively thin silicon oxide film 60 is formed on BPSG film 59 by the CVD method. Then, contact hole 61a exposing the surface of tungsten silicide film 55b of gate electrode portion 55 and contact hole 61b exposing the surface of impurity diffusion layer 56b are formed in BPSG film 59 and silicon oxide films 60, 58 by the prescribed photolithography and RIE methods. A polycrystalline silicon film, a tungsten silicide film and a silicon oxide film (they are not shown) are then formed on silicon oxide film 60 by the CVD method. Second interconnection layer 62 including polycrystalline silicon film 62a, tungsten silicide film 62b and silicon oxide film 62c is then formed by the prescribed photolithography and RIE methods.
Referring to FIG. 51, comparatively thin silicon oxide film 63 is formed on silicon oxide film 60 by the CVD method to cover second interconnection layer 62. BPSG film 64 is then formed on silicon oxide film 63 by the CVD method.
Referring to FIG. 52, BPSG film 64 is heated at a temperature of approximately 800.degree. C. to locally planarize the surface of BPSG film 64. Thereafter, BPSG film 64 is etched by the RIE method or a hydrofluoric acid solution , if necessary, to further planalize the surface of BPSG film 64.
Referring to FIG. 53, contact hole 65a exposing the surface of tungsten silicide film 55b of gate electrode portion 55, contact holes 65b, 65c exposing the surfaces of impurity diffusion layers 56c, 56d, and contact hole 65d exposing the surface of tungsten silicide film 62b of second interconnection layer 62 are formed in BPSG film 64 by the prescribed photolithography and RIE methods. Thereafter, an impurity of a prescribed conductive type is implanted in contact holes 65a, 65b, 65c, 65d. The impurity is activated by heating at a temperature of 750.degree. C. lower than the heating temperature for locally planarizing BPSG film 64.
Then, a tungsten thin film (not shown) is formed on BPSG film 64 by the CVD method using WF.sub.6, for example, as a material. The tungsten thin film is etched by the RIE method to form tungsten plugs (not shown) in contact holes 65a, 65b, 65c, 65d. An aluminum copper alloy film (not shown) is formed on BPSG film 64 by the sputtering method. Then, the third interconnection layers electrically connected to gate electrode portion 55, impurity diffusion layers 56c, 56d and the like are formed by the prescribed photolithography and RIE methods to complete the semiconductor device shown in FIG. 47. The conventional semiconductor device is manufactured as described above.
As LSIs miniaturize in recent years, processing of contact holes 61a, 61b, 65a to 65d, second interconnection layer 62 and third interconnection layer 67 with high dimensional precision is becoming difficult. Especially, in order to ensure prescribed dimensional precision in a lateral direction, the NA value (Numerical Aperture) of a lens used for an exposing device is set at a higher value to improve resolution in photolithography. When the planarity of a film surface to be applied with a resist is poor, however, halation makes it difficult to form a pattern that is highly dimensionally precise. Since the NA value of a lens is set at a higher value, it is difficult to ensure the depth of focus. In filling polycrystalline silicon, tungsten or the like in contact holes 61a, 61b, 65a to 65d that are formed in BPSG films 59, 64 and the like, the polycrystalline silicon or tungsten may be left without being etched at the step portions of BPSG films 59, 64. Therefore, more planarized surface shapes are required for BPSG film 59 serving as the base of second interconnection layer 62 and BPSG film 64 serving as the base of third interconnection layer 67.
Here, the step portions of the BPSG films are locally planalized by heating. The degree of planarization depends on the concentration of boron and phosphorous contained in the BPSG films, the heating temperature and the like, and the BPSG films are locally planarized to a greater extent as the concentration of boron and phosphorous is higher or as the temperature is higher.
When the concentration of boron and phosphorous in lower layer BPSG film 59 is made almost the same as the concentration of boron and phosphorous in upper layer BPSG film 64 so as to ensure the planarity of the base of second interconnection layer 62, lower layer BPSG film 59 is also reflowed and transformed in heating upper layer BPSG film 64. Therefore, second interconnection layer 62 formed on BPSG film 59 might be displaced as BPSG film 59 is transformed. Thus, second interconnection layer 62, for example, might come into contact with tungsten plug 66b, causing an electrical short.
In order to suppress such displacement of second interconnection layer 62, the displacement can be suppressed to approximately 1 .mu.m by setting lower the heating temperature for upper layer BPSG film 64. In order to cope with the requirement for the heating at a lower temperature as LSIs are miniaturized, however, the lower temperature of the heating for the upper layer BPSG film is approaching a limit. As the LSIs are further miniaturized, suppressing displacement of second interconnection layer 62 to approximately 0.1 .mu.m is required. Therefore, simultaneously ensuring the planarity of the base of the second interconnection layer and the like and preventing displacement of the second interconnection layer are expected to be extremely difficult in the conventional semiconductor device. As a result, easy miniaturization of LSIs is expected to be difficult.
USPTO Backgrounds
USPTO Backgrounds