Embedded single port and dual port static random access memories (SRAMs) are the key components in contemporary memory-rich Systems on a Chip (SoCs). In deep submicron technologies, read and write margins of these embedded SRAMs are degraded due to increased variations at low voltage conditions. Embedded dual port SRAMs are widely used as buffer memories in multimedia and graphical processing chips, and data caches in multi-core processors. Dual port SRAMs suffer from an extended write time when one of the ports of the SRAM array is used to perform a write operation in an SRAM cell while the second port is used to access another SRAM cell in the same row (i.e., same row addresses) or the same SRAM cell.
The extended write time can be mitigated by an active bit line equalizing circuitry (as described in Y. Ishii et al., “A 28-nm dual port SRAM macro with active bit line equalizing circuitry against write disturb issue,” in Symp. VLSI Circuits 2010 Dig. Tech. Papers, June 2010, pp. 99-100), a write-assist 8T cell (described in J. J. Wu et al., “A 45-nm Dual-port SRAM Utilizing Write-Assist cells against simultaneous access disturbances,” TCAS II, November 2012, pp. 790-994), or employing a priority row decoder and a shifted bit line access scheme (described in K. Nii et al., “Synchronous ultra-high-density 2RW dual-port-8T-SRAM with circumvention of simultaneous common-row-access,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 977-986, March 2009). All the above papers are incorporated into this application by reference. The circuit designs in Y. Ishii et al., J. J. Wu et al. and K. Nii et al. require double the hardware for the write driver circuitry and two separate “same row” address decoders for port A and port B. The circuit design with the write-assist 8T cell in J. J. Wu et al. only assist single-sided write ‘0’ in inter-port writing, and limits its influence to suppress the extended write time. While the circuit designs in Y. Ishii et al., J. J. Wu et al. support synchronous and asynchronous dual port SRAM operations, only synchronous dual port SRAM operations are possible with the circuit design in K. Nii et al.
It is therefore desirable to provide an SRAM device that supports both synchronous and asynchronous dual port SRAM operations and mitigates extended write time issues in dual port SRAMs.
USPTO Backgrounds
USPTO Backgrounds