The present invention relates generally to methods and systems for integrating a plurality of interacting cores into a single functional core assembly. More specifically, the present invention relates to a method and system for interconnecting chiplet-based cores or multiple cores into a single functional core.
The integration levels possible with today""s high density semiconductor processes have totally changed the model for intellectual property (IP) development and usage in the electronics industry. The ability to integrate millions of gates on an application specific integrated circuit (ASIC) has given rise to the System-On-Chip (SOC), or System-Level-Integration ASIC models where system houses cannot afford the development time and expense of developing their own IP for complex ASICs, and must, therefore, rely on integrating high-level functional cores together from the ASIC provider.
The task of integrating many large cores into a single SOC design involves many challenges for both the system house and the core provider from the interconnection of the cores to the functional verification and testing. Often, especially for complex cores, the core provider cannot create a single core to satisfy the requirements of all the users in all market segments. This forces the core provider to either generate and support many variations of the core, or modularize complex cores into many smaller pieces, commonly referred to as chiplets, which are then put together in various configurations to create specific variations of the core.
While the chiplet approach simplifies the core supplier maintenance task, it further complicates the core user""s (the system house""s) job, as they now have to manage more pieces and get involved with the core at a lower level than intended. The task of connecting the chiplets together into a core has been done by interconnecting all chiplet I/Os manually or with a schematic capture tool. Since there may be thousands of internal connections between chiplets inside a core, connecting the chiplets together manually or with a schematic capture tool can be an error prone process. If chiplets are interconnected manually, many errors can be introduced into the final product, such as misconnected pins and improper configurations which may violate an electrical or testing requirement. Since the high level HDL (e.g., VERILOG or VHDL) for the chiplets does not contain information about physical or interconnection requirements, it is impossible to automatically check the interconnections of the chiplets, and errors may not be discovered or corrected until the ASIC build step, losing critical design time and time to market.
The chiplets can also be interconnected by a custom configuration program created by the core provider that is specific to the chiplets. However, the flexibility in customer configuration is limited by the custom program""s algorithms. Furthermore, whenever a chiplet interface change occurs, the custom program must change accordingly.
It is an advantage of the present invention to provide an alternate approach to the prior art described above that simplifies the core user""s task of interconnecting chiplet-based cores, or multiple-cores, and automatically generates an error free high level model of the core.
It is a further advantage of the present invention to provide a configurator program tool that configures chiplet-based cores, or multiple-cores, automatically into a single functional core to meet customer specific needs and can be used on any core.
According to a broad aspect of the present invention, a method of creating a system of interconnected cores is provided, comprising the steps of: creating for each core a pin configuration structure based on a set of pin configuration rules; selecting a plurality of cores to be interconnected; accessing the pin configuration structure for the cores selected; and connecting the cores using a connectivity program based on the pin configuration structure and configuration rules for the selected cores.
The method further comprises the steps of: determining a fanout limit for each pin of the cores; and connecting the cores in a multiple fanout configuration using the connectivity program to ensure that an acceptable number of fanout connections is not exceeded. The method also comprises the steps of: determining for each pin of the cores whether the pin is part of a group of related pins; and using the connectivity program to match each group of related pins together when connecting the cores. The connectivity program is initialized by choosing a set of cores to be connected together, flagging external pins on the cores, and loading descriptive files containing the pin configuration structure and configuration rules. Upon executing the connectivity program, a high level source is generated that contains information about the system of interconnected cores created. A logical verification is then made based on the source.
According to another broad aspect of the present invention, a computer system is provided that has a central processing unit; a bus; a computer system memory, and a configurator tool stored in the computer system memory. The computer system memory is connected to the central processing unit via the bus. The configurator tool is executable on the central processing unit and is operable to create a system of interconnected cores based on a pin configuration structure and a set of configuration rules for the cores. The configurator tool is also operable to perform the other steps of the method described above.
According to still another aspect of the present invention, a computer-readable medium is provided that has computer-executable instructions for creating a system of interconnected cores. The instructions on the computer-readable medium are executable to perform the steps of: accessing a pin configuration structure and a set of configuration rules for the cores; and connecting the cores together based on the pin configuration structure and the configuration rules. The instructions on the computer-readable medium are further executable to perform the other steps of the method described above.
Numerous other advantages of the present invention will be apparent to those skilled in this art from the following description wherein there is shown and described a preferred embodiment of the present invention, simply by way of illustration of one of the modes best suited to carry out the invention. As will be realized, the invention is capable of other different embodiments, and its several details are capable of modification in various obvious aspects without departing from the invention. Accordingly, the drawings and description should be regarded as illustrative in nature and not restrictive.
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