The present invention relates generally to synchronous memory systems, and in particular to a memory interface that reduces overall memory system power consumption by incorporating functionality from SDRAM components.
Synchronous Dynamic Random Access Memory (SDRAM) components are widely deployed as the technology implementing main memory storage in a wide variety of computing systems, including portable devices. One or more memory controllers, such as a microprocessor, Digital Signal Processor (DSP), Direct Memory Access (DMA) engine, or the like, directs memory read and write requests to, typically, a plurality of SDRAM components. To reduce system bus loading, accommodate different bus architectures, provide configurability, improve performance by buffering data, offload refresh overhead and/or error correction processing from a processor, and for other reasons, a memory interface is often interposed between the memory controller(s) the SDRAM components.
FIG. 1 depicts a representative synchronous memory system, denoted generally by the numeral 8. The memory system 8 includes a memory controller 10 and a plurality of SDRAM components 12. Interposed between the memory controller 10 and the SDRAM components 12 is a memory interface 14. The memory interface 14 receives memory access requests from one or more memory controllers 10 across a system bus 16, which may for example include a system clock signal, a plurality of command signals, and address and data buses. The memory interface 14 is operative to perform read and write (and refresh) operations on the SDRAM components 12 across a memory bus 18. The memory bus 18 may include, as depicted in FIG. 1, a memory clock signal, an integrated control and address bus, a data bus (DQ), and a plurality of data strobe (DQS) signals. In general, the system bus 16 and the memory bus 18 may differ in organization, protocol, and/or timing. For example, the memory bus 18 may be matched to the Input/Output (I/O) of the SDRAM components 12, while the system bus 16 may be matched to a particular memory controller 10 or may otherwise be optimized for the data transfer constraints of a particular system design. Thus, one function of the memory interface 14 is to “bridge” the system bus 16 and memory bus 18. In some implementations, the memory interface 14 may additionally buffer data, further decoupling the two buses 16, 18.
In some embodiments, the memory interface 14 and plurality of SDRAM components 12 may be physically and electrically associated as a module 20. The Fully-Buffered Dual In-line Memory Module (FB-DIMM) is one example of such a memory module 20. Within the FB-DIMM, the Advanced Memory Buffer (AMB) is an example of a memory interface 14. The memory interface 14 and SDRAM components 12 may also be integrated into a Multi-Chip Package (MCP), wherein a plurality of integrated circuit (IC) die are included in one IC package. Of course, the memory system 8 may also be implemented as discrete components. No matter how they are packaged, the number of SDRAM components 12 may range from a few to a few hundred.
As further depicted in FIG. 1, the memory controller 10 includes a clock generation circuit 11 generating and distributing a system clock signal. In other embodiments, both the memory controller 10 and the memory interface 14 may receive a system clock signal from a system clock generator external to the memory controller 10. Data transfers across the system bus 16 are synchronous to the system clock signal.
The memory interface 14 includes a clock driver circuit 22 generating a memory clock signal (MEM CLK), which is distributed to all SDRAM components 12. Each SDRAM component 12 includes a Delay Locked Loop (DLL) 24 generating a read clock signal (R-CLK). A data I/O circuit 26 uses the read clock signal to synchronize data on the DQ bus and DQS strobe signals to memory clock signal edges in burst memory transfers.
FIG. 2 depicts read burst timing on the memory bus 18 for the memory system 8 depicted in FIG. 1. The memory interface 14 places a read command on the bus 18, via an encoding of command signals, and provides a read address. Following a programmed CAS latency (CL), an addressed SDRAM component 12 transfers four DQ-bus-width words of data (D0-D3) in a burst transfer, the transitions of which, and those of the DQS strobes (not shown), are aligned to memory clock signal edges. The burst read data are received by an I/O circuit 28 in the memory interface 14 (FIG. 1), and may be buffered or immediately passed on to the memory controller 10.
Each SDRAM component 12 also includes a Voltage Generator circuit 30, which generates a plurality of different voltage levels for use by circuits internal to the SDRAM component 12. For example, the DRAM array, sense amps, I/O driver circuits, digital control logic, and/or other circuits may all require different operating voltages. The generation and distribution of these different voltages is an internal function of the SDRAM component 12, and is generally transparent to the system designer.
A memory system 8—or module 20, if so organized—may include from a few to a few hundred SDRAM components 12, depending on their density and speed (and hence cost), and various system design constraints, such as available space, power, heat dissipation capability, weight limitation, and the like. One design constraint of particular criticality to portable electronic devices is power consumption. Portable devices are typically powered by batteries, which are either rechargeable or replaceable. The desire for long operative use periods between battery recharge cycles (or replacements), small size, low weight, and a low heat dissipation capacity due to the lack of cooling fans, combine to place a high cost on power consumption in portable electronic devices. As the number of SDRAM components 12 in a particular design increases, even relatively small per-SDRAM power savings can add up to a significant overall system-wide power savings.
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USPTO Backgrounds