1. Field of the Invention
This invention relates to a weak signal detecting circuit, and more particularly to a weak signal detecting circuit which consumes a very small amount of power in the detection of a weak signal from a memory cell of a semiconductor memory and, moreover, operates with high sensitivity, at high speed and with stability.
2. Description of the Prior Art
Generally, a typical circuit of a one-transistor type IC memory employing MIS transistors, that is, a memory having memory cells each composed of a MIS transistor and a capacitance, is such as shown in FIG. 1.
FIG. 1 shows one part of a circuit of a semiconductor memory manufactured and sold by Intel Corporation of the United States under the model No. i-2107B, illustrating the connections between a flip-flop type sensing circuit composed of MIS transistors Q.sub.1 and Q.sub.2 and memory cells of 2m bits. Reference characters W.sub.1, W.sub.2, . . . and W.sub.2m indicate word lines. Each memory cell M comprises a MIS transistor connected to each word line and a capacitance C.sub.S connected to the MIS transistor. A read operation in the above circuit may be summarized as follows: At first, bit lines B.sub.1 and B.sub.2 are precharged to a high level and a signal is applied to a predetermined word line to transfer information from the memory cell associated therewith to the bit line having connected thereto the memory cell. Within, a clock signal .phi..sub.D is applied to the gate of a transistor Q.sub.3 to actuate the flip-flop type sensing circuit to amplify a weak signal from the memory cell, thus completing the read operation. To ensure a stable operation, a dummy memory cell is usually connected as an additional circuit to each bit line to provide a reference level for the memory cell information stored in the memory cells.
In the conventional circuit shown in FIG. 1, the bit lines B.sub.1 and B.sub.2 are charged up by separate precharge circuits to an initial value which is a level intermediate between the power source voltage V.sub.DD and the ground and a signal from a selected one of the memory cells is applied to the bit line associated therewith. Thereafter, a clock signal .phi..sub.D is applied to transistors Q.sub.6 and Q.sub.7 to turn them on, amplifying the signal from the memory cell. Since the bit lines B.sub.1 and B.sub.2 generally have large parasitic capacitances C.sub.B1 and C.sub.B2, the transistors Q.sub.6 and Q.sub.7 are required to have a large gm for rapidly amplifying the signal applied from the selected memory cell to the bit line. Further, when the transistors Q.sub.6 and Q.sub.7 are turned on, a current path is formed between the power source and the ground through either one of the transistors Q.sub.6 and Q.sub.7, either one of the transistors Q.sub.1 and Q.sub.2 and the transistor Q.sub.3 to flow an extremely large current improper for an IC memory. This inevitably results in large power consumption and large heat generation, too.
Further, as a result of the present inventors' studies of the conventional circuit of FIG. 1, it has been found that when the load transistors Q.sub.6 and Q.sub.7 are assumed to be left out, the detection sensitivity is dependent upon the gain constants of the transistors Q.sub.1 and Q.sub.2 and the load capacitance of the sensing circuit, and that the following relationship equation holds: ##EQU1## where C.sub.0 is a designed central value of the parasitic capacitances C.sub.B1 and C.sub.B2 ; .beta..sub.0 is a designed central value of the gain constant .beta. (that is, .beta..sub.1 and .beta..sub.2) of the transistors Q.sub.1 and Q.sub.2 ; .DELTA.C.sub.B1 and .DELTA.C.sub.B2 are amounts of deviation from C.sub.0 ; and .DELTA..beta..sub.1 and .DELTA..beta..sub.2 are amounts of deviation from .beta..sub.0. In the equation (1), the sensitivity is defined as the "detectable minimum signal level." Accordingly, if this value is small, it represents a high sensitivity. In the conventional circuit depicted in FIG. 1, since the load capacitance during the detecting operation includes all the capacitances in the bit lines, C.sub.0 in the equation (1) becomes large and high sensitivity is difficult to obtain.
The above discussion has been made on the assumption that the load transistors Q.sub.6 and Q.sub.7 do not exist. However, where the transistors Q.sub.6 and Q.sub.7 are turned on and added to the components of the circuit during the detecting operation, the lower the impedances of these transistors, the more the sensitivity expressed by the equation (1) decreases. In other words, it further reduces the high sensitivity, as mentioned above.
In U.S. Pat. No. 3,879,621, there is disclosed the technique for separating the bit lines and the sensing circuit from each other, as required, by MIS transistors inserted therebetween. However, the invention of this United States patent is remarkedly different from the circuit of the present invention in that transistors for the power supply are disposed on the inside of the abovesaid separation transistors. Also the circuit of the referenced United States patent is of the type requiring no rewrite in the selected memory cell by the sensing circuit, and in that load transistors (identified by QP.sub.1 and QP.sub.2 in the specification of the above patent) of low impedance are turned on to greatly lower the detection sensitivity at the beginning of operation. These differences will become more apparent from the following detailed description of this invention.
USPTO Backgrounds
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