The present invention relates to a semiconductor storage device, and in particular to a semiconductor storage device including a plurality of memory areas.
In recent years, capacities of semiconductor storage devices such as DRAMs (Dynamic Random Access Memories) are becoming larger and larger. As a result, it is necessary to increase the integration densities of memory cell arrays in order to increase the capacities and reduce the costs even further.
Japanese Unexamined Patent Application Publication No. 10-303389 discloses a technique for effectively increasing the current capacity or the number of power-supply lines or signal lines, and thereby for improving the performance of peripheral circuits and/or the flexibility of wiring layout design. Japanese Unexamined Patent Application Publication No. 2001-210100 discloses a technique relating to a semiconductor storage device capable of detecting a failure in a dummy cell or on a dummy word line, and thereby improving the productivity.
USPTO Backgrounds
USPTO Backgrounds