The present invention relates generally to a process flow for processing semiconductor wafers, and, more particularly, to a process flow using a combination of plasma jet etching, high-gloss etching and Plasma Assisted Chemical Etching (PACE).
Semiconductor wafers used as starting materials for the fabrication of integrated circuits must meet certain surface flatness requirements. Such wafers must be an particularly flat in order to print circuits on them (or on layers deposited upon them) by, for example, an electron beam-lithographic or photolithographic process. Wafer flatness in the focal point of the electron beam delineator or optical printer is important for uniform imaging in the electron beam-lithographic and photolithographic processes. The flatness of the wafer surface directly impacts device line width capability, process latitude, yield and throughput. The continuing reduction in device geometry and increasingly stringent device fabrication specifications are forcing manufacturers of semiconductor wafers to prepare increasingly flatter wafers.
Wafers can be characterized for flatness in terms of a global flatness variation parameter (for example, "GBIR") or in terms of a local site flatness variation parameter (for example, Site Best Fit Reference Plane ("SFQR") or Site Total Indicated Reading, Back Reference Center Focus ("SBIR")). A more detailed discussion of the characterization of wafer flatness can be found in F. Shimura, Semiconductor Silicon Crystal Technology (Academic Press 1989), pp. 191-195.
GBIR, frequently used to measure global flatness variation, is the difference between the maximum and minimum thicknesses of the wafer. GBIR in the wafer is an important indicator of the quality of the polish of the wafer. SBIR, frequently used to measure local site flatness variation, is the sum of the maximum positive and negative deviations of the surface in a small area of the wafer from a theoretical reference plane which is approximately parallel to the back surface of the wafer and intersects the front surface at the center of the local site. SFQR, which is becoming more widely used to measure local site flatness variation, is the sum of the maximum positive and negative deviations of the surface in a small area of the wafer with reference to a best fit reference plane.
Semiconductor wafers are generally prepared from a single crystal ingot, such as a silicon ingot, which is trimmed and ground to have one or more flats for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers which are each subjected to a number of processing operations to flatten the wafer, remove damage, and to create a highly reflective surface. Typically, the peripheral edge of each wafer is rounded to reduce the risk of wafer damage during further processing. In a conventional process flow, each wafer is then lapped to improve thickness uniformity, to reduce saw damage and to reduce waviness in the wafer. The wafer may also be subjected to a rough grinding operation to remove damage caused by slicing. The wafer is then etched to smooth the surfaces and rough polished to polish and flatten the surfaces before undergoing final polishing and cleaning processes.
The conventional process flows are limited in the degree of wafer flatness and in the yield of acceptable wafers. This is due in part to the fact that the rough polishing operation often does not satisfactorily flatten the wafer. A conventionally rough polished wafer ideally has a SBIR of about 0.4 microns for any 20 mm.times.20 mm local site and a SFQR of about 0.18 microns for any 25 mm.times.32 mm local site (as disclosed in The National Technology Roadmap for Semiconductors: Technology Needs, published by the Semiconductor Industry Association, p.64 (1997 edition). Such values, however, depend upon actual process conditions and often are significantly larger than 0.4 microns. Indeed, only a small percentage of wafers in a conventionally processed group of wafers meets the above ideal flatness specification. The wafers that do not meet this flatness specification are often rejected. Moreover, there are certain disadvantages of the lapping, grinding and rough polishing operations which increase the cost of processing semiconductor wafers. Conventional lapping machines are not automated, which increases the manual labor involved and the time required for the operations. Polishing is a slow process and requires a relatively long time to remove material from the wafer. Thus, more polishing machines are needed to increase the volume or throughput of wafers. Expensive consumables (e.g., slurries, pads) are used in each lapping and rough polishing operation. While rough grinding has certain advantages over lapping, rough grinding is not completely satisfactory because it generally causes deeper crystal lattice damage than lapping, resulting in a lesser quality wafer and an increased risk of fracturing of the wafer. Additionally, low-frequency flatness parameters such as waviness are not efficiently improved by grinding alone. Therefore, there is a need for a new process flow capable of improving the flatness of a semiconductor wafer, the yield of a given production run, and the cost efficiency of the process flow.
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