1. Field of the Invention
The present invention relates to transmission and reception interfaces and especially to the data transmission and data synchronization between sender and receiver, such as, for example, between integrated circuits.
2. Description of Prior Art
The need for fast transmission with simultaneous data synchronization is high, especially in the field of working memories and in particular in the interface between the working memory and the requesting controller. Examples of memory technologies in which synchronization takes place in data transmission are, for example, SDRAM technology (SDRAM=Synchronous Dynamic Random Access Memory) and DDR SDRAM technology (DDR SDRAM=Double Data Rate Synchronous Dynamic Random Access Memory). It is common to all those technologies that in addition to the actual data, such as, for example, read or write data, a clock signal and/or strobe signal is transmitted to obtain synchronization between the controller and the memory chip and vice versa. DDR technology essentially differs from SDRAM technology in that sampling the data takes place at both the rising and the falling edge of the strobe or the clock, respectively.
In the interface between a DDR chip and a controller and vice versa, apart from data, a differential clock signal and a source-synchronous strobe or signal, respectively, are transmitted, of which the latter must be transformed into an internal clock signal with a phase shift of 90° by means of DLL. An example of a possible solution for data transmission between a sender 900 and a receiver 902 is shown in FIG. 5. The interface arrangement illustrated in FIG. 5 concerns the case of an interface between a controller 900 and a DDR SDRAM 902, which are connected to each other via four data lines 904, 906, 908 and 910 DQ0-DQ3 and a strobe signal line 912 DQS. Internally, the receiver 902 consists of a plurality of receiver units or differential amplifiers, respectively, 914, 916, 918, 920 and 922, of which a respective input, in this case the non-inverting input, is connected to a line of the lines 904 to 912 and the other input is connected to a reference voltage 924. The reference voltage 924 can be transmitted from the sender 900 to the receiver 902 as an additional signal, produced at a separate voltage generator or derived from a supply voltage at the receiver.
For synchronizing the data transmission between the sender 900 and the receiver 902, the sender 900 controls the strobe signal DQS in such a way that it comprises a signal transition, i.e. a reference voltage level transition, in the middle of each data cycle. The receiver 902 monitors the line 912 DQS upon a transition of the strobe signal DQS. When the transition on the line DQS 912 is detected, the receiver considers the data at the output of each receiver unit 916 to 922 connected to the data lines 904 to 910 as valid and samples it.
A disadvantage in the interfaces of the DDR and the SDRAM type is that, by the separation of the data lines from the clock signal lines the lines participating in the data transmission comprise different electrical characteristics and in particular different kinds of loads, which may lead to an impediment of synchronism and thus to a restriction of the transmission speed. It is of especial disadvantage for the interface of the DDR type illustrated in FIG. 5 that, at the transmission side end of the interface, a circuit, such as for example a DDL (DDL=Delay Locked Loop) (not shown) must be present, which must produce a delay of exactly one fourth of the clock period, and that a stable reference direct voltage VREF must be provided. Due to the fact that in SDRAM technology no edge-controlled sampling is performed, the data transmission rate in this interface technology is lower and restricted to about 150 MHz for longer busses. A further disadvantage of these interfaces is that all the lines can switch from 0 to 1 or from 1 to 0 and thus the supply system must be designed for higher peak currents. In addition, in these interfaces, the signal swing is only related to VREF and thus only half as large.
In the U.S. Pat. Nos. 6,151,648 and 6,160,423, issued to Jazio, Inc., an interface technology is described in which two fixed lines are used to transmit two source-synchronous voltage and timing reference signals apart from data. These signals SSVTR and /SSVTR (SSVTR=Source Synchronous Voltage and Timing Reference) are operated with levels opposite to each other and change their level every time valid data is driven on the data lines. The data is sampled by the receiver at times shortly following the times at which the signals SSVTR and /SSVTR change their levels. For sampling the data on the data lines, each data line is, on the receiving side, connected to a first input of two comparators, the second input of which is connected to the signal SSVTR or /SSVTR, respectively. Each receiver unit of a data line consisting of the two comparators thus produces two comparison signals at the outputs of the two comparators. Which comparison signal of the two comparison signals is taken for sampling depends on whether the signal level on the data line has changed between two subsequent samples or SSVTR and /SSVTR transitions, respectively, or not. In the change of the signal level on the data line, the output signal of that comparator is maintained, the output signal of which has been used for sampling the last time. Otherwise, the output signal of the respective other comparator is used for sampling. In this manner a high level difference at the inputs of the comparator is obtained in each sample, the output signal of which is used for sampling.
As in the interfaces of the DDR SDRAM type and the SDRAM type, however, a disadvantage of the interfaces according to the U.S. patents mentioned above is that the lines taking part in the transmission comprise considerably different electrical kinds of loads, i.e. the data lines are connected to fewer comparators than the source-synchronous voltage and timing reference signals.
USPTO Backgrounds
USPTO Backgrounds