For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor. FIG. 1 illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device.
Referring to FIG. 1, semiconductor device 100 includes a SONOS gate stack 104 including a conventional ONO portion 106 formed over a silicon substrate 102. Semiconductor device 100 further includes source and drain regions 110 on either side of SONOS gate stack 104 to define a channel region 112. SONOS gate stack 104 includes a poly-silicon gate layer 108 formed above and in contact with ONO portion 106. Poly-silicon gate layer 108 is electrically isolated from silicon substrate 102 by ONO portion 106. ONO portion 106 typically includes a tunnel oxide layer 106A, a nitride or oxy-nitride charge-trapping layer 106B, and a top oxide layer 106C overlying nitride or oxy-nitride layer 106B.
One problem with conventional SONOS transistors is the poor data retention in the nitride or oxy-nitride layer 106B that limits semiconductor device 100 lifetime and its use in several applications due to leakage current through the layer. One attempt to address this problem focused on the use of silicon-rich SONOS layers, which enable a large initial separation between program and erase voltages at the beginning of life but result a rapid deterioration of charge storing ability. Another attempt focused on oxygen-rich layers, which enable a reduced rate of deterioration of charge storing ability, but also reduce the initial separation between program and erase voltages. The effect of both of these approaches on data retention over time may be shown graphically. FIGS. 2 and 3 are plots of Threshold Voltage (V) as a function of Retention Time (Sec) for conventional nonvolatile charge trap memory devices.
Referring to FIG. 2, rapid deterioration of charge storing ability for a silicon-rich layer is indicated by the convergence of the programming threshold voltage (VTP) 202 and erase threshold voltage (VTE) 204 to a specified minimum 206. Referring to FIG. 3, a reduced separation between VTP 302 and VTE 304 is obtained for an oxygen-rich layer. As indicated by line 306, the overall useful lifetime of device is not appreciably extended by this approach.
USPTO Backgrounds
USPTO Backgrounds