SerDes devices are frequently used in communication networks in which an interface must be provided between parallel bus-connected devices and high-speed serial communication networks. Conventional SerDes devices typically utilize Voltage Controlled Delay Locked Loops (VCDLs) and/or interpolators to lock the frequency and phase of the device to an incoming serial data stream. With current testing techniques, the receive functionality of the SerDes device is not fully tested because the incoming serial data is synchronous to the reference clock utilized in the VCDL. The incoming serial data is typically generated by the SerDes device itself (e.g., in a serial loopback mode) or by an external automated test equipment (ATE) device. In addition, there is no asynchronous clock available for testing using the external test equipment. As a result, conventional techniques test the receive functionality of SerDes devices only for a phase that is locked to the synchronous serial data.
Thus, conventional testing techniques are insufficient. Such synchronous testing does not adequately test SerDes devices, because not all possible delay combinations are tested. The SerDes devices are not tested fully to determine whether the devices accurately lock to asynchronous incoming data, for both frequency and phase.
U.S. patent application Ser. No. 11/181,286, entitled “Pseudo Asynchronous Serializer Deserializer (SerDes) Testing,” discloses techniques for testing the receive path of a SerDes device. While the disclosed testing techniques ensure that a SerDes device accurately locks to asynchronous incoming data, for both frequency and phase, they can only be applied to SerDes devices that are based on a VCDL.
Another known technique (discussed further below in conjunction with FIG. 1) aligns the phases of an arbitrary transmit write clock (TWC) and a transmit byte clock (XCK) having the same frequency. When these two clocks TWC, XCK are phase aligned, the transmit (TX) parallel data can be passed directly from the TX data source operating using the TWC clock to the serializer using an internal bit clock and lower frequency derivatives down to the byte rate clock (XCK). This arrangement eliminates the need for a transmit first-in-first-out (FIFO) buffer between the two clock domains and thus reduces serializer latency.
A need therefore exists for improved techniques for asynchronous testing of the receive path of SerDes devices.
USPTO Backgrounds
USPTO Backgrounds