1. Field of the Invention
This invention relates to processors, and more particularly, to techniques for handling data errors within a processor.
2. Description of the Related Art
As semiconductor feature sizes shrink, processor data elements based on such features (e.g., random access memory (RAM) bit cells) become increasingly susceptible to transient or permanent errors. For example, environmental radiation such as cosmic rays or stray electromagnetic fields may couple sufficient energy to a data element to temporarily alter a value being stored or transmitted by the element. Further, electrostatic discharge or manufacturing flaws may cause a data element to permanently malfunction.
Although some such data errors may not impact operation of a system (for example, if they occur in a line of a data cache that is unallocated), in other instances, such errors may result in unstable or incorrect system operation, data loss, or other negative consequences. Consequently, critical data structures within a processor or processor core may be protected against undetected errors through the use of error detection and/or correction schemes. Detected errors may then be handled, e.g., by system software executing on the processor or processor core, in a programmatic way.
However, in a highly integrated processor including multiple processor cores configured to execute multiple threads as well as system components (e.g., peripherals, interfaces, etc.) external to the processor cores, there may exist data elements external to the processor cores for which error conditions may be detected. In a fine-grained multithreaded, multiple-core environment, it is ambiguous as to how errors occurring externally to processor cores may be efficiently and flexibly handled.
USPTO Backgrounds
USPTO Backgrounds