The disclosed embodiments relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating gate patterns and a landing plug contact in a semiconductor device.
Metal gate electrodes are generally applied to reduce resistance of gate electrodes. When a metal gate electrode is applied, a number of metal compound layers are formed to reduce resistance between a metal electrode and a polysilicon electrode, thereby forming a metal gate. Forming the metal gate having multiple layers often results in a slope profile due to the differences between etch rates and characteristics of thin layer materials.
FIGS. 1A and 1B illustrate micrographic views showing gates with a slope profile and distribution of the same.
Referring to FIG. 1A, the slope profile of metal gate electrodes is shown. Referring to FIG. 1B, the slope profile is more likely to be generated in edge regions of a wafer.
The slope profile generally increases a line width of a gate, and therefore causes a sidewall passivation layer for protecting sidewalls of the gate to be damaged while performing a self-aligned contact etch process for forming a subsequent landing plug contact. Consequently, a portion of a metal gate electrode may be exposed. The self-aligned contact etch process includes forming a contact by performing an anisotropic etching process using an etch selectivity between an oxide-based layer and a nitride-based layer without performing a mask process. The self-aligned contact etch process may result in a greater etched portion and loss when a slope profile is generated in a gate than a vertical profile because an etch region is not defined by a mask.
Furthermore, the metal gate electrode exposed by the damaged sidewall passivation layer may cause a bridge between the subsequent landing plug contact and the metal gate electrode. As a result, a self-aligned contact failure may occur.
USPTO Backgrounds
USPTO Backgrounds