1. Field of the Invention
The present invention relates to a method for receiving and outputting signals representative of full color containing half-tone, which are used for a color scanner, color CRT, color printer, color copying machine, or the like, and an apparatus for executing the method. More particularly, the invention relates to a method for transforming color signals in order to reproduce a color faithfully, and an apparatus for executing the method.
2. Description of the Related Art
In the fields of color printing, color television, color copying machine and the like, there are many proposals to transform color signals. In a typical example of those proposals, an input color space, e.g., a BGR coordinate, is directly transformed into an output color space, e.g., a YMC (K) coordinate by using a table memory. When three color signals in a BGR coordinate, for example, are transformed into digital signals at resolutions of the necessary gray levels, a great amount of table data is required. To store the data, a table memory with a large memory capacity must be provided. Such a memory is very expensive.
For example, in a case where each of the input colors B, G, and R are expressed by 8 bits, and the output colors Y, M, C, and K are also expressed by 8 bits, the required memory capacity of the table memory is 2.sup.24 .times.4 bytes. It is impractical to use such a big memory.
Many interpolation basis methods have been proposed for reducing the necessary memory capacity in transforming color signals by using the table memory. In these methods, a color correction memory addressed with the higher bits of the input signals is used for reducing the necessary memory capacity. The coarsened data is corrected by using an interpolation circuit using the lower bits.
The interpolation basis method disclosed in Published Examined Japanese Patent Application No. Sho. 58-16180 will be described with reference to FIG. 11 and with use of equation (1). ##EQU1##
FIG. 11 is an explanatory diagram showing the process to divide a unit cube. A unit cube as an object to be interpolated is divided, in three planes x=y, y=z, and z=x, into six tetrahedrons denoted as {1} to {6}. The equation (11) is a mathematical expression of the interpolation for the tetrahedral region {2}. In the equation, x.sub.h, y.sub.h, and z.sub.h represent the higher bits of an input; x.sub.1, y.sub.1, and z.sub.1, the lower bits of the same; X' (x, y, z) indicates a value of one output in the input (x, y, z).
In the interpolation method, the lower bits at a point to be interpolated are comparatively checked to determine which tetrahedron contains the interpolated point. The output values corresponding to the four vertexes of the tetrahedron containing the interpolated point are read out of a color correction memory, and are multiplied by four coefficients that are obtained by the subtraction of the lower bits, and the products are added together.
The above publication refers to the method of comparatively checking the lower bits, and the method of reading the output values corresponding to the four vertexes of the tetrahedron from the color correction memory, but does not refer to the details of the specific methods. However, the technique disclosed in the publication has the following problems as determined from the limited descriptions in the publication.
(1) An address calculation for the memory is complicated, when the output values corresponding to the four vertexes of the tetrahedron are read out of the color correction memory. When the hardware technique is used for the address calculation, the hardware construction is complicated. When the software technique is used for the same, much time is taken for processing the address calculation.
(2) Data must be regularly arranged in the color correction memory to allow the output values corresponding to the four vertexes of the tetrahedron to be read from the color correction memory. This technique is contradictory to the technique, proposed by the inventor of the present Patent Application (in Published Unexamined Japanese Patent Application No. Hei. 2-73779), in which the memory portion out of a color reproduction range of the output is removed by irregularly rearranging the regularly arranged data.
(3) As seen from the equation (1), a total number of required calculations is ten; three calculations for the lower bits, four calculations for multiplying the subtraction result by the outputs corresponding to the four vertexes of the tetrahedron, and three calculations for the final addition. A complicated hardware must be constructed for the calculations or much time must be taken for performing the calculations when the software is used for the calculations.
(4) When strictly considered, the dividing method of FIG. 11 has difficulty in handling data in the boundary face. For yf and zf, two comparisons must be made: yf&gt;zf and yf.gtoreq.zf.
To solve the problems (1) to (3), the inventor of the present Patent Application has proposed the interpolation method shown in FIG. 12 and mathematically expressed by an equation (2) in Published Unexamined Japanese Patent Application No. Hei. 2-187374. ##EQU2##
In the above equation, X'(x.sub.h, y.sub.h, z.sub.h) indicates a reference value of the output of a unit cube as an object to be interpolated.
a.sub.x (x.sub.h, y.sub.h, z.sub.h), a.sub.y (x.sub.h, y.sub.h, z.sub.h), and a.sub.z (x.sub.h, y.sub.h, z.sub.h) represent interpolation sensitivity signals for the unit cube.
b.sub.x (x.sub.h, y.sub.h, z.sub.h), b.sub.y (x.sub.h, y.sub.h, z.sub.h), and b.sub.z (x.sub.h, y.sub.h, z.sub.h) represent interpolation sensitivity select signals for the unit cube.
c (b.sub.x (x.sub.h, y.sub.h, z.sub.h), x.sub.1), c (b.sub.y (x.sub.h, y.sub.h, z.sub.h), y.sub.1), and c (b.sub.z (x.sub.h, y.sub.h, z.sub.h), z.sub.1) stand for interpolation values.
The interpolation method, as just mentioned, completes with only two steps, viz., one to make an access to the memory without any address calculation and the other to add together the readout data. The hardware to implement the method is simple in construction.
Further, the regular arrangement of data in the color correction memory is not essential. Accordingly, the technique is compatible with the technique (Published Unexamined Japanese Patent Application No. Hei. 2-73779) which removes the memory portion out of the color reproduction range of the output by rearranging the regularly arranged data into an irregular arrangement of data.
A modification of the FIG. 12 circuit that can readily be anticipated from the upper half of the equation (2) was also proposed. The modification is as illustrated in FIG. 13. A hardware to implement the modification that is constructed using the multipliers as in the case of FIG. 11, needs a total of only six calculations: three multiplications for each output and three additions for each output.
The deficiency common for the FIGS. 12 and 13 cases is that the boundary between the adjacent interpolation regions is discontinuous since a hexahedron including eight (8) vertexes, viz., an object to be interpolated of which freedom degree is eight (8) for each output color, is interpolated with four parameters X' (x.sub.h, y.sub.h, z.sub.h), and a.sub.h (x.sub.h, y.sub.h, z.sub.h), a.sub.y (x.sub.h, y.sub.h, z.sub.h) and a.sub.z (x.sub.h, y.sub.h, z.sub.h). Reduction of the interpolated regions, viz., increase of the higher bits, will apparently secure the continuity at the boundaries. However, the increase of the higher bits results in an increased memory capacity.
USPTO Backgrounds
USPTO Backgrounds