1. Field of the Invention
This invention relates to the field of integrated circuit design. In particular, it relates to output buffer designs in integrated circuits.
2. Description of the Related Art
An output buffer for transmitting a signal from an integrated circuit to an external circuit is typically designed to drive a relatively high load capacitance (e.g. tens of picofarads) in a very short period of time (e.g. a few nanoseconds). Often, such an output buffer switches simultaneously with other output buffers in the integrated circuit, and the currents required to switch these output buffers are supplied through power and ground pins, which are inherently inductive. Because of the inductance in such power and ground pins, the large instantaneous currents required for simultaneous fast operation of these output buffers may not be available. Consequently, when a large number of output buffers switch simultaneously, large noise pulses can be created on the integrated circuit's internal power and ground lines, resulting in spurious operation or failure of the integrated circuit in its operating environment.
In the prior art, reduction in switching induced noise in output buffers is typically achieved by either increasing the number of power and ground pins or by reducing inductance. However, such improvements are approaching their practical limits. An alternative method controls such noise by providing in the output buffers a substantially constant and controlled "turn on" rate ("slew rate"), which is defined as the rate of current increase ("di/dt") in the output buffer. Many examples of this alternative method can be found in the prior art.
An MOS output buffer is typically formed by one or more predriver stages and a driver stage. In most implementations, the predriver and driver stages are each formed by an inverting logic element. Also, in an MOS output buffer, the slew rate is controlled by both the size of each output transistor in the driver stage (the "output transistor") and the rate of change in gate voltage in the output transistor. Thus, for a fixed size output buffer, the slew rate can be controlled by the voltage ramp in the gate terminal of the output transistor. Several basic methods have been employed to control this voltage ramp, including (i) dividing the output transistor into several discrete transistors which are turned on sequentially; (ii) providing a resistive element (e.g. a high impedance transistor) serially connected to the gate terminal of the output transistor to limit the rise time of the gate voltage; (iii) providing a capacitive feedback to slow the rise time of the gate voltage; or (iv) driving the gate voltage of the output transistor by a constant current source derived from a conventional current mirror, so as to achieve a substantially linear voltage ramp.
The constant current source approach is very attractive in sub-micron MOS transistors, since a substantially linear voltage ramp at the gate terminal of a transistor provides a substantially constant slew rate (i.e. current change) over much of the output buffer's operating range of output voltages. Nonetheless, there are several problems with this approach. First, the effectiveness of this method depends on a substantially constant current, which is preferably independent of process variations. However, such a process insensitive current is difficult to achieve. Second, a significant delay exists between the time the input signal to the output buffer starts to switch and the time the output transistor turns on, which occurs only after the gate voltage rises above the threshold voltage of the output transistor. Third, the reference current in the constant current source typically draws power at all times, resulting in a significant level of power consumption for an integrated circuit with many outputs.
Normal process variations can affect the operation of an output buffer significantly. For example, transistor channel length can vary by as much as 25%, which can represent a near doubling of noise in the output buffer. Further, in a conventional output buffer which output transistor is driven by a current mirror circuit with an MOS reference transistor, a 25% decrease in transistor channel length results in the compounding or multiplicative effects of (i) the reference current increasing 25%, (ii) the predriver's load (i.e. the capacitance in the gate of the output transistor) decreasing 25%, and (iii) the gain of the output transistor increasing 25%. Consequently, noise generated by the output buffer is significantly increased.
A number of solutions are proposed in the prior art to overcome the above deficiencies of the constant current source approach. For example, U.S. Pat. No. 4,823,029, entitled "NOISE CONTROLLED OUTPUT BUFFER" to Gabara, uses a resistor to provide a reference current which is unaffected by variation in transistor channel length. However, high quality resistors in MOS integrated circuits are both difficult to manufacture and subject to other process parameter variations. Further, in addition to being well regulated, a reference current should preferably have a process sensitivity opposite to that of transistor gain, so that a change in reference current due to a variation of a process parameter can be automatically compensated by a corresponding reduction of gain in the output transistor to maintain a substantially constant current. Gabara's reference resistor does not provide such process sensitivity.
Other approaches minimize the delay between the switching of the output buffer's input signal and the output transistor's gate voltage reaching its threshold voltage. For example, U.S. Pat. No. 4,947,063, entitled "METHOD AND APPARATUS FOR REDUCING TRANSIENT NOISE IN INTEGRATED CIRCUITS" to O'Shaughnessy et al, describes using capacitance division (see below) to minimize such delay. O'Shaughnessy also provides a fixed capacitor at the output terminal of the predriver stage to provide a controlled voltage ramp which drives the output stage of the output buffer. The controlled voltage ramp reduces switching noise by constraining the discharge of the output load to a substantially linear rate of current change (di/dt). However, practical and adequate capacitors necessary for O'Shaughnessy's method are not readily available in most MOS processes.
Selected approaches in the prior art, including those discussed in Gabara and O'Shaughnessy, are discussed with reference to FIGS. 1 and 2 below.
FIG. 1 shows a prior art slew rate controlled output buffer 100. Pins 10 and 11 are respectively the input and output terminals of output buffer 100. Capacitor 12 represents the load typically driven by output buffer 100. A predriver stage 50, which is a CMOS inverter controlling the pull-down transistor 18 of the driver stage 51, is formed by transistors 13, 14 and 15. Transistors 17 and 18 form the output stage 51 of output buffer 100.
As shown in FIG. 1, when node 38 is pulled to logic high voltage by a transition in predriver stage 50, the gate voltage of transistor 18 is regulated, or slowed, by transistor 14's relatively high impedance (with respect to the impedance of transistor 15). Thus, transistor 14 slows the slew rate of transistor 18, and thereby reduces the rate of current change (i.e. di/dt) in transistor 18. Consequently, the noise generated when the signal at output terminal 11 switches from logic high voltage to logic low voltage is also reduced.
In FIG. 1, a complementary predriver circuit 52 (not shown) drives node 16, which is the gate terminal of the pull-up transistor 17, to control the low-to-high transition of the signal at output terminal 11. In complementary predriver 52, a relatively high impedance transistor similar to transistor 14, regulates the current flowing from node 16 to ground.
Circuit 100 is satisfactory in reducing the rate of current change in the output stage 51. However, several drawbacks are associated with this approach. First, the gate voltages for output transistors 17 and 18 do not increase linearly, but each gate voltage exhibits the exponential rise characteristic similar to that of an RC circuit. Thus, for a fixed noise level, output buffer 100 will respond more slowly than if linear gate voltage ramps were provided at nodes 16 and 38. Second, the performance of output buffer 100 can vary widely with process variation, so as to be undesirably slow when the process and operating conditions are under most unfavorable ("worst case") conditions, and excessively noisy under the most favorable ("best case") conditions. Third, even though initially aided by the capacitance division effect existing between node 7 (i.e. the source terminal of transistor 15) and node 38, a significant delay still exists between the time the gate voltage of output transistor 18 increases from zero volts to the time the gate voltage reaches threshold voltage. (The capacitance division effect is provided by the parasitic capacitors in the nodes 7 and 38. Immediately after transistor 15 is turned on, the charge stored in node 7 is divided between nodes 7 and 38, thereby increasing the rate at which node 38 is brought to the threshold voltage of output transistor 18).
Because of the above drawbacks, output buffer 100 is not satisfactory when both very fast response time and good noise control are required.
FIG. 2 is a schematic diagram of a prior art output buffer driver 200. To facilitate reference, components in FIGS. 1 and 2 which perform substantially the same functions are given identical reference numerals. Output buffer 200 incorporates a current mirror control circuit 28 into the pull-up of predriver stage 60, which is formed by current mirror control or reference circuit 28, and transistors 20, 21 and 22. Transistor 22, which is the output transistor of a conventional current mirror controlled by the current mirror control circuit 28, provides a substantially constant current output. Current mirror control circuit 28 comprises transistors 23 and 24. The output signal of predriver stage 60 drives node 38, which is the gate terminal of the pulldown transistor 18 of output stage 61. As in FIG. 1, output stage 61 of output buffer driver 200 comprises output transistors 17 and 18 driving an output load 12, which is connected to output pad 11. A complementary predriver circuit 62 (not shown), similar to predriver stage 60, is used to drive node 16 to provide the pull-up control of driver stage 61.
By incorporating current source control circuit 28 into predriver 60, the substantially constant current of transistor 22 provides a substantially linear gate voltage ramp at node 38, which is the gate terminal of output transistor 18. Thus, as compared to circuit 100 of FIG. 1, output buffer 200 can be designed to achieve either a reduced level of noise for the same performance as circuit 100, or increased performance over circuit 100 without exceeding the same noise level. A further advantage can be achieved by replacing transistor 24 in current mirror control circuit 28 by a resistor, which provides a relatively more stable current over a wider range of operating conditions than using a transistor (e.g. transistor 24) as a current reference. However, a resistor responds to process variations substantially differently than a reference transistor. Consequently, a resistor in place of transistor 24 exhibits a wide range of characteristics that is not tracked by transistors in the circuit.
The capacitance division effect discussed in FIG. 1 above can also be seen in FIG. 2. In FIG. 2, when the input signal of pin 10 switches from logic high voltage to logic low voltage, the charge stored in the parasitic capacitor of node 27 is divided between the parasitic capacitors of nodes 27 and 38. The current associated with this charge sharing increases the rate at which the gate voltage of output transistor 18 is brought to threshold voltage. A further improvement taught by O'Shaughnessy referenced above uses an additional coupling capacitor to speed up signal 38. However, while capacitance division or O'Shaughnessy's method, or both, may be satisfactorily used in some applications, the large coupling capacitors required for complete effectiveness may be impractical, especially if output transistor 18 has a large gate capacitance.
There are many examples in the prior art which use a current regulating transistor with an impedance controllable by a control circuit, such as the current mirror of FIG. 2 discussed above, which comprises current regulating transistor 22 and current mirror control circuit 28. In FIG. 2, pull-up transistor 22 of predriver stage 60 is coupled to a power supply pin VDD. (Similarly, the corresponding current regulating transistor in predriver stage 62 (not shown) is coupled to a ground pin). All such examples in the prior art invariably have such regulating transistors coupled directly to power or ground pins. By coupling current regulating transistor 22 to the power supply pin, a convenient common voltage reference to both transistor 22 and current mirror control circuit 28 is provided. Such common reference provides the advantages of easily predictable biasing, operation, and coupling of the control circuit and the current regulating transition. Furthermore, this connection scheme inherently permit some circuit speed up by capacitance division as discussed above.
However, neither circuits in FIGS. 1 and 2 satisfactorily minimize the output transistor's turn on time, which is the time it takes to increase the voltage at the gate of transistor 18 from ground voltage to its threshold voltage. This is because, for a large output transistor, such as transistor 18, the capacitance division effect provides insufficient impact on the speed at which the gate voltage of the output transistor reaches threshold voltage.
Further, because the current mirror control circuit requires a reference current flowing constantly, the output buffers of the prior art consumes power constantly. Neither Gabara nor O'Shaughnessy discloses or suggests any means to fully turn off the reference current when not needed.
USPTO Backgrounds
USPTO Backgrounds