1. Field of the Invention
The present inventive concept relates to a method of controlling a memory system in the event of a sudden power off.
2. Description of the Related Art
While a memory system is operating, a sudden power off, which is an abrupt power loss, may occur due to an unexpected power failure. The sudden power off leads to an external power off. However, since the memory system includes an auxiliary power device such as a super capacitor, it can be driven by the auxiliary power stored in the auxiliary power device. While being driven by the auxiliary power, the memory system may complete operations being performed by flash memory devices and dump necessary data to the flash memory devices. After the completion of the dump operation, the memory system may terminate all operations by cutting off the internal power supply (internal power off).
The memory system may include multiple flash memory devices, and the flash memory devices may be performing various operations when a sudden power off occurs. Here, the time required for the flash memory devices to complete an erase operation may be relatively longer than the time required to complete a read operation or a program operation. If a flash memory device starts to perform the erase operation at the same time as when a sudden power off occurs, since it requires a considerable amount of time to complete the erase operation, a power off time, which is the time required for the memory system to terminate all operations by cutting off the internal power supply after the occurrence of the sudden power off can be increased.
However, it is desirable to minimize the power off time because the amount of auxiliary power stored in the auxiliary power device is limited.
USPTO Backgrounds
USPTO Backgrounds