1. Field of the Invention
This invention relates to method and structures for the manufacture of semiconductor memory devices and more particularly to improved flash EPROM devices.
2. Description of Related Art
The processing of a silicon nitride (Si.sub.3 N.sub.4) spacer (180 A) etching is very critical for this type of manufacturing process for flash EPROM devices. Because the dimensions of the Si.sub.3 N.sub.4 spacers are so small, it is difficult to control and maintain this process. The function of this thin silicon nitride spacer is to prevent write disturbance that is caused by reverse tunneling.
In general sidewall spacers formed of multiple layers are known in the industry.
U.S. Pat. No. 5,573,965 of Chen et al. for "Method of Fabricating Semiconductor Devices and Integrated Circuits Using Sidewall Spacer Technology" shows a method of forming a transistor using multi-layered structures of silicon dioxide alone or of silicon dioxide/silicon nitride. Chen shows the first spacer layer underlying subsequent spacers which is similar in structure as the invention.
U.S. Pat. No. 5,183,771 of Mitsui et al. for "Method of Manufacturing LDDFET Having Double Sidewall Spacers" shows a method of forming a transistor having double sidewall spacers both formed from silicon oxide layers over silicon substrate adjacent to the polysilicon gate electrode of a compound polysilicon/polycide gate electrode of a CMOS device, without a floating gate electrode.
U.S. Pat. No. 5,489,546 of Ahmad et al. "Method of Forming CMOS Devices Using Independent Thickness Spacers in a Split-Polysilicon DRAM Process" shows a transistor having a double sidewall spacer formed over a gate oxide layer with both layers composed of silicon nitride designed to vary the channel length in a CMOS device with a compound polysilicon/polycide gate electrode, without any floating gate electrode. Ahmad et al. also shows the first spacer layer underlying the subsequent spacer.
The above patents do not show the details/(exact compositions of the two spacer layers) of the invention.
USPTO Backgrounds
USPTO Backgrounds