1. Field of the Invention
The present invention relates to a clock-synchronous semiconductor memory device and access method thereof which operates synchronously with a basic clock signal, and, in particular, to a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set synchronously with a basic clock signal, and a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set when a high-frequency basic clock signal is used.
2. Description of the Prior Art
The inventors of the present invention have previously proposed a basic method for controlling a memory operation for a semiconductor memory device synchronized with a basic clock signal (Japan Application No. 3-255354).
At that time, several methods were illustrated for controlling a memory access by means of an external control signal, but nothing was disclosed how to set a external control signals synchronously with a basic clock signal and with respect to setting specific timing for an address signal or the like for the external control signals.
Moreover, there is a problem that it is difficult to access data when a high-frequency basic clock signal is used in a conventional a clock-synchronous semiconductor memory device and access method thereof.
According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a counting circuit configured to receive a clock signal and counting a number of clock cycles of the clock signal; a control circuit configured to receive an external control signal, and to generate an internal control signal on the basis of the external control signal and/or an output signal from the counting circuit; a specification circuit configured to receive address signals in response to the internal control signal generated from the control circuit, and to designate a memory cell in the memory cell array; a selection circuit configured to receive the address signals in response to the internal control signal from the control circuit, and to select one of a normal operation mode and a synchronous mode in a mode setting cycle; and a data I/O circuit configured to input data into the memory cell selected by the specification circuit and to output the data from the memory cell selected by the specification circuit, wherein in the normal mode, setting of address signals of the memory cell in the memory cell array by the specification circuit is effected irrespective of the clock signal, and in the synchronous mode, a rising edge or a falling edge of the clock signal determines a setting timing of the address signals of the memory cell in the memory cell array by the specification circuit.
USPTO Backgrounds
USPTO Backgrounds