1. Field of the Invention
The present invention relates to integrated circuit testing, more particular to Automatic Test Pattern Generation (ATPG).
2. State of the Art
After fabrication, integrated circuits are tested by applying test patterns and observing response patterns. Rigorous testing of sequential circuits is difficult or impossible unless the integrated circuit is designed with testing in mind, so-called Design for Test, or DFT. A principal DFT technology is scan insertion. Scan insertion involves inserting scan flip flops into the circuit so as to enable the logic values of various internal nodes of the circuit to be set to known levels. Integrated circuit designs are described by netlists. During scan insertion, a modified netlists is generated in which scan flip flops ("scan flops") are added. Using scan insertion, a sequential circuit can, in effect, be partitioned into multiple combinatorial circuits, the inputs to which can be set by scan insertion and the outputs of which can be observed. Referring to FIG. 1, an example of scan insertion is shown. An integrated circuit is assumed to have a register of some number of bits, e.g., five. During scan insertion, scan flops are inserted, e.g., five flip flops, one corresponding to each register bit. For reasons made clear below, the scan flops are shown in dotted lines.
Following scan insertion, ATPG is performed using an ATPG tool. ATPG tools are offered by serveral commercial vendors. One popular tool is the Sunrise.TM. ATPG tool. During ATPG, circuit simulation is performed to arrive at an efficient set of test vectors for the integrated circuit that result in high fault coverage (e.g., 80-90%) for various categories of faults. Fault coverage refers to the percentage of possible faults that are tested by the set of test vectors. Because testing for some faults would inordinately increase the amount of testing required, 100% fault coverage is rarely achieved.
Scan insertion increases circuit size and power consumption, and may impact circuit performance. What is needed is a technique that avoids some of the overhead of scan insertion but that achieves as good or better fault coverage than if scan insertion had been used.
USPTO Backgrounds
USPTO Backgrounds