Semiconductor devices have become denser and smaller. 3D memories, going with the trend, have been developed. In a typical 3D memory semiconductor device, the structure used as the memory layer may also be used to provide the gate dielectric layer for the string select line. As such, during the program/erase of the memory cells, the gate dielectric layer for the string select line may also be charged. Thus, an extra circuitry is needed to control program/erase of the gate dielectric layer for the string select line.
USPTO Backgrounds
USPTO Backgrounds