This invention relates generally to semiconductor devices, and more specifically to lateral field effect transistor (FET) structures and methods of manufacture.
Metal-oxide semiconductor field effect transistors (MOSFETs) are a common type of integrated circuit device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate provided over the channel region. The gate includes a conductive gate structure disposed over and separated from the channel regions with a thin dielectric layer.
Lateral MOSFET devices are common devices used in high voltage (i.e., greater than 200 volts) applications such as off-line switching regulators in AC/DC voltage conversion. Lateral MOSFET devices typically comprise a source region and a drain region separated by an intermediate or drift region. A gate structure is disposed over the channel region of the device. In the on state, a voltage is applied to the gate to form a conduction channel region between the source and drain regions, which allows current to flow through the device. In the off state, voltage applied to the gate is sufficiently low so that a conduction channel does not form, and thus current flow does not occur. During the off state, the device must support a high voltage between the source and drain regions.
Lateral power FET devices typically are designed with source and drain regions that are elongated (i.e., much longer than they are wide), and interdigitated. In such designs, the source and drain regions typically terminate with source tips and drain tips respectively. FIG. 1 illustrates a top plan view of a typical prior art interdigitated lateral power FET 10 having source regions 11 interdigitated with drain regions 12. Source regions 11 are interconnected with or by a common diffused region 16, and drain regions 12 are interconnected with or by a common diffused region 17. Source regions 11 are formed within p+ high voltage (PHV) regions 13, and drain regions 12 are formed in well regions 14. This interdigitated design results in fingertips 18 and 19 on PHV regions 13 and drain regions 12 respectively.
In order for device 10 to withstand large blocking voltages (e.g., greater than 200 volts), special precaution must be taken to design termination regions for fingertips 18 because of electrical field crowding caused by the small radius of curvature of fingertip 18. Such electrical field crowding can lead to degraded blocking voltage performance or device failure.
To avoid degraded blocking voltage, device 10 includes a cut-out region 21 around fingertips 18 of PHV regions 13. As shown in FIG. 2, which is a highly enlarged partial cross-sectional view of device 10 taken along reference line 2—2, cut-out region 21 comprises a region of underlying substrate 26 wherein n-well 14 is pulled back to effectively increase the radius of curvature of fingertip 18, which reduces electrical field crowding. Cut-out regions 21 further comprise an “x” dimension and a “y” dimension that must be modified and optimized depending on desired blocking voltage characteristics.
Several problems exist with the design of device 10. For example, design parameters (e.g., x and y dimensions) are not well scalable with blocking voltage. This requires designers to perform multiple design iterations to optimize the design of fingertips 18 and cutout regions 21 if blocking voltage is changed (e.g., from 700 volts to 200 volts). Additionally, variations in wafer fabrication processes (e.g., doping levels and process temperature) result in variations in the characteristics of fingertips 18 (e.g., doping profiles, radius of curvature, etc.), which degrade blocking voltage characteristics and overall device reliability. In addition, because device 10 includes regions such as cut-out regions 21 and common diffused regions 17, the overall size of device 10 becomes larger, which in turn increases specific on resistance (i.e., Ron*Area).
Accordingly, a need exists for structures and methods that improve the blocking voltage capability and Ron*Area performance of lateral MOSFET devices. It would be advantageous for such structures and methods to be flexible to support a number of blocking voltages and to be cost effective.
USPTO Backgrounds
USPTO Backgrounds