This invention relates to thermally assisted magnetoresistive random access memory (TAS-MRAM), and more particularly, a TAS-MRAM cell structure with two mask adders.
There are two major groups in computer memory: non-volatile memory and volatile memory. Constant input of energy in order to retain information is not necessary in non-volatile memory but is required in the volatile memory. Examples of non-volatile memory devices are Read Only Memory (ROM), Flash Electrical Erasable Read Only Memory, Ferroelectric Random Access Memory, Magnetic Random Access Memory (MRAM), and Phase Change Memory (PCM); non-volatile memory devices being memory in which the state of the memory elements can be retained for days to decades without power consumption.
Embedding of non-volatile memory with a larger system of circuits often utilizes Flash memory technology. Current embedded memory solutions also tend to be expensive due to the use of many mask adders. These solutions also exhibit limited performance, such as low endurance and low maximum operating. Furthermore, cross-technology-node compatibility of current embedded memory solutions requires substantial redesign and optimization of both the memory cell for each node and the technology variant within each node.
MRAM is an excellent candidate technology for embedded non-volatile memory; it exhibits high speed and endurance and cross-technology-node compatibility. Existing thermally-assisted MRAM (TAS-MRAM) devices that can tolerate high temperature operation require more than two masks to embed.
Mask adders are lithography levels added to a standard chip fabrication process in order to incorporate additional functionality. A low number of mask adders may reduce the cost of fabrication and allow an increase in chip density.
USPTO Backgrounds
USPTO Backgrounds