With continued miniaturization semiconductor devices, there has been an increased demand for ultra-shallow junctions. For example, tremendous effort has been devoted to creating better activated, shallower, and more abrupt source-drain extension junctions to meet the needs of modern complementary metal-oxide-semiconductor (CMOS) devices.
To create an abrupt, ultra-shallow junction in a crystalline silicon wafer, for example, an amorphization of the wafer surface is desirable. Generally, a relatively thick amorphous silicon layer is preferred since a thin amorphous layer can cause more significant channeling, fewer dopant atoms confined in the amorphous layer, and more interstitials residing in an end-of-range area beyond the amorphous-crystalline interface. As a result, a thinner amorphous layer may lead to a deeper junction depth, a less abrupt doping profile, an inadequate activation of dopants, and more end-of-range defects after anneal, all of which represent major obstacles in modern CMOS device miniaturization, especially for source-drain extension doping.
It has been discovered that a relatively low wafer temperature during ion implantation is advantageous for amorphization of a silicon wafer. In current applications of ion implantation, wafers are typically cooled during the implantation process by a gas-assisted process using a chiller. In most cases, such cooling techniques put the wafer temperature between the chiller temperature (e.g., 15° C.) and an upper limit imposed to preserve photoresist integrity (e.g., 100° C.). Such a high temperature may enhance a self-annealing effect, i.e., the annihilation of Frenkel pairs (vacancy-interstitial pairs created from ion beam bombardments). Since amorphization of the silicon occurs only when a sufficient number of the silicon atoms are displaced by beam ions, the increase of Frenkel pair annihilation at high temperatures works against the much needed amorphization process, resulting in a higher dose threshold for amorphization and therefore less than ideal shallow junctions.
With other parameters being the same, the thickness of an amorphous silicon layer may increase with decreasing implantation temperature due to a reduction of the self-annealing effect. With a thicker amorphous layer, less tail channeling is expected. More damage created by beam ions is confined in the amorphous region and less damage is introduced into the crystalline region immediately beyond the amorphous-crystalline interface. Also, during a subsequent annealing, better activation can be achieved as more dopants find themselves in substitutional sites due to a solid-phase epitaxy process.
In addition to the benefits introduced by a thicker amorphous silicon layer, performing ion implantation at low temperatures also minimizes the movement of Frenkel pairs during the implantation. As a result, fewer Frenkel pairs are pushed into the region beyond the amorphous-crystalline interface as compared to the case of higher temperature implantation. Most of the Frenkel pairs will grow back into the lattice during the solid-phase epitaxy process and do not contribute to excess interstitials which cause transient enhanced diffusion or form extended defects. Fewer excess interstitials also lead to less impact of source-drain extension doping on channel or halo doping. With fewer interstitials pushing channel or halo dopants into a channel region, less negative coupling, such as reverse short channel effect, is expected. Thus, better process control and prediction of device performance may be achieved.
Rapid thermal anneals, in which the wafer is heated to, for example, 1000° C. in 5 seconds, have commonly been used to activate implanted dopants. Diffusion-less anneals are becoming preferred post-implant processes, wherein the temperature of a wafer is ramped up much faster (e.g., to 1000° C. in 5 milliseconds) using, for example, a laser as a heat source. These extremely rapid thermal processes act so quickly that the dopants do not have time to diffuse significantly, but there is also less time for the implant damage to be repaired. It is believed that low-temperature ion implantation may improve the extent of implant damage repair during such diffusion-less anneals.
Other reasons for low-temperature ion implantation also exist.
Although low-temperature ion implantation has been attempted, existing approaches suffer from a number of deficiencies. First, most existing low-temperature ion implantation techniques have been developed for batch-wafer ion implanters while the current trend in the semiconductor industry favors single-wafer ion implanters. Batch-wafer ion implanters typically process multiple wafers (batches) housed in a single vacuum chamber. The simultaneous presence of several chilled wafers in the same vacuum chamber, often for an extended period of time, requires extraordinary in-situ cooling capability. Pre-chilling an entire batch of wafers is not an easy option since each wafer will experience a different temperature increase while waiting for its turn to be implanted. In addition, extended exposure of the vacuum chamber to the low-temperature wafers may result in icing from residual moisture.
Second, almost all existing low-temperature ion implanters cool wafers directly during ion implantation. Apart from causing icing problems in a process chamber, direct cooling requires incorporation of cooling components (e.g., coolant pipelines, heat pumps, and additional electrical wirings) into a wafer platen. Usually, modern wafer platens are already fairly sophisticated and very difficult to modify. As a result, modification of an existing ion implanter or designing a new ion implanter to accommodate low-temperature processes can be prohibitively expensive while only managing to achieve marginal improvement. Moreover, modification of a wafer platen for low-temperature ion implantation may have unwanted impact on the ion implanter's capability of performing room temperature ion implantation processes. In addition, in-situ cooling often significantly slows down the overall ion implantation process and therefore reduces production throughput.
In view of the foregoing, it would be desirable to provide a solution for low-temperature ion implantation which overcomes the above-described inadequacies and shortcomings.
USPTO Backgrounds
USPTO Backgrounds