A large scale integrated circuit includes a great number of circuit elements in a very small space. Therefore, a process for manufacturing the large scale integration circuit is very complex and requires a large amount of time. Recently, a process called the master slice method was developed. In the master slice method, the processes carried out before the formation of the wiring by metallic evaporation are commonly carried out for many circuits. Only the final wiring process, such as an aluminium evaporation, is different, depending on the circuit to be formed.
One example of a transistor-transistor logic (hereinafter called TTL) circuit which is manufactured by the master slice method is disclosed in an article entitled "TTL 500-gate Master Slice LSI (MB 15000 Series)", by Norikuni Higashi et al, FUJITSU, Vol. 30, No. 1, pp 185.about.208. In the TTL circuit disclosed in the article, a multi-emitter transistor is used as the input stage. In this TTL circuit, when at least one of the input levels of the multi-emitter transistor becomes low by receiving an input logic signal, the multi-emitter transistor is placed in a conductive state and a large current flows in a collector of the multi-emitter transistor, so that a large emitter current flows in the multi-emitter transistor.
In the master slice method, when an LSI having numerous gates (such as more than 500), is manufactured by using a conventional TTL, and when the input level becomes low, a voltage drop in the input wiring connected to the emitter becomes large due to the large emitter current in the multi-emitter transistor. Further, since normally 0.35 V is used as a low level logic input and more than 1 V is used as a high level logic input, about 0.65 V is used as a threshold voltage. However, if a voltage drop in the input wiring portion is large, the difference between the low level logic input of the circuit and the threshold voltage becomes small.
FIG. 1 of the drawings depicts a conventional TTL circuit which includes a multi-emitter transistor Q.sub.1 having emitters connected to input terminals A, B . . . N, an output transistor Q.sub.2 having a collector connected to an output terminal (OUT), resistors R.sub.1, R.sub.2, R.sub.3 which are connected between an electric source terminal (VCC) and respectively the base of the multi-emitter transistor Q.sub.1 a connection point between the collector of the multi-emitter transistor Q.sub.1 and the base of the output transistor Q.sub.2 ; and the collector of the output transistor Q.sub.2.
In the conventional TTL circuit illustrated in FIG. 1, if at least one of the logic input levels A, B, . . . , N becomes low due to an input signal, the transistor Q.sub.1 is placed in a conductive state and a large collector current flows in the transistor Q.sub.1 via the resistor R.sub.2, so that a large current flows in the emitter of the transistor Q.sub.1.
If a master slice having many gates (such as more than 500 gates) is manufactured by using a conventional TTL illustrated in FIG. 1, when the input logic level becomes low, the voltage drop in the input wiring connected to the emitter becomes large due to the large emitter current in the multi-emitter transistor Q.sub.1. Further, since normally 0.35 V is used as a low level logic input and more than 1 V is used as a high level logic input, it is desirable that approximately 0.65 V be used as a threshold voltage. However, if a voltage drop in the input wiring is large, the difference, i.e., the margin, between the low level logic input of the circuit and the threshold voltage becomes small.
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