The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Some network devices, such as network switches, routers, edge devices and the like, include multiple switching cores that share workload of processing packets received by the network device. Such network devices often employ store and forward architectures in which received packets are stored in memory for subsequent transmission to desired destinations after processing. Conventionally, each switching core of a multi-core switching device is coupled to a respective memory. Only the switching core that is coupled to the memory can access the memory and utilize the memory space thereof, such that a given memory space is not shared among more than one core.
USPTO Backgrounds
USPTO Backgrounds