Testing and potentially modifying internal parameters of memory chips for the purpose of circuit optimization is critically important. This is particularly important because memory chips are becoming more complex and the time to market is a very critical factor in the success of any chip. In some chips, this is done by making modifications to masks such as metal or contact. The masks are processed toward the end of the fabrication process and making changes to the circuitry using these masks does not add too much of a time penalty. Although this is a valid solution, it still fails to allow for maximum flexibility or minimize turnaround times.
With memories such as non-volatile memories, more flexibility is added through the use of such memory elements in modifying circuit parameters. By programming a specific pattern in these memory elements, one can change the configuration of the circuitry and even the configuration of the entire chip. The modification of these settings are done through non-user modes of operation and usually during test mode operations. However, accidental modification of any of these settings can have devastating effects on the operation of the chip and must be avoided.
Test modes are non-user modes that are typically used for stressing or changing the internal settings of the parts. The accidental or even intentional use of such modes by a user could damage the part. Some test-mode enable schemes use high voltage signals to execute a test mode. With these approaches, however, a noisy set-up may potentially trigger a test mode. Still other schemes require a complicated software sequencing to achieve the desired test modes. With these test modes, however, software alone might still too easily allow a user to trigger a test mode, which could adversely affect the part.
USPTO Backgrounds
USPTO Backgrounds