1. Field of the Invention
This invention relates generally to programmable gain amplifiers (PGAs), and more particularly, to a method of configuring a switch network associated with a PGA to minimize errors caused by the switch resistance.
2. Description of the Prior Art
Numerous PGA architectures have been implemented to accommodate various applications. A general PGA architecture 100 as shown in FIG. 1 includes an amplifier 102, input resistor R1, feedback resistor R2 and n-bit decoder 104. For simplicity, only the single-ended version is described. The decoder 104 generates the signals necessary to switch in proper valued resistors R1 and R2. If the error caused by the finite amplifier open-loop gain is neglected, the gain of the PGA 100 can be represented by R2/R1. Either R1 or R2 or both can be changed depending on the applications. For multiple gains, a network of switches and resistors must be introduced to select the proper value of resistors R1 and R2 for a specific gain. If resistors R1 and R2 both can be changed, a moving-tap structure can be used as shown in FIG. 2.
FIG. 2 is a schematic diagram illustrating a moving-tap PGA 200 that is known in the art. Only one switch (S1, S2, S3 . . . ) is switched ON for one gain setup. Assume for example, only switch Si is ON (1xe2x89xa6ixe2x89xa6m), and let R1=Rtap1+Rtap2+ . . . Rtapi, 2=Rtapi+1+ . . . +Rtapm. The gain is determined by R2/R1. The switch resistance is not part of the input resistance or feedback resistance. This is nice, but not all applications can be implemented in this way. Many applications require resistor R1 or resistor R2 to be fixed. If, for example, the input resistor R1 is fixed, the feedback resistor R2 then needs to be programmable. The architecture shown in FIG. 3 is a common choice for this scenario.
FIG. 3 is a schematic diagram illustrating a common PGA structure 300 having a fixed input resistor R1. In FIG. 3, the switches S1, S2, . . . , Sm are part of the feedback resistor; and variable voltage signals across the switches (S1, S2 . . . Sm) are common during normal operation. As can be seen from FIG. 3, neglecting the finite gain of the amplifier 102, the PGA 300 gain is then represented by equation 1, where i is the index of gain steps, Gain is the ith gain, and Rsi is the switch resistance of switch Si.                               Gain          i                =                                            R2              i                        +                          R              si                                R1                                    (        1        )            
Popular CMOS switches have varied ON-resistances depending on the drain-source voltages. The variance causes gain error and distortion; so in practical implementations, the ON-resistance is made as small as possible. For example, to achieve a PGA gain of 0.1 (xe2x88x9220 dB) with resistor R1=10K, then the feedback resistor R2 need to be less than 1000 Ohms. A switch resistance of 2% or less then necessitates that the switch resistance be less than 20 Ohms. This will require a CMOS switch W/L ratio in the order of several hundred. If there are many gain steps like this in one PGA, many big switches will be needed, and this will consume extensive die area. Using multiple-stage PGA structure can significantly reduce the number of switches.
FIG. 4 shows a two-stage PGA 400, in which the first stage 402 has p coarse gain steps and the second stage 404 has q fine steps to construct total of p*q gain steps (wherein p and q are integers greater than or equal to 2). Comparing PGA 400 with a one stage PGA, the number of total switches needed for two-stage PGA is reduced from p*q to p+q. The two-stage PGA 400 reduced the number of switches from p*q to p+q. Although the reduction is substantial, reducing the switch sizes and die area is still a remaining problem for the gain steps that require very big switches and very small switch resistances. In view of the foregoing, it would be desirable and advantageous to provide a method of configuring a switch-network to implement Programmable Gain Amplifiers (PGAs) to provide high-accuracy and low-distortion with smaller area and less sensitivity to process and temperature variations when compared with traditional PGA architectures.
The present invention is directed to a method of configuring a switch network associated with an analog device or mixed-signal device such as a programmable gain amplifier that employs a switch network to determine a ratio between one or more fixed resistors and one or more programmable resistors to minimize errors caused by the switch resistance. Multi-step differential PGA configurations can also be easily obtained in accordance with different embodiments of the present invention. The method configures the switch network such that the switch resistance is a portion of a bigger resistor instead of a smaller resistor to ensure that errors caused by the switch resistance are smaller. The method allows use of smaller switches to maintain a constant error level. This method addresses device gain setups that require big switches to maintain small distortion, wherein the area of the switches is also big; and the gains are sensitive to the layout, process and temperature variations associated with the switches.
In one aspect of the invention, a programmable switch network is implemented within a programmable gain device such that the layout area associated with the switches is minimized.
In another aspect of the invention, a programmable switch network associated with a programmable gain device is implemented to provide a device gain that is insensitive to the layout, process and temperature variations associated with the switches.
One embodiment of the invention is directed to a method of configuring a switch network, the method comprising the steps of providing a variable gain circuit having a switch network that is configurable to control a ratio between at least one fixed resistor and at least one programmable resistor; comparing the resistance of the at least one fixed resistor with the resistance of the at least one programmable resistor for a desired circuit gain; and configuring the switch network such that any switch that is in a DC current path when activated to implement the desired circuit gain is activated such that the DC current path switch resistance combines solely with the at least one resistor having the larger resistance value, and further such that the DC current path switch resistance of any switch that is in a DC current path when activated to implement the desired circuit gain is activated such that the DC current path switch resistance divides equally among the at least one fixed resistor and the at least one programmable resistor when the resistance of the at least one fixed resistor is equal to the resistance of the at least one programmable resistor to implement the desired circuit gain.
Another embodiment of the invention is directed to a method of configuring a switch network comprising providing a variable gain device having a switch network that is programmable to control a ratio between a fixed resistance and a programmable resistance to vary the gain, and programming the switch network such that any switch that is in a DC current path when activated to implement a desired gain is activated such that the DC current path switch resistance combines solely with the largest resistance value selected from among the fixed resistance and the programmable resistance, and further such that the DC current path switch resistance of any plurality of switches that are in a DC current path when activated to implement the desired circuit gain are activated such that the DC current path switch resistance divides equally among the fixed resistance and the programmable resistance when the fixed resistance is equal to the programmable resistance to implement the desired circuit gain.
Still another embodiment of the invention is directed to a method of configuring a switch network within a programmable gain device having a switch network that is programmable to control a ratio between a fixed resistance and a programmable resistance to vary the gain, the method comprising programming the switch network such that at least one switch is in a DC current path when activated to implement a desired gain such that the at least one switch resistance combines solely with the largest value of resistance selected from among the fixed resistance and the programmable resistance when the fixed resistance and the programmable resistance are not equal, and further such that the at least one switch resistance divides equally among the fixed resistance and the programmable resistance when the fixed resistance is equal to the programmable resistance to implement the desired circuit gain.
USPTO Backgrounds
USPTO Backgrounds