1. Field of the Invention
The present invention relates to a delay circuit.
2. Description of Related Art
Many of control devices of double data rate (DDR) memory adjust a phase between data and strobe by using a delay locked loop (DLL) circuit in order to capture writing and reading data at both rising and falling edges of a data strobe signal. A DLL circuit is also incorporated into memory for the purpose of compensating a phase difference between an input clock and output data and establishing synchronization. One of major components of such a DLL circuit is a delay circuit.
A delay circuit is configured as a string of inverters connected in series, for example. A larger number of inverters are necessary as a delay to be obtained is larger. Further, it is necessary to mount the number of inverters large enough to obtain a desired delay even if a delay is small due to manufacturing variation in circuits or environmental variation in temperature, voltage or the like. This causes an increase in the scale of the delay circuit and thus an increase in the layout area of the delay circuit in the DLL circuit. The issue of a large proportion of the layout area of the delay circuit in the DLL circuit is pointed out in Japanese Unexamined Patent Application Publication No. 2004-104748 or the like.
With recent downscaling of semiconductor circuits, an operating speed is increasing. On the other hand, the functions incorporated into semiconductor circuits are becoming increasingly various, and not all functions have become faster. A solid state drive (SSD) control device is one such example, and a serial interface with a bandwidth of several GHz and a flash memory interface with a bandwidth of several tens to several hundreds MHz are mounted on one semiconductor integrated circuit. In order to absorb a difference in bandwidth between the serial interface and the flash memory interface, the scale of a delay circuit of the SSD control device becomes larger, which inhibits higher integration of the control device. The dominating flash memory interface is changing from a single data rate (SDR) type to a double data rate (DDR) type, and therefore a delay circuit such as a DLL is necessary. As described above, a delay circuit with a small circuit scale is required for a semiconductor circuit such as an SSD control device that is used between a high-speed interface and a low-speed interface.
A technique to address the above concern is disclosed in Japanese Unexamined Patent Application Publication No. 63-316918. FIG. 12 shows a delay circuit 1 that is disclosed in Japanese Unexamined Patent Application Publication No. 63-316918. Referring to FIG. 12, the delay circuit 1 includes an input terminal A, output terminals B1 to Bn, counters CUNT1 and CUNT2, inverters INV1 to INV6, NAND circuits NAND1 and NAND2, OR circuits OR1 to ORn, and delay flip-flops FF1 to FFn.
A high-level data input signal Din that is input to the input terminal A is input to the NAND circuit NAND1, the inverters INV3 and INV6, the delay flip-flop FF1 and the counter CUNT2. When the data input signal Din is input to the NAND circuit NAND1, a clock is generated by oscillation of a closed-loop circuit that is formed by the NAND circuit NAND1 and the inverters INV1 and INV2. The clock is input to the counter CUNT1 and counted. Before the counting operation, the reset operation of the counter CUNT1 is canceled by a low-level signal from the inverter INV3. On the other hand, the counter CUNT2 is set to the reset state by a high-level signal input to its reset terminal.
The counter CUNT1 outputs a signal from an output terminal Q1 at a specified predetermined clock number. The signal is input as a clock signal CPI to a clock input terminal of the delay flip-flop FF1 through the OR circuit OR1. In response to the clock signal CPI, the delay flip-flop FF1 captures the data input signal Din, stores it, and then outputs it as a data output signal D1out to the output terminal B1.
Then, if the data input signal Din becomes a low level, the reset operation of the counter CUNT2 is canceled. Further, by a high-level output signal from the inverter INV6, a clock is generated by oscillation of a closed-loop circuit that is formed by the NAND circuit NAND2 and the inverters INV4 and INV5. The clock is input to the counter CUNT2 and counted. On the other hand, the counter CUNT1 is set to the reset state by a high-level signal from the inverter INV3 input to its reset terminal.
The counter CUNT2 outputs a signal from its output terminal at the same predetermined clock number as the counter CUNT1. The signal is input as the clock signal CPI to the clock input terminal of the delay flip-flop FF1 through the OR circuit OR1. In response to the clock signal CPI, the delay flip-flop FF1 captures the low-level data input signal Din, stores it, and then outputs it as the data output signal D1out to the output terminal B1. In the same manner, delayed signals can be output as data output signals D2out to Dnout to the other output terminals B2 to Bn, respectively.
As described above, by combining the oscillation of the closed-loop circuit and the counter, the delay circuit 1 disclosed in Japanese Unexamined Patent Application Publication No. 63-316918 can generate a larger delay with a smaller circuit scale compared to a delay circuit composed only of inverters.
USPTO Backgrounds
USPTO Backgrounds