This invention relates to a method of lapping a wafer and, in particular, to a wafer lapping method including the step of lapping irregularities of a surface of the wafer to flatten the surface of the wafer with a semiconductor device formed on the surface of the wafer.
In a manufacturing process of a semiconductor device, use is made of a wafer lapping method of lapping, by the use of a wafer lapping device, irregularities resulting from the presence of elements and wirings formed on a surface of a wafer to flatten the surface of the wafer.
As will later be described, a conventional wafer lapping method is incapable of achieving a stable abrasion rate without increasing the running cost.
USPTO Backgrounds
USPTO Backgrounds