1. Field of the Invention
The invention relates to a display device having a thin film transistor and a storage capacitor storing a display signal applied to a pixel electrode through this thin film transistor on a substrate and a method of manufacturing the same.
2. Description of the Related Art
An active matrix type liquid crystal display device has a pixel selecting thin film transistor (hereafter, referred to as a “pixel TFT”) in each of a plurality of pixels disposed into a matrix on a glass substrate. It also has a storage capacitor formed for storing a display signal applied to a pixel electrode through the pixel TFT.
This liquid crystal display device and a method of manufacturing the device will be described referring to FIG. 5. A light-shielding metal layer 11 as a light-shielding layer made of molybdenum, chromium, or the like for blocking external light incident on a first substrate 10 is formed on a first substrate 10 in a pixel TFT portion. This light-shielding metal layer 11 prevents a light leakage current caused by light entering a pixel TFT 100T. Then, a buffer film 53 made of an insulation film such as a silicon oxide film, a silicon nitride film or the like is formed over the light-shielding metal layer 11 by, for example, PE-CVD (Plasma Enhanced Chemical Vapor Deposition). An amorphous silicon layer is then formed on the buffer film 53. The amorphous silicon layer is then crystallized by laser annealing to form a polysilicon layer 55. The polysilicon layer 55 is etched into an island-like pattern. The polysilicon layer 55 functions as an active layer of the pixel TFT 100T and a storage capacitor electrode in a storage capacitor 100C.
Then, a gate insulation film 56 made of a silicon oxide film or the like is formed over the polysilicon layer 55 by PE-CVD. This gate insulation film 56 serves as a storage capacitor film 56C in the storage capacitor 100C.
Then, a gate electrode 57 made of molybdenum, chromium or the like is formed on the gate insulation film 56 of the pixel TFT 100T. On the storage capacitor film 56C, an upper capacitor electrode 58 made of the same metal as that of the gate electrode 57 is formed. An impurity is then ion-implanted in the polysilicon layer 55 using the gate electrode 57 and the upper capacitor electrode 58 as a mask to form a source and a drain. This impurity is phosphorus or arsenic for an N-channel type thin film transistor. A region between the source and the drain serves as a channel.
Then, an interlayer insulation film 19 is formed over the gate electrode 57 and the upper capacitor electrode 58. Contact holes CH1 and CH2 are provided in the gate insulation film 56 and the interlayer insulation film 19, and a drain electrode 20D and a source electrode 20S are formed through these contact holes CH1 and CH2, being connected with the polysilicon layer 55. Then, according to needs, a passivation film 21 made of a silicon nitride film or the like and a planarization film 22 made of a photosensitive material or the like are formed over the source electrode 20S and the drain electrode 20D. A contact hole CH3 is provided in the passivation film 21 and the planarization film 22, and a pixel electrode 23 made of transparent metal such as ITO (Indium Tin Oxide) or the like is formed through the contact hole CH3, being connected with the source electrode 20S.
Furthermore, a second substrate 30 made of a transparent material such as glass is attached to the first substrate 10, sealing a liquid crystal layer LC. A common electrode 31 made of transparent metal such as ITO is formed on the second substrate 30, being opposed to the pixel electrode 23. A polarizing plate (not shown) is formed on the first substrate 10 and the second substrate 30.
An operation of this display device is as follows. When the pixel TFT 100T turns on in response to a pixel selection signal applied to the gate electrode 57, the alignment of the liquid crystal molecules of the liquid crystal layer LC is controlled in response to a display signal applied to the pixel electrode 23 through the source electrode 20S. At this time, the display signal is applied to the pixel electrode 23 for a predetermined period by being stored in the storage capacitor 100C. In this manner, a transmission amount of light from a backlight BL in a pixel is controlled, thereby making a black or white display. The relevant technology is described in Japanese Patent Application Publication No. Hei 11-111998.
When the polysilicon layer 55 having crystal grain size of 300 to 400 nm is formed by crystallizing the amorphous silicon layer by laser annealing, protrusions occur in a polysilicon grain boundary portion on the surface of the polysilicon layer 55, of which the height is twice the thickness of the polysilicon layer 55. These protrusions cause degradation of the coverage of the storage capacitor film 56C layered on the storage capacitor electrode and reduce dielectric strength between the polysilicon layer 55 (the storage capacitor electrode) and the upper storage capacitor electrode 58, and the yield may reduce. When the polysilicon layer 55 is formed under the condition of enhancing the flatness of the surface, the crystal grain size is reduced and thus the resistance of the storage capacitor electrode is increased. This increases contact resistance between the thin film transistor and the storage capacitor, and the yield may reduce.
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