As is known, a memory device testing basically involves execution of two types of operations: verifying possible read fails, which, as is known, are caused by defects that are eliminated by resorting to redundancy elements purposely provided in the memory device design stage, and, in the event of read fails being detected, analysing such fails so as to perform a sort of screening of the defects that arise during the manufacture of the memory device.
Read fail analysis basically envisages executing three operations: storing in the memory device a bitmap having a regular pattern, for example, a bitmap containing all zeros or all ones, or else all zeros except for a diagonal of ones, alternating zeros and ones (checkerboard pattern), etc., then reading the bitmap from the memory device, and, finally, analysing the deviation of the bitmap from the stored bitmap.
Read fail analysis, as well as verify of the possible presence of read fails, is performed using a tester connected on one side to the memory device to be tested and on the other side to a personal computer or a workstation.
FIG. 1 schematically illustrates by way of example the circuit arrangement for testing an embedded memory device, i.e., a memory device which, in use, is associated to an electronic device, typically a microcontroller or a dedicated logic, which sends to the memory device the addresses of the memory locations in which the data to be read are stored and acquires the data outputted by the latter.
In particular, in FIG. 1, the reference number 1 designates the embedded memory device; number 2 designates the memory to be tested forming part of the embedded memory device 1, which may be either of a nonvolatile type, for example a Flash memory, or of a volatile type, for example a static memory (SRAM) or a dynamic memory (DRAM); number 3 designates the microcontroller, which is associated to the memory 2 and also forms part of the embedded memory device 1; number 4 designates the tester; and finally number 5 designates the personal computer.
Tester 4 carries out autonomously the entire operation of verifying the possible presence of read fails, whilst, during the subsequent operation of read fail analysis, basically carries out the functions of accumulating the compressed data and generating a corresponding file, which is then supplied to the personal computer or to the workstation for a subsequent processing, for example, display or, if need be, a specific processing.
In detail, microprocessor 3 reads the state of the memory 2 and compresses the read data, and the compressed data are then stored in the internal memory of the microprocessor 3. When data compression is completed or the internal memory of the microprocessor 3 is full, a signal indicating this situation is generated by the microprocessor 3 and supplied to the tester 4, which reads from the internal memory of the microprocessor 3 the compressed data and saves them in a file. At the end of the operations, the file thus generated is supplied to the personal computer or to the workstation 5.
The testers 4 currently available on the market differ, among other things, basically for the speed with which they are able to supply to the personal computer 5 the data read from the memory device 2. In particular, amongst the testers currently available on the market, the ones which are operatively slower require even around 100 ms for supplying to the personal computer 5 even just one datum read, in so far as they use a serial communication protocol and have an extremely simple internal logic.
A very effective method that is currently used to increase the amount of data transmitted in unit time by the tester 4 to the personal computer 5 is represented by the implementation of the so-called data compression algorithms, the most widely used of which are essentially based upon the principle of sending to the personal computer just the bits or groups of bits for which a read fail has been verified and a corresponding address with respect to a reference bitmap.
The data compression algorithms based upon comparison of the bitmap read with a reference bitmap require first of all generation of the reference bitmap and their performances depend to a large extent upon the degree of “resemblance” of the bitmap read with the reference bitmap, and, in particular, their performances are satisfactory only in the case in which the bitmap read is not very different from the reference bitmap.
USPTO Backgrounds
USPTO Backgrounds