The present invention relates generally to semiconductor devices, and more particularly, it relates to semiconductor devices that allow system access to built-in self test circuitry for random access memories.
Integrated circuits such as application specific integrated circuits typically include an IEEE standard 1149.1 test access port (TAP) controller to allow production testing of memory components of the integrated circuit, such as random access memory (RAM). In addition, such integrated circuits typically also include a built-in self test (BIST) controller, which provides control for the self testing of the RAM memory. In such systems, the TAP controller can receive production tests and board level tests signals and can then enable the BIST controller to perform the built-in self test of the RAM cells.
In addition to production testing, system testing of RAM cells is also required. However, the production test provided in accordance with IEEE standard 1149.1 typically is not compatible with system testing. Thus, it is necessary to provide redundant logic for performing BIST testing of RAM cells from a system initiated signal, and for system monitoring of the BIST status and results.
In accordance with the present invention, an apparatus and method for system access to TAP-controlled BIST of random access memory are provided that overcome known problems with providing system access to BIST.
In particular, an apparatus and method for system access to TAP-controlled BIST of random access memory are provided that allow the TAP-controlled BIST logic to be utilized for system-initiated BIST of RAM.
In accordance with an exemplary embodiment of the present invention, an integrated circuit having functional logic that provides system access to test access port controlled built-in-self-test logic is provided. The integrated circuit includes a test access port controller having an enable output and a status input. A built-in-self-test controller having an enable input, a status output, one or more random access memory cell controller outputs and one or more random access memory cell inputs is also provided. A functional logic interface is connected to the functional logic, the test access port controller enable output, and the built-in-self-test controller enable input, and allows a built-in self-testing sequence to be initiated from the test access port controller or the system.
The present invention provides many important technical advantages. One important technical advantage of the present invention is an apparatus and method for providing system access to TAP-controlled BIST that does not require additional BIST logic to be provided for system-initiated BIST of RAM. The present invention is IEEE standard 1149.1 compliant, and reduces the cost and number of logical components required to provide for system access to BIST of RAM.
USPTO Backgrounds
USPTO Backgrounds