This invention relates to a method of manufacturing a semiconductor device and, more particularly, to improvements in isolation techniques in the manufacture of bipolar type or MOS type ICs and LSIs.
In the manufacture of a semiconductor device, particularly a bipolar IC, the isolation of elements is usually realized by a p-n junction and an oxide film formed by a selective oxidation process. This process will now be described in connection with the manufacture of a bipolar vertical npn transistor.
First, in a p-type silicon substrate 1 an n-type buried region 2 of high impurity concentration is selectively formed as shown in FIG. 1A. An n-type semiconductor layer 3 is then epitaxially grown. A silicon oxide film 4 is then formed to a thickness of approximately 1,000 .ANG., and then an oxidation-resistive silicon nitride film 5 is deposited to a thickness of approximately 1,000 .ANG.. The silicon oxide film 4 and silicon nitride film 5 are then patterned using the photoetching technology to form a silicon oxide film pattern 4a, 4b and a silicon nitride film pattern 5a, 5b as shown in FIG. 1B. The n-type semiconductor layer 3 is then selectively etched to a depth of approximately 5,000 .ANG. using the silicon oxide film pattern 4a, 4b and silicon nitride film pattern 5a, 5b as a mask. Then, boron is ion implanted using the patterns 4a, 4b and 5a, 5b as a mask to form p-type regions 6a and 6b as shown in FIG. 1C. Subsequently, a silicon oxide film 7a to 7c is selectively grown to a thickness of approximately 1 .mu.m through thermal oxidation carried out in steam or like wet atmosphere, as shown in FIG. 1D. The silicon nitride film pattern 5a, 5b is then removed, for instance using hot phosphoric acid, and a base region 8 is formed in that portion of the semiconductor layer 3 which has been under the silicon nitride film pattern 5a. Further, an n-type region 9 to serve as an emitter and an n-type region 10 to serve as a collector are formed by ion implantation of arsenic. A contact window is further formed in the silicon oxide film 4a. Then, an emitter electrode 12, a base electrode 11 and a collector electrode 13 are formed to obtain a vertical npn transistor as shown in FIG. lE. In this case, the isolation of the npn transistor is realized by the combination of the oxide film portions 7a and 7c with the thickness of approximately 1 .mu.m and p-type regions 6a and 6b. If the thickness of the n-type semiconductor layer 3 is of the order of 1 to 2 .mu.m, the isolation can be obtained with the oxide film only by forming the oxide film to be contiguous to the p-type substrate 1. Also, even in this case, it is desirable to form channel stop regions between the p-type substrate and oxide film by ion implanting a p-type impurity.
The method of manufacturing a bipolar IC using a selective oxidation process as described above, however, has various drawbacks as described in the following.
FIG. 2 shows a detailed sectional structure that is obtained when the field oxide film 7a, 7b is formed using the Si.sub.3 N.sub.4 film pattern 5a, 5b as a mask. Here, no process of etching the silicon layer 3 has been carried out. It is well known in the art that in a selective oxidation process an oxide film "wedges into" a region underneath Si.sub.3 N.sub.4 film pattern (as shown at F in FIG. 2). This portion of the oxide film 7b consists of a commonly termed bird's beak D, which is formed as the oxidizing agent and is diffused through the thin SiO.sub.2 film 4a under the Si.sub.3 N.sub.4 pattern 5a, and a portion E which is formed as the thick portion of the oxide film 7b extends laterally. When the oxide film 7b is grown to a thickness of 1 .mu.m with the Si.sub.3 N.sub.4 film 5a formed to have a thickness of 1,000 .ANG. and the SiO.sub.2 film 4a under the film 5a formed to have a thickness of 1,000 .ANG., the lateral dimension of the portion F increases to approximately 1 .mu.m. Therefore, if the distance A between the Si.sub.3 N.sub.4 pattern portions 5a and 5b is 2 .mu.m, the isolation region C inevitably has a width of at least 4 .mu.m because the portion F has a width of 1 .mu.m. This is a serious restriction on the integration density of an LSI. There have been attempts to suppress the bird's beak (i.e., portion D) by increasing the thickness of the Si.sub.3 N.sub.4 film pattern 5a, 5b while reducing the thickness of the SiO.sub.2 film and also to suppress the "wedging" portion F by reducing the thickness of growth of the oxide film 7b. However, in the former case an excessive stress results at the wedging portion of the isolation region. In this case, generation of defects is prone. In the latter case, the field inversion voltage is reduced. In addition, the wiring capacitance in the isolation region is increased. In either case, the selective oxidation process imposes restrictions on the integration density.
The problems that arise due to formation of the bird's beak will now be discussed in connection with a prior art method of manufacturing a bipolar transistor using a selective oxidation process as shown in FIGS. 3A and 3B.
In the illustrated method, a SiO.sub.2 film 22, 22b is formed by the conventional selective oxidation process on a semiconductor layer 21 which is also an n-type collector region as shown in FIG. 3A. With this oxide film as a mask, boron is ion implanted to form a p-type base region 23. Subsequently, an n-type emitter region 25 is formed by a diffusion process or an ion implantation process as shown in FIG. 3B. A SiO.sub.2 film 24 is formed as an insulating film for insulating the base and emitter electrodes from each other.
Problems in this method of manufacturing the bipolar transistor using the selective oxidation process reside mainly in the shape of the bird's beak of the SiO.sub.2 film 22a, 22b and the stress in the semiconductor. region in the neighborhood of the bird's beak as well as resultant generation of defects. The depth D of the base junction right beneath the bird's beak is less than the depth C of the base junction right beneath the principal surface of the semiconductor substrate by the thickness of the oxide film of the bird's beak. The value of the depth D is further reduced since the surface of the silicon oxide film is etched in the etching process during manufacture. If an aluminum electrode is formed as a base electrode, the aluminum is therefore liable to penetrate the base region due to reaction between aluminum and silicon. This would result in a defective element. In addition to the smaller depth of the base junction right beneath the bird's beak, the end of the bird's beak recedes in the etching process in manufacture. Therefore, the depth of the emitter junction beneath the bird's beak becomes greater than that beneath the other portions. Further, due to defects caused by stress produced in the selective oxidation process, abnormal diffusion takes place in the emitter region increasing the depth of the emitter junction. Therefore, the depth dimension B of the base right beneath the bird's beak becomes less than the normal base depth A. For the above reasons, defective collector-emitter breakdown voltage on the npn transistor becomes probable. This problem is encountered when the selective oxidation process is employed in the manufacture of a bipolar IC.
To overcome the above drawbacks, one of the inventors earlier proposed a method of manufacturing a bipolar semiconductor device (such as a vertical npn transistor), in which the isolation regions are formed in a novel process which will now be described with reference to FIGS. 4A to 4E.
First, in a p-type semiconductor substrate 101 a high-impurity concentration buried layer 102 doped with an n-type impurity is formed as shown in FIG. 4A. Atop the system an n-type epitaxial layer 103 is grown to a thickness of approximately 2.5 .mu.m. A resist pattern 104a, 104b, 104c is then formed by a photoetching process on the semiconductor layer 103. The semiconductor layer 103 is then selectively etched by an anisotropic reactive ion etching process with the resist pattern 104a, 104b, 104c as the etching mask. Thus, grooves 105a and 105b with a width of approximately 1 .mu.m and a depth of approximately 3 .mu.m are formed to isolate an island region of the n-type semiconductor layer 103, as shown in FIG. 4B. At this time, it is desirable to form p-type channel stop regions 106a and 106b by ion implanting boron.
Subsequently, the resist pattern 104, 104b, 104c is removed, and then a SiO.sub.2 film 107 is deposited by the CVD process to a thickness sufficiently greater than one half of the width of the isolating grooves 105a and 105b (which is approximately 5,000 .ANG.). At this time, SiO.sub.2 is gradually deposited on the surfaces of the grooves 105a and 105b to eventually fill the grooves. The SiO.sub.2 film 107 thus formed has a substantially flat surface. During the deposition process, re-distribution of the impurity in the p-type regions 106a and 106b hardly occurs unlike in the selective oxidation process in which thermal oxidation is carried out at a high temperature and for a long time. The SiO.sub.2 film 107 is then etched using ammonium fluoride until the semiconductor layer 103, other than the grooves 105a and 105b, is exposed. In this step, only the thickness of the SiO.sub.2 film 107 atop the semiconductor layer 103 is removed to leave SiO.sub.2 in the grooves 105a and 105b as shown in FIG. 4D. Thus, isolating layers 107a and 107b buried in the semiconductor layer 103 are formed.
Thereafter, a p-type base region 108 is formed by ion implanting boron in a resist block process in the semiconductor region isolated by the isolating regions 107a and 107b. An insulating film 109 is then formed to a thickness of approximately 3,000 .ANG. on the entire wafer surface. Emitter and collector impurity diffusion windows are formed by using a photoetching process. Arsenic is then ion implanted through the windows to form an n-type regio 110 which serves as emitter and an n-type region 111 which serves as collector. The insulating film 109 is then formed with a window for the p-type base region 108. An electrode material such as Al is then deposited on the wafer surface and patterned by a photoetching process to form a base electrode 112, an emitter electrode 113 and a collector electrode 114, as shown in FIG. 4E. An npn bipolar transistor is obtained in this way.
The method described above has various effects as described in the following.
Firstly, since the area of the isolating regions is determined by the area of the grooves formed in the semiconductor layer, narrow isolating regions can be readily formed by reducing the area of grooves. Thus, it is possible to obtain a bipolar semiconductor device having an increased integration density.
Secondly, since the depth of the isolating regions is determined independently of their area but solely by the depth of grooves formed in the semiconductor layer, it can be selected to a desired value. In addition, current leaks among individual semiconductor elements can be reliably prevented by the isolation regions. Thus, it is possible to obtain a high-performance bipolar semiconductor device.
Thirdly, the method is free from a high temperature and long time thermal oxidation treatment as in the ordinary selective oxidation process. Thus, the channel stop region impurity that has been selectively doped through the grooves will never re-diffuse laterally to reach the buried layer or active transistor regions in the isolated transistor region. This has the effect of preventing the reduction of the isolated element region. If the impurity doping is done by ion implantation, an impurity ion implantation layer can be formed at the bottom of each groove. In this case, even if re-diffusion of the impurity in the ion implantating layer is caused, the re-diffusion region will never develop to reach the surface layer in the isolated element region (i.e., active regions of transistor). Thus, it is possible to prevent deterioration of the impurity doped regions of the transistor as well as preventing the effective reduction of the isolated element region.
Fourthly, the isolating regions formed by leaving an insulating material in the entire grooves can be flush with the isolated element region. Thus, it is possible to eliminate disconnection of subsequently formed electrode at the boundary between the isolated element region and an isolating region.
While the above method has the various advantages described, it still is defficient when an isolating region having a large width is formed, though there is no problem when all the isolating regions have a small width. Since the width S of an isolating region is determined by the width S of the corresponding groove, in order to completely fill the groove with an insulating film, the thickness T of the insulating film must be set to be T&gt;1/2S. If it is intended to form an isolating region having a large width, it is necessary to deposit an insulating film to a considerable thickness. For example, in order to form an isolating region having a width of 20 .mu.m, it is necessary to deposit an insulating film to a thickness of at least 10 .mu.m. In this case, many difficulties are encountered in connection with the deposition period, precision of the film thickness, conditions free from the generation of cracks and so forth. Furthermore, by the above method it is very difficult to form an isolating region having as large a width as 200 .mu.m (such as the one under an aluminum bonding pad). If an isolating region having a large width is necessary, therefore, it is formed by a method as shown in FIG. 5. Here, after narrow isolating layers 107a, 107b and 107c have been formed in respective grooves, an insulating film (for instance a SiO.sub.2 film) is deposited and selectively photoetched to form an isolating region 107' having a large width.
Although an isolating region having a large width can be formed by this method, the isolating region thus obtained is not flush with the isolated element region, that is, a difference in level is produced between the isolating region and the isolated element region. When using the selective oxidation process, one half of the isolating layer (field oxide layer) is buried in the semiconductor layer, but according to the method of FIG. 5 the entirety of the insulating film 107' constitutes the difference in level. In other words, FIG. 5, the difference in level is more than when using the selective oxidation process. This is a serious drawback when microlithography is required in the neighborhood of the wide isolating layer.
USPTO Backgrounds
USPTO Backgrounds