1. Field of the Invention
The present invention relates to a differential output circuit which outputs a differential signal in response to a differential input signal.
2. Description of the Related Art
In association with a high-speed operation of a semiconductor integrated circuit, a differential signal is often used in an interface between circuits. The differential signal is superior in noise resistance and hard to receive the influence of variation in manufacturing the circuit. A differential output circuit for generating the differential signal is disclosed in Japanese Laid Open Patent Application (JP P2004-128747A). FIG. 1 is its circuit diagram. As shown in FIG. 1, the differential output circuit is provided with N-channel MOS transistors N11a, N11b, N12a and N12b, and P-channel MOS transistors P11a, P11b and a resistance element R.
The MOS transistors P11a, N12a and N11a are connected in series between a higher voltage power source VDD and a lower voltage power source VSS. That is, a source of the N-channel MOS transistor N11a is connected to the lower voltage power source VSS, and a drain of the N-channel MOS transistor N11a is connected to a source of the N-channel MOS transistor N12a. A source of the P-channel MOS transistor P11a is connected to the higher voltage power source VDD, and a drain of the P-channel MOS transistor P11a is connected to a drain of the N-channel MOS transistor N12a. Similarly, the MOS transistors P11b, N12b and N11b are connected in series between the higher voltage power source VDD and the lower voltage power source VSS. That is, a source of the N-channel MOS transistor N11b is connected to the lower voltage power source VSS, and a drain of the N-channel MOS transistor N11b is connected to a source of the N-channel MOS transistor N12b. A source of the P-channel MOS transistor P11b is connected to the higher voltage power source VDD, and a drain of the P-channel MOS transistor P11b is connected to a drain of the N-channel MOS transistor N12b. 
A gate of the N-channel MOS transistor N12a and a gate of the N-channel MOS transistor N12b are connected to the higher voltage power source VDD. Thus, the N-channel MOS transistor N12a and the N-channel MOS transistor N12b are always on and function as resistance elements. An input terminal INa is connected to a gate of the N-channel MOS transistor N11a, and an input terminal INb is connected to a gate of the N-channel MOS transistor N11b. An input signal supplied from the input terminal INa and an input signal supplied from the input terminal INb serve as a differential signal and have phases opposite to each other.
A node a between the N-channel MOS transistor N12a and the N-channel MOS transistor N11a is connected to the gate of the P-channel MOS transistor P11b. A node b between the N-channel MOS transistor N12b and the N-channel MOS transistor N11b is connected to the gate of the P-channel MOS transistor P11a. A node between the N-channel MOS transistor N12a and the P-channel MOS transistor P11a is connected to an output terminal OUTb, and a node between the N-channel MOS transistor N12b and the P-channel MOS transistor P11b is connected to an output terminal OUTa. The resistance element R is connected between the output terminal OUTa and the output terminal OUTb.
An operation of the differential output circuit will be described below. The circuit shown in FIG. 1 could be considered to be the synthesis of two circuits section for two signal routes. The first signal route is the signal route for receiving a signal from the input terminal INa and outputting the signal from the output terminal OUTa. The second signal route is the signal route for receiving a signal from the input terminal INb and outputting the signal from the output terminal OUTb.
In the first signal route, the N-channel MOS transistor N11a constitutes a source grounded amplifying circuit having, as a load resistor, the N-channel MOS transistor N12a and the P-channel MOS transistor P11a. Its output is obtained from the connection node a between the load resistor and the N-channel MOS transistor N11a. The signal on this node a is supplied to the gate of the P-channel MOS transistor P11b. The P-channel MOS transistor P11b constitutes a source grounded amplifying circuit having, as a load resistor, the N-channel MOS transistor N11b and the N-channel MOS transistor N12b. Thus, the signal supplied from the input terminal INa is amplified by the two-stage amplifying circuit composed of the N-channel MOS transistor N11a and the P-channel MOS transistor P11b, and outputted from the output terminal OUTa. The output signal outputted to the output terminal OUTa is negatively fed back through the resistance element R to the input side. Thus, the gain of the two-stage amplifying circuit is suppressed, thereby enlarging the flat band range in a frequency property.
Similarly, in the second signal route, the N-channel MOS transistor N11b constitutes a source grounded amplifying circuit having, as a load resistor, the N-channel MOS transistor N12b and the P-channel MOS transistor P11b. Its output is obtained from the connection node b between the load resistor and the N-channel MOS transistor N11b. The signal on this node b is supplied to the gate of the P-channel MOS transistor P11a. The P-channel MOS transistor P11a constitutes a source grounded amplifying circuit having, as a load resistor, the N-channel MOS transistor N11a and the N-channel MOS transistor N12a. Thus, the signal supplied from the input terminal INb is amplified by the two-stage amplifying circuit composed of the N-channel MOS transistor N11b and the P-channel MOS transistor P11a, and outputted from the output terminal OUTb. The output signal outputted to the output terminal OUTb is negatively fed back through the resistance element R to the input side. Thus, the gain of the two-stage amplifying circuit is suppressed, thereby enlarging the flat band range in the frequency property.
The signal supplied to the input terminal INa and the signal supplied to the input terminal INb serve as the differential signal and have the phases opposite to each other. In those input signals, small signals are superimposed on offset voltage signals. Thus, if the signal supplied to the input terminal INa is higher than its offset voltage signal, the signal supplied to the input terminal INb is lower than the offset voltage signal. For this reason, the voltage of the node b is higher than the voltage when the offset voltage signal is applied to the input terminal INb. The voltage of the node b is applied to the gate of the P-channel MOS transistor P11a serving as the load resistor of the N-channel MOS transistor N11a, so that the ON resistance of the P-channel MOS transistor P11a is high. Therefore, the amplification factor of the signal supplied from the input terminal INa through the N-channel MOS transistor N11a is made higher. In short, the amplifying operation is made stronger as compared with a case where only the single N-channel MOS transistor N11a is use. The frequency performance of this circuit has the flat gain of about 12 dB to about 2 GHz, as shown by a dashed line in FIG. 3, when proper parameters are set and SPICE is used to carry out a simulation.
As mentioned above, the differential output circuit shown in FIG. 1 can process the signal in the wide frequency band. Usually, a differential signal supplied to the input terminals INa and INb has offsets that are approximately equal. However, as shown in FIG. 4A, if the offsets of the differential signal supplied to the input terminals INa and INb are different (difference x), the offsets are also amplified, because this differential output circuit has the flat amplifying property over the wide frequency band from a DC component to an AC component. For this reason, the difference between the offsets is also amplified, which increases the difference. In particular, when the frequency of the small signal contains the component of 2 GHz or higher, the amplification factor of the small signal is made lower than the amplification factor of the DC component. Therefore, as shown in FIG. 4C, the difference of the offset is amplified to x″, and the signal component is amplified to y″. In this case, the duty of the differential signal is deteriorated.
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