1. Field of the Invention
The present invention relates to a class-AB push-pull drive circuit operable with a decreased input voltage as with a low power supply voltage.
2. Description of the Background Art
FIG. 2 is a circuit diagram of a conventional class-AB push-pull drive circuit disclosed in Japanese Patent Application No. 2-189908 by the applicant of the present application. The class-AB push-pull drive circuit of FIG. 2 comprises a buffer circuit 10, a voltage-to-current converter 20, and an inverting amplifier (or a current-to-voltage converter) 30.
The buffer circuit 10 includes an N-channel MOS transistor Q.sub.3, a P-channel MOS transistor Q.sub.4, and constant current sources I.sub.1, I.sub.4. The gate of the transistor Q.sub.3 is connected to an input terminal 1; the source thereof is connected to the source of the transistor Q.sub.4 and is grounded through the constant current source I.sub.4 ; and the drain thereof is connected to a power supply terminal 100 for supplying a power supply voltage V.sub.cc. The gate and drain of the transistor Q.sub.4 are connected in common and are connected to the gate of the N-channel MOS transistor Q.sub.1 serving as a first source-grounded transistor and are grounded through the constant current source I.sub.1.
The voltage-to-current converter 20 includes N-channel MOS transistors Q.sub.5, Q.sub.8, and resistors R.sub.1, R.sub.3, R.sub.4. The gate of the transistor Q.sub.8 is connected to the drain thereof and to the gate of the transistor Q.sub.5. The connecting point is connected to the source of the transistor Q.sub.3 in the buffer circuit 10 through the resistor R.sub.1 . The source of the transistor Q.sub.8 is grounded through the resistor R.sub.3, and the source of the transistor Q.sub.5 is grounded through the resistor R.sub.4.
The inverting amplifier (current-to-voltage converter) 30 includes P-channel MOS transistors Q.sub.6, Q.sub.7, a constant current source I.sub.2, and a resistor R.sub.2. The source of the transistor Q.sub.6 is connected to the power supply terminal 100, and the drain thereof is connected to the gate of the P-channel MOS transistor Q.sub.2 serving as a second source-grounded transistor and to one end of the resistor R.sub.2. The other end of the resistor R.sub.2 is connected to the gate of the transistor Q.sub.7 and to the drain of the transistor Q.sub.5 in the voltage-to-current converter 20 and is also grounded through a constant current source I.sub.3. The source of the transistor Q.sub.7 is connected to the gate of the transistor Q.sub.6 and is connected to the power supply terminal 100 through the constant current source I.sub.2, and the drain thereof is grounded.
The drain of a transistor Q.sub.1 is connected to an output terminal 2, and the source thereof is grounded. The drain of a transistor Q.sub.2 is connected to the output terminal 2, and the source thereof is connected to the power supply terminal 100.
As output-side drive transistors in the class-AB push-pull drive circuit, the P-channel transistor Q.sub.2 serving as the second source-grounded transistor is provided between the output terminal 2 and the power supply terminal 100, and the N-channel transistor Q.sub.1 serving as the first source-grounded transistor is provided between the output terminal 2 and the ground. The buffer circuit 10, the voltage-to-current converter 20 and the inverting amplifier (current-to- converter) 30 are provided so that a potential difference between the bases of the transistors Q.sub.1 and Q.sub.2 is always held constant independently of the input voltage of the input terminal 1. The buffer circuit 10 converts a high-impedance input signal into a low-impedance signal and applies a voltage in accordance with the input voltage of the input terminal 1 to the gate of the transistor Q.sub.1. The voltage-to-current converter 20 produces a current in accordance with the input voltage. The inverting amplifier (current-to-voltage converter) 30 converts the current again into a voltage which, when the input voltage is raised (or drops) and then a gate-source voltage V.sub.GS1 increases (or decreases), accordingly causing a source-gate voltage V.sub.SG2 of the transistor Q.sub.2 to decrease (or increase). This permits the voltage sum (V.sub.GS1 +V.sub.SG2) to be always held constant, so that the potential difference between the gates of the transistors Q.sub.1 and Q.sub.2 (i.e., V.sub.CC -(V.sub.GS1 +V.sub.SG2)) is also always held constant.
With respect to a source voltage V.sub.S3 of the transistor Q.sub.3 in the buffer circuit 10 of the class-AB push-pull drive circuit, a source-gate voltage of the transistors Q.sub.4 in the buffer circuit 10 is designated as V.sub.SG4 ; the gate-source voltage of the transistor Q.sub.1 for output drive is designated as V.sub.GS1 ; a gate-source voltage of the transistor Q.sub.8 in the voltage-to-current converter 20 is designated as V.sub.GS8 ; and a drain-source current thereof is designated as I.sub.DS8. Then the following relations hold. EQU V.sub.S3 =V.sub.SG4 +V.sub.GS1 ( 1) EQU V.sub.S3 =V.sub.GS8 +I.sub.DS8 .multidot.(R.sub.1 +R.sub.3)(2)
where R.sub.1, R.sub.3 are resistances of the resistors R.sub.1, R.sub.3 in the voltage-to-current converter 20, respectively.
From Expressions (1) and (2), the drain-source current I.sub.DS8 of the transistor Q.sub.8 is given as: ##EQU1## It is assumed that the transistors Q.sub.5 and Q.sub.8 in the voltage-to-current converter 20 provide a current mirror having a 1:1 mirror ratio. A drain current of the transistor Q.sub.5 is designated as I.sub.D5. Then the following relation holds. EQU I.sub.D5 =I.sub.DS8 ( 4)
The source-gate voltage of the transistor Q.sub.2 for output drive is designated as V.sub.SG2 ; a source-gate voltage of the transistor Q.sub.6 in the inverting amplifier 30 is designated as V.sub.SG6 ; a drain current thereof is designated as I.sub.D6 ; and a source-gate voltage of the transistor Q.sub.7 in the inverting amplifier 30 is designated as V.sub.SG7. Then the following relation holds. EQU V.sub.SG2 =V.sub.SG6 +V.sub.SG7 -R.sub.2 .multidot.I.sub.D6( 5)
where R.sub.2 is a resistance of the resistor R.sub.2 in the inverting amplifier 30.
A constant bias current from the constant current source I.sub.3 is designated as I.sub.B3. The drain current I.sub.D6 is expressed as: EQU I.sub.D6 =I.sub.D5 +I.sub.B3 ( 6)
Therefore ##EQU2##
A drain current of the transistor Q.sub.1 is designated as I.sub.D1 ; a constant determined by the configuration of the transistor Q.sub.1 is designated as .beta..sub.1 ; a drain current of the transistor Q.sub.2 is designated as I.sub.D2 ; a constant determined by the configuration of the transistor Q.sub.2 is designated as .beta..sub.2 ; a constant determined by the configuration of the transistor Q.sub.4 is designated as .beta..sub.4 ; a constant determined by the configuration of the transistor Q.sub.6 is designated as .beta..sub.6 ; a constant determined by the configuration of the transistor Q.sub.7 is designated as .beta..sub.7 ; and a constant determined by the configuration of the transistor Q.sub.8 is designated as .beta..sub.8. A threshold voltage of the N-channel MOS transistors is designated as V.sub.THON ; and a threshold voltage of the P-channel MOS transistors is designates as V.sub.THOP. Since the source-drain currents of the transistors Q.sub.4 and Q.sub.7 are respectively equal to the constant bias currents I.sub.B1 and I.sub.B2 given from the constant current sources I.sub.1 and I.sub.2, the following relationships hold. ##EQU3##
Expressions (8) to (13) are respectively transformed into: ##EQU4##
Substitution of Expression (6) into Expression (17) gives: ##EQU5##
Substitution of Expression (4) into Expression (20) gives: ##EQU6##
Substitution of Expressions (14) to (16), (18), (19), (21) into Expression (7) gives: ##EQU7##
Setting R.sub.1 +R.sub.3 =R.sub.2 for the purpose of simplification, the following relation holds. ##EQU8## Since I.sub.B1, I.sub.B2, I.sub.B3 are constant currents, the value on the right side of Expression (24) is approximately constant when variation of I.sub.DS8 is small. Accordingly ##EQU9##
Inserting R.sub.1 +R.sub.3 =R.sub.2 in Expression (7) for the purpose of simplification, Expression (7) is transformed into: EQU V.sub.GS1 +V.sub.SG2 =V.sub.SG6 +V.sub.SG7 -V.sub.SG4 +V.sub.GS8 -R.sub.2 .multidot.I.sub.B3 ( 26)
Since I.sub.B1 and I.sub.B2 are the constant currents, V.sub.SG4 and V.sub.SG7 are constant from Expressions (16) and (18). If the variation of I.sub.DS8 is small as above described, V.sub.GS8 and V.sub.SG6 are also approximately constant from Expressions (19) and (20). Suitable setting of R.sub.2 and I.sub.B3 permits the value (V.sub.GS1 +V.sub.SG2) to be always held constant. The potential difference between the gates of the transistors Q.sub.1 and Q.sub.2, which is equal to V.sub.CC -(V.sub.GS1 +V.sub.SG2), is always held constant by keeping the sum (V.sub.GS1 +V.sub.SG2) constant.
A current flowing between the drains of the transistors Q.sub.2 and Q.sub.1 when there is no load current flow in the output terminal 2 is referred to as an idle current I.sub.idle expressed as: EQU I.sub.idle =I.sub.D1 =I.sub.D2 ( 27)
From Expression (24) is derived: ##EQU10## The idle current is minimized by increasing R.sub.2 and I.sub.B3 as shown by Expression (28).
When a load is connected to the output terminal 2 and an outflow current I.sub.source is present, the source-gate voltage V.sub.SG2 of the transistor Q.sub.2 increases. Since the potential difference between the gates of the transistors Q.sub.1 and Q.sub.2 is then approximately constant as described with reference to Expression (26), the gate-source voltage V.sub.GS1 of the transistor Q.sub.1 decreases and the drain current I.sub.D1 of the transistor Q.sub.1 accordingly decreases.
In this state, if a source-drain voltage of the transistor Q.sub.2 is designated as V.sub.SD2, a maximum voltage V.sub.2max of the output terminal 2 is given as: EQU V.sub.2max =V.sub.CC -V.sub.SD2 ( 29)
Since the source-drain voltage V.sub.SD2 of the transistor Q.sub.2 is permitted to be sufficiently low (for example, 0.2 V or less), a high voltage approximately equal to the power supply voltage V.sub.CC is output.
Conversely, when a load is connected to the output terminal 2 and an inflow current I.sub.sink is present, the gate-source voltage V.sub.GS1 of the transistor Q.sub.1 increases. Since the potential difference between the gates of the transistors Q.sub.1 and Q.sub.2 is approximately constant as described with reference to Expression (26), the source-gate voltage V.sub.SG2 of the transistor Q.sub.2 decreases and the drain current I.sub.D2 of the transistor Q.sub.2 accordingly decreases.
In this state, if a drain-source voltage of the transistor Q.sub.1 is designated as V.sub.DS1, a minimum voltage V.sub.2min of the output terminal 2 is given as: EQU V.sub.2min =V.sub.DS1 ( 30)
Since the drain-source voltage V.sub.DS1 of the transistor Q.sub.1 is permitted to be sufficiently low (for example, 0.2 V or less), a low voltage approximate to the ground potential is output.
The operating voltage of the class-AB push-pull drive circuit of FIG. 2 will be described below. The respective transistors operate within a saturation region. Thus EQU V.sub.CC =V.sub.GS1 +V.sub.SG4 -I.sub.DS8 .multidot.R.sub.1 -V.sub.GS5 +V.sub.DS5 +I.sub.D6 .multidot.R.sub.2 +V.sub.SG2 ( 31)
where ##EQU11## where V.sub.GS5 is a gate-source voltage of the transistor Q.sub.5, V.sub.DS5 is a drain-source voltage thereof, and .beta..sub.5 is a constant determined by the configuration of the transistor Q.sub.5.
If a gate-source voltage of the transistor Q.sub.3 is designated as V.sub.GS3, an input voltage V.sub.1 is expressed as: EQU V.sub.1 =V.sub.GS3 +V.sub.SG4 +V.sub.GS1 ( 40)
Since the transistors Q.sub.1, Q.sub.3, Q.sub.4 operate in the saturation region, the following relations hold. ##EQU12## Substitution of Expressions (41), (42), (43) into Expression (40) gives: ##EQU13##
A drain current I.sub.D3 of the transistor Q.sub.3 is separated into constant currents I.sub.B1, I.sub.B4 and a drain-source current I.sub.D8 of the transistor Q.sub.8 as expressed by: EQU I.sub.D3 =I.sub.B1 +I.sub.B4 +I.sub.DS8 ( 45)
Expression (44) is transformed into: ##EQU14##
As the input voltage V.sub.1 is decreased, the currents I.sub.D1 and I.sub.DS8 decrease. As a result, a voltage across the resistor R.sub.2 decreases, so that the source-gate voltage V.sub.SG2 of the transistor Q.sub.2 and, accordingly, the drain current I.sub.D2 thereof increase. Conversely, as the input voltage V.sub.1 is increased, the currents I.sub.D1 and I.sub.DS8 increase. As a result, the voltage across the resistor R.sub.2 increases, so that the source-gate voltage V.sub.SG2 of the transistor Q.sub.2 and, accordingly, the drain current I.sub.D2 thereof decrease.
In the conventional class-AB push-pull drive circuit having such arrangement, the operating power supply voltage V.sub.CC is calculated from Expression (31). Variable terms on the right side of Expression (31) are I.sub.DS8 .multidot.R.sub.1, V.sub.DS5, and I.sub.D6 .multidot.R.sub.2. By setting the variable terms small, the operating power supply voltage V.sub.CC is considerably decreased. The input voltage V.sub.1 required to drive the first and second source-grounded transistors Q.sub.1 and Q.sub.2 as output transistors must be at some minimum levels since it is necessary for the input voltage V.sub.1 to operate the transistors Q.sub.3 and Q.sub.4 forming the buffer circuit 10 and the first source-grounded transistor Q.sub.1 within the saturation region. When the power supply voltage V.sub.CC is decreased approximately to the threshold level of Expression (31), the required minimum input voltage sometimes reaches or exceeds the power supply voltage. In such cases, the output voltage is fixed to a certain voltage level, so that the linear relationship between the input and output is broken. The conventional class-AB push-pull drive circuit has been disadvantageous in that it is not practical decrease the power supply voltage V.sub.CC significantly.
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USPTO Backgrounds