1. Field of the Invention
This invention relates to software tools and data structures to automate the construction and control of computer simulations and analyses of a circuit or system design.
2. Discussion of Related Art
Computer Aided Design (CAD) and electronic design automation (EDA) tools are used in the circuit design process to describe and analyze the physical arrangement of circuit components and their connections. CAD tools, for example, are used to specify a design for printed circuit boards (PCBs) and the like, by identifying the components to use in a design, their placement, and their inter-connectivity. EDA tools encompass both CAD tools and Computer Aided Engineering (CAE) tools which identify and simulate the electrical behavior of the components and their inter-connectivity.
FIG. 1 shows an exemplary design having three components or parts (such as microprocessors, memory chips, etc.). The components are identified by reference designators U1, U2, and U3. Sometimes, but not always (as naming conventions and standards may vary), a reference designator is indicative of the location where a component is placed on a PCB or in a system design. Component U1 has logical pin names A3, A2, A1, A0 (which can also be denoted in bus notation as A<3:0>) and physical pin numbers 4, 3, 2, and 1 (<4:1>); component U2 has logical pin names B<3:0> and physical pin numbers A<4:1>; and component U3 has logical pin names C<10:7> and physical pin numbers D1, C1, B1, A1. The logical pin names are typically an artifact of the component vendor's naming conventions and the pins' function (e.g., a data bus), and the physical pin numbers are typically an artifact of the CAD system being used to describe and design the circuit or system. Sometimes, but not always, a physical pin number is indicative of the location where a pin is located on a component. Different implementations of the same or similar components will often have the same logical pin names but different physical pin numbers. To precisely designate a physical pin in the physical design of the circuit or system, the reference designator and physical pin number are typically used, e.g., U1.4. (It is well known that the terms “physical pin numbers” and “logical pin names” actually refer to various forms of alphanumeric strings, including those recognized by various standards, such as JDEC, and those established by vendor naming conventions. It is also understood that some technologies do not actually employ pins per se but the term pin is still used to refer to the connection mechanisms.)
The components U1, U2, and U3 are interconnected via physical nets. Bus<0>, for example, is the physical net interconnecting U1.1, U2.A1, and U3.D1. Any electrical signal on such a physical net will be communicated to all such pins, though the actual waveform may differ at different pins.
Typical CAD systems create and maintain a data structure called a physical net list to describe the inter-connectivity of the components. For example, FIG. 3 illustrates a portion of an exemplary CAD file or data structure 300 to describe the physical nets of FIG. 1. The file 300 specifies that physical net Bus<0> interconnects U1.1, U2.A1 and U3.D1. Similar descriptions would exist for the other physical nets.
FIG. 2 shows a circuit similar to that of FIG. 1, except that the interconnection of components includes other devices. Two or more CAD nets sometimes perform such that a signal generated by a component on one of the CAD nets is propagated to a component on one of the other CAD nets. More specifically, the interconnections of this exemplary design include resistors, though other components such as connectors, cables, capacitors, diodes, FET switches or the like could have been included on the interconnections without loss of generality. The interconnection 205 is at times referred to as an “extended net,” “electrical net,” or the like. (As a shorthand, the terms “extended net” and “physical net” will be used herein.) The EDA system typically models an extended net to accurately describe its behavior. For example, in the case of FIG. 1, the system may model the metalization used to form a physical net Bus<0> as a function of the materials used, the length and shape of metalization segments to pins, etc. The extended net 205 of FIG. 2 may have a more complicated model than that of FIG. 1 to account for the other devices in the extended net.
FIG. 3 also shows a portion of a typical CAD file or data structure 305 known as a CAD parts list. Various reference designators, e.g., U1, are associated with a corresponding corporate part number, e.g., xx_003. The corporate part number identifies the part. Part xx_003 could be the corporate part number for a specific brand and model of a microprocessor chip, for example. (Sometimes companies use component vendor part numbers instead of corporate part numbers. In any case, the corporate part number is the part number used in the CAD system and is also called a CAD part number.)
To ensure that the components of a circuit or system design will inter-communicate correctly, various types of CAD and EDA tools (i.e., computer simulations) are used to ensure signal integrity and the like. This is because the signals that travel between input/output connections (IOs) or pins are distorted by the electromagnetic effects of the interconnect between the IOs and other physical phenomena or environment conditions.
Two typical types of signal integrity analysis are timing analysis and waveform analysis. Timing analysis tools, for example, analyze the simulated transfer of signals between components to ensure that certain criteria, such as “set up times” and “hold times,” are satisfied. Such tools typically employ one or more forms of circuit models and/or timing specifications to describe how components behave and to specify the various timing criteria and constraints. Two typical forms of simulation models are behavioral and transistor-level models. Behavioral allows the fastest simulation times, but transistor level models are often required for design accuracy. Models are usually available in one of these two formats. An example of an industry standard behavioral model would be an IBIS model. An example of an industry standard transistor model would be an SPICE model. Waveform analysis may be done by a designer via visual inspection of simulation results or with the assistance of software tools. Typically, waveform analysis tries to detect instances when specified signal criteria are satisfied or violated. For example, a check may be made if a signal at a given pin exceeds certain levels and thus creates something known as an overshoot condition.
FIG. 4, for example, shows portions of an IBIS file or data structure 400. The file 400 is associated with a specific component part and is often provided by the component vendor. In this example, the file 400 is for part xx_003. The model 400 is composed into a component section and a model section. The component section, among other things, specifies the physical pin number, e.g., 1–4, the associated logical pin names, e.g., A<3:0>, and identifies an IO buffer model for each pin. In this example each pin is associated with model IO4. The model section more specifically recites the various parameters and model information to describe the electrical behavior of the component pins, for example, specifying IV (current/voltage) and VT (voltage/time) curves or the like. Transistor level models are often considered to be a more accurate representation of how a component pin actually behaves as it models the actual pin at a transistor-level of operation.
One method of simulating and analyzing the behavior of a design is to exhaustively simulate and analyze all interconnections. For example, a designer or tool can cause the simulation and analysis of U1.1 driving a signal to U2.A0 and vice versa; U1.1 driving a signal to U3.D1 and vice versa; and U2.A0 driving a signal to U3.D1 and vice versa. The simulation tools would use the IBIS model and/or SPICE models discussed above (or perhaps other models) to simulate how the component pins behave.
The exhaustive approach often causes the simulation of “paths” that in fact are never expected to be used in the actual design. These are known as “false paths.” For example, assume that U1 is microprocessor and U3 is a register, and that the logical behavior of each component and its interfaces make U3 incapable of driving a signal to U1. The exhaustive approach would nonetheless simulate U3 driving U1, and such an approach may flag such a path as violating timing or other signal integrity criteria. A designer would then need to address such an error. For example, the designer could fix the problem by adding passive components to the extended net violating the criteria, or by changing the location of components, even though the path is never expected to be used. Or, the designer may study the logical design of the system in an attempt to determine whether or not the flagged path is a true or false path (sometimes this option is not practical or available). In either case, these approaches are wasteful of designer time and simulation time, and error prone.
Another approach to simulating the design is to have a designer familiar with the logical design of the system architecture (e.g., someone who knows that U3 never drives U1) construct the appropriate simulations and analyze the resulting waveforms. This approach is wasteful of designer time and error prone. It also requires such analysis to be performed by someone familiar with the logical design and, thus, potentially requires inefficient allocation of engineering talent. Moreover, if a design or component is changed (e.g., substituting one model of processor for another) or is re-characterized (e.g., a modified model is used to more accurately describe electrical behavior of a component already in the design), the simulations need to be reconstructed and analyzed by the designer.
USPTO Backgrounds
USPTO Backgrounds