The present invention relates to integrated circuits and, more particularly, to a monitoring system for detecting degradation of a semiconductor integrated circuit.
Semiconductor devices are being manufactured with an increased functionality to package pin count (external terminal or I/O count). This is partly because of improved silicon die fabrication techniques that allow die size reductions and thus a semiconductor die can be assembled into a relatively small package. Such improved silicon die fabrication techniques result in deep sub-micron semiconductor circuits comprising numerous transistors such as Field Effect Transistors (FETs).
When voltages are applied across the gate and source or drain and source electrodes of a FET, electric charges are created and stored in the FET. These charges are proportional to the voltages applied and if these voltages are sufficiently large, and are applied frequently enough or for relatively long durations, the intrinsic characteristics of the FET can be modified. Such intrinsic characteristics include Time Dependent Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), Negative Bias Instability (NBI) and threshold voltage breakdown. When there is an unacceptable alteration in a FET's performance due to changes in the intrinsic characteristics, a circuit that includes the FET is considered stressed or degraded. Such stressed or degraded circuits are typically replaced or reconfigured, however such stressed or degraded circuits may remain undetected and if they continue to operate within a system, the performance and accuracy of the system may be compromised.
USPTO Backgrounds
USPTO Backgrounds