The present invention relates to a semiconductor integrated circuit and, particularly, can be suitably used for a semiconductor integrated circuit in which operation frequency can be adjusted by register setting and an operation mode can be also changed.
In a semiconductor integrated circuit (LSI: Large Scale Integrated circuit) such as a microcomputer, there is a case that a high-speed process such as high-speed data computation has to be executed, and there is also a case that a high-speed process is unnecessary, for example, in a standby state such as an external interrupt. Consequently, a usage mode of using a high-speed clock in the case of executing a high-speed process by a program and switching it to a low-speed clock by the program in the standby state for the purpose of lowering power consumption is common.
Consequently, hardware of a microcomputer is configured so that the frequency of the operation clock can be properly changed by a method of internally generating clocks of a plurality of kinds of frequencies and switching the operation clocks. For example, a high-speed clock is generated by using a PLL (Phase Locked Loop) for a clock generated by an oscillator which is mounted internally or externally and, by dividing the frequency of the clock, a low-speed clock is generated. A low-speed clock generated by a plurality of oscillators such as a 32 kHz oscillator for clock is also generated. The microcomputer has a configuration that the operation clock frequency can be properly switched by a program.
As described above, the microcomputer has to be operated by clocks of various frequencies from the low-speed clock to the high-speed clock. When the current drive capability of a transistor of an internal circuit is adjusted so that the high-speed operation can be performed and the operation is performed with the capability also at a low-speed clock, the transistor has current drive capability which is more than necessary in the low-speed clock range, and the power efficiency deteriorates. To handle the problem and lower the power consumption, conventionally, for example, the following various measures have been taken.
(1) At a low-speed clock, the voltage of an internal step-down regulator is lowered to suppress power consumption.
(2) At a low-speed clock, the current supply capability of an internal step-down regulator is lowered or the number is reduced to reduce fixed current of the regulator.
(3) In an internal memory, at the time of operation at a high-speed clock, a sense amplifier is always operated for high-speed reading. At the time of operation at a low-speed clock, the sense amplifier is operated only when a read request is generated.
On the other hand, a technique of detecting the frequency (low/high) and the range of a clock signal supplied from the outside of a semiconductor integrated circuit, and changing a power supply voltage supplied to an internal circuit or changing the operation is proposed as follows.
In patent literature 1, an integrated circuit having a differentiation circuit, an integration circuit, and a comparator as circuit means detecting the frequency of an input clock signal is disclosed. An input clock signal is differentiated by the differentiation circuit and, after that, the resultant signal is processed in the integration circuit to output a voltage level depending on the frequency. The voltage level is compared with a predetermined level by the comparator. When a normal clock is input, the frequency is high, so that the output level of the integration circuit is high and exceeds the predetermined level. On the other hand, when a clock for a test is input, the frequency is low, so that the output level of the integration circuit is low and does not exceed the predetermined level. By switching the operation mode between a normal operation mode and a test mode in accordance with the output of the comparator, it becomes unnecessary to further provide a mode switching terminal, and the number of terminals does not increase.
In patent literature 2, an integrated circuit device having an operation voltage converting device capable of changing operation voltage supplied to a function circuit block in accordance with the operation speed of a system is disclosed. The operation voltage converting device has a frequency detection circuit detecting the frequency of an input clock, a low-voltage power supply circuit generating a plurality of operation voltages, and a power supply selection circuit selecting an operation voltage in accordance with the detected frequency.
In patent literature 3, a semiconductor device which can be adapted to any of high-speed operation and low-power-consumption operation by determining whether the operation is high-speed operation or low-speed operation on the basis of an input clock synchronization signal and switching an internal circuit is disclosed. The semiconductor device includes a clock generation circuit generating an internal clock having a predetermined phase relation for an input clock supplied, a determination circuit determining the cycle of the input clock on the basis of an internal signal of the clock generation circuit, and an internal circuit switching the operation mode in accordance with a determination result of the determination circuit.
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USPTO Backgrounds