Integrated circuits with high densities need efficient testing with a high failure coverage and low test costs. Several techniques to add circuitry that support this testing are known as design for testability (DFT). Many of these DFT techniques are based on scan chain concepts. Scan chains contain memory cells that are connected as shift registers when a scan mode is applied. If no scan mode is applied, the memory cells are not connected as shift registers, but perform their application function in their operational mode. The shift registers form a chain from an input that is driven by a test controller to an output that may also be read by the test controller. The test controller may be implemented externally as part of an automated test equipment (ATE) or may be integrated in the circuit that is under test.
In a scan test, data is shifted from the input to the memory cells to put them into a state in which the integrated circuit has to be tested. A test stimulus is applied to let the chip perform a defined operation to verify the functionality of the integrated circuit. The result of this operation is stored as data in the memory scan cells. After this operation, this data is shifted to the output of the integrated circuit to compare it with expected values.
USPTO Backgrounds
USPTO Backgrounds