(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to a method of reducing the dishing that occurs during chemical-mechanical polishing (CMP) of copper metal interconnections in semiconductor substrates.
(2) Description of the Related Art
Chemical-mechanical polishing, or, CMP, is becoming an even more important process in the manufacture of ultra large scale integrated (ULSI) circuits where more devices are being packed into smaller areas in semiconductor substrates and where unconventional metals, such as copper is being used in order to improve the over-all performance of the circuits. More devices in a given area on a substrate require better planarization techniques due to the unevenness of the topography formed by the features themselves, such as metal lines, or of the topography of the layers formed over the features. Because many layers of metals and insulators are formed successively one on top of another, each layer need to be planarized to a high degree if higher resolution lithographic processes are to be used to form smaller and higher number of features on a layer in a semiconductor substrate. Conventionally, etch-back techniques are used to planarize conductive (metal) or non-conductive (insulator) surfaces. However, some important metals, such as gold, silver and copper, which have many desirable characteristics as an interconnect, are not readily amenable to etching, and hence, CMP may have to be used.
It is the nature of semiconductor physics that as the feature sizes are scaled down, the performance of internal devices in integrated circuits improves in a compounded fashion. That is, the device speed as well as the functional capability improves. The overall circuit speed, however, becomes more dependent upon the propagation speed of the signals along the interconnects that connect the various devices together. With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, it has therefore become even more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivities for high signal propagation. Copper is often preferred for its low resistivity, as well as for resistance to electromigration and stress voiding properties.
Conventionally, the various metal interconnect layers in a semiconductor substrate are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate.
It will be observed that patterning, that is, photolithography and etching of metal layers to form the needed interconnects constitute a significant portion of the process steps of manufacturing semiconductor substrates, and it is known that both photolithography and etching are complicated processes. Furthermore, copper is very difficult to etch. This is one of the primary reasons why the current state of very large scale integration (VLSI) employ the use of aluminum for the wiring and tungsten plugs for providing the interconnection between the different levels of wiring. However, since copper has better electromigration property and lower resistivity than aluminum, it is a more preferred material for wiring and plugs than aluminum. In addition, copper has more improved electrical properties over tungsten, making copper a desirable metal for use as plugs as well. Thus, where it was relatively easy to etch aluminum or tungsten after depositing them to form lines or via plugs, substantial additional cost and time are now required to etch copper. Accordingly, chemical-mechanical polishing has become an attractive alternative to etching in removing unwanted copper.
Another method that is especially suited to forming composite copper interconnects, that is, metal lines and plugs together, with minimal etching is the damascene process. In a single damascene process, grooves are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, the conductive hole openings are also formed in the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The excess metal is then removed by chemical-mechanical polishing. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers. It will be noted that the sequence of first forming the groove in an upper insulating layer and then the hole in the underlying lower insulating layer can be reversed by forming the hole extending downwardly from the upper insulating layer to the bottom of the lower insulating layer and then "enlarging" the hole in the top layer to form the groove in the upper layer. Though each of the two approaches requires modification of some of the steps up to, but not including the last step of polishing, the details of the intermediate steps will not be given here so as to not obscure the understanding of the important step of CMP. An improvement over prior art CMP will be disclosed in the embodiments of the present invention.
As described by Guthrie, et al., in the Conference Proceedings ULSI-VII, 1992, Materials Research Society, CMP combines a chemical conversion of the surface layer to be removed with a mechanical removal of the converted layer. Ideally, the conversion product should be soft, according to Guthrie, et al., and readily removed to maintain high polishing rates. Because of the chemical nature of the conversion, rate selectivity for metal removal relative to insulator removal can be achieved by incorporating additives in the slurry to either enhance the metal removal and protect the insulator. Manipulation of the chemical component of CMP can be quite involved, while the mechanical component of the polishing mechanism can provide more straight-forward planarization characteristics.
The mechanical kinetics of CMP for a blanket deposited metal in grooves or holes in an insulator is illustrated in FIGS. 1a-1c and explained by the Preston equation given by EQU (.DELTA.H/.DELTA.t)=K.sub.p /A)(.DELTA.s/.DELTA.t), where
(.DELTA.H/.DELTA.t) is the removal rate of the material in terms of change in height per unit time of polishing, L is the load imposed over a surface area A, (.DELTA.s/.DELTA.t) is the relative velocity of the pad to the sample, and K.sub.p is Preston's coefficient. The equation predicts that, for a given (L/A), the weight loss of the polished material is proportional to the amount of travel, and it remains invariant with time. The polish rate increases with the pressure (L/A) and velocity. In other words, the removal rate is a linear function of pressure, so that high points are polished more rapidly, and the surface quickly becomes planar. This is shown at points (25) in FIG. 1a.
In FIG. 1a, metal (20) is deposited over an insulator (10) having groove and/or hole recesses (13) as shown. Excess metal is removed by performing mechanical polishing with pad (30) and a slurry, not shown. A slurry for removing tungsten metal, for example, may comprise the combination of two or three ingredients including: 1) a chemical base such as hydrogen peroxide (H.sub.2 O.sub.2) dissolved in water, 2) an abrasive, such as alumina, silica, or titanium oxide (TiO.sub.x where x equals 1 to 2), and 3) an optional fluid such as ethylene glycol in which the abrasive is suspended. It is to be noted in passing that the Preston equation implies that the removal rate is independent of the abrasive particle size in the slurry. Once the high points are quickly polished, the relatively high pressure at the high points are diminished since the load is now shared by lower points such as (23) which are now within reach of the pad. After total removal of the metal layer (20) from the surface of insulator (10), the polishing is shared between the metal layer that is level with the insulator surface and the insulator itself. Since the polishing rate of the metal is different from that of the insulator, and in the case of copper, faster than that of the insulator, metal is removed from further below the level of the insulator, thus leaving spaces (17) as shown in FIG. 1b. This in turn causes a higher pressure being built up at the edges of the groove/hole openings (13) and (17), and therefore, erosion of the insulator edge, (15). When compounded by the elastic deformation of the polishing pad material as shown in FIG. 1c, polishing continues below the level of the insulator surface, thus causing dishing (21) of the metal surface as shown in FIG. 1c. This in turn results in defects and reliability problems which are alleviated with the proposed method of the present invention.
Some prior art methods preclude the use of CMP in order to avoid the dishing problem. In U.S. Pat. No. 5,674,787, Zhao, et al., propose using selective electroless copper deposited interconnect plugs so that the metal in holes are built up to the level of the insulator layer. Ting, et al., of U.S. Pat. No. 5,619,680 also propose electroless deposition for IC fabrication where both selective and an additive process are provided for forming conductive layers. Allen of U.S. Pat. No. 5,654,245, on the other hand, teaches selective metallization through implantation of nucleating species for copper growth in areas where interconnects are formed. Wolleson shows in U.S. Pat. No. 5,659,201 a method of forming high conductivity interconnection lines of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms.
What is needed is an improvement over prior art methods of forming copper interconnects without dishing defects through a judicious use of a modified CMP process.
USPTO Backgrounds
USPTO Backgrounds