1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to a method of improving reliability of scaled-down memory cells.
2. Description of Related Art
Increased miniaturization of components, high performance, and low cost of integrated circuits have long been goals of the computer industry. One technique in the continuing scaling-down of semiconductor memory cells involves fabrication of a semiconductor gate, such as a control gate of a flash memory cell, including depositing a metal-containing material onto a semiconducting layer as a semiconductor gate to form silicide. However, if and to the extent the gate is damaged during fabrication, an associated deformed or non-uniform profile of the gate can adversely affect the silicide formation and, hence, chip quality.
A situation may arise, for example, where damage to a gate, such as a polysilicon (PL) gate, may cause, or contribute to, or occur in connection with, a following silicide formation being too closely disposed to an insulating layer. When the insulation layer is a charge trapping dielectric of the gate, such as an oxide-nitride-oxide (ONO) layer of a memory device, electrical problems may occur as a consequence of the silicide being formed too closely to the insulation layer. Such occurrence may undesirably manifest, for instance, resistance, reliability, retention and disturb issues.
A need thus exists in the prior art for a method of forming undamaged or optimized semiconductor gates suitable for silicide formation thereon, or the like, or improved operation therewith.
USPTO Backgrounds
USPTO Backgrounds