In recent years, a stacked semiconductor memory device has been proposed in which memory cells are integrated three-dimensionally. In such a stacked semiconductor memory device, a stacked body in which electrode films and insulating films are stacked alternately on a semiconductor substrate is provided; and semiconductor pillars that pierce the stacked body are provided. Then, memory cells are formed at each crossing portion of the electrode films and the semiconductor pillars. To realize even higher integration in such a stacked semiconductor memory device, it may be considered to dispose, between the semiconductor substrate and the stacked body, a portion of a control circuit controlling the memory cells.
USPTO Backgrounds
USPTO Backgrounds