The present invention generally relates to an improvement of increasing an operating speed of an output circuit employed in a semiconductor integrated circuit such as an output circuit employed in a semiconductor memory device. More specifically, the present invention is directed to an output circuit of a large-capacity dynamic random access memory (DRAM) having a multi-bit output terminal.
FIG. 6 represents a circuit diagram of an output circuit which has been conceived by the Inventors prior to an output circuit invented by these Inventors.
FIG. 7 is a circuit diagram of a boosting circuit indicated as a blank box. FIG. 8 represents an operation waveform diagram of the output circuit shown in FIG. 6. It should be noted that detailed circuit indications are omitted from the respective drawings, which have no direct relationship with the present invention, for the sake of simple explanation.
In the output circuit, symbol "VCCO (for instance, 5 V or 3.3 V)" indicates a power supply voltage externally applied, and symbol "VCC" shows another power supply voltage (for example, 3.3 V) applied from a voltage limiting circuit 1 (BST1) inside or outside a chip, and symbols "VSS" and "VSSO" represent ground power supply potentials (for instance, 0 V) externally applied. Although there is no restriction in implication, "VCC" and "VSS" may be regarded as one power supply potential and the other power supply potential, which constitute one pair of power supply potentials outputted from a single power supply. Similarly, "VCCO" and "VSSO" may be regarded as one power supply potential and the other power supply potential, which constitute one pair of power supply potentials outputted from a single power supply. Also, these potentials VCC, VSS, VCCO and VSSO may be called as first, second, third, and fourth power supply potentials. It should be understood that there is one case where VSS and VSSO are commonly, mutually connected to each other, and there is another case where VSS is separated from VSSO.
Symbol "DOE" shows an output control signal from the output circuit; symbols "DOT" and "DOB" denote input data entered into the output circuit so as to produce data which should be outputted from this output circuit; and symbol "IO" indicates an output terminal. Also, symbols "NAND1" and "NAND2" represent NAND gate circuits; symbol "INV1" shows an inverter circuit; symbols "NMOS1" and "NMOS2" denote n-channel type MOS transistors (will be referred to as "nMOS" hereinafter); and symbols "N1", "N2", "N3" and "N4" show internal nodes.
When the node N1 becomes a low level, namely VSS, the boosting circuit 1 (BST1) boosts the signal level of the node N3 higher than, or equal to VCC, so that the high level of the signal outputted from NMOS1 to the output terminal IO is increased higher than, or equal to a predetermined high level (VOH). In the case that the node N1 becomes a high level, namely VCC, a low level of the ground power supply potential VSS level is outputted to the node N3. This boosting circuit 1 (BST1) is also called a charge pump circuit, and may be realized as the circuit shown in FIG. 7.
In FIG. 7, symbol "IN" shows an input terminal; symbol "OUT" denotes an output terminal; symbols "VCC" and "VSS" represent a power supply terminal and a ground power supply terminal; symbol "INVB1" is an inverter circuit; symbols "NMOSB1" and "NMOSB2" are nMOS; symbol "PMOSB1" indicates a p-channel type MOS transistor (will be referred to as a "pMOS" hereinafter); symbol "C1" is a capacitor; and symbols "B1" and "B2" are internal nodes. It should also be noted that in FIG. 7, the p type MOS transistor is indicated by additionally using an arrow in order that this p type MOS transistor is discriminatable from the n type MOS transistor. In this boosting circuit of FIG. 7, when the level of the input IN is changed from a high level to a low level, the potential of the node B1 is changed from VSS to VCC, so that the potential at the node B2 is increased up to a level higher than VCC, and this node B2 is precharged to approximately the VCC level by the transistors NMOSB2 and NMOSB3 by coupling C1. In response thereto the output OUT becomes higher than, or equal to VCC. Conversely, when the input IN is changed from a low level to a high level, the transistor NMOSB1 is turned ON, and the output OUT becomes the VSS level.
When the output data should become a low level in the output circuit of FIG. 6, namely DOT=a low level and DOB=a high level, the output circuit is operated in such a manner that signals as indicated in FIG. 8 are produced. In other words, in the case that Levels of the input data DOT and DOB are determined, and the control signal DOE is changed from the VSS level to the VCC level, the level of the internal node N2 becomes the VSS level, and also the level of the node N4 becomes the VCC level by the inverter INV1. As a result, the transistor NMOS2 is turned ON and the output IO is lowered to the VSSO level. The low level of the output data of the output IO is outputted by the transistor nMCS, namely NMOS2. In response to this fact, no one conceives that there is no problem if the gate voltage of NMOS2 is equal to VCC, the low level output is produced.
Conversely, when the output data becomes a high level, namely DOT=a high level and DOB=a low level, the output circuit is operated in such a way that signals varied as indicated by dotted lines of FIG. 8 are produced. In other words, when the levels of the input data DOT and DOB are determined, and further the level of the control signal DOE becomes the VCC level, the potential level of the internal node "N1" becomes the VSS level in response to the above-described level changes, and also the potential level of another node "N3" is increased to such a high level higher than, or equal to the VCC level by the boosting circuit 1. As a consequence, even when the output transistor connected between the power supply terminal VCCO and the output IO is an nMOS (NMOS1), the output data having the level higher than, or equal to a VCC-VTH (note: VTH being threshold voltage of nMOS) can be outputted to the output IO.
In the above-described example, when the data is outputted outside the semiconductor chip, the ground potential is floated at the far portion of the VSS wiring line (pattern) formed on the chip, namely at the VSS wiring line portion located far from the bonding pad for the VSS wiring line formed on the chip. As a result, the effective power supply voltage level is lowered, so that the operating speed of the output circuit on the side of far portion is delayed. This ground level floating phenomenon is caused by the load on the output side (stray capacitance of board), and also the parasitic resistance of the VSS wiring line (ground wiring line) within the chip. Now, the above-described problem belonging to FIG. 6 will be described.
FIG. 9 schematically indicates an output circuit arrangement of a large capacity dynamic random access memory (DRAM) having a multi-bit output (e.g., 16-bit parallel output (.times.16)) structure. FIG. 10 shows a waveform diagram of this DRAM. Symbols VSSO(P), IO(N) and IO(F) show bonding pads which are electrically connected to the external circuit of the chip, and are provided on this chip. It should be noted that the bonding pad VCCO is omitted from FIG. 9.
Symbol "VSSO(N)" indicates a wiring line portion among the VSSO wiring line connected to the bonding pad VSSO(P) and located near this VSSO(P) pad (namely, near portion), whereas symbol "VSSO(F)" indicates another wiring line portion among the VSSO wiring line connected to this bonding pad VSSO(P) and located far from this VSSO(P) pad (namely, far portion). Symbol "Rpar" is a parasitic resistance of the VSSO wiring line, and corresponds to such a parasitic resistance between VSSO(N) and VSS(F). As schematically indicated, each of the output circuits is arranged by NMOS1, NMOS2, and CNT. In this case, symbol "NMOS1" is a MOS transistor for outputting a high level, and symbol "NMOS2" is a MOS transistor for outputting a low level. Symbol "CNT" indicates a control circuit for controlling NMOS1 and NMOS2 by employing DOE, DOT, and DOB. Symbol "N4" shows a control signal for controlling NMOS2. Also, the internal circuits INTC1 and INTC2 are connected to DOE, DOT and DOB. Also, symbol "VTH" of FIG. 10 indicates a threshold voltage of NMOS2.
In the case of the 16-bit parallel output arrangement, 16 output circuits are connected via the VSSO wiring lines to the VSSO bonding pads VSSO(P). Thus, in the DRAM output circuit of FIG. 9, when a large number of output circuits output low levels, the VSSO potential is floated at the far portion VSSO(F) of the VSSO wiring line, as indicated in FIG. 10, which is caused by currents flowing through loads (not shown) connected to the respective pads IO. Since the transistor NMOS2 is not turned ON when the difference between the signal N4 and the VSSO potential is increased higher than, or equal to the threshold value VTH, the operating speed thereof is delayed in response to such a fact that the VSSO potential is floated (namely, potential is raised from 0 V). Therefore, the difference in the operation timing between the output circuit at the far portion and the output circuit at the near portion is increased. This may cause such a problem that the data output speed is lowered. On the other hand, in order to avoid the potential floating phenomenon by reducing the impedance of the VSSO wiring line, the wiring pattern having such a large area must be employed by which a relatively large current is allowable. However, this large-area wiring line may increase the entire area, which could impede low-cost designing for manufacturing high integration DRAMs.
USPTO Backgrounds
USPTO Backgrounds