Stated more generally, a signal may contain multiple signal components, and the present invention aims to provide a signal processor capable of recognizing the exact frequency of a certain signal component in the received signal. Normally, a PLL (Phase Locked Loop) is used in a situation where the frequency of the frequency component is already known in approximation. For allowing the PLL to lock in on this frequency, it is known to start with the PLL having a relatively large bandwidth and then reducing the bandwidth while keeping the signal component within the band. However, there are cases where the received signal actually comprises multiple frequency components, of which the frequency distance may be relatively small, and of which the exact frequency is not approximately known in advance; the situation described in the introduction is an example of such case. If the conventional method of a PLL with an initially large bandwidth is used, chances are that the PLL will lock in on an incorrect frequency.
It is a particular object of the present invention to provide a device capable of reliably demodulating the received signal of such situation.
USPTO Backgrounds
USPTO Backgrounds