The present invention relates generally to semiconductor packages and, more specifically, to a method and system for assembling stacked semiconductor packages.
Electronic devices such as mobile phones, personal digital assistants (PDA), and portable computers, are being designed to achieve the smallest possible size. Miniaturization of the electronic devices has increased the demand for small component footprints. A component footprint is defined as the space occupied by a component in an electronic device. Small component footprints have increased the popularity of stacked semiconductor packages.
Stacked semiconductor packaging is an advanced packaging technology that aids in making the electronic devices compact while maintaining high functionality and good performance. In a stacked package, individual semiconductor packages are stacked on top of one another. Each semiconductor package includes a substrate and a die attached on a surface of the substrate and electrically connected to the substrate. The die and the electrical connections also are encapsulated with a mold compound. The mold compound protects the die and the electrical connections from dust, moisture, mechanical stress, etc. Solder balls are formed over bond pads on the substrate. The solder balls provide an electrical interface for a second package stacked on the first package. Thus, a dense package structure is formed having a footprint of a single semiconductor package.
However, the distance between the first package and the second package, that is the substrate-to-substrate distance, should be greater than the bottom package encapsulation height in order to allow for good solder ball interconnection between the packages. Normally, the substrate-to-substrate distance is equal to the solder ball diameter, and the bottom encapsulation height is less than solder ball diameter. Hence, the height of the solder balls must be greater that that of the encapsulation, which increases the overall profile of the stacked package.
Referring now to FIG. 1, a schematic diagram illustrating a conventional center gate molding apparatus 100 for molding a semiconductor package is shown. The center gate molding apparatus 100 includes a runner 102, a gate 104, and a chase 106. The runner 102 is coupled with the gate 104. The gate 104 is located at the center of the chase 106. The semiconductor package includes a substrate 108 and a semiconductor die 110 attached on the substrate 108. The substrate 108 is electrically connected to the die 110 with wires 112 via wire bonding. The die 110 and the wires 112 are placed inside a cavity of the chase 106 for encapsulation with a mold compound 114. The runner 102 supplies the mold compound 114 to the gate 104. The mold compound 114 may include a non-conductive material such as epoxy and resin. Thereafter, the gate 104 injects the mold compound 114 into the cavity of the chase 106 to encapsulate the die 110 and the wires 112. Once the encapsulation is complete, the gate 104 is separated. During separation, the runner 102 and the gate 104 move upward while the chase 106 holds the now encapsulated die 110. However, since the mold compound 114 is viscid in nature, it can stick to the gate 104. Thus, the upward movement of the gate 104 may pull the mold compound 114 off the top surface of the package, thereby damaging the package. In some cases, the surface of the die 110 may become exposed, which adversely affects package reliability.
The efficiency of a semiconductor package design is primarily determined by the substrate utilization. However, with the apparatus described above, the chase 106 that surrounds the die 110 occupies a significant amount of surface area, which means the substrate must be larger than necessary. This reduces substrate utilization and ultimately, package efficiency. Further, the process, as described above, requires a unique molding apparatus based on the die and package sizes, which increases cost and reduces the flexibility of package design. Thus, it would be desirable to be able to assemble a stackable semiconductor package that has efficient substrate utilization in a reliable manner.
USPTO Backgrounds
USPTO Backgrounds