1. Field of the Invention
The present invention relates to a plasma processor to process a sample of a substrate shape such as a semiconductor wafer disposed in a processing chamber using plasma formed in the processing chamber in a vacuum vessel such as in etching, asking, chemical vapor deposition (CVD), or the like.
2. Description of the Related Art
In order to improve yield rates of plasma etching steps in mass production of semiconductor devices, it is desirable to perform uniform processing over a surface of semiconductor wafers (hereinafter simply referred to as a wafer). Especially, uniformity of processing over a surface of critical dimensions (CDs) desired for etching steps to form transistors is increasingly stringent year by year.
When distribution of radical density on a wafer is ununiform upon etching, a radical is ununiformly incident on an etching pattern. As a result, this contributes to degradation of CD uniformity. In order to secure CD uniformity, therefore, a plasma etching apparatus to implement a uniform radical density on a wafer is important.
In general plasma etching apparatuses, an ion or a radical generated by plasma diffuses inside the apparatus and is thereby supplied onto the wafer. Radicals are, however, deactivated in the process of transfer to the wafer due to gas phase reactions or on an inner wall of a chamber of the etching apparatus and thus distribution of radical flux incident on the wafer tends to be ununiform.
As a method to cause the distribution of radical flux to be uniform, mounting, inside the etching apparatus, a means to additionally supply a radical is considered to be effective. For example, JP-09-162169-A discloses a configuration where a first plasma generating chamber set at a relatively high pressure environment is mounted to an outer peripheral portion of a second plasma generating chamber set at a relatively low pressure environment.
JP-2013-84653-A further discloses a configuration where a second high frequency power source to supply high frequency power and a gas introducing mechanism to supply second gas are arranged in an outer peripheral portion of a wafer, thereby generating plasma around the outer periphery of the wafer.
USPTO Backgrounds
USPTO Backgrounds