This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-184162, filed Jun. 29, 1999; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device which is provided with protective transistors as protective circuit to protect internal circuits against an over-voltage.
2. Description of the Related Art
In general, many types of conventional semiconductor integrated circuits such as semiconductor memories are provided with protective circuits in order to protect internal circuits therein against an over-voltage. This protective circuit can avoid the occurrence of electronic breakdown in insulation films and breakdown at an junction portion by an Electro-Static Discharge (ESD).
For example, a NMOS transistor QN shown in FIG. 1 is used as the protective circuit. The drain of the NMOS transistor QN is connected to a signal line connected to a pad (PAD) and both the source and gate thereof. Both the source and gate are connected to a ground voltage source (Vss).
The NMOS transistor QN can protect internal circuits by a large current flow generated by a change of a voltage between the drain and the source thereof.
The necessity of the protective circuits is becoming increasingly high according to miniaturization and high density of circuit elements in semiconductor integrated circuits. It is necessary to increase the size of the protective transistor as the protective circuit in order to increase the protection against ESD. However, this causes drawbacks to increase an input-output capacitance in the internal circuits, and also to increase the area of the semiconductor chip. Accordingly, this conventional solving method has a limit basically. Furthermore, it is desirable to apply the protective circuit to various applications other than the ESD resistance.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a semiconductor device with an excellent resistance against the ESD by adding a circuit of a simple configuration to a protective circuit. Further, an another object of the present invention is to provide a semiconductor device capable of applying the protective circuit to functions other than the ESD resistance.
In accordance with a preferred embodiment of the present invention, a semiconductor device has an internal circuit, a pad, a protective circuit connected between a first power source and a node on a signal line through which the pad and the internal circuit is connected, and a first logical gate connected to a control terminal of the protective circuit. The first logical gate operates to keep an OFF state in the protective circuit during a normal operation of the internal circuit. Accordingly, when the power voltage source is ON, the output of the first logical gate, namely, the gate of the protective transistor (protective circuit) as the control terminal enters a floating state. In the floating state, a small amount of forward bias is generated in the protective transistor when an over-voltage is supplied to the PAD. It is thereby possible to obtain an excellent ESD resistance when compared with a conventional semiconductor device in which the control terminal of the protective transistor is fixed to a zero of the bias voltage.
In the semiconductor device as another preferred embodiment of the present invention, the first logical gate inputs both an output signal from the test circuit and a control signal in order to set the output signal from the test circuit into an activated state, the first logical gate outputs the output signal to a gate of the protective circuit according to a level of the control signal, and the protective circuit outputs the output signal from the test circuit to outside of the semiconductor device. The test circuit is a circuit to store information of the semiconductor chip and comprises a fuse circuit, for example. The protective transistor can be used as the output transistor for the output signal from the test circuit.
In the semiconductor device as another preferred embodiment of the present invention, a plurality of the pads and a plurality of the test circuits (each test circuit corresponds to each pad) are incorporated in the semiconductor device. Each test circuit is a fuse circuit to store a desired data item which comprises a resistance and a fuse connected in series between the first power source and a second power source.
In the semiconductor device as another preferred embodiment of the present invention, an addition resistance is further incorporated. The addition resistance is connected between the pad and a second power source.
The semiconductor device as another preferred embodiment of the present invention, further includes a transistor connected between the node and a second power source, and a second logical gate for inputting a signal whose level is an inverted level of the control signal in order to activate the output signal from the test circuit. The second logical gate controls an operation of the transistor by providing the output, signal from the test circuit to the control terminal of the transistor according to the control signal of the inverted level.
In the above semiconductor device, the first logical gate and the second logical gate output complementary signals to the corresponding protective circuit and the transistor, respectively.
In the semiconductor device as another preferred embodiment of the present invention, the protective circuit is a NMOS transistor whose drain is connected to the node on the signal line, whose source is connected to the first power source, and whose gate is connected to the first logical gate. The transistor is a PMOS transistor whose drain is connected to the node on the signal line, whose source is connected to the second power source, and whose gate is connected to the second logical gate.
The semiconductor device as another preferred embodiment of the present invention, further includes a transfer control gate placed at the node on the signal line through which the pad is connected to the internal circuit. The transfer control gate operates according to the control signal to activate the output signal from the test circuit, and prevents to transfer the output signal from the test circuit to the internal circuit through the protective circuit.
In the semiconductor device as another preferred embodiment of the present invention, the transfer control gate is a CMOS transfer gate whose ON/OFF operation is performed based on a value of the control signal to activate the output signal of the test circuit. The transfer control gate prevents to transfer the output signal of the test circuit to the internal circuit when the value of the control signal indicates to activate the output signal of the test circuit.
In the semiconductor device as another preferred embodiment of the present invention, a control signal indicates whether or not a voltage potential of the PAD is fixed to a desired voltage level during an execution of a test for the internal circuit. The control signal is transferred to the first logical gate, and the first logical gate controls ON/OFF operation of the protective circuit based on the value of the control signal.
In the semiconductor device as another preferred embodiment of the present invention, a control signal indicates whether or not a voltage potential of the PAD is fixed to a desired voltage level. The control signal is transferred to the first logical gate instead of the output signal from the test circuit.
In the semiconductor device described above, the protective circuit is a NMOS transistor, whose drain is connected to the node on the signal line, whose source is connected to the first power source, and whose gate is connected to the first logical gate.
USPTO Backgrounds
USPTO Backgrounds