Semiconductor components, such as dice, wafers and chip scale packages, are fabricated to include external contacts to allow electrical connections to be made from the outside of the components to integrated circuits contained on the components. A semiconductor die, for example, typically includes patterns of bond pads formed on a face of the die. At the wafer level, the bond pads are used for probe testing the integrated circuits on the die. At the die level, the bond pads are used for testing, and also for making electrical connections, such as wire bonds, for packaging. Typically, the bond pads comprise planar aluminum pads, or alternatively solder bumps on solder wettable pads.
The interconnects described above are but one type of interconnect that can be utilized with semiconductor components. Numerous other types of interconnects are known. For instance, semiconductor packages, such as chip scale packages, can utilize solder balls arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA).
FIGS. 1-5 illustrate an exemplary semiconductor component 10 having interconnects associated therewith. FIG. 1 is a top view of a fragment of the component 10, and shows a plurality of conductive traces 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34 and 36. The conductive traces extend from inner lead bond pads 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60 and 62 to outer lead bonds 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86 and 88. The shown relative sizes of the outer lead bonds and inner lead bonds are for diagrammatic purposes only. Accordingly, although the inner lead bonds are shown uniform in size and larger than the outer lead bonds which are also uniform in size, it is to be understood that the constructions can also have inner lead bonds and/or outer lead bonds which are not uniform in size, and can have inner lead bonds which are smaller than the outer lead bonds.
FIGS. 2 and 3 show a top view and a cross-sectional side view of an expanded region of the FIG. 1 fragment. Such views show that the trace 18 is a layer 100 of conductive material. Outer lead bond 70 comprises a solder ball 102 over a nickel-containing solder-wettable material 104. Inner lead bond 44 comprises a solder interconnect 106 having a conductive material cap 108 thereover. Conductive material cap 108 can comprise, for example, nickel and/or a solder ball.
Trace 100 can be referred to as a redistribution layer, in that it distributes an electrical signal from the central location of the inner lead bond 44 to the laterally outward location of outer lead bond 70 and vice versa.
The semiconductor component of fragment 10 comprises a semiconductor die 110 which can correspond to, for example, a monocrystalline silicon wafer. The die 110 has various levels of integrated circuitry (not shown) associated therewith. An electrically insulative passivation layer 112 extends around die 110 and insulates the die from the solder material 106. Passivation layer 112 can comprise, consist essentially of, or consist of silicon dioxide, and will typically have a thickness of from about 2000 Å to about 8000 Å. An insulative material 114 is provided over passivation layer 112, and is utilized to support circuit trace 100, and can also be utilized during patterning of circuit trace 100. Layer 114 can comprise, for example, polyimide.
Semiconductor die 110 can be considered a semiconductor substrate, or alternatively the die 110 in combination with various other materials of component 10 can be considered a semiconductor substrate. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
The die 110 has two opposing sides 111 and 113, which are typically referred to as a front side and a back side, respectively. Component 10 has opposing outer surfaces 115 and 117 that are proximate the front side 111 and the back side 113, respectively, of die 110. Surfaces 115 and 117 can be referred to as a front-side surface and back-side surface, respectively, of component 10.
Solder material 106 extends entirely through component 10, and accordingly extends from the front-side surface 115 of the component to the back-side surface 117 of the component. Solder material 106 can ultimately be utilized for an electrical connection to an external device proximate back-side surface 117, and can be utilized for electrically interconnecting such device to another device associated with pad 102 of outer lead 70.
A method of forming the structure of FIGS. 2 and 3 is described with reference to FIGS. 4 and 5. Specifically, the construction 10 is shown prior to formation of leads 44 and 70 (FIGS. 2 and 3). A hole 130 is etched through component 10 to extend from front-side surface 115 to back-side surface 117. The hole can be formed by, for example, laser-etching. The hole comprises a depth 132 extending from the front-side surface 115 to the back-side surface 117, and comprises a width dimension 134 orthogonal to the depth. The hole can be substantially circular when viewed from above (as shown), and accordingly width dimension 134 can correspond to a diameter of the circle. Alternatively, the hole can have a polygonal shape (such as, for example, a square shape) when viewed from above. Regardless of the shape of the hole 130, the maximum width dimension will typically be less than or equal to about 100 microns, and frequently will be less than or equal to about 35 microns.
A problem is encountered in uniformly filling hole 130 with solder. Specifically, the small dimension of hole 130 makes it difficult to flow solder into the hole. Various efforts have been made to provide solder-wetting agents along the peripheral sidewalls of the hole 130 in order to draw the solder into the hole. However, the provision of the solder-wetting agents will frequently comprise relatively high-temperature processing (specifically, processing in excess of 300° C.), which can adversely impact circuitry associated with die 110. Accordingly, it is desired to develop new methods for forming interconnects within semiconductor components.
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