The invention relates to a current sample-and-hold circuit having a plurality of subcircuits which store a current signal, at least one of the subcircuits containing a switch which is at a constant potential.
The invention also relates to an analog/digital converter having at least one current sample-and-hold circuit.
The invention also relates to a method for operating a current sample-and-hold circuit.
The accuracy of analog/digital converters depends, inter alia, on the sample-and-hold circuits used (Sample and Hold Circuits), which provide an analog input signal at discrete times for subsequent quantization.
Particularly in the case of sample and hold circuits using CMOS technology, whose information transfer is effected in the voltage domain, the relevant switching elements are known to need to be at a virtual ground potential at any turn-off time (zero-switching technique) in order to attain a high level of accuracy. The turn-off pulse thus always injects the same fault charge into the sampling capacitance, which avoids sampling errors dependent on the input signal and results in a high level of sampling accuracy.
If currents are used for information transfer instead of voltages (current mode), then the current is usually attributed to a voltage which can be stored in a capacitor. Since the switching transistor""s channel is at a potential which is dependent on the input signal in most architectures, the fault charge injected during the turn-off operation distorts the sampling result. By using an operational amplifier, a zero-switching technique can also be implemented in this case, but this has negative effects on the bandwidth of the circuit.
A generic current sample-and-hold circuit is known from the article by Jonsson and S. Eriksson: xe2x80x9cNew Clock-Feedthrough Compensation Scheme for Switched-Current Circuitsxe2x80x9d, Electr. Lett., Vol. 29, No. 16, pp. 1446-1447, August 1993. This circuit requires four subcircuits for storing the signal.
Another generic current sample-and-hold circuit is known from the book by B. Jonsson et al., Switched-Current Circuits: From Building Blocks to Mixed Analog-Digital Systems, Stockholm 1999, pp. 27-33.
The use of switching elements, for example n-MOS transistors, which are at the same virtual ground potential at any time is referred to as a zero-switching technique. In contrast to the use of transmission gates, consisting of n-MOS and p-MOS transistors, the hold time can be determined very exactly in this case, since a single signal is used to turn off all the switches simultaneously, especially since all the switching transistors are always at the same constant potential. Particularly in the case of fast analog/digital converters (ADCs), such as are used, by way of example, to process video signals or other radio-frequency signals, the jitter, that is to say the discrepancies in the turn-off time, otherwise significantly determines the accuracy of the sampling element. In addition, the turn-off pulse always injects the same fault charge into the sampling capacitance when the switch potential is constant, which avoids sampling errors which are dependent on the input signal. The invention comprises a simple method for discrete-time current signal sampling, where the relevant switching elements are always at a virtual ground potential, and this results in the aforementioned advantages (low jitter, constant charge-injection). Its low complexity means that it is particularly suitable for high signal bandwidths.
To reduce the signal-dependent sampling errors which cannot be eliminated by virtue of a fully differential design, various measures are taken which are known by the terms n-step principle, zero-switching technique and replica technique.
In addition, U.S. Pat. No. 5,227,676 describes a current sample-and-hold circuit having a subcircuit which is used for storing the current. The known current sample-and-hold circuit also contains linear resistors, which are actually arranged outside the subcircuit. A similar situation applies to the current sample-and-hold circuit described in (B. Razavi, A 200-MHz 15-mW BiCMOS Sample-and-Hold Amplifier with 3 V Supply, IEEE Journal of Solid State Circuits, Vol. 30, No. 12, pp. 1326-1332, December 1995).
The invention is based on the object of providing a current sample-and-hold circuit in which signal-dependent sampling errors are eliminated as far as possible.
The invention achieves this object by virtue of a generic current sample-and-hold circuit being designed such that the subcircuits each contain at least one linear resistor which is connected such that the current signal produces a voltage drop across a resistor, and such that the subcircuits each contain at least one control amplifier which is operated so as to cause inversion and, in a hold mode, sets an output current for the circuit which causes a voltage drop across the resistor which is essentially the same size as the voltage drop across the resistor before the hold mode.
A simple structure to the circuit and a simple clock sequence for the signals means that only a few turn-off pulses, preferably only a single turn-off pulse, are required. Consequently, the current sample-and-hold circuit is also particularly suitable for radio-frequency applications, for example for processing video signals.
Preferably, the invention includes a fully differential design for the circuit. A differential design allows errors to be suppressed.
The invention also relates to performance of a method for operating a current sample-and-hold circuit having a plurality of subcircuits, the subcircuits each storing a current signal, such that the current signal produces a voltage drop across a resistor, and such that a control amplifier which the subcircuits contain and which is operated so as to cause inversion sets, in a hold mode, an output current for the circuit which causes a voltage drop across the resistor which is essentially the same size as the voltage drop across the resistor before the hold mode.
One preferred embodiment of the current sample-and-hold circuit and of the method for operating is distinguished in that at least two subcircuits can be connected to one another using a connecting switch.
In this context, it is particularly expedient that the connecting switch is arranged such that, in a turned-on state of the connecting switch, a charging current for storage capacitors is produced solely by the current signal.
It is also advantageous to design the current sample-and-hold circuit such, or to perform the method for operating the current sample-and-hold circuit such, that all the subcircuits contain switches which are each at the same potential.
USPTO Backgrounds
USPTO Backgrounds