The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor device properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, low power consumption, and good reliability must be maintained while satisfying a number of critical performance parameters.
Commonly, system designers specify or define a number or required operational parameters (e.g., max/min voltage, signal timing) for certain circuitry segments in a system. Semiconductor devices (i.e., integrated circuits) must comply with such required parameters in order to be used in the system. For example, a system may require that a semiconductor device operate over supply voltage range of 10V to 20V, optimized for performance at 15V. In another example, a system may require that a semiconductor device provide a specified timing parameter (e.g., trise(MIN), tfall(MAX)).
Unfortunately, however, there are a large number of variables in semiconductor device manufacturing that can affect any given performance parameter. Intra-process variations, feature matching issues, and layout considerations are among a number of concerns that impact a device manufacturer's ability to provide a specified performance parameter. In some cases, a semiconductor device's standard operational parameters may be sufficient to provide a required performance level in a given system. In a number of other cases, however, a given system may require a very specific or peculiar performance parameter—such that an integrated circuit must be designed specifically for that application, if possible.
Consider, for example, the conventional circuitry system 100 illustrated in prior art FIG. 1. System 100 depicts a portion of a common high side driver circuit application, illustrating some of the concerns mentioned above. System 100 comprises an end equipment system 102 coupled, via an operative interface 104 (e.g., a pin), to an integrated circuit segment 106 within semiconductor device 108. For purposes of illustration, symbolic boundary 110 demarcates an operational border (e.g., physical, electrical), between device 106 and system 102, and along which interface 104 is disposed.
Segment 106 comprises a high side driver circuit, having a first transistor 112, a second transistor 114, and a third transistor 116. Transistor 116 has a first terminal coupled to supply voltage 118, a second terminal coupled to node 120, and a third terminal—which serves as an output for segment 106—coupled to interface 104. Transistor 112 has a first terminal coupled to supply voltage 122, a second terminal coupled to node 124, and a third terminal coupled to node 120. Transistor 114 has a first terminal coupled to node 120, a second terminal coupled to node 126, and a third terminal coupled to ground.
Segment 106 is utilized to drive an operational load 128 within system 102. Load 128 is represented in FIG. 1 by capacitor 130 and resistor 132, coupled in parallel between interface 104 and ground. Load 128 may comprise any operational load (e.g., another semiconductor device, an electro-mechanical assembly, an antenna) requiring a drive signal of a specified voltage. Appropriate control signals are asserted at nodes 124 and 126 to turn transistor 116 on and off, as desired. For purposes of explanation and illustration, transistor 116 is depicted as an NMOS transistor. When on, transistor 116 supplies load 128 with a desired drive signal. Again, for purposes of explanation and illustration, it is assumed that—through the selection of supply voltages 118 and 122, and the size and layout its constituent components—segment 106 supplies load 128 with sufficient voltage for operation of system 102.
If, however, rise and fall times of a drive signal originating from segment 106 are particularly critical, then certain issues may arise in system 100. Where a target propagation delay—between the time at which a driver off or on signal is asserted at nodes 124 and 126 and the time at which the voltage at interface 104 has sufficiently dissipated or charged, respectively—must be relatively small, common circuit phenomena can have significant consequences. Signal fall times and propagation delays are typically affected to a greater extent, since—generally—device discharge phenomena tend to be more problematic than device charging phenomena. For example, capacitive coupling effects from load 128 can impede the discharge of transistor 116 through load 128 and, consequently, extending the actual fall time and propagation delay beyond the target. This can present a significant problem, especially in a number of modern end-equipment applications where increasingly faster data transfer and performance rates are demanded.
Certain conventional systems have attempted to adjust or control the propagation delay by incorporating some sort of alternative discharge path from transistor 116. Unfortunately, a number of these conventional systems channel that discharge through the semiconductor device itself, not load 128. This increases power dissipation in device 108. Furthermore, circuitry and routing for such a purpose can add considerable design and fabrication overhead to a semiconductor device. Such an approach usually results in increased costs, decreased reliability, or yield problems.
Some conventional systems rely directly on complementing MOS structures (e.g., PMOS) as a supplemental discharge mechanism for transistor 116 (NMOS). In most semiconductor fabrication processes, however, there are considerable process variations and tolerances between the complementary technologies. As a result, inexact device matching can, and often does, occur. This can shift propagation delays on a device-to-device, wafer-to-wafer or lot-to-lot basis—profoundly degrading overall device reliability. Furthermore, such approaches can create undesirable circuitry behaviors—such as overdriving the output into cutoff, or loss of fall time control. Overdriving the output into cutoff can cause an output fall time to have a large dv/dt during a portion of the fall time.
In other instances, where such discharge systems are not implemented, devices may simply be screened or tested for parameter compliance. When a device is non-compliant, it is scrapped—degrading yield and increasing costs.
As a result, there is a need for a system that provides accurate and manageable control of drive signal timing parameters through driver circuitry—satisfying critical timing requirements and providing reliable device performance in an easy, efficient and cost-effective manner.
USPTO Backgrounds
USPTO Backgrounds