1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming CMOS based semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, since the speed of creating the channel, which depends in part on the conductivity of the gate electrode, and the channel resistivity substantially determine the characteristics of the transistor, the scaling of the channel length, and associated therewith the reduction of channel resistivity, are dominant design efforts used to increase the operating speed of the integrated circuits.
FIGS. 1A-1C depict one illustrative prior art process flow for forming a semiconductor device 100 that includes an illustrative PMOS transistor 100P and an illustrative NMOS transistor 100N. As shown in FIG. 1A, the process begins with the formation of a trench isolation structure 12 in a semiconducting substrate 10. The isolation region 12 defines a P-Active region 10P and an N-Active region 10N in the substrate 10. Next, illustrative gate electrode structures 14 for the PMOS transistor 100P and the NMOS transistor 100N are formed above the regions 10P, 10N and above the isolation region 12. The gate electrode structures 14 generally include a gate insulation layer 14A and one or more conductive gate electrode layers 14B. A gate cap layer 16, made of a material such as silicon nitride, is formed above the gate structures 14. The gate electrode structures 14 depicted herein are intended to be schematic and representative in nature, as the materials of construction used in the gate structures 14 may be different for the PMOS transistor 100P as compared to the NMOS transistor 100N, e.g., the PMOS transistor 100P may have multiple layers of conductive metal, etc. The gate insulation layer 14A may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a high-k (k value greater than 10) insulating material. The gate electrode layer 14B may be comprised of one or more layers of conductive materials, such as polysilicon, a metal, etc. The structure depicted in FIG. 1A may be formed by a performing a variety of known techniques. For example, the layers of material that make up the gate insulation layer 14A, the gate electrode layer 14B and the gate cap layer 16 may be blanket-deposited above the substrate 10 and, thereafter, one or more etching processes are performed through a patterned mask layer (not shown) to define the basic gate structures 14 depicted in FIG. 1A.
FIG. 1B depicts the device 100 after several process operations have been performed. More specifically, illustrative silicon nitride spacers 18 have been formed adjacent the gate structures 14 for both the PMOS transistor 100P and the NMOS transistor 100N. The spacers 20 are typically formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. Also depicted in FIG. 1B are illustrative raised source/drain regions 22P, 22N. In general, although the raised source/drain regions 22P, 22N are formed at different times, each of them may be formed by forming cavities in the substrate 10 of the appropriate gate stack and thereafter performing one or more epitaxial growth processes to grow a semiconductor material, such as silicon/germanium or silicon/carbon in the cavities. The raised source/drain regions 22P, 22N are typically doped with an appropriate dopant material at the time the semiconductor material is formed, i.e., an in situ doping process.
To form the structure depicted in FIG. 1B, a series of masking steps are performed to expose one of the active regions, e.g., the P-active region 10P, while covering the other active region, e.g., the N-active region 10N. This masking process is required because the different devices, i.e., the PMOS transistor 100P and the NMOS transistor 100N, are comprised of different materials and each may be manufactured using slightly different techniques. Several of these masking processes may be performed to form the device 100 depicted in FIG. 1B. For example, the NMOS device 100N may be masked when the sidewall spacers 18 are formed for the PMOS device 100P and, conversely, the PMOS device 100P may be masked when the sidewall spacers 18 are formed for the NMOS device 100N. Unfortunately, the area above the isolation region 12, including the gate structure 14 positioned thereabove, is typically masked during all of these various masking and etching processes. As a result, the overall height of the structure positioned above the isolation region 12 may be taller, and sometimes significantly taller, than the gate structures 14 of the adjacent transistor devices, which is more dominant for FinFET devices. These relatively tall structures are sometimes referred to as “bumps” within the industry. FIG. 1C is a picture of an integrated circuit device depicting the bumps 20 on a real-world device.
The presence of such bumps 20 can be problematic for several reasons. In general, with the very small devices that are being manufactured today, surface planarity is a very important aspect of device fabrication. Thus, the presence of such bumps causes a manufacturer to perform time-consuming and expensive process operations, such as one or more chemical mechanical polishing (CMP) operations, in an effort to remove such bumps 20. However, despite the best of efforts, performing such CMP processes may result in unacceptable levels of dishing, which may ultimately lead to variations in the thickness of the various gate electrode structures. Such variations may lead to the fabrication of integrated circuit products that have degraded performance capability and, in some cases, to the fabrication of products that do not meet performance specifications.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds