1. Field of the Invention
The present invention relates to a substrate with built-in passive elements such as a capacitor, an inductor, a resistor, a signal transmission element or an optical waveguide element.
2. Description of the Related Art
In the technical field of electronic component packaging, the 3D packaging is rapidly becoming mainstream instead of the conventional SMT (surface mount technology). Particularly, owing to an increasing demand for miniaturization, high speed and low power consumption, there has been a remarkable progress in the 3D-SiP technology, where the 3D packaging is combined with SiP (system in package) in which a system composed of a plurality of LSIs is enclosed in a single package. The SiP also has an advantage in reducing the power consumption, shorting the development times and reducing the cost. The integration of an advanced system can be achieved by the combination of the SiP and the 3D packaging which enables high density packaging.
As an essential technology for the above-mentioned 3D packaging, there has been known a TSV (through silicon via) technology. By using the TSV technology, a great deal of functionality can be packed into a small footprint, and critical electrical paths through the device can be drastically shortened, leading to faster operation.
However, when the operation is made faster by using the TSV (through silicon via) technology, for example, switching noise generated in a semiconductor chip may cause a malfunction of the integrated circuit. As a countermeasure against it, for example, it is effective to filter the noise by disposing a passive element such as a capacitor, an inductor or a resistor between a power bus line and a ground bus line. In this case, it is a common practice to additionally mount a finished passive component on or outside a multilayer circuit board.
However, if a capacitor is mounted on the circuit board as an additional component, the wiring inductance increases because of a large connection distance between the capacitor and the semiconductor chip, impairing the advantage of the TSV technology.
In order to deal with these problems, Japanese Unexamined Patent Application Publication No. 2007-220943 discloses a wiring circuit board having passive elements built therein, in which a pattern electrode is formed on a first thin-film multilayer wiring layer formed on one surface of a silicon substrate, and a thick-film passive element film is connected to the pattern electrode, and then, a second thin-film multilayer wiring layer is formed so as to cover the above members. The first thin-film multilayer wiring layer or the second thin-film multilayer wiring layer contains a thin-film passive element film.
In Japanese Unexamined Patent Application Publication No. 2007-220943, however, since the first thin-film multilayer wiring layer, the thick-film pattern electrode, the thick-film passive element film, the second thin-film multilayer wiring layer and the thin-film passive element film are formed on the silicon substrate, the entire thickness of the wiring circuit board having passive elements built therein inevitably becomes large.
Moreover, since the planar passive elements are arranged on the substrate, it is difficult to arrange the passive elements at high density. Therefore, it is less suitable for the TSV technology intended for high-density packaging.
USPTO Backgrounds
USPTO Backgrounds