Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. All memory can be considered either volatile or non-volatile.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures. These architectures are named for the resemblance that the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuits, respectively.
In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (word lines) and their drains are connected to column bitlines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the wordline connected to their gates. The row of selected memory cells then place their stored data values on the column bitlines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected column bitlines.
FIG. 1 illustrates a simplified diagram of a typical prior art NAND flash memory array. The memory array of FIG. 1, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bit lines are shown (BL1 and BL2) when the number of bit lines required actually depends upon the memory density.
The array is comprised of an array of floating gate cells 101 arranged in series strings 104, 105. Each of the floating gate cells 101 are coupled drain to source in each series chain 104, 105. A word line (WL0-WL31) that spans across multiple series strings 104, 105 is coupled to the control gates of every floating gate cell in a row in order to control their operation. The bit lines BL1, BL2 are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.
In operation, the word lines (WL0-WL31) select the individual floating gate memory cells in the series chain 104, 105 to be written to or read from and operate the remaining floating gate memory cells in each series string 104, 105 in a pass through mode. Each series string 104, 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line (BL1, BL2) by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
During a read operation, the unselected word lines of a selected memory block are biased at Vpass—read that is typically approximately 5V. This enables the unselected memory cells to act as pass gates for the memory cells on the selected word line.
FIG. 2 illustrates a plot of control gate voltage (Vcg) versus drain current (Id) during a read operation. During a read of the memory cells on WL0 208, there are no source side pass gates. The select gate source transistor is adjacent to the memory cells of WL0. Therefore, the memory string resistance between the selected memory cell and ground is minimal and the sub-threshold slope 208 is very steep. However, a drain-side cell read operation (e.g., WL31) has a greater quantity of memory cells between the selected cell and ground and, therefore, a larger string resistance during a read operation. This provides a gentler sub-threshold slope 210 and an increased probability of read failure due to decreased cell current caused by the increased resistance. The plot for the middle word line (i.e., WL16) shows a slope 209 between the other slopes 208 and 210.
FIG. 2 also shows the drain current pass/fail trip point 200. This is the Id at which a memory read operation either passes or fails, depending on Id. The read voltage, Vcg 203, is shown as the vertical dotted line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to address read failure in a memory device.
USPTO Backgrounds
USPTO Backgrounds