The following relates to the electronic arts, electronic devices arts, electronic circuitry arts, and related arts.
Silicon based field effect transistor (FET) devices are building blocks of silicon-based digital, analog, and hybrid electronics. In a known approach, a metal-oxide-silicon (MOS) structure is used, where in practice the “oxide” may be replaced by various dielectric materials of suitable characteristics. p-type MOS devices and n-type MOS devices are interconnected to generate so-called “complementary” MOSFET circuits, known as CMOS transistor circuitry, that has substantial advantages in terms of low power and high speed operation. In an ever-increasing quest for high device speeds, a principle design optimization tool has been reduction of the channel length, which for CMOS devices is now well into the submicron range for commercial devices. A side benefit is miniaturization of the CMOS circuitry leading to ever more compact electronics.
However, CMOS technology is believed to be approaching certain fundamental limits with respect to channel length, power consumption, steep subthreshold slopes, and related aspects such as leakage current and defect effects that may impose limits on the speed of CMOS circuitry. These limitations are considered to be consequences of the rather complex material formulation of CMOS which combines electronic conductor, dielectric, and semiconductor materials, with the primary electrical current flowing laterally along and proximate to the dielectric/semiconductor interface.
Substantial effort has therefore been directed toward developing improved performance device topologies that can be scalable to still smaller dimensions with consequent speed enhancement. Diffusion-based current transport is limited by thermal broadening and sets a limit upon CMOS transistor subthreshold slopes of 60 mV per decade of current, which in turn restricts their low-voltage operation. As chip power consumption has become a premium challenge, a shift towards lower drive voltages mitigates some power losses, but now a physical barrier exists for conventional CMOS.
One approach to break this physical barrier is the tunneling field effect transistor (TFET). For example, one TFET configuration is the p+in diode design, in which a degenerately p-type silicon layer is spaced apart from an n-type silicon layer by a low-doped silicon separator layer (the “i” silicon layer, which may in general be either p-type or n-type but is generally doped at a lower magnitude than the p+ and n end regions). Unlike MOS devices that to date employ lateral current conduction, many TFET designs envisioned are vertical devices, although some lateral TFETs are sought to retain lateral topologies for historical consistency. Some such vertical devices are described, for example, in Bhuwalka et al., “Vertical Tunnel Field-Effect Transistor”, IEEE Transactions on Electron Devices vol. 51 no. 2 pp. 279-82 (2004) and Sedlmaier et al., “Gate-controlled resonant interband tunneling in silicon”, Applied Physics Letters vol. 85 no. 10, pp. 1707-09 (2004).
The p+in TFET device design operates on the basis of band-to-band tunneling current injection into the channel, bypassing limits placed by diffusion injection. Advantageously, it is reported that the device can operate substantially symmetrically in either an “n-channel” mode or a “p-channel” mode. In the n-channel mode a positive gate bias induces a tunnel junction proximate to the p+ silicon layer; whereas, in the p-channel mode a negative gate bias induces a tunnel junction proximate to the n-type “drain” end of the diode. Yet another advantage is that the use of heavy doping in the p+in diode design might be expected to lead to suppressed impact of defects on the TFET device performance.
However, in the unbiased state there is little or no excess charge available proximate to the junction. As a consequence, turn-on voltage is undesirably high. The “on” current density is also lower than desired for device applications. Further, the p-channel operating mode does not exhibit drain current (ID) saturation, which limits applicability in digital circuitry and leads to asymmetry between the performance of the p-channel and n-channel TFET devices, respectively. The lack of truly symmetric n-channel and p-channel devices also constrains the ability to mimic the complementary transistor circuitry of CMOS technology in this TFET system.
To reduce turn-on voltage, it has been proposed to replace the p+ silicon layer with a thin, degenerately doped p-type silicon germanium (SiGe) layer. Such devices are proposed and mathematically modeled in Bhuwalka et al., “Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering”, IEEE Transactions on Electron Devices vol. 52 no. 5, pp. 909-17 (2005). In this variant p+in diode TFET, the lower bandgap of the thin p+ SiGe layer provides a quantum confinement for storing excess charge proximate to the source (p-end) of the pin diode junction, which is predicted to improve “on”-current and threshold voltage characteristics.
However, these p+-SiGe/i-silicon/n-silicon diode TFETs also have problems. Reported results so far have shown smaller “on” currents than will be required for circuit drive compatibility and smaller “off” currents than desired. The mathematical simulations predict increased “off” currents with increasing Ge content. The ratio of “on” current to “off” current is an important parameter impacting device applicability in diverse areas. For example, reliable low-power digital electronics rely upon a small ratio to enable the use of low “on” voltages. Additionally, the inclusion of Ge at the p-source end is predicted to affect the n-channel device performance more greatly, thus increasing the already-significant performance asymmetry between the n-channel and p-channel modes observed for the homogeneous p+in silicon diode TFET devices.
Accordingly, improved TFET designs would be advantageous for use in FET applications generally, and for use in complementary (that is, “CMOS-like”) elements particularly.
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