1. Field of the Invention
The present invention relates to a data processor specialized for inner product operation or matrix operation, and further to a data processing system optimal for three-dimensional graphics control, and relates to a technology effective as applied for a data processor for executing application frequently using floating point number vector or matrix less than or equal to length 4, for example.
In three-dimensional graphics and so forth, matrix operation employing 4.times.4 transform matrix for rotation, expansion, contraction, perspective projection and parallel translation and so forth of a graphic pattern may be often utilized, and inner product operation may also be utilized for determining brightness of a light receiving surface, and so forth. Repeating of multiply-add operations is necessary for such matrix operation or inner product operation. Also, in concerning data to be handled in three-dimensional graphics, floating point number has been conventionally used in a high-end system. Even in the field having severe constraint of cost, such as a game machine, handheld PC and so forth, the handling data is shifting from integer to floating point number method. This is because that floating point number facilitates programming and is adapted to higher level process.
2. Description of the Related Art
A multiply-add unit is designed to perform operation of (A.times.B)+C as single function. For example, "PA-8000 Combines Complexity and Speed", Microprocessor Report, Vol 8, No. 15, Nov. 14, 1994, pages 6 to 9, there has been disclosed a processor employing the multiply-add unit, in which parallelism of the multiply-add unit has been 2.
In "Nikkei Electronics" (Nikkei PB K.K.) No. 653, Jan. 15, 1996, pages 16 to 17, there has been disclosed a semiconductor integrated circuit, in which three-dimensional drawing function is integrated on one chip. In the disclosed semiconductor integrated circuit, a multiply-add unit performing operation of eight fixed point number data in one cycle, has been incorporated thereinto. Also, there is a disclosure that transformation of coordinates utilizing 4.times.4 matrix can be processed in two cycles.
On the other hand, JP-A-64-3734 discloses a multiplier circuit constituted of four multipliers and an adder summing the outputs of four multipliers with matching digits. Since the multiplier circuit is adapted to process multiplication of basic word length and double word length. Therefore, digit matching function is simply specialized for this process and thus, inner product operation of floating point number cannot be performed.
In JP-A-5-150944, a digital signal processor having a plurality of multiply-add units and means for connecting therebetween has been disclosed. The digital signal processor is adapted for integer.
Also, JP-A-5-216657 discloses a high speed processor for digital signal processing. There is a disclosure for geometry process employing a multiply-add unit for floating point number by the high speed processor.
On the other hand, JP-A-5-233228 discloses a floating point arithmetic unit and operation method thereof. There is a disclosure of means for reducing size of a floating point unit. However, since the disclosed system makes a multiplying array into half to use twice, the performance becomes half. Since components other than multiplying array are not reduced the sizes, an area-to-performance ratio of the floating point unit is lowered.
All of the above set forth have not considered speeding up of 4.times.4 matrix operation or inner product operation, at all.
USPTO Backgrounds
USPTO Backgrounds