A transistor is a solid-state semiconductor device that can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a voltage applied to the gate (G) controls current flowing between the source (S) and drain (D). In FETs, the source-to-drain current flows in a narrow conducting channel formed near (usually primarily under) the gate. This conductive channel permits electrical current to flow between the source and drain terminals. By varying the voltage between the gate (G) and source (S) terminals, the conductive channel region is widened and narrowed in response, thereby making the electrical path between the drain (D) and source (S) terminals (via the channel region) correspondingly more or less conductive controlling the current flowing therebetween.
FIG. 1 shows a cross-sectional view of a FET 100 and the schematic symbol 120 generally associated therewith. The FET 100 comprises a p-type substrate 102 (which may be implemented as p-well in an n-type substrate), and two spaced-apart n-type diffusion areas 104A and 104B, one of which (104A) serves as the “source” of the transistor while the other (104B) serves as the “drain” of the transistor. A thin dielectric layer 108 (“dielectric”) is disposed on the substrate overlying and spanning the space between the source 104A and drain 104B, and a “gate” conductor 106 (G) is disposed atop the dielectric layer, also spanning the space between the source 104B and drain 104B. The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”. The area 110 of the p-type substrate 102 between the n-type source 104A and n-type drain 104B immediately underlying the dielectric 108 is the “channel” of the FET 100. The channel 110 is where current flows between the source 104A (S) and the drain 104B (D).
Electrical connections (not shown) may be made to the source 104A (S), the drain 104B (D), and the gate 106 (G). The substrate 102 may be grounded or biased at a desired voltage depending on the application.
Assuming that the substrate 102 and source 104A are kept at the same voltage (e.g., by connecting them together), the voltage applied between the gate 106 and source 104A controls the conductivity of the channel 110. Generally, when the gate-to-source voltage (Vgs) is zero and a positive voltage (relative to the source 104A) is applied to the drain 104B, there is no electrical conduction between the source 104A (S) and the drain 104B (D) because the “p-type” material in the channel 110 forms a non-conductive “depletion region” free of mobile carriers. As voltage applied to the gate 106 becomes more positive relative to the source 104A, a “field effect” occurs in the channel 110 whereby the positive voltage attracts free electrons in the substrate 102 into the channel region. Before current can flow in the channel, however, enough electrons must be attracted into the channel region 110 to counter the p-type dopant ions therein. The gate-to-source voltage at which this occurs is known as the “threshold voltage” (Vt) of the FET. As the gate-to-source voltage is increased above Vt, additional free-floating electrons attracted into the channel 110 effectively convert the p-type material to n-type, permitting current flow between source 104A and drain 104B. When Vgs is below the threshold voltage Vt the channel 110 is non-conductive. When Vgs is greater than Vt, the channel 110 is conductive, with greater conductivity associated with greater Vgs.
The FET 100 shown in FIG. 1 is typical of an n-channel enhancement mode MOSFET. It is referred to as an “n-channel” device because conduction occurs through an n-type conductive channel formed in a p-type substrate. It is referred to as an “enhancement mode” FET because in its un-energized state with zero gate-source voltage, the channel is non-conducting. The field-effect is used to “enhance” the normally non-conductive channel region to make it conductive. The name “MOSFET” refers to the physical configuration of the FET: metal (gate) overlying oxide (dielectric) overlying semiconductor (channel/substrate), hence Metal-Oxide-Semiconductor FET. Hereinafter, this type of n-channel FET will be referred to as an “nFET”.
Exchanging p-type and n-type dopants in the example of FIG. 1 creates a similar, but oppositely polarized “p-channel” MOSFET or “pFET”. A pFET is formed in an n-type substrate (or in an n-well). Spaced-apart p-type source and drain regions are formed within the substrate (or well) and a thin gate oxide and gate conductor are formed above the space between the source and drain regions. This pFET behaves in exactly the same way as the nFET, but with opposite polarity. In CMOS (complementary metal oxide semiconductor) technology, nFETs and pFETs are connected in complementary paired configurations to form amplifiers, inverters, gates, etc.
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
SOI Substrates
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire (also known as silicon-on-sapphire or “SOS”). The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost silicon layer also vary widely with the intended application.
SiO2-based SOI substrates (or wafers) can be produced by several methods:
SIMOX—Separation by IMplantation of OXygen—uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.
Wafer Bonding—the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
Seed methods—wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.
An exemplary SOI-type substrate may comprise a layer of silicon (“SOI”) atop a buried oxide (BOX, insulator) layer, which is atop an underlying substrate which may be a silicon substrate. The BOX layer may have a thickness of 500-2500 Å (50-250 nm). The silicon (SOI) layer may have a thickness of 50-200 Å (5-20 nm). Pad films comprising a layer of oxide and a layer of nitride may be disposed atop the SOI layer. The pad oxide layer may have a thickness of 10-20 Å (1-2 nm), and the pad nitride layer may have a thickness of 400-1500 Å (40-150 nm).
Silicon-on-insulator (SOI) devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of “latchup,” which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
A drawback in some SOI circuits is the floating body effect. Due to the additional isolation of the SOI device, the body or well node is not typically contacted. In principal, body tie structures may be employed in SOI CMOS to add a contact to the floating body node, but this introduces parasitic resistances and capacitances that would negate the favorable impact of adaptive well biasing.
For many digital circuits, this impact can be neglected. However, certain circuit array cell stability, such as the commonly used 6T (six transistor) SRAM cell, is degraded due to tolerance issues arising from the floating body. This is typically handled by increasing the linear threshold voltage (Vt) of the FETs in the array, but this is usually at the cost of lowering the overall array performance.
SRAM
Static random access memory (SRAM) is a type of semiconductor memory where the word “static” indicates that it, unlike “dynamic” RAM (DRAM), does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. However, SRAM is still volatile in the (conventional) sense that data is lost when powered down.
Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit.
A typical static random access memory (SRAM) cell includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up pFET (p-channel) transistor connected to a complementary pull-down nFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch which stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor cell, a pair of access transistors or pass gates (when activated by a word line) selectively couple the inverters to a pair of complementary bit lines.
Typically, memory cells are arranged in an array comprising many rows and columns, between wordlines extending horizontally (as usually depicted) across the array and bitlines extending vertically (as usually depicted) up and down the array. A memory array typically comprises many millions (“mega”), including billions (“giga”) of memory cells.
FIG. 2 illustrates a single conventional six-transistor (“6T”) SRAM memory cell 200 connected to two adjacent bitlines 232 (BL) and 234 (BR), and one wordline 220 (WL). The memory cell may also be connected to a voltage source (Vdd) and ground (gnd).
The SRAM cell structure includes a memory cell 200 (in dashed lines) comprising six interconnected MOSFET transistors 202 (P1), 204 (N1), 206 (P2), 208 (N2), 210 (NL) and 212 (NR). Transistors 202 (P1) and 206 (P2) are pFETs; the other four (204, 208, 210 and 212; N1, N2, NL and NR, respectively) are nFETs. pFET P1 202 and nFET N1 204 are connected to form a CMOS inverter circuit, such that a source terminal of pFET P1 202 is connected to Vdd, a source terminal of nFET N1 204 is connected to ground; gates of P1 202 and N1 204 are connected together, forming an input of the inverter and drains of P1 202 and N1 204 are connected together forming an output (“A”) of the inverter. Considering the P1-N1 inverter configuration by itself in isolation, the input voltage will be assumed to be either Vdd (“high” or logic “1”) or ground (“low” or logic “0”). When the input of the P1-N1 inverter formed by P1 202 and N1 204 is at Vdd (logic “1”), the channel of N1 204 is conductive and the channel of P1 is non-conductive, effectively creating a (relatively) low-impedance path from the output of the inverter to ground. Assuming no other circuit influence (i.e., NL 210 is in a non-conducting state), then since P1 202 is non-conductive in this state no current flows through N1 204 and the voltage at the output (“A”) of the inverter is at ground potential (logic “0”). Conversely, when the input of the inverter is at ground potential (logic “0”), the channel of P1 202 is conductive while the channel of N1 204 is non-conductive. Again assuming no outside circuit influence, no current flows through either P1 202 or N1 204, but since P1 204 is conductive and N1 is non-conductive in this state, the output (“A”) of the P1-N1 inverter is at Vdd potential (logic “1”). Accordingly, whichever state the input of the P1-N1 inverter assumes, the output will assume the opposite or “inverse” state—hence the name “inverter”.
pFET P2 206 and nFET N2 208 are similarly connected in an inverter configuration, producing an output “B”. The P1-N1 inverter is cross-connected with the P2-N2 inverter such that the output “A” of the P1-N1 inverter connects to the input of the P2-N2 inverter and the output “B” of the P2-N2 inverter connects back to the input of the P1-N1 inverter in a positive feedback configuration that forms a bi-stable “latch” circuit. The circuit is bi-stable, because it has two possible states and if undisturbed, it will remain indefinitely in whichever of the two states it is placed.
The voltages at the outputs “A” and “B” of the P1-N1 and P2-N2 inverters characterize the two states of the bi-stable latch circuit. If “A” is at logic “0”, then the output “B” of the P2-N2 inverter (which has “A” as its input) will be at logic “1”. Since “B” provides the input to the P1-N1 inverter, this reinforces the logic “0” at “A”, which is also the output of the P1-N1 inverter. This circuit state is stable and will remain indefinitely unless disturbed or until power is removed. Accordingly, this circuit condition characterizes one state of the bi-stable latch formed by P1 202, N1 204, P2 206 and N2 208.
Conversely, if “A” is at logic “1”, then the output “B” of the P2-N2 inverter (which has “A” as its input) will be at logic “0”. Since “B” provides the input to the P1-N1 inverter, this reinforces the logic “1” at “A”, which is also the output of the P1-N1 inverter. This circuit state is also stable and will remain indefinitely unless disturbed or until power is removed. Accordingly, this circuit condition characterizes a second state of the bi-stable latch formed by P1 202, N1 204, P2 206 and N2 208.
In this bi-stable latch circuit, since no current flows in either stable state, transistors P1 202, N1 204, P2 206 and N2 208 need not present a very low impedance to Vdd or ground in their respective conductive states. This means that if a very low-impedance driving circuit is connected to output “A” and/or output “B”, these outputs can be overwhelmed and overridden to place them at a different potential. nFET NL 210 acts as a passgate (effectively a switch) to connect the output “A” of the P1-N1 inverter to a bitline BL 232, and nFET NR 212 acts as another passgate to connect the output “B” of the P2-N2 inverter to another bitline BR 234. The gates of NL 210 and NR 212 are connected together to a “write line” WL 220 so that they operate in concert. When WL 220 is at Vdd potential (logic “1”), NL 210 and NR 212 are conductive, connecting “A” to BL 232 and “B” to BR 234. Conversely, when WL 220 is at ground potential (logic “0”) NL 210 and NR 212 are non-conductive, effectively isolating “A” and “B” from BL 232 and BR 234.
Bitlines BL 232 and BR 234 can be driven by a low impedance source to opposite logical states. When WL 220 is at a logic “0” state (ground-NL 210 and NR 121 non-conducting) the state of the bi-stable latch formed by P1 202, N1 204, P2 206 and N2 208 is unaffected. However, when WL 220 is at a logic “1” state (Vdd), “A” is forced to assume to voltage level (logic state) present on BL 232 and “B” is forced to assume the voltage level (logic state) present on BR 234. If the voltage levels on bitlines BL 232 and BR 234 are opposite those present on “A” and “B”, respectively prior to when passgates NL 210 and NR 212 were made conductive, the bi-stable latch changes state. (It should be noted that although current must flow to overwhelm the inverter outputs, this current only flows until the bi-stable latch reaches its new stable state, at which time further current flow ceases.) When WL 220 is returned to logic “0”, NL 210 and NR 212 stop conducting and the bi-stable latch retains its new state. In this manner, the SRAM cell 200 can be placed in either of two stable states, which it will retain until re-written (as just described) or until power is removed.
Bitlines BL 232 and BR 234 can also be used to read out the current state of the bi-stable latch (SRAM cell 200) non-destructively. If bitlines BL 232 and BR 234 are left un-driven (i.e., in a high-impedance state), then when “WL” is at logic “1” (Vdd) potential, the voltages at “A” and “B” will appear on bitlines BL 232 and BR 234, respectively. Given that the SRAM memory cell 200 can assume either of two stable states, that those states can be externally applied and can be read back non-destructively, the SRAM memory cell 200 can be said to be capable of storing one “bit” (binary digit) of information.
Leakage in MOSFETs
It is well known to those of ordinary skill in the art that even when well formed, practical MOSFET devices may exhibit some very small amount of “leakage”, which as used herein refers to undesired current flow between source and drain when a transistor is in its “off” or nominally non-conducting state. Generally, in well-formed MOSFETs, such leakage current is near zero and is vanishingly small when compared to “on” state current. It is also well known that certain types of defects in the fabrication and processing of MOSFETs devices can result in leakage currents that are much higher than normal.
CMOS (Complementary MOS) circuits (such as inverters and logic gates) generally rely on complementary pairings of n-channel and p-channel MOSFETs (nFETs and pFETs) wherein nFET and pFET devices are operated alternately such that when an nFET device is active or “on” (conducting) its associated complementary pFET device is inactive or “off” (non-conducting), and vice-versa. As a result, only leakage current flows in a CMOS circuit that is in a stable, non-transitioning logic state.
When leakage current is near zero (which is the normal case for well-formed MOSFETs) then CMOS circuits require virtually zero-power to maintain their stable, non-transitioning logic states. However, high leakage current in even a single transistor can cause numerous problems in CMOS circuits, including, but not limited to: high power consumption, localized heating, and significant change in the output voltage representing either or both of the circuits stable logic levels. These localized problems due to MOSFET leakage can in turn cause problems in other neighboring CMOS circuits to which such leakage-affected circuits connect. Depending upon circuit configuration and the severity of a leakage defect, a single “leaky” MOSFET can render useless an entire semiconductor chip comprising millions of MOSFETs. For example, in the absence of redundancy mechanisms, even a single bad “bit” in a large SRAM device comprising millions of bits of storage capacity would constitute an irrecoverable failure of the device.
USPTO Backgrounds
USPTO Backgrounds