The present invention provides synchronous state machines for efficiently handling the erasing and programming of flash memory cells in a flash memory device.
On-chip state machines are used to control the memory erase process in many flash memory devices. However, in many of these devices, when the erase state machine aborts, the discharge of high voltages from internal nodes is not a well controlled process. Race conditions can occur, such as failure of the discharge process to complete prior to the performance of a next operation by the memory device.
It is a goal of the present invention to make the erasing and programming of flash memory cells quick and easy for end users, and to provide mechanisms for appropriately and reliably handling (A) user abort requests to abort an erase or programming operation in mid-process, and (B) device failures in which one or more memory cells fails to erase or program after a reasonable number of erase or program cycles.
USPTO Backgrounds
USPTO Backgrounds