1. Technical Field of the Invention
The present invention relates generally to system on chip (SoC) circuits and, more particularly, to a method and apparatus for maximizing energy efficiency of SoC circuit operation by dynamically operating the SoC circuit at the margins of acceptable voltage and/or frequency.
2. Description of Related Art
A system on chip (SoC) circuit is typically designed with “worst case” process and operating conditions (such as voltage and temperature) in mind. The actual or typical operating conditions for the SoC circuit are rarely at or even near such worst case conditions, and thus the SoC circuit most often operates with more than necessary safety margins. This is undesirable to some degree as it results in inefficiency. However, it is known to try and recover these available margins by operating the SoC circuit with reduced voltage (lower power) and/or increased frequency (increased throughput) for a given operating condition. Some dynamic control can be exercised over this operation. When trying to recover these available margins dynamically, however, instances may arise where the SoC circuit is placed into a near failure region. In such instances, the possibility of timing failures due to operating condition variation must be addressed through a recovery operation.
There is accordingly a need for a system which can not only adaptively control operating conditions of a SoC circuit (such as voltage and/or frequency) so as to achieve lower power for a given speed or higher speed for a given power, but also provide for fault-free operation and further predict failure and provide for fault-free recovery from such adaptive changes in operating conditions so as to prevent failure.
Reference is now made to FIG. 1 which shows a block diagram of a prior art adaptive voltage scaling (AVS) solution for a system on chip (SoC) circuit. The system on chip circuit 10 includes a digital domain 12 which receives a regulated (variable) voltage Vdd. The regulated (variable) voltage Vdd is generated by an adaptive voltage scaling circuit 14 (separate from the SoC circuit 10) that includes a voltage regulator 16. The output of the voltage regulator 16 is the regulated (variable) voltage Vdd applied to the digital domain 12 of the SoC circuit. A controller 18 outputs a control signal applied to the voltage regulator 16. The control signal sets the value of the regulated (variable) voltage Vdd.
The AVS circuit 14 further includes a critical path replica circuit 20 which is also powered by the regulated (variable) voltage Vdd output from the voltage regulator 16. The critical path replica circuit 20 is a standalone sensor for timing margins by replicating circuits and conditions in the digital domain of the SoC. Circuits of this type are well known to those skilled in the art (see, for example, Drake, et al., “A Distributed Critical-Path Timing Monitor for a 65 nm High-Performance Microprocessor,” ISSCC 2007, Session 22, pages 398-399, FIG. 22.1.1, the disclosure of which is hereby incorporated by reference). The output of the critical path replica circuit 20 is a margin signal which is applied to the input of the controller 18. The controller responds to the margin signal by adjusting the regulated (variable) voltage Vdd applied to the digital domain 12 (for example, by lowering the voltage to recover available operating system margin).
Analogously, the controller may alternatively, or additionally, respond to the margin signal by adjusting the clock frequency of SoC circuit digital domain 12 operation (for example, by increasing clock frequency to recover available operating system margin). This adaptive frequency scaling (AFS) implementation is not shown in FIG. 1.
The circuit of FIG. 1, however, does have a deficiency. It is noted that some variations in operating performance can, and often do, exist between the critical path replica circuit 20 (within the separate AVS circuit 14) and the critical path circuits within the SoC circuit digital domain 12. Such variations may exist with respect to voltage, frequency, or both. As such, there exist variations between the available voltage or frequency margin estimated by the critical path replica circuit 20 and the actual margins of the SoC circuit digital domain 12 critical path circuits where the supply voltage and/or clock frequency adjustments are actually applied. The variability experienced between the estimated and actual margins for a given SoC circuit may be due to one or more of the following factors: a) static variability due to spatial differences in circuit characteristics; b) dynamic variability due to differences between the actual circuit and the sensor circuit caused by supply network, local temperature variation and local aging; c) real time operation differences.
Ideally, it would be beneficial to exercise the critical paths of the SoC circuit to validate that the margins after adaptive voltage scaling (as controlled by the critical path replica) are indeed sufficient. However, the prior art discussed above does not provide a mechanism for exercising the critical paths of the SoC circuit deterministically during operation. The AVS solution of the prior art accordingly cannot be said to be fail safe under an actual low energy operating point. The controller 18 may instruct the voltage regulator 16 to apply a regulated (variable) voltage Vdd (based on the margin signal output from the critical path replica circuit) whose level is sufficient for satisfying critical path replica circuit 20 operations but is insufficient to properly operate the actual critical path circuits within the digital domain 12 of the SoC circuit. Inadvertent failure may result. Likewise, controller 18 may select a clock frequency (based on the margin signal output from the critical path replica circuit) that is sufficient for critical path replica circuit 20 operations but insufficient to properly operate the critical path circuits of the digital domain 12 for the SoC circuit.
There is a need in the art to address the foregoing deficiencies.
USPTO Backgrounds
USPTO Backgrounds