1. Field of the Invention
The invention relates in general to image processing. More particularly, this invention relates to a method and apparatus for improving the performance of an SDRAM-based memory buffer in imaging applications that require efficient access to multiple lines of an image bitmap.
2. Description of the Related Art
Image processing algorithms frequently modify pixels within an image to effect some desired improvement or to detect some characteristics of the image. Most of these algorithms are based on the nearest neighbors of each particular pixel, requiring calculations for several lines of the image data. Access to neighboring pixels on multiple lines of the image can be slower when the image is stored in dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM) due to the functional characteristics of the memory devices. For DRAM and SDRAM, pixel data in a common row in memory can be accessed very efficiently, but accessing pixel elements in other rows can be quite inefficient.
DRAM devices support a “page mode” operation whereby, once a particular row of the memory array is accessed, subsequent accesses to the same “open” row can be immediate. However, accesses to pixel data in other rows of the memory array require that the current row be “closed” and the new one “opened” before actual data access cycles can take place. SDRAM devices typically have four separate internal memory arrays, each of which may have a current open row. This improves performance in that four regions of memory can be accessed efficiently without opening and closing rows. For example, if an image processing algorithm required access to four lines of the image data, and each of those lines resided in a different memory array, then efficient access is possible. Unfortunately, many algorithms will require access to a greater number of lines of the image, so some of the accesses will require opening and closing a row for each pixel read or write.
In environments where more lines must be accessed than there are separate memory arrays available, and the controlling device must open and close rows of the array for some accesses, the controlling device must either: a) open and close each row for every access; or b) be knowledgeable of which rows must be opened and closed in which memory array based on the address of the target data.
For these reasons, many image processing hardware implementations are based on static random access memory, either within an ASIC device or based on external SRAM devices. The SRAM devices are efficient due to the non-multiplexed nature of their address bus, but are more expensive, less dense and reduced in capacity. Image processing hardware implementations that operate on large, high-resolution images and implement algorithms based on many lines of the image are severely restricted by the smaller capacity of the SRAM devices. These implementations either hold only a small portion of the image in SRAM memory, or are very costly when large amounts of SRAM are implemented. The more cost effective, dense DRAM or SDRAM devices lack only in the bandwidth available due to the overhead cycles required to open and close rows of the arrays while accessing multiple lines of the image (for these types of nearest-neighbor algorithms).
In U.S. Pat. No. 6,286,075, Stracovsky discloses a method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M. However, Stracovsky does not address the improvements that can be achieved when sophisticated controller structures and features are complemented with dynamic addressing schemes that improve the probability that a desired set of items will be located within a single page of memory.
USPTO Backgrounds
USPTO Backgrounds