1. Field of the Invention
The invention relates to a clock distribution system for integrated circuits and PC boards, and more particularly to a clock distribution system which synchronizes the operation of multiple levels of logic simulation environments.
2. Description of the Related Art
Modern large scale digital circuitry utilizes one or more clock signals transmitted to many separate levels within the circuitry, each level can consist of several circuit blocks. Uniform timing of these clock signals is critical to system operation, as the amount of time required for information to flow through the processing circuitry in a single processing cycle can determine the efficiency of the system. Generally, one system clock signal is passed to the various levels within the system.
When a system clock signal is transmitted through the circuitry, delays to the clock signal may occur within the various levels. Delays throughout a large system are caused by a number of factors, including variations in manufacturing tolerances, differing logic schemes for generating and passing the signal from one level to the next, and long transmission lone propagation time. The clock signal could experience elongation of the clock pulse dwell time, shifting of the clock phase, which is known as skew, or latency. These delays can result in one level of system integration falling out of synchronization with other levels. Thus, uniform synchronization of the clocking signals in a large system is necessary for adequate real time performance.
Prior methods of achieving clock signal synchronization have been utilized with limited success. A common method of synchronizing two clocks is to adjust the timing of the remote clock to the system clock signal. Such a solution to synchronizing two clocks is shown in U.S. Pat. No. 5,118,975, issued Jun. 2, 1992, by Hillis et al. The ""975 patent utilizes a phase comparator to compare the system clock signal to the remote clock, and the phase of the remote clock is compensated to correct for the phase delay. However, this method does not fully account for inherent delays within the system. Calibrating the remote clocks to the system clock fails to resolve the problem of the system clock falling out of synchronization due to long propagation delays. Consequently, a clock delay at one level of the operating environment may differ from a delay at another level.
Similarly, the method of tuning clocks in U.S. Pat. No. 5,087,829, issued Feb. 11, 1992, by Ishibashi et al. uses a multiphase arrangement which provides tuning of multiple clocks at varying rates. The multiphase method uses a delay time detection circuit in the second phase which calculates the amount of delay in the system. Timing adjustments are accordingly made within the circuit to compensate for these system delays. This second control phase thus requires added circuitry to calculate system delay times. The delay time detection circuit depends on the number of clocks to be synchronized and the levels of delay for which to compensate. Therefore, this method does not provide a modular solution, since the circuits cannot be used interchangeably.
These prior art solutions cannot be uniformly adapted for modular application since they were either only suitable for particular designs, required significant hardware to implement, or otherwise reduced overall system performance. In view of these deficiencies in the prior art, it should be apparent that there exists a critical need for a modular integrated circuit clock distribution method.
Accordingly, it is an object of the present invention to provide a modular strategy for clock distribution within a logical simulation environment, which minimizes latency and skew delays and improves system efficiency.
The invention provides a new and improved clock distribution method for use in connection with either integrated circuit chips or printed PC boards constituting part of a digital simulation environment. The method compensates for the latency and skew delay to the clock signal induced by the independent blocks of the system.
Rather than synchronizing the clock signal provided to each block of the environment to the system clock, the method of the present invention synchronizes the clock signal for each successive block to the clock signal from a preceding block which has experienced the greatest amount of delay. This way, each of the blocks would be turned to the slowest bock and would remain in synchronization with respect to each other. Subsequent blocks can be added to the system without risk of losing synchronization.
In accomplishing these and other objections, there is provided an improved clock distribution system for a system having a series of independent blocks, with each independent block having an average load tap signal. The clock distribution circuit uses the load tap signal from the slowest independent block (A_BACK) to synchronize the clock used in the remaining blocks. The clock for the subsequent block (B_CLOCK-OUT) is tuned to the A-BACK signal. The system clock signal (CLK) is incrementially delayed until it is in tune with the A-BACK signal, then it can be provided to the subsequent block as the B-CLOCK-OUT signal.
The clock distribution system consists of several sequential delay stages to incrementally delay the CLK signal. A shift register controls each stage of delay, by enabling a multiplexer to allow the incrementally delayed CLK signal to pass. The B_CLOCK_OUT signal is compared with the A_BACK signal of the previous slowest block. As long as the B_CLOCK_OUT signal is faster than the A_BACK signal, the shift register will incrementally increase the delay placed on the CLK signal. Upon reaching a match between the B_CLOCK_OUT signal and the A BACK signal, the shifting stops and the CLK signal has been synchronized with the A_BACK signal. If the magnitude of each incremental delay is equivalent to one-eighth of a clock pulse width, it would take a maximum of eight clock cycles to bring the B_CLOCK_OUT signal into synchronization with the A_BACK signal.
A more complete understanding of the integrated circuit clock distribution system will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by consideration of the following detailed description of the preferred embodiment. Reference will be made to the appended sheets of drawings, which will be first described briefly.
USPTO Backgrounds
USPTO Backgrounds