The performance of the CMOS logic devices has been greatly improved by using SOI (Silicon-On-Insulator) substrate. Yet, further improvement of the SOI logic chip was achieved by integrating DRAM compartments within the logic chip (e.g., Embedded DRAM on SOI). Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. The advantage of DRAM is its structural simplicity; i.e., only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. DRAM cell structures have been successfully scaled for several decades to increasingly smaller dimensions that allow for reducing manufacturing costs and increasing levels of integration within the DRAM cell structures.
While DRAM cell structures have been successfully scaled for several decades, the scaling of DRAM cell structures is not entirely without problems. In particular, such scaling, while physically achievable for both a field effect transistor and a storage capacitor within a dynamic random access memory cell structure, is problematic for the storage capacitor insofar as storage capacitors when aggressively scaled may not have adequate storage capacitance for proper operation of a dynamic random access memory cell structure.
However, it is becoming more and more difficult to maintain enhanced performance at decreased dimensions. Particularly, forming buried plate electrodes became extremely challenging. For example, with deep trench capacitors in SOI, the conventional diffusion doping or implanting process is becoming very difficult through smaller and smaller deep trench openings. That is, as the openings of the deep trench become smaller, it is becoming increasingly more difficult to implant dopants into the opening in order to form one of the plates from the substrate material. Also, during the doping process, unwanted implants are being implanted into the SOI. Additionally, due to the small spacing between the deep trenches, leakage between DT arrays become problematic. This leakage (i.e., lack of isolation between the deep trenches) results in adjacent capacitors turning on and off at the same time. Moreover, it has been found that after the SOI bonding/anneal process, dopants such as, for example, phosphorous, tend to diffuse from an epi layer into the underlying substrate, which may cause isolation issues.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds