In the production of microelectronic products, a microelectronic chip or die is typically packaged before it is sold. The package may provide electrical connection to the chip's internal circuitry, protection from the external environment, and heat dissipation. In one package system, a chip may be flip-chip connected to a substrate. In a flip-chip package, electrical leads on the die are distributed on its active surface and the active surface is electrically connected to corresponding leads on a substrate.
FIGS. 1A-1D illustrate a prior art method for producing and packaging a microelectronic chip or die. FIG. 1A illustrates a die 100 including a substrate 105, a device region 110, an interconnect region 115, a bond pad 120, a passivation layer 125, a barrier metal 130, and a bump 140. Interconnect region 115 includes a plurality of metal interconnect layers that interconnect the devices of device region 110 and provide electrical routing to external circuitry. The metal interconnect layers include metal traces separated and insulated by an interlayer dielectric (ILD) material. Adjacent metal interconnect layers are typically connected by vias which are also separated and insulated by an ILD.
FIG. 1A also illustrates an undercut 135. Undercut 135 may result from a barrier metal layer etch in the presence of bump 140 which etches a layer of barrier metal material from passivation layer 125 and leaves barrier metal 130. Undercut 135 provides a location for the formation of undesired cracks in passivation layer 125 and/or interconnect region 115. For example, undercut 135 may cause a first crack in passivation layer 125 which subsequently causes an additional crack or cracks in the ILD of interconnect region 115. The subsequent cracks may be connected to the initial crack or they may be disconnected from, but related to, the initial crack. In particular, low dielectric constant (low-k) ILD materials are typically susceptible to cracks. The cracks in passivation layer 125 and/or interconnect region 115 may cause poor performance or failure of die 100.
Further, even in the absence of an undercut, bump 140 and the corners of bump 140 near passivation layer 125 are typically causes of undesired cracking and stress in passivation layer 125 and the ILD of interconnect region 115.
In FIGS. 1B and 1C, die 100 is flip-chip bonded to a substrate 180 which includes bumps 190. In bonding die 100 and substrate 180, stresses are typically imparted on die 100 due to coefficient of thermal expansion mismatches between die 100 and substrate 180, and other causes. These stresses may cause additional opportunity for cracking in passivation layer 125 and/or interconnect region 115. Further, after die attach and during “sit” time prior to further processing, cracks may continue to propagate in passivation layer 125 and/or interconnect region 115. In FIG. 1D, an underfill 195 is formed between die 100 and substrate 180.
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