1. Field of the Invention
The present invention relates to a wiring board for mounting a semiconductor element, and to a method for manufacturing the same. The present invention particularly relates to a wiring board in which the connection via structure of the power source and ground is improved, and to a method for manufacturing the same.
2. Description of the Related Art
Examples of the heretofore used wiring boards for mounting a semiconductor element include ceramic wiring boards such as the one disclosed in Japanese Laid-open Patent Application No. 8-330474 that uses alumina or another insulating material; build-up substrates such as those disclosed in Japanese Laid-open Patent Application No. 11-17058 and Japanese Patent No. 2679681, in which an organic resin is used as the insulating material, and a micro-circuit is formed by forming copper wiring using an etching method and a plating method; and the tape-type substrate disclosed in Japanese Laid-open Patent Application No. 2000-58701, in which copper wiring is formed in a polyimide-based film or other film.
Recently developed boards for mounting a semiconductor element generally employ a build-up substrate that can be adapted to narrow-pitch connections. However, increased density is particularly sought in electronic devices such as mobile telephones. This demand results from rapid progress in miniaturization, thickness reduction, and increased density, as well as the increase in the number of terminals that accompanies increased speed and functionality of semiconductor elements.
Particularly in build-up substrates for mounting semiconductor elements, it has become possible to stably provide a minute pattern having a wiring pattern width of 25 μm and a via diameter of about 70 μm. However, the circuit dimensions that a build-up substrate must accommodate are increasing due to increases in performance and functionality of semiconductor elements. It is therefore not uncommon for the layer count to reach ten or more even when micro-wiring and an extremely small via diameter is used.
Diminished electrical characteristics due to increased wiring resistance have become a problem in this type of multilayer board that uses micro-wiring and an extremely small via diameter. Specifically, increased wiring resistance creates a situation in which the power source voltage supplied is insufficient for operating the semiconductor element, and the system fails to operate. A method for providing a plurality of vias having the same shape is employed as a measure for overcoming this problem, but this method has problems in that the surface area used exclusively by the vias and the conductor connected to the vias increases, making it more difficult to increase the density.
USPTO Backgrounds
USPTO Backgrounds