Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored information when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and phase change random access memory (PCRAM), among others.
Various types of memory can be used in memory systems. For example, Flash memory can be part of a memory system as internal memory or as removable memory that can be coupled to the memory system through an interface via a format such as USB (universal serial bus), MMC (multi media card), CF (compact flash), or SD (secure digital), among others. Flash memory devices, including floating gate flash devices and charge trap flash (CTF) devices, may be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for sold state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. Some uses of flash memory may include multiple reads of data programmed to a flash memory device without erasing the data.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases form) an access line (e.g., a word line as commonly referred to in the art). However each memory cell is not directly coupled to a data line (e.g., a bit line as commonly referred to in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a bit line, where the memory cells commonly coupled to a particular bit line are referred to as a “column”.
A NAND memory device can include a number of arrays of memory cells organized into physical blocks of memory cells. Data stored in the blocks can become corrupted due to various mechanisms (e.g., program disturb, read disturb, and/or erase disturb, among other mechanisms). For instance, one or more bits of data associated with a page of data being read may have changed (e.g., become incorrect) since it was stored to a particular block. Many memory systems employ an error detection/correction engine capable of detecting and correcting a certain number of incorrect bits associated with read operations. Such detection/correction engines may use an error correction code (ECC) to detect and/or correct incorrect bits. An ECC failure results when the detection/correction engine is not capable of correcting all of the incorrect bits within the data being read (e.g., the number of bit failures within the data exceeds the correction capabilities of the detection/correction engine). This can be referred to as an uncorrectable ECC error (a UECC error).
A UECC error can indicate that the data stored within a particular block has become corrupted (e.g., one or more bits have become incorrect due to various disturb mechanisms). A UECC error can also indicate that a particular block/page is defective (e.g., the particular block/page includes defective memory cells). As such, future read operations on the same block/page may also result in UECC errors, which can result in reduced system performance and/or system failure. In various memory systems, a block/page is retired from use if an uncorrectable ECC error is encountered in association with a read operation performed on the block/page. However, retiring blocks/pages from use has drawbacks such as reducing the memory capacity of the system and increasing wear on the remaining blocks/pages, which can reduce the effective life of a memory device, among other drawbacks.
USPTO Backgrounds
USPTO Backgrounds