I. Field of the Invention
This invention relates to a high speed memory system and related method with 100% bandwidth capability.
II. Background Information
Memory systems are known which have the capacity to store a large amount of data and which further have the capacity to communicate that data to a plurality of input/output ports over an interconnecting data bus. One such memory system is illustratively illustrated in FIG. 1. The prior art memory system of FIG. 1 includes a memory board 10, a plurality of input/output ports 12, a data bus 14, an address bus 16, a control bus 18, and a request and acknowledge bus 20.
Memory board 10 is illustrated as comprising address buffer 22, memory control 24, memory 26 and data buffer 28. Address buffer 22 has an input connected to address bus 16 and an output connected to an address input of memory 26. Memory 26 has a data terminal coupled to a first data bus terminal of data buffer 28 and data buffer 28 in turn has a second data bus terminal connected to data bus 14. The operation of address buffer 22, memory 26 and data buffer 28 is governed by the operation of memory control 24 which has an input connected to control bus 18.
Input/output ports 12 each comprise an address generator 30, input/output port control 32, memory 34 and data buffer 36. Address generator 30 has an output coupled to address bus 16. Address generator 30 is coupled by address bus 36 to an address bus terminal of memory 34. Memory 34 has a data bus terminal connected by data bus 38 to a first data bus terminal of data buffer 36. Data buffer 36 has a second data bus terminal coupled to data bus 14. The operation of address generator 30, memory 34 and data buffer 36 is governed by input/output port control 32. Input/output port control 32 has a first input port terminal coupled to control bus 18 and a second input terminal coupled to request and acknowledge bus 20.
The prior art memory system of FIG. 1 further includes a request arbitration unit 40 which includes a request arbitration circuit 42 coupled to request and acknowledge bus 20.
In operation of the prior art circuit illustrated in FIG. 1, input/output ports 12 generate request signals in input/output port control 32 to either read data from memory 26 of memory board 10 or to write data into memory 26 of memory board 10. These request signals are transmitted over request and acknowledge bus 20 and received by request arbitration circuit 42. Circuit 42 determines which input/output port should be given priority and therefore access to memory board 10. Circuit 42 then sends a corresponding priority acknowledgement signal over request and acknowledge bus 20 to the port 12 to which priority has been granted. This acknowledgement is received over bus 20 by input/output port control 32 of the selected port 12. Input/output port control 32 of the selected port 12 then issues the appropriate data read request or data write request over contool bus 18 for receipt by memory port 10. In addition, control 32 authorizes address generator 30 to transmit the appropriate address signal over address bus 16 for receipt by address buffer 22 of memory board 10. Control 32 in the case of a write data request, further causes the appropriate data to be read from memory 32 onto data bus 14 through the operation of data buffer 36. In the case of a read data request, input/output port control 32 operates to control transfer from data bus 14 through data buffer 36 into memory 34, of data read from memory 26 onto bus 14 by operation of memory board 10.
In turn, memory board 10, upon receipt of a read data request signal by memory control 24 over control bus 18, operates to cause address buffer 22 to deliver the appropriate address data from address bus 16 to memory 26 and operates to read from memory 26 the addressed data through data buffer 28 onto data bus 14. Upon receipt of a write data request signal over control bus 18, memory control 24 operates, as is well known to those skilled in the art, to write data from data bus 14 through data buffer 28 into memory 26 at an address location indicated by the address received over address bus 16 through address buffer 22.
Prior art memory systems such as those illustrated in FIG. 1 may be said to operate in a sequence of memory cycles each of which memory cycle includes a request cycle phase, access cycle phase, and data transfer cycle phase as is illustrated in FIG. 2. As may be seen in FIG. 2, during the request cycle phase of memory cycle 1 a read request signal R1 is received by memory board 10 over control bus 18. In the access phase of subsequent memory cycle 2, read request R1 results in a transfer of data to be read from memory 26 to data buffer 28. In the data transfer cycle phase of subsequent memory cycle 3 read request R1 results in the read data being transferred from data buffer 26 onto data bus 14 for receipt by the requesting input/output port 12. Accordingly, a reading of data from memory board 10 requires a request cycle phase of memory cycle 1, a subsequent access cycle phase of memory cycle 2, and a still subsequent data transfer cycle phase of memory cycle 3.
As is further illustrated in FIG. 2, memory cycle 2, in addition to executing the access cycle phase for read request R1 is also capable of receiving a second data read request R2 in the request cycle phase. Data request R2 results in a data access cycle phase in memory cycle 3 and a data transfer cycle phase in memory cycle 4.
To write data into memory board 10, a data write request W1 is received over control bus 18 during the request cycle phase of memory cycle 4. During the data transfer cycle phase of memory cycle 5, data to be written into memory 26 is received from data bus 14 and stored in data buffer 28. During the access cycle phase of memory cycle 6, as shown in FIG. 2, write request W1 data is transferred from data buffer 28 to memory 26. As is also shown in FIG. 2, during the request cycle phase of memory cycle 5 a second write request W2 may be received which results in a data transfer cycle phase for write request W2 during memory cycle 6 and a subsequent access cycle phase for write request W2 during memory cycle 7.
The prior art system of FIG. 1 thus is capable of executing sequentially received write requests and sequentially received read requests during request cycle phases of consecutive memory cycles. However, the prior art system of FIG. 1 is not capable of receiving contiguous sequentially intermixed read and write requests. The term "contiguous sequential requests" refers to requests which are received in time sequence from one another during a continuous series of request cycle phases; that is to say the requests are received in a series of request cycle phases which are 100% utilized. For example, as shown in FIG. 3, if a write request W1 is received by the prior art system of FIG. 1 in a request cycle phase of a memory cycle 2 which immediately follows a request cycle phase in which a read request R1 was received (thereby creating contiguous sequential intermixed read and write requests), there is a conflict during the data transfer cycle phase of the subsequent memory cycle 3 between read request R1 and write request W1. Specifically, during the data transfer cycle phase of memory cycle 3 an attempt is made to move the read request R1 data from data buffer 28 to data bus 14 and at the same time during the same data transfer cycle phase of memory cycle 3 there is an attempt to move the data to be written in response to write request W1 from data bus 14 to data buffer 28. This simultaneous attempt to access data bus 14 results in an intolerable clash during the data transfer cycle phase of memory cycle 3.
A similar impermissible clash results in the access cycle phase of the third memory cycle following sequential write requests and read requests. This clash is shown with regard to memory cycles 5, 6 and 7 in FIG. 3. Specifically, with write request W2 and subsequent read request R2 in request cycle phases of contiguous sequential memory cycles 5 and 6, during the access cycle phase of memory cycle 7 an attempt is made to move the data to be read in response to read request R2 from memory 26 to data buffer 28 and to simultaneously during the same access cycle phase of memory cycle 7 to move data to be written in response to write request W2 from data buffer 28 to memory 26. As a consequence, there is a simultaneous attempt to access memory 26 which results in an impermissible clash.
To avoid such impermissible clashes as those illustrated above with regard to FIG. 3, prior art systems as illustrated in FIG. 1 employ a request arbitration circuit 42 which assures that at no point will there be contiguous sequential read requests and write requests or contiguous sequential write requests and read requests of the type referred to above with regard to FIG. 3. Instead, whenever a change is to be made from a read request to a write request or from a write request to a read request in the request cycle phases of contiguous sequential memory cycles, one request cycle phase of a memory cycle between the change must be left vacant as is illustrated in FIG. 2. This means that in prior art systems as shown in FIG. 1 there is less than 100% bandwidth utilization of data bus 14, since each vacant request cycle phase of a memory cycle will ultimately result in a corresponding vacant data transfer cycle phase of a subsequent memory cycle and a vacant access cycle phase of a subsequent memory cycle.
These vacant data transfer cycle phases and access cycle phases are illustrated in FIGS. 4 and 5. In FIG. 4 port 1 is illustrated as generating a series of six contiguous sequential read requests R1 through R6 over a control bus. Subsequently, port 2 executes a series of contiguous consecutive write requests W1 through W5. However, request arbitration circuit 42 of FIG. 1 is required to leave the request cycle phase of memory cycle 7 vacant in order to avoid a data transfer cycle phase clash of the type discussed above with regard to FIG. 3. Moreover, port 3 is illustrated in FIG. 4 as subsequently sending a series of read request signals R1 through R4 over a control bus which also must be separated from write requests W1 through W5 by a vacant request cycle phase for memory cycle 13. As a consequence, access cycle phases of memory cycles 8 and 9 are left vacant and data transfer cycle phases of memory cycles 14 and 15 are left vacant as shown in FIG. 4. This results in less than 100% bandwidth for the system of FIG. 1.
In FIG. 5 ports 1, 2 and 3 are shown to have generated alternative read and write requests. As a consequence, the request cycle phase of each even memory cycle 2, 4, 6, 8, 10, 12, 14, 16 and 18 must be maintained vacant in order to avoid the clashes disclosed above with regard to FIG. 3. This results in the access cycle phases of memory cycles 3, 4, 7, 8, 11, 12, 15, 16 and 19 remaining vacant and the transfer cycle phases of memory cycles 5, 6, 9, 10, 13, 14, 17 and 18 remaining vacant. As a consequence, the prior art system of FIG. 1 experiencing a read and write request sequence as shown in FIG. 5 would have only a 50% bandwidth utilization.
USPTO Backgrounds
USPTO Backgrounds