The advantages associated with organizing data processing memory into a hierarchical structure are well recognized in the art. By way of example, a processing system's internal memory may be organized as CPU registers, cache, backing (or bulk, auxiliary or secondary) memory and external memory. Today, external memory is most often implemented as a magnetic storage device, such as a magnetic direct access storage device (DASD). Magnetic disc storage typically comprises random access storage (i.e., direct access storage) in which any location designated by address can be accessed (data searched) within the same access time irrespective of a preceding access address. The drawback to magnetic storage is that higher power rates are necessary to operate the device, which is particularly significant today in view of the trend towards portability in the computer industry.
Nonvolatile semiconductor storage and other technologies such as optical storage require less power and have several orders of magnitude significantly better read access times (e.g., nanoseconds) compared with read access time for magnetic disc storage (e.g., milliseconds). In addition, projections indicate that the cost effectiveness of nonvolatile semiconductor storage will one day overtake that of magnetic storage DASD.
Although nonvolatile semiconductor read access cycle time is on the order of 100 ns, write access cycle times are still at least several orders of magnitude greater. Nominal values of 1 ms -1 sec for a write operation are common. As a specific example, consider a memory hierarchy including a cache, backing storage and a memory in which the write cycle is at least 10.times. (an order of magnitude) longer than the read cycle (e.g. nonvolatile semiconductor memory). In a well mannered system, a cache hit ratio of 99% might be obtained, along with a backing store hit ratio of 95%. Given these numbers and employing a 20 MHz processor, one process cycle in 2,000 can be expected to initiate a replacement page transfer from backing store to nonvolatile semiconductor memory. However, not all page transfers require a write operation into the direct access storage device.
Continuing with the example (and assuming that one-third of the transfer replacement pages need to actually be rewritten in the nonvolatile semiconductor memory), it can be shown that a write operation in the nonvolatile semiconductor memory proceeds at a slower rate than the frequency of page transfer operations (generated by the CPU) moving replacement pages from the backing store to the nonvolatile semiconductor memory. Thus, a significant data blockage can occur in a relatively short period of time, and the superior access time of the nonvolatile semiconductor memory would rarely be realized since almost all access to this memory will encounter a write cycle already in progress.
Therefore, a genuine need exists in the data processing art for a control technique for managing the transfer of data between certain memories of a hierarchical memory structure (including main store and long-write-cycle memory) in order to reduce the possibility of multiple write operations effectively blocking executing read operations between the main store and nonvolatile semiconductor memory. The present invention addresses this need; and, thereby, significantly enhances the capability of a system designer to provide a practical data processing system implementation employing nonvolatile semiconductor storage.
USPTO Backgrounds
USPTO Backgrounds