1. Field of Invention
The invention relates to core memory systems, and more particularly to circuitry and methods for reliably addressing, reading, and writing data into very large, high density ferrite core arrays.
2. Description of the Prior Art
Random access memories composed of high density arrays of ferrite cores have been widely used, both in computer main frame memories and in a wide variety of other applications, especially applications where non-volatile memories are required and where memories are required to operate at very high and/or low temperatures. As the state of the art has progressed, numerous problems have been encountered in reliably manufacturing faster, larger, denser core memory systems. Although improved manufacturing techniques have made it possible to thread the necessary X and Y select conductors and sense/inhibit conductors through tiny toroidal ferrite cores to provide a high density core array containing over half a million bits on a single card having an area of roughly six to eight inches square, it has been extremely difficult and expensive to provide electronic addressing, writing, and sensing circuitry which can reliably address, sense, and write data into such a large, high density core array at the desired high operating speeds.
Accordingly, it is an object of this invention to provide a system and circuitry for addressing, sensing information in, and writing information into individual cores of a high density core array more reliably and less expensively than circuits and systems of the prior art.
Until now, in order to obtain a reliable system including a large, high density core array of as many as a half a million bits along with addressing, writing, and sensing circuitry, it has been necessary to individually, precisely, and laboriously match and balance various individual addressing, sensing, and writing circuit components in order to ensure reliable operation. This has greatly added to the cost of prior art high speed, high density core memory systems.
Accordingly, it is yet another object of the invention to provide method and circuitry for reliably accessing very high density core memory arrays without the necessity to individually trim and balance various circuit components of the addressing, sensing, and writing circuitry.
The main cause of difficulties experienced in reliably accessing extremely high density core memory arrays has been the presence of a large amount of capacitive coupling between the various X, Y, and sense/inhibit lines passing through the various ferrite cores in the array. Although the large, high density core arrays can lead to low cost and high speed performance, the amount of such capacitive coupling also increases as size of core diminishes, allowing the spacings between the various lines to decrease. Further, the amount of capacitive coupling between lines increases as the lengths of the various lines increases. The parasitic coupling between the sense/inhibit lines and the respective X and Y select lines is especially deleterious in extremely high density core arrays. Such parasitic capacitive coupling between the X or Y select lines and the sense/inhibit conductors can cause large voltages to be coupled to the sense/inhibit line during write operations, thereby causing undesired data to be written into "half-selected" cores. This, of course, is completely intolerable.
Accordingly, still another object of the invention is to provide circuitry and method for accessing high density ferrite core arrays in such a manner as to avoid capacitive coupling between the various conductors threaded throughout the core array.
A novelty search directed to the invention described herein uncovered the following patents, which are believed to be generally indicative of the state of the art for core memory systems: U.S. Pat. Nos. 3,693,176; 3,419,856; 3,671,951; 3,568,168; 3,510,853; 3,540,015; 3,524,175; 3,069,662 and 3,127,600.
USPTO Backgrounds
USPTO Backgrounds