1. Field of the Invention
The present invention relates to a semiconductor memory comprising memory cells each having a charge storage layer, and a manufacturing method of the device, particularly to a semiconductor memory further comprising reference cells used as criteria for judging various states of the memory cells, or other memory cells used to read only, and a manufacturing method of the device.
2. Description of the Related Art
Various portable electronics and home electric products are becoming multifunction, thus increased the importance of technique for integrating a nonvolatile semiconductor memory including charge storage layers (floating gates), such as EPROM or EEPROM, in which stored data is kept even after cutting the power supply, into a semiconductor memory represented by one-chip microcomputer. Such a semiconductor memory can be provided with semiconductor elements used with their stored data being hardly renewed (or erased), differently from the main memory cells of the device.
For example, a semiconductor memory is provided with, as necessary semiconductor elements, various reference cells used as criteria for judging various states of the main memory cells, e.g., used for read, for write verification, for erasion verification, and for over-erasion detection. The reference cell for read is used as a criterion in a normal read operation. The reference cell for write verification is used as a criterion after a write operation. The reference cell for erasion verification is used as a criterion after an erasing operation. The reference cell for over-erasion detection is used as a criterion for judging whether over-erasion has occurred due to an erasing operation for an adjacent memory cell. The device can be optionally provided with, e.g., redundancy memory cells for storing data to be displaced from a defective bit to a non-defective bit, or OTP region cells formed in a specific region (OTP region) to be programmable only once and inhibited from being erased after then.
Such semiconductor elements are usually formed into the same structure in the same process as the main memory cells, in view of, e.g., shortening of the manufacturing process, control of temperature characteristics and unevenness in process, and, in case of reference cells, an advantage that their threshold values being set can be minutely adjusted in testing process.
In manufacturing a semiconductor memory including such various semiconductor elements as described above, the semiconductor elements are formed simultaneously with the main memory cells and then their threshold values are set to the respective requested values by write and erasing operations, because they are mainly used to read only. More specifically, in the manufacturing process, the semiconductor elements and the main memory cells are simultaneously subjected to threshold value control (control to regulate into an initial threshold value) in their channel regions, and then the threshold values of the semiconductor elements are adjusted to the respective requested values.
Recently, integration in such a semiconductor memory is getting higher and higher, and it requires more miniaturization of memory cells, reference cells, etc., and more increase in interconnecting layers. It is generally known that the distance and the quantity of the interconnecting layer between a floating gate and a contact hole affect the so-called data retention characteristic in that occurrence of unexpected injection of electrons into the floating gate (charge gain) or unexpected extraction of electrons from the floating gate (charge loss) causes transformation of stored data. It is conjectured that etching plasma damage in forming the contact hole is a prime cause of deteriorating the data retention characteristic. The higher the integration and miniaturization are, the more the damage is apt to occur inevitably. So, the higher the integration and miniaturization in a semiconductor memory are, the more the data retention characteristic deteriorates.
Deterioration of the data retention characteristic is accelerated not only by integration and miniaturization in a semiconductor memory but also by heat and stress due to electric field. Such semiconductor elements as described above, which are mainly used to read only with their stored data being hardly renewed (or erased), e.g., various reference cells, redundancy memory cells, or OTP region cells, are subjected to very frequent read operations because of their modes of use, in comparison with the main memory cells of the device. For this reason, they receive electric field stress due to read operations for a longer time than the main memory cells. Such electric field stress may cause charge gain or loss. This is the same in case of reference cells having their threshold values widely different in accordance with their functions.
It is an object of the present invention to provide a semiconductor memory and a manufacturing method of the device, wherein the data retention characteristic of second cells (e.g., various reference cells, redundancy memory cells, or OTP region cells) formed into the same construction in the same process as first cells (memory cells) is considerably improved without unnecessarily increasing steps of manufacturing process.
According to an aspect of the present invention, a semiconductor memory comprises a first cell which is a memory cell including a charge storage layer, and a second cell including a charge storage layer and used with its set threshold value fixed to a certain value, wherein the second cell has its initial threshold value in manufacturing, different from the initial threshold value of the first cell, and controlled to approach the set threshold value as closely as possible.
The second cell may be one of various reference cells used as criteria for judging the threshold values set in accordance with various states of the first cell.
The second cell may be a memory cell used to read only.
For realizing such a feature of the second cell, the impurity concentration in the channel region of the second cell is preferably different from that of the first cell.
According to another aspect of the present invention, provided is a manufacturing method of a semiconductor memory comprising a first cell which is a memory cell including a charge storage layer, and a second cell including a charge storage layer and used with its set threshold value fixed to a certain value. The method comprises a step of introducing impurities into the channel region of the first cell to set its initial threshold value, and a step of introducing impurities into the channel region of the second cell to set its initial threshold value such that the initial threshold value approach the set threshold value as closely as possible. The step for the second cell is performed separately from the step for the first cell.
In the method, the first and second cells are preferably formed in the same process except the above steps.
Generally in a semiconductor memory comprising memory cells (first cells) as its main storage elements, and cell (second cells) each of which is formed into a nonvolatile memory structure including a charge storage layer like the memory cells, and used with its set threshold value fixed to a certain value, each second cell has the following nature. That is, the closer its set threshold value before being damaged is to its initial threshold value, the better its data retention characteristic is kept even when it is affected by high integration and miniaturization, and damaged by stress due to heat or electric field which is a prime cause of accelerating deterioration of its data retention characteristic. The present invention utilizes this nature. That is, the threshold values requested to be set for the respective second cells are used as standards, and the initial threshold values of the second cells are respectively controlled to approach the threshold values to be set, as closely as possible. More specifically, the impurity concentrations of the second cells are respectively controlled independently of the first cells when impurities for threshold value control are introduced into their channel regions in manufacturing. By thus decreasing the difference between the initial threshold value and the set threshold value, variation of the set threshold value before and after being damaged, becomes little, so the data retention characteristic is kept good.
The present invention, therefore, makes it possible to improve considerably the data retention characteristic of each second cell (such as a reference cell, a redundancy memory cell, or an OTP region cell) formed into substantially the same construction in substantially the same process as the first cells, without unnecessarily increasing steps of manufacturing process.
USPTO Backgrounds
USPTO Backgrounds