Integrated semiconductor memories, for example, DRAM (Dynamic Random Access Memory) semiconductor memories, generally contain a plurality of memory cell arrays or memory banks which contain memory cells arranged in matrix form. FIG. 1 shows, for example, four memory cell arrays or memory banks B1, B2, B3, B4 arranged on a semiconductor memory module M. To improve the yield, integrated semiconductor memories are equipped with redundancy during production. A memory bank equipped in this manner has both regular memory cells and redundant memory cells. For example, the memory bank B3 has a first area of the memory cell array 10a, where regular memory cells are arranged, and a second area 10b, 10c, where redundant memory cells are arranged.
FIG. 2 shows an enlarged detail from the memory bank B3. The first regular memory area 10a and the second redundant memory areas 10b, 10c have memory cells SZ arranged along row lines R1, R2, R3 and column lines S1, S2, S3 in matrix form. The memory cells may be DRAM memory cells, for example. As an example of this, FIG. 2 shows the structure of a DRAM memory cell SZ arranged along the row line R3 and the column line S1. The DRAM memory cell SZ have a selection transistor AT, which can be controlled by a control signal on the row line R3, and a storage capacitor SC, which can be connected to the column line S1 via the selection transistor AT.
If faulty memory cells arise during the production process, a redundancy analysis uses the identified faults and the available sound redundancy to ascertain whether it is possible to repair the semiconductor memory. In this case, a faulty row line in the regular memory cell array 10a, to which line at least one faulty memory cell is connected, is replaced with a redundant row line in the redundant memory area 10b of the memory cell array. It is likewise possible for a column line in the regular memory area 10a of the memory cell array, to which line at least one faulty memory cell is connected, to be replaced with a column line 10c in the redundant area of the memory cell array.
FIG. 3A shows an example of a faulty row line R in the first memory area 10a. The line is able to be addressed using an address x=7 and replaced with a sound redundant row line Rr with the address xr=2. FIG. 3B shows a faulty column line S, which can be activated using the address y=7 and replaced during the redundancy analysis with a sound column line Sr, which can be activated using the address yr=2, in the redundant memory area 10c. 
There are numerous examples for the implementation of an efficient redundancy analysis. For example, an integrated semiconductor memory with regular and redundant word lines where each are divided into individual line segments is known. If a memory cell connected to one of the segments is faulty, then the regular word line segment in question is replaced with a redundant word line segment. By replacing respective individual portions of a regular word line, it is possible to make efficient use of the redundant word lines, whose availability is limited.
An integrated semiconductor memory with a redundancy control unit which can store addresses for faulty memory cells is also known. If the occurrence of a faulty memory cell is detected during the production of the integrated semiconductor memory, the memory cell's address is supplied to the redundancy control unit, where the memory cell's address is compared with already stored addresses for faulty memory cells. If the address of the faulty memory cell does not match any of the addresses already stored, a new faulty memory cell has appeared during production. At the end of the manufacturing process, it is possible to establish whether it is still possible to repair the integrated semiconductor memory due to the number of faults uncovered.
Information about the use of a redundant line is generally indicated by the status of laser fuses or electrical fuses. A circuit for programming electrical fuses including a bit generator that supplies individual control bits to a shift register is known. A line for generating a programming voltage is activated by a program data stream. The fuses are connected to the individual registers in the shift register and to the programming line, and are programmed based on the state of the register connected to the fuses and the data stream on the programming line.
An integrated circuit for decoding address signals that can be used for addressing redundant word lines, in particular, is known. The circuit uses a first decoder to decode a row address and to generate a first address signal for addressing word lines in a first half of a memory bank and a second decoder to decode the row address in combination with data indicating the status of fuses in order to generate a second address signal for addressing word lines in a second half of the memory bank. The first and second address signals simultaneously select first and second word lines in the first and second halves of the memory bank. The row address can be used to select one of the redundant word lines, which replaces a faulty one of the first and second word lines.
A method for compressing a “bit fail map,” which has information relating to a fault analysis, is known. Fault information is indicated in marked areas of the bitmap. The fault classification can be formed using the shape and dimension of the fault areas in the marked areas of the bit map. The use of a compressed bitmap greatly reduces the memory requirement for storing the fault information.
During operation of the integrated semiconductor memory, if a faulty row line or column line in the regular memory area is addressed or detected, the associated redundant row line or column line in the redundant memory area is activated instead of the faulty row and column line. The associated requisite readdressing of a regular row and column line with a redundant row and column line is burnt permanently into a fuse circuit using a “laser fuse process.” After the laser fuse process, the memory chip is operational. The regular cell array has been repaired by replacing faulty row and column lines in the regular area of its memory cell array with sound redundant row and column lines in the redundant area of the memory cell array.
To test the integrated semiconductor memory, a special test mode makes it possible to turn the redundancy addressing on or off. For example, it is possible to establish whether a regular memory cell has been replaced with a redundant memory cell. The special test mode turns on the redundancy addressing at the beginning. Next, a logic 0 is written to the memory with redundancy, for example. Because the redundancy is turned on, this prompts a faulty memory cell in the regular memory area to be replaced with a redundant memory cell in the redundant memory area. Next, a further test mode turns off the redundancy addressing again, so that externally applied addresses are used to address only memory cells in a regular memory area, regardless of whether these cells are sound or faulty. A logic 1 is written to the memory cells in the regular memory cell array. To read the content of the memory cells in the regular and redundant areas, the redundancy addressing is then turned on again. Redundant memory cells in which a logic 0 was stored, while the redundancy addressing was turned on and were then no longer addressed upon transfer to the logic 1, will fail upon being read during the assessment for logic 1. The address applied in this case is thus used to address a cell from the redundancy, not the associated regular memory cell.
Although such a test method makes it possible to establish whether a regular memory cell has been replaced with a redundant memory cell or whether an addressed row line or column line in a regular memory cell array has been replaced with a redundant row line or column line, it is a very complex matter or even impossible to establish which of the redundant row lines in the second memory area is replacing which regular row line in the first memory area or which redundant column line in the second memory area has which regular column line in the first memory area associated with it (redundancy scrambling).
Precise evaluation of the redundancy scrambling is currently possible only by opening the memory chip to decrypt the laser fuse code which has been burnt. However, when the chip is opened, the use of selective etching methods often results in corrosion of the unprotected laser fuses, so that the redundancy scrambling information which is burnt in is lost during the actual preparation.
Particularly, with the use of E-fuses, it is important to ascertain the redundancy scrambling without complex preparation steps or opening the component. In contrast to the evaluation of laser fuses, when analyzing the E-fuses, a further difficulty arises because their state cannot immediately be seen from them. In addition, the E-fuses are generally buried in deeper layers and are protected against corrosion, which means that complex preparation steps are required in order to analyze them.
An integrated semiconductor memory with redundant memory cells and a method, which provides a simplest way of establishing which faulty row and column line in the regular memory cell array has been replaced with which sound row and column line in the redundant area of the memory cell array, are desirable.
USPTO Backgrounds
USPTO Backgrounds