1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, a super junction structure has been proposed which is a power MOSFET achieving a reduced loss (Jpn. Pat. Appln. KOKAI Publication No. 2002-170955).
FIG. 12 is a sectional view showing an example of a conventional super junction MOSFET (SJ-MOSFET) that uses a trench structure. In FIG. 12, reference numeral 61 denotes an n-type drain layer (n-type semiconductor substrate) of a high impurity concentration. Reference numeral 62 is an insulating film buried in a trench. Reference numerals 63, 64, and 65 denote a p-type pillar layer, an n-type pillar layer, and a p-type base layer. Reference numerals 66, 67, and 68 denote an n-type source layer, a gate insulating film, and a gate electrode.
To completely deplete a drift region in SJ-MOSFET, it is necessary to control the dose in the pillar layers to at most about 1×1012 cm−2. The dose in the pillar layers is determined by the product of the net concentration of impurities in the pillar layers and the width of the pillar layers. To reduce the resistance of the pillar layers, it is necessary to reduce the width of the pillar layers (reduce pillar pitch), while increasing the concentration of impurities.
In the conventional trench type super junction structure, a reduction in pillar pitch increases the ratio of the area of trenches to the area of an element region in which the pillar layers are formed. Further, ions are obliquely implanted in sides of the trenches. This precludes the width of the trenches from being reduced. Therefore, in the conventional structure, the resistance cannot be efficiently reduced simply by reducing the pillar pitch.
Thus, in the conventional SJ-MOSFET, it is difficult to reduce the pillar pitch (to reduce the width of the pillar layers). Accordingly, the concentration of impurities in the pillar layers cannot be increased. This makes it difficult to reduce the resistance of the pillar layers (to reduce on resistance). Furthermore, in the conventional SJ-MOSFET, it is difficult to efficiently form pillar layers.
USPTO Backgrounds
USPTO Backgrounds