1. Field of The Invention
The present invention relates to a method of controlling multiprocessing system in which a main memory is shared in common by a plurality of programs concurrently executed on a plurality of processors, and more specifically to such a method for controlling sharing of one or more common resources of the main memory. The present invention also relates to a hardware arrangement for accomplising the above-mentioned method.
2. Description of the Prior Art
A multiprocessing system carries out more than one program at the same time. It has been known in such a system to use a so-called TEST AND SET instruction in order to control sharing of a common resource (viz., a common storage area) of the main memory by more than one program. The operand of the TEST AND SET instruction is a data which indicates whether or not a corresponding shared resource is locked. For the sake of convenience, the operand of the TEST AND SET instruction will be referred to as the TS instruction, while the operand of the TS instruction will be referred to as a GATE. It should be noted that each shared resource has its own GATE. The first bit (the leftmost bit) of the GATE is used as a control bit. If the control bit is a logic "1", a control code is set to a logic "1" which indicates that the shared resource is locked (viz., not available for use because a program executed on one processor is now in use). On the other hand, if the control bit is a logic "0", the control code is set to a logic "0" which indicates that the shared resource is unlocked (viz., available for use).
The TS instruction has been described in a manual published by IBM, entitled "IBM System/370 Principles of Operation" (GA22-7000-7, File No. S370-01).
In order to make clear the advantage of the present invention over the prior art, reference will be made to FIG. 1 which is a flowchart showing how the sharing of the common resource is controlled utilizing the TS instruction according to the prior art.
In FIG. 1, one of the plurality of processors obtains a right to use a common bus (step 10) in order to access the shared resource of the main memory. The processor reads out the GATE (step 12) from the main memory, after calculating or determining the address of the GATE. The processor checks whether the first bit of the GATE is a logic "1" (step 14). If the first bit of the GATE is a logic "1", the program goes to step 16 in which a condition code (abreviated CC in FIG. 1) is set to a logic "1", and if a logic "0", the condition code is set to a logic "0" at step 18. Thereafter, the entire GATE is set to all "1"s (step 20), and the processor abandons the right to use the common bus (step 22). The above-mentioned steps 10 through 22 constitute the TS instruction which is enclosed by a broken line. No access by another processor is permitted to the GATE between the moment of fetching and the moment of storing all "1"s. It should be noted that each processor is provided with a register for storing the condition code.
Subsequently, the processor checks whether the condition code is a logic "0" (step 24). If the condition code is a logic "1", the program recycles to step 10 and repeats the aforesaid steps until the condition code is detected to be a logic "0" at step 24. Contrarily, if the condition code is determined to be a logic "0" at step 24, the program goes to step 26 in which the program executed on the processor in question accesses the shared resource and executes a predetermined operation(s). Thereafter, the GATE is set to all "0"s at step 28 in order to unlock or free the shared resource.
The above discussion shows that if a first program executed on a first processor intends to use the shared resource while a second program executed on a second processor has taken a priority of use of the same, the first program has to repeat the TS instruction until the second program unlocks the resource. As shown in FIG. 1, the TS instruction includes two accesses to the main memory: (a) the readout of the GATE and (b) the writing of all "1"s to the entire GATE. Using the main memory (viz., using the common bus) by the second processor during the TS instruction, prevents other processors from accessing the main memory, and hence the repeating of the TS instructions causes the access of the other processor to the main memory to be delayed. This means that the second processor is delayed in unlocking the shared resource. Consequently, the overall system efficiency is lowered by the repeating of the TS instruction.
In order to solve the above difficulties, two methods may be considered. Viz., if the condition code is determined to be a logic "1", (a) the program sets a timer and thence becomes free from the control of the processor, and thereafter again being executed by the processor upon the expiration of a predetermined time interval and processing the TS instruction or (b) a predetermined number of no-operation instructions are repeated. However, the first method (a) makes a so-called overhead large due to the program switching. Whilst, the second method (b) does not contribute to the increase of the system execution speed in that each no-operation instruction should be read out from the main memory.
USPTO Backgrounds
USPTO Backgrounds