The present invention relates generally to write voltage generating circuits and related write voltage generating methods. More particularly, the invention relates to a write voltage generating circuit and method for use with a non-volatile memory device.
So-termed write operations performed in the context of non-volatile memory devices include program operations, erase operations, etc. A write operation typically starts only after related voltages provided by a write voltage generating circuit have reached their target values, or after a defined period of time has elapsed, where said period of time is deemed sufficient to allow the voltages to reach their target values.
Figure (FIG.) 1 is a timing diagram illustrating changes in certain write voltage levels over time beginning with the start of a constituent write operation (i.e., a typical program operation). Referring to FIG. 1, in response to the start of charge pump operation, each voltage level for; (1) a high write voltage (VPI_CP), (2) a program bit line voltage (VPB_CP), and (3) a program bulk voltage (VBULK_CP) begins its transition towards a defined target value. Once the charge pump reaches operative saturation and each voltage reaches its target value, a write start signal (PGMSTART) activates (e.g., transitions from a low to a high logic level) to begin the write operation. In conventional nonvolatile memory devices, the requisite voltage settling time (TC) associated with the generation of these voltages may actually take about the same time amount of time as the subsequently performed write operation. As such, the voltage settling time (TC) represents a serious impediment to ongoing attempts to reduce the overall time requires perform a write operation, whether a program operation, an erase operation, etc.
In sum, once a write command is received by a conventional non-volatile memory device, an internal voltage boosting circuit begins boosting various voltages implicated in the write operation. Only after the voltage boosting operation(s) are complete can the write operation be performed. Recognizing the numerous write operations may be performed in relation to the nonvolatile memory device, the operation of the internal voltage boosting circuit becomes an important design consideration. For example, once a particular write operation is complete, an associated internal voltage boosting circuit does not necessarily assume a state effectively supporting subsequent (i.e., continuous) write operations, (i.e., such that the time interval between successive ON/OFF operations may be reduced). See, for example, Japanese Publication Patent No. 2002-230985.
USPTO Backgrounds
USPTO Backgrounds