1. Technical Field
The present invention relates to a semiconductor device having a capacitor element.
2. Related Art
Capacitor elements having predetermined values of capacitance are adopted to semiconductor devices which contain analog circuits and digital circuits.
Japanese Laid-open patent publication NO. 2001-85630 describes a technique of forming a load capacitance or capacitor, making use of capacitance between interconnects in the same layer or between through-holes. The publication particularly describes that each of doubly-provided seal rings is used as each electrode of the capacitor.
Japanese Laid-open patent publication NO. 2006-261455 describes a capacitor making use of two comb-like electrodes formed in the same layer. Each electrode is formed over a plurality of interconnect layers and via layers, wherein the lowermost electro-conductive layer of each electrode is composed of a metal interconnect layer located above a transistor.
Japanese Laid-open patent publication NO. 2004-241762 describes a technique of forming a capacitor, using strip-like electrodes arranged in a plurality of interconnect layers. The plurality of strip-like electrodes are formed in the individual interconnect layers, according to a single design rule. Vertically overlapped electrodes are connected with each other through vias.
Japanese Laid-open patent publication NO. 2008-124449 describes a capacitor element formed in the same layer with contact plugs which are connected to transistors.
The patent inventors have recognized as follows. Shrinkage of the semiconductor devices requires shrinkage of areas occupied by the capacitor elements. Shrinkage of the area occupied by the capacitor element may preferably be achieved by allowing the electrodes, which compose the capacitor elements, to extend in the direction of stacking. However, layout of interconnects may be restricted, if the electrodes of the capacitor elements are formed over all of the interconnect layers.
USPTO Backgrounds
USPTO Backgrounds