The present invention relates to a semiconductor integrated circuit device, specifically to a technique effective in use for a semiconductor integrated circuit device provided with a static random access memory.
As one of the parameters for evaluating the memory cells of a static random access memory (hereunder, simply referred to as SRAM), the static noise margin (hereunder, simply referred to as SNM) is generally used. The SNM indicates the stability of data stored in the memory cells. As the value of the SNM becomes increased, the data retaining operation of the memory cells becomes more stabilized; on the contrary however, the writing of inverse data to the retained data stored in the memory cells becomes difficult. The Japanese Unexamined Patent Publication No. 2002-042476 is disclosed as a technique for solving such a problem. The inventors of this application examined the circuit construction of the SRAM on the basis of the above publication. FIG. 17 illustrates the block diagram of the SRAM. The technique of this publication uses a voltage supply circuit as shown in FIG. 18 for reading data, brings a signal WEi into Low level to activate a P-channel MOSFET, and supplies the memory cells with the same level voltage as an external supply voltage Vcc, thus intending to secure a stable driving. In the write operation, the technique brings the signal WEi into High level to deactivate the P-channel MOSFET and activate an N-channel MOSFET instead, and lowers the internal supply voltage supplied to the memory cells to Vcc-Vth. Thereby, this technique lowers the SNM of the memory cells selected by the word lines and enhances the write margin.    Patent Document 1: Japanese Unexamined Patent Publication No. 2002-042476
USPTO Backgrounds
USPTO Backgrounds