SRAM circuits that store digital information are widely used in a variety of mobile and handheld devices, notably smart phones, tablets, laptops, and other consumer electronics products. Solid State memory can include stand-alone memory circuits, with a dedicated substrate, or embedded memory circuits, where the SRAM circuit shares a substrate with other electronic components. Typically, SRAM circuits consists of arrays of SRAM bit cells, and surrounding circuits such as decoders, sense amplifiers, write buffer, timers and control logic. The bit cell consists of a number of transistors. The most common SRAM cell uses six CMOS transistors connected as a latch with two pass gates. While fast and reliable, SRAM memory circuits requires substantially continuous power for operation, making efficient electrical power usage a key concern.
In recent years, due to the growth of portable electronics, there has been a push to decrease the power of the circuits used in portable electronic appliances. With a lower power, typically smaller batteries can be used. The power consumption of a circuit may be reduced by using a lower supply voltage, or by reducing the amount of internal capacitance being charged and discharged during the operation of the circuit. A memory that uses less power will be not drain a battery supply as much, and therefore a system with such memory would not need as frequent battery recharging.
In some systems, power consumption of a circuit may be reduced by using a lower supply voltage. A standard technique used in SRAM is to lower the supply voltage on the SRAM cells during a retention mode. A retention mode is a mode where the SRAM is not accessed, neither read nor written, but data is kept in the SRAM cells. There is a practical limit to how low the supply can be brought during this retention mode. If the supply is brought too low, the characteristics of the transistors in a cell may force the cell to flip state, resulting in a loss of data. In many instances most cells could function, i.e. keep their data, at this lower supply, but a few cells may fail to keep their data. However, once a regular supply is re-established, out of retention mode, these few cells would show an erroneous state.
As will be appreciated, systems and methods that could reduce or correct erroneous states would improve SRAM cell accuracy, efficacy, and could allow for reduction in overall power usage.
USPTO Backgrounds
USPTO Backgrounds