The present invention relates to a semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device including a DRAM (Dynamic Random Access Memory).
DRAMs of recent years adopt the stack structure having an information storage capacitor arranged above a memory-cell-selecting MISFET to compensate for a decrease of stored charge (Cs) of the information storage capacitor due to the miniaturization of the memory cell.
Of all memory cells of the stack type, a memory cell of the Capacitor Over Bitline (COB) type having an information storage capacitor arranged over the bit line for input/output of information stored in the memory cell has the features: (a) the underlying level difference of the storage node of the information storage capacitor is reduced by the bit line and therefore the difficulty in the process of forming the information storage capacitors is lessened; and (b) the bit line is shielded by the information storage capacitor, making it possible to achieve a high signal to noise (S/N) ratio.
In the DRAM memory cell, two memory-cell-selecting MISFETs which share the same bit line is formed in each active region surrounded by a field insulating film. Furthermore, the bit line is connected through the first contact hole to a semiconductor region located in the center of the active region (first semiconductor region) and the storage nodes of the information storage capacitors are connected through the second contact holes to semiconductor regions located at the two end portions of the active region (second semiconductor regions).
Meanwhile, in a memory cell of the above-mentioned COB structure, after the bit line connected to the first semiconductor region, the storage node of the information storage capacitor is connected to the second semiconductor region. Therefore, if the bit line is extending right above the second semiconductor region which is to be connected to the storage node, it is impossible to connect the storage node to the second semiconductor region.
To take an example, in U.S. Pat. No. 4,970,564 issued on Nov. 13, 1990, the adopted memory cell layout is such that the active region and the bit line are so arranged as to obliquely intersect each other to avoid the presence of the bit line right above the second semiconductor region.
Only the arrangement of the active region and the bit line obliquely intersecting each other is not enough because the areas of the both end portions of the active region are decreased by the bird's beak that grows at the LOCOS structure adopted for isolation purposes. Therefore, as shown in JP-A-5-291532 laid open on Nov. 5, 1993 and the like, memory cells of the COB structure having active regions called the sea gull wings from their external appearance.
The active region of this sea gull wing structure has a shape of symmetrical sea gull wings and a plurality of the active regions of this type are arranged on a semiconductor substrate.
In the memory cells of the sea gull wing structure, the first contact hole is formed on the first semiconductor region located in the center portion of the active region which corresponds to the body of a sea gull, and at this first contact hole, the bit line and the first semiconductor region are connected together. The channel regions of the memory-cell-selecting MISFETs are located in those portions of the active region which correspond to the inner wing portions of a sea gull, and the second contact holes are formed on the second semiconductor regions which correspond to the outer wing portions of a sea gull, and at each second contact hole, the storage node of the information storage capacitor and the second semiconductor region are connected together.
A plurality of word lines are arranged substantially in parallel, and each word line being wide at portions thereof corresponding to the channel regions to secure a sufficient channel length for the memory-cell-selecting MISFETs. On the other hand, a plurality of bit lines are provided at right angles with the word lines, and each bit line has projections to completely cover the area of each first contact hole above the first semiconductor region. Furthermore, since the fabrication of the word lines and the bit lines requires the highest degree of miniaturization, a phase shift mask is sometimes used in photolithography of those lines. In this case, it is required to keep the adjacent lines apart for a constant distance, for which reason, those portions of the lines corresponding to the wide or projecting portions of the adjacent lines need to be shaped as indentations, with the result that the word lines and the bit lines are generally not straight but complicated and irregular in their profiles.
However, if the word lines and the bit lines have complicated, irregular shapes due to the use of a phase shifting mask, for example, a problem arises when the circuit is scaled down to realize progressive integration and miniaturization in recent years. This problem is described in U.S. patent application No. 08/703,067 filed on Aug. 26, 1996, assigned to the assignee of the invention in this patent application (corresponding to Korean Paten Application No. 35498/96 filed on Aug. 26, 1996 or Taiwanese Patent Application No. 84109007 filed on Aug. 29, 1995).
Specifically, the problem is that the word lines and the bit lines are patterned in such a way that large portions are made much wider and small portions are made much smaller.
FIG. 1a is a plan view showing a typical layout of the word lines, FIG. 1b is a plan view showing the formed shape of the word lines, and FIG. 1c is a plan view showing the shape of the word lines including a defect.
In the stage of layout design, the word line mask pattern 101 in FIG. 1a includes wide and narrow portions. This is because expanded portions 102 are provided in the word line mask pattern 101 to secure a sufficient channel length for the active regions and also because recessed portions 103 are provided for the neighboring expanded portions 102 to make uniform the distance between the adjacent portions, which is required when the phase shifting mask is used.
FIG. 1b shows the word lines 104 patterned using the layout pattern shown in FIG. 1a. The word lines 104 are formed by patterning a polysilicon film or a layered film, including a polysilicon film and a silicide film, as the material for the word lines. By comparison between FIG. 1a and FIG. 1b, it can be confirmed that the dilated portions 105 of the word lines 104 corresponding to the expanded portions 102 are wider than specified in layout design, and that the constricted segments 106 of the word lines 104 corresponding to the recessed portions 103 are narrower than specified in the layout design. In other words, the wide portions are patterned much wider and the narrow portions are patterned much narrower than the designed ones.
Under the circumstances, if there is a slight pattern dislocation or a little variation in the process conditions, the above-mentioned phenomena tend to occur readily, with a result that a disconnection 107 will occur in the word line 104 as shown in FIG. 1c.
Such disconnections as in the words line also occur in the bit lines. FIG. 2a is a plan view showing a typical layout pattern of bit lines, FIG. 2b is a plan view showing the bit lines patterned using the layout pattern shown in FIG. 2a, and FIG. 2c is a plan view showing the bit lines including a defect. Just as in the word lines, a disconnection 109 occurred in the bit line 108.
USPTO Backgrounds
USPTO Backgrounds