The present disclosure relates to a semiconductor structure, and particularly to semiconductor fins electrically isolated from an underlying semiconductor layer by a well trapping fin portion and a method of manufacturing the same.
Semiconductor devices formed on a semiconductor fin on a bulk semiconductor substrate typically suffer from leakage currents between the semiconductor fin and an underlying semiconductor material of the bulk semiconductor substrate. For example, the source region and the drain region of a fin field effect transistor can have leakage paths to the underlying semiconductor material.
While use of a semiconductor-on-insulator (SOI) substrate can provide electrical isolation of semiconductor fins from the substrate, SOI substrates are not generally compatible with use of stress-generating embedded semiconductor materials that can enhance the strain in the channel of a field effect transistor. Inserting a dielectric material underneath a semiconductor fin requires additional processing steps and increases the total processing time.
USPTO Backgrounds
USPTO Backgrounds