1. Field of the invention
The present invention relates, in general, to the formation of capacitor in manufacturing a semiconductor device and, more particularly, to a method for the fabrication of DRAM cell, capable of increasing the capacitance.
2. Description of the Prior Art
It is indispensable to reduce the area of memory cell and to thus secure the charge storage capacitance in the cell for the high integration of dynamic random access memory (hereinafter referred to as "DRAM") device. In addition, a semiconductor device for very large scale integrated circuit, especially if the charge storage capacitance of capacitor is reduced, is likely to show frequent soft errors due to alpha particles.
Accordingly, intensive studies has been carried out on the development, an earnest subject in the art, for process for securing not only the charge storage capacitance but also device reliability.
In order to better understand the background of the present invention, there will be given description for a conventional DRAM cell with reference to FIG. 1.
On a silicon substrate 1, as shown in FIG. 1, a field oxide is initially formed, to define an active region, followed by the formation of a gate oxide 3 and a gate electrode 4. The gate electrode 4 is then insulated by an oxide layer 4' with a spacer oxide 5 being formed at a sidewall of the gate electrode and oxide layer. Thereafter, dopants are implanted into the silicon substrate, to form a transistor.
Subsequently, a nitride 8 is deposited entirely over the transistor and etched selectively to expose a source region, which is then connected with a first charge storage electrode 9. Over the resulting structure is entirely coated an oxide, so as to planarize its surface.
Next, the first charge storage electrode 9 is exposed and connected with a second charge storage electrode 11 which has a cross section of a vertical rod.
Finally, a dielectric film 13 and a plate electrode are formed in due order as shown in the figure, to complete the DRAM cell which may secure relatively much charge storage capacitance.
However, as semiconductor device is highly integrated, the height of the charge storage electrode vertically formed is restricted, so that the conventional method faces a difficulty, that is, further establishment of charge storage capacitance is difficult to obtain.
USPTO Backgrounds
USPTO Backgrounds