The present invention relates to a random access memory which performs a data write/read operation and, more particularly, to realization of a high-speed operation with low current consumption of a large-capacity random access memory.
In order to realize a high-speed operation with low current consumption, some large-capacity random access memories (RAMs) have a memory cell array which is divided into a plurality of memory blocks. In such a RAM, a selected memory block among a plurality of memory blocks is activated during access. Some RAMs of this type have a memory array which is divided into a plurality of memory blocks along only a bit line direction. However, when such a RAM has a multi-bit arrangement wherein access is performed in units of a plurality of bits, wires must be provided between memory blocks to correspond in number to that of the data input/output bits. As a result, the area of the wiring portion is widened, and the chip size is increased. Therefore, a RAM having a memory cell array which is divided into memory blocks only along a bit line direction is not suitable for a RAM with a multi-bit arrangement.
Some RAMs have a memory cell array which is two-dimensionally divided into a plurality of memory blocks.
In a RAM of this type, for example, a first data line is provided for every n memory blocks, and a second data line is provided for every 2 sets of the n memory blocks. During a data read operation, one memory cell is selected in each of the n memory blocks, and one cell data of each selected memory cell is selectively read out to each first data line. Either of the data read out by 2 first data lines is transferred to the second data line. Then, the second data lines are selected for the number of required bits, and data of the selected second data lines are supplied to a data I/O circuit. Note that during a data write operation, the basic concept is the same as described above except that data flows in the reverse order.
In a RAM having the above arrangement, wires need not be provided between memory blocks to correspond in number to that of the input/output data bits. For this reason, when the number of input/output bits is increased by the multi-bit arrangement, and the chip size need not be increased.
However, all the second data lines are activated at once during access. That is, cell data are read out to all the second data lines during the data read operation. During the data write operation, cell data are read out once to all the second data lines, and write data is supplied only to the selected second data line.
In order to realize high-speed data transfer during memory access, capacitance which is driven during data transfer must be minimized. In order to minimize the capacitance, the number of memory blocks is increased to increase the number of the second data lines. However, each second line is provided between the memory block and the data I/O circuit and hence has a large wiring length, thereby having a relatively large capacitance. For this reason, as the number of second data lines is increased, current consumption is increased.
In addition, the number of second data lines must be decreased to decrease the current consumption. In this case, the number of memory blocks is decreased, and the number of sense amplifiers connected to the second data lines is increased along therewith. Therefore, a load capacitance of each second data line is increased, resulting in a low data transfer speed.
As described above, a conventional RAM having a memory cell array which is divided into a plurality of memory blocks cannot satisfy the problems of current consumption and a data transfer speed at the same time.
USPTO Backgrounds
USPTO Backgrounds