The trend in the computer industry is toward designing systems with higher processing speeds and smaller packaged subsystems to increase performance and throughput in support of increasingly demanding applications. Information access from off-chip caches and memories to the processing unit dictates overall performance of these computing systems. A processing unit made up of an integrated circuit typically connects to an external cache or memory IO through wiring (i.e. a bus) on a printed circuit board. External bus speeds do not scale with improvements in speed within the integrated circuit or processing unit due to the limiting effects of board level parasitics, which include connecting wires and discontinuities in the signal path such as those associated with vias and stubs.
Component package parasitics on power and ground paths limit power delivery to on-die circuitry to support high speed switching transients. Bus performance is generally improved in terms of timing and noise margin by optimizing the interconnect topology between the connecting devices, by reducing wiring lengths, matching wire lengths, minimizing discontinuities, providing proper termination and adequate decoupling.
Circuit boards such as motherboards designed for high performance systems need to support a variety of fine pitch components with high IO density using a combination of signal redistribution, signal routing, and power and ground layer configurations thus driving overall layer count and board thickness higher. Connectivity or transition between various metal layers is accomplished using vias with conductive walls through openings in dielectric layers. These vias present themselves as electrical discontinuities to the controlled impedance interconnect path from the controller to the memory devices. Compared to standard memory dual in line memory modules (DIMM) modules which host only memory devices, layer to layer via transitions for signal routing in motherboards has become more electrically significant because of relatively large board thickness.
Accordingly, this invention arose out of concerns associated with providing improved memory systems and related methods.
USPTO Backgrounds
USPTO Backgrounds