As memory devices of all types have evolved, continuous improvements have been made to enhance performance in a variety of respects. Increases in memory bandwidth, capacity, and reliability have been implemented in an attempt to satisfy evolving demands, such as in applications requiring high quality video playback. To achieve better performance, manufacturers have utilized several approaches. For example, in some instances, the bit width of a data bus of a memory system may be increased to provide additional bandwidth to external devices. This is not a solution for all manufacturers, however, as many devices cannot feasibly be retooled to interface with a larger data bus bit-width.
Other issues often arise in design considerations as well. One such issue is the performance limitation of memory associated with memory access response times. Typically, accessing data in memory may require that an address of memory first be sensed, and data corresponding to that address provided to a data bus. Thus, if a memory receives too many read commands within a particular time period, each command cannot be fully executed before the next command is received, and an output of incorrect or corrupt data may result. A sense operation in particular may incur substantial delays, limiting the frequency at which read commands may be executed, and as a result, also the rate at which data can be provided. Because the amount of time required to complete memory accesses is based at least in part by physical characteristics of the memory itself, increasing response times to improve output may not always be possible.
In some cases, designs can be implemented to increase performance, but at a cost of functionality. For example, some memories may be configured to execute page reads at a higher rate than other memories, but may be limited in their ability to efficiently respond to more random requests of read data. In other instances, memory designs may allow for more efficient operation, but may also limit the number of memories that can simultaneously operate in a memory system.
Therefore, a need exists for a system and method to provide improved data output without increasing data bus bit-width, limiting functionality, or increasing the frequency of read commands provided to a memory.
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