1. Field of the Invention
This invention generally relates to frequency/phase locked loops and, more particularly to a system and method for determining when a device receiving non-synchronous communication signals should switch from frequency acquisition to phase acquisition.
2. Description of the Related Art
Voltage controlled oscillators are commonly used in monolithic clock data recovery (CDR) units, as they're easy to fabricate and provide reliable results. Clock recovery PLLs generally don't use phase-frequency detectors (PFDs) in the data path since the incoming data signal isn't deterministic. PFDs are more typically used in frequency synthesizers with periodic (deterministic) signals. Clock recovery PLLs use exclusive-OR (XOR) based phase detectors to maintain quadrature phase alignment between the incoming data pattern and the re-timed pattern. XOR based phase detectors have limited frequency discrimination capability, generally restricting frequency offsets to less than the closed loop PLL bandwidth. This characteristic, coupled with the wide tuning range of the voltage controlled oscillator (VCO), requires CDR circuits to depend upon an auxiliary frequency acquisition system.
FIG. 1 depicts a PLL loop consisting of a phase frequency detector, a voltage controlled oscillator, a charge pump, and a low-pass filter placed into the forward path of a negative feedback closed loop configuration (prior art). A charge pump is used if the PFD is insufficient to charge (or discharge) reactances in the loops filter.
There are two basic PLL frequency acquisition techniques. The first is a VCO sweep method. During an out-of-lock condition, auxiliary circuits cause the VCO frequency to slowly sweep across its tuning range in search of an input signal. The sweeping action is halted when a zero-beat note is detected, causing the PLL to lock to the input signal. The VCO sweep method is generally used in microwave frequency synthesis applications. The second type of acquisition aid, commonly found in clock recovery circuits, uses a PFD in combination with an XOR phase detector. When the PLL is locked to a data stream (the REFCLK input), the PLL switches over to a PFD that is driven by a stable reference clock source. The reference clock frequency is proportional to the data stream rate. For example, if the data stream rate is D and the reference clock rate is R, then D α R.
In this manner, the VCO frequency is held very close to the data rate. Keeping the VCO frequency in the proper range of operation facilitates acquisition of the serial data and maintains a stable downstream clock, even if the serial data CDR input is lost. When serial data is again applied to the CDR, the XOR-based phase detector replaces the PFD when frequency is reacquired, and data re-timing resumes using the reference clock.
One difficulty in switching between frequency and phase detectors is in determining the switch point, the point at which the serial data signaling frequency has been acquired. Since the serial data is received as a non-synchronous pattern of random or pseudo-random binary bits, it is not always easy to “find” the carrier or signaling frequency. Further, a determination must be made as to when the VCO frequency is accurate enough to begin operation based upon the phase detection of the reference clock.
It would be advantageous if a method existed that permitted a CDR synthesized signal to switch from frequency acquisition of a non-synchronous communication signal to phase acquisition of a reference clock.
USPTO Backgrounds
USPTO Backgrounds