Interrupts are a commonly used mechanism that peripheral devices use to request the service of a central processing unit (CPU). For example, a parallel port connected to a printer can generate an interrupt to the CPU requesting that the CPU transmit additional characters to the printer. In this way, the CPU is able to perform other tasks until the printer requires service.
FIG. 1A illustrates an exemplary interrupt-driven computer system 100. There is shown a host CPU 102 and a bus bridge 104 connected to a host bus 106. The bus bridge 104 contains an interrupt routing mechanism 108 and an interrupt controller 110. The bus bridge 104 is connected to a Peripheral Component Interface (PCI) bus 112 and an Industry Standard Architecture (ISA) bus 114. One or more peripheral devices 116A-116N are connected to the PCI bus 112 (herein referred to as PCI devices) and one or more peripheral devices 118A-118M are connected to the ISA bus 114 (herein referred to as ISA devices).
The interrupt routing mechanism 108 receives the interrupts from the PCI devices 116 and routes them to an appropriate interrupt request (IRQ) signal. The interrupts from the ISA devices 118 are IRQ signals which are transmitted directly to the interrupt controller 110. The IRQ signals are received by the interrupt controller 110 which generates an appropriate interrupt to the host CPU 102.
Each PCI device 116 can be an add-in board or a component embedded on the board containing the PCI bus 112. Four interrupt pins are associated with each PCI device 116 and are herein referred to as pin A, pin B, pin C, and pin D. Pin A is typically associated with the INTA# interrupt signal, pin B is associated with the INTB# interrupt signal, pin C is associated with the INTC# interrupt signal and pin D is associated with the INTD# interrupt signal. Single-function PCI devices utilize pin A and multi-function PCI devices can utilize more than one interrupt pin. The interrupt pins associated with each PCI device 116 can be connected to the system board traces in a variety of ways. An example of one such way is shown in FIG. 1B.
There is shown three PCI devices, 116A, 116B, 116C, where the interrupt traces or signals are shared between the three PCI devices, 116A-116C. An interrupt signal is shared between the PCI devices 116 in order to compensate for the limitation of four interrupts. Interrupt trace or signal INTA# is tied to interrupt pin B of PCI device.sub.1 116A, interrupt pin C of PCI device.sub.2 116B, and interrupt pin A of PCI device.sub.3 116C. Interrupt signal INTB# is tied to interrupt pin C of PCI device.sub.1 116A, interrupt pin A of PCI device.sub.2 116B, and interrupt pin B of PCI device.sub.3 116C. Likewise, interrupt signal INTC# is tied to interrupt pin A of PCI device.sub.1 116A, interrupt pin B of PCI device.sub.2 116B, and interrupt pin C of PCI device.sub.3 116C. All of the D pins are tied to the INTD# signal.
Each of the interrupt signals, INTA#-INTD#, is hardwired to a separate input of the interrupt routing mechanism 108. The interrupt routing mechanism 108 is used to assign each interrupt signal, INTA#-INTD#, to a specific interrupt request signal, IRQ.sub.1 -IRQ.sub.L. The interrupt controller 110 receives the interrupt request signals, IRQ.sub.1 -IRQ.sub.L, and in response asserts a corresponding interrupt request to the host CPU 102.
A recent trend in the computing industry has been to use intelligent peripheral devices to control portions of the I/O activity ongoing in a computer system. In this way, the CPU is relieved of controlling these tasks and can be utilized to perform other tasks. An example of such an intelligent device is a redundant array of inexpensive disks (RAID) controller which is shown in FIG. 2.
There is shown an exemplary computer system 130 utilizing a RAID controller 132 to control the transfer of data to and from external storage devices 134A-134B. The RAID controller 132 is connected to a PCI bus 112. Additional PCI devices 116A-116N can be connected to the PCI bus 112 as well. In addition, a bus bridge 104 connects the PCI bus 206 to a host bus 212, to which is coupled to a host CPU 102. The bus bridge 104 includes an interrupt routing mechanism 108 that receives interrupts from each of the PCI devices and the RAID controller 132 and which generates a corresponding IRQ signal that is transmitted to an interrupt controller 110. The interrupt controller 110, in turn, generates a corresponding interrupt to the host CPU 102.
The RAID controller 132 includes a processor module 138 that is in communication with the PCI bus 112 and an internal bus 136. One or more small computer system interface (SCSI) controllers 140A-140N or the like can be connected to the internal bus 136. The processor module 138 can include a processor, an interrupt router, and an interrupt controller (all not shown) that receive and service the interrupts generated from the devices connected to the internal bus 136.
A drawback with this computer system 130 is that the host CPU 102 receives the interrupts from each of the peripheral devices 132, 116 connected to the PCI bus 112. This unnecessarily burdens the host CPU 102 thereby degrading the overall performance of the computer system 130. In order to improve the performance of the computer system 130, it would be beneficial for the RAID controller 132, or other intelligent peripheral device, to control the interrupts generated from the other PCI devices 116 rather than the host CPU 102. In this way, the CPU 102 is not burdened with servicing these interrupts and is able to proceed with processing other tasks.
USPTO Backgrounds
USPTO Backgrounds