This invention relates generally to high voltage breakdown semiconductor devices and fabrication techniques therefor, and more particularly to a structure in which the lower junction termination of a multilayer semiconductor device formed in a wafer is extended to the top surface of the wafer, and a method of fabricating such structure.
There are many circuit applications for semiconductor devices which provide symmetrical blocking of applied voltages of different polarities and which exhibit high reverse breakdown voltages. In fabricating such device, it is necessary to control the geometries and characteristics of the device junctions. This can be accomplished by fabricating the device with a lateral, rather than vertical, structure. By bringing the lower junction termination of the device to the top surface of the wafer, better control of the symmetry and breakdown characteristics of the device can be achieved; however, this requires that the substrate of the device be electrically connected to the top surface of the wafer. While there are known ways to connect the substrate of a semiconductor device to its top surface, they generally have disadvantages which complicate the manufacture of semiconductor devices, such as the necessity of performing processing steps on each individual die. This is difficult and hence disadvantageous from a manufacturing standpoint.
It is desirable to provide a semiconductor device of relatively simple construction, having symmetrical blocking and high voltage breakdown characteristics, with its substrate being electrically connected to active layers on its upper surface, and a method of fabricating such a device which is suitable for large scale production. It is to this end that the present invention is directed.
USPTO Backgrounds
USPTO Backgrounds