In the semiconductor industry, microlithography (or simply lithography) is the process of printing circuit patterns on a semiconductor wafer (for example, a silicon or GaAs wafer). Currently, optical lithography is the predominant technology used in volume manufacturing of semiconductor devices and other devices such as flat-panel displays. Such lithography employs light in the visible to the deep ultraviolet spectral range to expose photosensitive resist on a substrate. In the future, extreme ultraviolet (EUV) and soft x-rays may be employed. Following exposure, the resist is developed to yield a relief image.
In optical lithography, a photomask (often called a mask or a reticle) that serves as a template for the device structures to be manufactured is first written using electron-beam or laser-beam direct-write tools. A typical photomask for optical lithography consists of a glass (or quartz) plate of six to eight inches on a side, with one surface coated with a thin metal layer (for example, chrome) of a thickness of about 100 nm. The device pattern is etched into the metal layer, hence allowing light to transmit through the clear areas. The areas where the metal layer is not etched away block light transmission. In this way, a pattern may be projected onto a semiconductor wafer.
The mask contains certain patterns and features that are used to create desired circuit patterns on a wafer. The tool used in projecting the mask image onto the wafer is called a “stepper” or “scanner” (hereinafter collectively called “exposure tool”). FIG. 1 is a diagram of an optical projection lithographic system 10 of a conventional exposure tool. System 10 includes an illumination source 12, an illumination pupil filter 14, a lens subsystem 16a-c, a mask 18, a projection pupil filter 20, and a wafer 22 on which the aerial image of mask 18 is projected. Illumination source 12 may be a laser source operating, for example, at UV (ultra-violet) or DUV (deep ultra-violet) wavelengths. The light beam of illumination source 12 is expanded and scrambled before it is incident on illumination pupil 14. Illumination pupil 14 may be a simple round aperture, or may have specifically designed shapes for off-axis illumination. Off-axis illumination may include, for example, annular illumination (i.e., illumination pupil 14 is a ring with a designed inner and outer radii), quadruple illumination (i.e., illumination pupil 14 has four openings in the four quadrants of the pupil plane), and others such as dipole illumination.
After illumination pupil 14, the light passes through the illumination optics (for example, lens subsystem 16a) and is incident on mask 18, which contains the circuit pattern to be imaged on wafer 22 by the projection optics. As the desired pattern size on wafer 22 becomes smaller and smaller, and the features of the pattern become closer and closer to each other, the lithography process becomes more challenging. The projection optics (for example, lens subsystems 16b and 16c, and projection pupil filter 20) images mask 18 onto wafer 22. Pupil 20 of the projection optics limits the maximum spatial frequency of the mask pattern that can be passed through the projection optics system. A number called “numerical aperture” or NA often characterizes pupil 20.
When the resist is exposed by the projected image and thereafter baked and developed, the resist tends to undergo complex chemical and physical changes. The final resist patterns are typically characterized by their critical dimensions, or CD, usually defined as the width of a resist feature at the resist-substrate interface. While the CD is usually intended to represent the smallest feature being patterned in the given device, in practice the term CD is used to describe the linewidth of any resist feature.
In most exposure tools, the optical system reduces the size of the pattern from the mask level to the wafer level by a reduction factor, typically 4× or 5×. Because of this the pattern at the mask level is typically larger than the desired pattern at the wafer level, which relaxes the dimensional control tolerances required at the mask level and improves the yield and manufacturability of the mask-making process. This reduction factor of the exposure tool introduces a certain confusion in referring to “the dimension” of the exposure process. Herein, features sizes and dimensions refer to wafer-level feature sizes and dimensions, and the “minimum feature size” refers to a minimum feature at the wafer level.
For an exposure process to pattern a device correctly, the CDs of all critical structures in the device must be patterned to achieve the design target dimensions. Since it is practically impossible to achieve every target CD with no errors, the device is designed with a certain tolerance for CD errors. In this case, the pattern is considered to be acceptable if the CDs of all critical features are within these predefined tolerances. For the exposure process to be viable in a manufacturing environment, the full CD distribution must fall within the tolerance limits across a range of process conditions that represents the typical range of process variations expected to occur in the fab.
Factors that limit or degrade the fidelity of the pattern transfer process include imperfections in the mask-making process, in the projection optics, in the resist process, and in the control of the interaction between the projected light and the film stacks formed on the wafer. However, even with a perfect mask, perfect optics, a perfect resist system, and perfect substrate reflectivity control, image fidelity becomes difficult to maintain as the dimensions of the features being imaged become smaller than the wavelength of light used in the exposure tool. For exposure processes using 193 nm illumination sources, features as small as 65 nm are desired. In this deep sub-wavelength regime, the pattern transfer process becomes highly non-linear, and the dimensions of the final pattern at the wafer level become a very sensitive function not only of the size of the pattern at the mask level, but also of the local environment of the feature, where the local environment extends out to a radius of roughly five to ten times the wavelength of light. Given the very small feature sizes compared to the wavelength, even identical structures on the mask will have different wafer-level dimensions depending on the sizes and proximities of neighboring features, and even features that are not immediately adjacent but still within the proximity region defined by the optics of the exposure tool. These optical proximity effects are well known in the literature.
In an effort to improve imaging quality and minimize high non-linearity in the pattern transfer process, current processing techniques employ various resolution enhancement technologies (“RET”). One of the leading types of RETs in use today is optical proximity correction (OPC), a general term for any technology aimed at overcoming proximity effects. One of the simplest forms of OPC is selective bias. Given a CD vs. pitch curve, all of the different pitches could be forced to produce the same CD, at least at best focus and exposure, by changing the CD at the mask level. Thus, if a feature prints too small at the wafer level, the mask level feature would be biased to be slightly larger than nominal, and vice versa. Since the pattern transfer process from mask level to wafer level is non-linear, the amount of bias is not simply the measured CD error at best focus and exposure times the reduction ratio, but with modeling and experimentation an appropriate bias can be determined. Selective bias is an incomplete solution to the problem of proximity effects, particularly if it is only applied at the nominal process condition. Even though such bias could, in principle, be applied to give uniform CD vs. pitch curves at best focus and exposure, once the exposure process varies from the nominal condition, each biased pitch curve will respond differently, resulting in different process windows for the different features. Therefore, the “best” bias to give identical CD vs. pitch may even have a negative impact on the overall process window, reducing rather than enlarging the focus and exposure range within which all of the target features print on the wafer within the desired process tolerance.
Other more complex OPC techniques have been developed for application beyond the one-dimensional bias example above. A two-dimensional proximity effect is line end shortening. Line ends have a tendency to “pull back” from their desired end point location as a function of exposure and focus. In many cases, the degree of end shortening of a long line end can be several times larger than the corresponding line narrowing. This type of line end pull back can result in catastrophic failure of the devices being manufactured if the line end fails to completely cross over the underlying layer it was intended to cover, such as a polysilicon gate layer over a source-drain region. Since this type of pattern is highly sensitive to focus and exposure, simply biasing the line end to be longer than the design length is inadequate because the line at best focus and exposure, or in an underexposed condition, would be excessively long, resulting either in short circuits as the extended line end touches neighboring structures, or unnecessarily large circuit sizes if more space is added between individual features in the circuit. Since one of the key goals of integrated circuit design and manufacturing is to maximize the number of functional elements while minimizing the area required per chip, adding excess spacing is a highly undesirable solution.
Two-dimensional OPC approaches have been developed to help solve the line end pull back problem. Extra structures (or assist features) known as “hammerheads” or “serifs” are routinely added to line ends to effectively anchor them in place and provide reduced pull back over the entire process window. Even at best focus and exposure these extra structures are not clearly resolved and they alter the appearance of the main feature without being fully resolved on their own. Assist features can take on much more aggressive forms than simple hammerheads added to line ends, to the extent the pattern on the mask is no longer simply the desired wafer pattern upsized by the reduction ratio. Assist features such as serifs can be applied to many more cases than simply reducing line end pull back. Inner or outer serifs can be applied to any edge, especially two dimensional edges, to reduce corner rounding or edge extrusions. With enough selective biasing and assist features of all sizes and polarities, the features on the mask bear less and less of a resemblance to the final pattern desired at the wafer level. In general, the mask pattern becomes a pre-distorted version of the wafer-level pattern, where the distortion is intended to counteract or reverse the pattern deformation that will occur during the lithographic process to produce a pattern on the wafer that is as close to the one intended by the designer as possible.
In another OPC technique, instead of appending assist structures such as serifs to a feature, completely independent and non-resolvable assist features are added to the mask. These independent assist features are not intended or desired to print as features on the wafer, but rather are intended to modify the aerial image of a nearby main feature to enhance the printability and process tolerance of that main feature. Often referred to as “scattering bars,” this type of sub-resolution assist feature (SRAF) adds yet another layer of complexity to a mask. A simple example of a use of scattering bars is where a regular array of non-resolvable scattering bars is drawn on both sides of an isolated line feature, which has the effect of making the isolated line appear, from an aerial image standpoint, to be more representative of a single line within an array of dense lines, resulting in a process window much closer in focus and exposure tolerance to that of a dense pattern. The common process window between such a decorated isolated feature and a dense pattern will have a larger common tolerance to focus and exposure variations than that of a feature drawn as isolated at the mask level.
Many of these OPC techniques must be used together on a single mask with phase-shifting structures of different phases added in as well for both resolution and process window enhancement. The simple task of biasing a one-dimensional line becomes increasingly complicated as two-dimensional structures must be moved, resized, enhanced with assist features, and possibly phase-shifted without causing any conflict with adjoining features. Due to the extended proximity range of deep sub-wavelength lithography, changes in the type of OPC applied to a feature can have unintended consequences for another feature located within half a micron to a micron. Since there are likely to be many features within this proximity range, the task of optimizing OPC decoration becomes increasingly complex with the addition of more aggressive approaches. Each new feature that is added to a design has an effect on other features, which then must be re-corrected in turn, and the results must be iterated repeatedly to converge to a mask layout where each feature can be printed in the manner in which it was originally intended while at the same time contributing in the proper manner to the aerial images of its neighboring features such that they too are printed within their respective tolerances.
Due to this complexity and mutual interaction between features, OPC technology has become a major field of innovation and many techniques have been widely described on how to “segment” or “dissect” the features into a manageable number of edges for co-optimization, how to prioritize the optimization routines so that the most critical structures are best protected from unintended distortion by nearby OPC assist features on neighboring features, how to resolve phase and placement conflicts between features, how to trade off computational speed versus ultimate convergence of the resulting feature to the desired results, and other details of the full implementation of OPC as a manufacturable technology.
OPC has generally moved from a rule-based to a model-based approach. In model-based OPC, both the effect of the exposure tool on the aerial image and the effect of the resist processing are modeled mathematically. FIG. 2 is a flowchart showing a typical model-based OPC design process. In step 210, a pre-OPC layout, an OPC technology file, an optical model, and a resist model are obtained. The OPC technology file describes the types of model-based OPC techniques that are to be used, for example linewidth bias corrections, corner rounding corrections, or line end pull back corrections. The optical model describes the illumination and projection optics of the exposure tool. The optical model may also include the effect of imaging into a thin-film resist or the effect of the mask topography. The resist model describes the changes in the resist after being illuminated by the mask pattern in the exposure tool. An etch model may also be used in the method of FIG. 2. The optical, resist, and etch models can be derived from first principles, determined empirically from experimental data, or a combination of both. The models are usually calibrated at the nominal process condition. See R. Socha, “Resolution Enhancement Techniques,” Photomask Fabrication Technology, Benjamin G. Eynon, Jr. and Banqiu Wu, Editors, McGraw-Hill, pp. 466-468, 2005. The pre-OPC layout, the OPC technology file, and the models are all inputs to the model-based OPC software.
In step 212, the model-based OPC software dissects the features in the pre-OPC layout into edge segments and assigns control points to each edge segment. Each feature is dissected prior to applying any OPC techniques because each feature, even identically-shaped features, will be subject to different proximity environments. The control points (or evaluation points) are the locations where CD or edge placement errors (EPE) will be evaluated during the OPC design process. The assignment of the control points is a complex process that depends on the pattern geometry of the pre-OPC layout and the optical model. FIG. 3 shows an L-shaped feature 310 with dissection points represented by triangles and assigned control points represented by circles.
In step 214, the model-based OPC software simulates the printed resist image on the wafer by applying the optical model and the resist model to the pre-OPC layout. In general, the simulation is performed at the nominal process condition at which the optical model has been calibrated. In step 216, the model-based OPC software generates the contours of the simulated resist image by comparing the simulated resist image values to a predetermined threshold value. The model-based OPC software then compares the simulated contours with the pre-OPC layout at all of the control points to determine if the design layout will deliver the desired patterning performance. The comparisons are typically quantified as a CD or an EPE at each control point. In step 218, the model-based OPC software determines whether a figure of merit for the contour metric of each edge segment is satisfied. In one embodiment, the figure of merit is satisfied when the total error for the contour metric, e.g., CD or EPE, of each edge segment is minimized. In another embodiment, the figure of merit is satisfied when the total error for the contour metric of each edge segment is below a predetermined threshold. If the figure of merit is satisfied the process ends, but if the figure of merit is not satisfied, the process continues with step 220.
FIG. 4 shows two EPEs with opposite signs measured at two control points. If an assumed simulated resist image contour 414 does not overlap the feature's designed geometry 412 at the control point, then the EPE is determined based on the difference at that control point. Returning to FIG. 2, in step 220 the model-based OPC software calculates the edge correction amount at each control point. If it is assumed that the EPE of the i-th edge segment (Ei) is ΔEi determined at control point Ci, the simplest edge correction amount ΔLi is a negation of the error: ΔLi=−ΔEi. Such a straightforward correction function does not work well for non-linear processes because changes on the mask are not linearly reflected in the printed resist image. To account for nonlinearities such as the mask error factor (MEF), a slightly more complicated correction function can be used:
      Δ    ⁢                  ⁢          L      i        =      -                            Δ          ⁢                                          ⁢                      E            i                          MEF            .      
In a real application, the method of calculating the appropriate correction is much more complex, and the correction algorithms can depend on factors such as linewidth error, fabrication process, correction goals, and constraints. See A. K. Wong, Resolution Enhancement Techniques in Optical Lithography, SPIE Press, pp. 91-115, 2001. For example, if it is assumed that there are N edge segments of a feature and one control point for each edge segment, and that the correction amount for the i-th edge segment is ΔLi, the ultimate goal is to solve for ΔL1, ΔL2, . . . , ΔLN, such that the difference between resist image values RI(Ci) and the predetermined threshold values T at all control points are equal to zero as:RI(Ci)−T=0 for i=1, . . . , N, where Ci are the control points.Or minimize the function
      ∑          i      =      1        N    ⁢          ⁢            [                        RI          ⁡                      (                          C              i                        )                          -        T            ]        2  
Next, in step 222, the model-based OPC software adjusts the entire edge segment Ei according to the calculated correction amount ΔLi for all edge segments to produce a post-OPC layout, such that the simulated resist image contour moves to match the design geometry. Then the method returns to step 214, where the model-based OPC software simulates a resist image using the post-OPC layout produced in step 222. The resist image contours and error are then calculated for the simulated resist image produced using the post-OPC layout in step 216. In step 218 the model-based OPC software determines whether the total EP error is minimized or below a certain threshold. The total EP error may be defined as:
      Error    total    =            ∑              i        =        1            N        ⁢                  ⁢                  (                  Δ          ⁢                                          ⁢                      E            i                          )            2      Alternatively, the total EP error can be defined as the maximum EP error of all segments, i.e.,max{|ΔEi|}, i=1, . . . , N since the OPC goal may be set such that all edge placement error must be below a certain threshold.
In the method of FIG. 2, the correction amount is determined individually for each edge segment in the mask layout, without taking into account effects from the movements of other edge segments in the layout. As feature size decreases, solving for the correction amount for individual edge segments experiences convergence problems. What is needed is a technique for determining correction amounts for each edge segment that takes into account the movements of other edge segments in the layout.
USPTO Backgrounds
USPTO Backgrounds