The present invention relates to microelectronic apparatuses and methods for making microelectronic components for microelectronic packages and assemblies.
Semiconductor chips are commonly provided in packages that facilitate handling of the chip during manufacture and during mounting of the chip on an external substrate such as a circuit board or other circuit panel. For example, many semiconductor chips are provided in packages suitable for surface mounting. Numerous packages of this general type have been proposed for various applications. Certain types of packages have been developed, which utilize a microelectronic component having a dielectric substrate having conductive traces disposed thereon. In such an arrangement, electrically conductive posts or pillars project from a surface of the substrate. Each post is connected to a portion of one of the traces. This type of microelectronic component is particularly useful in chip packages having arrangements that allow each post to move independently of the other posts. The movement of the posts allows the tips of the plural post to simultaneously engage contact pads on a circuit board despite irregularities in the circuit board or the package, such as warpage of the circuit board. Additionally, this facilitates testing of the package using simple test boards that may have substantially planar contacts, and avoids the need for specialized, expensive test sockets.
This type of microelectronic component has various applications and can be used in a number of different microelectronic package arrangements. As disclosed in certain preferred embodiments of U.S. patent application Ser. Nos. 11/014,439; 10/985,119; and 10/985,126, the disclosures of which are incorporated by reference herein, one such microelectronic package can include a microelectronic element such as a semiconductor chip and a microelectronic component comprising a substrate spaced from and overlying a first face of the microelectronic element. Such a component can include a plurality of conductive posts extending from the substrate and projecting away from the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. Additionally, such a package can include a plurality of support elements disposed between the microelectronic element and the substrate and supporting the substrate over the microelectronic element. Desirably, at least some of the conductive posts are offset in horizontal directions parallel to the plane of the substrate from the support elements. For example, the support elements may be disposed in an array with zones of the substrate disposed between adjacent support elements, and the posts may be disposed near the centers of such zones.
The dielectric substrate utilized in such a microelectronic component can be made from a material such as a polyimide or other polymeric sheet. It includes a top surface and a bottom surface remote therefrom. Although the thickness of the dielectric substrate will vary with the application, the dielectric substrate most typically is about 10 m-100 m thick. The sheet has conductive traces thereon. In one embodiment the conductive traces are disposed on the bottom surface of the sheet. However, in other embodiments, the conductive traces may extend on the top surface of the sheet; on both the top and bottom faces or within the interior of substrate. Conductive traces may be formed from any electrically conductive material, but most typically are formed from copper, copper alloys, gold or combinations of these materials. The thickness of the traces will also vary with the application, but typically is about 5 m-25 m. Traces are arranged so that each trace has a support end and a post end remote from the support end. The dielectric sheet, traces and posts can be fabricated by a process such as that disclosed in co-pending, commonly assigned U.S. patent application Ser. No. 10/959,465, the disclosure of which is incorporated by reference herein. As disclosed in greater detail in the '465 application, a metallic plate is etched or otherwise treated to form numerous metallic posts projecting from the plate. A dielectric layer is applied to this plate so that the posts project through the dielectric layer. An inner side of the dielectric layer faces toward the metallic plate, whereas the outer side of the dielectric layer faces towards the tips of the posts. Previously this dielectric layer has been fabricated by forcibly engaging the posts with the dielectric sheet so that the posts penetrate through the sheet. Once the sheet is in place, the metallic plate is etched to form individual traces on the inner side of the dielectric layer. Alternatively, conventional processes such as plating may form the traces or etching, whereas the posts may be formed using the methods disclosed in commonly assigned U.S. Pat. No. 6,177,636, the disclosure of which is hereby incorporated by reference herein. In yet another alternative, the posts may be fabricated as individual elements and assembled to the sheet in any suitable manner, which connects the posts to the traces.
Despite these advances in the art, still further improvements in making microelectronic components would be desirable.
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USPTO Backgrounds