1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package suitable for packaging a center pad layout-shaped memory chip wherein paddles of a lead frame are removed and outer leads of a lead frame are not protruded from the package but only exposed to a lower surface of molding resin of a semiconductor package.
2. Description of the Prior Art
Generally, semiconductor packages may be mainly classified into a semiconductor of SOP (small outline package) type and a semiconductor of SOJ (small outline J-lead) type.
In this case, the semiconductor packages are manufactured in accordance to following procedures. A semiconductor chip is attached on paddles of a lead frame and then wire bonding is carried out between inner leads of the lead frame and pads on the semiconductor chip. The wire bonded semiconductor and lead frame are molded by molding resin. Thereafter, the resulting product is subjected to deflash, trimming and forming procedures so that outer leads of the lead frame are protruded from the molded resin and then bent into predetermined shape respectively.
Referring to FIGS. 2 and 3, there are shown a front section and a bottom of a semiconductor package of LOC (lead on chip) type. In the semiconductor package shown in FIGS. 2 and 3, a semiconductor chip 3 is formed with a plurality of bond pads 3a at central portion thereof. Inner leads 4a of a lead frame 4 without paddles are attached on a surface of the semiconductor chip 3 at both sides of the bond pads 3a by means of insulation tapes 6. The inner leads 4a are electrically connected to the bond pads 3a of the semiconductor chip 3 by means of metal wires 7, respectively. Also, power supplying pads of the bond pads 3a are electrically connected to bus bars 5 by metal wires 7, respectively. Thereafter, the resulting semiconductor chip 3 and the inner leads 4a of the lead frame 4 are molded by molding resin 1.
The above-mentioned prior semiconductor packages are manufactured in such a manner that a semiconductor chip aggregate is subjected to a sawing step for dividing the semiconductor chip aggregate into separate semiconductor chips 3 and the semiconductor chip 3 is subjected to a die bonding step for attaching the separated semiconductor chip 3 to a lead frame 4, a wire bonding step for electrically connecting bond pads 3a of the semiconductor chip 3 to inner leads 4a of the lead frame 4 respectively, a molding step for enveloping the wire bonded semiconductor chip 3 and lead frame 4, a deflashing step, a solder plating step, a trimming step for cutting dampers of the lead frame 4, a forming step for bending outer leads into a certain shape, and a marking step.
The semiconductor package prepared as described above have outer leads protruded from the mold resin. The outer leads are formed into a certain shape and then mounted on a printed circuit board.
However, the prior semiconductor packages have various disadvantages as follows. The prior semiconductor packages occupy large space due to the outer leads protruded from mold resins when the semiconductor packages are mounted on printed circuit boards.
Since the semiconductor packages have outer mechanical shock when their forming procedure, fine gaps may occur in contact areas between outer leads protruded from package bodies and mold resins, thereby causing humidity resistant property to be deteriorated due to the gaps.
Also, since the semiconductor packages require a trimming step and a forming step after a molding procedure, manufacturing process of the packages becomes complicated so that their manufacturing cost and poor products occurring rate are increased.
In addition, in case of the LOC type of semiconductor packages using lead frames without paddles, electrical property is decreased because of their long length between inner leads and outer leads.
Furthermore, so-called "good rate" which is a rate of good products in products identified as poor packages is increased because of poor lead contacts in testing of finished products.
USPTO Backgrounds
USPTO Backgrounds