The present invention relates to a digital signal processing apparatus for mixing which is suited for application to digital mixers etc. that process sound or audio signals.
Heretofore, there have been known digital signal processing apparatus (DSPs) which perform various arithmetic operations on input digital signals. The DSP is used, for example, in an electronic musical instrument, to perform an effect impartment process for imparting various audio effects to tones (digital audio signals) and other processes. Generally, the DSP includes an interface for connection with other DSPs; by connecting with a plurality of other DSPs via the interface, an enhanced arithmetic capability can be achieved as a whole. Among examples of interfaces for interconnecting DSPs are a serial I/O and audio bus I/O.
First, the serial I/O is explained. Each DSP includes a serial input port and serial output port. The serial output port of a first DSP is connected to the serial input port of a second DSP, so that audio signals are transferred from the first DSP to the second DSP. Namely, unidirectional transfer of digital signals is permitted between such directly-interconnected DSPs. In this case, one DAC period (one sampling period) is required for “serial conversion in the first DSP”→“signal transfer”→“parallel conversion in the second DSP”.
Next, the audio bus I/O is explained. Each DSP includes an audio bus I/O. When a plurality of DSPs are to be interconnected, the audio bus I/Os of all of the DSPs are connected to bus lines of a common audio bus. Each of the DSPs transmits or transfers audio signals using frames allocated to the DSP. The “frames” are time sections allocated to the individual DSPs when data are to be transferred in a DAC period by time-divisional processing. The DSP at a transmitting end transfers, to the common audio bus, signals in a frame allocated thereto, and the DSP at a receiving end receives, from the common audio bus, the transferred signals in that frame. In this way, signals of a given DSP connected to the common audio bus can be transferred to another DSP. In this case, one DAC period is required for “transmitting DSP”→“audio bus”→“receiving DSP”.
The DSP performing signal processing as noted above is also used in audio signal mixing processing by a digital mixer. In a digital mixer, a quantity of arithmetic operations performed in mixer processing increases/decreases in accordance with the number of channels to be processed, and thus, the arithmetic capability of just one DSP alone may sometimes be insufficient. In such a case, a plurality of DSPs are interconnected via the above-mentioned interfaces to allow signals to be transferred bi-directionally between the DSPs so that mixer processing is performed cooperatively by the DSPs.
The mixer processing comprises two major processing: adjustment processing, such as processing by an equalizer and compressor, for adjusting characteristics of audio signals; and mixing processing for mixing audio signals after controlling levels of the audio signals. Whereas the adjustment processing varies in content depending on the model type, operation mode, etc. of the processing apparatus, the mixing processing repeats same operations irrespective of the model type, operation mode, etc. of the processing apparatus. It is not efficient to use a programmable DSP in such monotonous repetition of the same operations.
Japanese Patent Application Laid-open Publication No. HEI-11-085155 and No. 2003-255945 (hereinafter referred to as “Patent Literature 1” and “Patent Literature 2”, respectively) each disclose a prior art technique where a DSP for performing ordinary or normal signal processing and a DSP for performing mixing processing are integrated into one chip, although the disclosed DSPs are indented for use in a tone generator of an electronic musical instrument rather than in a digital mixer.
Patent Literature 1 discloses an integrated circuit in which are collectively incorporated a tone generation section for generating tones of a plurality of channels, a DSP section for performing the adjustment processing (e.g., effect impartment) and a mixer section for performing the mixing processing. The mixer section inputs signals of 96 channels, multiplies the input signals of the individual channels by eight different coefficients, performs mixing of the results of the multiplication via 32 mixing buses and then outputs resultant mixed signals of 32 channels. Here, the numbers of the input channels and mixing buses are fixed and non-changeable.
Patent Literature 2 too discloses an integrated circuit in which are collectively incorporated a tone generation section for generating tones of a plurality of channels, a DSP section for performing the adjustment processing and a mixer section for performing the mixing processing. The mixer section can select, for each of the input channels, which signal should be input and to which bus the signal should be output. The mixer section can select, per input channel, the numbers of times the coefficient multiplication and mixing in a mixing bus should be performed. Further, the mixer section can designate, for each of the mixing buses, signals of how many channels and of which channels should be input to that mixing bus. Thus, the mixer section disclosed in Patent Literature 2 can achieve an extremely high degree of freedom.
However, the technique disclosed in Patent Literature 1, where the numbers of the channels and mixing buses are fixed, can not flexibly meet user's requests, such as 1) a request that the number of the channels be increased although the number of the mixing buses may be decreased, 2) a request that the adjustment processing per channel be made more complicated with the number of the channels decreased and 3) a request that the number of the mixing buses be increased. Similar inconvenience is encountered in a case where mixing processing is implemented through operation of fixed microprograms; to meet the above-mentioned request, it is necessary remake the microprograms.
In the case where arrangements are made to permit designation of input and output channels per mixing channel as disclosed in Patent Literature 2, there can be achieved a higher degree of freedom as a mixer, separate registers are required for setting input and output channels per mixing channel and settings have to be performed on all of these registers, which would complicate processing for managing the mixer section.
As regards algorithms of mixing processing performed in ordinary digital mixers, an output point at which an audio signal is to be output from an input channel to a mixing bus varies (e.g., by pre-fader/post-fader switching), but an input point at which an audio signal is to be input from a mixing bus to an output channel is fixed. Therefore, in order to implement such mixing processing, it is not essential to permit designation of an output destination per mixing channel.
In some cases, mixing apparatus are designed which differ from each other in the number of input channels, content of processing performed in the input channels, number of mixing buses, etc. in accordance with their requested specifications. However, the conventional DSPs can not meet such various requirements. Besides, with the conventional DSPs, which audio transmission terminals are to be used for what purposes and which audio reception terminals are to be used for what purposes are not decided in advance. Thus, in a case where mixing processing is performed cooperatively by a plurality of DSPs, it has been necessary to allocate content of the mixing processing to be implemented to the individual DSPs with audio signal transfer between the DSPs taken into account. Thus, designing of a circuit board and processing programs tends to be very complicated.
In a case where a plurality of DSPs are to be interconnected in such a manner that desired signal transfer can be achieved using serial I/Os, the connection tends to be complicated like a puzzle, which would lead to very difficult designing. On the other hand, interconnecting a plurality of DSP in such a manner that desired signal transfer can be achieved using audio bus I/Os is not so difficult; however, using audio buses of high general versatility in order to increase the number of channels is very wasteful and inefficient.
Further, in a case where a plurality of DSPs are interconnected in a cascade fashion (i.e., “cascade-connected”), a signal received in a given sampling period is mixed with outputs of the individual DSPs in the next sampling period and then output to the next DSP in the still next sampling period. Therefore, a signal received in a given DAC period can not be output to the next DSP in the next DAC period. Namely, in the case where a plurality of DSPs are cascade-connected so that an audio signal is sequentially transferred between the DSPs, a time delay of a length equal to at least two sampling periods would be produced in the signal per DSP. In recent business-use audio equipment, requested specifications to strictly eliminate undesired sample displacements are sometimes required, and thus, there is a need to minimize a time delay per DSP in the case where a plurality of DSPs are cascade-connected.
Generally, in the case where mixing apparatus are designed which differ in the number of input channels, content of processing performed in the input channels, number of mixing buses, etc. in accordance with their requested specifications, as noted above, the conventional DSPs would present the problem that they can not flexibly meet the various requirements by the DSPs being just simply interconnected. Particularly, the conventional DSPs can not properly meet a request for strictly eliminating undesired sample displacements.
V Further, the conventional signal processing integrated circuits as discussed above contain a plurality of blocks, such as an input block, output block and signal processing block. In a case where signals are to be transferred from one of the blocks to another, it has been conventional to provide fixed connection wiring corresponding to a transfer path of the signals, which however tends to be very inefficient. It is conceivable to replace such fixed connection wiring with a block-to-block (inter-block) communicating memory, in which case, however, the communicating memory has to be a high-speed memory because it receives write accesses and read accesses from a plurality of blocks. In addition, a frequency band width necessary for the communicating memory increases as the number of the blocks, constituting the integrated circuit, increases, which would make designing of the integrated circuit more difficult.
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