Embodiments of the present invention provide a shift register as it may, for example, be used in one-of-many shift registers. Further embodiments provide a one-of-many shift register as it may, for example, be used in image sensors or generally in multiplexers.
With a one-of-many selection circuit, exactly one output of a number N of outputs has a digital level of “1”. All other outputs have a level of “0”. For the realization, a shift register is used through which a “1” is shifted.
The setup of such a conventional shift register (SR) is illustrated in FIG. 4.
The flip-flops 401a to 401n are connected to each other such that all D flip-flops 401a to 401n receive the same clock signal 403 (or at least the same clock levels and clock edges). The output of one D flip-flop is connected to the input of the next D flip-flop.
The D flip-flops illustrated in FIG. 4 may here be set up as illustrated in FIG. 5.
In FIG. 5, in addition two inverters 501, 503 for clock inversion and clock conditioning are introduced which are contained in many standard cells.
The inverter 501 at the input of the D flip-flop 401a is responsible for refreshing an input signal 505 and the inverter 503 at the output of the D flip-flop 401a is responsible for driving the output load. In between, two latches 507, 509 are located (latch memory member), which have an inverted clock control.
A first latch 507 takes over the data at the input when an input switch 511 of the first latch 507 is closed (conductive). In FIG. 5, the first latch 507 takes over the input data, when CKD is “0” and CKN is “1”, i.e. when CK=“0” (with a low level of the clock signal 403). A feedback switch 513 of the first latch 507 is then opened (not conductive) and inverters 515, 517 of the first latch 507 take on a state which depends on the input signal 505. While CK=“0”, any change of the input signal 505 causes a change of the inverter outputs of the two inverters 515, 517 of the first latch 507. One says that the latch is transparent. At the rising edge of CK (the clock signal 403), the input switch 511 of the first latch 507 opens and the feedback switch 513 of the first latch 507 closes. Here, the preceding input value is stored in the feedback inverters 515, 517. The first latch 507 is no longer transparent.
Due to the series connection of the invertedly clocked latches 507, 509, one latch is transparent, while the other latch latches. While CK=“0”, the input (the signal state of the input signal 505 at the input) in the first latch 507 is taken over transparently. The second latch 509 meanwhile maintains the old output value. When CK rises to “1”, the first latch 507 stores the preceding input value and forwards the same to the second latch 509. The second latch 509 is now transparent, but the output does not change as the input does not change (as the first latch 507 is in the non-transparent state). The input is forwarded to the output. Thus, the D flip-flop 401a takes over the input with a rising clock edge to the output. Between the clock edges, the input signal 505 may change without the output changing.
In the shift register illustrated in FIG. 4, it is assumed in the output state that all D flip-flops 401a to 401n have “0” at the input and output and that the clock level is “0”. If “1” is applied to the input of the shift register (at a data input of the first D flip-flop 401a) and a rising edge is applied to the clock, this “1” is taken over into the first D flip-flop 401a, all other D flip-flops 401b to 401n take over the inputs to the outputs, according to the initial value “0”. Then, a “0” is applied to the input of the shift register and a further clock period is generated. The “0” at the input is taken over into the first D flip-flop 401a, while the second D flip-flop 401b takes over the “1” of the first D flip-flop 401a. All other D flip-flops again take over “0”. With every further rising clock edge (of the clock signal 402), the “1” is shifted on by one D flip-flop.
This circuit may be used to select one of N. For this purpose, N DFFs are needed.
The number of transistors needed to implement the function is N*24, as a DFF contains 24 transistors. It is a precondition here that a switch and an inverter are each set up from two transistors.
There is the possibility of using dynamic DFFs. The same have the disadvantage, however, that they operate error-free only from a minimum clock frequency. For each output of the shift register, thus a D flip-flop is needed. As conventional D flip-flop implementations (as are illustrated, for example, in FIG. 5) need 24 transistors, for such a shift register a large number of transistors and thus a large area for the shift register is needed.
USPTO Backgrounds
USPTO Backgrounds