1. Field of the Invention
The invention relates to a multi-layered, three-dimensional integrated circuit and to a method for fabricating a multi-layered, three-dimensional integrated circuit.
2. Description of the Related Art
Multi-chip 2-dimensional module approaches currently used in the integrated circuit (IC) industry for interconnecting chips into an electronic system suffer from several significant limitations. These include: high electrical impedance between individual chips; low areal and vertical densities; and high cost, complexity and inefficiency in thermal management.
A particularly important limitation of 2-dimensional approaches is interconnect signal delay. Interconnect delays in large 2-dimensional chips have begun to increase per unit length in successive generations of IC technology. A need clearly exists, therefore, for technologies that reduce overall interconnect length in tandem with increasing device density.
One potential way of overcoming the shortcomings of 2-dimensional integrated circuits is the development of 3-dimensional integrated circuit technology. The fabrication of 3-dimensional ICs by several techniques has been previously reported. However, previous techniques still suffer from many disadvantages rendering such techniques less commercially advantageous. One shortcoming of known techniques is ineffective thermal management. Interlayer alignment tolerance is also a limitation of current techniques.
The present invention provides 3-dimensional integrated circuits, and methods of preparing the same, in which many of the problems of prior art systems, including signal delays and ineffective thermal management, are overcome.
USPTO Backgrounds
USPTO Backgrounds