1. Field of the Invention
The present invention relates to a method of fabricating a dual damascene structure on a surface of a semiconductor wafer.
2. Description of the Prior Art
Adual damasceneprocess is a method of forming a conductive wire coupled with a plug. The dual damascene structure is used to connect devices and wires in a semiconductor wafer and functions as an insulator from other devices using surrounding inter-layer dielectrics (ILD). The dual damascene structure is widely applied in the manufacturing process of integrated circuits. Thus, advancement in integrated circuit technology makes yield improvement of the dual damascene structure an important issue in the manufacturing process of integrated circuits.
Please refer to FIG. 1 to FIG. 5 of cross-sectional views of a dual damascene structure 36 manufactured by a via-first dual damascene process according to the prior art. As shown in FIG. 1, a semiconductor wafer 10 comprises a substrate 12, a conductive layer 14 positioned on a surface of the substrate 12 in a predetermined area, a passivation layer 16 composed of silicon nitride horizontally covering the substrate 12 and the conductive layer 14, a first dielectric layer 18 composed of silicon oxide covering the passivation layer 16 and a second dielectric layer 20 composed of silicon oxide covering the first dielectric layer 18. The passivation layer 16, the first dielectric layer 18 and the second dielectric layer 20 can be respectively deposited by a plasma-enhanced chemical vapor deposition (PECVD) method.
As shown in FIG. 1, the prior art method of fabricating a dual damascene structure 36 is to first uniformly coat a first photoresist layer 22 on a surface of the second dielectric layer 20 using a lithography process. An opening 24 extending to the surface of the second dielectric layer 20 is formed in a predetermined area of the first photoresist layer 22 directly above the conductive layer 14, and the opening 24 is used to define a via pattern. Then, as shown in FIG. 2, an anisotropic dry etching process is performed to vertically remove the second dielectric layer 20 and the first dielectric layer 18 not covered by the first photoresist layer 22 along the opening 24 so as to form a hole 26 extending to a surface of the passivation layer 16. Thereafter, a photoresist stripping process is performed to completely remove the first photoresist layer 22.
As shown in FIG. 3, another lithography process is performed uniformly coating a second photoresist layer 28 over the second dielectric layer 20. The second photoresist layer 28 is a positive photoresist and fills the hole 26. As shown in FIG. 4, in exposure and development processes performed on the semiconductor wafer 10, parallel lights 30 from a light source pass through a mask 32 mainly composed of glass to the photoresist layer 28 composed of photo-sensitive material so as to transfer patterns of the mask 32 to the second photoresist layer 28. Since the second photoresist layer 28 is composed of a positive photoresist layer, a portion of the second photoresist layer 28 that is exposed to light decomposes to form a structure that is soluble in developer solution. Then an alkaline solution such as sodium hydroxide (NaOH) or potassium hydroxide (KOH) is used as a developer solution to remove the developed photoresist layer by a neutralization reaction. As shown in FIG. 5, a line-opening is formed on the second photoresist layer 28 after the exposure and development processes, which is used to define the pattern of wiring lines connecting between each device.
The prior art method of fabricating a dual damascene structure 36 on a semiconductor wafer 10 proceeds an exposure and development process by placing the semiconductor wafer 10 in a photolithography apparatus so as to define wiring line patterns. As the semiconductor process becomes more and more delicate, the aspect ratio of void 26 is great so the photoresist layer filling in a bottom of void 26 does not easily receive sufficient light irradiation. Therefore, the portion of positive photoresist does not decompose to form a structure soluble in developer solution, so the photoresist layer in the bottom of void 26 can not be neutralized with developer solution to be completely removed in a subsequent photoresist removing process. This residual photoresist 29 in the bottom of void 26 may cause polymer aggregating in corners in the subsequent etching process, which results in a via open issue of the fabricated via hole and influences the electrical performance of the hole semiconductor integrated circuit.
It is therefore a primary objective of this invention to provide a method for fabricating a dual damascene structure on a surface of a semiconductor wafer so as to solve the above-mentioned problem of residual photoresist and improve product yield.
In a preferred embodiment of the present invention a first passivation layer, a first dielectric layer, a second passivation layer, a second dielectric layer, a third passivation layer and a third dielectric layer are formed respectively on a surface of the semiconductor wafer followed by etching of the third dielectric layer to form a pattern of an upper trench of the dual damascene structure. Then the third passivation layer and the second dielectric layer are etched down to a surface of the second passivation layer to form a pattern of a via hole of the dual damascene structure. Thereafter, the third passivation layer and the second passivation layer not covered by the third dielectric layer and the second dielectric layer are removed. The third dielectric layer and the second passivation layer are used as hard masks to remove the second dielectric layer and the first dielectric layer to the surface of the first passivation layer. Finally, the second passivation layer and the first passivation layer not covered by the second dielectric layer and the first dielectric layer are removed to a surface of the conductive layer so completing the process of fabricating the dual damascene structure.
The present invention firstly uses photoresist layers to define an upper trench pattern and a via hole pattern of the dual damascene structure respectively in a dielectric layer and in a passivation layer. Then the dielectric layer and the passivation layer are used as hard masks to perform an etching process simultaneously forming the position of wiring lines and contact plugs. Therefore, the problem of a residual photoresist layer in the bottom of the via hole according to the prior art method does not occur, so process efficiency and throughput is improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
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