1. Field of the Invention
The present invention relates to parallel data counter circuits, and more specifically, to parallel data counter circuits which calculate the total numbers of "1"'s or "0"'s in parallel data which is generated in synchronization with a clock.
2. Description of the Related Art
Hereinbelow, an example of a conventional parallel data counter circuit will be explained with reference to FIG. 6. FIG. 6 shows a parallel data counter circuit which calculates the number of "1"'s in four parallel groups of data comprising four m-bit counter circuits 6-9. The m-bit counter circuits 6-9 respectively have parallel data input terminals 20-23, and each of their input sides are connected to a clock terminal 30, a storage signal input terminal 40, and a reset terminal 50. Initially, storage data output terminals 70-73 are respectively connected to the output sides of m-bit counter circuits 6-9.
As examples of m-bit counter circuits 6-9, it is possible to use those comprising an m-bit counter 200 and a storage circuit 201 such as that shown in FIG. 7. A data input terminal 220, a clock input terminal 230 and a reset terminal 250 are connected to m-bit counter 200, while a storage signal input terminal 240 and a storage data output terminal 270 are connected to the storage circuit
In the m-bit counter circuit of FIG. 7, m-bit counter 200 performs a count by means of clock signal 230A input from clock terminal 230, with data 220A input from data input terminal 220 as a control signal. In this example, m-bit counter 200 has a control structure such that the clock signal 230A counts up when the data 220A is equal to 1. The count value 200A of this m-bit counter 200 is inputted to the storage circuit 201.
In order to read out the count value for a given time, storage circuit 201 stores the count Value 200A according to a signal 240A input to the storage signal terminal 240. Then the count value 200A is output from storage data output terminal 270 as an output signal 270A. The m-bit Counter 200 is initialized when a reset signal 250A is input to reset terminal 250.
Next, the operation of a conventional parallel data counter circuit will be explained with reference to FIG. 6. Four pieces of parallel data 20A-23A which have been input to data input terminals 20-23, are respectively input to the data input terminals of m-bit counter circuits 6-9. The m-bit counter circuits 6-9 perform calculations based on clock signal 30A input from clock input terminal 30.
When reading out the results of the calculations in the parallel data counter circuit at a given time, a signal 40A in synchronization with clock signal 30A is input to storage signal input terminal 40. The signal 40A is input to the storage signal input terminals of the m-bit counter circuit 6-9. Then, each of the m-bit counter circuits 6-9 stores the calculated value for that time and outputs storage data 6A-9A. These storage data 6A-9A are output from the storage data output terminals 70-73. When a reset signal 50A is input to reset terminal 50, each m-bit counter circuit 6-9 is initialized, thereby initializing the parallel data counter circuit of FIG. 6.
Next, the procedure for calculating all of the calculation values in the parallel data counter circuit from the above-mentioned storage data will be explained. The storage data 6A-9A for a given time are equal to the calculation values of the four parallel data 20A-23A respectively. Therefore, the total calculation value of the parallel data counter circuit is 6A+7A+8A+9A.
While FIG. 6 shows an example of a quadruple parallel data counter circuit, it is possible to have an n-parallel data counter circuit provided with n m-bit counter circuits for n groups of data. Additionally, the total calculated value for such as case, when taking the calculated value for each m-bit counter circuit to be X.sub.n, would be .SIGMA.X.sub.n.
However, with conventional parallel data counter circuits, it is necessary to provide n counter circuits corresponding to n parallel data in order to calculate the total value over all of the data. For this reason, the number of counter circuits increases with the number of parallel data to be calculated, which can lead to problems with enlargement of the circuit.
Additionally, it is necessary to, increase the number of bits m for each counter circuit when increasing the count number of the counter circuit. When the bit number m of each counter circuit is increased in this way, there is a problem in that the size of the circuit could increase even further by m times for the n parallel data over the entire parallel data counter circuit.
USPTO Backgrounds
USPTO Backgrounds