The trend in the semiconductor industry is toward more and more complexity on each integrated circuit (IC) produced. The increased complexity results in an increase in the number of devices, transistors and the like, required to implement the circuits. As the number of devices increases there is a demand for smaller feature sizes; that is, smaller lines and smaller spaces between lines.
Extensive use is made of photolithography to transfer images from a photo mask to the surface of a semiconductor substrate upon which the IC is being fabricated. As the feature size is reduced it becomes more difficult to reliably reproduce the mask images on the substrate. Reproducing feature sizes in the range of tens of nanometers (nm) requires high numerical aperture (NA) optics and off-axis illumination. Unfortunately such techniques for dealing with small feature sizes can lead to difficulties with reproducing large features. For example, when trying to reproduce wide, spaced apart lines on a semiconductor substrate using optical tools suited for small features, a dip in image intensity between the lines can result in underexposure and a resist scum. The resist scum, in turn, can result in unacceptable process yield.
Accordingly, it is desirable to provide methods for fabricating photolithographic masks that overcome the above-mentioned problems. In addition, it is desirable to provide methods for fabricating semiconductor integrated circuits at high yields. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
USPTO Backgrounds
USPTO Backgrounds