1. Field of the Invention
The invention relates to a process for preparing a semiconductor device, and more particularly to a process for preparing a mask for use in ion implantation.
2. Description of the Related Art
A conventional method for the preparation of a semiconductor device involves such manner that on the surface of an intermediate product of a semiconductor device, which comprises a semiconductive silicon substrate 11, an active layer (Source and Drain) 12, a gate oxide film 13, a gate electrode 14, an isolating oxide film 15, a passivation film (a protective layer) 16 and metal wiring 17 each formed on the substrate in this order as shown in FIG. 5, is formed a photoresist film 18 of 1 to 2 .mu.m in thickness which photoresist film then applied at its portion above the gate electrode 14 with light by lithography and developed to have an opening. An impurity ion with 400 keV high energy is applied to the photoresist film 18 from above to implant the impurity ion under the gate oxide film 13 through the opening of the photoresist film 18 used as a mask, so that a channel region is provided under the gate oxide film of the semiconductor device. A combination of a silicon thermal oxide film or a silicon nitride film with a photoresist film is also used for an ion implantation mask in place of the above photoresist film 18.
The photoresist film is limited in thickness to 1 to 2 .mu.m to keep its inherent resolution. The conventional ion implantation technique is conducted generally by ion acceleration energy or 200 keV and maximum acceleration energy of 400 keV in double charging process. Also, a commercially available ion implantation equipment developed recently can provide a high ion acceleration energy of MeV level. Hence, the photoresist is poor in stopping power of ion having such high accelerated energy to permit implanted ion to pass through the resist. For example, when a photoresist film 18 of 1.1 .mu.m is used as a mask for applying with a high energy of 400 keV an impurity ion under the gate oxide film 13 in the MOS transistor including the protective film 16 as shown in FIG. 5, the implanted ion passes through the photoresist film 18 and further the metal wiring 17 or stops therein to deteriorate reliability of the metal wiring 17.
In detail, when the ion uses .sup.11 B.sup.+, it is so calculated that an average of projection range R.sub.p of B at 400 keV is 3.076 .mu.m, a standard deviation .DELTA.R.sub.p 0.180 .mu.m, R.sub.p in the metal (Al) 0.935 .mu.m and .DELTA.R.sub.p therein 0.123 .mu.m. In this case, the implanted B having 400 keV must stop in the metal wiring and distribution of the B ion therein is simulated as FIG. 3 (a). The metal wiring has problems in wiring resistance, moisture proof and reliability and is desired to be improved for the processes particularly after 0.5 to 0.3 .mu.m ruling.
Also, to avoid interference between the implanted ion and the metal wiring, such means may be adopted that (i) a lower energy for ion implantation is used, (ii) thickness of photoresist is made larger, and (iii) any mask element of a higher ion stopping power is employed. The means (i) is not available due to the inherent process of device construction, and the means (ii) has presently a limit to 3 .mu.m at maximum in relation to pattern shift and resolution of the resist. Also, PIQ (polyimide) used recently for photoresist has problems in an opening portion that tends to be largely tapered to thereby be substantially decreased in diameter, and also in uniformity in coating of the wafer surface portion. For the means (iii), a mask element such as a thermal oxide film, a CVD metal film or the like is not usable due to a critical heat resistance (575.degree. C.) of metal wiring (Al) and the trouble in holing process of a formed mask element.
The present invention has been designed to overcome the above problems.
USPTO Backgrounds
USPTO Backgrounds