An on-chip set associative cache is a local memory storage device for a data processor. The on-chip set associative cache contains a duplicate copy of frequently utilized instructions and data for the data processor. A cache allows the data processor to minimize instruction and data accesses to external memory which require additional time, thereby obtaining an increase in data processing performance. An aspect of the on-chip set associative cache that provides an increase in data processing performance is the output line bit length of the on-chip set associative cache. That is, a relatively longer line bit length provides more instruction and data information for the data processor to access. A problem common to on-chip set associative caches, and in particular, to an on-chip set associative cache with a relatively long output line bit length, is excessive power consumption. Known methods of reducing the power consumption of the on-chip set associative cache include, but are not limited to, reducing the number of associated sets, and limiting the output line length for the on-chip set associative cache. However, both of the above mentioned solutions to reducing power have a common disadvantage of degrading performance of the data processing system with an on-chip set associative cache.
USPTO Backgrounds
USPTO Backgrounds