The present invention relates to a method and an apparatus for producing a bonded dielectric separation wafer, and in more specific, to a method for producing such a bonded dielectric separation wafer having a certain physical relationship established between a position of an orientation flat, xe2x80x9cOFxe2x80x9d, of a supporting substrate wafer and a position of a pattern of dielectric isolation grooves of an active layer wafer and also to an apparatus used for bonding those wafers.
In the prior art, a bonded dielectric separation wafer has been produced through respective steps shown in FIGS. 5 and 6.
In one prior art method, at first, a silicon wafer 10 having a mirror-polished surface is fabricated and prepared in accordance with a well-known method, which will be formed into an active layer wafer (see FIG. 5(a)). This silicon wafer 10 has an orientation flat xe2x80x9cOFxe2x80x9d formed therein. Secondary, a mask oxide film 11 is formed on a surface of this silicon wafer 10 (FIG. 5(b)). Further, after a photo resist 12 is deposited over the mask oxide film 11, the photo lithography method is applied to form openings in predetermined locations (in apredetermined pattern) thereof. Then, the mask oxide film 11 exposed through these openings is removed so as to form windows of predetermined pattern in the mask oxide film 11. Consequently, the top surface of the silicon wafer 10 can be partially exposed through these windows. Then, after the photo resist 12 is removed, this silicon wafer 10 is dipped in an alkaline etchant (IPA/KOH/H2O) to anisotropically etch the inside of the window defined on the top surface of the wafer (FIG. 5(c)). Through these steps, V-shaped dielectric isolation grooves 13 are formed in the surface of the wafer.
In a subsequent step, this mask oxide film 11 is cleaned and removed using a dilute hydrofluoric acid solution or a buffer hydrofluoric acid solution (FIG. 5(d)). Then, a dielectric separation oxide film 14 is formed on the surface of the silicon wafer 10 through a thermal oxidation processing (FIG. 5(e)). As a result, the dielectric separation oxide film 14 having a predetermined thickness is formed over the surface of the silicon wafer 10 including the surfaces of the dielectric isolation grooves 13.
Subsequently, this silicon wafer 10 is coated with a seed polysilicon layer 15 over the surface thereof, i.e., over the dielectric separation oxide film 14, up to a predetermined thickness. After that, a high temperature CVD method is applied at the temperature of about 1200 to 1300xc2x0 C. so as for a high temperature polysilicon layer 16 to grow over the dielectric separation oxide film 14 until it reaches the thickness of about 150 xcexcm (FIG. 5(f)). After that, a peripheral portion of this silicon wafer 10 is beveled. In a subsequent step, polishing is applied to a back surface of this silicon wafer 10 so as to remove undesired portion of high temperature polysilicon, which has expanded to cover partially the back surface, thus to obtain a flat surface. Then, grinding and polishing are carried out until the high temperature polysilicon layer 16 on the top surface of the silicon wafer 10 becomes about 10 to 80 xcexcm thick (FIG. 6(g)).
After that, a low-temperature CVD method is applied at a temperature in the range of 550 to 700xc2x0 C. so as for a low-temperature polysilicon layer 17 to grow over the surface of the silicon wafer 10 up to 1 to 5 xcexcm thick. In order to flatten a bonding surface, the top surface of this low-temperature polysilicon layer 17 is mirror-polished (FIG. 6(g)).
On the other hand, a silicon wafer 20 covered with a silicon oxide film 21 is prepared separately from said silicon wafer 10, which will function as a supporting substrate wafer (FIG. 6(h)). A surface of this silicon wafer 20 has also been mirror-polished. In addition, this silicon wafer 20 has been processed to have the orientation flat.
Then, this silicon wafer 20 is bonded with the other silicon wafer 10 prepared for the active layer wafer as described above, with the mirror-polished surfaces thereof contacting to each other (FIG. 6(i)). Thus, a base material of the bonded wafer has been fabricated.
After that, a thermal processing is applied to thus bonded wafer to enhance its bonding strength.
Then, as shown in FIG. 6(j), the peripheral region of this bonded wafer in the active layer wafer side is beveled. Specifically, the grinding is applied to the bonded wafer from the top surface of the silicon wafer 10 at an oblique angle such that a portion as defined to pass through the bonding interface and to reach the surface layer of the silicon wafer 20 may be cut off.
Then, the top surface of the bonded wafer in the active layer wafer side is ground and further polished (FIG. 6 (k)). The volume to be ground and polished off from the active layer wafer should be determined such that the dielectric separation oxide film 14 may be partially exposed to the outside and thus dielectric separation silicon islands 10A separated from each other by the dielectric separation oxide film 14 may appear on top of the high temperature polysilicon layer 16. It is to be noted that the silicon oxide film 21 will be removed by the HF cleaning after the above step.
In this method according to the prior art as discussed above, after the high temperature polysilicon layer 16 having grown on the silicon wafer 10, the beveling process is applied thereto to remove the polysilicon deposited on the peripheral region of the wafer. However, in practice, it is impossible to carry out this removing process completely, and typically, a part of the polysilicon should be left in the peripheral region of the wafer in order to avoid the reduced diameter of the silicon wafer 10 owing to an excessive grinding.
This means that the polysilicon layers may also be left in the orientation flat (OF) portion of the silicon wafer 10.
This has often led to such a situation in which after the beveling, the xe2x80x9cOFxe2x80x9d formed by the residual high temperature polysilicon layer 16 is not in the parallel relationship with the xe2x80x9cOFxe2x80x9d of the silicon wafer 10.
Generally, the bonding of the wafers is carried out in such a manner that the xe2x80x9cOFxe2x80x9d of the active layer wafer and the xe2x80x9cOFxe2x80x9d of the supporting substrate wafer should be matched and then, in one example, the both wafers are bonded to each other from the central portions toward the peripheral portions thereof so as to increase the bonded area. In this manner, the two wafers can be bonded to each other, while keeping a certain physical relationship between the xe2x80x9cOFxe2x80x9d of the supporting substrate wafer and the grid pattern of the dielectric isolation grooves formed on the active layer wafer. In specific, the horizontal dielectric isolation grooves or structural elements of the grid pattern in parallel with Y-direction in FIG. 4 are set to be in parallel with the xe2x80x9cOFxe2x80x9d of the wafer for the supporting substrate. As a result from this setting, auto-alignment with reference to the xe2x80x9cOFxe2x80x9d of the supporting substrate wafer will be effective in each consecutive processing step following this bonding step.
However, whether or not this auto-alignment will effectively work depends on the condition of the xe2x80x9cOFxe2x80x9d portion of the active layer wafer, that the xe2x80x9cOFxe2x80x9d of the high temperature polysilicon layer should be in parallel with the original xe2x80x9cOFxe2x80x9d inherent to the active layer wafer. This is because the pattern of the dielectric isolation grooves is externally shielded with the high temperature polysilicon layer and accordingly it would not be possible to bond the supporting substrate wafer to the active layer wafer while visually observing the xe2x80x9cOFxe2x80x9d of the supporting substrate wafer and the horizontal grooves of said pattern on the active layer wafer and keeping the parallel relationship therebetween on the screen of a monitor, for example. That is, if the xe2x80x9cOFxe2x80x9d of the high temperature polysilicon layer is not parallel with the xe2x80x9cOFxe2x80x9d of the active layer wafer, the auto-alignment could not be carried out in any consecutive steps, such as an exposing process, for example.
The present invention has been made in the light of the problems described above, and an object thereof is to provide a method for producing a bonded dielectric separation wafer which allows an auto-alignment to be carried out with reference to an orientation flat xe2x80x9cOFxe2x80x9d of a supporting substrate wafer after a wafer bonding step, and an apparatus used for bonding those wafers.
The invention as defined in claim 1 provides a method for producing a bonded dielectric separation wafer comprising the steps of: growing a polysilicon layer on a top surface of an active layer wafer which has dielectric isolation grooves in a predetermined pattern having formed therein with reference to an orientation flat thereof and has been covered with a dielectric separation oxide film; polishing a top surface of the polysilicon layer; fabricating a bonded wafer by bonding the polished surface of the active layer wafer to a surface of a supporting substrate wafer having an orientation flat; beveling a peripheral portion of the bonded wafer; and after the beveling step, applying grinding and polishing to a back surface of the active layer wafer thereby making appear in the polished surface a plurality of dielectric separation silicon islands isolated by the dielectric separation oxide film; wherein in said bonding step, a transmission light, which may pass through the wafers, is used to detect a position of the pattern of the dielectric isolation grooves in the active layer wafer and a position of the orientation flat of the supporting substrate wafer, and based on the detected positions, the pattern of the dielectric isolation grooves of the active layer wafer and the orientation flat of the supporting substrate wafer are adjusted to fall in a certain physical relationship, and thereafter the bonding of the two wafers is carried out with the physical relationship held as adjusted.
A high temperature CVD method represents such a method in which a source gas containing silicon is introduced into a reactor together with a carrier gas (such as a H2 gas) to cause silicon, which has been generated by heat decomposition or reduction of the source gas, to be deposited on a heated silicon wafer. Typically a chemical compound containing silicon, such as SiCl2H2, SiHCl3 and SiCl4, is used therefor.
As for the reactor, for example, a pancake reactor or a cylinder reactor may also be employed.
The temperature used in growing of the high temperature polysilicon may be varied depending on the heating system employed in the reactor. In a vertical reactor, for example, which is most typically used in this application, preferably the temperature is within a range of 1200 to 1290xc2x0 C., more preferably within a range of 1230 to 1280xc2x0 C. At the temperature below 1200xc2x0 C., disadvantageously the silicon wafer is apt to be broken. On the other hand, the temperature higher than 1290xc2x0 C. disadvantageously may cause a slip, leading an irregular bowing or a breaking of the silicon wafer.
The polysilicon layer may be grown to be such thick that will be equal to a thickness defined by multiplying the depth of anisotropic etching required for forming the dielectric isolation grooves by 2 to 3 and further adding a thickness of the polysilicon layer desired to be left. The polysilicon layer not as 2 times thick as the depth of the applied anisotropic etching sometimes could not be sufficient to fill up the etching grooves. On the other hand, the polysilicon layer more than 3 times thicker leads to undesired growth, meaning it to be uneconomical.
The etchant to be used in this anisotropic etching may include KOH(IPA/KOH/H2O), KOH(KOH/H2O), and KOH(hydrazine/KOH/H2O). As for the anisotropic etching condition, a conventional condition may be applied thereto.
Generally applicable conditions may be employed in each process required for forming a window portion in a resist film lying on the top surface of the wafer for the anisotropic etching.
The transmission light as discussed above is not limited to but may be any light that can pass through respective wafers. For example, an infrared ray or an X-ray may be used. In the case where the silicon wafer is used, the infrared ray having a wave length of 1.1 microns (xcexcm) or longer may be used. For the wafer of GaAs, the infrared ray having the wave length of 0.9 xcexcm or longer may be used.
A transmission image of the active layer wafer and a transmission image of the supporting substrate wafer captured by the transmission light may be visually observed, for example, on a monitor screen. Consequently, an operation of placing those transmission images with one on the other can be executed on that monitor screen.
In the present invention as defined in claim 1, based on those transmission images, the pattern in the active layer wafer and the orientation flat of the supporting substrate wafer may be adjusted to fall in a certain physical relationship.
In this context, adjusting the pattern in the active layer wafer and the orientation flat of the supporting substrate wafer into a certain physical relationship means that, for example, an extending direction of the lateral grooves which are structural elements of the grid pattern is set to be parallel with the orientation flat of the supporting substrate wafer. Alternately, the grooves in the other direction (the longitudinal grooves) may be positioned to be orthogonal to the xe2x80x9cOFxe2x80x9d of the supporting substrate wafer.
The present invention as defined in claim 2 provides a method for producing a bonded dielectric separation wafer in accordance with claim 1, in which an extending direction of the dielectric isolation grooves on said active layer wafer is set to be parallel with the orientation flat of the supporting substrate wafer.
The present invention as defined in claim 3 provides a method for producing a bonded dielectric separation wafer in accordance with claim 1 or 2, in which the active layer wafer and the supporting substrate wafer are both silicon wafers and further an infrared ray is used as the transmission light.
The present invention as defined in claim 4 provides a method for producing a bonded dielectric separation wafer comprising the steps of: growing a polysilicon layer on a top surface of an active layer wafer which has dielectric isolation grooves in a predetermined pattern having formed therein with reference to an orientation flat thereof and has been covered with a dielectric separation oxide film; polishing a top surface of the polysilicon layer; fabricating a bonded wafer by bonding the polished surface of the active layer wafer to a surface of a supporting substrate wafer having an orientation flat; beveling a peripheral portion of the bonded wafer; and after the beveling step, applying grinding and polishing to a back surface of the active layer wafer thereby making appear in the polished surface a plurality of dielectric separation silicon islands isolated by the dielectric separation oxide film; wherein in said bonding step, a transmission light, which may pass through the wafers, is used to detect a position of the orientation flat of the active layer wafer and a position of the orientation flat of the supporting substrate wafer, and based on the detected positions, the two orientation flats are matched with each other, and thereafter the bonding of the active layer wafer and the supporting substrate wafer is carried out with the physical relationship therebetween held as matched.
The present invention as defined in claim 5 provides a method for producing a bonded dielectric separation wafer in accordance with claim 4, in which the active layer wafer and the supporting substrate wafer are both silicon wafers and further an infrared ray is used as the transmission light.
The present invention as defined in claim 6 provides an apparatus for bonding wafers, comprising: a first holding means for holding an active layer wafer; a second holding means for holding a supporting substrate wafer; a positioning means for determining proper positions for placing one upon another of the active layer wafer and the supporting substrate wafer held by the first and the second holding means, respectively; and a bonding means for bonding the active layer wafer to the supporting substrate wafer, after the positions for placing the wafers one upon another having been determined, wherein said positioning means has a transmission detecting section for detecting respective portions in respective wafers working as markers in placing the wafers one upon another based on a transmission image of the supporting substrate wafer and another transmission image of the active layer wafer, each image captured as a result of irradiation of a transmission light capable of passing through those wafers, and executes the positioning of the active layer wafer and the supporting substrate wafer for placing one upon another based on the detected result from the transmission detecting section.
As for the first and the second holding means, for example, a wafer retainer plate utilizing a vacuum chuck may be employed.
As for the bonding means, for example, such an apparatus that can move the active layer wafer and the supporting substrate wafer in directions so as for the bonding surfaces thereof to come closer to each other may be employed. At that time, only the active layer wafer may be moved. Or otherwise, only the supporting substrate wafer may be moved. Alternatively, both of the wafers may be moved.
The marker for the supporting substrate wafer and the marker for the active layer wafer, which are used for placing one wafer on the other wafer is not limited. For example, the maker for the former may be the pattern of the dielectric isolation grooves in the active layer wafer or the orientation flat of the active layer wafer. Further, the marker for the latter may be the orientation flat of the supporting substrate wafer.
If the transmission light is the infrared ray, the infrared ray irradiated from an infrared illumination source (the transmission light capable of passing through the wafer) can be observed by an infrared TV camera. As the infrared TV camera may be used an infrared ray vidicon camera tube sensitive to the wave length in a range up to 1.9 xcexcm. It is a matter of course that an image formed on the infrared TV camera may be made clearer to see with the aid of a contrast enhancing function, for example.
According to the present invention, after the polysilicon having grown, the peripheral region of the active layer wafer is beveled and then the bonding position of the active layer wafer with the supporting substrate wafer should be determined.
At that time, the transmission light is used to capture the transmission images of the active layer wafer and the supporting substrate wafer. From those two transmission images, the position of the marker (the pattern or the orientation flat) in the active layer wafer and the position of the marker (the orientation flat) in the supporting substrate wafer for placing wafers one upon another are detected, respectively, and then based on the respective detection results, the positions of the active layer wafer and the supporting substrate wafer are determined for placing one upon another. After the positioning having been determined, the both wafers are bonded to each other thus to fabricate the bonded wafer.
With this positioning completed, the auto-alignment of the bonded dielectric separation wafer with reference to the orientation flat of the supporting substrate wafer could be carried out in the processing steps (e.g., the exposing process) subsequent to the wafer bonding step.
The orientation flat for those wafers may be a main xe2x80x9cOFxe2x80x9d or a sub xe2x80x9cOFxe2x80x9d. The sub xe2x80x9cflatxe2x80x9d may be formed in a location at an angle of 90 or 45 degrees with respect to the main xe2x80x9cflatxe2x80x9d along the circumferential direction.
According to the present invention, since the positions of the active layer wafer and the supporting substrate wafer for placing one upon another are determined from the positions of the markers in the both wafers for placing one on another captured by irradiating the transmission light against them, therefore the auto-alignment of the bonded dielectric separation wafer can be carried out with reference to the orientation flat of the supporting substrate wafer in the steps subsequent to the wafer bonding step.
USPTO Backgrounds
USPTO Backgrounds