When circuit patterns, which are formed on chrome masks, are projected by reduction optics onto semiconductor wafers, the intensity of the zero diffraction order of the electromagnetic radiation, is used to form the structure on the semiconductor wafer. If, in general, the radiation dose of the first and of a higher diffraction order exceeds a limit value for the sensitization of the radiation-sensitive layer, then undesirable parasitic structures can be formed in the immediate vicinity of the structures, which are intended to be formed in the radiation-sensitive layer. These parasitic structures are also referred to as side lobes.
Side lobes virtually never occur in chrome masks because the intensity component in the zero diffraction order is large compared to those higher diffraction orders, and because the structure separations or grating periods of the circuit patterns are formed to be comparatively large. The interval between the diffraction orders is very small so that local maxima occur in the flanks of the resist profiles and are projected from the circuit pattern into the radiation-sensitive layer.
The circuit patterns, which are formed in a radiation-sensitive layer, are miniaturized by the use of phase masks. These result in steeper resist profiles and intensity profiles in the imaging plane. They have the intrinsic characteristic of having a greater proportion of the intensity of the light in higher diffraction orders. Due to miniaturization, their distance from a structure to be formed in the radiation-sensitive layer is greater than in the conventional case.
In particularly poor cases, diffraction maxima of a higher order of mutually adjacent structures may be superimposed on one another. This then increasingly leads to the formation of side lobes. If the radiation-sensitive layer, which has been exposed in this way, is developed, and the resultant resist structure is transferred to a layer, which represents a contact hole plane in memory products, then the formation of undesirable electrical connections and failure of the integrated circuit is possible.
This disadvantageous effect is assisted by possible drift in the wavelength of the projection light beam when it passes through different parts of the lens system of the projection optics, or of the phase mask.
If the structure of a layout pattern is transferred to a wafer by an x:1 reducing projection apparatus, side lobes may be created, for example, by pure edge diffraction as a result of discontinuous Fourier transformation, or as a result of the diffracted light being superimposed on the background radiation. The intensity of side lobes increases as the transmission increases, and, for coherent light, is described by:ISide-Lobe=|Emin|2=E2*(1.09*SQRT(T)+0.09)2 where T is the local transmission. For partial coherence, this side lobe intensity can be described by means of Lommel functions. ISide-Lobe for a phase mask (PSM) is in consequence greater than ISide-Lobe for a light/dark mask.
One particular problem with large scale integrated periodic circuit patterns is that side lobes are regularly mapped into the radiation-sensitive layer. Since side lobes occur regularly, side lobes are difficult to identify during subsequent inspection of the semiconductor wafer, particularly when no reference pattern with which the mapped circuit pattern can be compared is available for inspection. The regular arrangement of the side lobes gives the operator of the inspection equipment the impression that they represent a part of the circuit, and are thus part of the layout.
The problem of the occurrence of side lobes is identified in the back end, when functional tests of the completed circuits are carried out on the semiconductor wafer. However, the integrated circuits can no longer be repaired at this development stage, so that 50 to 100 wafer batches, each comprising 25 semiconductor wafers, for example, will often have been produced incorrectly with side lobes before the damage can be identified.
Until now, one approach has been to arrange the circuit patterns such that side lobes are deliberately used to form structures which themselves in turn represent part of the circuit pattern. However, this approach has not been found to be practicable, due to the difficulty in determining the tolerance limits for the parameters which can be used for projection, such as focus, radiation dose, numerical aperture, etc.
A known solution describes carrying out a computer simulation of the transfer of the circuit pattern to the radiation-sensitive layer. The simulation is carried out based on the electronically stored data (layout data), which represents the circuit pattern, and the projection apparatus parameters, which are set for the projection. The simulation result is used to identify positions in the electronically stored circuit pattern at which the side lobes are predicted to occur during projection under the stated conditions. The design of the electronically stored circuit pattern at the corresponding positions, and in the vicinity of these positions, is changed in a subsequent step to predict that side lobes will no longer occur. The mask with the changed circuit pattern is not produced until this stage, and is used for the actual projection onto a semiconductor wafer.
An analogous method for identification of side lobes and for correcting them can also be found, for example, on the Internet at:
http://www.mentor.com/dsm/techpapers/mentorpaper—2964.pdf.
The known methods, however, do not take account of large-volume manufacturing conditions. Typical large-volume manufacturing sites producing 10,000 to 50,000 or more wafer starts per month have a large number of exposure systems and projection apparatuses. Some of which differ not only in manufacturers or different technology generation, but also, even if the equipment type is identical, considerable discrepancies, for example, with respect to lens characterization or the radiation source. Each of the individual exposure systems has its own individual tolerances, which are dependent on manufacture, which, if exceeded make the formation of side lobes during projection probable. Even during the design stage of the circuit pattern, a single computer simulation cannot take account of these differences in the manufacturing conditions.
Taking into account manufacturing conditions, a method for wafer exposure which can avoid the occurrence of side lobes is desirable.
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