The present disclosure relates generally to computer aided testing of a circuit design, and more specifically to improving the performance of modeling a power consumption of the circuit design.
Integrated circuit (IC) designers commonly describe their designs in hardware description language (HDL) such as Verilog, VHDL, SystemC, and the like. In IC design, hardware emulation may refer to the process of replicating behavior of one or more pieces of hardware such as an initial circuit design, hereinafter also referred to as a design under test (DUT), with another piece of hardware, such as a special-purpose emulation system. An emulation model is usually generated in accordance with an HDL source code representing the design under test. The emulation model is compiled into a format used to program the emulation system that may include one or more field programmable gate array (FPGA). Thereby, the DUT is mapped by the compiler into the FPGA(s) of the emulation system. Running the emulation system as programmed with the emulation model enables debugging and functional verification of the DUT. Overall progress of the emulation is usually controlled by a master clock signal generated on the emulator hardware, which enables the emulation model to run on the emulation hardware at much higher speed than when simulating the DUT entirely in software. A DUT, such as for example an application specific IC (ASIC), may include a huge number of signals that makes simulating the DUT a challenge.
Currently, the power and current consumption profiling of a DUT is typically performed by extracting the waveforms of huge quantities of design signals from the simulation or emulation, then applying more software tools to compute the powers and currents based on the waveform data, which is time consuming and resource intensive. As a result, there may be poor coverage over long simulation cycles or corner cases within the constraints imposed by time-to-market. The resulting power design errors may incur high costs to redesign, re-manufacture, and/or recall and replace the products.
With recent technology advances, circuit designs include ever greater numbers of signals. Therefore, there is a need for accurately modeling the power consumption of a DUT, while reducing the amount of computer resources needed to perform the power consumption modeling.
USPTO Backgrounds
USPTO Backgrounds