The present disclosure relates to semiconductor structures, and more specifically, to field effect transistors.
Typical circuit components utilizing field effect transistors (FETs) utilize conductive contacts that overlap diffusion regions to conduct current to and from the FET. The size of these conductive contacts is often limited by lithographic constraints of the technology node in which the circuit is implemented and design constraints of the larger circuit into which the circuit component is implemented. The limited size of conductive contacts may increase the resistance across those contacts, limiting the performance of the circuit.
USPTO Backgrounds
USPTO Backgrounds