1. Introduction
This invention relates to new multilayered circuit boards and to processes for manufacture of the same. More particularly, the invention relates to new multilayered circuit boards having capacity for increased chip and other component attachment and further characterized by increased circuit density. The multilayered circuit boards are formed by new sequential build procedures.
2. Description of the Prior Art
Multilayer circuit boards (MLBs) permit formation of multiple circuits in a minimum volume or space. They typically comprise a stack of layers where layers of signal lines (conductors) are separated from each other by a layer of dielectric material. The signal lines are in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias”. Such stacks also typically contain power and ground planes.
Known processes for fabricating MLBs are extensions of methods used for fabricating double-sided circuit boards. A typical method comprises fabrication of separate innerlayer circuits. The circuits are formed by coating a photosensitive layer or film over the copper of a copper clad innerlayer base material. The photosensitive coating is imaged, developed and etched to form conductor lines. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the innerlayer base material.
Following formation of individual innerlayer circuits, a multilayer stack is formed by preparing a lay-up of innerlayers, ground planes, power planes, etc., typically separated from each other by a dielectric pre-preg comprising a layer consisting of glass cloth impregnated with partially cured material, typically a B-stage epoxy resin. The top and bottom outer layers of the stack comprise copper clad, glass filled, epoxy planar boards with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed has copper cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the innerlayer circuits, A photosensitive film is applied to the copper cladding. The coating is exposed to patterned activating radiation and developed. An etchant is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers.
Vias or interconnects are used to electrically connect individual circuit layers within an MLB to each other and to the outer surfaces and typically pass through all or a portion of the stack. Vias are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pretreatment steps, the walls of the vias are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electroless copper plating solution to form conductive pathways between circuit layers. Following formation of the vias, exterior circuits, or outerlayers are formed using the procedure described above.
To construct an electronic device using an MLB, chips and other electrical components are mounted at appropriate locations on the exterior circuit layers of the multilayer stack, typically using solder mount pads to bond the components to the MLB. The components are in electrical contact with the circuits within the MLB through the conductive vias. The pads are formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the board and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using procedures known to the art such as wave soldering.
The uses, advantages and fabrication techniques for the manufacture of multilayer boards are described by Coombs, Printed Circuits Handbook, McGraw Hill Book Company, New York, 2nd Edition, pp. 20-3-23-19, 1979, incorporated herein by reference.
MLBs have become increasingly complex. For example, boards for main frame computers may have as many as 36 layers of circuitry or more, with the complete stack having a thickness of about ¼ inch. These boards are typically designed with 4 or 5 mil wide signal lines and 12 mil diameter vias. For increased densification, the industry desires to reduce signal lines to a width of 2 mils or less and vias to a diameter of 2 to 5 mils or less. Known commercial procedures now used are incapable of economically forming the dimensions desired by the industry.
In addition to decreasing line width and via diameter, the industry also desires to avoid manufacturing problems frequently associated with MLB manufacture. As described above, current procedures utilize innerlayer materials that are glass-reinforced resin layers having a thickness of from about 4 to 5 mils clad with copper on both surfaces. The glass reinforcing material is used to contribute strength and rigidity to the MLB stack. However, since lamination is at a temperature above 150° C., the resinous portion of the laminate shrinks during cooling to the extent permitted by the rigid copper cladding. If the copper is etched to form a discontinuous pattern, laminate shrinkage may not be restrained by the copper cladding. This problem is exacerbated as feature size decreases. Consequently, further shrinkage may occur. The shrinkage may have an adverse affect on dimensional stability and registration between board layers.
As described above, to form the MLB, a first step involves lay-up of layers prior to lamination. Care must be exercised to avoid shifting of the innerlayers during lamination. Otherwise, the layers will not be aligned and electrical contact between layers will not be achieved. In addition, during lay-up, air is often trapped in spaces adjacent to signal lines because a solid pre-preg is laid over the signal lines that does not completely fill all recesses between signal lines. Care must be taken to evacuate entrapped air. Residual air pockets can cause defects and subsequent problems during use of the multilayer board.
The use of glass reinforced inner and outerlayer materials creates additional problems. The glass fiber is needed for board strength. However, when holes are drilled to form vias, glass fibers extend into the holes and must be removed prior to metallization. Removal creates the need for additional pretreatment steps such as the use of glass etchants to remove glass fibrils extending into the holes. If the glass is not removed, a loss of continuity might occur in the metal deposit. In addition, the glass fibers add weight and thickness to the overall MLB.
The attachment of chips and other electrical components to a finished MLB adds additional, costly processing steps to the overall fabrication of an electronic device. Solder mask must be applied and imaged after the MLB is completed. The solder mask is screened onto a board through a screen or applied as a coating and then imaged. Solder is then applied such as by floating the board on a bath of molten solder. The elevated temperatures cause differential expansion of layers within the board resulting in undesirable pressures within the MLB.
An improvement in methods for manufacture of MLBs is disclosed in U.S. Pat. No. 5,246,817 incorporated herein by reference, hereafter the “'817 patent”. In accordance with the procedures of the '817 patent, manufacture of the MLB comprises sequential formation of layers using photosensitive dielectric coatings and selective metal deposition procedures. In accordance with the process of the patent, the first layer of the board is formed over a temporary or permanent carrier that may become an integral part of the board. When the carrier is a circuit, the process comprises formation of a dielectric coating over the circuit with imaged openings defining the vias. The imaged openings may be obtained by exposure of a photosensitive dielectric coating to activating radiation through a mask in an imaged pattern followed by development to form the imaged openings. Alternatively, imaging may be by laser ablation in which case the dielectric material need not be photosensitive. Metal is deposited into the recesses within the dielectric coating to form vias. Thereafter, an additional layer of dielectric is coated onto the first dielectric layer, imaged in a pattern of circuit lines, and the recesses are then plated with metal. Alternatively, after imaging the first dielectric coating, it may be coated with a second dielectric coating and imaged and the recesses plated with metal to form the vias and circuit lines simultaneously. By either process, the walls of the imaged opening or recesses in the dielectric coating contain metal as it deposits during plating and assures a desired cross-sectional shape of the deposit. Plating desirably fills the entire recess within the imaged photosensitive coating. The process is repeated sequentially to form sequential layers of circuits and vias.
The procedures disclosed in the '817 patent include alternative selective metal plating methods whereby metal is selectively deposited within the imaged openings to render the same conductive. The procedures disclosed in the patent involves selectively depositing metal in imaged openings without increase in the surface resistivity of an underlying substrate between conductor lines. Selective metal deposition may be performed by several new techniques disclosed in said patent to avoid increased conductivity between signal lines. The selective deposition procedures of the '817 patent typically involve multiple coating steps using sacrificial layers.
The process of the '817 patent is an advance in the art. For example, to obtain imaged openings in a dielectric coating, the coating is exposed to activating radiation in an image pattern and developed or laser ablated in a pattern to yield a relief image. The resolution of the imaged openings is dependent upon the imaging process and materials used. Photosensitive dielectric coatings may be capable of development to yield high resolution relief images including openings that are smaller than the thickness of the coating. By use of such coatings, imaged openings for vias and conductors can be of a size equivalent to the resolution capability of the dielectric material and the method of imaging. Accordingly, the cross section or configuration of a feature may be in any desired shape with a dimension far smaller than obtainable using prior art procedures. In addition, the MLBs are made without use of glass reinforced epoxy innerlayer materials. Therefore, the final MLB is free of the glass reinforcement conventionally used in the fabrication of MLBs. This is an advantage as it eliminates many problems associated with conventional MLB manufacture. For example, problems and preparative steps associated with glass fibers extending into via openings during metallization are avoided. Without the glass reinforced innerlayer material, the overall thickness of the stack is reduced. Registration problems encountered during lay-up of the stack are eliminated. Shrinkage caused by thermal cure of the B stage epoxy resin in the conventional process is avoided because a thermal cure step is not required by the process of the '817 patent.
Though the process of the '817 avoids many of the problems noted above, it would be desirable to further simplify the process, especially by avoidance of electroless metal deposition procedures to form circuit lines and vias, multiple coating steps to enable selective plating, and use of molten solder to form solder mount pads.
USPTO Backgrounds
USPTO Backgrounds