1. Field of the Invention
The present invention relates to a through-hole interconnection structure for a semiconductor wafer. More particularly, the present invention relates to a through-hole interconnection structure for a semiconductor wafer used in a semiconductor device which includes plural wafers stacked together.
2. Background Art
A three-dimensional semiconductor integrated circuit device has been known which includes two or more wafers stacked together and electrically connected via buried wiring. For example, Japanese Unexamined Patent Application, First Publication No. 2007-59769 discloses a semiconductor device in which a desired semiconductor circuit is provided by bonding plural substrates together and electrically connecting semiconductor circuit sections formed on each substrate. In the semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-59769, a semiconductor circuit section of an upper substrate and a semiconductor circuit section of a lower substrate are bonded and electrically connected to each other with a through-hole interconnecting section exposed from a back surface of the upper substrate and a bump on a principal surface of the lower substrate being in contact.
That is, in a conventional semiconductor device which includes plural wafers bonded together, the wafers are electrically connected to each other via an electrical signal connecting section such as a through-hole interconnecting section and a bump which protrudes from a bonding surface. In particular, in the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-59769, the upper and lower substrates are electrically connected via a through-hole interconnecting section protruding from the back surface of the upper substrate and a bump protruding from the principal surface of the lower substrate.
In this case, however, in which plural wafers are electrically connected via the electrical signal connecting section protruding from the bonding surface, the electrical signal connecting section may be damaged at the time of wafer bonding. Damages to the electrical signal connecting section may cause deterioration in electrical conduction property and stability in the electrical signal connecting section or may cause deterioration in stability in dynamic characteristics of the semiconductor device. Thus, a semiconductor device with stable performance cannot often be obtained.
In view of the aforementioned, an object of the present invention is to provide a through-hole interconnection structure of a semiconductor wafer which has sufficient rigidity to withstand load it receives at the time of wafer bonding, in which electrical signal connecting section protruding from the bonding surface is less easily damaged, and is excellent in reliability and stability of performance.
USPTO Backgrounds
USPTO Backgrounds