Embodiments relate to a semiconductor device and a method of fabricating the same, and more particularly, to technology for forming a metal contact having a small size as a program gate of an antifuse.
In recent years, with rapid spread of information media such as computers, semiconductor devices have developed dramatically. In the terms of function, the semiconductor devices may desirably exhibit high speed operation and large storage capacity. Thus, technology for fabricating semiconductor devices has been developed to improve a degree of integration, reliability, and a response speed.
Methods of fabricating the semiconductor devices typically include a fabrication (FAB) process which forms cells having integration circuits, by repeatedly forming preset circuit patterns on a substrate formed of a silicon material. An assembly process packages the substrate in which the cells are formed, in chip-sized units. An electrical die sorting (EDS) process for inspecting electrical characteristics of the cells formed on the substrate, is performed between the FAB process and the assembly process.
The EDS process is a process for determining whether or not the cells formed on the substrate, are in an electrically operational state or in a failed state. The failed cells are removed through the EDS process before performing the assembly process, so that an effort and cost for the assembly process can be saved. Further, the failed cells can be found in advance and repaired through a repair process.
Hereinafter, the repair process will be described in detail.
To improve device yield when defects occur in the semiconductor device fabrication process, redundancy cells configured to replace defected elements or circuits are added. A fuse configured to connect the redundancy cells to an integrated circuit is designed in device design. The location information of cells to be repaired is generated by cutting only specific fuses.
However even when the repair process for repairing defective cells at the wafer level is performed, after a package process 1-bit or 2-bit defects can still occur in the chips which have been not failed in the wafer level. This can lead to a defect rate of about 10% occurring. Therefore, introduction of the repair process after the package process is desirable.
Multi-chip packages may include a plurality of packaged chips. Since a relatively high-priced flash device as well as a dynamic random access memory (DRAM) can be rendered unusable by the 1-bit or 2-bit defect, the introduction of the repair process after the package process is desirable.
However, since the laser repair equipment cannot be used after the package process, a fuse configuration different from that used in the repair process before packaging, is desirable.
Hereinafter, the fuse type used in the repair process after the package process will be described.
The fuse used after the package process is generally referred to as an antifuse. This is because the repair is performed not by cutting the fuse used after the packaging, but instead by a mutual connection of the fuse while the repair is performed by cutting the fuse before the packaging. That is, the antifuse has as meaning relative to the fuse before packaging, and the antifuse is a fuse which is electrically opened in a normal state and short-circuited when an insulator between conductors is broken by voltage application if necessary. The antifuse may be formed in a peripheral circuit area and is typically formed of a static random access memory (SRAM) of a non-refresh type.
The antifuse allows repair at the package level, and may be widely used to increase the net die throughput, improve product characteristics, and overcome the dependence on equipment and a process of the existing laser fuse according to high integration.
Therefore, it is desirable to successfully rupture the antifuse and to ensure reliability.
Further, as the density of a DRAM is increased, the number of fuses required is increased, and thus the overall fuse area size is increased and the net die is reduced.
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