1. Field of the Invention
The present invention relates to various apparatus for electrically calculating estimated interconnect delay values in a semiconductor integrated circuit. More particularly, the present invention is widely applicable to previously calculate delay times resulting from interconnect wires for connection between macro cells when a semiconductor integrated circuit including a plurality of macro cells is designed.
The present invention also relates to both software technology used for the apparatus and a medium for storing data necessary to the operation of the apparatus.
2. Description of the Background Art
In the past, only a delay time Tgate of a signal generated in macro cells has been determined and set as an estimated delay value TPD when a semiconductor integrated circuit is designed. An example of such processing is disclosed in Japanese Patent Application Laid-Open No. 8-30648 (1996).
However, the calculation of only the cell delay of the device causes a significant difference between the estimated delay value and an actual delay value provided in the semiconductor integrated circuit. Recently, there has been a shift toward the design technique of calculating an estimated interconnect delay Tline as well as the cell delay Tgate to provide the sum of the estimated interconnect delay Tline and the cell delay Tgate as the estimated delay value TPD (=Tgate+Tline).
Unfortunately, paths and branches of interconnect wires for connecting macro cells and the number of interconnect wires are various and complicated depending upon design. It is hence necessary to set circuit models for calculation of the estimated interconnect delay value Tline. Two circuit models to be described below have been considered.
(Background Art 1)
One of the two circuit models is a circuit model known as "Worst-Case RC Tree" disclosed in the on-line manual (Ver. 3.4a), Library Compiler Reference, Synopsys, U.S.A., Vol. 1, pp.4.9-4.12.
FIG. 16 illustrates such a circuit model. The circuit model of FIG. 16 includes macro cells connected to the extreme end of an interconnect wire and has no interconnect wire branch. In FIG. 16, the reference character Rw designates the total estimated resistance of the interconnect wire; Cw designates the total estimated capacitance of the interconnect wire; Cp designates the sum of pin capacitances of the macro cells to which the interconnect wire is connected. In this circuit model, the estimated interconnect delay value Tline is given by calculation using a delay calculation expression=Rw (Cw+Cp).
FIG. 17 is a functional block diagram of an interconnect delay calculation apparatus for calculating the estimated interconnect delay value Tline on the basis of the circuit model of FIG. 16. In FIG. 17, the reference numeral 1 designates a circuit diagram file for storing data of information (fan-out and the like) of a circuit to be designed when the circuit model illustrated in FIG. 16 is used; and 2 designates a coefficient file portion for filing a coefficient required to calculate an estimated wiring capacitance as a table value. The coefficient file portion 2 contains (1) a wiring resistance per unit interconnect wire length, (2) a wiring capacitance per unit interconnect wire length, and (3) an estimated interconnect wire length for each fan-out, all of which are written therein. For calculation of the estimated interconnect wire length using a linear expression, a coefficient of the linear expression may be set in the coefficient file portion 2 in place of the estimated interconnect wire length for each fan-out.
The reference numeral 3 designates a portion for extracting the pin capacitance of the macro cell to which the interconnect wire is connected; the reference character 3A designates a file portion for storing the respective pin capacitances of a plurality of types of macro cells as a library; 4 designates a portion for calculating the sum of the pin capacitances extracted by the extracting portion 3; 5 designates a portion for extracting the fan-out of the interconnect wire; 6 designates a portion for extracting the coefficient required to calculate the estimated wiring capacitance from the coefficient file portion 2; 7 designates a portion for calculating the estimated wiring capacitance on the basis of the coefficient extracted by the extracting portion 6; 8 designates a portion for extracting a coefficient required to calculate an estimated wiring resistance from the coefficient file portion 2; 9 designates a portion for calculating the estimated wiring resistance on the basis of the coefficient extracted by the extracting portion 8; 10 designates a portion for calculating the estimated interconnect delay value on the basis of the above described delay calculation expression by using the calculated sum of the pin capacitances, the calculated estimated wiring capacitance, and the calculated estimated wiring resistance; and 11 designates an output file portion for storing the calculated estimated interconnect delay value therein. A memory may be used in place of the output file portion 11 to store the estimated interconnect delay value therein.
FIG. 18 is a flow chart illustrating the operation of the interconnect delay calculation apparatus shown in FIG. 17. In FIG. 18 is illustrated the procedure of calculating the estimated delay value of each interconnect wire when the estimated interconnect wire length for each fan-out is set in the coefficient file portion 2.
The calculation procedure comprises extracting the pin capacitance of the macro cell to which the interconnect wire is connected, calculating the sum Cp of the extracted pin capacitances, extracting a fan-out, extracting the estimated interconnect wire length from the coefficient file portion 2 on the basis of the extracted fan-out, extracting the capacitance per unit interconnect wire length, extracting the resistance per unit interconnect wire length, calculating the estimated wiring capacitance Cw from the estimated interconnect wire length and the capacitance per unit interconnect wire length, calculating the estimated wiring resistance Rw from the estimated interconnect wire length and the resistance per unit interconnect wire length, and calculating the estimated delay value of each interconnect wire by the delay calculation expression=Rw (Cw+Cp) using the sum Cp of the pin capacitances, the estimated wiring capacitance Cw and the estimated wiring resistance Rw.
The construction and operation of the interconnect delay calculation apparatus shown in FIGS. 17 and 18 and an interconnect delay calculation apparatus shown in FIGS. 20 and 21 to be described later are considered as being not known in the art.
(Background Art 2)
The second circuit model is known as "Balanced-Case RC Tree" also disclosed in the above described on-line manual. Such a circuit model is shown in FIG. 19. In the circuit model of FIG. 19, it is assumed that only interconnect wire branches are provided between macro cells.
In FIG. 19, the reference character n designates a fan-out; Rw designates the total estimated resistance of the interconnect wire; Cw designates the total estimated capacitance of the interconnect wire; and Cp designates the sum of the pin capacitances of the macro cells to which the interconnect wire is connected. In the circuit model of FIG. 19, the estimated interconnect delay value Tline is given by calculation using a delay calculation expression=(1/n.sup.2) Rw (Cw+Cp).
FIG. 20 is a functional block diagram of an interconnect delay calculation apparatus for calculating the estimated interconnect delay values using the circuit model of FIG. 19. In FIG. 20, the reference numeral 12 designates a circuit diagram file portion for holding data about circuit diagram information (fan-out and the like) when the circuit model shown in FIG. 19 is applied to the interconnect line between macro cells for a circuit to be actually designed; and 13 designates a coefficient file portion. The coefficient file portion 13 contains (1) a wiring resistance per unit interconnect wire length, (2) a wiring capacitance per unit interconnect wire length, and (3) an estimated interconnect line length for each fan-out, all of which are written therein. For calculation of the estimated interconnect wire length using a linear expression, a coefficient of the linear expression may be set in the coefficient file portion 13 in place of the estimated interconnect wire length for each fan-out. The reference numeral 14 designates a portion for extracting the pin capacitance of the macro cell to which the interconnect wire is connected; 15 designates a portion for calculating the sum Cp of the pin capacitances extracted by the extracting portion 14; 16 designates a portion for extracting the fan-out n of the interconnect wire; 17 designates a portion for extracting the coefficient required to calculate the estimated wiring capacitance; 18 designates a portion for calculating the estimated wiring capacitance Cw on the basis of the coefficient extracted by the extracting portion 17; 19 designates a portion for extracting the coefficient required to calculate the estimated wiring resistance; 20 designates a portion for calculating the estimated wiring resistance Rw on the basis of the coefficient extracted by the extracting portion 19; 21 designates a portion for calculating the estimated interconnect delay value Tline from the sum Cp of the pin capacitances, the estimated wiring capacitance Cw, and the estimated wiring resistance Rw on the basis of the above described calculation expression; and 22 designates an output file portion for storing the estimated interconnect delay value therein. Of course, a memory may be used in place of the output file portion 22.
FIG. 21 is a flow chart illustrating the operation of the interconnect delay calculation apparatus shown in FIG. 20. The calculation procedure comprises extracting the pin capacitance of the macro cell to which the interconnect wire is connected, calculating the sum Cp of the extracted pin capacitances, extracting the fun-out n, extracting the estimated interconnect wire length from the coefficient file portion 13 on the basis of the extracted fan-out n, extracting the capacitance per unit interconnect wire length, extracting the resistance per unit interconnect wire length, calculating the estimated wiring capacitance Cw from the estimated interconnect wire length and the capacitance per unit interconnect wire length, calculating the estimated wiring resistance Rw from the estimated interconnect wire length and the resistance per unit interconnect wire length, and calculating the estimated delay value of each interconnect wire by the above described delay calculation expression=(1/n.sup.2) Rw (Cw+Cp) using the sum Cp of the pin capacitances, the estimated wiring capacitance Cw, the estimated wiring resistance Rw, and the fan-out n.
In the conventional art circuit models, it is assumed that the interconnect wire between the macro cells has no interconnect wire branches as shown in FIG. 16 and that the interconnect wire between the macro cells is comprised of only interconnect wire branches as shown in FIG. 19. Calculation of the estimated interconnect delay values using such circuit models which are poles apart results in very low accuracy of the estimated interconnect delay values.
More specifically, the circuit model of "Worst Case RC Tree" presents a pronounced problem in that the estimated interconnect delay value calculated using the model during the design is constantly much greater than the interconnect delay value determined from the actually manufactured circuit. This problem may be expressed in different words that a great design margin is set in the circuit model of FIG. 16. Such a design margin is advantageous when the operating rate of the circuit is relatively low. However, the circuit model having an excessive design margin yields undesired results in the design technique of semiconductor integrated circuits under the recent tendency toward higher and higher operating rates of the circuit. That is, the increase in interconnect delay time for each interconnect wire length set using the circuit model of Background Art 1 finally results in the unsatisfactory specs of the whole semiconductor integrated circuit. In this case, the user must extract suitable portions of the designed interconnect wires to re-design the portions so that the specs of the whole semiconductor integrated circuit are completely satisfactory, resulting in an inefficient and complicated process for designing the circuit.
On the other hand, the circuit model of "Balanced-Case RC Tree" depicted in FIG. 19 presents a problem in that the interconnect delay value calculated using the circuit model is constantly less than the actual delay value. If the estimated interconnect delay value of each interconnect wire length set using the circuit model of FIG. 19 satisfies the specs during the design phase, the actual products do not satisfy the specs, and the semiconductor integrated circuit fails to operate. Thus, the design using the circuit model of FIG. 19 poses a significant risk. This problem is considered to result from the passive design principle of considering the interconnect delay for the time being for design as a result of the interconnect delay value which has been regarded as zero but becomes non-negligible with the size reduction of the interconnect wires.
USPTO Backgrounds
USPTO Backgrounds