1. Field of the Invention
The present invention relates to a duty cycle correction device used for a semiconductor memory chip. More particularly, the present invention relates to a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) circuit by using a phase mixer.
2. Description of the Prior Art
As generally known in the art, a DLL circuit is a clock generation device, which is accommodated in a synchronous memory device so as to compensate for skew between an external clock and an internal clock. Synchronous memory devices, such as DDR, DDR2, etc., control the timing for input/output operations in synchronization with an internal clock output from a DLL circuit. In the case of these synchronous memory devices, since data are input/output in synchronization with the rising and falling edges of an external clock, it is preferred if the duty cycle of an internal clock output from a DLL circuit is set as 50%. In order to adjust the duty cycle of an internal clock output from the DLL circuit to a level of approximately 50%, a duty cycle correction (DCC) device employing a delay circuit or the like is typically used.
However, the conventional DCC device, which employs the delay circuit or the like in order to adjust the duty cycle of an internal clock output from a DLL circuit, has a problem in that the correcting ability for the duty cycle is very poor.
USPTO Backgrounds
USPTO Backgrounds