On-chip clocking circuits are ubiquitous in electronic devices for timing, data, logic, and memory in synchronous systems. A clock network requires repetitive energization and de-energization of circuit nodes between logical “zero” and “one” states. This switching between states leads to wasteful power consumption and/or heating. This heating often limits the performance of these circuits and of commercial and non-commercial devices and systems that are made from these circuits.
Approaches have been developed in attempts to reduce clock system heating. These methods include non-resonant and resonant strategies. Other methods for increasing energy efficiency, such as dynamic voltage and frequency scaling (DVFS), and adiabatic charging and discharging, have been demonstrated. These methods reduce heating but cannot be used concurrently at GHz speeds. For example, DVFS can save average energy over extended use, but the method ultimately wastes energy every time an output goes from “one” to “zero” states.
USPTO Backgrounds
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