Phase locked loop (PLL) circuits can be utilized in a wide variety of applications, including timing applications for integrated circuits. A typical PLL can include a phase detector that determines a phase difference between a received signal and a feedback signal, a loop filter that can derive a control voltage from the phase difference indicated by the phase detector, and a voltage controlled oscillator (VCO) that can generate a feedback signal having an oscillation frequency corresponding to the control voltage. In some arrangements, the VCO output signal may be frequency divided before being returned to the phase detector.
A VCO can take many forms. In one particular configuration, a VCO can utilize a “ring” oscillator. A ring oscillator can include a number of delay stages (i.e. cells) configured in series and fed back to form a ring. Typically, a ring oscillator includes an odd number or inverting stages. In this way, a signal propagating through the ring can be inverted by such stages and the negative feedback feature of having an odd number of stages generates an oscillation. In a VCO application, a delay introduced by each stage can be established according to a control voltage to thereby generate an oscillation based on the control voltage.
In many applications, a VCO can be the most critical portion of a PLL. For example, in some applications it may be desirable for a PLL circuit to have a wide input/output frequency range without having to adjust/include divider circuits. In such a case, a VCO response can limit the range over which a PLL can operate.
A conventional delay cell of a VCO is set forth in FIG. 6 and designated by the general reference character 600. Conventional VCO delay cell 600 can include a differential stage 602 and a cross-coupled stage 604. Conventional VCO delay cell 600 receives a differential input voltage (ip and in) and provides a differential output voltage (outp and outn).
Differential stage 602 can include transistors (M1 and M2) that form a differential pair, a resistor-capacitor load (RL and CL), and a variable current source 606. Transistors (M1 and M2) receive differential input voltage (ip and in) at respective gate terminals. Transistor M1 has a drain connected to the first differential output node outp and a source commonly connected to the source of transistor M2. Transistor M2 has a drain connected to the second differential output node outn. A resistor-capacitor load (RL and CL) is connected to each differential output node (outn and outp). Variable current source 606 is connected between the common source node of transistors (M1 and M2) and a ground.
Differential stage draws a current shown as current I0. Current I0 is the combined current through transistors (M1 and M2).
Variable current source 606 includes a constant current component that draws a current (2I) and a variable current component that provides a current (I/2−Ivc, where Ivc is a voltage controlled current).
Cross-coupled stage 604 can include cross-coupled transistors (M3 and M4) and variable current source 608. Transistor M3 has a drain connected to differential output node outp, a gate connected to differential output node outn, and a source commonly connected to a source of transistor M3. Transistor M4 has a drain connected to differential output node outn and a gate connected to differential output node outp. Variable current source 608 is connected between commonly connected sources of transistors (M3 and M4) and a ground.
Cross-coupled stage draws a current shown as current I1. Current I1 is the combined current through transistors (M3 and M4).
Variable current source 608 includes a constant current component that draws a current (I) and a variable current component that provides a current (I/2+Ivc, where Ivc is a voltage controlled current).
In a conventional VCO employing a conventional VCO delay cell 600 as illustrated in FIG. 6, an output frequency can be proportional to 1/(RL*CL), where RL is the resistance value of load resistor RL and CL is the capacitance value of load capacitor CL, and currents I0/I1 at a fixed control voltage Vc. The current Ivc can be proportional to a control voltage Vc in a range of −I/2 to I/2.
In the conventional case shown, at a maximum frequency, a current Ivc=I/2, and essentially all current drawn can be through the differential pair (M1 and M2) of differential stage 602 and essentially no current is drawn through cross-coupled pair (M3 and M4) of cross-coupled stage 604 (i.e., I0=2I and I1=0). At a minimum frequency, current Ivc=−I/2, and essentially equal current can flow through both differential pair (M1 and M2) of differential stage 602 and cross-coupled pair (M3 and M4) of cross-coupled stage 604 (i.e., I0=I1=1).
A drawback to conventional VCO delay cell 600 is that the tuning range (range of frequencies at which a lock can occur) can be limited unless post VCO voltage dividers are adjusted. In particular, a lower frequency range may be limited. If a ratio between current (I0) sourced by differential pair (M1 and M2) and current (I1) sourced by cross-coupled pair (M3 and M4) falls below one, a ring oscillator may cease oscillating.
In light of the above, it would be desirable to provide a VCO delay cell that may be employed in a ring type oscillator that can provide a wider frequency tuning range than a conventional VCO delay cell.
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