A variety of semiconductor devices use strained-layer quantum well structures to achieve high-performance field effect transistors (also called SQWET's). In this class of devices, the buried quantum well serves as a spatially confined conduction path for source-drain current which may then be modulated by a gate voltage applied above the quantum well. The purpose for introducing strain into the quantum well is to optimize the device's performance by increasing carrier concentration and by reducing the effective mass of the active carriers. Unfortunately, as strain is increased in the quantum well layer, the stability of the quantum well against the introduction of misfit dislocations is reduced. Such dislocations cause serious degradation in the device's performance by providing centers for carrier recombination.
When a material is grown on a chemically similar but lattice mismatched substrate, a coherently strained layer may be formed if the lattice mismatch is sufficiently small. The lattice structure in such a coherent arrangement undergoes biaxial strains which force the lattice parameters perpendicular to the direction of growth, to become equal. As a result, a coherent structure with a homogeneous strain energy results. By contrast, in an incoherent structure, the mismatched strain is accommodated by a combination of biaxial strain and interfacial misfit dislocations. Obviously, in active devices, it is generally preferred that such dislocations be avoided.
In the prior art, when p-channel SQEFET's were fabricated the devices often showed poor performance as well as direct signs of structural degradation, such as misfit dislocations and poor photoluminescence efficiency. The implication was that the structures were meta-stable, rather than stable and that high temperature annealing, which was needed to activate ion-implanted dopants in the p-channel devices, provided conditions under which a large amount of structural relaxation had occurred.
In addition to assuring that strained quantum well devices exhibit stable strained layers, the need for electrical isolation of neighboring devices often produces a surface structure with complex morphology. Such a surface can present a significant limitation on the complexity and/or the further processing of the completed circuit. As a result, it is generally desirable, following a given series of processing steps, to restore a flat surface in order to simplify further processing steps. This procedure is called planarization.
The prior art has accomplished both buried features and planarization in a number of ways. U.S. Pat. Nos. 4,654,090 to Burnham et al., 4,771,010 to Epler et al., and 4,751,194 to Cibert et al. all describe methods for patterning a semiconductor heterostructure by disordering, (i.e. locally converting the original structure into a disordered alloy). In U.S. Pat. No. 4,751,194, ion implantation is employed for disordering; laser heating is employed in No. 4,654,090 and an "energy beam" is employed in No. 4,771,010. The regions of disordered alloy then confine transport electrons by presenting a different gap energy.
In U.S. Pat. Nos. 4,585,491 and 4,727,555, both to Burnham et al., tuning of the wavelength of quantum-well lasers is described through the use of thermal annealing. Such annealing drives interdiffusion between the quantum well and the surrounding material. These patents teach a diffusive process which takes place without any spatial patterning.
In U.S. Pat. Nos. 4,571,486 to Arai et al. and 4,605,447 to Brotherton et al. descriptions are provided of methods for selectively processing specific areas on a substrate, either for insulating a given region from the effect of a plasma, or by locally altering the reflectivity of a surface so that flashlamp heating produces different temperatures on selected regions.
In U.S. Pat. Nos. 4,835,116 to Lee et al. and 4,876,219 to Eshita et al., post-growth annealing is described to obtain a desired semiconductor structure. There is no teaching in these patents of any method for differentially annealing different regions of the semiconductor structures, nor are stability properties of strained-layer materials essential features of their described methods.
In two additional patents, No. 4,806,996 to Lauryi and No. 4,876,210 to Barnett et al., the notion of introducing special patterns into a material to obtain a final structure, not otherwise accessible, is described. In Luryi, a patterned substrate is described as providing dislocation-free epitaxial layers, whereas in Barnett et al., a lattice-graded interface layer is included between a substrate and a heteroepitaxial layer.
Accordingly, it is an object of this invention to provide a method for patterning subsurface features in a semiconductor substrate.
It is a further object of this invention to provide a subsurface patterning method wherein a planar surface morphology can be retained.
USPTO Backgrounds
USPTO Backgrounds