1. Field of the Invention
The present invention relates to integrated injection logic, a circuit technique implemented with bipolar transistors fabricated by conventional integrated circuit processes. The invention relates to the topology or physical arrangement of the circuit features on the integrated circuit including the disposition of the individual transistor regions, the internal current paths, and the external contacts. A novel topology is shown which improves the uniformity of electrical response in individual circuit units and in collections of such circuit units.
2. Description of the Prior Art
Integrated injection logic (I.sup.2 L) has been described in the literature, as for instance Hart, C. M. and Slob, A., "Integrated Injection Logic--A New Approach to LSI", 1972 IEEE International Solid State Circuits Conference Digest of Technical Papers, pp 92-93, and Berger, H. H. and Wiedmann, S. K., "Merged Transistor Logic--A Low Cost Bipolar Logic Concept", 1972 ISSCC Digest of Technical Papers, pp 90-91. In addition, certain practical devices using the I.sup.2 L technique have been marketed by at least two major semiconductor manufacturers.
The technique has several attractive features. One desirable feature of the technique is that the speed power product is very small, being demonstrated at less than 1.0 picojoules. This figure is an order of magnitude better than most conventional techniques including "CMOS", "Schottky-TTL", TTL", "ECL", etc. In addition to its excellent speed power product, it seems to have the potential of achieving radiation hardness compatible with a majority of severe applications. In addition, because it can use conventional linear bipolar devices, the fabrication processes are conventional and manufacturing costs are relatively inexpensive.
Integrated injection logic is based on the idea of operating conventional integrated bipolar transistors in an inverted mode. In I.sup.2 L logic, NPN transistors which consist of successively stacked horizontal layers have their emitter layer lowermost, the base layer above the emitter, and the collector layer topmost, usually in separate islands within the base. The resultant multiple collector device is compact and, when supplied with an appropriate base biasing current source or "injector", constitutes a basic "NOR" type gate building block. The "NOR" function results when the collectors of different multiple collector devices are connected together. The current source used to bias the base of the I.sup.2 L multi-collector NPN transistors can be realized in many ways. The most popular I.sup.2 L configuration uses a lateral PNP transistor as the base biasing source. A less popular configuration uses a vertical PNP injector arranged beneath the NPNs.
In practical devices utilizing both arrangements, there is a general variation in the response of individual collectors.
USPTO Backgrounds
USPTO Backgrounds