The present invention relates to capacitors and in particular to circuit arrangements having capacitors with higher packing density.
With a view to faster and faster components with higher integration densities, the structural sizes of integrated circuit arrangements decrease from generation to generation. For capacitors as components, problems occur as packing density increases because reducing the dimensions of a capacitor reduces the surface area of the capacitor electrodes. As a result, the capacity of the capacitor is diminished.
To solve this problem, capacitor dielectrics with high dielectric constants were developed. Such dielectrics effect a large capacity despite a small surface area of the capacitor electrodes. (See Lee et al, xe2x80x9cIntegration of (Ba, Sr)TiO3 Capacitor with Platinum Electrodes Having SiO2 Spacer,xe2x80x9d Conference Proceedings IEDM-97, IEEE 1997: 249-252).
In the reference xe2x80x9cA 1.28 xcexcm2 Bit-Line Shielded Memory Cell Technology for 64 Mb DRAMsxe2x80x9d (Y. Kawamoto et al, Techn. Digest of VLSI Symposium 1990: 13 and 14), a DRAM cell arrangement with a capacitor is described, in which a capacitor electrode is constructed as a crown structure. Despite a small cross-sectional area, a crown structure has a large surface area. A crown-shaped capacitor electrode promotes a large capacity of the capacitor, given a simultaneous high packing density. Generally, polysilicon material is used for the capacitor electrode.
In capacitors with dielectrics consisting of barium-strontium-titanate (BST), primarily platinum is currently used as a material for the capacitor electrodes. (See R. B. Khamankar et al., xe2x80x9cA Novel BST Storage Capacitor Node Technology Using Platinum Electrodes for Gbit DRAMs,xe2x80x9d IEDM (1997): 245-248). A disadvantage of using platinum is that a suitable anisotropic etching process having an etching rate of up to 1 xcexcm per minute, which is common in semiconductor production, is still unknown. Due to the slow and incomplete anisotropic etching process, only relatively thin platinum layers can be constructed. At present, it is not possible to create a complicated crown structure from a thick platinum layer for the enlargement of the surface of the capacitor electrodes, and ultimately for increasing the capacity of the capacitor having a simultaneous high packing density.
The use of ruthenium as a material for capacitor electrodes has been proposed in Y. Nishioka et al.""s xe2x80x9cGiga-bit DRAM Cell with New Simple Ru/(Ba,Sr)TiO3/Ru Stacked Capacitors Using X-ray Lithography,xe2x80x9d IEDM (1995):903-906. However, ruthenium has not yet been incorporated into semiconductor production. As a result, the incorporation of ruthenium entails the risks of contaminants thus reducing the yield. Furthermore, a significant amount of time would be required to develop new production apparatuses in order to utilize ruthenium.
The reference xe2x80x9cAmorphous Metallic Alloys in Semiconductor Contact Metallizationsxe2x80x9d by Mark Nicholett 400 Solid State Technology 26 (December 1983, ); Nr. 12; Port Washington, N.Y., teaches the arranging of a thin film made of an amorphous metallic compound between a substrate and a metallizing layer. The thin film prevents the diffusion of atoms from the metallizing layer into the substrate. Amorphous materials do not have grain boundaries which act as rapid diffusion paths for atoms. Rules have been proposed for the selection of elements to obtain amorphous metallic alloys. The combination of these elements yields an amorphous metallic compound. According to these rules, it is particularly important that the atomic size of the elements differ by at least 10%.
A European Patent Document 0 412 185 A1 teaches the use of tungsten and silicon as WSix, with 0.3 less than x less than 0.7, as a material for a thin diffusion barrier which is arranged between a metallizing layer and a GaAs substrate.
A German Patent Document DE 43 00 808 teaches a method for the production of a multilayer capacitor. To produce the capacitor, a multilayer construction is deposited on a substrate. The multilayer construction is made from alternating conductive layers and dielectric layers in which successive conductive layers are formed from one of two different materials that are mutually selectively etchable to each other. Two openings are created in the multi-layer construction. Undercuts are created in the first opening by selective etching of one material, and in the second opening by selective etching of the other (second) material, so that only the conductive layers of the non-etched material are adjacent to contacts built into the openings. It is important that the first material be selectively etchable to the second material. It is proposed that the first material be composed of tungsten and the second material of WSi0.4, since WSi0.4 comprises distinctive etching characteristics.
The invention provides a circuit arrangement with at least one capacitor that has a higher packing density and a reduced procedural outlay. The invention also provides a method for producing the same.
To this end, in an embodiment a circuit arrangement has at least one capacitor, in which at least one capacitor electrode of the capacitor contains WSix where 0.3 less than x less than 0.7 and a capacitor dielectric that contains a ferroelectric.
In an embodiment, the capacitor includes two capacitor electrodes. The first capacitor electrode at least partially includes WSix, with 0.3 less than x less than 0.7. The capacitor also has a capacitor dielectric which contains a ferroelectric. It is within the framework of the invention to have the second capacitor electrode also contain WSix, with 0.3 less than x less than 0.7 as its material. However, the second capacitor electrode need not necessarily contain WSix as its material. In such a case, the following applies only to the first capacitor electrode.
An advantage of the present invention is the use of WSix as the material for the capacitor electrodes to reduce the procedural outlay.
A further advantage of the present invention is that tungsten W is well-known in semiconductor production and does not represent a contamination risk.
Another advantage of the present invention is that WSix can be etched using a conventional production apparatus, thus reducing development costs.
Another advantage of the present invention is that common sputter apparatuses or CVD apparatuses can be used for the creation of WSix layers.
To this end, the reduction of the procedural outlay applies particularly if the circuit arrangement is created in substrates which have silicon, such as monocrystalline silicon wafers or SOI substrates.
An exemplifying embodiment of the invention which is depicted in the Figures is detailed below.
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