1. Field of the Invention
The present invention relates in general to memories having spare rows and columns of memory cells that can be used to replace rows and columns having defective cells, and in particular to an apparatus for testing such a memory and for generating data for facilitating allocation of spare rows and columns.
2. Description of Related Art
A typical random access memory (RAM) includes an array of rows and columns of memory cells, each cell having a unique combination of row and column address. Many RAMs include redundant storage elements in the form of spare rows and columns of memory cells. When such a RAM is found to have a defective memory cell, a row or column containing that memory cell can be replaced with one of the RAM's spare rows or columns by using a laser or other means to alter the RAM so that the spare row or column is addressed in lieu of the row or column containing the defective cell.
Each cell resides in one row and one column of a RAM, and when a cell is defective it can be repaired by replacing either its row or column with a spare row or column. However when a RAM has many defective cells it is important to allocate spare rows and columns efficiently. For example assume a RAM has one spare row and three spare columns. Assume also that the RAM has 6 defective cells with three of them occurring in its first row. If we replace the first row with the spare row, then we can use the three spare columns to replace columns containing the three defective cells that are not in the first row. However if we use the three spare columns to replace the columns containing the three cells in the first row, we may not have enough remaining spare rows and columns to replace the three cells that are not in the first row.
Prior art memory testers typically test each memory cell of a RAM device under test (DUT) by writing data to the memory cell and then reading the data back out to determine whether the data read out matches the data written into the cell. A high speed memory tester employs a pattern generator or counters to produce the data, address and control signals needed to write data into the memory cells and read it back out. A hardware comparator typically compares the memory input and output data and supplies data indicating the result of the comparison to an “error capture memory” having one storage memory for each memory cell to store the results of the comparison. After each memory cell of the DUT has been tested, the contents of the error capture memory constitutes a bit map of the DUT, with each bit indicating whether a corresponding memory cell of the DUT is defective. Following the test, a computer reads the contents of the error capture memory and determines therefrom how to best allocate spare rows and columns when replacing the defective memory cells.
One problem with such a system is that since the error capture memory has to have as many cells as the memory being tested, it can take a relatively long time for the computer to read all of the data out of the error capture memory. In a production environment where thousands of memories are being tested in succession, the total time the computer requires to read the captured error data is substantial and comprises a significant portion of the time required to test and repair the memories.
U.S. Pat. No. 6,256,757 entitled “Apparatus for Testing Memories with Redundant Storage Elements” issued Jul. 3, 2001 to Brian Arkin, et. al, describes an apparatus for testing a memory formed by rows and columns of memory cells. The test apparatus includes an error capture memory for keeping track of the defective cells, but also includes a separate counter for each row and each column of the array. Whenever the tester finds a defective memory cell, it not only makes note of the failed cell in the error capture memory, it increments the count of the counters corresponding to the defective cell's row and column. Thus at the end of a memory test, the counts indicate the number of defective cells in each row and in each column. The tester sends the counts to a computer which can usually determine how to allocate spare rows and columns to repair the memory on the basis of the counts alone. The test apparatus therefore sends data from the error capture memory to the computer only when the computer is unable to determine how to repair the memory solely on the basis of counts. The system is advantageous because the test apparatus can forward the relatively small amount of count data to the computer much faster than the relatively large amount of error capture memory data. However since the test apparatus must provide a separate counter for each row and column of the array, the apparatus requires a large number of counters in order to test memories having a large number of rows and columns.
Thus it would be beneficial to provide a memory test system that can test a memory and quickly provide a computer with a relatively small amount of data that will enable the computer to determine how to allocate spare rows and columns, which does not require the computer to always read the entire contents of an error capture memory, and which need not provide a separate counter for each row and column of the memory.
USPTO Backgrounds
USPTO Backgrounds