1. Field of the Invention
One embodiment relates to an arithmetic processing unit.
2. Description of the Related Art
In many arithmetic processing units (e.g., central processing units), architecture called stored program system is employed. In an arithmetic processing unit using the stored program system, instructions and data for executing the instructions are stored in a memory device (e.g., a semiconductor memory device), and the instructions and the data are read sequentially to execute the instructions.
The memory device includes a main memory device for storing data and instructions and a cache memory which can perform data writing and data reading at high speed. In order to reduce access to a low-speed main memory device and speed up the arithmetic processing, a cache memory is provided in an arithmetic processing unit between an arithmetic unit (arithmetic part) or a control unit (control part) of the arithmetic processing unit and the main memory device. In general, a static random access memory (SRAM) or the like is used as a cache memory.
The capacitance of a cache memory provided in an arithmetic processing unit increases year after year. With this increase, the proportion of power consumption of a cache memory to the total consumption of an arithmetic processing unit remarkably increases; thus, various methods have been suggested in order to reduce power consumption of the cache memory.
For example, a method in which a cache memory is divided into several blocks and the less frequently used blocks (or lines) acquired by historical information are operated with a low voltage has been suggested. A method for stopping power supply to a cache line which is less likely to be accessed has also been suggested.
The cache memory needs to hold data and the like even when arithmetic operation is hardly performed. In such a case, power consumption can be reduced by backing up data in the other memory device and stopping the supply of power to the cache memory. The other memory device for backing up data is preferably provided inside the arithmetic processing unit for a high-speed response.
For example, Patent Document 1 discloses a structure in which a volatile memory such as an SRAM and a backup memory having higher data holding characteristics than the volatile memory are used in combination as a cache memory. In this structure, data in the volatile memory is backed up in the backup memory (backup) before power supply is stopped and the data is returned to the volatile memory (recovery) after power supply is restarted.
USPTO Backgrounds
USPTO Backgrounds