With the continuous improvement of semiconductor integration technology, the circuit system is developing toward to the direction of high density and integration. In order to meet the requirement of high integration, the integration technology of power semiconductor is widely used in circuit system. The damage of Electrostatic discharge named as ESD (Electro-Static discharge) to CMOS integrated circuit has attracted the attention of electronic engineers and researchers, and the traditional protection methods and measures of low voltage ESD have achieved some effects. Due to the introduction of integration technology of power semiconductor, the working voltage of the circuit system is continuously increasing, the traditional protection methods and measures of low voltage ESD can not be simply transplanted into the IC system of power semiconductor nowadays. The ESD protection of power semiconductor IC or on-chip high voltage IC has become an important issue and research focus in the field of ESD protection. The high voltage IC usually works in high voltage, high current, strong electromagnetic interference, frequent hot plug, ultra higher or lower than room temperature and other high-intensity environment, on-chip ESD protection of high voltage IC is facing a more severely challenges. Therefore, designers need to make additional technical considerations when designing ESD protection for power IC.
The laterally diffused metal oxide semiconductor named as LDMOS is usually used as the driven transistor of the circuit load and ESD self-protection device at the output of high voltage IC, due to the high voltage endurance capability and low on-resistance. However, the application of LDMOS used as ESD protection is more restricted by the weakened voltage endurance capability and ESD robustness per area, resulting by the continuously decreased feature size of the IC fabricated process, as well as the chip area. Therefore, the LDMOS is becoming more difficult to meet the ESD protection standards named as the IEC6000-4-2, required by International Electrotechnical Commission, and the ESD protection capability of electronic products should be no less than 2000 V measured by the human body model. After trial and error, researchers found that the embedded SCR of LDMOS structure named as LDMOS-SCR, was significantly helpful to improve the ESD robustness of devices. However, the holding voltage reduced remarkably when the LDMOS-SCR turned on under the ESD pulse stress, and results in the easier latch-up effect risk. If the holding voltage or current of the LDMOS-SCR device can be improved up to the normal operation voltage or current of the protected circuits, the latch-up risk can be effectively avoided. This invention provides an embedded high voltage LDMOS-SCR device with high holding voltage and current, strong voltage clamp and ESD robustness, by combining the strong robustness of LDMOS-SCR and the large capacitance of interdigital MOS structure. Under the ESD pulse stress, the invented ESD high voltage protection device will form a ESD current discharge path with LDMOS-SCR structure, which can enhance the current discharge capability and ESD robustness of the device. In addition, the resistance capacitance coupling current discharge path resulted by the embedded PMOS and NMOS interdigital structure will help to trigger the device and turn on quickly when the ESD pulse is approaching. Moreover, the interdigital structure of PMOS and NMOS increases the parasitic capacitance, the turn-on speed and the trigger current of the device. On the other hand, when the device is turned on, the holding current increases, and the emission rate of electron and hole in the path of SCR device can be reduced, thereby holding voltage and the voltage clamp capability of the device are enhanced.
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