1. Field of the Invention
The present invention is directed to a logic analyzer for representing a data of digital circuits.
2. Description of the Prior Art
Logic analyzers of the type generally set forth above are known, German Pat. No. 3,149,460, in which, by way of clock channels, a plurality of clock signals is respectively derived from the digital unit under test, the clock signal determining the sampling time for the data which are likewise derived from the digital unit via the data channels. When it is desired to analyze plural, independent processes which are executed without any correlation in terms of time, as would be the case, for example, with multi-processor systems, it is not readily possible to connect some of the clock channels to the one process and other clock channels to the other process, because with an approximate simultaneity of clock signals, one of the clock signals will never be recognized by the logic analyzer so that the storing of the data channel data clocked by that clock signal will not be effected.
It has already been attempted to solve this problem for two mutually-independent processes by two separate logic analyzers, wherein each logic analyzer additionally records correlation bits at the same time the other logic analyzer records a data pattern. In this connection, reference is taken to the Tektronix 1240 dual timebase logic analyzer. In this analyzer, evolution of the stored data is relatively complex because the correlation between the two separate recordings must also be analyzed. Above all, however, the known principle can be used with only two processes, since apparatus expense would be unacceptably high for more than two processes.
USPTO Backgrounds
USPTO Backgrounds