As shown in FIG. 1, in circuit diagram of a power converter formed by two N-channel MOSFETs, high-side MOSFET (HS) drain electrode D1 connects to port Vin, its source electrode S1 connects to drain electrode D2 of low-side MOSFET (LS), and the source electrode S2 of low-side MOSFET connects to ground Gnd. Generally, a bypass capacitor C is in parallel with Vin-Gnd of this power converter. The capacitor is used to suppress the voltage surge while the power converter turns on to improve its performance. Further more, as shown in FIG. 2, a power converter control IC (PIC) is connected with gate G1 of high-side MOSFET and gate G2 of low-side MOSFET, forming a DC-DC converter.
It is desirable to package both the high side and low side MOSFETs into one package to reduce the component count and reduce space in assembling a DC-DC converter. It is further desirable that the bypass capacitor C be placed closely to the two N-channel MOSFETs in order to minimize parasitic inductance therefore improve the suppression effect of voltage surge.
Thus there is a need for a new semiconductor package to encapsulate both high side and low side MOSFETs for power converter application. There is a further need for a new semiconductor mixed package structure which encapsulates the two MOSFETs and the bypass capacitor for power converter application, or even encapsulates the PIC into the same semiconductor package to form a complete power converter or DC-DC converter therefore effectively reduce the distance between different circuit components, improve the performance of power converter and also shrink the size of whole semiconductor package structure.
USPTO Backgrounds
USPTO Backgrounds