1. Field of the Invention
The present invention relates to a semiconductor memory device including an SRAM (Static Random Access Memory) having a CMOS (Complementary Metal Oxide Semiconductor) configuration, and more particularly relates to a layout structure of a memory cell directed to increase the processing speed of a multiport memory or an associative memory (CAM: Content Addressable Memory).
2. Description of the Background Art
In recent years, as electronic devices are becoming smaller and lighter, demand for realizing higher processing speed of the devices has been increased. In such an electronic device, it is indispensable to mount a microcomputer nowadays and to realize a higher-speed memory of a larger capacity in the configuration of the microcomputer. As a personal computer is being rapidly spread and the performance of the personal computer is increasing, to realize higher-speed processing, increase in the capacity of a cache memory is being demanded. Specifically, a RAM used by a CPU (Central Processing Unit) at the time of executing a control program and the like is requested to have a higher processing speed and a larger capacity.
As a RAM, generally, a DRAM (Dynamic RAM) and an SRAM are used. For a part requiring high-speed processing like the above-described cache memory, usually, an SRAM is used. As the configuration of an SRAM memory cell, a high-resistive load type configuration of four transistors and two high-resistive elements, and a CMOS type configuration of six transistors are known. Particularly, a CMOS type SRAM is considerably reliable since a leak current at the time of retaining data is very small, so that it is in the mainstream at present.
FIG. 23 is a diagram showing an equivalent circuit of an SRAM memory cell having a general 6 transistor configuration. Referring to FIG. 23, a memory cell has two driver transistors N101 and N102, two access transistors N103 and N104, and two load transistors P101 and P102. Each of the two driver transistors N101 and N102 and two access transistors N103 and N104 takes the form of an nMOS transistor, and each of two load transistors P101 and P102 takes the form of a pMOS transistor.
A first inverter is formed of nMOS transistor N101 and pMOS transistor P101, and a second inverter is formed of nMOS transistor N102 and a pMOS transistor P102. An output terminal of each of the first and second inverters is connected to an input terminal of the other inverter, thereby forming storage nodes “a” and “b”.
The source, gate, and drain of nMOS transistor N103 are connected to storage terminal “a”, a word line WL, and a bit line BL, respectively. The source, gate, and drain of nMOS transistor N104 are connected to the other storage terminal “b”, word line WL, and the other bit line/BL, respectively.
The source of each of driver transistors N101 and N102 is connected to the GND potential, and the source of each of load transistors P101 and P102 is connected to the VDD potential.
The layout in plan view of such an SRAM memory cell is, for example, as shown in FIG. 24.
FIG. 24 is a schematic plan view showing the layout of, mainly, a transistor part of an SRAM memory cell having a conventional 6 transistors configuration. Referring to FIG. 24, the memory cell is formed in the surface of an n-type well and a p-type well formed in the surface of a semiconductor substrate. Two nMOS transistors N101 and N102 as a pair of driver transistors and two nMOS transistors N103 and N104 as a pair of access transistors are formed in a p-type well. Two pMOS transistors P101 and P102 as a pair of load transistors are formed in an n-type well.
Each of two nMOS transistors N101 and N102 has a source and a drain formed in a pair of n-type diffusion regions 105a, and a gate 106b. Each of two nMOS transistors N103 and N104 has a source and a drain formed in a pair of n-type diffusion regions 105a, and a gate 106a. Each of two pMOS transistors P101 and P102 has a source and a drain formed in a pair of p-type diffusion regions 105b, and gate 106b. 
The six transistors are connected as shown in FIG. 23. Word line WL (not shown) is connected to gate 106a and extends across the memory cell in the direction X in the figure. Bit lines BL and /BL (not shown) as a pair are connected to drains 105a of access transistors N103 and N104 and extend across the memory cell in the direction Y in the figure.
The layout of the SRAM memory cell having the conventional 6 transistors configuration is as described above.
In the layout of the SRAM memory cell having the conventional 6 transistors configuration shown in FIG. 24, since the orientation of access transistors N103 and N104 and that of driver transistors N101 and N102 are different from each other, the dimension in the bit line direction (direction Y) of the memory cell layout is long, and the bit line is therefore long. Accordingly, the line capacity of the bit line is large, the capacity between the bit lines is large, and it causes a problem of long access time.
Since the orientation of access transistors N103 and N104 and that of driver transistors N101 and N102 are different from each other, optimization to finish the memory cell into desired dimensions is difficult. There is a problem such that it is difficult to assure a margin for variations in manufacturing such as a deviation of a mask.
To deal with the problems, the configuration in which the dimension in the bit line direction of the memory cell layout is shortened in an SRAM memory having the 6 transistors configuration is proposed in, for example, Japanese Patent Laying-Open Nos. 10-178110 and 2001-28401. The layout of an SRAM memory cell having the 6 transistors configuration disclosed in Japanese Patent Laying-Open No. 10-178110 will be described hereinafter.
FIGS. 25 and 26 are schematic plan views each showing the layout of the SRAM memory cell having the 6 transistors configuration disclosed in the publication. Referring to FIG. 25, a memory cell is formed in the surface of an n-type well formed in the surface of a semiconductor substrate and in the surface of p-wells formed on both sides of the n-type well. Two pMOS transistors P101 and P102 as a pair of load transistors are formed in the n-type well in the center. nMOS transistor N101 as a driver transistor and nMOS transistor N103 as an access transistor are formed in the p-type well in the left part of the figure. nMOS transistor N102 as a driver transistor and nMOS transistor N104 as an access transistor are formed in the p-type well in the right part of the figure.
Referring to FIG. 26, bit lines BL and /BL are formed separately as second metal wiring layers. Each of bit lines BL and /BL is connected to one of semiconductor terminals of access transistors N103 and N104 in the lower layer. A power supply line VDD is formed in parallel with the bit lines as the second metal wiring layer and connected to one of semiconductor terminals of load transistors P101 and P102 in the lower layer. Two ground lines GND are formed as the second metal wiring layer in parallel on both sides of word line WL. Further, word line WL is formed as a third metal wiring layer in the direction orthogonal to bit lines BL and /BL and is connected to the gate of each of access transistors N103 and N104 in the lower layer.
However, also with the layout disclosed in the publications, a concrete solving method is not found for a multiport SRAM memory and an associative memory.
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