Digital logic circuits which combine bipolar and complementary Metal-Oxide-Silicon ("CMOS") technologies in a single integrated circuit have been developed. A digital logic circuit that combines bipolar and CMOS technologies is particularly advantageous since the superior aspects of each may be exploited to yield optimal circuit performance.
For example, CMOS circuits have the advantages of extremely low quiescent power consumption, rail to rail output capability, high density, and a very high input impedance. Bipolar logic circuits, on the other hand, are useful in driving large capacitive loads, have fast switching capabilities, and feature better performance over temperature and power supply. These attributes have led to the development of a family of BiCMOS logic circuits which employ bipolar transistors to drive output loads, while utilizing CMOS devices to perform the basic logic functions.
One type of prior BiCMOS circuit is a BiCMOS tristate buffer. A BiCMOS tristate buffer typically provides as output a first voltage equivalent to a binary one condition, a second voltage equivalent to a binary zero condition, and an open circuit condition. The tristate buffers are used in many integrated circuit systems because it is typically desirable that when many different circuits are connected together to form a system, the circuit that drives its subsequent circuits should appear as though it does not exist in the system when that particular circuit does not drive its subsequent circuits.
One type of prior art BiCMOS tristate buffer circuit 10 is shown in FIG. 1. FIG. 2 illustrates the circuit of another type of prior art BiCMOS tristate buffer circuit 40. Referring to FIG. 1, BiCMOS tristate driver or buffer circuit 10 includes a pair of P-channel Metal-Oxide-Silicon field effect transistors ("PMOSFETs") 12 and 14 that are serially connected to a power supply V.sub.CC and a node 15. A pair of N-channel MOSFETs 16 and 18 are connected in parallel between node 15 and ground. A bipolar transistor 20 has its base connected to node 15, its collector connected to the power supply V.sub.CC, and its emitter connected to an output node 25. A bipolar transistor 21 is connected between output node 25 and ground. The base of transistor 21 is connected to ground via a pair of transistors 26 and 28. Transistors 26 and 28 are connected together in parallel. The base of transistor 21 is also connected to output node 25 via a pair of serially connected transistors 22 and 24.
Transistors 14, 16, and 24 receive a DATA IN signal. Transistors 12, 18, and 28 receive an ENABLE signal and transistor 22 receives an ENABLE signal which is the inverting signal of the ENABLE signal. The gate of transistor 26 is connected to node 15. When the ENALBE signal is logically high, transistor 22 is on and transistors 18 and 28 are switched off by the logical low ENABLE signal. Transistor 12 is, however, switched on. At this time, if the DATA IN signal is logically low, transistor 20 is turned on and transistor 26 is turned on which turns off transistor 21. This causes output node 25 to output a logical high voltage. If the DATA IN signal is, however, logically high, transistor 20 is off. Meanwhile, transistor 24 is turned on which causes transistor 21 to be diode connected, connecting output node 25 to ground. This causes output node 25 to output a logical low voltage.
When the ENABLE signal is logically low, transistors 18 and 28 are both on, turning both transistors 20 and 21 off. The causes output node 25 to float which presents the open circuit condition.
Disadvantages are, however, associated with this prior art BiCMOS tristate driver circuit. One disadvantage associated is that when another circuit connected also to output node 25 drives the output node high when node 25 is caused to float by transistors 20-21, a negative base-emitter voltage (i.e., -V.sub.BE) is developed across the base and emitter junction of transistor 20. If the condition remains for some time, then the operation of the circuit may be degraded after certain period of time or may fail after repeated applications of such negative V.sub.BE voltage.
One prior solution to this problem is shown in FIG. 2. Referring to FIG. 2, BiCMOS tristate buffer circuit 40 includes a first bipolar transistor 47 connected to the power supply V.sub.CC and an output node 48 and a second bipolar transistor 53 connected between output node 48 and ground. The base of transistor 47 is connected to a node 44 which is then connected to a DATA IN signal via an inverter 41 and a transmission gate formed by transistors 42 and 43. Another transmission gate formed by transistors 45 and 46 is connected between nodes 44 and 48. The two transmission gates are controlled by the ENABLE signal and its inverting signal ENABLE to be alternately turned on. The base of transistor 53 is connected to ground via a pair of transistors 51-52. A pair of transistors 49-50 are serially connected between output node 48 and the base of transistor 53.
During operation, when the ENABLE signal is logically high, circuit 40 operates as an inverting driver circuit and output node 48 generates a logical low voltage when the DATA IN signal is logically high, and a logical high voltage when the DATA IN signal is logically low.
When, however, the ENABLE signal is logically low, the transmission gate formed by transistors 42-43 disconnects node 44 from inverter 41, causing node 44 to float. At this time, the transmission gate formed by transistors 45-46 connects nodes 44 and 48 together. Transistor 53, meanwhile, is turned off by the conducting transistor 51, causing the circuit to be in the open circuit condition. Because the transmission gate formed by transistors 45-46 connects nodes 44 and 48 together, transistor 47 is bypassed and no negative V.sub.BE voltage is developed on transistor 47.
The prior art BiCMOS tristate inverter of FIG. 2, however, still bears disadvantages. One disadvantage of the circuit is that by employing the transmission gate along the path to the base of transistor 47, the switching speed of the circuit is adversely affected. This is due to the fact that the transmission gate embeds a resistance into the path, which typically slows the signal transmission to transistor 47.
Another disadvantage associated with the circuit of FIG. 2 is that a relatively large number of transistors are employed to configure the circuit. Note that one CMOS inverter used to generate the ENABLE signal from the ENABLE signal is not shown in FIG. 2, and for a noninverting stage, another CMOS inverter should be used to convert the DATAIN signal to a DATAIN signal. This typically causes the circuit to occupy more space on the silicon substrate. In addition, the circuit typically requires relatively high power consumption because of the relatively large number of transistors in the circuit.
USPTO Backgrounds
USPTO Backgrounds