1. Field of the Invention
The present invention relates to silicon on insulator structures and more particularly to a method for fabricating such structures with a defect free silicon active area.
2. Description of the Prior Art
Those skilled in the art have long recognized the desirability of silicon-on-insulator structures for fabricating semiconductor devices. The resulting circuit and device isolation can eliminate latchup problems and reduce soft errors from alpha particles (or other ionizing radiation) while reducing intrinsic and parasitic capacitance. During the past several years, there has been an increase in efforts to improve the electronic quality of silicon on insulator (SOI) structures for VLSI applications. One method of fabricating such a device comprises forming a silicon layer above an existing oxide layer. Examples are laser or strip heater recrystallization and selective epitaxial methods. Generally, the quality of the silicon layer is inferior to that normally associated with silicon processing. A second technique in fabricating SOI structures comprises forming an oxide layer beneath an existing high quality silicon layer. Examples are oxidized porous silicon and oxygen ion implantation. Generally these methods result in an inferior oxide and the quality of the SOI may be degraded during oxide formation.
Another technique for forming silicon on insulator structures is disclosed by Lasky et al. IEDM Technical Digest, page 684 (1985). The Lasky et al. process as shown in FIG. 1, comprises growing a lightly doped epitaxial layer 2 on a heavily doped substrate 4 and growing a thermal oxide 6 on the lightly doped layer 2. Thereafter, a lightly doped carrier wafer 8 is bonded to the oxide layer 6. A preferential etch is used to remove the heavily doped substrate 4 leaving the thin lightly doped epitaxial layer above the thermally growing oxide layer. The Lasky et al. process and variations thereof have not been actively integrated into commercial device manufacturing because of the difficulty in achieving thickness uniformity over the wafer surface and problems in obtaining thin layers of controlled doping profile. These problems are partly due to the wide doping gradient which characterizes the etch stop region and the stress produced at the epitaxial layer-substrate interface. The stress produces defects in a resultant thin active area. Thus, there is a need to reduce defects and improve the thickness control in the fabrication of thin silicon layers on an insulating substrate.
USPTO Backgrounds
USPTO Backgrounds