There is an increasing demand for semiconductor test systems that perform capacitance measurement on a large scale (in terms of volume), and at a high speed. Semiconductor manufacturing processes are implementing semiconductor process dispersion control and new process designs. Test systems capable of large scale and high volume capacitance testing are needed in order to meet the demands of such the newest semiconductor processes. On the other hand, finer design rules for the physical design of the semiconductor devices are resulting in ever thinner MOSFET gate dielectric films. A thinner gate dielectric increases the likelihood of a tunnel effect that generates a leakage current. Leakage currents create problems such as, a reduction of measurement dynamic range and an increase in measurement costs. The problems created by leakage currents complicate industry-wide efforts to meet the demands of large scale and high volume capacitance testing.
Various techniques are utilized for minimizing the effect of leakage currents on test measurements. A typical capacitance measurement test system may measure capacitance on a device-under-test (“DUT”) by probing the DUT and treating the circuitry between the probes as an equivalent circuit having capacitance, Cp, in parallel with resistance, Rp, or Cp//Rp. The Cp-Rp measurement mode is amenable to measurement with an LCR meter using the auto balancing bridge method.
In the LCR meter with auto-balancing bridge method, a voltage oscillator output is applied to the DUT causing a current in the in the DUT with an impedance, Zx=Cp//Rp. The current then flows into a feedback resistor of a current-to-voltage (“I-V”) converter. The I-V converter operates so that the current in the feedback resistor and the current in the DUT are at the same level. When the levels are the same, the voltage potential at a node between the DUT and the I-V converter is at zero (0) volts. In this state, the Zx value may be determined by comparing the voltage applied to the DUT and the output voltage of the I-V converter. When the voltage at the node between the DUT and I-V converter is not zero, the I/V converter detects an error current and its output is divided into a component of 0 degree and a component of 90 degree by a phase detector. The output signal of the phase detector is a DC level corresponding to the magnitude of the non-balanced component by the loop filter. The DC level signal is sent to a vector modulator to modulate each of the 0 degree component signal and the 90 degree component signal, respectively. Reverse amplification of the output signal of the vector modulator is performed. The signal passes through the feedback resistor and returns to the node between the DUT and I-V converter. The signal is designed to negate or cancel the leakage current flowing in the DUT.
One problem with the LCR with auto-balancing bridge method is that the measurement range for the resistance is determined by the smaller one of the two impedances of Cp and Rp. Therefore, the measurement error for either Cp or Rp increases as the ratio of Cp and Rp increases. Typically, for DUTs having a large leakage current, the impedance Rp is frequently lower than the impedance Cp resulting in an increase in the measurement errors of Cp. Another problem is that the LCR meter measurement time for 1 device is several tens of milliseconds making this technique largely unsuitable for use in high volume testing.
Another method for cancelling leakage current is the quasi-static C-V (“QSCV”) method. In the QSCV method, a voltage varying in time is applied to the DUT capacitance. The voltage varies at a certain rate for a predefined time. The DUT capacitance is determined by measuring the produced DC current. A method to cancel leakage current uses an independent DC source to address the problem relating to limitations in the measurement range due to the leakage current.
However, the QSCV method has problems as well. For example, high precision current sources are needed to reduce the measurement error. In an example implementation, a capacitor to be measured may have a capacitance of 10 pF and a leakage current resistance of 1 kΩ, and the measurement may be performed using a 1V/20 ms ramp wave using a measurement current of 500 pA. In order to keep the measurement error under 1%, the precision current source must generate current at an error rate of 0.0000005% or smaller in order to cancel a leakage current of 1 mA. Therefore, this method is unsuitable for capacitance measurement for an advanced process where leakage current is large. It also takes 20 ms or more to measure one device making this method largely unsuitable for high volume testing.
Another method used for cancelling leakage current the Direct Charge Measurement (DCM) method, which uses a step voltage generator and an integrator with a reset switch. The step voltage generator applies a voltage Vstep to the DUT. The integrator integrates a signal representing an electric charge generated by the DUT. If the Rp is large enough, the capacitance, Cp, of the DUT can be expressed by the output of the integrator, Vout, and the capacitance of integrator capacitor, Crange, as follows:Cp=−(Vout/Vstep)*Crange.The reset switch is triggered ‘ON’ at the conclusion of the measurement. The electric charge of the integrator capacitor, Crange, is discharged. The minimum measurement time of an integrator is typically determined by the response time of the integrator, which is typically on the order of several micro-seconds. Therefore, the DCM method is capable of performing high speed capacitance measurements making it possible to measure a large number of capacitances in a short time, which improves measurement speed over the LCR meter method by several orders of magnitude.
If the resistance, Rp, has a finite value, the charge due to leakage current and the charge due to the capacitance, Cp, being measured are integrated at the same time. Each charge can be distinguished by measuring the variation of the voltage output during the integration. However, the leakage current decreases the resolution of the measurement of the capacitance, Cp, thereby increasing the measurement error. In an example implementation, a capacitor to be measured may have a capacitance of 10 pF and a leakage current resistance of 1 kΩ. The integration time, tint, of the integrator may be 1 μsec, and Vstep may be set to vary from 0 V. to 1V. The integrator integrates the charge as follows:Q=IDUT*tint+CpVstep=1 nC+10 pC=1.01 nCAssuming a measurement is taken using a voltage supply with 0.01% resolution, the resolution of the capacitance measurement is about 0.1 pC, which is 1% of the measured capacitance value. The resolution of the capacitance measurement is about 100× the measurement resolution of the output voltage, Vout, which would mean there would be a 100× increase in the measurement error.
In view of the foregoing, there is an ongoing need for improved systems and methods for measuring capacitance in high volume and large scale processes with low measurement error at high leakage currents.
USPTO Backgrounds
USPTO Backgrounds