An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 10. Each cell 10 contains a storage capacitor 14 and an access field effect transistor or transfer device 12. For each cell, one side of the storage capacitor 14 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 14 is connected to the drain of the transfer device 12. The gate of the transfer device 12 is connected to a signal line known in the art as a word line 18. The source of the transfer device 12 is connected to a signal line known in the art as a bit line 16 (also known in the art as a digit line). With the memory cell 10 components connected in this manner, it is apparent that the word line 18 controls access to the storage capacitor 14 by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line 16 to be written to or read from the storage capacitor 14. Thus, each cell 10 contains one bit of data (i.e., a logic “0” or logic “1”).
A typical DRAM circuit has input/output (I/O) transistors that allow data to be read from and written to a memory array using specific I/O data lines. Due to the DRAM memory array structure, I/O data line lengths will vary. This occurs because a particular I/O data line is coupled to an individual memory module that can be located in one of various locations within the memory array. The capacitance on an individual I/O line varies with the length of the data line. The longer the I/O data line, the greater the capacitance of the I/O data line and the greater amount of time required before data transmitted on the I/O can be sensed.
FIG. 2 illustrates a conventional DRAM circuit 100. DRAM circuit 100 includes DRAM memory array 110, datapath 120, delay circuit 130, combinatorial logic circuit 140 and output pads 150. Memory array 110 includes individual DRAM memory modules 112, 114, 116 and 118 that possess a certain amount of memory, for example 512 Kb. The memory array 110 may contain more or less memory modules. Moreover, the size of each module may contain more or less memory than illustrated. Each memory module 112, 114, 116, 118 is connected to a data sense amplifier (DSA), such as for example, DSAs 122 and 124, in datapath 120 by I/O data lines.
As illustrated, due to an alignment of memory modules, the I/O data lines 113 for memory module 112 are longer than the I/O data lines 119 for memory module 118. The difference in length is due to the fact that memory module 112 is farther away from the data sense amplifiers than memory module 118. Consequently, the capacitance of the I/O data lines 113 (e.g., 0.8–1.2 pf, typically around 1 pf) connected to memory module 112 is greater than the capacitance of the I/O pair line 119 (e.g., 0.4–0.8 pf, typically around 0.6 pf) connected to memory module 118. A threshold distance between I/O data lines which is considered short or long is dependent upon various factors that include e.g., speed, current, layout, process and voltage.
Delay circuit 130, which includes delay device 132, is coupled to an enable line of each data sense amplifier and controls the timing of when data is received by the data sense amplifiers from an I/O data line. The length of delay produced by delay circuit 130 before enabling all data sense amplifiers is associated with the memory module with the longest I/O data lines, in this case memory module 112. Thus, each I/O data line, regardless of its length, has the same delay (i.e., the delay associated with memory module 112 and I/O data lines 113).
Because transmissions on all the I/O data lines are given the same amount of delay, longer I/O data lines, i.e., 113, experience an acceptable change in voltage (delta V) of approximately 300 mV as illustrated in FIG. 5. Shorter I/O data lines; however, experience a delta V equal to a full rail voltage, which results in unnecessary power consumption.
Once data is sensed by the sense amplifiers, i.e., DSAs 122 and 124, the sensed data is transmitted to combinatorial logic circuit 140 via data lines. The data is subsequently sent to output pads 150 for use by a requesting device.
FIG. 5 illustrates the signal timing for DRAM circuit 100. At time t1, a chip select signal CS for all data sense amplifiers transitions from low to high. At time t2, the delay signal Hfflat produced by delay circuit 130 transitions from low to high, enabling all data sense amplifiers in datapath 120. Delay signal Hfflat is associated with and generated in accordance with the time required for the most capacitive I/O data lines, in this case the I/O data line 113. Delay signal Hfflat is used to transfer data from memory module 112 to DSA 124 within a given time period, for example 2 ns. At time t3, the delay signal Hfflat transitions from high to low. While the delay signal Hfflat is high, the delta V for the more capacitive I/O data lines is approximately 300 mv. However, the delta V for the less capacitive I/O data lines is a full rail voltage, which produces an unnecessary current draw for the less capacitive I/O data lines. At time t4, I/O pull up signal IOPU transitions from low to high in order to pull the I/O lines high.
As discussed above, in current designs all I/O data lines coming from a memory array are given equal separation time before being sensed by a datapath sense amplifier. The delay for transmission on the I/O lines affects the memory access time for the memory array. In addition, I/Os with a lower capacitance must remain on longer to accommodate the timing of more capacitive I/Os, resulting in excessive power consumption.
Thus, it is desirable to produce a memory device with reduced power consumption.
USPTO Backgrounds
USPTO Backgrounds