a. Conventional Memory Core
FIG. 1a shows a memory core 101a. Typically, a memory core 101a is constructed with Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM) cells that store binary information (i.e., a “1” or “0”). For RAM cells, binary information is written to the cells via the Data_In input 102 and Information is read from the cells via the Data_Out output 104.
Other forms of cells that may be used to construct memory core 101a include Content Addressable Memory (CAM) cells and Read Only Memory (ROM) cells. CAM cells are designed to look for a “match” between stored information and offered information. As such, offered information is presented at the Data_in input 102 and the address location of matching data is presented at the Data_Out output 104. ROM cells are typically programmable. As such, the information to be programmed is entered at the Data_ln input 102 and read from the Data_Out output 104.
Regardless of the type of memory cell used to construct memory core 101a, both the Data_in input 102 and the Data_Out output 104 typically take the form of a bus that holds a plurality of bits. As such, multiple cells may be simultaneously written to or read from. The address bus 103 is used to identify the particular group of cells that are simultaneously written to or read from. A read enable (RE) 190 is active during a memory read and a write enable (WE) 191 is active during a memory write.
b. Multi-Port Memory Core
A multi-port memory core includes a plurality of memory ports such as the three Data_In ports 102a, 102b, 102c and the three Data-Out ports 104a, 104b, 104c seen in the exemplary, three port, multi-port memory core 101b of FIG. 1b. The exemplary multi-port memory core 101b of FIG. 1b also has three address ports 103a, 103b, 103c. Each input/output port pair is used with its corresponding address port. That is, for example, input port Data_InA 102a is provided write data that is written to the address specified by address port 103a. Similarly, output port Data_OutA is provided read data that is read from the address specified by address port 103a. Each port also has its own corresponding write enable input (e.g. We_A 190 for input port A, We_B 191 for input port B and We_C 192 for input port C). A write enable input is active if its corresponding input port is to be written to. A separate read enable input (not shown in FIG. 1b for simplicity) may also be activated to read data from a particular output port.
A problem with memory cores, whether conventional as seen in FIG. 1a, multi-port as seen in FIG. 1b, or otherwise, is the testing of such devices. Typically memory cores have dedicated, hardwired built in self test (BIST) circuitry that can apply only a limited overall range of combinations of data patterns and/or data addresses that the memory could be asked to perform in the field.
Furthermore, as a system (e.g., a computing or networking system) frequently depends upon the operation of a plurality of memories, the testing problem described above becomes more severe if testing of a plurality of memories is attempted. That is, the system (or at least the memory portion of system) can only be tested to a limited overall range of data patterns and/or addresses that the collection of memories could be asked to perform in the field.
USPTO Backgrounds
USPTO Backgrounds