Computer-disk storage systems record digital data onto a surface of a storage medium, which is typically a rotating magnetic or optical disk, by changing a surface characteristic of the disk in a pattern determined by the digital data itself. The digital data determines how a write transducer (write head), operating at a predetermined speed, records binary sequences onto the disk surface. In magnetic recording systems, for example, the digital data modulates electric current in a write coil in order to record a series of magnetic flux transitions onto the surface of a magnetizable disk. Similarly, in optical recording systems, the digital data may modulate the intensity of a laser beam in order to record a series of “pits” onto the surface of an optical disk. Other systems, for instance, magneto-optical systems use a hybrid combination of the two. When reading the previously recorded data, a read transducer (read head), positioned near or otherwise sensing the surface of the spinning disk, senses the alterations on the medium and generates a sequence of corresponding pulses in an analog read signal. These pulses are then detected and decoded by read-channel circuitry in order to reproduce the digital sequence.
In a conventional analog read channel, detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector. More recent designs find it preferable to use a discrete-time sequence detector in a sampled-amplitude read channel because, among other reasons, these systems compensate for intersymbol interference and are less susceptible to channel noise. Consequently, discrete-time sequence detectors increase the capacity, speed, and storage integrity of the storage system.
There are several well known discrete-time sequence detection methods including discrete-time pulse detection (DPD), decision-feedback equalization (DFE), partial response (PR) with Viterbi detection, maximum-likelihood sequence detection (MLSD), enhanced decision-feedback equalization (EDFE), as well as numerous others.
In a conventional peak-detection read channel, analog circuitry detects peaks in the continuous-time analog read signal generated by the read head. The analog read signal is “segmented” into bit cell periods and interpreted during these segments of time. A peak detected during a bit cell period may represent a binary “1” bit, whereas the absence of a peak may represent a binary “0” bit. Errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. To this end, timing recovery in the read channel adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run-length limited (RLL) to limit the number of consecutive “0” bits.
One of the commonly used pieces of analog circuitry that detects the data in the continuous-time analog read signal generated by the read head is a Finite Impulse Response (FIR) filter. The FIR filter modifies (or filters) the original analog wave signal so that digital data can be more easily and accurately extrapolated from it. By developing better FIR filtering techniques, data reading devices can operate more quickly, at a higher frequency, and/or have increased data integrity and data reliability.
Sampled-amplitude detection such as that performed by a FIR filter requires timing recovery in order to correctly extract the digital sequence, and therefore a timing-recovery circuit is also part of the analog circuitry used to read a data channel. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak-detection systems, sampled-amplitude systems synchronize the pulse samples to the frequency of the data transmission. In conventional sampled-amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector determines the estimated sample values from the read-signal samples. Even in the presence of intersymbol interference the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
Therefore, in addition to creating better FIR filters, new techniques and circuits in timing recovery can be used to help create data storage devices with higher capacity, increased accuracy, and lower cost.
A standard use of a FIR filter according to the prior art is shown in FIG. 1. In that figure, a data system 10 is shown. The data system 10 can be a component part of any device that uses a receiver 20 including a FIR filter, such as those described above. The data system 10 includes a transmitter response and transmission channel 12, that sends an impulse response l(t) that the receiver 20 receives as an input signal s(t). Within the receiver 20 is a filter 22, such as a low pass filter, a FIR filter 24, and a timer-recovery circuit 26. The output of the FIR filter 24 is provided to the timing-recovery circuit 26, which, when used in conjunction with the FIR filter 24, is used to create an output signal r(tk). It is the goal of the output signal to be identical to a target response h(t), which is the expected readback signal shape used by the receiver 20 to estimate the patterns on the surface of the disk. The signals s(t) and r(tk) are defined by the following equations:
                              s          ⁡                      (            t            )                          =                              ∑                          k              =                              -                ∞                                      ∞                    ⁢                                                    a                k                            ·              1                        ⁢                          (                              t                -                                  k                  ⁢                                                                          ⁢                  T                                            )                                                          (        1        )                                          r          ⁡                      (                          t              k                        )                          =                              ∑                          m              =                              -                ∞                                      ∞                    ⁢                                    a              m                        ·                          h              ⁡                              (                                                      t                    k                                    -                                      m                    ⁢                                                                                  ⁢                    T                                                  )                                                                        (        2        )            where tk=kT+φT . . . 0≦φ<1
One type of timer recovery circuit 26 is called an Interpolated Timing Recovery (ITR) circuit. These circuits stem from reconstruction criteria of a sampled signal s(t). A continuous-time waveform signal can be recovered without information loss from its samples provided that the Nyquist sampling criterion is met. This criterion is met when a waveform is sampled at a rate at least twice its highest frequency.
To reconstruct the signal provided to the FIR filter, the following reconstruction formula is used:
                              s          ⁡                      (            t            )                          =                              ∑                          n              =                              -                ∞                                      ∞                    ⁢                                                    s                ⁡                                  (                                      n                    ⁢                                                                                  ⁢                                          T                      S                                                        )                                            ·              sin                        ⁢                                                  ⁢                          c              ⁡                              (                                  t                  -                                      n                    ⁢                                                                                  ⁢                                          T                      S                                                                      )                                                                        (        3        )            where sin c(t)=sin(πt)/πt
Through filtering the incoming samples through a finite-length approximation of the sin c function, the correct phase of the signal s(t) can be recovered. The mean-squares optimization of the interpolating filter gk yields:
                                                                                                              min                    ⁢                                          ∫                                                                        -                          1                                                /                        2                                                                    1                        /                        2                                                                                                              ⁢                                                      ∑                                          k                      =                                              -                        L                                                              L                                    ⁢                                                            g                      k                                        ·                                          ⅇ                                                                        -                          ⅈ2π                                                ⁢                                                                                                  ⁢                        k                        ⁢                                                                                                  ⁢                        f                                                                                                        -                              ⅇ                                                      -                    ⅈ                                    ⁢                                                                          ⁢                  φ                                                                          2                ⁢                  ⅆ          f                                    (        4        )            where gk=sin c(k−φ)
FIG. 2A shows an example diagram of a filtering circuit 30 including a combination of a FIR filter and a ITR circuit known in the prior art. A FIR filter 24 couples to the ITR circuit 26, similar to that shown in FIG. 1. The ITR circuit 26 includes N phase shifters (individually labeled 28-1, 28-2, . . . 28-N), or filter tap sets to shift the input signal received from the FIR filter 24. Each phase shifter 28 is operable during a different time period of a sampling period. The number N of different phase shifters 28 in the ITR 26 is determined as the set number of intervals of the sampling period. This number is chosen as a trade-off between system performance and implementation complexity. The ITR circuit 26 includes a multiplexer MUX that provides the shifted input signal from a selected one of the phase shifters 28 to thereby provide the output of the ITR circuit.
The output of the ITR 26 is the output of the filtering circuit 30. This output is fed-back into a timing controller 32 that generates two timing signals, which are coupled to the ITR 26 and a Filter Coefficient Adaptation unit (FCA) 34. The FCA 34 provides FIR filter coefficient updates. When enabled, the FCA 34 provides estimated updated FIR filter coefficients, based on an internal adaptation algorithm. The FCA 34 is enabled based on the state of an enable signal generated by the timing controller 32. Additionally, the timing controller 32 generates a signal to control a selection of the proper interpolating phase (Tau).
In operation, the data-read-channel signal is received by the FIR filter 24 and passes it to the ITR 26. In each sampling period, the timing controller 32 selects the appropriate sampling phase among the N available. At each sampling period, only one phase out of N is selected.
The FCA 34 operates only when the first phase shifter 28-1 is active in the ITR 26. The reason for this is that the adaptation rate for the FIR filter (performed by the FCA 34) and the selection process of the ITR phase shifters 28 (performed by the timing controller 32) need to occur at very different rates. The selection of ITR phase shifters must be achieved quickly to keep up with relatively large sampling jitters, but the FIR convergence is achieved on a PR system over a time span of thousands of samples. Because there is only a predefined subset of ITR responses, one for each phase connection quantization, there is no problem for ITR stability. To guarantee adaptation convergence for the FIR filter leads to much slower updating.
In present systems, the FIR-coefficient adaptation is updated only over a subset of sampling phases. The easiest phase to perform the adaptation is when the first phase shifter 28-1 is in operation, or stated otherwise, when the interpolating phase φ is “close” to zero. In this phase, the FIR filter 24 does not need to compensate for any fixed group delay, which in turn means that the FIR filter can be of minimal length. However, this means that there is no possibility to compensate any further spectrum distortion due to the finite length of the ITR 26.
FIG. 2B shows a graph of a sampling period divided into 360°. The phase shifters 28 from FIG. 2A are represented as square boxes, with the phase shifter 28-1 shaded, while the rest of the phase shifters are not shaded. The shading for the phase shifter 28-1 indicates that the FCA 34 updates the filter coefficients for the FIR filter 24 only during the time when the phase shifter 28-1 is active. In all of the other times of the sampling period, i.e. when the phase shifter 28-1 is inactive, no coefficients for the FIR filter 24 are being updated.
A standard way to dynamically adapt coefficients for a FIR filter system is to use a stochastic gradient method. FIG. 3 shows the feedback mechanism used in the adaptation. The FIR filter 24 has a set of coefficients {fk}. The signal output from the FIR filter 24 is passed to a FIR adaptation device 40, which could be the Filter Coefficient Adaptation unit 34 of FIG. 2A. The adaptation device 40 produces sample-level estimates, which are combined with the signal input to the FIR filter 24 to create updated coefficients that are passed to the FIR filter as updated coefficients. One method of adaptation of a FIR filter uses a stochastic gradient method as shown in Equation (5).
                              f                      k            ∈            S                                n            ⁢                                                  ⁢            e            ⁢                                                  ⁢            w                          =                              f                          k              ∈              S                                      o              ⁢                                                          ⁢              l              ⁢                                                          ⁢              d                                -                                    ɛ              ·              g                        ⁢                                                  ⁢            r            ⁢                                                  ⁢            a            ⁢                                                  ⁢                          d              ⁡                              (                                  |                                                            o                      ⁢                                                                                          ⁢                      u                      ⁢                                                                                          ⁢                                              t                        n                                                              -                                          1                      n                                                        ⁢                                      |                    2                                                  )                                                                        (        5        )            under the constraints: S={−L, . . . , −1, 2, . . . , L}; {f0}=1; {f1}=constant.
This or similar criteria avoid convergence to the trivial solution with all zero values for the FIR taps.
One technical problem not solved by the prior art is how to jointly optimize, in a Partial-Response-channel filtering system, both the equalizer and timing-interpolation filters.
USPTO Backgrounds
USPTO Backgrounds