In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers. Besides, single or dual damascene processes are applied to more advanced semiconductor manufacturing technologies. Since Copper is quite difficult to be removed by dry etching method, Cu CMP application is more suitable for both extra Cu removed and further planarization in damascene process.
Deposition of non-conductive layers on the wafer substrate can be carried out using any of a variety of techniques. These include oxidation, LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric-pressure chemical vapor deposition), and PECVD (plasma-enhanced chemical vapor deposition). In general, chemical vapor deposition involves reacting vapor-phase chemicals that contain the required deposition constituents with each other to form a nonvolatile film on the wafer substrate. Chemical vapor deposition is the most widely-used method of depositing films on wafer substrates in the fabrication of integrated circuits on the substrates.
Due to the ever-decreasing size of semiconductor components and the ever-increasing density of integrated circuits on a wafer, the complexity of interconnecting the components in the circuits requires that the fabrication processes used to define the metal conductor line interconnect patterns be subjected to precise dimensional control. Advances in lithography and masking techniques and dry etching processes, such as RIE (Reactive Ion Etching) and other plasma etching processes, allow production of conducting patterns with widths and spacings in the submicron range. Electrodeposition or electroplating of metals on wafer substrates has recently been identified as a promising technique for depositing conductive layers on the substrates in the manufacture of metal interconnect lines in integrated circuits and flat panel displays. Such electrodeposition processes have been used to achieve deposition of the copper or other metal layer with a smooth, level or uniform top surface. Consequently, much effort is currently focused on the design of electroplating hardware and chemistry to achieve high-quality films or layers which are uniform across the entire surface of the substrates and which are capable of filling or conforming to very small device features. Copper has been found to be particularly advantageous as an electroplating metal.
Electroplated copper provides several advantages over electroplated aluminum when used in integrated circuit (IC) applications. Copper is less electrically resistive than aluminum and is thus capable of higher frequencies of operation. Furthermore, copper is more resistant to electromigration (EM) than is aluminum. This provides an overall enhancement in the reliability of semiconductor devices because circuits which have higher current densities and/or lower resistance to EM have a tendency to develop voids or open circuits in their metallic interconnects. These voids or open circuits may cause device failure or burn-in.
A typical standard or conventional electroplating system for depositing a metal such as copper onto a semiconductor wafer includes a standard electroplating cell having an adjustable current source, a bath container which holds an electrolyte electroplating bath solution (typically acid copper sulfate solution), and a copper anode and a cathode immersed in the electrolyte solution. The cathode is the semiconductor wafer that is to be electroplated with metal. Both the anode and the semiconductor wafer/cathode are connected to the current source by means of suitable wiring. The electroplating bath solution may include an additive for filling of submicron features and leveling the surface of the copper electroplated on the wafer. An electrolyte holding tank may further be connected to the bath container for the addition of extra electrolyte solution to the bath container, as needed.
In operation of the electroplating system, the current source applies a selected voltage potential typically at room temperature between the anode and the cathode/wafer. This potential creates a magnetic field around the anode and the cathode/wafer, which magnetic field affects the distribution of the copper ions in the bath. In a typical copper electroplating application, a voltage potential of about 2 volts may be applied for about 2 minutes, and a current of about 4.5 amps flows between the anode and the cathode/wafer. Consequently, copper is oxidized at the anode as electrons from the copper anode and reduce the ionic copper in the copper sulfate solution bath to form a copper electroplate at the interface between the cathode/wafer and the copper sulfate bath.
The copper oxidation reaction which takes place at the anode is illustrated by the following reaction equation:Cu---->Cu+++2e−
The oxidized copper cation reaction product forms ionic copper sulfate in solution with the sulfate anion in the bath 20:Cu++SO4−−---->Cu++SO4−−
At the cathode/wafer, the electrons harvested from the anode flowed through the wiring reduce copper cations in solution in the copper sulfate bath to electroplate the reduced copper onto the cathode/wafer:Cu+++2e−---->Cu
After the copper is electroplated onto the wafer, the wafer is frequently subjected to a CMP (chemical mechanical polishing) process to remove excess copper (copper overburden) from the electroplated copper layer and smooth the surface of the layer to form the metal interconnect lines. Important components used in CMP processes include an automated rotating polishing platen and a wafer holder, which both exert a pressure on the wafer and rotate the wafer independently of the platen. The polishing or removal of surface layers is accomplished by a polishing slurry consisting mainly of colloidal silica suspended in deionixed water or KOH solution. The slurry is frequently fed by an automatic slurry feeding system in order to ensure uniform wetting of the polishing pad and proper delivery and recovery of the slurry. For a high-volume wafer fabrication process, automated wafer loading/unloading and a cassette handler are also included in a CMP apparatus.
In a typical ECP process, an acidic copper or other metal electroplating bath solution typically includes various additives such as suppressors, accelerators and levelers. In order to meet 65-nm technology gap fill requirements, the additive concentrations are selected to achieve rapid bottom-up fill optimization in high aspect ratio vias and trenches, as well as microscopic and macroscopic uniformity. Consequently, excessive post-ECP copper overburden is common, particularly in the fabrication of metal interconnect lines in dense circuit patterns on wafers.
In situations in which metal interconnect lines are densely-packed, defects such as dishing and erosion are often induced in the metal lines as a result of the post-ECP CMP process to remove overburden, particularly with regard to the use of low-k IMDs (intermetal dielectrics). Dishing is an unintended reduction in the thickness of a material toward the center of a feature. Erosion is the excessive thinning of the metal in the high-density patterned area.
One technique which has been used to reduce copper overburden prior to a post-electroplating CMP process includes subjecting the electroplated copper to reverse ECP, in which the substrate is the anode and loses excess metal from the metal overburden humps. However, while this reverse ECP process is capable of lowering the overburden humps prior to CMP, there is always a risk that gapfilling will be reduced through the process. Accordingly, a novel method is needed for the elimination of copper overburden generated during an ECP process, which method is capable of preventing or at least reducing dishing and erosion effects associated with the post-CMP or reverse-ECP treatment of metal interconnect lines in high-density circuit patterns.
An object of the present invention is to provide a novel method which is capable of eliminating copper overburden generated during an ECP process.
Another object of the present invention is to provide a novel reverse tone mask method which is capable of preventing or at least reducing dishing and erosion in an electroplated metal layer during post-ECP chemical mechanical planarization or reverse electrochemical plating.
Still another object of the present invention is to provide a novel reverse tone mask method which includes the use of a masking layer to expose areas of metal overburden, or “overburden humps”, in a metal layer electroplated on a substrate to eliminate the metal overburden humps and planarize the metal layer by chemical mechanical planarization or reverse electrochemical plating.
Yet another object of the present invention is to provide a novel reverse tone mask method in which a mask layer is deposited on an electroplated metal as an isolation layer for the selective exposure and removal of metal overburden humps in the metal.
USPTO Backgrounds
USPTO Backgrounds