Generally speaking, some problems are encountered in the field of speech synthesis. For example, it is difficult to spend lower signal storage cost to obtain higher speech synthesizing performance. The current measure for achieving a proper compromise between the signal storage cost and the speech synthesizing performance generally decreases the sampling frequency to reduce the storage amount of sampled signals for economizing the signal storage cost, and utilizes an interpolation or a compensation method to increase the smoothness of the outputted signals for obtaining a satisfactory speech quality.
Please refer to FIG. 1 which is a block diagram showing a conventional speech synthesizer. The speech synthesizer 1 shown in FIG. 1 includes a speech ROM 11, a speech signal synthesizing circuit 12, an oscillation circuit 13, a control circuit 14 and a D/A converting circuit 15. The oscillation circuit 13 is used for generating a clock necessary for the speech synthesizer 1. The control circuit 14 is used for serving as an input/output processing interface. The speech signal synthesizing circuit 12 and the speech ROM 11 are electrically connected at point F so as to obtain the same frequency. When the speech signal synthesizing circuit 12 reads a speech signal from the speech ROM 11, a speech synthesized signal is outputted through point T. The working principles of the speech ROM 11 and the D/A converting circuit 15 are known to those skilled in the art so that they are not to be redundantly described here.
The interpolation method used for improving the speech synthesizing performance of the conventional speech synthesizer is illustrated with reference to FIGS. 2A and 2B. FIG. 2A shows that an additional block representing an interpolation circuit 2 is electrically connected between the speech signal synthesizing circuit 12 and the D/A converting circuit 15 of the speech synthesizer shown in FIG. 1. The interpolation circuit 2 includes a delay circuit 21, a D/A converting circuit 22 and a summation circuit 23. FIG. 2B schematically shows the waveform of the speech synthesized signals generated by the speech synthesizer shown in FIG. 2A. The solid line portions R and dash line portions E in FIG. 2B respectively represent the signals respectively outputted through lines DA1 and DA2 in FIG. 2A. The speech synthesized signal outputted through point T has first been processed by the summation circuit 23.
Because the interpolation circuit 2 is a circuit externally applied to the conventional speech synthesizer 1, the circuitry of the entire synthesizer will become more complicated when the interpolation circuit 2 is applied, and thus the cost will be increased.
Of course, another circuit can be used for improving the speech synthesizing performance. Please refer to FIG. 3, in which the block representing the interpolation circuit 2 in FIG. 2A changes into a block representing a compensation circuit 3. The compensation circuit 3 includes an up/down counter 31, a D/A converting circuit 32 the same as the D/A converting circuit 22 of FIG. 2A and a summation circuit 33 simpler than the summation circuit 23 of FIG. 2A.
The working principle of the speech synthesizer shown in FIG. 3 is illustrated by an example hereinafter. Assuming that the output of the speech signal synthesizing circuit 12 is a set of most signed bit (MSB) data from Bit 12 to Bit 4, the MSB data initiate the compensation circuit 3 and are also inputted into the D/A converting circuit 15, and then a signal is outputted via the line DA3 after the MSB data have been completely transmitted through the D/A converting circuit 15. On the other hand, after the converting circuit 3 is initiated, a set of least signed bit (LSB) data from Bit 3 to Bit 0 are outputted by the up/down counter 31 and manipulated through the D/A converting circuit 32 to have another signal outputted via the line DA4. The signal outputted via line DA4 is inputted into the summation circuit 33 together with the signal outputted via line DA3 to be processed, and then a Bit 12.about.Bit 0 speech synthesized signal with better speech quality is outputted via point T. The summation circuit 33 in this case is much simpler than that in the case shown in FIG. 2B because the MSB data generated by the speech signal synthesizing circuit 12 and the LSB data generated by the compensation circuit 3 are separately processed. However, the compensation circuit 3 is still an external circuit as the interpolation circuit 2 is, so the total cost is still high.
In general, if a speech synthesizer having a satisfactory performance is designed primarily based on the basic structure of the synthesizer shown in FIG. 1, the cost will be economized to a great extent since in such a speech synthesizer, the interpolation circuit 2 and the compensation circuit 3 are not required, and the design cost and the material cost are accordingly reduced.
Asada et al. (U.S. Pat. No. 4,435,832) discloses a speech synthesizer having a speech parameter memory, a register and an interpolator for a synthesizing operation. The speech parameter memory stores data such as for PARCOR coefficients obtained by analyzing the speech wave, amplitudes, pitches, voice/un-voice switching and the like. The register temporarily stores therein the parameters delivered from the speech parameter memory, and the interpolator interpolating these parameters before the synthesizing operation. Since the external interpolating circuit is needed for Asada et al.'s device, it is accordingly bearing on the problems described above.
USPTO Backgrounds
USPTO Backgrounds