1. Field of the Invention
The invention relates to a method for manufacturing a semiconductor layout pattern, a method for manufacturing a semiconductor device, and a semiconductor device, and more particularly, to a method for manufacturing a semiconductor layout pattern, a method for manufacturing a semiconductor device, and a semiconductor device avoiding adverse impact from line-end rounding effect.
2. Description of the Prior Art
Being an essential step in semiconductor fabrication, photolithography is used to transfer layout patterns of specific integrated circuits (ICs) to a photoresist layer formed on a semiconductor chip with a certain percentage and subsequently processed with techniques to transfer the layout pattern to the semiconductor chip.
With the trend toward higher complexity and higher integration for ICs, the size of the device is getting smaller and smaller. It is found that completeness of the layout pattern of the shrunk device is deteriorated after the photolithography process. In other words, deviations between the real layout pattern formed on the chips and the originally designed layout pattern are increased. Such deviations may be caused by several effects, including optical proximity distortions and chemical processing fluctuations. Consequently, effects such as corner rounding, line-end shorting, and line-end rounding are always observed. Additionally, those effect may also have dependency on the substrate material layer and local density of the patterns.
Please refer to FIG. 1, which is a schematic drawing illustrating a photoresist patterned by a conventional photolithography process. As shown in FIG. 1, a patterned pre-layer 12 such as a doped pattern, conductive pattern, or insulating pattern is formed on the wafer 10. Then, a photoresist layer (not shown) is formed on the wafer 10 and followed by performing a photolithography process. Accordingly, an IC layout pattern is transferred to the photoresist layer and thus a patterned photoresist layer 14 is obtained. As shown in FIG. 1, it is desirably expected that all the included angles formed by the overlapped patterned photoresist layer 14 and the patterned pre-layer 12 are 90° (as depicted by the included angle θ2). However, it is noteworthy that because of the optical proximity effect as mentioned afore, an included angle θ1 formed by the end of the patterned photoresist layer 14 and patterned pre-layer 12 is not 90° as expected. The acute included angle formed by the patterned photoresist layer 14 and the patterned pre-layer 12 manifests the transferred pattern suffers distortion. Such pattern distortion increases process complexity and causes device distortion or even device loss. Briefly speaking, the pattern distortion adversely impacts the yield of the semiconductor fabrication and the performance of the semiconductor devices.
Since the optical proximity effect cannot be completely avoided from the photolithography process, which means the line-end rounding issue is always found in the photolithography process, there is therefore a continuing need in the semiconductor processing art to diminish the adverse impact rendered from the line-end rounding effect.
USPTO Backgrounds
USPTO Backgrounds