The present invention relates to error propagation in storage devices generally and, more particularly, to a method and/or apparatus for implementing constraint codes with low error propagation.
Read channel integrated circuits are used in magnetic storage. Such read channel integrated circuits often contain significant digital signal processing and error correction logic to reliably reconstruct the original data stored on the media. Conventional read channel integrated circuits often introduce error propagation, which can adversely effect the performance of the storage if the error is excessive.
It would be desirable to implement a method and/or apparatus for implementing constraint codes in a read channel that introduces little or no error propagation.
The present invention concerns a method for generating constraint codes in a stream of data having a plurality of multi-bit source words, comprising the steps of (A) checking a sequence portion of the multi-bit source words for one or more constraint violations and (B) if no constraint violations are detected, modifying a predetermined portion of each of the multi-bit source words to generate a plurality of corresponding multi-bit code words configured to prevent the constraint violations of the sequence portions across an adjacent two of the multi-bit code words.
The objects, features and advantages of the present invention include providing a method and/or apparatus for implementing constraint codes in a read channel integrated circuit that may (i) be implemented while introducing minimal additional error propagation, (ii) be implemented in connection with existing read channel devices, (iii) be implemented with minimal coding overhead, and/or (iv) be implemented easily.
USPTO Backgrounds
USPTO Backgrounds