High performance semiconductor die can generate excess heat during operation. Efficient heat dissipation may thus be important to ensure proper functioning of the die. In instances wherein a semiconductor die is encapsulated within a surrounding dielectric material having a relatively low thermal conductivity, such as when the semiconductor die is encapsulated utilizing a Fan-Out Wafer Level Packaging (FO-WLP) approach, heat dissipation from the die may be reduced by the surrounding encapsulant. In certain instances, thermal performance of the package can be improved by placing the backside of the die in thermal contact with a heat sink structure, such as a copper slug, exposed to the ambient environment. In instances wherein the microelectronic package includes multiple package layers bonded in a stacked relationship, however, the overlying package layer or layers can obstruct attachment of the copper slug to any semiconductor die contained within the underlying package layer. Furthermore, the overlying package layer will typically cover most, if not all, of the copper slug if attached to the die backside and thus interfere with the convective cooling thereof. As a still further drawback, positioning a copper slug between stacked package layers can result in undesired heating of any microelectronic components contained within the overlying package layer, which may have thermal tolerances less than that of the heat-generating die contained within the underlying package layer. Package performance can suffer as a result.
There thus exists an ongoing need to provide microelectronic packages and methods for fabricating microelectronic packages having improved heat dissipation capabilities. Ideally, embodiments of the microelectronic package would provide enhanced thermal performance even when containing multiple package layers bonded in a stacked relationship, one or more of which are encapsulated utilizing a FO-WLP approach. It would also be desired if, in at least some embodiments, the package fabrication method could be performed on a panel level, at least in substantial part, to optimize manufacturing efficiency and throughput. Other desirable features and characteristics of embodiments of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying drawings and the foregoing Background.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.
USPTO Backgrounds
USPTO Backgrounds