1. Field of the Invention
This invention relates in general to a protection circuit suitable for use in deep sub-micron semiconductor fabrication, and more specially relates to a protection circuit for avoiding electrostatic discharge.
2. Description of Related Art
In the fabrication of integrated circuits, electrostatic discharge is usually the main cause of damage to the integrated circuits. At present time, it is one of the main reasons for malfunction in deep sub-micron integrated circuits. To overcome the problems accompanying electrostatic discharge, on-chip electrostatic discharge protection circuits are applied to the bonding pad of inputs and outputs of CMOS integrated circuits. However, with the continuing development of semiconductor fabrication, the function of electrostatic discharge protection circuits becomes increasingly insufficient. Therefore, how to effectively increase the efficiency of the electrostatic discharge protection circuits is very important for the industrial community at present.
FIG. 1 shows a conventional circuit diagram of an electrostatic discharge protection circuit. A field oxide device F1, a short channel first NMOS transistor N1, and a resistor R1 serially connected to F1 and N1 form an anti-electrostatic discharge circuit at the input of an input bonding pad 10. When an over-stress voltage is applied to the input bonding pad 10, the over-stress voltage is applied to the gate oxides of a PMOS transistor and an NMOS transistor of an input block 12 through the resistor R1. In order to control the over-stress voltage of the gate oxides of the input stage 12, the gate-grounded first NMOS transistor N1 is designed to operate at the breakdown region. Due to the high-speed operation and low working voltage in the technology of deep sub-micron integrated circuits, the thickness of the gate oxide is decreased, and the breakdown voltage of the gate oxide of input stage 12 is considerably reduced.
For the electrostatic discharge protection circuit of input stage 12 to be effective, the breakdown voltage of the gate-grounded first NMOS transistor N1 must be lower than that of the gate oxide of input stage 12. In order to provide a lower breakdown voltage, the channel length of the gate-grounded first NMOS transistor N1 should be short. An NMOS transistor with a shorter channel length usually has a lower breakdown voltage. The gate-grounded NMOS transistor with a short channel also has a lower tolerance of electrostatic discharge voltage. Therefore. a serial-connecting resistor R1 is used to limit the current of electrostatic discharge through the gate-grounded NMOS transistor N1. In order to effectively limit the current of electrostatic discharge through the NMOS transistor N1, the value of resistor R1 has to be as large as possible. However, if the value of resistor R1 connecting input bonding pad 10 and input stage 12 is too large, there will be a time delay for the input signal, which is not suitable for the high speed operation of integrated circuits.
FIG. 2 shows a circuit diagram of another conventional electrostatic discharge protection circuit. As shown in FIG. 2, a PMOS transistor P2, an NMOS transistor N2 and a resistor R2 form an anti-electrostatic discharge circuit at the input of input bonding pad 20. If a positive voltage is applied to the input bonding pad 20 when the direct bias V.sub.DD is grounded, a parasitic diode is formed in a PMOS transistor P2, making current flow through it. And if a negative voltage is applied to the input bonding pad 20, an avalanche breakdown occurs at the parasitic bipolar junction transistor in PMOS transistor P2 and makes current flow through it. In the same way, if a negative voltage is applied to the input bonding pad 20 when a relative low level voltage V.sub.SS is grounded, the parasitic diode is formed in a NMOS N2 to conduct current through it; if a positive voltage is applied to the input bonding pad 20, an avalanche breakdown occurs at the parasitic bipolar junction transistor in NMOS N2 and cause current through it.
When the gate oxide of invertor 22 of input stage is thinner, the breakdown voltages of PMOS transistor P2 and NMOS transistor N2 are approximately the same or even greater than that of the gate oxide of invertor 22. Nevertheless, if the value of resistor R2 is exceeded, it causes an operational delay. Therefore, the invertor 22 usually reaches its breakdown voltage before the parasitic bipolar transistors PNP or NPN of protection circuit turn on, so the electrostatic discharge protection circuit cannot provide effective protection for the internal circuit 24.
All of the conventional electrostatic discharge protection circuits discharge electrostatics to the direct bias V.sub.DD or the relative low voltage V.sub.SS mentioned above to protect the internal circuits by means of connecting other components serially or in parallel, of which increase the total area and affect the speed and performance. Moreover, the electrostatic discharge protection circuits always need additional and special fabricating conditions to provide proper operation, which increases the complexity of its structure.
USPTO Backgrounds
USPTO Backgrounds