In a chip with an on-chip non-volatile memory, MOS transistors coexist with memory cells. The performance and the reliability of such components strongly depend on the characteristics of their gate dielectrics. However, methods used to form dielectrics optimized for transistors and dielectrics optimized for memory cells in a same chip raise different implementation issues. A method enabling to form, in a same chip, transistors and memory cells provided with optimized dielectrics is thus desired.
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