1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a thin film transistor (TFT) substrate for inspecting shorts between gate lines and common lines and an inspection method using the same.
2. Discussion of the Related Art
There has been increasing demand for a variety of display devices with the development of an information society. Accordingly, many efforts have been made to research and develop a variety of flat display devices such as the liquid crystal display (LCD), the plasma display panel (PDP), the electroluminescent display (ELD), and the vacuum fluorescent display (VFD). These flat display devices used as the displays for a variety of equipment.
Among the various flat display devices, liquid crystal display (LCD) devices are widely used because of their thin profile, light weight, and low power consumption. LCD devices have been substituted for Cathode Ray Tube (CRT) displays. In addition to mobile applications such as displays for notebook computers, LCD devices have been deployed as computer monitors and as the displays of televisions that receive and display broadcasting signals.
A typical LCD device includes a liquid crystal panel for displaying images and a driver for applying signals to the liquid crystal panel. The liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space maintained between the substrates, and a liquid crystal layer formed between the first and second glass substrates. The liquid crystal layer may be formed by injection of liquid crystal between the bonded substrates.
The first glass substrate (TFT array substrate) includes a plurality of gate lines arranged along a first direction at fixed intervals; a plurality of data lines arranged along a second direction perpendicular to the first direction at fixed intervals crossing the gate lines; a plurality of matrix type pixel electrodes formed in pixel regions defined by the crossing gate and data lines; and a plurality of TFTs each connected to a respective pixel electrode and switched by signals on the gate lines to transfer signals on the data lines to the respective pixel electrodes.
The process of forming the TFTs is referred to as the TFT array process.
The second glass substrate includes a black matrix layer for shielding light from portions other than the pixel regions; R/G/B color filter layers for displaying various colors; and a common electrode for generating an electric field for producing an image.
The predetermined space is maintained between the first and second glass substrates by a spacer, and the first and second substrates are bonded to each other by a sealant. A liquid crystal layer is formed between the first and second substrates. The sealant may have a liquid crystal injection hole allowing liquid crystal to be injected between the two substrates after the substrates are bonded to each other.
The operating principle of the LCD device is based on optical anisotropy of the polarizing properties of the liquid crystal. Liquid crystal molecules have a long thin shape and when aligned in a common direction, the liquid crystal displays directional polarization characteristics. By applying an electric field to the liquid crystal, the alignment direction of the liquid crystal molecules may be controlled. When the alignment direction of the liquid crystal molecules is changed, the light polarization changes due to the optical anisotropy of the liquid crystal. This principle may be used to display an image.
The above-described LCD device is referred to as a twisted nematic (TN) mode LCD device. TN mode devices have disadvantageous characteristics including a narrow viewing angle. In-plane switching (IPS) mode LCD devices have been developed as a solution to the narrow angle viewing problem.
In the IPS mode LCD device, a pixel electrode and a common electrode are formed in a pixel region of a first substrate in parallel with each other at a fixed interval, so that an IPS mode electric field (that is a horizontal electric field) may be generated between the pixel electrode and the common electrode. The IPS mode electric field aligns the liquid crystal layer in a horizontal direction corresponding to the direction of the IPS mode electric field.
The driver for applying a driving signal to the liquid crystal panel is formed as a drive integrated circuits (ICs) connected to each pad of the gate and data lines.
A gate drive IC sequentially supplies scan signals to the gate lines so that lines of pixels arranged in a matrix arrangement and parallel to the gate lines are sequentially selected. Data signals are supplied from the data drive IC to the selected pixels.
Hereinafter, a related art LCD device will be described with reference FIGS. 1 and 2 of the accompanying drawings.
FIG. 1 is a plane view illustrating one pixel of a related art IPS mode LCD device, and FIG. 2 is a plane view illustrating gate lines, common lines and signal applying sides of the related art IPS mode LCD device.
As shown in FIG. 1, the related art IPS mode LCD device includes a plurality of gate lines 11 and a plurality of data lines 12 formed on a first substrate 10. The gate lines 11 are arranged to perpendicularly cross the data lines 12. A plurality of pixel regions is defined by the gate and data lines 11 and 12. A plurality of TFTs is formed with each TFT near the crossings of the gate lines 11 the data lines 12. A plurality of pixel electrodes 13 and a plurality of common electrodes 15a are alternately formed within the pixel regions.
Each of the TFTs includes a gate electrode 11a extended from the gate lines 11, a source electrode 12a extended from the data lines 12, and a drain electrode 12b spaced apart from the source electrode 12a at a predetermined interval. Each of the TFTs further includes a semiconductor layer 14 formed below the source and drain electrodes 12a and 12b to cover the gate electrode 11a. 
Furthermore, a gate insulating layer (not shown) is formed on the entire surface of the first substrate 10 including the gate line 11, and a passivation layer (not shown) is formed on the gate insulating layer. The passivation layer above a predetermined portion of the drain electrode 12b is exposed to define a passivation hole (not shown). The pixel electrode 13 is connected to the drain electrode 12b through the passivation hole. The gate insulating layer and the passivation layer are formed of inorganic insulating material and deposited at a thickness of 2000 Å to 4000 Å.
The common electrodes 15a extend from common lines 15 parallel to the gate lines 11. The common electrodes 15a are alternated with the pixel electrodes 13.
The second substrate (not shown) is arranged opposite the first substrate 10 and includes a black matrix layer (not shown) that shields non-pixel regions (gate lines 11, data lines 12 and TFTs); R/G/B color filter layers formed on the color filter substrate (not shown) including the black matrix layer to correspond to the pixel regions, and an overcoat layer formed on the entire surface of the second substrate including the color filter layers.
As shown in FIG. 2, in the IPS mode LCD device of the related art, a plurality of gate lines 11 are formed on the first substrate 10 at constant intervals, and common lines 15 are formed in parallel with the gate lines 11 to correspond to the respective gate lines 11. Since the common lines 15 are formed within a small pitch between two adjacent gate lines 11, a gate line 11 may contact a common line 15 causing a short.
A display area (dotted line area) and a non-display area outside the display area are defined on the substrate 10. The gate lines 11 are formed in the display area and are extended to the non-display area at one side to connect to respective gate pad lines. The common lines 15 are partially extended to the non-display area at the other side, and are electrically connected to common vertical lines perpendicular to the common lines 15. A common voltage applied to the common vertical lines is commonly applied to the common lines.
Although not shown, the data lines are extended to the non-display area to connect to the data pads.
However, the related art IPS mode LCD device has several problems.
In the related art IPS mode LCD device, the plurality of gate lines are formed at predetermined intervals and the common lines are formed between adjacent gate lines. Because the distance between the common lines and the gate lines is very narrow, shorts (unintended electrical connection) between the gate lines and adjacent common lines may occur in the process of forming the common lines and the gate lines. Such shorts may result in a rework process being performed on 30 to 50% of IPS mode LCD devices after the array process. Since shorts between the gate lines and adjacent common lines directly affect yield, a process for inspection of short is performed.
In an inspection process for a related art LCD device to detect shorts between the gate lines or the data lines, the gate lines or the data lines are divided into odd numbered lines and even numbered lines. The odd numbered lines are connected together at one side with a first shorting bar, the even numbered lines are connected together at one side with a second shorting bar, and different voltages are applied to the first and second shorting bars. Voltage values are measured at the sides of the odd numbered lines and the even numbered lines opposite to the shorting bars. The measured voltage values are then compared with the applied voltages to inspect whether adjacent lines are in contact with each other.
However, the above described shorting bar inspection method cannot be used to detect shorts between the gate lines and the common lines in an IPS mode LCD device in which the common lines are formed between the respective gate lines.
USPTO Backgrounds
USPTO Backgrounds