1. Field of the Invention
Embodiments of the invention are directed to a secure mode operation of system-on-a-chip (SoC) devices. More particularly, the embodiments are directed to ensuring that secure mode entry instructions enter the processor and are executed by the processor.
2. Description of the Related Art
Mobile electronic devices such as personal digital assistants (PDAs) and digital cellular telephones are increasingly used for electronic commerce (e-commerce) and mobile commerce (m-commerce). The programs that execute on the mobile devices to implement the e-commerce and m-commerce functionality may need to operate in a secure mode to reduce the likelihood of attacks by malicious programs and to protect sensitive data.
For security reasons, most processors provide two levels of operating privilege: a first level of privilege for user programs; and a higher level of privilege for use by the operating system. The higher level of privilege may or may not provide adequate security, however, for m-commerce and e-commerce, given that this higher level relies on proper operation of operating systems with highly publicized vulnerability. In order to address security concerns, some mobile equipment manufacturers implement yet another third level of privilege, or secure mode, that places less reliance on corruptible operating system programs, and more reliance on hardware-based monitoring and control of the secure mode. U.S. Patent Publication No. 2003/0140205, entitled “Secure Mode for Processors Supporting MMU and Interrupts,” incorporated herein by reference as if reproduced in full below, describes a hardware monitored secure mode for processors.
The '205 publication describes a system-on-a-chip, or “megacell,” implementation where a plurality of logical components are integrated onto a single semiconductor die. Some of the components may comprise a processor, a digital signal processor, shared memory, and a security state machine which monitors various system parameters and controls entry of the megacell into the secure mode. The security state machine may monitor the processor's data and instruction buses, and place the megacell in the secure mode upon the proper execution of a sequence of events. Thereafter, the security state machine ensures that only privileged programs (e.g., within the secure portion of the shared RAM) are accessed by the processor.
The inventors of the present specification have found that, with improvement in processor technology, it may be possible for malicious programs to misdirect or redirect processor execution even after the proper secure instructions have been delivered from the secure RAM and/or ROM to the processor. Thus, there exists a need for methods and related systems to obviate the potential for a malicious program to trick the system into entering a secure mode and yet execute non-secure instructions.
USPTO Backgrounds
USPTO Backgrounds