Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are synthesis, placement, and routing of the system on the target device.
When designing large systems to be implemented on target devices, EDA tools may require a significant amount of time to perform the compilation procedures. The generation of placement and routing solution that allow the system to achieve timing closure may require several iterations before an optimal solution is discovered.
After the compilation or a partial compilation of a design, a designer may wish to update a subset of the design modules (“kernels”) in the system. The update may involve relocating a module from a first location of the target device to a second location of the target device, replicating an instance of the module throughout the target device, or importing an optimized module onto a different target device. In the past, these types of updates required that the EDA tool recompile the system and seed-sweep the entire design from scratch. This recompilation required additional time which was costly and undesirable.
USPTO Backgrounds
USPTO Backgrounds