1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a surface channel type MOS transistor, a bipolar transistor, a resistive element and a capacitive element in mixture on the same substrate, and more specifically to a method of manufacturing a semiconductor device which is designed to realize high efficiency by reduction of manufacturing steps.
2. Description of the Related Art
With the progress of the technique for manufacturing semiconductor integrated circuit (IC) devices, there has been used a semiconductor IC device having a digital circuit and an analog circuit on the same substrate. As such IC device, a BiCMOS device which contains a CMOS transistor with which a logic circuit can be easily formed and a bipolar transistor which is capable of processing the faint analog signal at high speed and linearly are suitable. Especially, in case the IC device is applied to the GHz band communication technique and the like, a greater speed operation is required on the bipolar transistor, so that there is used in general a transistor formed by self-alignment of an emitter region and a base contact region.
It is rarely the case for such IC device to be constituted by only a CMOS transistor and a bipolar transistor, and there is assembled, for example, a circuit called ECL (Emitter Coupled Logic) circuit along with the resistive element in the digital circuit. The ECL circuit is a current changeover type logic circuit, in which the IC device can be operated at extremely high speed without causing saturated motion of the bipolar transistor.
On the other hand, in an analog circuit, a resistive element is indispensable for the constitution of a bias circuit for determining the operating point. Further, for the constitution of a filter circuit which is indispensable for the analog circuit, there is required not only the resistive element but also a capacitive element.
As described above, in order to manufacture the above semiconductor IC device, it is necessary to form not only the transistors but also the passive elements such as resistive element and capacitive element. Accordingly, it is important not to induce the increased number of steps as far as possible, in forming these elements in the same substrate.
In view of the above, in the formation of the passive elements, there is extensively practiced a method of using a polycrystalline line silicon layer which forms a base electrode of a self-alignment bipolar transistor, gate electrode of a MOS transistor or the like together with the electrodes of the passive elements.
Especially, there is disclosed a method of adding a capacitive element to a semiconductor device such as BiCMOS LSI and the like without largely increasing the number of steps (Japanese Unexamined Patent Publication (Kokai) No. Hei 6-291262). FIGS. 1A to 1G are sectional views showing a method of manufacturing a semiconductor device in order of process disclosed in Japanese Unexamined Patent Publication (Kokai) No. Hei 6-291262. In the manufacturing method as disclosed in the publication, first, as shown in FIG. 1A, by photolithographic technique and ion implantation of arsenic to a P-type silicon substrate 101, an N.sup.+ -type buried layer 102 is formed selectively in a bipolar transistor portion, in which a bipolar transistor is to be formed. Next, in order to make electrical insulation and separation of the bipolar transistor portion, a P.sup.+ -type buried layer 103 is formed around the N.sup.+ -type buried layer 102. Subsequently, the substrate 101 is heated to a level higher than 1000.degree. C., and an N-type single crystalline silicon layer 105 is grown on the silicon substrate 101 in a film thickness of about 2 .mu.m. In this case, the N.sup.+ -type buried layer 102 and the P.sup.+ -type buried layer 103 are expanded to the N-type single crystalline silicon layer 105. Next, in the region positioned above the P.sup.+ -type buried layer 103, a P-type channel stopper layer 104 is formed in the N-type single crystalline silicon layer 105. Further, for separation of elements, an element separation oxide film 106 is formed on the surface of the N-type single crystalline silicon layer 105 by the selective oxidation (LOCOS) method. Here, a film thickness of the element separation oxide film 106 is about 500 nm, and a long time thermal oxidation at 1000.degree. C. is required for forming the film 106. The P.sup.+ -type buried layer 103 and the P-type channel stopper layer 104 are expanded by thermal diffusion of boron impurities during this thermal oxidation step. By the phenomenon, the bipolar transistor portion is electrically separated from other portions, in which other elements are to be formed, by the P-type silicon substrate 101, P.sup.+ -type buried layer 103 and P-type channel stopper layer 104.
The formation of the P.sup.+ -type buried layer 103 may be carried out simultaneously with the formation of the P-type channel stopper layer 104.
Next, as shown in FIG. 1B, N-type impurities such as phosphorus are selectively ion-implanted to the N-type single crystalline silicon layer 105 with a mask. And, the implanted impurities are electrically activated by providing a thermal processing in nitrogen atmosphere at 900 to 1000.degree. C. for 10 to 30 minutes. By the step, a collector leading region 107 of an NPN-type transistor, which is a bipolar transistor is formed. Next, a gate oxidation film 108 having a film thickness of 10 to 20 nm is formed. Subsequently, a polycrystalline silicon layer 109 having a film thickness of about 100 to 200 nm is formed by CVD method on the whole surface. Next, by patterning by dry etching with a mask, a base-emitter forming region 110 is formed.
Further, as shown in FIG. 1C, regions to become a gate electrode of a P-channel MOS transistor or the like are formed by patterning the polycrystalline silicon layer 109. Then, a polycrystalline silicon layer 111 having a film thickness of 100 to 200 nm is formed on the whole surface by CVD method. As a result, the thickness of the polycrystalline silicon layer becomes 300 to 400 nm in the maximum. Thereafter, with a mask, N-type impurities are ion implanted in high concentration into a region in which the gate electrode of the P-type MOS transistor is to be formed, and P-type impurities are ion implanted in high concentration into a region in which a base electrode of the bipolar transistor portion is to be formed. Subsequently, by dry etching technique, there are processed the polycrystalline silicon layers 109 and 111 in a region other than the region in which the gate electrode is to be formed and the region in which the base electrode is to be formed.
Further, a P.sup.- LDD diffusion layer 112 is formed by ion-implanting P-type impurities in low concentration only in the P-channel MOS transistor portion by with a mask. Thereafter, an oxide film having a film thickness of 200 to 400 nm is formed on the whole surface by CVD method, and the whole surface of the substrate is subjected to an isotropic etching by dry etching technique to form a side wall 113. Next, by ion-implanting P-type impurities in high concentration into the MOS transistor portion with a mask, a P.sup.+ source-drain diffusion layer 114 is formed.
In FIG. 1C, the P-channel MOS transistor portion is formed in the N-type single crystalline silicon layer 105, but it is general to form an N-type well on the P-channel MOS transistor portion by adding a sheet of mask.
In FIG. 1C, the P-channel MOS transistor portion is illustrated, but an N-channel MOS transistor portion is not illustrated. To form an N-channel MOS transistor, in the same manner as in the P-channel MOS transistor, two masks are necessary for forming a LDD region and a source-drain region. Further, a mask is necessary for forming a P-type well in the N-channel MOS transistor portion.
Next, as shown in FIG. 1D, an oxide film 115 having a film thickness of 300 to 400 nm is deposited on the whole surface of the substrate by CVD method.
Subsequently, as shown in FIG. 1E, the oxide film 115 in the region 116 in which a capacitive element is to be formed is selectively opened by lithographic technique and etching technique. Next, a nitride film having a film thickness of 30 to 60 nm is formed by CVD method and dry etching is processed to allow a capacitive nitride film 117 to remain in the region in which a MIS capacitor is to be formed.
Next, as shown in FIG. 1F, the oxide film 115 in an emitter contact region 118, in which an emitter contact of the bipolar transistor is to be formed, and polycrystalline silicon layers 109 and 111 are removed by dry etching technique. Then, an intrinsic base region is formed in the emitter contact region 118 by ion implantation. Then, an oxide film having a film thickness of 400 to 600 nm is formed by CVD method, and etching-back is performed by isotropic etching of dry etching technique. As a result, an oxide film side wall 119 for separating the emitter and the base electrode region is formed on the side wall of the emitter contact region 118, by which the base electrode region and the emitter electrode region are electrically insulated.
Next, a polycrystalline silicon layer is grown on the substrate in a thickness of 100 to 200 nm, and a polycrystalline silicon layer 120 for forming the emitter is formed by dry etching technique. The polycrystalline silicon layer 120 functions also as an upper electrode of the capacitive element. And, the ion implantation into the polycrystalline silicon layer 120 and heat treatment are conducted. By the step, the source-drain diffusion layer of the P-channel MOS transistor portion is activated, and the P-type impurities are diffused in high concentrations from the base drawing electrode to form a graft base 123. Also, the emitter is formed by the impurity diffusion of arsenic or phosphorus from the polycrystalline silicon layer 120.
Next, as shown in FIG. 1G, an inter-layer insulation film 121 having a film thickness of 300 to 400 nm is formed by CVD method, after which contact holes 122 are opened with the wiring technique to form the respective electrodes. Hereinafter, the semiconductor device is completed by the conventional method.
On the other hand, recently, with respect to a MOS transistor of short gate length, in order to reduce the resistance of the gate electrode and the resistance of the source-drain diffusion layer, there is practiced a method of silicifying the gate electrode surface and the source-drain diffusion layer with, for example, a refractory metal such as Ti. In this case, it is necessary to have the surfaces of the diffusion layer and the polycrystalline silicon layer to be silicified exposed in advance.
However, recently, high efficiency system has been demanded in the semiconductor device manufacturing process, and the requirements cannot be met by the conventional method as described above.
Furthermore, according to the conventional manufacturing method as described above, because the oxide film is grown over the whole surface of the substrate and the MOS transistor portion is fully covered for forming the capacitive element, there is required a mask for) selectively removing the oxide film in order to expose the surfaces of the silicifying diffusion layer and polycrystalline silicon layer. Furthermore, in case of using the gate electrode of the MOS transistor or the base electrode or the emitter electrode of the bipolar transistor as the resistive element, it becomes necessary to form a protective film to prevent the whole surface of the resistive element from being silicified, thereby increase of processes is invited.
In the conventional semiconductor IC device, in both the P-channel MOS transistor and the N-channel MOS transistor, the N-type gate electrode is applied. Therefore, although the N-channel MOS transistor is a surface channel type one, the P-channel MOS transistor essentially becomes a buried channel type one. Since the buried channel type MOS transistor shows low current-off characteristics, it has a defect of showing larger leak current than the surface channel type one. Also, it has large short channel effect, and involves difficulty in threshold level control. Accordingly, when the gate length is shortened, it becomes essential to use a surface channel type MOS transistor for the P-channel MOS transistor as well as the N-channel MOS transistor.
However, when it is desired to apply the surface channel type P-channel MOS transistor to the conventional manufacturing method as described above, in view of the problem of thermal career, it is difficult to form it without deteriorating the respective characteristics of the P-channel MOS transistor and the bipolar transistor.
That is because, while conventionally there is normally used an ion implantation for forming the gate, the source and the drain of the P-channel MOS transistor and there are independently practiced the heat treatment necessary for formation of the bipolar transistor and the heat treatment necessary for formation of the gate, the source and the drain of P-channel MOS, oozing out of the boron implanted into the gate, the source or the drain to the channel region tends to occur. Especially, for the formation of the graft base of the bipolar transistor, there is required at least the furnace annealing at 850.degree. C. for 10 to 30 minutes. But, the heat treatment is excessive with respect to the P-channel type MOS transistor under the condition of the boron in the gate, the source and the drain being activated. Namely, when the heat treatment is provided, formation of the P-channel MOS transistor having the fine gate length becomes difficult.
Further, there is proposed a method of manufacturing a semiconductor device in which the voltage dependency of the capacitive element can be reduced without increasing the number of manufacturing steps (Japanese Unexamined Patent Publication (Kokai) No. Hei 7-273285). In the conventional semiconductor device manufacturing method as described in the above publication, for example, arsenic ion is implanted simultaneously into the upper electrode of the capacitive element and the source-drain diffusion layer of the MOS transistor.
According to the conventional method as described above, as the impurity concentration difference between the upper electrode and the lower electrode of the capacitive element can be restricted, the voltage dependency of the capacitive element can be made small. In addition, as the ion implantation into the upper electrode is made simultaneously with the ion implantation into the source-drain diffusion layer, the increase of cost can be kept to a small degree.
However, even by the above conventional method, the problem that the number of steps increases due to the silicifying the gate electrode surface and the source-drain diffusion layer is not settled. Furthermore, the problem that occurs at the time of making the P-channel MOS transistor of a surface channel type is not settled.
In Japanese Unexamined Patent Publication (Kokai) No. Hei 7-273285, there is proposed a semiconductor device which is schemed to lower the voltage dependency of a capacitive element. However, in the publication a semiconductor device having a capacitive element and a MOS transistor in mixture on the same substrate is described, but it is utterly silent of the relations with the BiCMOS.
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