The development of manufacturing electronic products is continually being challenged by a growing market demand for smaller, more efficient, and a higher performance product. The current trend towards miniaturization is driven to a large extent by portable electronic product applications. However, other product categories are under pressure to reduce sizes, as well, such as in the medical device industry where size is also important. For example, implantable medical devices such as pacemakers require smaller components yet are being required to provide higher performance than previous product. For example, more memory must occupy smaller space. There are numerous packaging techniques that have been used in the past. For example, some of such techniques include dual in-line packaging (DIP), leadless chip carrier processing, leaded molded plastic packaging, surface mount processing, etc. In addition, more recently, chip scale packaging (CSP) has been introduced. Generally, CSP includes the packaging of integrated circuits in packages which are substantially the same size or slightly larger than the integrated circuit die being packaged.
Various techniques have been developed for increasing integrated circuit die density on a printed circuit board or other type of circuit assembly, i.e., density of die on a longitudinal plane such as a plane defining a printed circuit board. For example, as described above, the smaller the component package of a semiconductor die (e.g., CSP), the greater the density of semiconductor die on such a longitudinal plane defining the circuit board. In other words, the number of die packages which can be mounted on the circuit board is increased.
Further, for example, vertical stacking (i.e., vertical relative to the horizontal plane) of dice or packaged dice has also been described for increasing chip density on printed circuit boards. For example, it is known to use connector structures for connecting a plurality of automated bonding tapes each having a respective semiconductor die attached thereto. Such connectors are used to stack the semiconductor dice attached to the die tape and provide electrical connection of each die being stacked to the printed circuit board. However, such connectors are separately constructed components adding to the overall cost and complexity of the stacked device. In addition, such connectors may use additional space leading to a decrease in die density on the circuit board. Packaged surface mount components have also been vertically stacked using separately constructed connection elements for providing vertical stacking of the packages and electrical connection of the individual packages of the stack to the printed circuit board upon which the stacked device is to be mounted.
Further, as described in an article from Tessera, Inc. entitled "Tessera Application Notes--Application Note 001--Stacked chips for high density memory module applications,"(August 1995), microball grid array technology available under the trade designation of (.mu.BGA) can be used for chip stacking. As described in this article, a stack of four packaged memory chips is created by fanning leads outward away from the die in lead frame fashion. The lead frame-like flex or rigid carrier of each of the die is interconnected by a stack of single solid core solder balls. Such stacking of the packaged chips uses membranes between the stacked packaged chips, such as Tessera Compliant Mounting Tape (TOMT) available from Tessera, Inc., which extend past the edge of the packaged chip such that the stack of solder balls can interconnect the stacked memories in a bus structure.
The Tessera approach using a single stack of solder balls for interconnection of the memory chips, requires backlapped die for matching thicknesses within the stacked packaged component device. For example, the die must be backlapped such that the solder balls used extend from one of the membranes between the stacked packaged chips to the next membrane for interconnection therebetween. However, a backlapping process may produce unusable die. In other words, the yield from a wafer of suitable die produced using a backlapping process is generally less than when no backlapping process is used.
The stacking techniques described above suffer from one or more of a number of problems. For instance, many of the techniques require the manufacture of custom dice that are specifically designed or backlapped for stacking, or many of such techniques involve the use of separately constructed connection elements. Further, many of such techniques for stacking dice are not useable in mass production techniques and/or are not cost effective to produce.
For example, in particular, with respect to memory devices used in medical apparatus, many of the above techniques can be used to stack memory die for increasing density but they are not cost effective or easily mass producible. In the case of implantable medical devices, medical personnel desire as much memory as possible in such devices without increasing the device size. By vertically stacking memory die, memory size can be increased by only taking up vertical height. In other words, semiconductor die density on a circuit board of the implanted medical device is substantially increased by vertical stacking without use of precious circuit board area along the horizontal plane defining the circuit board or assembly upon which the device is mounted.
Table 1 below lists U.S. Patents that describe a couple of stacking techniques:
TABLE 1 ______________________________________ U.S. Pat. No. Inventor(s) Issue Date ______________________________________ 5,198,888 Sugano, et al. 30 March 1993 5,514,907 Moshayedi 7 May 1996 ______________________________________
All patents listed in Table 1, and elsewhere herein, are incorporated by reference in their respective entirety. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Embodiments, and claims set forth below, many of the devices and methods disclosed in the patents of Table 1 may be modified advantageously by using the teachings of the present invention. However, the listing of any such patents in Table 1 is by no means an indication that such patents are prior art to the present invention.
USPTO Backgrounds
USPTO Backgrounds