1. Field of the Invention
The present invention generally relates to an apparatus and method of depositing a conductive material over sub-micron apertures formed on a substrate.
2. Description of the Related Art
Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 2:1, and particularly where the aspect ratio exceeds 4:1. Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free, sub-micron features having high aspect ratios.
Currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 xcexcxcexa9-cm compared to 3.1 xcexcxcexa9-cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
Electroplating is one process being used to fill high aspect ratio features on substrates. Electroplating processes typically require a thin, electrically conductive seed layer to be deposited on the substrate. Electroplating is accomplished by applying an electrical current to the seed layer and exposing the substrate to an electrolytic solution containing metal ions which plate over the seed layer. The seed layer typically comprises a conductive metal, such as copper, and is conventionally deposited on the substrate using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques. A continuous metal seed layer is essential for conducting the current required during electroplating. As feature sizes decrease, the ability to deposit conformal seed layers can be compromised. A discontinuous seed layer over the substrate may cause a number of problems during electroplating.
For example, when a discontinuity is present in the metal seed layer, the portion of the seed layer that is not electrically connected to the bias power supply does not receive deposition during the electroplating process. Particularly with physical vapor deposition of a seed layer, it is very difficult to deposit a continuous, uniform seed layer within a high aspect ratio, sub-micron feature. The seed layer tends to become discontinuous especially at the bottom surface of the feature because it is difficult to deposit material through the narrow (i.e., sub-micron) aperture of the feature. Discontinuities in the metal seed layer may cause void formations in high aspect ratio interconnect features. During the electroplating process, the metal deposits on all of the surfaces that are electrically connected to the bias power supply. Because the electroplated metal grows in all directions, the deposition around an area of discontinuity in the seed layer typically forms a bridge over the discontinuity, leaving a void adjacent the discontinuity within the feature. The void changes the operating characteristics of the interconnect feature and may cause improper operation and premature breakdown of the device. U.S. Pat. No. 6,197,181 entitled xe2x80x9cApparatus and Method For Electrolytically Depositing a Metal on a Microelectronic Workpiecexe2x80x9d discloses repairing a PVD or CVD copper seed layer to form an xe2x80x9cenhanced seed layerxe2x80x9d by electroplating a copper layer by utilizing an alkaline plating solution. Bulk deposition is then performed by electroplating copper by utilizing an acidic plating solution which has higher deposition rates than with use of an alkaline solution. One problem with the disclosed process is that providing an xe2x80x9cenhanced seed layerxe2x80x9d depends on an electroplating process over a copper seed layer which may exhibit the problems discussed above.
Electroless deposition is another process used to deposit conductive materials. Although electroless deposition techniques have been widely used to deposit conductive metals over non-conductive printed circuit boards, electroless deposition techniques have not been extensively used for forming interconnects in VLSI and ULSI semiconductors. Electroless deposition involves an autocatalyzed chemical deposition process that does not require an applied current for the reaction to occur. Electroless deposition typically involves exposing a substrate to a solution by immersing the substrate in a bath or by spraying the solution over the substrate. Those of skill in the art in manufacturing printed circuit boards acknowledge the problems of utilizing electroless deposition techniques to deposit metals in high aspect ratio features, such as through-holes of printed-circuit boards having diameters of 0.028 inches or 0.018 inches. For example, U.S. Pat. No. 5,648,125, entitled xe2x80x9cElectroless Plating Process For The Manufacture Of Printed Circuit Boards,xe2x80x9d which discloses an electroless nickel deposition process, states that the trend of smaller higher-aspect-ratio holes, such as 0.18 inch diameter through-holes, places increasing pressure on methodologies for producing printed circuit boards with regard to the always difficult task of properly plating the through-holes. (See, col. 4, Ins. 25-46.)
U.S. Pat. No. 6,197,688 entitled xe2x80x9cInterconnect Structure in a Semiconductor Device and Method of Formation,xe2x80x9d suggests materials for electroless deposition. The patent, however, does not disclose the processing conditions for the electroless deposition of the materials over sub-micron features. Accordingly, a satisfactory method of utilizing electroless deposition in the processing of substrates having sub-micron geometries has yet to be demonstrated.
Deposition of a conductive material in micron technology by electroless or electroplating techniques require a surface capable of electron transfer for nucleation of the conductive material to occur over that surface. Non-metal surfaces and oxidized surfaces are examples of surfaces which cannot participate in electron transfer. Barrier layers comprising titanium, titanium nitride, tantalum, and tantalum nitride are poor surfaces for nucleation of a subsequently deposited conductive material layer since native oxides of these barrier layer materials are easily formed. A seed layer, such as a copper seed layer, can serve as a surface capable of electron transfer. However, where there are discontinuities in the seed layer, nucleation of a subsequently deposited conductive material layer is incomplete and may not form uniformly over the seed layer.
Therefore, there is a need for an improved apparatus and method for depositing a conductive metal in sub-micron features formed in a substrate.
One embodiment provides an apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. The catalytic layer provides a surface capable of electron transfer for subsequent deposition and nucleation of a conductive material. Noble metals and semi-noble metals are not readily oxidized, and thus provide a surface capable of electron transfer. Examples of noble metals include gold, silver, platinum, palladium, iridium, rhenium, mercury, ruthenium, and osmium. In one embodiment, the noble metal used comprises palladium or platinum, and most preferably the noble metal comprises palladium. Examples of semi-noble metals include, iron, cobalt, nickel, copper, carbon, aluminum and tungsten. In another embodiment, the semi-noble metal used comprises cobalt, nickel, or tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In one aspect, the catalytic/barrier layer comprises cobalt, tungsten or combinations thereof. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a xe2x80x9cpatchxe2x80x9d of any discontinuities in the seed layer.
Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating. In yet another embodiment, the conductive material is deposited over the catalytic layer by chemical vapor deposition.
USPTO Backgrounds
USPTO Backgrounds