1. Field of the Invention
The present invention relates generally to input buffer circuits for semiconductor integrated circuits, and more particularly, to an input buffer circuit having reduced current flow through the buffer when the level of input signal to the buffer changes.
2. Description of the Background Art
In order to constitute a circuit available for various uses such as in a computer system, many circuits provided in semiconductor chips are used. Terminals of the respective semiconductor chips are connected to each other through interconnection to constitute a circuit with the desired function. As examples of such integrated circuits provided in semiconductor chips, transistor-transistor logic (referred to as TTL hereinafter) circuits and metal oxide semiconductor (referred to as MOS hereinafter) circuits are known. Generally, TTL circuits employ bipolar transistors while MOS circuits employ MOS-type transistors which are a kind of field-effect transistor. The invention is directed to connecting these two types of transistors.
FIG. 6A is a circuit block diagram showing a semiconductor chip comprising MOS circuits 91 through 9n and 101 to which semiconductor chips 81 through 8n each including a TTL circuit are connected. The semiconductor chip 100 is connected to receive output signals from the externally provided TTL circuits 81 through 8n. The semiconductor chip (or semiconductor integrated circuit device) more specifically comprises input buffer circuits 91 through 9n each connected to receive an output signal from the corresponding one of the TTL circuits 81 through 8n, and an internal processing circuit 101 responsive to input signals for processing. The signals processed by the internal processing circuit 101 are outputted through output terminals.
FIG. 6B is a diagram showing the characteristics which are compatible with the TTL circuit. In a case where the TTL circuits and the MOS circuits are interconnected to each other as shown in FIG. 6A, it is required to adjust the differences between the two types of circuits in their operating current and voltage. The input circuits 91 through 9n are provided with such characteristics as compatible with the TTL circuit so as to adjust the differences. That is, as shown in FIG. 6B, the input buffers 91 to 9n detect logical "1" when an input signal having a voltage higher than the threshold voltage Vth1 is applied, and detect logical "0" when an input signal having a voltage lower than the threshold voltage Vth1 is applied. When the supply voltage Vcc is 5.0 volt, for example, the threshold voltage Vth1 is about 1.5 volt.
FIG. 6C is a logic state diagram which defines logical level of general MOS circuits. When the supply voltage of Vcc=5.0 volt is applied, the MOS circuits generally determine logical "1" or "0" depending on whether or not an input signal has a voltage higher than the threshold voltage Vth2 (=Vcc/2), or 2.5 volt in this case. That is, when an input signal of a voltage higher than 2.5 volt is applied, logical "1" is detected, and when an input signal of a voltage lower than 2.5 volt is applied, logical "0" is detected. Therefore, the input buffers 91 to 9n shown in FIG. 6A are provided to convert input signals received from the TTL circuits 81 to 8n into signals Vout which are acceptable to the internal processing circuit 101 constituted of an MOS circuit.
FIG. 7 is a circuit diagram of the conventional input buffer circuits 91 through 9n shown in FIG. 6A. Since the input buffer circuits 91 through 9n are equal to each other in their circuit structure, a somewhat detailed description is given only to the input buffer circuit 91 in the diagram. Referring to FIG. 7, the input buffer circuit 91 comprises PMOS transistors 11, 12 and an NMOS transistor 13 which are connected in series between a power supply line 61 and a ground line 62. The gates of the respective transistors 12 and 13 are connected together to receive an input signal Vin. Another NMOS transistor 14 is connected between a connection node (referred to as output node No hereinafter) of the transistors 12 and 13 and the ground line 62. The gates of the transistor 11 and the transistor 14 are connected together to receive a signal S. The signal S includes, for example, a chip select signal CS. Therefore, the transistors 11 through 14 constitute an NOR circuit. In the following, however, since a description will be made on a case where a low level signal S is applied, the circuit comprising the transistors 11 through 14 can be regarded as an inverter. Between the node No and the ground line 62, there is further connected a capacitor 15 as indicated by broken line, which shows gate capacitance of the transistors connected in a subsequent stage contained, for example, in the internal processing circuitry and stray capacitance between the node No and the ground line 62. Resistances 21 and 22 represent inherent resistances in the wiring forming the circuit in the inverter.
In operation, one or the other of the transistors 12 and 13 is turned on in response to the input signal Vin to charge or discharge the capacitor 15. As a result, an inverted output signal Vout is developed.
FIG. 8 is a diagram showing the relation between the through current which flows through the input buffer 91 shown in FIG. 7 and the voltage of the input signal Vin, where 5.0 volts is applied as supply voltage Vcc. Since the input buffer 91 should have the characteristics compatible with the TTL circuit, the inverter comprising the transistors 12 and 13 is provided with such characteristics as shown in FIG. 6B. Therefore, the transistors 12 and 13 are substantially brought in the "ON" state when an input voltage Vin of approximately 1.5 volts is applied. Accordingly, the maximum through current Ip2 flows from the supply voltage Vcc toward the ground Vss through this inverter.
Meanwhile, in order to provide the input buffer 91 with the characteristics shown in FIG. 6B, it is designed in such a manner that the transistors 11 and 12 have smaller gate widths and the transistor 13 has a larger one. Accordingly, the transistors 11 and 12 have high on-resistances, while the transistor 13 has a low on-resistance. As a result, the logical level shown in FIG. 6B can be implemented.
FIG. 9 is a diagram for explaining that the supply voltage Vcc and the ground voltage Vss of the input buffer 91 fluctuate in response to the input voltage Vin, where the input voltage Vin varies from 0 to 5.0 volts. As shown in FIG. 8, the through current Ip of the input buffer circuit 91 attains the maximum value (Ip2) when the input voltage Vin of approximately 1.5 volts is applied so that this excessive current Ip2 causes a fall of the supply potential Vcc and a rise of the ground potential Vss. That is, the supply potential Vcc decreases by a potential V4 and the ground potential Vss increases by a potential V5. As a result, the logical threshold value of the inverter changes temporarily.
More specifically, the logic state of the TTL circuit shown in FIG. 10A changes to that shown in FIG. 10B. Referring to FIG. 10B, the supply potential temporarily changes from Vcc to Vcc' (=Vcc-V4), and the ground potential temporarily changes from Vss to Vss' (=Vss+V5). As a result, the logical threshold value temporarily changes from Vth1 to Vth1' (=Vth1+V6). A voltage difference V6 is caused by the fluctuation in the supply potential level and the ground potential level. The voltage difference V6 takes a value which meets the expression V11:V12=V21:V22 in FIGS. 10A and 10B.
Additionally, it is to be noted that the excessive current Ip2 appears as undesirable noise that has deleterious effects on the internal processing circuit 101. Furthermore, even the logical threshold values of circuits provided in the proximity of the input buffer 91 may change under the influence of such potential fluctuations.
FIG. 4 is a waveform chart showing, with respect to time, transition of the input voltage Vin and the output voltage Vout of the input buffer 91 shown in FIG. 7. As previously described, the input buffer 91 should have the characteristics shown in FIG. 6B so that it is set in such a manner that sum of the on-resistances of the transistors 11 and 12 is larger than that of the transistor 13 alone. Accordingly, it takes only a little time for the capacitor 15 to be discharged by the transistor 13 while it takes more for the same to be charged. As a result, as indicated by dotted line in FIG. 4, the output voltage Vout is delayed in rising. Consequently, it is to be understood that a high-speed operation of the semiconductor integrated circuit 100 is prevented by its own characteristics as shown in FIG. 6B.
USPTO Backgrounds
USPTO Backgrounds