The present invention relates to a data transfer system in a data processing system having a central processing unit (CPU).
The data transfer system includes a serial transfer system in which n-bit data (n being an integer) is transferred bit by bit sequentially from a low or high order bit, and a parallel transfer system in which n-bit data is simultaneously transferred in parallel. A floppy disk unit has been widely used as an external storage for a computer or the like. It employs the serial transfer system in which eight-bit data is serially transferred bit by bit. On the other hand, since the eight-bit data is processed in parallel in a data processing unit, a floppy disk controller includes a register connected to a data bus, and a shift register for parallel-to-serial conversion of the data placed between the register and the floppy disk unit.
A write operation of involving the writing eight-bit data into the floppy disk unit is now explained. The CPU reads in the eight-bit data from a RAM in accordance with a procedure stored in a ROM and sends out the data to the register. The data loaded in the register is transferred to the shift register in parallel, and the shift register transfers the data, bit by bit, at a constant interval in synchronism with a clock signal, to the floppy disk unit. After the register has transferred the data to the shift register, it sends a transfer request signal (flag bit) to the CPU requesting the next data transfer. In response to the request signal, the CPU reads out the data to be next transferred, from the RAM and transfers it to the register. When the data is loaded into the register, it extinguishes the transfer request signal and keeps the transfer request signal extinguished until that data has been transferred out. In this manner, the CPU responds to the transfer request signal to periodically load the data into the register. One CPU write operation needs a total of approximately 20 machine cycles (system clocks) including a step for checking the presence or absence of the transfer request signal, a step for reading the data to be loaded into the register into the CPU from the RAM and a step for loading the read data into the register. If a general purpose CPU operating at 1 MHz is used, approximately 20 microseconds are needed to complete each write operation. On the other hand, since the transfer rate of the floppy disk unit is usually 500K bits/sec (2 microseconds per bit), sixteen microseconds are needed to transfer the eight-bit data. Since the general purpose CPU cannot process twenty machine cyles in sixteen microseconds, a special and expensive high speed CPU must be used when the floppy disk unit is used. In order to avoid the above problem, a DMA system has been proposed in which the data is transferred not through the CPU but directly between the RAM and the floppy disk unit. In the DMA system, however, not only a DMA control IC, but also a bidirectional address bus buffer and data bus buffer and a control circuit for controlling the direction of the buffers are required. As a result, the circuit is of large scale and hence the DMA data transfer system is complex and expensive.
USPTO Backgrounds
USPTO Backgrounds