Integrated circuit technologies at 0.13 microns and below use thinner and longer wires thereby increasing wire-to-wire coupling capacitance. Due to capacitive coupling, a transition that occurs on a first net (aggressor) may be partially transmitted to a second net (victim), thereby resulting in a change in the delay in the victim, which may also include a change in logic transition in the victim. This cross-coupling effect (crosstalk) creates noise problem, which is especially pronounced at deep sub-micron processing such as 90 nm or below. Crosstalk causes glitches in static signals, delay variation in signals in transition and sometimes glitches are also possible on signals in transition.
Referring now to the drawings, FIG. 1 (prior art) shows driver circuits 102 and 104 drive receiver circuits 106 and 108 respectively. Coupling capacitance 140 affects the performance of nets 120 and 124 in that signal driven along net 120 induces a crosstalk glitch in net 124. Net 120 is therefore called an aggressor net and net 124 is understood as a victim net. It should be understood that coupling capacitance 140 is depicted as a lumped element for the sake of simplicity, it is in reality a distributed capacitance between the aggressor net 120 and victim net 124. As a result of the coupling capacitance, a signal with a sharp signal slope 128 may result in a noise glitch 126 in the victim net 124.
FIG. 1 shows a simplistic view of how crosstalk glitch affects a victim. When a signal transition occurs in neighboring wires, the coupling capacitance between the wires causes a transfer of charge from a net where a signal transition occurs to a net where no transition occurs. The former is called an aggressor net and the latter a victim net. The nature and intensity of the crosstalk glitches depend on the switching speed of the signals in the aggressor net, and the amount of mutual crosstalk capacitance between the wires. Though the aggressor net and victim net are shown as different tracks in the figure, it should be understood that each track may be formed from multiple segments that occupy multiple layers of metallization.
Known methods of minimizing crosstalk require a significant amount of place-and-route modifications that are often accompanied by design rule errors as well as timing issues to an already synthesized, placed and routed design, resulting in difficulties in design closure. That is because known methods work on all crosstalk victims in a design and attempt to fix them one by one, even though only a subset of victims (namely, those that drive either primary outputs or data inputs of flip-flops) will actually cause timing or functional failure. Therefore, there is a need for an improvement in the art.
USPTO Backgrounds
USPTO Backgrounds