1. Field of the Invention
The present invention relates to integrated circuit fabrication. More specifically, the present invention relates to a method and apparatus for compensating for effects of topography variation by using a variable intensity-threshold during an OPC process.
2. Related Art
Dramatic improvements in semiconductor integration circuit (IC) technology presently make it possible to integrate tens of millions of transistors, onto a single semiconductor IC chip. These improvements in integration densities have been achieved through corresponding improvements in semiconductor manufacturing technologies. In particular, advances in optical lithography technology have been driving IC chip feature sizes into deep-submicron ranges, with the help of Optical Proximity Correction (OPC) techniques.
Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to perfectly control these complex physical and chemical interactions, these processes typically have process variations that can cause the characteristics of the actual integrated circuit to be different from the desired characteristics. However, if a process variation is predictable and systematic, OPC techniques can be used to model this process variation and compensate for it by modifying the layout.
One such process variation relates to topography variation on a wafer surface, which can cause defocusing during an optical lithography process. During the optical lithography process, the optical exposure system and the wafer surface are configured so that the focal plane of the optical exposure system coincides with the surface of the wafer on which an in-focus aerial-image of the layout is desired to be printed. Topography variation on the wafer surface can cause portions of the wafer's surface to be above or below the focal place, which can result in the aerial-image to become defocused.
Generally, an optical exposure system can operate over a range of focus variation called “usable depth of focus” (UDOF), which is the amount of focus variation that can be tolerated while maintaining an acceptable lithography quality. UDOF is typically a function of both wavelength and numerical aperture (NA). However, as the wavelength continues to decrease and NA continues to increase, UDOF correspondingly decreases, making the lithography process more sensitive to the defocus caused by topography variations.
During exposure, an image of the layout is formed on photoresist coated on the wafer surface. The exposure creates different intensity profiles on the wafer's surface. Each type of photoresist has a certain intensity threshold, which is the amount of energy required to print features using the photoresist. The defocus caused by topography variation can cause the image intensity at a point on the wafer to be different from the image intensity that is expected under in-focus conditions. This can cause variations in the critical dimension (CD) of the printed patterns.
Unfortunately, current OPC techniques do not provide mechanisms to correct for such topography variations. As a result, the associated CD variations are carried to the downstream processes and eventually decrease the yield and performance of IC chips that are manufactured without correcting for such topography variations. Additionally, the CD variations due to topography variation can increase CD variations due to other process variations.
Specifically, during the optical lithography process, a process margin allows the printed features to vary within a tolerance around the design value. Even though the topography variation is not the only contributor to the lithography process margin, it has become an increasingly significant contributor due to shrinking UDOF. If the error introduced by topography variation can be corrected, designers and manufactures can have more process margin to cope with other types of process variations.
Hence, what is needed is a method and an apparatus to compensate for the effects of topography variations on the performance of semiconductor manufacturing processes without the above-described problems.
USPTO Backgrounds
USPTO Backgrounds