1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly, to a semiconductor integrated circuit device capable of supplying internal clock signals in various timings to internal circuit blocks and input/output latch circuits which operate synchronously with internal clock signals.
2. Description of the Background Art
In the field of semiconductor integrated circuit devices, with the advance of large scale integration and high speed operation of circuits, skews of clock signals are no longer ignorable. As the number of pins increases in response to such large scale integration of circuits, the magnitude of simultaneous switching noises poses a serious problem.
FIG. 21 is a block diagram showing an example of a conventional semiconductor integrated circuit device. Referring to FIG. 21, the LSI includes on a semiconductor substrate 100, a driver transistor 101, input buffer circuits 31, 32, and 33, input latch circuits 41, 42 and 43, internal circuit blocks 21, 22 and 23, output latch circuits 51, 52 and 53, and output buffer circuits 61, 62 and 63.
First internal circuit block 21 receives as an input an externally applied first input data signal I1 through first input buffer circuit 31 and first input latch circuit 41. A first output data signal O1 is output externally from the LSI from first internal circuit block 21 through first output latch circuit 51 and first output buffer circuit 61.
Similarly, second internal circuit block 22 receives an external second input data signal I2 through second input buffer circuit 32 and second input latch circuit 42. A second output data signal O2 is output externally from the LSI from second internal circuit block 22 through second output latch circuit 52 and second output buffer circuit 62.
Similarly, third internal circuit block 23 receives as an input an externally applied third input data signal I3 through third input buffer circuit 33 and third input latch circuit 43. A third output data signal O3 is output externally from the LSI from third internal circuit block 23 through third output latch circuit 53 and third output buffer circuit 63.
Driver transistor 101 receives an external clock signal CLK which is externally applied to the LSI. Driver transistor 101 provides a single internal clock signal to first to third input latch circuits 41 to 43, first to third internal circuit blocks 21 to 23, and first to third output latch circuits 51 to 53.
Now, operation of the LSI in FIG. 21 will be described. Driver transistor 101 responds to external clock signal CLK and outputs a single internal clock signal simultaneously to first to third input latch circuits 41 to 43, first to third internal circuit blocks 21 to 23, and first to third output latch circuits 51 to 53.
First to third input latch circuits 41 to 43, first to third internal circuit blocks 21 to 23, and first to third output latch circuits 51 to 53 operate in synchronization with the provided internal clock signal.
The operation will be described by way of illustrating the signal transmission path from first input buffer circuit 31 to first output buffer circuit 61. First input data signal I1 is applied to first input latch circuit 41 through first input buffer circuit 31. First input latch circuit 41 performs a prescribed latch operation in synchronization with the applied internal clock signal, and applies the applied first input data signal I1 to first internal circuit block 21.
First internal circuit block 21 performs a prescribed signal processing to first input data signal I1 in synchronization with the applied internal clock signal, and applies first output data signal O1 to first output latch circuit 51 as a result. First output latch circuit 51 performs a prescribed latch operation in synchronization with the applied internal clock signal, and applies the applied first output data signal O1 to first output buffer circuit 61 as a result. First output data signal O1 is output externally from the LSI through first output buffer circuit 61.
The operation of each element in the signal transmission path from second input buffer circuit 32 to second output buffer circuit 62 and the operation of each element in the signal transmission path from third input buffer circuit 33 to third output buffer circuit 63 are conducted similar to the operation of each element in the signal transmission path from first input buffer circuit 31 to first output buffer circuit 61 described above.
Such a conventional semiconductor integrated circuit device is encountered with the following problems for its configuration.
Firstly, difference in distances from driver transistor 101 to respective internal circuit blocks generates a clock skew for an internal clock signal between the internal circuit blocks, which results in erroneous operations when the LSI operates at a high speed.
Secondly, since all output data signals are outputted simultaneously in order that each output circuit can operate synchronously with a single internal clock signal, simultaneous switching noises are generated. The simultaneous switching noise is caused by currents which are passed through semiconductor substrate 100 in response to simultaneous switching operations of a plurality of output buffer circuits.
Thirdly, in a system for transmitting/receiving data signals between a plurality of LSIs, if a signal is delayed to different degrees between LSIs and yet the LSIs operate in the same operation timing, each LSI cannot appropriately receive a data signal output from another LSI for the delay of the data signal. In order to solve such a problem, input/output timings for data signals to/from LSIs must be different. In a conventional LSI, however, the operation timing of an input latch circuit and the operation timing of an output latch circuit are fixed. Changing input/output timings for data signals after LSIs are mounted onto the board requires troublesome operation of changing the phases of internal clock signals to be produced in the LSIs.
Finally, since in a conventional LSI input latch circuits have the same operation timing, if data signals are delayed differently for every signal line connected to each input latch circuit after the LSIs are mounted on the board, delay elements must be inserted in the signal lines in order to match the phases of data signals to be inputted to the input latch circuits. Similarly, if data signals are delayed differently for every signal line connected to each output latch circuit, a delay element must be inserted in each signal line in order to make the phases of output data signals in phase in an LSI to which that data signals are destined. Such insertion of delay elements in signal lines expands the mounting area of the circuit.
An invention related to a solution to clock skews between a plurality of LSIs for clock signals applied to the LSIs is disclosed, for example, in Japanese Patent Laying-Open No. 1-261018. The invention disclosed in the document includes within the LSI a delay signal generation circuit for generating a plurality of delay signals by delaying a clock input signal by small amounts, and a select circuit for selectively outputting a necessary delay signal from said plurality of delay signals. According to the document, the delay signal generation circuit and the select circuit adjust clock skews between a plurality of LSIs operating synchronously with a clock input signal.
As an invention directed to a solution to interphase skews in internal clock signals of a plurality of phases generated based on an external clock signal is disclosed, for example, in Japanese Patent Laying-Open No. 2-194721. The invention disclosed in the document includes a frequency dividing circuit for frequency-dividing an external clock signal and a differential circuit receiving the output signal of the frequency dividing circuit. According to the document, internal clock signals of a plurality of phases with reduced interphase skews are generated based on an external clock signal by the provision of these circuits.
These two inventions concern a solution to a clock skew between a plurality of clock signals by delaying clock signals. Accordingly, application of such techniques generates a plurality of internal clock signals of difference phases by delaying the external clock signal bit by bit in the signal generation portion, and clock skews between internal circuit blocks would be solved by these internal clocks supplied to a plurality of internal circuit blocks spaced at different distances from the signal generation portion, respectively.
However, an LSI in which a plurality of internal clock signals of difference phases are simply generated for application to internal circuit blocks is further encountered with the following problem. The problem will be described.
FIG. 22 is a block diagram showing part of a transmission path for clock signal and a transmission path for internal data signal in a conventional LSI. In FIG. 22, transmission paths for internal clock signal and data signal through a clock buffer circuit 102, an output latch circuit 54, and an output buffer circuit 64 are shown as examples of such transmission paths for clock signal and data signal.
Clock buffer circuit 102 generates an internal clock signal in response to an external clock signal CLK. Output latch circuit 54 receives the internal clock signal and a data signal applied from an internal circuit block (not shown), performs a latch operation for the data signal in response to the internal clock signal and outputs the data signal as output data signal O through output buffer circuit 64.
FIG. 23 is a waveform chart showing signals at respective elements in the LSI in FIG. 22. The waveforms shown in FIG. 23 are those of external clock signal CLK, an internal clock signal a at an output node of clock buffer circuit 102, an internal clock signal b at an input node of output latch circuit 54, a data signal c at an output node of output latch circuit 54, and output data signal O.
Referring to FIG. 23, problems associated with the above-described two inventions will be described.
Internal clock signal a has a delay Dcb from external clock signal CLK through clock buffer circuit 102. Internal clock signal b has a delay Dline from internal clock signal a through the interconnection from clock buffer circuit 102 to output latch circuit 54. Data signal c has a delay Dol from internal clock signal b which corresponds to the period from a rising of the internal clock signal to latch output in output latch circuit 54. Output data signal O has a delay Dob from data signal c through output buffer circuit 64.
With these delays, the delay Dtotal of output data signal O with respect to external clock signal CLK is the total of all the delays Dcb, Dline, Dol, and Dob. Such delays Dcb, Dline, Dol, and Dob each fluctuate with temperature and process irregularities. The above two inventions therefore cannot prevent the variance of output timings for output data signals in the LSI.
Such delays for output data signals with respect to an external clock signal is disadvantageous for following reasons.
FIG. 24 is a block diagram showing the configuration of a CPU and a plurality of LSIs which operate in synchronization with a common system clock. Referring to FIG. 24, CPU 300, first LSI 301 and second LSI 302 are connected to a common bus 304. CPU 300, first LSI 301 and second LSI 302 operate in synchronization with a system clock signal (external clock signal) and transmit/receive data between them.
In operation, when one of first LSI 301 and second LSI 302 outputs data, the output of the other is brought to a high impedance state, in order to avoid collision of the data outputted from first LSI 301 and data outputted from second LSI 302.
The operation will be described. FIG. 25 is a timing chart for use in illustration of a normal operation state of the system shown in FIG. 24. FIG. 25 includes a system clock signal SC, the data output signal A of first LSI 301 and the output data signal B of second LSI 302.
Referring to FIG. 25, first LSI 301 and second LSI 302 output data signals A and B in synchronization with system clock signal SC. In this case, when one LSI outputs data d, the output data signal of the other LSI attains a high impedance HZ. Thus, data d outputted from first LSI 301 does not collide with data d outputted from second LSI 302.
In the following case, however, data d outputted from these two LSI 301 and 302 collide with each other. FIG. 26 is a timing chart for use in illustration of an abnormal operation of the system shown in FIG. 24. FIG. 26 also includes system clock signal SC, the output data signal A of first LSI 301, and the output data signal B of second LSI 302. FIG. 26 shows an example of an abnormal operation of the system in FIG. 24, in which the output data signal B of second LSI 302 is delayed from the output data signal A of first LSI 301.
Referring to FIG. 26, when output data signal B is delayed by delay Dtotal from the external clock signal, system clock signal SC as described above, data d collide with each other in a period t1 as a result of delay Dtotal.
In order to prevent such collision of data d, the output timing of output data signal A must be delayed such that output data signals A and B are in phase. However, the delay Dtotal of the output data signal with respect to the external clock signal fluctuates depending upon temperature and process irregularities as described above. Therefore, adjusting delay Dtotal requires readjustment of the system after designed (after actually mounted on the board).
Now, problems associated with delays of output data signals from the external clock signal will be described. FIG. 27 is a block diagram showing a system in which data signals are transmitted/received between at least three LSIs.
Referring to FIG. 27, the system includes a first LSI 401, a second LSI 402, and a third LSI 403. A first interconnection line 1 is provided between first LSI 401 and second LSI 402. A second interconnection line 2 is provided between first LSI 401 and third LSI 403. A third interconnection line 3 is provided between second LSI 401 and third LSI 403.
Now, the operation of the system in FIG. 27 will be described. The output data signal of first LSI 401 is applied to second LSI 402 through first interconnection line 1 and to third LSI 403 through second interconnection line 2. The output data signals applied to second and third LSIs 402 and 403 are simultaneously output from first LSI 401. Third LSI 403 performs data processing for 1 clock to the applied output data signal, and applies the resulting output data signal to second LSI 402 through third interconnection line 3.
Such a system is encountered with the following problem due to delays of output data signals with respect to an external clock signal. FIG. 28 is a timing chart for use in illustration of the operation of the system in FIG. 27.
FIG. 28 includes a data signal AO at an output node on the side of first interconnection line 1 in first LSI 401, a data signal BI1 at an input node on the side of first interconnection line 1 in second LSI 402, a data signal BI2 at an input node on the side of third interconnection line 3 in second LSI 402, a data signal CI at an input node of third LSI 403, and a data signal CO at an output node of third LSI 403.
Referring to FIG. 28, data A1, A2, . . . are sequentially outputted from first LSI 401. Data signal BI1 has a delay Dline 1 through first interconnection line 1. Data signal CI1 has a delay Dline 2 with respect to data signal AO through second interconnection line 2. Data signal CO has a delay Dchip with respect to data signal AO by a delay of the data signal within third LSI 403. Data signal BI2 has a delay Dline 3 with respect to data signal CO through third interconnection Dline 3.
In this case, second LSI 402 can receive the data A2 of data signal BI1 and the data C1 of data signal BI2 at a time in a period T2 (=T-Dchip) produced by subtracting delay Dchip from the cycle T of external clock signal. This however applies only if delay Dline 1 is equal to delay Dline 3. In this system, as delay Dtotal in third LSI 403 increases, delay Dchip increases as well. As delay Dchip increases, cycle T2 increases.
In this system, second LSI 402 must receive the data signal applied from first LSI 401 and the data signal applied from third LSI 403 at a time. To this end, the timings of the data signals from first LSI 401 and third LSI 403 must be equalized by insertion of an additional element such as a delay element to first interconnection line 1 after the system is designed.
The above-described two inventions are also encountered with another problem. More specifically, an external clock signal and an internal clock signal cannot be in phase. A still another problem is encountered. More specifically, once the duty cycle of the external clock signal applied to the LSI is below 50% by the influence of temperature changes and electrical characteristics of signal transmission paths provided externally to the LSI, the duty cycle cannot be recovered to 50%.
USPTO Backgrounds
USPTO Backgrounds