Since the invention of integrated circuits, many improvements have been made in reducing the size of components of integrated circuits as well as increasing the speed of those components. At present, it is common for integrated circuits to have minimum features with lengths as short as 1 micron. Sub-micron features are currently in production and will soon be commonplace.
The size of features on an integrated circuit is highly dependent upon the apparatus used to fashion such features. Most integrated circuits are fashioned using an optical lithography apparatus including projection aligners and reduction steppers. Projection aligners simultaneously expose an entire wafer to an optical mask. However, when using standard photoresists, the minimum line width of such aligners is about two microns. In order to achieve smaller geometries of 1 micron or less, the optical lithography tool most often used is an optical reduction stepper. Such equipment is very expensive and tends to obsolete existing projection aligners. Steppers expose only a predetermined field on a given wafer to an optically reduced mask. The wafer is then stepped beneath an exposure station so that the field of exposure may be stepwise repeatedly exposed on the wafer.
A number of techniques have also been proposed for sub-micron lithography including the use of electron beam lithography. However, electron beam lithography is slow and requires expensive electron beam equipment. Another technique is x-ray lithography. However, x-ray lithography equipment is also expensive and is still in its developmental stage. Still another solution relies upon the use of phase shift masking to achieve narrow lines at reduced expense. However, there remains an unmet desire for a method that can use a projection aligner with ordinary photoresist to achieve sub-micron geometries of features including geometries of 1/2 micron or less.
USPTO Backgrounds
USPTO Backgrounds