PFC circuits are widely used in power converting systems to correct the phase of the input current to improve the power factor and to reduce the power loss. The definition of power factor (PF) is the ratio of average power to apparent power, i.e.:
  PF  =                    average        ⁢                                  ⁢        power                    apparent        ⁢                                  ⁢        power              =          cos      ⁢                          ⁢      θ      ⁢                          ⁢              1                              1            +                          THD              2                                          wherein θ represents the phase difference between the input line voltage and the input current, and THD represents the total harmonic distortion of the input current. Controlling the phase difference θ to be zero is highly required.
FIG. 1 schematically shows a traditional PFC circuit 50. As shown in FIG. 1, the PFC circuit 50 comprises: a first input port 11 and a second input port 12, configured to receive an input line voltage Vin, wherein the input line voltage is typically a sine wave; a rectifier 13, coupled to the first input port 11 and the second input port 12 to rectify the input line voltage Vin to a rectified voltage Vz (i.e., a half sine wave); an input capacitor 14, coupled between the rectifier 13 and a reference ground; a power switch circuit 15 including at least a power switch, wherein the power switch circuit 15 is coupled to the rectifier 13 to receive the rectified voltage Vz, and to generate a desired output voltage VO to power a load based on the rectified voltage Vz; and a control circuit 16, configured to receive a voltage sense signal Vifb indicative of the input line voltage Vin, a current sense signal indicative of a current flowing through the power switch circuit 15, and the output voltage VO, to generate a control signal to control the power switch, so as to get the desired output voltage VO.
When the PFC circuit 50 is in operation, there is a current ic flowing through the input capacitor 14. However, the control circuit 16 is configured to receive the current sense signal indicative of the current flowing through the power switch circuit 15, but not to receive an input current iin of the PFC circuit 50. So the current flowing through the power switch circuit 15 is corrected to be in-phase with the input line voltage Vin and/or with the rectified voltage Vz by the PFC circuit 50. The timing waveforms of the input current iin in the PFC circuit 50, the current ic flowing through the input capacitor 14, the current is flowing through the power switch circuit 15, and the rectified voltage Vz are shown in FIG. 2. That is, there still exists relatively large phase difference between the input current and the input line voltage under traditional PFC control. FIG. 3 schematically shows the phase diagrams of the input line voltage Vin, the current is flowing through the power switch circuit 15, the current ic flowing through the input capacitor 14 and the input current iin in the PFC circuit 50.
As a result, the input capacitor influences the power factor as well as the THD in prior art. The higher the capacitance of the input capacitor, the lower the power factor, especially under light load condition.
USPTO Backgrounds
USPTO Backgrounds