The present invention relates to computers and, more particularly, to testing computer systems fabricated on an integrated circuit. A major objective of the present invention is to provide computer-system-on-a-chip designs with enhanced built-in testability.
Much of modern progress is associated with the increasing prevalence of computers, including embedded controllers as well as general-purpose computers. A typical computer includes a processor, memory, and peripherals that communicate with each other over a system bus. In many computers, the processor, memory, and some peripherals are embodied in separate integrated circuits. However, with advances in integrated-circuit manufacturing technology allowing millions of transistors on an integrated circuit, it is now practical to build computer systems on an integrated circuit (chip). Instead of assembling separate integrated circuits on a printed-circuit board, computers can be designed by assembling functional blocks on an integrated-circuit layout.
Testing of complex integrated circuits, such as single-chip computers is an essential and formidable task. While the functional block designs are often well characterized, they are subject to manufacturing defects. In addition, each circuit design represents a novel arrangement of functional blocks that requires testing both for design integrity and for defects in the connections between function blocks.
The prior art provides a default method for testing a computer system. A test program can be run on the computer processor, which can write to peripherals coupled to the system bus and then read from the system bus to determine if the expected results occur. While much can be accomplished with this approach, it is typically not effective at testing non-system-bus connections between on-chip peripherals or between on-chip peripherals and off-chip devices. Likewise, on-chip functions that rely on non-system-bus inputs, e.g., communications from a modem, can be hard to evaluate. Accordingly, several approaches to augmenting this processor-based testing approach have been considered.
One prior-art xe2x80x9cmultiplex-to-pinsxe2x80x9d approach is to multiplex the input-output ports of functional blocks to provide controllability of input and observability of outputs. This allows for external test equipment to test the non-system bus connections. A major problem with this multiplex-to-pins approach is that it precludes many possible test combinations. Tests requiring more than one use of a pin at a time cannot be performed. If a pin is used to access an internal connection, its normal use is precluded. Likewise, if a pin is multiplexed to more than one internal connection, only one of these may be accessed at a time. Even with careful assignment of pins to internal connections, the restrictions on test combinations can be prohibitive. Typically, only a single peripheral is tested, not its connections to the rest of the system, thus degrading a key goal of the test. In addition, the multiplex-to-pins approach requires flexible test hardware to map peripheral test patterns to pinsxe2x80x94since that mapping varies from device to device.
In addition, this multiplex-to-pins approach becomes less practical as the number of internal connections increases relative to the number of pins. Multiplexing internal connections to pins consumes routing resources, and the inter-blocks routes tend to be very costly in terms of area. Moreover, non-test application performance can be adversely affected not only by the additional multiplexers, but also by the parasitic capacitances along the paths between the input-output ports and the pins.
Scanning approaches introduce data serially and read out the results serially, thus avoiding much of the routing complexity of the multiplex-to-pins approach. JTAG (xe2x80x9cJoint Test Action Groupxe2x80x9d) is a standardized test-interface specification for the scanning. The JTAG specification requires a five-pin interface to test equipment. These pins are xe2x80x9cserial test-data inxe2x80x9d (TDI), xe2x80x9cserial test-data outxe2x80x9d (TDO), xe2x80x9ctest clockxe2x80x9d (TCK), xe2x80x9ctest resetxe2x80x9d (TRST), and xe2x80x9ctest-mode selectxe2x80x9d (TMS). Thus, the number of pins required for testing using the prevailing scan approaches is small and fixed. Thus, problems with routing and test-pin count are vastly reduced compared to the multiplex-to-pins approach.
The vast majority of complex chips use a xe2x80x9cfulls scanxe2x80x9d approach to test for manufacturing faults. In the full-scan approach, all registers, including those internal to functional blocks, are arranged in a serial shift chain. Typically, the order of registers in a full-scan serial-shift chain is not determined as part of the design process, but as an automated post-design procedure. Due to the functionally arbitrary order and large number of registers involved, functional testing using the full-scan approach is impractical. Instead, functional testing is achieved by simulation, and the full scan is used to check for manufacturing faults. Furthermore, scan approaches are destructive in nature, since old state data will be shifted out as new data is shifted in.
The simulation used for design validation and the full scan used for finding manufacturing faults are performed before an integrated circuit is integrated into a system. Configurations not anticipated in the simulation are not tested. Latent manufacturing defects that become overt during use (e.g., due to gradual electro-migration) may not be detected by the full scan. In addition, in view of the large amount of shifting required, the full scan can be very time consuming.
The prior-art also reaches a more limited xe2x80x9cperipheral-scanxe2x80x9d (also known as xe2x80x9cpartial-scanxe2x80x9d or xe2x80x9cscan-wrapperxe2x80x9d) approach. In the peripheral-scan approach, non-system-bus functional block ports are multiplexed to latches or registers arranged in a serial shift chain. Test data can be shifted in from external test equipment, a clock cycle run to clock data into the peripheral and capture outputs, and then the data can be shifted out to the external test equipment. Thus, the peripheral-scan approach can be used for functional testing. However, scanning data in and out is still quite time consuming.
The approaches discussed above all involve difficult tradeoffs. While the full-scan is relatively comprehensive in the components it can test, it is impractical to use it for functional testing. On the other hand, while a peripheral-scan allows for functional testing, the range of components that are tested is more limited than it is for the full-scan approach. The multiplex-to-pins approach is faster, but is costly in terms of routing resources.
A bus-access approach couples external testing equipment a system bus. Each module to be tested has a test harness with test registers. Each test register can be associated with a module input or outputs. During testing, these registers are coupled to the system bus so that they can be accessed by the external test equipment. Such a test approach is disclosed by Arm Limited in xe2x80x9cAHB Example AMBA System Technical Reference Manualxe2x80x9d. This document was obtained in the year 2000 the Arm, Limited website at www.arm.com. The document is copyrighted 1999, and no publication date is given.
The bus-access approach is faster than the scan approaches and consumes fewer routing resources than does the multiplex-to-pins approach. However, Arm""s implementation still requires thirty-six dedicated pins, which is costly in terms of packages and board area.
The bus-access, scan and the multiplex-to-pin approaches share many limitations. A salient limitation is the requirement for dedicated testing equipment. The testing equipment is expensive. The requirement of the external testing makes it impractical to test circuits once they are in use, which, in turn, makes it difficult to test in the context of signals associated with normal use.
More generally, the bus-access, scan, and multiplex-to-pins approaches all require a test mode in which conditions are very difficult from normal operation. Functional modules are not performing their normal functions and none of the circuitry being tested is operating at normal speed. Thus, many problems that could occur during normal functioning at normal operating speed may not occur under test conditions. Thus, differences between test conditions and normal operating conditions limit test comprehensiveness.
Summarizing the known prior art, the multiplex-in-pins and scan approaches expand upon the default processor-based approach to testing integrated circuits generally, and system-on-a-chip computers specifically. The multiplex-to-pins approach allows relatively rapid testing; however, it imposes severe limits on combinations of inputs that can be applied during testing, and it can be expensive in terms of routing resources. The scan approaches allow data to be scanned or shifted to and from the non-system-bus ports; this approach is less taxing on routing resources and less restrictive of the test inputs. However, the serial scanning of data into and out of the integrated circuit is time consuming. Sophisticated test software is required to stimulate and observe specific areas of the design. All these approaches are limited by the requirement of dedicated test equipment and test conditions that are very different from normal operation.
What is needed is a novel approach to enhancing the default testing that does not require external testing equipment. Preferably, the novel approach would be less taxing on routing resources than is the pin-multiplexing approach. Also, preferably, the novel approach would be less time-consuming than the scan approaches. Finally, it is desired that testing under near-normal operating conditions be available after an integrated circuit is installed in an incorporating system.
The present invention provides for system self-testing in which a processor has access via a system bus both to bus and non-bus connections. The non-bus connections are made accessible through the bus during testing (but not during execution of normal application programs) via multiplexers. The invention is especially applicable to embedded controllers and system-on-a-chip computers. The computer system includes a processor, a system bus, and a set of peripherals, all of which can be fabricated on a single integrated circuit.
The system also includes test-driver multiplexers and test-driver registers. Each register has a data input coupled to the system bus and a control input coupled to an address decoder. The address decoder decodes addresses asserted by the processor to determine when to enable the register so that it can be written to.
One of the integrated peripherals is connected either to one of the multiplexer data inputs or to the multiplexer output. The other of these two multiplexer ports is coupled to another functional module. This other functional module can also be one of the integrated peripherals or it can be a non-peripheral on-chip functional module or it can be an external device. The remaining multiplexer data input is coupled to an output of said register.
Preferably, the multiplexer control input is also coupled to an output of said register, in this case, the control input and the second data input respond to different bit positions of a value stored in the register. Alternatively, another means can be used to control the multiplexerxe2x80x94e.g., the address decoder in response to a separate address assigned to control the multiplexer.
During execution of an application program, the test-driver multiplexer is set so that the peripheral and the functional module are connected. During execution of a test program, the test-driver multiplexer can be controlled so that the test-driver is selected as the active multiplexer input. In this case, the data value is provided to whichever functional module is connected to the test-driver multiplexer output.
The invention provides a method in which a test program is initiated, data is written to a test-driver register via the system bus, a test-driver multiplexer is switched to connect the test-driver register output to a non-system-bus connection, and then the result of the test is read by the processor via the system bus. The reading of a test result can take different forms. In some cases, the result can be read by the processor via a system bus connection that is normally in place during execution of an application program. For example, the test can involve conveying the test data to a non-system-bus input of a system-bus-peripheral that, as a matter of course, makes the result available via the system bus.
If the peripheral receiving the test data is not connected to the system bus or does not provide the result of interest to the system bus as a matter of course, a test sampler can be used. For signals that can be statically controlled or that change slowly enough that polling by the processor will not miss any important states, a test sampler can involve a tap from a non-system-bus connection to a multiplexer having an output to the system bus. To observe transient states, sample-and-hold circuitry, trigger logic, and/or edge-sensitive logic can be used. In response to a read request, the multiplexer can be controlled to select the test-sampler as a bus input so that the processor can read non-system-bus data.
The invention provides for incorporating test drivers and/or test samplers in module function blocks for optimal design convenience in providing enhanced testability of computers systems on a chip. However, for function blocks not including required test drivers or test samplers, these can be provided external to the function blocks as part of a dedicated test-mode controller peripheral. The required registers can be written to by addressing the test-mode controller peripheral, which also controls the associated test-driver multiplexers.
A major advantage of the present invention over the default processor-based testing scenario is that there is direct testability of ports not normally addressable by a processor over a system bus. The invention consumes fewer routing resources than does the multiplex-to-pins approach, and it much less time consuming than the scanning approach. In part because of its speed, the present invention makes comprehensive functional testing practical, in contrast to both the peripheral-scan approach and the full-scan approach.
A major advantage over the alternative enhancements to the default approach is that no external testing equipment is required. Moreover, tests can be run in context and at normal operating speeds so that test conditions more closely compare to normal operation. Accordingly, the validity of test results is enhanced.
Furthermore, test drivers and samplers can be selected individually; and unselected circuitry can functional normally and at full speed. The precision with which tests can be directed permits testing to go beyond merely determining whether or not an integrated circuit functions as intended; the present invention allows faults to be isolated. In other words, the present invention allows not only validation but also debugging of circuitry. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.
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