1. Field of the Invention
This invention relates to delay cells and, more particularly, to differential delay cells with reduced power, jitter and area. The differential delay cells may be incorporated, e.g., within a voltage controlled oscillator (VCO) of a phase locked loop (PLL) or a delay line of a delay locked loop (DLL).
2. Description of the Related Art
The following descriptions and examples are given as background only.
Phase-locked loops (PLLs) and delay-locked loops (DLLs) are routinely used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. In some cases, for example, PLLs and DLLs may be used in the I/O interfaces of digital integrated circuits to hide clock distribution delays and to improve overall system timing. In general, a PLL or DLL may be used to generate one or more clocking signals that are in phase alignment with a reference clock. More specifically, a PLL is a closed-loop device that uses a voltage-controlled oscillator (VCO) to obtain accurate phase alignment between a reference signal and the clock signals generated by the PLL device. A DLL device, on the other hand, generally differs from a PLL device in that it uses a delay line, instead of a VCO, to obtain accurate phase alignment between the reference and clocking signals.
Unfortunately, the rising demand for high-speed electronics has created an increasingly noisy environment in which PLLs and DLLs must function. Deterministic noise and random noise are two examples of noise components, which may cause the output clocks of a PLL or DLL to “jitter” from their ideal timing. Deterministic noise is described herein as noise that originates from a known source, such as power supply noise or substrate noise. Examples of random noise include, but are not limited to, thermal noise and flicker noise. Jitter is undesirable because it often leads to decreased stability around the operating frequency (or “center frequency”) of the PLL/DLL device. With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter PLLs and DLLs has become very challenging.
Many solutions have been proposed to improve the phase noise performance of the voltage controlled oscillators (VCOs) within PLLs. As one example, phase noise (e.g., random noise generated primarily in the VCO) may be reduced by setting the loop bandwidth as high as possible. Unfortunately, the loop bandwidth is affected by many process technology factors, and as a result, is often constrained well below the lowest operating frequency needed for stability. This solution may also cause the PLL to have a narrow operating frequency range (since the loop bandwidth depends on the VCO gain). Although VCOs have recently been fabricated using CMOS technology to obtain higher operating frequencies (e.g., several Gigahertz, GHz) and to meet the increasing demand for lower cost and higher integration, phase-noise reduction remains a challenge for typical CMOS voltage controlled oscillators.
For example, CMOS LC-tank oscillators with on-chip spiral inductors have been used in the past to improve phase noise performance. Although CMOS LC-tank oscillators provide some improvement in phase noise performance, they have not been able overcome several barriers preventing them from becoming a reliable VCO. One such barrier is that the implementation of a high-quality inductor in a standard CMOS process is limited by parasitic effects and usually requires extra non-standard processing steps. Another barrier is that the LC-tank oscillator often demonstrates a narrow tuning range, causing PLL performance to be sensitive to process variations.
Unlike the LC-tank oscillator, a ring oscillator may be integrated into a standard CMOS process without requiring extra processing steps (since it does not require passive resonant elements). In addition, a wide operating range can be obtained when the ring oscillator is employed as a VCO. However, the ring oscillator is not without limitations and usually demonstrates worse phase noise performance than the LC-tank oscillator. In some cases, differential delay cells have been used within ring oscillators to reduce phase noise levels. However, conventional delay cells consume large amounts of current and area, and often fail to reduce phase noise components to acceptable levels.
As indicated above, solutions have been implemented to reduce the amount of phase noise (i.e., random noise) generated within the VCO of a PLL device. However, phase noise is not the only noise component which contributes to jitter within the PLL—deterministic noise must also be reduced. Therefore, a need remains for an improved architecture and method for reducing all noise components, which may cause a PLL or DLL to jitter from their ideal timing. Such noise components may include, for example, random and deterministic noise. In one preferred embodiment, an improved delay cell architecture, which consumes less current and area and provides better jitter performance than conventional delay cell architectures, is desired. Such a delay cell architecture may enable a PLL or DLL device to meet (and/or exceed) the current, area and jitter specifications required for optimal operation of the PLL or DLL device.
USPTO Backgrounds
USPTO Backgrounds