The implementation of dynamic circuit topologies in modem microprocessors brings with it a series of technical challenges that must be overcome in order to show that the actual operation of the circuit matches the logical specification for that circuit. In situations where the details of the circuit have not been sufficiently managed, the actual operation of the device can be very different from the intended functionality. Typically, the areas for concern for a circuit designer include node leakage, input noise sensitivity, and charge share protection. To discuss each of these areas of concern, a description of a typical dynamic circuit will be subsequently provided.
FIG. 1 illustrates a standard dynamic circuit which implements a logical AND function (F=A*B). For a dynamic circuit such as that illustrated in FIG. 1, two functional phases must be executed correctly for the circuit to perform as desired. These two functional phases include a pre-charge phase and an evaluate phase. The evaluate phase is that portion of a processor clock cycle in which the circuit performs its desired logic function, and is defined by a clock signal having an active high voltage level. For instance, if a two-input AND gate is used to implement the logic function, F=A*B, the output "F" will properly represent that logic function only during the evaluate phase, since the output of the circuit can only be active high when a clock input has an active high level. The pre-charge phase is defined as the portion of the processor cycle that sets the clock signal to a low voltage level. The pre-charge time has the function of preparing the circuit for correct operation during the crucial evaluate phase by setting the voltage levels of internal nodes of the circuit to logic levels which will ensure correct functionality during the following evaluation stage. More specifically, the pre-charge phase will set the voltage on the internal nodes, such as N1 (illustrated in FIG. 1), to a logic high level. During the pre-charge phase, the voltage level on the internal nodes are set by a pull-up transistor M3 (102) that is active when the clock signal has a logic low value. Since the output of AND circuit 100 is the inverse of node N1, an output of AND circuit 100 will be a logic low during the pre-charge phase. When AND circuit 100 enters the evaluate phase, the clock signal will be active high, and the logic levels of inputs A and B will determine whether the internal node N1 is discharged to an electrical ground level. If node N1 transitions to a logic low value, the output of AND circuit 100 will be a logic high value, completing the generation of the intended logic function.
From this basic description of operation of dynamic AND circuit 100, several complications can be added to increase the design complexity of AND circuit 100 substantially. One such complication is derived from the fact that the voltage level set during the pre-charge phase on node N1 is not actively sustained during the evaluate phase since the clock signal will be a logic high level (by definition) during the evaluation phase. By providing the clock input at a high logic level on the gate of transistor (M3) 102, transistor (M3) 102 will be disabled from conducting electrical current. If input data A is at a logic low value, it may be observed that the conditions for transistor (M1) 104 and transistor (M3) 102 will combine to cause the voltage on node N1 to be controlled by secondary electrical effects. During the time in which node transistors actively control the voltage level of node N1, the voltage level on node N1 will be maintained by the node capacitance at that location. However, the material characteristics of the transistors involved in the design of AND circuit 100 will cause the electrical charge that has been stored on node N1 to leak away at a rate which will cause problems in the operation of this AND gate 100. If node N1 is allowed to drop in voltage to the level of the switching point of inverter 110, an improper output transition will occur. The transition is improper because it is not based on the value of input A and B, but is based only on a rate of decay of the voltage on internal node N1. Although several approaches may be used to solve this problem, the most common solution is the addition of a feed back transistor. Such a configuration is illustrated in FIG. 2.
In FIG. 2, the feedback transistor is transistor (M4) 212. Transistor (M4) 212 will offset any leakage current from the previously described mechanism and will, therefore, prevent invalid output transitions of that nature. Therefore, through the addition of transistor (M4) 212, the problem of leakage has been solved.
A second issue which faces dynamic circuit designs is that of charge share. As was previously mentioned, the voltage on node N1 is sustained by the capacitance of that node. Since this capacitance is formed, in part, by the diffusion of transistor (M1) 204, transistor (M3) 202, and transistor (M4) 212 implanted during processing steps, it may be understood that there will be some capacitance present on node N2 for the same reason. In addition, as was previously noted, a functional problem can occur when the voltage on node N1 is allowed to drop to a level near the switching threshold of the output inverter. By recognizing these two insights, another important circuit design consideration can be easily described. From basic electrical theory, it may be observed that when a charged capacitor and an uncharged capacitor are brought into parallel contact, there will be a redistribution of charge that will cause the final voltage on the two capacitors to be identical. This situation is illustrated in FIG. 3-A, which illustrates two capacitors (C1 and C2), connected by an electrical switch.
As is illustrated in FIG. 3-A, capacitor C1 has a voltage at V1 and capacitor C2 has a voltage of zero volts before the electrical switch is used to couple the two capacitors together. After the switch is closed, a final voltage for both capacitors (C1 and C2) will transition to a new value, V.sub.2. From electrical theory, it may be illustrated that the value of V.sub.2 can be found by using the following equation: ##EQU1##
The resultant sharing of charge among capacitors C1 and C2 is illustrated in greater detail in FIG. 3-B. The situation illustrated in FIGS. 3-A and 3-B is similar in concept to the charge share problems that are routinely encountered by circuit designers. Specifically, the N1 node will be pre-charged to a high logic level and node N2 will have a voltage between V.sub.DD and an electrical ground value. If node N2 is at a voltage near zero volts, input A is active, and input B is inactive, a charge that has been stored in the capacitance on node N1 will be shared between nodes N1 and N2. Equation (1) provided above predicts a final voltage, V2, that will be present on nodes N1 and N2, when secondary effects are neglected. If the capacitance of node N2 is comparable to that of node N1, the voltage level on node N1 may drop below the switching threshold of the output inverter and cause an incorrect output transition. As with the previously described scenario, such charge sharing is unallowable because the output of AND circuit 200 will no longer be a proper representation of the input signals thereto. For this reason, a degree of charge sharing present in a circuit must be kept within a manageable range. It is worth noting that charge sharing cannot totally be eliminated without the addition of additional circuit elements.
While it is possible to use standard design techniques to minimize the node capacitance on node N2, and thereby minimize charge share, such techniques are only practical to the amount of benefit they will allow for proper operation of the circuits. Therefore, many circuit designers use additional design elements to ensure the voltage on node N2 (in this example) is substantially higher than the zero volt level used in the previous example. Typically, this requires the addition of a transistor that will also pre-charge the N2 node during the pre-charge phase of operation. An example of this circuit is illustrated in FIG. 4.
AND circuit 400 of FIG. 4 effectively tackles the charge share problem. In FIG. 4, transistor (M5) 414 has been added to pre-charge node N2 and is used at the same time that node N1 is pre-charged to a logic high level. Of primary concern is the fact that the charge placed on node N2 by transistor (M5) 414 will be subject to leakage in the same manner that charge placed on node N1 by transistor (M3) 402 was subject to leakage in the earlier example. If the charge from node N2 leaks away during an evaluation phase when the Clock signal has disabled transistor (M5) 414, then the potential for charge sharing is as great as it would be without the addition of transistor (M5). In that case, little protection is offered by transistor (M5) 414. Furthermore, it should be noted that during high-temperatures, slow clock rate operation such as would be observed in a manufacturing test, the leakage on nodes N2 and N1 will be greatly increased. It should also be noted that the use of an n-channel device in such circuit implementations is superior to a p-channel device in terms of its effect on circuit evaluation time. However, the n-channel device still may have charged leakage concerns during the evaluation phase and must be driven by a clock signal. For this reason, the use of a single clock-gated device, whether n-channel or p-channel, is to be avoided.
Therefore, the fact that transistor (M5) 414 is enabled by the Clock signal presents serious operational concerns. It should be noted that while an AND circuit is illustrated in FIG. 4, this disadvantage also applies to other circuits implemented using a similar methodology. For these reasons, the circuit implementation illustrated in FIG. 4 provides insufficient charge share protection.
The solutions for circumventing the charge share issues described above have suffered from charge leakage problems related to the deactivation of such anti-charge sharing devices during the evaluation phase. It is possible to change a topology of circuits such as AND circuit 400 to allow the anti-charge sharing devices to be active during evaluation or during some other time period. It may be observed that activating the pre-charge devices, such as transistor (M5) 414, only during the evaluation phase will not provide sufficient time to pre-charge internal nodes, such as node N2, before an evaluation event occurs. Such an evaluation event will occur when input A or B transitions from one logic state to another. Because this alternative will not operate in a correct manner, this alternative will not be considered in greater detail. Additionally, a feedback loop with an inverter could be used for node N2, as was done with node N1. However, the cost of adding these circuit elements typically requires an increase in overhead which may be unacceptable. A remaining possibility is to implement a circuit which activates the anti-charge share device at all times. This would require implementing an n-channel or p-channel device (as illustrated in FIG. 5), so that the anti-charge share device conducts at all times.
As illustrated in FIG. 5, the previously described problem of charge leakage during the evaluation phase does not exist because transistor (M5) 514 will reinforce the voltage level on node N2. However, the use of transistor (M5) 514 in this manner significantly degrades performance for the following reasons. During operation, transistor (M5) 514 pulls node N2 to a high logic level. Then, transistor (M2) 506 and any other device below node N2 in the n-channel "stack" of AND circuit 500 will attempt to pull node N2 to a low logic level. This situation results in a significant DC power problem if this technique is used widely within a data processing system. The most serious concern for this implementation is that this circuit design is susceptible to a phenomena referred to as "data-dependent reset." When the following case is analyzed, it will become apparent why this issue is so significant.
In the following example, assume that AND circuit 500 is in an evaluation phase and inputs A and B are both at an active high level. It is to be noticed that the output of AND circuit 500 would also be an active high level. If, however, input B transitions to an inactive state, it is possible for transistor (M5) 514 to pull node N2 and node N1 to such a higher level such that voltage output inverter 510 of AND circuit 500 transitions to an inactive logic level. If the circuits that received the output of AND circuit 500 do not properly consider this possibility, a serious functional problem could be introduced by such an early reset operation. There might be a situation where AND circuit 500 fed one input of a second AND circuit, and this stage could evaluate a reset before the second input to the following stage was received. In such a situation, the second logic stage would suffer from improper functionality since both inputs were active during different portions of the evaluation phase, but the output of the second AND circuit did not transition to reflect this condition. Indeed, this is a serious problem, and the detection of this situation is not straightforward in all cases.
FIG. 8 illustrates an alternate prior art implementation which provides some charge share protection in dynamic circuits. FIG. 8 illustrates an AND circuit 800 which is configured in accordance with one embodiment of the present invention. AND circuit 800 comprises a transistor 802, a transistor 804, a transistor 806, a transistor 808, an inverter 810, a transistor 812, and a transistor 814. A first terminal of transistor 802 is coupled to a first reference voltage. A second terminal of transistor 802 is coupled to receive a clock signal. A third terminal of transistor 802 is coupled to a first terminal of transistor 804, a first terminal of transistor 812, a first terminal of transistor 814, and an input of inverter 810. A second terminal of transistor 804 is coupled to receive the A input signal. A third terminal of transistor 804 is coupled to a first terminal of transistor 806 and a second terminal of transistor 814. It should be noted that the connection between transistors 804 and 806 forms the node N2. The B input signal is provided to a second terminal of transistor 806 and a third terminal of transistor 806 is coupled to a first terminal of transistor 808. The clock signal is coupled to a second terminal of transistor 808 and a third terminal of transistor 808 is coupled to a reference ground voltage. A third terminal of transistor 814 is coupled to the first reference voltage. An output of inverter 810 is coupled to a second terminal of transistor 812 and a third terminal of transistor 812 is coupled to the first reference voltage. Furthermore, the output of inverter 810 provides an output signal having the form: F=A*B.
FIG. 8 illustrates an alternate embodiment of a prior art AND circuit. In FIG. 8, assume that an external user is not concerned with a zero current of IDDQ test. In this situation, a charge sharing device is formed by transistor 814 alone. In this situation, a source of an anti-charge sharing device is coupled to a node which should be charge share protected. Therefore, in the embodiment of the invention illustrated in FIG. 8, a source of transistor 814 is coupled to node N2, as node N2 is the node which should be protected from charge sharing. In FIG. 8, as in FIG. 6, transistor 814 is a pre-charge type anti-charge share device. As with the embodiments of the invention illustrated in FIGS. 6 and 7, the anti-charge sharing device (transistor 814) is controlled directly or indirectly (through an inverter) by node N1. Therefore, transistor 814 will remain enabled as long as AND circuit 800 is in its pre-charged condition. Therefore, once AND circuit 800 has been prepared for evaluation, it is in its pre-charge condition and will be held therein by transistor 812 as node N1 is a logic high value. Furthermore, transistor 814 will remain enabled to keep node N2 charged for an indefinite period of time.
When node N2 is charged, node N1 can not be discharged by conduction through transistor 804, leakage into the substrate from node N2, or through leakage from transistor 806 when the B input signal is noisy.
While the description presented above provides an exhaustive description of charge share anomalies in dynamic logic circuits, it should be noted that similar issues are present in static circuits. Therefore, a need exists for a circuit and method for providing charge share protection in static and dynamic circuits which do not require significant amounts of power or significantly degrade circuit performance.
USPTO Backgrounds
USPTO Backgrounds