1. Field of the Invention
The present invention relates to semiconductor integrated circuits. More specifically, the present invention relates to a semiconductor integrated circuit serving as an interface between a CPU and the outside for communication between systems.
2. Description of the Background Art
FIG. 7 is a schematic block diagram of a data processing system having a function of communication between a CPU and the outside, and FIG. 8 shows a format of a HDLC (High-level Data Link Control) frame transmitted by the system shown in FIG. 7.
In FIG. 7, a CPU 1, a memory 2, a DMA controller 3 and an I/O device 4 are connected to each other by a system bus 5. Communication lines 6 and 7 are connected to the I/O device 4 for communication with the outside.
The operation of the system shown in FIG. 7 will be described. Communication under transmission control by the HDLC format shown in FIG. 8 will be described as an example. As shown in FIG. 8, the HDLC frame format comprises an opening flag F1 of 1 byte indicating the head of the frame, an address field A of 1 or 2 bytes, a control field C of 1 or 2 bytes, an information field I whose number of bytes is changed frame by frame, a frame check sequence FCS of 2 bytes, and a closing flag F2 of 1 byte indicating the end of the frame.
Generally, the I/O device 4 has an FIFO therein. When communication is to be done by using the frame of FIG. 8, the CPU 1 once sets data to be transmitted, that is, the information field I on the memory 2 through the system bus 5, generates a control signal requesting data transmission to the I/O device 4 through the system bus 5 and successively writes data to be transmitted in the FIFO in the I/O device 4 through the system bus 5.
When DMA transfer is to be carried out, data transfer from the memory 2 to the I/O device 4 is carried out by the DMA controller 3 through the system bus 5. Then the I/O device 4 carries out the transmitting process to transmit data to the communication line 7. In the reverse operation, that is, when data is to be received, the I/O device 4 carries out data receiving process while writing the information field I in the FIFO of the I/O device. Meanwhile, the CPU 1 monitors the state of the FIFO in the I/O device, and appropriately reads data from the FIFO through the system bus to write the same to the memory 2, so as to prevent an overflow of the FIFO.
In the data processing system having the communicating function between the CPU and the outside shown in FIG. 7, the communication process is conventionally carried out in the above described manner. Therefore, the load of the CPU 1 with respect to data transmission and reception is large. In addition, the period of occupation of the system bus 5 for data transfer is long.
USPTO Backgrounds
USPTO Backgrounds