1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly to a semiconductor device including a stack structure of conductive patterns.
2. Related Art
A memory device having memory cells capable of storing data is one of the examples of semiconductor devices. As miniaturization of devices proceeds, designs for the memory device follow in the same pattern. The desire to improve integration density leads to the development of three-dimensional semiconductor products. For example, the memory cells may be vertically arranged. The memory cells arranged in the three-dimensional cell array may be coupled to various conductive patterns that are disposed at different heights, and the conductive patterns may be penetrated by slits.
The slits may define a layout of the conductive patterns. Some of the slits may overlap each other. The slits may be formed by etching a stack structure having a plurality of layers stacked on top of one another. A region where the slits overlap each other may be subjected to etching processes twice. Thus, the layers placed in the region where the slits overlap each other may be excessively etched. In this case, in the region where the slits overlap each other, some of the slits may extend to an active region of a substrate or may be placed near the active region of the substrate.
In a process of manufacturing the semiconductor device, a conductive material may remain in bottoms of the slits. If the conductive material remains in some slits that are deeply formed due to the excessive etching, the remaining conductive materials may cause a bridge failure, which means that the active region may be electrically connected to a gate pattern on the active region. The bridge failure leads to the malfunction of the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds