1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory in which an electrical write and erase operation can be performed and a program verification method of a nonvolatile semiconductor memory. More particularly, the present invention relates to a nonvolatile semiconductor memory and a program verification method in which a program verification operation can be effectively performed.
2. Description of the Related Art
In a nonvolatile semiconductor memory such as an E.sup.2 PROM, and a flash memory, in which an electric write and erase operation can be performed, it is necessary to check whether or not a write and erase operation of data is actually performed after the write and erase operation of data. This checking operation is referred to as a verification. Then, a verification performed when the data is written is referred to as a program verification, and a verification performed when the data is erased is referred to as an erasable verification.
A conventional nonvolatile semiconductor memory will be described below with reference to FIG. 1. As shown in FIG. 1, the nonvolatile semiconductor memory is provided with a memory cell array 1, an address buffer 2, a row decoder 3, a column decoder 4, a sense amplifier 5, an input and output buffer 6, a comparison circuit block 7, a write circuit block 8 and a control circuit 9.
In the memory cell array 1, memory cells are arranged in a form of array. The address buffer 2 latches an address signal sent from an external portion to output to the row decoder 3 and the column decoder 4. The row decoder 3 decodes a low address signal from the address signal sent from the external portion to select a word line. The column decoder 4 decodes a column address signal from the address signal sent from the external portion to select a data line.
The sense amplifier 5 amplifies the data read out through the data line from the memory cell array 1. The input and output buffer 6 inputs a signal from a data bus 6a and outputs a signal to the data bus 6a.
The comparison circuit block 7 compares a signal (read out data), in which the data stored in the memory cell array 1 is amplified by the sense amplifier 5, with a signal in which the data (expectation value data) sent from the data bus 6a is amplified by the input and output buffer 6.
The write circuit block 8 writes the data to the memory cell array 1, if the signal outputted by the sense amplifier 5 does not coincide with the output signal from the input and output buffer 6, as the comparison result in the comparison circuit block 7.
The control circuit 9 controls the sense amplifier 5, the input and output buffer 6, the comparison circuit block 7, the write circuit block 8 and the like.
The operation of the program verification in the nonvolatile semiconductor memory shown in FIG. 1 will be described below with reference to a flowchart shown in FIG. 2.
At first, the write operation is started at a step S0. Next, at a step S1, the number of times (number of write times) is counted in which the write circuits of the write circuit block 8 have already written data to the memory cells of the memory cell array 1.
For example, if a length of data is 16 bits, and an inner bus has 16 bits wide, there are 16 write circuits of the write circuit block 8. Those 16 write circuits respectively perform the write operations on the 16 memory cells. The control circuit 9 counts the number of write operations in each write circuit.
Next, at a step S2, it is judged whether or not the number of write operations counted at the step S1 reaches a predetermined maximum value. If it reaches the maximum value, an abnormal end is performed at a step S4. That is, the write operation is performed by implanting a hot electron into a floating gate of the nonvolatile semiconductor memory to change a threshold value of a transistor of the memory cell. In this case, even if the hot electron is implanted into the floating gate for a predetermined number of times, it is abnormal unless the threshold value of the transistor reaches the predetermined value. Hence, this case is treated as a defect.
Next, the program verification is performed at a step S3, if it is judged at the step S2 that the number of write operations does not reach the maximum value. That is, the comparison circuit block 7 compares the read out data with the expectation value data which should be written to the memory cell. The comparison circuit block 7 judges that the write operation has been normally completed if both of them coincide with each other (pass) as the compared result. Then, a write completion is established at a step S5.
If both of them do not coincide with each other (fail) as the compared result, the expectation value data is written to the memory cell array 1 by using the write circuits of the write circuit block 8 at a step S6. At this time, a power supply for the 16 write circuits of the write circuit block 8 has a high voltage, and a current in the write operation is large. Accordingly, the current in the write operation may cause noise or heat to be induced. Also, there is the restriction on the current drive ability of an inner power supply. Thus, the 16 write circuits can not write the data to the memory cells at the same time. Hence, the write operation is actually performed by dividing into four sessions for each four bits (predetermined value).
Next, the number of write operations is counted at the step S1, and the processes on and after the step S2 are similarly repeated.
For example, as shown in FIG. 3, the conventional nonvolatile semiconductor memory has the following problem, if there are only four bits judged as the fail at the step 53 of FIG. 2, of the 16 bits. That is, the number (four) of fails is equal to or less than the predetermined value. Therefore, the four bits for the fail can be written all at once even if the restriction on the drive ability of the inner power supply and the erroneous operation resulting from the noise occurrence when the write current flows are considered. Although it, the write operation must be performed by dividing into the four sessions. This results in a problem that a useless write cycle is induced to thereby make a write process time longer.
A technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-144277) is well known for the nonvolatile semiconductor memory. A CMOS flip-flop serving as a data latch and a sense amplifier is provided at one end of a bit line direction of a memory cell array. So, this technique has a verification control means for setting a unit write time for a memory cell in a predetermined range of the memory cell array, and simultaneously writing data, and then performing a re-write operation if there is a memory cell in an insufficiently written state after the data in the memory cell is read out. When a write verification operation is performed, a logical operation is performed between the exteriorly read out data in the memory cell and the write data latched in the flip-flop. Then, the re-write data is automatically set for each bit so that an unnecessary write operation is not performed.
USPTO Backgrounds
USPTO Backgrounds