1. Field of the Invention
The present invention relates generally to the process of etching silicon and, more particularly, to providing an accurate etch stopping mechanism for producing pressure sensors and other semiconductor devices. The present invention also relates to products made by this method.
2. Description of the Prior Art
As is well known by those skilled in the art, semiconductor devices are typically manufactured by producing a large plurality of devices on a single silicon wafer and then, after the numerous manufacturing steps have been completed to produce the plurality of silicon dice, each die is separated from the silicon wafer. When the semiconductor devices require etching, it is necessary to assure that the etching procedure stops at the appropriate point when the etchant penetrates a desired depth into the thickness of the silicon wafer. If the thickness of the wafer comprises different materials, particular etchants are selected which selectively etch one material, but not the other. A particular problem occurs when the wafer comprises only a singular material such as silicon. When this occurs, it is typical to etch for a predetermined time or to take advantage of the different dopant characteristics of the material. For example, if the substrate portion of the wafer comprises P type silicon and a first surface of the wafer comprises an N type epitaxial layer, the differently doped regions are used to provide a diode effect because of the PN junction at the interface where the substrate and the epitaxial layer meet. By connecting the epitaxial layer to a power supply and connecting the solution to ground and maintaining the epitaxial layer at a voltage potential sufficiently above that of the substrate, an etchant such as potassium hydroxide can be used to etch a preselected shape into the substrate. When the etchant penetrates sufficiently through the substrate of the wafer and reaches the N type epitaxial layer, the anode of the diode is removed by the etchant and the voltage potential between the epitaxial layer and the etchant decreases appreciably. The current flow between the epitaxial layer and the opposite side of the wafer can be monitored and, as the anodization begins, the current begins to rise. As the etching process is terminated, the current decreases to a lower level. The anodic oxide which is formed prevents further etching from occurring.
The etching process described above is subject to several problems that can adversely affect the quality of the etching procedure. To describe these problems, a back-side etching process will be described wherein a silicon wafer with a first side and a second side is processed to provide numerous semiconductive components on the surface of the first side with an etched recess formed on the second side. According to this type of procedure, a voltage potential is connected in electrical communication with the epitaxial layer of the first side and an etchant, such as potassium hydroxide, is disposed in fluid communication with selected regions of the second side.
One type of failure mechanism in a process such as that described above is when the etchant does not stop etching when it penetrates completely through the substrate and into the epitaxial layer. Under these circumstances, a silicon dioxide layer does not form at the etching surface because the epitaxial layer is debiased and the voltage at the first side of the wafer is not uniform across the entire surface of the wafer. For example, if the electrical contacts at the first side of the wafer do not make good electrical contact with the surface of the epitaxial layer, the appropriate voltage potential between the first and second sides of the wafer is not provided.
Another failure mechanism occurs when the etching stops prematurely and does not penetrate completely through the substrate to reach the epitaxial layer. This type of failure mechanism can be caused by several factors. If the epitaxial layer is electrically shorted in some way to the substrate, then the diode does not function as intended. A second cause of this type of premature etch stopping is the electrical contact between the voltage source and a P+ type diffusion area which is typically present in the surface of the first side of the silicon wafer. If the voltage source contacts a P+ diffusion, there exists an SCR structure between the power supply and the etchant. That SCR structure comprises the P+ type diffusion, the N type epitaxial layer, the P type substrate and the N type etching solution such as potassium hydroxide. This SCR is turned on spontaneously when the P substrate is sufficiently thinned by the etchant so that the P substrate is electrically connected to the bias power supply. This stops any further etching of the P substrate.
Another severe problem can occur when certain particular types of devices are manufactured. For example, if each die location of a silicon wafer is intended for use as a pressure sensor that also contains an integrated circuit on the same die, the surface of the first side of the die in the region of the diaphragm area may be surrounded by a P+ isolation type diffusion that is used to isolate the diaphragm region of the surface from the integrated circuit portion of the surface on the first side of the die. Since the etching occurs on the second side of the wafer to create the diaphragm of the pressure transducer, the P+ type isolation diffusion surrounding that area isolates it from most other areas of the silicon wafer surface. In order to etch the back-side, or second side, of the wafer in the manner described above, electrical contact would have to be made between the power supply and the first side of the wafer within the area surrounded by the P+ type diffusion on every die in the wafer. Because of the small size of the diaphragm area of the die, it is very difficult to assure electrical contact between the power supply and the first side of the wafer within the P+ type isolation diffusion that surrounds the area where that voltage potential must be provided in order to assure an appropriate back-side etching procedure without contacting the P+ isolation region. Furthermore, the diaphragm area of the die may require electrical connection to the power supply terminal of the completed integrated circuit product. This connection could allow conduction paths through the circuit components to the substrate, limiting the voltage potential available to the diaphragm area or possibly causing overload of the etching power supply.
It would therefore be significantly beneficial if a means is provided for etching a silicon wafer on a second side and assuring appropriate electrical connection to the first side of the wafer at the proper locations for each die of the wafer structure.
USPTO Backgrounds
USPTO Backgrounds