Metrology targets and methods aim at deriving measurements which represent the production accuracy of designed devices. Metrology faces the challenges of yielding measurable signals which reflect accurately properties of the devices, at a rate that is high enough and a real estate that is low enough, to minimize the hindrances to the production. Current metrology overlay (OVL) algorithms uses special targets that have periodic structures in two layers, which are offset differently in different target cells.
U.S. Patent Application Publication No. 2014/0316730, which is incorporated herein by reference in its entirety, discloses methods and systems for performing semiconductor metrology directly on device structures using an on-the-fly model-based algorithm.
U.S. Patent Application Publication No. 2009/0244538, which is incorporated herein by reference in its entirety, discloses a lithographic apparatus arranged to transfer a pattern from a patterning device onto a substrate with a reference set of gratings provided in the substrate, the reference set including two reference gratings having line elements in a first direction and one reference grating having line elements in a second, perpendicular, direction. US 2009/0244538 requires identical (or very similar) designs for x and y in order to calculate the sensitivity of one direction and apply it to the second direction. However, this x-y design symmetry breaks in the device due to electrical functionality needs (and also the lithography process in critical layers is not symmetric).
U.S. Patent Application Publication No. 2011/0255066, which is incorporated herein by reference in its entirety, discloses measuring overlays using multiple targets in multiple fields, assuming that the overlay sensitivity of targets across the fields of the wafer is constant, ignoring intra-field process variations.
Young-Nam Kim et al. 2009 (Device based in-chip critical dimension and overlay metrology, Optics Express 17:23, 21336-21343), which is incorporated herein by reference in its entirety, discloses a model-based in-chip optical metrology technique that allows direct measurement of both critical dimensions and overlay displacement errors in the DRAM manufacturing process, performed on the actual semiconductor devices without requiring special target structures.
USPTO Backgrounds
USPTO Backgrounds