1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device where passive elements are integrated by a TSV technology.
2. Description of the Related Art
With fast evolution of deep submicron technology, a single chip is normally demanded to integrate a great number of different circuits. For a submicron CMOS (Complementary Metal Oxide Semiconductor) circuit, interaction between active CMOS elements and passive elements is a critical subject in the system design of high-performance VLSI (Very Large Scale Integration) circuits.
At present, there has been an integration technology embedding passive elements in a chip containing CMOS elements to solve the problem of layout volume expansion caused by connecting CMOS circuits with external passive elements. The technology can decrease the layout area, shorten the signal transmission paths and promote the overall performance of the semiconductor device. Refer to FIGS. 1A, 1B and 1C respectively a perspective view of a conventional semiconductor device, a circuit diagram and a top view of a conventional passive element. In the conventional technology, a CMOS element 12 and a deep trench 14 are fabricated in a silicon substrate 10 to realize a high-capacitance design. An annular insulation layer 16 is formed on the inner wall of the deep trench 14. A metal layer 18 is formed inside the insulation layer 16. Thus is formed an equivalent capacitor (C). One end of the equivalent capacitor extends from the metal layer 18 and electrically connects with the CMOS element 12 through a conductive wire. The other end of the equivalent capacitor is grounded through the silicon substrate 10. The objective of fabricating the passive elements in the semiconductor device is to increase the capacitance to filter noise or overcome ground bounce. The conventional technology can indeed integrate passive elements and CMOS elements in a single chip. However, the semiconductor device fabricated by the conventional technology can only allow voltage signals to pass unidirectionally. Therefore, the semiconductor device can only apply to digital circuits. While larger resistors, larger capacitors, larger inductors, or a great number of passive elements are intended to integrate with CMOS elements 12 in a single chip, they would occupy a larger area. Further, it becomes more difficult to design CMOS elements 12 or miniaturize the chip in such a scenario. Besides, signal interference is more likely to occur in such a scenario.
Accordingly, the present invention proposes a semiconductor device integrating passive elements to overcome the abovementioned problems.
USPTO Backgrounds
USPTO Backgrounds