Integrated chips are formed by operating upon a semiconductor workpiece with a plurality of different processing steps. Deposition processes are widely used on varying surface topologies in both front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) processing. For example, in FEOL processing deposition processes may be used to form polysilicon material on a substantially flat substrate, while in BEOL processing deposition processes may be used to form metal interconnect layers within a cavity in a dielectric layer. Deposition processes may be performed by a wide range of deposition tools, including physical vapor deposition (PVD) tools, electro-chemical plating (ECP) tools, atomic layer deposition (ALD) tools, etc.
USPTO Backgrounds
USPTO Backgrounds