1. Field of the Invention
This invention generally relates to a semiconductor package, and more particularly to a chip sized package (CSP) with an improved thin substrate for eliminating a die crack problem.
2. Description of the Related Art
As the need for lighter and more complicated semiconductor devices becomes greater semiconductor chips have become more and more complex thereby requiring more electrical connections. Therefore, the ball grid array (BGA) has been developed by the semiconductor chip packaging industry to meet these needs.
FIG. 1 depicts a conventional BGA semiconductor chip package 100 including a chip 101 attached on a substrate 102 having a dielectric layer 102a. The chip pads on the active surface of the chip 101 are connected to conductive traces 102c disposed on the upper surface 102b of the dielectric layer 102a by bonding wires 103 and the conductive traces 102c are electrically connected through the plated through holes (PTH) 107 to the solder ball pads 102f disposed on the lower surface 102d of the dielectric layer 102a. Each solder ball pads 102f has a solder ball 104 mounted thereon for electrical connection to outer circuit, such as a printed circuit board. A package body 105 encapsulates the chip 101, bonding wires 103 and the substrate 102.
The dielectric layer 102a of the substrate 102 is generally made of fiberglass reinforced bismaleimide-triazine (BT) resin, FR-4 fiberglass reinforced BT epoxy resin or polyimide and the thickness of the substrate 102 is about 0.56 mm. A copper die pad 108 is disposed on the central surface of the substrate 102 for carrying the chip 101. The plated through holes (vias) 107 are arranged around the die pad 108.
However, the overall volume of the above BGA semiconductor chip package 100 is too large to meet the packaging requirements for high density semiconductor chip. Accordingly, the packaging industry further develops a chip sized package (CSP) technology to meet the packaging requirements for high density semiconductor chip. Generally, the overall dimension of the chip sized package is smaller than 1.2 times of the chip dimension so as to increase the packaging density.
FIG. 2 illustrates a conventional CSP semiconductor chip package 200 including a chip 201 attached on a substrate 202 having a dielectric layer 202a. The chip pads on the active surface of the chip 201 are connected to conductive traces 202c disposed on the upper surface 202b of the dielectric layer 202a by bonding wires 203 and the conductive traces 202c are electrically connected through the plated through holes (PTH) 207 to the solder ball pads 202f disposed on the lower surface 202d of the dielectric layer 202a. Each solder ball pads 202f has a solder ball 204 mounted thereon for electrical connection to outer circuit, such as a printed circuit board. A package body 205 encapsulates the chip 201, bonding wires 203 and the substrate 202. According to the CSP semiconductor chip package 200, the area surrounded by the solder balls is usually smaller than the area of the chip 201.
According to the CSP semiconductor chip package 200 as shown in FIG. 2, the thickness of the substrate 202 is about 0.36 mm or less than 0.36 mm and the plated through holes (vias) 207 of the substrate 202 are arranged within the periphery of the chip 201. At room temperature, the Storage Modulus (E') of the fiberglass reinforced bismaleimide-triazine (BT) resin for the substrate is about 7,000-9,000 MPa, while the Young's Modulus (E) of copper for the plated through holes (vias) 207 is about 110,000 MPa. During resin molding (about 175.degree. C.), the Storage Modulus (E') of the BT substrate is about 2,000-3,000 MPa, while the Young's Modulus (E) of copper for the plated through holes (vias) 207 is about 103,000 MPa. Therefore, during resin molding (about 175.degree. C.), the ratio of the copper's Young's Modulus (E) to the BT's Storage Modulus (E') increases from 15 to 500 such that the BT substrate 202 without vias 207 is relatively softer than the BT substrate 202 with vias 207 and the area of BT substrate 202 without vias 207 is unable to provide sufficient strength for supporting chip 201. Besides, since the chip 201 is not supported by the die pad, in the CSP package, stress caused by molding pressure will exert on the edge 201a of the chip 201 and the chip will crack at the edge 201a area. This will lower the yield for production.
Accordingly, there is a need for the packaging industry for eliminating the die crack problem for the chip sized package.
USPTO Backgrounds
USPTO Backgrounds