The present invention relates to a vertical synchronous signal detection circuit for detecting a vertical synchronizing pulse from an input signal digitized in a digital video decoder for generating a digital video signal from a composite video signal.
A conventional vertical synchronous signal detection circuit comprises a comparator, a change detecting unit, a detection counter, and a protective counter.
The comparator compares an input signal sampled with a clock signal of, for example, 13.5 MHz and converted to digital values with a predetermined threshold level set between a retrace blanking level and a synchronous level and outputs a compare signal CP corresponding to the result of comparison. The change detecting unit detects timing at which the input signal falls below the threshold level, and outputs a change signal. The compare signal and the change signal are supplied to the detection counter.
The detection counter starts counting based on the change signal to thereby count the number in which the input signal that falls below the threshold level, is successive. When the so-counted value reaches a constant number (e.g., 350), the detection counter outputs a detect signal. On the other hand, the protective counter is used to protect against a malfunction of the detection counter due to noise. Further, the protective counter counts the number in which the input signal that falls above the threshold level is made successive, and causes the detection counter to continue counting unless the count value exceeds a constant value (e.g., 15).
In the vertical synchronous signal detection circuit, the input signal converted to the digital values is inputted to the comparator and the change detecting unit. The input signal is compared with the threshold level by the comparator, and the compare signal corresponding to the result of comparison is supplied to the detection counter and the protective counter. The timing in which the input signal falls below the threshold level, is detected by the change detecting unit, and the change signal is supplied to the detection counter.
Thus, the detection counter starts counting from the timing in which the input signal falls below the threshold level. When the input signal falls above the threshold level during the counting of the detection counter, the protective counter performs counting. Unless the count value of the protective counter exceeds 15, the detection counter is not reset and continues counting. When the count value of the detection counter reaches 350, the input signal is judged to be a vertical synchronizing pulse and hence a detect signal is outputted from the detection counter.
On the other hand, when the time at which the input signal falls above the threshold level, becomes long, and the count value of the protective counter exceeds 15 during the counting of the detection counter, the detection counter is reset to stop counting. The once-deactivated detection counter is not re-started till timing in which the input signal falls below the threshold level again.
Thus, even if the input signal instantaneously falls above the threshold level due to noise during a period of the vertical synchronizing pulse, the counting of the detection counter is protected by the protective counter and continued if such a period falls within a predetermined time. Thus, even if a composite video signal is mixed with noise due to a weak electric field or the like, the vertical synchronizing pulse can be detected.
However, the conventional vertical synchronous signal detection circuit is accompanied by the following problems.
Namely, when such noise as to successively exceed a predetermined number of pixels (e.g., 15) exists during a vertical synchronous pulse period of the input signal, the detection counter is deactivated so that the vertical synchronizing pulse cannot be detected.
USPTO Backgrounds
USPTO Backgrounds