1. Field of the Invention
The present invention relates to semiconductor device fabrication and, in particular, to processes for the fabrication of patterned silicon gate layers.
2. Description of the Related Art
The fabrication of semiconductor devices, such as transistors, often involves the processing of a semiconductor substrate (e.g. a silicon wafer) through a series of steps, including the implantation of dopant atoms into the substrate, the deposition/growth of electrically insulating and conducting layers on the substrate, and the formation of patterned layers on the substrate via lithography and etching techniques. A prevailing trend in semiconductor device fabrication technology is to reduce the size of the semiconductor devices in order to increase device performance and device packing density (i.e. the number of semiconductor devices per unit area of semiconductor substrate), as well as to decrease the power consumption of the semiconductor devices. For transistors that employ a polysilicon gate, the width of the polysilicon gate (i.e. the "physical gate length") is a primary factor in determining the size of the transistor. Upon patterning of polysilicon gate layers, it is, therefore, desirable to define the resulting polysilicon gate width to minimum dimensions for a given process technology. As these minimum dimensions (i.e. "critical" dimensions) are reduced below 0.25 microns to 0.10 microns and less, however, it becomes increasingly difficult to controllably define the polysilicon gate width using conventional lithographic techniques.
There remains, therefore, a need in the field for a process for defining the width of polysilicon gates to critical dimensions that is controllable and extendible to well below 0.25 microns width (e.g. to width of 0.10 microns and below). The process should also be inexpensive and compatible with standard semiconductor device fabrication technologies.
USPTO Backgrounds
USPTO Backgrounds