1. Field of the Technology
The present technology relates to three-dimensional (3D) memory devices, and more particularly to methods to fabricate such memory devices.
2. Description of Related Art
Three dimensional (3D) semiconductor devices are characterized by multiple layers forming a stack of alternating active layers and insulating layers. In a memory device, each of the layers can include a planar array of memory cells. For certain three-dimensionally stacked memory devices, active layers can comprise active strips of materials configured as bit lines or word lines for memory cells stacked in spaced-apart ridge-like structures. The active layers can be made from a conductor, an undoped semiconductor, or a doped (p-type or n-type) semiconductor. In such 3D memory, memory cells can be disposed at the cross-points of the stacked bit lines or word lines and the crossing word lines or bit lines, forming a 3D memory array. A stack of bit line pads connects respective strips in the plurality of stacks of strips for selection of planes of memory cells.
One method for manufacturing a 3D memory device includes forming a stack of alternating active layers and insulating layers, etching the layers to define stacks of active strips connected to a stack of pads configured for making interlayer contacts to the layers, forming a memory layer over the stacks, forming memory cell gates or channels over the memory layer, and forming isolation material between the stacks. In such a method, a layer-by-layer implantation can be used to form different doping concentration profiles in various regions of the active layers, including the strips and the pads after each layer of semiconductor material is deposited. However, high thermal processes used in the method can affect high concentration junctions (e.g. >1018 cm−3) such as in the pads and consequently degrade the device performance. Furthermore, the cost of manufacturing using the method increases with the number of layers in the stacks because each layer of semiconductor material needs an individual implantation step for its own junction formation.
It is desirable to provide a method for improving fabrication of high concentration junctions, such as in bit line pads, in vertical gate 3D NAND flash memories.
USPTO Backgrounds
USPTO Backgrounds