Electronic fuses are commonly used in integrated circuits to define or alter the configuration or operation of the integrated circuits following fabrication. For example, in random access memories (RAMs) electronic fuses are typically used to enable redundant memory banks in place of memory banks determined to be defective during testing.
FIG. 1 shows a typical two-terminal electronic fuse 10. A low resistance material 12 such as nichrome metal or polysilicon is disposed between first 14 and second terminals 16. The electronic fuse 10 presents itself as a short circuit when not “programmed” and as an open circuit after it is programmed. The fuse 10 is programmed (i.e. is “blown”) by forcing a high current through the low resistance material 12. The high current causes the low resistance material 12 to melt or rupture, thereby forming an open circuit between the first 14 and second terminals 16.
Another commonly used fuse element is the antifuse. An antifuse is, in effect, the opposite of a fuse, and presents itself as an open circuit when not programmed and as a short circuit after being programmed. FIG. 2 shows a typical antifuse element 20. A first metal or polysilicon terminal 22 of the antifuse is separated from a diffusion region 24, which embodies the second terminal of the antifuse, by a thin insulating layer 28 formed over a semiconductor substrate 26. Prior to being programmed the antifuse 20 presents itself as an open circuit. If during programming a sufficient voltage is applied across the polysilicon and diffusion terminals 22, 24, the thin insulating layer 28 melts, thereby shorting the polysilicon and diffusion terminals 22, 24 together.
In addition to being used to enable redundant memory in RAMs, fuses and antifuses are commonly used in programmable logic structures such as programmable logic devices (PLDs), programmable array logic (PAL), programmable logic arrays (PLAs), and field programmable gate arrays (FPGAs). Integrating fuses or antifuses with such logic structures allows a chip manufacturer to design a generic logic chip having uncommitted logic gates and circuits, which it can sell to many different users having varying circuit designs. A particular user can then configure (i.e. customize) the programmable chip by programming selected ones of the integrated fuses or antifuses as needed to implement the user's desired circuit design.
Programming a two-terminal fuse or antifuse element of the type described above is permanent. In many applications, however, it is desirable to have the ability to reprogram the fuse or antifuse elements. To satisfy this desire efforts have been made to provide a fuse technology that allows the logic gates and other circuit elements (e.g., as in an FPGA) to be reprogrammable. One known reprogrammable fuse approach uses a static RAM (SRAM) cell (or “memory element”, the terms “cell” and “memory element” being used interchangeably herein) to control a switching element. Because the SRAM cell can have one of two output states, these two states can be used to control the opening or closing of the switch, thereby effectively implementing a fuse function. Whereas the SRAM/switch structure has the benefit of being reprogrammable, one drawback of its use relates to the fact that SRAM cells are volatile. This means that the fuse is unable to maintain its latched state after power is removed. A second problem with the SRAM/switch approach is that the state of the fuse is not immediately available upon power-up. In other words, the SRAM must first be programmed before the switching element can be configured to its intended state.
To overcome the volatility problem associated with the SRAM/switch structure, another known fuse technology approach uses bits stored in nonvolatile memory arrays, for example EEPROM (electrically erasable programmable read only memory) arrays to control the state of switches. Although this approach overcomes the volatility associated with the SRAM/switch approach, the problem remains that the states of the switches are not immediately available upon power-up. In other words, even if nonvolatile memory arrays such as EEPROM arrays are used, the bits must be first read out of the memory array and applied to the switches before the states of the switches are actually configured to their desired states.
USPTO Backgrounds
USPTO Backgrounds