1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor devices having an impedance calibration function and integrated circuits including the same.
2. Related Art
In recent years, fast semiconductor systems have been increasingly in demand. Accordingly, timing margins between internal signals used in the semiconductor systems have been reduced. A threshold voltage and a turn-on current of NMOS transistors or PMOS transistors included in the semiconductor system may change depending on process conditions for fabricating the semiconductor system, and variation of the threshold voltage and the turn-on current of the NMOS transistors or the PMOS transistors may affect a skew of the internal signals used in the semiconductor system. If the timing margin between the internal signals is reduced due to a variation of the skew, the semiconductor system may malfunction.
As a level swing width of a transmission signal corresponding to an interface signal between semiconductor devices included in the semiconductor system operating at a high speed is gradually reduced, reflection of the transmission signal due to impedance mismatch of an interface unit may be raised as a serious issue. The impedance mismatch may occur due to variation of process conditions. Thus, the semiconductor system employs an impedance matching circuit such as an on-die termination (ODT) circuit.
Impedance calibration (ZQ calibration) may mean generation of codes for adjusting a resistance value of the ODT circuit, which varies according to a process condition. The ODT circuit having a resistance value adjustable by the impedance calibration may remove the impedance mismatch of the interface unit to prevent distortion of the transmission signal.
USPTO Backgrounds
USPTO Backgrounds