1. Field of the Invention
Embodiments of the present invention generally relate to methods and apparatus for processing semiconductor substrates. More particularly, embodiments of the present invention relates to methods and apparatus for selective oxide etching in semiconductor fabrication.
2. Description of the Related Art
In semiconductor fabrication, oxide fabrication is critical, especially for the thin oxide which is an essential part of gate structure for MOS (Metal Oxide Semiconductor) technology. With proper manufacturing control, oxide layers have high quality, stability and desirable dielectric properties. A variety of oxide fabrication processes are used in integrated device manufactures (IDM) to obtain oxides of different properties for different functions. Thermal oxides and deposited oxides are most used in semiconductor devices. Additionally, native oxides may be generated during process. Different oxides may also respond differently to subsequent processes and may require different treatment for the same purpose.
Thermal oxides are grown thermally by high temperature anneal in an oxygen environment. Thermal oxides may be used as a dielectric material, device isolation, screens for implants, stress-relief (pad-oxides), reoxidizing nitride, and photoresist adhesion and stress reduction for polysilicon surfaces.
Deposited silicon oxides are fabricated by reacting a silicon source and oxygen in a chamber. Oxides can also be deposited by a combination of chemistries such as Ozone/Tetreethylorthosilicate (TEOS) or carbon based chemistries. An exemplary deposited oxide may be HARP (High Aspect Ratio Process) oxide which is produced by a unique process. HARP, also known as sub-atmospheric chemical vapor deposition (SACVD), is a non plasma based chemical vapor deposition (CVD) solution using ozone/TEOS chemistry to deposit an oxide in high aspect ratio gaps, such as shallow trench isolation (STI) and pre-metal dielectric (PMD). Annealing is usually needed to harden HARP oxides.
A native oxide typically forms when a substrate surface is exposed to oxygen. Oxygen exposure occurs when substrates are moved between processing chambers at atmospheric conditions, or when a small amount of oxygen remains in a vacuum chamber. Native oxides may also result from contamination during etching. Native oxides are typically undesirable and need to be removed prior to a subsequent process.
During semiconductor fabrication, structures may be formed with excessive material and then etch and/or polished back to a desired dimension. For oxide features, polishing and etching are generally used after formation to reach desired size. Some oxide features may have two or more oxides that respond differently to the same process, hence posing difficulties in processing, especially when feature sizes are smaller.
STI (Shallow Trench Isolation) is one of the oxide structures that have several forms of oxides. STI is a primary form of device isolation technology used for sub-0.25 micron fabrication. Oxides filled trenches are used to isolate devices formed on a semiconductor substrate. Trenches are first etched on a semiconductor substrate, followed by thermal growth of an oxide layer. The purpose of this high temperature oxide layer is the appropriate corner rounding to avoid early gate dielectric break down and to relieve stress post CVD oxide deposition. The thermal oxide layer also passivates the silicon surface and serves as a barrier layer between silicon and deposited oxide layer. The trench is then filled with High Density Plasma (HDP) or HARP oxide, polished, and etched back. A chemical mechanical polishing (CMP) process may be performed to the oxide filled trench after deposition, followed by an etching process to prepare the trench and other structures on the substrate for the subsequent process, such as various well implants, gate oxidation, and eventually poly deposition and patterning.
Sputter etching processes and wet etching processes are conventionally oxide etching processed used in STI etching. However, sputter etching process generally cannot completely remove oxides and can damage delicate silicon layers by physical bombardment. Wet etching use chemical solutions, for example hydrofluoric acid (HF) and deionized water, to remove oxides. However, diluted HF has the disadvantage of having a variable oxide etch rate. Nitrided oxides etch much slower than non-nitride oxides. Thermal oxides etch at a different rate compared to deposited oxides. Furthermore, annealed oxides have different etch rates than deposited oxides. This causes significant variability and integration issues in the process flow.
In shallow trench isolations for examples, three different oxides are used to fill the trench. Yet to keep the planarity of the oxide post polish and various cleans, an etch chemistry is required that etches all the oxides at the same rate. In reality various process variabilities cause significant unwanted leakages which contribute to the main current flow from source to drain. One example of such an unwanted leakage is the poly silicon wrap around near the STI corners. Traditionally post STI etch/clean a high temperature STI oxide liner that is grown prior to oxide deposition to fill the trench. During various HF etch-backs, the various oxides in the trench etch at different rates. Subsequently, deposited polysilicon intrudes inside the over etched cavities in the oxides. Polysilicon wraps around inside the trench causes unwanted leakage and yield loss.
Therefore, there is a need for apparatus and methods for etching all the oxides at the same rate.
USPTO Backgrounds
USPTO Backgrounds