1. Field of the Invention
This invention generally relates to digital-to-analog converters (DACs) and, more particularly, to a current impulse DAC system and method.
2. Description of the Related Art
At the time of this writing the DACs with the widest signal bandwidth of greater than 50 gigasamples per second (GS/s) have been implemented using indium phosphorous (InP) or silicon germanium (SiGe) BiCMOS [1] technologies. While the availability of such heterojunction bipolar transistor (HBT) devices helps with the signal bandwidth, these technologies are not well suited for integration with other fast digital logic. Interfacing high speed digital data into the DAC is a major system level challenge, and bringing the DAC into the same CMOS die with the digital signal processing (DSP) blocks is also highly desirable. It has been shown [2] that the most advanced CMOS nodes are suitable for designing DACs with record braking update rates, but signal bandwidth and linearity remain a big challenge.
Time interleaving is a concept widely used in high speed analog-to-digital (A/D) converters (ADCs) to achieve a higher sampling rate than can be obtained using a single ADC core. The technique uses multiple slowly clocked ADCs that operate in parallel, and takes turns sampling the input and converting it to a digital value. With properly aligned sampling clock phases, the composite sampling rate is the sampling rate of the individual ADC core multiplied by the number of the cores used.
The same principle can be applied to DACs as well. The current steering DAC architecture, which is the most common choice in high speed applications, is inherently very fast and has conventionally been able to satisfy the needs of almost all applications. For that reason interleaving is not very widely used in DACs. Another important reason is that one cannot interleave just any kind of DAC because they need to have return-to-zero type output signals to provide the narrow signal pulses needed for interleaving. This means that although the update rate of the DAC core is relaxed due to interleaving, signals must be used with pulse widths similar to the clock period at the full rate.
FIG. 1A is a schematic depicting the general concept of an interleaved DAC, and FIG. 1B depicts associated waveforms (prior art). The waveforms show how four DACs generate quarter period long output pulses that are then added together to form the final composite output signal. The pulsed output signal of the DAC core goes to zero between the pulses, hence the name return-to-zero (RZ). This is necessary; as not zeroing the output would result in inter symbol interference, which manifests itself in the frequency domain as a sin(x)/x response with zeros at fs/N, where N is the number of the interleaved channels.
One of the known problems with the return-to-zero waveform is its jitter sensitivity. Any variation in the pulse width due to clock jitter is translated into an error in the output current. In the interleaving application some but not all jitter sources cancel out, making the situation somewhat better.
It can be argued that achieving a wide signal bandwidth is an even bigger challenge in very high speed DAC design than is realizing a faster update rate. The bandwidth is mainly limited by the capacitance at the output node. It is clear that interleaving, with many parallel DACs connected to the same output, simply increases the capacitance. Techniques such as adding a cascode stage after combining the currents, and design principles borrowed from distributed power amplifiers can be used alleviate the bandwidth issue [1,2]. However, keeping the interleaving factor low and having a DAC core with small output capacitance are both still essential.
FIG. 2 is a schematic depicting a simplified unit cell in a return-to-zero current steering DAC (prior art). The complete DAC consists of an array of these cells connected to the same outputs and controlled with different data bits. The cell has a current source, sized according to the weight of the data bit, followed by a data switch controlled by the data bit and its complement. The switch steers the current either toward the positive or the negative output. A second level of switches, controlled with the clock, is placed between the data switch and the output. These clock switches create the RZ waveform by switching the current either to the load or to a dummy output.
The open loop architecture of the current steering DAC makes it simple and fast. It can directly drive resistive loads and can easily be adapted to deep submicron technologies. A known drawback of the architecture is the fact that its output impedance is signal dependent, as the number of current sources connected to each output changes with the digital input data. At high signal frequencies the capacitive part of the impedance dominates and is the main source of nonlinearity in the DAC.
The differential current switches in the DAC are operated in the saturation region of the transistor's IV curve. This provides isolation between the output and the current sources, and minimizes voltage variation in the common source node. One drawback, however, is that the switches require more voltage headroom, leaving less output signal range. This signal range issue is problematic in advanced technology nodes that use very low power supply voltages. The switch control voltages are not simple CMOS logic levels, but require a certain common mode level and a reduced voltage swing. This means that the switches need a special driver circuit, which often becomes the speed bottleneck in very high speed design. The size of the switch transistor should ideally be as small as possible to minimize its parasitic capacitances, but operation in saturation region with limited voltage headroom forces the use of fairly large switch transistors.
The current source in the current steering DAC is a transistor with its gate biased with a control voltage and the drain usually cascoded with another transistor. This current source is slow to turn on and off and thus the output current is steered in one of two ways instead of being turned on and off.
This is not the only way to implement a current source, though. A resistor can be used as a current source, for instance. Another way, which has some added benefits, is the use of a switched capacitor. A capacitor that is charged to voltage V during one clock phase and then discharged to ground during another, delivers a charge packet C*V in the form of a current impulse in every clock cycle. The average current is fclk*C*V, where fclk is the clock frequency and C the capacitance. What makes this very attractive for high sampling rate operation is that the current grows with the clock frequency, making it practical to implement currents in the range of tens of milliamps with capacitors of just few hundred femtofarads (fF).
FIG. 3 is a schematic depicting a switched capacitor DAC cell (prior art). Switched capacitor (SC) techniques are commonly used in the industry, but typically at much lower frequencies. Whether used in switch-cap filters, delta-sigma modulators, or pipelined ADCs, the switched capacitors are combined with operational amplifiers to provide a discrete-time voltage output. The switched capacitor alone doesn't make a practical current source. It needs a virtual ground to which the capacitor is discharged. Voltage mode SC circuits use opamps for this purpose.
It would be advantageous if a time-interleaved DAC could be realized that overcome the limitations of a current steering return-to-zero DAC, using a fast open loop architecture with a current mode output capable of driving resistive loads without buffering.    [1]A. Balteanu, et. al., “A 6-bit Segmented RZ DAC Architecture with up to 50-GHz Sampling Clock and 4 Vpp Differential Swing”, IEEE Int. Microwave Symp. (IMS), 2012 IEEE.    [2]H. Huang, et. al, “An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications”, IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 4, pp. 1211-1218, April 2015.
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