There are many steps required in manufacturing multi-level integrated circuits (IC). Such steps include depositing conductive and insulator materials on a semiconductor wafer or substrate followed by full or partly removal of these materials using photo-resist patterning, etching, and the like. After photolithography, patterning and etching steps, the resulting surface is generally non-planar as it contains many cavities or features such as vias, lines, trenches, channels, bond-pads, and the like that come in a wide variety of dimensions and shapes. These features are typically filled with a highly conductive metal material before additional processing steps such as etching and/or chemical mechanical polishing (CMP) is/are performed. Accordingly, a low resistance interconnection structure is formed between the various levels/sections of the IC.
Copper (Cu) is quickly becoming the preferred material for interconnections in ICs because of its low electrical resistively and high resistance to electro-migration. Electrodeposition is one of the most popular methods for depositing Cu into the features on the substrate surface.
As can be expected, there are many different designs of Cu plating systems that have been used in this industry. For example, U.S. Pat. No. 5,516,412 issued on May 14, 1996, to Andricacos et al. discloses a vertical paddle plating cell that is designed to electrodeposit a film on a flat article. Next, U.S. Pat. No. 5,985,123 issued on Nov. 16, 1999, to Koon discloses yet another vertical electroplating apparatus, which purports to overcome the non-uniform deposition problems associated with varying substrate sizes. Further, U.S Pat. No. 5,853,559 issued on Dec. 29, 1998, to Tamaki et al. discloses an electroplating apparatus that minimizes waste of the plating electrolyte and accomplishes high recovery of the electrolyte.
During the Cu electrodeposition process, specially formulated plating solutions or electrolyte are used. These solutions or electrolyte contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.
There are many types of Cu plating solution formulations, some of which are commercially available. One such formulation includes Cu-sulfate (CUSO4) as the copper source (see James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H2SO4), and a small amount of chloride ions. As is well known, other chemicals can be added to the Cu plating solution to achieve desired properties of the deposited material.
The additives in the Cu plating solution can be classified under several categories such as suppressors, levelers, brighteners, grain refiners, wetting agents, stress-reducing agents, accelerators, etc. In many instances, different classifications are often used to describe similar functions of these additives. Today, solutions used in electronic applications, particularly in manufacturing ICs, contain simpler additives consisting of two-component two-ingredient packages (e.g., see Robert Mikkola and Linlin Chen, “Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization”, Proceedings of the International Interconnect Technology Conference, pages 117-119, Jun. 5-7, 2000). These formulations are generically known as suppressors and accelerators.
Suppressors are typically polymer formulated from polyethylene glycol-PEG or polypropylene glycol-PPG and is believed to attach themselves to the substrate surface at high current density regions, thereby forming a high resistance film and suppressing the material deposited thereon. Accelerators are typically organic disulfides that enhance Cu deposition on portions of the substrate surface where they are adsorbed. The interplay between these two additives and possibly the chloride ions determines the nature of the Cu deposit.
The following figures are used to more fully describe the conventional electrodeposition method and apparatus. FIG. 1 illustrates a perspective view of a cross-section of a substrate 3 having an insulator 2 formed thereon. Using conventional etching techniques, features such as a row of small vias 4a and a wide trench 4b are formed on the insulator 2 and the substrate 3. In this example, the vias 4a are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large). Typically, the widths of the vias 4a are sub-micron. The trench 4b, on the other hand, is typically wide and has a small aspect ratio. In other words, the width of the trench 4b may be five to fifty times or more greater than its depth.
FIGS. 2a-2c illustrate a conventional method for filling the features with Cu. FIG. 2a illustrates a cross sectional view of the substrate 3 in FIG. 1 having various layers disposed thereon. For example, this figure illustrates the substrate 3 and the insulator 2 having deposited thereon a barrier/glue or adhesion layer 5 and a seed layer 6. The barrier layer 5 may be tantalum, nitrides of tantalum, titanium, tungsten, or TiW, etc., or combinations of any other materials that are commonly used in this field. The barrier layer 5 is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD), or by electroless plating methods. Thereafter, the seed layer 6 is deposited over the barrier layer 5. The seed layer 6 material may be copper or copper substitutes and may be deposited on the barrier layer 5 using various sputtering methods, CVD, or electroless deposition or combinations thereof.
In FIG. 2b, after depositing the seed layer 6, a conductive material 7 (e.g., copper layer) is generally electrodeposited thereon from a suitable acidic or non-acidic plating bath or bath formulation. During this step, an electrical contact is made to the Cu seed layer 6 and/or the barrier layer 5 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the Cu material 7 is electrodeposited over the substrate surface using the specially formulated plating solutions, as discussed above. By adjusting the amounts of the additives, such as the chloride ions, suppressor/inhibitor, and the accelerator, it is possible to obtain bottom-up Cu film growth in the small features.
The Cu material 7 completely fills the via 4a and is generally uniform in the large trench 4b, but does not completely fill the trench 4b because the additives that are used are not operative in large features. For example, it is believed that the bottom up deposition into the via 4a occurs because the suppressor/inhibitor molecules attach themselves to the top of the via 4a to suppress the material growth thereabouts. These molecules can not effectively diffuse to the bottom surface of the via 4a through the narrow opening. Preferential adsorption of the accelerator on the bottom surface of the via 4a results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile as shown in FIG. 2b. Without the appropriate additives, Cu can grow on the vertical walls as well as the bottom surface of the via 4a at the same rate, thereby causing defects such as seams and/or voids.
Adsorption characteristics of the suppressor and accelerator additives on the bottom surface of the large trench 4b is not expected to be any different than the adsorption characteristics on the top surface of the field regions 8 of the substrate. Therefore, the Cu thickness t1 at the bottom surface of the trench 4b is about the same as the Cu thickness t2 over the field regions 8.
As can be expected, to completely fill the trench 4b with the Cu material 7, further plating is required. FIG. 2c illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t3 over the field regions 8 is relatively large and there is a step s1 from the field regions 8 to the top of the Cu material 7 in the trench 4b. For IC applications, the Cu material 7 needs to be subjected to CMP or other material removal process so that the Cu material 7 as well as the barrier layer 5 in the field regions 8 are removed, thereby leaving the Cu material 7 only within the features. These removal processes are known to be quite costly.
Thus far, much attention has been focused on the development of Cu plating chemistries and plating techniques that yield bottom-up filling of small features on substrates. This is necessary because, as mentioned above, lack of bottom-up filling can cause defects in the small features. As part of these development efforts, it was discovered that the filling behavior of the small features could be affected not only by the solution chemistry, but also by the type of the power supply used for electrodeposition.
Recent studies suggest that it might be preferable to use pulse or pulse-reverse plating methods to deposit defect free Cu into the small vias (e.g., U.S. Pat. No. 5,972,192 issued to Dubin et al. on Oct. 26, 1999, and Gandikota et al. “Extension of Copper Plating to 0.13 um Nodes by Pulse-Modulated Plating”, Proceedings of the International Interconnect Technology Conference, pages 239-241, Jun. 5-7, 2000). In the pulse-reverse plating process, a cathodic voltage pulse rather than a cathodic DC voltage is applied to the substrate surface. After a short period of plating during the cathodic pulse, the polarity of the voltage is reversed for a brief period causing electrochemical etching from the deposited material. Plating and etching cycles are then repeated until the small features are filled with high quality Cu. A recent study (e.g., C. H. Hsieh et al., “Film Properties and Surface Profile after Gap Fill of Electrochemically Deposited Cu Films by DC and Pulse Reverse Processes”, Proceedings of the International Interconnect Technology Conference, pages 182-184, Jun. 5-7, 2000), shows that the filling of the vias is controlled mainly by the additive diffusion when the DC process is used, whereas it is mainly controlled by additive adsorption when a pulse-reverse process is used.
As described above, the attention in the semiconductor industry has mainly been concentrated on filling the various features on semiconductor wafers with Cu. Both DC and pulsed power supplies have been used in the deposition of these Cu films. Filling properties of Cu into small features was found to be a strong function of the type of the power supply used. Although the exact roles of the plating solution additives and their interaction with the applied voltage waveforms are not well understood, it is clear that the kinetics of the additive adsorption and diffusion processes influence the way metals deposit on non-planar substrate surfaces.
As mentioned above, special bath formulations and pulse plating processes have been developed to obtain bottom-up filling of the small features. However, these techniques have not been found effective in filling the large features. In large features, the additives can freely diffuse in and out of them. The use of standard pulse plating techniques in conjunction with the commonly used additive systems containing chloride ions, accelerators and suppressors/inhibitors do not yield accelerated growth from the bottom surface of the features where the width of the feature is considerably larger than its depth. The growth of Cu in such features is conformal and the film thickness deposited on the bottom surface of the large features is approximately the same as that deposited on the field regions.
Methods and apparatus to achieve accelerated bottom-up plating in small as well as large features on a substrate would be invaluable in terms of process efficiency and cost since such a process would yield a Cu deposit that is generally planar as illustrated in FIG. 3. The Cu thickness t5 over the field regions 8 in this example is smaller than the traditional case as shown in FIG. 2c, and the step height s2 would also be much smaller. Removal of the thinner Cu layer in FIG. 3 by CMP or other methods would be easier, providing important cost savings.
Others have previously recognized attractive features of a plated Cu structure such as the one shown in FIG. 3. For example, in a PCT application (“Electroplated Interconnection Structures on Integrated Circuit Chips”, WO 98/27585, Jun. 25, 1998) researchers from International Business Machines Corporation state that the plating processes described therein produce super-filling of only the sub-micron size cavities when plating was carried out in a conventional plating cell. However, it also states that a further benefit could be realized when a cup plating cell is used as described in U.S. Pat. No. 4,339,319 issued on Jul. 13, 1982, to Aigo. In addition, when the substrate surface was held in contact with the meniscus of the electrolyte during plating in a cup plating cell, cavities of greatly different widths could be filled rapidly at the same rate yielding a structure similar to that shown in FIG. 3. The PCT application also mentions that superior performance of the meniscus plating approach was due to the higher concentration of the surface active additive molecules at the air-liquid interface.
In the co-pending U.S. application Ser. No. 09/201,928, entitled “Method and apparatus for electrochemical mechanical deposition”, commonly owned by the assignee of the present invention, a technique is disclosed that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited. The plating electrolyte in this application is supplied to the small gap between the pad and the substrate surface through a porous pad or through asparities in the pad.
FIG. 4 shows a schematic depiction of an electrochemical mechanical deposition apparatus that can be used for planar or near-planar Cu deposition on a semiconductor wafer. A carrier head 10 holds a semiconductor wafer 16 and provides an electrical lead 17 connected to the conductive portion of the wafer 16. The head 10 can be rotated clockwise or counter-clockwise about a first axis 10b and can be moved in x, y, and z directions. A pad 18 is provided on top of an anode assembly 19, which pad 18 faces the wafer 16. An electrolyte 20 containing the plating material is applied to the wafer 16 surface using the anode assembly 19. The electrolyte 20 can be flowed through the holes/openings in the pad 18, which makes physical contact with the wafer 16 surface. The electrolyte 20 then flows in the narrow gap between the wafer 16 and the pad 18, eventually flowing over the edges of the pad 18 into a chamber 22 to be re-circulated (not shown) after cleaning/filtering/refurbishing. A second electrical lead 24 is connected to the anode assembly 19. Any other known method for providing the electric potentials to the anode assembly 19 and cathode wafer 16 can be used herein.
The anode assembly 19 can also be rotated around a second axis 10c at controlled speeds in both the clockwise and counter-clockwise directions. It is also understood that axes 10b and 10c are substantially parallel to each other. The gap between the wafer 16 and the pad 18 is adjustable by moving the carrier head 10 in the z direction. When the wafer 16 surface and the pad 18 are in contact, the pressure that is exerted on the two surfaces can also be adjusted. The co-pending U.S. application Ser. No. 09/511,278, entitled “Pad Designs and Structures for a Versatile Materials Processing Apparatus”, filed Feb. 23, 2000, describes various shapes and forms of the holes in the pad 8, through which the electrolyte flows to the wafer surface.
During operation, a potential is applied between the electrical lead 17 to the wafer 16 and the electrical lead 24 to the anode assembly 19, making the wafer 16 surface more negative than the anode assembly 19. The electrolyte 20 can be introduced to the pad 18 from a reservoir (not shown) located in proximity to the anode assembly 19. The anode assembly 19 can have an in-channel and holes that are made therein, which together provide a path for the electrolyte 20 to be fed to the gap between the pad 18 and the wafer 16.
Under applied potential, Cu plates out of the electrolyte 20 onto the wafer 16 surface. The moving pad 18 that is pushed against the wafer 16 surface at a controlled pressure minimizes accumulation of Cu over certain portions of the wafer 16 surface by polishing the same.
The pad 18 is preferably nonconductive, hard, porous, or perforated type material so that an electric field can pass through it, while preventing shorting between the anode assembly 19 and the cathode wafer 16. The spacing or gap between the pad 18 and the cathode wafer 16 may range from less than 1 micron up to 2 millimeter. The diameter or cross sectional length of the pad 18 and the wafer 16 may range from about 5 millimeter to over 300 millimeter. The larger the wafer 16 diameter, the larger the pad 18 diameter.
USPTO Backgrounds
USPTO Backgrounds