1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Recently, as shrinkage of an electronic device and increase in capacity thereof have been required, shrinkage of a semiconductor device integrated and increase in capacity thereof have been in progress. As a result, a Chip-On-Chip (CoC) semiconductor device has been on the development in which semiconductor chips each having a through electrode are stacked and mounted.
Japanese Unexamined Patent Application, First Publication No. JP-A-2007-214220 discloses the CoC (Chip-On-Chip) semiconductor device. The CoC semiconductor device has a configuration that a plurality of semiconductor chips are stacked and mounted on a wiring board (a semiconductor wafer for an interposer).
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-319243 discloses that stacking the plurality of semiconductor chips over the wiring board using an underfill material may cause a void. To suppress the void formation between the semiconductor chips, a resin can be used having a viscosity lower than that of the underfill material. Japanese Unexamined Patent Application, First Publication, No. JP-A-2000-124164 discloses a method of suppressing the void formation by performing a sealing process under depressurized condition.
If semiconductor chips stacked and mounted have different chip sizes, the underfill material is not well-filled between the semiconductor chips. Any voids may be formed in gaps between the semiconductor chips.
If the temperature of the semiconductor device is increased in a reflow process gas in voids in the underfill material will expand. The gas expansion way cause cracking between the semiconductor chip and the wiring board or the semiconductor chips. As a result, flip chip connection are weakened and the reliability of the semiconductor device deteriorates.
In a CoC (Chip-On-Chip) semiconductor device of the related art, the plurality of semiconductor chips is stacked and mounted on the wring board (the semiconductor wafer for the interpose), resulting in the increased thickness of the package.
USPTO Backgrounds
USPTO Backgrounds