The present invention relates to a multiple processor electronic data processing system, and more particularly to such a system having a Multibus II or similar system bus (Multibus II is a trademark of the Intel Corporation, Santa Clara, Calif.).
A system bus performs two major functions in an electronic data processing system. First of all, it transfers data. A data transfer is typically made by sequentially transferring a group or block of words from one agent, such as a processor, a random access memory, a peripheral, etc., to another agent. This group or block of sequential words is often referred to as a data packet or a data burst. Typically, data transfers are the predominant function performed by the system bus.
The second function of the system bus is to control the next system function, such as which agent will make a data transfer. One or more control conductors are typically included as part of the system bus to interconnect the agents on the system bus. A priority and/or contention subsystem is usually included in order to provide each agent the access to the system bus that it requires.
Thus, the main function of the system data bus is to transfer data. It is logical then that bus efficiency is defined as a result of dividing an amount of time that is occupied transferring data by an amount of time that is preselected as a sample period, and subsequently converting the result into a percentage. With such a definition, when the bus system is in the midst of an extremely lengthy data block transfer, the measured bus efficiency will approach one hundred per cent. Thus, as a general rule for meaningful efficiency measurements, the duration of the sample period should be somewhat greater than the duration of the longest data block.
The control function, on the other hand, is typically viewed as a necessary evil. The time periods that are used to manage and apportion the utilization of the system bus are generally grouped together and referred to as overhead. Overhead is the remainder when the data transfer efficiency is less than one hundred per cent.
From an efficiency standpoint, the ideal electronic data system would store up data, wait for access to the system data bus, and then transfer data between agents in very large blocks. Unfortunately, most systems cannot operate in that manner. Systems which have only a single processor typically cannot have the processor monopolized with data transfers concerning a single agent to the exclusion of the other agents within the system. Similarly, systems with a single system bus cannot have the system bus monopolized by two agents constantly transferring lengthy data blocks between each other. It is axiomatic that all the other agents cannot wait forever; because, if the other agents could wait forever there would not be any reason to include them into the system in the first place. This means that each agent must be afforded a periodic opportunity to transfer data over the system bus.
Thus, on one hand is the ideal of one hundred per cent efficiency of the system data bus, and on the other hand is the reality that data transfers must be short enough to allow each agent on the system bus periodic access to the bus. To achieve high data transfer efficiency, a small number of lengthy data blocks are desirable; but to achieve a high accessibility among agents, a large number of short data blocks are desirable. The problem of the system designer is how to balance these two competing demands. This balancing problem has been accentuated by the fact that the block length is almost universally fixed by the operating system hardware or software and cannot be changed without a hardware or software change. Since it is all but unchangeable, a data block length is typically selected to provide each agent with sufficient data transfer time periods occurring with sufficient frequency to meet essential control and data transfer requirements. After all the essential requirements have been met, and if any bus capability remains, the length of the data blocks may then be selected to optimize the data transfer efficiency for what is considered to be the typical operating condition. If this approach followed, the result is that the system bus has only a single data block length available. This single block will of necessity be a compromise between bus efficiency and data latency considerations.
Thus, it is an object of the present invention to provide a data system bus which may be optimized for a plurality of differing operating conditions.
It is another object of the present invention to provide each agent of a data system bus with means to select a data block length that is closest to the optimal data block length for that agent's next data transfer.
It is a further object of this invention to provide a method for selecting a block length that is closest to the optimal data block length for the agent's next data transfer.
USPTO Backgrounds
USPTO Backgrounds