1. Field of the Invention
The present invention relates to a nonvolatile storage device and a method of manufacturing the same, and a storage device and a method of manufacturing the same.
2. Description of the Related Art
In a semiconductor nonvolatile memory joined the mainstream at present, size of the minimum processing line width capable of drawing by lithography (hereinafter, referred to as photolithography) using light or X-ray is one of factors restricting storage capacity. In the photolithography, there exists a limit in miniaturization of processing line width, and therefore, an increase of storage capacity with miniaturization cannot be expected in future. With respect to such photolithography, lithography technology using a self-organization pattern such as nanoimprint and a block copolymer has been proposed recently. The minimum processing line width can be small in such lithography, as compared with photolithography for use in manufacturing of a known semiconductor memory.
Furthermore, a probe memory which uses a probe (needle) using principle of a Scanning Probe Microscope (referred to as SPM) is conventionally proposed (for example, “The “millipede” project”, [online], IBM, [retrieved on Jul. 21, 2005], Retrieved from the Internet, <URL: http://www.zurich.ibm.com/st/storage/millipede.html>, Michel Despont, Ute Drechsler, R. Yu, H. B. Pogge, and P. Vettiger, Journal of Microelectromechanical Systems, 13, 895(2004)., H. Pozidis, Member, W. Haberle, D. Wiesmann, U. Drechsler, M. Despont, T. R. Albrecht, and E. Eleftheriou, IEEE Transactions on Magnetics, 40, 2531(2004)., H. Jonathon mamin, Robert P. Ried, Bruce D. Terris, and Daniel Rugar, Proceedings of the IEEE, 87, 1014(1999).). The probe memory uses thousands of arm type devices so called a cantilever having a sharp nanoscale leading end like a probe of SPM and microscopic holes representing respective bits are made on a thin plastic film to constitute a memory in which a state where a hole is present represents “1” of 1 bit; a state where a hole is absent represents “0”.
However, there is a problem in that nanoimprint, more particularly, patterning by the hot embossing method cannot be applied to semiconductor memories with the same structure as a conventional semiconductor memories, because size Δx as the tolerance of a position deviation when performs superposition necessary for pattern positioning to form a pattern of the next process in response to a pattern formed in the former process is larger than the minimum processing dimension f.
For example, in manufacture of semiconductor nonvolatile memories, for example, a NAND type flash memory, high positioning accuracy lithography is required in connection between ends of memory cell columns coupled together in a NAND type and bit lines or source lines and between bit lines and a sense amplifier. Such connection is performed by vias. In a via forming process, contact holes are formed in electrode patterns and elements and in an insulation layer thereabove by etching, and electrode patterns are further formed thereabove after making plugs. Therefore, in lithography used in forming such patterns, deviation size ΔX in positioning needs to be smaller than the minimum processing dimension F. That is, when an ordinary large-scale integration (referred to as LSI) is manufactured, lithography in which positioning deviation ΔX is smaller than the minimum processing dimension F is required for connection between wiring made for memory cells and peripheral circuits such as a sense amplifier and an address decoder, but not required for the memory cell portion itself.
Furthermore, in probe memories, different from general semiconductor memories, there is a problem in that access speed of reading, writing, and erasing is slow because mechanical operation is involved and parallel access to reading, writing, and erasing cannot be performed. Further, parallel operation which simultaneously performs access to reading, writing, and erasing by arranging a plurality of probes (needles) like a probe memory disclosed in the above first document is proposed. However, there is a limit to the parallel operation because a driving mechanism becomes too minute and miniaturization of the probe is difficult, as compared with wiring in the semiconductor memory.
USPTO Backgrounds
USPTO Backgrounds