Metal-oxide-silicon ("MOS") devices are fabricated on a substrate wherein source and drain regions are spaced-apart a distance defining an equivalent electrical channel length L.sub.eff. A gate overlies and is separated from the channel by a gate oxide. In use, a V.sub.cc potential is presented to the device from drain to source, and a gate-source potential is coupled to the gate. The gate-source signal modulates the channel conductivity and, in a digital application, turns the MOS device on or off.
As process geometries shrink, electric fields present within the MOS device increase, since the distances across which potentials act is diminished. The resultant high magnitude electric fields generate hot carriers, which are electrons accelerated to relatively high velocities.
Hot carriers can become trapped in MOS oxides and can detrimentally affect MOS device performance, altering, for example, device threshold voltage levels and degrading drain-source current I.sub.ds. Hot carrier lifetime is typically a measurement of the length of time it takes for the MOS device drain-source current I.sub.ds to degrade an arbitrary amount, for example 10%. From the standpoint of MOS device reliability, the hot carrier lifetime should be as long as possible. Because electric fields create hot carriers, hot carrier generation may be reduced by decreasing the V.sub.cc power supply magnitude and/or by lengthening the device channel length.
However, although a long channel length MOS device operating at low V.sub.cc might be reliable, the device would not be able to perform at higher switching speeds. The perennial need for higher speed switching characteristics dictates using the largest possible drain-source current. In modern production processes, the maximum value for device current can be limited by hot carrier lifetime, rather than by process lithography and/or manufacturing equipment. In this situation, a business decision must be made between reliability on one hand, and high speed performance on the other hand.
Thus the maximum I.sub.ds is chosen based upon the minimum value of hot carrier lifetime acceptable by the MOS device manufacturer for device outgoing reliability.
Unfortunately, the normal range of process variations associated with integrated circuit fabrication can yield MOS devices whose effective channel length can vary by as much as 30% to 40% from the process minimum to maximum L.sub.eff range. Thus in practice, prior art fabrication plants are designed to produce MOS devices whose minimum L.sub.eff will exceed a certain dimension yielding a device that meets a minimum hot carrier lifetime.
However, because the majority of the produced devices will not be optimized for hot carrier lifetime versus high speed performance, this mode of production yields too many MOS devices with L.sub.eff too large for optimum high speed performance. On the other hand, where high switching speed is of the utmost consideration, prior art practice is such that the center of the spread of the fabricated devices will have sufficiently small L.sub.eff for high speed switching. But unfortunately, doing so produces too many devices whose L.sub.eff is too small for acceptable hot carrier lifetime and yield.
What is needed is a method and apparatus for determining where, within a production range of L.sub.eff, MOS devices have been fabricated on a particular integrated circuit. Where L.sub.eff is identified as exceeding that required for a desired minimum hot carrier lifetime, such method and apparatus should permit higher speed operation of the integrated circuit by compensating for excess hot carrier lifetime with increased V.sub.cc operating potential. In this fashion, integrated circuit production can be optimized for yield, without sacrificing loss of high speed performance in those devices produced with unnecessarily large L.sub.eff, as contrasted with the prior art. Such method and apparatus would permit even MOS devices having unnecessarily large L.sub.eff to be operated in a regime permitting device performance to approach that of devices produced on an integrated circuit with an optimum minimum L.sub.eff.
Preferably, such method and apparatus should provide a compensation mechanism whereby MOS integrated circuits fabricated with too short a channel length may nonetheless be operated in a lower voltage regime such that hot carrier lifetime exceeds at least a minimal duration. Finally, such a method and apparatus should permit an integrated circuit fabrication process to be optimized for yield rather than for critical control of L.sub.eff and hot carrier lifetime. The present invention discloses such a method and apparatus.
USPTO Backgrounds
USPTO Backgrounds