Standard semiconductor integrated circuits operate based on a preset input logic high voltage level (VIH) and preset logic low voltage level (VIL). The VIH and VIL are typically determined by industry standards. For example, dynamic random access memory (DRAM) devices in complementary metal oxide semiconductor (CMOS) integrated circuits, such levels are typically 0.8 volts plus or minus 100 millivolts for VIL and 2.4 volts plus or minus 100 millivolts for VIH. Transistor-transistor logic trip points are typically 0.8 volts for VIL and 2 volts for VIH. Thus, in traditional non-adjusting trip point input buffers, as the input voltage (VIN) increases to 2 volts and higher, VIN is interpreted as a high logic level. As VIN decreases to 0.8 volts and lower VIN is interpreted as a low logic level. VIN is subject to self induced noise and noise from other lines via inductances, parasitic capacitances, and leakage currents. Trip points are typically set so they do not drift into the range where false highs or lows can be perceived.
For a variety of known reasons such as to reduce power consumption and prevent oscillation due to the input signal fluctuating between the logic high and logic low trip points, TTL level CMOS input buffers have been designed with hysteresis, such as the TTL level CMOS input buffer disclosed in the McAdams U.S. Pat. No. 5,034,623.
An input buffer disclosed in the Lipp U.S. Pat. No. 5,347,177 uses a system clock to determine when to synchronously and dynamically adjust the trip points of a CMOS input buffer to improve switching speed of the input buffer. In addition, this synchronous adjustment of the trip points reduces problems where the incident wave causes voltage overshooting resulting in a hazardous signal of a magnitude greater than the supply voltage. The Lipp input buffer reduces the input threshold voltage or trip point in the direction of the existing input voltage level. For example, when the input level is at a logic low, the input threshold voltage level is adjusted to below 50% of supply voltage for example 30% of supply voltage. Typically, prior fixed input buffers set the threshold voltage level at a nominal 50% of the supply voltage and in order to ensure switching only on a valid noise-immune signal in a conventional receiver, the signal level needs to be 70% of the supply voltage.
The Lipp input buffer operates by making the input threshold voltage level on the input buffer closer to the supply voltage level than to ground when a signal on a controlling lead is a logic low. Alternatively, when the signal on the controlling lead is at a logic high, the input threshold voltage of the input buffer is analogously lower to be closer to the ground voltage. The signal on the controlling lead has a logic state opposite to the input signal. The signal on the controlling lead is delayed by latches controlled by a system clock signal. After a logic state transition on the input signal, the signal on the controlling lead does not change its logic state until after the system clock signal cycles from a logic low to a logic high. This delay of the signal on the controlling lead allows the input signal to fully switch and stabilize before the input threshold voltage level is adjusted. Without this delay circuitry, the input buffer may oscillate.
There is, however, a need for an asynchronous dynamically adjustable input circuit that does not rely on a system clock to switch the trip points of the input circuit.
USPTO Backgrounds
USPTO Backgrounds