1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the device.
2. Description of the Related Art
An active-matrix-addressed display uses an active-matrix substrate on which a huge number of thin-film transistors (TFTs) are arranged in matrix. Those TFTs are integrated together on a substrate of an insulating material such as glass by thin film deposition, photolithography, and other manufacturing technologies similar to normal LSI manufacturing technologies. More particularly, a silicon thin film is deposited on a substrate by a CVD process, for example, and then patterned into a plurality of islands, which will be eventually used as active areas for respective TFTs.
The TFTs fabricated in this manner are roughly classifiable into amorphous silicon TFTs and polysilicon TFTs according to the crystallinity of the silicon thin film to be used. The field effect mobility of a polysilicon film is usually higher than that of an amorphous silicon film. Thus, a polysilicon TFT can operate faster than an amorphous silicon TFT.
By adopting such high-speed-operating polysilicon TFTs, not just switching elements in the display area but also driver circuitry around the display area may consist of TFTs. However, if a source driver (data driver) and other peripheral driver circuits are made up of polysilicon TFTs, then variations will arise in the threshold voltage of the transistors and other TFT characteristics, thus posing a difficult problem in practice.
Meanwhile, a so-called “System on Glass” display system, in which not just peripheral driver circuits but also an image processor, a timing controller and other more sophisticated functional blocks are integrated together on the same substrate, has been extensively researched and developed recently to meet a high demand for that type of display systems.
However, even if just the source driver is additionally integrated, those variations in TFT characteristics are inevitable as described above. Thus, as can be easily expected, it is extremely difficult to integrate together controllers, DA converters and other functional circuits, which should exhibit even higher TFT performance, as a monolithic assembly on a high-strain-point non-alkaline glass substrate.
Also, to make TFTs for such a high-performance functional circuit, the performance of the TFTs needs to be further improved. However, there is a limit on the performance improvement of a polysilicon TFT. This is because a polysilicon film has localized states in gaps resulting from the imperfect crystallinity and defects around the crystal grain boundary, thus decreasing the mobility or increasing the S coefficient (sub-threshold coefficient). Consequently, even a polysilicon film cannot ensure sufficiently high transistor performance.
In view of these considerations, to further improve the performance of TFTs with the variations in their characteristics minimized, it was proposed that a single crystal silicon (single crystal silicon) film be used as an active layer (as a channel region) for the TFTs. A TFT of that type is called a “single crystal silicon TFT”.
Japanese National Stage Publication No. 7-503557 and J. P. Salerno in “Single Crystal Silicon AMLCDs”, Conference Record of the 1994 International Display Research Conference (IDRC), pp. 39-44, 1994 disclose the technique of fabricating a display panel for an active-matrix-addressed LCD by bonding single crystal silicon TFTs, which have been prepared in advance, onto a glass substrate with an adhesive.
However, according to the technique disclosed in Japanese National Stage Publication No. 7-503557, single crystal silicon TFTs, which are high-performance devices, are bonded onto a glass substrate with an adhesive, thus resulting in low yield and poor productivity. Also, after the single crystal silicon TFTs have been bonded onto the substrate, the substrate has bonding portions of the adhesive, and therefore, has low thermal resistance and easily emits gases. Thus, it is virtually impossible to further deposit a high-quality inorganic insulating film or a different group of TFTs on the substrate on which the single crystal silicon TFTs have been bonded.
On top of that, in making an active-matrix substrate using such single crystal silicon TFTs, a device including an array of single crystal silicon TFTs needs to be bonded onto another substrate. For that reason, there are some limits on sizes and costs.
Furthermore, Japanese National Stage Publication No. 7-503557 just discloses the technique of transferring prepared single crystal silicon TFTs onto a glass substrate. However, just by using those simply transferred single crystal silicon TFTs, it is impossible to obtain high-performance, high-function semiconductor devices that are in increasingly high demand these days.
Meanwhile, techniques of fabricating single crystal silicon TFTs on an insulating substrate without using adhesive are disclosed by Q. Y. Tong and U. Gesele, “SEMICONDUCTOR WAFER BONDING”, SCIENCE AND TECHNOLOGY, John Wiley and Sons, New York, 1999. These documents describe a so-called “smart-Cut” (which is a SOITEC Corporation's trademark) method for bonding (or transferring) a single crystal silicon layer with hydrogen embrittlement.
In making an active-matrix substrate for use in an LCD, for example, not just single crystal silicon TFTs but also polysilicon TFTs are preferably integrated on the same substrate together. The applicant of the present application proposed in Japanese Patent Application No. 2003-67109 a method of making an active-matrix substrate in which single crystal silicon TFTs are fabricated on a substrate by utilizing the bonding method described above and then non-single crystal silicon TFTs (e.g., polysilicon TFTs) are fabricated on the same substrate.
Hereinafter, the method proposed in those patent applications will be described with reference to FIGS. 6A through 6H.
First, as shown in FIG. 6A, a substrate 30 with an insulating surface 31 is prepared. Meanwhile, hydrogen ions are implanted at a particular dose level into a single crystal silicon substrate 50 with a silicon dioxide layer 51 on the surface, thereby forming a hydrogen ion implanted layer 55 at a predetermined depth in the single crystal silicon substrate 50. In this process step, a single crystal silicon layer is produced between the hydrogen ion implanted layer 55 and the silicon dioxide layer 51 and will be referred to herein as an “upper single crystal silicon layer”. Optionally, before hydrogen ions have been implanted, the upper single crystal silicon layer may be subjected to either a doping process to define a gate electrode or source/drain regions or a doping process to define a base, a collector and an emitter, thereby forming a thin-film transistor, the surface of which may subsequently be planarized and made hydrophilic. Next, the single crystal silicon substrate 50, in which the hydrogen ion implanted layer 55 has been produced, and the substrate 30 are bonded together such that the silicon dioxide layer 51 of the single crystal silicon substrate 50 is in contact with the insulating surface 31 of the substrate 30. Thereafter, these substrates 30 and 50 are heated to a temperature at which hydrogen ions dissociate themselves from silicon in the hydrogen ion implanted layer 55. As a result, the surface of the single crystal silicon substrate 50 (i.e., the silicon dioxide layer 51) and the insulating surface 31 can be bonded together even more strongly. In addition, micro bubbles are produced in the hydrogen ion implanted layer 55, thereby making the silicon dioxide layer 51 and upper single crystal silicon layer cleavable and removable at the hydrogen ion implanted layer 55 from the single crystal silicon substrate 50. In this manner, a bonded substrate 60, including the single crystal silicon layer 52 and MOS single crystal silicon TFTs, can be obtained without using adhesive as shown in FIG. 6C.
The bonded substrate 60 has a structure in which the surface portion of the single crystal silicon substrate 50 above the hydrogen ion implanted layer 55 (i.e., the upper single crystal silicon layer and the silicon dioxide layer 51) is bonded to the substrate 30. Thus, as shown in FIG. 6C, a big level difference is created between a portion of the bonded substrate 60, to which that surface portion has been bonded (i.e., bonding portion), and the other portions thereof. This level difference is greater than the thickness of the silicon dioxide layer 51 (which is normally in the range of about 100 nm to about 500 nm).
The process steps of fabricating a device, including non-single crystal silicon, on such a substrate 60 will be described as an example.
First, as shown in FIG. 6D, an insulating film 56 of SiO2, for example, and an amorphous silicon film 57 are deposited in this order over the entire surface of the substrate 60. Next, as shown in FIG. 6E, the amorphous silicon film 57 is crystallized into a polysilicon film 57p. Subsequently, as shown in FIG. 6F, the polysilicon film 57p is patterned into a patterned polysilicon layer 57′, which is then covered with a gate insulating film 58 of SiO2. Thereafter, a conductor film (not shown) is deposited on the gate insulating film 58 and then etched into the pattern of gate electrodes 59.
Subsequently, as shown in FIG. 6G, the surface of the substrate 60 is further covered with a passivation film and an interlayer dielectric film 62. Thereafter, as shown in FIG. 6H, metal interconnects 61 are defined on the interlayer dielectric film 62 so as to be electrically connected to the polysilicon layer 57′ and single crystal silicon layer 52 through contact holes that have been provided through the interlayer dielectric film 62 and so on. In this manner, single crystal silicon TFTs and polysilicon TFTs can be fabricated on the same substrate.
According to this method, however, the following problems may arise due to the significant level difference between the bonding portion on the surface of the bonded substrate 60 and the other portions.
The gate electrodes 59 are usually defined by patterning the conductor film (not shown), which has been deposited on the gate insulating film 58, by a dry etching process (see FIG. 6F). In this process step, there are some deep stepped portions 70 on the surface of the substrate 60. Accordingly, some residues of the conductor film may remain on the side surface of those stepped portions 70. Also, if interconnects are defined so as to cross the stepped portions 70, then the interconnects are more likely to disconnect.
As described above, if single crystal silicon devices are fabricated on a substrate by a transfer technique, for example, and then non-single crystal silicon devices are further fabricated on the same substrate, then fine-line interconnects may disconnect or some conductor may be left on the stepped surface portions of the substrate even after the dry etching process, thus possibly affecting the reliability and the yield of the resultant device.
USPTO Backgrounds
USPTO Backgrounds