The present inventive concept relates to semiconductor devices and, more particularly, to semiconductor memory devices having enhanced reliability.
Semiconductor devices have been highly integrated for satisfying high performance and low manufacture costs of semiconductor devices, which are required by users. Since integration of the semiconductor devices is an important factor in determining product price, high integrated semiconductor devices are increasingly demanded. Integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, such that it is greatly influenced by the level of technology for forming fine patterns. However, the extremely expensive processing equipment needed to increase pattern fineness may set a practical limitation on increasing the integration of the two-dimensional or planar semiconductor devices.
To overcome such limitations, three-dimensional semiconductor devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass produce three-dimensional semiconductor memory devices, new process technologies should be developed in such a manner that can provide a lower manufacture cost per bit than two-dimensional semiconductor devices while maintaining or exceeding their level of reliability.
USPTO Backgrounds
USPTO Backgrounds