A conventional voltage comparing circuit is shown in FIG. 1. Two input voltages, V.sub.i+ and V.sub.i-, are applied on a non-inverting input terminal 5 and an inverting input terminal 4, respectively. An output voltage Vo appears on an output terminal 2, the voltage Vo corresponding to the difference between the input voltages, V.sub.i+ and V.sub.i-.
Referring to FIG. 1, the voltage comparing circuit is mainly comprised of a differential amplifier, a level shift circuit, and an output circuit, the differential amplifier comprising p-channel Metal-Oxide-Semiconductor (MOS) transistors M.sub.3 -M.sub.6 and n-channel MOS transistors M.sub.12 -M.sub.14, the level shift circuit comprising p-channel MOS transistors M.sub.7 and M.sub.8 and n-channel MOS transistors M.sub.15 and M.sub.16, and the output circuit comprising a p-channel MOS transistor M.sub.g and an n-channel MOS transistor M.sub.17.
The input voltages V.sub.i+ and V.sub.i- are input to the differential amplifier which amplifies their voltage difference. The two voltages having the amplified voltage difference are applied to the respective gates of the transistors M.sub.7 and M.sub.8 in the level shift circuit.
Given that the input voltage V.sub.i- is a specified reference voltage, when the input voltage V.sub.i+ is less than the reference voltage V.sub.i-, the drain voltage of the transistor M.sub.7 is the threshold voltage V.sub.th of the transistor M.sub.15 and the drain voltage of the transistor M.sub.8 is the high voltage V.sub.cc-h on the high supply voltage terminal 1.
When the input voltage V.sub.i+ increases in excess of the reference voltage V.sub.i-, the gate voltages of the transistors M.sub.7 and M.sub.8 are inverted, so that the drain voltage of the transistor M.sub.7 becomes the voltage V.sub.d voltage-divided by the on-state resistances of the transistors M.sub.7 and M.sub.15 and the drain voltage of the transistor M.sub.8 becomes the low voltage V.sub.cc-l on the low supply voltage terminal 3. To sum up, the drain voltage of the transistor M.sub.7 increases from V.sub.th to V.sub.d, and the drain voltage of the transistor M.sub.8 decreases from V.sub.cc-h to V.sub.cc-l.
When such a voltage change occurs in the level shift circuit, however, charging or discharging current flows into or out of the gate capacitances and the drain and source diffusion capacitances of the transistors in the level shift circuit. This means that the drain voltage of the transistor M.sub.8, that is, the output voltage of the level shift circuit does not increase or decrease until such a charge or discharge terminates. In other words, there is a delay time caused by the charge and discharge which passes between the input voltages changing and the corresponding output of the level shift circuit changing, resulting in delayed response time of the entire voltage comparing circuit.
This conventional circuit operation is simulated and its characteristics is shown in FIG. 2, where the reference input voltage V.sub.i- is 2.5 V, the waveform 21 indicates the input voltage V.sub.i+ increasing from 2.41 V to 2.51 V, and the waveform 22 indicates the output voltage Vo appearing on the output terminal 2 in response to the input voltage V.sub.i+.
USPTO Backgrounds
USPTO Backgrounds