The present invention relates to a method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitor for silicon on insulator (SOI) devices.
Fabricating smaller, more densely packed devices having greater computing capability is a continuing objective in building semiconductor devices. Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology are leading to the development of more complex and faster computer integrated circuits that operate with less power.
Silicon on insulator technology incorporates a buried insulator just below the transistors. Performance of silicon on insulator transistors is increased due to reduced diffusion capacitance and due to the floating body effect resulting in lower threshold voltages as compared to bulk silicon devices. However power supply decoupling capacitance is also reduced due to this same reduced diffusion capacitance and also due to the removal of well to substrate junctions, which supply significant desirable decoupling on bulk silicon products.
A principal object of the present invention is to provide a method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. Other important objects of the present invention are to provide such method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is formed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is formed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers. A connection to the first intermediate silicon layer is formed without making electrical connection to the second intermediate silicon layer.
In accordance with features of the invention, transistors are built in the second intermediate silicon layer including device isolation oxides. A deep trench is formed that extends through one device isolation oxide in the second intermediate silicon layer, the buried oxide layers and the first intermediate silicon layer into the bulk silicon substrate layer. The deep trench is filled with a conductor to create a connection to the bulk silicon substrate layer without making electrical connection to the intermediate silicon layers. A second trench is formed that extends through the shallow buried oxide layer and the second intermediate silicon layer into the first intermediate silicon layer. The second trench is filled with a second conductor to create a connection to the first intermediate silicon layer without making electrical connection to the second intermediate silicon layer.
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