1. Field of the Invention
The present invention relates to improvement of a contact structure of an interconnection in a region having steps in a semiconductor device having a multilayer interconnection structure.
2. Description of the Background Art
In the field of a semiconductor device, increase of integration density and miniaturization of an element structure are required. In order to meet such requirements, a structure is conceived in which a plurality of elements are stacked three-dimensionally on a surface of a semiconductor substrate. Such a stacked type semiconductor device increases integration density of a main surface of the semiconductor substrate; however, it has been pointed out that several problems arise from the fact that an interconnection layer is arranged on a region having steps.
As one example of a semiconductor device having a structure in which semiconductor elements are stacked on a substrate, a structure of an SRAM (Static Random Access Memory) will be described. FIGS. 26 through 28 show a structure of a memory cell of a CMOS type SRAM using a thin film transistor as a load, which is shown in "A Memory Cell with Polysilicon Thin Film Transistor (TFT) for a 4 Mbit SRAM", Tsutsumi et al., Institute of Electronics and Communication Engineers of Japan Technical Report, Vol. 90, No. 48, p7-p13. FIG. 29 is an equivalent circuit diagram of a memory cell of the SRAM. Referring to FIG. 29, a memory cell of a CMOS type SRAM has a pair of CMOS inverters. One CMOS inverter has an n channel MOS drive transistor 20a and a p channel MOS thin film load transistor 21a. The other CMOS inverter has an n channel MOS drive transistor 20b and a p channel MOS thin film load transistor 21b. The gates of transistors 20a, 21a of said one CMOS inverter are cross connected to a store node 25b common to transistors 20b, 21b of said the other CMOS inverter, and the gates of transistors 20b, 21b of said the other CMOS inverter are cross-connected to a stored node 25a common to transistors 20a, 21a of said one CMOS inverter to constitute a flip-flop circuit. The sources of p channel MOS thin film load transistors 21a, 21b are connected to a power supply 23. Each of the sources of n channel MOS drive transistors 20a, 20b is connected to ground. Store nodes 25a, 25b of the flip-flop circuit are connected respectively to n channel MOS transfer transistors 21a, 22b. The gates of n channel MOS transfer transistors 21a, 22b are connected to a word line 27. The drain regions of n channel MOS transfer transistors 21a, 22b are respectively connected to bit lines 26a, 26b.
An operation of writing information into a memory cell will be described. For example, if store node 25a is set at a ground potential, and store node 25b at a power supply potential then bit line 26a is set at a ground level, and bit line 26b at a power supply level. N channel MOS transfer transistors 21a, 22b are turned on by applying a prescribed potential to word line 27.
An operation of reading information from a memory cell will be described. Bit lines 26a, 26b are connected to a sense amplifier circuit. Under the condition, word line 27 is supplied with a prescribed potential to turn on n channel MOS transfer transistors 21a, 22b. As a result, potentials of store nodes 25a, 25b are read to bit lines 26a, 26b.
A specific structure of a memory cell of an SRAM will be described with reference to FIGS. 26 through 28. FIGS. 26 and 27 are plan structural views of a memory cell. For convenience, the memory cell is divided into a lower layer portion and an upper layer portion of a substrate to show a plan structure of the lower layer portion of the memory cell in FIG. 26 and a plan structure of the upper layer portion in FIG. 27. FIG. 28 is a sectional structural view taken along line X--X in FIGS. 26 and 27. Referring to FIGS. 26 through 28, the memory cell of an SRAM comprises n channel MOS drive transistors 20a, 20b and n channel MOS transfer transistors 21a, 22b, etc. in a lower region closer to a surface of a silicon substrate 1. P channel MOS thin film load transistors 21a, 21b are arranged in an upper region formed on a main surface of silicon substrate 1 with an interlevel insulating layer 9 interposed.
Referring mainly to FIG. 28, a p well region 2 is formed on a surface of silicon substrate 1. A field oxide film 4 and a p.sup.+ isolation region 3 are formed in an isolation region on a main surface of p well region 2. An n channel MOS drive transistor 20a and an n channel MOS transfer transistor 22b each comprises n.sup.+ source/drain regions 7, 7, a gate oxide film 5 and gate electrode 6. Gate electrode 6 has a polycide structure formed of a polycrystalline silicon layer 6a and a metal silicide film 6b which was formed on a polycrystalline silicon layer 6a.
The surface of silicon substrate 1 is covered with a thick interlevel insulating layer 9. The p channel thin film load transistor 21b is formed on a surface of interlevel insulating layer 9. A thin film transistor 14 comprises a gate electrode 8b formed on the surface of interlevel insulating layer 9, a gate oxide film 13 covering a surface of gate electrode 8b, p.sup.+ source/drain regions 12a, 12c, and a channel region 12b. P.sup.+ source/drain regions 12a, 12c and channel region 12b are formed in a thin polycrystalline silicon layer having a thickness of about 20 nm. Gate electrode 8b includes impurity of p type.
An interconnection structure of store node 25b in which n channel MOS drive transistor 20a is formed in a lower layer, n channel MOS transfer transistor 22b, and p channel MOS thin film load transistor 21b are formed in an upper layer will be described. An opening 16 is formed in interlevel insulating layer 9. Inside opening 16, gate electrode 6 of n channel MOS drive transistor 20a and one of n.sup.+ source/drain regions 7 of n channel MOS transfer transistor 22b is exposed. An interconnection layer 8a of polycrystalline silicon is formed inside opening 16 and connected simultaneously to gate electrode 6 of n channel MOS drive transistor 20a and n.sup.+ source/drain region 7 of n channel MOS transfer transistor 22b. Such a contact structure is termed shared contact. A portion of interconnection layer 8a extends to the surface interlevel insulating layer 9. A polycrystalline silicon layer constituting a p.sup.+ source/drain region 12a of p channel MOS thin film load transistor 21b is connected to a surface of the interconnection layer 8a. Interconnection layer 8a is formed of polycrystalline silicon, and p type impurity is included therein to provide conductivity. At the bottom portion of opening 16, a titanium silicide layer 11 is formed between interconnection layer 8a and source/drain region 7. Titanium silicide layer 11 prevents the formation of pn junction caused by direct connection of interconnection layer of p type 8a and source/drain region of n type 7. A structure this typed is termed a direct contact structure in which interconnection layer 8a arranged on the surface of interlevel insulating layer 9 is connected to a lower layer, for example, an impurity region formed on the silicon substrate, through opening 16.
However, when a direct contact structure is formed to have large differences of level such as interconnection layer 8a used for the above mentioned memory cell of an SRAM, there is a problem that patterning of an interconnection layer is difficult. FIG. 30 is a sectional view showing a manufacturing step of forming interconnection layer 8a shown in FIG. 27. After opening 16 is formed in interlevel insulating layer 9, polycrystalline silicon layer 8 is deposited on the whole surface using, for example, a CVD method. A resist is applied onto a surface of the polycrystalline silicon layer 8. The resist is developed to have a prescribed pattern shape after exposure, using a photolithography method, to form a resist mask. A polycrystalline silicon layer 8 is etched using a resist mask, and interconnection layer 8a and gate electrode 8b of thin film transistor 14 are formed.
Polycrystalline silicon layer 8 is formed on the surface of interlevel insulating layer 9 having steps as shown. There are large steps of the polycrystalline silicon layer in the vicinity of opening 16. It is extremely difficult to form a very small resist mask on the surface of polycrystalline silicon layer 8 having such large steps, using an exposure technology. A recent exposure device particularly tends to reduce depth of focus. Therefore, a resolution of the resist mask deteriorates, which causes a problem that a pattern of interconnection layer 8a formed of the polycrystalline silicon layer becomes indistinct. Degradation of precision of an interconnection pattern hinders miniaturization of interconnection and impairs reliability of interconnection.
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