The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of self-aligned multiple patterning.
Device structures, which have been fabricated on a substrate during front-end-of-line processing, may be connected with each other and with the environment external to the chip by an interconnect structure. Self-aligned patterning processes used to form a back-end-of-line interconnect structure involve the formation of linear mandrels acting as sacrificial features that establish a feature pitch. Sidewall spacers are formed adjacent to the sidewalls of the mandrels and non-mandrel lines are arranged as linear spaces between the sidewall spacers. After pulling the mandrels to define mandrel lines, the sidewall spacers are used as an etch mask to transfer a pattern predicated on the mandrel lines and the non-mandrel lines into an underlying hardmask. The pattern is subsequently transferred to a dielectric layer to define trenches in which the wires of the back-end-of-line interconnect structure are formed.
Mandrel cuts may be formed in the mandrels in order to section the mandrels and define discontinuities between the sections, which are filled by merged portions of the subsequently-formed sidewall spacers. After the mandrel cuts are formed, non-mandrel cuts may also be formed along non-mandrel lines and may include portions of the material used to form the sidewall spacers. The mandrel cuts and non-mandrel cuts are included in the pattern that is transferred to the hardmask and subsequently transferred from the hardmask to form the trenches in the dielectric layer. The mandrel cuts and non-mandrel cuts appear in the interconnect structure as adjacent wires that are spaced apart at their tips with a tip-to-tip spacing related to the dimension of the discontinuity.
The mandrel cuts and the non-mandrel cuts may be sequentially formed by patterning a spin-on hardmask to define respective high-aspect ratio pillars. For each type of cut, the pillars function as etch masks during subsequent etching processes. The organic material of the patterned spin-on hardmask is characterized by a low hardness and weak adhesion, and may exhibit poor macro-loading when performing reactive ion etching. These negative properties of organic materials may lead to pillar flapping or even missing pillars that each are capable of producing systematic defects in the interconnect structure.
Improved methods of self-aligned multiple patterning are needed.
USPTO Backgrounds
USPTO Backgrounds