The present invention relates generally to computer memories and more particularly computer memories of the type in which a given memory can be accommodated to operate with different computer systems having different timing requirements without modifying the memory and in which several memory modules possessing memory chips of different timing characteristic requirements may be used with the same computer without the necessity for modifying the timing signals from the computer to the different memory modules.
Most large computer companies manufacture several different types of computers with varying capacities and operating speeds. Generally the memory system for each different type of computer is custom designed for the particular computer in which the memory is to be utilized. In designing such computer systems the requirements of the particular memory selected are accommodated for by designing the computer-memory interface, or memory controller, in such a way as to provide the memory modules with the necessary timing signals required to read and write the information. The memory and computer were thus designed together to optimize the best features of each.
Generally such memories could be utilized for that one computer only and would not be adaptable to utilization in other computers with different timing characteristics.
In many prior art memory systems if two words were to be sequentially read out of different address locations in a particular memory module it was necessary to provide the same delay time for addressing the second word as was required for reading the first.
USPTO Backgrounds
USPTO Backgrounds