1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of generating circuit layouts using self-aligned double patterning (SADP) techniques.
2. Description of the Related Art
There have been many advancements in the area of manufacturing of semiconductor devices. Various processes are performed on semiconductor substrates in manufacturing integrated circuit products. Photolithography is one of the basic processes used in manufacturing integrated circuit products. Generally, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to alight generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching and/or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
The ultimate goal in integrated circuit fabrication is to accurately reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength immersion photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as multiple patterning, e.g., double patterning. Generally speaking, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern s printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be impossible using existing photolithography tools.
The Self-Aligned-Double-Patterning (SADP) process is one such multiple) technique. The SADP process may be an attractive solution for manufacturing next-generation devices, particularly metal routing lines on such next-generation devices, due to better overlay control that is possible when using an SADP process.
FIGS. 1A-1K depict one illustrative example: of a device 10 wherein an illustrative prior art SADP process was performed to form metal features, e.g. metal lines, in a layer of insulating material 12. With reference to FIG. 1A, a hard mask layer 14 is formed above the layer of insulating material 12 and a layer of mandrel material 16, such as poly silicon, was formed above the hard mask layer 14. Also depicted is a patterned layer of photoresist material 17, that was formed above the layer of mandrel material 16 using traditional, single exposure photolithography tools and techniques. The layer of mandrel material 16 may be comprised of a material that may be selectively etched with respect to the hard mask layer 14.
Next, as shown in FIG. 1B, an etching process is performed on the layer of mandrel material 16 while using the patterned layer of photoresist material 17 as an etch mask. This etching process results in the formation of a plurality of mandrels 16A. In the depicted example, the mandrels are formed so as to have a pitch 16P and a minimum width 16W. The pitch 16P and the width 16W may vary depending upon the particular device 10 under construction. FIG. 1C depicts the device 10 after the patterned layer of photoresist 17, i.e. the mandrel mask, has been removed.
Next, as shown in FIG. 1D, a layer of spacer material 18 was deposited on and around the mandrels 16A by performing a conformal deposition process. The layer of spacer material 18 should be a material that may be selectively etched relative to the mandrels 16A and the hard mask layer 14. FIG. 1E depicts the device 10 after an anisotropic etching process was performed on the layer of spacer material 18 to define a plurality of sidewall spacers 18A, having a lateral width 18W, positioned adjacent the mandrels 16A. The width 18W of the spacers 18A may vary depending upon the particular device 10 under construction. As an example, in order to form patterns with 1:1 ratio line and space, the width of the spacers 18A need equal to the width of the mandrel 16A. Next, as shown in FIG. 1F, the mandrels 16A are removed by performing an etching process that is selective relative to the hard mask layer 14 and the sidewall spacers 18A.
FIG. 10 depicts the device 10 after a patterned photoresist mask 20, a so-called block mask, is formed above the layer of spacers 18A and the hard mask layer 14. In one example, the block mask 20 may be formed using traditional, single exposure photolithography tools and techniques. FIG. 1H depicts the device 10 after an etching process has been performed to transfer the pattern defined by the combination (or union) of the sidewall spacers 18A and the block mask 20 to the hard mask layer 14. FIG. 1I depicts the device 10 after one or more process operations were performed to remove the sidewall spacers 18A and the block mask 20 from above the now-patterned hard mask layer 14. Next, as shown in FIG. 1J, an etching process was performed on the layer of insulating material 12 through the patterned hard mask 14 to define illustrative trenches 22 in the layer of insulating material 12. FIG. 1K depicts the device 10 after schematically depicted metal features 24, e.g., metal lines, were formed in the trenches 22 and after the patterned hard mask layer 14 was removed. The manner in which such metal features 24 may be formed in the layer of insulating material 12 are well known to those skilled in the art.
In the SADP process, the metal features 24 that are formed are typically referred to as the “mandrel-metal” features (“MM”) or “non-mandrel-metal” features (“NMM”). As depicted in FIG. 1K, the al features 24 that are positioned under the location where the mandrels 16A and the features of the mandrel mask 17 (both shown in dashed lines in FIG. 1K) were located, are so-called “mandrel-metal” features designated as “MM” in FIG. 1K. All of the other metal features 24 formed in the layer of insulating material 12 are “non-mandrel-metal” features designated as “NMM” in FIG. 1K. As it relates to terminology, the MM features and NMM features are referred to as being different “colors” when it comes to decomposing an overall pattern layout that is intended to be manufactured using an SADP process, as will be described more fully below. Thus, two MM features are said to be of the “same color” and two NMM features are said to be of the “same color, while an MM feature and an NMM feature are said to be of “different colors.”
To use double patterning techniques, an overall pattern layout for a circuit must be what is referred to as double patterning compliant. Double patterning compliant generally refers to an overall pattern layout being decomposed into two separate patterns, such that each may be formed using existing photolithography tools and other techniques. An overall pattern layout may have many regions or areas that cannot be directly printed because the plurality of closely spaced features in those regions are spaced too close to one another for existing photolithography tools to be able to such closely spaced features as individual feature. To the extent a particular region under investigation has an even number of such features, such a pattern is sometimes referred to as an “even cycle” pattern, while a region that has an odd number of features is sometimes referred to as an “odd cycle” pattern. “Even” cycle patterns can be formed using double patterning techniques, while “odd” cycle patterns cannot be formed using double patterning techniques.
One well-known double patterning technique is referred to as LELE (“litho-etch-litho-etch) double patterning. As the name implies, the LELE process involves forming two photoresist etch masks and performing two etching processes to transfer the desired overall pattern to a hard mask later that is then used as an each mask to etch an underlying layer of crial. With respect to terminology, the different masks employed in the LELE double patterning process are said to be different “colors.” Thus, depending upon the spacing between adjacent features, the features may be formed using the same photoresist mask (“same color”) or they may have to be formed using different photoresist masks (“different color”). In an LELE process, if two adjacent features are spaced apart by a distance that can be patterned using traditional single exposure photolithography, then those two adjacent features may be formed using the same (“same color”) photoresist mask. In contrast, if the spacing between the two adjacent features is less than can be formed using single exposure photolithography, then those features must be either formed using different photoresist masks (“different color”) or the spacing between the features must be increased by changing the circuit layout such that hey may be formed using the same photoresist mask.
As noted above, any circuit layout to be formed using double patterning techniques must be checked to confirm that it can be decomposed into two separate photoresist masks. A layout must have zero odd-cycles to be decomposable in an LELE process. To determine if a circuit layout is double-patterning compliant, a mask engineer, using very sophisticated and well-known computer programs, connects adjacent features by “drawing” a “polygon loop” that connects the centroid of the features under investigation. FIG. 1L, contains a simplistic example of such a polygon loop 30 drawn for live (A-E) adjacent features. The polygon loop 30 is comprised of five edges 31. In this example, due to the relative spacing between adjacent features, all of the features are required to be formed using “different color” (“DC”) masks. Thus, the polygon loop 30 has five “DC” edges connecting the various features. The polygon loop 30 represents an odd-cycle layout due to the odd number of DC edge (five total) in the polygon loop 30. Due to the odd number of DC edges in the polygon loop 30, the pattern reflected by the polygon loop 30 is not decomposable using double pattering techniques.
The SADP odd cycle check is generally more complicated than the LELE odd cycle check due to the complicate SADP design rules. One example of an SADP design rule is shown in FIG. 1M. The example of FIG. 1M illustrates that when two features are spaced between 72 nm and 120 nm, they must be on same color, i.e., both of the features are either MM or NMM. This “must-on-same-color” spacing rule is SADP specific as, in LELE, two features that are separated by a distance larger than same color spacing rule can be put on either same mask or different masks. Correspondingly, a SADP polygon loop for odd cycle check will compose same color edge (SC). One example of SADP polygon loop 32 is shown in FIG. 1N, which consists of three different color (DC) edge and two same color (SC) edges and is not decomposable due to the odd number of DC edges.
In an LELE router, the odd cycle is generally checked continuously while generating metal connection wires to assure; there is zero odd cycle in the final routing layout. However, in an SADP router, given the complexity of SADP design rules and odd cycle check, it can be time consuming and may cause inaccuracies if the SADP odd cycles were continuously checked while generating metal connection wires. Instead of checking SADP odd cycles, circuit designers often perform circuit layout to assure that the circuit design is decomposable. One common SADP design restriction to assure decomposable SADP layout entails using discrete metal widths that are integer number factors of a default width. In examples of a default metal width of 24 nm, the allowed metal width will be 48 nm, 72 nm, 96 nm, 120 nm, etc.
Another common strategy to comply with SADP rules entails uni-directional application of features on grid design, as illustrated in FIG. 1P. FIG. 1P depicts a simplistic example of a prior art circuit layout, e.g., a plurality of metal lines 52 that are to be formed using an SADP process. The metal lines 52 may be representative of metal lines that are to be formed in the metal-2 (M2) layer of an integrated circuit product. The dotted lines in FIG. 1P may be metal routing tracks may have alternating color assignments. The uni-direction on grid design however imposes further restriction on metal width as will be clarified below.
FIG. 1Q depicts a simplistic example of a prior art circuit layout, e.g., a plurality of metal lines 52, 56, 58 that are to be formed using an SADP process. The metal lines 52, 56, 58 may be representative of metal lines that are to be formed in the metal-2 (M2) layer of an integrated circuit product. The metal lines 52, 56, 58 are arranged on various tracks (“M2 tracks”), as depicted in dashed lines in FIG. 1Q. As it relates to the SADP process, the metal lines 52, 56, 58 may be divided into mandrel-metal lines and non-mandrel-metal lines. In the depicted example, the mandrel-metal lines are arranged on the M2 tracks with the “0” designation, while the non-mandrel-metal lines are arranged on the M2 tracks with the “1” designation.
In the depicted example, the metal line 52 has a critical dimension or width 53 and they have a pitch 51. The metal line 55 has a critical dimension of 56, and the metal line 57 has a critical dimension of 58. In some applications, SADP metal design rules require that a minimum different color (DC) pitch be 48 nm. The minimum DC spacing would then be 48 nm minus 24 nm, thus 24 nm. The minimum same color (SC) pitch in this case is 96 nm, thus the same color spacing would be 72 nm (i.e., 96 nm-24 nm). In SADP applications, metal widths are generally required to be integer times the minimum width, e.g., 24 nm. In the example of FIG. 1Q, the metal line 55 may be 72 nm, and the metal line 57 may be 168 nm.
Generally, an SADP metal wire design that occupies an even number of tracks is prone for decomposition violations. As shown in FIG. 1R, the metal wires that occupy even number of tracks (2, 4, 6, . . . ) will cause violations of decomposition rules. As shown in FIG. 1R, if a default metal wire feature (minimum metal width) is used, such as a 24 nm metal feature (53A) using color 1 (NMM), with a spacing 59 of 72 nm spacing followed by a 72 nm metal feature (53B), followed by a 24 nm spacing and a subsequent 24 nm metal feature (53C) of color 1 (NMM), the problem is metal features 53A and 53B have to be of the same color, and 53B and 53C have to be different color according to SADP design rules as shown in FIG. 1M. Therefore, no matter which color is assigned to the center metal feature (53B), a decomposition violation will occur since there exists consecutive same-color metal features, which would cause color spacing violation(s). Accordingly, the design of FIG. 1R would be forbidden by the SADP decomposition rules.
To prevent the risk of SADP decomposition error in SADP design, such as SADP routing, a metal line must occupy an odd number of M2 tracks in order to comply with SADP decomposition rules which in some examples have to be 24 nm, 120 nm, 216 nm, etc. This width restriction makes circuit design very difficult at least because the flexibility of providing metal width larger than the minimum width is desirable to reduce IR drop and improve clock skew and latency.
The present disclosure is directed to various methods of generating circuit layouts that are to be formed using self-aligned double patterning (SADP) techniques which may solve or at least reduce one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds