1. Field of the Invention
The invention relates to a circuit structure and a manufacturing method thereof. More particularly, the invention relates to a circuit structure capable of preventing Galvanic effects from occurring in an etching process or in any process that can lead to electrochemical reaction and a manufacturing method of the circuit structure.
2. Description of the Related Art
Circuit boards applied in the existing semiconductor package process have advantages of closed wiring, compact assembly, and favorable performance, the circuit boards have become one of the most applicable package devices. A circuit board can be assembled to a plurality of electronic components, e.g., chips, passive components, and so forth. The electronic components can be electrically connected by the circuit board, and thereby signals can be transmitted among the electronic components.
In most cases, the circuit board is formed by alternately stacking a plurality of patterned circuit layers and a plurality of dielectric layers. The patterned circuit layers are electrically connected through conductive blind holes or conductive vias. Here, the patterned circuit layers are mostly made of copper or copper alloy. Hence, in order to slow down or even preclude oxidation, a nickel gold layer, a nickel silver layer, or a nickel palladium gold layer that can act as a surface passivation layer is often formed on the outermost patterned circuit layer. Based on actual requirements, subsequent processes on the circuit board may be required. Since the patterned circuit layers made of copper or copper alloy and the noble metal (e.g., the gold layer or the silver layer) have different redox potential, when a wet etching process or a wet micro-etching process is subsequently performed, the patterned circuit layers serve as the anode, and the noble metal (e.g., the gold layer or the silver layer) serves as the cathode. This results in the well-known Galvanic cell effect. The patterned circuit layers made of copper or copper alloy are thus etched or dissolved in an accelerated manner. Thereby, the etching rate cannot be well managed for producing favorable etching result. Moreover, due to the expedited dissolution of the copper or the copper alloy, the copper or the copper alloy may not have the required thickness, such that the electrical quality of the circuit board may be deteriorated.
USPTO Backgrounds
USPTO Backgrounds