1. Field of the Invention
The present invention relates to an input circuit which converts a signal. The invention also relates to a display device and an information display apparatus each of which uses such an input circuit. More specifically, the invention relates to an input circuit which is necessary when the output signal of a large-scale integrated circuit (LSI) of low-voltage amplitude is inputted to a thin film transistor (TFT) circuit which operates at a high voltage.
2. Description of the Related Art
As a device which displays an input video signal on a two-dimensional plane, there is a display panel, such as a liquid crystal panel or an EL panel, which needs an input circuit for converting an input signal level into a high signal level.
The input circuit used in such a display panel needs to be of the type which converts a signal level, for example, from 5 V to 10 V, in a case where the output signal of an LSI is inputted to a TFT circuit. In particular, a small-sized display panel of the type which is used in a mobile device is desired to have a power saving feature, and is required to use an input circuit of low power consumption. In addition, the input circuit used in the display panel needs to operate in response to a horizontal scanning clock for generating sampling pulses for acquiring an input video signal, and therefore, needs to perform a highest-speed operation.
FIG. 4 shows a related-art input circuit. This input circuit receives, at its input, signals which are inverted with respect to each other and outputted from an LSI circuit which operates at a source voltage VCC2 of approximately 5 V. The input circuit converts the input signals into a signal of a level operable at a source voltage VCC1 of approximately 10 V, and outputs an output signal.
A positive input signal Pi is inputted to a gate of a transistor M100 whose source is connected to ground potential GND, while a negative input signal Ni is inputted to a gate of a transistor M400 whose source is connected to ground potential GND. The drain M100/D (drain of the transistor M100) is connected to a transistor M200 which has a source connected to the source voltage VCC1 and has a gate and a drain shorted together. The gate M200/G is connected to a gate of a transistor M300 whose source is connected to the source voltage VCC1. The drain M300/D and the drain M400/D are connected to each other at an output signal terminal Po. Incidentally, for the convenience of explanation in the present specification, the gate electrode, the source electrode and the drain electrode of each transistor are respectively denoted by shortened symbols /G, /S and /D.
FIG. 5 is a time chart for explanation of the operation of the input circuit shown in FIG. 4. The input signals Pi and Ni are signals which are inverted with respect to each other and outputted from the LSI, and are like a signal (a) whose level transition time is short on a time axis to be described below.
Before time t1, since the signal Pi is at its L level (the signal Ni is at its H level), the transistor M100 is off, the transistor M300 is off, and the transistor M400 is on, so that the output signal terminal Po is at its L level.
At time t1, when the signal Pi goes to its H level (the signal Ni goes to its L level), the transistor M100 is turned on, and the transistor M400 is turned off, so that an M200/G voltage (a gate voltage of the transistor M200) decreases and the transistor M300 starts current driving. Therefore, as shown in (b), the Po voltage starts increasing and reaches the voltage VCC1 at time t2, so that the current driving capability of the transistor M300 disappears.
At time t3, when the signal Pi again goes to the L level (the signal Ni goes to the H level), the transistor M100 is turned off and the transistor M400 is turned on, so that the M200/G voltage increases by self-discharge and the transistor M300 loses its current driving capability. Therefore, as shown in (b), the Po voltage starts decreasing and reaches ground potential GND at time t4, so that the current driving capability of the transistor M400 disappears.
During the period from time t1 to time t3 during which the signal Pi is at the H level, since the transistor M100 decreases the M200/G voltage, current driving continues.
During a period following time t3 at which the signal Pi is at the L level, only the transistor M400 generates current only during the period from time t3 to time t4.
FIG. 6 shows a construction example in which a circuit for converting one input signal into signals which are inverted with respect to each other is provided in the construction shown in FIG. 4.
U.S. Pat. No. 6,373,454 discloses an EL display.
It is necessary to note that current consumption is influenced by an input level and the source voltage VCC1 pulsatively varies owing to power-source interconnection resistance.
In the above-described input circuit, if the M200/G voltage is decreased to a low voltage as rapidly as possible, the current driving capability of the transistor M300 can be increased, so that the upward transition period (from time t1 to time t2) of the Po voltage can be shortened and the input waveforms of signals which are inverted with respect to each other can be more faithfully reflected onto the output signal. However, as the amount of driving current to be generated by the transistor M100 is increased, the current consumption from time t1 to time t3 increases. Therefore, since the current driving capability of the transistor MICO cannot be increased, the upward transition period (from time t1 to time t2 ) of the Po voltage cannot be shortened, like in (b). Particularly in a TFT circuit whose transistors are poor in current driving capability, the upward transition period (from time t1 to time t2 ) of the Po voltage increases to a further extent like in (c).
In addition, it is necessary to note non-uniformity in current driving capability among individual transistors. Namely, particularly in a TFT, the non-uniformity of threshold voltages Vth of individual transistors tends to become large, so that the threshold voltages Vth of the transistors M200 and M300 may differ. In this case, during the period following time t4, the gate-to-source voltage Vgs of the transistor M300 differs from Vth, so that a leak current occurs in the transistor M300.
Therefore, the related-art input circuits shown in FIGS. 4 and 6 have the following problems.
First, the related-art input circuits are incapable of shortening the level transition time of the output signal, so that the input circuits deform the waveforms, such as the duty ratios, of the input signals which are inverted with respect to each other and cannot cope with higher-speed operations. In addition, this problem will become conspicuous as a result of variations in the current driving capabilities of the transistors used, which variations are caused by source voltage variations and temperature variations of the transistors.
In addition, the related-art input circuits in either of which current is steadily consumed by the level of an input signal cannot be easily used in a system which is required to have a power saving feature.
According to a first aspect of the invention, an input circuit which receives first and second signals at its input and outputs an output signal having a level difference different from the first and second signals, at least includes:
a first transistor whose output current is controlled by the level of the first signal;
second and third transistors whose output currents are controlled by the level of the second signal;
a first current mirror circuit which receives a current output of the first transistor at its input and includes a first switch;
a second switch which receives a current output of the second transistor at its input; and
a second current mirror circuit which receives an output of the second switch at its input.
The first current mirror circuit performs its normal operation when the first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off;
the second current mirror circuit is connected to the first current mirror circuit so that the output current of the first. current mirror circuit is decreased by an output current of the second current mirror circuit;
a current output of the third transistor and a current output of the first current mirror circuit are connected and outputted as an output signal; and
the first and second switches are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.
Preferably, the first current mirror circuit performs its normal operation when the first switch is turned on, and is constructed so that the period during which the first current mirror circuit can output a large amount of current is realized when the first switch is turned off.
According to a second aspect of the invention, the input circuit according to the first aspect of the invention further includes a conversion circuit for converting the level of the first signal and has a construction in which the output current of the first transistor is controlled by a signal obtained by converting the level of the first signal.
According to a third aspect of the invention, the input circuit according to the first or second aspect of the invention further includes a conversion circuit for converting the level of the second signal and has a construction in which the output currents of the second and third transistors are controlled by a signal obtained by converting the level of the second signal.
According to a fourth aspect of the invention, the input circuit according to any of the first to third aspects of the invention is constructed so that the second signal is connected to one of two electrodes of the first transistor except for a gate electrode thereof, the one being an electrode different from an electrode through which the current output is outputted.
According to a fifth aspect of the invention, the input circuit according to any of the first to fourth aspects of the invention is constructed so that the first signal is connected to one of two electrodes of the second transistor except for a gate electrode thereof, the one being an electrode different from an electrode through which the current output is outputted.
According to a sixth aspect of the invention, the input circuit according to any of the first to fifth aspects of the invention is constructed so that the first signal is connected to one of two electrodes of the third transistor except for a gate electrode thereof, the one being an electrode different from an electrode through which the current output is outputted.
An operation-enable level need only to be given to one of the two electrodes of each of the first, second and third transistors other than the gate electrode thereof, the one electrode being the electrode which is not the electrode through which the output current is outputted, and it is preferable to construct the input circuit in the above-described manner. The invention is particularly useful in the case where a source-follower circuit is used as the circuit for converting the level of the first or second signal.
According to a seventh aspect of the invention, in the case where the input circuit receives one signal at its input, the input circuit is preferably constructed to further include a circuit for generating the first signal and the second signal from the one signal.
According to an eighth aspect of the invention, in the input circuit according to any of the first to seventh aspects of the invention, the first signal and the second signal are signals which are inverted with respect to each other.
The invention also encompasses a display device which includes an input circuit for converting an input signal according to any of the first to eight aspects of the invention, and a display element driven by a signal supplied from the input circuit. The invention also encompasses an information display apparatus which includes an information input part to which information is to be inputted, and the display device which provides visual display according to the information inputted to the information input part.
USPTO Backgrounds
USPTO Backgrounds