It is desirable for data processing and data storage systems to be able to support scan functions that allow test data to be input to certain nodes of the system and to be scanned out of the system, thereby enabling effective testing of the system. In order to be able to support a scan function within a memory macro, all input and output latches must be able to hold the scan value during a scan sequence. A simple way of implementing this would be to convert each input or output latch into a flip-flop. However, this has the disadvantage of significantly increasing the area for the memory.
A further problem with testing memory macros, is associated with testing standard cell logic attached to the outputs of memory macros. Testing this logic efficiently is difficult as writing through the memory can take many test cycles. Test time is expensive so reducing it is important. Adding multiplexers to bypass the memory introduces at-speed test issues and also adds extra logic into potentially critical timing areas which could impact overall system performance in normal operation.
FIG. 1a shows a memory macro 5 having a storage array 10, an output latch 20 and input latch 30 according to the prior art. This memory macro 5 has a data input D for inputting data in response to a write request to input latch 30. This is then sent for storage to array logic 10 and in response to a read request is read out using sensing circuitry 40 to output latch 20. Input latch 30 is clocked by CLKB while output latch 20 is clocked by clock CLKA. These clocks are synchronised with each other. In addition to these input and output latches there are additional input latches 31 and 32 which are used to input test data which can be stored in the array during a testing sequence.
FIG. 1b shows such a memory macro according to the prior art that has been converted to support a scan function by adding an additional latch 22, a multiplexer 26 and a scan input gate 24 at the output of the memory. This additional latch is clocked by the same clock CLKA as the output latch and acts with this latch as a flip flop. There is a scan input to this additional latch 22 and when the input gate 24 is enabled using scan enable signal SE, the scan input is transmitted to latch 22 and is clocked through the two latches 20, 22 that are connected together via multiplexer 26 to form a flip flop and is output as scan data. In normal functional operation this input gate 24 is switched off and data entering the array logic is output in the conventional fashion.
As can be seen providing a scan function in this way requires an additional latch 22 as well as gating circuit 24 and multiplexer 26.
It would be desirable to produce an improved memory that was able to support an efficient scan function.
USPTO Backgrounds
USPTO Backgrounds