The present invention generally relates to the fabrication and design of devices and integrated circuits. More particularly, the present invention relates to the fabrication and design of silicon on insulator (SOI) devices.
The traditional integrated circuits fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operating integrated circuit. An integrated circuit (IC), may include superimposed layers of conducting, insulating, and transistor-forming materials, usually formed on a silicon wafer substrate. By arranging, constructing and fabricating predetermined geometric shapes in each of these superimposed layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process typically includes of the patterning of a particular sequence of successive layers using lithography to define them and etch by various chemicals to remove portions of the various layers. Many different processes exist for creating a pattern on the underlying silicon wafer with different processes being specifically adapted to produce the desired type of integrated circuit.
Processes have been developed for fabricating integrated circuit devices commonly known as silicon on insulator (SOI) devices. SOI devices are semiconductor devices fabricated within a relatively thin silicon layer that overlies an electrically insulating region formed over a substrate material. This insulating region may include, for example, a layer of SiO2 deposited or grown over a semiconductor substrate material such as silicon or gallium arsenide. The SOI fabrication process allows circuit devices to be created that are electrically isolated from the underlying substrate.
SOI devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of xe2x80x9clatchup,xe2x80x9d which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
SOI has been proposed for high performance CMOS ICs with a floating body node. Keeping the body of the SOI floating may provide a better circuit delay and since no body contact is necessary, then better front-end transistor dominated circuit density may be achieved. A floating body node causes the floating body effect (FBE), which makes circuit design challenging. One example of floating body effect is the history effect that a designer needs to margin (guard band) for when designing integrated circuits. History effect means that the circuit delay is a function of the previous status of the circuit as determined by switching of the gate and drain transistor signals. Floating body effect modulates the device threshold voltage in static CMOS circuits, for example, such that a threshold voltage change causes the device drive current to vary, which in turn causes changes in circuit delay. History effect refers to this variability in delay and is determined based on input history and conditions prior to switching activity. The history effect of the delay in SOI is a design obstacle for adopting SOI technology.
USPTO Backgrounds
USPTO Backgrounds