The present invention relates to data processing systems and, more particularly, to the transmission of data over a bit serial line or link between two subsystems of a data processing system.
Modern data processing systems are often comprised of a plurality of subsystems where each subsystem processes or generates data. For example, such systems may include one or more processing subsystems, disc subsystems, magnetic tape subsystems, and the like.
Because data processing and generating functions are spread over several subsystems, it is necessary for the subsystems to frequently communicate with each other. Since processors generally operate at high speeds, it is necessary that the transmission lines or links between the subsystems be capable of transferring data at a high speed comparable to the speed with which data is processed.
A number of approaches have been proposed in the past for providing high speed transmission lines between subsystems. One approach has been to provide a "common trunk", that is, a bus or plurality of transmission lines which carry data bits in parallel and which is connected to each subsystem. Common trunks are used in a number of current commercially available data processing systems, including, for example, the 8400 and 8500 series of data processing systems sold by NCR Corporation, Dayton, Ohio. The drawback to the use of the common trunk is, of course, that a large number of electrical conductors are required to provide the common trunk and, accordingly, it is expensive to manufacture. While the concept of transmitting data serially over a single transmission line or link has been known in the past, this approach has not been widely used for connecting subsystems within a single data processing system because of the high cost of the circuitry needed to serially receive and serially transmit the data at sufficiently high speeds to match the speed of the processors within the system.
Recently, there have been improvements in the cost and operating capability of integrated circuitry. For example, integrated circuits implemented in emitter coupled logic (ECL) can operate on data at much faster speeds than integrated circuits implemented in earlier logic families, and have a cost which is now comparable to the integrated circuits in earlier logic families. As a result, it is now feasible to use logic circuitry in conjunction with a bit serial link that can transmit data at speeds sufficiently high for use within data processing systems. Since these bit serial links use only one conductor line to transmit data and are, as a consequence, less expensive than common trunks, there has arisen the need for circuitry to transmit and receive the serial data at high speeds.
To transmit serial binary data over a transmission line normally requires that the data be somehow encoded. While encoding the binary data into analog signals is desirable for data transmission over long distances, because of the inherent greater immunity of analog signals to noise and interference, digital pulse encoding techniques are sufficient between data processing subsystems located within close proximity to each other.
A number of digital or binary encoding techniques have been employed in the past. These techniques include non-return to zero (NRZ) encoding, return to zero (RZ) encoding, phase encoding, and multilevel binary encoding, NRZ encoding is not suitable in many applications because it is not self-clocking, and accordingly, a separate clocking signal must be generated with the encoded data. RZ encoding likewise has disadvantages. While RZ does include some self-clocking features, the clock is sometimes very difficult to recover and accordingly, it is subject to some failure.
Multilevel binary encoding, on the other hand, is very reliable. However, it uses three or more voltage levels to transmit binary data and, as a consequence, requires extensive circuitry for converting between the binary data levels and the three voltage levels.
For the above reasons, phase encoding is perhaps the most ideally suited means of serially encoding binary or digital data in a data processing system. Phase encoded pulse signals use signal level transitions to carry both binary data and synchronization (clocking) information, and at least one signal level transition occurs during each bit period or interval. The various types of phase encoded pulse signals include the biphase-level code (also known as the Manchester code), the biphase-mark code (also known as the diphase code), and the biphase-space code. For a more detailed description of each of these binary pulse codes, reference can be had to a number of United States patents and printed publications including, for example, Fairchild Camera and Instrument Corporation, The Interface Handbook--Line Drivers and Receivers, Chapter 4 (1975).
A number of techniques have been used in the past for recovering data that has been encoded in phase encoded pulse codes. The recovering of the clocking or synchronization signal in the encoded data is one of the most vexing problems in the use of these codes, and phase locked oscillators are normally employed to aid in the recovery of the clocking signal. The disadvantage of phase locked oscillators is that they generally include extensive circuitry and are relatively expensive in cost. Furthermore, commercially available phase locked oscillators frequently have to be tuned so that they can operate with the specific frequency used in the code.
Techniques that have been used in recovering data are disclosed in U.S. Pat. No. 3,603,945, issued to Friedrich R. Hertrich, and U.S. Pat. No. 3,597,751, issued to Robert F. Neidecker and Friedrich R. Hertrich. The data recovery circuitry shown in each of these patents uses a delay circuit for delaying the read back signal from a magnetic recording apparatus, and combining the delayed read back signal with an undelayed read back signal. By detecting the amplitude of the combined signals, data can be recovered from the read back signal. The circuitry in both patents, however, is concerned with recovering data from a read back signal generated by magnetic fluxes on a magnetic medium that has the nature of an analog signal, rather than recovering the data from a signal that has the nature of binary pulses and that is transmitted over a bit serial link between two data processing subsystems.
USPTO Backgrounds
USPTO Backgrounds