1. Field of the Invention
The present invention relates to a scanning circuit. More specifically, the invention relates to a scanning circuit to be employed for a peripheral driver circuit such as for a liquid crystal display, a plasma display and so forth.
2. Description of the Related Art
For the purpose of down-sizing and reduction of cost of a liquid crystal display device, development of technology for integrating a peripheral driver circuit on a liquid crystal display substrate in common has been progressed. The peripheral driver circuit can be divided into a vertical driver circuit for scanning gates of thin film transistors (hereinafter referred to as TFT) forming an active matrix array and a horizontal driver circuit supplying a video signal to a data bus line. These peripheral driver circuits are typically formed by integrating polycrystalline silicon thin film transistor (hereinafter referred to as p-SiTFT). Among various circuit forming the peripheral driver circuit, a scanning circuit generating a gate scanning pulse signal or sampling pulse signal is one of important circuit components.
A task for the scanning circuit is, at first, speeding up for adapting for increasing of resolution of the liquid crystal display abruptly evolving. On the other hand, in order to adapt for higher function, such as display inverting function and so forth, a capability of bidirectional scanning is required.
Particularly, in case of a three panel type liquid crystal display employing three liquid crystal displays, it becomes necessary to provide a display inverting function of the liquid crystal display due to difference of number of times of mirror reflection. Therefore, a bidirectional scanning circuit is an essential circuit. As a construction of the bidirectional scanning circuit, a construction as disclosed in Japanese Unexamined Patent Publication No. Heisei 7-146462 has been employed.
However, such bidirectional circuit requires an additional circuit for switching a shifting direction, and thus, a circuit speed becomes lower than that of a unidirectional scanning circuit. On the other hand, in Japanese Unexamined Patent Publication No. Heisei 7-134277, a construction of a bidirectional scanning circuit operating at high speed has been disclosed. FIG. 15 discloses a circuit construction. In the shown circuit construction, number of outputs of the scanning circuit is assumed to be 120. As shown in FIG. 15, the shown circuit is constructed with transfer gates 109-1 to 109-121 mutually connected in series for transferring a signal from a former stage to a later stage with a delay by clock signals A and B, and feedback circuits 110-1 to 110-119 for preventing attenuation of an amplitude of a pulse signal transferred with a delay, and an output buffer circuits 113-1 to 113-119.
As shown in FIG. 15, the feedback circuit is constructed with an inverter and a clocked inverter. The clocked inverter is controlled activation by clock signals C and D. The detailed construction of the clocked inverter is as shown in FIGS. 14A and 14B.
Namely, in FIG. 14A, there is shown symbols of clocked inverter circuits (transistors T3 and T4) supplying the clock signals C and D to gates of respective of an n-channel transistor T2 and a p-channel transistor T1, and a circuit construction. On the other hand, in FIG. 14B, there is shown symbols of clocked inverter circuits (transistors T3 and T4) supplying the clock signals D and C to respective of an n-channel transistor T2 and a p-channel transistor T1.
The operation of this circuit will be discussed with reference to FIGS. 16 and 17. FIG. 16 is a timing chart of the case of rightward shifting. In case of rightward shifting, a start pulse STR is input to an input/output terminal 101 at a shown timing and a second input/output terminal 102 is held open. On the other hand, the clock signals A and D are taken as a common clock signal .phi., and the clock signals B and C are taken as a common clock signal for . Namely, the clocks A and B are complementary two phase signals, and also the C and D are complementary two phase signals. By setting as set forth above, a scanning pulse signal shifting from a scanning outputs OUT1 to OUT120 in sequential order can be output.
On the other hand, FIG. 17 shows a timing chart in the case of leftward shifting, the start pulse is input to the second input/output terminal 102 at a shown timing, and the first input/output terminal 101 is held open. On the other hand, the clock signals B and D are input as the common clock signal and the clock signals A and C are input as the common clock signal for . By thus setting, the scanning pulse signal shifting from OUT120 to OUT1 in sequential order can be output, as shown in FIG. 17.
As set forth above, by employing the circuit shown in FIG. 15, shifting direction can be switched without providing an additional circuit for switching the shifting direction.
It should be appreciated that in the example of FIG. 15, as shown in timing charts of FIGS. 16 and 17, shifting outputs respectively shifted in phase for half period of clocks A to D are lead out to the scanning outputs POUT1 to POUT120 in sequential order. However, in order to obtain shifting outputs having phase shift for one period of the clock, the shifting output may be lead out from respective scanning outputs in odd number.
While the bidirectional scanning circuit to be employed in a driver circuit integrated type liquid crystal display is described above, it has been considered, in the recent years, to apply the p-SiTFT driver circuit to a driver IC chip of the liquid crystal display or the plasma display. For example, Japanese Unexamined Patent Publication No. Heisei 6-88971 discloses an example where a driver IC chip fabricated by integrating the p-SiTFT driver circuit on a glass substrate, is directly mounted on a liquid crystal display. Even when the p-SiTFT driver circuit is applied for the driver IC chip, it is naturally required a bidirectional scanning circuit which can operate at high speed.
However, when J (J is a natural number) in number of the bidirectional scanning circuits are connected as the driver IC chip and a signal is transferred from the first chip to the chip in (J)th order, it can be caused a problem that an output at the final bit does not operate normally for the fact that the input/output terminal of the (J)th chip becomes a floating condition. Such malfunction is caused in the case where floating capacitors 114 of the input/output terminals 101 and 102 are greater in the order of one to two digits in comparison with a gate capacitance (10 to several hundreds fF) of the transistors forming the scanning circuit.
Therefore, when the bidirectional scanning circuit of FIG. 15 is employed alone, it becomes possible to prevent appearance of malfunction signal of the final bit on the input/output 102 by providing a dummy bit DB1 at the final bit as shown in FIG. 18. However, if such scanning circuit is applied as the driver IC chip, the following problems should be encountered.
FIG. 19 is an illustration showing a circuit construction in the vicinity of connecting portion 1901 of the chips 1101 and 1102 when a plurality of driver IC chips formed with the bidirectional scanning circuits. By adding the dummy bit DB1, the output timing of the output signal OUT121 is delayed for one clock period from the normal timing.
On the other hand, since no feedback circuit 110 is provided at the connecting portion 1901, attenuation of the signal is caused to make it impossible to transfer the normal scanning pulse signal subsequent to the OUT 121 (the first output OUT1 of the second chip 1102).
For the reason discussed above, the bidirectional scanning circuit shown in FIGS. 15 to 18 cannot be applied to the driver IC chip.
USPTO Backgrounds
USPTO Backgrounds