Field of Invention
The present invention relates to controlling the amount of flux emitted by a semiconductor light emitting device by treating a surface of the device.
Description of Related Art
Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes such as surface-emitting lasers (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. Typically, III-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, III-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p-type regions.
FIG. 1 illustrates a light emitting device described in more detail in U.S. Pat. No. 7,256,483. To form the device of FIG. 1, a conventional LED is formed on a growth substrate. Each LED die includes n-type layers 16, an active layer 18, and p-type layers 20. A metal (metallization layer plus bonding metal) 24 contacts the p-layer. Portions of the p-layer 20, active layer 18, and possibly metal 24 are etched away during the LED forming process, and metal 50 contacts the p-layer 16 on the same side as the p-contact metal 24. An underfill material 52 may be deposited in the voids beneath the LED to reduce thermal gradients across the LED, add mechanical strength to the attachment, and prevent contaminants from contacting the LED material. The metallization layers 50 and 24 are bonded to metal contact pads 22A and 22B, respectively, on a package substrate 12. The package substrate 12 may be formed of the electrically insulating material AN, with metal contact pads 22A and 22B connected to solderable electrodes 26A and 26B using vias 28A and 28B and/or metal traces. The growth substrate is removed, then the light-emitting top surface of the LED (n-layer 16) is roughened for increased light extraction. For example, layer 16 may be photo-electrochemically etched using a KOH solution 46.
USPTO Backgrounds
USPTO Backgrounds