1. Field of the Invention
The present invention relates to a dynamic RAM (Random Access Memory) or similar semiconductor memory which is implemented by complementary MOS (CMOS) transistors. More particularly, the present invention is concerned with the sense circuit configuration of a sense amplifier which is built in such a semiconductor memory.
2. Description of the Prior Art
In the semiconductor memories art, various achievements have been reported including "FAM 17.2: A 90 ns 1 Mb DRAM with Multi-Bit Test Mode" by Kumanoya et al, Digest of Technical Papers (1985-2-15), IEEE International Solid State Circuit Conference (U.S.A), pp. 240-241. As shown in FIG. 2, a semiconductor memory disclosed in this paper has a dynamic RAM configuration adopting a shared sense amplifier system.
As shown in a left part of FIG. 2, the dynamic RAM includes a plurality of bit line pairs 10 for sending data and each having two complementary bit lines 10a and 10b, and a plurality of word lines 11. Memory cells 12 are individually connected to the bit line pairs 10 and word lines 11 so as to store data therein. The word lines 11 are adapted to select any of the memory cells 12. Likewise, as shown in a right part of the figure, a plurality of bit line pairs 20 each having two complementary bit lines 20a and 20b and a plurality of word lines 21 are provided, while memory cells 22 are individually connected to the intersecting points of the bit line pairs 20 and word lines 21. The right and left bit line pairs 10 and 20 are interconnected via field effect transistors (FETs) 13a, 13b, 23a and 23b. A sense amplifier 30 is made up of two n-channel FETs and connected between a node Na which extends between the FETs 13a and 23a and a node Nb which extends between the FETs 13b and 23b. The FETs 13a and 13b constitute switches each being turned on and off by a gate signal SL which is determined by an address signal. Likewise, the FETs 23a and 23b serve as switches each being turned on and off by a gate signal SR which is determined by an address signal. A sense amplifier enable signal S is applied to the sense amplifier 30 for causing it to sense and amplify potentials appearing on the complementary nodes Na and Nb.
The bit line pair 10 on the left-hand side of the figure are connected to a complementary data bus 32 via a pair of transfer gates 31a and 31b. The transfer gates 31a and 31b are each implemented by an n-channel FET which is turned on and off by a column select signal Yi.
The operation of the prior art semiconductor memory shown in FIG. 2 will be described with reference to FIG. 3. The semiconductor memory, or dynamic RAM, of FIG. 2 adopts a shared sense amplifier principle, as stated earlier. To read or write data in the array of memory cells 12 on the left-hand side, the FETs 23a and 23b are disabled by the gate signal SR so as to disconnect the bit line pair 20 on the right-hand side from the sense amplifier 30. Simultaneously, the FETs 13a and 13b are enabled by the gate signal SL to connect the bit line pair 10 on the left-hand side to the sense amplifier 30. Conversely, to read or write data in the array of memory cells 22 on the right-hand side, the FETs 23a and 23b are enabled to cause the bit line pair 20 on the left-hand side into connection with the sense amplifier 30.
How data is read out will be described specifically by taking the case of one of the memory cell 12 of the array located on the left-hand side, with reference to the timing chart of FIG. 3. It is to be noted that all the bit line pairs 10 are precharged to a source voltage Vcc before the start-up.
At a time t1 shown in FIG. 3, the gate signal SR associated with the right memory cell array which is not selected is controlled to reach the bit line potential or source potential Vcc prior to the build-up of a left word line 11. Since the bit line pair 10 has the source level Vcc, the FETs 23a and 23b are turned off so that the left bit line pair 20 is isolated from the sense amplifier 30. The left word line 11 builds up at a time t2 with the result that a signal representative of data is read on the bit line pair 10 out of a memory cell 12 which is associated with the bit line pair 10.
At a time t3, the gate signal SL associated with the memory cell array which is selected is lowered to the source level Vcc. This turns off the FETs 13a and 13b and thereby disconnects the bit line pair 10 from the sense amplifier 30. Consequently, a potential representative of the data stored in the associated memory cell 12 is confined in the node Na or Nb which is associated with the sense amplifier 30. Subsequently, at a time t4, the sense amplifier enable signal S is lowered to a low level "L" for thereby causing the sense amplifier 30 to perform a sensing operation. Hence, one node Na, for example, is turned to "L" and the other node Nb is maintained at a high level "H". In this example, therefore, the FETs 13a and 23a are enabled again as soon as the node Na becomes "L", causing a transition of the bit lines 10a and 20a to "L".
At a time t5, the gate signals SL and SR are raised to a predetermined level higher than the source level Vcc. Then, the FETs 13b and 23b are also enabled so that the bit lines 10a and 10b are settled respectively at, in this particular example, "L" and "H". Further, at a time t6, the column select signal Yi is enabled to "H" to in turn enable the transfer gates 31a and 31b. As a result, a signal representative of data on the bit line pair 10 is transferred to the complementary data bus 32 via the transfer gates 31a and 31b, i.e., the data stored in the memory cell 12 is fed out to the outside.
The prior art semiconductor memory constructed as shown and described has various problems left unsolved. Specifically, a VLSI (Very Large Scale Integration) memory or similar memory having a large storage capacity has a great number of bits, resulting in the bit line pairs 10 and 20 which are extremely great in total number. The above-described memory implements the sensing operation by disabling the FETs 13a, 13b, 23a and 23b to isolate the sense amplifier 30 from the bit line pairs 10 and 20 and thereby confining potentials on the nodes Na and Nb, as stated earlier. This kind of scheme is successful in enhancing rapid sensing operations. However, when it comes to a memory having a large capacity and therefore a large bit line capacitance, the prior art memory is apt to fail to transfer data at a high speed within a given memory cell time because it is so constructed as to transfer data read out by the sense amplifier 30 to the complementary bus 32 by way of the bit line pair 10.
Another problem with the prior art semiconductor memory is ascribable to the confinement type sense amplifier 30 which is constituted by n-channel FETs only. Specifically, dropped voltages (Vcc-.alpha.) on, among the bit line pairs 10 and 20, the bit lines 10a and 20a or the bit lines 10b and 20b which have the "H" level at the time of sensing remain as they are, obstructing rapid sensing operations.
USPTO Backgrounds
USPTO Backgrounds