1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit design and devices, and more specifically to pre-designed system-on-chip architectures with HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suite, and makefiles.
2. Description of the Prior Art
As systems-on-chip (SoC) become more complex, it will be increasingly difficult for a single company to provide its customers with all of the semiconductor intellectual property (SIP) cores and library macrocells they require. Companies have to evaluate whether human resources, capital and time are expendable on extraneous developments. A growing trend is to outsource the areas that fall outside of their core competencies.
Time-to-market is the dominant factor directing this make vs. buy decision. SoC's are reaching higher levels of integration, but their complexity is inversely proportional to the allowable time-to-market. “Buying” semiconductor intellectual property will become essential for surviving in an environment that demands increased profits and decreased time-to-market. For companies to meet the technology challenges of integrating externally developed semiconductor intellectual property into a single chip, within the given time window, they may decide to partner with others, including, in some cases, their competitors.
Outsourcing and partnership will be the essential elements of a successful semiconductor business in the next century because those capabilities will help companies deliver what customers want. Companies using SoC technologies have recognized the need to license or buy semiconductor intellectual property from other companies. But just purchasing the semiconductor intellectual property is not enough. Integrating semiconductor intellectual property in a system-on-chip is complicated, especially when components from multiple sources are involved. Semiconductor intellectual property integrators and providers need to actively work together to make sure that all of the pieces of the SoC fit seamlessly. One way to leverage the strength of a partnership is by offering an open on-chip architecture.
Successful semiconductor companies must be able to deliver to the customer an on-chip architecture, in which components can be dropped in and interconnected with little difficulty. Open means that it is supported by third-party companies, thereby producing a collaborative effort to reduce the design-integration struggles found in SoC development, including hardware and software co-design and co-verification. That also results in reducing time-to-market. Customers may include choices in how they build their SoC devices, which semiconductor intellectual property components to integrate, and what software and operating system to implement. Outsourcing and partnership are keys to successfully offering customers what they want. Taking this a step further, providing and/or supporting an open architecture gives customers the flexibility they need.
The electronics industry has been driven by the need to increase performance, reduce costs and enhance features. Many of these needs have been met through the use of newer, faster and cheaper technologies. Newer technologies continue to allow for more functions and features to be placed on a single piece of silicon. Functions that previously were placed on separate chips can now be integrated in a system-on-chip with new functions added.
In any processor-driven embodiment, a number of peripheral devices are needed. These include timers, DMA engines, interrupt controllers and memory controllers. In many cost-sensitive applications, a shared memory structure is preferably used to reduce memory component costs. An architecture is needed which addresses the memory needs of all devices without severely degrading the performance of any single device.
The PCIbus, ISA, VMEbus, and most other buses were designed as system level buses to connect discrete devices on a printed circuit board (PCB) substrate. At the board level, a key issue is minimizing the number of bus signals because pin and signal count translate directly into package and PCB costs. A large number of device pins increases the package footprint and reduces component density on the board. System level buses must support add-in cards and PCB backplanes where connector size and cost are also directly related to signal count. This is why traditional system level buses use shared tri-state signaling and, in the case of PCIbus, multiplexed address and data on the same signals. Timing problems can be investigated in the laboratory using prototype PCBs that can then be modified and re-spun in a few days.
In the on-chip world, signal routing consumes silicon area but does not greatly affect the size or cost of packages, PCBs and connectors. The limited capabilities of today's logic synthesis tools directly impact embodiment time and performance and must be taken into account. Getting the lowest possible routing overhead is of little value if the system design time balloons way out of proportion and the market window is missed. Synthesis tools find it difficult to deal with shared tri-state signals with several drivers and receivers connected to the same trace. Static timing analysis is preferably awkward, and often the only way to verify timing is to use a circuit level simulator, e.g., SPICE. All of this takes time and effort without adding real value in terms of device functionality or features. Bus loading also limits theoretical performance and the verification problems associated with bus loading can lead to a conservative embodiment whose performance falls short of the inherent technology capabilities.
USPTO Backgrounds
USPTO Backgrounds