The present invention relates to storage of data in nonvolatile memories such as flash memories and, more particularly, to a memory and methods of reading using optimized placement of threshold levels for reading hard and soft bits.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile and retains its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory, both embedded and in the form of a removable card are ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
Flash memory typically comprises of EEPROM (Electrically Erasable and Programmable Read-Only Memory). It is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Each memory cell is formed by a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range or voltage bands within the threshold window may, in principle, be used to designate a definite memory state of the cell. In general, when the threshold window is partitioned into 2m voltage bands by 2m−1 demarcation reference threshold voltages, the cell can store up to m bits of data. For example, when the threshold voltage is partitioned into two distinct voltage bands, each memory cell will be able to store one bit of data. Similarly, when the threshold voltage window is partitioned into more than two distinct voltage bands, each memory cell will be able to store more than one bit of data.
The memory device may be erased by a number of mechanisms. For EEPROM, a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling.) Typically, the EEPROM is erasable byte by byte. For flash EEPROM, the memory is electrically erasable either all at once or one or more blocks at a time, where a block may consist of 512 bytes or more of memory.
In order to increase memory capacity, flash memory devices are being fabricated with higher and higher density as the state of the semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.
Originally, flash memories stored only one bit per cell. Flash memories that store two bits per cell now are available commercially, and flash memories that store more than two bits per cell are being developed. Flash memories that store one bit per cell are called “Single Level Cell” (SLC) memories. Flash memories that store more than one bit per cell are called “multi-state” or “Multi Level Cell” (MLC) memories.
The transistor serving as a memory cell is typically programmed to a “programmed” state by one of two mechanisms. In “hot electron injection,” a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric onto the floating gate. In “tunneling injection,” a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.
The memory devices typically comprise one or more memory chips that may be mounted on a card. Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. The more sophisticated memory devices operate with an external memory controller that performs intelligent and higher level memory operations and interfacing.
There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may be flash EEPROM or may employ other types of nonvolatile memory cells. Examples of flash memory and systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, 5,313,421 and 6,222,762. In particular, flash memory devices with NAND string structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935. Also flash memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. Such memory devices utilizing dielectric storage element have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
The reference voltages demarcating the voltage bands of the threshold window for programming references can be considered as “hard” reference voltages (also equivalently referred to as “integral reference voltages” or “integral reference thresholds”). Programming a memory cell aims to place its threshold in the middle of one of the voltage bands or at least within the boundaries of the voltage band. Reading with respect to these hard reference thresholds will yield corresponding hard bits (HB). When the memory is programmed with sufficient margin between the various voltage bands, the distribution of programmed threshold levels in each voltage band is well defined. Thus, reading with respect to the hard reference thresholds are adequate in locating each programmed threshold of the cells accurately.
In practice, the distribution about each voltage band has a spread and there is a finite probability that some member of a distribution strayed over to a neighboring voltage band. In that case, the hard read levels will yield erroneous read results. A common practice is to incorporate an error correction code (“ECC”) computed on the hard bits to correct errors that may crop up.
With the desire to produce memory with higher density, each generation of memory device is fabricated with more integration, resulting in the memory cells being closer to each other. This has created issues with increased interactions and perturbations between cells, resulting in the further spreading of the distribution of programmed threshold levels in each voltage band. Furthermore, the problem is exacerbated by the implementation of MLC storage, in which more and more bits are crammed into each cell. This results in having to partition the fixed threshold windows into more and more voltage bands, thereby requiring the distribution of programmed threshold levels in each band and the margins between bands to be narrower.
The threshold voltages of the cells are distributed statistically around the centers of their respective voltage bands. There are several reasons for the finite widths of these distributions. The programming process is a stochastic one that relies on inherently stochastic processes such as quantum mechanical tunneling and hot injection. The precision of the read/program circuitry is finite and is also limited by random noise. In some flash technologies, the threshold voltage of a cell being read is affected by the threshold voltages of neighboring cells. Chip-to-chip variations and variations in the manufacturing process cause some cells to behave differently than other cells when read/programmed. Furthermore, the cell threshold voltage distributions tend to change over time. As a flash memory is programmed and erased, the sizes of the voltage window and the voltage bands tend to change. These phenomena limit the number of times a MLC flash memory can be erased and re-programmed. Also, the threshold voltage of a flash cell that is not programmed for a long time tends to drift to a lower threshold voltage. This phenomenon limits the time that data can be reliably retained in a flash memory.
The voltage bands of a flash cell should be designed to be wide enough to accommodate all these phenomena, but not too wide. A voltage band that is too narrow, relative to the associated threshold voltage distribution curve and relative to the drift of that curve over time, leads to an unacceptably high bit error rate. Making the voltage bands very wide relative to the associated threshold voltage distributions limits the number of bits in the bit patterns that can be stored reliably in the flash cell. In practice, flash memories are designed to have one error per 1014-1016 bits read. Some flash technologies are unable to achieve this error rate while storing the desired number of bits per cell. Some flash memories based on such technology use error correction circuits to compensate for their high intrinsic error rates.
The use, in addition to integral reference thresholds, of other reference thresholds that lie within voltage bands, allows the programmed threshold of a cell to be located at a higher resolution within the threshold window. Such reference thresholds are termed “fractional reference thresholds” or “fractional reference voltages” herein. With the additional fractional reference thresholds, the threshold window is resolvable into more voltage bands, which are codable by additional bits, known as “soft bits”. These soft bits will help to improve the performance of the ECC operation.
Soft bit (SB) readings (also known as ‘resolution bits’) in flash memory devices have already been introduced in the past in connection with improving the reliability and operation of an algebraic ECC decoder by allowing it to perform bit flips on less reliable bits. For example, U.S. Pat. No. 6,751,766 and U.S. Pat. No. 7,023,735 disclose using soft bits to improve the correction capability of an ECC decoder. Another example in which resolution bits are employed to improve upon the operation of a soft input decoder is detailed in WO 2008/042593 A1.
It is therefore desirable to partition the threshold window of a memory cell in an optimal manner to yield additional soft bits that are efficient in correcting errors and efficient to handle.
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