Semiconductor memory integrated circuits are in high demand, and the industry is always striving to improve the density of such devices. Currently, the Dynamic Random Access Memory (DRAM) is in widespread use. However, DRAM cells require a capacitor, which requires refreshing to preserve the stored data.
Accordingly, newer memory cell technologies are under consideration for the mass market. One such new memory technology is the Phase Change Random Access Memory (PCRAM). In a PCRAM, the capacitor of the DRAM cell is replaced with a phase change material, such as Germanium-Antimony-Telluride (GST) or other chalcogenide materials. An example of such a cell 30 as fabricated is shown in cross section in FIG. 1B, and is shown in schematic form in FIG. 1A. Because the structure and operation of PCRAMs are well known to those skilled in the art, they are only briefly described. The PCRAM cell is an exciting alternative to traditional capacitor-based DRAM cells because they do not require refresh and are easily scalable. (Capacitors require a given surface area to store the requisite number of charges, and hence are not easily scaled).
As shown, each PCRAM cell 30 comprises an access transistor 32 and a phase change material 34. Each access transistor 32 is selectable via a word line (row) 20, which when accessed opens a transistor channel between a bit line (column) 24 and a reference line 22. The phase change material 34 is in series between the transistor channel and the cell selection line 24, and so can be set (i.e., programmed to a logic ‘1’ state), reset (i.e., erased to a logic ‘0’ state), or read via the passage of current through the material. As is well known, phase change material 34 can be set by passing a current therethrough, which modifies the material into a more conductive crystalline state (e.g., less than 10K ohms). This phase change of the material 34 is reversible, and so the material 34 may be reset back to an amorphous resistive state (e.g., more than 500K ohms) by the passage of even a larger amount of current through the material. Such phase changing occurs in the region 34a adjacent to the bottom electrode 42b as shown in FIG. 1B. Once set or reset to make the material 34 relatively conductive (denoting storage of a logic ‘1’) or resistive (denoting storage of a logic ‘0’), the cell may be read by passing a relatively small current through the phase change material 34 and sensing the resulting voltage on the bit lines 24.
Processing of the PCRAM cell 30 uses standard semiconductor CMOS processing techniques, and does not require significant explanation to those of skill in the art. As shown in FIGS. 1B and 1C, the cell 30 uses polysilicon gate for the word lines 20 as is common, and uses conductive plugs to contact the diffusion regions 44 in active portions of the silicon substrate. The phase change material 34 is sandwiched between top and bottom electrodes 42a and 42b. Contact from the bit line 24 to top electrodes 42a is established by plugs 40. Of course, conductive structures are surrounded by at least one dielectric material 35, such as silicon dioxide or silicon nitride as is well known. Pairs of adjacent cells 30 are isolated from one another using trench isolation 46, again a standard technique for isolating active structure in a silicon substrate.
Other details concerning PCRAM memory composition, operation, and fabrication can be found in the following references, all of which are incorporated by reference herein in their entireties: S. H. Lee et al., “Full Integration and Cell Characteristics for 64 Mb Nonvolatile PRAM,” 2004 Symp. on VLSI Technology Digest of Technical Papers, pps. 20-21 (2004); S. Hudgens and B. Johnson, “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology,” MRS Bulletin, pps. 829-832 (November 2004); F. Yeung et al., “Ge2Sb2Te5 Confined Structures and Integration of 64 Mb Phase-Change Random Access Memory,” Japanese Journal of Applied Physics, Vol. 44, No. 4B, pps. 2691-2695 (2005); Y. N. Hwang et al., “Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24 um-CMOS Technologies,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pps. 173-147 (2003); W. Y. Cho, et al., “A 0.18-um 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (PRAM),” IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, pps. 293-300 (January 2005); and F. Bedeschi, et al., “An 8 Mb Demonstrator for High-Density 1.8V Phase-Change Memories,” 2004 Symposium on VLSI Circuits Digest of Technical Papers, pps. 442-445 (2004).
The array 10 of PCRAM cells 30 can be operated as follows. First, a cell 30 to be accessed is determined by the logic of the integrated circuitry in which the array is formed (not shown), and an appropriate word line 20 and bit line 24 are respectively activated via row decoder/driver circuitry 12 and column decoder/driver circuitry 14. The reference drivers 16 send a reference potential to each of the cells 30 in the array 10 at all times, which can be ground for example. An activated word line 20 can comprise a voltage sufficient to form a channel under the access transistors, e.g., 1.5V. The voltage to be placed on the selected bit line 24 depends on whether the accessed cell is being set, reset, or read. When the cell is being set, the voltage on the bit line might be approximately 2.0V, and when reset a higher voltage of perhaps 3.0V can be used. When the cell is being read, a smaller bit line 24 voltage is used (e.g., 0.5V), and the current draw through the bit line is assessed via sense amplifiers (not shown) in the column decoder/driver circuitry 14. Because such decoder/driver circuitry 12, 14, 16 is well known, it is not further discussed.
It has been discovered that PCRAM cells can suffer from reliability problems. For example, the performance of a cell can eventually degrade as the cell is continually set or reset. For example, FIG. 2 shows exemplary performance of a cell which is continually erased to a logic ‘0’ reset condition through the application of high current. As can be seen from the graph, initially, the resistivity of the cell behaves well, and the phase change material 34 exhibits a high resistance of about 500K ohms. However, as the cell is continually erased (without any intervening programming to a logic ‘1’ set condition), eventually the resistance of the cell starts to degrade, perhaps to 200K ohms after 1000 erase cycles. Of course, this is not optimum, because as the resistivity of the logic ‘0’ erased bits starts to fall, the sensing margin between the logic ‘0’ erased bits and the logic ‘1’ programmed bits begins to degrade, with the result that sensing of the logic state of the bit becomes more uncertain, or slower, or generally becomes more unreliable.
This problem is not merely academic, but can have a real impact in a commercially-marketable PCRAM integrated circuit. While cells in a PCRAM integrated circuit can be freely set (logic ‘1’) or reset (logic ‘0’), they typically are done so on a byte or word basis. Take for example a PCRAM integrated circuit which is byte (8-bit) programmable. A given address in the PCRAM might currently be programmed with a given byte, say ‘01111111’ for example. It might be desired to change the data stored at this address to make the least-significant bit a logic ‘0’; in other words, it might be desired that the byte at the address be updated to ‘01111110’. To effectuate such a change to the data at this address, it is generally not efficient to design the circuitry so as to only reset the least-significant bit to a logical ‘0’. Instead, preferably, the entire byte of data is reprogrammed at the address, i.e., ‘01111110’ is programmed at the address location. Of course, this means that the data state of some of the cells in the byte may not actually be changed. For example, the most-significant bit ‘0’ remains unchanged in this example, and so is redundantly reset with a high current.
But as just noted, such continual resetting of this most-significant bit will eventually degrade the resistivity of the phase change material in that bit. To continue the example above, supposed that the address is continually programmed back and forth with the logic states ‘01111111’ and ‘01111110’. The effect of this hypothetical is that the most-significant bit will be continually reset with a high current to the logic ‘0’ state, which as FIG. 2 notes, will eventually degrade its performance. As the resistivity of the various logic ‘0’ states across an array of PCRAM bits eventually becomes more dispersive as bits are more or less affected by this phenomenon, eventually overall reliability of the PCRAM integrated circuit will suffer.
Although not illustrated in FIG. 2, it has been noted that a similar degradation exists in continually setting a logic ‘1’ to the same bit (without any intervening reset to a logic ‘0’ state). Thus, if a bit is continually set to a logic ‘1’ state, its resistively, normally about 10K ohms, will eventually start to increase as a function of the number of cycles. Although such degradation has not been noticed to be as stark for the logic ‘1’ case versus the logic ‘0’ case, the inadvertent increase of the resistivity of the logic ‘1’ bits also degrades the sensing margin between a logic ‘0’ and a logic ‘1,’ and similarly tends to decrease the reliability of the PCRAM integrated circuit.
A solution to this problem is therefore desirable, and is provided in this disclosure.
USPTO Backgrounds
USPTO Backgrounds