1. Field of the Invention
The present invention relates to a semiconductor device for use in an electronic circuit for a variety of technical fields such as an automobile, an electric power generating plant, an artificial satellite as well as an OA machine and an electronic product for a private use such as a copying machine, a facsimile machine, a printer and a video camera, and a method of manufacturing the semiconductor device.
In particular, the present invention relates to a semiconductor memory device for storing a required information signal.
2. Related Background Art
FIG. 45 illustrates the structure of a semiconductor memory capable of storing and programming data only one time, the semiconductor memory being constituted by an MOS type field effect transistor (hereinafter called an "MOSFET") serving as an insulated gate type field effect transistor and a memory cell having an insulating film.
A memory of the aforesaid type has been disclosed in, for example, "A New Programmable Cell Utilizing Insulator Breakdown", IDEM' 85, pp 639 to 642.
Another type semiconductor arranged as shown in FIG. 46 has been known.
FIG. 46 is a cross-sectional view which illustrates the semiconductor memory of the aforesaid type. Referring to FIG. 46, reference numeral 120 represents an n-type substrate, 121 represents a p.sup.+ drain, 122 represents a P.sup.+ source, 123 represents a floating gate, 124 represents an insulating layer, 125 represents a drain wiring and 126 represents a source wiring. The floating gate 123 is manufactured by, for example, embedding a polycrystalline silicone in a silicone oxide film.
A transistor for use in ULSIs and having a gate length of sub-micron order has been developed thanks to progress of the fine processing technology.
FIG. 101 is a schematic cross sectional view which illustrates an LDD (Lightly Doped Drain) structure as a typical MOS type field effect transistor (hereinafter called a "MOSFET").
Referring to FIG. 101, reference numeral 201 represents a P type semiconductor substrate, 202 represents a field oxide film, 203 and 204 respectively represent n.sup.+ layer of the source region and that of the drain region and 205 represents a gate insulating film, 206 represents a gate electrode. Reference numerals 207 and 208 respectively represent n.sup.- layer provided for the purpose of relieving the field concentration taken place adjacent to the gate of the source region and that of the drain region, 290 represent a channel dope layer formed by an ion injection operation for the purpose of making the threshold to be a desired value and 210 represents a P.sup.+ layer.
However, the transistor structured as described above arises the following problems.
A first problem takes place in that drain current ID and the mutual inductance (gam) are too small due to the presence of the n.sup.- layers 207 and 208. A second problem arises in that the mobility is deteriorated, and a third problem will arise in that the gate width W cannot be fined with the similar scaling to that for use to fining the gate length L.
The aforesaid problems will now be described.
FIG. 102 is a graph which illustrates an example of the relationship between the length of the channel and the drain current as disclosed in K. Yano, M. Aoki, and T. Masahara Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Material (1986) PP85 to 88. FIG. 102 shows results of comparisons made between a drain voltage VD of 0.1 V, 5 V, temperature of 77 K. and 300 K.
As can be understood from FIG. 102, parasitic drain resistance generated due to the n.sup.- layers 207 and 208 causes the decrease of the length of the channel and the increase in the drain current are not in proportion to each other as designated by a dashed line XA but are made as designated by a solid line XB. Referring to FIG. 102, symbol XC shows measured values. Since a large drain current is not obtained as described above, the mutual conductance characteristics (the gm characteristics) are deteriorated.
A rule of scaling a typical MOSFET is shown in Table 1.
TABLE 1 ______________________________________ Parameter Scaling Ratio ______________________________________ Length of channel 1/K Width of channel 1/K Thickness of gate oxide film 1/K Depth of joint 1/K Thickness of Depletion layer 1/K Concentration of impurities K in channel Voltage 1/K ______________________________________
As can be understood from Table 1, the punch-through current between the source and the drain generated due to fining of the channel length L can be prevented by raising the impurity concentration Na of the region which is formed into the channel. However, the concentration of the impurities in the channel is raised, the mobility of the carrier is lowered and thereby the gm characteristics are deteriorated. It might therefore be considered feasible to employ a method in which the p.sup.+ layer 210 is brought near the gate insulating film 205. In this case, the field intensity in the vertical direction in relation to the direction in which the carrier is moved is raised. Therefore, also the mobility of the carrier is lowered while maintaining the correlative relationship as shown in FIG. 103 (which illustrates the relationship between the field intensity (axis of abscissa) in the vertical direction and the mobility (axis of ordinate) as disclosed in, for example, A. G. Sabnis et al IEDM 79 PP18 to 21, where XD, XE and XF are measured values when the power supply voltage was 0.1 V, -5.0 V and -20.0 V, respectively).
That is, the characteristics of the MOSFET having the gate length L ranged from 0.5 to 0.8 .mu.m can be improved to a certain degree according to the scaling rule shown in Table 1. However, the gate length L is smaller than the aforesaid range, the drain current and the gm characteristics excessively deteriorated. Furthermore, the fining operation will cause the proportion of the wiring section to be enlarged. Therefore, there is a desire of a transistor having further improved gm characteristics. However, it can be met by only widening the gate width W under the present conditions. Therefore, the original object of fining the size cannot be achieved.
Also a GOLD type (Gate Overlap Lightly Doped Drain) MOSFET which is a modification to the LDD type MOSFET encounters the aforesaid problems.
In order to overcome the aforesaid problems experienced with the MOSFET structured as described above, a surrounding gate transistor (SGT) has been disclosed which is arranged in such a manner that four gate electrodes face one another as suggested in H. Tadato, K. Sunoushim, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka IEDM (International Electron Device Meeting) (1988) PP222 to 225. The structure of it is shown in FIG. 128. FIG. 128A is a perspective view and 128B is a cross section taken along line A-A'.
Referring to FIGS. 66 and 67, reference numeral 215 represents a substrate, 216 represents a p well layer, 217 represents a source region, 218 represents a gate electrode, 219 represents a gate insulating film, 220 represents a drain region and 221 represents a drain outlet electrode. In the aforesaid structure, the gate electrode 218 is formed to surround the channel region. Therefore, the following advantages can be obtained: the concentration of the electric field can be relieved, the adverse effect of the hot carrier or the like can be eliminated and the control of the potential of the channel portion by using the gate can be easily performed.
FIG. 104A and FIG. 104B respectively are a plan view and a circuit diagram which illustrate a CMOS invertor circuit which utilizes an SGT. FIGS. 105 and 106 are cross-sectional views respectively taken along line A-A' and C-C' of FIG. 104A. The contact portions between Vin and PMOSFET and NMOSFET are represented by 230 and 231.
In the aforesaid conventional transistor, the portion between the source and the drain is not conductive in a normal state. Writing can be performed by applying negative high voltage between the source and the drain of the transistor, avalanche-breaking down the pn junction on the drain side and injecting large energy electrons generated at this time into the floating gate so as to cause the portion between the source and the drain to be a conductive state. In a case where the aforesaid device is used as a memory, facts whether or not the charge is injected into the floating gate are made correspond to information 1 and 0.
However, since the charge stored in the floating slightly leaks in the memory of the aforesaid type, problems arises in that information cannot be stored permanently and the reading characteristics are undesirably changed with time.
Furthermore, the aforesaid MOSFET is not suitable to be fined and its characteristics (gm characteristics) encounter a problem in that the mutual conductance is too small.
In addition, if the gate length is 0.5 .mu.m or less at the time of the fining operation, the improvement of the aforesaid MOSFET by scaling cannot be expected.
As a dynamic random access memory (DRAM), a vertical memory cell constituted by using a surrounding gate transistor (SGT) as the addressing transistor and by forming a trench capacitor in its main electrode region of the substrate has been suggested.
However, the inventors of the present invention found that a DRAM of the aforesaid type has the following problems: with the high integration exceeding 16M bits and further fining of the cell, the capacitor size is limited and the capacity is thereby reduced. As a result, a large signal charge cannot be stored. On the contrary, the parasitic capacity of the wiring is increased due to the fining process. As a result, the signal transmitted finally becomes too small and the SN ratio is also lowered at the time of reading the stored signal by means of the capacity division. Therefore, the memory is erroneously operated.
Furthermore, since the shape is formed into an vertical shape, the manufacturing process is too complicated and therefore the yield cannot be improved. As a result, a problem in terms the commercial viewpoint arises.
That is, the inventors of the present invention found that the original object to satisfactorily apply the fine transistor such as the SGT to the DRAM cannot be achieved.
Another semiconductor memory has been known which is arranged as shown in FIG. 46.
FIG. 46 is a cross sectional view which illustrates a semiconductor memory of the aforesaid type. Referring to FIG. 46, reference numeral 120 represents an n-type substrate, 121 represents a p.sup.+ drain, 122 represents a P.sup.+ source, 123 represents a floating gate, 124 represents an insulating layer, 125 represents a drain wiring and 126 represents a source wiring. The floating gate 123 is manufactured by, for example, embedding a polycrystalline silicone in a silicone oxide film. The portion between the source and the drain is not conductive in a normal state. Writing can be performed by applying negative high voltage between the source and the drain of the transistor, avalanche-breaking down the pn junction on the drain side and injecting large energy electrons generated at this time into the floating gate so as to cause the portion between the source and the drain to be a conductive state. In a case where the aforesaid device is used as a memory, facts whether or not the charge is injected into the floating gate are made correspond to information 1 and 0.
However, since the charge stored in the floating slightly leaks in the memory of the aforesaid type, problems arises in that information cannot be stored permanently and the reading characteristics are undesirably changed with time. Furthermore, the aforesaid MOSFET is not suitable to be fined and its characteristics (gm characteristics) encounter a problem in that the mutual conductance is too small.
In addition, if the gate length is 0.5 .mu.m or less at the time of the fining operation, the improvement of the aforesaid MOSFET by scaling cannot be expected.
The aforesaid conventional technology encounters another problem in that the voltage resistance of the oxide film in the Si edge portion is deteriorated.
FIG. 67 illustrates the process of the change in the thickness of the oxide film in the Si edge portion. Assuming that the thickness of the oxide film in the flat region made of Si is .delta.2 and that in the edge portion is .delta.1 as designated by 254 shown in FIG. 67, the following relationship is held: EQU .delta.1&lt;.delta.2 (1)
Furthermore, the shape of the Si in the edge portion tends to be formed into an wedge shape, causing the voltage resistance of the portion in the vicinity of the edge to be lowered.
Therefore, the reliability of the semiconductor device will be deteriorated.
The integrated circuits of the semiconductor integrated circuits using the MOS transistor have been further highly integrated. With the tendency of raising the degree of integration, the MOS transistor for use in the integrated circuit has been fined to a sub-micron order. However, if the gate size is reduced to the sub-micron order, the following problems arise:
1. The leak current increases due to the short channel effect. PA1 2. The VTH and the mutual conductance are undesirably changed due to the hot carrier effect.
In order to overcome these problems, an MOS transistor having a surrounding gate is used in the existing state.
FIG. 82 is a cross sectional view which illustrates an example of the structure of the conventional surrounding gate-type MOS transistor.
Referring to FIG. 82, reference numeral 651 represents a N-type Si substrate, 652 represents a P.sup.- layer for forming a columnar semiconductor layer, 653 represents a drain N.sup.+ layer of the NMOS, 654 represents a gate electrode, 655 represents a source N.sup.+ layer of the N-MOS, 656 represents an Al electrode for ejecting the drain, 659a represents a gate oxide film formed around the columnar semiconductor layer and 659b represents a gate oxide film formed under the gate electrode.
In the aforesaid conventional surrounding gate type MOS transistor (hereinafter called an "SGT-MOS Tr"), the thickness of the oxide film 659b under the gate electrode is the same as that of the oxide film (the side portion of the columnar semiconductor layer). In a case where the thickness of the oxide film 659b under the gate electrode is about 20 to 150.ANG., the gate . source capacity in the MOS Tr increases, causing a problem to arise in that the switching characteristics of the memory excessively deteriorate.
However, if the DRAM is formed by integrating 1-gigabit memory devices, it is considered that the size of a cell becomes about 0.3 .mu.m square. Therefore, the aforesaid vertical MOS transistor which is the most promising device in the age of the high integration devices encounters multiple problems at the time of the manufacturing process if the size is the aforementioned order.
In the method of manufacturing the conventional vertical MOS transistor, the top surface of the columnar silicon monocrytal region serving as a source region of the MOS transistor and the gate electrode are separated from each other while interposing a thin gate oxide film. Therefore, there arises the following problems:
(Problem 1)
The size of the contact portion of the source electrode becomes very small in a very fine pattern in which the vertical transistor is able to exhibit its performance. Therefore, a slight positional deviation taken place in relation to the lower layer at the time of forming a contact opening will cause a short circuit to be generated between the gate electrode and the source electrode. If the columnar silicon region is enlarged in order to overcome the aforesaid problem, the degree of integration of the overall circuit will be lowered.
(Problem 2)
If the introduction of impurities into the source region is performed by the ion injection, the gate oxide film adjacent to the source region can be easily damaged. Therefore, the short circuit between the source and the gate will take place or the reliability of the gate oxide film will be deteriorated.
(Problem 3)
Since the parasitic capacity between the source and gate electrodes increases, the high speed operation of the circuit is hindered.
Furthermore, the aforesaid conventional structure encounters a problem that patterning at the time of ejecting the wiring from the upper portion of the columnar semiconductor layer cannot be easily performed in a state where the width of the columnar semiconductor layer has been fined with proceeding of the fining operation. Therefore, the fining speed is limited.
FIG. 107 is an enlarged view which illustrates a contact hole portion shown in FIG. 104. Referring to FIG. 107, the contact hole 231 to be opened when the wiring is taken from the upper portion of the columnar semiconductor 217 is formed in such a manner that its longer side runs parallel to the longer side of the upper portion of the columnar semiconductor.
Therefore, assuming that the shorter side of the upper portion of the columnar semiconductor 217 is a and the alignment margin between the contact hole 231 and the columnar semiconductor 217 is x, the width of the contact hole 231 becomes a -2x or less.
As a result, it is very difficult to perform aligning with the contact hole and therefore the yield becomes too difficult. This leads to a fact, when a becomes a sub-micron order, the aforesaid process cannot be performed at the existing technological level.
What is even worse, when the aforesaid conventional structure is constituted, it is very difficult to perform a process in which wiring is arranged from the gate electrode, that is, a photolithography process in which both of the surrounding gate and the gate wiring portion are left. The aforesaid problem becomes critical with proceeding of the fining process and it is a critical problem for the surrounding gate type MOSFET.
USPTO Backgrounds
USPTO Backgrounds