A communications system equalizer is a circuit used in a receiver to compensate a received signal for losses and distortion experienced in a communication path between a transmitter of the signal and the receiver. In RF communication systems, such as cellular telephone systems, conventional practice could construct the equalizer circuit using discrete components or, more recently, using a suitably programmed digital signal processor (DSP). In this approach the DSP is normally not dedicated to performing only the equalizer function, but more typically is responsible for the execution of a number of other signal processing tasks as well. As a result, as data rates continue to increase it has been found that the DSP capacity, and especially the lack of available DSP capacity, has created a problem. The increase in data rates also increases the equalizer algorithm complexity, and thus requires higher DSP processing performance. Simply using a faster and higher powered DSP also creates problems, as this approach requires a significant number of skilled engineers, and a large amount of time, resources and risk, to migrate the existing DSP-executed software applications to a new DSP platform. In addition, faster DSPs generally consume more current, which can be a significant disadvantage in battery powered devices such as cellular telephones and personal communicators. This situation has created a need to transfer the DSP equalizer software functionality to hardware.
An Application Specific Integrated Circuit (ASIC) hardware implementation provides more processing power and is more area efficient than a DSP solution. Thus, there is a need for an equalizer implemented in hardware that is power and area efficient. There is also a need for a scalable equalizer. However, ASIC technology does not provide a quick design implementation, and is limited in its ability to be changed to accommodate revisions to a design or specification.
Trellis searching architectures have been studied for GSM (Global System for Mobile Communications) systems using serial (centralized) and parallel (distributed) approaches, as evidenced by A. Lloyd, M. Reynolds and Y. Shah, “VLSI Architectures for Viterbi Decoding,” IEE Colloquium on VLSI Implementations for Second Generation Digital Cordless and Mobile Telecommunication Systems, 1990, pp. 6/1–6/7, hereafter referred to as Lloyd and incorporated by reference herein in its entirety. The scalability of a systolic approach, as discussed by P. Gulak and T. Kailath, “Locally Connected VLSI Architectures for the Viterbi Algorithm,” IEEE Journal on Selected Areas in Communications, Vol. 6, No. 3, April 1988, pp. 527–537, hereafter referred to as Gulak and incorporated by reference herein in its entirety, has lead to a single type of processing element (PE) which can be used as the basis for either a serial or parallel approach to Viterbi decoding. The PE is amenable to the pipelining of computational elements, see P. Pirsch, “Architectures for Digital Signal Processing,” John Wiley, New York, 1996, hereafter referred to as Pirsch and incorporated by reference herein in its entirety, which allows multiple operations to occur on each clock edge.
In Lloyd a locally connected array is shown (FIG. 3), and these authors state that their VLSI architecture is applicable to both Viterbi decoding and Viterbi equalization.
Also of interest is publication by Chakraborty, Mrityunjoy and Suraiya Pervin, “A systolic array realization of the adaptive decision feedback equalizer”, Signal Processing, Vol. 80 (2000), No.: 12, pp. 2633–2640.
A need exists, as yet unfulfilled prior to this invention, to provide a scalable channel equalizer that is constructed and operated as a parallel, systolic array of like processing elements that exhibits, among other features, reduced state sequence estimation, decision feedback and a global search function for metric normalization and soft value determination in a serial parallel processor structure.
USPTO Backgrounds
USPTO Backgrounds