In the fabrication of integrated circuits (ICs) or chips, features are created by etching into the silicon substrate that may or may not include one or more device layers. These features are used to form devices or portions of devices. One type of feature such as a deep trench (DT), for example, is used to form a trench capacitor of a memory cell. Typically, in the process for forming a random access memory (RAM) integrated circuit (IC) or chip, an array of deep trenches are etched in the array region of the substrate. Trench capacitors are then formed from the trenches. Such trench capacitors are used to create an array of memory cells, which are interconnected by word-lines and bit-lines to form a memory IC.
FIGS. 1a-d show a portion of a process for forming the array of trench capacitors. As shown in FIG. 1a, a conventional pad stack 110 is formed on the surface of a substrate 101. The pad stack includes, for example, sequential layers of a pad oxide 112 and a pad nitride 114. Above the pad stack is a hard mask layer 116 comprising, for example, TEOS. The hard mask layer serves as a hard mask used to form the DTs. A layer of photoresist (not shown) is deposited over the hard mask and patterned to selectively expose areas within the array region where the DTs are to be formed. The substrate is then etched by a reactive ion etch (RIE), forming the DTs.
The RIE erodes the hard mask layer at a greater rate in the array region 135 than the non-array (field) region 130, resulting in a large step between the field and array regions. Subsequently, at least after formation of a node dielectric, the trenches are filled with, for example, heavily doped polysilicon (poly) 150. Since the poly is conformal, the topography created during RIE is transferred the poly layer as well.
In FIG. 1b, a chemical mechanical polish (CMP) is performed to provide a planar surface. The CMP is selective to the hard mask layer, removing the poly without effectively removing the hard mask. As can be seen, the CMP erodes the poly in the array region, causing a depression to form therein. This is referred to as dishing. Due to the large step that exists, poly residuals remain at the edges 160 of the array after CMP. After stripping the hard mask layer as shown in FIG. 1c, poly "ears" 165 protrude above the pad nitride layer in the DTs. Because of the poly residuals remaining in the edges during the previous CMP step as a result of the topography, the ears at the array edges are higher than the ears in the middle or plateau portion 162. For example, the height of ears at the edges can be&gt;than about 2500A and the height of the ears in the plateau car range from about 0 to 1500A.
A touch up CMP is required to remove the poly ears. However, as shown in FIG. 1d, the touch up CMP causes erosion of the pad nitride layer in the array region. Further, the pad nitride erosion is more pronounced at the edge than at the plateau portion of the array region. Such erosion causes variations in gate threshold voltage and, in some designs, increases buried strap resistance, adversely affect yield.
As apparent from the foregoing discussion, it is desirable to provide an improved pad stack for use in etching DTs.
USPTO Backgrounds
USPTO Backgrounds