The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to solder bump connections and methods for fabricating solder bump connections during back-end-of-line processing of semiconductor chips.
A chip or die includes integrated circuits formed by front-end-of-line processing, a local interconnect layer formed by middle-end-of-line processing, and stacked metallization levels of an interconnect structure formed by back-end-of line processing. Chips may be packaged and mounted on a circuit board or other chip carrier using a controlled collapse chip connection or flip chip process. The solder bumps provide mechanical and electrical connections between features in the last or top metallization level and the circuit board. The solder bumps can be formed using any number of methods, including electroplating, evaporation, printing, and direct placement. The solder bumps establish physical attachment and electrical contact between an array of pads on the chip and a complementary array of pads on a circuit board.
Solder bump connections and fabrication methods are needed that improve on conventional solder bump connections and fabrication methods.
USPTO Backgrounds
USPTO Backgrounds