As the development of semiconductor technology, the size of CMOS (Complementary Metal Oxide Semiconductor) devices continues to shrink. After entering the nanometer times, many problems relative to the limit of the semiconductor device have appeared. Such problems include, in particular, capacitance loss, short channel effects, increase of leakage, and degradation of device isolation, which are caused by diffusion of dopants in the source/drain regions into the substrate. The problem of the diffusion of the dopants into the substrate is currently solved by SOI (Semiconductor On Insulator) technology, in which an insulating layer (e.g. a SiO2 Buried Oxide) is buried between two semiconductor substrates (e.g. Si substrates) to isolate transistor devices. The SiO2 Buried Oxide can effectively prevent diffusion of the dopants into the substrate, so as to alleviate the parasitical capacitance of the device and the short channel effects.
However, in the SOI technology, CMOS devices are manufactured using a SOI wafer formed by complex processes as a substrate. Thus, it is necessary to improve the structure of the CMOS devices and their manufacturing process to provide a simpler structure for preventing the dopants in the source/drain regions from diffusing into the substrate, as well as a method for forming the structure.
USPTO Backgrounds
USPTO Backgrounds