RAM devices have become widely accepted in the semiconductor industry. Furthermore, system-on-chip (SOC) devices typically include internal RAM for storage of information such as instructions and/or data. Internal memory blocks in an SOC device typically occupy substantial chip area of an integrated circuit (IC) chip that contains the SOC device. For example, internal memory blocks may occupy as much as about 70% of the IC chip area of an SOC device. The configuration of internal memory in SOC devices are generally similar to the configuration of memory in individual memory chips.
Each block of RAM includes a number of memory cells. Each memory cell typically stores one bit of information. Typical RAM blocks have capacity to store anywhere from thousands to millions of bits of data. Since vast numbers of memory cells are used to store information in RAM blocks, the size of RAM blocks depends, to large extent, on the size of each memory cell.
Memory cells in dynamic random access memory (DRAM) blocks typically require less number of transistors per bit than cells in a static random access memory (SRAM). DRAMs typically cost less to produce than other types of memory devices due to their relative simplicity. For example, some DRAM blocks contain memory cells with three transistor (3-T) per bit, while other DRAM blocks contain memory cells with one transistor (1-T) per bit. Therefore, DRAM blocks of SOC devices and DRAM chips are typically smaller than SRAM blocks with similar information storage capacity.
However, DRAM cells need to be refreshed periodically for retaining the stored charge. A typical refresh operation comprises of selecting a memory cell, reading the stored value, and writing the same stored value back to the respective cell. Since typically the memory is accessed one word at-a-time, the refresh operation may be performed at a higher rate of one word at-a-time rather than one cell at-a-time, however, the time interval between refreshing word may still be large. This large time interval between refreshing particular words may not be sufficient for memory cells in a large memory module to retain their charges.
The maximum time interval between required refreshes is directly proportional to the capacitance of the DRAM cell and exponentially related to the (additive) inverse of the absolute operating temperature. Traditional DRAM memories are fabricated with a capacitance of 15-30 femto-Farad per bit. This capacitance is achieved by chip fabrication steps which are not usually a part of logic CMOS processing. DRAM memories which are integrated on-chip and fabricated with a standard CMOS process flow have a lower capacitance, in the range of 3-10femto-Farad per bit for 0.18 μm technology. These cells require shorter refresh intervals. For a large memory, it may be necessary to refresh more than one memory word simultaneously to meet the refresh interval requirement, particularly at temperatures above 100 C.
Furthermore, traditional mechanisms for selecting a word of a hierarchical memory for refresh involves supplying an address that is decoded and results in the unique activation of a memory bank and one global word line. This mechanism utilizes almost the entire memory infrastructure to accomplish an action that is local to a particular memory block.
Therefore, there is a need for a flexible system and method capable of refreshing many words simultaneously.
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