1. Field of the Invention
The present invention relates to the field of fabrication of microelectronics devices. More particularly, the present invention relates to the fabrication of inter-level metal dielectric (IMD) layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics devices are becoming increasingly complex and the density of circuits has increased as dimensions have shrunk. It has become necessary to have additional levels of interconnection wiring to handle this increase in need. For this reason, multiple levels of conductor and dielectric materials are now commonly employed within microelectronics fabrications. In addition to the necessary properties such materials must have to fulfill the needs of conduction and insulation, there are the increasingly demanding requirements upon patterning method, electrical contact resistance control, dielectric constant and so forth.
In order to facilitate multiple levels of interconnection wiring, there has been developed an inter-level metal dielectric (IMD) layer technology for microelectronics fabrication. This type of structure employs lower conductor level separated from an upper conductor level by means of an intermediate dielectric layer or layers with electrical via contacts therewith to interconnect the conductor layers. There are several variations on the basic IMD approach, and one of the more common IMD methods employs recessed wiring layers within the dielectric layer to maintain surface planarity as the number of levels increase. When both the via contact openings and the inlaid trench for the wiring pattern are filled with a conductor material, the entire system is referred to as a "dual damascene" IMD layer. The openings for the via contact layer and the wiring trench for the interconnection layer are generally formed employing photoresist technology as is known in the art of microelectronics fabrication.
Although the dual damascene conductor interconnection layer inlaid within an IMD layer is a method which is in general satisfactory, this IMD layer technology is not without problems. For example, it is often desirable to employ low dielectric constant dielectric material to form one or more of the dielectric layers in an IMD layer, in order to reduce capacitance. Many low dielectric constant dielectric materials with otherwise excellent properties are formed of organic polymers, and there is occasionally an incompatibility with photoresist materials, which are also organic polymers formulated with solvents, which may interact with the organic polymer low dielectric constant materials. Likewise, after employment of photoresist material to form either the via openings or the wiring trench pattern of a dual damascene interconnection structure, it is often difficult to remove photoresist residues without simultaneously damaging the low dielectric constant dielectric layer.
It is thus towards the goal of forming an inter-level metal dielectric (IMD) layer employing low dielectric constant dielectric materials and a dual damascene interconnection scheme with attenuated degradation from interaction with organic material residues that the present invention is directed.
Various methods have been disclosed for providing inter-level metal dielectric (IMD) layers with attenuated degradation from organic material residues and common cleaning and stripping procedures.
For example, Gue et al., in U.S. Pat. No. 5,763,010, disclose a method for reduction of migration of dopant atoms from halogen-doped silicon oxide dielectric films during processing. The method employs a prior heating step at between 300 and 350 degrees centigrade to outgas loosely bonded halogen atoms from the doped silicon oxide film, thus stabilizing the remaining halogen atoms during subsequent processing.
Further, Chen et al., in U.S. Pat. No. 5,866,945, disclose a method for reduction of degradation of silsesquioxane (HSQ) dielectric layers due to subsequent photoresist processing. The method employs plasma treatment of the HSQ dielectric layer to restore Si--H bonds and thus passivate the surface of the HSQ dielectric layer with respect to damage resulting from subsequent photoresist processing such as stripping with an oxygen-containing plasma.
Yet further, Denison et al. in U.S. Pat. No. 5,869,149, disclose a method for forming a fluorine containing silicon oxide with enhanced moisture resistance. The methods forms first a fluorine-containing silicon oxide layer by plasma enhanced chemical vapor deposition (PECVD) followed by nitridation of the surface of the fluorine-doped silicon oxide layer employing a nitriding gas in a plasma at a temperature above 300 degrees centigrade. The nitriding gas may be nitrogen, nitrous oxide and/or ammonia.
Still further, Ngo et al., in U.S. Pat. No. 5,888,898, disclose a method for forming a low dielectric constant dielectric layer with minimized dielectric constant. The method first forms a silsesquioxane (HSQ) low dielectric constant dielectric layer which is baked in an inert nitrogen atmosphere followed by soaking in a nitrous oxide atmosphere for 10 seconds. A layer of PECVD silicon oxide is then formed over the HSQ layer.
Yet still further, Chang et al., in U.S. Pat. No. 5,899,751, disclose a method for forming a planarized dielectric layer employing silsesquioxane (HSQ) dielectric material, with improved thermal stability and dielectric constant. The method employs dissolving HSQ dielectric material in a solvent, casting a layer and allowing the solvent to evaporate. The remaining HSQ layer is heat treated from between 150 to 400 degrees centigrade to form a silica coated later. A fluoride implant treatment is then employed.
Further still, Tao et al., in U.S. Pat. No. 5,904,566, disclose a method for forming a via through a nitrogenated silicon oxide dielectric layer. The method first forms a nitrogenated silicon oxide dielectric layer, followed by employment of a patterned photoresist etch mask and a reactive plasma etch to etch the pattern of via holes through the nitrogenated silicon oxide dielectric layer.
Yet further still, Yamashita, in U.S. Pat. No. 5,918,146, discloses a method for forming an inter-level metal dielectric layer with improved planarization obtained by reflow of the dielectric layer. The method forms silicon oxide dielectric layers employing aromatic or heterocyclic organic compounds reacting first with an oxidant to form a product layer with reflowed planarized surface. The layer is then converted by heat treatment to form a silicon oxide dielectric layer with excellent planarity and a low dielectric constant.
Finally, Tran, in U.S. Pat. No. 5,942,801, discloses a method for forming silsesquioxane (HSQ) dielectric layers in which may be formed via holes with improved properties. The method employs local heating of the HSQ dielectric layer to increase the density and etch resistance in regions where via holes are to be formed. Local heating may be accomplished by heating an adjacent metal line to afford local infrared heating.
Desirable in the art of microelectronics fabrication are additional methods for forming inter-metal dielectric (IMD) dielectric layers with patterned conductor layers and via hole contact layers formed therein with attenuated degradation from organic material residues and means for cleaning and stripping same.
USPTO Backgrounds
USPTO Backgrounds