1. Field of the Invention
The present invention relates to a one-chip microprocessor with built in memory, such as a cache, a TLB (Translation Lookaside Buffer) and the like, more particularly, the invention relates to techniques which prevent using improper data generated by memory faults in the memory built in the microprocessor, and improper address/data inputted from the outside of the microprocessor. It also relates to a one-chip microprocessor wherein a restoration rate after the occurrence of internal error is improved.
2. Description of the Related Art
With the progress of LSI manufacturing techniques, a central processing unit (CPU) and large-scale memories can be integrated in one chip. However, on the other hand, a reliability of LSI having an improved degree of integration becomes an important problem.
FIG. 1 is a block diagram showing a general configuration of a CPU board, whereon a one-chip microprocessor building in a cache memory and a TLB (Translation Lookaside Buffer) is installed.
The CPU board 1 includes, a conventional microprocessor 2 building in the cache memory and the TLB, an interrupt controller 3 which asserts an interrupt signal to the microprocessor 2 and a system controller bus 9, an external cache memory 5, an external cache controller 4 controlling the external cache memory 5, a main memory 7, a main memory/bus controller 6 controlling the main memory 7 and a system data bus 8 and so on.
The microprocessor 2, interrupt controller 3 and external cache controller 4 are interconnected by a processor bus 10, and the external cache controller 4, external cache memory 5, main memory/bus controller 6 and main memory 7 are interconnected by a memory bus 11.
FIG. 2 is a block diagram showing an internal configuration of the conventional one-chip microprocessor 2 shown in FIG. 1.
The conventional microprocessor 2 includes, a built-in cache memory unit 20, a cache access control unit 22, an instruction execution unit 23, a bus snoop control unit 24, a bus control unit 27, an input/output address unit 51, an input/output data unit 52, an address translation unit 74 and so on.
The cache access control unit 22, the instruction execution unit 23, the input/output address unit 51 and the address translation unit 74 are interconnected by an internal address bus 40, and the cache access control unit 22, the instruction execution unit 23, the input/output data unit 52 and the address translation unit 74 are interconnected by an internal data bus 41.
The cache access control unit 22 controls read/write of the built-in cache memory unit 20. A cache-hit signal 47 is asserted to the instruction execution unit 23 from the cache access control unit 22. A cache access address signal 45 and an access request signal 46 are given to the cache access control unit 22 from the instruction execution unit 23, and besides, a built-in cache invalidating signal 43 is given thereto from a bus snoop control unit 24.
The instruction execution unit 23 processes data according to an instruction sequence. The cache-hit signal 47 is given to the instruction execution unit 23 from the cache access control unit 22. The cache address signal 45 and the access request signal 46 are outputted to the cache access control unit 22 from the instruction execution unit 23, and an address translation control signal 76 is received from and given to the address translation unit 74.
The bus snoop control unit 24 controls to invalidate a specific address stored in the built-in cache memory unit 20 responding to a bus snoop signal 31 inputted from the outside of the microprocessor 2. Specifically, when the bus snoop signal 31 is inputted from the outside of the microprocessor 2, the bus snoop control unit 24, by asserting the built-in cache invalidating signal 43 to the cache access control unit 22 responding thereto, invalidates the specific address stored in the built-in cache memory unit 20.
When the microprocessor 2 accesses the external bus, the bus control unit 27 controls it by inputting and outputting a bus access control signal 36.
The input/output address unit 51 controls the input and output of address between an address bus 32 outside the microprocessor 2 and an internal address bus 40.
The input/output data unit 52 controls the input and output of data between a data bus 34 outside the microprocessor 2 and an internal data bus 41.
The address translation unit 74 builds in the TLB, and translates the address while sending and receiving an address translation control signal 76 to and from the instruction receiving unit 23.
Numeral 30 designates a clock signal supplied to the microprocessor 2.
Next, the operation of the conventional one-chip microprocessor 2 having the above-mentioned configuration is described.
At first, the operation at the time of TLB access and cache memory access is described.
TLB access is performed when the instruction execution unit 23 instructs the address translation unit 74 to translate an address to be accessed. Specifically, when the instruction execution unit 23 requests the address translation to the address translation unit 74 by outputting the address translation control signal 76, and outputs the address to be translated to the internal address bus 40, the address translation unit 74 fetches the address to be accessed from the internal address bus 40 and retrieves the built-in TLB.
When the address to be translated is registered in the built-in TLB, the address translation unit 74 outputs TLB data registered in the built-in TLB to the data bus 41. The instruction execution unit 23 fetches the data outputted from the address translation unit 74 from the data bus 41 to execute the instruction. The address translation unit 74 also outputs the address translation control signal 76 to the instruction execution unit 23 to inform completion of the address translation.
Cache memory access is performed as follows.
When the access request signal 46 and the cache access address signal 45 which designates address to be accessed are asserted to the cache access control unit 22 from the instruction execution unit 23, the cache access control unit 22 retrieves whether the address designated by the cache access address signal 45 is registered in the built-in cache memory unit 20 or not. When the address designated by the cache access address signal 45 is registered in the built-in cache memory unit 20, the cache access control unit 22 asserts the cache-hit signal 47 to the instruction execution unit 23, reads corresponding cache data from the built-in cache memory unit 20 and outputs it to the internal data bus 41. The instruction execution unit 23 fetches the data outputted to the internal data bus 41 to execute the instruction.
Now, when TLB access address data is not registered in the built-in TLB or data designated by the cache access address signal 45 is not registered in the built-in cache memory unit 20 at the time of TLB access, the microprocessor 2 executes bus access to the external memory of the microprocessor 2 or the main memory 7 shown in FIG. 7. When an abnormal state has occurred at the time of bus access, this is alerted to the microprocessor 2 by a bus error (berr#: # means low active) signal which is one of the bus access control signal 36. When the bus error signal is asserted at completion of the bus access, the microprocessor 2 stores error in formation of address, data, data size, read/write and so on which have generated the error in an internal register.
Next, the bus snooping operation is described.
When DMA (Direct Memory Access) is transferred by the main memory/bus controller 6 on the CPU board 1 and data stored in a certain address of the main memory 7 is changed, there is a possibility that a consistency of data stored in the built-in cache memory unit 20 and the main memory 7 as the same address data can not be held.
In this case, it is necessary to invalidate the specific address of the built-in cache memory unit 20 to hold the consistency of data between the built-in cache memory unit 20 and the main memory 7. Such an operation is the bus snooping and is specifically described in the following.
The external cache controller 4 always monitors whether the data stored in the main memory 7 has been reloaded or not, and instructs the bus snooping operation to the microprocessor 2 according to the monitor result.
At the time of the bus snooping operation, at first, the bus snoop control signal 31 is asserted to the microprocessor 2 from the external cache controller 4, and address to be invalidated is outputted to the address bus 32. When an mreq# signal which is one of the bus snoop control signal 31 is asserted, the input/output address unit 51 suspends to output the address to the address bus 32 and inputs the address to be invalidated from the address bus 32. When ms# signal which is one of the bus snoop control signal 31 is inputted to the bus snoop control unit 24, which asserts the built-in cache invalidating signal 43 to the cache access control unit 22.
At this time, the input/output address unit 51 outputs the address to be invalidated to the internal address bus 40. When receiving the built-in cache invalidating signal 43, the cache access control unit 22 fetches the address to be invalidated outputted to the internal address bus 40 and retrieves the built-in cache memory unit 20. As a result, when the address is already registered in the built-in cache memory unit 20, the cache access control unit 22 invalidates the address.
In the above-mentioned memory access operation of the conventional microprocessor, even when memory faults such as software errors have occurred in the built-in cache memory unit, the TLB and the like, there is no way to detect it, thus there was a possibility that the instruction is executed intact by using data having the memory fault for false operation, results in data destruction.
Since a memory cell of the built-in cache, the TLB and the like can be more downsized by using an NMOS (high resistance load type) than using a CMOS, it is desirable to use the NMOS from the view point of a high integration of a chip. However, when the memory cell is constituted by the NMOS, a possibility of occurrence of memory faults is relatively high.
Since a function for checking the address to be invalid dated inputted to the microprocessor at the time of bus snooping operation is not included in the conventional microprocessor, when the bus fault has occurred on the CPU board, the wrong address caused by the bus fault is inputted to the microprocessor, thereby the built-in cache memory is invalidated at an address at which the built-in cache memory need not be invalidated and the address which was to be invalidated originally is not invalidated. In such cases, the built-in cache memory is accessed without the consistency of data between the main memory and the built-in cache memory, thus there was also a possibility that the old data which is to be invalidated originally is used to execute the instruction, results in a wrong operation and data destruction.
Furthermore, when error information related to errors generated at the time of bus access is to be saved, only read/write information related to the type of bus cycle can be saved in the conventional microprocessor. For example, as to the read bus access, it was problematic in that, conventionally, the instruction read and the address translation table read for data storage can not be distinguished.
Regarding this respect, for example, in the Japanese Patent Application Laid-Open No. 62-143149 (1987), a memory management unit of an information processing system, having holding means for holding error information including details on failure causes when access to a storage medium has failed is disclosed. However, in the invention disclosed in the Japanese Patent Application Laid-Open No. 62-143149 (1987), a virtual memory management method is adopted in the information processing system for pipeline processing of a decode-and-address calculating stage and an operation execution stage, and a technique coping with page fault generated thereby is disclosed, but address errors, data errors and the like in the CPU board whereon the one-chip microprocessor is installed are not considered.
USPTO Backgrounds
USPTO Backgrounds