(a) Field of the Invention
The invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device for enabling a rapid random access while saving power dissipation.
(b) Description of the Related Art
For a semiconductor memory device, in particular, for a dynamic random access memory device (DRAM), a page mode or nibble mode technique is implemented as a technology which achieves a higher access rate. Recently, a technology referred to as synchronous technique (synchronous DRAM) was developed. Also adopted was an interleave technique in which a memory unit is divided into a plurality of banks, to which addresses are consecutively allocated, and an access demand is consecutively applied for each bank independently to achieve a parallel operation.
The synchronous technique, the nibble mode and the interleave technique are technologies which achieve a higher rate when accessing data located at consecutive addresses, and hence have scarcely any effect when accessing random addresses. By contrast, the page mode allows an access of a group of memory cells, which are located in a single row and selected by a row address, to be accessed consecutively and in a random manner by merely changing a column address without repeating the row address, and is highly appreciated in the field where a rapid random access is required.
FIG. 1 is a block diagram of a conventional DRAM which has such a page mode function. In this example, DRAM 100 essentially comprises: a memory cell assembly 104 including a plurality of word lines 101, a plurality of bit line pairs 102 which intersect the word lines 101 while being insulated therefrom, and a plurality of memory cells 103 which are located at the intersections between the bit line pairs and the word lines 101 and which allow a read-out of stored data onto a selected bit line pair 102 or a storage of data from a selected bit line pair 102 when a particular word line 101 is at its selected level; and an associated peripheral circuit.
The peripheral circuit includes a sense amplifier assembly 105 including individual sense amplifiers each for amplifying data which is read out onto a corresponding bit line pair, read/write controlling switches and other switches which precharge/equalize the bit line pairs 102, a row address decoder 106 which selects a particular word line 101 in accordance with an input row address, a sense amplifier control circuit 107 which controls the sense amplifier assembly 105, and a column address decoder 108 which selects a particular bit line pair on which an output is to be delivered in accordance with an input column address.
The dynamic random access memory also includes a pair of input/output data lines 109, and receives from outside the memory cell a reference clock 110, a row address 111, a column address 112, a chip select signal 113 and a read/write control signal 115. In FIG. 1, a particular row 114 is exemplarily selected from the memory cell assembly 104 and shown in detail.
FIG. 2 is a timing chart illustrating the operation of the DRAM 100 shown in FIG. 1 when memory cells "a" to "e" located within the row 114 are accessed randomly in the sequence of "a", "b", "d", "c", and "e". When a row address 111 is input in synchronism with a reference clock 110, the row address decoder 106 brings the particular row 114 corresponding to the row address 111 to its selected level, thus connecting the respective memory cells disposed in the row 114 with the bit line pair 102, and the sense amplifier assembly 105 operates under the control of the sense amplifier control unit 107 to amplify the data which is read out onto the bit line pair 102. This operation continues for the duration that the row address 111 continues as long as the chip select signal 113 is active.
When a column address 112 which selects a memory cell "a" is input in synchronism with the reference clock 110, the column address decoder 108 responds thereto by selecting the bit line pair 102 which is connected to the memory cell "a" and connecting the bit line pair 102 with the input/output data lines 109. In this manner, the data from an initial memory cell "a" is read out at a timing as shown in FIG. 2 for a read operation. Subsequently, as the column address 112 is sequentially changed in synchronism with the reference clock 110 while maintaining the row address 111 fixed, memory cells "b", "d", "c" and "e" are consequentially accessed. Accordingly, it will be seen that, assuming that one row contains m bits, a random access is achieved at a higher rate in a range within the m bits.
There is proposed another semiconductor memory device which incorporates a plurality of higher rate technologies. For example, Patent Publication No. JP-A-58 (1983)-196,671 proposes a semiconductor memory device including a mode controlling latch and a selecting circuit which selects one of the page mode and nibble mode which corresponds to a set-up in the mode controlling latch, thus allowing the supported higher rate operation mode to be changed in accordance with the set-up in the mode controlling latch. Also, Patent Publication No. JP-A-3 (1991)-1,394 proposes a semiconductor memory device including a mode specifying register and a selecting circuit which selects one of the page mode and the interleave control mode in accordance with the set-up in the mode specifying register, thus changing the supported higher rate operation mode in accordance with the set-up in the register.
As mentioned above, a higher rate operation of a semiconductor memory device is realized by employing a page mode in a field where a rapid random access is required. However, in a conventional semiconductor memory device which is provided with the page mode function, the random access at a higher rate is limited to memory cells disposed in a single row which is selected by a row address. To extend a region over which the random access is enabled, it is necessary to increase the number of memory cells disposed in one row. This increases the number of sense amplifiers which are activated at a time, presenting a difficulty that the power dissipation becomes greater.
In a semiconductor memory device which is provided with a page mode as well as other types of higher rate technologies such as the nibble mode or interleave control mode, only one mode is selected at any time. Accordingly, when the page mode is selected for the rapid random access, the area which permits rapid random access is limited to memory cells disposed in a single row, presenting the similar difficulty as mentioned above.
USPTO Backgrounds
USPTO Backgrounds