1. Field of the Invention
The present invention relates to a technique of adjusting a dot clock signal for processing a video signal. Especially the invention pertains to a technique of adjusting the phase of a dot clock signal as well as to a technique of adjusting the frequency of the dot clock signal. The video signal in the present invention denotes an image signal supplied from an image signal output device such as a personal computer.
2. Description of the Related Art
FIG. 40 is a block diagram illustrating a video image display apparatus utilizing a conventional technique. The video image display apparatus includes an A-D converter 1, a driving circuit 2, a display device 3, a display timing control circuit 5, a PLL (Phase Locked Loop) circuit 7, and a delay circuit 10. The PLL circuit 7 multiplies the frequency of a horizontal synchronizing signal 102 for an analog video signal 101, by a predetermined factor Nd to generate a reference clock signal 200. The delay circuit 10 gives a delay φ to the reference clock signal 200 to generate a dot clock 201. The analog video signal 101 is sampled by an A-D converter 1 at a rise of the dot clock 201 and converted to a digital video signal 110. The driving circuit 2 executes a signal processing on the digital video signal 110 to make it suitable for the display device 3, and supplies the processed video signal to the display device 3 for display of an image. The dot clock 201 is also given to the driving circuit 2, the display device 3, and the display timing control circuit 5. The display timing control circuit 5 further receives the horizontal synchronizing signal 102. The display timing control circuit 5 controls the display timing of the display device 3 according to the horizontal synchronizing signal 102 and the dot clock 201.
The PLL circuit 7 and the delay circuit 10 constitute a dot clock regeneration circuit for regenerating a dot clock signal (dot clock) suitable for the processing of the analog video signal 101, from the horizontal synchronizing signal 102. The factor Nd in the PLL circuit 7 and the delay φ in the delay circuit 10 are adjustable parameters in generating the dot clock 201. In other words, it is desirable to set appropriate values to both the delay φ and the factor Nd, in order to regenerate the dot clock signal 10 suitable for the analog video signal 101. The delay φ of the dot clock signal relates to the phase of the dot clock signal, whereas the factor Nd relates to the frequency of the dot clock signal. There are some problems regarding the adjustment of the delay φ (that is, the adjustment of the phase) and the adjustment of the factor Nd (that is, the adjustment of the frequency) as described below.
The analog video signal 101 output from a video image output apparatus, such as a personal computer, was generated in synchronism with an internal video clock of the video image output apparatus. The signal level thus varies at the cycles of the internal video clock. A dot clock (also referred to a sampling clock) having the same frequency as that of the internal video clock of the video image output apparatus is required in order to carry out appropriate signal processing for displaying a video image corresponding to the analog video signal 101 on the display device 3 or the signal processing for writing the analog video signal 101 into a memory. In the computer system, such as a personal computer, however, no video clock is output to an output terminal of video signals. In the conventional system shown in FIG. 40, the PLL circuit 7 multiplies the frequency of the horizontal synchronizing signal 102 by the factor Nd to generate the reference clock signal 200, and the delay circuit 10 further gives a delay to the reference clock signal 200 to regenerate the dot clock 201. Here the factor Nd in the PLL circuit 7 is set to coincide with a demultiplication factor, or frequency division ratio, used for generating the horizontal synchronizing signal 102 from the video clock in the video image output apparatus. This makes the dot clock 201 to have the same frequency as that of the original video clock.
FIGS. 41(a)-41(c) are timing charts showing the relationship between the video signal 101 and the dot clock 201. The video signal 101 has a stable range 121 having image information proper to the video signal 101 and a transient range 122 including ringing and rounding generated by the effects of an output circuit of the video image output apparatus and a connection cable. When a dot clock rising in the stable range 121 such as a dot clock 201A shown in FIG. 41(b) is used, a normal video image is displayed on the display device 3. When a dot clock rising in the transient range 122 such as a dot clock 201B shown in FIG. 41(c) is used, on the other hand, the A-D converter 1 samples image information that is not proper to the video signal 101, and the resulting video image displayed on the display device 3 accordingly has undesirable noises or poor sharpness.
FIGS. 42(a)-42(c) are timing charts showing the relationship between the horizontal synchronizing signal 102, the reference clock 200, and the dot clock 201. The reference clock 200 output from the PLL circuit 7 is in phase with the horizontal synchronizing signal 102. Since the relationship between the phase of the horizontal synchronizing signal 102 and that of the video signal 101 is not specifically defined, the phase at a rise of the reference clock 200 may deviate from the phase of the video signal 101. A rise of the dot clock 201 may accordingly exist in the transient range 122 (FIG. 41(a)).
In the conventional system, a user manually adjusts the delay time φ (that is, the phase) of the dot clock 201 shown in FIG. 42(c) to an optimum state while checking a video image on the display device 3 so that the displayed video image has no noise and sufficient sharpness. This manual operation is, however, rather troublesome, and little understanding of the requirement for the adjustment may lead to some misunderstanding that the display device has poor performance or even malfunctions.
A method of automatically adjusting the phase of the dot clock 201 is, for example, disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 4-276791. This method comprises the steps of: sampling two sets of image data in synchronism with dot clocks having different phases; storing them into two different memories; and determining an optimum phase of the dot clock so that the two sets of image data read out of the memories coincide with each other. When the video signal includes ringing and rounding and has a narrow stable range, only a little shift of the phase causes a difference in the resulting image data. Potential noise also slightly changes the image data. The two sets of image data obtained with the dot clocks with different phases thus hardly coincide with each other actually, and it is rather difficult to determine the optimum phase of the dot clock. This method also requires two high-speed line memories to process high-speed video signals, thereby undesirably raising the equipment cost.
The adjustment of the factor Nd in the PLL circuit 7 (FIG. 40), that is, the adjustment of the frequency of the dot clock, also has the following problem. FIG. 43 shows timing of the video signal 101 in a two-dimensional manner. A standard video signal is a one-dimensional signal representing a video image on each scanning line. One page image is constructed by scanning each line from left to right in the horizontal direction and repeating the scanning procedure for all the lines in one page from an upper left end to a lower right end. A horizontal synchronizing signal 102 adjusts the scanning timing of the video signal 101 in the horizontal direction, whereas a vertical synchronizing signal 103 adjusts the scanning timing of the video signal 101 in the vertical direction. A CRT display requires a time period for returning the electron beam from right to left and from bottom to top, so that blanking areas 302 are set both in the horizontal direction and in the vertical direction. An effective signal area 301 other than the blanking area 302 is the area in which a video image is actually displayed. The timing of the blanking area 302 and the effective signal area 301 in the horizontal direction is expressed by the number of pixels corresponding to the number of pulses of the dot clock. Although the timing in the vertical direction should be expressed by the number of scanning lines, it is often expressed by the number of pixels instead.
In personal computers, there are several standard sizes for the effective signal area 301. Typical standards include VGA (640 pixels (dots) in the horizontal direction×480 pixels in the vertical direction), SVGA (800 pixels×600 pixels), XGA (1024 pixels×768 pixels), and SXGA (1280 pixels×1024 pixels). The specific standard applied to the video signal can be identified from the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal of the video signal.
These standard sizes represent the number of pixels included in the effective signal area 301 of FIG. 43 and do not define the total number of pixels in one scanning line including both the blanking area 302 and the effective signal area 301. A variety of arbitrary values are actually used as the total number of pixels for one line. While the number of pixels in the effective signal area 301 can be determined from the synchronizing signals, the total number of pixels for one line is unknown, and therefore the optimum factor Nd to be set in the PLL circuit is unknown.
FIGS. 44(a-1)-44(a-3) and FIGS. 44(b-1)-44(b-3) are timing charts showing the relationship between the analog video signal 101, the dot clock 201, and the digital video signal 110. The digital video signal 110 is shown in the analog form for the clarity of explanation. FIGS. 44(a-1) through 44(a-3) show the case in which the factor Nd in the PLL circuit 7 is equal to a frequency division ratio used for generating the horizontal synchronizing signal from the video clock in the video image output apparatus that generates the video signal 101. In this case, the phase of the dot clock 201 relative to the variation points of the video signal 101 is fixed. The resulting digital video signal 110 appropriately reproduces the video signal 101 and enables a proper video image to be displayed on the display device 3.
If the factor Nd in the PLL circuit 7 is different from the frequency division ratio in the video image output apparatus, on the other hand, the phase of the dot clock 201 relative to the video signal 101 varies with respect to each position in the horizontal direction as shown in FIGS. 44(b-1) through 44(b-3). In this case, the amplitude of the digital video signal 110 varies according to the pixel position, and thus shows “beats”. A resulting video image displayed on the display device 3 shows vertical lines due to the small amplitude portion of the beats and may suffer from a loss of some image information.
In the conventional video image display apparatus, appropriate factors Nd for the commercially-available popular personal computers may be registered in advance. The type of the video image output apparatus is identified according to the frequencies and the polarities of the horizontal synchronizing signal 102 and the vertical synchronizing signal 103. The optimum factor Nd for the video image output apparatus is then selected from the preset alternatives and set in the PLL circuit 7. In case that the appropriate factor Nd has not been registered for a specific video image output apparatus, the user has to manually set the optimum factor Nd while monitoring the screen of the display device.
Known methods for automatically determining the unknown factor Nd are, for example, disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 3-295367 and No. 5-66752.
The method disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 3-295367 stores the sampled video signals in a compressed form and checks whether or not the data are stable with respect to a plurality of inputs, thereby detecting a deviation of the factor.
This method only detects whether the factor is deviated or not, and cannot determine the degree of the deviation. This method would repeat the comparison while varying the factor and thus requires a relatively long time for determining the optimum factor. Further, if the phase of the dot clock (that is, the delay φ in the delay circuit 10) is improper, this conventional method cannot determine the optimum factor.
Another known method disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 5-66752 detects a dot cycle from the edge component of the video signals: detects a scanning cycle from the horizontal synchronizing signal; and compares the dot cycle with the scanning cycle to determine the factor in the PLL circuit.
This method, however, requires another clock signal having a significantly higher frequency than that of the dot clock to measure the dot cycle. An extremely high dot clock frequency would be required for signals having a large total number of pixels. This method is accordingly not practical.
USPTO Backgrounds
USPTO Backgrounds