1. Field of the Invention
The present invention relates to a technique for evaluating the characteristics of devices and interconnect lines which constitute an integrated circuit by using simulation and, more particularly, to correction for configuration simulation.
2. Description of the Background Art
The degree of integration in integrated circuits (referred to hereinafter as "ICs") is becoming increasingly higher year by year, and the configuration and construction of semiconductor devices and interconnect lines are becoming finer and more complicated. The characteristics of the ICs significantly depend upon the properties of such internal devices and interconnect lines of the ICs. For example, a capacitance between electrodes of a MOSFET is greatly associated with the operating characteristics of a circuit in high-frequency ranges, and a parasitic capacitance between interconnect lines causes a signal delay. The uncertainty of physical quantities dependent upon the configuration and construction inside the ICs might cause operation failures such as a difference between an actual operating speed and an estimated operating speed when designed.
Thus, when ICs are designed, a large number of simulators are used to obtain predictable configurations and operations of the ICs being fabricated or having been fabricated. Examples of the simulators include: a process simulator for predicting changes in profiles at respective locations in an IC and changes in configurations of cross sections and surfaces in accordance with variations in parameters such as processing time in each step and a set temperature; a device simulator for calculating electrical parameters of devices based on information about an impurity profile, an oxide film configuration, and an electrode or interconnect line configuration; and a circuit simulator for verifying whether or not a circuit operates as designed. Simulation is repeated using these simulators to reproduce the predictable configurations and operations of the ICs as faithfully as possible for achieving optimum IC design.
Such simulation techniques include a capacitance simulation. The capacitance simulation calculates capacitances between electrodes or interconnect lines in a structure which further comprises dielectrics, by using a potential distribution and a charge amount distribution obtained by solving Laplace's equation and, if required, Poisson's equation, a current continuity equation, and a current drift and diffusion equation (which are referred to simply as "equations" hereinafter) by using numerical calculations. Solving the equations using the numerical calculations and determining the capacitance values have been widely studied as disclosed in, for example, Japanese Patent Application Laid-Open No. P03-89531A (1991) and Japanese Patent Application Laid-Open No. P05-89212A (1993).
The capacitance values depend on the charge amount distribution and the spatial potential distribution in the structure as above described. In other words, the capacitance values depend on the dielectric constant of dielectrics included in the given structure and on the configurations of the dielectrics and conductors. Thus, a high-accuracy simulation requires precise information about the structure.
There is a technique for determining resistance values and inductances in an IC based on the structure of the electrodes or interconnect line regions made of conductors. Similarly, this technique also requires precise information about the structure.
In particular, a demand for implementation of the capacitance simulation in a three-dimensional structure is increasing at present. However, three-dimensional complicated structures inside ICs are difficult to manually presume and are hence required to be determined by configuration simulation.
The configuration simulation is a technique for reproducing the configurations of fabricated semiconductor devices and interconnect lines in a simulative manner by providing information about masks used in IC wafer fabricating process steps and process conditions. The configuration simulation is performed using the above described process simulator. In the configuration simulation, a region to be analyzed is in many cases divided into minute regions referred to as cells for representation of the configuration thereof.
However, the configuration simulation technique using the cells is currently under study. Thus, if in particular a three-dimensional complicated structure is subjected to the configuration simulation, materials of metal parts, semiconductor substrate parts and the like which would be completely removed in an actual fabrication process are sometimes left unremoved as a result of the configuration simulation. This results from errors that occur because of the use of discrete configurations of the cells for calculation. Then, if the conductor regions provided by the configuration simulation are recognized simply as electrodes or interconnect lines, the subsequent simulation such as the capacitance simulation is performed under conditions different from those of the actual structure. In the case of the capacitance simulation, in particular, since the capacitance values are the physical quantities determined by the physical properties and arrangement of the conductor regions and a dielectric provided therebetween, the minute conductor regions created by the errors interfere with the increase in precision. A solution to such a problem has not yet been established.
USPTO Backgrounds
USPTO Backgrounds