1. Field of the Invention
The present invention relates to an interconnect having peripheral leads. The interconnect is particularly adapted for connecting a multi-chip module or a PCB to a circuit substrate such as a PCB to form a circuit assembly. The invention also relates to processes for making and using an interconnect having peripheral leads.
2. Brief Description of Prior Developments
Numerous interconnect devices are employed in electronic packaging for electronic devices. U.S. Pat. Nos. 5,558,271, 6,034,423, 6,041,495, and 6,071,754 illustrate many of these approaches such as the use of lead and tape frames, ball grid arrays, and flip-chip interconnects.
Pin and socket type interconnects for stacking modules are described in U.S. Pat. Nos. 5,460,531 and 5,613,033.
U.S. Pat. No. 5,069,626 discloses a semiconductor device package comprising a molded polymeric substrate having castellated leads. The interconnect of this electronic package does not connect a multi-chip module or a PCB to a circuit board. It is a component package providing an integrated circuit to board connection. In contrast in accordance with this invention a multi-chip device package or PCB is connected to a circuit substrate or PCB by a separate interconnect member having leads in peripheral depressions.
U.S. Pat. No. 5,247,423 discloses stackable multi-chip modules employing a plurality of edge metal conductors that form half-vias which provide a castellated appearance. Solder plated wires are fitted within the half-vias and reflowed to the conductor traces to interconnect the semiconductor devices of the modules. In contrast in accordance with this invention a multi-chip device package or PCB is connected to a circuit substrate by a separate interconnect member having leads in peripheral depressions.
USPTO Backgrounds
USPTO Backgrounds