A known problem in integrated circuit design is the need to provide protection from short high current electrical spikes caused by Electro-Static Discharge during handling. For example, such protection is needed in all Complimentary Metal-Oxide Semiconductor (CMOS) products. This protection may be provided by introduction of what is referred to as an Electro-Static Discharge (ESD) protection circuit on the input or output lines of a circuit to be protected. Example input or output lines include data, address or power lines leading into the circuit.
Specifically, for a given integrated circuit there is a critical voltage (V.sub.crit) level. If an input to the circuit exceeds the critical voltage level, physical breakdown of the circuit may occur. Such high voltage levels may be encountered for example during handling when no power is applied to the device. In these circumstances, the voltage on the input line must be limited so as not to exceed the critical voltage, and the associated current must be dissipated.
A further requirement in Electro-Static Discharge protection circuits, is that the protection circuit not adversely affect normal operations of the circuit to be protected. Accordingly, the protection circuit must for example not draw excessive current when no voltage spike is present, and not introduce any excessive capacitance or leakage.
In existing systems, diodes have been placed on input or output (I/O) lines of circuits to protect the circuits from voltage spikes. Such diodes have for example been placed between the input source and what is referred to as a "clamp" circuit. The clamp circuit is designed such that if it is connected to the input source directly, the voltage from the input source is limited to below the critical level for the circuit to be protected, and any current associated with excessive voltage is dissipated. In this type of protection circuit, a bipolar transistor may be used as the diode device. Where a bipolar transistor is used, the voltage operational characteristics of the device become more effective as the base and emitter resistance within the bipolar transistor is reduced. Specifically, the transistor will drop a lower voltage at the same current when this resistance is lower, thus lowering the voltage further below V.sub.crit and accordingly providing better protection of the circuit to be protected.
In existing systems for integrated circuit fabrication, protection circuits are formed using a vertical bipolar PNP transistor having base and emitter contacts arranged in alternating stripes on the surface of the device separated by field isolation regions provided by the underlying CMOS fabrication process. For example, shallow trench (STI) or LOCOS field isolation regions are commonly used for this purpose in existing systems. In a typical existing system each emitter stripe is arranged adjacent to two base contacts.
The bipolar transistors resulting from such existing fabrication systems exhibit several disadvantages. The base resistance relevant to performance of a bipolar transistor in general is known to be the sum of the intrinsic base resistance and the extrinsic base resistance. The extrinsic base resistance is the resistance of the base region between approximately the edge of the emitter region and the edge of the base contact. The extrinsic base resistance is accordingly a function of both the distance between the emitter and the base contact, and the resistivity (or doping level) of that region in the base.
In PNP bipolar transistors of protection circuits fabricated using existing systems, the distance between the emitter and the edge of the base contact is determined by the width of the standard field isolation region for the integrated circuit. The doping for the extrinsic base region is the standard N-well doping and other standard CMOS implants of the fabrication process.
The intrinsic base resistance of the bipolar transistor is the resistance of the base beneath the emitter stripe. The intrinsic base resistance is determined primarily by the ratio of area to perimeter in the surface geometry of the emitter stripe. Bipolar transistors in protection circuits fabricated using existing systems have emitter stripe widths that are determined by the spacing between field isolation regions. Such spacing results in an undesirably large ratio of surface area to perimeter in the emitter stripe. Further, the doping of the region beneath the emitter stripe is the standard N-well doping of the fabrication process, for example the N-well doping in a standard p-substrate CMOS fabrication process. Such existing systems fail to provide a base resistance sufficiently low for many applications without using a prohibitively large surface area for the emitter stripes.
For the reasons stated above there is required a new ESD protection circuit and fabrication process. The new protection circuit should include a bipolar transistor having a lower base resistance than is provided by existing fabrication systems. The new fabrication system should provide a new bipolar transistor in a protection circuit having lower extrinsic and intrinsic base resistance while using conventional fabrication process steps. Further, the new bipolar transistor in the protection circuit should advantageously use less geographic area than in existing protection circuits to accomplish the same functionality.
USPTO Backgrounds
USPTO Backgrounds