(a) Field of the Invention
The present invention relates to a master slice semiconductor integrated circuit (IC) and, more particularly, to a master slice semiconductor IC wherein a gate array or standard cells are formed on a silicon on insulator (SOI) substrate.
(b) Description of the Related Art
The application specific IC (generally referred to as ASIC) is increasingly used in the art. FIG. 1 shows a typical ASIC in a plan view wherein the CMOS SOG (a gate array) has a plurality of basic cells each implemented as a two-input NAND gate. FIGS. 2A and 2B are sectional views taken along E--E and F--F lines, respectively, in FIG. 1, and FIG. 3 is an equivalent circuit diagram for the basic cell in FIG. 1. Each basic cell 401 has an N-well contact region 402, P-well contact region 407, a pair of PMOS transistors 416a and 416b including P.sup.+ -diffused regions 403a, 403b and 403c and pMOS gate electrodes 405a and 405b, and a pair of nMOS transistors 417a and 417b including N.sup.+ -diffused regions 404a, 404b and 404c and nMOS gate electrodes 406a and 406b.
Source potential (Vdd) is applied to N-well contact region 402 and P.sup.+ -diffused regions 403a and 403c via source line 408 and contact hole. Ground potential is applied to P-well contact region 407 and N.sup.+ -diffused regions 404a via ground line 409 and contact hole 412. The common drain 403b of the pair of parallel pMOS transistors 416a and 416b having sources 403a and 403c connected to source lines is coupled via output line 411 to the drain 404c of one of serial nMOS transistors 417a and 417b, namely nMOS transistor 417b, having a source maintained at the ground potential. A pMOS gate electrode 495a is coupled to nMOS gate electrode 406a via input line 418, PMOS gate electrode 405b is coupled to nMOS gate electrode 406b via input line 419 to thereby constitute the two-input NAND gate. The basic cell in a conventional CMOS SOG is generally implemented as a two-input NAND gate in this manner or a two-input NOR gate. Input lines 418 and 419 are implemented by a first layer aluminum alloy film and connected to interconnects implemented by a second layer aluminum alloy film not shown in the drawings.
With the advance of CMOS ASIC technology to a higher speed and a higher integration, the basic cell as shown in FIG. 1 has been developed toward a finer pattern. In addition, a technique for reducing power consumption is especially required for the CMOS ASIC in view of the wide use of portable communication systems. This technology greatly increases the continuous use of portable communication systems that operate with a battery.
Power consumption P(watt) in the CMOS logic circuit is expressed in terms of operating frequency f(Hz), source voltage Vdd(volts) and load capacitance C(farad) as follows: EQU P=0.5.times.C.times.f.times.Vdd.sup.2 (1)
As understood from equation (1), the power consumption is proportional to a square of the source voltage, and reduction of power consumption is most effectively achieved by reduction of the source voltage. The reduction of the source voltage in an internal circuit can be achieved by a circuit configuration using a forward voltage drop of a diode as described in, for example, Patent Publication No. JP-A-01-246861. FIG. 4A shows a circuit arrangement in a plan view wherein the technique described in the publication is directed to the basic cell shown in FIG. 1. FIGS. 4B and 4C are circuit arrangements wherein the technique is applied to a source line and a ground line, respectively, for the basic cell.
In FIG. 4B, source voltage Vdd is applied, while reducing the same by a forward drop voltage of diode 502a, to CMOS inverter including pMOS transistor 516a and nMOS transistor 517a. Specifically, N.sup.+ -diffused region 504b and nMOS gate electrode 506a of a basic cell 501 are coupled to source line 508, and P-well contact region 521 is coupled to ground line 509, thereby implementing the diode 502a. Further, pMOS gate electrode 505f and nMOS gate electrode 506d of the adjacent basic cell are coupled by input line 510a, N-well contact region 520 is coupled to source line 508, P.sup.+ -diffused region 503i is coupled to N.sup.+ -diffused region 504a via line 527a, N.sup.+ -diffused region 504f is coupled to ground line 509, and P.sup.+ -diffused region 503h is coupled to N.sup.+ -diffused region 504e via output line 511a, thereby implementing a CMOS converter. The configuration that pMOS gate electrode 505e is coupled to source line 508 and nMOS gate 506c to ground line 509 prevents the channels underlying these gate electrodes from conducting, which might otherwise occur due to the potential of output line 511a.
Similarly, as shown in FIG. 4C, diode 502b implemented by a pMOS transistor and interposed between the CMOS inverter and ground line also reduces power consumption in the CMOS inverter. Specifically, P.sup.+ -diffused region 503a of a basic cell is coupled to pMOS gate electrode 505b thereof via ground line 509, and N-well contact region 520 is coupled to source line 508, thereby implementing diode 502b. Further, pMOS gate electrode 505c and nMOS gate electrode 506e of the adjacent basic cell are coupled together via input line 510b, P-well contact region 521 is coupled to ground line 509, P.sup.+ -diffused region 503c is coupled to N.sup.+ -diffused 504g region via line 527b, P.sup.+ -diffused region 503d is coupled to source line 508, P.sup.+ -diffused region 503e is coupled to N.sup.+ -diffused region 504h via output line 511b, and P.sup.+ -diffused region 503e is coupled to N+-diffused region 504h via output line 511b, thereby implementing a CMOS inverter. The configuration that pMOS gate electrode 505d is coupled to source line 508, and nMOS gate electrode 506f to ground line 509 prevents the channel regions underlying these gate electrodes conducting, which might otherwise occur due to the potential of output line 511b.
As described above, although a low power consumption can be realized in the CMOS basic cell formed on a bulk substrate, the CMOS basic cell used in this purpose also reduces the integration density of the ASIC due to use of the additional basic cell. In addition, the P-N junction between the source region of the nMOS transistor or pMOS transistor implementing the diode and the P-well or N-well, which is maintained at the ground potential or source potential for reverse biasing, can retard a high speed operation. In addition, the large parasitic capacitance requires a large charge/discharge current, which impedes the reduction of power consumption.
Another method for reduction of source voltage is to incorporate a devoted P-N junction into a basic cell. FIG. 5A shows such a configuration wherein a twin-well CMOS process is effected to a P-type bulk substrate to layout a mixture of a CMOS transistor and a diode having an anode or cathode which is neither maintained at a source potential nor ground potential in the substrate and coupled to the circuit by metallic lines. FIG. 5B is a circuit diagram wherein diode 602a is interposed between a source line and a CMOS inverter, FIG. 5C is a circuit diagram wherein diode 602b is interposed between ground line and a CMOS inverter, and FIGS. 6A and 6B are cross-sectional views taken along G--G and H--H lines, respectively.
FIGS. 6A and 6B show the diode formed in the N-well 622a adjacent to PMOS transistors and the diode formed in the P-well 623a adjacent to nMOS transistors, respectively. The diodes have cathodes implemented by N.sup.+ -diffused regions 604d and 604e in N-well 622b and 622d and anodes implemented by P.sup.+ -diffused regions 603d and 603e. The P-type silicon substrate is maintained at the ground potential.
In FIG. 6A, a pair of PMOS transistors are implemented by N-well contact region 620, P.sup.+ -diffused regions 603a, 603b and 603c, and pMOS gate electrodes 605a and 605b. N-well 622a for the pair of pMOS transistors is applied with source potential via source line 608, contact hole 612 and N-well contact region 620. P-well 623c is provided to separate N-well 622a from N-well 622b maintained at the same potential as the cathode of the diode.
In a current CMOS transistor process using a 0.5 .mu.m design rule in gate length, the width for P-well 623c is about 2 .mu.m at a minimum. It is also necessary to secure the distance between P-well 623c and the anode of the diode implemented by P.sup.+ -diffused region 603d at about 1 .mu.m and the distance between P-well 623c and N-well contact region 620 at about 1 .mu.m. Accordingly, the separation region for the diode should have width about 4 .mu.m around the diode, which reduces the integration density of the IC.
The diode shown in FIGS. 5a and 6a has cathodes implemented by N.sup.+ -diffused regions 604d and N-well 622b. The parasitic capacitance associated with the cathode is a sum of the P-N junction capacitances between the same and P.sup.+ -diffused region 603d constituting the anode, between the same and P-wells 623c and 623d, and between the same and P-substrate 613. The large parasitic capacitance of the cathode consumes a larger power during the potential change thereof compared to the source or drain region of the MOS transistor provided that the cathode and source or drain region occupy an identical amount of area.
In FIG. 6B, the pair of nMOS transistors are implemented by P-well contact region 621, N.sup.+ -diffused regions 604a, 604b and 604c, and nMOS gate electrodes 606a and 606b. P-well 623a for the pair of nMOS transistors is maintained at the ground potential by ground line 609, contact hole 612 and P-well contact region 621. In this case, a separating region similar to the separation region for the diode is provided for assuring the rectangular area for the basic cell arranged in a matrix, although the separating region is not required to have a constant width such as required for the separation region in FIG. 6A.
In addition, the parasitic capacitance associated with the cathode terminal in FIG. 6B is a sum of P-N junction capacitances between the same and P.sup.+ -diffused region 603e constituting the anode, between the same and P-well 623a, 623b and 623c and between the same and P-substrate 613, similarly to the case of FIG. 6A.
The large capacitance of the cathode terminal requires a larger power consumption during the potential change thereof compared to the case of source or drain region provided that the cathode and source or drain region occupy an identical amount of area. In short, the use of a diode basic cell for the CMOS basic cell is inferior to the use of CMOS basic cell itself in integration density, operational speed and power consumption.
USPTO Backgrounds
USPTO Backgrounds