The present invention relates generally to memory devices and, more particularly, to a method for programming and erasing memory devices.
Memory devices for non-volatile storage of information are in widespread use today. Some of the non-volatile memory devices function based on charge trapping. Examples of such charge-trapping devices are silicon-oxide-nitride-oxide-semiconductor (SONOS), and nitrided read only memory (NROM). Charge-trapping devices generally include a charge-trapping layer sandwiched between two oxide layers. The charge is stored in the charge-trapping layer and the data is recorded using the stored charge. The erase method for charge-trapping devices is much more difficult than floating gate devices because the electrons reside in the deep level trap causing electron de-trapping to be very slow.
FIG. 1 shows a SONOS structure. The figure includes a substrate 10, a source 12, and a drain 14. The SONOS structure further includes an oxide-nitride-oxide (ONO) film layers 16, 18, and 20 respectively, between the substrate 10 and the gate 22. The nitride layer 18 is used for trapping charge. The charge is injected to or rejected from the nitride layer 18.
SONOS is generally programmed and erased by direct tunneling. Tunneling is a quantum mechanical process where charge carriers acquire sufficient energy to tunnel through an oxide layer and get trapped in the nitride layer. However, in conventional SONOS devices, a thin tunnel oxide layer of about 20 Å is used to enhance the erase speed. In this type of structure, direct tunneling of holes is the major mechanism used for erasing. The direct tunneling of holes is used to compensate for the electrons. For SONOS, the erase state VT is negative due to this hole direct tunneling. But, the use of thin tunnel gate oxide suffers from poor retention properties due to charge leakages.
In order to prevent charge leakage NROMs have been used. Each of the NROM cell bits is programmed by channel hot electron injection. Channel hot electron injection involves applying a high voltage at the drain and the gate, which causes electrons to pass from the channel into the trapping layer. However, electrons cannot be removed from the trapped layer as the electrons are deeply embedded in the trapped layer. Therefore, the erase process involves hot-hole injection through the bottom oxide. The holes are generated by band-to-band tunneling, accelerated by a lateral field, and then injected through the bottom oxide to compensate for the electrons. However, hot hole injection requires a large junction bias and this is well-known to cause damage to the bottom oxide layer. The damage to the bottom layer is likely the cause of reliability problems such as high VT charge loss, low VT charge gain and read disturb.
In light of the foregoing, there is a need for a reliable and structured, programming and erasing method for charge-trapping memory devices.
USPTO Backgrounds
USPTO Backgrounds