1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device comprising a memory cell part having stacked capacitor cells and a peripheral circuit part comprising a logic circuit etc. which are mixed on a single substrate and a method of fabricating semiconductor device.
2. Description of the Background Art
In relation to a semiconductor device, particularly a dynamic RAM (DRAM), three-dimensionalization of memory cells has been attempted following the 4-M (mega) DRAM generation with development of improvement in integration and capacitance, in order to maintain soft error resistance and assurance of capacitance. Structures for such three-dimensionalization of memory cells have been wed out with development of the DRAM generation, and are now being intensified to stacked capacitor cells and trench capacitor cells.
Contrarily to the trench capacitor cells which are prepared by forming grooves in a silicon substrate for ensuring capacitances by depths thereof, stacked capacitor cells are prepared by forming capacitors on a silicon substrate in a stacked manner for ensuring capacitances by the heights thereof. Typical examples thereof are thick film stacked capacitor cells which have been employed since the 16-M DRAM generation, and cylindrical and fin capacitor cells which have been employed since the 64-M DRAM generation. Among these stacked capacitor cells, the structures of and fabrication steps for cylindrical capacitor cells are now described with reference to FIGS. 39A and 39B to 41A and 41B.
FIG. 39A is a partial sectional view showing a memory cell part (data holding part) of a DRAM, and FIG. 39B is a partial sectional view showing a peripheral circuit part of a logic circuit, a sense amplifier, a decoder etc. formed around the memory cell part of the DRAM.
First, description is made on the structure of the memory cell part before formation of aluminum wires with reference to FIG. 39A.
Referring to FIG. 39A, a P-type well region 3 is formed on a P-type silicon substrate 1. N-type source/drain regions 71, 72 and 73 are selectively formed in a surface of the P-type well region 3. In order to electrically isolate these N-type source/drain regions 71, 72 and 73 from other semiconductor regions, field oxide films 2 are selectively formed. A gate oxide film 5 is formed on the N-type source/drain regions 71, 72 and 73.
Gate electrodes 6 are formed over edge upper portions of the N-type source/drain regions 71 and 72 and those of the N-type source/drain regions 72 and 73 through the gate oxide film 5, while word lines 61 formed in the same step as the gate electrodes 6 are arranged on upper portions of the field oxide films 2.
On an upper portion of the P-type well region 3, an interlayer insulating film 11 is formed to cover the gate electrodes 6, the word lines 61 and the remaining structures. A bit line 13 is selectively formed on an upper portion of the interlayer insulating film 11, while a bit line contact hole 12 which is formed through the interlayer insulating film 11 and the gate oxide film 5 while having a buried layer 25 in its interior is provided between the bit line 13 and the N-type source/drain region 72, to electrically connect the same with each other.
Another interlayer insulating film 14 is formed on an upper portion of the interlayer insulating film 11. Storage nodes SN forming cylindrical capacitors are selectively formed on an upper portion of the interlayer insulating film 14. The storage nodes SN are formed by bottom surface films 16 serving as bottom portions and side surface films 17 formed around the bottom surface films 16 for serving as side wall portions. Between the bottom surface films 16 of the two storage nodes SN and the N-type source/drain regions 71 and 73, storage node contact holes 15 having buried layers 28 therein are formed through the interlayer insulating films 14 and 11 and the gate oxide film 5.
Surfaces of the storage nodes SN are covered with capacitor gate oxide films 18, while cell plate electrodes 19 are formed to further cover outer sides thereof. The cell plate electrodes 19 are formed to cover the storage nodes SN in response to the contour shapes thereof.
Still another interlayer insulating film 20 is formed on an upper portion of the interlayer insulating film 14, to cover the cell plate electrodes 19.
The structure of the peripheral circuit part before formation of aluminum wires is now described with reference to FIG. 39B.
Referring to FIG. 39B, P-type and N-type well regions 3 and 4 are formed on the P-type silicon substrate 1. N-type source/drain regions 74 and 75 are selectively formed in the surface of the P-type well region 3, and N.sup.+ -type source/drain regions 91 and 92 are selectively formed in these N-type source/drain regions 74 and 75. On the other hand, P.sup.+ -type source/drain regions 81 and 82 are selectively formed in a surface of the N-type well region 4. Field oxide films 2 are selectively formed in the surface of the N-type well region 4.
The gate oxide film 5 is formed on upper portions of the N-type source/drain regions 74 and 75, the N.sup.+ -type source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82.
Gate electrodes 6 are formed through the gate oxide film 5 over edge upper portions of the N.sup.+ -type source/drain regions 91 and 92 and those of the P.sup.+ -type source/drain regions 81 and 82, and side wall oxide films 10 are formed on both ends of the gate electrodes 6.
The interlayer insulating film 11 is formed on upper portions of the P-type and N-type well regions 3 and 4 to cover the gate electrodes 6 and the remaining structures, while the interlayer insulating films 14 and 20 are successively formed on the upper portion of the interlayer insulating film 11.
Generally in a DRAM which is improved in the degree of integration and capacitance, high resolution is required in photolithography and hence the focus margin is reduced as a tradeoff therefor.
If height difference in a pattern step portion is so increased following improvement in integration and capacitance that its magnitude exceeds the focus margin, therefore, it is extremely difficult to form wires by photolithography. Particularly in stacked capacitor cells formed by stacking capacitors on a silicon substrate, the height difference in the pattern step portions is remarkable.
Further, the wires are easy to disconnect if the height difference in the pattern step portion is increased, and it is necessary and indispensable to reduce the height difference to the minimum. In the DRAM described with reference to FIGS. 39A and 39B, therefore, the interlayer insulating films 11, 14 and 20 are flattened.
However, such flattening of the interlayer insulating films causes new problems in the structure and fabrication steps of the DRAM. These problems are now described with reference to FIGS. 40A, 40B, 41A and 41B showing steps of forming aluminum wires.
FIGS. 40A and 40B show a step of forming contact holes 21A and 21X for connecting the cell plate electrodes 19 of the memory cell part and the N.sup.+ -type source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82 of the peripheral circuit part described with reference to FIGS. 39A and 39B to aluminum wires.
On the other hand, FIGS. 41A and 41B show a step of forming aluminum wires 22 on upper portions of the interlayer insulating film 20 while simultaneously burying the aluminum wires 22 in the contact holes 21A and 21X as buried layers 27. Those buried as the buried layers 27 are not restricted to the aluminum wires 22, but may be prepared from any ones so far as the same are conductor layers of metals or the like.
Referring to FIG. 40A, the contact hole 21A is formed through the interlayer insulating film 20 to reach the cell plate electrode 19. Referring to FIG. 40B, the contact holes 21X are formed through the interlayer insulating films 20, 14 and 11 to reach the N.sup.+ -type source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82.
As clearly understood from FIGS. 40A and 40B, the height of the memory cell part is larger than that of the peripheral circuit part. This results from the fact that the memory cell part has the stacked capacitor cells.
Applicants determined that since the contact holes 21X in the peripheral circuit part must be formed deeper than the contact hole 21A in the memory cell part due to the height difference, inconvenience by overetching results from the difference between the depths of the contact holes 21A and 21X.
Applicants also determined that when formation of the contact holes 21A and 21X is simultaneously performed in the same etching step, and hence such a situation occurs that etching of the deeper ones (the contact holes 21X) is not completed even if that of the shallower one (the contact hole 21A) is completed, and the etching is continued resulting in the thickness of electrode 19 being reduced or an actual breaking of that electrode.
The second problem discovered by Applicants was the occurrence of inconvenience resulting from the fact that the aspect ratio of the contact hole 21X is extremely increased.
In general, barrier metal layers are formed on inner wall surfaces of contact holes in advance of burying of conductor layers in the contact holes, and hence the conductor layers are buried in holes having inner diameter dimensions obtained by subtracting the thicknesses of the barrier metal layers from the inner diameter dimensions of the contact holes. Considering this, it is only assumed that burying is difficult if the aspect ratio exceeds 5 in the present circumstances.
If the inner diameters of the contact holes 21X are so large that the thicknesses of the barrier metal layers are negligible or the depths of the contact holes 21X are small, therefore, it is not difficult to bury the aluminum wires 22 in the contact holes 21X. In practice, however, applicants found that the aspect ratio was so extremely increased that the conductor layers cannot be stably buried in process and the aluminum wires and diffusion layers cannot be electrically stably connected with each other.
USPTO Backgrounds
USPTO Backgrounds