The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
One advancement implemented to realize the smaller feature size is the use of multigate devices such as fin field effect transistor (finFET) devices. FinFETs are so called because a gate is formed on and around a “fin” that extends from the substrate. As the term is implemented in the present disclosure, a finFET device is any fin-based, multigate transistor. FinFET devices may allow for shrinking the gate width of device while providing a gate on the sides and/or top of the fin including the channel region. Another advancement implemented as technology nodes shrink, in some IC designs, has been the replacement of the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One method of forming the metal gate electrode is a “gate last” or “replacement gate” methodology where a dummy gate, typically polysilicon is replaced by a metal gate. Providing the metal gate later in the process can avoid problems of the stability of the work function metal during processing.
However, challenges in providing an appropriate stress and/or gate resistance in devices such as metal gate finFETs. For example, low stress on the gate and/or high gate resistance can cause a degradation of performance of device.
USPTO Backgrounds
USPTO Backgrounds