Integrated circuits being designed with increasing device density, with more and more complex circuit functions being crowded into the same device area. In order to accommodate the increasing density and increasing complexity of the circuit functions, the size of each individual device is being reduced. The reduction in device size implies a reduction in the dimensions of each individual device. As the gate length of an insulated gate field effect transistor decreases, serious device design problems are encountered. The most significant of these problems is the problem associated with hot carrier injection which results from the high electric fields encountered with the smaller geometry devices. The problem caused by the hot carrier injection is one of oxide damage where the term oxide damage refers to both the incorporation of fixed charges within the oxide and the increase in the density of interface states at the interface between the oxide and adjacent silicon or polycrystalline silicon material.
A number of attempts have been made to change the device design to overcome or lessen the hot carrier injection problem. Almost all of the existing solutions address the problem of hot carrier injection by attempting to reduce the lateral electric fields within the device in order to decrease the hot carrier generation rate. The most notable design change has been the introduction of the lightly doped drain (LDD) structure which was introduced to enhance the reliability of insulated gate field effect transistors (IGFET) while maintaining a 5 Volt power supply with gate lengths in the range of one micrometer. The LDD structure, and the numerous modifications of the LDD structure which have been proposed, have the goal of reducing the impact ionization rate by decreasing the electric field peak in the critical region where the device channel and drain region intersect. The various LDD structures have been successful in reducing the hot carrier injection problem in those devices for which it was designed. As device designs shrink even further to the submicrometer and even sub-half micrometer range, however, the LDD structure cannot provide sufficient protection against the problem. Even with scaling back of the power supply voltage to 3.3 Volts, the LDD structure is not adequate for the very short channel lengths which are desired and which are becoming increasingly necessary. An additional problem with the LDD structure is that the more lightly doped is the drain region, which serves to reduce the lateral electric field, the more serious is the increase in the series resistance of the current path through the drain region.
The LDD structure is a planar structure. To push the state-of-the-art in small devices beyond the planar LDD structure, a new type of elevated drain structure has been proposed for reducing hot carrier generation. The hot carrier suppression (HCS) structure differs markedly from the LDD type device in that a low doped (about 10.sup.16 cm.sup.-3) N.sup.- polycrystalline silicon layer is located above the conventional LDD N.sup.- drain region and is capped with a horizontal N.sup.+ layer. (In this and the following discussion, the superscript plus and minus signs are used in conventional manner to indicate relative doping concentration.) The HCS structure reduces the electric fields substantially and allows scaling of the IGFET down to the quarter micrometer range because of reduced charge sharing effects in the channel and reduced lateral dimensions of the source/drain regions. This source/drain construction, however, suffers from several structural drawbacks even beyond those of manufacturability issues. The highest fields and current densities in the HCS structure are located at or near the oxide corner which is formed at the oxide/silicon and the oxide/polycrystalline silicon interfaces. This means that the hot carriers which are generated are generated very close to the oxide interface and their high energy cannot be attenuated by scattering mechanisms within either the silicon or the polycrystalline silicon regions. Moreover, the quality of the oxide on the sidewall of the gate electrode is usually lower than that of the gate oxide, thus rendering the sidewall oxide interface highly vulnerable to hot carrier injection. In addition, any sidewall oxide damage can easily deplete the underlying adjacent N.sup.- layer and significantl affect the transistor performance by increasing the series on-resistance of the device.
Thus it is apparent that a need existed for an improved insulated gate field effect transistor (IGFET) which would provide relief from the effects of hot carrier injection and not, at the same time, cause other serious device design, manufacturability, or reliability problems.
USPTO Backgrounds
USPTO Backgrounds