Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a vertical transistor, and a method for forming the same.
A semiconductor memory device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges move between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region.
When a typical transistor is formed over a semiconductor substrate, a stack-type gate is formed on the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. In this case, a region between the source and the drain under the gate becomes a channel region of the transistor. The transistor including the horizontal channel region occupies a large-sized area of the semiconductor substrate. Accordingly, it is difficult to reduce the overall area of a complicated semiconductor device since semiconductor device includes a plurality of transistors.
A variety of methods have been proposed to reduce the overall area of the semiconductor device. A representative method uses a vertical transistor including a vertical channel region instead of a conventional planar transistor including a horizontal channel region.
USPTO Backgrounds
USPTO Backgrounds