1. Field of the Invention
This invention relates to Asynchronous Transfer Mode (ATM) switches, and in particular, to the implementation of flow control and isochrone traffic within ATM switching systems.
2. Description of Related Art
Asynchronous Transfer Mode (ATM), also known as "cell relay", is a telecommunications standards-based technology designed to meet the demand for the public network to simultaneously multiplex and switch data over a wide spectrum of data rates. These requirements are the result of emerging multimedia, high-speed data and imaging applications. ATM is a statistical multiplexing and switching method which is based on fast packet switching concepts, and is a radical departure from the circuit switching techniques that are used by today's digital switches. ATM provides dedicated circuits for voice, data, and video communications by dividing the information flow within each of these three types of traffic into individual "cells", each cell including an address or directions specifying the location to which the information carried within the cell should be delivered. Direction instructions are added to the information carried by the cell in the form of a label, which is processed by the ATM switch as the cell is routed through the switch.
Several factors drive the design of broad-band ATM switching architectures:
1. The need to accommodate a wide range of traffic types from voice to video to data;
2. The high speed at which the switch has to operate (from 155 Mb/s to over 1.2 Gb/s); and
3. The burst-like nature of data communications.
If communications networks continue to be deployed with large switches in central locations, then a large-scale ATM switch will be necessary. If such a switch is to serve 50,000 to 100,000 customers, each operating at the SONET STS-3 rate (155 Mb/s), then the total customer access capacity at the switch-customer interface is about 10 terabits per second (Tb/s) in each direction. If only one-in-ten customers use their assigned access capacity at any one time, then the core of this large-scale ATM switch must be capable of switching about 1 Tb/s of traffic, which is several orders of magnitude larger than the capacity of today's local digital switches.
Several high-performance packet switching fabrics have been proposed in the past. These switch fabrics can be categorized into different architectures--internal buffer, input buffer, output buffer, shared buffer, or various combinations of these. Internal-buffered switches include the buffered banyan network. With the assumption of having single-cell buffers at the intermediate stage, and a balanced and uniform traffic pattern, the banyan switch's maximum throughput is only about 45% of that required for large-scale ATM switches. Input-buffered architectures include Batcher-banyan networks with ring reservation, or a self-routing crossbar network with parallel, centralized contention resolution. Because of head-of-line (HOL) blocking, its maximum throughput is about 58% of that required. Certain techniques, such as allowing two cells of each input port to compete with others increases the maximum throughput of input-buffered architectures to approximately 70%.
The other types of ATM switch architectures each have their own advantages. Switches with output buffering, for example, have been proven to give the best delay/throughput performance in large-scale switch architectures. The shared buffer architectures have been shown to improve memory utilization significantly. Other switches in the prior art include those equipped with mixed input and output buffers, and a Sunshine switch implemented with both internal and output buffers. Besides point-to-point switches, several multicast ATM switches have also been proposed.
Each type of switch architecture has its own advantages and disadvantages. For example, the Batcher-banyan network has fewer switch elements than a crossbar network does, but it has more difficulty in synchronizing all signals in every stage because interconnection wires are not identical between stages, and the wire-length difference increases as the network grows. Conversely, the crossbar network has more uniform and regular interconnections, resulting in easier synchronization, but it has more switch elements.
All of the prior art switches, and most of the current research in the area of ATM switching, is oriented toward developing switchcores of greater magnitude and complexity in order to provide the switching capacity necessary for a large-scale central switch operating under its maximum projected traffic load. Networks utilizing a dozen or more ATM chips have been designed in such switches in order to provide the large buffers and multiple pathways necessary to ensure a high probability that a cell will pass through the switchcore. There is also a great need, however, for high quality ATM switches which are optimally designed for smaller relay nodes within various communications networks. None of the prior art ATM switch architectures, large or small, solve the capacity, throughput, and loss problems using access control, and none are capable of providing isochronal service.
USPTO Backgrounds
USPTO Backgrounds