Fusible links are employed in integrated circuits to create programmable elements. To reduce the number of processing steps needed to fabricate a programmable integrated circuit, the material used to make fuses often serves other purposes in the circuit. For example, U.S. Pat. No. 4,491,860 describes a programmable memory in which a patterned layer of titanium-tungsten nitride provides fusible links and also functions as a barrier metal between semiconductor material and another metal in the electrical interconnection system for the memory.
In U.S. Pat. No. 4,491,860, the starting point for defining a fusible link is a monocrystalline silicon semiconductor body having a dielectric layer along its upper surface. Several apertures extend through the dielectric layer down to the silicon. Thin metal silicide films lie along the silicon at the bottoms of some of the apertures.
A blanket layer of titanium-tungsten nitride (approximate formula TiW.sub.2 N) is deposited on the dielectric layer and into the apertures down to the silicon or metal silicide. The TiW.sub.2 N layer is patterned so as to leave a main portion of the titanium-tungsten nitride in an elongated lateral shape consisting of a pair of end sections and an intermediate section extending between the end sections. The intermediate TiW.sub.2 N section, which reaches a width much less than that of either end section, constitutes the fusible link. Other TiW.sub.2 N portions remain in the apertures having the metal silicide films.
A first electrical interconnect layer is created by depositing a blanket layer of aluminum on the upper surface of the structure and patterning the aluminum to remove selected parts, including all the aluminum on the TiW.sub.2 N fusible link. Aluminum remains on both TiW.sub.2 N sections at the ends of the fuse. Aluminum also remains on the TiW.sub.2 N portions in the apertures having the metal silicide films. The titanium-tungsten nitride in these apertures acts as a diffusion barrier to prevent the aluminum and silicon from intermixing.
A second dielectric layer is deposited on the upper surface of the structure. Apertures are then etched through the second dielectric layer down to selected parts of the patterned first aluminum. The basic interconnection system for the memory is completed by providing the structure with a patterned second aluminum layer that lies on the second dielectric layer and extends through the apertures in it down to the first aluminum.
To program the memory element containing the fuse, a suitable high voltage is applied between the TiW.sub.2 N sections at the ends of the fuse. This creates an open circuit by causing the fusible link to melt (at the narrowest cross-section).
One difficulty with using the same material for both the fuse and barrier metal, as in U.S. Pat. No. 4,491,860, is that the fuse and barrier metal have certain opposing requirements. The barrier metal effectiveness is compromised if the metal is too thin. On the other hand, the fuse blows easier when there is less metal to melt.
Given an acceptable minimum barrier metal thickness (e.g., 1,000 angstroms), one way of approaching the problem is to make the fuse quite narrow. That is, the "width" of the fuse in the lateral direction perpendicular to the current flow should be made small. However, with conventional photolithographic/etching equipment of reasonable cost, the minimum achievable width is approximately 1 micron with a fairly wide variation. This frequently results in a fuse resistance that is too low. Consequently, the programming yield is poor.
The fuse resistance can be controlled by performing an oxidation on the fuse after it has been photolithographically defined and etched. See published Japanese patent application 59-54240. The oxidation reduces both the width and thickness of the fuse, thereby increasing its resistance.
A disadvantage of the foregoing Japanese application is that a buffer metal is used between the fuse metal and the overlying interconnect layer. The buffer metal is patterned at the same time as the interconnect layer and then, after the oxidation, is etched further to reduce the lateral area. The use and further etching of the buffer metal increase the fabrication time and expense.
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