The invention relates to a solid state image sensor comprising static induction transistors (SITs) arranged in a matrix, each SIT having both a photoelectric converting function and a switching function for signal readout and forming a picture cell.
Such a solid state image sensor comprising a SIT matrix is known from Japanese Patent Laid Open No. 55-15229. FIG. 1 shows a sectional view of the static induction transistor forming a picture element in the known image sensor.
As shown in FIG. 1, the known SIT transistor has a vertical structure in which a drain region is formed by an n+ type substrate 1, a source region is formed by an n+ type region 3 provided in a surface of an n.sup.- type epitaxial layer 2 which is deposited on the substrate 1 and forms a channel region, and in the surface of the epitaxial layer 2 there is further provided a signal charge storage gate region 4 which surrounds the source region 3. On this gate region 4 there is provided an insulating film 5 on which is provided an electrode 6 to form a so-called MIS gate electrode having an electrode/insulating film/gate region structure. The doping concentration of the n.sup.- type epitaxial layer 2 forming the channel region is selected such that the channel region 2 is depleted and pinched off by a high potential barrier even when no bias voltage is applied on the gate electrode 6.
The principle of operation of such an SIT is as follows. In the condition where there is no biasing between the drain and the source of the SIT, when rays of light are incident on the channel and gate regions 2 and 4, electron-hole pairs are produced in these regions, the holes of the pairs are stored in the gate region 4, while the electrons are drained through the drain region 1 to the ground. The holes stored in the gate region by the incident light raise the potential of the gate region 4 and lower the potential barrier in the channel region 2 according to the incident light. When a bias voltage is applied between the drain and the source and a forward voltage is applied to the gate electrode 4, then a current flows through the source-drain path, which current depends on the amount of the holes stored in the gate region 4, whereby an amplified output is obtained for the optical input. The optical amplification factor .mu. of the SIT is usually 10.sup.3 or more and hence the sensitivity thereof is 10 or more times as high as that of a conventional bipolar transistor. The optical amplification factor .mu. is described as ##EQU1## where w is a distance between the gate and source regions, d.sub.1 is a depth of the gate region and d.sub.2 is a distance between the source and drain regions (which corresponds to the thickness of the n.sup.- epitaxial layer 2 when the N.sup.+ source region 3 is very thin). As apparent from this formula, in order to obtain a much higher optical amplification factor .mu. the distance w must be made small while the thickness of the epitaxial layer 2 and the depth of the gate region 4 must be made large. For example, in order to obtain the amplification factor .mu. of 10.sup.3 -10.sup.4, in usual d.sub.2 =5-6 .mu.m and d.sub.1 =2-3 .mu.m are required. In the image sensor it is further necessary to provide an isolation region 7 between the SITs in order to isolate the signal charges stored in the respective SITs. In general, the isolation region may be formed by means of local oxidation, diffusion or V-shaped groove formation, etc. so as to extend through the epitaxial layer 2 from the surface thereof to the substrate. Thus, if the epitaxial layer 2 has a large thickness the formation of the isolation region becomes difficult. Further, the formation of deep gate region 4 by means of diffusion etc. which improves the optical amplification factor has a limitation. Moreover, the deep gate region strongly absorbs the incident light rays and thus the spectral sensitivity is deteriorated. Accordingly, the solid state image sensor comprising vertical SITs has a limitation in the improvement of its sensitivity because of its structure as described above.
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