In recent years, a CMOS image sensor has attracted attention as a solid-state imaging element (image sensor) that is an alternative to a CCD. This is for the following reasons.
A dedicated process is necessary to fabricate a CCD pixel. A plurality of power supply voltages are necessary for operation of the CCD pixel, and a plurality of peripheral ICs need to be combined and operated.
On the other hand, a CMOS image sensor overcomes a problem of a very complicated system in such a CCD.
The same fabrication process as for a typical CMOS integrated circuit can be used to fabricate the CMOS image sensor, which can be driven by a single power supply, and also both an analog circuit and a logic circuit using a CMOS process are incorporated in the same chip.
Thereby, the CMOS image sensor has great merits of the number of peripheral ICs being reduced.
An output circuit for the CCD is mainly a 1-channel (ch) output using a floating diffusion (FD) amplifier with an FD layer.
On the other hand, the CMOS image sensor has an FD amplifier for each pixel, and an output of the CMOS image sensor is mainly a column-parallel output in which any one row in a pixel array is selected and pixels on the row are simultaneously read in a column direction.
This is because it is difficult to obtain sufficient driving capability from an FD amplifier arranged in the pixel and accordingly a data rate needs to be lowered and parallel processing is advantageous.
Here, in such a solid-state imaging element, a unit cell size of a pixel becomes smaller with multiple pixels and miniaturization.
Accordingly, in the solid-state imaging element, a percentage of an area of a transistor in the pixel increases and an area of a photodiode (PD) becomes small, such that a saturation charge amount and sensitivity are degraded and image quality is deteriorated.
Further, high-speed reading in a number of pixels, such as 30 fps realization in an HD mode, is necessary.
Thereby, in a solid-state imaging element including pixels having a small unit cell size, methods of adding some pixel signals in an analog or digital manner for enhancement of sensitivity and S/N or high-speed reading have been proposed.
One method is a method in which an FD is shared among a plurality of pixels and charges obtained through photoelectrical conversion in each pixel are added at the FD.
However, if the FD is formed to add the same color pixels while a unit cell size of the pixel is being reduced, the PD area is further reduced, leading to degradation of a saturation charge amount and sensitivity and deterioration of image quality.
Another addition method is a method of performing conversion into a digital signal and then addition in a solid-state imaging element with an analog digital (AD) converter.
In an all-pixel mode, one AD conversion is performed in a certain period. However, when digital addition is performed to realize high speed, a plurality of AD conversions are necessary in the certain period, and there are issues of a need for fast AD conversion and generation of noise due to the fast AD conversion.
A source follower addition in which a load MOS circuit connected to a read signal line performs addition is known as a method capable of avoiding issues caused by the FD addition and the digital addition and realizing enhancement of sensitivity and S/N and high speed (e.g., see Patent Literature 1).
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