The present invention relates to a device for reading a two-dimensional charge image such as is disclosed, for instance, in U.S. Pat. No. 4,592,029.
In this publication, a device for reading a two-dimensional charge image is disclosed which contains an array of electrodes which are arranged on the narrow sides of stacked circuit boards. Always one of the flat sides of the circuit board is provided with a recess extending parallel to the narrow sides. The recess serves to make room for the electronic components located on the board adjacently in the stack. The electrodes arranged one behind the other in the lengthwise direction on the narrow side of a circuit board are connected via connecting conductors of approximately equal length to switchable amplifiers which are likewise arranged one behind the other in the longitudinal direction. The electrodes belonging to a circuit board form the rows of a matrix on the stack. As switchable amplifiers, dual-gate MOS-FETs are provided, the input of which is additionally protected by a leak resistor arranged on the circuit board. The amplifiers located on a circuit board belong to an image row of the matrix. The outputs of these amplifiers are connected to a common output line. The control inputs of the amplifiers are each connected to main control lines which are arranged on the narrow side of the circuit board opposite the electrodes in the direction of the columns of the matrix. The amplifiers belonging to a column of the matrix are associated here with a common main control line. The charge image generated on the electrode matrix can thereby be read out column by column. In order to obtain high local resolution, the thickness of the circuit board as well as the raster pitch for the electrode is limited to values which are smaller than 1 mm. Since only little space is available for the electronic components regarding the overall height due to the limited depth of the recesses milled into the circuit board, the circuit boards are made by a standard hybrid technique. The passive components, for instance, the leak resistor, are applied to the circuit board of aluminum oxide Al.sub.2 O.sub.3 by a thin-film technique and the switchable dual-gate MOS-FETs are cemented and wire bonded as semiconductor chips on the circuit board.
This known arrangement, however, has the disadvantage that it can be ascertained only after a circuit board is assembled and the bond connections are made whether a component, for instance, the dual-gate MOS-FET, is defective. If this is the case, the entire assembled circuit board is useless. Since such a circuit board can contain up to 200 amplifier chips, a low yield can be expected in production. A defect rate in bonding the individual chips of, for instance, only 1% would lead to the situation that of about eight circuit boards only one is usable on the average. In addition, the entire circuit board must be replaced if a defect occurs in operation, for instance, by mechanical damage to an electrode.
USPTO Backgrounds
USPTO Backgrounds