The present invention relates to a flash memory device, and more particularly to a control circuit of a flash memory having a data area and a file allocation table (FAT) area, and a method of operating the flash memory device.
In flash memory devices, an erase/write (E/W) cycling characteristic is an important factor in reliability. The E/W cycling characteristic is used in determining a physical limitation in the number of erase operations and program operations of a flash memory device. This physical limitation is further increased with higher densities of a flash memory device. Recently, a multi-level cell (MLC) technology has been proposed. In the MLC technology, a cell state is divided into more than two states and 2 or more bits of data can be stored in a single cell. However, as the MLC technology is applied to the flash memory devices, the limitation in the E/W cycles becomes more serious.
The localized E/W cycling stress can be reduced by appropriately allocating locations where data are to be written. That is, if data are sequentially written, the E/W cycling stress is concentrated on a previous block. The E/W cycling stress at a specific location can be reduced by writing data at several locations in a uniform manner. This method can reduce the concentration of the E/W stress at the specific block. Hence, the E/W cycling limitation problem that most blocks encounter can be solved to some degree.
The above-described method is effective in the data area but ineffective in the FAT area. The data area refers to a memory area where data are stored, and the FAT area refers to a memory area where information such as location of data within the data area are stored. Therefore, an erase operation is performed on the data area only when new data are written. On the other hand, a data update operation must be performed on the FAT area whenever a data state in the data area is changed. Therefore, the FAT area is more vulnerable to the E/W cycling stress than the data area.
The vulnerability to the E/W cycling stress in the FAT area becomes more serious when operation schemes are different. In the flash memory device, a program operation is performed on a page basis, while an erase operation is performed on a block basis. A plurality of pages define one block. In the data area, an erased state is indicated by “1”, which means that a current flows because the erased state has a negative threshold voltage. A programmed state is indicated by “0”, which means that no current flows because the programmed state has a positive threshold voltage. That is, the state of “1” represents that no data is written. Therefore, in the case of the data area, an additional program has only to be performed on a page basis whenever new data are added. On the other hand, the convention for the FAT area is opposite to that of the data area because of compatibility with other systems, e.g., an operating system. That is, an erased state is indicated by “0” and the programmed state is indicated by “1”. Therefore, when some data are added, an erase operation is performed to change some regions of the FAT area from the “0” state to the “1” state. However, since the erase operation is performed on a block basis, it is impossible to perform the erase operation on only the needed regions. That is, the erase operation is performed over the FAT area and the program operation is then performed to update data.
For these reasons, the E/W cycling characteristic tends to be more important in the FAT area than in the data area. As illustrated in FIG. 1, as the E/W cycling stress increases, an amount of a current flowing within cells gradually decreases. More specifically, when all cells in FIG. 1 are programmed, a drain current level in a fresh state 110 is sufficiently higher than a sensing level 100, but a state 120 after the cycling is so low that it is close to the sensing level 100. Even though unit cells are alternately programmed, a drain current level in a fresh state 130 is sufficiently higher than the sensing level 100, but a state 140 after the cycling is so low that the gap from the sensing level 100 is reduced. Generally, a smallest amount of cell current flows when all cells are programmed. As illustrated in FIG. 1, an over-program problem may be caused when a current level becomes lower than the sensing level of the page buffer due to the E/W cycling stress.
USPTO Backgrounds
USPTO Backgrounds