1. Field of the Invention
The present invention relates to a testing device. More particularly, the present invention relates to a testing device that tests an electronic device.
2. Description of Related Art
Conventionally, a testing device that performs a match detection task detecting a correspondence between an output signal from an electronic device and an expected value is known as disclosed, for example, in Japanese Patent Laid-Open No. 1995-73700, particularly pages 2 and 3, and FIGS. 1 to 4 thereof. The testing device detects, e.g., a completion of writing and erasing of a flash memory by the match detection task.
In the testing device, a pattern generator generating a test pattern uses an instruction pipeline that sequentially prefetches and processes instruction codes. The pattern generator outputs the test pattern based on an output of the instruction pipeline.
However, for example, when changing the test pattern according to the result of the match detection mask, it is necessary to destroy an instruction stream stored in the instruction pipeline to generate a new instruction stream, in some cases. In this case, since the instruction pipeline is repacked in order to generate a new instruction stream, there has been a problem that testing time increases.
Here, in order for a pattern generator to adequately output a test pattern varying at high speed, for example, an instruction pipeline having the number of stages of about 100 stages is used in some cases. In this case, repacking the instruction pipeline needs, e.g., time of about several milliseconds or more. Moreover, since a match test is frequently used, e.g., in case of testing a flash memory, etc., a test cost increases due to time required for repacking the instruction pipeline.
USPTO Backgrounds
USPTO Backgrounds