1. Field of the Invention
This disclosure relates to a method of fabricating an integrated circuit device, and more particularly, to a method of fabricating a recess transistor in an integrated circuit device and a recess transistor in an integrated circuit device fabricated by the same.
2. Description of the Related Art
As integrated circuit devices become highly integrated and the length of channels of MOS transistors shortens, punch-through errors may occur between a source and a drain in a flat-type transistor. Thus, a shortened channel in the MOS transistors causes the integrated circuits to malfunction. As a result, recess transistors have been developed to increase a channel length.
FIG. 1 is a plan diagram illustrating an active region pattern (A/P) and a gate pattern (G) for a unit cell in a conventional recess transistor. FIGS. 2A through 2C are cross-sectional diagrams illustrating the conventional recess transistor of FIG. 1. FIGS. 2A, 2B, and 2C are taken along the lines A-A′, B-B′, and C-C′ of FIG. 1, respectively.
Referring to FIG. 2A, a gate trench (90) is formed in an active region, which is defined by a shallow trench isolation (STI) (40a). Here, a recess transistor includes a recess gate (98) buried in the gate trench (90) and source/drain regions (50) formed at the both sides of the recess gate (98). In the conventional recess transistor, a channel is formed along the circumference of the trench (90), as shown in FIG. 2A. Accordingly, the channel length (Chc) of the recess transistor is larger than the channel length (Chp) of a conventional flat-type transistor, which is formed on a silicon substrate (10) in parallel. Accordingly, the generation of punch-through errors between the source region and the drain region is minimized.
However, when the recess transistor is formed by a conventional method, the STI (40a) and the gate trench (90) are not formed with completely vertical sidewalls but are inclined due to the limits of dry etching for forming the STI (40a) and the gate trench (90), as shown in FIG. 2C. Accordingly, portions of the silicon substrate (10) remain between the sidewalls of the STI (40a) and the sidewalls of the gate trench (90) as shown in the dotted circles of FIG. 2C. When the portions of the silicon substrate (10) remain at the lower parts of the source/drain regions (50), the channel length (Chc) of the recess transistor at the central portion of the active region, which will be referred to as TRc hereafter, and the channel length (Che) of the recess transistor at the edges of the active region, which will be referred to as TRe hereafter, become different, as shown in FIGS. 2A and 2B, respectively. In other words, the channel length (Che) of TRe shown in FIG. 2B becomes shorter than the channel length (Chc) of TRc shown in FIG. 2A. When the channel length is reduced, the threshold voltage of the transistor is reduced so that subthreshold leakage current in TRe increases. Moreover, when the silicon substrate (10) remains in the source/drain regions (50), shorts may occur between the source region and the drain region. Accordingly, an improved recess transistor is required.
Embodiments of the invention address these and other disadvantages of the conventional art.
USPTO Backgrounds
USPTO Backgrounds