1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a method for driving the same.
2. Related Art
A conventional semiconductor memory apparatus includes a DLL (Delay Locked Loop) clock control unit 10, a DLL clock generating unit 20, and a synchronizing unit 30, as shown in FIG. 1.
The DLL clock control unit 10 generates a control signal “ctrl” in response to an idle signal “idle,” a power down exit mode signal “SPPD_A12,” and a clock enable signal “CKE.” When the clock enable signal “CKE” is disabled, the semiconductor memory apparatus enters a power down mode. The idle signal idle is an internal precharge signal that is enabled a predetermined time after the semiconductor memory apparatus enters the power down mode. The type of power down exit mode is determined according to whether the power down exit mode signal “SPPD_A12” is enabled or not. For example, when the power down exit mode signal “SPPD_A12” is enabled, the semiconductor memory apparatus operates in a slow power down exit mode. Alternatively, when the power down exit mode signal “SPPD_A12” is disabled, the semiconductor memory apparatus operates in a fast power down exit mode.
The clock enable signal “CKE” is disabled when the power down exit mode signal “SPPD_A12” is enabled. That is, if the semiconductor memory apparatus enters the slow power down exit mode, the DLL clock control unit 10 disables the control signal “ctrl” when the idle signal “idle” is enabled.
When the control signal “ctrl” is enabled, the DLL clock generating unit 20 generates a DLL clock “DLL_CLK” in response to a clock signal “CLK.” When the control signal “ctrl” is disabled, the DLL clock generating unit 20 stops generation of the DLL clock “DLL_CLK.”
The synchronizing unit 30 synchronizes an external ODT (on-die termination) signal “ODT_ext” with the DLL clock signal “DLL_CLK,” and outputs it as an internal ODT signal “ODT_int.” In this case, the external ODT signal “ODT_ext” is input from outside the semiconductor memory apparatus. The internal ODT signal “ODT_int” is output by synchronizing the external ODT signal “ODT_ext” with the DLL clock signal “DLL_CLK” and then used in the semiconductor memory apparatus. During an enable period of the internal ODT signal “ODT_int,” the semiconductor memory apparatus performs a termination operation.
When the clock enable signal “CKE” is disabled, the semiconductor memory apparatus enters a power down mode. When the power down exit mode signal “SPPD_A12” is enabled, the semiconductor memory apparatus enters a slow power down exit mode, which is one type of power down exit mode. After a predetermined time from the disabling of the clock enable signal “CKE,” the idle signal “idle” is enabled at a high level. The external ODT signal “ODT_ext” is input to the semiconductor memory apparatus after the clock enable signal “CKE” is disabled. The control signal “ctrl” is disabled when the idle signal “idle” is enabled. The internal ODT signal “ODT_int” is enabled at a high level after two cycles of the DLL clock signal “DLL_CLK.”
Since the enable timing of the internal ODT signal “ODT_int” is later than the enable timing of the external ODT signal “ODT_ext” by two cycles of DLL clock signal “DLL_CLK,” as illustrated in FIG. 2, the disable timing of the internal ODT signal “ODT_int” should be later than the disable timing of the external ODT signal “ODT_ext” by the two cycles of the DLL clock signal “DLL_CLK.” However, the control signal “ctrl” is disabled at the enable timing of the idle signal “idle,” and the transition of the DLL clock signal “DLL_CLK” is stopped. In this case, since the transition of the DLL clock signal “DLL_CLK” is stopped, the internal ODT signal “ODT_int” is not disabled. Accordingly, in the general semiconductor memory apparatus, a sufficient margin is required between the disable timing of the external ODT signal “ODT_ext” input from outside of semiconductor memory apparatus during the slow power down exit mode and the enable timing of the idle signal “idle.”
As such, in the general semiconductor memory apparatus, when a sufficient margin is not maintained between the disable timing of the external ODT signal “ODT_ext” input during the slow power down exit mode and the enable timing of the idle signal “idle, the internal ODT signal “ODT_int” is not disabled.
USPTO Backgrounds
USPTO Backgrounds