In many embedded designs, the Joint Test Action Group (JTAG, IEEE 1149.1) interface on a device or system provides access to test and debug capabilities on, for example, a processor. This interface conforms to the IEEE 1149.1 Test Access Port (TAP) protocol and requirements. Systems-on-a-chip designs often have multiple cores, each of which has their own TAP. When multiple processors are present in a system, the TAP of each processor could be connected in series or dynamically managed by a TAP linking module. When a TAP linking module exists on a device, debug software, executing on a host, programmatically selects which TAPs are to be connected in series and visible between the JTAG input and output pins (test data in (TDI) and test data out (TDO)).
Usually, the selection of which secondary TAPs are linked together to form the scan path between the system's TDI and TDO pins is explicitly specified and programmed by the host debug system. When a TAP is added to the master scan path, the length of the scan path between the TDI and TDO will increase due to the inclusion of the scan bits in the newly added TAP. Because the host has programmed the selection of the newly added TAP, the host knows that the overall scan path length has changed. In this fashion, the host always knows the overall length of the scan path between the TDI and TDO pins and the location of the serial scan chain of each selected TAP.
There are circumstances, however, in which the TAP linking module must deselect and unlink a secondary TAP without being explicitly instructed to do so by command from the host. For example, if power is turned off to one of the secondary TAPs that is currently included in the master scan path, the serial scan chain between the device's TDI and TDO pins would be broken. Scan to any and all TAPs in the system would be broken because shift cannot occur through the shift registers in the now unpowered TAP. Another reason for spontaneously and abruptly, removing a secondary TAP from the master scan path is due to a change in scan access rights to a TAP. In order to protect confidential information being processed on an embedded device, some devices are equipped with security features to block viewing of some data. This requirement conflicts with the debug features provided on the JTAG interface that seeks to provide complete system visibility. A security module on the device may be programmed to prohibit all scan access to a TAP in the system. If this TAP is currently selected as part of the mater scan path, the TAP linking module must enforce the restricted scan access rights by deselecting the secondary TAP.
Ideally, the power and security settings for a secondary TAP should not change while the debug software has included the secondary TAP in the scan chain. However, system design considerations do not always make this possible. At times, the TAP linking module may be required to automatically disconnect from a secondary TAP. The disconnect can occur at any point in time, even while a scan operation is occurring. When the TAP linking module must make a change to the scan path that was not programmed by the host, the host's debug software will not know that the overall scan path length has changed. Furthermore, because one or more TAPs was eliminated from the serial scan path, the position of the remaining TAPs has changed. The length of the scan data generated by the debug software does not match the scan chain length. Since the host debug system is not aware of this change in position, it will incorrect apply scan bits to the wrong place and even the wrong TAP in the system. System behavior will be unpredictable and potentially harmful.
USPTO Backgrounds
USPTO Backgrounds