Field
Embodiments of the present invention generally relate to methods for selectively etching a silicon material disposed on a substrate for semiconductor manufacturing applications.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions and beyond, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, multiple materials in the semiconductor structures are often utilized to form high-density of transistor devices.
When forming these features, such interconnection structures in a film stack disposed on a substrate, an etch process using a photoresist layer as an etching mask is often utilized. Typically, conventional etchants have low selectivity to etch one material over another material present in the structure, such as gate dielectric, gate electrode and/or underlying materials in a gate structure, thereby leaving void space, also known as silicon recess, foot, or other associated defects on the interface of different materials. Low selectivity of the etchants between different materials often result in etching profile deformation, specifically forming defects on sidewalls, corners, or bottom the substrate surface which may deteriorate device performance and electrical properties of the device structure.
Thus, the etch selectivity for polysilicon and silicon materials to other silicon containing compounds, such as silicon oxide, silicon carbide or silicon nitride, in the device structure should be very high in order to protect or passivate the sidewall, features or the surface of the device structure.
Thus, there is a need for improved methods for etching a silicon material with high selectivity for semiconductor chip manufacturing applications and other semiconductor devices.
USPTO Backgrounds
USPTO Backgrounds