The present invention relates to a correlating device for calculating the correlation between an analog input signal and binary-code sequence with respect to time, which is suitable for use, for example, as a correlating device for synchronizing an input signal and a binary-code sequence, or a correlating device for demodulating spread data into the original form, for example, in spread spectrum communications.
As a correlating device, for example, one can use switched capacitor circuit as in FIG. 16, which directly calculates an analog signal Aout indicative of the correlation between an analog input signal Vin and a binary-code sequence a(i) with respect to time without converting the analog input signal into digital.
In such a correlating device, however, in order to prevent saturation before the calculation of the correlation completes, as the length of binary-code sequence becomes longer, it is required to increase the capacitance of an integration capacitor C101, that in turn increases the amount of parasitic capacitance. The presence of these parasitics translate into large power consumption in order to achieve the desired speed of operation.
Furthermore, in a general spread spectrum communication receiver, the functional blocks, such as path searcher, tracking controller or rake receiver, which follow the correlating device 101 are usually implemented by digital circuits. In this case, the output signal Aout of correlating device 101 has to be converted to a digital value before it is passed to those digital circuits. This conversion requires separate AD converter(s) and hence further increase of power consumption.
It is an object of the present invention to realize a correlating device capable of operating at low power consumption even at high operating speeds and for long binary-code sequences, that gives its output in digital form without using separate AD converters.
In order to achieve the above object, a correlator for calculating a correlation value between an analog input signal and a code sequence with respect to time, is characterized by a multiplier that multiplies a sampled analog input signal by a code from the code sequence; an analog integrator; a quantization circuit that quantizes an integrated value from the analog integrator; a digital accumulator that accumulates digital values outputted by the quantization circuit, and outputs a result of accumulation as the correlation value; and a negative feedback circuit that converts the digital value outputted by the quantization circuit to an analog value of inverse polarity; wherein the analog integrator integrates a sum of a negative feedback signal outputted by the negative feedback circuit and an output from the multiplier.
With this arrangement, the quantization circuit and the negative feedback circuit form a negative feedback loop, and therefore, compared with the case without a negative feedback loop, the absolute value of the integrated value of the analog integrator is reduced. Therefore, even when the length of code sequence becomes longer, it is possible to prevent the saturation of the integrated analog output without increasing the size of integrator capacitor which stores the integrated value, thereby realizing a correlator of small power consumption.
Furthermore, upon completing a computation with respect to all the values of the code sequence, the digital output of the digital accumulator indicates a correlation value between the analog input signal and the code sequence with respect to time. Thus, unlike the conventional arrangement wherein the correlation value of the analog signal integrator is subjected to AD conversion, it is possible to output a digital value indicative of a correlation value without providing an AD converter as a the second stage of the correlator.
Here, as in the conventional arrangement, in the case of converting the correlation value which is once output in a analog value and then converted into a digital value, as the maximum analog value is a product of the number of quantization levels and the quantization interval, it is difficult to increase the number of quantization levels, and thus a calculation with an improved precision is difficult to be achieved. Furthermore, another problem may arise due to limitations of the conversion rate of low-power AD converters, unless complex structures are used.
In contrast, the number of quantization levels L which can be outputted by the correlator according to the present invention is (Nxe2x88x921)xc2x7M+1 wherein N is the number of quantization levels of the quantization circuit and M is a length of the code sequence. Therefore, without increasing the number of quantization levels of the quantization circuit, the number of quantization levels L of the correlator increases as the code sequence becomes longer.
As a result, it is possible to reduce the number of quantization levels N of the quantization circuit (for example, two or three quantization levels) to be smaller than the number of quantization levels L of the correlator (for example, 64 to 256), thus outputting a high precision correlation value with a simple circuit structure.
Incidentally, the maximum quantization error of the correlator having the above arrangement is determined by the maximum quantization error of the quantization circuit, and thus a small maximum quantization error of the correlator can be achieved which is less than twice as much as the maximum quantization error of the quantization circuit even when initialization is not performed.
In order to achieve a high precision correlation calculation, it is preferable that initializing means be provided, which, at the beginning of each cycle of the code sequence, adjust at least one of the integrated value of the analog integrator and a value indicated by an output of the quantization circuit, so that the integrated value and the value indicated by the output are equal.
With this arrangement, the integrated value of the analog signal integrator and the quantized value indicated by the output of the quantization circuit before computation of a correlation value starts coincide with each other. Thus, compared with the case where these values are different, the maximum quantization error can be reduced by half and a computation can be performed with a still improved precision.
The arrangement of the initialization is made by means of CDS (Correlated Double Sampling) operation, that sets a predetermined value of the output of the analog integrator and at the same time suppresses the low-frequency noise, thereby increasing the accuracy of the computation.
It may be also arranged so as to further include measuring means, which, prior to correlation computation, measure offset error of the correlator; and offset compensation means, which adjust a result of computation by the correlator, so that the offset error can be cancelled based on the offset error as measured, for example, by subtracting the offset error from the correlation value computed by the correlator, or adjusting beforehand the initial value of the digital accumulator according to the offset error.
With this arrangement, a natural offset error of the correlator in use can be cancelled, and thus a computation can be performed with an improved precision.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds