1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to an MOS transistor having shallow junction. The present invention relates also to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIGS. 13-16 are cross sections showing the steps of manufacturing a conventional field effect transistor (MOSFET).
Referring to FIG. 13, a gate insulating film 51 is formed on a semiconductor substrate 50. A polysilicon film 52 is formed on gate insulating film 51. Polysilicon film 52 and gate insulating film 51 are patterned to a shape of a gate electrode 53.
Referring to FIG. 15, impurity ions are implanted into a surface of semiconductor substrate 50 on both sides of gate electrode 53, and a pair of source/drain regions 54 are formed. An interlayer insulating film 55 is formed on semiconductor substrate 50 to cover gate electrode 53. A contact hole 56 for exposing a portion of a surface of source/drain layer 54 is formed in interlayer insulating film 55. An Al electrode 57, i.e. a source/drain electrode is formed, which is connected through contact hole 56 to the source/drain layer.
The conventional MOSFET is produced in such a manner as described above. With miniaturization of a device, shallow junction has been required. The shallow junction means that, referring to FIG. 17, distance between a top surface 54a and a bottom surface 54b of source/drain region 54 is short. If junction is deep, as shown by dotted line 57 and chain dotted line 58, distance between the pair of source/drain regions 54 and 54 becomes short under gate electrode 53, which might cause punch through. Shallow junction has been required in order to prevent such punch through.
In order to form shallow junction, channeling (deep entrance of impurity ions) and diffusion of impurity ions in a substrate must be suppressed. Consequently, pre-ion-implantation in which nitride, silicon, germanium or the like is implanted into a surface of a substrate before implantation of electrically active impurity ions has been proposed.
FIGS. 18-21 are cross sections showing the steps of conventional pre-ion-implantation.
Referring to FIG. 18, a silicon substrate 11 which is formed of single crystal is prepared. Although a gate electrode has been formed already by this time, it is not shown in the figure.
Referring to FIG. 19, atoms of nitrogen, silicon, germanium or the like are implanted into a surface of silicon substrate 11, and an amorphous layer 12 is formed. Implantation of atoms 59 of silicon, nitrogen, germanium or the like causes crystal lattice disorder resulting in amorphous layer 12 formed at the surface of silicon substrate 11. Amorphous layer 12 is formed when the above-described atoms are implanted by more than a critical amount (an amount at which amorphous is formed). Then, electrically active impurity (arsenic or phosphorus in the case of n-type, and boron in the case of p-type) is implanted into amorphous layer 12 at high concentration (at least 1.times.e.sup.15 /cm.sup.2), and source/drain region 54 is formed. Pre-ion-implantation can suppress channeling and diffusion in the substrate. That is because disorder of the crystal lattice causes electrically active impurity ions to collide with the crystal lattice, which results in suppression of diffusion thereof, and because an amorphous layer has no path for atoms to spread into silicon at the time of thermal processing.
Referring to FIG. 20, thermal processing is performed at a temperature in the range of 600.degree. to 900.degree. C.
Thus, referring to FIGS. 20 and 21, solid phase epitaxial growth in which a monocrystal lattice serves as a nucleus takes place from a crystal surface of silicon substrate 11 in the direction of arrows, and a monocrystalline layer 16 in the substrate is formed.
At this time, a secondary-defect layer 15 which extends horizontally is formed between silicon substrate 11 and monocrystalline layer 16 in the substrate. Since use of nitrogen or the like for the pre-ion-implantation significantly reduces recrystallization rate of an amorphous layer, the amorphous layer is not completely restored to the monocrystalline layer in the substrate and amorphous layer 12 remains, as shown in FIG. 21.
In the figure, a portion indicated by reference character 54a is a top surface of source/drain region 54, and a portion indicated by reference character 54b is a bottom surface of source/drain region 54.
An MOSFET with such a source/drain region as shown in FIG. 21 has the following problems.
That is, referring to FIG. 21, since source/drain region 54 is not completely crystallized, electrical activation of impurity ions cannot be carried out in the remaining amorphous layer 12 (in other words, holes or electrons will not be produced therein.). Consequently, carrier concentration is significantly reduced, resulting in increase in sheet resistance, poor contact characteristic at the surface, or the like.
In addition, generation of a number of secondary defects (15) in an interface region between silicon substrate 11 and monocrystalline layer 16 in the substrate results in increased leak current when reverse bias is applied.
USPTO Backgrounds
USPTO Backgrounds