Advances in non-volatile memory (NVM) are reducing the size of individual memory cells and enabling some memory cells, referred to as multilevel cells, to represent more than two states. Each state of a multilevel cell is associated with a corresponding logic value and is defined by a respective range of a specific physical quantity, e.g., a voltage. Each of these advances is associated with its own reliability issues. For example, increasing the number of possible states for a multilevel cell involves a reduction of the voltage ranges between each logic value, which makes the device more sensitive to noise. For another example, reducing the size of the memory cell may be associated with issues relating to retention, drain disturbances, floating gate coupling, etc.
Control codes, e.g., error correction codes (ECCs), have been used to improve the reliability of these advanced NVM devices. ECCs add redundant information to every predetermined set of bits, e.g., a page. Such redundant information is used to detect and correct, if possible, any errors in the page. This allows some defective cells to be accepted in the memory device without jeopardizing its operation. In this way, the production cost of the memory device can be significantly reduced.
Using known techniques to embed ECCs into NVM devices may limit subsequent manipulation of data. For example, NVM such as flash memory cannot program a “1” data on a selected cell with “0” content without erasing and rewriting a whole block of data. As a consequence, manipulation of the ECC bits and page data may be severely restricted.
USPTO Backgrounds
USPTO Backgrounds