The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Digital-to-analog converters (DACs) convert digital signals into analog signals. Typically, an N-bit DAC converts an N-bit digital input into an analog output having a voltage between 0 and Vref, where Vref is a reference voltage supplied to the DAC, and N is an integer greater than 1. The value of the analog output changes by (Vref/2N) when the value of the digital input changes by one least significant bit (LSB). Accordingly, a resolution of the DAC is defined as Vref/2N.
Referring now to FIGS. 1A-1H, DACs can be of different types and may be implemented using circuit elements such as resistors and current sources. For example, DACs may be binary-weighted or thermometer-coded. In FIG. 1A, a table shows a 3-bit binary code and a 3-bit thermometer code that is equivalent to the 3-bit binary code. In FIGS. 1B and 1C, exemplary resistance-based and current-source based 4-bit binary-weighted DACs are shown, respectively. A binary-weighted DAC may include a resistance or a current source for each bit of a binary input. The resistances may be arranged in the form of an R-2R ladder as shown or a resistance string (not shown). The R-2R ladder (or the resistance string) and the current sources are binary-weighted and are connected to a summing point that generates the analog output of the binary-weighted DACs.
In FIGS. 1D and 1E, exemplary resistance-based and current-source based 3-bit thermometer-coded DACs are shown, respectively. A thermometer-coded DAC includes resistance segments or current-source segments. The resistance segments and the current-source segments are of equal value as shown. In other words, the thermometer-coded DACs are linearly (i.e., equally) weighted. For example, the 3-bit thermometer-coded DACs shown include seven equally weighted segments. The resistance segments and the current-source segments are connected to a summing point that generates the output of the thermometer-coded DAC.
In FIGS. 1F-1H, exemplary segmented DACs are shown. Segmented DACs typically comprise a first DAC that converts LSBs of the binary input and a second DAC that converts most significant bits (MSBs) of the binary input. The first and second DACs may include a binary-weighted DAC and a thermometer coded DAC, respectively. Alternatively, both first and second DACs may include thermometer-coded DACs.
In FIGS. 1F and 1G, exemplary resistance-based and current-source based 7-bit segmented DACs are shown, respectively. The 7-bit segmented DACs each comprise a O-bit binary-weighted DAC that converts 4 LSBs and a 3-bit thermometer-coded DAC that converts 3 MSBs.
In FIG. 1H, an exemplary 6-bit segmented DAC comprises two current-source based 3-bit thermometer-coded DACs that convert 3 LSBs and 3 MSBs, respectively. The G-bit segmented DAC is 100% segmented since the 6-bit segmented DAC comprises fully thermometer-coded DACs. Contrarily, DACs comprising fully binary-weighted DACs are 0% segmented.
Many systems use DACs to convert digital data into analog signals. For example, in communication systems, transmitters use DACs to convert digital data to be transmitted into analog signals. The analog signals are then transmitted over transmission lines.
Referring now to FIG. 2A, a communication device 10 comprises a physical layer (PHY) device 12, a medium access controller (MAC) 14, and a host 16. The communication device 10 may communicate with other communication devices via a transmission medium 18 (hereinafter medium 18 or line 18). The PHY device 12 interfaces the communication device 10 to the medium 18. The MAC 14 provides access control when the communication device 10 communicates with the other communication devices via the medium 18. The host 16 processes data that is transmitted and received via the medium 18.
The communication device 10 may comply with one or more communication standards including the I.E.E.E. 10 Gigabit/second twisted-pair (10GBaseT) Ethernet standard, which is incorporated herein by reference in its entirety. According to the 10GBaseT Ethernet standard, the medium 18 may include unshielded twisted-pair (UTP) wires. The PHY device 12 may transmit and receive signals via the same UTP wires. Consequently, the PHY device 12 may receive a combined signal. The combined signal may comprise a transmit signal transmitted by the PHY device 12 to a remote communication device via the medium 18. Additionally, the combined signal may include a receive signal received by the PHY device 12 from the remote communication device via the medium 18. In other words, the transmit signal may mix with the receive signal.
The transmit signal may be prevented from mixing with the receive signal by using a hybrid in the PHY device 12. Alternatively, instead of using the hybrid, a replica DAC may be used to replicate the transmit signal. The replicated transmit signal is then subtracted from the combined signal to extract the receive signal from the combined signal. The receive signal is then input to a signal processing module of the PHY device 12.
Referring now to FIGS. 2B and 2C, PHY devices with the hybrid and the replica DAC are shown. In FIG. 2B, a PHY device 12-1 comprises a hybrid 20, a transceiver 21-1 that includes a transmitter 22 and a receiver 24, and a digital signal processing (DSP) module 26. The hybrid 20 outputs transmit signals generated by the transmitter 22 to the medium 18. The hybrid 20 outputs receive signals received from the other communication devices to the receiver 24. The hybrid 20 prevents the transmit signals from mixing with the receive signals.
The DSP module 26 generates and outputs digital transmit data to the transmitter 22. The transmitter 22 generates the transmit signals based on the digital transmit data. Additionally, the DSP module 26 processes digital receive data received from the receiver 24. The receiver 24 generates the digital receive data based on the receive signals.
The transmitter 22 may comprise a transmit DAC 28, a filter 30, and a line driver 32. The transmit DAC 28 converts the digital transmit data into analog transmit signals. The filter 30 filters out unwanted signals from the analog transmit signals and outputs filtered transmit signals. The line driver 32 conditions (e.g., amplifies) the filtered transmit signals and generates the transmit signals that are suitable for transmission by the hybrid 20 via the medium 18.
The receiver 24 may comprise an amplifier 34, a filter 36, and an analog-to-digital converter (ADC) 38. The amplifier 34 amplifies the receive signals and outputs amplified receive signals. The filter 36 filters out noise from the amplified receive signals and outputs filtered receive signals. The ADC 38 converts the filtered receive signals into the digital receive data.
In FIG. 2C, a PHY device 12-2 comprises a transceiver 21-2. The transceiver 21-2 comprises all the components of the transceiver 21-1 except the hybrid 20. Additionally, the transceiver 21-2 comprises a replica DAC 52, a amplifier 53, and a subtractor 66. The transceiver 21-2 transmits signals to the remote communication device via the line 18. The transceiver 21-2 receives signals from the remote communication device via the line 18 (i.e., via the same UTP wires). In other words, the transceiver 21-2 transmits and receives signals via the same UTP wires. Consequently, the transceiver 21-2 receives the combined signal comprising the transmit and receive signals that are transmitted and received by the transceiver 21-2 via the same UTP wires.
The transceiver 21-2 extracts the receive signal from the combined signal by removing the transmit signal generated by the transmit DAC 28 from the combined signal. Specifically, the transceiver 21-2 uses the replica DAC 52 that is a closely matched replica of the transmit DAC 28 to replicate the transmit signal. The replicated transmit signal generated by the replica DAC 52 is amplified by the amplifier 53 to generate an amplified replica signal. The amplifier 53 has a gain that matches the gain of the line driver 32. The amplified replica signal is then subtracted from the combined signal to extract the receive signal from the combined signal.
Ideally, a clean receive signal may be generated by removing the transmit signal from the combined signal. Practically, however, the transmit signal cannot be completely removed from the combined signal when the replicated transmit signal does not match the transmit signal due to variations in size of the circuit elements used to implement the replica and transmit DACs 52, 28.
Generally, the variations are inversely proportional to the size of the circuit elements. In other words, as the size of the circuit elements increases, the variations decrease. Accordingly, the replica and transmit DACs 52, 28 may be implemented using large circuit elements to minimize the variations.
Using large circuit elements, however, may be disadvantageous since large circuit elements may dissipate more power. Additionally, using large circuit elements may be impractical when the maximum size of the circuit elements is limited by high signal frequencies (e.g., when communication devices use the 10GBaseT Ethernet standard).
USPTO Backgrounds
USPTO Backgrounds