1. Field of the invention
This invention relates to the process of removing and vaporizing small layers from semi-conductor substrate materials with halide gases in the presence of water. More particular it relates to removing and vaporizing native oxides in contact holes etc., in order to prepare a wafer for a subsequent step, specifically to try to restore the interface to a virginal state so as to be able to e.g. grow epitaxial silicon, grow selective W, selective metal silicides etc., or to realize very thin, very uniform and very reliable oxide layers to be used for gates, dielectrics etc. For all of this the interface has in any case to be free from organic or metal debris. In the art this is done in a wet etch. However, a wet etch is of limited use if the feature size is such that the liquid surface tension prevents the reactant to reach the very bottom of e.g. the contact hole. Because of that a wet etch is incapable of completely removing the oxide built-up (typically 10 to 20 .ANG. thick) in deep contact holes.
2. Description of the prior art
Because of this in the prior art, e.g. U.S. Pat. No. 4,749,440 it is proposed to use a gaseous etch to remove this so called native oxide in order to clean the interface. This gaseous etch does not have surface tension. In the method according to the above U.S. specification halide gas does enter the reaction chamber at near atmospheric pressure in the presence of water. The flow of the halide is controlled by a mass flow controller and with a vent continuously open to atmosphere or throttled to increase the pressure. The etch time is typically between 5 and 30 seconds.
The use of a mass flow controller in a dynamic process gives rise to several problems. First of all the mass flow controller has to be constructed from a material resistant to the reactive gases used. Furthermore it has been found that it is extremely difficult to exactly control the rate of etching with a fluctuating flow of etchant gas and therefore at fluctuating partial pressures.
The nature of the application in the prior art requires a process on a single wafer to be finished within 5-30 s. i.e. etching of hundreds to thousands of .ANG. at relatively high etch rate. It has been established that actual etching may suffer from a delay in time ranging from 1 second up to 5 minutes. This is a phenomenon not understood. Therefore in 5-30 s. one can either have zero etching or many thousands of .ANG. removed either locally or all over the wafer. Of course this is unacceptable. This is particular true when dealing with patterned wafers. It should not be that when the removal of 30 .ANG. of a native oxide is required, intentially deposited oxide layers are also for the most part removed because of an appreciable overetch.
USPTO Backgrounds
USPTO Backgrounds