1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device such as a MOS field effect transistor (FET) having gate electrodes of different conductivity types.
2. Description of the Related Art
A CMOS type semiconductor device is known which has two MOSFETs of different types, i.e., a p-channel type MOSFET and an n-channel type MOSFET. More specifically, the device comprises a p-type semiconductor substrate, an n-type diffusion layer (n-well region) formed in the substrate, and an SiO.sub.2 film formed on the substrate and the n-well region and functioning as an element isolating region. The device further comprises gate electrodes formed on the substrate and the n-well region, each spaced a predetermined distance apart from the SiO.sub.2 film, and source and drain regions formed between the SiO.sub.2 film, and each of the gate electrodes.
In general, n-type polycrystal silicon containing phosphorus (P) or arsenic (As) as impurities is used to form the gate electrodes of MOSFETs. However, if the gate electrodes are 1 .mu.m or less wide, it is then necessary to prevent the short channel effect which may result on account of the gate electrodes being of such narrow width. Thus, to prevent the occurrence of the short-channel effect, the gate electrode of the p-channel MOSFET must be made of p-type polycrystal silicon containing boron (B). Hence, the p-channel MOSFET must have a p-type gate electrode, and the n-channel MOSFET an n-type gate electrode.
Referring to FIGS. 1A though 1F, it will now be described how the above-mentioned conventional CMOS semiconductor device is manufactured.
First, as shown in FIG. 1A, n-type diffusion layer 14 is formed in that portion of p-type semiconductor substrate 12 where a p-type gate electrode (mentioned later) is to be formed.
Then, as shown in FIG. 1B, SiO.sub.2 film 16, or an element isolating region, is formed on that portion of n-type diffusion layer 14 which is in contact with p-type semiconductor substrate 12.
Next, as shown in FIG. 1C, thermal oxide film 18, or a gate insulating film, is formed on p-type semiconductor substrate 12 and n-type diffusion layer 14. Thereafter, polycrystal silicon 20, or a gate electrode, is formed on thermal oxide film 18 and SiO.sub.2 film 16.
Further, as shown in FIG. 1D, resist pattern 22 is formed such that it covers that region where an n-channel MOSFET is to be formed (the left half of FIG. 1D). Then, boron ions are injected into that portion of polycrystal silicon film 20 where a p-channel MOSFET is to be formed (the right half of FIG. 1D). Similarly, arsenic ions are injected into that portion of polycrystal silicon film 20 where the n-channel MOSFET is to be formed.
Next, SiO.sub.2 film 24 is formed on polycrystal silicon film 20 by the CVD (chemical vapor deposition) method. Then, gate electrodes 20a and 20b are patterned as shown in FIG. 1E. In addition, resist pattern 26 is formed such that it covers the region where the n-channel MOSFET is to be formed. Subsequently, boron ions are injected into the p-channel MOSFET in a self-aligning manner.
Thereafter, as shown in FIG. 1F, source and drain region 28 is formed by annealing. Similarly, arsenic ions are injected into the n-channel MOSFET, and source and drain region 30 is formed. Then, resist pattern 26 and SiO.sub.2 film 20 formed on gate electrodes 20a and 26b are removed. As a result, a p-channel and an n-channel MOSFET are produced according to the prior art method.
In the above-described prior art method for producing a semiconductor device, the impurity is doped into polycrystal silicon film 20 by means of ion injection. If polycrystal silicon film 20 is relatively thick, e.g., 2000 .ANG. or more, semiconductor substrate 12 will not be affected by the ion injection. However, if the width of the gate electrode is 1 .mu.m or less, this necessitates polycrystal silicon 20 being proportionally thin, with the result that the impurity will inevitably diffuse through film 20 and into semiconductor substrate 12, and degrades the characteristics of the MOSFET.
As has been described above, in the prior art, the impurity ions are injected into the polycrystal silicon film functioning as a gate electrode. Consequently, the narrower and thinner the gate electrode is, the greater the degradation of the characteristics of the resultant MOSFET.
USPTO Backgrounds
USPTO Backgrounds