(1) Field of the Invention
The present invention relates to a decoder circuit, more particularly to a decoder circuit which is used, for example, in a semiconductor memory device and in which metal insulator semiconductor (MIS) transistors are connected to decode signal output lines shared by adjacent decode signal output lines, thereby increasing the degree of integration of the integrated circuit device including the decoder circuit.
(2) Description of the Prior Art
In recent years, the memory capacity of semiconductor memory devices has become larger and the size of the memory chips thereof has become smaller. Therefore, it has become desirable to reduce the size of each circuit block therein, for example, decoder circuits such as column address decoder circuits, which select bit lines, or row address decoder circuits, which select word lines.
A conventional decoder circuit of a semiconductor memory device comprises one or more separate decoder units which are disposed side by side and each supplies a pair of decode output signals according to an input address signal. Therefore, in the conventional decoder circuit, each of the decoder units occupies a large area on the semiconductor chip and it is necessary to form isolation areas between adjacent decoder units. As a result, the degree of integration of semiconductor memory devices using the conventional decoder circuit has not been great enough. It has been impossible to further increase the degree of integration thereof.
USPTO Backgrounds
USPTO Backgrounds