The present invention relates to a semiconductor memory device and a technology for improving a noise margin and an operating speed of an SRAM (Static Random Access Memory) and achieving low power consumption thereof, e.g., a technology effective for application to an SRAM having CMOS flip-flop circuit type memory cells or an LSI (Large Scale Integration) with the SRAM built therein.
In a semiconductor memory device (hereinafter called a “semiconductor memory” or simply “memory”) such as an SRAM, an increase in capacity has been put forward with the scale-down of an elemental device by a process. On the other hand, when process-based scale-down is effected according to a so-called scaling law in a semiconductor memory comprising MOSFETs, a gate insulating film for MOSFETs constituting a memory cell and a peripheral circuit becomes thin. Therefore, a withstand voltage of each MOSFET becomes low with the scale-down. In a semiconductor integrated circuit, the lower a source or power supply voltage, the less its power consumption. Further, as the MOSFET becomes low in threshold voltage, the semiconductor integrated circuit can perform a high-speed operation. Therefore, a reduction in power supply voltage has been carried out with the scale-down.
Meanwhile, when a threshold voltage of each MOSFET that constitutes a memory cell, is reduced or a source or power supply voltage for the memory cell is lowered in the SRAM, a defective condition takes place in that a leak current increases and a static noise margin is reduced, and a so-called soft error in which memory information is reversed due to an α ray, is apt to occur.
There has heretofore been proposed an invention wherein in order to prevent an increase in leak current due to a reduction in threshold voltage of each MOSFET constituting a memory cell and improve an operating speed, the threshold voltage of each MOSFET constituting the memory cell is set high and the threshold voltage of each MOSFET constituting a peripheral circuit is reduced (e.g., see Unexamined Patent Publication No. Hei 3(1991)-83289). There has also been proposed an invention wherein in order to reduce power consumption while the speeding-up of read and write operations is being carried out, a source or power supply voltage for each memory cell is set high and the threshold voltage of each MOSFET that constitutes the memory cell, is set high, whereas a power supply voltage for a peripheral circuit is reduced (e.g., see Unexamined Patent Publication No. Hei 10(1998)-242839 (corresponding U.S. Pat. No. 6,046,627), and Unexamined Patent Publication No. Hei 9(1997)-185886 (corresponding U.S. Pat. No. 5,757,702)).
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