1. Field of the Invention
The present invention relates to liquid crystal display devices. More particularly, the present invention relates to liquid crystal display devices implementing in-plane switching (IPS) where an electric field applied to liquid crystals is generated in a plane parallel to a substrate.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite orientational alignment as a result of their long, thin shapes. The alignment direction can be controlled by an applied electric field. In other words, as an applied electric field changes, so does the alignment of the liquid crystal molecules. Due to the optical anisotropy, the refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling an applied electric field, a desired light image can be produced.
Of the different types of known liquid crystal displays (LCDs), active matrix LCDs (AM-LCDs), which have thin film transistors (TFTs) and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
LCD devices have wide application in office automation (OA) equipment and video units because they are light and thin and have low power consumption characteristics. The typical liquid crystal display panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors and pixel electrodes.
LCD device operation is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an electric field applied between the common electrode and the pixel electrode. Thus, the alignment direction of the liquid crystal molecules is controlled by the application of an electric field to the liquid crystal layer. When the alignment direction of the liquid crystal molecules is properly adjusted, incident light is refracted along the alignment direction to display image data. The liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
In a related art LCD device, the pixel and common electrodes are positioned on the lower and upper substrates, respectively, and the electric field induced between the pixel and common electrodes is substantially perpendicular to the lower and upper substrates. However, these related art LCD devices have a very narrow viewing angle. In order to solve the problem of narrow viewing angle, in-plane switching liquid crystal display (IPS-LCD) devices have been proposed. The IPS-LCD devices typically include a lower substrate in which a pixel electrode and a common electrode are disposed, an upper substrate having no electrode, and a liquid crystal interposed between the upper and lower substrates. A detailed explanation of a related art IPS-LCD panel will be provided with reference to FIG. 1.
FIG. 1 is a plan view illustrating an array substrate for use in a related art IPS-LCD device. As shown in FIG. 1, a plurality of gate lines 14 are disposed in a transverse direction and spaced apart from each other by a predetermined distance. A plurality of common lines 18 are also disposed parallel to the gate lines 14, and each common line 18 is adjacent to each gate line 14. A plurality of data lines 30 are disposed in a longitudinal direction substantially perpendicular to the gate and data lines 14 and 18. Pairs of the gate and data lines 14 and 30 define a pixel region P. A gate pad 16 is disposed at one end of each gate line 14, and a data pad 40 is disposed at one end of each data line 30. Near a crossing of the gate and data lines 14 and 30, a thin film transistor T is provided including a gate electrode 12, an active layer 26, a source electrode 32, and a drain electrode 34. The gate electrode 12 extends from the gate line 14, whereas the source electrode 32 extends from the data line 30. The active layer 26 is disposed over the gate electrode 12, and the source and drain electrodes 32 and 34 are in contact with the active layer 26.
In the pixel region P, a plurality of pixel electrodes 38 are substantially parallel to the data lines 30. The plurality of pixel electrodes 38 are electrically connected to the drain electrode 34 of the thin film transistor T. A plurality of common electrodes 20 are also disposed within the pixel region P and substantially parallel to the data lines 30. The common electrodes 20 are substantially perpendicular to and connected to the common line 18. The common electrodes 20 are arranged in an alternating pattern with the pixel electrodes 30.
In the pad portions where the gate and data pads 16 and 50 are located, there are provided gate pad electrodes 48 and data pad electrodes 50. The gate pad electrodes 48 contact the gate pads 16, respectively, and the data pad electrodes 50 contact the data pads 40, respectively.
In the above illustrated array substrate for use in the IPS-LCD panel, the source and drain electrodes 32 and 34 and the data lines 30 are usually single-layered patterns formed of molybdenum (Mo) or chromium (Cr). However, the Mo and Cr metals have a high electrical resistance, the array substrate including the Mo or Cr patterns may not be used for an IPS-LCD panel that requires a large size and an ultra high resolution.
FIGS. 2A-2D, 3A-3D, 4A-4D and 5A-5D are cross sectional views taken along lines II-II, III-III, IV-IV and V-V of FIG. 1, respectively, and illustrate the process of forming the array substrate of FIG. 1 according to a related art.
In FIGS. 2A, 3A, 4A and 5A, a conductive metallic material, for example, aluminum (Al) or aluminum alloy, is deposited on a substrate 10, and then patterned using a first mask (not shown), to form a gate electrode 12, a gate line 14, a gate pad 16, a common line 18, and a plurality of common electrodes 20. As described with reference to FIG. 1, the gate and common lines 14 and 18 are formed adjacent to and parallel to each other. The gate electrode 12 extends from the gate line 14, and the gate pad 16 is disposed at one end of the gate line 14. The common electrodes 20 perpendicularly extend from the common line 18 in a direction opposite to the adjacent gate line. After patterning the conductive metallic material, a gate insulating layer 24 is formed over an entire surface of the substrate 10 to cover all of the gate electrode 12, the gate line 14, the gate pad 16, the common line 18, and the plurality of common electrodes 20.
In FIGS. 2B, 3B, 4B and 5B, pure amorphous silicon (a-Si:H) and doped amorphous silicon (n+ a-Si:H) are sequentially deposited on the gate insulating layer 24, and then patterned using a second mask, to form an active layer 26 and an ohmic contact layer 28 on the gate insulating layer 24 in series. Especially, the active and ohmic contact layers 26 and 28 are disposed over the gate electrode 12.
Next in FIGS. 2C, 3C, 4C and 5C, a second metallic material (e.g., chromium or molybdenum) is deposited over the gate insulating layer 24 and covers the active and ohmic contact layers 26 and 28. Thereafter, the second metallic material is patterned by a third mask process, to form a data line 30, a source electrode 32 and a drain electrode 34. The data line 30 perpendicularly crosses the gate line (reference 14 of FIG. 1), and defines a pixel region P. The source electrode 32 extends from the data line 30, and contacts the ohmic contact layer 28. The drain electrode 34 is spaced apart from the source electrode across the gate electrode 12, and also contacts the ohmic contact layer 28. When patterning the second metallic material in order to form the data line 30, a plurality of pixel electrodes 38 are also formed on the gate insulating layer 38. Each pixel electrode 38 being parallel with the data line 30 is disposed between the common electrodes 20. Additionally, a gate pad 40 is formed at one end of the gate line 30. After patterning the second metallic material, a passivation layer 42 is formed over an entire surface of the substrate 10 to cover all of the data line 30, the source and drain electrodes 32 and 34, the pixel electrodes 38, and the data pad 40. The passivation layer 42 is silicon oxide (SiO2) or silicon nitride (SiNX). Thereafter, the passivation layer 42 is patterned using a fourth mask to form a gate pad contact hole 44 and a data pad contact hole 46. The gate pad contact hole 44 exposes a portion of the gate pad 16, whereas the data pad contact hole 46 exposes a portion of the data pad 40, as shown in FIGS. 4C and 5C.
In FIGS. 2D, 3D, 4D and 5D, a transparent conductive material, for example, indium tin oxide (ITO), is deposited on the passivation layer 42 and then patterned using a fifth mask. Thus, a gate pad electrode 48 contacting the gate pad 16 is formed, and a data pad electrode 50 contacting the data pad 40 is also formed.
However, the array substrate fabricated by the above-mentioned process has some disadvantages. Because the data lines and the source and drain electrodes are all formed of the metallic material having a low electrical resistance, for example, molybdenum (Mo) or chromium (Cr), the array substrate is not adequate in a LCD panel requiring a ultra high resolution.
USPTO Backgrounds
USPTO Backgrounds