1. Field of the Invention
The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of forming contacts for a memory device.
2. Description of the Related Art
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
A dynamic random access memory (DRAM) is made up of memory cells. Each cell of a modern DRAM includes a transistor and a capacitor, where the capacitor holds the value of each cell, namely a “1” or a “0,” as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
Referring to FIG. 1, a schematic diagram of an illustrative DRAM memory cell 10 is depicted. The cell 10 is illustrated as having a capacitor 12 and an access transistor 14. The capacitor 12 is used to store a charge. The charge represents a bit of information. The access transistor 14 acts as a switch for the capacitor 12. That is, the access transistor 14 controls when a charge is placed on the capacitor 12, and when a charge is discharged from the capacitor 12. A word line 16 is coupled to a control gate of the access transistor 14. When a cell is read, the word line 16 activates the control gate of the transistor 14. Once this happens, any charge (or lack of charge) stored on the capacitor 12 is shared with a conductive digitline 18 coupled to the drain of the access transistor 14. This charge is then detected in the digitline 18 by a sense amplifier (not shown) and then processed to determine the bit state of the cell 10. Tiling a selected quantity of cells 10 together, such that the cells 10 along a given digitline 18 do not share a common word line 16 and the cells 10 along a common word line 16 do not share a common digitline 18, forms a memory array. A typical memory array contains thousands or millions of cells 10.
A simplified block diagram of a prior art DRAM 20 is described in FIG. 2. The memory device can be coupled to a processor 32 for bi-directional data communication. The memory includes an array of DRAM memory cells 22. Control circuitry 28 is provided to manage data storage and retrieval from the array 22 in response to control signals from the processor 32. Address circuitry 26, X-decoder 26a and Y-decoder 26b analyze address signals and storage access locations of the array 22. Sensing circuitry 24 is used to read data from the array 22 and couple output data to I/O circuitry 30. The I/O circuitry 30 operates in a bi-directional manner to receive data from the processor 32 and pass this data to array 22. Of course, those skilled in the art will understand that the illustrative circuitry depicted in FIG. 2 does not include all of the circuitry of a functioning DRAM.
The manufacture of memory devices, particularly DRAMs, is a very competitive industry. Thus, process engineers are faced with continuous pressure to become ever more efficient in the processing techniques and methods used to form such devices. In general, manufacturing a DRAM device involves the performance of many individual process steps. For example, multiple deposition, cleaning, etching, ion implantation, polishing and heating processes are typically performed in a precise order to produce a DRAM device. Such processes typically involve the use of very complex processing tools that are very expensive to maintain and use.
During the formation of memory devices, several conductive connections must be made to device features formed in and above a semiconducting substrate. Conductive connections that couple a conductive metal line to a device formed in or above the substrate, or ones that are coupled to the substrate itself are sometimes referred to as contacts. Conductive connections between layers of conductive lines that are positioned in layers of insulating material are sometimes referred to as vias. For example, in a DRAM array 22 having a dual bit memory cell structure, a so-called digitline contact is provided between a digitline and an access device, e.g., a transistor, formed in or above a substrate. So-called storage node contacts are formed between the access transistor and a capacitor or storage node where electrical charge may be stored. Additionally, there are many contacts that must be formed to other semiconductor devices, e.g., transistors, resistors, capacitors, that are used to form contacts in areas of the DRAM outside of the memory array 22. For example, contacts must be formed to the semiconductor devices that comprise the sensing circuitry 24 as well as other circuits located outside of the array 22, i.e., the non-array circuitry.
In a typical process flow used to form a DRAM, contacts formed within the array 22 are formed at a different time relative to the formation of contacts to circuits outside of the array 22. Thus, although the precise methodology of forming the contacts may involve similar steps, the process steps are performed at different points in time during the course of manufacturing the device. Additionally, the formation of a digitline contact and the storage node contacts is generally formed by performing a sequence of process steps that typically involves several polishing steps wherein an upper surface of the gate electrode for the access transistor is used as a polishing stop surface in a chemical mechanical polishing (CMP) process. Since the upper surface of the gate electrode is frequently covered with a layer of silicon nitride (a “nitride cap”), such processing steps are sometimes referred to as stop-on-nitride (SON) polishing techniques. In the case of a DRAM with a buried access device, CMP processes may lead to dishing within the array 22 which, in turn, may lead to problems with future photolithography processes. When performing such a CMP process on a DRAM with non-buried access devices, it is generally preferable to remove the nitride cap on the gate electrodes outside of the array 22 by using a photolithography step to protect the array 22. Typically, contacts inside the array 22 are filled with polysilicon and contacts outside of the array 22 are filled with a metal, such as tungsten.
What is needed is a more efficient methodology for forming contacts on DRAMs. The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.
USPTO Backgrounds
USPTO Backgrounds