a) Field of the Invention
The present invention relates to a semiconductor integrated circuit device having MOSFETs, and more particularly to a CMOS semiconductor integrated circuit device having very long and wide area wirings.
b) Description of the Related Art
As semiconductor integrated circuits become fine and gate oxide films of MOSFETs become thin, gate oxide films become likely to be deteriorated or damaged during manufacturing processes. Damaged gate oxide films pose problems of a variation of a MOSFET threshold voltage and low reliability.
These problems are likely to occur when a very long and wide area wiring is connected to a gate electrode. One of the reasons of damaging a gate oxide film may be electric charges accumulated on a wiring layer connected to a gate electrode during manufacturing processes which electric charges may cause tunnelling current through through the gate oxide film and result in a dielectric breakdown of the gate oxide film. U.S. patent application Ser. No. 08/275,426 filed on Jul. 15, 1994, is incorporated herein by reference.
Accumulation of electric charges on a wiring layer during manufacturing processes may be considered as resulting from a large aspect ratio of an opening in a resist mask formed on a wiring layer which leads to an excess amount of positive charges than the amount of electrons incident upon the opening. Even if an opening has a large aspect ratio, electric charges are prevented from being accumulated on a wiring layer if processes ensuring the equal amounts of positive and negative charges are realized. It is very difficult, however, to realize such processes.
It is possible to reduce damage to a gate oxide film by limiting the length and area of a wiring connected to the gate electrode. However, this is practically difficult from the following reasons.
FIG. 12B is a circuit diagram of a CMOS type NAND circuit. A parallel circuit of p-channel MOS transistors PM1 and PM2 and a serial circuit of n-channel MOS transistors NM1 and NM2 are serially connected.
One input signal IN1 is applied to the gate electrodes of the MOS transistors PM1 and NM1, and the other input signal IN2 is applied to the gate electrodes of the MOS transistors PM2 and NM2. An output signal OUT is obtained from the interconnection between the parallel circuit of the p-channel MOS transistors PM1 and PM2 and the serial circuit of the n-channel MOS transistors NMl and NM2.
The four transistors shown in FIG. 12B are usually formed closely one another on a substrate. However, pre-stage circuits for supplying the input signals IN1 and IN2 are not always formed near each other. If the AND circuit is formed near one pre-stage circuit for supplying one input signal, a wiring for the other input signal becomes long. It is therefore difficult to lay out a circuit with a plurality of input terminals so that all input wirings become short.
Another means for reducing electric charges stored on a wiring connected to a gate electrode is to connect a diode for protecting the gate electrode. Electric charges on a wiring layer are discharged via the diode.
FIG. 12A shows a conventional circuit for preventing electric charges from being accumulated on a wiring layer connected to a gate electrode.
A p-channel MOS transistor PM3 and an n-channel MOS transistor NM3 are serially connected. An input signal is supplied to the gate electrodes of the transistors PM3 and NM3 from a pre-stage circuit PS via a long and wide area input wiring line. The gate electrodes of the transistors PM3 and NM3 are connected via a protection diode D1 to an n-type well in which the p-channel MOS transistor PM3 is formed, and also connected via a protection diode D2 to a p-type well in which the n-channel MOS transistor NM3 is formed. Each diode D1, D2 is connected in a reverse biased direction at a normal operation voltage.
When a positive high potential is generated by electric charges on an input wiring layer, current flows via the protection diode D1 into the n-type well, whereas when a negative high potential is generated, current flows via the protection diode D2 into the p-type well. In this manner, electric charges accumulated on the input wiring layer are discharged via the protection diode D1 or D2 into the n- or p-type well. It is therefore possible to prevent a high electric field from being applied to the gate oxide film.
As shown in FIGS. 12A and 12B, input wirings of a CMOS circuit are connected to both n- and p-channel MOS transistors. As shown in FIG. 12A, for one input wiring, two protection diodes are required to be connected in association with the n- and p-channel MOS transistors. Therefore, an area occupied by the CMOS circuit becomes large in opposition to the demands for high integration.
USPTO Backgrounds
USPTO Backgrounds