Two supply voltages have been used in memories in which the periphery circuitry uses voltage VDDp provided by a first power supply node, and the bit (or cell) arrays use voltage VDDc provided by a second power supply node. In those approaches, to save power in low frequency reading and writing operations (e.g., in the 100 Mhz range), voltage VDDp is lowered, but voltage VDDc is kept at the usual level in order to avoid writing problems that usually occur in low voltage operations (e.g., VDDc is at the minimum required voltage). In high frequency operations (e.g., in the 1 Ghz range), both voltage VDDp and voltage VDDc, however, are kept at the same usual voltage level (e.g., at voltage VDDc) to achieve the desired speed. Those approaches thus save power, e.g., leakage current, in the periphery circuitry, but the bit arrays are still subject to the high power consumption during the active operations (e.g., reading and writing). As a result, little power is saved because during active operations the leakage current affected by voltage VDDc in the bit array is dominant over the leakage current affected by voltage VDDp in the peripheral circuit.
Like reference symbols in the various drawings indicate like elements.
USPTO Backgrounds
USPTO Backgrounds