1. Field of the Invention
The present invention relates in general to a bus architecture technology. In particular, the present invention relates to a bus structure with a middle pull-up element for point-to-point communication, thereby increasing the signal transmission speed and facilitating the circuit layout.
2. Description of the Related Art
Due to the high-speed requirement for electronic systems, the data transmission rate between various integrated circuits (ICs) also must be increased. There are several transmission bus architectures designed for raising the practical data transmission rate in a bus. For example, in some bus structures, such as the open scheme bus, the amplitude of the transmission signals is enhanced by utilizing the reflection effect at the receiver. Otherwise, some bus structures employ coupled resistors at the transmitter to eliminate the deviation of the transmission conditions caused by PVT factors, where P represents the manufacturing process factor, V represents the voltage factor and T represents the temperature factor. In addition, some bus structures involve DC termination resistors at both ends of the bus to eliminate reflection waves, such as the Gunning Transceiver Logic (GTL) bus. These bus technologies have their own advantages and drawbacks. The following description will focus on the open scheme bus and the GTL bus.
FIG. 1 (Prior Art) is a diagram illustrating the configuration of the open scheme bus for point-to-point communication in the prior art. Such bus structure is applied for receiving or transmitting signals between integrated circuits (ICs). As shown in FIG. 1, IC 12 and IC 14 are directly connected with transmission line 10, where one IC functions as a transmitter and the other IC functions as a receiver. Therefore, in the open scheme bus, it is quite easy to layout printed circuit boards (PCBs). Note that the output impedance of the IC serving as the transmitter should match with the characteristic impedance Z0 of transmission line 10. Since the reflective index is 1 at the receiver, the reflection wave is the same as the incident wave. Accordingly, the receiver can acquire a good-quality digital waveform.
FIG. 2 (Prior Art) is a waveform diagram of voltage signals on the transmitter, the receiver and a middle point 10a in the open scheme bus shown in FIG. 1. In FIG. 2, numeral 15 represents the voltage signal on the transmitter, numeral 17 represents the voltage signal on the receiver and numeral 19 represents the voltage signal on the middle point 10a. As shown in FIG. 2, the voltage signal 15, which appears on the transmitter, requires the double of the flight time to reach the steady state. On the other hand, however, the voltage signal 17, which appears on the receiver, has a quite perfect signal waveform.
The main advantage of the conventional open scheme bus is to facilitate the circuit layout due to its simple architecture. Practically, however, the open scheme bus has some drawbacks:
(1) The prerequisite of acquiring better waveforms at the receiver is the output impedance of the transmitter must exactly match with the characteristic impedance Z0 of the transmission line 10. However, the output impedance of the transmitter may vary with various operating conditions and the fabrication process. Accordingly, it requires a compensatory circuit in the transmitter to compensate the deviation of the output impedance caused by the PVT factors.
(2) Referring to FIG. 2, the voltage on the transmitter requires the double of the flight time to reach the steady state. In other words, the double of the flight time may limit the data transmission rate of the bus. If the data transmission rate exceeds the limitation, power and ground in the circuit will be unstable, and the noise and the skew of the data transmission time among various data transmission lines will be deteriorated.
Next, the structure of the GTL bus will be described as follows. FIG. 3 (Prior Art) is a diagram illustrating the configuration of the conventional multi-point transceiving GTL bus, where the voltage VTT is typically 1.2V. If the voltage VTT is changed to 1.5V, such a GTL bus version is called the GTL+ bus, which is applied to the interconnection between Intel P6 CPUs and their chipsets. As shown in FIG. 3, a plurality of transmission lines 20 are shown and connected to I/O pins of different ICs 22a, 22b, . . . and 22c. In addition, there are two pull-up resistors RT connected to both ends of the transmission line 20, respectively. The resistance value of the pull-up resistors RT is designed to match with the characteristic impedance Z0 of the transmission line 20. Accordingly, there is no reflective wave in the transmission line 20 during the transmission period since the reflective indexes at both ends are zeros. The signal waveforms on the transmission line 20 are almost the same everywhere. The only difference among these signal waveforms is the arrival time.
The GTL bus is not only applied to the multi-point communication applications, but also to point-to-point communication applications. FIG. 4 (Prior Art) is a diagram illustrating the configuration of the conventional point-to-point GTL bus. In FIG. 4, the transmission lines 30, 30a and 30b have the same characteristic impedance Z0. In addition, the input/output circuit of IC 32 is connected at an intersectional point of the transmission lines 30 and 30a, and the input/output circuit of IC 34 is connected at an intersectional point of the transmission lines 30 and 30b. As similar to FIG. 3, both ends of the whole transmission line, including lines 30, 30a and 30b, are connected to termination resistors RT, respectively. The resistance values of termination resistors RT are the same as the characteristic impedance Z0.
FIG. 5 (Prior Art) is a waveform diagram of voltage signals on the transmitter, the receiver and a middle point 33 in the conventional GTL bus shown in FIG. 4. In FIG. 5, numeral 35 represents the voltage signal waveform on the transmitter, numeral 37 represents the voltage signal waveform on the receiver and numeral 39 represents the voltage signal waveform on the middle point 33. As shown in FIG. 5, the voltage signal waveform on the receiver is perfect and the voltage signal waveform on the transmitter reaches the steady state regardless of the length of the transmission line. Accordingly, the data transmission rate can theoretically be upgraded unlimitedly.
However, the GTL bus still has drawbacks. The first drawback is that it is necessary to mount a plurality of termination resistors at the ends of the transmission lines to have the better electricity characteristic. FIG. 6 (Prior Art) is a diagram of the layout of the conventional GTL bus on a printed circuit board. As shown in FIG. 6, there are two additional transmission lines 30a and 30b at the I/O pins of the ICs 32 and 34 to couple to termination resistors RT. Therefore, for a packaged IC with dense wiring, it is quite difficult to further interconnect for all of the I/O pins with the corresponding termination resistors RT. Since such scheme almost doubles the number of the interconnections for each IC, the circuit layout and the wiring design are complicated.
To solve the problem caused by dense interconnections, one solution is to place the termination resistors within the IC to decrease the interconnections for the IC. FIG. 7 (Prior Art) is a diagram illustrating the configuration of the conventional GTL bus when the termination resistors are placed within the IC. As shown in FIG. 7, the transmission line 30 is used to connect IC 32 with IC 34, where IC 32 is a dense-wiring IC. For the decrease of the wiring number of IC 32, the termination resistor RT is installed within IC 32. More specifically, one end of the termination resistor RT is coupled to the I/O pin of the IC 32 via an internal bonding wire 30a and the other end of the termination resistor RT is coupled to an external voltage source VTT. Since no additional interconnecting traces for coupling with the termination resistor is required, the interconnecting traces on the printed circuit board for the IC 32 does not increase.
Placing the termination resistors within the IC can truly solve the layout problem. However, since there is parasitic inductance 36 between the IC internal power source and the external power source, a noise expressed by L*dI/dT will be immediately induced as the data is transmitted or received, where L denotes the inductance value of parasitic inductor 36 and dI denotes the variation of the current flowing through the termination resistor RT within a time interval dT. Since dI is inversely proportional to the resistance value of termination resistor RT, the noise will increase as the resistance value of termination resistor RT decreases. In fact, the noise source can worsen the skew of the data transmission time among various data transmission lines and cause the errors of the transmitted data.
According to the above description, the bus structure with a reflective index of 1, such as the open scheme bus, has an advantage of easy implementation, but suffers a drawback that the voltage of the transmitter requires the double of the flight time to reach the steady state. The data transmission rate is therefore limited. On the other hand, since the GTL bus uses the termination resistors in the bus structure, the data transmission rate of such bus can be theoretically upgraded unlimitedly. However, its drawback is that the termination resistors must be connected to the I/O pins of the IC via extra lines, therefore, the circuit layout for the GTL bus is complicated. Although mounting the termination resistors within the IC can facilitate the circuit layout, the solution method may introduce another noise issue.
USPTO Backgrounds
USPTO Backgrounds