Recently, various new technologies have been developed for improving a data transferring speed of a double data rate (DDR) memory device. For instance, an off chip driver (OCD) calibration technology has been introduced to a specification of the DDR memory device by the JEDEC (Joint Electron Engineering Council) in order to adjust an impedance of a data output unit of the DDR memory device.
That is, the optimum impedance of a data output driver for a current system is detected by measuring a voltage, or a current which flows from an external circuit such as a chip set to the data output driver, so that an impedance of the data output driver is adjusted to the optimum impedance. For this purpose, a DDR2 synchronous semiconductor memory device additionally includes an OCD control unit for adjusting an impedance of the data output driver.
A termination impedance is needed for stably transferring a signal between circuits. If the termination impedance is not appropriately matched, a signal reflection error can occur, i.e., a transferred signal can be reflected back. However, if an external fixed resistor is provided, an appropriate matching may not be obtained due to aging of an integrated circuit, temperature variations or manufacturing process variations.
Therefore, a technology for adjusting the termination impedance has been developed in order to obtain an impedance match with an external reference impedance by controlling the number of turned-on transistors among a plurality of transistors connected in parallel.
FIG. 1 is a block diagram showing a conventional on-die termination (ODT) control device.
As shown, the conventional ODT control device includes first to third driving control units 10, 20 and 30.
The first driving control unit 10 includes a first inverter I1, first and second PMOS transistors P1 and P2, and first and second NMOS transistors N1 and N2. The first PMOS transistor P1 and the first NMOS transistor N1, connected in series between a source voltage and a ground voltage, have a common gate for receiving a first decoding signal S0 and a common drain for outputting a first pull-up control signal PU_S0. The second PMOS transistor P2 and the second NMOS transistor N2, connected in series between the source voltage and the ground voltage, have a common gate for receiving an inverted first decoding signal and a common drain for outputting a first pull-down control signal PD_S0.
The second driving control unit 20 includes a second inverter I2, third and fourth PMOS transistors P3 and P4, and third and fourth NMOS transistors N3 and N4. The third PMOS transistor P3 and the third NMOS transistor N3, connected in series between the source voltage and the ground voltage, have a common gate for receiving a second decoding signal S1 and a common drain for outputting a second pull-up control signal PU_S1. The fourth PMOS transistor P4 and the fourth NMOS transistor N4, connected in series between the source voltage and the ground voltage, have a common gate for receiving an inverted second decoding signal and a common drain for outputting a second pull-down control signal PD_S1.
The third driving control unit 30 includes a third inverter I3, fifth and sixth PMOS transistors P5 and P6, and fifth and sixth NMOS transistors N5 and N6. The fifth PMOS transistor P5 and the fifth NMOS transistor N5, connected in series between the source voltage and the ground voltage, have a common gate for receiving a third decoding signal S2 and a common drain for outputting a third pull-up control signal PU_S2. The sixth PMOS transistor P6 and the sixth NMOS transistor N6, connected in series between the source voltage and the ground voltage, have a common gate for receiving an inverted third decoding signal and a common drain for outputting a third pull-down control signal PD_S2.
In the conventional ODT control device including the first to the third driving control units 10 to 30, if the first decoding signal S0 is a logic level ‘HIGH’, a termination impedance becomes 150Ω. If the first and the second decoding signals S1 and S2 are a logic level ‘HIGH’, the termination impedance becomes 75Ω. If all of the first to the third decoding signals S1 to S3 are a logic level ‘HIGH’, the termination impedance becomes 50Ω.
The conventional ODT control device further includes an ODT block (not shown) having a plurality of main termination units whose PMOS transistors and NMOS transistors are simultaneously turned on or off. Accordingly, in the conventional ODT control device, it is possible to adjust the termination impedance by controlling a pull-up impedance and a pull-down impedance of each PMOS transistor and each NMOS transistor provided in the plural main termination units based on the first to the third pull-up control signals PU_S0 to PU_S2, and the first to the third pull-down control signals PD_S0 to PD_S2.
However, during adjusting the termination impedance, the termination impedance is varied because the pull-up impedance and the pull-down impedance are varied according to other PMOS transistors or NMOS transistors which are simultaneously turned on or off. Accordingly, it is difficult to accurately detect an error occurring in the pull-up impedance of the PMOS transistors and the pull-down impedance of the NMOS transistors.
In addition, when there are changes in process, voltage and temperature, the PMOS transistors and the NMOS transistors exhibit different physical properties. As a result, operation of the PMOS transistors and the NMOS transistors should be appropriately varied according to the process, the voltage and the temperature. However, in the conventional ODT control device, it is difficult to test the operation so as to modify the termination impedance as intended.
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