This application claims the benefit of Korean Patent Application No. 2004-0071223, filed on Sep. 7, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a transmitter of a semiconductor device that can adjust and output signals to match the common mode level and amplitude of a connected circuit.
2. Description of the Related Art
FIG. 1 is a block diagram of a system including a conventional multi-port multimedia semiconductor device.
Referring to FIG. 1, the system 100 includes a first circuit block 110, a second circuit block 160, and a multi-port multimedia semiconductor device 140.
The semiconductor device 140 may be, for example, a memory device such as a DRAM. The semiconductor device 140 employs a specific signaling system for data communication with the first and second circuit blocks 110 and 160. An example of the data communication is disclosed in U.S. Patent Publication No. 2004/0137676, and the signaling system is defined by a direct current (DC) (or average) level and amplitude (or swing range) based on the DC level. The DC level is called as a common mode level.
To transmit data between the semiconductor device 140 and the first and second circuit blocks 110 and 160 at a high speed, the semiconductor device 140 and circuits of the first and second circuit blocks 110 and 160 include additional input/output (I/O) circuits 114, 115, 116, 118, 120, 141 through 148, and 161 through 164, which appropriately convert the signaling system of a connected I/O circuit to the signaling system of the semiconductor device 140 or the first or second circuit blocks 110 or 160. Each of the I/O circuits 114, 115, 116, 118, 120, 141 through 148, and 161 through 164 includes a transmitter (or an output buffer) and/or a receiver (or an input buffer).
The first circuit block 110 includes an audio input circuit 111, a video input circuit 112, a digital media processing circuit 113, an audio output circuit 117, and a video output circuit 119.
The audio input circuit 111 processes an audio input signal Ain and transmits the processed audio input signal to the I/O circuit 141 of the semiconductor device 140. The I/O circuit 141 converts the processed audio signal into a signal having the common mode level and the amplitude used by the semiconductor device 140.
The video input circuit 112 processes a video input signal Vin and transmits the processed video input signal to the I/O circuit 141 of the semiconductor device 140. The I/O circuit 141 converts the processed video signal into a signal having the common mode level and the amplitude used by the semiconductor device 140.
The digital media processing circuit 113 transmits/receives signals to/from the I/O circuits 141, 142 and 143 of the semiconductor device 140 via the I/O circuits 114, 115 and 116.
The audio output circuit 117 converts the common mode level and the amplitude of the signal transmitted from the I/O circuit 144 of the semiconductor device 140 using the external I/O circuit 118 and processes the signal having the converted common mode level and amplitude to output the signal as an audio output signal Aout.
The video output circuit 119 converts the common mode level and the amplitude of the signal transmitted from the I/O circuit 144 of the semiconductor device 140 using the internal I/O circuit 120 and processes the signal having the converted common mode level and amplitude to output the signal as a video output signal Vout.
The second circuit block 160 may be a circuit block having elements similar to the elements of the first circuit block 110, a memory device, or a memory controller. The second circuit block 160 includes the I/O circuits 161 through 164 used in communications with the I/O circuits 145 through 148 of the semiconductor device 140.
As described above, to transmit signals between the semiconductor device 140 and the first and second circuit blocks 110 and 160 at a high speed, additional I/O circuits converting a signaling system are required. Such additional I/O circuits may increase the cost of the entire system. Also, the number of additional I/O circuits is increased according to an increase in the number of circuits of the first and second circuit blocks 110 and 160, thereby increasing the cost of the system.
USPTO Backgrounds
USPTO Backgrounds