One of the common elements required in electrical circuit devices is the simple pull up (or pull down device) from an active device to one of the power supply buses. The pull up is simple if used to construct a circuit using discrete components in that all that is required is selecting a resistor of the desired resistance and tolerance, connecting it between an active device, such as an open collector transistor, and V.sub.CC and the transistor's output would be pulled up to V.sub.CC once the transistor is forward biased. With the advent of the integrated circuit (IC) however, fabricating a resistance onto a wafer substrate, such as silicon or gallium arsenide, takes special consideration particularly when resistivity and tolerances play an important part in circuit operation.
For example, as SRAMs have evolved from the small 4 Kb memory arrays to more densely packed array sizes, tolerances of pull up resistances had to be tightly controlled. In order to minimize standby current many fabrication processes adopted using an active device as the pull up. In CMOS fabrication it is common to see a PMOS transistor acting as the current path between a memory cell access transistor and the power supply bus. In this manner the PMOS could be gated on only when the desired line was to be pulled to V.sub.CC and turned off otherwise, thereby Virtually eliminating leakage current and minimizing standby current for the SRAM device as a whole.
The main drawback to using an active device for a pull up device is the amount of space required to fabricate the device. Now that the SRAM generation has grown to the 1 Mb array size, die space is a critical factor to consider, especially as arrays become even more dense. Technology has basically pushed all types of ICs to be more densely packed and pull ups are a common element in many circuit designs.
The present invention introduces a unique method to fabricate a self-aligned vertical intrinsic resistance, having low leakage properties, to replace an active device pull up while requiring less die space.
USPTO Backgrounds
USPTO Backgrounds