Generally, through silicon vias may be formed in a semiconductor substrate in order to provide electrical connections to a backside of the semiconductor substrate. By providing such an electrical connection, the possibility of connecting the semiconductor substrate may be expanded beyond electrical connections located on only a single side of the semiconductor substrate as in previous generations of semiconductor processes. This expansion allows for, among other things, a three-dimensional stacking of semiconductor dies, with connections going through the through silicon vias and providing power, ground, and signal lines throughout the three-dimensional stack.
To form the through silicon vias, an opening may be formed on an active side of the semiconductor substrate, wherein the opening extends into the semiconductor substrate further than active devices located in or on the semiconductor substrate. These openings may then be filled with a conductive material. After the openings have been filled, the backside of the semiconductor substrate may be thinned through, e.g., a chemical mechanical polishing (CMP) or etching process in order to expose the conductive material, thereby leaving a planar surface between the conductive material and the surrounding materials. A conductive glue layer may then be formed over the planar surface in order to provide an interface between the through silicon via and a contact to be formed.
However, the relatively smaller diameter of the through silicon via in relation to the contact can cause a non-uniform current distribution known as current crowding to occur at the interface between the through silicon via and the glue layer. This current crowding, in addition to being a problem in itself, can also induce electromagnetic failure and cause the formation of hillocks and voids within the structure.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
USPTO Backgrounds
USPTO Backgrounds