1. Field of the Invention
The present invention relates to intellectual property (IP) cores. In one example, the present invention relates to methods and apparatus for generating optimized IP cores in a secure manner.
2. Description of Related Art
Programmable chips can be implemented in a variety of ways. In some examples, designers can provide complete hardware descriptor language files to allow configuration of logic and circuitry on a programmable device. In some instances, designers can write these hardware descriptor language files from scratch. However in many instances, designers are aided by the use of IP cores available from logic libraries provided with a programmable chip. The IP cores are generally tested and debugged blocks of logic that can be used for specific purposes to simplify implementation on a programmable chip.
In some instances, the IP cores are static and a user simply selects the static core, such as a counter, from a library for use in a hardware design. Although the counter may not be customizable for a particular user's needs, several counters may be available in a library and a designer can select the appropriate counter for a particular design. Some IP core libraries include parameterizable IP cores. The parameterizable IP cores can be more specifically configured based on particular user needs. For example, a user may select a 4-bit counter or an 8-bit counter. Alternatively a user may select whether a counter rolls over.
Furthermore, IP cores can be provided in presynthesized form to allow even greater ease-of-use for a particular designer. However, each of these techniques for providing logic has associated drawbacks. Consequently, it is desirable to provide improved mechanisms for providing and generating IP cores for implementation on a programmable chip.
USPTO Backgrounds
USPTO Backgrounds