The present invention relates to a step-down voltage output circuit used in a semiconductor integrated circuit.
Referring to FIG. 2 and FIG. 9, a step-down voltage output circuit using a charge pump circuit of a conventional example will be described. FIG. 9 is a block diagram of the step-down voltage output circuit using the charge pump circuit in the conventional example. FIG. 9 shows an oscillating circuit 1 which oscillates at a predetermined frequency and outputs a clock signal V1, a control logic 2 which receives the clock signal V1 as an input signal, a P-channel MOS transistor 3 (hereinafter referred to as “M1”), an N-channel MOS transistor 4 (hereinafter referred to as “M2”), an N-channel MOS transistor 5 (hereinafter referred to as “M3”), an N-channel MOS transistor 6 (hereinafter referred to as “M4”), a capacitor 7 having a capacity of C1, an inverter circuit 8 (hereinafter referred to as “INV1”), a power supply voltage applying terminal 9 (hereinafter referred to as “VCC terminal”. The power supply voltage applied to the VCC terminal is defined as VCC) and a step-down voltage output terminal 10 (hereinafter referred to as VSUB terminal).
FIG. 2 is a view for showing the timing of operations of the step-down voltage output circuit using the charge pump circuit in the conventional example. To generate step-down voltage output voltage in the step-down voltage output circuit configured as shown in FIG. 9, the operation timings T3→T1→T3→T2→T3 forming one cycle need to be repeated. The operations in each timing T1, T2 and T3 will be described below.
Firstly, when the voltage VCC is applied from the VCC terminal 9, the oscillating circuit 1 starts self-oscillation and outputs the clock signal V1.
The clock signal V1 is an input signal of the control logic 2. The control logic 2 output signals V2 and V4 for controlling the ON/OFF operation of the M1, M2, M3 and M4. The signal V2 is an input signal of the INV1. The INV1 outputs the signal V3 of the inverted polarity to the signal V2.
During the operation timing T1, as the V2 is LOW, the V3 is HIGH and the V4 is LOW in polarity, the M1 is turned ON (operating state), the M2 is turned ON (operating state) and the M3 and M4 are turned OFF (non-operating state).
In this state, as one electrode of the capacitor 7 is connected to the VCC terminal and other electrode thereof is connected to the ground (hereinafter referred to as “GND”), the capacitor 7 is charged at a time constant determined by an ON resistance R1 of the M1 and capacity C1 of the capacitor 7 (hereinafter the voltage charged to the capacitor 7 is defined as “VC”). The voltage VC is substantially equal to the power supply voltage VCC.
During the operation timing T2, as the V2 is HIGH, the V3 is LOW and the V4 is HIGH in polarity, the M1 is turned OFF (non-operating state), the M2 is turned OFF (non-operating state) and the M3 and M4 are turned ON (operating state).
In this state, as one electrode of the capacitor 7 is connected to GND and other electrode thereof is connected to the VSUB terminal, the voltage charged during the operation timing T1 is discharged and step-down voltage −VC (=−VCC) is output to the VSUB terminal.
During the operation timing T3, as the V2 is HIGH, the V3 is LOW and the V4 is LOW in polarity, the M1, M2, M3 and M4 are turned OFF (non-operating state).
When the LOW period of the control signal V2 and the HIGH period of the control signal V4 are made to come close each other, the switching from LOW to HIGH in V2 and the switching from HIGH to LOW in V4 are delayed due to the effect of parasitic capacity consisted between gate electrodes of the M1 and M3 and substrate, and the M1 and M3 are turned ON (operating state) simultaneously, so that a pass-through current is passed between VCC and GND. For this reason, by putting the operation timing T3 for temporarily turning OFF all of the transistors at the shift from the operation timing T1 to the operation timing T2, the above-mentioned pass-through current is prevented from occurring.
By repeating the operation timings T3→T1→T3→T2→T3, the voltage charged to the capacitor 7 during the operation timing T1 eventually reaches VCC and the voltage of −VCC occurs in the VSUB terminal.
In the case where a semiconductor integrated circuit has such step-down voltage output circuit therein and feeds the substrate potential from the VSUB terminal, the circuit which is connected to the VSUB terminal and serves as a load of the step-down voltage output circuit can receive the power supply voltage −VC as well as the power supply voltage VC. For example, when an audio circuit is the load circuit, the output dynamic range of the audio circuit which receives the power supply voltage VC and −VC becomes larger twice as much as the circuit which receives only the power supply voltage VC.
However, in the conventional step-down voltage output circuit configured as mentioned above, when the VSUB terminal 10 is connected to the substrate potential, there causes a delay between activation of the power supply VCC and output of the clock signal V1 at a predetermined amplitude from the oscillating circuit 1. During the period between the time when the power supply VCC is activated and the time when the oscillating circuit 1 outputs the clock signal V1 at the predetermined amplitude and the charge pump circuit is operated fully according to the clock signal V1, the step-down voltage which is generated at the VSUB terminal 10 is a low voltage close to the GND potential. In addition, during the period, as the VSUB terminal 10 is connected to a drain terminal of the N-channel MOS transistor M4, the output impedance of the VSUB terminal 10 becomes high impedance and the substrate potential connected to the VSUB terminal 10 becomes unstable. As a result, the conventional step-down voltage output circuit has the disadvantage that a thyristor formed of parasitic elements on the load circuit of the substrate potential is triggered at activation, which tends to cause the damage of the circuit, that is, so-called latch-up phenomenon.
USPTO Backgrounds
USPTO Backgrounds