The present invention relates to interface circuits for timing signal generators with two non-overlapping phases, having a rectangular-type pulse waveform. More particularly, it relates to an interface circuit with field-effect transistors with MOS-type insulated gates that can be used in integrated digital circuits with two-phase logic, e.g., in digital tuning systems for TV receivers. An interface circuit for such timing signal generators which is capable of being coded according to a binary logic scheme mainly has the function of uncoupling the user circuit which is controlled by the timing signals generated by the generator, in order to avoid reactions tending to modify the logic levels of the generated signals, and for supplying the necessary signal power required by the user circuit.
The interface circuits of the prior art which comprise field-effect transistors usually employ final stages that include a capacitor called "bootstrap capacitor" by those skilled in the art and which enables one to improve the time response of the system.
A final stage of this type can be simply formed by two transistors connected in series with the source and the drain electrodes between the two terminals of a supply voltage generator and having the gate electrodes coupled to an input terminal of the circuit which is connected to the timing signal generator by which they are switched on in phase opposition. The gate electrode of the transistor connected to the positive terminal is coupled to the junction point of the two transistors by means of a bootstrap capacitor.
The junction point of the two transistors constitutes an output terminal of the circuit. The gate electrode of the transistor which is connected to the negative terminal is coupled to the input terminal by means of an inverter circuit. Hence, the ON or OFF states of the transistor correspond to low or high input signal levels to which can be associated, respectively, the logic binary values 0 and 1 according to positive logic.
Between the source and the drain electrodes of a field-effect transistor there is virtually a short circuit in the ON state and an open circuit in the OFF state. Therefore, one can still associate, again according to "positive logic", a logic binary value 0 or 1, respectively, with the potential level of the output terminal corresponding to an input 0 or 1. Thus, the logic level of the input signal is properly transmitted to the output, and the output signal also turns out to be a pulse-type waveform. The use of a bootstrap capacitor permits a reduction in the rise time of the leading edges of the pulses of the output signal, whose waveform can thus better resemble an ideal rectangular-type waveform.
As a matter of fact, if the bootstrap capacitor is properly charged prior to a changeover from 0 to 1 of the input signal, then, when the occurrence of the leading edge of an input pulse causes the transistor connected to the negative terminal to be turned off and causes the output level to become equal to the potential of the positive terminal, the potential of the gate electrode of the transistor which is connected to the positive terminal is brought to a higher level than that which would permit the coupling with the input and with the supply voltage itself.
Without a bootstrap capacitor, the voltage supplied to the gate electrode of the transistor which is connected to the positive terminal would be constant. Therefore, simultaneously with the raising of the potential of the output terminal, or of the source electrode of the transistor, there would be a gradual reduction of the gate-source voltage supplied to the transistor and, hence, a reduction of its conductivity, which would delay the transient of the output rise with an exponential-type shape.
The bootstrap capacitor, on the other hand, keeps the gate-source voltage substantially constant and, thus, permits for all of the switching transients a rise rate of "1" of the substantially constant output. The capacitor must then be discharged so as to not impede the subsequent transition from 1 to 0.
Thus, an interface circuit which utilizes a bootstrap capacitor in the final stage or stages included therein must also have appropriate means in order to charge or discharge the capacitor without interfering with the proper logic operation of the circuit.
For timing signal generators with two non-overlapping phases with a rectangular-type pulse waveform, having two separate output terminals, an interface circuit is formed with MOS-type field-effect transistors. Such an interface circuit is known to those skilled in the art and satisfies such requirements. This circuit comprises two separate identical twin circuits, each having an input terminal for connection to the signal generator, and an output terminal for connection to a user circuit of such signals.
FIG. 1 shows one of such identical circuits which comprises a final stage formed by a first transistor, Q.sub.1, and a second transistor, Q.sub.2, respectively of the "enhancement" and the "depletion" type, and which are connected in series between the positive terminal, +V.sub.CC, and the negative terminal, -V.sub.CC of a supply voltage generator.
The source electrode of Q.sub.1 is connected to -V.sub.CC and the drain electrode of Q.sub.2 is connected to +V.sub.CC. The drain electrode of Q.sub.1 and the source electrode of Q.sub.2 are connected together in a circuit node which constitutes an output terminal U.sub.1.
The circuit shown in the figure has an input terminal, A, for connection to a timing signal generator. Said terminal is connected to the gate circuit of Q.sub.1 via a first inverter circuit, I.sub.1, a second inverter circuit, I.sub.2, and a third inverter circuit, I.sub.3.
The gate electrode of Q.sub.2 is connected to the output circuit node by means of a bootstrap capacitor, C.sub.1.
The circuit comprises a third transistor, Q.sub.3, and a fourth transistor, Q.sub.4, respectively of the enhancement and the depletion type.
The source electrode of Q.sub.3 is connected to -V.sub.CC, the drain electrode of Q.sub.4 is connected to +V.sub.CC. The drain electrode of Q.sub.3 and the source electrode of Q.sub.4 are connected to a circuit node formed by the junction point between the gate electrode of Q.sub.2 and the capacitor C.sub.1.
The gate electrode of Q.sub.3 is connected to the output of the first inverter circuit I.sub.1 ; the gate electrode of Q.sub.4 is connected to the output of a logic NOR circuit, N.sub.1, having a first input which is connected to the input terminal A of the circuit by means of a fourth inverter circuit, I.sub.4, and having a second input which is connected to the output of the second inverter circuit I.sub.2.
Let us now consider in particular the operation of one of the twin circuits, the operation of the other being identical.
Assume, first, that the level of the input signal is low, that is, it corresponds to the logic value 0, and that Q.sub.1 and Q.sub.3 are switched on, the values of the outputs of I.sub.1 and I.sub.3 being equal to 1; in these conditions, the bootstrap capacitor C.sub.1 is assuredly discharged and Q.sub.2 is turned off; therefore, the potential level of the output corresponds to the logic value 0.
We observe that, since the value of the output of I.sub.4 is 1, the output of the logic circuit N.sub.1 must, of necessity, also be 0; therefore, Q.sub.4 is also conducting very little (i.e., it has the lowest conductivity that can be achieved with the source electrode at 0 and the gate electrode at a non-negative potential), and C.sub.1 cannot be charged.
When the level of the input signal switches to the logic value 1 upon the appearance of the leading edge of a pulse, the outputs of I.sub.1 and I.sub.4 fall simultaneously to the 0 level.
Since the output level of I.sub.2 rises to 1 only after a certain time interval, due to analogic delays of the inverter circuit, during all this time interval, both inputs of the NOR circuit, N.sub.1, have the logic value 0. Thus, the output takes on the value 1 and brings about the conduction of Q.sub.4 for said period of time.
Since Q.sub.3 is already turned off and since the output is still at 0, the bootstrap capacitor C.sub.1 is charged through Q.sub.4 to a voltage close to that of the supply voltage.
As soon as the output of I.sub.2 rises to 1, N.sub.1 turns off Q.sub.4, but C.sub.1 remains charged, since Q.sub.3 continues to turn off.
With a given delay, the output of I.sub.3 drops to the 0 level, turning off Q.sub.1. The potential level of the circuit output starts to rise, raising at the same time the gate potential of Q.sub.2 beyond the level of +V.sub.CC by means of the bootstrap capacitor, which keeps the gate-source voltage Q.sub.2 substantially constant.
Since the conductivity of a depletion-type transistor, having a negative threshold voltage, is essentially higher upon increasing the positive voltage supplied to the gate, the potential of the output U.sub.1 of the circuit rises to the 1 level with a very brief transient. Then, upon the occurrence of the trailing edge of the signal pulse, the input A switches to 0, the outputs of I.sub.1 and I.sub.4 rise simultaneously to 1, bringing about the conduction of Q.sub.3 which permits the unloading of C.sub.1 and the turn-off of Q.sub.2, and confirming the 0 value of the output of the NOR circuit which causes Q.sub.4 to remain turned off. With a given delay, due to similar delays of I.sub.2 and I.sub.3, whose outputs change over to, respectively, 0 and 1, Q.sub.1 is turned on and the potential of the output U.sub.1 drops to the 0 level, restoring the initial conditions.
The prior art interface circuit described in FIG. 1 ensures a rapid switching of the output, thus producing signal pulses having a shape which closely resembles rectangular-type pulses.
However, the presence of several serially connected circuits produces non-negligible signal delays between their inputs and outputs. Moreover, since the time available for the charging of the bootstrap capacitor is very brief, which is effected by making use of analogic delay in the inverter circuits, high load-current levels are needed with more expensive sizing of the circuit components.
More noise and a greater heat dissipation correspond to higher current flows in the metal connections and in the junctions of the integrated device. Precisely because of such considerable heat dissipation, the high-frequency operating temperature, which often approaches or exceeds the levels at which the junctions deteriorate or are destroyed, causes the reliability of the device to quickly diminish.
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