Since silicon carbide (hereinafter referred to as “SiC”) has a larger band gap compared to silicon (hereinafter referred to as “Si”) and is excellent in physical properties such as dielectric breakdown field intensity, saturated electron velocity, and thermal conductivity, it has a superior nature as a material for semiconductor power devices. Especially, because significant reduction in power loss, downsizing and the like are possible with a SiC power device resulting in realizing energy saving at conversion for electric power supply, it has possibility of becoming a key device in realizing low carbon society such as improving electric vehicle performance and improving solar cell system function.
When manufacturing a SiC power device, epitaxial growth of a semiconductor device active area in advance on a SiC bulk substrate with a thermal CVD method (thermal-chemical vapor deposition method) or the like is indispensable. Here, the active area means a cross sectional area that is planned to be manufactured by finely controlling doping density in a crystal and a film thickness and that includes a growth direction axis. Such an epitaxial growth layer is necessary in addition to the bulk substrate because the doping density and the film thickness are almost specified by a device design specification and also because finer controllability is usually required compared to that in bulk substrate doping density.
Hereinafter, a wafer of a SiC bulk substrate on which an epitaxial growth layer is formed is referred to as an epitaxial wafer. Since a SiC device is manufactured by performing various processes on an epitaxial wafer, a rate of the number of devices having intended characteristics manufactured from one wafer, that is what is called a yield of semiconductor devices, depends strongly upon electrical characteristic uniformity of the epitaxial growth layer. That is, if there exists a local area whose dielectric breakdown field is smaller than that in another area or which carries a relatively large electric current by applying a predetermined voltage in the epitaxial wafer, a device containing such an area has, for example, an inferior withstand voltage characteristic among its characteristics and there arises a problem of flowing what is called a leakage current even if the applied voltage is relatively small. In other words, a factor primarily rules the yield of semiconductor devices is crystallographic uniformity of the epitaxial wafer. As a uniformity impeding element, there is known a presence of various what is called leakage current defects caused by a problem during the epitaxial growth.
A common characteristic of the above described crystal defects is that periodicity of an atomic arrangement in the crystal is locally imperfect along a crystal growth direction. As a defect generated by the SiC epitaxial growth, a leakage current defect called as a carrot defect, a triangular defect, or the like is known based on its surface shape characteristic.
As a method for preventing generation of such defects, there is described in Patent Document 1, for example, a method of growing an epitaxial growth layer between a bulk substrate and an active layer at a typical growth temperature of less than 1500 degrees C. in order to inhibit defects generation.
Also, there is described in Patent Document 2, for example, an embodiment of obtaining an epitaxial wafer having average basal face dislocation density of 20 pieces/cm2 by 40 minutes hydrogen etching under a condition of a temperature of 1400 degrees C. and a pressure of 30 Torr (4.0 kPa) and further by an epitaxial growth under a 150 degrees C. increased temperature and a relatively increased pressure of 42 Torr (5.6 kPa).
It is well known that specific periodicity called as polytype exists in SiC crystal. That is, while a stoichiometric ratio of Si and C is 1:1 and a crystal lattice has a hexagonal closest packing structure, there exists another kind of periodicity in an atomic arrangement along c-axis of the present structure. Physical properties of SiC are specified by a period in an atomic scale and symmetry of the crystal lattice. A type called 4H—SiC now receives the most attention from a standpoint of device application. In a power device using 4H—SiC, from a standpoint of mainly reducing a raw material cost, mainly used is an epitaxial wafer that has a top surface tilted no more than around 5 degrees in a <11-20> direction from a <0001> face and employing a face where Si atoms can be more stably arranged than C atoms.
In such an epitaxial wafer, asperity having a difference of elevation of several nano-meters usually appears on a wafer surface parallel to a <1-100> direction. The asperity of the surface shape is called as step bunching. In a case of step bunching existence, an electrical carrier induced by an electric field etc. near an epitaxial growth layer surface becomes a direct potential barrier when the carrier moves in a direction not parallel to the step bunching in a face parallel to the surface. That is, mobility or electrical conductivity decreases and device characteristics are degraded. Therefore, when the step bunching exists, a problem arises that uniformity of the electrical conductivity in the wafer face is degraded. Accordingly, when the step bunching exists, in a device such as MOS type in which a carrier is induced near an epitaxial growth layer surface, flexibility of concrete device structure in design and manufacture stages is significantly restricted.
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