Traditional techniques for fabricating semiconductors include chemical vapor deposition (“CVD”), which is used typically to deposit relatively thin films onto semiconductor substrates to form electronic devices. Generally, CVD provides relatively enhanced step coverage over topologies and features over which a film is deposited. By contrast, other traditional deposition techniques may provide less desirable step coverage than CVD. To illustrate, consider the structure in FIG. 1. Diagram 100 includes a semiconductor substrate 140 over which an insulator structure 130, an electrode structure 120 (e.g., a bottom electrode), and insulator structures 110a and 110b are formed consecutively. Less than desirable step coverage in some traditional deposition processes can form voids 112 inadvertently in aperture features between, for example, insulator structures 110a and 110b. Voids 112 may form when vertical features (e.g., trench walls) have less thickness than horizontal features. Such voids 112 can degrade electrical performance of an electronic device, among other things.
While functional, there are a variety of drawbacks associated with CVD process techniques. One drawback is that CVD may generate a relatively significant amount of defects and imperfections in the crystalline structure of the deposited film, thereby degrading electrical performance. Further, CVD processes may use or produce hazardous precursor gases and byproducts, thereby requiring additional processing steps to ensure safety, which, in turn, increases costs and consumes resources. In the semiconductor memory industry, such additional processing steps can increase the cost of a memory device more than otherwise might be the case.
In view of the foregoing, it is be desirable to provide a method for overcoming the drawbacks of the conventional deposition processes to deposit non-metal layers to form, for example, a chalcogenide-based film.
USPTO Backgrounds
USPTO Backgrounds