Decreasing the dimensions of semiconductor devices and increasing the level of their integration are two of the major trends in the current semiconductor device manufacturing. As a result of these trends, the density of elements forming a semiconductor device continuously increases.
Generally, an integrated circuit includes one or more levels of metal lines to connect the electronic devices of the IC to one another and to external connections. An interlayer dielectric is placed between the metal levels of the IC for insulation.
Typically, an IC fabrication process includes a front end of line (FEOL) portion and a back end of line (BEOL) portion. The FEOL portion refers to a first stage of the IC fabrication where the individual devices (e.g., transistors, capacitors, resistors) are patterned in the semiconductor wafer. The BEOL refers to a second stage of the IC fabrication where the individual devices are interconnected with a wiring on the wafer. Generally, BEOL involves forming contacts (e.g., pads), interconnect wires (e.g., one or more levels of metal lines), vias, insulating layers (dielectrics), and bonding sites for chip-to-package connections.
To increase the level of the device integration, three dimensional integrated circuits (3D ICs) are created by interconnecting wafers, dies, or both vertically using through silicon vias (TSVs) to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. Typically, the traditional 3D IC fabrication techniques complicate the integration process and are costly.
USPTO Backgrounds
USPTO Backgrounds