To satisfy excellent performance and low cost, it is required to increase a degree of integration in semiconductor devices. Particularly, a degree of integration in memory devices is an important factor for determining the prices of products. In typical Two-Dimensional (2D) memory devices, a degree of integration is mainly determined in proportion to the occupied area of memory cells, which is affected by the level of fine pattern forming technology. However, since high-cost equipment is required for reducing pattern size, a degree of higher integration in 2D semiconductor memory devices may become limited.
To overcome these limitations, Three-Dimensional (3D) memory devices including three-dimensionally arranged memory cells are being proposed. For mass production of the 3-D memory devices, however, a process technology which reduces manufacturing costs per bit relative to 2-D memory devices and realizes reliable product characteristic is required.
USPTO Backgrounds
USPTO Backgrounds