The present invention relates to semiconductor integrated circuits, including semiconductor memory devices and microprocessors, and particularly to their output buffer circuits.
With regard to the operation of conventional output buffer circuitry in semiconductor integrated circuit devices, switching noise has become a serious problem. The cause of this problem is the occurrence of a transient abrupt fluctuation in current due to rapid charging and discharging of a large capacity external load. Generally, a final stage output transistor in an output buffer circuit is designed to satisfy a particular specification for I.sub.OH (high level output current) or I.sub.OL (low level output current), so a relatively large capacity output transistor is used. Such a large capacity output transistor provided with a large driving capacity, once it starts its operation, tends to bring about a large current fluctuation because of its extremely large current increase rate in a time elapsed, thereby becoming a large noise source. Further, when an output transistor becomes larger in capacity, in particular, in the case of a MOS transistor, its gate input capacitance will increase, and in the case of a bipolar transistor, its capacitance between the base and emitter will increase. Therefore, the time lag from the start of a driving operation in the driver section to the start of a driving operation in the output transistor becomes greater, which causes an increase in the delay time. Therefore, in order to obtain a high speed and low noise output buffer circuit, it is necessary to control a driving state in such an output transistor.
As a means for controlling the driving state of output transistors in the prior art, a parallel connection of one set of output transistors has been provided, with their driving operation lagging the other output transistors in time by using a delay circuit, as discussed in Japanese Patent Laid-Open No. 62-220026 (1987).
An example of the above prior art technology is shown in FIG. 1. One of the problems associated with this prior art technology is that because output transistors (M57 and M68) connected to driving circuits (I7 and I10) provided with delay circuits (D1 and D2) inevitably are delayed in the start of their driving operation, it is difficult to increase the speed of operation in the buffer circuits. Another problem arising from such an arrangement to set on a non-conduction state all at once in the output transistors (M57 and M58 or M67 and M68) connected in parallel is that insufficient consideration has been given to the fact that there occurs an abrupt decrease in current, because of a rapid transition from the on-state to the off-state in the output transistors, thus causing a greater noise.
USPTO Backgrounds
USPTO Backgrounds