The present invention relates to a semiconductor chip embedded with a test circuit.
As semiconductor device manufacturing technology has developed, semiconductor packages having semiconductor devices have been increasingly capable of processing an increased amount of data.
Semiconductor packages are manufactured through a semiconductor chip manufacturing process for manufacturing semiconductor chips on a wafer made of silicon with high purity, a die sorting process for electrically inspecting the semiconductor chips, and a packaging process for packaging good quality semiconductor chips.
In semiconductor packages, it is the norm that electrical connections are formed using metal wires.
However, use of metal wires may introduce problems in the semiconductor packages. For example, there may be degradation of signal integrity due to close proximity of the metal wires. Therefore, to help suppress the electrical characteristics of the semiconductor packages from being degraded, and enable the miniaturization of the semiconductor packages, there has been increasing use of through-electrodes.
In semiconductor packages using the through-electrodes, the electrical degradation of the semiconductor packages is substantially prevented, operation speeds of the semiconductor chips are improved, and it is possible to achieve further miniaturization of the semiconductor packages.
In general, a semiconductor chip using through-electrodes has an increased number of pads when compared to a semiconductor chip not using through-electrodes. This resulting pitch decrease may present problems. For example, when performing a test, an existing probe type may encounter difficulties because a semiconductor chip may have too fine a pitch. In particular, in a wafer having memory chips for high speed operation, since several hundreds or several thousands of pads are internally connected with one another, it may be impossible to separately perform tests for electrical connections between the pads and the through-electrodes.
Efforts have been made to manufacture separate test boards. However, this may lead to problems such as excessive lead time and cost to manufacture the test equipment.
USPTO Backgrounds
USPTO Backgrounds