1. Field of the Invention
This invention relates to a solid-state electronic image sensing device having a number of photodiodes formed in row and column directions, vertical transfer paths formed adjacent to photodiodes in the row direction and in which vertical transfer electrodes have been formed, and transfer gates for transferring signal charge, which has accumulated in the photodiodes, to the vertical transfer paths.
2. Description of the Related Art
In digital still cameras and the like having a solid-state electronic image sensing device such as a CCD as image sensing means, image data having a high image quality needs to be obtained when the image data is recorded on a recording medium. Such high-quality image data is not necessarily required at the time of autoexposure (AE), autofocus (AF) and when shooting a subject for the purpose of displaying the image of the subject on a display device provided on the digital still camera.
Greater numbers of pixels are being used to construct solid-state image sensing devices. When the number of pixels is not that large, the device is driven by the same drive method regardless of whether the camera is performing autoexposure or autofocus, shooting a picture of a subject or recording a video signal representing the image of the subject on a recording medium.
With the trend toward use of greater numbers of pixels in solid-state electronic image sensing devices, however, driving the solid-state electronic image sensing device by the same drive method at all times means that signal processing such as AE and AF processing and processing for displaying the image of the subject on the display device cannot be performed in rapid fashion. As a consequence, image data representing the image of a subject cannot be recorded on the recording medium promptly, possibly resulting in the loss of photographic opportunities.
Though it has been contemplated to subsample the video signal output by the solid-state electronic image sensing device to thereby reduce the quantity of video output by the solid-state electronic image sensing device and speed up image processing, it is difficult to raise the degree of subsampling.
Accordingly, an object of the present invention is to raise the degree of subsampling.
According to the present invention, the foregoing object is attained by providing a solid-state electronic image sensing device having a number of photodiodes formed in row and column directions, vertical transfer paths formed adjacent to photodiodes in the row direction and in which vertical transfer electrodes have been formed, and transfer gates for transferring signal charge, which has accumulated in the photodiodes, to the vertical transfer paths, wherein signal lines for applying gate pulses to the transfer gates are connected so as to apply gate pulses simultaneously to transfer gates for photodiodes of (n+1)th, (n+5)th and (n+13)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of an (n+2)th row, apply gate pulses simultaneously to transfer gates for photodiodes of (n+3)th, (n+7)th, (n+11)th and (n+15)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of (n+4)th, (n+8)th, (n+12)th and (n+16)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of (n+6)th, (n+10)th and (n+14)th rows, and apply gate pulses simultaneously to transfer gates for photodiodes of an (n+9)th row.
The present invention provides also an operation control method suited to the above-described solid-state electronic image sensing device. Specifically, the present invention provides a method of controlling the operation of a solid-state electronic image sensing device having a number of photodiodes formed in row and column directions, vertical transfer paths formed adjacent to photodiodes in the row direction and in which vertical transfer electrodes have been formed, and transfer gates for transferring signal charge, which has accumulated in the photodiodes, to the vertical transfer paths, comprising the steps of: applying gate pulses simultaneously to transfer gates for photodiodes of (n+1)th, (n+5)th and (n+13)th rows; applying gate pulses simultaneously to transfer gates for photodiodes of an (n+2)th row; applying gate pulses simultaneously to transfer gates for photodiodes of (n+3)th, (n+7)th, (n+11)th and (n+15)th rows; applying gate pulses simultaneously to transfer gates for photodiodes of (n+4)th, (n+8)th, (n+12)th and (n+16)th rows; applying gate pulses simultaneously to transfer gates for photodiodes of (n+6)th, (n+10)th and (n+14)th rows; and applying gate pulses simultaneously to transfer gates for photodiodes of an (n+9)th row.
Subsampling so as to halve the amount of data is achieved by applying gate pulses to transfer gates for photodiodes in odd- or even-numbered rows. Interlacing is achieved by alternating the application of gate pulses to transfer gates for the photodiodes in the odd-numbered rows with the application of gate pulses to transfer gates for the photodiodes in the even-numbered rows.
Subsampling to halve the amount of data can be achieved even if gate pulses are applied simultaneously to the transfer gates for photodiodes in two rows among (m+1)th, (m+2)th, (m+3)th and (m+4)th rows in odd-numbered fields and simultaneously to transfer gates for photodiodes of (m+1)th, (m+2)th, (m+3)th and (m+4)th rows in even-numbered fields with the exception of those transfer gates of rows to which gate pulses were applied in the odd-numbered fields.
Subsampling to halve the amount of data can be achieved also by applying gate pulses simultaneously to transfer gates for photodiodes in two rows among (m+1)th, (m+2)th, (m+3)th and (m+4)th rows regardless of whether rows are odd- or even-numbered.
Subsampling to reduce the amount of data to one-fourth can be achieved by applying gate pulses simultaneously to transfer gates for photodiodes in one row of (m+1)th, (m+2)th, (m+3)th and (m+4)th rows.
Subsampling to reduce the amount of data to one-eighth can be achieved by applying gate pulses simultaneously to transfer gates for photodiodes of (n+2)th and (n+9)th rows.
USPTO Backgrounds
USPTO Backgrounds