Recently, in accordance with the development of smart devices, specifications of the respective components thereof have increased. Particularly, specifications of an application processor (AP), a core integrated circuit (IC) of a smart device, have been rapidly developed. In order to satisfy such high specifications, an AP package and a memory package have recently been used in a package-on-package (POP) manner.
Meanwhile, recently, a size of the AP package has been decreased, and the number of inputs/outputs (I/Os) of a memory has increased. Therefore, all balls connected to a memory package may not only be disposed in a fan-out region of the AP package. Therefore, an interposer may be disposed between the memory package and the AP package to connect the memory package and the AP package to each other or a separate backside redistribution layer may be formed on a top surface of the AP package to connect the AP package to the memory package.
In addition, a power management IC (PMIC) is disposed on a printed circuit board, separately from the AP package and the memory package as described above, to manage power.
USPTO Backgrounds
USPTO Backgrounds