1. Field of the Disclosure
This Disclosure relates generally to testing intellectual property (IP) cores via a test structure called a wrapper. The wrapper resides at the boundary of a core and provides a way to test the core and interconnections between the cores. Particularly, the Disclosure relates to a test architecture for accessing wrappers within an integrated circuit.
2. Description of Related Art
FIG. 1 illustrates the test structure of a prior art wrapper 100. The wrapper includes test interface signals 109, an instruction register 105, and set of data registers 106-108. The instruction register is a register accessed by the test interface signals to load test instructions that control the operation of the wrapper, in particular the instructions control the selection of a data register and control the mode of operation of the selected data register. The selected data register may be accessed by the test interface to shift test data in and out of the wrapper. The set of data registers shown in FIG. 1 includes; (1) an internal scan register 108 for testing the core circuitry, (2) a boundary scan register 107 for controlling the inputs and outputs of the core during testing, and (3) a bypass register 106 for bypassing the wrapper via a single bit. Any number of additional user defined data registers may be included in the set of data registers of the wrapper, such as data registers supporting core emulation and programming operations as described in the referenced patent application Ser. No. 09/864,509.
The test interface 109 includes; (1) a clock signal for timing wrapper shift and test operations, (2) a shift signal for enabling data to be shifted through the wrapper from the serial input (SI) to the serial output (SO), (3) a capture signal for causing data to be captured into the instruction register or a selected data register, (4) an update signal for causing data to be output from the instruction register or a selected data register, (5) a reset signal for initializing the wrapper's instruction and data registers, and (6) a select signal for selecting data to be shifted through either the instruction register from SI to SO, or through a selected data register from SI to SO.
In the example of FIG. 1, the test interface signals are simply gated, via AND gates (A), by the select signal to either allow them to be coupled to the instruction register or to the data registers. Other coupling methods may be used, but gating is used in this example. As can be seen, when select is high, gates 101 couple the test interface signals to the instruction register and the serial output of the instruction register is coupled to SO via multiplexer 103. In this configuration, the instruction register may be shifted via SI and SO for instruction loading/unloading. When select is low, gates 102 couple the test interface signals to the data registers and the serial output of the selected data register, as determined by the instruction loaded in the instruction register, is coupled to SO via multiplexers 104 and 103. In this configuration, the selected data register may be shifted via SI and SO for data loading/unloading.
As one skilled in the art of testing will see, the IEEE P1500 wrapper architecture is similar to the IEEE 1149.1 boundary scan architecture. The main difference between the P1500 wrapper architecture and 1149.1 boundary scan architecture is that the P1500 wrapper architecture accesses the instruction and data registers using discrete test interface signals 109 rather than accessing the instruction and data registers using the 1149.1's test access port (TAP) state machine interface. Thus P1500 wrappers are free of 1149.1 TAP interfaces.
FIG. 2 illustrates a core 201 equipped with the wrapper 100 of FIG. 1. The test interface signals 109 of FIG. 2 are indicated as Control (CTL), and SI and SO are indicated as labeled in FIG. 1. As the name implies the wrapper simply wraps around the core to provide a test access mechanism local to the core's input/output boundary. The instruction register 105, bypass register 106, and boundary register 107 are part of the wrapper. The internal scan register 108 is part of the core circuitry that may be accessed via the wrapper for testing the core.
FIG. 3 illustrates a prior art method of connecting three individual wrappers 307-309 of cores 1-3 onto a single scan chain arrangement 301. The wrapper arrangement 301 will exist inside an IC. The serial inputs of the wrappers 307-309 are indicated as SI-1, SI-2, SI-3. The serial outputs of the wrappers 307-309 are indicated as SO-1-, SO-2, and SO-3. The test interface signals 109 are bussed to the CTL-1, CTL-2, and CTL-3 inputs of wrappers 307-309. As seen in FIG. 3, the arrangement 301 scan chain passes serially through the wrappers 307-309 from SI 302 to SO 303. In this arrangement, all wrappers 307-309 can be controlled to load instructions via the SI 302 and SO 303 scan path, or all wrappers 307-309 can be controlled to load data via the SI 302 and SO 303 scan path. Access to the SI 302, SO 303, and test interface signals 109 of the arrangement 301 is typically provided to tester external of the IC.
FIG. 4 illustrates the wrapper design of FIG. 1 being modified to include an enable/disable capability. The modification includes adding an enable signal 402 and adding circuitry 401 (i.e. the OR (O) gate, AND (A) gate, and an inverter), responsive to the enable signal 402 to cause the wrapper to either be enabled to respond to the test interface 109 or be disabled from responding to the test interface 109. In this example, a low on enable 402 will disable the wrapper from responding to the test interface 109 and a high on enable 402 will enable the wrapper to respond to the test interface 109.
FIG. 5 illustrates an alternate method of enabling/disabling wrappers. In this example, it is assumed the wrapper design is fixed (hard) and cannot be modified, as could the wrapper design of FIG. 4. With a fixed wrapper design, the enabling/disabling capability must be external of the wrapper. In FIG. 5, gating circuitry 501 is inserted into the test interface 109 signal path to the wrapper and an enable signal 502 is added and connected to the gating circuitry to either enable the test interface signals 109 to be input to the wrapper or disable the test interface signals 109 from being input to the wrapper. In this example, a low on enable 502 will disable the wrapper from receiving the test interface signals and a high on enable 502 will enable the wrapper to receive the test interface signals. The use of wrapper enable signals, while not necessarily as shown in the examples of FIGS. 4 and 5, is known.
The IEEE P1500 standard will define the connections to a wrapper test structure for an individual core of an IC. The standard leaves open the interconnection of the wrappers around multiple cores and the interconnection of wrappers around hierarchically arranged cores within cores.
USPTO Backgrounds
USPTO Backgrounds