Complementary metal-oxide-semiconductor (CMOS) circuits include n-channel field effect transistors (nFETs), in which electron carriers are responsible for conduction in the channel, and p-channel field effect transistors (pFETs), in which hole carriers are responsible for conduction in the channel. CMOS circuits have been traditionally fabricated on silicon wafers having a single crystal orientation, ordinarily a (100) crystal orientation. Electrons have a higher mobility in silicon characterized by a (100) crystal orientation in comparison with silicon of a (110) crystal orientation. In contrast, holes have higher mobility in silicon characterized by a (110) crystal orientation in comparison with silicon of a (100) crystal orientation.
In recognition of this ability to optimize transistor performance, hybrid orientation technology (HOT) has evolved to produce hybrid substrates characterized by device regions of different crystal orientations that are carried on a common bulk substrate. Using such hybrid substrates, CMOS circuits can be fabricated with nFETs formed in silicon device regions of a (100) crystal orientation and pFETs formed in silicon device regions of a (110) crystal orientation. Consequently, the performance of the different transistor types in the CMOS circuit can be individually optimized.
Hybrid substrates may include bulk device regions and semiconductor-on-insulator (SOI) device regions having different crystal orientations or, under certain circumstances, having the same crystal orientation. Each of the SOI device regions is electrically isolated from the bulk substrate and also from adjacent bulk device regions. Latch-up may represent a significant issue for FETs fabricated using the bulk device regions of a hybrid substrate. For space-based applications, electron-hole pairs generated by high-energy ionizing radiation and particles (e.g., cosmic rays, neutrons, protons, alpha particles) may induce latch-up. Because the CMOS circuit cannot be easily replaced in space flight systems, chip failure induced by latch-up may prove catastrophic. Hence, designing hybrid substrates carrying bulk CMOS devices with a high tolerance to latch-up may be an important consideration for circuit operation in the natural space radiation, as well as in terrestrial environments for military systems and other high reliability commercial applications.
Various types of radiation events may cause latch-up or may cause circuit upset that may lead to latch-up. Single event effects (SEE) are caused by a single particle, typically an alpha particle having energies between 3 MeV and 7 MeV, and are generally a terrestrial event. An SEE type event can cause a single event upset (SEU) in which a single radiation particle upsets a storage circuit (e.g. SRAM, DRAM, latch, flipflop), or can cause a multi-bit upset (MBU). Either SEU or MBU events can lead to single event latchup (SEL). A single event transient (SET) results from a single radiation particle that causes a voltage transient, generally by hitting combinatorial logic. If the transient (or glitch) of the SET latches, it is sometimes termed an SEU. A single event functional interrupt (SEFI) arises from a single particle that causes a device to cease to function and switch to a standby mode. A single event gate rupture represents gate breakdown from a single particle striking the gate of a transistor. Total ionizing dose (TID) is a cumulative effect from trapped holes in oxide layers caused by electron-hole pairs generated by ionizing radiation. The electrons of the electron-hole pairs are mobile enough to escape the oxide layers, which leaves behind residual trapped holes that increase leakage or turn on parasitic devices in the transistors.
Despite the success of hybrid substrates for their intended purpose, improved design structures are needed to further enhance the latch-up resistance of integrated circuits built using hybrid substrates.
USPTO Backgrounds
USPTO Backgrounds