Traditionally, complementary metal-oxide-semiconductor (CMOS) type digital integrated circuits represent binary states by means of voltage levels. Specifically, a binary state of "one" is represented by a voltage level of five volts with respect to a circuit ground potential level; and, a binary state of "zero" is represented by a voltage level of zero volts with respect to the circuit ground potential level. The use of such a system of representation is advantageous in that circuits in conformance therewith are relatively simple to implement, since no external reference is required. Further, such a system is advantageous in that circuits in conformance therewith need dissipate relatively little static power, since relatively little current is required except during changes of state. In addition, such a system is advantageous in that circuits in conformance therewith have a relatively high noise immunity when a binary threshold of two and one half volts with respect to the circuit ground potential level is employed. Unfortunately, such a system is disadvantageous in that the switching speed of circuits in conformance therewith is relatively slow when the circuits are loaded by a relatively high capacitance. This is because the propagation delay of such a circuit is directly proportional to the magnitude of the voltage swing and the loading capacitance. Further, such a system is disadvantageous in that in a random-access-memory (RAM) decoder (binary-to-thermometer-code converter), such a system requires a relatively large number of transistors and, thus, is relatively slow.
USPTO Backgrounds
USPTO Backgrounds