This invention relates to and methods of manufacture of ultra-thin body Field Effect Transistor (FET) devices as well as the ultra-thin body FET devices produced thereby.
In semiconductor devices Field Effect Transistors (FETs) such as Complementary Metal Oxide Semiconductor (MOS) FETs or Metal Insulator Semiconductor (MIS) FETs, the trend continues to be a steady reduction in the minimum feature size of the devices. The reduction of the minimum transistor gate length, realizable on a chip, has helped the microelectronic industry to produce products with a resultant spectacular increase in computational capability and integration density.
FIG. 1 shows a conventional prior art MOSFET device 10 formed on a p-type doped silicon substrate 11. A gate dielectric layer 12 (e.g. gate oxide) and a gate electrode 14 (e.g. doped polysilicon) are formed as a gate electrode stack on the top surface of the substrate with an n+ doped source region 15 and an n+ doped drain region 16 formed alongside the gate electrode 14 with a channel region 13 therebetween below the gate electrode 14. Voltage V is connected to the drain region 16 through wiring 18 which connects to drain contact 19.
In principle, such devices as Complementary MOSFET devices or Complementary MISFET devices can be made smaller and smaller. However, if only the length “L” of the gate electrode is scaled down, i.e. reduced in scale, with-out changing other parameters of an FET device, the drain-field will have more and more influence upon the channel region as compared to the influence which can be exerted by the gate electrode.
Eventually, as a function of the reduction in scale, the gate electrode can lose control of the channel region and a punch-through condition occurs in the FET device as explained in S. M. Sze “Semiconductor Devices Physics and Technology”, John Wiley & Sons, page 213 (1985) because the channel width is too narrow or too short. This is the so-called Short-Channel-Effect (SCE). A device encumbered by an SCE condition ceases to function as an electronic switch if the gate electrode fails to turn off the FET effectively.
On the other hand, referring again to FIG. 1, to reduce the scale of the MOSFET devices by a divisor α which is a number larger than “1”, the vertical dimensions (gate oxide thickness tox, junction depth, and depletion width xd shown in FIG. 1) must be scaled down to be commensurate with the lateral dimension, such as the length “L” of the gate electrode 14, the width “W” of drain contact 18, and width “C” of the channel 13. This guideline guarantees appropriate proper device characteristics when a larger device 10 is scaled down to a smaller device by the scaling divisor α.
The depletion width xd in region 17 below the source region 15 and drain region 16 is reduced by increasing the concentration of dopant that is present in the substrate 11. However, increasing the dopant concentration to an excessively high level will degrade the performance of the device 10 because of increased threshold voltage Vt, junction capacitance, and junction leakage. The mobility is also reduced as a function of higher substrate doping.
A Super-Steep Retrograde Well (SSRW) has a low-high-low (low-high) channel doping profile which can improve the control of Short-Channel Effect (SCE) without degrading mobility. However, the doping level in the ground plane is generally high, which could cause increased junction leakage and increased junction capacitance.
FIG. 2 shows an example of a prior art SSRW type of MOSFET device 20 formed on a p-type doped silicon substrate 21. A gate dielectric layer 22 (e.g. gate oxide) and a gate electrode 24 (e.g. doped polysilicon) are formed as a gate electrode stack on the top surface of the substrate with an n+ doped source region 25 and an n+ doped drain region 26 formed alongside the gate electrode 24 with a channel region 23 therebetween below the gate electrode 24. The device includes n− lightly doped source (LDS) regions 27 adjacent to the source regions 25 and an n− lightly doped drain (LDD) region 29 adjacent to the drain region 26 reaching under the gate electrode 24, respectively. A source halo region 27L extends between the LDS region 25 and the left edge of the channel 23. A drain halo region 29H extends between the LDD region 29 and the right edge of the channel 23. A Super Steep Retrograde Well (SSRW) 24 is formed in the substrate 21 with a retrograde dopant profile which involves a relatively low dopant concentration formed in the channel 23 just below the gate dielectric layer 22. In a SSRW device the dopant concentration increases sharply as a function of distance from the gate dielectric layer 22 and then levels off deeper into the channel region 23. (See page 9 of Thompson et al. “MOS Scaling: Transistor Challenges for the 21st Century” Intel Technology Journal Q3′98 pp 1–19) which states at page 9 that “The retrograde profile is typically created by using a slow diffusing dopant species such as arsenic or antimony for PMOS devices and indium for NMOS devices.”
An ultra-thin SOI MOSFET (with SOI thickness less than 50 nm) is another attractive option to reduce the vertical dimensions (such as junction depth and depletion width). It can effectively reduce the short-channel-effect and eliminate most of the leakage current.
U.S. Pat. No. 6,084,271 of Yu et al. entitled “Transistor with Local Insulator Structure”, which describes a fully-depleted Silicon-On-Insulator (SOI) MOSFET states “According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction in the depletion layer thickness is realized by a super-step retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing). The ion implantation process can generally only achieve an 80 nanometer or larger body thickness for a transistor. Thus, conventional fabrication techniques for bulk semiconductor type-devices cannot create transistors with body thickness less than 80 nm.” “Accordingly, bulk semiconductor-type devices can be subject to disadvantageous properties due to the relatively large body thicknesses. These disadvantageous properties include less than ideal sub-threshold voltage rolloff, short channel effects (can change to “large subthreshold swing”), and drain induced barrier layering. Further still, bulk semiconductor-type devices can be subject to further disadvantageous properties such as high junction capacitance, ineffective isolation, and low saturation current. These properties are accentuated as transistors become smaller and transistor density increases on ICs.”
U.S. Pat. No. 6,730,568 of Sohn entitled “Method for Fabricating Semiconductor Device with Ultra-Shallow Super-Steep-Retrograde Epi-Channel by Boron-Fluoride Compound Doping” describes a method for fabricating a semiconductor device with an epi-channel formed by ultra low energy ion implantation and by a laser thermal annealing (LTA) process. A field oxide layer with an (STI) structure is formed on a semiconductive substrate, and P-type dopants are ion-implanted into the substrate to form a P-type well. Sequentially, boron ions are implanted under ultra low energy (1 keV) to form a delta doped channel doping layer. Then, the laser thermal annealing (LTA) process is performed without pre-amorphization for amorphizing a surface of the semiconductor substrate. The laser thermal annealing process suppresses the redistribution of boron within the channel doping layer, as well as changing the channel doping layer into a chemically stable channel doping layer. Then an epitaxial layer is selectively grown on the channel doping layer at an elevated temperature to form a Super Steep Retrograde (SSR) epi-channel structure.
U.S. Pat. No. 6,323,073 of Yeh et al. entitled “Method for Forming Doped Regions on an SOI Device” states in the abstract that an SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A Shallow Trench Isolation (STI) structure is formed on the silicon layer, which passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer forming an N-well or P-well doped region. Next, in a thermal diffusion process dopants are driven into a second region of the silicon layer so as to form a P-well or N-well doped region. Then, an epitaxial layer, about 200 angstroms thick, is grown on the surface of the silicon layer by an Molecular-Beam Epitaxy (MBE) growth process, a Liquid-Phase Epitaxy (LPE) growth process, or a Vapor-Phase Epitaxy (VPE) growth process. The Yeh et al. patent states, “In this manner, the doping concentration distribution presents an SSR distribution curve. Under the SSR distribution, the doping concentration is reduced in the region near the gate. This enhances the mobility of the electrons and holes in the channel, significantly improving the current velocity over the prior art. Additionally, short channel effects (SCE) are prevented. The junction capacitance (Cj) at the interface of the source and the well, and the drain and the well is also reduced, thus enhancing the electrical performance of the MOS transistor.” U.S. patent application No. 20020033511 A1 of Babcock entitled “Advanced CMOS Using Super Steep Retrograde Wells” states that “The use of super steep retrograde wells with intrinsically doped channel regions has significant performance advantages for CMOS devices. These advantages include reduction of short channel effects, increased mobility in the channel region, higher mobility, less parasitic capacitance, and a reduction in short channel effects. Although the super steep retrograde wells have significant advantages for advanced CMOS devices, it is very difficult to achieve these structures when manufacturing these devices for high volume integrated circuit applications. This difficulty is due to the out-diffusion of the retrograde well dopant species into the channel region especially for p-well device such as the NMOS transistor. In fact, it has been shown that current silicon processing techniques will not be able to achieve stringent doping profiles that are targeted to change by as much as three orders of magnitude in less then 4 nm by the year 2008. There is therefore a great need for new processing techniques that will allow the formation of super steep retrograde well structures with near intrinsic transistor channel regions.” In claim 1, Babcock et al. states as follows:
A transistor with a SSRW, comprising: providing a semiconductor substrate with an upper surface; a capping layer containing carbon positioned at a first distance beneath the upper surface of the substrate; a retrograde well region in the substrate positioned beneath capping layer; source and drain regions in said substrate positioned above said capping layer and separated by a second distance; a gate dielectric layer on the upper surface of the substrate; and a conductive gate layer on the gate dielectric layer positioned between said source and drain regions.
An ultra-thin SOI CMOS FET or CMIS FET (with SOI thickness less than 50 nm) is another attractive option to reduce the vertical dimensions (such as junction depth and depletion width). It can effectively reduce the short-channel-effect and eliminate most of the leakage current.
U.S. Pat. No. 6,495,401 of Hsu entitled “Method of Forming an Ultra-Thin SOI MOS Transistor” states that a silicon wafer has an oxide layer formed thereon. A top silicon layer is deposited by state of the art deposition techniques on the oxide layer. The top silicon layer is thinned by thermal oxidation, or etching, to a desired thickness, which is preferably between about 10 nm and 30 nm. Device isolation is accomplished by etching silicon islands for mesa isolation, or by a LOCOS process.
U.S. Pat. No. 6,501,134 of Krivokapic entitled “Ultra Thin SOI Devices with Improved Short-Channel Control” shows an SOI device with a buried oxide layer usually undoped SiO2 with thickness of approximately 50–60 nm, atop a bulk substrate. Above the buried oxide layer is an undoped ultra-thin undoped SOI silicon layer which has a thickness between 5–20 nm. Above the SOI silicon layer a gate dielectric is formed comprised of silicon dioxide or alternately silicon nitride, aluminum oxide, tantalum pentoxide or hafnium oxide with equivalent oxide thickness of 0.8–1.4 nm. A conducting metal gate electrode is deposited and patterned from TiN, TaN, TaW, W, Al, Ni, Ta, Mo, or Cr, and has thickness of approximately 2.5–25 nm, with gate length of 30–60 nm. A polysilicon encapsulation layer with thickness of 50–100 nm is deposited on and patterned with the gate electrode. The patent states that “Encapsulation layers in general are necessary to prevent cross-contamination of the fab line during post-gate formation processing.” The patent indicates that “10–15 nm polysilicon is deposited and anisotropically etched to form poly spacers which when doped function as side gates.” There is no indication that the SOI silicon layer is ever doped to form a doped channel region and the source region and the drain region are formed in the SOI layer.
Zhang U.S. patent application No. 20020060338 A1 entitled “Methods of Fabricating Vertical Field Effect Transistors by Conformal Channel Layer Deposition on Sidewalls and Vertical Field Effect Transistors Fabricated Thereby” stated as follows: “In attempts to reduce short channel effects, planar fully depleted ultra-thin body Semiconductor-On-Insulator (SOI) FETs have been developed. For example, using a semiconductor-on-insulator substrate and etchback or oxide thinning, ultra-thin SOI channels may be obtained. See, for example, Choi et al., “Ultra-Thin Body SOI MOSFET for Deep-Sub-Tenth Micron Era”, Paper 3.7.1, IEDM, 1999, pp. 919–921. Other approaches have deposited a thin layer of amorphous silicon or silicon germanium alloy on a planar oxide surface, followed by lateral solid-state crystallization. See, Yeo et al., Nanoscale Ultra-Thin-Body Silicon-On-Insulator P-MOSFET with a SiGe/Si Hetero-structure Channel, IEEE Electron Device Letters, Vol. 21, No. 4, 2000, pp. 161–163.”
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