Most large scale integrated circuits (ICs) are presently packaged in plastic or ceramic packages with metal leads extended therefrom for soldering to a printed circuit (PC) board or for insertion into a socket. Typically, these IC packages are configured as dual-in-line or quad-flat packages. In most instances only a single IC is contained within a package, although multiple chips are sometimes contained within a package. The circuit density resulting from this packaging technology is not very great since the ceramic or plastic package consumes relatively large areas of the mounting surface, usually a printed circuit board, particularly if a socket is used.
Moreover, printed circuit (PC) boards are becoming smaller and denser. A compact packaging technology is needed when mounting area is limited dictating that circuit elements be closely spaced. PC boards have typically been designed so that semiconductor devices in the form of packaged semiconductor dice are mounted thereon to make a final circuit. For memory boards, the drive for increased memory capacity is limited by board space. Thus, when the size of the board is fixed, the number of devices that can possibly be mounted on the board is limited. A module consisting of a plurality of semiconductor devices is used to densely dispose semiconductor devices. Mounting to the PC board can be accomplished by a surface mount or a through-hole technique.
Several methods exist for fabricating a semiconductor multiple chip module. One such method uses a laminated cofired ceramic substrate, onto which bare semiconductor dice are directly attached to the ceramic mounting surface and are wire bonded to conductive areas on the mounting surface, or are inverted and connected directly to metallized areas on the ceramic mounting surface by, for example, a solder-bump technique. This multiple chip module technology has several limitations, however. Interconnecting multiple ICs on a single ceramic mounting surface requires deposition of a metallic material in a pattern which desirably avoids cross-overs. Furthermore, a disadvantage of direct chip attach is the difficulty of burn-in before module assembly. Burn-in is performed to screen out weak devices. If a module fails during burn-in due to a weak device, the entire module must be discarded or repaired after burn-in, whereas if each component of the module could be burned-in prior to module assembly, the yield for functional modules can be increased.
Another method of fabricating a semiconductor multiple chip module involves tape automated bonded (TAB) semiconductor dice to a flexible circuit leadframe. The semiconductor dice are tested as discrete units before being mounted, or they can be tested in the final circuit form after the TAB process. After testing and reworking, the flexible circuit leadframe is encapsulated. The dice and circuitry on the leadframe except outer portions of the leadframe are encapsulated in a mold forming a single package body for the entire module. The disadvantage to this approach is that repair of the module after encapsulation is not possible. Hence, any failure of a semiconductor die inside the encapsulated module would cause the entire module to be rejected.
Another approach to form a multiple chip module is to stack pin grid arrays (PGAs). A bottom substrate is provided with copper pins in a conventional manner. Semiconductor dice are then flip-chip mounted to chip carrier substrates. An interposer physically and electrically couples a chip carrier substrate to another chip carrier or to the bottom substrate by way of solder joining the interconnections. The copper pins of the PGAs and the interposers provide the stand-off between the carriers to keep them from collapsing onto each other. A limitation to stacked PGAs is the overall height of the module. The standoff from the copper pins and the interposers between each carrier increases the height of the module which is not desirable since PC board real estate in the Z-direction is becoming as precious as PC board real estate in the X-Y plane.
USPTO Backgrounds
USPTO Backgrounds