This invention relates to digital signal processors and in particular to address generation units used to generate a location address in a memory for retrieving or storing M and Y operanda.
Examples of the prior art address generation units are U.S. Pat. No. 5,450,553 which disclosed a digital processor for processing digital signals, comprising an address generation unit for generating an address of an addressing mode which is used for processing the input digital signals; a setting unit for setting an initial value necessary for generating the address in advance in the address generation unit; and an instruction designating unit for designating only execution and stop of address generation to the address generation unit, wherein the address generation unit in which is set the initial value is so constructed as to perform execution and stop of address generation only by designation of the execution and stop outputted from the instruction designating means.
In a second example, Motorola Corporation of Schaumburg, Ill. disclosed in the manual for the DSP56300 core an Address Generation Unit (AGU). The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. The AGU implements four types of arithmetic: linear, modulo, multiple wrap-around modulo and reverse-carry and operates in parallel with other chip resources to minimize address overhead.
USPTO Backgrounds
USPTO Backgrounds