(1) Field of the Invention
This invention relates to a Read Only Memory (ROM) semiconductor device, and more particularly to a method and structure of manufacturing a high-density split gate memory cell for a flash memory or EPROM (Erasable Programmable Read Only Memory).
(2) Description of the Related Art
ROM devices are well known and widely used in the computer technology. In general, a ROM device consists of an array of MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) arranged in columns and rows where selected MOSFETs are rendered permanently conductive, or non-conductive, depending on the type of transistor. The ability to set the conductive state of each MOSFET provides a means for storing binary information, and is done typically during a manufacturing process. In a ROM device, this information is non-volatile, i.e., it is maintained even when power is removed from the circuit.
EPROM devices differ from ROMs in their ability to be programmed and erased by a user, after the manufacturing process is complete. They offer advantages such as a small single-cell structure, made of a single MOS transistor with a double-polysilicon gate, and thus high density. Programming is typically accomplished by channel hot-electron injection, outside of the circuit in which the EPROM is used, and erasing by exposure to ultraviolet light, or other means. These somewhat cumbersome techniques explain the popularity of EEPROMs (Electrically Erasable Programmable Read Only Memory), which can be erased and programmed while in-circuit, using Fowler-Nordhiem tunneling. However, EEPROMs have a large cell size and require two transistors per cell.
An EEPROM uses a floating gate structure in the MOSFET cell to provide programmability. The floating, or unconnected, gate provides a conductive surface isolated from the source and drain regions of the MOSFET by a thin gate oxide. A second conductive gate, called the control gate, is adjacent to but isolated from the floating gate. The threshold voltage characteristics of the MOSFET cell is controlled by the amount of charge on the floating gate. The amount of charge is set to one of two levels, to indicate whether the cell has been programmed "on" or "off".
The memory cell's state is "read" by applying appropriate voltages to the MOSFET source and drain, and to the control gate, and then sensing the amount of current flow through the transistor. The desired memory cell is selected by choosing the source and drain lines in the column where the cell is located, and applying the control gate voltage to the control gates in the row of the cell being addressed.
The memory cell's programmable state may be erased by removing charge from the floating gate. A fairly recent technology is "flash" memories, in which the entire array of memory cells, or a significant subset thereof, is erased simultaneously.
A known problem with the EEPROM is that of "over-erasing", in which positive charge remains on the floating gate after an erase. One solution is the split-gate structure of FIG. 2, which solves the over-erase problem but at the expense of a larger cell size. Source 24 and drain 25 regions are self-aligned in a substrate 23 with the edges of floating-gate 26 and isolation gate 27, which have channel lengths 28 and 29, respectively. An example is shown in U.S. Pat. No. 4,868,629 (Eitan). Eitan teaches the use of a photoresist pattern to cover part of the floating gate area and the channel region of the "isolation transistor" (which is connected in series with the floating-gate transistor), during source/drain implant. There are two problems associated with this method for making a split-gate Flash cell. First, consistency of the total channel length of the cell--floating gate plus isolation gate --cannot be easily controlled, since it is dependent on photolithography alignment and CD (Critical Dimension) loss. Second, the total channel length (and thus the cell size) tends to be larger due to the same photolithography process limitation.
A second split-gate structure is shown in U.S. Pat. No. 5,115,288 (Manley). A polysilicon spacer is utilized to form a self-aligned channel for the isolation transistor, and thus produce a constant total channel-length for the entire cell. However, this process requires an extra polysilicon layer (three, instead of two layers), and a critical photoresist masking step is required which uses resist to cover half of the floating gate for removing a poly spacer on one side.
Since two transistors are connected in series for the split-gate Flash memory cells described above, a larger cell size than for a single-transistor Flash cell will result.
In the semiconductor technologies, and particularly in memory structures, there is a constant effort to reduce the lateral size of each device, thus allowing increased density of devices on the same or similar size semiconductor chip. One approach to reducing the lateral area of the device is to build a more vertical structure, as is shown in "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs", by H. Takato et al, IEDM 88 pages 222-224. As shown in FIGS. 1 and 1A (in which FIG. 1A is a cross-section along line 1A-1A' of FIG. 1), a vertical "silicon island" 14 is formed from a p-well region 12 formed over a silicon substrate 10. The side-walls of the island are utilized as the channel region of the device, and the conductive gate layer 18 is formed surrounding the sidewalls and separated therefrom by a thin gate oxide 16. The source 20 and drain 22 regions are formed in horizontal regions around the base of, and in the top of, respectively, the silicon island.
USPTO Backgrounds
USPTO Backgrounds