Non-volatile memory devices in general and charge-trapping memory devices in particular are widely used in electronic devices as a reliable type of storage. In particular, battery-operated devices make use of different types of non-volatile memory devices for storing information that is preserved even in the absence of an operational voltage.
In charge-trapping memory devices known as NROM, a programming state of a memory cell of the device is stored by means of trapping electrons in a nitride layer placed between a control gate and a source/drain channel of a modified MOSFET. NROM memory devices can be used to store more than one bit per memory cell. For example, a first charge indicative of a first bit can be stored near a source terminal of an NROM cell whereas a second bit can be stored near a drain terminal of the NROM cell. NROM cells are described in more detail in U.S. Pat. No. 6,011,725 by Eitan, which is incorporated herein by reference.
Unlike other types of non-volatile memory devices, which are typically worn out after a certain number of subsequent programming and erase cycles, NROM memory devices can be cycled almost infinitely and thus have a very long expected lifetime.
However, especially for long-term storage or frequent use, data stored in an NROM memory device may become invalid. This is mainly due to the fact that operations accessing one charge-trapping memory cell can affect other memory cells not accessed. For example, charging a bitline connected to a first memory cell in a first sector and a second memory cell in a second sector will affect the threshold level indicative of a programming state of both cells even though just one cell is actually accessed, for example for erasing, programming or reading.
Non-volatile memory devices often comprise a data area and a redundancy area. Data stored in the redundancy area may be used to validate data stored in the data area. Thus, not every bit error in a non-volatile memory device leads to invalid data or results in an application error. In particular, error correction codes (ECC) may be stored in the redundancy area that allow to detect and correct up to a certain amount of bit failures in a segment of the array. The number of correctable bit failures depends on the concrete organization of the array, in particular the number of segments contained in an erase sector of an array.
For example, an array and an associated control circuit may be adapted to correct single and double bit failures in a segment. However, segments with more than two faulty bits cannot be corrected and consequently pose a risk for application and data consistency.
USPTO Backgrounds
USPTO Backgrounds