1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly to the layout of power supply lines in a semiconductor storage device.
2. Description of the Related Art
FIG. 46 is a plan view illustrating a dynamic random access memory (DRAM) which is a conventional semiconductor storage device disclosed in, for instance, Japanese Unexamined Patent Publication No. Hei. 4-212454. In the drawing, reference numeral 101 denotes a region in which sense amplifiers are arrayed in a row (sense-amplifier forming region), 102 denotes a region in which a group of storage elements are arrayed (memory cell array), 103 denotes a region in which the sense-amplifier forming region 101 on the one hand, and a word-line backing region 104 for connecting a relatively high-resistance wiring and a low-resistance metal wiring formed in a layer separate from that wiring on the other hand, intersect each other. In addition, FIG. 47 is an enlarged view of the region denoted by a character X in FIG. 46, and illustrates the detail of the wiring of the power supply lines. In FIG. 47, numeral 105 denotes a power supply line for supplying power supply potential, 106 denotes a grounding line for supplying ground potential; and 107 and 108 denote through holes for connecting the power supply line 105 and the grounding line 106 extending in the horizontal direction (in this drawing) to the power supply line 105 and the grounding line 106 extending in the vertical direction (in this drawing).
Thus, in accordance with the prior art, as shown in FIG. 47, the power supply lines 105 and the grounding lines 106, extending in the vertical and horizontal directions in the sense-amplifier forming regions 101, are respectively connected to each other via the through holes 107 and 108, and are thereby arranged in mesh form. As the power supply lines 105 and the grounding lines 106 are thus arranged in mesh form, the supply of power to drive circuits for driving the sense amplifiers is effected speedily so as to speed up the operations of reading and writing information with respect to the memory cells.
In addition, if an assembly of the memory cells is denoted by memory portions 109a to 109d, an actual DRAM chip can be shown in FIG. 48. In this arrangement, row decoders 110a and 110b and column decoders 111a and 111b necessary for the designation of memory cells are arranged. The two memory portions 109a and 109c are disposed on both sides of the column decoder 111a extending in the direction of the rows, the memory portions 109b and 109d are disposed on both sides of the column decoder 111b, the memory portions 109a and 109b are disposed on both sides of the row decoder 110a extending in the direction of the columns, and the memory portions 109c and 109d are disposed on both sides of the row decoder 110b.
Next, an enlarged view of a portion of FIG. 48, i.e., a region including a boundary between the column decoder 111a and the memory portion 109c, is shown in FIG. 49. As already described, the power supply lines 105 and the grounding lines 106 are arranged on the memory portions 109a to 109d in mesh form, and extension lines of these wirings (105, 106) are also arranged on an adjacent column decoder 111a.
Since the wirings (105, 106) are thus arranged in the region where the column decoder 111a is formed, the region where the column decoder 111a is effectively formed becomes small, so that it has been difficult to secure a space necessary for forming the column decoder 111a having a complicated configuration. In addition, since the power supply lines 105 and the grounding lines 106 are generally formed in an identical plane in the same process, it has been difficult to form a single power supply line by combining the plurality of power supply lines 105 (or grounding lines 106) without short-circuiting the power supply lines 105 and the grounding lines 106 or increasing the number of processes involved.
In addition, in the sense-amplifier forming regions 101 in the memory portions 109a to 109d, the power supply lines 105 extending in the direction of the columns and the power supply lines 105 extending in the direction of the rows, as well as the grounding lines 106 extending in the direction of the rows and the grounding lines 106 extending in the direction of the columns, are respectively connected together via the through holes 107 and 108. However, since these through holes require relatively large areas for formation, if an attempt is made to form a through hole at the respective intersections of the power supply lines 105 and the grounding lines 106, restrictions occur in the interval between the power supply line and the grounding line.
Meanwhile, in a synchronous DRAM, which is a type of DRAM, a plurality of banks which are assemblies of memory cells capable of operating independently are provided in a single semiconductor chip, and the banks operate simultaneously. The inputting and outputting of data to and from the banks for the inputting and outputting of external data are effected at high speed. While the operation of accessing a designated address X1, Y1 of one of the banks is being carried out, the operation of accessing a designated address X2, Y2 of another bank is carried out, and the inputting and outputting of external data by the two banks are effected by being delayed by one cycle each, thereby making a high-speed operation possible. In this synchronous DRAM, since the plurality of banks operate simultaneously, in a case where two banks operate simultaneously, power consumption twice that necessary for the operation of one bank is required, so that the supply of sufficient power is necessary.
The conventional semiconductor storage devices are configured as described above, and since the wirings including the power supply lines and the grounding lines are disposed on the column decoder, there has been a drawback in that the area where the column decoder is effectively formed becomes small.
In addition, in the case where the through holes are formed at the respective intersections of the power supply lines (or grounding lines) extending in the direction of the columns of the memory cells and the power supply lines (or grounding lines) extending in the direction of the rows thereof, there has been a problem in that restrictions occur in the interval between the power supply line and the grounding line.
Further, the power supply wiring for strengthening the power supplying capability is not formed in regions (shunt regions) for connecting a relatively high-resistance wiring and a low-resistance wiring, such as a metal wiring, via through holes in the case of a semiconductor storage device using a word line shunt system, and in regions for connecting main word lines and sub-word lines (regions where sub-decoding circuits are formed) in the case of a semiconductor storage device using a word line division system.
Furthermore, if there is a region where power consumption is large partially in a memory cell array, it is necessary to strengthen the power supplying capability with respect to the particular region. With the conventional methods, however, it has been difficult to improve the power supplying capability of a particular region. Further, since the conventional synchronous DRAM is formed as described above, power consumption twice that necessary for the operation of one bank is required. Consequently, there has been a drawback in that operations of banks, which should be independent of each other, affect each other due to a decline in the power supply potential depending on the method of supplying power to the memory cell array, resulting in the loss of leeway in the operation of the memory cell array.
USPTO Backgrounds
USPTO Backgrounds