The present invention is related to a semiconductor device and a method for manufacturing the semiconductor device.
A semiconductor device, such as a semiconductor substrate or a transistor, may include a doped portion, such as a channel-stop layer. The dopant distribution of the doped portion may significantly affect the performance of the semiconductor device. For example, a channel-stop layer of a fin field effect transistor (FinFET) may substantially affect the threshold voltage variation of the FinFET. In general, a channel-stop layer having a substantially concentrated dopant distribution may be desirable.
Nevertheless, in manufacturing of the semiconductor device, for forming one or more insulating members, such as one or more shallow trench isolation (STI) members, an annealing process may be performed at a substantially high temperature for a substantially long time duration. The long, high-temperature annealing process may cause the doped portion to have an undesirably wide dopant distribution.
USPTO Backgrounds
USPTO Backgrounds