For applications such as 3-D graphics, digital VCRs, real-time image processing and radio signal processing, there is a need for faster signal processing with corresponding need to minimize the power consumption and dissipation.
Various differential signaling technologies are known. Low voltage differential signaling (LVDS) is the subject of technical standards: (1) ANSI/TIA/EIA-644 standard (published in 1995 by American National Standards Institute, as updated from time to time); and (2) IEEE 1596.3 standard (published in 1996 by Institute of Electrical and Electronics Engineers as updated from time to time).
Current implementations of LVDS have differential driver output voltage in the order of 250 mVolts (up to the technical standard maximum of 450 mVolts) and receiver input threshold of about 100 mVolts. Preferred embodiments of LVDS requires only half the voltage swing of Positive Emitter Coupled Logic (PECL) technology (which has differential driver output voltage in the order of 600 mVolts to 1 Volt; and receiver input threshold of about 200 to 300 mVolts), while maintaining comparable data transfer rates of at least 400 Mbps.
USPTO Backgrounds
USPTO Backgrounds