Technical Field
This patent Disclosure relates generally to filter circuits, and more particularly to loop filter circuits used in phase-locked loop (PLL) circuits such as for clock data recovery.
Related Art
Analog phase-locked loop control systems include a VCO (voltage or current controlled oscillator) with a frequency/phase control loop including a phase (or phase/frequency) detector PD/PFD, and a loop filter. The PD/PFD compares the phase of an input signal and a VCO feedback signal, and generates an phase error output, which is low pass filtered by the loop filter to provide a VCO control voltage to phase lock the VCO output signal with the input signal.
FIG. 1 illustrates a PLL 10 with a VCO 12 and a phase/frequency detector (PFD) 14, and an example charge pump loop filter 20 driven by the PFD. Loop filter 20 includes a loop filter capacitor C1, and an optional secondary filter (smoothing) capacitor C2. Loop filter 20 low pass filters the PDF phase error output to provide a VCO control voltage V1.
One application of phase-locked loop control systems is for clock data recovery. In an integrated CDR, the loop filter capacitor can use 25% or more of the die area. Alternative design approaches to reducing this die area penalty are to use an external loop filter cap, or to replace an analog PLL/CDR design with a digital PLL/CDR.
While this Background information references CDR circuits, the Disclosure is more generally directed to filter circuits for PLL systems.
USPTO Backgrounds
USPTO Backgrounds