1. Field of the Invention
The embodiments disclosed herein relate to modeling parasitic resistances in semiconductor devices and, more particularly, to embodiments of a method, a system and a program storage device for modeling the total parasitic resistances of the source/drain regions of a multi-gate field effect transistor (MUGFET), which incorporates multiple semiconductor fins.
2. Description of the Related Art
The resistances associated with the source/drain regions of a field effect transistor (FET) are relatively large parasitic resistances that will impact performance. Thus, during FET design, accurate modeling of the total parasitic resistances of the source/drain regions is very important. Various techniques are well known in the art for modeling the total parasitic resistances of the source/drain regions of conventional planar FETs. Recently, however, multi-gate non-planar field effect transistors (MUGFETs) (e.g., dual-gate non-planar FETs, also referred to herein as fin-type FETs (FINFETs), and tri-gate non-planar FETs) and, particularly, multi-fin MUGFETs have been developed to provide reduced-size field effect transistors, while simultaneously providing enhanced control in short channel effects (SCE) and reducing drain induced barrier lowering (DIBL) significantly. Unfortunately, for such multi-fin MUGFETs, the prior art modeling techniques do not provide accurate results without dramatically increasing simulation time. Therefore, there is a need in the art for technique that can be used to more accurately model diffusion region resistance of multi-fin MUGFETs with a much smaller transistor network.
USPTO Backgrounds
USPTO Backgrounds