(1) Technical Field
This invention relates to the general field of semiconductor devices, and more particularly, to a method for handling small thin plastic ball grid array substrates (STPBGA), in preparation for front-of-line assembly operations.
(2) Description of the Prior Art
The following documents relate to methods dealing with handling of thin substrates during processing.
U.S. Pat. No. 4,915,057 issued Apr. 10, 1990 to Boudreau et al., shows methods and apparatus for registration or alignment of thin film structure patterns on a substrate formed with the use of an apertured mask in a vacuum deposition system.
U.S. Pat. No. 6,037,026 issued Mar. 14, 2000 to Iwamoto discloses a substrate carrier jig which supports a substrate of a liquid crystal display element on its surface and carries the substrate with the jig to a process.
The conductors used for interconnection within a semiconductor chip are extremely fine, being of the order of a few microns, or less, in width. The ability to construct such tiny conductors has made possible chips containing four to five orders of magnitude, and more, of interconnected components. This high level of integration has presented an enormous challenge in assembly during the front-of-line die-attach operations, which include, solder reflow or epoxy attach, plasma cleaning, plastic underfilling, curing of the underfilling, and removal of the substrate carrier.
There are several other types of package technologies that include such rigid substrates as ceramics with straight-through vias, flexible polymer tape in tape automated bonding (TAB) with bumps or balls on either end, also, wafer-level assembly such as redistribution of peripheral I/Os to area array I/Os on chip and lead-on-chip(LOC).
Interconnections at the chip level were and are being achieved by wire bonding to plastic or ceramic single chip packages which are then bonded to printed wiring boards using surface mount technology (SMT). The trend is toward Flip Chip and Ball Grid Array (BGA), and to direct-chip attach to the board.
The packaging technologies that span the microelectronics industry from consumer electronics to low-end systems to high-performance systems are very diverse. The number of chips needed to form a system in the past increased from a few, in consumer electronics, to several thousands, in supercomputers. Given this, the viable carriers which are used to handle BGA devices are becoming equally diverse and more complex, especially for the front-of-line assembly operations.
The development cycle for first level packaging is extremely time consuming and costly. When the technology itself is developing in parallel, but on different time scales, resolution of the problems does not become easier. All of these issues are exacerbated by the continuing advance of VLSI and ultra large-scale integration (VLSI) technology, where exponential increases in the number of conductors are matched by its interconnected components.
An improvement in packaging efficiency for ball grid arrays (BGAs) is being achieved by a so-called small thin plastic ball grid array (STPBGA) substrate, a fire retardant synthetic resin/glass cloth laminate, typically 0.2 mm thick. However, there are many problems encountered in the processing of these very thin, and flimsy STPBGA substrates. Bending under the slightest influence of force is one of the problems, and warping during solder reflow causing the C4 balls of the chip to be pushed away from the distorted substrate especially when passing through the reflow oven at temperatures above 200xc2x0 C. Because of the fast moving advancements in packaging technology, prior art availability of carriers to solve the above problems were non-existing. A type of process carrier used during product development is described with reference to FIG. 1. The process carrier 10 used during the development cycle was simply a flat support plate 18 having pins 11 for guiding the substrate 30, and a top weighted means 12 to hold the substrate down against the carrier. The weighted mass was needed to affect the required clamping force thus preventing substrate distortions during solder reflow which lengthened the reflow cycle as compared to a thicker more solidly stable substrate. Reprofiling the oven zone temperatures and slowing the conveyor speed was needed because of the added thermal mass passing through the oven.
The present invention has been accomplished in view of the above mentioned conventional problems and is an object of the present invention to provide a substrate process carrier to eliminate the problems encountered in the processing of these very flexible substrates which include the group of thin STPBGA substrates, thick STPBGA substrates and flexible tape. Bending under the slightest influence of force, and warping during solder reflow causing the C4 balls of the chip to be pushed away from the distorted substrate especially when passing through the reflow oven at temperatures above 200xc2x0 C. has been eliminated. Prior process carriers using a top weighted plate to effect the required clamping force during solder reflow, lengthening the solder reflow cycle because of the added thermal mass of the weighted plate, is no longer needed.
Another object of the invention has been to provide a substrate carrier for flexible substrates having a low thermal mass for improved temperature profiling.
According to the present invention, the substrate carrier holds a flexible substrate during many of the early assembly operations such as; die attach, solder reflow, plasma cleaning, underfilling of plastic, curing the underfilling, as well as wirebond, lead bond and TAB bond, etc. The carrier includes a main structural support member having a first surface for placing thereon a substrate wherein the support member has two rows of pins which are positioned longitudinally and fitly into datum apertures disposed inboard the side edges of the substrate. The two rows of apertures in the substrate accurately locate the substrate on the first surface of the substrate carrier. A plurality of high temperature magnetic inserts, which retain appreciable magnetization indefinitely, are affixed to the first surface of the support member and disposed parallel and outboard the two rows of pins. A hold down cover, selected from a group consisting of magnetically soft metals, is placed over the substrate. The hold down cover has openings extending laterally and longitudinally to bare the conductive patterns of the substrate and has two rows of apertures matching the two rows of apertures in the substrate, the cover, also fitly into the two rows of pins of the support member, is aligned relative the substrate, and pulled against the thin substrate by the magnets, thereby, pressing the outer periphery of the thin substrate against the first surface of the support member
USPTO Backgrounds
USPTO Backgrounds