1. Field of the Invention
The present invention generally relates to a method and a circuit for asynchronous transmission, and more particularly, to a method and a circuit for asynchronous transmission that are applicable to serial data communication.
2. Description of the Related Art
A start-stop synchronization system is one of conventional asynchronous transmission systems. The start-stop synchronization system inserts a start bit F-Top at the head of a data item and a stop bit at the tail of the data item, allowing a receiving device to recognize the head and tail of the transmitted data item without transmitting any sync signal (see Japanese Patent Laid-Open Application No. 9-8863, for example).
The data item starting with the start bit and ending with the stop bit may be referred to as a “frame.” A state in which no data is transmitted through a communication channel is referred to as an “idle” state (logical value “1”). In response to detection of a start bit F-Top (logical value “0”), the receiving device in the idle state detects the start of data item, and start the sampling of the data item. The receiving device continues the sampling for a predetermined data length, and returns to the idle state in response to detection of the stop bit (logical value “1”). The receiving device receives subsequent frames in the same manner.
It is necessary that a transmitting device and a receiving device share information such as bit rate, data length, stop bit length, and error detection (parity bit and CRC, for example) in advance.
In the case of conventional asynchronous data communication, an idle state period needs to be longer than transmission time required for the transmission of a single data frame in order to keep the reliability of communication high, that is, in order to detect the start bit without fail thereby to receive the data. This is because the start bit is detected under the following condition (communication protocol): “an idle state (successive logical values “1”) longer than transmission data, and transition to logical value “0””. Otherwise, if the transmission data contains successive logical values “1” followed by a transition to logical value “0”, the receiving device may erroneously detect the transition to the logical value “0” as a start bit, resulting in the reception of false data.
FIG. 1 is a schematic diagram showing an exemplary waveform according to a conventional asynchronous transmission method. As shown in FIG. 1, a data frame consists of 1-bit start bit F-Top, 32-bit data, and 1-bit stop bit. The data frame is followed by an idle state period of length of 33 bit or more.
There exists an idle state period longer than the data frame after the transmission of each data frame. This degrades the efficiency of data transmission significantly.
USPTO Backgrounds
USPTO Backgrounds