This invention relates generally to simulation of computer system hardware and more particularly to the modelling and simulation of memory systems.
As is known in the art, a computer system is generally comprised of a central processing unit (CPU), a memory unit, at least one input/output device, and a bus which is used to connect the aforementioned devices. The central processing unit is used to fetch and decode incoming instructions, execute commands, and manipulate data, whereas the memory unit, which includes multiple storage locations, stores data to be used by the CPU. The I/O device is generally used to input data to and output data from the computer system. Typical types of I/O devices include printers, keyboards, displays and mass storage units such as disk drives etc. These devices are often interfaced to the computer system with an I/O interface controller circuit.
Designing a computer system involves numerous, complex steps. Engineers generally design computer systems by starting with a high level functional description of the desired system. Once the functional description of the design is determined, it is used to provide a detailed logic design for the system. The detailed logic design process is an elaborate process which involves determining actual logic circuits to provide the functional description and electrical characteristics of those circuits. Moreover, the process generally requires determination of the interactions of interconnected circuits until the electrical design is complete and corresponds to the initial functional description.
As the complexity of computer systems has increased it has become necessary to verify the functionality of a computer system design before the system is built. A universally accepted technique of doing this is through simulation.
Simulation of a computer system involves producing software models which simulate the actual hardware logic design. Test programs are run on these software models to test the design and uncover design errors. In this way, the designer can observe how the hardware will operate under various test conditions.
Typically, when modelling a computer system including memory devices, each memory device in the system is individually modeled. Each memory device model includes the characteristics of the memory device necessary to duplicate its functionality, as well as storage in which to save any data written to it. Under this scheme, each available memory location of the design system has a counterpart in the simulation. This approach requires the use of large amounts of the simulation system's memory to reproduce the design system's memory system.
A problem associated with simulation is that computer system hardware is often very complex, and thus, the software models of the hardware and the test programs to exercise the software models are likewise complex. As such, execution of the software models and test programs can dominate use of a simulation computer system's resources and moreover, take a very long time to complete execution. Usually, test programs are very CPU intensive, that is the test programs use large blocks of time in the CPU. Accordingly, such programs can disable other processes from gaining processing time in the CPU. In addition, these software models and test programs can take days or weeks to complete before the program data becomes available to the engineer modelling the system.
In addition to the demands on central processor time, a further problem with simulations is that the software models of the computer hardware can occupy large blocks of memory in the computer system executing the simulation, because all the information necessary to fully model all characteristics of the hardware must be stored. While the program executes, additional portions of memory are required to store the actual data obtained from the simulation as mentioned above. The simulation computer system, in addition to storing the actual data resulting from the simulation generally also stores the predicted data expected from the simulation. Generally, these two data collections are compared to determine whether any errors occurred during the execution of the test program.
Typically, in the computer system executing the simulation, the predicted data is stored in a block of memory, which may be ordered into an array structure. The actual data from the simulation is found in the individual memory models. Each individual memory model typically occupies a segment of memory and includes inter alia locations to store results of the transactions. In order to verify the data, the predicted array is compared to the data stored in the individual memory models. For each location of the predicted array, the location of the corresponding memory model is determined and the data stored in the model is accessed. This data is collected and ordered into an array similar in structure to the predicted array resulting from the transactions. Once the new array has been provided, the contents of the two arrays are then compared to determine whether any errors occurred during the simulation. This requires the additional time necessary to produce the array of actual data. As such, twice as many accesses to memory are required, one to produce the array and one to compare the data, thus slowing down the verification process.
USPTO Backgrounds
USPTO Backgrounds