The present invention relates to techniques for controlling signal offsets, and more particularly, to techniques for correcting signal offsets associated with integrated circuit buffers and amplifiers using programmable resources.
Generally, interface circuitry such as input and output buffer circuits are used to amplify and/or condition signals for detection or transmission. In the case of an input buffer in a telecommunication system, the input buffer circuit receives an input signal that has typically undergone degradation and attenuation as it propagated through a transmission link. The function of the input buffer is therefore to amplify and recondition the received signal, and in some cases to provide frequency equalization, so that the receiver circuitry can properly resolve the incoming bits. In the case of an output buffer, the circuit is typically required to drive an output signal at the appropriate levels for a given transmission link. In either case, any signal offset that may be caused by the buffer circuitry can contribute to operational error. Signal offsets, typically voltage offsets, reduce the available timing margins needed to resolve incoming data bits. This causes an increase in the bit error rate (BER) of the receiver circuit. In the case of output buffers, offsets cause undesirable duty cycle distortion for the output signal.
Various offset cancellation techniques have been developed to eliminate or reduce the adverse effects of signal offsets. For example, in differential circuits, input and output buffer circuits often include selectable current sources coupled to outputs of a differential amplifier circuit. Each current source is typically connected in parallel with a respective transistor output of the transistor pair. Such an arrangement allows the current source and respective transistor to form a voltage divider. The voltage divider is used to adjust a voltage offset with respect to the amount of fixed current being drawn by the current source. Unfortunately, such a conventional arrangement often adds additional unnecessary load to the transistor output when voltage offset is not required. For example, controlling the voltage offset may be unnecessary where the voltage offset may be designed within a tolerance range or part of a given circuit that is unaffected by voltage offsets.
Moreover, as such selectable current sources are generally run parallel to one another, and draw different amounts of fixed current, the amount of change in voltage offset is adjustable by selecting different current sources alone or in parallel to achieve the desired offset voltage amount. Unfortunately, even with precise process control during circuit manufacturing, process variations often introduce differences in the differential circuit components. Such differences often translate into variations in offset signal control with respect to each differential input/output. In addition, the circuitry used to control the current sources and the current sources themselves consumes valuable circuit space on the die.
There is therefore a need for circuits and methods to reduce or eliminate signal offsets when desired in order to improve integrated circuit operational performance while requiring less die space and complexity than conventional signal offset correction circuits.
USPTO Backgrounds
USPTO Backgrounds