1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to fabrication of NAND-type flash EEPROMS without field oxide isolation.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of electrical power. Read only memory (ROM) is a non-volatile memory commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices.
ROM devices typically include multiple memory cell arrays. Each memory cell array may be visualized as including intersecting word lines and bit lines. Each word and bit line (or bit line pair) intersection can correspond to one bit of memory. In mask programmable metal oxide semiconductor (MOS) ROM devices, the presence or absence of an active MOS transistor at word and bit line intersections distinguishes between a stored logic ‘0’ and logic ‘1’.
A programmable read only memory (PROM) is similar to mask programmable ROM except that a user may store data values (i.e., program the PROM) using a PROM programmer. A PROM device is typically manufactured with fusible links at all word and bit line intersections. This corresponds to having all bits at a particular logic value, typically logic ‘1’. The PROM programmer is used to set desired bits to the opposite logic value, typically by applying a high voltage that vaporizes the fusible links corresponding to the desired bits. A typical PROM device can only be programmed once.
An erasable programmable read only memory (EPROM) is programmable like a PROM, but can also be erased (e.g., to an all logic ‘1’s state) by exposing it to ultraviolet light. A typical EPROM device has a floating gate MOS transistor at word and bit line intersections. Each MOS transistor has two gates: a floating gate and a non-floating or control gate. The floating gate is not electrically connected to any conductor, and is surrounded by a high impedance insulating material. To program the EPROM device, a high voltage is applied to the non-floating gate at each bit location where a logic value (e.g., a logic ‘0’) is to be stored. This causes a breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. During subsequent read operations, the negative charge prevents the MOS transistor from forming a low resistance channel between a drain bit line and a source bit line (i.e., from turning on) when the transistor is selected.
An EPROM integrated circuit is normally housed in a package having a quartz lid, and the EPROM is erased by exposing the EPROM integrated circuit to ultraviolet light passed through the quartz lid. The insulating material surrounding the floating gates becomes slightly conductive when exposed to the ultraviolet light, allowing the accumulated negative charges on the floating gates to dissipate.
A typical electrically erasable programmable read only memory (EEPROM) device is similar to an EPROM device except that individual stored bits may be erased electrically. The floating gates in an EEPROM device are surrounded by a much thinner insulating layer, and accumulated negative charges on the floating gates can be dissipated by applying a voltage having a polarity opposite that of the programming voltage to the non-floating gates.
A relatively recent development in non-volatile memory is localized trapped charge devices. While these devices are sometimes referred to as nitride read only memory (NROM) devices, the acronym “NROM” is a part of a combination trademark of Saifun Semiconductors Ltd. (Netanya, Israel).
EEPROM arrays can be fabricated in either NOR or NAND configurations. The NAND configuration, which typically comprises parallel strings of memory cells connected in series, source-to-drain (NAND strings), may be preferred over the NOR configuration because of economy in the use of semiconductor real estate. Fabrication of NAND-type EEPROM arrays normally requires that isolation be provided between NAND strings in order that potentials applied to program a given cell do not influence the program state of neighboring EEPROM cells. Field oxide formed in a substrate between NAND strings may be used to provide the needed isolation. Shallow trench isolation (STI) may be employed as well. Field oxide and STI normally are formed before cell threshold voltage adjustment can be done. Including field oxide isolation in the design of EEPROM arrays may contribute undesirably to an increase in the thickness of individual cells, making it relatively difficult to fabricate flat arrays. Both STI and field oxide may consume substrate area that would be better utilized to provide a greater number of memory cells. That is, the requirement for field oxide isolation regions or STI in EEPROM arrays wastes semiconductor area and contributes to a decrease in the density of EEPROM arrays.
A need thus exists in the prior art for an EEPROM array without field oxide isolation regions. A further need exists for an EEPROM array without shallow trench isolation.
USPTO Backgrounds
USPTO Backgrounds