When an error occurs, an interface device that couples an arithmetic processing device, such as a central processing unit (CPU), to another device notifies of the occurrence of the error by an interrupt to the arithmetic processing device. For example, in a PCI express (hereinafter, referred to as “PCIe”), a root complex is notified of an error related to a PCIe bus by an error message, and when receiving the error message, the root complex notifies the arithmetic processing device of the occurrence of the error by an interrupt. Here, the root complex is a top device out of a plurality of devices coupled in a tree form in the PCIe and is coupled to the arithmetic processing device.
An error processing unit of an operating system (OS) operated in an arithmetic processing device displays or logs a device that have detected an error and an error type in order to allow a maintenance personnel or the like to determine an abnormal spot. The error processing unit is requested to properly process an error detected in each of the plurality of devices coupled to the PCIe bus.
Regarding error process, there is an existing technique that reduces an error processing load due to frequent error occurrence by counting the number of error occurrence and notifying a diagnosis device at the time when the number of error occurrence reaches a preset threshold.
In a PCIe as well, there is a related technique that enables flexible error detection appropriate for the system by counting errors by a counter circuit, and when errors of the number allowed to be set by a user occur, performing interrupt notification. There is a related technique that allows an operator to understand a failed spot in a short period of time by determining, when an interrupt occurs, whether the interrupt is a periodic interrupt or an error interrupt, and when the interrupt is a periodic interrupt, storing error history information and specifying a suspicious spot of the error at the time of the error interrupt. Related art is disclosed in, for example, Japanese Laid-open Patent Publication No. 2010-170462, Japanese Laid-open Patent Publication No. 2009-140246, and International Publication Pamphlet No. WO2012/063358.
The root complex sometimes receives error messages from a plurality of devices in one time. Alternatively, it also sometimes receives a large number of error messages instantaneously from one or a plurality of devices due to frequent occurrence of an error for a temporary noise or the like. For example, when the transmission rate per lane is 8 giga (G) bits/second and a link is formed with eight lanes, a PCIe has transmission performance of 64 Gbits/second. One packet size is estimated at most as approximately 600 bytes. Accordingly, the PCIe is capable of communicating 10,000,000 or more packets in a second. Even when 1/100 of the packets become errors for a temporary noise and the like, there is a possibility that 100,000 error messages are transmitted to the root complex in a second.
It is difficult that the error processing unit processes them one by one. Even when it tries, there are problems that the processing load on the error processing unit increases and thus other processes are affected. Even in the related technique to interrupt when the number of error occurrence reaches a preset threshold, it is difficult to set the threshold. As just described, it is desired to be able to avoid a process of the arithmetic processing device to an error of the interface device from affecting other processes.
USPTO Backgrounds
USPTO Backgrounds