1. Field of the Invention
This invention relates to a scan test circuit, and more particularly, to a scan test circuit which utilizes a scan clock signal for inputting test data, wherein the test data is input to a feedback node of the scan test circuit.
2. Description of the Prior Art
Developments in technology and miniaturization of components have enabled hand-held electronic devices such as smart phones and tablet computers to be widely available. An essential part of these electronic devices is the microprocessor. Microprocessors are made up of many storage elements, typically realized by D type flip-flops or latches, wherein data is input to the flip-flop and then output according to an edge transition of a clock.
During a testing mode of a flip-flop, scan test data needs to be input. Conventionally, two types of scan test circuit are utilized. In the first, a scan chain is created by means of multiplexers at the input of each flip-flop. A data signal D, a test data signal TD and a test enable signal TE are input to each multiplexer. When the test enable signal TE is not enabled, the data signal D will be input to the flip-flops in the functional path via the multiplexers, such that the circuit will operate in a normal mode. When the test enable signal TE is enabled, the test data signal TD will be input to the flip-flops in the functional path via the multiplexers, such that the circuit will operate in a test mode. The disadvantage of this circuit is that the data signal D must go through the multiplexers when the circuit is operating in the normal mode, and each multiplexer will add a certain amount of delay to the functional path, as well as increasing the overall circuit area.
To overcome this problem, the second type of scan test circuit utilizes a separate scan chain, wherein the test data TD is input to this separate scan chain and then input to an internal node of the flip-flop or latch (usually, the QBI node). In order for this test data to be input correctly, the normal data input D must be held. This is achieved by creating a long buffer chain for holding a clock signal used for clocking the circuit, such that the test data TD can be input. This increases the complexity of the clock path, as well as increasing the amount of capacitance in the circuit as test data is input to the feed forward node of the circuit.
In short, the implementation of either circuit will result in a trade-off between power consumption and timing delay in the functional path.
USPTO Backgrounds
USPTO Backgrounds