1. Technical Field
The disclosure relates to integrated circuits, and in particular to transistors of integrated circuits.
2. Discussion of the Related Art
FIG. 1 shows a conventional depletion mode Lateral Double-diffused Metal-Oxide Semiconductor (LDMOS) transistor 5 that is fabricated on a silicon substrate 10. Substrate 10 is doped with a dopant of a first conductivity type, here a P-type dopant. An epitaxial layer 15 doped with a dopant of a second conductivity type, here an N-type dopant, is grown over substrate 10. A well 20 of the second conductivity type and a body region 40 of the first conductivity type are formed in epitaxial layer 15.
A drain region 30, also of the second conductivity type, is formed in well 20 and is in contact with a drain electrode 35. Drain region 30 is doped with a higher concentration of the dopant of the second conductivity type that well 20.
A source region 50 is formed within and abuts body region 40. Like drain region 30, source region 50 is heavily doped with the dopant of the second conductivity type. Source region 50 is electrically coupled to a source electrode 55.
Also formed within body region 40 is a body contact region 60 of the first conductivity type. Body contact region 60 is more heavily doped with the dopant of the first conductivity type than body region 40. Body contract region 60 is in electrical contact with body electrode 65. Source region 50 and body contact region 60 are isolated from each other by oxide 70.
A gate electrode 80 has a first portion 82 that overlies a field oxide 75, an inclined intermediate portion 83 that overlies an inclined beaked portion of field oxide 75, and a second portion 84 that overlies well region 20, an implant region 90, and source region 50. An insulative gate oxide layer isolates gate electrode 80 from underlying layers.
Implant region 90 is a depletion implant for LDMOS transistor 5. Implant region 90 is of the second conductivity type, and is contiguously formed in a channel region of the transistor within well 20, body region 40 and source region 50. Implant region 90 couples well 20 to source region 50 across body region 40. In terms of layout, a portion of second portion 84 of gate 80 overlies implant region 90. Another portion of second portion 84, including peripheral edge 110, extends past the distal edge 125 of implant region 90 in a direction toward source electrode 55. Implant region 90 does not extend beyond the perimeter of gate electrode 80.
A buried layer 45 of the first conductivity type can be added to LDMOS transistor 5 in order to relieve high electric fields at the junctions of well 20 and body region 40. An isolation region 25 isolates the numerous transistors that may be formed on substrate 10 from each other.
Unfortunately, LDMOS transistor 5 has some shortcomings in the areas of reliability and ruggedness. For instance, as the voltage at the drain increases, the gate bias voltage required to turn-on the transistor decreases due to leakage. This reduction in the gate bias voltage can cause erroneous turn-on of LDMOS transistor 5, which could result in damage to downstream devices.
In addition, in the event of an electrostatic discharge (ESD), a large voltage can be imparted to LDMOS transistor 5. This poses a particular problem for LDMOS transistor 5, because a low breakdown voltage is inherent at the junction between source region 50 and body region 40. Hence, an ESD event can easily cause degradation of this junction.
Accordingly, a more reliable and rugged transistor structure is desirable.
USPTO Backgrounds
USPTO Backgrounds