1. Field of the Invention
The present invention relates to an apparatus for processing a repeatedly performed arithmetic operation for digital signal processor (DSP) and a method thereof, and in particular to an improved apparatus for processing a repeatedly performed arithmetic operation for digital signal processor and a method thereof which are capable of significantly reducing a processing time of digital signal processor and effectively operating the digital signal processing by providing a plurality of registers each having a stack structure for storing values corresponding to a repeat block and pushing and popping the values stored in each register in order to process a repeat block which occurs during an arithmetic operation when repeatedly processing an arithmetic operation in the digital signal processor.
2. Description of the Conventional Art
Generally, the digital signal processor (DSP) is applicably used for a video, sound, speech signal processing apparatus for processing the signals in real time. In the digital signal processor (DSP), a processing speed thereof is considered as one of the most important factors in determining the performance of the DSP.
The programmer codes an algorithm used for an application with repect to a video, sound, speech, etc. into an assembly language which is provided by a corresponding DSP and an application is implemented by performing the coded language with respect to a corresponding DSP.
In the algorithm based on the assembly language, many arithmetic operations are repeatedly performed. Such repeatedly performed arithmetic operations are generally processed by one instruction.
There is one method which is recited herein as a conventional art which is disclosed in "a user's guide of TMX320C2x series and TMX320C5x series" published by TEXAS INSTRUMENT CO. According to the above-described article, the TEXAS INSTRUMENT CO. uses a TMX320C2x series and TMX320C5x series as a digital signal processor (DSP).
The block having a repeatedly performed arithmetic operation is called a repeat block. In the DSP of the TI Co., it is impossible to concurrently implement multiple repeat blocks. Therefore, if a programmer wishes to use multiple repeat blocks, the following technique is needed.
When there are provided a plurality of repeat blocks, in order to process an internal repeat block contained in an external repeat block, one instruction and three memory mapped registers should be used. A programmer loads the values which are inputted into and outputted from the registers to a predetermined load portion before the repeat block is performed. When the last instruction is performed, the programmer reads a corresponding value from the load portion and then corrects a corresponding register.
Here, a PASR register indicating a start address of a repeat block, a PAER register indicating an end address of a repeat block, and a BRCR register indicating the number of repeats are used. In addition, "RPTB" instruction is used as a block repeat instruction. The RPTB instruction is programmed such that a corresponding value is loaded to the PASR and PAER registers, and the BRCR register receives a corresponding value before the RPTB instruction is started.
FIG. 1 illustrates a program of a conventional method for processing an arithmetic operation which is repeatedly performed in the DSP. This method is used by TEXAS INSTRUMENT CO. There are provided two repeat blocks which are an internal repeat block and an external repeat block.
The SPLK, SMMR and LMMR are instructions for storing or loading a predetermined value, and RPTB is a block repeat instruction for repeatedly performing several instructions. LAC is an instruction for loading a corresponding value to an accumulator (not shown), SUB is an instruction for decreasing the value loaded into the accumulator by "1", and BC is a conditional branch.
In addition, BRCR, PASR and PAER are memory mapped registers. Among these registers, BRCR register stores the number of repeats therein, PASR register stores a start address of a block therein, and PAER register stores an end address of a block therein. TEMP1, TEMP2 and TEMP3 are temporary registers.
The operation of the conventional apparatus will now be explained with reference to FIGS. 1 and 2.
At the 0th address, NUM1 which is the number of repeats of an external repeat block is stored into the BRCR register. At the 1st address, an end address END.sub.-- BLOCK1 of the external repeat block is stored into the PAER register. At the 2nd address, the start address STARTBLK of the external repeat block is stored into the PASR register.
At each of the 4th through 9th addresses, a predetermined instruction (not shown) is performed.
Next, at the 15th through 20th addresses, the internal repeat blocks are performed. Since the BRCR, PASR and PAER registers are continuously used in the internal repeat block, the values stored into the BRCR, PASR and PAER registers at the 10th through 12nd addresses are stored into the temporary registers TEMP1, TEMP2 and TEMP3, respectively.
Next, the arithmetic operation of the internal repeat block is performed.
At the 15th address, NUM2 is the number of repeats of the internal repeat block. Here, NUM2 is stored into the BRCR register. By the RPTB instruction which is performed at the 16th address, the start address of th internal repeat block is stored into the PASR register, and the end address END.sub.-- BLOCK2 of the repeat block is stored into the PAER register.
At the 17th through 19th addresses, when the internal repeat block is performed once, NUM2 is reduced by "1", and the internal repeat block is repeatedly performed until NUM2 becomes 0(zero).
When NUM2 becomes 0 and then the arithmetic operation is finished in the internal repeat block, at the 21st and 23rd addresses, the values loaded in the temporary registers TEMP1, TEMP2 and TEMP3 are again stored into the registers BRCR, PASR, and PAER, respectively.
At the 24th through 29th addresses, a predetermined instruction is performed, and at the 30th address, the value stored into the BRCR register is loaded into the accumulator. At the 31st address, the value loaded into the accumulator is decreased by "1".
At the 32nd address, the value loaded into the accumulator is judged to be a non-equal zero. As a result of the judgement, if the condition is satisfied, the address is jumped to the address of STARTBLK. Otherwise, the external block, namely, the entire program is terminated.
FIG. 2 illustrates a DSP hardware apparatus which is implemented based on the program of FIG. 1. In the drawings, reference numeral 1 denotes a BRAF register which indicates a start of a repeat block, 2 denotes a PASR register which loads the start address of the repeat block, 3 denotes a PAER register which loads the end address of the repeat block, 4 denotes a BRCR register which loads the number of repeats of the repeat block, 5 denotes a program counter (PC), 6 denotes a comparison unit, and 7 denotes a multiplexer which determines the value of the program counter 5 and the next value of the program counter 5 based on the value loaded into the PASR register 2, respectively.
The operation of the internal repeat block of FIG. 1 will now be explained.
When a control code ss which indicates a start of the system is inputted from the BRAF register 1, an address corresponding to the instruction which is currently performed is inputted from the comparison unit 6 to the program counter 5, and the value END.sub.-- BLOCK is inputted from the PAER register 3.
The comparison unit 6 reduces the value stored in the BRCR register 4 by 1. If the thusly reduced value is not "0", the values are compared whether the value inputted from the program counter 5 is identical with the value END.sub.-- BLOCK1, and then the control code cs concerning thereto is outputted to the multiplexer 7. The multiplexer 7 receives the value of STARTBLK from the PASR register 2 and the output value from the program counter 5. The multiplexer 7 selects one value between two values and outputs to the program counter 5.
The above-described routine is repeatedly performed until the value stored in the BRCR register 4 becomes "0".
In the conventional method of processing an arithmetic operation which is repeatedly performed in the DSP, when the internal repeat blocks and the external repeat blocks are concurrently used, an additional process is needed for processing an arithmetic operation with respect to multiple repeat blocks.
In order to process an arithmetic operation with respect to the multiple repeat blocks, three temporary registers are additionally used. Therefore, the instructions SMMR and LMMR which are related to the temporary registers should be processed. In addition, the LAC, SUB and conditional branch which are instructions for repeatedly performing the external repeat block should be used.
In addition, since a nested loop is used in a computer program language such as C, Pascal, etc., an additional process for processing an arithmetic operation with respect to the multiple repeat blocks is not needed. However, in the above-described technique, since the nested loop can not be used, the time required to process the instructions related to the multiple repeat blocks is overloaded.
Furthermore, as the number of repeats of the repeat block is increased, the time overload is more increased. Therefore, the processing performance of the DSP is decreased.
USPTO Backgrounds
USPTO Backgrounds