Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), rapid thermal processing (RTP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Due to the ever shrinking integrated circuit node sizes, the characterization of semiconductor wafer geometry has become increasingly important. Wafer geometry has traditionally been classified with parameters that vary at low frequency across a given wafer. Such characteristics may include shape and/or flatness. Shape is typically defined as the deviation of the median surface of a wafer from a reference plane, and is quantified using a global metric, such as warp or bow. Flatness is defined as the thickness variation of a substrate with the back surface assumed to be completely flat, and is characterized by site-based metrics such as SFQR (site front surface least square fit plane range).
Shape characterization is performed using methods that measure large variations across an entire surface of a wafer. In addition to the low frequency components of wafer shape it is advantageous to quantify the higher order components of shape, which are limited to localized regions of the substrate, and generally cannot be characteristic satisfactorily using a global shape metric, such as warp and bow. With increased demand on defocus and overlay budgets, the importance of high order shape characterization continues to increase. In addition, the application of semiconductor processes to a wafer may impact wafer topography, such as wafer shape. These changes in wafer shape lead to in-plane as well as out-of-plane distortions of the wafer.
An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. Overlay error is traditionally determined with an overlay target having structures formed on one or more layers of a semiconductor wafer. If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. Overlay error is the misalignment between any of the patterns used at different stages of semiconductor integrated circuit manufacturing.
The in-plane distortions created by changes in wafer shape result in a misregistration between features in sequential patterning steps, which are manifest in measured overlay error between the patterned layers. As such, there is a need for improved wafer shape and wafer shape change characterization. As such, it is advantageous to provide a method and system that remedies these identified deficiencies.
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