DRAM integrated circuit arrays have existed for more than twenty five years and have evolved from the earliest one kilobit (Kb) generation to the recent 256 megabit (Mb) generation. This dramatic increase in storage capacity has been achieved through advances in semiconductor fabrication technology and circuit design technology. The tremendous advances in these two technologies have also achieved higher and higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
A DRAM memory cell typically comprises, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of a charge. Typically, a charge of one polarity is stored on the capacitor to represent a binary ONE, and a stored charge of the opposite polarity represents a binary ZERO. The basic drawback of a DRAM is that the charge on the capacitor eventually leaks away and therefore provisions must be made to "refresh" the capacitor charge or else the data bit stored by the memory cell is lost.
The memory cell of a conventional SRAM, on the other hand, comprises, as basic components, an access transistor or transistors and a memory element in the form of two or more integrated circuit devices interconnected to function as a bistable latch. An example of such a bistable latch is cross-coupled inverters. Bistable latches do not need to be "refreshed", as in the case of DRAM memory cells, and will reliably store a data bit indefinitely as long as they continue to receive supply voltage.
Efforts continue to identify other forms of memory elements for use in SRAMs. Recent studies have focused on resistive materials that can be programmed to exhibit either high or low stable ohmic states. A memory element of such material could be programmed (set) to a high resistive state to store, for example, a ONE data bit or programmed to a low resistive state to store a ZERO data bit. The stored data bit could then be retrieved by detecting the magnitude of a readout current switched through the resistive memory element by an access device, thus indicating the stable resistance state it had previously been programmed to.
A known programmable, bistable resistive material is chalcogenide, as disclosed in Ovshinsky et al., U.S. Pat. No. 5,414,271, the disclosure of which is incorporated herein by reference. Typical chalcogenide compositions for memory elements include average concentrations of Te in the amorphous state well below 70%, typically below about 60% and ranging in general from as low as about 23% up to about 56% Te and most preferably to about 48% to 56% Te. Concentrations of Ge are typically above about 15% and range from a low of about 17% to about 44%, but remaining generally below 50% Ge, with the remainder of the principal constituent elements in this class being Sb. The percentages given are atomic percentages, which total 100% of the atoms of the constituent elements. This class of materials is typically characterized as Te.sub.a Ge.sub.b SB.sub.100-(a+b), where a is equal to or less than about 70% and preferably between about 60% to about 40%, b is above about 15% and less than 50%, preferably between about 17% to about 44% and the remainder is Sb.
A memory element comprised of chalcogenide material can be programmed to a stable high resistive state by passing a narrow, high amplitude current pulse through it. A lower amplitude current pulse of longer duration programs the chalcogenide memory element to a stable, low resistive state. The chalcogenide memory element is simply written over by the appropriate current pulse to reprogram it, and thus does not need to be erased. Moreover, the memory element of chalcogenide material is nonvolatile, in that it need not be connected to a power supply to retain its programmed high or low resistive state.
It has, however, been discovered that a chalcogenide material, once formed as memory elements suitable for integration into an SRAM matrix array, must be electrically conditioned in order to optimize memory element characteristics, basically with regard to reducing the levels and durations of the current pulses required to reprogram it. One suitable conditioning process has been found to involve passing a conditioning current of varying amplitude through the memory elements.
Unfortunately, the conditioning voltage and current magnitudes, required to render the chalcogenide memory elements optimally programmable, exceed the current carrying capacities of SRAM components, such as the memory cell access transistors. Thus, conditioning the memory elements can not utilize the read/write access circuitry of the finished SRAM that would necessarily require the access transistors to conduct the conditioning current. The problem then becomes how to condition the resistive memory elements of the multitude of memory cells of an SRAM matrix array in a cost effective manner without involving memory cell access circuitry, particularly the access transistors.
USPTO Backgrounds
USPTO Backgrounds