Continuous development of more multifunctional and faster semiconductor devices has resulted in an increase in the number of electrode pads (hereinafter referred to as IC pads) provided on an IC chip for connections to an external circuit. Accordingly, a wire bonding scheme of connecting IC pads formed on the periphery of the IC chip to an external circuit via wires has reached performance limits. Thus, a flip chip scheme has been more frequently adopted which involves connecting the IC pads to the external circuit via bumps (projecting electrodes) in order to increase the number of IC pads while minimizing the size of the IC chip.
However, to mount an IC chip with a large number of IC pads on a mother board (mounting board) in an electronic apparatus in accordance with the flip chip scheme, it is necessary to match the land pitch of the mother board with the pad pitch of the IC pads. Consequently, the mother board must be an expensive wiring board on which fine wires can be formed. This is not economical.
Thus, attempts have been made to make wiring rules lenient by using, as an intermediate board (interposer), a resin board (for example, a buildup wiring board) or a ceramic wiring board produced in accordance with intermediate wiring rules between those for the pad pitch of the IC pads and those for an inexpensive mother board.
The interposer also serves to relax thermal stress imposed on solder connections between the IC pads (in actuality, bumps formed on the IC pads) on the IC chip and mounting lands on the mother board, that is, thermal stress resulting from a difference in the coefficient of liner thermal expansion between the IC chip and the mother board (see, for example, Japanese Patent Laid-Open No. 9-64236 and Japanese Patent Laid-Open No. 2001-102492).
However, for resin wiring boards, wires are formed using a plating technique called an additive method. Accordingly, the wiring pitch is limited in terms of the flatness of a base board. For ceramic wiring boards, wires are formed by printing with a conductive paste, preventing the formation of fine wires.
Thus, to cope with the further reduced pitch of the IC pads, a proposal has been made to use a silicon wiring board as a first interposer to increase the pad pitch and to connect the silicon wiring board to a second interposer (for example, a resin wiring board).
However, for silicon wiring boards, wires are formed by deposition or the like, preventing an increase in the cross section of each wire. The wiring resistance of connection wires thus poses a problem when the silicon wiring board is used as an interposer between a high-speed signal or large-current IC chip and an external circuit.
To cope with this problem, a proposal has been made of a structure in which a low-melting-point metal layer is integrally formed on a wiring layer comprising output signal wires or the like through which a relatively large current flows (see, for example, Japanese Patent Laid-Open 61-194744). With this structure, as shown in FIG. 7, a low-melting-point metal layer 103 is formed on a selected wire such as an aluminum wire 102 on a silicon wiring board 101 by a deposition process. The low-melting-point metal layer 103 is then melted and integrated with the wire, while being raised by surface tension. This increases the wiring cross section. The sectional shape of the low-melting-point metal layer 103 portion becomes semi-circular as shown in the figure.
However, for small-pitch wiring, the width of each wire itself needs to be reduced. It is thus difficult to increase the cross section even by raising the low-melting-point metal layer on the wire as described above.
USPTO Backgrounds
USPTO Backgrounds