1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Semiconductor) type semiconductor device, and more particularly to the structure of an element-isolation region provided in the MOS.
2. Description of the Related Art
Microfabrication of semiconductor devices has recently advanced. To realize microfabrication of semiconductor devices and enhance the performance, such as current drivability, of the devices, scaling down is performed in accordance with a predetermined scaling rule. To scale down semiconductor devices, it is also necessary to scale down element isolation regions provided for electrically isolating element regions formed in its semiconductor substrate.
However, there are indications that the performance of a semiconductor device will vary if the diffusion layers forming the source and drain regions of a MOS transistor formed in and on an element region are reduced. This is because the insulating layer filled in the element isolation region produces stress in the element region. More specifically, in, for example, so-called shallow trench isolation (STI) in which a trench is formed in a substrate and filled with an insulating layer, thereby providing an element isolation region, the insulating layer produces stress in the element regions. As a result, the mobility of electrons or holes in a MOS transistor formed in and on each element region varies, which causes the performance of the semiconductor device to vary (see document 1 (G. Scott et al., IEDM Tech. Dig. 1999, pp. 827–830); document 2 (K. Rim et al., VLSI Symp., 2001, p. 59); and document 3 (K. Rim et al., VLSI Symp., 2002, p. 98)).
In existing CMOS devices, Si, for example, is used as the material of element regions, while an SiO2-based material, such as TEOS, is used as the material of element isolation regions. Since the coefficient of thermal expansion of SiO2 is lower than that of Si, an element isolation region produces stress in an element region, compressing the element region. In other words, when each material is cooled from a high temperature to room temperature after a thermal process, Si contracts more than SiO2. At this time, compressive stress is produced in the element region by the element isolation region that contracts less than the element region. As a result, in an NMOS transistor provided at the element region, the mobility of electrons is reduced due to the compressive stress. This means that the NMOS transistor is degraded in performance, compared to transistors in which the source/drain regions have a large area.
USPTO Backgrounds
USPTO Backgrounds