1. Field
Example embodiments relate to a package on package structure, and more particularly to a package on package (POP) structure that may be made by vertically laminating one or more semiconductor packages.
2. Description of the Related Art
Semiconductor packages have been developed in the direction of satisfying demands for multifunction, high capacity, and miniaturization. For this, a system in package (SIP), in which several semiconductor packages are integrated into one semiconductor package to achieve the high capacity and multifunction and to greatly reduce the size of the semiconductor package, has been proposed.
The SIP has progressed briefly from two sides. One is a multi-chip package (MCP) in which several semiconductor chips are formed to be laminated inside one semiconductor package, and the other is the package on package (POP) in which semiconductor packages, which are separately assembled and of which an electric inspection has been completed, are formed to be vertically laminated.
Hereinafter, with reference to FIGS. 1 to 3, a package on package (POP) structure in the related art will be briefly described. FIGS. 1 and 2 are sectional views illustrating an upper semiconductor package and a lower semiconductor package in the related art, and FIG. 3 is a sectional view illustrating a structure in which packages as illustrated in FIGS. 1 and 2 are laminated.
Referring to FIG. 1, an upper semiconductor package 100 includes a substrate 102, a semiconductor chip 104, an encapsulant 108, and solder balls 110.
The semiconductor chip 104 is attached to an upper surface 112 of the substrate 102, and is electrically connected to wire bonding pads (not illustrated) of the substrate 102 by wires 106.
The encapsulant 108 is formed on the whole upper surface 112 of the substrate 102 to cover the semiconductor chip 104 and the wires 106.
The solder balls 110 are attached to a lower surface 114 of the substrate 102, and are electrically connected to the semiconductor chip 104 through a printed circuit pattern (not illustrated) formed in the substrate 102.
Referring to FIG. 2, a lower semiconductor chip 200 includes a substrate 202, a semiconductor chip 204, an encapsulant 208, and solder balls 210, and further includes a plurality of connection pads 216.
The semiconductor chip 204 is attached to an upper surface 212 of the substrate 202, and is electrically connected to wire bonding pads (not illustrated) of the substrate 202 by wires 206.
The encapsulant 208 is formed on a portion of the upper surface 212 of the substrate 202 to cover the semiconductor chip 204 and the wires 206. Specifically, the encapsulant 208 is not formed on the upper surface 212 of the substrate 102, on which the connection pads 216 are arranged, to expose the connection pads 216.
The solder balls 210 are attached to a lower surface 214 of the substrate 202, and are electrically connected to the semiconductor chip 204 through a printed circuit pattern (not illustrated) &Lined in the substrate 202.
The connection pads 216 are to connect the solder balls 110 of the upper semiconductor package 100 to the lower semiconductor package 200, and are arranged on the upper surface of the substrate 202 to correspond to the solder balls 110 of the upper semiconductor package 100, respectively.
Referring to FIG. 3, the upper semiconductor package 100 is arranged on the upper portion of the lower semiconductor package 200, and the solder balls 110 of the upper semiconductor package 100 are connected to the corresponding connection pads 216, so that the package on package (POP) structure, in which the lower semiconductor package 200 and the upper semiconductor package 100 are laminated, is formed.
However, due to the recent trend of multifunction and high capacity, the number of input/output (I/O) pins of the semiconductor package is increased to cause the pitch and the size of the solder balls to be gradually decreased, whereas the thickness of the semiconductor package is gradually increased as two or more semiconductor chips are packaged in one semiconductor package. Accordingly, it becomes difficult to vertically laminate the semiconductor packages in the above-described manner.
In other words, in the POP structure as described above with reference to FIGS. 1 to 3, if the thickness of the lower semiconductor package 200, and particularly, the thickness of a region where the semiconductor chip 204 is packaged, is increased, the pitch and the size of the solder balls 110 of the upper semiconductor package 100 should also be increased as much as the increment of the thickness in order for the solder balls 110 of the upper semiconductor package 100 to be connected to the connection pads 216 of the lower semiconductor package 200. However, since the pitch and the size of the solder balls 110 are on a decreasing trend as described above, the above-described POP structure cannot be implemented.
USPTO Backgrounds
USPTO Backgrounds