1. Field of the Invention
The present invention relates to a display device, particularly, to an active matrix type display device in which gradation display is carried out by gradation voltage as well as time gradation.
2. Description of the Related Art
The technique that has recently accomplished rapid development is one for manufacturing a semiconductor device in which semiconductor thin films are formed on an inexpensive glass substrate, for example, a thin film transistor (TFT). This is because of growing demand for an active matrix type display device.
For example, in an active matrix type display device, a pixel TFT is put in each of pixel regions as many as several hundred thousands to several millions is arranged in matrix, and electric charge that flows into and out of a pixel electrode connected to each pixel TFT is controlled by switching function of the pixel TFT.
As images acquire higher definition and higher resolution in recent years, demand for multi-gradation display which, desirably, is capable of full color display has been established.
Accompanying the movement regarding display devices towards higher definition and higher resolution, the active matrix type display device that has drawn attention most is a digital driven active matrix type display device which can be driven at a high speed.
The digital driven active matrix type display device needs a D/A converter circuit (DAC) for converting digital video data inputted from the external into analogue data (gradation voltage). There are various kinds of D/A converter circuits.
The multi-gradation display capability of the active matrix type display device is dependent on the capacity of the D/A converter circuit, namely, how many bits of digital video data the D/A converter circuit is capable of converting into analogue data. For instance, in general, a display device having a D/A converter circuit that processes 2 bit digital video data is capable of 22=4 gradation display. If the circuit processes 8 bit data, the device is capable of 28=256 gradation display, if n bit, 2n gradation display.
However, enhancement of the capacity of the D/A converter circuit costs complicated circuit structure and enlarged layout area for the D/A converter circuit. According to a lately reported display device, a D/A converter circuit is formed on the same substrate where a pixel region is formed, using a poly silicon TFT. In this case, however, the structure of the D/A converter circuit is complicated to lower the yield of the D/A converter circuit, resulting in yield decrease of the display device. In addition, increased layout area of the D/A converter circuit makes it difficult to downsize the display device.
USPTO Backgrounds
USPTO Backgrounds