1. Field of the Invention
This invention relates in general to the fabrication of semiconductor integrated circuit (IC) devices and, in particularly, to the fabrication of dynamic random-access memory (DRAM) IC devices. More particularly, this invention relates to the fabrication of storage capacitors for the memory cell units of DRAM IC devices.
2. Description of Related Art
FIG. 1 illustrates the schematic diagram of the circuit of a memory cell unit in the memory array of a typical DRAM device. As is illustrated, a transfer transistor T and a storage capacitor C constitute a basic memory cell unit for a DRAM. The source terminal of the transfer transistor T is connected to a corresponding bit line BL for the memory cell unit in the array, while the drain thereof is connected to one electrode 10 of the storage capacitor C. Gate electrode of the transfer transistor T is strobed by a word line WL of the memory array. Electrode 12 of the storage capacitor C opposite to electrode 10 is connected to a fixed electrical potential of the DRAM system, for example, the ground potential. Sandwiched between the electrodes 10 and 12 of the storage capacitor C is a layer of dielectric material 14.
FIG. 2 depicts the cross-sectional view of a conventional DRAM memory cell unit. In the illustrated configuration, although only one is seen in the drawing, a series of field oxide regions 21 are formed in the semiconductor substrate 20 for providing electrical insulation between active regions of consecutive memory cell units in the array. Over the surface of the field oxide 21, a gate structure is formed by subsequently forming a gate oxide layer 22, a polysilicon layer 23 and a cap oxide layer 24 and then patterning. Sidewall of this gate structure is covered by sidewall spacer 25 formed of deposited oxide. A self-aligned procedure then follows to form the source/drain regions 26a and 26b in the substrate 20, forming a cell unit MOS transistor. A polysilicon layer is then formed and patterned to contact one of the transistor source/drain regions 26b electrically which serves as the bit line 27 for the cell unit. In a blanket deposition procedure, an insulating layer 28 such as oxide then covers the substrate and the gate structure formed thereon. A photolithographic procedure then patterns the insulating layer 28 to form a self-aligned contact opening 29, which exposes one of the transistor source/drain regions 26a. The subsequent fabrication procedures then forms the bottom electrode for the cell unit storage capacitor.
Due to resolution limitations in photolithography, dimension of the contact opening 29 can not be made sufficiently small for typical DRAM memory cell units. This requires the reduction of the thickness of the insulation layer that isolates the gate electrode 23 from the conductive layer formed after the gate. Potential short-circuiting between the two deteriorates the yield rate of the DRAM devices fabricated.
Meanwhile, in the continuous effort of seeking to increase the charge-storing capacity of the cell unit storage capacitors for DRAM devices, other than utilizing materials with higher dielectric constant or controlling both the quality and thickness of the deposited dielectric layer, another straight-forward strategy is to increase the surface area of the capacitor electrodes. This efforts however, contradicts the tendency that cell units of DRAM devices are being made ever smaller as a result of increased fabrication resolution. The dilemma of making larger storage capacitor electrode surface area out of ever shrinking average capacitor die area has been a problem for DRAM fabrication design.
Conventional measures to increase the storage capacitor bottom electrode surface area has been to fabricate non-planar surface characteristics for the electrode. Configurations known as crown-, pillar-, fin-, tree- or cavity-shaped bottom electrodes have been made, and some are further added with a hemispherical-grain polysilicon (HSG-Si) layer over the electrode surface. All these are aimed at increasing the electrode surface area for the storage capacitor.
USPTO Backgrounds
USPTO Backgrounds