This invention relates to the output buffer stages of integrated circuits. More specifically, this invention relates to so-called "triple state" output buffers. A triple state output buffer has three potential states relative to its output terminal. Those states are logical 1 (i.e., providing current when the output terminal voltage is above the logical 1 voltage level), logical 0 (i.e., drawing current when the output terminal voltage is below the logical 0 voltage level), and high impedance (i.e., neither sourcing or sinking current thereby allowing the output terminal voltage to be determined by external circuitry). In addition, this invention relates to triple state output buffers which are capable of maintaining the high impedance output state when the output terminal of the buffer is connected to a data bus which may have a wide range of voltage levels above and below the supply voltage levels.
FIG. 1 is a schematic diagram of a simple prior art output buffer capable of functioning as a triple state output buffer. Transistor 4 is a PNP bipolar pull-up transistor. Transistor 5 is an NPN bipolar pull-down transistor. When the input signal on terminal 1 is a logical 0 (approximately 0 volts) and the input signal on terminal 2 is a logical 0, transistor 4 is on and transistor 5 is off, thereby connecting output terminal 3 to positive voltage source V and providing a logical 1 output signal (approximately 5 volts). Conversely, when the input signal on terminal 1 is a logical 1 and the input signal on terminal 2 is a logical 1, transistor 4 is off and transistor 5 is on, thereby connecting output terminal 3 to ground 6, thereby providing a logical 0 output signal. When the input signal on terminal 1 is a logical 1 and the input signal on terminal 2 is a logical 0, transistor 4 is off and transistor 5 is off and output terminal 3 has a high impedance output state, which means a high impedance exists between output terminal 3 and positive voltage source V and between output terminal 3 and ground 6. The output buffer in FIG. 1 is undesirable because it requires the use of a PNP transistor. For the purposes of output buffering PNP transistors have two significant problems:
(1) PNP transistors rely on holes as majority carriers and are therefore slower than NPN transistors which rely on electrons as majority carriers (electrons have a higher mobility than holes), and
(2) it is difficult to construct an integrated circuit including vertical NPN transistors and vertical PNP transistors; therefore, slower lateral PNP transistors must be used. These problems cannot be solved using instead vertical PNP transistors and lateral NPN transistors because, as explained below, both lateral NPN and PNP transistors must have a large base region, thereby reducing the speed of the lateral transistor and the circuit containing that lateral transistor.
FIG. 2 is a schematic diagram of a simple prior art output buffer capable of functioning as a triple state output buffer which uses only NPN transistors. Transistor 8 is a NPN bipolar pull-up transistor. Transistor 9 is an NPN bipolar pull-down transistor. When the input signal on terminal 11 is a logical 1 and the input signal on terminal 10 is a logical 0, transistor 8 is on and transistor 9 is off, thereby connecting output terminal 12 to positive voltage source V and providing a logical 1 output signal. Conversely, when the signal on input terminal 11 is a logical 0 and the signal on input terminal 10 is a logical 1, transistor 8 is off and transistor 9 is on, thereby connecting output terminal 12 to ground 6, and providing a logical 0 output signal. When the signal on input terminal 11 is a logical 0 and the signal on input terminal 10 is a logical 0, transistors 8 and 9 are off and output terminal 12 has a high impedance output state, which means a high impedance exists between output terminal 12 and positive voltage source V and between output terminal 3 and ground 6. Buffer 13 is undesirable if output terminal 12 is to be connected to a bus (not shown) which may have a voltage level more negative than a logical 0 voltage level, because when buffer 13 has a high impedance output state and the voltage level of output terminal 12 goes below the voltage corresponding to a logical 0 signal, output terminal 12 is clamped to a voltage level of one base to emitter voltage drop (about 0.7 volts) below the logical 0 level on the base of transistor 8. Thus, buffer 13 sources current, contrary to its intended high impedance state.
FIG. 3a is a cross-sectional diagram of one method of constructing a vertical NPN transistor. Vertical NPN transistor 30 includes an emitter region 35, base region 34, and a collector which is formed by the combination of regions 33 and 32. Region 32 is an epitaxial layer of N type material formed upon P type substrate 31. Region 33 is a buried diffusion of N+ type material. Region 36 is an isolation diffusion made of P type material which isolates transistor 30 from other components (not shown) constructed in epitaxial layer 32. In order to provide vertical PNP transistors in an integrated circuit where N type transistors are constructed as shown in FIG. 3a, another masking and diffusion step must be performed in order to form a P region 67 in N region 35 (as shown in FIG. 3b). Vertical PNP transistor 60 in FIG. 3b includes base region 65, emitter region 67, and collector region 64. Another masking and diffusion step in the process is undesirable because each diffusion step creates additional expense in the manufacture of the integrated circuit. More importantly, if a P type diffusion is added to create a vertical PNP transistor, the concentrations of the N type diffusions will have to be modified; this results in substandard NPN devices. In order to avoid the additional masking and diffusion step and the accompanying performance degradation, it becomes necessary to use a lateral PNP transistor.
FIG. 3c is a cross-sectional diagram of a lateral PNP transistor 40. Region 41 is a P type substrate, and region 42 is an N type epitaxial layer formed on P type substrate 41. N type epitaxial layer 42 functions as the base region for lateral PNP transistor 40. Regions 43 and 44 are P type diffusion areas formed in N type epitaxial layer 42; these regions form the collector and emitter, respectively, of lateral PNP transistor 40. Region 45 is a P type isolation region which isolates lateral PNP transistor 40 from other components (not shown) formed in epitaxial layer 42. Collector 43 and emitter 44 must be spaced apart in order for the lateral PNP transistor 40 to function. In order to compensate for the inaccuracies of integrated circuit fabrication caused by photolithographic inaccuracies and lateral diffusion of dopants, collector 43 and emitter 44 must be spaced relatively far apart (approximately 6.5 microns) to avoid having collector 43 and emitter 44 run together during the diffusion process. Lateral PNP transistors are relatively slow due to the relatively large base region created by the wide spacing between collector 43 and emitter 44, and due to the low mobility of holes, which serve as the majority carriers in a PNP transistor.
FIG. 4a is a schematic diagram of an output buffer containing NPN pull-up transistor 56 and NPN pull-down transistor 54. When input terminal 51 receives a logical 1 input signal, transistor 52 is forward biased and is therefore on, and current flows from positive voltage source V through resistor 57 and transistor 52 into the base of transistor 54, thereby turning on transistor 54. Transistor 54 thus provides a low impedance path between output terminal 55 and ground 6. Therefore, the output signal of output buffer 50 is a logical 0 in response to a logical 1 input signal received on input terminal 51. Conversely, when the input signal on terminal 51 is a logical 0, transistor 52 is turned off. Therefore, the current provided by resistor 57 flows into the base of transistor 56 and thus forward biases transistor 56, and transistor 56 turns on and provides a low impedance path between positive voltage source V and output terminal 55. Simultaneously, resistor 53 pulls down the base of transistor 54, thus keeping transistor 54 turned off. Thus, the output signal from output buffer 50 is logical 1 in response to a logical 0 input signal. However, circuit 50 is undesirable in that it provides only two output states--logical 1 and logical 0, and is incapable of operating as a triple state output buffer, which is capable of providing a high impedance output signal on its output terminal.
To operate output buffer 50 as a triple state output buffer, NPN transistor 58 is added as shown in FIG. 4b. The high impedance output state is achieved by providing a logical 0 on terminal 51 and a logical 1 on terminal 59. The logical 0 on terminal 51 turns off transistors 52 and 54 as explained earlier. The logical 1 on terminal 59 causes transistor 58 to turn on and pull down the base of transistor 56 so that transistor 56 is turned off. The output signal on output terminal 55 is thus a high impedance state because both transistors 54 and 56 are turned off. The disadvantage with this output buffer circuit is that the high impedance state is maintained over a very narrow output voltage range; if the voltage on output terminal 55 is below ground voltage, transistor 56 turns on and causes output terminal 55 to clamp at a voltage equal to one base-emitter voltage drop below the base voltage of transistor 56.
FIG. 5 is a schematic diagram of an output buffer circuit similar to the output buffer circuit in FIG. 4a, except that circuit 90 includes input terminal 126, PNP transistor 125, Schottky diode 121, Schottky diode 114, and Schottky diode 118. Circuit 90 in FIG. 5 is designed to provide three logical states (logical 1, logical 0, and high impedance) over a wide voltage range on output terminal 113. When the input signal on input terminal 126 is pulled low, transistor 125 is on and therefore functions as a current source much the same as resistor 57 in FIG. 4a. Therefore, when the input signal to input terminal 126 is a logical 0, circuit 90 in FIG. 5 functions in the same manner as circuit 50 in FIG. 4a as explained above. When the input signal to input terminal 126 is a logical 1, transistor 125 is off and therefore no current is supplied to bias either transistors 54 or transistor 56. Therefore, transistors 56 and 54 provide high impedance paths from output terminal 113 to voltage source V and ground 6, respectively. Circuit 90 is designed to be in the high impedance state when the input signal on input terminal 126 is a logical 1, and to maintain this high impedance state over large swings of voltages applied to output terminal 113 (as much as +12 volts above ground and as low as -7 volts below ground 6). Diode 121 is included to prevent current flow from the emitter of transistor 56 (as a result of junction breakdown) to the collector of transistor 56 and then to the voltage source V, when transistor 56 is on and the voltage applied to output terminal 113 is greater than V. Diodes 114 and 118 are included to prevent current flow from the collectors of transistors 52 and 54, respectively, when the voltage on output terminal 113 is below ground. When NPN transistors 52, 54 and 56 are constructed as in FIG. 3a, substrate 31 in FIG. 3a is connected to ground. When a voltage below ground is applied to collector 33, the PN junction between regions 31 and 33 is forward biased. Therefore, if diodes 114 and 118 were not included in circuit 90 (FIG. 5), when the voltage on output terminal 113 became more negative than ground, current would flow from the substrate through the collectors of transistors 52 and 54, and the voltage on output terminal 113 would be clamped to a voltage level equal to one diode voltage drop below ground, when output terminal 113 should be in the high impedance state. Circuit 90 is limited in operational speed by the fact that PNP transistor 125 must be a lateral PNP transistor, for reasons explained earlier. Lateral PNP transistor 125 slows the transition from an enable state to a disable state and vice versa.
USPTO Backgrounds
USPTO Backgrounds