This invention relates to a circuit for driving a high-capacitance wordline of an integrated-circuit memory cell array in response to a voltage input from a decoder circuit.
Wordline driver circuits are used to apply voltages to the program/read gates of floating-gate transistors in integrated-circuit memory-cell arrays. When in the program mode, such drivers translate signals from integrated decoder circuits to signals which must be of sufficiently high voltage to charge the floating gates. When in the read mode, the driver circuits must provide a lower voltage signal having a risetime sufficiently rapid to charge the capacitance associated with and inherent in wordlines. The risetime must be sufficiently rapid to meet the operating speed requirements of the particular integrated circuit.
Construction, in integrated circuit form, of a driver circuit that is capable of furnishing the high voltage necessary for programming and that also provides a rapid response time during the read operation is difficult because driver transistors fabricated in integrated circuit form for high voltage use must have relatively long source-drain channels. The relatively long source-drain channels result in high capacitance characteristics that slow response time and decrease drive capability.
Accordingly, there is a need for an integrated-circuit wordline driver that is capable of providing high voltage signal output for programming floating gate transistors and that is capable of providing a low voltage output signals with rapid response times during read operation.
USPTO Backgrounds
USPTO Backgrounds