The present invention relates to a multiplication system for digital signal processing and, more particularly, to a multiplying method with a positive/negative symmetrical round-off function for reducing an error, and circuitry therefor.
Multiplying circuitry with a round-off function has customarily been used to enhance the accuracy of the result of multiplication, as taught in, e.g., Japanese Patent Laid-Open Publication Nos. 64-53228 and 6-103304. However, the conventional multiplying circuitry has the following problems (1) through (3) left unsolved.
(1) When a plurality of products are accumulated, desired accuracy is not achievable with the round-off function. Specifically, when a ONE is added to a bit just below the figure to be rounded off, the mean value of the figure to be rounded off is not a ZERO. The resulting errors are sequentially accumulated.
(2) A method of the kind correcting an error is not feasible for a microprocessor or similar application which performs correction at each time of operation in order to store the result of operation in a register file. Specifically, assuming n-bit multiplication, a value for correcting an error appears only at a figure even lower than the lowermost bit of a 2n-bit product. Therefore, should the product be rounded of by correction at each time of calculation, the correction value would be rounded down and would thereby prevent the effect of correction from appearing in the resulting product.
(3) The circuitry is not practicable without scaling up hardware. The circuitry proposed in the above Laid-Open Publication No. 6-103304, for example, additionally includes a subtracter for the correction of the mean error of round-off calculation. This scales up hardware and therefore increases the processing time.
USPTO Backgrounds
USPTO Backgrounds