1. Field of the Invention
The present invention relates, in general, to a semiconductor device having a gate, and more particularly to a semiconductor device for preventing the drawbacks due to the use of tungsten as the gate material.
2. Description of the Related Art
For increasingly high integration of the semiconductor devices, the channel length of a transistor is significantly shortened and the threshold voltage of the transistor is set to decrease abruptly, all of which contribute to the so-called “short channel effect” to become more serious. In an effort to increase a channel length of a transistor, many researches for a recess gate were conducted, according to which a recess is defined on a silicon substrate to increase a transistor channel length. A recess gate forming method increases a channel length by forming a gate in a recess; thus, the short channel effect can be reduced when it is compared to a conventional planar gate structure.
Therefore, as the integration degree of a semiconductor device increases, a material having a very low resistance (such as tungsten) is known for use as a gate material when forming a recess gate in order to decrease the resistance of the gate.
Hereafter, a conventional method of forming a recess gate in a semiconductor device which uses tungsten as the gate material is described with reference to FIGS. 1A through 1D.
Referring to FIG. 1A, a isolation layer 2 is formed in a semiconductor substrate 1 through a shallow trench isolation (STI) process to define the active region. Then, an oxide layer 3 and a hard mask layer 4 are sequentially deposited on the substrate 1, which are going to be used as an etch barrier layer for forming a recess gate.
Referring to FIG. 1B, the hard mask layer 4 and the oxide layer 3 are sequentially etched to formed an etch mask through which a plurality of the gate forming regions of the substrate 1 are exposed. Then, the exposed portions of the substrate 1 are etched using the etch mask formed by the etched hard mask layer 4 and the oxide layer 3, to form recesses 5. After forming the recesses 5, the hard mask layer 4 and the oxide layer 3 are sequentially removed. As shown in FIG. 1B, Here, when etching the substrate 1 to define the recess 5, the portions in the isolation layer 2 of the substrate 1 are also partially etched.
Referring to FIG. 1C, a gate oxide layer 6 is formed on the surface of the active region of the substrate 1 including the surface of the recesses 5 in the active region. Then, a polysilicon layer 7, a tungsten nitride layer 8, a tungsten layer 9, and a gate hard mask layer 10 are sequentially formed on the surface of the resultant substrate 1, and these layers are then patterned to form tungsten gates 11 on the recesses 5.
Referring to FIG. 1D, a gate selective oxidation process is performed on the resultant substrate 1 in order to form a re-oxidation layer 12 on the surface of the etched polysilicon layer 7 and on the surface of the active region of the substrate 1 as shown in FIG. 1D. Thereafter, in order to prevent the abnormal oxidization of tungsten by a subsequent process, a gate capping nitride layer 13 is formed on the entire surface of the resultant substrate 1 including the tungsten gate 11.
However, when tungsten is used as the gate material, if process and equipment conditions become unstable while the gate selective oxidization process is conducted, the possibility of an abnormal oxidization phenomenon to occur increases, in which a re-oxidation layer is abnormally formed on tungsten. Also, due to the fact that oxygen can intrude through the tungsten layer 9 to form an insulation layer between tungsten 9 and polysilicon 7 while conducting the gate selective oxidization process and due to issues such as the contamination of tungsten, etc., a detrimental defect can be caused when operating the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds