This invention relates to power MOSFETs and more particularly to a novel process and resulting product which allows a reduction in threshold voltage while retaining a low on-resistance.
MOSFETs and processes for their manufacture are well known. A typical device and process for its manufacture is disclosed in copending application Ser. No. 09/436,302, filed Nov. 8, 1999 entitled LOW VOLTAGE MOSFET AND PROCESS FOR ITS MANUFACTURE AND CIRCUIT APPLICATION (IR-1531) which is incorporated herein by reference.
One limitation encountered in making low voltage (under 50 volts), low on resistance (RDSON) MOSFETs is the Rdson test condition at a low Vgs. To provide a low Vgs gate drive condition the channel component of Rdson becomes increasingly larger, eventually becoming larger than all of the other components combined. There are several known ways of reducing this channel component of on resistance under these circumstances but one of the most direct is to lower the threshold voltage Vth, ensuring that the device is fully on at the low Vgs condition. In many cases the gate oxide thickness can be reduced to lower the threshold voltage. However, when this thickness is fixed due to Vgs max concerns, other means must be used.
The threshold voltage, Vth, can also be reduced if the channel dose is lowered. In addition, the channel junction must be shallow so that the channel length can be kept short. To maintain the shallow channel junction, the overall thermal budget, that is, the cumulative diffusion drive cycles, must be low. This introduces constraints on the shape of the source region so that its shape is more xe2x80x9coblongxe2x80x9d (or elongated in depth) in the vertical direction relative to the substrate surface than under other conditions. This creates a region in the device where the corner of the source region is very near the xe2x80x9ccornerxe2x80x9d (in cross-section) of the channel junction.
FIG. 1 is an idealized sketch of a vertical conduction MOSFET cell after the formation of the source and channel diffusions and a trench for a contact. The structure shown is for a P channel device, although all conductivity types can be reversed for an N channel device. In FIG. 1, a P type epitaxially deposited substrate (and drain region) 10 receives, in a conventional DMOS process, an N type channel implant and diffusion 11 and a P type source implant and diffusion 12. The window in gate structure 13 is the implant widow for both regions 11 and 12. Note that the source junction 12 is very close to channel junction 11 at the corner of the device cell, shown as distance xe2x80x9cXxe2x80x9d. Thus, because, thermal treatment after the formation of channel junction 11 must be kept to a minimum, there is relatively little lateral diffusion of the source junction 12 under gate 13. The shape of source junction 13 is therefore deeper with less lateral spreading than usually found, i.e. more xe2x80x9coblongxe2x80x9d than a typical diffused junction. Consequently, dimension xe2x80x9cXxe2x80x9d is reduced so that, when the diode junction 11 is reverse biased, punchthrough occurs at low voltage.
The punchthrough condition introduces unnecessary leakage from the drain to the source. Punchthrough is a phenomena associated with the merging of the depletion regions of the source and drain junctions and occurs when the channel length is small, so that, as the depletion region forms in the reverse biased body diode, it extends to the source region where majority carriers are forced into the body diode depletion region, creating premature leakage from drain to source, before reaching the avalanche condition. Further, Vth was unstable with time, particularly with P channel devices, (similar to the condition known as walkout). The condition of walkout manifests itself with a gradually increasing voltage as a function of time, for the same applied current. The scale could be a few milliseconds to 100""s of milliseconds (in the worst condition) and is very undesirable.
Referring to FIG. 1, it will be seen that a trench 20 is formed. A heavily doped, shallow N+ base 21 is implanted in the bottom of the trench to serve as a good contact region for the body diode. The trench 20 is especially useful in P channel devices. Body 21 has been made in the past by a phosphorus implant employing normally used implant energies.
Thus, the resulting device in the prior art had a tradeoff of increased on resistance for low Vgs; and further, P channel devices exhibited walkout. More particularly, in the prior art, it was known that Vgs could be reduced by lower channel concentration, at the cost of increased RDSON; or by reducing gate oxide thickness, at the cost of reduced gate ruggedness. Also, it was known that RDSON could be reduced by using a shorter channel and using a deeper source, but that increased the likelihood of punchthrough.
It would be very desirable to provide a process and structure which resolves these tradeoffs in which the Vgs, and RDSON can be both reduced without creating a punchthrough condition or, in P channel devices, a walkout condition.
In accordance with the present invention, both RDSON and Vth are simultaneously reduced by the control of the positions and shapes of the source and channel regions and by the proper control of the spreading of the reversed biased depletion region.
This novel process and design revolves around three concepts:
1) Controlling the relative position and shape of the source and channel regions. This is achieved by making the source implant as shallow as possible to limit punchthrough. Thus, the source implant energy is constrained to be as low as possible, right to the verge of beam blowup. This implant and its associated diffusion is done ideally within the framework of a very shallow channel junction. By way of example, the source and channel implants are preferably less than 0.3 xcexc and 3.0 xcexc, respectively.
2) Controlling the reverse biased depletion region spreading by the amount and distribution of charge buried deep within the channel junction. For a p channel device, this is done by using a very high energy implant, in this case a 200 kV implant of doubly charged phosphorus ions P++ (resulting in an effective 400 keV implant). This implant also helps to limit the occurrence of punchthrough. This is accomplished by a heavy base implant that is placed as deep as possible by implanting doubly ionized phosphorus at very high energies. This charge, when placed strategically, acts as charge balance for the reverse biased diode, limiting depletion spreading into the channel side (as opposed to the epi side) of the junction. Similar concepts apply to the N channel device.
3) In addition, the extra depth of the 400 keV implant helps to make the Vth measurement stable with time. It is thought that when the heavy dose of the P++ implant is deeper due to the high energy of the implant, that the increased charge makes it more difficult for a walkout condition to occur. Typically, walkout occurs in more lightly doped regions (e.g. it is often a problem in high voltage devices).
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