1. Field of the Invention
The present invention relates to a large-scale (e.g., wafer-scale) semiconductor integrated circuit device and a method of retrieving the fault of the same and, more particularly, relates to a technology which is effective for application to a large-scale semiconductor integrated circuit device such as a wafer hole having a memory circuit such as a RAM (Random Access Memory) and a method of relieving a fault therefrom.
2. Description of the Related Art
A known semiconductor memory device made of a very large wafer LSI is exemplified in Japanese Patent Laid-Open No. 59-201441. In this large wafer semiconductor memory device, as disclosed in the above Japanese Patent Laid-Open number, the isolation and relief of a defective chip are accomplished by cutting the fuse or power supply line through irradiation by using a focused ion beam or laser beam and by connecting only good chips (i.e. non-defective chips) through final wiring lines. Topics related to the super LSI of the next generation having the supercomputer functions packed in a silicon wafer having a diameter of about 10 cm has been discussed on Dec. 21, 1985in the Nikkei Sangyo Newspaper.
The large wafer semiconductor integrated circuit device described above has not taken into consideration the signal delay in the internal signal lines, the concentration of the operating current, and aspects concerning improving the versatility thereof, and a variety of problems associated therewith which must be solved for the large-scale semiconductor integrated circuit device having a large wafer to be realizable. On the other hand, the relief of a fault is accomplished by cutting (i.e. electrically isolating) the defective or faulty chip discovered thereby resulting in a problem of a substantial drop in the degree of integration.
USPTO Backgrounds
USPTO Backgrounds