One challenge of designing computer processors is protecting against soft errors, where a bit-flip occurs spontaneously, such as due to radiation events. Since a soft error can change a data value stored in computer memory or affect the outcome of processing an instruction, soft error detection and handling logic is often incorporated into computer processor designs.
Computer processor designs are often tested by creating a model of a design using a hardware description language, such as VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL), and performing a software simulation of the operation of the design based on the model. While such simulations may be employed to test the effects that soft errors have on a design, this can be particularly challenging where a design has a large logic state-space, and where logic for detecting and handling a specific error may behave differently for different instructions or data.
USPTO Backgrounds
USPTO Backgrounds