1. Field of the Invention
The invention relates generally to the field of pulse generators and more specifically to pulse generators which produce very high voltage, current, and power pulses of very brief duration. More particularly, the invention discloses a lumped transmission line oriented pulse generator and pulse shaper utilizing the summed power output of a series of stages wherein each stage consists of at least one avalanche transistor, a decreasing capacitance per stage and a power source for the transistor stages coupled through a respective resistance and zener diode network.
2. Description of Related Art
Avalanche pulse devices have been in general use for some time as have lumped delay lines as specialized transmission lines in which line parameters are adjusted to decrease the velocity of signal transmission. In a lumped-constant delay line, the normally distributed inductance and capacitance per unit length, that one sees in a lengthy transmission line, is synthetically reproduced by a plurality of individual stages coupled in series, wherein each individual stage consists of an inductor and capacitor combination coupled in a low pass filter configuration as illustrated in FIG. 1.
Applicant's pulse generator somewhat parallels the lumped transmission line concept by coupling a plurality of stages in series, wherein the inductor in each stage of the transmission line is replaced by a power source in series with an avalanche transistor, which transistor inherently carries an inductance, and together with a respective capacitor acts like a very fast switch, illustrated in FIG. 2.
Prior art pulse generating circuits utilizing avalanche transistors and tunnel diodes have been implemented in the past to develop high power pulses at high repetition rates. Such pulse generating circuits utilizing avalanche transistors conventionally require a storage capacitor coupled in the load current path for limiting the peak current during avalanche multiplication so as to prevent damage to the transistor. Traditional setups require the transistor to be biased to an avalanche operating point by a power supply and biasing resistor coupled in series to a point between the capacitor and the load current circuit of the transistor. The capacitor conventionally recharges after formation of each output pulse by current flowing through a biasing resistor from the power supply.
Although the prior art pulse generator described included a plurality of sequentially operating pulse generator stages wherein each stage includes an avalanche transistor, the stages were coupled in parallel, not in series like the present invention, and for the purpose of increasing pulse repetition rates as opposed to applicant's intent to substantially increase power regardless of repetition rate. Such prior art in fact teaches away from applicant's concept.
Other pulse generators using strings of avalanche transistors have been around for a long time. Strings of avalanche transistors were used by applicant in an accelerator beam sweeper as early as 1970 and strings of avalanche transistor pulsers have been produced by Kentec, a British Company, which produce 5 kV pulses with 100 picosecond widths.
In still other circuits pairs of avalanche transistors in series have been utilized as a pulse shaping device with the output of a second transistor cutting short the output of a first transistor. Other avalanche transistor string circuits have been designed for generating variable delay pulses; however, such circuits again were of a parallel circuit design.
Although other parallel and series coupled avalanche transistor pulse generators have been conceived with capacitors to build up current to add power to a pulse, the current and voltage limitations inherent in all the prior art continues to necessitate a pulse generator of even greater capacity such as the type disclosed herein.
In none of the prior art was there any disclosure nor suggestion to stack multiple avalanche transistors in parallel to enable a large current flow, then couple the stacks in a series of stages to combine all the current flow, and shunting a plurality of RC balanced capacitors in parallel through the stages to enable the avalanche transistor to turn on hard with high and constant current flow.
USPTO Backgrounds
USPTO Backgrounds