The present invention relates generally to electronic circuits that delay digital signals in continuous time and in particular to circuits used in time-to-digital convertors (TDC), digital phase locked loops (PLLs), fractional-N PLLs, and clock deskew circuits.
Typically, a delay line comprises a delay chain, which is a chain of delay elements. This is illustrated in FIG. 1, where the delay line 100 comprises a single-ended delay chain 110, built up with N consecutive delay elements 120, where N is 1 or larger. Usually a delay element consists of one or more digital gates, whereby a variety of gates may be used, the simplest and often fastest being a single inverter, as depicted. In this case, the successive outputs will have alternating polarity. The overline on outputs OUT1, OUT3 and successive odd-numbered outputs indicates that their polarity is reversed in reference to the input signal IN. The resolution of the delay line equals the average delay T of single inverters (the nominal or unit delay time), and the range provided by the delay line equals N×T.
In physical embodiments of delay lines, manufacturing tolerances can cause mismatch between the components, leading to differences in delay between different instances of the delay element that are designed to be identical. Thus, the real delay of a given delay element may not be accurately known. For some manufacturing processes, including for components integrated on a single semiconductor chip, these differences can be significant. When delays vary between instances that have been designed to be identical, all identical instances are considered to have a nominal delay and each individual instance has a real delay which is the nominal delay plus or minus some error. In some applications, alternating polarity signals can be used as easily as signals of the same polarity. In other applications, the polarity must be the same for all outputs. In such a case, every second output may be used, at the expense of loss of resolution (which becomes 2τ).
One common solution is to use a differential delay chain (see FIG. 2), which offers both inverted and non-inverted polarity signals. The delay chain 200 comprises N consecutive delay elements 210. The delay elements each delay both the propagated IN and overline IN signals. Although the polarity alternates using simple inverters, at each stage J there is an output signal OUTJ as well as an inverted signal OUTJ available.
Due to mismatch between the physical circuits, significant skew might appear between the two propagating signals. This can be corrected by using deskew circuits W (230) in the delay elements. This may comprise cross-coupled weak inverters as shown in detail in box 240. In this context, weak means that the drive strength of the cross-coupled inverters is less than that of the forward inverters in the chain, so that the cross-coupled inverters can help but not dominate the state of the output nodes. The inverter pair helps to deskew the propagating signals by speeding up the slow output node and slowing down the fast output node.
The above differential delay chain solves some important limitations. However, other design disadvantages include sensitivity of the delay to temperature and slow and fast power supply variations, and the fact that some applications require a resolution which is finer than the average delay of a single inverter. Yet other applications require a delay time that can be controlled.
To reduce the delay sensitivity to temperature and supply voltage, or to control the unit delay, the delay chain can operate from a regulated supply voltage. An alternative approach is current starving the gates, where the gates essentially no longer operate from a regulated supply voltage but from a regulated supply current. In either case, the regulated supply can be used to compensate for temperature variation, or to control the average delay of the delay elements. Whether a regulated supply voltage or regulated supply current is used, designers have to make sure that the output of such a supply source has a sufficiently high bandwidth, otherwise short-term timing variations or jitter will occur. One approach has been described in U.S. Pat. No. 6,476,656 (W. J. Daily et al.).
A further way of controlling the speed of the delay elements is by varying the back-gate voltage of the MOS transistors used in the gates.
In applications where not all outputs (output taps) are used simultaneously, the resolution can be improved below τ by selecting two neighboring outputs and passing their signals to a phase splitter or phase generator, which interpolates a few more phases. However, this solution is impractical for applications where all signals need to be available simultaneously.
Phase generators are commonly built using phase blenders, blocks that provide a phase blending technique (illustrated in FIGS. 3a-b). Signals with phase ΦAin, and ΦBin, which are one unit delay apart, are applied to the inputs in order to create an output signal, the phase ΦABout of which is in between ΦAout and ΦBout. FIG. 3a shows a non-inverting circuit that propagates both ΦA and ΦB along with ΦAB. FIG. 3b shows a reduced circuit which does not propagate ΦB, only the inverted versions of ΦA and ΦAB. Phase blenders in current mode logic (CML) have a topology modified from FIGS. 3a-b (not depicted).
The circuit of FIGS. 3a-b can generate any phase ΦABout in between ΦAout and ΦBout. The relative strengths of the inverters in the path from ΦAin to ΦABout and ΦBin to ΦABout control the phase, with more strength in the path from ΦAin pulling ΦABout closer to ΦAout and more strength in the path from ΦBin pulling ΦABout closer to ΦBout. By replicating the part of the circuit that generates ΦABout, and changing the ratios on the different instances, multiple output phases can be generated simultaneously.
Multistage approaches are common, where the output signals of one blender can be used as inputs for two or more blenders in the next stage. Phase generators according to different topologies have also been reported.
Using modern IC fabrication processes, where components do not match accurately, phase blenders and phase generators have limited timing accuracy, and signals propagate through a delay chain at variable speed. Thus, an unmet need exists for a system that overcomes the accuracy problems and provides a resolution smaller than the nominal delay τ.
USPTO Backgrounds
USPTO Backgrounds