The present invention relates to semiconductor devices and, more particularly, to the novel use of an elongated, relatively narrow ribbon of resistive material in an edge passivation structure of a semiconductor device for increasing the breakdown voltage of the device.
The maximum reverse voltage that a semiconductor device having a P-N junction can withstand is limited by the breakdown voltage of the junction. The actual breakdown voltage of the junction normally falls short of the theoretical breakdown voltage because excessively strong electric fields are present at certain locations in the device under reverse bias. One of the locations most susceptible to formation of excessively strong electric fields is in the perimeter of the device where the P-N junction terminates. In this region a transition is made from an electric field supported within the semiconductor material to an electric field supported within the surrounding dielectric material. Further discussion of this phenomenon may be found in Semiconductor Power Devices by S. K. Ghandhi beginning at page 56.
High voltage semiconductor devices may include an edge passivation structure to reduce the intensity of the electric fields associated with P-N junction termination. The edge passivation structure provides an area for transition from the high electric potential gradient in the active area of the device to the different electric potential gradient at the edge of the device. The edge passivation structure reduces field intensity by spreading the equipotential lines across the edge passivation region, thereby reducing the crowding of the equipotential lines (i.e., reducing the voltage gradient). The transition from the one potential gradient in the active area to the other potential gradient at the edge of the device is desirably made without introducing excess current leakage and without trapping surface charges that may crowd the equipotential lines and cause localized avalanching or induce channel leakages in the underlying silicon.
Various edge passivation structures are known in the art, including beveled edges, depletion-etched edges, graded-density depletable regions, conductive field plates, resistive field plates, conductive top-surface equipotential rings, diffused equipotential rings, subsurface equipotential rings, etc. depending, at least in part, on the voltage of the device.
For example, devices operable up to about 600 volts may use diffused equipotential rings with graded spaces between the rings such as shown in FIG. 1. In such devices, the edge passivation region 10 between the active area 12 and edge region 14 of the device may include annular guard rings 16 that are diffused into the body of the device. A layer of silicon dioxide 20 may be deposited on top of the body followed by an insulative layer such as phosphorous silicon glass 22 followed by an appropriate overcoat 24. The annular guard rings 16 each have a different potential that varies from the potential in the active region 12 to that of the edge region 14.
Because the present invention relates to a variety of semiconductor devices in which edge passivation is desirable, the device of FIG. 1 and all subsequent devices are depicted and discussed without reference to the structure of the device below the P-N junction. It is understood by those skilled in the art that the present invention is applicable to many different types of devices having many different types of structures below (or above) the P-N junction.
As may be seen in FIG. 1, the equipotential lines in the region 26 adjacent the curved portion 28 of the P-N junction 30 are spread into the passivation region 10 by the annular rings 16, instead of following the contour of the curved portion 28 of the junction 30 and crowding together at the surface of the device.
In the absence of extraneous surface charges, such a structure may be adequate for some applications. However, in the presence of surface charges the equipotential lines become crowded at one end or the other (depending on the polarity of the charges) causing high surface fields and surface leakage due to localized unstable avalanche breakdown in the high field regions near the surface. Another disadvantage of such diffused edge passivation structures is that they use a lot of chip surface area. The minimum space between diffused rings is approximately equal to the minimum line width capability of the photomask operation plus approximately twice the diffusion depth. To compound this problem, the ring-to-ring voltage is not firmly fixed so that extra rings and extra space must be included to allow for variations.
Another known structure which is less influenced by surface charges is the resistive field plate illustrated in FIG. 2. In this structure, a plate 32 of resistive material extends between the active area 12 and the edge region 14 of the device. The voltage difference between the active area and the edge region is spread out linearly across the field plate 32. The field inside the body of the device is forced to spread out over the same distance as in the overlying field plate thereby spreading the equipotential lines in a fashion similar to that shown in FIG. 1. The body is shielded from charges outside the plate so as to reduce the influence of the surface charges. While this is an effective means of edge passivation, it is not commonly used because the resistive layer 32 must have a very high sheet resistivity, on the order of gigohms per square, in order to avoid excessive leakage through the layer 32. Such high resistivity layers are difficult to construct using the materials and processes commonly employed in the manufacture of semiconductor devices.
Another known edge passivation structure includes annular equipotential rings 34 such as illustrated in FIG. 3. The rings are connected by resistors or diodes (not shown) to force voltage to be distributed uniformly from ring-to-ring across the edge passivation area 10. Because the potential of each of the rings is set by the resistors (or diodes), the voltage in the body beneath the rings is also forced to spread out across the passivation area independently of any surface charges. As the potential of each of the rings is set, their resistivity is not critical (in contrast to the resistive field plate in FIG. 2) so that the materials for the rings may be selected from those commonly used in the fabrication of semiconductor devices, such as metal or polysilicon. As is apparent, however, the rings must be connected by resistors or diodes that are added in potentially costly and extra fabrication steps.
Accordingly, it is an object of the present invention to provide a novel structure for an edge passivation region that obviates the above described problems of the prior art.
It is another object of the present invention to provide a novel structure for an edge passivation region for a semiconductor device in which the electrical potential difference between the active area and the edge region of the device is spread along an electrically resistive ribbon that spirals around the active area.
It is yet another object of the present invention to provide a novel structure for an edge passivation region for a semiconductor device in which the electrical potential difference between the active area and the edge region of the device is spread along an electrically resistive ribbon that is diffused into the semiconductor material and spirals around the active area.
It is still another object of the present invention to provide a novel structure for an edge passivation region for a semiconductor device in which the electrical potential difference between the active area and the edge region of the device is spread along an electrically resistive ribbon that is deposited on top of the semiconductor material and spirals around the active area.
It is a further object of the present invention to provide a novel structure for an edge passivation region of a semiconductor device in which the current flow between the active area and the edge of the device is at an angle from directly radial.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.
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