The present disclosure relates generally to an apparatus for mitigation of warping of one or more electronic components. More specifically, the embodiments of the disclosure relate to an interface unit with a coefficient of thermal expansion complementary to the electronic component(s).
Decreasing packaged circuit board size, decreasing packaging costs, and increasing component-packaging (i.e. connectors) density are ongoing goals of the computer industry. A problem exists, however, with varying coefficients of thermal expansion (CTE) between connectors and printed circuit boards (PCBs), which effectively creates high stresses on associated solder interfaces. It is understood that during a solder re-flow process, both the PCB and connector are heated. At or near the conclusion of the solder re-flow process, the PCB is subject to cooling, and the solder solidifies.
During the cooling phase of the solder re-flow process, a mismatch between the CTE of the board and connector creates stress(es) in the solder joints, which may cause fracture of the solder connection. Further, the CTE mismatch can cause warpage of either or both the connector and the PCB, which in one embodiment could lead to reliability problems and low manufacturing yields. Additionally, the CTE mismatch may cause warping of the connector that lifts the connector contacts, which may result in missing or insufficient solder connection. Further, if the connector remains warped, a plugging issue may occur since the plug will not seat fully into the connector. Accordingly, the CTE mismatch effects the mechanical and/or electrical properties of the component packaging.
USPTO Backgrounds
USPTO Backgrounds