Memory in a computer system can be used to store information, including, for example, information that represents audio, video and multimedia content. When a transfer of information to or from memory is "asynchronous," delays can occur that interfere with timely completion of the transfer. Consider, for example, FIG. 1, which illustrates a known architecture for coupling an external Input/Output (IO) device 10 to a system 100, such as a computer system. The system 100 includes a processor 110 coupled to a main memory 200 through a memory controller 300. The external IO device 10 communicates with an 10 unit 400, which is also coupled to the main memory 200 through the memory controller 300.
The IO device 10, such as a digital video camera acting as a sending device, may store an indication in the main memory 200, acting as a receiving device, that a "record" mode has been selected. To do so, a single asynchronous message can be sent from the IO device 10 to the system 100 in response to the selection, and the information will then be stored in the main memory 200. Typically, an asynchronous transfer of information to the main memory 200 may be delayed by other, more important, activities without adversely impacting system performance. However, even a minor delay or gap in some types of information streams may noticeably degrade the quality of the information, such as by causing a momentary freeze in a video presentation or by introducing a stuttering effect in an audio transmission.
When a transfer of information is "synchronous," the sending and receiving devices are synchronized, such as by using the same or a synchronized clock signal, and the transfer of information recurs at identical periodic intervals. For example, the IO device 10 might send a synchronous message, indicating the camera's current mode, to the system 100 once every second. However, because the IO device 10 and the system 100, or components within the system 100 such as the main memory 200, may be difficult to synchronize, a synchronous transfer of information is not appropriate in many situations.
When a transfer of information is "isochronous," the sending and receiving devices are only partly synchronized, but the sending device transfers information to the receiving device at regular intervals. Such transfers can be used, for example, when information is to arrive at the receiving device at the same rate it is sent from the sending device, but without precise synchronization of each individual data item. For example, the IO device 10 may send an isochronous stream of video information to the system 100 which ensures that the information flows continuously, and at a steady rate, in close timing with the ability of the system 100 to receive and display the video. While a synchronous transfer of information occurs at the same time with respect to a clock signal, an isochronous transfer of information may require that up to "X" bits of data be transferred every "T" time units, although precisely when the X bits are transferred within the time T can vary. The IEEE 1394 standard (1995), entitled "High Performance Serial Bus" and available from the Institute of Electrical and Electronic Engineers, is an example of an interface that supports the isochronous transfer of information.
In addition to the isochronous transfer of information between the IO device 10 and the system 100, the transfer of information within the system 100 may also be isochronous. U.S. patent application Ser. No. 09/110,344, entitled "Architecture for the Isochronous Transfer of Information Within a Computer System," to John I. Gamey and Brent S. Baxter, filed on Jul. 6, 1998 and assigned to Intel Corporation discloses an architecture that provides for the isochronous transfer of information within the system 100.
Even if the transfer of information within the system 100, such as between the 10 unit 400 and memory controller 300, is isochronous, the information may still not be transferred with the main memory 200 in an isochronous fashion. This is because the transfer of information between the memory controller 300 and the main memory 200 is typically asynchronous in nature. That is, even though information is transferred from the IO device 10 to the memory controller 300 in an isochronous way, the information is treated in an asynchronous way when transferred with the main memory 200. For example, when an "agent," such as the processor 110, accesses the main memory 200, a delay or gap in an isochronous stream being sent from the IO device 10 to the main memory 200 may occur. If so, the benefits of using an isochronous stream of information, such as, for example, making sure that information flows continuously, and at a steady rate, in close timing with the ability of the system 100 to receive and display the image, are reduced or lost altogether.
To solve this problem, a large data buffer, such as a First-In, First-Out (FIFO) data buffer, can be provided to store isochronous information when the main memory 200 cannot be accessed. In this case, information being transferred, for example, between the IO device 10 and the main memory 200 can be stored to, or retrieved from, the buffer when the main memory 200 is not available. This buffering can reduce the delays or gaps in an isochronous stream within the system 100, such as those caused by, for example, traditional cache coherence management or memory arbitration. Such a buffer, however, may increase the cost, lower the performance and/or make the system 100 more difficult to build, validate and test. Moreover, unless these problems are solved, the system may still not deliver information to or from the main memory 200 in a reliable and timely fashion.
USPTO Backgrounds
USPTO Backgrounds