The invention relates to a packaging method, a packaging structure and a package substrate for electronic parts, and particularly to a packaging method, a packaging structure and a package substrate for electronic parts including an LSI and a capacitor connected thereto.
There has hitherto been, as shown in FIG. 18, a package substrate 154, wherein an LSI (Large Scale Integrated circuit) 151 and a capacitor 152 are mounted on both surfaces of a thin film substrate 150, and this thin film substrate 150 is laminated on a parent board (board) 153 (refer to, e.g., Japanese Patent Application Laid-Open Publication No. 2002-314031).
The thin film substrate 150 is used for reducing an inductance between the LSI 151 and the capacitor 152 that are mounted on both sides of the substrate. Note that the thin film substrate generally indicates a substrate of which a thickness is equal to or smaller than 50 μm.
On the occasion of manufacturing this package substrate 154, to begin with, as shown in FIG. 19(a), wiring is formed on the thin film, and metal terminals 155 are formed by a plating process.
Next, as shown in FIG. 19(b), the LSI 151 is bonded by, for instance, a solder 159 to a surface 150a of the thin film substrate 150. Next, an underfill agent 156 fills between the LSI 151 and the thin film substrate 150.
Herein, the underfill agent 156 fills for relieving a stress at a bonding portion between the respective portions. Namely, a coefficient of thermal expansion of the thin film substrate 150 is different from that of the LSI 151, and hence there might be a possibility of causing a crack in the solder if leaving as it is.
Such being the case, the underfill agent 156 fills between the thin film substrate 150 and the LSI 151, and the stress due to the difference between the coefficients of thermal expansions is thereby relieved, thus preventing the occurrence of the crack in the solder.
Next, as shown in FIG. 19(c), the capacitor 152 is mounted on an undersurface 150b of the thin film substrate 150.
On the other hand, as shown in FIG. 20, the parent board 153 is formed with an opening 157 having a predetermined size and with solder balls 158.
Then, as shown in FIG. 18, the thin film substrate 150 mounted with the LSI 151 and the capacitor 152 is laminated on the parent board 153. The thin film substrate 150 is bonded through the solder balls 158 to the parent board 153.
At this time, the capacitor 152 mounted on the thin film substrate 150 is inserted into the opening 157 of the parent board 153.
Thus, with the conventional package substrate 154, the capacitor 152 mounted on the undersurface 150b of the thin film substrate 150 is inserted into the opening 157 of the parent board 153.
This package substrate 154 enables both an enhancement of a packaging density of the electronic parts and down-sizing.
USPTO Backgrounds
USPTO Backgrounds