Field of the Invention
This invention relates generally to semiconductor device pin designation. Specifically, the present invention relates to the ability of the user to programmably designate one or more semiconductor device pins to perform an expanded and flexible set of address functions, as well as other I/O functions.
Description of the Prior Art
The current state of the art describes semiconductor devices such as microprocessors and microcontrollers that have bi-directional I/O ports to a common pin that are capable of performing one function when in the input mode and a second function when in the output mode.
The current state of the art also describes semiconductor devices such as microprocessors and microcontrollers that are capable of using a particular pin as either an address pin or a data pin, depending on state of the device with respect to the memory access cycle. For example, a microprocessor capable of driving a 16 bit wide data bus is likely to have 16 pins that function as data I/O. The microprocessor has an internal capability that allows the same 16 pins to drive an address bus. If additional addressing capability is needed, then additional pins must be dedicated to fulfill this need. Under the prior art, the internal architecture of address pin assignments is defined by the semiconductor manufacturer and cannot be modified by the user.
The prior art, as found in U.S. Pat. No. 5,686,844, "INTEGRATED CIRCUIT PINS CONFIGURABLE AS A CLOCK INPUT PIN AND AS A DIGITAL I/O PIN OR AS A DEVICE RESET PIN AND AS A DIGITAL I/O PIN AND METHOD THEREFOR," describes semiconductor devices with the capability of configuring integrated circuit (IC) pins as clock/reset signals or other digital I/O.
Other schemes have described a multifunctional pin approach for test circuits, which purport to test multiple segments of memory simultaneously. See U.S. Pat. No. 4,495,603, "TEST SYSTEM FOR SEGMENTED MEMORY." However, this prior art describes the introduction of a "logic box" which contains little more than tri-state buffers that generate read and write test clocks for segmented memory devices. Furthermore, there is no suggestion that these test circuits or "logic boxes" are integral to the processing unit and thus are not programmable for customizing the I/O function of the processing unit.
U.S. Pat. No. 5,473,758, "SYSTEM HAVING INPUT OUTPUT PINS SHIFTING BETWEEN PROGRAMMING MODE AND NORMAL MODE TO PROGRAM MEMORY WITHOUT DEDICATING INPUT OUTPUT PINS FOR PROGRAMMING MODE," claims a common set of processing unit I/O pins to function in either a programming mode (e.g. programming non-volatile memory) or a normal mode (e.g. executing program memory).
Thus, a problem is created that manifests itself as either insufficient or excessive addressing capability, depending on the programmer's application. Furthermore, the prior art does not anticipate a flexible addressing capability that may be programmed for the specific application of the semiconductor device.
Therefore, a need existed to provide a semiconductor device where the number of address pins required to meet the design specification may be programmably designated.
USPTO Backgrounds
USPTO Backgrounds