1. Field of the Invention
This invention relates generally to a process for the fabrication of semiconductor devices and, more particularly, to the interconnection of multiple layers of conductive leads, the conductive leads electrically coupling the components of the integrated circuit.
2. Description of the Related Art
In the related art, contacts and vias are fabricated in integrated circuit devices and provide interconnections between various circuit components and the wiring layers, the wiring layers providing the conducting paths between the circuit components. Contacts connect a first wiring layer with the surface of the semiconductor substrate (and to the circuit elements located on the surface of the semiconductor substrate). Vias connect a second wiring layer through a second insulator layer to the first wiring layer. When it is necessary to connect the second wiring layer to the substrate, both a via and a contact are used. A conductive path (contact) is fabricated from the substrate through an insulating layer to the first wiring layer and a second conductive path (via) is fabricated from the first wiring layer through a second insulating layer to a second wiring layer.
Referring to FIG. 1, a typical integrated circuit device with a plurality of wiring layers is shown. A semiconductor substrate 10 includes components (illustrated by component 11) fabricated thereon. Conductive paths (contacts 13) extend through the first insulating layer 12 and are electrically coupled to the first wiring layer 14. A via 16 extends from the first wiring layer through a second insulating level 15 to a second wiring layer 17. The wiring layers are fabricated on the semiconductor substrate, according to the related art, with the following process steps.
Forming a metal inter-level oxide insulating layer PA1 Patterning the contact holes on the insulating layer PA1 Etching the contact holes PA1 Forming the contact hole plug PA1 Depositing a first conductive layer PA1 Patterning the first conductive layer PA1 Etching the first conductive layer to form the first wiring layer PA1 Forming a second metal inter-level oxide insulating layer PA1 Patterning the via holes on the insulating layer PA1 Etching the via holes PA1 Forming the via hole plugs PA1 Depositing the second conductive layer PA1 Patterning the second conductive layer PA1 Etching the second conductive layer to form the second wiring layer
In this device fabrication process, the steps, wherein the contacts and the vias are formed, require careful and time consuming procedures. These procedures increase the cost and time required to fabricate these devices. One of the principal problems in the fabrication has been in the formation of the plugs, i.e., the material introduced into the contact and via holes to provide the conducting path. As the density of components has increased the dimensions of the integrated circuits have been reduced and the difficulties in insuring that a conducting path in the contact and via has been created by the plugging process have increased. In addition, the aspect ratio of the holes, i.e., the ratio of the depth to the width of the hole, has increased which, further increasing the difficulty of filling the holes and forming a acceptable conducting path. Recently, techniques have been developed which provide greater reliability for the fabrication of contacts and vias (cf. U.S. patent application Ser. No. (TI-20162) and assigned to the assignee of the present Patent Application; an article entitled ENHANCED BOTTOM COVERAGE OF SUB-MICRON CONTACT HOLES USING A NOVEL HI-FILL Ti/TiN SPUTTER-PROCESS; and an article entitled A NOVEL HIGH PRESSURE LOW TEMPERATURE ALUMINUM PLUG TECHNOLOGY FOR SUB-0.05 um CONTACT/VIA GEOMETRIES).
A need has therefore been felt for a technique by which the time required for the fabrication of an integrated circuit device having multiple wiring layers is reduced and in which the process for the formation of acceptable conductive paths between the wiring layers is improved.
USPTO Backgrounds
USPTO Backgrounds