Low on-resistance MOS transistors are desirable for their low power loss and ability to conduct high currents. It is well known that a cellular array of vertical double-diffused MOS (VDMOS) transistors can be made to have a very low on-resistance (R.sub.ON) X Area product (.OMEGA. mils.sup.2). This is partly because no top surface area is used to form drain regions, thus allowing a higher density of transistors to be connected in parallel and a source metal layer to substantially cover the top surface of the transistor structure. The large source metal width provides a low metal resistance, while the high density of the transistors connected in parallel provide a very low transistor on-resistance between the source regions and the drain. FIG. 8 illustrates a conventional N-channel VDMOS transistor to be described in detail later.
For integrated circuit (IC) applications, forming N-channel and P-channel VDMOS transistors in the same substrate is impractical. Additionally, it may be desirable to connect the body of a transistor to a separate biasing voltage, which cannot be done with cellular VDMOS transistors. Other limitations also exist with VDMOS transistors when formed in an IC, such as a high drain-to-substrate capacitance and a large overhead associated with bringing the drain up to the top surface of the substrate for interconnecting the VDMOS transistors with other circuitry on the same substrate. A VDMOS transistor when formed as a discrete device may require a large overhead associated with terminating the outer edges, as well as contain a large parasitic JFET and have a high epitaxial drain resistance.
Forming P-channel discrete VDMOS transistors creates additional problems due to the difficulty in fabricating a low resistivity P+ substrate, the need for a thicker P epitaxial layer to allow for P autodoping by the substrate, and the difficulty in controlling the resistivity of the P epitaxial layer.
In situations where the drawbacks of a VDMOS transistor prevent its use, lateral MOS transistors have traditionally been used, although their R.sub.ON X Area product is not as low as that of the VDMOS transistors.
FIG. 1 is a top-down view of a conventional lateral P-channel MOS transistor which serves to illustrate some causes of increased on-resistance. In FIG. 1, an N-type substrate 10 has formed over it a relatively wide polysilicon gate 12 which is insulated from the top surface of substrate 10 by a layer of gate oxide. The gate 12 acts as a mask while doping the area 14 with P-type dopants to form self-aligned source and drain regions 16-19. A layer of oxide (e.g., one micron thick) is deposited over the polysilicon gate 12 (after the polysilicon is oxidized) to insulate gate 12 from a metal layer which is subsequently deposited over the surface of the wafer to contact the source and drain regions 16-19.
The metal layer is selectively etched away to form metal strips overlying the source regions 16 and 18 and the drain regions 17 and 19. The metal strips contact the source and drain regions at spaced contact points 20 along the length of the source and drain regions. The metal strips contacting the source regions 16/18 are connected to a source voltage V.sub.S. Similarly, the metal strips contacting the drain regions 17/19 are connected to a drain voltage V.sub.D. A gate voltage V.sub.G is connected to one or both ends of the polysilicon gate 12.
As seen by the schematic representations of resistance along the metal strips, the voltages along the lengths of the metal strips vary. The metal-to-source or metal-to-drain contacts 20 along the lengths of the source and drain regions force the source and drain regions to have a size larger than the contacts 20. Increasing the spacing of the contacts 20 or reducing the size of the contacts 20, especially along the source regions, adversely affects the transistor gain between the contacts 20 due to the resistance of the source and drain regions. As seen, numerous tradeoffs must be made between on-resistance, transistor gain, and transistor size when using a strip type lateral MOS transistor design.
One conventional method used to decrease the on-resistance of the transistor shown in FIG. 1 is to increase the width of the metal strips and increase the metal-to-source and metal-to-drain contact area; however, this also increases the size of the transistor and thus does little to reduce the R.sub.ON X Area product of the transistor. Forming the metal strips thicker to reduce on-resistance requires complicated dry-etching techniques to etch the metal and, thus, increases the cost of the product.
What is needed is a novel lateral transistor which has very low on-resistance but does not lower on-resistance by sacrificing area, and which could be used in CMOS applications.
USPTO Backgrounds
USPTO Backgrounds