In the field of semiconductor mounting, flip-chip mounting by which IC (integrated circuits) are directly mounted on a printed substrate or a flexible wiring board attracts notice as a new mounting form adaptable to achievement of lower cost and higher precision.
As methods for such flip-chip mounting, known are a method in which solder bumps are provided at terminals of a chip to effect solder bonding and a method in which electrical interconnection is made via a conductive adhesive. These methods have a problem that a stress due to a difference in coefficient of thermal expansion between the chip and the substrate that are to be bonded to each other may be generated to lower connection reliability when products are exposed to environment of various types. Accordingly, a method has come to be commonly studied in which an underfill material of an epoxy resin type is injected into a chip-/substrate gap in order to relax the stress at the bonding interface.
There, however, is another problem that the step of injecting such an underfill makes a process complicate to bring about a disadvantage in view of productivity and cost. To solve such a problem, what recently attracts notice from the viewpoint of process simplicity is flip-chip mounting that makes use of an anisotropic conductive adhesive having both anisotropic conductivity and encapsulation function.
However, where a chip is directly mounted on a substrate via the anisotropic conductive adhesive, the stress due to a difference in coefficient of thermal expansion between the chip and the substrate may be generated in a temperature cycle test. This brings about a problem that the adhesive may cause an increase in connection resistance or separation at adhesive layers when reliability tests such as a thermal shock test, a PCT (pressure cooker test) and a solder bath immersion test are made. Also, where projected electrodes are formed at connecting terminals of a chip, there is a problem that the stress due to a difference in coefficient of thermal expansion between the chip and the substrate may concentrate at the interface between the projected electrodes and the chip in the reliability tests, making the projected electrodes separate from their interface with chip electrodes to cause faulty conduction.
USPTO Backgrounds
USPTO Backgrounds