In the formation of component elements, such as a wiring pattern or an insulating layer, of an electronic device, by using not a vacuum process but a printing process, it is possible not only to achieve an improvement in productivity, but also to reduce costs because the printing process eliminates the need for an expensive film formation device.
Japanese Patent Application Laid Open No. 2014-191169 discloses using flexographic printing or inkjet printing in the formation of a semiconductor layer included in a thin-film transistor array, a protective layer covering the semiconductor layer, and an interlayer dielectric film covering the entire array.
The thin-film transistor array in Japanese Patent Application Laid Open No. 2014-191169 has a configuration in which a pixel electrode is formed on the interlayer dielectric film. A via hole is formed in the interlayer dielectric film for electrical continuity between the pixel electrode and a drain electrode.
Since low-viscosity ink is used in flexographic printing or inkjet printing, the ink flows noticeably. This makes it necessary to exercise care not to allow the ink to spread out of a desired printing pattern due to the flow of the ink.
In accordance with Japanese Patent Application Laid Open No. 2014-191169, the drain electrode that is made to be electrically continuous with the pixel electrode located on an upper layer of the interlayer dielectric film by the via hole of the interlayer dielectric film is a solid electrode (in other words, a plane electrode) forming the entire bottom face of the via hole. Therefore, even when the insulating ink forming the interlayer dielectric film spreads over the drain electrode located on the bottom face of the via hole, poor conduction is less likely to occur.
However, if a conductor for electrical connection which is exposed at the bottom face of the via hole is, for example, linear wiring extending from the outer edge of the via hole, the insulating ink may move on a wiring line and cover the wiring line. As a result, there is a high possibility of the occurrence of poor conduction.
USPTO Backgrounds
USPTO Backgrounds