A known DC-DC converter comprises a switching element which is turned on and off to intermittently convert DC voltage from a DC power source into an electric power of high frequency, and a transformer for converting the electric power into a stabilized DC power then supplied to an electric load through a rectifying smoother. For example, a prior art DC-DC converter shown in FIG. 1 comprises a primary winding 2a of a transformer 2 and an N-channel MOS-FET 3 as a switching element connected in series to a DC power source 1; secondary and auxiliary windings 2b and 2c of transformer 2 electro-magnetically coupled to primary winding 2a and each other; a main rectifying smoother 14 which has a main rectifying diode 29 and main smoothing capacitor 30 connected to secondary winding 2b; an output voltage detector 5 for detecting DC output voltage VO1 from main rectifying smoother 14 to produce a detection signal; a current detector or detecting resistor 28 for detecting winding current ID through MOS-FET 3 as a detection voltage VR1 of the level corresponding to the amount of winding current ID; and a control circuit 6 for producing drive signals VG to turn MOS-FET 3 on and off in response to detection voltage VR1 from current detector 28 and detection signal from output voltage detector 5 through a photo-coupler 34.
Secondary and auxiliary windings 2b and 2c are electro-magnetically coupled to primary winding 2a in the adverse polarity to each other. Output voltage detector 5 picks out output voltage VO1 to produce an error voltage between output voltage VO1 and a given reference voltage, and the error voltage induces electric current flowing through a light emitting diode 34a to turn it on. By way of example, output voltage detector 5 shown in FIG. 1 comprises a detective series circuit connected between both end terminals of main smoothing capacitor 30, and detective series circuit comprises resistors 33 and 35, an NPN transistor 36 for voltage detection, a Zener diode 37 and light emitting diode 34a of photo-coupler 34 connected in parallel to resistor 33. Also, connected to both terminals of main smoothing capacitor 30 are dividing resistors 38 and 39 whose junction is connected to a base terminal of transistor 36. When DC output voltage VO1 between DC output terminals exceeds a voltage set by breakdown voltage of Zener diode 37 and resistors 38 and 39, an electric current flows through light emitting diode 34a, transistor 36 and Zener diode 37 to irradiate light from light emitting diode 34a. Thus, Zener diode 37 and resistors 38 and 39 provide an output reference voltage.
In the DC-DC converter shown in FIG. 1, when MOS-FET 3 is turned on and off, secondary winding 2b of transformer 2 produces DC output voltage VO1 to an electric load 4 through main rectifying smoother 14, and at the same time, auxiliary winding 2c of transformer 2 generates DC drive voltage VO2 which is applied to control circuit 6 through auxiliary rectifying smoother 20. Upon start-up of the converter, an initial current flows from DC power source 1 through a trigger resistor 40 and an auxiliary capacitor 32 to electrically charge auxiliary capacitor 32. When charged voltage in auxiliary capacitor 32 reaches a serviceable level, control circuit 6 starts driving, and once activated, thereafter, it is driven by DC drive voltage VO2 generated from auxiliary rectifying smoother 20. Control circuit 6 comprises an oscillator 10 for generating pulse signals VOSC of constant frequency; a drive signal generator 11 for producing on-off signals to a control or gate terminal of MOS-FET 3 synchronously with pulse signals VOSC from oscillator 10; and an intermittent controller 12 for producing control signals VC1 to drive signal generator 11 in response to the level of detection signal from output voltage detector 5 to switch MOS-FET 3 to the intermittent operation during the light load period.
Drive signal generator 11 comprises an AND gate 22 as a gate circuit for producing drive signals VG to gate terminal of MOS-FET 3; an RS flip flop (RSF/F) 21 set when pulse signal VOSC from oscillator 10 is supplied to a set terminal S of RSF/F 21 to forward an output signal VQ from the output terminal Q to an input terminal of AND gate 22; a normal power supply 25 for producing a basic reference voltage VES1; and a first comparator 23 as a first comparing circuit for comparing detection voltage VR1 from current detecting resistor 28 at the non-inverted input terminal+with comparative voltage VFB appearing at the inverted input terminal−and on a junction between a relative resistor 26 and phototransistor 34b of photo-coupler 34. First comparator 23 produces a reset signal to a reset terminal R of RSF/F 21 which is then reset.
Intermittent controller 12 comprises a power supply 27 for producing a reference voltage VES2/VES3, and a second comparator 24 as a second comparing circuit for comparing comparative voltage VFB at the non-inverted input terminal+with reference voltage VES2/VES3 from second power supply 27 at the inverted input terminal−. In this case, comparative voltage VFB becomes lower with the increase in DC output voltage VO1, and current detecting resistor 28 picks up detection voltage VR1 of the level corresponding to the amount ID of winding current flowing through MOS-FET 3. When comparative voltage VFB is lower than detection voltage VR1, first comparator 23 produces the control signal to stop drive signal VG from AND gate 22 and determine the on period of MOS-FET 3. When comparative voltage VFB is lower than reference voltage VES2/VES3, second comparator 24 produces control signal VC1 to AND gate 22 to make AND gate 22 inhibit to produce drive signal VG to thereby provide an off or inoperative period for temporarily stopping switching operation of MOS-FET 3 so that MOS-FET 3 is shifted from the ordinary operation to the intermittent operation.
FIGS. 2, 3 and 4 indicate voltage waveforms at selected locations of DC-DC converter in FIG. 1 wherein (A), (B), (C), (D), (E) and (F) respectively denote a voltage VDS between drain and source terminals of MOS-FET 3, voltage VOSC of pulse signal of constant frequency developed from oscillator 10, output voltage VQ at output terminal Q of RSF/F 21, voltage VG of drive signal output from AND gate 22, comparative voltage VFB and detection voltage VR1 from current detecting resistor 28, and voltage VCC of drive power supplied to control circuit 6. Also, FIGS. 2, 3 and 4 represent the waveforms respectively of during the non-light load period, of immediately before MOS-FET 3 comes to the intermittent operation, and of under the intermittent operation of MOS-FET 3 during the light load period. In the waveform (E), dotted lines indicate levels of reference voltages VES2 and VES3.
In operation of DC-DC converter shown in FIG. 1, a switch not shown is turned on to supply electric power to the converter, thereby DC voltage E of DC power source 1 generates an initial current through trigger resistor 40 to auxiliary smoothing capacitor 32 of auxiliary rectifying smoother 20 to electrically charge auxiliary smoothing capacitor 32. When charged voltage VOO2 in auxiliary smoothing capacitor 32 reaches a serviceable level of control circuit 6, drive voltage VCC is applied to oscillator 10, drive signal generator 11 and intermittent controller 12 to cause control circuit 6 to start driving. Accordingly, oscillator 10 produces an output signal or pulse signal VOSC of high voltage level and constant frequency to set input terminal of RSF/F 21 to set RSF/F 21 which therefore produces the output of high voltage level at output terminal Q to AND gate 22. At the moment, as detection voltage VR1 on current detecting resistor 28 is lower than comparative voltage VFB, first comparator 23 produces the output of low voltage level to reset terminal R of RSF/F 21 not to reset RSF/F 21. On the other hand, as comparative voltage VFB is higher than reference voltage VES2/VES3, second comparator 24 produces output VC1 of high voltage level to AND gate 22 which then forwards drive signal VG of high voltage level to gate terminal of MOS-FET 3 to turn it on.
When MOS-FET 3 is turned on, winding current ID flows from DC power source 1 through primary winding 2a of transformer 2, MOS-FET 3 and current detecting resistor 28 which constitute a primary closed circuit to accumulate electromagnetic energy in transformer 2, and current detecting resistor 28 converts winding current ID into detection voltage VR1 of the level corresponding to the amount of winding current ID. As shown in FIG. 2(E), when detection voltage VR1 reaches the level of comparative voltage VFB, first comparator 23 produces the output of high voltage level to reset terminal of RSF/F 21 which therefore is reset. As a result, RSF/F 21 produces the output of low voltage level at the output terminal Q to change drive signal VG to low voltage level to turn MOS-FET 3 off. After the turning-off of MOS-FET 3, electric current flows from secondary winding 2b of transformer 2 through main rectifying diode 29 and main smoothing capacitor 30 of main rectifying smoother 14 to supply DC output current to load 4 under DC output voltage VO1, releasing electromagnetic energy from transformer 2. Simultaneously, drive current flows from auxiliary winding 2c of transformer 2 through auxiliary rectifying diode 31 and auxiliary smoothing capacitor 32 of auxiliary rectifying smoother 20 to control circuit 11 under DC drive voltage VO2, also discharging electromagnetic energy from transformer 2. Output voltage detector 5 compares DC output voltage VO1 with output reference voltage set by Zener diode 37 and resistors 38 and 39 to produce an error or differential signal between DC output voltage VO1 and output reference voltage so that differential signal causes electric current to flow through light emitting diode 34a of photo-coupler 34. Light output from light emitting diode 34a is received in primary side by photo-transistor 34b which allows electric current of the amount corresponding to the level of DC output voltage VO1 to pass through photo-transistor 34b and thereby induce comparative voltage VFB at a junction of relative resistor 26 and photo-transistor 34b. 
Under the non-light condition including the heavy and ordinary conditions of load, DC output voltage VO1 becomes lower and less amount of electric current flows through photo-transistor 34b to cause the level of comparative voltage VFB to rise. Accordingly, first comparator 23 does not provide the output of high voltage level to reset terminal R of RSF/F 21 to reset RSF/F 21 until detection voltage VR1 reaches the level of comparative voltage VFB. However, when winding current ID increases so that detection voltage VR1 becomes higher than comparative voltage VFB, first comparator 23 produces the output of high voltage level to reset terminal R of RSF/F 21 which therefore is reset. When load 4 is in the light condition, DC output voltage VO1 rises to increase electric current flowing through photo-transistor 34b and lower the level of comparative voltage VFB. Accordingly, at an early stage after MOS-FET 3 is turned on, detection voltage VR1 becomes higher than comparative voltage VFB so that first comparator 23 produces the output of high voltage level to reset terminal of RSF/F 21 which therefore is reset. Reset RSF/F 21 produces at the output terminal Q signal VQ of low voltage level to switch drive signal VG from AND gate 22 to low voltage level and thereby control or reduce time-width or span of drive signal VG to gate terminal of MOS-FET 3. In this way, the on-period of MOS-FET 3 to reduce winding current ID through primary closed circuit of transformer 2 to control and stabilize DC output voltage VO1 to load 4 to a substantially constant level.
When load 4 becomes still lighter to a ultra-light condition including an unloading, DC output voltage VO1 rises and adversely comparative voltage VFB drops below reference voltage VES2. At this time, second comparator 24 produces control signal VC1 of low voltage level to prevent AND gate 22 from generating drive signal VG. At the same time, control signal VC1 of low voltage level shifts reference voltage from first VES2 to second VES3 higher than VES2. As MOS-FET 3 has already stopped the on-off operation, the output voltage VO1 gradually decreases, and as a result, comparative voltage VFB gradually increases. When comparative voltage VFB soon exceeds second reference voltage VES3, second comparator 24 produces control signal VC1 of high voltage level so that AND gate 22 issues drive signal VG to gate terminal of MOS-FET 3. Concurrently, control signal VC1 of high voltage level shifts reference voltage from VES3 to VES2 lower than VES3 to make MOS-FET 3 resume the switching operation to raise DC output voltage VO1. As above-mentioned, intermittent controller 12 can switch MOS-FET 3 to the intermittent operation which provides an abeyance period for ceasing switching operation of MOS-FET 3 during the light load period including unloading as shown in FIG. 4.
For example, as shown in FIG. 5, intermittent controller 12 comprises a first series circuit of a resistor 41 and a normal power supply 27 connected between inverted input terminal of second comparator 24 and ground, and a second series circuit of a resistor 42 and an intermittent NPN transistor 43 connected in parallel to first series circuit. A base terminal of intermittent NPN transistor 43 is connected to output terminal of second comparator 24 through a resistor 44. When load 4 moves from the non-light condition to the light condition, intermittent transistor 43 is in the on or conductive condition because base terminal of intermittent transistor 43 receives control signal VC1 of high voltage level from second comparator 24, and therefore, inverted input terminal−of second comparator 24 receives first reference voltage VES2 split by dividing resistors 41 and 42 from reference voltage VES. Second comparator 24 compares comparative voltage VFB with first split reference voltage VES2 to produce control signal VC1 of low voltage level to AND gate 22 to shift MOS-FET 3 to the intermittent operation because comparative voltage VFB is lower than first split reference voltage VES2.
When MOS-FET 3 is shifted to the intermittent operation, output voltage VO1 immediately drops so that output voltage detector 5 detects detection signal of lowered level to raise comparative voltage VFB. Accordingly, again second comparator 24 produces control signal VC1 of high voltage level to turn MOS-FET 3 on, and no further intermittent operation is maintained. However, intermittent controller 12 shown in FIG. 5 changes reference voltage from first low VES2 to second high VES3 when second comparator 24 produces control signal VC1 of low voltage level to turn intermittent transistor 43 off so that inverted input terminal—of second comparator 24 receives second high VES3 to thereby maintain comparative voltage VFB lower than high VES3. Consequently, second comparator 24 continues to produce control signal VC1 of low voltage level to AND gate 22 to retain MOS-FET 3 in the intermittent operation. Specifically, while comparative voltage VFB rises immediately after MOS-FET 3 is shifted to the intermittent operation, second comparator 24 switches reference voltage from first low VES2 to second high VES3 during the light load period to extend the term of rising comparative voltage VFB lower than high VES3. In this way, second comparator 24 has the hysteretic characteristics by two different values VES2 and VES3 for reference voltage to extend the abeyance period of the intermittent operation, thereby resulting in reduction in switching loss of MOS-FET 3 during the light load period.
DC-DC converter shown in FIG. 1, however, has a drawback of low efficiency in power conversion during the light load period because oscillator 10 continues to produce pulse signals VOSC during the intermittent operation of MOS-FET 3 as undesirably the converter represents power consumption of very unchanged level between the light and non-light load periods. In other words, during the intermittent operation of MOS-FET 3, oscillator 10 spends major amount of electric power supplied to control circuit 6, but, other circuits in control circuit 6 than oscillator 10 are kept in a pause for using almost no power. Japanese Patent Disclosure No. 4-42771 discloses a high efficiency DC-DC converter for ceasing power supply to a control circuit in response to output from an output voltage detector during the light load period to convert a switching element to the intermittent operation by control circuit. In this converter, cease of power supply to control circuit can reduce power consumption by oscillator in control circuit.
However, the DC-DC converter shown in the foregoing reference interrupts whole drive power to control circuit, and therefore, suspends power supply to power supplies for producing reference voltages, comparators, amplifiers or the like other than oscillator each time switching element comes to the intermittent operation. Also, as it takes a necessary time until reference voltages inside of control circuit reach a steady level from no-power supplied condition, similarly to upon power-on, large output ripples may appear in DC output due to the delayed response when switching element is converted from the intermittent operation to the ordinary operation so that output ripples may disadvantageously cause malfunction in devices connected to the switching power source. To suppress output ripples, rectifying smoother needs a capacitor of large capacitance, or electric current to load has to be reduced to a small amount, however, these measures may unfavorably increase costs in manufacture due to employment of large capacitance capacitor, expanded size of the converter and shortage of supplied power by reduction in electric current to load.
Accordingly, an object of the present invention is to provide a DC-DC converter capable of reducing power consumption in an oscillator by effectively ceasing oscillation of the oscillator when a switching element is converted to an intermittent operation during the light load period.
USPTO Backgrounds
USPTO Backgrounds