1. Field of the Invention
The present invention relates to an image processing apparatus and an image forming apparatus. Particularly the present invention relates to the image processing apparatus or the image forming apparatus in which the image processing section is connected with generic bus.
2. Description of Related Art
In the image processing apparatus and the image forming apparatus, various interface controls and relatively high-speed data transmission have been attained by proving high-speed local bus for a CPU and separately proving generic bus such as PCI bus.
FIG. 17 illustrates a block diagram to show a configuration of a conventional image forming apparatus. In FIG. 17 connected with local bus 100A, which is an external bus of the CPU 101, are a CPU 101 as a controller, a ROM 102 for memorizing various setting data as a memory, a RAM 103 for memorizing image data as a memory (an image memory) in which data can be rewritten and an interface section 105 including a UART for communicating with the outside of the image forming apparatus and an I/F section 105 such as LAN interface.
A USB I/F section 111, an IDE I/F section 112 and the UART 113 are connected with PCI bus #0 (it will be called PCI bus 100B hereinafter) as generic bus or expansion bus, which is different from the local bus 100A described above. The PCI bus 100B is connected with the local bus 100A through a PCI bridge #0 (it will be called PCI bridge 107 hereinafter).
An Image processing section 120 for executing image processing to image data is connected with PCI bus #1 (it will be called PCI bus 100C) as generic bus or expansion bus, which is different from the local bus 100A. The PCI bus 100C is connected with the local bus 100A described above through a PCI bridge #1 (it will be called PCI bridge 108). A printer engine 140 for forming an image on a recording paper is connected with the image processing section 120.
In the image processing apparatus and the image forming apparatus, the CPU and the image memory are connected with local bus which is substantially the same as the external bus of a CPU. Meanwhile, the image processing section and other devices are connected with generic bus. In many case, the local bus and the generic bus are connected each other through a bridge.
In recent years, in order to improve printing performances and to change a printing method in the image forming apparatus, a part of image processing is executed by a hardware-based image processing section. At presert, it is thought that to improve the image processing performance is necessary. However, the data transmission bandwidth of the generic bus with which the image processing section of the image forming apparatus is connected is a bottleneck for high-speed data transmission.
In order to resolve the problems, it is feasible to design a North-chip having dedicated high-speed bus and to develop a high-speed hardware connecting with an image processing hardware, or to develop a controller in which a North-chip having the latest and high-speed generic bus is used.
Since the many hours and the large man-hour to develop the hardware having a high-speed dedicated bus are needed, it is not suitable for the products requiring short-developing terms. The cost of the North-chip having high-speed generic bus therein is higher comparing with that of a North-chip having the most widely spread generic bus. Since the adoption of the North-chip having the latest high-speed generic bus is difficult for a printer in the lowest priced segment due to the cost restriction, and the printing speed of the printer is low, the high-speed bus is not necessary. Consequently, when developing the image processing hardware having a high-speed generic bus, it is necessary to separately develop a different image processing hardware for the printer in the lowest priced segment.
In the technologies associated with the image forming apparatus disclosed in FIG. 1 and in the first page of Japanese Patent Application Open to Public Inspection No. H9-251439, adopted is a method for improving the efficiency by way of transmitting the same data at a time through a multicast circuit to a plurality of targets connected with the same PCI bus. In this case, there is a problem that the limitation of data transmission is limited by the limitation of the data transmission speed of PCI bus. Further, only the same data can be sent to two targets. Accordingly, when conducting image processing in the image processing section connected with the PCI bus, the bandwidth of the PCI bus becomes a bottleneck and it is not feasible to resolve the problems, which become obstacles of high-speed data transmission.
In the technologies disclosed in FIG. 1 and page 1 of Japanese Patent Application Open to Public Inspection No. 2002-264400, scanned image data is memorized in the memory through PCI bus and the memorized image data is also outputted through the PCI bus. In this case, a controller efficiently controls the PCI bus by providing a buffer in front of the PCI bus for the scanned image data and memorized image data for printing to decrease the occupancy time of the PCI bus. This is an invention for efficiently controlling one PCI bus. Accordingly, it is impossible to resolve the problem that when conducting the image processing in the image processing section connected with PCI bus, the data transmission bandwidth of PCI bus becomes a bottleneck and the obstacle for high-speed data transmission.
The image data flow and the cause of the obstacle to high-speed data transmission, resulted from the bottleneck of PCI bus bandwidth will be describe below in detail by referring to flowcharts shown in FIG. 18 and FIG. 19 onward, which are detailed drawing of the block diagram shown in FIG. 17.
The CPU 101 works as an interpreter and generates image data having expanded bitmap format when the CPU 101 receives the image data of various formats from an outside apparatus (not shown). Here, the CPU 101 generates the bitmap image data per a band, which is one of the plural bands into which one page image data are divided, in order to swiftly execute image processing in each section.
Firstly, the. CPU 101 determines whether a space area of an expanded band area in the RAM 103 for storing bitmap image data is available (Step S1 in FIG. 19). If there is the space area for storing bitmap image data (Step S1: YES in FIG. 19), the CPU 101 allows the RAM 103 to store the bitmap image data per a band (Step S2 in FIG. 19, (a) in FIG. 18).
Here, the CPU 101 checks the operation state of an image processing section 120 (Step S3 in FIG. 19). The image processing section 120 comprises an image transform processing A for generating processed image data having a compressed bitmap format by compressing image data having an expanded bitmap format and an image transformation processing B for generating output image data from the processed image data.
When the image processing section 120 stays in a state that the image transformation processing A has completed (under the condition that image transformation processing has completed)(Step S3: YES in FIG. 19), the CPU 101 requests the image forming section 120 to start image transform processing A (Step S4 in FIG. 19).
Here, the image processing section 120 shifts to an image transform processing execution state (Step S11 in FIG. 20). Then the image processing section 120 reads out the band bitmap image data from the RAM 103 (S12 in FIG. 20). Namely, bitmap image data per a band are transferred in a DMA mode from the RAM 103 to the image processing section 120 through the Local bus 100A, the PCI bridge 108 and the PCI bus 100C ((b) in FIG. 18).
Then, the image processing section 120 executes image processing (Step S13 in FIG. 20) and compression processing (S14 in FIG. 20) to the bitmap image data per a band, and generates the compressed bitmap image data as processed image data.
Here, the image processing section 120 stores the compressed bitmap image data generated from the bitmap image data per a band into the compressed bitmap image data area of the RAM 103 (Step S15 in FIG. 20). Namely, the compressed bitmap image data per a band is transmitted in a DMA mode from the image processing section 120 to the RAM 103 through the PCI bus 100C, the PCI bridge 108 and the local bus 100A ((C) in FIG. 18.). Then, the state of the image processing section 120 shifts to an image transform processing finished state (Step S16 in FIG. 20).
The CPU 101 deletes the bitmap image data per a band stored in the RAM 103 after DMA transmission (Step 12 in FIG. 20) has completed. Or the CPU 101 deletes the bitmap image data per a band, which have been transmitted by a move operation, not a copy opertion of the image data when the image processing section 120 reads the image data.
Further, the CPU 101 generates expanded bitmap image data of a plurality of bands corresponding to one page image data. The CPU 101 determines that whether the CPU has completed the generation of bitmap image data of all the bands in the one page (Step S5 in FIG. 19).
If the CPU 101 has not completed the generation of bitmap image data of all bands in one page (Step S5: NO in FIG. 19), the CPU 101 further determines whether the space area for storing the bitmap image data in the expanded band area (Step S1 in FIG. 19) in the RAM 103. If the space area is available (Step S1: YES in FIG. 19), the CPU 101 stores the bitmap image data of a next band unit into the RAM 103 (Step S2 in FIG. 19 and (a) in FIG. 18).
Then, the CPU 101 repeats the determination of operation status of the image processing section 120 (Step S3 in FIG. 19), the request of image transform processing to the image processing section 120 (Step S4 in FIG. 19) and image transformation processing in the image processing section 120 (Steps S11-S16 in FIG. 20). Those operations will be executed over the bitmap image data of the all bands in a page per a band.
When the CPU 101 has completed the image transform processing per a band of all band bitmap image data in one page (Step S5: YES and Step S6: YES in FIG. 19), the CPU 101 requests the image processing section 120 to start an image output processing 1 to (Step S7 in FIG. 19). Here, the image processing section 120 has a function to transmit the compressed bitmap image data from the RAM 103 to a printer engine 140 other than the image transform processing (generation of compressed image data) described above.
Here, the CPU 101 checks the operation status of the image processing section 120 (Step S21 in FIG. 21). If the image processing section 120 has not completed the image output processing, the CPU 101 stands by and waits for the start of image output processing (Step 21: NO in FIG. 21). If the image processing section 120 has completed the image output processing (Step 21: YES in FIG. 21), the CPU 101 issues a request for starting image output processing B to the image processing section 120 (Step S22 in FIG. 21). The CPU 101 comes back to Step 1 to check the operation status of the image processing section 120 when there is a request of an image output processing (Step 23: YES in FIG. 21), otherwise (Step 23: No in FIG. 21), completes the image output processing 1.
Here, the image processing section 120 shifts to an image output processing execution state (Step S31 in FIG. 22). And the image processing section 120 reads out the compressed bitmap image data from the RAM 103 (Step S32 in FIG. 22).
And the image processing section 120 transmits the compressed bitmap image data to the printer engine 140 from a video port a page by a page and a color by a color corresponding to image formation of the printer engine 140 (Step 33 in FIG. 22). When completing the transmission of one page compressed image data, the image processing section 120 shifts to the image output completing state (Step S34 in FIG. 22) The CPU 101 determines whether there are next image data when completing the image formation of all the one page image data (Step S8 in FIG. 19). Here, if there are next data (Step S8: YES in FIG. 19), then the CPU 101 repeats the steps from step 1 in FIG. 19. And if there are no image data (Step S8: No in FIG. 19), the CPU 101 finishes the processing and comes to a completion state.
When executing an image formation of a plurality of pages of images in the configurations and operations described above, the image processing section 120 generates compressed bitmap image data while the printer engine 140 is executing image formation.
Namely, data transmission of three systems, such as reading out bitmap image data from the RAM 103 ((b) in FIG. 18), writing compressed bitmap image data onto RAM 103 ((c) in FIG. 18) and reading out the compressed bitmap image data from RAM 103 ((e) in FIG. 18) through the PCI bridge 108 and the PCI bus 100C are executed at substantially the same time.
The applicants of the present application have revealed through their study that by this reason the data transmission speed (bandwidths) of the PCI bridge 108 and the PCI bus 100C become an obstacle for high-speed data transmission.
The applicants also have revealed that the productivity of image formation (the number of output sheet of image formation per a unit time) is limited by the data transmission speed (bandwidth) of the PCI bridge 108 and the PCI bus 100C.
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