1. Technical Field
This disclosure relate s to semiconductor devices and more particularly, to an apparatus and method for forming deep trench isolation layers for semiconductor memories.
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells. These memory cells include storage nodes. Generally these storage nodes are formed with in deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charge to be stored in the storage node or retrieves charge from the storage depending on whether the desired action is a read or write function. It is often necessary to ensure that the storage node is sufficiently electrically isolated from a gate conductor.
One way to ensure sufficient electrical isolation of the storage node is to provide a top trench oxide layer over the storage node. The storage nodes typically include polysilicon material that partially fills the deep trench. During fabrication the polysilicon leaves a recess remaining at the top of the trench. An oxide (silicon dioxide) is deposited over the surface of the semiconductor device. During the oxide deposition, oxide is formed over the polysilicon in the trench. Other portions of the deposited oxide are removed by planarizing the surface of the semiconductor device and by recessing the oxide to leave a 30-50 nm oxide layer at the bottom of the recess. This oxide layer is referred to as a trench top oxide or isolation.
The oxide recessing is difficult to control. This difficulty introduces a lot of variability in the remaining oxide layer thickness. The trench top oxide thickness is an important parameter and must be maintained in order for the semiconductor memory to work properly. As described above, the trench top oxide electrically isolates the storage node from the gate conductor of the semiconductor device.
Therefore, a need exists for a trench top dielectric having a controlled thickness. A further need exists for a method of providing the trench top isolation for transistors formed on top of deep trenches.
USPTO Backgrounds
USPTO Backgrounds