1. Field of the Invention
The present invention relates to a delay circuit, and more specifically to a delay circuit which is suitable for implementation in a MOS (metal oxide semiconductor) integrated circuit.
2. Description of Related Art
In the prior art, one typical delay circuit implemented in a MOS integrated circuit is composed of a first CMOS (complementary MOS) inverter having an input connected to an input terminal, a second CMOS inverter having an output connected to an output terminal and an integration circuit formed of a resistor and a capacitor and connected between an output of the first CMOS inverter and an input of the second CMOS inverter. In this delay circuit, a delay time is determined by a resistance and a capacitance of the integration circuit and a logical threshold of the second CMOS inverter. The logical threshold of the second CMOS inverter is greatly dependent upon a transconductance g.sub.m and a threshold V.sub.T of each of a P-channel transistor and an N-channel transistor which form the second CMOS inverter. However, the transconductance g.sub.m and the threshold V.sub.T cannot be precisely controlled in an integrated circuit manufacturing process. Therefore, it has been difficult to obtain a desired delay time in the conventional MOS delay circuit. In other words, the delay time will vary dependently upon variation of characteristics of MOS transistors.
USPTO Backgrounds
USPTO Backgrounds