In the world of computers and processors there is an unrelenting drive for additional computing power and faster calculation times. In this context, then, systems in which several processors can be combined to work in parallel with one another are necessary.
Imaging systems which obtain visual images and perform various manipulations with respect to the data and then control the display of the imaged and stored data inherently require large amounts of computations and memory. Such imaging systems are prime candidates for multi-processing where different processors perform different tasks concurrently in parallel. These processors can be working together in the single instruction, multiple data mode (SIMD) where all of the processors are operating from the same instruction stream but obtaining data from various sources or the processors can be working together in the multiple instruction, multiple data mode (MIMD) where each processor is working from a different set of instructions and working on data from different sources. For different operations, different configurations are necessary.
In a multi-processor system each processor can have several buses or ports for the communication of data. Thus, assuming two buses for data and one bus for instructions, and assuming only four processors in the system, a minimum of twelve buses must be switched. When it is realized that additional buses may be required for master processors and control processors to handle simultaneous data input/output on a particular memory module and processing via a particular processor on other memory modules, the problem is compounded. In some situations it may be desirable to isolate certain memories for access only by a particular processor, such as a master processor.
Making the problem even more severe is the fact that in a multi-processing system the true power comes from the ability of any processor to communicate with any memory at any time combined with the ability of the processors to communicate with each other, all occurring simultaneously.
There is thus a need in the art for a system which handles multi-processors having multi-memories such that the address space from all of the memories is available to one or more processors concurrently even when the processors are handling different instruction streams.
One method of solving the huge interconnection problem in complex systems such as the image processing system shown in one embodiment of the invention is to construct the entire processor as a single device. Conceptually this might appear easy to achieve, but in reality the problems are complicated.
First of all, an architecture must be created which allows for the efficient movement of information, while at the same time consuming a minmum amount of precious silicon chip space in order to achieve a high performance to cost ratio. The architecture must allow a very high degree of flexibility, since once fabricated, it cannot easily be modified for different applications. Also, since the processing capability of the system will be high, there is a need for high bandwidth of each data input/output signal which moves information on and off the chip. This is so since the physical number of leads which can attach to any one chip is limited.
It is also desirable to design an entire parallel processor system, such as an image processor, on a single silicon chip while maintaining the system flexible enough to satisfy wide ranging and constantly changing operational criteria.
It is further desirable to construct such a single chip parallel processor system where the processor memory interface is easily adaptable to operation in various modes, such as SIMD and MIMD, as well as adaptable to efficient on-off chip data communications.
USPTO Backgrounds
USPTO Backgrounds