The field of the invention is SOI (Silicon On Insulator) CMOS circuits employing wafers formed using any one of possible methods, such as SIMOX, bond and etchback, SMARTCUT, etc.
In the field of SIMOX SOI wafer manufacture, it is known that the implantation process to produce industry standard wafers having an insulating layer about 0.4 xcexcm thick is time consuming and causes defects in the silicon device layer. The art has experimented with reducing both the magnitude of the oxygen implant dose and the thickness of the implanted layer.
A significant drawback of the use of a lower thickness buried oxide (BOX) is that the capacitance from the sources and drains of the transistors to the substrate below the BOX increases as the thickness is reduced. That capacitance increase is reflected in a reduction of circuit performance. The same capacitance increase will also apply to other components such as diodes, resistors, and inductors.
U.S. Pat. No. 5,994,759 teaches the formation of a doped layer under the BOX, creating an n-type layer in a p-type substrate, and then biasing this layer to form a thick depleted layer. In that approach, however, the n-type layer creates a ground plane underneath the BOX. The capacitance from the sources and drains and other circuit elements to the ground plane will be the same as, or greater than the capacitance to the original substrate.
The art has sought a thinner BOX layer having the capacitance of the thicker BOX without success.
The invention relates to a method of decreasing capacitance between circuit elements in SOI CMOS circuits and the p-doped substrate below the buried oxide (BOX) layer by implanting a lightly doped electrically unbiased area of n-type dopant at the bottom of the BOX, preferably thereby forming a fully-depleted region.
USPTO Backgrounds
USPTO Backgrounds