1. Field of the Invention
The present invention generally relates to the field of inspection and analysis of specimens and, more particularly, to defect inspection and analysis of semiconductor integrated circuits.
2. Description of the Prior Art
In the semiconductor integrated circuit (IC) industry, there is a continuing demand for higher circuit packing densities. This demand of increased packing densities has led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Manufacturing IC's at such minute dimensions adds more complexity to circuits and the demand for improved methods to inspect integrated circuits in various stages of their manufacture is ever present.
Although inspection of such products at various stages of manufacture is very important and can significantly improve production yield and product reliability, the increased complexity of IC's increases the cost of such inspections, both in terms of expense and time. However, if a defect can be detected early in production, the cause of the defect can be determined and corrected before a significant number of defective IC's are manufactured.
In order to overcome the problems posed by defective IC's, IC manufacturers sometimes fabricate semiconductor defect test structures. Such defect test structures are dedicated to defect analysis. The defect test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained. Such defect test structures are often constructed on the same semiconductor substrate as the IC products.
One example of a defect test structure is found in the Copper CMP Test Mask Set designed at MIT. This test mask set is designed to quantify the dependence of the resulting copper line profile on parameters such as line pitch, line width and line aspect ratio. However, the MIT mask set is designed to be probed using conventional electrical testing in which current is passed through the device by contacting predefined pad of large area (approximately 100×100 μm2) with electrical probes, not by electron beam. As is well known in the art, defect detecting systems frequently utilize charged particle beams. In such systems, a charged particle beam, such as an electron beam, is irradiated on defect test structures. The interaction of the electron beam with features in the circuitry generates a number of signals in varying intensities, such as secondary electrons, back-scattered electrons, x-rays, etc. Typically, electron beam methods employ secondary electron signals for the well known “voltage contrast” technique for circuit defect detection.
The voltage contrast technique operates on the basis that potential differences in the various locations of a test structure under examination cause differences in secondary electron emission intensities. Thus, the potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates only at the path swept by the scanning electron beam. A defective portion can be identified from the potential state of the portion under inspection. In one form of inspection, the mismatched portion between the defective voltage contrast image and the defect free one reveals the defect location.
Thus, in such systems, the voltage contrast is simultaneously monitored for both defective and defect free circuits for each circuit manufactured. However, considering the density of IC's currently produced, the time necessary to scan voltage contrast data to perform comparisons is significant. The inspection and analysis of such circuits may take several days. Accordingly, more efficient voltage contrast inspection systems are desirable.
USPTO Backgrounds
USPTO Backgrounds