(1) Field of the invention
The present invention relates to a process for formation of thin film transistor liquid crystal display. Particularly, the present invention relates to a thin film transistor liquid crystal display and a formation process therefor, in which data lines are isolated from thin film transistors, and the data lines are made of a material having a low chemical reactivity with ITC (indium-tin oxide).
(2) Description of the prior art
Currently, the thin film transistor (TFT) liquid crystal display (LCD) has become an important class of the semiconductor device, and has been put the practical use. If the performance of the thin film transistor is to he improved, the aperture ratio has to he increased, and the length of the channel has to he shortened, so that the mobility would he improved. Meanwhile, if the productivity is to he improved, and if the production cost is to be saved, then the number of the masks which are used in the manufacturing process has to be reduced. Under this condition, it is important that the improvement of performance of the thin film transistor has to be compromised with the reduction of the number of the masks.
In the etch-back type thin film transistor, there is known a manufacturing process in which the number of masks is reduced to 2 or 3 so far, while in the etch stopper type thin film transistor, it is generally manufactured by reducing the number of masks down to 4.
The 2-mask process and the 3-mask process for the conventional etch-back type thin film transistor will be described below referring to the attached drawings.
FIG. 1A to 1E are sectional views showing the manufacturing process for a thin film transistor based on the conventional 2-mask process. This process is described in "Two-mask step-inverted staggered a-Si TFT-Addressed LCDs" (Youtaka Miya et al.), SID (Society for Information Display) 89, Digest pp 155-158.
First, as shown in FIG. 1A, a conductive material is deposited on a transparent substrate 1, and a patterning is carried out by using a first mask, thereby forming a gate electrode 2.
Then as shown in FIG. 1B, a silicon nitride layer (SiNx) 3, an intrinsic amorphous silicon layer (i-a-Si) 4 and a doped amorphous silicon layer 5 are successively deposited by applying a plasma enhanced chemical vapor deposition (PECVD) method. Then a positive photoresist is spread. Then, by using the gate electrode as a mask, ultraviolet rays are irradiated starting from the rear portion of the substrate to make the photoresist sense the rays, and then, a development is carried out.
Then as shown in FIG. 1C, by utilizing the remaining photoresist as a mask, the doped amorphous silicon layer 5 and the intrinsic amorphous silicon layer 4 are etched.
Then as shown in FIG. 1D, a metal layer is deposited, and a patterning is carried out by using a second mask, thereby forming a source electrode 6 and a drain electrode 7.
Finally, as shown in FIG. 1E, by utilizing the source electrode 6 and the drain electrode 7 as a mask, the doped amorphous silicon layer 5 is etched, thereby completing the formation of the thin film transistor.
In the above described conventional process, when the gate electrode is formed, and when the source electrode and the drain electrode are formed, one mask each is required respectively, and therefore, two masks are required in total.
However, in the above described 2-mask process, in order to form a pixel electrode, one mask has to be added, and therefore, three masks are required in actual.
Another example of the 2-mask process is U.S. Pat. No. 5,015,597, and this process is illustrated in FIG. 2.
As shown in FIG. 2, a metal layer 2, an insulating layer 3, an amorphous silicon layer 4, a doped amorphous layer 5 and another metal layer 6' are successively deposited upon a transparent substrate 1. Then a patterning is carried out by using a first mask, and then, a negative photosensitive material such as a polyimide layer 9 is spread to carry out a rear side exposure and a development. Then a transparent conductive material layer 8 composed of ITO (indium-tin oxide) or the like is deposited, and then, a pixel portion is formed by using a second mask.
Unlike the treatise of Youtaka Miya et al., the above described process completes up to the pixel portion by using two masks.
Besides the above two examples, 2-mask processes are described in U.S. Pat. Nos. 4,783,147 and 4,778,560, and in "A Self-aligned, Trilayer, a-Si:H Thin Film Transistor Prepared from Two Photomasks" by Y. Kuo, Journal of Electrochemical Society, Vol. 139, No. 4, Apr. 1992.
The above described conventional 2-mask processes have advantages such that the productivity is improved, and the production cost is saved. However, generally the switching function of the thin film transistor is not perfect, and therefore, they cannot be put to the practical use.
Because of the above described disadvantage of the 2-mask processes, a 3-mask process is preferred. Now the conventional 3-mask process used in manufacturing a thin film transistor liquid crystal display will be described referring to the attached drawings.
FIG. 3 is a sectional view showing the manufacturing process for the liquid crystal display based on a 3-mask process as presented in "A Three-mask Process for High-Mobility a-Si:H TFTs by a 14-inch AM-display (J. Glueck, E. Lueder, T. Kallfass, F. Hirschburger, and M. Brikenstein) published in Euro Display 93 AMLCD-3.
FIG. 4 illustrates the types of masks, and, in accordance with the types of FIG. 4, FIG. 3 is divided into 3A to 3C which are sectional views taken along a line A-A' while FIG. 3D is a sectional view showing a completed device.
In this process, a thin film transistor, a pixel electrode and a storage capacitor are formed by using three masks.
First, a metal such as chrome (Cr) is deposited upon a transparent substrate, and then, a patterning is carried out as shown in FIG. 4A. Thus, a gate line, a gate electrode 2 connected to the gate line, and a storage capacitor lower electrode 10 are formed. Then a silicon nitride layer 3, an amorphous silicon layer 4 and an n+ doped amorphous silicon layer 5 are successively formed by applying a PECVD method, thereby forming a silicon triple layers as shown in FIG. 3A.
Then, a chrome/aluminum (Cr/A1) layer is deposited, and then, as shown in FIG. 4B, a patterning is carried out, thereby forming a first longitudinal data line 6' and a storage capacitor upper electrode 11. Then, by using the chrome/aluminum layer as a mask, the n+ doped amorphous silicon layer 5 and the amorphous silicon layer 4 are etched within a CF4/O2 plasma, so that the structure of FIG. 3B would be formed.
Then an ITO layer is deposited, and then, a patterning is carried out as shown in FIG. 4C, so that a second longitudinal data line 12 and a pixel portion 13 would be formed as shown in FIG. 3C. Finally by using the remaining ITO layer as a mask, the chrome/aluminum layer 6' and the n+ doped amorphous silicon layer 5 are etched, so that a source electrode 6 connected to the data line, a drain electrode 7 connected to the pixel electrode, and a contact layer would be formed. Then, a silicon nitride layer 14 is deposited, thereby competing a liquid crystal display as shown in FIG. 3D.
However, in the above described conventional liquid crystal display which is manufactured by applying the etch-back type 3-mask process, as shown in FIGS. 4B and 4C, there are elongate triple silicon layers containing an amorphous silicon which generates an optical current leakage upon being irradiated by light. These triple silicon layers are lying under the data line, and therefore, if light is irradiated from the rear portion of the substrate, then the optical current leakage is greatly increased, with the result that the off current of the thin film transistor is increased. Further, the source electrode, the drain electrode and the data line are composed of aluminum which is chemically reacted with ITO. Therefore, due to the chemical corrosion of aluminum and ITO, a wiring defect can occur.
Further, the above described disadvantages of the conventional technique occur in a 4-mask process in the same way.
USPTO Backgrounds
USPTO Backgrounds