In the process of manufacturing semiconductor devices having multi-layered interconnection structures, such as a damascene structure, the following steps are performed, for example. Specifically, a resist film is formed on an inter-level insulating film, and is then subjected to light exposure with a predetermined pattern and development. Thereafter, the resist pattern thus formed is used as an etching mask for performing plasma etching on the inter-level insulating film, thereby patterning the inter-level insulating film. Also in the process of fabricating a photo-mask, a resist pattern is formed on a light shielding layer disposed on a substrate, and dry etching is then performed thereon, thereby patterning the light shielding layer.
In order to control the line width and so forth of an etched pattern thus formed, the shapes of etched patterns are periodically observed by an SEM, as disclosed in Patent Document 1 set out below. Where the shape of an etched pattern is out of a predetermined dimension range, etching conditions and process conditions (the light exposure amount and focus value) in a photolithography step for forming a resist pattern to be used as an etching mask are adjusted by an operator, on the basis of past process data or the like, thereby correcting dimensions of etched patterns.
However, since SEM observation requires skill and entails individual differences in judging shapes, it takes a long time to determine light exposure conditions. Further, according to the dimension correcting method described above, dimensions of etched patterns are adjusted in accordance with the average dimensions in one wafer (or one lot), and thus planar fluctuations of dimensions on one wafer cannot be corrected.
[Patent Document 1]
Jpn. Pat. Appln. KOKAI Publication No. 2003-59990
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