In the field of integrated circuits (ICs) and semiconductor devices, it is known for manufacturing and fabrication processes to have variable effects on the performance and characteristics of individual integrated circuits. For example, the performance and characteristics of individual integrated circuits typically varies depending on the location of each electrical element within the integrated circuit.
In order for cells within an integrated circuit to function correctly at a specific operating frequency, a minimum supply voltage is required in order to drive the cells within the integrated circuit such that logical transitions performed by those cells occur fast enough to achieve the required operating frequency. Performance of the logical cells, which is typically composed from transistors, and which usually perform simple logic operations such as OR, AND, XOR, INV and the like, depends on production process parameters, supply voltage and temperature. Due to the performance variations within individual integrated circuits, the minimum supply voltage that is needed to achieve a required operating frequency typically varies between individual integrated circuits.
A system comprising an integrated circuit may be arranged to provide a predetermined supply voltage to the integrated circuit, and to provide an operating clock signal to the integrated circuit comprising an operating frequency at which the semiconductor device is required to operate based on the system design. The supply voltage may be set dependent upon whether the system is required to be optimised to achieve a particular performance (e.g. a higher supply voltage) or for power consumption (e.g. a lower supply voltage), where the operating frequency may be determined based on the supply voltage, in order to achieve optimum performance for that supply voltage. Alternatively, the operating frequency may be set dependent upon whether the system is required to be optimised to achieve a particular performance (e.g. a higher operating frequency) or for power consumption (e.g. to a lower operating frequency), where the supply voltage may be determined based on the operating frequency in order to achieve an optimum performance for that operating frequency.
Due to the performance variations within individual integrated circuits, the system design must take into account the worst case scenario for the integrated circuit in order to ensure correct operation of substantially all integrated circuits and components used within respective systems. Accordingly, in the case where a specific supply voltage is provided to the integrated circuit, the operating frequency will be based on the operating characteristics of a worst case integrated circuit. Alternatively, in the case where a specific operating frequency is required, the supply voltage is determined based on the operating characteristics of a worst case integrated circuit.
A problem with this situation is that the worst case scenario is only applicable to a small proportion of the integrated circuits used. As a result, for the majority of cases, the integrated circuits are operating at a frequency below that of which they are capable, and/or are being provided with a supply voltage greater than that which they require for correct operation. Accordingly, for the majority of cases, the performance and/or power consumption of the system is not optimised. Whilst this problem can be lessened by selecting and only using integrated circuits that have similar performance characteristics, and thus reducing the range of performance characteristics that need to be taken into consideration, the identification and selection of such integrated circuits introduces additional complications and cost/time implications into the fabrication/manufacturing processes. Furthermore, such a solution does not compensate for variations in the performance characteristics of an integrated circuit due to, for example, changes in environmental conditions, such as chip-internal supply voltage (changing due to IR drop phenomenon), temperature, the aging of components, etc. Accordingly, a margin of error must still be allowed for in order for, such variations to be tolerated. This impedes the optimisation of the performance and/or power consumption of the system.
A known method for overcoming these problems is to use performance detection circuitry, for example in the form of a ring-oscillator that is able to generate a signal based on, say, a detected timing performance. This signal may then be used to modify, for example, a voltage supply to ensure a sufficient supply voltage is provided to the integrated circuit in order for the integrated circuit to function correctly at a specific operating frequency. In this manner, a system may be configured for, say, normal case (or even best case) performance characteristics for the integrated circuit. As a result, a lower voltage supply may be used to achieve a required operating frequency than would be the case if the system were configured for worst case performance characteristics, thereby improving the power consumption of the system. However, if an integrated circuit used within the system comprises performance characteristics that are inferior to those for which the system has been configured, the performance detection circuitry will detect as such, and modify the supply voltage as required. Thus, for worst case integrated circuits, the voltage supply is modified such that these integrated circuits are able to function correctly at a specific operating frequency, whilst for normal or best case integrated circuits, improved performance/power consumption is achieved.
However, FIG. 1 illustrates an example of a timing diagram for this known technique of using such performance detection circuitry, demonstrating a problem therewith. A supply voltage is illustrated at 110, which is required to remain above a nominal value 112 in order of for the integrated circuit to function correctly at a specific operating frequency. Also illustrated is a clock signal 120 for the integrated circuit (and the performance detection circuitry). The supply voltage 110 is configured to be above the nominal value 112 during normal operating conditions by only a small amount in order to substantially optimise the power consumption of the system. As a consequence of this, the supply voltage 110 is susceptible to dropping below the nominal value 112 for intervals of time, for example due to a high load current causing a high voltage drop (IR-drop), as illustrated at 114. When the voltage supply 110 drops below the nominal value 112, the performance detection circuitry detects that the voltage supply 110 has dropped below that required for the integrated circuit to function correctly, and modifies the supply voltage 110 such that it rises back above the nominal value 112. However, as can be seen, there is a delay of a complete clock cycle 122 of the clock signal 120 between the supply voltage 110 dropping below the nominal value 112 and the performance detection circuit modifying the supply voltage 110 such that it rises back above the nominal value 112. As will be appreciated, this delay in correcting the supply voltage may result in critical paths within integrated circuit operating at a too slow rate to perform their functions correctly, and thus causing errors within the integrated circuit.
In order to overcome this problem of the delay in correcting the supply voltage, one known solution is to double-sample signals within the integrated circuit in order to detect ‘late’ arriving signals (for example see the Razor technique authored by: Ernst et al, “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation”).
Upon detection of such ‘late’ arriving signals, all data sent within the current clock cycle is purged, and correct data is re-sampled. However, in order for such a solution to be effective, a large number of signals are required to be sampled, which for large and complex integrated circuits is not practical. Furthermore, such a solution would be problematic for non-pipeline type designs, where data processing paths are not serial and may have logic loops, and where stopping input data flow is not feasible.
It is also known within electronic systems for power management techniques to be implemented whereby the supply voltage and operating frequency for an integrated circuit are adjusted during operation, in order to improve power consumption or performance dependent upon the system requirements prevalent at that time. For example, during a period of low activity, the supply voltage and operating frequency may be reduced in order to reduce the power consumption of the device. When activity subsequently increases, the voltage supply and operating frequency may be increased in order to optimise the performance of the device. Whilst such power management techniques are generally able to improve the overall power-to-performance efficiency of a system, they still suffer from the same problem of having to take into account the worst case scenario for the integrated circuit in each configuration.
USPTO Backgrounds
USPTO Backgrounds