1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to an improved process of implanting excess atoms within active areas of a semiconductor substrate laterally adjacent to a trench isolation structure to enhance properties of the integrated circuit.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by conductors which extend over a dielectric that separates or “isolates” those devices. Implementing an electrical path across a monolithic integrated circuit thus involves selectively connecting devices which are isolated from each other. When fabricating integrated circuits it is therefore necessary to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for a MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS processing involves oxidizing field regions of a silicon-based substrate between device areas. The oxide grown in the field or isolation regions is termed “field oxide”. The field oxide is grown during the initial stages of integrated circuit fibrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in field regions pre-implanted with a channel-stop dopant LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems associated with LOCOS. First, a growing field oxide extends laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery, causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topographical disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field regions (i.e., field areas of small lateral dimension) relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the “shallow trench process”. The shallow trench process is particularly suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension. Conventional trench processes involve the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. The trench is then planarized to complete formation of the isolation structure. The trench process eliminates bird's-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning is reduced in narrow isolation spaces, and the threshold voltage is constant as a function of channel width.
While the conventional trench isolation process has many advantages over LOCOS, the trench process also has problems. Because trench formation involves etching of the silicon substrate, it is believed that dangling bonds and an irregular grain structure form in the silicon substrate near the walls of the trench. Such dangling bonds may promote trapping of charge carriers within the active areas of an operating transistor. As a result, charge carrier mobility may be hindered, and the output current, ID, of the transistor may decrease to an amount at which optimum device performance is unattainable.
Further, during subsequent anneal steps (e.g., thermal oxidation for gate oxide formation), the irregular grain structure may provide migration avenues through which oxygen atoms can pass from the trench isolation structures to the active areas. Moreover, the dangling bonds may provide opportune bond sites for diffusing oxygen atoms, thereby promoting accumulation of oxygen atoms in the active areas near the edges of the isolation structures. It is believed that oxygen atoms present in active areas of the silicon may function as electron donors. Thus, inversion of subsequently formed p-type active areas may undesirably occur near the walls of the isolation trench. Further, the edge of a device may conduct less current than the interior portion of the device. Therefore, more charge to the gate of a transistor may be required to invert the channel, causing threshold voltage, VT, to shift undesirably from its design specification.
It is postulated that during the growth of a gate oxide across regions of the substrate exclusive of the isolation regions, the presence of foreign oxygen atoms at the surface of the silicon crystal lattice may lead to a relatively high defect density in the gate oxide. It is further postulated that foreign oxygen atoms accumulating within the active areas may result in regions of the substrate having a high defect density. For example, clusters of foreign atoms may cause dislocations to form in the substrate. It is also believed that low breakdown voltages in thin gate oxides correlate with high defect density near the surface of the substrate.
In a subsequent processing step, the active areas of the semiconductor substrate may be implanted with impurity species to form source/drain regions therein. The semiconductor topography may be subjected to a high temperature anneal to activate the impurity species in the active areas and to annihilate crystalline defect damage of the substrate. Unfortunately, impurity species which have a relatively high diffusivity, such as boron, may undergo diffusion into the isolation region when subjected to high temperatures. As a result, the threshold voltage in the isolation region may decrease and current may inadvertently flow (i.e., leakage) between isolated active areas.
It is therefore desirable to develop a technique for forming a trench isolation structure between active areas in which problems related to dangling bonds and to an irregular grain structure at the edges of the active areas are alleviated. Such a technique is necessary to inhibit charge carriers and oxygen donors from being entrapped in the active areas. It is also necessary that the trench isolation technique provide for the growth of a high quality gate oxide which does not easily undergo breakdown. Yet further, it is desirable that inversion of silicon within the active areas near the edges of the trench isolation structures be prevented.
USPTO Backgrounds
USPTO Backgrounds