Recently, with an increase in a demand for further miniaturization/high-density integration, multilayer wiring formation becomes necessary, and therefore advanced planarization technology is required. This planarization technology is mainly applied to a semiconductor substrate represented by a silicon wafer, and further to a film-shaped multilayer wiring thin film which recently attracts attention and, for example, seems promising for application to SiP (silicon in Package).
Conventionally, a CMP (Chemical Mechanical Polishing) method has been mainly adopted as a method of planarizing an insulating layer or a wiring layer formed on a silicon semiconductor substrate. In this method, the insulating layer or the wiring layer as a surface to be processed is formed relatively flatly in advance, and its surface is finely and flatly processed chemically/mechanically with slurry (chemical polishing agent) while a flat polishing pad is pressed thereon. A hard insulating material surface or metal surface which is provided in advance functions as a stop layer, and CMP is finished. CMP is a method which is independent of variations in semiconductor substrate thickness and TTV (Total Thickness Variation) defined as a difference between a maximum thickness and a minimum thickness.
In addition to the CMP method, several planarization methods, for example, using a cutting tool are thought out (See Patent Documents 1, 2, 3, and 4, for example). However, they are directed to planarization of an SOG film of a partial region on an LSI, and similarly to CMP, they are methods in which cutting is performed with a surface to be cut as a reference and independent of TTV of the semiconductor substrate.
On the other hand, it is thought that in a mounting substrate required to realize SiP, only a thin film wiring layer is used as an interposer to form the mounting substrate inexpensively and simply. Conventionally, a thin-film multilayer wiring substrate without any through-hole formed by preparing plural resin films, in each of which via holes filled with a conductive paste and wirings are formed, and stacking them collectively in a final process is developed. This wiring substrate can be realized at low cost, but scaling down is difficult since the via diameter is approximately between 120 μm and 200 μm, L/S (Line/Space) is approximately between 100 μm/100 μm and 200 μm/200 μm. Hence, to realize both scaling down and low cost, it is effective to separate a multilayer wiring thin film formed on the substrate and make it of a substrate.
Fine planarization can be realized if the CMP method is used, but its process requires a high manufacturing cost since a processing apparatus is expensive and throughput is low. When a metal such as copper and an insulator are planarized at the same time, a hollow called dishing sometimes occurs in a portion where a pattern is sparse. From the need for avoiding this occurrence of dishing, the size of a wiring pattern in an LSI or the like is restricted, so that such an arrangement that a blank portion of the pattern is not formed is required.
On the other hand, for the aforementioned formation of the multilayer wiring thin film, it is necessary to first form the multilayer wiring thin film on a supporting base and strip off or remove the supporting base. As a method of stripping it off, there is a method of coating only a peripheral portion of the substrate with an adhesion improving material using the fact that the adhesiveness between an insulating resin of the multilayer wiring thin film and the supporting base is low and separating the portion coated with the adhesion improving material and a portion uncoated therewith after the formation of a wiring layer is completed to thereby separate the multilayer wiring thin film from the supporting base. This stripping method is, so to speak, the image of stripping off a film, and has a possibility of causing damage to a circuit. On the other hand, the method of removing the supporting base is a method of, for example, if the supporting base is a semiconductor substrate, removing it by grinding and etching. Moreover, if a metal plate made of Al or Cu is the supporting base, it is removed by etching.
Even if either of these methods is adopted, the supporting base itself is reflected in cost, in addition, if the supporting base is a semiconductor substrate in the latter method, a residue after grinding all becomes rubbish, and an enormous amount of rubbish is produced through the process, so that a bad influence on the environment cannot be ignored.
(Patent Document 1) Japanese Patent Application Laid-open No. Hei 7-326614
(Patent Document 2) Japanese Patent Application Laid-open No. Hei 8-11049
(Patent Document 3) Japanese Patent Application Laid-open No. Hei 9-82616
(Patent Document 4) Japanese Patent Application Laid-open No. 2000-173954
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