1. Field of the Invention
This invention relates to a thin film transistor substrate for a liquid crystal display. More particularly, it relates to a thin film transistor substrate, and to a method of fabricating that substrate, having an improved aperture ratio.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) uses an active matrix drive system to produce a moving image. Such systems typically use thin film transistors (TFT's) as switching devices that selectively control individual pixels. Since LCDs can be made relatively small, they have become widely used in personal computers, notebook computers, office equipment (such as copiers), cellular phones, and pagers.
An LCD display usually includes a thin film transistor (TFT) substrate. Referring now to FIG. 1 and to FIG. 2, a typical TFT substrate 1 includes a TFT TP arranged at an intersection between a data line 4 and a gate line 2. A pixel electrode 22 is connected to a TFT drain electrode 10. A data pad portion DP is connected to the data line 4, and a gate pad portion GP is connected to the gate line 2.
The TFT TP includes a gate electrode 6 connected to the gate line 2, and a source electrode 8 connected to the data line 4. Additionally, the drain electrode 10 is connected to the pixel electrode 22 via a drain contact hole 20B. Further, the TFT TP includes semiconductor layers 14 and 16 for defining a channel between the source electrode 8 and the drain electrode 10. Such a TFT responds to gate signals on the gate line 2 by selectively applying data signals on the data line 4 to the pixel electrode 22.
The pixel electrode 22 is positioned in a pixel cell area defined by data lines 4 and gate lines 2. The pixel electrode 22 is comprised of a transparent conductive material having a high light transmissivity. Potential differences between the pixel electrode 22 and a common transparent electrode (not shown) on an upper substrate (also not shown) are produced by data signals applied via the contact hole 20B. The potential differences cause the optical properties of a liquid crystal disposed between the lower substrate 1 and the upper substrate (not shown) to change because of the dielectric anisotropy of the liquid crystal. Thus, the liquid crystal selectively allows light from a light source to be transmitted to the upper substrate when an appropriate data signal is applied to the pixel electrode 22.
The gate pad portion DP applies scanning signals comprised of gate pulses from a gate driving integrated circuit (IC) (which is not shown) to the gate lines 2. A gate pad terminal electrode 30 electrically contacts a gate pad 26 via a gate contact hole 20C.
The data pad portion DP applies data signal from a data driving IC (not shown) to the data line 4. A data pad terminal electrode 28 electrically contacts to a data pad 24 via a data contact hole 20A.
An LCD further includes an alignment layer that provides an initial alignment of a liquid crystal (which is not shown) that is disposed between the TFT substrate and the upper substrate. That alignment layer is provided with an alignment structure that aligns the liquid crystal molecules to provide an initial twist to the liquid crystal. That alignment structure is usually formed by rubbing the alignment layer with a special rubbing material in a carefully controlled rubbing direction. Thus, it should be understood that an LCD has a defined rubbing direction.
The TFT substrate 1 is beneficially fabricated by electrophotographic techniques. First, a gate metal layer is deposited on the TFT substrate 1. That metal layer is then patterned to form a gate line 2, the gate pad 26, and the gate electrode 6, reference FIG. 3A. Referring now to FIG. 3B, a gate insulating film is then formed over the TFT substrate 1, over the gate line 2, over the gate pad 26, and over the gate electrode 6. Then, first and second semiconductor layers are deposited on the gate insulating film 12 and over the gate electrode 6. Those semiconductor layers are patterned to form an active layer 14 and an ohmic contact layer 16.
Referring now to FIG. 3C, a data metal layer is deposited on the gate insulating film 12. That metal layer is patterned to form the data line 4, the data pad 24, the source electrode 8 and the drain electrode 10. After the source electrode 8 and the drain electrode 10 are formed, an ohmic contact layer (16) portion at a location that corresponds to the gate electrode 6 is patterned to expose the active layer 14. The portion of the active layer 14 between the source electrode 8 and the drain electrode 10 acts as a channel.
Next, as shown in FIG. 3D, an insulating material is deposited over the gate insulating film 12. That insulation material is patterned to form the protective layer 18 (reference FIG. 2). The data contact hole 20a and the drain contact hole 20B for exposing the data pad 24 and the drain electrode 10, respectively, through the protective layer 18, and the gate contact hole 20C for exposing the gate pad 26 through the protective layer 18 and the gate insulating film 12, are then defined.
After that, a transparent conductive material is deposited on the protective layer 18. That material is patterned to form the pixel electrode 22, the gate pad terminal electrode 30, and the data pad terminal electrode 28, reference FIG. 3E. The pixel electrode 22 electrically contacts the drain electrode 10 via the drain contact hole 20b. The gate pad terminal electrode 30 electrically contacts the gate pad 26 via the gate contact hole 20c. The data pad terminal electrode 28 electrically contacts the data pad 24 via the data contact hole 20a. 
In the TFT TP described above, the gate electrode 6 has a rectangular shape. Referring now to FIG. 1, an overlapping area D between the gate electrode 6 and the drain electrode 10, and an overlapping area S between the gate electrode 6 and the source electrode 8 exist. As those areas are enlarged, parasitic capacitances Cgd and Cgs, which are proportional to the overlapping areas D and S, are increased. The increases of the parasitic capacitances Cgd and Cgs produce a flicker and a residual image that reduce picture quality. Furthermore, the resulting LCD device has a problem in that the upper edge of the gate electrode 6 limits an aperture ratio.
USPTO Backgrounds
USPTO Backgrounds