Referring to FIG. 1, an IC wafer 102 having photoresist applied thereon is routinely placed on a hot plate 104 during a photolithography process for fabrication of integrated circuits on the IC wafer 102, as known to one of ordinary skill in the art of integrated circuit fabrication. FIG. 1 is a top view of the IC wafer 102 and the hot plate 104, and FIG. 2 is a side view of the IC wafer 102 and the hot plate 104. Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.
Referring to FIG. 2, during a photolithography process, a layer of photoresist 106 is deposited on the IC wafer 102. The IC wafer 102 with the layer of photoresist 106 is placed on the hot plate 104 which is heated to an operating temperature to heat and cure the layer of photoresist 106 on the IC wafer 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The operating temperature of the hot plate 104 for heating and curing the layer of photoresist 106 is typically at least 30.degree. Celsius.
Referring to FIG. 3, with extended use of the hot plate 104 for heating a high number of IC wafers over time, debris and particles of unwanted material 108 form and may even become stuck on the hot plate 104. For example, photoresist from the IC wafer 102 may bake onto the hot plate 104.
The presence of such debris and particles of unwanted material 108 on the hot plate 104 is disadvantageous for heating the IC wafer 102. Uniform baking across the IC wafer 102 is important for reliable and accurate fabrication of integrated circuit structures on the IC wafer 102. The presence of any debris and particles of unwanted material on the hot plate 104 when the IC wafer 102 is placed thereon may cause a temperature gradient across the IC wafer 102 during heating of the IC wafer 102 by the hot plate 104. Such a temperature gradient across the IC wafer 102 may result in line width variations in the integrated circuit structures across the IC wafer 102.
In the prior art, the debris and particles of unwanted material 108 on the hot plate 104 are removed by shutting off the heat source to the hot plate 104 such that the hot plate 104 cools down. The time for cooling down the hot plate 104 from the elevated operating temperature may take approximately 45 minutes. After the hot plate 104 has cooled down sufficiently, an acetone soaked clothe is used to manually wipe off the debris and particles of unwanted material 108 on the hot plate 104. The hot plate 104 is then reheated to the operating temperature. This process of cleaning the hot plate 104 in the prior art may take approximately one hour resulting in a relatively long down time during integrated circuit fabrication of IC wafers. Moreover, if the hot plate has not been thoroughly cleaned with the cleaning process of the prior art, this cleaning process is repeated resulting in even longer down time.
Thus, a mechanism is desired for effectively cleaning the hot plate 104 while the hot plate is at elevated operating temperatures to minimize down time during fabrication of integrated circuits on IC wafers.
USPTO Backgrounds
USPTO Backgrounds