A metal oxide semiconductor field-effect transistor (MOSFET) device operates by virtue of a field controlled channel established in a semiconductor body or surface. MOSFET devices come in a wide variety of forms and employ other materials besides simple metals and oxides. Persons of skill in the art understand that the word “metal” in the term MOSFET refers to any form of an electrically conductive material (e.g., simple metals, polysilicon, metal alloys, semi-metals, mixtures, semiconductors, conductive organics, conductive silicides, conductive nitrides, and the like). Accordingly, the terms “metal” and “silicide” as used herein are intended to include such variations as well as other suitable conductors.
A wide variety of semiconductors may be used for forming MOSFET devices (e.g., types IV, III-V and II-VI semiconductors, organic semiconductors, layered structures, etc.) such as, for example, semiconductor-on-insulator (SOI) structures. Accordingly, the term “semiconductor” is intended to include these and other materials, and arrangements suitable for forming field controlled devices. Persons of skill in the art further understand that the word “oxide” in the label MOSFET stands for any of a large number of insulating dielectrics, and is not limited merely to oxides. Accordingly, the terms metal, oxide, semiconductor, and MOSFET are intended to include these and other variations.
Further, MOSFET devices may be formed with a p-type or an n-type channel (P-channel and N-channel, respectively), depending upon the conductivity type of the various semiconductor regions and/or the polarity of the control voltage. Furthermore, MOSFET devices may function as enhancement mode or depletion mode devices depending upon the threshold voltage of the MOSFET device. For convenience of explanation, and not intended to be limiting, the various embodiments described herein relate to N-channel MOSFET devices. However, persons of skill in the art will understand that P-channel MOSFET devices may be obtained by interchanging the various P-regions and N-regions of the disclosed MOSFET devices. That is, N-type regions replaced by P-type regions, and P-type regions replaced by N-type regions. Accordingly, the description herein of N-channel MOSFET devices serves to illustrate either N-channel or P-channel devices, and the identification of particular regions of the device as being N-type or P-type may be replaced by the more general terms “first conductivity type” or “second, opposite, conductivity type,” where the “first conductivity type” may be either an N-type or a P-type, and the “second, opposite, conductivity type” will then be a P-type or N type, respectively, the choice depending upon what type of MOSFET device (N-channel or P-channel) is desired.
Conventional MOSFET devices may inherently include parasitic bipolar devices. While such parasitic bipolar devices may not interfere significantly with operation of the MOSFET device under many operating conditions, the existence of parasitic bipolar devices may significantly degrade the properties of a MOSFET device operating at voltage and/or current extremes. The inclusion of parasitic bipolar devices sometimes provides a MOSFET device safe operating area (SOA) that is smaller than desired and/or the MOSFET device may be more susceptible to transient stress failure.
As an example, FIG. 1 illustrates a schematic of a conventional N-channel MOSFET device 100. N-channel MOSFET device 100 includes a p-type substrate 110 (P-substrate) formed of, for example, silicon and having surface 1110. P-substrate 110 also includes a negative well 115 (N-well) and a positive well 120 (P-well) formed in P-substrate 110. Dielectric isolation regions 125 and 130 (e.g., silicon oxide) are also formed in surface 1110 of P-substrate 110. A highly doped negative (N+) source region 135 is formed in P-well 120 and an N+ drain region 140 is formed in N-well region 115. N+ source region 135 and N+ drain region 140 are spaced apart in surface 1110. N+ drain region 140 is proximate dielectric isolation region 125 on the opposite side thereof from N+ source region 135. A gate dielectric 1510 (e.g., silicon oxide) is formed on surface 1110 and a gate 150 (e.g., doped polysilicon) is provided overlying gate dielectric 1510. Gate 150 is located so as to be above a portion of P-well 120 proximate source 135, and in this example, also above a portion 1115 of P-substrate 110, and also extending above a portion 1150 of N-well region 115 to isolation region 125. In this example, portion 1115 of P-substrate 110 extends to surface 1110, but this is not essential, and P-well 120 and N-well region 115 may abut; that is, without portion 1115 there between. A highly doped positive (P+) ohmic body contact 160 is provided to P-well 120, which in turn is in ohmic contact with P-substrate 110.
An electrode 165 is provided in ohmic electrical contact with N+ drain region 140. Another electrode 167 is provided in ohmic electrical contact with gate 150. Yet another electrode 170 is provided in ohmic electrical contact with N+ source region 135 and P+ ohmic body contact 160. P+ ohmic body contact 160 and N+ source region 135 are generally shorted together by electrode 170, although this is not essential. When appropriately biased, a source-drain current (Is/d) 180 flows from N+ source region 135 through an N-channel 185 in P-well 120, (and P-substrate 110 if a portion thereof extends to surface 1110) into N-well region 115, and under dielectric isolation region 125 to N+ drain region 140.
FIG. 2 shows an example of a schematic diagram of an equivalent circuit of N-channel MOSFET device 100 (see FIG. 1) having a parasitic bipolar device 200 therein when N-channel MOSFET device 100 is operating under a high-voltage and high-current condition. With assistance from current Id 180 flowing through N-well region 115, an avalanche electron-hole pair generation region 195 may form proximate N+ drain region 140 and adjacent to dielectric isolation region 125. While hot electrons flow to and are collected by N+ drain region 140, hot holes flow to P+ ohmic body contact 160 through a finite resistance 198, under N+source region 135, and forms Ip 199. The portion of P-well 120 beneath N+ source region 135 through which Ip 199 passes has a finite resistance 198, which provides a base-emitter bias to parasitic bipolar device 200. Since Is/d 180 is an electron current and Ip 199 is a hole current, the total current (Itotal) between electrodes 170 and 165 is the sum of the magnitude of the two currents; that is, |Itotal|=|Is/d|+|Ip|.
Under certain operating conditions, positive feedback may occur in N-channel MOSFET device 100. Positive feedback may cause Itotal to rapidly increase, which leads to premature device instability and/or failure. As a consequence of the existence of parasitic bipolar device 200, the properties of N-channel MOSFET device 100 may be degraded, especially the safe operating area (SOA) and/or the ability of N-channel MOSFET device 100 to resist destructive damage due to transient currents.
It has been discovered that adverse consequences of parasitic bipolar device 200, which is inherently associated with many MOSFET devices, are reduced by adopting a source including interdigitated, interwoven, or alternating P+/N+ regions. Accordingly, it is desirable to provide a MOSFET device with a source including interdigitated, interwoven, or alternating P+/N+ regions. In addition, it is desirable to provide a MOSFET device with improved operating characteristics, and more particularly, MOSFET devices with an enhanced SOA, reduced size, and a greater manufacturing yield. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
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USPTO Backgrounds