1. Field of the Invention
The present invention relates to the semiconductor computer memories, and more particularly to a technique for local word-line redundancy that incorporates both word and match-line steering in content-addressable memories (CAM)
2. Background Description
In recent years the level of integration of a semiconductor memory has been increased greatly. However, as the level of integration of a semiconductor memory is made larger, each element is decreased in size, and/or the semiconductor chip is increased in area. Either can aggravate a problem that the manufacturing yields of the memory become correspondingly reduced. In order to reduce effects of this problem, the so-called redundancy technique is used, in which defective memory cells are replaced by spare memory cells already provided on a chip.
Associative memories or content-addressable memories (CAM) retrieve information on the basis of data content rather than addresses. A CAM is adapted to perform fast searches of list based data stored in plurality of locations called CAM entries. Each CAM entry stores a word of data in a plurality of CAM cells, and includes circuits to perform comparisons with externally asserted comparand word typically stored in a comparand buffer. The explosive growth in the communications industry is driving the need for larger CAM circuits. As the area and/or number of devices of the CAM increases, the probability of a process defect occurring in the CAM circuits increases. To alleviate this problem and to improve the manufacturing yields, it becomes important to provide redundancy in CAM circuits.
CAM designs present a unique problem when considering word-line redundancy in that CAM entries are both written and read as well as used for matching, therefore one cannot simply exchange or replace a bad entry with a redundant entry with decoder steering alone. There are known techniques that provide word-redundancy for CAMs. One method uses a separate redundant array architecture for providing address translation, so that the redundant entries are represented as the correct entry index that they are replacing. This technique is the subject matter of concurrently filed application FIS9-20011-0213 US1.
A second approach uses priority encoder to implement word-line redundancy. This technique limits test capability by potentially missing faults. For example, with a priority encoder which gives priority to higher addresses, the most significant failing address can mask other failing addresses. A disadvantage of this technique is increasing of the test time since each match-line is compared to an expected value during test.
Built-in self-test (BIST) is used for testing of memory for existing errors. In general, BIST is special technique in which an external test resource is not needed to apply test patterns for checking a circuit's response to those patterns. BIST also has ability to capture the test results without the need for an external tester. This is often achieved by using a multi-input signature register to capture individual test results and compress these into an overall value called the test signature.
USPTO Backgrounds
USPTO Backgrounds