1. Field of the Invention
This invention generally relates to a digital communication system and, more particularly, to a system and method for generating a jitter-attenuated clock from a gapped clock source.
2. Description of the Related Art
As noted in Silicon Laboratories Application Note AN561, synchronous networks have a hierarchical approach to distributing network timing. They do this by establishing a timing master and slaving the various sub networks and nodes to the master. This approach has met with success for SONET/SDH and packet-based wide area networks.
In contrast, local area networks tend to generate timing locally and slave the immediate receiver's timing to the transmit timing of the driving node. The transmitting node's timing is often completely asynchronous to the timing of its receiver. Two examples of these two distinct approaches are SONET and Ethernet, though neither uses purely a single approach.
SONET typically synchronizes everything to one timing master and distributes timing in a hierarchical manner. However, transport paths can experience jitter and wander with magnitudes that can be greater than one UI (unit interval or the period of the clock frequency), while some payloads cannot be made synchronous and must remain plesiochronous.
The solution that SONET has adopted is payload pointers, which embed the frame slip information into the overhead portion of the SONET frame. Pointer processing is a very effective method of embedding plesiochronous payloads in synchronous SONET frames, but as the SONET data rates have increased over the year, pointer processing has become more and more difficult to implement in FPGAs and ASICs.
Conventionally, every Ethernet transmitter runs at a rate that is determined by its local and individual timing source, which is usually a crystal oscillator, a free running clock with +100 ppm accuracy. The receiving node slaves its timing to the transmitting source using the isochronous timing information that is embedded in the Ethernet data stream. This approach is both efficient and inexpensive. However, one consequence is that timing mismatches between the various asynchronous nodes can accumulate and result in bit errors and dropped packets. This is not a serious issue for the data payloads that Ethernet is intended to carry because the higher level IP protocols implement frame error detection and retransmission. However, as voice payloads have become more common, the situation is more complicated because packet retransmission interrupts the steady flow required for good voice sound quality. Synchronous Ethernet (SyncE) and Timing Over Packet (IEEE-88) are two methods of distributing synchronization through packet networks so that they can interoperate with conventional circuit switches services, such as SONET/SDH.
The solution that is used by OTNIOTU is a compromise between SONET and Ethernet in that it is specifically designed to accept plesiochronous payloads and efficiently place them in containers that are ready for optical transmission over long distances. The timing master for an OTN/OTU node can be asynchronous, and the OTN/OTU wrapper can accept payloads from a variety of sources. It is quite common for OTN/OTU systems to use gapped clocks to achieve these goals.
FIG. 1 is a schematic block diagram depicting a transmitter using a gapped clock (prior art). Gapped clocks are periodic clock signals of a single clock frequency that have clock pulses removed from their stream. Well-formed gapped clocks do not have reduced width pulses (known as runt pulses). Rather, each individual clock pulse is either completely present or completely absent. In a typical application, one in N clock pulses is removed, where N can be a constant or can be constrained to be within a range of values. Advantageously, the reference frequency can be used to create the gapped clock, varying the gapped clock frequency in response to the number of removed clock pulses, at the cost of some irregular periods (gaps) between clock pulses.
As shown in FIG. 1, the data source is plesiochronous with respect to the transmission output rate. That is, the fixed clock can be implemented with an XO or a TXCO that is not locked to anything, including the data source dock. The data source clock and data go into a FIFO so that data comes in at a uniform rate, and is clocked out of the FIFO with a clock that is aperiodic, i.e. gapped.
The purpose of the framer is to add FTC (forward error correction), framing, and other overhead bits that are needed to create a wrapper that conforms to whatever convention or protocol is in use. For this to function properly, the output clock rate must be higher than the data source clock rate because bits are being added to the stream.
FIG. 2 is a schematic block diagram of a Clock Data Recovery (CDR) receiver using a gapped clock (prior art). The CDR separates the isochronous data stream into clock and data signals. Since the input clock to the FIFO only occurs for payload bits, only the payload bits enter the FIFO. The FIFO input clock is not strictly periodic (by virtue of it being gapped). Since downstream consumers of the output data are not usually tolerant of gapped clocks, a jitter attenuator is used to create a clock output that has the same average frequency as the gapped clock with less jitter. The use of a jitter attenuator in the systems of FIGS. 1 and 2 adds considerably to their expense and size.
It would be advantageous if a means existed for creating a jitter-attenuated clock from a gapped clock source.
USPTO Backgrounds
USPTO Backgrounds