The present invention relates to the formation of semiconductor devices. More specifically, the present invention relates to the etching of features into silicon material.
Features such as via holes and trenches are formed in a silicon substrate using anisotropic etching in which sidewalls of the features are protected from etching reaction by a passivation layer formed thereon. The etch gas typically contains halogen gas (such as SF6) for chemical etching and oxygen (O2) gas for passivation. The passivation layer is typically an oxide film containing silicon oxide (SiOx-based film) formed by oxidation of the feature sidewalls. The composition of the passivation layer may be affected by etch chemistry and mask material. Too much sidewall passivation may cause pinch-off, and too little side wall passivation may cause bowing, undercut and CD (critical dimension) degradation.
Deep features may also be formed in silicon substrates by the use of “rapidly alternating” plasma etch processes (gas modulation processes), which utilize a fast repetition of alternating plasma etch cycle and deposition (passivation) cycle. In general, SF6 and C4F8 are the principal process gases for the etch and deposition cycles, respectively. A sidewall-protecting polymer layer is deposited during the C4F8 passivation cycle so as to achieve directional etch. During the SF6 etch cycle, the passivation polymer is removed from horizontal surfaces (such as the bottom of vias) by ion-enhanced etching, and then silicon is etched isotropically from the exposed areas by free fluorine.
In a gas modulation process, the process gases supplied to a plasma processing reactor are rapidly toggled on and off, resulting in the process quickly changing from the etch condition where silicon is removed from the wafer, to the deposition condition where material is deposited onto the wafer and silicon is not removed, and then back again to the etch condition. The duration of the alternating cycles is typically relatively short, and a large number of cycles are typically required to achieve a desired depth into the silicon substrate.
USPTO Backgrounds
USPTO Backgrounds