The present invention relates to semiconductor MOSFET technology and more particularly to a trench MOSFET having self-aligned features.
Power MOSFETs (metal oxide semiconductor field effect transistors) are well known in the semiconductor industry. One variety of power MOSFETs is the vertically-conducting trench MOSFET. A cross-section view of such a MOSFET is shown in FIG. 1. MOSFET 100 has trenches 111 each including a polysilicon gate 112 insulated from body regions 114 by a gate dielectric 110. Source regions 116 flank each side of trenches 111. Dielectric layer 120 insulates gates 112 from overlying metal layer 126. Substrate region 102 forms the drain of MOSFET 100.
When MOSFET 100 is biased in the on state, current flows vertically between source regions 116 and substrate 102. The current capability of MOSFET 100 in the on state is a function of the drain to source resistance (Rdson). To improve the current capability of the MOSFET, it is necessary to reduce the Rdson. One way to reduce the Rdson of the trench MOSFET is to increase the trench density (i.e., to increase the number of trenches per unit area). This may be achieved by reducing the cell pitch. However, reducing the cell pitch of MOSFETs is limited by the particulars of the MOSFET cell structure and the specific process recipe used to manufacture the MOSFET. Reducing the cell pitch is made further difficult by such limitations of the manufacturing process technology as the minimum critical dimensions the photolithography tools are configured to resolve, the minimum required spacing between different cell regions as dictated by the design rules, and the misalignment tolerances.
The different dimensions that determine the minimum cell pitch for trench MOSFET 100 are shown in FIG. 1. Dimension A is the minimum trench width the photolithography tools are configured to resolve, dimension B is the minimum contact opening the photolithography tools are configured to resolve, dimension C is the minimum trench-to-contact spacing dictated by the design rules, and dimension D is the contact registration error tolerance or contact misalignment tolerance. The minimum cell pitch for MOSFET 100 thus equals A+B+2C+2D. Reduction of any of these dimensions without complicating the process technology is difficult to achieve.
Thus, a new approach wherein the cell pitch of the trench MOSFET can be reduced without increasing the process complexity is desirable.
USPTO Backgrounds
USPTO Backgrounds