1. Field of the Invention
This invention relates to computer systems, and more particularly, to memory organization in computer systems.
2. Description of the Related Art
Because memory space in computer systems is limited while the desire for memory space is unlimited, various techniques may be employed to extend the apparent size of a main memory in a given computer system. One such technique is the use of virtual memory, wherein main memory may be augmented with storage space on a disk. Moreover, certain virtual memory schemes may utilize overlays known as pages, wherein an address space may be partitioned into equal sized blocks. These blocks may be swapped between a disk storage system and main memory as needed during operation of a computer system. Some virtual memory schemes may also utilize segments, wherein blocks of an address space are partitioned into blocks of varying sizes.
In computer systems using virtual memory, virtual memory addresses may need to be mapped to physical memory addresses. When a request for an access is made, the request may be issued in terms of the virtual memory address. The virtual memory address may then be translated into a physical address in order to determine the physical location at which the requested information is stored. Information providing mapping between virtual address and physical addresses (i.e. address translations) may be tracked via the use of either a page table or translation storage buffer (TSB). A page table or TSB may be a data structure stored in main memory that includes virtual-to-physical address translations.
A higher-level cache known as a translation lookaside buffer (TLB) may also be used to store virtual-to-physical address translations. When a processor issues a virtual address in conjunction with a memory request, a TLB may be searched to determine whether or not an associated address translation is stored therein. If the address translation is stored in the TLB, known as a ‘TLB hit’ (and the requested data is not stored in a cache), the processor may then access the data from the physical address indicated by the address translation. If the address translation is not stored in the TLB (a ‘TLB miss’), then the processor may access the page table or TSB in main memory and search of the translation.
If the search of the page table or TSB finds a valid address translation (indicating that the corresponding page is residing in main memory), the processor may repeat the memory request, accessing the data at the indicated physical address. On the other hand, if the search of the page table or TSB does not find a valid address (indicating that the page does not reside in main memory), an exception known as a page fault may be generated. Responsive to the page fault, the page containing the requested data may be loaded into main memory from disk storage (and the requested data may also be loaded into at least one cache residing between the main memory and the processor's execution core). Accessing a page of virtual memory from a disk storage system may include asserting an interrupt to a processor and invoking I/O driver software in order to access the disk storage system, and more generally, the I/O hierarchy of the computer system. After the page has been loaded into main memory from the disk storage system, the processor may repeat the request, accessing the data from at least main memory (if not from a higher level cache) as a result of the repeated request.
Accordingly, the miss penalty incurred resulting from a page fault may have a significantly greater latency than for accesses to data from memory (or a higher level cache) where no page fault occurs. In recent years, solid-state drives (SSD's) have been used to reduce some of the latency associated with a miss penalty. An SSD may utilize flash memory or other type of storage that may be significantly faster than typical disk storage. The SSD may be placed in the I/O hierarchy, and upon a page fault, driver software for accessing the SSD may be invoked. However, since SSD accesses may be faster than disk storage, the miss penalty incurred from a page fault may be reduced.
USPTO Backgrounds
USPTO Backgrounds