Sense amplifier circuit timing is very critical to the overall performance a static RAM. The sense amplifier amplifies the differential voltage that is presented on the bit lines during a read operation. The timing of the sense amplifier has a major impact on the read or write through access time of the static RAM. FIG. 1 is a schematic diagram of a typical CMOS static RAM (SRAM) sense amplifier. Prior to a read operation, the SRAM bit line signals “sti” and “sci” are pre-charged to Vdd by lowering reset enable signal (“rse”). When the read operation starts, the “rse” signal is disabled and one of the bit lines is pulled lower, depending on the content of the selected memory cell. Once a significant voltage is developed across the bit lines, the sense amplifier is enabled lowering the sense enable signal “sae” and the sense amplifier amplifies the differential signal to full rail voltage. The sense amplifier output is a dynamic signal whose leading edge depends upon the arrival of the “sae” signal and whose trailing edge depends upon the arrival of the “rse” signal.
In CMOS SRAM design, in order to guarantee data integrity, it is necessary to maximize the signal to noise ratio of the data being transferred from the bit line and bit switch circuitry to the sense amplifier. This can be accomplish by insuring that the differential voltage on a given bit line pair during a READ mode operation is >=(0.15 * VDD), before the sense amplifier enable signal (“sae”) is launched, where VDD is the SRAM supply voltage. Also the sense amplifier restore signal (RSE), which restores the bit lines to VDD must be orthogonal to (i.e. not overlap) the SAE signal, in order to prevent a signal collision, which can result in an excessively high current, and can put the bit lines in an indeterminate state. The “sae” and “rse” signals directly effect the dynamic output of the sense amplifier and the overall operation of the SRAM.
USPTO Backgrounds
USPTO Backgrounds