This invention relates generally to the fabrication of integrated circuits in a semiconductor wafer, and more particularly the invention relates to reducing charging damage to ICs during ion implant and plasma processing of the semiconductor wafer in IC fabrication.
The charging of wafer surface in IC process equipment utilizing charged particles for their operation, such as ion implanters and plasma-based process equipment, is well documented. The build-up of this surface charge on MOS transistor gates and capacitors leads to increasing voltage across the gate oxides until the oxides begin to conduct, shunting the deposited charge to wafer substrate. Since the wafer substrate is typically floated electrically, the current entering the substrate in one part of the wafer exits the substrate in some other part of the wafer, as illustrated in FIG. 1 for wafer 10, transistor 12, and currents 14. Consequently, both positive currents (entering the wafer) and negative currents (leaving the substrate) have been recorded with the CHARM-2 monitor wafers. See Lukaszek U.S. Pat. No. 5,594,328. Since the passage of current through gate oxides is accompanied by charge trapping in the oxide, leading to oxide damage and MOS transistor performance degradation or failure, it is highly desirable to minimize the current flow through gate oxides during IC fabrication in order to maximize IC yield and reliability.
The characterization of the charging current densities with the CHARM-2 monitor wafers in ion implanters and other plasma-based equipment indicates that typical positive and negative J-V plots are of the form shown in FIGS. 2(a) and 2(b). It should be observed that both positive and negative J-V plots obtained at any location on the wafer show monotonically decreasing current density with increasing surface-substrate potential (in accordance with plasma theory). Consequently the sums of all positive and negative currents over the wafer are also monotonically decreasing function of surface-substrate potential, similar to FIGS. 2(a) and 2(b), representing the operational characteristics of the plasma within the physical and electrical constraints imposed on it by the given plasma equipment configuration in its particular operating state.
It has also been observed through the use of the CHARM-2 monitor wafers that when the wafer surface is covered with photoresist in a manner which limits the gate oxide area available for conduction of the charging currents, the magnitudes of the surface-substrate potentials and the corresponding oxide current densities increase. This phenomenon may be understood with the help of FIGS. 2(a) and 2(b): decreasing the gate oxide area available for conduction of charging currents results in a different plasma operating state, characterized by reduced over-all current flow through the substrate, but accompanied by increased surface-substrate potentials, in accordance with FIGS. 2(a) and 2(b).
The present invention is directed toward minimizing the surface-substrate potentials to minimize the currents which flow through the gate oxides, thus minimizing MOS transistor damage during IC fabrication.
USPTO Backgrounds
USPTO Backgrounds