The present invention is directed generally to semiconductor interconnect layers exhibiting a low RC time delay, and, more particularly, to semiconductor interconnect layers made of a material having a low resistivity that is surrounded by a material with a low dielectric constant.
It is common in the semiconductor art to use layers of metal, polysilicon, or another conductor to conduct current between various semiconductor devices that form integrated circuits. The layers of conductor are connected to each other by means of vias and are connected to other materials by means of contacts.
When a metal is used to form the interconnect layers of conductors, the metal is usually deposited on the semiconductor by sputtering, chemical vapor deposition (CVD), or evaporation. The CVD process forms a non-volatile solid film on a substrate by the reaction of vapor phase chemicals that contain the desired constituents. The metals that are commonly used for the interconnect layers are aluminum and its alloys. The metal layers are typically deposited over dielectric materials, such as silicon dioxide. Thus, parallel plate capacitive effects are observed due to this structure. The capacitance for a layer can be represented as:
                    C        =                                            ε              0                        ⁢                          ε              ins                        ⁢            A                    D                                    (        1        )            where:
D=SiO2 thickness
A=Area of plates
∈0=Permittivity of free space
∈ins=Permittivity of SiO2 
This capacitance increases as the density of the integrated circuits increases. Also, the line resistance due to the metal layers increases as the density of the integrated circuits increases. The resistance of a sheet of conducting material is given as:
                              R          s                =                              p            ⁢                                                  ⁢            l                                t            ⁢                                                  ⁢            W                                              (        2        )            where:
p=Material resistivity
t=Material thickness
L=Material length
W=Material width
Thus, the time delay caused by the product of the line resistance and the capacitance becomes critical.
FIG. 1 shows a cross sectional view of a typical semiconductor device (a transistor) in simplified form. A Local Oxidation of Silicon (LOCOS) process is performed on a substrate layer 10 to create a gate oxide region 12 separated by field oxide regions 13. A polysilicon layer 14 is then deposited; typically to form the gate structure of the transistor, and a spacer 15 is fabricated around the remainder of layer 14. Impurities are diffused into the substrate layer 10 to form diffusion areas 16, which typically form the drain and source structures of the transistor. A layer of silicon dioxide 18 is grown and the contact and via areas are removed by etching. A silicide or metal layer 20 is formed on the diffusion areas 16, which typically provide areas for interconnection with the drain and source structures of the transistor. A first layer of metal 22, typically aluminum or an alloy of aluminum, is then deposited and areas are removed to form the required interconnection pattern. Alternatively, metal contact plugs may be formed in the contact and via area formed in layer 18. Subsequent layers of silicon dioxide and metal may be grown and deposited, respectively, depending on the interconnection pattern required for the integrated circuit.
An attempt to reduce the capacitance associated with interconnect layers deposited on dielectric materials is shown in Togo, et al., “A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs”, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39. Togo, et al. outlines a transistor structure in which the sidewalls of the gate structure are surrounded by an air gap. A silicon nitride sidewall is first fabricated that surrounds the gate. A layer of silicon dioxide is formed around the silicon nitride sidewall. The silicon nitride sidewall is removed by a wet etching process to form an air gap between the gate structure and the silicon dioxide.
Another attempt to reduce the capacitance associated with interconnect layers deposited on silicon is shown in Anand, et al., “NURA: A Feasible, Gas-Dielectric Interconnect Process”, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 82-83. Anand, et al. outlines a metal interconnect structure in which layers of a gas are formed between thin layers of silicon dioxide. The thin layers of silicon dioxide have metal interconnect layers deposited on them. The process begins when layers of carbon are formed on a surface and trenches are formed for future interconnections. An interconnect metal layer is formed in the carbon trenches and a thin layer of silicon dioxide is sputter-deposited. Oxygen is then furnace ashed into the carbon layer through diffusion and the oxygen reacts with the carbon to form carbon dioxide. This process is repeated to form the interconnect structure of the device under fabrication.
Although Togo, et al. claims to reduce the capacitance associated with the interconnect layers by reducing the dielectric constant of the materials between the interconnect layers, Togo, et al. only provides a low dielectric material (air) around the gate contact of a transistor. Also, Togo, et al. does not disclose an interconnect structure that has reduced resistivity.
Likewise, even though Anand, et al. claims to reduce the capacitance associated with the interconnect layers by reducing the dielectric constant of the materials between the interconnect layers, Anand, et al. adds complexity to the semiconductor fabrication process because carbon is used in the process, which is not typically used in the manufacture of semiconductor devices. The method of Anand, et al. does not disclose an interconnect structure that has reduced resistivity.
Thus, the need exists for a semiconductor interconnect structure with reduced capacitance and reduced resistivity, thereby decreasing the RC time delay associated with the interconnect layers. The need also exists for a method of fabricating such a structure using standard fabrication steps in conjunction with commercially available processing equipment.
USPTO Backgrounds
USPTO Backgrounds