Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. The flash memory may be erased and reprogrammed in blocks.
NAND may be a basic architecture of flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). Example NAND architecture is described with reference to a construction 2 of FIG. 1.
The construction includes a pair of memory strings 3 and 3a. The strings may be identical to one another, but string 3a is shown with less detail than string 3.
Referring to string 3, such includes a stack 10 of alternating electrically conductive levels 4 and electrically insulative levels 6. The levels 4 and 6 may comprise, for example, conductively-doped polysilicon and silicon dioxide, respectively.
A hardmask material 7 (e.g., silicon nitride) is over stack 10.
The stack 10 is over source side select gate material 12 (e.g., conductively doped polysilicon), which is over electrically insulative etch stop material 14 (e.g., aluminum oxide and/or silicon dioxide), which is over common source material 16 (e.g., tungsten silicide), which is over a semiconductor base 18 (e.g., monocrystalline silicon).
Breaks are provided within the stack 10, and between the common source material 16 and the base 18, to indicate that there may be more levels or materials than those shown in FIG. 1.
Vertically-stacked memory cells 20 are within the stack 10. The memory cells comprise control gates 22 (only some of which are labeled, and which correspond to regions of conductive levels 4), blocking dielectric 24 (e.g., one or more of silicon nitride, silicon dioxide, hafnium oxide, zirconium oxide, etc.), and charge storage material 26 (e.g., material suitable for utilization in floating gates or charge-trapping structures; such as, for example, one or more of silicon, silicon nitride, nanodots, etc.).
A channel material 28 (e.g., polysilicon) forms a pillar extending through the stack 10 to the common source material 16.
Gate dielectric material 30 (e.g., silicon dioxide) is between the channel material 28 and the charge storage material 26 of the memory cells 20.
The channel material connects to a drain side select device 32, which in turn connects to a data line (e.g., a bitline) 34.
Referring to string 3a, such also includes the stack 10, hardmask 7, source side select gate material 12, and etch stop material 14. Further, string 3a is shown to comprise the channel material 28 and gate dielectric material 30, with the channel material 28 extending to the common source material 16. The string 3a comprises memory cells of the type shown as cells 20 of string 3, but such memory cells are shown in a more simplified view in string 3a. A drain side select device (like device 32) and data line (like line 34) would also be electrically coupled with channel material of string 3a, but such are not shown.
A prior art problem is shown in locations were channel material 28 of strings 3 and 3a interfaces with common source material 16. Specifically, the common source material may react with oxygen to form an oxide 36 which is difficult to remove. The oxide 36 may problematically reduce the quality of the electrical contact between materials 16 and 28; which can impair performance of devices, and in some cases render devices non-operational.
USPTO Backgrounds
USPTO Backgrounds