It has been a trend in the field of making semiconductor devices to increase the packing density of a silicon wafer. IC designers are continuously tempted to scale down the size of each device and increase chip level integration at an ever faster pace. Further, the manufacturers of the devices are striving to reduce the sizes while simultaneously increasing their speed.
As the semiconductor production continuously grows, more types of package are developed. One of the most notable is the plastic molded package, such as described in U.S. Pat. No. 5,586,010. The renewed interest in high density hybrid is driven by the requirement to handle large numbers of IC interconnections, the increasing clock rate of digital systems and the desire to pack greater functionality into smaller spaces. Therefore, the number of a package's leads becomes more and more. An important consideration in making small, high speed and high density devices is providing packages capable of the spreading heat generated by the devices. A further problem confronting the technology is the relentless need for more I/O per chip. A conventional lead frame package, such as SOP, PQFP, has a limitation to increase the number of the package's lead.
VLSI integrated circuits packages having high connection capacity are pin grid array (PGA) and ball grid array (BGA). One such package type is plastic ball grid array (PBGA) that uses a bismaleimidetraizine (BT) as a substrate. The PBGA offers many advantages over conventional packages such as solder ball I/O and high speed. The PBGA package has high speed due to a short path for signal transformation. The solder balls are set on a package surface in a matrix array which can provide more signal contacts.
Connections are made form bond pads of a semiconductor die to contact pads of wiring bonds. Conductive metal patterns connect to the solder balls of the BGA package. The package has a die and a housing for protection of the die. The semiconductor die is covered by an encapsulated cap.
Although the PBGA has a shorter path for spreading heat than a conventional package, but the substrate of the PBGA is made of BT so that the efficiency of spreading heat is poorer than the leadframe package. In order to solve the problem, pad array semiconductor devices have been proposed (see U.S. Pat. No. 5,285,352). The structure uses a thermal conductor in a pad array device permits routing of conductive traces and terminals beneath a semiconductor die for improved utilization of substrate area. An opening and a thermal conductor are set under the die on BT substrate. The heat that is generated by devices is dissipated to computer board via silver epoxy, the opening and a metal ground plane.
A ball grid array package having integral bumps is described in U.S. Pat. No. 5,629,835 entitled "METAL BALL GRID ARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY" by Mahulikar et al. The purpose of art is to provide a lead frame having outer lead pins substantially perpendicular to the inner lead portion.
Unfortunately, the structure of the conventional package can not meet the requirement of the trend. Further, the efficiency of spreading heat is poor. Thus, what is required is an improved package with good efficiency of spreading heat.
USPTO Backgrounds
USPTO Backgrounds