In semiconductor memories, there is continuous pressure in industry to reduce component dimensions and fit more components in a given amount of chip area. As dimensions shrink, numerous technical hurdles become more significant. For example in non-volatile memory devices, such as NAND memory, when data line spacing is reduced, adjacent data lines begin to affect each other during operation. One solution to this problem has been to only operate every other data line at one time. This approach simply ignores the effect of adjacent data lines by never operating adjacent data lines at the same time. Improved memory device configurations and methods are desired to provide improved device operation and ability to operate at smaller scales.
USPTO Backgrounds
USPTO Backgrounds