1. Field of Invention
The present invention relates generally to mass digital data storage systems. More particularly, the present invention relates to systems and methods for efficiently testing flash memory systems.
2. Description of the Related Art
The use of non-volatile memory systems such as flash memory storage systems is increasing due to the compact physical size of such memory systems, and the ability for non-volatile memory to be repetitively reprogrammed. The compact physical size of flash memory storage systems facilitates the use of such storage systems in devices which are becoming increasingly prevalent. Devices which use flash memory storage systems include, but are not limited to, digital cameras, digital camcorders, digital music players, handheld personal computers, and global positioning devices. The ability to repetitively reprogram non-volatile memory included in flash memory storage systems enables flash memory storage systems to be used and reused.
The reliability of a flash memory storage system, or a flash memory package, is important to ensure that information may be reliable stored and retrieved. In order to effectively ensure that a flash memory package is reliable, a flash memory package may be tested as a part of an overall manufacturing process. FIG. 1 is a diagrammatic representation of a testing device which is suitable for testing non-volatile, flash memory packages. A testing device 102 includes a computing device 104 and heads 106. As shown, testing device 102 may include two heads 106 which are each arranged to hold approximately thirty-two packages 112 in an array 108. Each head 106 tests an array 108 of packages 112, i.e., head 106a tests packages 112 associated with array 108a and head 106b tests packages 112 associated with array 108b. Specifically, heads 106 test packages 112 by performing operations on packages 112 at the command of computing device 104.
With reference to FIG. 2a, the configuration of one conventional package 112 will be described. As shown, package 112 includes pads 202 and a plurality of dies 210a, 210b which are arranged to receive signals, e.g., test signals, from computing device 104 of FIG. 1. Herein and after, for ease of discussion, dies 210a, 210b will generally be referred to as dies 210. Once test signals are received by pads 202, test signals are processed by a first die 210a. By way of example, if a test signal is a program signal, then memory cells associated with die 210a are programmed. Once a test signal associated with die 210a are processed, the test signal may be sent across connections 214 to a second die 210b, which then processes the test signal. That is, dies 210 are arranged to process signals or, more generally, to be accessed, in a serial manner such that substantially all actions associated with die 210a are completed before the actions are performed with respect to die 201b. 
As mentioned above, dies 210 include memory cells which are arranged to store data, e.g., data provided in a test signal. FIG. 2b is a diagrammatic representation of package 112 of FIG. 2a which shows memory cells in accordance with an embodiment of the present invention. Each die 210 includes any number of memory cells 220, 224. Memory cells 220, 224 are arranged to store data which may be retrieved or read as needed.
Dies 210 process signals or commands in a serial manner such that when a program instruction, for example, is received, memory cells 220 are programmed before memory cells 224 are programmed. That is, memory cells 224 which are associated with die 210b are not programmed until after memory cells 220 of die 210a are programmed, i.e., dies 210 are programmed serially with memory cells 220 of die 210a being programmed before memory cells 224 of die 210b. 
In general, package 112 is tested using a tester such as testing device 102 of FIG. 1. Testing package 112 generally enables a determination to be made regarding whether package 112 is viable or reliable, e.g., whether package 112 is suitable for use by a consumer, as previously mentioned. FIG. 3 is a process flow diagram which illustrates the steps associated with a conventional method of testing a flash memory package with multiple dies. A process 302 begins at step 306 in which a flash memory package is placed in a tester. Typically, a tester includes a mechanical support, test heads, and a computing system, as will be appreciated by those skilled in the art. It should be understood that although a tester such as testing device 102 of FIG. 1 generally tests multiple packages at any given time, for ease of discussion, process 302 is described in terms of testing a single package. Once the package is placed in the tester, power is provided to the package in step 310. That is, the package is powered up.
After the package is powered up, the dies in the package are enabled for serial operation in step 314. Enabling the dies for serial operation typically involves issuing commands using the tester such that memory cells on dies may be tested serially, one die at a time. In step 318, program stress testing is performed in a serial manner. Program stress testing is typically testing that stresses specific parts of transistors associated with the memory cells, and often involves ensuring that the package may survive a ten year life span. Performing such testing in a serial manner generally involves serially testing substantially all memory cells of one die before serially testing substantially all memory cells of another die.
Once program stress testing is completed, the package is powered down in step 322. Upon powering down the package, all dies are enabled for serial operation in step 326, and erase stress testing is performed in a serial manner in step 330. Erase stress testing typically involves stressing transistors used in erase operations. After erase stress testing is performed, the package is powered down in step 334, and the dies are enabled for serial operation in step 338. Then, in step 342, read stress testing, which generally involves stressing transistors used in read operations, is performed in a serial manner. When the read stress testing is completed, substantially all stress testing is considered to be completed. Accordingly, process flow moves to step 346 in which program-read-erase testing is performed. The steps associated with one conventional method of performing program-read-erase testing will be described below with respect to FIGS. 4a and 4b. When program-read-erase testing is completed, the process of testing a flash memory package with multiple dies is effectively completed.
With reference to FIGS. 4a and 4b, the steps associated with one conventional method of performing a program-read-erase test, e.g., step 346 of FIG. 3, on a flash memory package with multiple dies will be described. A process 346 begins at step 402 in which the package is powered down. Once the package is powered down, the dies in the package are enabled for serial operation, i.e., using the tester which is performing the program-read-erase test, in step 406. After the dies are enabled, the dies are serially programmed in step 410. Typically, each memory cell associated with each die is serially programmed to a particular value.
In step 414, the package is once again powered down. Then, in step 418, all dies in the package are enabled for serial operation, and the contents of the dies or, more specifically, the contents of the memory cells associated with the dies, are read serially. The read data is then analyzed in step 426 to ascertain whether the data that has been read was accurately programmed in step 410. That is, the analysis in step 426 may be performed to ascertain whether the data that was programmed in step 410 was stored in the memory cells accurately, or, more generally, if the read data is consistent with what is expected.
Once the read data is analyzed in step 426, the package is powered down in step 430. In step 434, all dies are enabled for serial operations, and the dies are serially erased in step 438. The package is then powered down in step 442. From step 442, process flow proceeds to step 446 in which all dies are enabled for serial operation. After the dies are enabled for serial operation, the contents of the dies are read serially in step 450 such that the memory cells of one die within the package are read serially before the memory cells of another die within the package are read serially. The data that is read from the memory cells is analyzed in step 454, for example, to determine if the memory cells were properly erased in step 438 or, more generally, if the read data is as expected.
The package is powered down in step 458, after the read data is analyzed in step 454. From step 458, process flow proceeds to step 462 in which it is determined if the package failed the program-read-erase test. If it is determined that the package failed testing, then the indication is that at least one memory cell associated with the package either failed to be programmed properly, failed to be read properly, or failed to be erased properly. Hence, the package is rejected in step 470, and the process of performing a program-read-erase test is completed. Alternatively, if it is determined in step 462 that the package did not fail testing, then the package is accepted, e.g., considered to be reliable, in step 466, and the process of performing a program-read-erase test is completed.
The overall process of testing a flash memory package is time-consuming. In particular, program and erase operations account for a significant percentage of the time required to perform an overall testing process. For example, one standard overall testing process performed on a flash memory package may require over three hours, with a substantial percentage of the three hours being associated with programming and erasing memory cells of the package. The amount of time associated with an overall testing process may also be shorter, or much longer, however, depending upon the associated test flow and the density of the flash memory package. A long testing process generally reduces the throughput associated with a tester, e.g., testing device 102 of FIG. 1. That is, the number of flash memory packages which may be testing by a testing device is typically limited by the amount of time required to test the packages. As the cost of testing devices is relatively high, obtaining additional testing devices to increase the number of flash memory packages which may be testing in a given time period is generally not desirable.
Therefore, what is desired is a method for increasing the throughput of a testing device. That is, what is needed is an efficient method for testing flash memory packages.
USPTO Backgrounds
USPTO Backgrounds