This application relates generally to automatic test equipment for electronics (ATE), and more particularly to the synthesizing clock signals for use with ATE systems.
A need frequently arises in ATE systems for generating accurate, low-jitter clock signals from a reference clock. If the desired clock frequency is an integer quotient of the reference clock frequency, a simple frequency divider such as a counter can be used. Similarly, if the desired frequency is an integer multiple of the reference clock frequency, a frequency multiplier can be used. The frequency multiplier may take the form of a harmonic generator followed by a filter, orxe2x80x94more commonly todayxe2x80x94a phase-locked loop with a frequency divider in the feedback path.
Frequency division and multiplication are often combined in a single system, providing signals that bear an N/M relationship to the reference clock frequency. The performance of these systems tends to degrade, however, when N and M become large. Limiting N and M to smaller values sacrifices frequency resolution.
An alternative approach called Direct Digital Synthesis (xe2x80x9cDDSxe2x80x9d) provides arbitrarily high frequency resolution, but at the expense of increased complexity. FIG. 1 illustrates a conventional DDS for generating clock signals. A phase accumulator 114 is made to increment once per cycle of a reference clock. The size of each increment of the phase accumulator 114 is represented by the output of divider 110. This value equals the full-scale value of the phase accumulator 114 (nominally 1) times the frequency of the desired output clock, divided by the frequency of the reference clock. For example, assuming a 100 MHz reference clock, the value at the output of the divider 110 would nominally equal {fraction (1/100)} to generate a 1 MHz output clock. The phase accumulator 114 would then be made to increment by steps of {fraction (1/100)} upon each cycle of the reference clock.
This action of incrementing the phase accumulator 114 causes it to reach its full-scale value and xe2x80x9croll overxe2x80x9d once per period of the desired output clock. The values stored in the phase accumulator 114 thus represent relative phase of the desired output clock, with zero to full-scale representing 0 to 2xcfx80 radians. Upon each cycle of the reference clock, a look-up table 116 converts the phase stored in the phase accumulator 114 into a digital representation of the desired output waveform (generally the sine of the phase at that instant). A digital-to-analog converter 118 then converts the digital representation into voltage, and a filter removes artifacts from the output signal.
The performance of a DDS is generally limited by the number of entries in the look-up table 116 and the resolution of the digital-to-analog converter 118. Often, simple filters are insufficient to remove conversion artifacts, and it is necessary to add a phase-locked loop 120 at the output of the converter. The resulting implementation tends to be complex and expensive, as those skilled in the art are well aware.
Another alternative for generating clock signals is disclosed in U.S. Pat. No. 5,274,796, assigned to Teradyne, Inc., of Boston, MA. In that patent, a timing generator is disclosed that produces clock signals for which each cycle is composed of an integer number of reference clock cycles, plus a non-integer delay. An interpolator supplies the non-integer delay in response to a digitally derived xe2x80x9cresiduexe2x80x9d signal on a cycle-by-cycle basis, to correct for errors due to missing fractional portions of a reference clock cycle. Although accurate, the interpolator technique tends to be expensive, due to the high cost of the interpolators themselves.
With the foregoing background in mind, it is an object of the invention to generate clock signals from a reference clock more economically than can be done using conventional techniques.
To achieve this object and other objectives and advantages, a clock generator produces a time-quantized signal having a period equal to the period of a desired clock signal to within a quantization error. A noise-shaping requantizer processes the quantization error on a cycle-by-cycle basis to generate noise-shaped values, and a variable pipeline delay selectively delays the time-quantized signal by an integer number of reference clock periods, based upon the noise-shaped values. The effect of noise shaping the quantization error and selectively delaying the time-quantized signal in response to the noise shaped values is to shift jitter in the time-quantized signal from relatively low frequencies to relatively high frequencies. A phase-locked loop can then be used to filter the remaining high-frequency jitter.
USPTO Backgrounds
USPTO Backgrounds