1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a method for manufacturing a MOS (referred to as MOS hereafter) device with improved well control stability.
2. Description of the Prior Art
Offset spacers are used in semiconductor devices. The Offset spacers can benefit the process window of photolithography and allow the realization of smaller cell size and therefore smaller chip size.
FIGS. 1A through 1C illustrate, in cross-section, the conventional offset spacers process. This process begins by providing a semiconductor substrate 10 having a gate electrode 12. The gate electrode 12 includes a gate oxide layer 14 and a conducting gate 16 as shown in FIG. 1A. The conducting gate 16 is typically a polysilicon (poly) gate.
Next, as shown in FIG. 1B, offset spacers 18 are formed on sidewalls of the gate electrode 14. The offset spacers 18 typically have a fixed width, such as 150 angstroms.
As shown in FIG. 1C, source and drain extensions 20 are formed in the semiconductor substrate 10 by ion implantation. Spacers 22 are formed on sidewalls of the gate electrode 12. Source and drain regions 24 are formed in the semiconductor substrate 10 by ion implantation.
However, the channel length of the device is fixed after poly etching and the critical dimension of the poly gate is not easily controlled by the patterning process beyond 0.13 xcexcm. In addition, since the critical dimension of the poly gate is not precise, electric characteristics are unstable and can not be remedied. Thus, the minimization of the feature size can not be achieved.
An object according to the present invention is to provide a method for manufacturing a MOS device with improved well control stability characterized by improvement of electric characteristics of the device.
The present invention achieves the above-indicated object by providing a method for determining conducting gate spacer thickness to well control MOS device stability comprising the steps of: providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.
USPTO Backgrounds
USPTO Backgrounds