1. Technical Field
The present disclosure relates to the field of Analog-to-Digital Converters (ADCs).
2. Description of the Related Art
In many electronic applications, a measure of analog signals is required. Usually, a General-Purpose Analog-to-Digital Converter or GPADC is used to convert such analog signals from the analog domain to the digital domain while measuring them. One of these electronic applications is, for example, mobile phones wherein many analog signals have to be continuously monitored to keep the microprocessor of the mobile phone device aware of the state of the device itself.
Particularly, analog-to-digital (A/D) converters with Successive Approximation Register (SAR) charge redistribution are widely used for such applications.
Even if SAR A/D converters have usually good performances in terms of conversion speed, in many applications is nowadays often desirable that such converters have also a resolution of 12 or up to 14 bits in order to increase precision in the measurements.
To overcome related problems emerging with converters having increased resolution, such as reduction of the settling time of analog voltages or noise immunity constraints, known solutions provide for implementing some expedients into digital blocks without incrementing the performances of analog blocks. In order to preserve performances of the converter, methods for calibrating or correcting errors into the digital domain have to be used. Some of these methods are indicated as redundancy techniques by the person skilled in the art.
As known, a traditional SAR algorithm for an N-bit A/D converter schedules N comparisons done in a row, with a bit in the output code defined at the end of each comparison, starting from the Most Significant Bit (MSB) and down to the Least Significant Bit (LSB). By applying a redundancy method to the same N-bit SAR A/D converter, the comparisons to be scheduled are more than N in order to correct possible errors that might occur because of noise, disturbances, or lack of an adequate settling time of the voltages that have to be compared.
However, the redundancy techniques known in the art are almost always generic, e.g., they are not linked to any particular A/D converter topology. As a consequence, applying a known redundancy technique to an existing SAR A/D converter would require for the designer heavy and time-wasting modifications on the original topology and layout of the converter itself.
In addition, contrary to a conventional SAR algorithm, the redundancy techniques known in the art require additional processing to be performed by the digital controller of the converter during the conversion to determine a correct code to be compared. This can lead to meta-stability problems, whose aftermaths are not always easy to foresee and minimize.
USPTO Backgrounds
USPTO Backgrounds