1. Field of the Invention
This invention relates to a system for scan testing logic circuit networks.
2. Description of the Prior Art
Scan testing is a widely accepted means for functional testing of large scale integrated circuits and very large scale integrated circuits. To implement scan testing a special shift register is usually added to an integrated logic circuit solely for the purpose of functional testing. The special shift register comprises interconnected test blocks which are connected to the logic circuit.
FIG. 1 shows a typical prior art scan testing circuit arrangement including a network of combinational logic circuits 1, 2, 3 . . . n. The primary inputs IN.sub.1, to the IN.sub.2, . . . IN.sub.n combinational logic circuitry and the outputs OUT.sub.1, OUT.sub.2, . . . , OUT.sub.n from the combinational logic circuitry remain unchanged, but test blocks 10, 20, 30 . . . n0 are connected respectively to the combinational logic circuitry 1, 2, 3 . . . n at points which permit surveillance of the functions performed in each logic circuit. The test blocks are interconnected to form a shift register 45 having a serial input terminal (scan-in input line) 4 and serial output terminal (scan-out output line) 5. The operation of the combinational logic circuits and the special shift register are generally dependent only upon the digital logic level, and correct operation is not dependent upon the rise time, fall time, or minimum delay of any individual circuit or signal.
Each test block in FIG. 1 has four input lines and one output line. For example, the test block 10 has a primary data input line 13 associated with combinational logic circuit 1, an auxiliary data input line 11, a scan control input line 14, and a clock input line 12. The auxiliary data input line 11 is connected to the scan-in input line 4. The output line 15 of the first test block 10 is connected to the auxiliary data input line 21 of the second test block 20, the output line 25 of the second test block is connected to the auxiliary data input line 31 of the third test block 30, and the output line of each test block is connected to the auxiliary data input line of the next test block up to the last test block n. The output line n5 of the final test block n is tied to the scan-out output line 5.
A scan test consists of two basic parts. The operation of the special shift register 45 comprising the interconnected test blocks 10, 20, 30, . . . , n0 is first checked. Then the operation of the logic system is checked. To verify operation of shift register 45 a test vector is scanned through shift register 45. A scan test is used to verify the operation of the logic system. Proper sequencing of the clock signal, scan control signal, test signals, and primary input signals is necessary to perform the scan test. The scan test applies known input signals to combinational logic circuits and then the output signals, generated by the logic circuit response to the known input signals, are measured. Comparison of the predicted output signals with the measured output signals indicates the functionality of the circuits.
The sequencing of the clock signals, scan control signal, test signals and the primary input signals will depend upon the configuration of the test blocks. A typical test block 10' which requires only a single clock line is shown in FIG. 2. A primary data input line 100 from a combinational logic circuit such as circuit 1, 2, 3, . . . or n of FIG. 1 is connected a first input terminal of the AND gate 120. A first line 101 connects the scan control line 103 to an inverter on the second input terminal of the AND gate 120. The auxiliary data input line 102 and the scan control line 103 are connected to the input terminals of a second AND gate 121. The output line 105 from the AND gate 120 and the output line 106 from the AND gate 121 are connected to the input terminals of OR gate 122. The output line 107 from the OR gate 122 is connected to the input terminal D of the master latch 123. A clock input line 104 is connected to the clock terminal C of the master latch 123 and to an inverter 126. The output line 109 from the master latch 123 is connected to the input terminal D of a slave latch 124. The output line 110 from the inverter 126 is connected to the clock input C of the slave latch 124. The test block output line 111 is connected to the output terminal Q of the slave latch 124.
The normal mode of operation for the test block shown in FIG. 2, requires a low signal on the scan control line 103. With a low signal on the line 103, the output signal of AND gate 121 on the line 106 is always low, and the signal from the inverter on the second input terminal of the AND gate 120 is high. If the signal on input line 100 to AND gate 120 is high, the output signal on line 105 is high, but if the signal on line 100 is low, the signal on line 105 is also low. Thus, the signal on the line 105 follows the signal on the primary input line 100.
The output signal of the OR gate 122 on line 107 follows the signal on the input line 105 because the signal on the other input line 106 to the OR gate 122 is low in the normal mode of operation. Therefore, since the signal of the line 105 follows the signal on the input line 100, the signal on line 107 follows the signal on the input line 100, i.e., the primary input signal is applied to the input terminal D of the master latch 123 in the normal mode of operation.
To pass the input signal on line 107 through the master slave flip-flop 125 to the output line 111, a clock signal is provided on line 104. The signal on line 107 is then passed through the flip-flop 125 to the output line 111. Thus, the user of a circuit which contains this test block must provide a sequence of clock signals to the flip-flop 125 which coincide with the signals on line 100 so that the circuit will function normally. Further, the test block also degrades the circuit's normal performance because it introduces additional delays associated with the switching of the master slave flip-flop 125.
To perform a scan test with the test block 10' of FIG. 2, a high signal is applied on the scan control line 103. This places the test block in the scan mode. In this mode, any signal applied on line 102 is present on the input line 107 of the master latch 123 and when a clock pulse is provided on line 104 the input signal is loaded into the flip-flop 125 and available on the output line 111. After this seqeunce of operations the test block is in the test mode because a known test signal is available on the output line 111 which is connected to an input line of the logic circuit under test. To determine the results of applying a known input signal to the logic circuit under test the logic circuit is given time to stabilize and then the data receive mode is used.
In the data receive mode, the high logic signal on the scan control line 103 is switched to a low logic level. As described previously, for a low signal on the scan control line 103, the signal on the input line 100 is applied to the input terminal D of the master latch 123. Thus, if the line 100 is connected to the output line of a logic circuit under test, the output signal is available to the input terminal D of the master latch. Application of a clock pulse on the clock input line 104 stores the test output signal in the flip-flop 125.
Next the signal on the scan control line 103 is again switched to a high signal, and a sequence of clock pulses is applied to shift the stored test signals out of the shift register 45 comprised of the interconnected test blocks, as shown in FIG. 1.
The implementation of this prior art scan technique requires that the flip-flops in the each test block remain in the normal signal path of the combinational logic circuit network even after the test is completed. The extra circuitry introduces timing delays as well as the need for clock pulses to pass the normal circuit logic signal through the latches.
While other prior art test blocks are used in scan testing, these other block tests also require that the normal combinational logic circuit output signals pass through one or more flip-flops before the signals are availale to the next portion of the combinational logic circuitry. This requires sequencing of one or more clock pulses to the flip-flops during normal operation of the combinational logic circuitry. The user must not only understand the general logic circuit but also the interaction of the test blocks with the circuits. A malfunction of the flip-flop in a test block under normal operation will directly affect the output signal from the combinational logic circuitry.
Another prior art system 150 for scan testing of logic circuits is shown in FIG. 3. The normal output lines 180 from the logic circuit under test are a first set of input lines to a multiplexer 191. The multiplexer output lines 184 are the input lines to a group of output registers 192 controlled by line 187. The output lines 185 from the output registers 192 are the output lines for the logic circuit. The lines 186 are connected to the output lines 185 and to the inputs of the scan register 190. The scan register 190 also has a clock input line 181, scan-in line 182, a mode control input line 183, a scan-out output line 193, and a set of output lines 188, which are a second set of input lines to the multiplexer 191. The scan register 190 is basically a register with shift capability. The mode control input line 183 is also connected to the multiplexer 191.
This system has some advantages over the other prior art scan testing systems because the normal signal path through this system requires only that the signal on the mode control line be set so that the multiplexer passes the signals on the input lines 180 to the output lines 184. Hence, the user is not required to sequence clock pulses with the normal signals from the logic circuit under test to pass the normal logic circuit signals through the scan testing system. Also, a test vector may be loaded into the scan register while the normal signals from the circuit are passed through the scan system.
However, this system requires additional hardware and the system still permits only a high degree of fault coverage. Therefore, the prior art scan testing systems while assisting in determining the functionality of a logic circuit are difficult for the user to use and introduce additional failure modes which may not easily be checked or verified by the user.
USPTO Backgrounds
USPTO Backgrounds