1. Field of the Invention
This application relates to non-volatile semiconductor memory devices and, more particularly, to methods of discharging an erase voltage of a semiconductor memory device and semiconductor memory devices performing the methods.
2. Description of the Related Art
Semiconductor memory devices which are capable of electrically erasing or programming data stored therein without refreshing the data are required. Accordingly, studies on increasing the storage capacity and the degree of integration of semiconductor memory devices are underway. An example of a non-volatile semiconductor memory which provides both high capacity and high integration without refreshing the stored data is a NAND flash memory device.
Since NAND flash memory devices retain stored data when power is turned off, NAND flash memory devices are widely used for mobile terminals, notebook computers, etc. However, NAND flash memory devices need to discharge an erase voltage after erasing data.
A NAND flash memory device has a cell array including NAND strings. Each NAND string includes a series of cell transistors serially connected to each other. Specifically, each NAND string includes a first selection transistor, a plurality of cell transistors, and a second selection transistor serially connected to each other. The drain of the first selection transistor is connected to a corresponding bit line. Generally, all NAND strings in a column of the cell array share the same bit line. The second selection transistor has a source connected to a common source line (CSL) for a sector including the NAND string. The operation of discharging the NAND flash memory device can be performed in a discharge circuit for performing the discharge operation connected to the CSL.
FIG. 1 is a circuit diagram of a discharge circuit 100 of a conventional NAND flash memory device.
Referring to FIG. 1, the discharge circuit 100 includes a first node 106 connected to a CSL; a first high-voltage depletion transistor H1 connected between the first node 106 and a second node 108; a resistor R, a second high-voltage depletion transistor H2, and a first NMOS transistor N1 which are connected in series between the first node 106 and a ground voltage; a PMOS transistor P1 and a third high-voltage depletion transistor H3 which are connected in series between a supply voltage and the second node 108; and a second NMOS transistor N2 connected between the second node 108 and the ground voltage. The gates of the first and second high-voltage depletion transistors H1 and H2 are connected to the supply voltage and the gate of the third high-voltage depletion transistor H3 is connected to the ground voltage.
A program control signal 110 is applied to the gate of the PMOS transistor P1. The program control signal 110, a control signal applied when data is programmed to a memory cell, acts to apply a voltage lower than the supply voltage to the CSL. Accordingly, by setting the CSL to 1.2 V, it is possible to prevent coupling when data is programmed to a memory cell.
The first and second high-voltage depletion transistors H1 and H2 are used for protecting the first and second NMOS transistor N1 and N2, and the third high-voltage depletion transistor H3 is used for protecting the PMOS transistor P1.
A first discharge control signal 112 is applied to the gate of the first NMOS transistor N1 and a second discharge control signal 114 is applied to the gate of the second NMOS transistor N2.
The CSL shown in FIG. 1 is connected in common to NAND strings of NAND memory cells connected in series to each other in the NAND flash memory device not shown in FIG. 1.
FIG. 2 is a timing diagram of the first and second discharge control signals 112 and 114 shown in FIG. 1.
The operation of the conventional discharge circuit 100 will be described with reference to FIGS. 1 and 2.
When the NAND flash memory device programs memory cells, the CSL voltage is set to about 1.2 V. When the NAND flash memory device reads data from memory cells, the CSL voltage is set to 0 V. Also, when the NAND flash memory device erases data of the memory cells, the CSL voltage is set to a high voltage of about 20 V. Accordingly, after an erase operation is completed, the CSL must be discharged.
The conventional discharge method performs a second discharge when a predetermined time T elapses after a first discharge is performed through a resistor path.
As illustrated in FIG. 2, after data is completely erased, the first discharge control signal transits to logic ‘high’, and the second discharge control signal transits to logic ‘high’ after a predetermined time T elapses.
Referring to FIG. 1, if the first discharge control signal 112 transits to logic ‘high’, the first NMOS transistor N1 is turned on and the CSL is discharged through a first path 102 including the resistor R.
In the conventional discharge method, the timing relationship between a first discharge and a secondary discharge is set in advance. Therefore, if an erase time (tERS) is reduced, it is difficult to correctly decide on a restore time.
USPTO Backgrounds
USPTO Backgrounds