The present invention relates generally to electronic circuits, and more particularly, to circuits capable of controlling a quiescent current in a communication device.
Line drivers have been generally used in communication systems such as digital subscriber line (DSL) systems, for example, for delivering signal power to a remote terminal over a twisted-pair line. For example in association with a modem at an asymmetric digital subscriber line (ADSL) customer-premises equipment (CPE) side, a line driver may be used to deliver signal power of approximately 13 dbm (decibel milliwatt) over the line within a frequency band in the range of 20 KHz (Hertz) to 300 KHz. Furthermore, the line driver may be required to process signals of relatively high peak power with minimum distortion so as to meet the bit error ratio (BER) requirements in a DSL system.
To support high-power, high-frequency applications, such as in a DSL communication system, a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor may be used to serve as a push-pull output stage in a communication circuit. The push-pull transistor pair, in particular the PMOS transistor due to its relatively low mobility, may have a relatively large size in order to drive a low resistive load. Such a large size may disadvantageously result in large parasitic capacitive loads between the push-pull transistor pair and a previous stage such as a pre-drive stage. In some applications, such as high speed line drivers in communication circuits where a large output swing in frequency over several mega Hertz may be needed, a peak current through the parasitic capacitive load can reach several milliamperes (mA). Therefore, a pair of operational transconductance amplifiers (OTAs) with good current driving capability may be employed to drive the output-stage PMOS and NMOS transistors, respectively. The use of a pair of OTAs in a pre-drive stage has been discussed in a paper entitled “A High Performance CMOS Power Amplifier” by J. A Fisher, IEEE J. Solid-State Circuits, vol. SC-20, pp. 70-75, December 1985. An issue with such an OTA-pair circuit structure may lie in that quiescent current becomes hard to control. Various studies have tried to resolve the issue of quiescent current control. An example may be found in “A CMOS Line Driver for ADSL Central Office Applications” by A. Bicakci et al., IEEE J. Solid-State Circuits, pp. 2201-2208, December 2003, in which an additional digital-to-analog converter (DAC) is used for offset calibration.
FIG. 1 is a schematic diagram of a circuit 10 including an offset calibration device. Referring to FIG. 1, the circuit 10 may include an input stage, a pre-drive stage, an output stage and an offset calibration device 13. The input stage may include an operational transconductance amplifier (OTA) 11, which receives an input voltage signal Vin at a positive or non-inverting terminal and provides an output voltage signal Vip2 at another positive terminal. The pre-drive stage may include a first OTA 12-1 and a second OTA 12-2, each of which includes a positive terminal coupled with the output Vip2. The output stage may include a PMOS transistor labeled MP and an NMOS transistor labeled MN, which together form a push-pull pair. The PMOS transistor MP includes a gate terminal coupled to a negative or inverting terminal of the first OTA 12-1 and biased at a voltage Vgp from the negative terminal. The NMOS transistor MN includes a gate terminal coupled to a negative terminal of the second OTA 12-2 and biased at a voltage Vgn from the negative terminal. The offset calibration device 13, based on the voltages Vgp and Vgn, may provide a feedback voltage to the positive terminals of the first OTA 12-1 and the second OTA 12-2 for offset calibration. In operation, an output voltage Vout of the output stage increases as Vgp or Vgn decreases, and decreases as Vgp or Vgn increases. However, the circuit 10 may lose control of quiescent current if the voltages Vgp and Vgn, which are independent of one another, go in opposite directions. For example, Vgp may go up toward a power rail voltage while Vgn may go down toward a ground voltage, or vice versa, depending on the offsets inside the OTAs 12-1 and 12-2. With the increasing demands for higher data rate and wider bandwidth, the circuit 10 may be not suitable for high-power and high-frequency applications and may not meet the requirements for relatively high linearity in, for example, a very high data rate DSL (VDSL) communication system.
It may be desirable to have a circuit that is able to address the issue of quiescent current control in a communication device. It may also be desirable to have a circuit that is able to provide a robust quiescent current control without interfering with the operation of a pre-drive stage.
USPTO Backgrounds
USPTO Backgrounds