1. Technical Field of the Invention
The present invention relates generally to an arithmetic apparatus which may be built in a digital signal processor for fixed-point arithmetic operations, and more particularly to an improved arithmetic apparatus which is designed to perform an overflow correction in double precision and/or to perform parallel arithmetic operations with high accuracy.
2. Background Art
In recent years, digital signal processors have been widely used in digital portable telephones, for example. Such built-in type digital signal processors usually have an arithmetic logic unit for a fixed-point arithmetic operation from the standpoint of economic production costs.
In a fixed-point arithmetic operation unit, a decimal point is often placed on the right of a number to be displayed for handling the number as an integer. In addition, when the results of an arithmetic operation overflow, an overflow correction is carried out to correct it to either a positive maximum value or a negative minimum value according to a direction of the overflow.
An overflow correction in a conventional arithmetic apparatus will be described below with reference to FIG. 9.
The conventional arithmetic apparatus includes generally N-bit data storage memories 1 and 2, an arithmetic logic unit (ALU) 5, buses 3 and 4 for transmitting data stored in the memories 1 and 2 to the ALU 5 respectively, an overflow-detection circuit 6, a carry flag register 7, a maximum/minimum value-setting circuit 8, and operation result-storage registers 9 and 10.
The overflow-detection circuit 6 is connected to the ALU 5 and includes a circuit structure, as shown in FIG. 10, which outputs a carry from the highest-order position in the ALU 5 as an overflow sign signal 12 (a "0" denotes a positive value and a "1" denotes a negative value) and also provides as an overflow-detection signal 11 a "0" signal when a carry value of the number at the highest-order position agrees with a carry value from the next right position and a "1" signal when disagreement is established.
The carry flag register 7 is arranged to store a carry occurring in the most significant bit of the lower-order positions in a double precision arithmetic operation.
The maximum/minimum value-setting circuit 8, as shown in FIG. 11, includes a maximum/minimum value-outputting element and a multiplexer. The maximum/minimum value-outputting element is designed to provide a negative minimum value "10000 . . . " when the overflow sign signal 12 shows a negative value (1) and a positive maximum value "01111 . . . " when the overflow sign signal 12 is a positive value (0). The multiplexer serves as a switching means which is responsive to the overflow-detection signal 11 of 0 to produce the output from the ALU 5 as is, while it provides the output from the maximum/minimum value-outputting element when the overflow-detection signal 11 is a 1. The registers 9 and 10 store therein the outputs from the maximum/minimum value-setting circuit 8.
Assume that the number of bits N of data in the memories 1 and 2, the buses 3 and 4, the ALU 5, and the registers 9 and 10 is sixteen (16). In the double precision arithmetic operation, an addition or subtraction is carried out twice for handling 32 (=2N) bit data transmitted from the buses 3 and 4, respectively.
A positive maximum value formed with 16 bits may be expressed in 2's complement form as "7 f f f", while a negative minimum may similarly be expressed as "8000". Thus, the maximum/minimum value-setting circuit 8 provides the positive maximum value "7 f f f" when the overflow-detection signal 11 is active (1) and the overflow sign signal 12 is positive (0), and the negative minimum value "8000" when the overflow-detection signal 11 is active and the overflow sign signal 12 is negative (1).
Hereinafter, addition or subtraction operations of double precision data X and Y (2N=32 bits) will be discussed.
Addition or Subtraction of lower-order bits of both the data X and Y
Data XL formed with 16 lower-order bits of the data X is first read out of the memory 1 to output it to the bus 3. Similarly, from the memory 2, data YL formed with 16 lower-order bits of the data Y is read to output it to the bus 4. The ALU 5 performs an addition or subtraction operation of the data XL and YL and stores resultant data in the register 10 through the maximum/minimum value-setting circuit 8. In addition, a carry produced at the highest-order position is stored in the carry flag register 7. The maximum/minimum value-setting circuit 8 then transfers the output from the ALU 5 to the register 10.
Addition or Subtraction of higher-order bits of both the data X and Y
Data XU defined by 16 higher-order bits of the data X is first read out of the memory 1 to output it to the bus 3. Next, data YU defined by 16 higher-order bits of the data Y is read out of the memory 2 to output it to the bus 4. The ALU 5 performs an addition or subtraction operation of the data XU and YU and a value of the carry flag register 7, and stores results thereof in the register 9 through the maximum/minimum value-setting circuit 8.
The overflow-detection circuit 6, when the results of the arithmetic operations in the ALU 5 overflow, provides the overflow-detection signal 11 and the overflow sign signal 12 indicative of a direction of the overflow. The maximum/minimum value-setting circuit 8, when the overflow-detection signal 11 is active (1) and the overflow sign signal 12 is positive (0), provides the positive maximum value "7 f f f" in 2's complement form, while it outputs the negative minimum value "8000" in 2's complement form when the overflow-detection signal 11 is active and the overflow sign signal 12 is negative. Further, it provides the output from the ALU 5 as is when the overflow-detection signal 11 is not active (0).
With the above two-step arithmetic operations, the addition and subtraction of the double precision data are performed. The results of the arithmetic operation of the 16 lower-order bits are stored in the register 10, while the results of the 16 higher-order bits are stored in the register 9.
The above conventional arithmetic apparatus, however, has suffered from a drawback in that the data formed with the 16 lower-order bits of the 32-bit operation results is not corrected even if overflow occurs, so that the 32-bit operation results are not corrected to either a 32-bit positive maximum value or a 32-bit negative minimum value.
Further, in recent years, for error correction in digital communication, a convolution code has become used frequently. For decoding the convolution code, the Viterbi decoding process is useful. The Viterbi decoding is accomplished by repeating the so-called addition comparison selection (ACS) arithmetic operation. The ACS arithmetic operation is a process wherein addition is performed twice and two results of the addition are compared in number size to select either of them. The repetition of the ACS arithmetic operation thus consumes considerable time until the Viterbi decoding has been completed.
USPTO Backgrounds
USPTO Backgrounds