1. Field of the Invention
The present invention relates generally to semiconductor processing. More specifically, the present invention relates to a structure and method for forming an integrated circuit device having a multilayer interlayer dielectric structure.
2. Description of Related Art
During manufacturing of a semiconductor integrated circuit, electrically conductive materials patterned in electrical circuitry are layered over a base transistor structure that is disposed on a semiconductor substrate. The electrically conductive materials (e.g., copper) are in different and noncontiguous planes. Vias or pathways connect the various layers of electrically conductive materials. An insulator or dielectric material is placed between the separate planes of conductive material around the vias and also within the trenches in the circuit pattern of a layer of conductive material. Vias are usually formed as landed vias (i.e., the via rests entirely on a conductive layer) and not as unlanded vias (i.e., the via rests partially on a conductive layer and partially on an insulator). In addition, the typical insulator used is silicon dioxide, which has a dielectric constant (K) of about 4. Because better device performance can be achieved with lower capacitance between conductive lines within an insulating layer, the trend is to use insulators with a lower dielectric constant, such as an organic polymer.
FIGS. 1A-1D illustrate a related art method of forming landed vias. In FIG. 1A, a first conductive material 103 (e.g., aluminum) is deposited over silicon dioxide 101, which is disposed over a silicon substrate 100. An organic polymer 105 is surrounded on its side surfaces by conductive material 103 and silicon dioxide 107. The top surface of silicon dioxide 107 and organic polymer 105 are covered by a silicon nitride layer 109. In earlier steps (not shown), the silicon dioxide layer 107 and the conductive material 103 were etched to form an opening that was filled with polymer 105. In FIG. 1B, another layer of silicon dioxide 111 and a photoresist layer 113 are deposited over the structures shown in FIG. 1A.
In FIG. 1C, the photoresist layer is patterned to form a landed via 115. Silicon dioxide layer 111, nitride layer 109 and silicon dioxide layer 107 are etched to form two landed vias 115. Landed via 115 rests entirely over conductive material 103. The next step, as shown in FIG. 1D, is to remove photoresist layer 113. A second conductive material is formed in landed via 115 and then planarized to form conductive structure 117. The second conductive material can be tungsten or any other applicable metal. Thus, FIGS. 1A-1D illustrate a related art method of forming landed vias.
The industry trend is moving toward unlanded vias instead of landed vias because of the need for increased packing density. The semiconductor industry is also moving toward using organic polymers, which have a lower dielectric constant than silicon dioxide, in order to decrease the capacitance of the interconnection system. FIGS. 2A-2B illustrate how the related art method of FIGS. 1A-1D fails to produce a reliable unlanded via in the presence of an organic polymer. FIG. 2A illustrates a structure similar to FIG. 1C except that an unlanded via 216 is formed partially over conductive metal or layer 203 and partially over polymer 205. Photoresist layer 213 has been patterned and silicon dioxide layer 211, nitride layer 209 and polymer 205 have been etched during the formation of unlanded via 216.
In FIG. 2B, photoresist layer 213 is removed using oxygen (O.sub.2) plasma. The polymer 205 is not protected from the oxygen plasma during the photoresist layer 213 strip and removal. As a result, a substantial amount of polymer 205 is eroded or destroyed by the oxygen plasma since polymer 205 is an organic material like the photoresist 213. Therefore, the oxygen plasma also etches the polymer 205 during the etch and removal of the photoresist layer 213. The result is an unlanded via 217 with an undesirable undercut. If polymer 205 is exposed to the oxygen plasma for a sufficiently long period, all of the polymer 205 will be removed. The overetch of the polymer 205 causes reliability problems and device failure. Thus, the related art method illustrated in FIGS. 1A-1D cannot be used to form an unlanded via in the presence of a low dielectric constant material, such as an organic polymer.
USPTO Backgrounds
USPTO Backgrounds