1. Field of the Invention
The present invention relates generally to non-volatile memory (NVM) devices. More particularly, the present invention relates to a single polycrystalline silicon (single-poly) NVM cell.
2. Description of the Prior Art
Nonvolatile memory (NVM) devices are well known in the art. A NVM device does not lose its data when the system or device is turned off. As the demand for small size portable electrical devices such as cellular phones increases, there is a great need of the embedded memory for logic circuits and system on a chip. High-performance embedded memory is a key component in VLSI or ULSI because of its high-speed and wide bus-width capability, which eliminates inter-chip communication. A NVM device, which is fully compatible with CMOS logic processes and has low power consumption, improved writing efficiency, low cost and high packing density is highly desirable.
A NVM device typically comprises a MOS transistor having a source, a drain, a floating gate, and a control gate. Electrons may be transferred from the floating gate to the substrate by tunneling through a thin silicon dioxide layer. Tunneling is the process by which an NVM can be either erased or programmed. Storage of the charge on the floating gate allows the threshold voltage to be electrically altered between a low and a high value to represent logic 0 and 1, respectively. In floating gate memory devices, charge or data is stored in the floating gate and is retained when the power is removed.
To embed memory cells into a standard logic process without changing the single-poly process typically used in the fabrication of the logic circuitry, the single-poly memory scheme has been developed. The prior art single-poly memory cell typically includes N+ source and N+ drain regions formed in a P-type substrate and a polycrystalline silicon gate overlying a channel region extending between the source and drain regions. An N-type diffusion region formed in the P-type substrate serves as the control gate and is capacitively coupled to a floating gate via a thin gate oxide layer. The single-poly memory cell may be programmed by electron-tunneling from the floating gate to the substrate.
Although compatible with standard CMOS fabrication, conventional single-poly NVM suffers from high-voltage operation, slow programming, and incapability of electrical erase.
U.S. Patent Pub. No. 2009/0201742 A1 discloses a single-poly NVM cell that can be programmed and erased with low operation voltages. The single-poly NVM cell includes a programming charge coupling MOS capacitor formed in a first P well and a storage MOS transistor formed in a second P well. The first and second P wells are formed in a deep N well in a P-type substrate. The programming charge coupling MOS capacitor comprises N+ source and N+ drain regions, and a program-coupling floating gate that is electrically connected to a charge-storage floating gate of the storage MOS transistor to form a floating gate node. The N+ source and N+ drain regions and the first P well of the programming charge coupling MOS capacitor are commonly connected to a well biasing voltage. However, to establish a large coupling ratio, the physical size of the MOS capacitor is approximately 10 times greater than that of the storage MOS transistor.
As the size of memory cells shrinks, the capacitance area between the floating gate and the control gate shrinks as well. As a result, the drive current and/or coupling ratio are usually insufficient to effectively perform operations such as programming, erasing and reading. Therefore, there is a need in this industry to provide a single-poly NVM cell with high coupling ratio suited for deep sub-micron dimensions, preferably 65 nm technology nodes and beyond, which does not exhibit the above-mentioned problems.
USPTO Backgrounds
USPTO Backgrounds