This invention relates generally to the fabrication of semiconductor devices and specifically to deposition techniques.
Incompatibilities between the metal and oxide layers in Metal-Oxide-Semiconductor or Metal-Oxide-Silicon (MOS) structures may arise in those MOS structures having a dielectric with a high dielectric constant (high-k) and a polysilicon or metal gate electrode. For example, a MOS structure having a high-k dielectric and a polysilicon gate electrode may form nodules that may short the dielectric. Further, the nodules may pin the Fermi level in the polysilicon gate. Alternately, a MOS structure having a high-k dielectric and a metal gate electrode may experience an undesirable shift in the gate metal work function. A shift in work function may lead to unstable threshold voltages thereby affecting device performance. As such, another oxide such as a buffer oxide may be deposited between the high-k dielectric and gate material.
Buffer oxides may be deposited on a substrate via chemical vapor deposition (CVD) processing techniques. For example, deposition precursors may first be deposited on the substrate and then oxidized. However, some of the precursors used in the CVD of buffer oxide may be highly toxic and may spontaneously ignite and burn on contact with air. Thus, the CVD buffer oxide precursors pose a significant risk to those working in the semiconductor industry. Further, unconsumed CVD process gases and deposition products may be as toxic as the starting materials. Thus, there is an additional hazard to the environment at large as a result of CVD of buffer oxide.
Accordingly, there continues to be a need for deposition techniques that are both environmentally and user friendly.
USPTO Backgrounds
USPTO Backgrounds