1. Field of Invention
Embodiments of the invention generally relate to graphics systems, and in particular to display controllers employed in graphics processing systems.
2. Discussion of Related Art
Display controllers are often used in computer systems to output 2D or 3D images to a display monitor. In general, the display controller is included in graphics processing systems.
FIG. 1, illustrates an example of a system 10 including a set 11 of processing units 1, 2 . . . N, a memory unit 12 and a graphics processing system 13 used to generate images for display on a display device 14 (e.g., screen, display, monitor, etc.). The system 10 may also include a bus 15 that interconnects various elements of the system 10. The graphics processing system 13 may receive instructions from an application running on at least one of the processing units 11 to generate a virtual image or to process graphics or video data for display on the display device 14. The graphics processing system 13 may be used to display images on more than one display device and each of the devices may be of different types (TV, wall, monitor, etc). In some embodiments, one or more of the display devices may be included in a video processing system. In a version of these embodiments, the video processing system may include a video recorder and/or monitor. In some embodiments, the processing units 11 may include a host processor (commonly referred to as a CPU). System 10 may also include dedicated processing units such as a video editing processor and/or an image processing unit among the set of processing units 11.
As illustrated in FIG. 1, a graphics processing system 13 may include an interface 21, a graphics processor 22, a frame buffer 23, a display controller 24 and an output port 25. The frame buffer may be external to the graphics processing system 13. The frame buffer 23 may store instructions and data sent by an application running on one of the plurality of processing units 11. Further the frame buffer may store the processed data while it is being processed in the graphics processor or once its processing is completed. In general, the interface 21 is used to connect the graphics processing system 13 to the processing units 11 and the memory 12 through the bus 15. The graphics processor 22 may receive data and instructions through the interface 21. Once processed, data is stored in the frame buffer 23 and is output by the display controller 24 to the display device 14. The display controller 24 may be configured by a driver to output data from the frame buffer 23 through the output port 25 according to the monitor's parameters (e.g., device resolution, refresh rate, etc.). These parameters may be defined at an initialization step, when the system 10 is switched on, or they may be defined by a user at any moment during the system's run time.
In general, display controllers run in a continuous mode and generate data at a preset refresh rate. The refresh rate is the rate at which the display monitor may display data. The refresh rate may be either automatically set by the system 10 according to the monitor's characteristics, or according to parameters defined by the user. A variety of methods, known in the art, may be used to set up the refresh rate and to allow the user to define a refresh rate corresponding to the display monitor connected to the system and the desired display resolution.
Although graphics processing systems are customarily designed to display images on a monitor, current computer systems may use a graphics processing system to perform a variety of tasks. Video editing or image processing are examples of applications for which a standard graphics processor may be used. As an example, a graphics processing system may be used in combination with a video editing system to mix 3D graphics characters to a video scene.
Traditional approaches in which the display controller operates in a continuous mode were sufficient for historical uses of display controllers but are not suitable for some current applications. For example, the incorporation of a 3D character in a movie scene should be synchronized to other sources and mixed to a video stream when the video editing application requests it. These requirements are often incompatible with a continuous output of data, e.g., at a constant refresh rate.
Accordingly, some prior approaches have attempted to output processed data from a graphics processing system upon receipt of an output request. In one approach, the interface 21 is used. In this approach, an application sends data to be processed by the graphics processing system via the interface 21. The application also receives the processed data from the system via the interface 21. That is, data returns through the interface 21. This approach however, uses a lot of bandwidth on the bus 15 which connects the graphics processing system to the external processors. Further, this approach may prevent the graphics processing system from processing new data while it is outputting data through the interface. As a result, the graphics processing system operates inefficiently because it is employed outputting data during periods when it might otherwise be processing data.
In another approach a continuous stream of data is communicated from the output port of the graphics processing system to the application at a predetermined refresh rate. The application then extracts relevant data from the data-stream. For example, a dedicated hardware module may receive the data in a continuous mode and store and transfer the data to the processor requesting it at a different rate or frame-by-frame upon request. However, such an approach requires the addition of the dedicated hardware module in addition to the display controller and other components of the graphics processing system.
Currently, display controllers are often equipped with a control unit such as a cathode ray tube controller (“CRTC”). The control unit may contain various counters that are used to control the output of an image and to generate the timing signals that the display devices require. One example of a signal generated by the control unit is the horizontal synchronization signal (“hsync”). In one embodiment, the hsync signal indicates to the display device that it should move its displaying position to the next line. Another example is the vertical synchronization signal (“vsync”). In one embodiment, the vsync signal is used to indicate to the display device that it should move its displaying position to the first line. In general, the control unit employs horizontal and vertical counters that can increment periodically and compares the values of the counters to one or more registers to know when to restart at zero for a new frame and when to toggle the state of different control signals.
The control unit may generate a plurality of signals that are used to control the display of data. FIG. 2 illustrates an example of an embodiment of a control unit that may generate one of these signals, e.g., the hsync signal. The control unit includes a horizontal signal counter 46 which is associated with the generation of the hsync signal.
The horizontal signal counter 46 increments at each clock cycle in accordance with the illustrated embodiment. In the illustrated embodiment, the control unit also includes a plurality of horizontal registers 47A-47C, for example, the registers hsyncstr (i.e., horizontal synchronization start) and hsyncend (i.e., horizontal synchronization end). In accordance with one embodiment, the control unit includes a plurality of comparators 48A-48C that are employed to perform a comparison between the value in one or more of the plurality of horizontal registers and the value of the horizontal signal counter 46. The horizontal registers 47A-47C each contain a separate value that is compared to the value of the horizontal signal counter 46, for example, at each clock cycle. In accordance with one embodiment, each time the value in the hsyncstr register 47A equals the value of the horizontal signal counter 46, the signal hsync is activated. Further, each time the value in the hsyncend register equals the value of the horizontal signal counter 46 the signal hsync is deactivated. The example provided by FIG. 2 illustrates the generation of one control signal employed by the display device, i.e., the horizontal sync signal for the generation of the horizontal pixels (e.g., lines) of an image. Typically, the control unit generates additional control signals associated with the illustrated counters and may include additional counters associated with the generation of the additional control signals, for example, a vertical counter.
Further, the control unit may include a preload register 49 that is employed to initialize the horizontal signal counter at a desired value. As illustrated in FIG. 2, the horizontal signal counter 46 may receive the trigger signal (e.g., a video reset signal, “vidrst”) which is employed to trigger an upload of the value of the preload register 49 to the horizontal signal counter 46.
In a further embodiment, the control unit may include an htotal register 47C among the horizontal registers. In the illustrated embodiment, comparator 48C is employed to compare the value of the htotal register 47C with the horizontal counter 46. In one embodiment, the horizontal counter 46 is reset to a starting value (for example, zero) when the output of the comparator 48C supplies a restart signal to the horizontal counter 46 as a result of the comparison of the value of the htotal register 47C and the horizontal counter 46.
Thus, a traditional graphics processing system including a traditional display controller generally operates to process and output a frame of image data in response to a request for the graphics processing system to process the data. Further, this data continues to be output until the graphics processing system receives a subsequent request.
USPTO Backgrounds
USPTO Backgrounds