The inventive subject matter relates to semiconductor devices and, more particularly, to non-volatile memory devices.
It is generally desirable for a NAND flash memory device for a mobile product to have low power consumption. To this end, it may be desirable for a cell transistor used in the NAND flash memory device to have a low operating voltage. However, increasing the integration level of the cell transistor may cause a short channel effect.
Conventional techniques for obtaining a sufficient amount of cell current adjusting a cell Vth implant in a gate region and an LDD implant in a source/drain region. In a 20 nm cell array structure, however, accurate implant adjustment may be difficult to achieve, which may make it difficult to obtain a cell current level sufficient to meet product performance requirements. In addition, there may be an increasing difference in the cell current level between cell transistors.
USPTO Backgrounds
USPTO Backgrounds