Recently, so-called build-up multilayer wiring board are in demand or high densification of multilayer wiring boards. This build-up multilayer wiring board is produced, for example, by a method as described in JP-B-4-55555. That is, an insulating agent composed of a photosensitive adhesive for electroless plating is applied onto a core substrate, dried, exposed to a light and developed to form an interlaminar insulating resin layer having openings for viaholes, and then the surface of the interlaminar insulating resin layer is roughened by treating with an oxidizing agent or the like, and a plating resist is formed on the roughened surface, and thereafter a non-forming portion of the plating resist is subjected to an electroless plating to form viaholes and conductor circuits, and then such steps are repeated plural times to obtain a build-up multilayer wiring board.
However, in the thus obtained multilayer printed circuit board, the conductor circuit is formed on the non-forming portion of the plating resist and the plating resist remains in the inner layer as it was.
Therefore, if IC chips are mounted on such a wiring board, there is a problem that warping of the board is caused by a difference of thermal expansion coefficient between IC chip and the insulating resin layer in the heat cycle to concentrate stress into a boundary portion between the plating resist and the conductor circuit due to poor adhesion property therebetween and hence cracks are generated in the interlaminar insulating layer contacting with the boundary portion.
As a technique capable of solving this problem, there is a method of removing the plating resist retained in the inner layer and forming a roughened layer on the surface of the conductor circuit to provide an adhesion to the interlaminar insulating layer. For example, JP-A-6-283860 discloses a technique of removing the plating resist in the inner layer and providing a roughened layer of copper-nickel-phosphorus on the surface of the conductor circuit composed of an electroless plated film to prevent interlaminar peeling.
In the invention of JP-A-6-283860, however, there is no understanding about cracks caused when the heat cycle test is actually carried out after the mounting of IC chips, and only a conductor circuit composed of only an electroless plated film is disclosed. Moreover, when a supplementary test of the heat cycle at −55° C.-+125° C. is carried out (see Comparative Example 1 as mentioned later), cracking is not observed in about 1000 cycles, but when the cycle number exceeds 1000 cycles, cracking is observed.
As another technique capable of solving the above problem, there is considered a method of adopting so-called semi-additive process to remove the plating resist. In the semi-additive process, however, the conductor circuit is comprised of an electroless plated film and an electrolytic plated film, so that there is a problem that when the surface of the insulating resin layer is subjected to a roughening treatment, a surface portion composed of the electrolytic plated film of the conductor circuit is dissolved by the local electrode reaction.
On the other hand, in order to mount IC chips on the printed circuit board, it is necessary to form a solder bump on the circuit board. As a method of forming the solder bump, there has hitherto been adopted a method wherein an alignment mark composed of a conductor layer is previously formed on a mask for printing such as a metal mask, a plastic mask or the like and a printed circuit board in order to determine positioning of the mask for printing and the printed circuit board, and then both alignment marks are adjusted to each other to laminate the mask for printing on the printed circuit board at a given position, and thereafter a cream solder is printed thereon. In this case, a solder resist layer opening a portion of the alignment mark or the pad for solder bump formation is formed on the printed circuit board.
Therefore, if IC chips are mounted on such a printed circuit board, there is a problem that warping of the board is caused by a difference of thermal expansion coefficient between IC chip and the insulating resin layer in the heat cycle to concentrate stress in a boundary portion between the solder resist layer and the conductor layer (inclusive of the alignment mark and the pad for solder bump formation) due to the absence of adhesion therebetween and hence cracks are generated in the solder resist layer starting from the boundary portion and the solder resist is peeled off.
It is, therefore, an object of the invention to solve the aforementioned problems of the conventional technique.
It is a main object of the invention to provide a printed circuit board capable of effectively preventing cracks and interlaminar peeling of the interlaminar insulating layer created in the heat cycle without degrading other properties, particularly peel strength of conductor: (adhesion between a conductor circuit and an interlaminar insulating layer, adhesion between a viahole and an under layer conductor circuit, or adhesion between a conductor layer and a solder resist layer).
It is another object of the invention to provide a printed circuit board capable of preventing the dissolution of the surface of the conductor circuit through the local electrode reaction.
It is still another object of the invention to provide a method of advantageously producing such a printed circuit board.
USPTO Backgrounds
USPTO Backgrounds