1. Field of the Invention
The present invention relates to a conductive resin composition, a connection method between electrodes using the same, and an electric connection method between an electronic component and a circuit substrate using the same.
2. Description of Related Art
In recent years, due to an increase of density and an increase of integration of a semiconductor integrated circuit (LSI) that is used for electronic equipment, an increase in the number of pins and narrowing of a pitch of an electrode terminal of a LSI chip have proceeded rapidly. For packaging these LSI chips on circuit substrates, flip chip packaging is used widely in order decrease wiring delay. And, in this flip chip packaging, it is common that a solder bump is formed on an electrode terminal of the LSI chip, and is connected to a connection terminal formed on the circuit substrate via the solder bump in one piece.
However, in order to package a next-generation LSI with the number of electrode terminals of more than 5,000 on a circuit substrate, which becomes finer, it is necessary to form a bump that corresponds to a narrow pitch of 100 μm or less, but a current technique for forming a solder bump is difficult to adapt to it.
Moreover, since it is necessary to form a large number of bumps that correspond to the number of the electrode terminals, high productivity by shortening a mounted time of each chip also is required in order to reduce the cost.
Similarly, in the semiconductor integrated circuit, a peripheral electrode terminal is changed into an area-disposed electrode terminal with the increase of the electrode terminals. Moreover, due to the requirements for the increase of the density and the increase of the integration, a semiconductor process is expected to proceed from present 65 nm, and further to 45 nm, 32 nm.
As a result, the wiring becomes more finer, and a capacity between the wirings is increased, so that problems of an increase of a speed and a loss of power consumption become serious, and the demand for a decrease of a dielectric constant (Low-K) of an insulation film between wiring layers is increased further. Since such Low-K of the insulation film is realized by treating an insulation layer material to be porous, a mechanical strength thereof is low, which prevents a decrease of a thickness of the semiconductor.
In addition, when structuring the area-disposed electrode terminal as described above, there is a problem in strength on the porous film due to the Low-K, and since an electrode is needed on an active area of the semiconductor integrated circuit, it is difficult to form the bump on the area-disposed electrode and achieve the flip chip packaging itself. Thus, a low-load flip chip packaging method, which corresponds to the development of the semiconductor process in the future, and is suitable for a semiconductor with a small thickness and a high density, is demanded.
Conventionally, as a technique for forming a bump, a plating method, a screen printing method and the like are developed. The plating method is suitable for a narrow pitch, but requires complicated processes and results in a problem in productivity. On the other hand, the screen printing method has excellent productivity, but is not suitable for narrowing a pitch from the standpoint of using a mask.
In the light of the problems described above, several techniques for forming a solder bump selectively on an electrode of a LSI chip or a circuit substrate have been developed recently. These techniques not only are suitable for forming fine bumps, but also have excellent productivity because of enabling the formation of the bumps in a lump, which attract attention as techniques that can be applied to packaging of the next-generation LSI on the circuit substrate.
For example, in a technique described in Patent Document 1, a solder paste obtained by mixing conductive particles and flux is applied solidly onto a substrate having an electrode formed on a surface thereof, and the substrate is heated, whereby the conductive particles are melted so as to form a solder bump selectively on the electrode with high wettability.
Moreover, in the technique described in Patent Document 2, a paste-type composition (chemical reaction deposition-type solder) that contains an organic acid lead salt and metal tin as main components is applied solidly onto a substrate on which an electrode is formed, and the substrate is heated, whereby a substitution reaction between Pb and Sn is caused so as to deposit an alloy of Pb/Sn on the electrode of the substrate selectively.
By the way, the flip chip packaging using a conventional bump formation technique further requires a step of injecting a resin called an underfill between the semiconductor chip and the circuit substrate so as to fix a semiconductor chip on the circuit substrate, after mounting the semiconductor chip on the semiconductor substrate on which a bump is formed. Thus, after mounting the semiconductor chip on the circuit substrate and melting the solder bump so as to achieve an electric connection, a mechanical strength is low, and it is unstable until the underfill is cured completely.
Then, as a method for achieving an electric connection between the electrode terminals of the semiconductor chip and the circuit substrate that face to each other, and fixing the semiconductor chip onto the circuit substrate at the same time, a flip chip packaging technique (for example, see Patent Document 3) using an anisotropic conductive material is developed. This achieves the electric connection between the electrode terminals of the semiconductor chip and the circuit substrate and the fixation of the semiconductor chip onto the circuit substrate at the same time, by supplying a thermosetting resin containing conductive particles between the circuit substrate and the semiconductor chip so as to apply a pressure onto the semiconductor chip, and heating the thermosetting resin at the same time.
However, in the flip chip packaging using the anisotropic conductive material, since conduction between the facing electrode terminals is obtained by a mechanical contact between the conductive particles that are dispersed uniformly in the resin, the conductive particles that contribute the conduction between the electrode terminals are limited to a part of the conductive particles contained in the resin. Moreover, the reliable electric connection between the conductive material and the facing electrode terminal requires a certain load, and is not suitable for packaging the area-disposed semiconductor integrated circuit using the porous film (Low-K).
Further, since the conductive particles that do not contribute to the conduction between the facing electrode terminals also can be a factor that inhibits insulation between the adjacent electrode terminals, the flip chip packaging using the anisotropic conductive material has numerous problems to be solved in the light of the productivity and the reliability, for being applied to the next-generation LSI chip with the number of connection terminals of more than 5,000.
Further, for the purpose of preventing such conductive particles from being present between the adjacent electrode terminals, a method of melting and integrating solder particles that are dispersed uniformly and collecting them between the electrode terminals is suggested (for example, see Patent Document 4).
According to the present method, by disposing a conductive adhesive between facing terminals such as electrodes and heating it at a temperature that is higher than a melting point of the conductive particles and does not terminate the curing of the resin, the melted conductive particles assume a state of being spread.
Further, the conductive particles that are melted are in a “wetting state” on its terminal surfaces, and further, the conductive particles are arranged so as to be in contact with each other and expanded, so that the terminals are connected electrically.
[Patent Document 1] JP 2000-94179 A
[Patent Document 2] JP 1(1989)-157796 A
[Patent Document 3] JP 2000-332055 A
[Patent Document 4] JP 2004-260131 A
However, in the flip chip packaging using the anisotropic conductive material by the integration method of the melted conductive powders described above, by the physical contact of the conductive particles in which the melted conductive powders are dispersed uniformly in the resin, the respective conductive powders are integrated due to the wetting caused by the contact, and obtain the conduction between the facing electrode terminals, and thus, unless a large amount of the conductive particles that contribute to the conduction between the electrode terminals are present in the resin, the conduction cannot be obtained. That is, the melted conductive powders that are dispersed in the resin are required to be present so as to have a probability to be in contact with each other, and redundant conductive powders also are required to be added so as to obtain the conduction between the electrode terminals reliably.
Thus, also in the present method, only a part of the conductive particles contribute to the conduction. Moreover, the conductive particles that do not contribute to the conduction between the facing electrode terminals are present, which can be a factor in inhibiting the insulation between the adjacent electrode terminals.
That is, even the flip chip packaging using the anisotropic conductive material by the integration method of the melted conductive powders has numerous problems to be solved in the light of the reliability, for being applied to the next-generation LSI chip with the number of the connection terminals of more than 5,000.
USPTO Backgrounds
USPTO Backgrounds