The present invention relates generally to continuity testing and, in particular, to a method of testing for power and ground continuity of a semiconductor device.
Interconnection faults such as, for example, missing wire bonds, wire bond lifting, missing solder balls, and ball bond lifting are a source of package defects. Continuity testing is performed to identify and screen out semiconductor devices with interconnection faults. Conventional load boards, typically designed and fabricated for parametric and functional testing, are not suitable for power and ground continuity testing. Consequently, power and ground continuity testing is carried out using either modified or customized load boards. However, there are considerable costs associated with the use of such customized or modified load boards. Hence, it would be desirable to have a method of performing power and ground continuity testing for a semiconductor device using a conventional load board.
USPTO Backgrounds
USPTO Backgrounds