1. Field of the Invention
The present invention relates to a mask ROM (read only memory), more particularly, to a mask ROM for storing multi-valued data in each memory cell.
2. Description of the Related Art
As known in the art, the mask ROM is one of commonly used non-volatile memory devices. Differently from an EEPROM (Electrically Erasable Programmable ROM), data store on the mask ROM are not rewritable; data are programmed onto a mask ROM in the manufacture process.
Japanese Laid-Open Patent Application No. JP-A-Heisei, 10-22481 discloses a mask ROM in which data are stored as connections of aluminum interconnections integrated within memory cells. More specifically, each memory cell includes a MOS transistor integrated within a semiconductor substrate. Contact holes reaching the source and drain of the MOS transistor are formed through an interlayer dielectric film covering the MOS transistor, and the contact holes are filled with metal electrodes which reach the top surface of the interlayer dielectric film. In some memory cells, adjoining metal electrodes are connected to each other through an aluminum interconnection integrated within an interconnection layer on the interlayer dielectric film to provide a permanent electrical connection between the source and drain. A memory cell which includes such aluminum interconnection is defined as storing one of data “0” and “1”, and another memory cell which does not include such aluminum interconnection is defined as storing the other of data “0” and “1”.
One requirement for the mask ROM is reduction of the layout area (or the memory size). One approach for satisfying this requirement is to store three-value or more-value data (that is, multi-value data) onto each memory cell. Such mask ROM able to store multi-value data in each memory cell is referred to as “multi-valued mask ROM”, hereinafter.
Japanese Laid-Open Patent Application No. JP-A-Heisei, 9-232449 (the '440 application, hereinafter) discloses a multi-valued mask ROM in which memory cell transistors are arranged in rows and columns. To store four-value data (or two-bit data) in each memory cell transistor, the threshold voltage of the memory cell transistor is set to one of four allowed threshold voltage depending on data to be programmed. The adjustment of the threshold voltage is achieved by controlling the impurity concentration in the channel region of each memory cell transistor. That is, the impurity concentration in the channel region is selected from four different impurity concentrations depending on the data to be programmed. The impurity concentration control provides desired one of the four different threshold voltages for each memory cell transistor to allow programming four-value data.
In the technique disclosed in the '440 application, the impurity implantation into the channel region is achieved as follows. After memory cell transistors are integrated within a semiconductor substrate, ion implantation is repeatedly performed the same number of times as the number of allowed values of the program data. A resist mask is formed to cover the semiconductor substrate and the memory cell transistors in the programming of certain data. The resist mask is provided with openings which only expose memory cell transistors to be programmed. The ion implantation is performed with a dose amount in accordance with the program data by using the resist mask. After that, the resist mask is removed and a new resist mask for programming next data is formed. The ion implantation is performed with a different dose amount by using the new resist mask. The same processing will be repeated the same number of times as the number of allowed values of the program data. It should be noted that thick resist masks are used in the ion implantation, since high energy ions are implanted into the channel regions of the memory cell transistors.
Although the multi-valued mask ROM is advantageous for reduction of the layout area, the technique disclosed in the '449 application undesirably requires repeatedly performing the formation of the resist masks and the ion implantation into the channel regions the same number of times as the number of allowed values of the program data. This leads to an undesirable increase in the TAT (turn-around time) and manufacture cost. In addition, when data of the same value are programmed onto two adjoining memory cell transistors, two openings are formed through the thick resist mask across a narrow spacing. This may result in collapse of the portion of the thick film resist mask between the two openings. To prevent the resist mask from collapsing, it is required to provide a sufficient spacing between the adjoining memory cell transistors. This undesirably leads to the increase in the layout area.
USPTO Backgrounds
USPTO Backgrounds