1. Field of the Invention
This invention relates to photosensitive semiconductor devices consisting of at lesat one row of photodetecting points, a row coupled to a readout register of the charge-transfer type. The invention is applicable particularly to linear arrays made of several parallel rows of photodetecting points operating in the integration and charge carry mode (abbreviated "IRC"), and it relates to means of significantly reducing the smearing effect.
2. Description of Background
FIG. 1 diagrammatically shows the conventional architecture of a photosensitive array BP of the type formed by several rows L1, L2, . . . , Ln with photosensitive surface elements S1n, S2n, . . . , SMn. The rows of photosensitive surface elements are parallel and these photosensitive surfaces are arranged so that they form rows L1 to Ln and columns C1 to CM perpendicular to the rows.
According to a conventional arrangement, a readout register RL (formed by a shift register operating by charge transfer) is located beside one of the ends of columns C1 to CM formed by the photosensitive surface elements belonging to first row L1. Each of these photosensitive surface elements S1 to SM of first row L1 is connected, by a gate Pl to PM, to a storage space, CS1 to CSM respectively, of readout register RL. In a conventional way, readout register RL operates, for example, in the two-phase mode, with two transfer control inputs ET1, ET2, to which there are applied control signals SC1, SC2 having phases suitable for transferring, to an output SO of the register, electrical charges that have been discharged in the latter. Output SO is connected to a readout circuit CL, conventional in the art, notably comprising an amplifier A that supplies a succession of signals (not shown) in the form of voltage, for example, each having an amplitude corresponding to the quantity of charges discharged in a space CS1 to CSM.
Each of rows L1 to Ln comprises a control input EC1 to ECn to which there are applied transfer control signals called row signals SL1 to SLn; these row signals are used to transfer, in the direction of columns C1 to CM, i.e., from rows to rows, the charges stored at the photosensitive surface elements forming these rows L1 to Ln, until these charges are discharged in storage spaces CS1 to CSM of readout register RL.
The "IRC" type of operating mode is well known in the art. It is used notably in the case of a relative linear movement between an image and photosensitive array BP. In FIG. 1, an arrow designated 3 symbolizes the shifting of the image (not represented) relative to array BP. Operation in IRC mode consists in shifting rows L1 to Ln or, more precisely, in transferring the charges accumulated at a given row L1 to Ln to a following row, synchronized with the shifting of the image and in the same direction. In this configuration, when the photosensitive surfaces of a given row are illuminated, row Ln for example, the photosensitive surfaces of this row accumulate charges during a period called integration time Ti that corresponds to the time it takes one row to analyze some of the image compared to this row of photosensitive surfaces. Then, with the relative shifting of the image and of the photosensitive array, this same row for analyzing some of the image (not shown) arrives at the level of the following row of photosensitive surfaces, i.e., row Ln-1: the charges stored in this row Ln-1 having been transferred in advance to the following row, in the direction of transfer shown by an arrow 5, row Ln-1 then finds itself emptied of all charge and row signal Sln controls the transfer of charges that were stored in row Ln and that are then transferred into adjacent row Ln-1, and then the integration period begins for the photosensitive elements of this row Ln-1. Thus it is for each photosensitive surface element of this row Ln-1; each of these photosensitive surface elements produces charges that are added to charges already stored by the illumination at the same point of a same row of the image. Also, continuing in this way up to first row L1 near the readout register, the information projected by the image is integrated n times longer.
The usefulness of a photosensitive sensor operating in the IRC mode consists in the considerable improvement of the signal-to-noise ratio, this ratio being a determining factor for detection. Indeed, if only the dominant noise and the photon noise are considered, the signal is multiplied by n while the noise is multiplied by .sqroot.n. The signal-to-noise ratio is thus increased by the factor .sqroot.n.
As a reminder, on the one hand that, the shift register, which forms the readout register RL, and controlled gates P1 to PM placed between the readout register and photosensitive array BP, are formed on the same semiconductor substrate as photosensitive array BP and, on the other hand, readout register RL and controlled gates P1 to PM are masked by a filter that is opaque to light (visible or near-visible), while the photosensitive elements are exposed to this light to produce more numerous negative charges (electrons) the more intense the illumination. The opaque filter is shown in FIG. 1 by slanted lines designated 14. Array BP thus comprises a photosensitive surface SP divided into photosensitive surface elements S1.sub.1 to SM.sub.n forming rows L1 to Ln and columns C1 to CM: row L1 is made of photosensitive surface elements S1.sub.1, S2.sub.1, S3.sub.1 . . . , SM.sub.1 ; row L2 is made of photosensitive surface elements S1.sub.2, S2.sub.2, S3.sub.2, . . . SM.sub.2, and so on; column C1 is made of surface elements S1.sub.1, S1.sub.2, S1.sub.3, . . . S1.sub.n ; column C2 is made of surface elements S1.sub.2, S2.sub.2, S2.sub.3, . . . , S2.sub.n and the same for the other columns. In the nonlimiting case shown in FIG. 1 by way of example, each photosensitive surface element S comprises, in a known way, two electrodes electrically connected to one another, one of which has a threshold voltage different from the other to direct the charge transfer in the direction of arrow 5, thus forming a pair of electrodes made of a transfer electrode ET followed by a storage electrode ES (in the direction of columns C1 to CM), with storage electrode ES beside readout register RL. Thus each column C1 to CM comprises a succession of photosensitive surface elements, each having a storage electrode and a transfer electrode so that each of the columns forms a shift register for charge transfer. If first column C1 is considered, for example following a direction opposite to that shown by arrow 5, starting at first row L1 there is found: a first storage electrode ES1 followed by a first transfer electrode ET1 in first surface element S11; then, at second row L2, a second storage electrode ES2 is found, followed by a second transfer electrode ET2; then a third storage electrode ES3 followed by a third transfer electrode ET3; and so on until last row Ln, where a storage electrode ESn followed by a transfer electrode ETn is found.
The unit operates cyclically with, for each cycle, a control for readout register RL, a control that causes, in the latter, a gradual transfer, toward the readout circuit, of data or charges that were stored in the various columns and that have been discharged in corresponding spaces of readout register RL, this is performed by gate circuits P1 to PM to which there were applied, for this purpose, authorizing pulses SA, authorizing the passage of the charges.
The transfer of charges for each column C1 to CM, from row Ln up to row L1, is obtained using row signal pulses SL1 to SLn. These row signals follow one another with phase deviations that depend on the operation of photosensitive array BP, this operation being able to be conventional, either the two-phase, three-phase, or four-phase type, or, moreover, these pulses can follow one another with a phase such that time .DELTA.T, which separates two successive pulses applied to two adjacent rows, corresponds to the ratio of cycle time TC to number of rows n (.DELTA.T=TC/n); this last type of operation is known by the English expression "ripple clock."
FIG. 2 is a timing diagram showing the phase relation among signals to be applied to a photosensitive array operating in the IRC mode, with eight "ripple clock" phases, i.e., an array comprising eight rows of photosensitive surface elements.
Rows a to h of FIG. 2 show, respectively, row signals SL1 to SL8 made of negative voltage pulses intended to be applied respectively to rows L1 to L8.
Moment t1 marks the start of row signal SL1 applied to first row L1, and moment t2 marks the end of this signal. We mention that first row L1, to which this signal SL1 is applied, is the row closest to readout register RL, and that moment t2 marks the end of the transfer of charges stored at storage electrodes ES1 of this row; these charges being transferred in the corresponding spaces of the readout register. We note that the beginning is thus first row L1 being emptied of its charges, thus leaving it ready to receive charges coming from second row L2.
Signal SL2 applied to second row L2 starts at a moment t3, which follows moment t2 by a time .DELTA.t; the end of pulse SL2 is found at a moment t4 and marks the end of the transfer of charges stored at second row L2, these charges being transferred at the storage electrodes of first row L1; second row L2 thus being freed in its turn.
A similar operation is found for pulses SL3 to SL8, applied respectively to rows L3 to L8 and beginning, respectively, at moments t7, t9, t11, t13, t15; and ending at moments t8, t10, t12, t14, t16.
At a moment t17, found after moment t16, a second pulse SL1' starts that is applied again to first row L1 to discharge the charges contained in the latter in corresponding spaces of the readout register; this pulse SL1' ends at an instant t18.
The time interval between moment t2 and moment t18 corresponds to an integration time Ti of first row L1. It can be thought that a cycle time Tc is between moment t2 and moment t18, which marks the end of second pulse SL1' applied to first row L1.
FIG. 3 shows a column C1 to CM in a diagrammatic, cutaway view, first column C1, for example, and shows the potential profiles at the electrodes of this column, these potential profiles being produced by applying row signals SL to these electrodes; as is customary concerning charge transfer devices, the positive potentials increase toward the bottom.
In the example described, first column C1 comprises 8 pairs of electrodes, ES1 to ES8 and ET1 to ET8, i.e., it belongs to an array comprising 8 rows L1 to L8.
Each pair of electrodes symbolizes a row L1 to L8 and comprises a storage electrode and a transfer electrode, the two electrodes of the same pair being connected together and controlled by the same row signal. Thus there is found successively, starting from the right of the figure in a direction opposite to charge transfer direction 5: an electrode ECs1 that controls first space CS1 of shift register RL; then an electrode EP that represents the controlled gates located between photosensitive array BP and readout register RL; then photosensitive zone or surface SP of column C1 begins, i.e., first storage electrodes ES 1 is followed by first transfer electrode ET1, these two electrodes being connected and intended to receive row signal SL1. Then there is found a second pair of electrodes made of the second storage electrode followed by the second transfer electrode, and so on up to the eighth pair of electrodes formed by an eighth storage electrode Es8 followed by en eighth transfer electrode Et8. These electrodes are carried in a conventional way by a semiconductor substrate 10, by an electrically isolating layer 11 that isolates the electrodes from one another and from substrate 10. Semiconductor substrate 10 can be of silicon, for example, of the P-doped type, but it can comprise, under isolating layer 11, a layer 12 with N-type doping, intended to form, in a conventional way, a buried channel promoting charge transfer.
As we indicated above, the zones corresponding to readout register RL and to the gates authorizing the passage of charges toward the readout register are masked by an optical filter 14, made of aluminum for example, which prevents any illumination of these zones, while photosensitive surfae SP remains exposed to light. This is illustrated in FIG. 3, in which optical filter 14, opaque to light, extends above a zone ZPL protected from light, i.e., above passage electrode P1 and above first space CS1 of readout register RL; the photons are symbolized by wavy arrows 16 that can penetrate up to the substrate to produce charges there; storage and transfer electrodes ES1 to ES8 and ET1 to ET8 being made, for example, of highly doped silicon, they are transparent to light, isolating layer 11 being also transparent to light.
It should be noted that transfer electrodes ET1 to ET 8 produce, in a conventional way, a threshold voltage higher than the storage electrodes to define an isolating wall between rows to orient the direction of the charge transfer as shown by arrow 5, i.e., in the direction starting from storage electrode ES8 toward first storage electrode ES1 and toward shift register EL. This threshold difference can be obtained in a conventional way, for example, by a difference in the doping of the semiconductor material in zones marked N-, which are located at transfer electrodes ET1 to ET8; these zones N- having the same type of conductivity as buried channel 12 with N-type doping, but less doped than the latter.
FIG. 3a is to be read with FIG. 3 and it illustrates the potential profile that exists at transfer and storage electrodes ET1 to ET8 and ES1 to ES8, just before moment t1 mentioned in FIG. 2, i.e., in the absence of row signal; this moment t1 marks the start of the pulse of row signal SL1 applied to first row L1 and subsequently applied to first transfer and storage electrodes ET1, ES1.
Thus, just before moment t1, the potential applied to all the electrodes is a resting potential which, for example, is positive with respect to a reference potential to which substrate is brought. The voltage threshold mentioned above, which transfer electrodes ET1 to ET 8 produce, creates, at these electrodes, a potential VP1 that is more negative than a potential VP2 that is created at storage electrodes ES1 to ES8. As a result, at each storage electrode ES1 to ES8, there is created a potential well PU1 to PU8 whose bottom corresponds to positive potential VP2, and these potential wells are separated by potential barriers B1 to B7 produced, respectively, at transfer electrodes ET1 to ET8; barriers B1 to B7 make it possible to separate the charges (symbolized in the figure by hatch marks) stored at storage electrodes ES1 to ES8 in corresponding potential wells PU1 to PU8. It can be noted that, in charge transfer direction 5, each potential well PU8 to PU1 contains more charges than the preceding potential well; so that just before moment t1, potential well PU1, located at storage electrode ES1, contains all the charges that were successively integrated for the same point of the image during the shifting of the latter.
FIG. 3b illustrates the transfer, in space CS1 of readout register RL, of charges that were contained in first potential well PU1, this charge transfer being completed at moment t2, at which the pulse of row signal SL1 ends: it can be seen that, with the application of row signal SL1, made by a pulse of negative voltage, the potentials at the first transfer electrode and the first storage electrode become more negative and pass respectively to values VP5, VP6, with value VP5 more negative than value VP6, so that potential barrier B1 is maintained and prevents the charges that were contained in first potential well PU1 from returning to second potential well PU2. In contrast, following a pulse of positive voltage applied to gate electrodes EP, the resting potential at the latter becomes more negative and of a value, for example VP7, which it had before moment t1 when it formed a potential barrier BPP, it passes to a more positive value, for example VP1, so that it does not form an obstacle to discharging, in space CS1 of the readout register, of the charges that were originally contained at first storage electrode ES1, i.e., in first potential well PU1.
FIG. 3c shows the potential profile between moment t2 and moment t3, represented in FIG. 2; it can be seen that potential well PU1 at first storage electrode ES1 has been emptied of its charges, and consequently it is ready to receive the charges stored in preceding potential well PU2, located at second storage electrode ES2.
FIG. 3d illustrates the transfer, into first potential well PU1, of charges that, before moment t3, were contained in second potential well PU2: between moment t3 and t4 (represented in FIG. 2), signal SL2, made of a pulse of negative voltage, is applied to second transfer and storage electrodes ET2, ES2 and the potentials at these electrodes pass to more negative values, respectively from VP2 to VP5 and from VP1 to VP6, as in the case of the preceding example. The result is that at moment t4 (shown in FIG. 2), the charges that were originally contained in second potential well PU2 are again stored in first potential well PU1.
FIG. 3e shows that, at moment t4 (illustrated in FIG. 2), second potential well PU2 is empty, and it is able, as a result, to receive the charges contained in the potential well preceding it, i.e., third potential well PU3 formed at third storage electrode ES3.
FIG. 3f illustrates the variations of potential produced at third transfer and storage electrodes ET3, ES3 by applying the pulse of negative voltage, of which row signal SL3 is made, applied to these third electrodes and which leads to transferring, in second potential well PU2, the charges that were contained in third potential well PU3; this is according to the same type of operation as in the preceding examples.
These operations are repeated in a similar manner (not shown) successively to transfer the charges contained in potential wells PU4, PU5, PU6, PU7 and PU8. The subsequent discharge, in space CS1 of readout register RL, of the charges contained in first potential well PU1 is performed, in a way similar to that shown in FIG. 3b, between moments t17 and t18 (shown in FIG. 2) at which a new row signal SL1' is again applied to first row L1, i.e., to first transfer and storage electrodes ET1, ES1. It should be noted that, between these two successive transfer operations in the spaces of register RL of the charges that were stored in first potential well PU1, the readout register was activated so as to advance gradually, toward readout circuit CL (shown in FIG. 1), all the charges that were stored in spaces CS1 to CSM.
This operation and this configuration of a photosensitive device operating in the integration and charge carry mode are conventional in the art. But this configuration produces a major drawback that consists in an especially significant smearing effect that can affect the entire image.
USPTO Backgrounds
USPTO Backgrounds