1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, this invention relates to a device for reading cell information from memory cells in a semiconductor memory device.
2. Description of the Related Art
With the rapid change in integrated circuit technology, there is an increasing demand for semiconductor memory devices that incorporate a larger memory capacity and operate at increasingly faster speeds. To achieve such an increase in such a device's operating speed, the power consumption and noise burdens on a supply voltage should be reduced. It is therefore necessary to reduce the power consumption and noise burdens on the supply voltage, in cell information reading devices, and thereby to increase the operation speed thereof.
In reading cell information from a DRAM, as an example of a semiconductor memory device, a specific memory cell is selected based on address signals. The cell information stored in the selected memory cell is read out onto bit lines. The read cell information is latched and amplified by a sense amplifier and is then output onto data buses. The cell information, output on the data bus, is further amplified and latched by a sense buffer. The cell information latched by the sense buffer is output to an external circuit via an output circuit.
In the above-mentioned DRAM, cell information is read in a specific order from memory cells by a repetitive reading operation, wherein a single reading cycle is defined from the input of an instruction signal, to start the reading operation, to the output of the read cell information from the output circuit. As soon as the reading operation starts, the output circuit is enabled, so as to output the data latched in the sense buffer. At the beginning of the reading operation, the sense buffer latches the cell information that has been read in the previous cycle, and the latched cell information must be temporarily output as invalid data from the output circuit. Then, after the normal accessing time in the reading operation has elapsed, the cell information read from the selected memory cell is latched by the sense buffer, and then the latched cell information is output as valid data from the output circuit.
When the invalid data and the valid data have a complementary relation, it is necessary for the output circuit to invert the invalid data, which has been temporarily output, in order to output the valid data. This hinders the improvement in the reading speed, from the selection of a specific memory cell to the outputting of the cell information in that memory cell as valid data.
When invalid data is switched to valid data, a through current between a High voltage-supply and a Low voltage supply (e.g. ground level) and/or a charge/discharge current between a terminal and one of the High and low voltage-supplies is generated in the output circuit and/or in another circuit at the preceding stage thereof. Such a through current, or a charge/discharge current increases the consumed power, and causes supply-voltage noise to occur.
USPTO Backgrounds
USPTO Backgrounds