(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of reliable dielectric layers capable of filling gaps having widths less than 0.15 xcexcm to 0.25 xcexcm without voids in the dielectric layer and without damage to underlying circuit devices.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits the integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through the use of patterned conductor layers which are separated by dielectric layers. As integrated circuit microelectronics fabrication integration levels have increased and integrated circuit device and patterned conductor layer dimensions have decreased, the spacings between adjacent features on a substrate have, also, decreased. Therefore, an important challenge, when depositing dielectric layers, is to provide voidless gapfill capability over high aspect ratio (up to 5) trenches, where aspect ratio is defined as the height of the trench divided by the width of the trench.
Many approaches to fill gaps with dielectric material have been proposed, as shown in the following patents. U.S. Pat. No. 5,937,323 entitled xe2x80x9cSequencing of The Recipe Steps For The Optimal Low-K HDP-CVD Processingxe2x80x9d granted Aug. 10, 1999 to Maciek Orczyk et al. describes a method for producing a stable, halogen-doped silicon oxide layer using a high-density plasma chemical vapor deposition (HDP-CVD) system. The sequence of steps includes introducing a substrate into a chamber and setting an initial chamber pressure with process gases. Then, a plasma is formed by applying radio frequency (RF) power to a plasma coupling structure, whereby the substrate is heated to a temperature above 100xc2x0 C. prior to layer deposition. Layer deposition comprises a relatively thin layer of undoped silicon oxide deposited onto the substrate having a temperature above 100xc2x0 C., followed by a thicker layer of a halogen-containing silicon oxide. During deposition of the halogen-containing silicon oxide layer the radio frequency (RF) power applied to the plasma coupling structure is reduced in order to suppress heating of the substrate.
And, U.S. Pat. No. 6,004,863 entitled xe2x80x9cNon-Polishing Sacrificial Layer Etchback Planarizing Method For Forming A Planarized Aperture Fill Layerxe2x80x9d granted Dec. 21, 1999 to Syun-Ming Jang describes a high-density plasma chemical vapor deposition (HDP-CVD) process which employs both a side source of radio frequency power and a top source of radio frequency power.
In general, HDP (High Density Plasma) CVD (Chemical Vapor Deposition) processes have been used for deposition of dielectric layers and can provide voidless gapfill over high aspect ratio features. However, high density plasma processes can, also, induce damage to underlying semiconductor circuit devices. FET devices having thin gate oxide are particularly vulnerable to plasma induced damage (PID). Subjecting such devices to high density plasma deposition processes, as used for the deposition of dielectric layers, can damage the gate oxide and result in reduced process yield. Furthermore, PID can result in degraded device reliability because the integrity of the gate oxide is compromised. For these reasons utilization of HDP-CVD for deposition of IPO (Inter-Poly-Oxide) dielectric or ILD (Inter-Level Dielectric) has not gained acceptance.
The present invention is directed to a novel method of depositing dielectric layers using high-density plasma chemical vapor deposition (HDP-CVD). The novel process permits voidless gapfill over high aspect ratio trenches and minimization of plasma induced damage to underlying semiconductor circuit devices.
It is a general object of the present invention to provide an improved method of depositing dielectric layers by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto semiconductor substrates containing integrated circuit devices.
A more specific object of the present invention is to provide an improved method of depositing dielectric layers by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto semiconductor substrates containing integrated circuit devices, whereby the deposited dielectric layer produces voidless gapfill over high aspect ratio trenches.
Another object of the present invention is to provide an improved method of depositing dielectric layers by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto semiconductor substrates containing integrated circuit devices, whereby the deposited dielectric layer produces voidless gapfill over high aspect ratio trenches and with minimization of plasma induced damage to underlying semiconductor circuit devices.
In accordance with the present invention, the above and other objectives are realized by using a method of forming a dielectric layer by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto a semiconductor substrate containing active circuit devices, the method comprising the following steps: providing a semiconductor substrate, having active circuit devices therein; loading the semiconductor substrate, having active circuit devices therein, into a HDP-CVD (High-Denisty Plasma Chemical Vapor Deposition) system having at least two RF power sources; heating the semiconductor substrate, having active circuit devices therein, to a temperature in the range between about 400 and 700xc2x0 C.; flowing process gases into the HDP-CVD system under conditions suitable for depositing the dielectric layer; controlling the RF power to one of the at least two RF power sources in the range between about 1000 and 2000 Watts; controlling the RF power to the second of at least two RF power sources to be less than about 2000 to 2500 Watts; and depositing the dielectric layer to a thickness between about 1000 and 20,000 Angstroms.
In a second embodiment of the present invention, the above and other objectives are realized by using a method of forming a dielectric layer by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto a semiconductor substrate containing active circuit devices, the method comprising the following steps: providing a semiconductor substrate, having active circuit devices therein; loading the semiconductor substrate, having active circuit devices therein, into a HDP-CVD (High-Denisty Plasma Chemical Vapor Deposition) system having at least two RF power sources; heating the semiconductor substrate, having active circuit devices therein, to a temperature in the range between about 400 and 700xc2x0 C.; flowing process gases into the HDP-CVD system under conditions suitable for depositing the dielectric layer; controlling the RF power to one of the at least two RF power sources in the range between about 1000 and 2000 Watts; controlling the RF power to the second of at least two RF power sources in the range between about 1500 and 2500 Watts; and depositing the dielectric layer to a thickness less than about 20,000 Angstroms.
In a third embodiment of the present invention, the above and other objectives are realized by using a method of forming a dielectric layer by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto a semiconductor substrate containing MOSFET circuit devices, the method comprising the following steps: providing a semiconductor substrate, having MOSFET circuit devices therein; loading the semiconductor substrate, having MOSFET circuit devices therein, into a HDP-CVD (High-Denisty Plasma Chemical Vapor Deposition) system having at least two RF power sources; heating the semiconductor substrate, having MOSFET circuit devices therein, to a temperature in the range between about 400 and 700xc2x0 C.; flowing process gases into the HDP-CVD system under conditions suitable for depositing said dielectric layer; controlling the RF power to one of the at least two RF power sources in the range between about 1000 and 2000 Watts; controlling the RF power to the second of at least two RF power sources to be less than about 2000 to 2500 Watts: and depositing the dielectric layer to a thickness between about 1000 and 20.000 Angstroms.
And in yet a fourth embodiment of the present invention, the above and other objectives are realized by using a method of forming a dielectric layer by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) onto a semiconductor substrate containing MOSFET circuit devices, the method comprising the following steps: providing a semiconductor substrate, having MOSFET circuit devices therein; loading the semiconductor substrate, having MOSFET circuit devices therein, into a HDP-CVD (High-Denisty Plasma Chemical Vapor Deposition) system having at least two RF power sources; heating the semiconductor substrate, having MOSFET circuit devices therein, to a temperature in the range between about 400 and 700xc2x0 C.; flowing process gases into the HDP-CVD system under conditions suitable for depositing the dielectric layer; controlling the RF power to one of the at least two RF power sources in the range between about 1000 and 2000 Watts; controlling the RF power to the second of at least two RF power sources in the range between about 1500 and Watts; and depositing the dielectric layer to a thickness less than about 20,000 Angstroms.
USPTO Backgrounds
USPTO Backgrounds