In recent years, most of the mobile communication (3GPP LTE) systems have replaced the turbo code interleaver of the physical layer in 3G mobile communication system with the QPP interleaver to improve the decoding speed of the decoders. QPP interleaver, in addition to the advantage of memory contention free, shows promising results in both hardware complexity and decoding capability. QPP interleaver allows the turbo decoding to avoid the memory contention problem after the maximum A posterior probability (MAP) algorithm computing the MAP, while in the mean time, using a plurality of sliding windows to achieve the parallelism to accelerate the computation of decoder.
The common design for turbo code interleaver is to store the computed interleaver address in a memory or an address table in advance, as the serial and parallel structure shown in FIG. 1A and FIG. 1B. In the serial structure of FIG. 1A, after a sliding window 110 outputs one extrinsic information 110a, sliding window 110 needs an interleaver address; hence, a corresponding interleaver address in an address table 120 is read to act as the address of memory 130 for storing extrinsic information 110a. 
In the parallel structure of FIG. 1B, after a sliding window outputs a plurality of intrinsic information, a plurality of corresponding interleaver addresses are read from an address table 121. In combination with a data multiplexer 125 for selecting, these addresses are used as the corresponding addresses in the memory for storing the plurality of extrinsic information.
Take LTE turbo code as example. The decoding length may range from 40 to 6144 bits. In other words, the number of bits in each code segment may range from 40 to 6144 bits. For 188 types of decoding length specifications, the memory must be able to store 188 interleaver addresses of length ranging from 40 to 6144 bits. This is a considerable demand on the memory capacity.
For example, U.S. Pat. No. 6,845,482 disclosed an element for generating prime number index information and a technology of five lookup tables, as shown in FIG. 2, for generating memory address of turbo code interleaver. The memory address generation technology generates interleaved address of turbo code that is compliant to W-CDMA standard. For all the possible code segment lengths supported in W-CDMA standard, table 210 stores all the possibly used prime numbers, 52 prime numbers in total. Table 220 stores four inter-row permutation sequences 221-224. Table 230 stores 52 intra-row base sequences. Each prime number P in table 230 corresponds to an intra-row base sequence. The length of the intra-row base sequence is P−1. Table 240 stores the starting addresses of these 52 intra-row base sequences. Table 250 stores 52 prime number sequences, with each prime number sequence having the length of 20.
U.S. Patent Publication No. US2008/0115034 disclosed a QPP interleaver, applicable to an encoder for turbo code. In FIG. 3, QPP interleaver 300 includes an interleaver memory 310, an address generator 320 and a control unit 330. Modulo-counter 331 of control unit 330 provides an input index n to address generator 320. The n-th value Π(n) of the output sequence of address generator 320 may be described as:Π(n)=(f1n+f2n2)mod k, n=0, 1, . . . , k−1,Where Π(n) is the n-th interleaved output position, f1 and f2 are QPP coefficients, k is the information block length of the input sequence, and mod is the modulus computation. The computed Π(n) is stored in interleaver memory 310, and is serially read out from interleaver memory 310 when needed.
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USPTO Backgrounds