1. Field of the Invention
The present invention relates to a method of forming a suspension object on a monolithic substrate, and more particularly to a method capable of precisely releasing and suspending a microstructure on a monolithic substrate by using a process combining an anisotropic dry etching method and a wet etching method, on the monolithic substrate integrating an integrated circuit (IC) and the microstructure.
2. Related Art
With the quick development of the IC process and the evolution of the market demands, ICs having different properties and different processes may be finished gradually after being integrated on the same chip, such that as compared with the system achieved by using a plurality of chips through a wire bonding configuration, the formed system-on-chip (SOC) has a higher and more stable IC capacity, and the SOC, advantageous in being light, thin, short, and small, being power saving, and having a high integrity, results in a greatly improved market competitiveness of the product.
In another aspect, the SOC may also be applied to the process technique of integrating the micro machine, such that the suspension microstructure and the IC circuit are integrated on a single chip. Complementary metal oxide semiconductor (CMOS)-Compatible micro electro mechanical systems (MEMS) (CMOS-Compatible MEMS) is a technique combining the semiconductor CMOS circuit process and the MEMS, in which the IC circuit and the MEMS are integrated on the same silicon chip with the same design interface, and then a silicon micromachining technique of the MEMS is used for auxiliary, so as to manufacture the suspension microstructure of the MEMS on the silicon chip, such that the suspension microstructure may generate mechanical motion. According to the sequence of manufacturing the MEMS and the CMOS circuit, the process may be classified into the following modes. (A) The process of etching the MEMS structure and the IC process are used together, so as to etch holes to be etched under the MEMS structure when the IC circuit is laid or etched. (B) The IC circuit and the MEMS structure are integrated on the same chip with the same design interface, and then a suspension microstructure is manufactured on a silicon wafer by using the silicon micromachining technique of the MEMS. Although the holes under the MEMS structure may be easily etched in the mode (A), the original equipment manufacturer (OEM) needs to change the original processing steps to match with the MEMS process, which results in a high cost, and requires a more precise calculation to increase the yield of the product. If the products do not exist in quite a large quantity, the MEMSs are not manufactured by the OEM.
Therefore, most of the MEMS products are manufactured by using a post-process of the mode (B). The MEMS structure is stacked on an etched layer, and then the MEMS structure is processed and released by using the post-process. Although the etching step is complicated, it is unnecessary to design a new silicon wafer process for the specific MEMS product. Meanwhile, as compared with the mode (A), the mode (B) utilizing the existing standardized CMOS process is more easily developed, and saves much manufacturing cost.
The conventional etching method is classified into two types. One is a common wet etching method, in which the etching is performed by using the specific chemical reaction of a chemical solution to the chip. The other is a dry etching method, which is usually a plasma etching, in which ions in the plasma impact the material of a surface of the chip and make the material to fall off, or the etching is performed by using the mechanical reaction between active free-radicals in the plasma and atoms on the chip.
In the wet etching method, usually an etchant used to exclusively etch the specific material can be found, such that although the wet etching method belongs to a diffusion type isotropic etching, the etchant has a specificity on the material, such that patterns may be etched on the chip with a mask made of special materials on the surface of the chip. However, the etching mode is still the isotropic etching, so an aspect ratio of the etching is usually small.
The etching mode of the dry etching method achieves the etching effect by using the impacting force of the ions, such that the dry etching may perform a directional anisotropic etching having an aspect ratio achieving a depth greater than 5:1, or may even use a deep reactive ion etching (RIB) to achieve an aspect ratio up to 30:1.
Therefore, when it intends to etch the suspension object structure having an aspect ratio more than five times that of the conventional mode (B), mostly the dry RIE method is adopted, so as to achieve the anisotropic etching having a higher aspect ratio. In U.S. Pat. No. 6,712,983, Zhao et al., a two-stage dry etching method is disclosed. Referring to FIGS. 4A-4B, a two-dimensional pattern on a microstructure a0 is formed through anisotropic etching by using a photoresist layer a2 above a circuit layer a1 as a mask (as shown in FIG. 4B), in which an etching depth reaches to a silicon base layer a3 under the circuit layer a1 (as shown in FIG. 4C). Then, the silicon base layer a3 under the microstructure a0 is etched through semi-anisotropic dry etching (as shown in FIG. 4D). Finally, the silicon base layer a3 under the microstructure a0 is further etched to form a hole through isotropic dry etching, such that the microstructure a0 is released and suspended (as shown in FIGS. 4D-4E). In U.S. Pat. No. 6,712,983, the microstructure having the high aspect ratio is obtained through etching, but the processing steps are complicated with strict processing demands, and are time and labor consuming, and the size and the shape of the hole under the microstructure region cannot be precisely controlled through etching. In addition, referring to FIGS. 5A to 5C, after the etching is finished and the single chip is packaged, when it intends to separate each microstructure a0, a cap a4 needs to be cut to perform an etching process again, such that not only the complexity and the cost of the process are increased, but also the process needs to have a detailed consideration and calculation on a mechanical configuration of the microstructure.
Although the dry etching method may achieve the higher aspect ratio, the etching speed thereof is much slower than that of the wet etching method, and the cost is higher. Further, when a size of the MEMS structure is changed, the new dry etching process, the proportion of ingredients, and the etching time etc. need to be tested again, which, however, greatly increases the time, the man power, the material resources, and the material cost for developing the MEMS chip.
Accordingly, in order to solve the problem how to combine the advantages of the quick and cheep etching manner of the wet etching method and the high aspect ratio of the dry etching method, simplify and accelerate the process, and reduce the manufacturing cost and material cost, the inventor proposes the present invention through years of experiences and continuous research and development.
USPTO Backgrounds
USPTO Backgrounds