1. Technical Field
The present disclosure relates to a recessed gate field effect transistor.
2. Description of the Related Art
As the semiconductor manufacturers continue to explore the use of processes that are below 32 nm, traditional field effect transistor (FET) designs often fail to function properly. One characteristic of FETs that manifests undesirable traits in smaller dimensions is the increased sheet resistance of the gate. As the dimensions, and therefore the gate length, become smaller, the resistive effect of the sheet resistance of the gates of traditional FET designs increases. Increased sheet resistances at the gates results in slower switching speeds as a result of RC time delays, and also requires more power.
USPTO Backgrounds
USPTO Backgrounds