1. Field of the Invention
The invention relates to a memory device, in particular, a Flash Nand memory device including a page buffer circuit.
2. Description of Related Art
Flash Nand memory device includes a memory cell and a page buffer which is used as a read circuit to temporarily store the logical value attributed to the cell threshold condition: the common way is to attribute a value 0 (programmed) or 1 (erased) depending on whether the cell driven by a read voltage on its gate contact is switched off or not.
If the cell is switched on, and the gate is driven at the read voltage, the cell conducts a current. Otherwise, the cell does not conduct a current. The system used to sense the cell current is to let a charged capacitor discharge in a fixed time: depending on whether the final voltage of the capacitor is lower or higher than a threshold value, the read cell is considered erased or programmed.
FIG. 1 shows the page buffer and the connection to a single cell: Cbl is the capacitor discharged by the cell's current (arrow 1) during the fixed time called evaluation time. Actually the Cbl is not a discrete device but the whole bit line, that is a long strip of metal. It is not the purpose of this invention to explain the read procedure adopted with such type of page buffer and architecture, what is relevant for the invention is that at the end of the evaluation time the bitline connected to the read cell, reaches a voltage value that depends on the starting voltage, the cell's current and the evaluation time itself.
Finally the bitline selector bsele (or bselo in case of odd page read) switches on and connects the selected bitline to the inner page buffer node called datab. Thanks to the charge sharing the datab voltage reaches the same value of the bitline (arrow 2) and if this value is high enough to switch on the mdata transistor (the condition is the typical mos switch on condition V(datab)=VGS(mdata)>VTH(mdata)) a pulse on readpb signal can easily drive the pre-charged latp node to ground (arrow 3), and force the page buffer latch to flip, otherwise the latp can't be discharged and remain high and so the page buffer latch maintains the starting value. This roughly the way the page buffer is used during a read operation as a transducer of a analog quantity (the final value of the bitline voltage) to a digital value (the final value of latp/latn nodes).
In a flash NAND device the number of the page buffer circuits in the page buffer block is the same size of the page, typically 4 KB (32768 bits), or more and thanks to the particular position of thee block in the device, attached to the nand matrix, the layout of the page buffer block makes impossible to access to the inner nodes of the circuits and the test of the circuit must be done using indirect measures.
One of the relevant information about the page buffer is its “0-reading threshold” (VTH-0), that is the bitline's voltage above which the circuit reads the cell as programmed (latp=0) while below the circuit reads the cell as erased (latp=1). FIG. 2 shows an ideal behavior of a page buffer read.
USPTO Backgrounds
USPTO Backgrounds