The present invention realtes to a multiprocessor system comprising a plurality of processors, and more particularly to a multiprocessor system used in a data transfer between a plurality of microprocessors.
Hitherto, for transferring data between a plurality of microprocessors, there have been proposed a system called "input/output (I/O) connection system", a system using a FIFO (First-In First-Out) controller, or a system using a shared memory, etc.
The first system called "I/O connection system", e.g., comprises first and second processors, a parallel I/O controller (PIO) for controlling input of data to the first processor and/or output of data therefrom, and another parallel I/O adapter (PIA) for controlling input of data to the second processor and/or output of data therefrom. The first processor and the PIO are connected by means of a bus, the PIP and the PIA are connected by means of a data line, and the second processor and the PIA are connected by means of a bus. Transfer data from the first processor is fed to the PIO through the bus. Then, the transfer data fed to the PIA from the PIO through the data line is fed to the second processor through the bus. Likewise, transfer data from the second processor is fed to the PIA through the bus. Then, the transfer data fed to the PIO from the PIA through the data line is fed to the first processor through the bus. With the system, mutual data transfer between the first and second processors can be performed. However, the drawback with this system is that data transfer per byte is only possible, resulting in degrading the transfer efficiency.
Further, the second system using a FIFO controller is disclosed in, e.g., Japanese Patent Laid-open Publication No. 110167/1981 wherein data transfer between first and second processors is performed via a data line and the FIFO controller. The system can perform mutual data transfer between processors, but has drawbacks that the whole system becomes costly because the FIFO controller is expensive and the FIFO controller has a limited number of processors connectable thereto.
Furthermore, the third system using a shared memory is disclosed in, e.g., Japanese Patent Laid-open Publication No. 50037/1982 wherein data transfer between first and second processors is performed in a manner that one processor writes the transfer data into the shared memory through an access controller and the other processor reads it from the shared memory through the access controller. The system can perform mutual data transfer between processors, but has drawbacks that the both processors cannot access the shared memory at the same time and the access controller becomes structurally complicated.
USPTO Backgrounds
USPTO Backgrounds