As electronic circuits and devices have become more complex, testing of these devices has become increasingly difficult. Test standards have been developed to address at least some of these testing difficulties. One such standard, written by the Joint Test Action Group (“JTAG”), is IEEE standard number 1149.1, which describes the Standard Test Access Port and Boundary-Scan Architecture. Boundary scan is a methodology that allows controllability and observability of the boundary pins in a JTAG compatible device via software control. This capability allows testing of circuit boards that otherwise might not be practical or possible given the trace pitch and multi-layering of printed circuit boards today. Testing is accomplished through a series of registers, accessible through a serial bus, which allow the pins of JTAG compatible devices to be temporarily isolated from their respective devices. The pin on one isolated JTAG compatible device may be set to a known test state while the pin on another isolated JTAG compatible device is monitored to confirm that it is in the same known state. In this way individual traces on a printed circuit board may be tested. This type of testing has generally represented the limits of the testing capabilities of the JTAG architecture.
USPTO Backgrounds
USPTO Backgrounds