As one can readily ascertain, time and timing are extremely important factors in any digital transmission system. It is apparent that when signals are generated by a transmitter and received by a receiver the speed of the receiver must be the same or very close to that of the transmitter. In this manner it follows that whenever a receiver accumulates a timing error, it will process data incorrectly.
Thus, as one can ascertain, all currently used data transmission systems are synchronized in some manner. One prior art technique is referred to as start/stop or asynchronous operation. With such systems a character begins with mark-to-space transition at the beginning of the start space. Then a number of unit intervals later the timing causes the receiving device to sample the first information element which simply is a mark or space decision. The receiver continues to sample at one-bit intervals until the stop mark is received. In start/stop systems the last information bit is the most susceptible to cumulative timing errors. Such systems have other problems regarding the mutilation of the start element and so on. Synchronized data systems do not have start/stop elements but consist of a continuous stream of information elements or bits.
As such, such systems have timing generators or clocks to maintain stability. The transmitting device and its companion receiver at the far end of the circuit must maintain a timed system. In normal practice the transmitter is the master clock of the system. The receiver also has a clock and in every case the receiver's clock is corrected by some means to its transmitter's master clock equivalent at the far end.
As such, there are many techniques for providing such correction. The prior art, for example, utilized what is referred to as a "rubber" clock. Such "rubber" clocks or programmable interval timers are available at the receiver which essentially has logic circuitry for deriving a receiving clock from the transmitted waveform. The receiving circuitry uses the derived clock to synchronize its sampling clock with the clock derived from the transmitted waveform.
This in turn assures that the receiver will sample at the correct intervals to thereby regenerate the transmitted data. In any event, the use of programmable interval timers or "rubber" clocks requires a great deal of additional hardware and further makes the circuit in the receiver extremely complicated. As indicated, the most prevalent system in use today is one that uses transition timing where the receiving device is automatically adjusted to the signaling rate of the transmitter by sampling the transitions of the incoming pulses. This type of timing offers advantages in regard to automatic compensation for variations in propagation time. With this type of synchronization the receiver determines the average repetition rate and phase of the incoming signal transitions and adjusts its own clock accordingly.
As one can understand in digital transmission, the concept of a transition is very important. The transition is what really carries the information. In binary systems the space-to-mark and mark-to-space transitions as positioned in a time reference contain the information. In sophisticated systems, decision circuitry generates and retimes the pulses on the occurrence of a transition. Unlike decision circuits, timing circuits that reshape the pulse when a transition takes place must have a memory for the case when a long series of marks or spaces is received.
Hence, modem internal timing systems tend to have a long term stability of 1.times.10.sup.-8 or better at both the transmitter and receiver. At a data rate of 2,400 bps before a significant timing error can build up, the accumulated time difference between the transmitter and receiver must exceed 2.times.10.sup.-4 seconds. Whenever the circuit of a synchronized transmitter or receiver is shut down, the clocks must differ at least by 2.times.10.sup.-4 seconds before significant errors take place. This essentially means that the leading edge of the receiver clock equivalent timing pulse is 2.times.10.sup.-4 in advance or retarded from the leading edge of the pulse received from the distance end.
Thus, in such systems an idling signal is sometimes sent to synchronize data circuits during periods of no traffic to maintain the timing. Such systems utilize high stability clock circuits which require resychronization over prolonged intervals. Thus, as indicated, the above types of prior art systems utilize a great deal of additional hardware that is necessary in order to synchronize the receiving clock to the transmitting clock. This additional hardware increases the cost of such systems and further reduces the reliability.
It is, therefore, an object of the present invention to provide an improved locking system or synchronizing system for locking a receiving modem to a transmitting modem without the use of additional hardware.
The apparatus and method to be described employs a modem phase locking technique which technique employs a burst signal for such synchronization and which signal avoids complicated circuitry as implemented by the prior art.
USPTO Backgrounds
USPTO Backgrounds