1. Field of the Disclosure
This disclosure relates to a display device, and more particularly to the display device of a chip-on-glass (COG) type preventing a contact defect of a driver integrated circuit chip, and a manufacturing method thereof.
2. Description of the Related Art
As the information society grows, flat display devices capable of displaying information have been widely developed. These flat display devices include liquid crystal display (LCD) devices, organic electro-luminescence display (OLED) devices, plasma display devices, and field emission display devices. Among the above display devices, LCD devices have the advantages that they are light and small and can provide a low power drive and a full color scheme. Accordingly, LCD devices have been widely used for mobile phones, navigation systems, portable computers, televisions and so on.
LCD devices include two substrates and a liquid crystal layer interposed between the substrates. A driver-integrated circuit is disposed on the peripheral region of the liquid crystal panel. The driver-integrated circuit is classified into a chip on glass (COG) type, a tape carrier package (TCP) type, or a chip on film (COF) type according to its loaded shape on the liquid crystal panel. Among these types, the COG type is mainly applied to liquid crystal panels of middle and small sizes because of its simple configuration and easy loading method.
FIG. 1 is a planar view showing an LCD device of the COG type according to the related art. As shown in FIG. 1, an LCD device of the COG type according to the related art includes first and second substrates 11 and 13, a liquid crystal layer (not shown) interposed between the substrates 11 and 13. A portion of the device in which the first and second substrates 11 and 13 overlap each other, is defined as a display area 9 displaying an image. The other portion of the device in which the first and second substrates 11 and 13 do not overlap each other is defined as a non-display area 10.
On the non-display area 10 of the first substrate 11, a flexible printed circuit (FPC) board 3 is connected with the first substrate 11, and gate-driving integrated circuits 5 and data-driving integrated circuits 25 to 27 are mounted. Such a configuration corresponds to the above COG type because the gate-driving integrated circuits 5 and the data-driving integrated circuits 25 to 27 are mounted on substrate 11, which is a glass material.
A plurality of pattern lines 15a to 15d, 17a, and 17b are formed on the non-display area 10. More specifically, the plural pattern lines include gate pattern lines 17a and 17b connecting the gate-driving integrated circuits 5 with the FPC board 3, and data pattern lines 15a to 15d connecting the data-driving integrated circuits 25 to 27 with the FPC board 3. The data-driving integrated circuits 25 to 27 are cascade-connected to one another by the data pattern lines 15a to 15d. 
The gate-driving integrated circuits 5 are connected to the display area 9 by means of gate lines 21. The data-driving integrated circuits 25 to 27 are connected to the display area 9 by means of data lines 23.
A first data-driving integrated circuit 25 receives power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as a gamma voltage, a data signal, and a control signal, which are applied from the FPC board 3 through the data pattern lines 15a to 15d. Data voltages derived from the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal are applied to the display area 9 through the data lines 23.
Parts of the power signals VDD and VDD_gnd are reference voltages, while the rest of the power signals VCC, and VCC_gnd are drive voltages for driving the data-driving integrated circuits 25 to 27. These power signals VDD, VDD_gnd, VCC, and VCC_gnd have values desired by a specification (or a standard), but can be easily varied. The variation induces the data voltages output from the data-driving integrated circuits 25 to 27 to vary as well, thereby causing noise or a dim defect (A: area of causing block dim or block noise, FIG. 1). Actually, the power signals VDD, VDD_gnd, VCC, and VCC_gnd are varied by a contact defect between the data-driving integrated circuits 25 to 27 and the data pattern lines 15a to 15d upon the connection of the data-driving integrated circuits 25 to 27 and the data pattern lines 15a to 15d. 
FIG. 2 is a planar view showing the data-driving integrated circuits shown in FIG. 1. As shown in FIG. 1, each of the data-driving integrated circuits 25 to 27 includes a plurality of bumps 31, 33, and 35. The bumps 31, 33, 35 function as cross-linking members which connect the respective data-driving integrated circuits 25, 26, or 27 to the data pattern lines 15a to 15d. 
The bumps 31, 33, and 35 include input bumps 31 and output bumps 33 which are arranged on both horizontal edges of the respective data-driving integrated circuit 25, 26, or 27. They also include data signal output bumps 35 arranged on a longitudinal edge of the respective data-driving integrated circuit 25, 26, or 27. The input bumps 31 receive the power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as the gamma voltage, the data signal, and the control signal. The output bumps 33 output the power signals VDD, VDD_gnd, VCC, and VCC_gnd, and the gamma voltage, the data signal, and the control signal. The data signal output bumps 35 output the data voltages.
Similarly, the gate-driving integrated circuit 5 includes bumps which connect the gate-driving integrated circuit 5 to the gate pattern lines 17a and 17b and the gate lines 21.
FIG. 3 is a cross-sectional view showing the data-driving integrated circuit and the first substrate taken along the line I-I′ shown in FIG. 2. As shown in FIG. 3, the substrate 11 includes a gate insulation film 43, data pattern lines 45, a passivation (or protective) film 47, and contact electrodes 48. The reference number “41” is a substrate. The gate insulation film 43 is formed on the non-display area 10 of the substrate 11. The data pattern lines 45 are formed separately from each other on the gate insulation film 43. In other words, the data pattern lines 45 are formed in input terminal portions and output terminal portions of the data-driving integrated circuits 25, 26 or 27, respectively. The passivation film 47 is formed to expose the data pattern lines 45 on the gate insulation film 43. The contact electrodes 48 are formed on the exposed data pattern lines 45. The contact electrodes 48 can electrically connect the respective data-driving integrated circuits 25, 26, or 27 to the data pattern lines 45.
The first substrate 11 further includes an anisotropic conductive film (ACF) 49 having a plurality of conductive balls 50 and disposed on its non-display area 10. The data-driving integrated circuit 26 which includes bumps 31 and 33 is disposed on the ACF 49. When the data-driving integrated circuit 26 is depressed by pressure upon heat, the bumps 31 and 33 of the depressed data driver integrated circuit 26 in turn depress the ACF 49, and the ACF 49 is molten. Thus, the conductive balls 50 included into the ACF 49 are electrically connected to the contact electrodes 48.
However, it is well-known that adhesions between the ACF 49 and/or the conductive balls 50 and contact electrodes 48 are so bad. In addition, as shown in FIG. 4, as the time passes by, the ACF 49 is hardened. Thus, the ACF 49 including the conductive balls 50 is detached from the contact electrodes 48 such that the conductive balls 50 are not connected to the contact electrodes 48 any more. Therefore, contact defects are generated in contact areas of the input terminal portions and/or the output terminal portions of the data-driving integrated circuits 25, 26 or 27. The contact defects can be defined as dimensions in which the bumps 31 and 33 overlap with the contact electrodes 48, respectively.
Furthermore, it is well-known that adhesions between the contact electrodes 48 and the data pattern lines 45 are comparatively bad. Contact defects are further generated in contact areas of the input terminal portions and/or the output terminal portions of the data-driving integrated circuits 25, 26 or 27.
Due to this contact defect, a contact resistance between the bump 31 or 33 of the data-driving integrated circuit 26 and the contact electrode 48 increases. Accordingly, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, as well as the gamma voltage, the data signal, and the control signal vary due to the increased contact resistance. For instance, voltage levels of the power signals VDD and VCC decreases, whereas voltage levels of the power signals VDD_gnd and VCC_gnd increases. The power signals VCC and VCC_gnd are used to drive each data-driving integrated circuit 25, 26 and 27, and the power signals VDD and VDD_gnd are used as reference voltages for generating the gamma voltage.
As shown in FIG. 5, in the case where the power signals VCC and VCC_gnd are set at voltages of “2.7” and “0” according to design specifications (or standards), the power signal VCC drops to a voltage of “2.6” but the power signal VCC_gnd rises to a voltage of “0.4” when the contact resistance between the contact electrode 48 and the bump 31 or 33 of the data-driving integrated circuit is increased. As such, the margin width of VCC (i.e., a voltage difference between VCC and VCC_gnd) reduces from a voltage of “2.7V” down to a voltage of “2.2V”. The data-driving integrated circuit 26 is then not driven due to the reduced margin width.
More specifically, contact defects can be generated at the input terminal portions and the output terminal portions of the data-driving integrated circuits 25 to 27, which are cascaded to one another and have a margin width with a voltage of “2.3”. In this case, the margin width between the power signal VCC and the power signal VCC_gnd is increasingly reduced according to the procession of from the first data-driving integrated circuit 25 to the last data-driving integrated circuit 27. As such, the last integrated date driver circuit 27 and other data-driving integrated circuits (for example, a middle data driver integrated circuit 26) adjacent to it are not driven and no data voltages are applied to portions of the display area 9 opposite to the last integrated date driver circuit 27 and other adjacent data-driving integrated circuits 26. This can cause a block noise.
In addition, the increased contact resistance forces the power signal VDD to be lowered and the power signal VDD_gnd to be higher. This causes the generation of varied gamma voltages instead of the desired gamma voltages. The varied gamma voltages generate variations in the data voltages output from the data-driving integrated circuits 25 to 27, thereby causing a gray distortion. Such a gray distortion is more serious according to the procession of from the first data-driving integrated circuit 25 to the last data-driving integrated circuit 27. To rectify this, the gray distortion is generated on the data lines of the display area, which are connected to the last data-driving integrated circuit and the adjacent data-driving integrated circuits, due to the variation of the power signals VDD and VDD-gnd by the contact defect, resulting in a picture defect such as block dim is caused.
The contact defect is also generated between the bump 31 or 33, the data-driving integrated circuit 26 and the data line 23. The data voltage applied from the data-driving integrated circuit 26 to the data line 23 is distorted due to the contact defect.
In view of these points, it is necessary to fundamentally prevent the contact defect.
USPTO Backgrounds
USPTO Backgrounds