The generation of the physical layout of a semiconductor device having MOSFETs (metal oxide semiconductor field effect transistors) formed on a semiconductor substrate is a challenging task. An extensive amount of time and resources are spent during the creation of the physical layout. However, the effort can be reduced if new physical layouts utilize substantial portions of existing physical layouts. For example, a new physical layout comprising body-biased MOSFETs would consume fewer resources if an existing physical layout comprising MOSFETs without body biasing is utilized and modified according to the needs of the new physical design.
Unfortunately, this process of modifying the existing physical layout typically requires forming one or more additional routing layer(s) for the body biasing voltage(s) on the surface of the semiconductor device, creating a serious issue as the existing physical layout typically utilizes most if not all, of the available surface area. Additionally, it is highly desirable to accommodate the use of such a modified semiconductor device in applications designed for the unmodified (prior) semiconductor device. Consequently, it would be advantageous to provide a mechanism to vary the body voltage applied within such an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds