1. Field of the Invention
The present invention relates to a memory device and a system incorporating same. More particularly, the invention relates to a system and related memory device wherein the memory device has alternative bit organizations selectable by a system central processing unit (CPU).
2. Description of the Related Art
Within various contemporary systems, various memory devices are configured for use with the system's central processing unit (CPU). That is, one or more volatile memory devices, such as dynamic random access memory (DRAM) and/or static random access memory (SRAM) may be configured for use with the CPU. Additionally or alternatively, one or more nonvolatile memory (NVM) devices, such as NAND type flash memory and/or NOR type flash memory, may be configured for use with the CPU.
Many different memory system architectures may be configured in this manner. For example, one system configuration of note includes a low power dual data rate (LPDDR) nonvolatile memory (NVM) configured to share a common bus with a DRAM. This type of system configuration is becoming a de facto standard of sorts for many mobile electronic devices. U.S. Pat. No. 6,721,212 describes this configuration and related design and implementation aspects in some additional detail and is hereby incorporated by reference.
Figure (FIG. 1 is a block diagram of a conventional system configuration including a NVM and a DRAM connected to a CPU via a common bus. In the system shown in FIG. 1, a first data bus (DQ0-15 or DQ0-31) associated DRAM 11 and a second data bus DQ′0-15 associated with NVM 13 are separately connected to CPU 15. Additionally, a command/address bus CMD/ADD is shared by both DRAM 11 and NVM 13. A first chip select signal CS0 is applied to DRAM 11 and a second chip select signal CS1 is applied to NVM 13.
Since the first data bus (DQ0-15 or DQ0-31) associated with DRAM 11 and the second data bus DQ′0-15 associated with NVM are separate in the system shown in FIG. 1, it is possible to access both DRAM 11 and NVM 13 simultaneously and thus there is an advantage of improved system performance.
However, in a case where the first data bus associated with DRAM 11 is configured as an X32 bit data bus (DQ0-31), there is a drawback of increased cost due to an increased number of bus signal lines and related Input/Output (I/O) pins within the system.
FIG. 2 is a block diagram of another conventional system configuration comprising a NVM and a DRAM. In the system shown in FIG. 2, both a data bus DQ0-15 and a command/address bus CMD/ADD are shared by a DRAM 21 and a NVM 23. That is DRAM 21 and NVM 23 are connected to CPU 25 via data bus DQ0-15 and the command/address bus CMD/ADD. Here again, the first chip select signal CS0 is applied to DRAM 21 and the second chip select signal CS1 is applied to NVM 23.
Since the data bus DQ0-15 is shared between DRAM 21 and NVM 23, it is impossible to access DRAM 21 and NVM 23 simultaneously. Thus, there is a drawback of decreased overall system performance.
However, since the data bus is configured with a preset width of X16 bits (DQ0-15) and this data bus is shared by DRAM 21 and NVM 23, significantly fewer data bus signal lines and related I/O pins are required in the system.
USPTO Backgrounds
USPTO Backgrounds