1. Field of the Invention
The present invention relates to an insulated gate field effect transistor (herein after refer to as an insulated gate FET or an FET) and its manufacturing method.
2. Description of the Prior Art
Heretofore there has been proposed an insulated gate FET of the type that it has a high resistivity semiconductor layer formed on a substrate having an insulating surface, a gate electrode formed on the semiconductor layer with a gate insulating layer sandwiched therebetween in a manner to divide the semiconductor into two as viewed from above, and N or P conductivity type source and drain regions formed in the semiconductor layer in a manner to leave a channel forming region between first and second regions on both sides of the gate electrode as viewed from above, the source and drain regions being lower in resistivity than the channel region.
The insulated gate FET of such a construction is called an N-channel type or P-channel type insulated gate FET depending upon whether the source and drain regions are the N or P conductivity type, and it operates in such a manner as follows:
When supplied with a control voltage across the source region and the gate electrode with a DC power source connected across the source and drain regions via a load, the insulated gate FET remains in the OFF state if the control voltage is lower than a certain threshold voltage when the FET is the N-channel type, or if the control voltage is higher than the threshold voltage when the FET is the P-channel type. In this case, substantially no current flow (drain current) is caused in the drain region, supplying no current to the load. In the case where the control voltage is higher than the threshold voltage when the FET is the N-channel type, or where the control voltage is lower than the threshold voltage when the FET is the P-channel type, however, a channel region of the same conductivity type as that of the source and drain regions is formed in the channel forming region to extend between the source and drain regions on the side of the gate insulating layer, and the FET is turned ON to cause the drain current to flow, feeling current to the load
As a modification of the above insulated gate FET has been proposed such a structure that the entire region of the semiconductor layer is formed of a single-crystal semiconductor, and accordingly, the channel forming region, the first and second regions and the source and drain regions formed therein, respectively, are all formed of the single-crystal semiconductor.
With such an insulated gate FET, however, the semiconductor layer cannot be formed on the substrate unless the substrate is made of an insulating or semi-insulating single-crystal semiconductor.
when the semiconductor layer is formed of the single-crystal semiconductor layer, especially when the channel forming region is formed of the single-crystal semiconductor, it has a smaller optical energy gap than does it when formed of a non-single-crystal semiconductor. For example, when the semiconductor layer is made of the single-crystal silicon, the optical energy gap of the channel forming region is 1.1 eV. On account of this, when the FET is in the OFF state, the drain current is small but larger than in the case where the channel forming region is formed of the non-single-crystal semiconductor.
For this reason, the abovesaid insulated gate FET is poorer in the OFF characteristic than in the case where the channel forming region is made of the non-single-crystal semiconductor.
Another modified form of the above insulated gate FET heretofore proposed has such a structure that the entire region of the semiconductor layer is formed of a non-single-crystal semiconductor doped with a recombination center neutralizer.
In the case of such an insulated gate FET, even if the substrate is not made of the insulating or semi-insulating single-crystal semiconductor, and even if the substrate is a metallic substrate which has an insulated surface, or such as a glass, ceramic, organic synthetic resin or like insulating material substrate, the semiconductor layer can be formed on the substrate. Further, since the channel forming region is made of the non-single-crystal semiconductor doped with a recombination center neutralizer, it has a larger optical energy gap than in the case where it is formed of the single-crystal semiconductor, so long as it is sufficiently doped with the recombination center neutralizer. For instance, when the semiconductor layer is formed of non-single-crystal silicon well doped with the recombination center neutralizer, the channel forming region has an optical energy gap in the range of 1.7 to 1.8 eV. In consequence, when the insulated gate FET is in the OFF state, the drain current will be markedly small, negligible as compared with that when the channel forming region is formed of the single-crystal semiconductor. Accordingly, so long as the semiconductor layer is sufficiently doped with the recombination center neutralizer, the FET will exhibit a more excellent OFF characteristic than does it when the channel forming region is made of the single-crystal semiconductor.
In the case of such an insulate gate FET having the semiconductor layer formed of the non-single-crystal semiconductor, impurity-doped regions are formed in the first and second regions, for example, by ion implantation of an N- or P-type impurity, and then the source and drain regions are formed by heat treatment for the activation of the impurity doped in the impurity-doped regions. During the heat treatment, however, the recombination center neutralizer doped in the channel forming region is diffused therefrom to the outside by the heat. Therefore, the channel forming region contains no required and sufficient amount of recombination center neutralizer, and hence has a smaller optical energy gap than the predetermined.
Accordingly, the conventional insulated gate FET with the semiconductor layer formed of the non-single-crystal semiconductor possesses an excellent OFF characteristic as compared with the case where the channel forming region is made of the single-crystal semiconductor, but the OFF characteristic is not fully satisfactory.
Moreover, in the case of the above prior art insulated gate FET of the type having the semiconductor layer formed of the non-single-crystal semiconductor, since the source and drain regions are also obtained by heat treatment, the recombination center neutralizer doped therein is diffused to the outside during the heat treatment. Thus, since the source and drain regions have the same optical energy gap as that of the channel forming region, there is set up between each of the source and drain regions and the channel forming region substantially no or very small potential barrier against carriers flowing from the source or drain regions toward the channel forming region.
This is another cause of the unsatisfactory OFF characteristic of the conventional insulated gate FET which has the semiconductor layer formed of the non-single-crystal semiconductor.
Besides, when the semiconductor layer, and accordingly the source and drain regions are formed of the non-single-crystal semiconductor, they has the same degree of crystallization as that of the channel forming region and a far higher resistance than in the case where they are made of the single-crystal semiconductor. On account of this, in the conventional insulated gate FET of the type having the semiconductor layer formed of the non-single-crystal semiconductor, the speed of switching between the ON and the OFF state is lower than in the case where the source and drain regions are formed of the single-crystal semiconductor. Accordingly, this FET has the defect that its ON-OFF operation cannot be achieved at high speed.
USPTO Backgrounds
USPTO Backgrounds