1. Field of the Invention
The present invention relates to an overcurrent limiting circuit, an overcurrent limiting method, and a power supply circuit.
2. Description of the Related Art
A constant-voltage power supply circuit supplies a constant voltage stably even when an output current changes due to a load fluctuation or the like.
However, when the load fluctuation is large and a current flows beyond the rated value, e.g., in a case of occurrence of a ground fault, etc., there is a need to prevent damage to the transistor at an output stage (hereinafter output stage transistor) of the power supply caused by heat which is generated by an overcurrent.
The constant-voltage power supply circuit is thus required to have an overcurrent limiting circuit which limits the maximum output current so as not to exceed an upper limiting value defined as the rated value (refer to, for example, Japanese Patent Application Laid-Open No. 2009-48362).
In Japanese Patent Application Laid-Open No. 2009-48362, there is provided an overcurrent limiting circuit illustrated in FIG. 8 which suppresses lowering of a gate voltage V1 of an output stage transistor 105 upon grounding of an output terminal 102 to thereby limit an overcurrent flowing through the output stage transistor 105. Adjusting a limit voltage V3 limiting the overcurrent flowing through the output stage transistor 105, based on an output voltage Vout or a feedback voltage VFB, the overcurrent limiting circuit suppresses the overcurrent flowing through the output stage transistor 105 according to the degree of the grounding of the output terminal 102. The output stage transistor 105 is a P-channel MOS transistor, and each of transistors M1 through M6 is an N-channel MOS transistor.
In FIG. 8, the transistor M4 through which a current of a constant current source 110 flows and the transistors M1, M2 and M3 construct a current mirror circuit. When the transistor M5 is in an on state, current also flows through the transistor M2, and hence the current flowing through the resistor 113 is the sum of drain currents of the transistors M1 and M2. When the transistors M5 and M6 are respectively in an on state, current also flows through the transistors M2 and M3, and hence the current flowing through the resistor 113 is the sum of drain currents of the transistors M1, M2, and M3. Thus, the current flowing through the resistor 113 is controlled in a multi-stage manner by controlling the transistors M5 and M6.
When the feedback voltage VFB falls below a threshold voltage of the transistor M6 along lowering of the output voltage Vout, the transistor M6 turns off so that no current flows through the transistor M3, and hence the current flowing through the resistor 113 lowers. Further, when the output voltage Vout lowers and falls below the threshold voltage of the transistor M5, the transistor M5 turns off so that no current flows in the transistor M2, and hence the current flowing through the resistor 113 lowers. When the output voltage Vout comes close to zero volt (0V) due to a ground fault or the like, the current flowing through the resistor 113 becomes only the drain current of the transistor M1, and hence the limit voltage V3 rises.
Further, a voltage V2 is controlled to follow the limit voltage V3 to thereby suppress a reduction in the gate voltage V1 of the output stage transistor 105 and hence limit the current of the output stage transistor 105.
USPTO Backgrounds
USPTO Backgrounds