The present invention relates to a duty correction circuit, and more particularly, to a duty correction circuit that is implemented as a digital-type duty correction circuit and is capable of reducing the layout area and current consumption.
In general, a duty correction circuit (DCC) detects duty errors of an external clock signal and corrects the external clock signal such that the duty rate of an internal clock signal of a semiconductor device such as a DRAM is maintained at 50%.
A semiconductor device such as a DDR SDRAM receives and transmits data in synchronization with the rising edges and the falling edges of an external clock signal. Therefore, data outputted from or inputted to such a semiconductor device must be aligned exactly with the rising or falling edges of the external clock signal.
The DDR SDRAM controls the output of data using a Delay Locked Loop (DLL) circuit or a Phase Lock Loop (PLL) circuit, both of which generate internal clock signals, in order to synchronize the data with the external clock signal.
When the duty rate (the ratio between a low pulse width and a high pulse width) of an external clock signal is distorted or when the duty rate of the data output control clock signal in a semiconductor device is distorted, the valid data window decreases in size and becomes problematic. Considering that signal integrity is optimal when the clock duty rate of a data output is 1:1, a duty correction circuit is necessary to correct any distorted duty rate.
Duty correction circuits are classified into analog duty correction circuits and digital duty correction circuits, as well as closed loop duty correction circuits and open loop duty correction circuits. A high percentage of analog duty correction circuits are classified as closed loop duty correction circuits.
Analog duty correction circuits are considered to be of high precision and are insensitive to changes in the Process Voltage Temperature (PVT). However, analog duty correction circuits are not suitable for high-speed operations because too much time is consumed in obtaining a clock signal with a duty rate of 50% since duty errors are detected by using capacitors.
Accordingly, in order to resolve this problem characteristic of analog duty correction circuits, a conventional phase mixer type digital duty correction circuit, as illustrated in FIG. 1, can be used. The conventional phase mixer type digital duty correction circuit allows high-speed operation but requires two DLLs (a first DLL and a second DLL) to align the external clock signal CLK and the inverted external clock signal CLKB, both of which are from an external clock signal, with the rising edges and to generate a rising clock signal CLK1 and a falling clock signal CLK2. For this reason requiring use of two DLLs, the conventional phase mixer type digital duty correction circuit requires a wide layout area and consumes a high level of current.
Also, the conventional phase mixer type digital duty correction circuit as shown in FIG. 1 forms two delay loops (a first delay loop and a second delay loop) through which the output of the phase mixer is fed back. The conventional duty correction circuit therefore depends on the DLLs (for example, the first and second DLLs), which is not desirable.
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