The scaling of CMOS technology provides denser and faster semiconductor devices. At the nanometer level, though, scaling is becoming ever more complex and difficult. Illustratively, to increase the integration density of semiconductor devices, the thickness of dielectric layers such as traditional SiO2 needs to be reduced. However, the reduction of the thickness of SiO2 layers results in diminishing reliability of the SiO2 layers as gate dielectrics. Therefore, in the continuous scaling of CMOS technology, the low-k dielectric SiO2 layer has been found to limit the capacitance of the semiconductor device.
Processes have thus migrated towards the use of higher-k dielectric materials in the dielectric stack. However, even the use of higher-k dielectric materials in the dielectric stack have its limitations; although, reduction of the thickness of the low-k interfacial layer (e.g., the layer between the high-k dielectric and the substrate, such as SiO2 or SiON) of higher-k dielectrics can further improve the effective k value of the entire dielectric stack. The methods to reduce the thickness of the low-k interfacial layer is the key for the scaling.
By way of illustrative example, a typical starting surface for a dielectric stack is an oxide material. The oxide material can be patterned using any conventional etching techniques such as diluted hydrofluoric acid (HF). After etching, the patterned oxide undergoes standard cleaning processes to remove organic resist and other contamination. For example, in a first standard cleaning process, e.g., SC1, the oxide layer is subject to, for example, NH4OH and deionized water in addition to hydrogen peroxide (H2O2). In another standard cleaning process, e.g., SC2, any additional organic contamination and metal contamination is removed from the oxide. In this standard cleaning process, the oxide layer is subject to HCl (acid), H2O2 and deionized water.
As an alternative, the oxide layer can undergo a piranha clean, which encompasses a mixture of sulfuric acid (H2SO4) and H2O2, which cleans organic residues from a surface of the oxide and substrate. Because the mixture is a strong oxidizer, it will remove most organic matter, and it will also hydroxylate most surfaces (add OH groups), making them extremely hydrophilic (water compatible). In any of these cleaning processes, the SiO2 layer (chemical oxide) will be formed after HF etching to about 5 Å to about 7 Å, which is currently the thinnest possible starting interfacial layer (IL) obtainable for scaling. The cleaning is followed by further oxidation, nitridation and annealing, which all end with a thicker interfacial layer. However, this interfacial layer will substantially decrease the effective k value of the gate dielectric stack.
There are two methods commonly used to eliminate the SiO2 layer to form no interfacial layer high-k dielectric on the substrate. In the first approach, HF etch is used to remove the SiO2 layer. However, there are several drawbacks by using this method. First, the surface, after HF etching, is terminated by hydrogen which is a poor surface for the deposition of a high-k film such as using CVD or ALD methods due to the inactive surface Si—H bonds. Second, the HF will affect other areas on the wafer causing structural damage or degradation. Surface reoxidation is another concern by using HF as a last processing step.
In alternative processes, the dielectric stack can be formed by depositing metal or metal oxide on the interfacial SiO2 and followed by annealing at high temperature to form graded high-k dielectric. By using this method, upon annealing, silicates develop at a significant level of Si (e.g., 10-15 at %), which may reduce the capacitance of the stack. In many cases, the SiO2 interfacial layer still exists after >900° C. anneal and cannot be fully graded. Further, once the metal-oxide layer is deposited, post-growth oxidation may be needed to reduce the leakage current when using metal to scavenge the SiO2 interfacial layer, which will also reduce the capacitance of the stack.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds