The present invention relates to a semiconductor device and a method of manufacturing the same. Particularly, the present invention is concerned with a technique applicable effectively to the manufacture of a semiconductor device (non-leaded semiconductor device) such as SON (Small Outline Non-leaded package) and QFN (Quad Flat Non-leaded package) wherein external electrode terminals are exposed to a mounting surface side without intentional projection thereof on a side of a package.
A lead frame is used in manufacturing a resin-sealed type semiconductor device. The lead frame is fabricated by patterning a metallic plate into a desired pattern by punching with use of a precision press or by etching. The lead frame has a support portion called tab or die pad for fixing a semiconductor element (semiconductor chip) thereto and plural leads whose front ends (inner ends) face around the support portion. The tab is supported by tab suspending leads which extend from a frame portion of the lead frame.
In manufacturing the resin-sealed type semiconductor device with use of such a lead frame, a semiconductor chip is fixed to the tab in the lead frame and electrodes on the semiconductor chip and front ends of the leads are connected with each other through electrically conductive wires, thereafter inner end sides of the leads, including the wires and the semiconductor chip, are sealed with an insulating resin to form a sealing body (package), and then unnecessary lead frame portions are cut off. Where required, the leads projecting from the sealing body are subjected to a forming work.
On the other hand, as a resin-sealed type semiconductor device manufactured by using a lead frame there is known a semiconductor device (non-leaded semiconductor device) wherein a single-side molding is performed for one surface of a lead frame to form a package and leads as external electrode terminals are exposed to one surface of the package without intentional projection thereof from the peripheral surface of the package. As semiconductor devices of this type there are known SON wherein leads are exposed to both side edges of one surface of a package and QFN wherein leads are exposed to four sides of a quadrangular package. There also is known a semiconductor device wherein an upper surface of a tab is exposed to an upper surface of a sealing body (see, for example, Patent Literature 1).
In Patent Literature 1 is disclosed a semiconductor package wherein lower surfaces of leads are exposed to the peripheral portion of a lower surface of a resin capsule (sealing body). According to the structure disclosed therein, lower surfaces of lead inner ends are half-etched and the half-etched surfaces and electrodes on a lower surface of a semiconductor chip are connected with each other through wires. Further, electrodes on the semiconductor chip and pads are electrically connected with each other through ground wires.
[Patent Literature 1]
Japanese Unexamined Patent Publication
No. 2002-134676
USPTO Backgrounds
USPTO Backgrounds