The manufacture of the integrated circuit is to form devices on a wafer and then the metallic stage of the integrated circuit is achieved. Consequently, the metallic stage is to form the contact holes on the active region of the devices and then deposit the metal layers to be filled into the contact holes.
In the stage of forming the contact holes of the integrated circuit, verniers of the integrated circuit are formed in this stage. The verniers of the integrated circuit are wide trenches on the substrate and are the alignment marks for the photolithography equipment. Please refer to FIG. 1, this drawing shows a cross-section's view of a substrate. On the substrate, a metallic structure is formed thereon. Firstly, a substrate 100 is provided. The substrate 100 is a semiconductor. The integrated circuit is manufactured in the substrate 100 and the integrated circuit is a semiconductor device or a logical circuit. Afterwards, a metal layer 110 is formed on the surface of the substrate 100 and an intermetal dielectric layer 120 is deposited on the metal layer 110. After the deposition, the intermetal dielectric layer 120 is etched back and the contact holes and verniers are then formed in the IMD layer 120. Also, the contact holes are the metal contact of the metal layer 110 and the verniers are the alignment marks of the integrated circuit for the photolithography stage.
Afterwards, a barrier layer 130 is deposited on the surface of the contact holes, vernier's region and IMD 120. A tungsten-metal layer is then formed on the surface of the barrier layer 130 and is etched back to remove part of the tungsten metal layer. The plugs 140 of the contact holes and the spacers 145 of the verniers are thus formed. Finally, an aluminum metal layer is formed on the surface and the metallic stage of integrated circuit is finished.
In the above structure, the verniers are the alignment marks for photolithography and the spacers are formed thereon. The tungsten spacers are easily peeled off in the etching stage of the tungsten metal so that the peeling part of the tungsten spacers can be the short between the cells of the integrated circuit.
Currently, the aligning method of the photolithography stages is a calculating procedure, which is to calculate the distances between the verniers. Referring to FIG. 2, this drawing shows two groups of the verniers and a top view of the verniers of the integrated circuit. One is vernier 200 and the other one is vernier 210. The aligning method of photolithography equipment is to calculate the distances between the vernier 200 and vernier 210. The black lines in FIG. 2 are gaps in the IMD 120. Referring to FIG. 3, this drawing illustrates the calculation of the alignment. In the aligning procedures, point A and point B are assigned on the vernier 200, and point C and point D are assigned on the vernier 210 initially. Afterwards the distance between point A and point C, and the distance between point A and point D, the distance between point B and point C, the distance between point B and point D are calculated. The aligning procedure is then finished following the distances checking.
Consequently, the verniers are necessary for manufacturing the integrated circuit. However, since the spacers of the verniers are very thin films. The peeling phenomena of the spacers is often happened after the etching of metal and deposition. Thus, a method of preventing the peeling phenomena is needed.
USPTO Backgrounds
USPTO Backgrounds