A cache comprises a memory that holds recently accessed data in order to speed up subsequent access to the same data. Caches are routinely deployed on microchips between processors and main memory for this purpose. More particularly, a cache generally includes a portion of memory made of high-speed Static Random Access Memory (SRAM), contrasted with the relatively slower and cheaper Dynamic Random Access Memory (DRAM) used for main memory. Caching is effective because most programs repeatedly access the same data or instructions. By keeping as much of this information as possible in SRAM, the computing device may avoid accessing the slower DRAM. A cache maintains tags, or index information, to manage whether data stored in entries of the cache is valid and among data in the main memory.
Some caches are built into the architecture of microprocessors. Such internal caches are often called Level 1 (L1) caches. Many computing devices also come with a relatively larger, external cache memory, called Level 2 (L2) caches. L2 caches are positioned between the CPU and the DRAM. Disk caching works under the same principle as memory caching, but instead of using high-speed SRAM, a disk cache uses conventional main memory. The most recently accessed data from the disk (as well as adjacent sectors) is stored in a memory buffer. When a program needs to access data from the disk, it first checks the disk cache to see if the data is there. Disk caching can dramatically improve the performance of applications, because accessing a byte of data in RAM can be thousands of times faster than accessing a byte on a hard disk.
In conventional systems, manufactures design the structure of a device's cache and associated hardware programming around an expected data flow, or traffic pattern. Data flow generally relates to an order or set of rules according to which data is processed. Communication protocols have different traffic flow patterns, and consequently, different data handling requirements for devices. For instance, Ethernet devices may require processing suited for a random distribution of packets, while the traffic pattern of a hard drive may be a more predictable stream of data.
As such, computing devices are conventionally designed to include a dedicated hash function configured to most efficiently parse the particular data flow associated with an expected protocol. A hash function is an operation that maps the addresses of the data from a main memory to the data entries of the cache. A device ideally uses a hash function tailored to the specific data format and sequencing of the traffic pattern to locate data and thereby meet most performance goals. For instance, a device with a Small Computer System Interface (SCSI) port may be configured with a particular hash function against the expectation of receiving Serial Bus Protocol data. Another computing device may be manufactured with a hash function configured to most efficiently receive data packets formatted according to a data flow associated with the Ethernet protocol.
Predicting what hardware should be used as the expected, critical data flow pattern has become increasingly complex. Cellular phones, audio and video file players, Personal Digital Assistants (PDA's) and other devices are routinely expected to handle increasing loads having different functions and features. Input/Output (I/O) microchips in such hybrid devices must manage memory in the face of a multitude of functions that include both video and audio streams, among others, each of which present a different data flow pattern. This industry trend is at odds with the fact that devices hardwired for a single, critical data flow.
The cache and hash function are consequently inefficient when exposed to data flows that stray from the particular, expected traffic pattern. For instance, a hash function under such conditions may point to only a small subset of a cache. An unacceptable amount of cache misses and other inefficiencies can result from the hash function not being specifically configured for the different traffic formats. As such, using the wrong hash function can seriously and detrimentally impact performance.
Microchip designers make some concessions to support different workloads. For instance, some microchips include caches with increased sizes, so that even a bad hash will work most of the time. This conventional remedy, however, forces each design to accept the performance loss on other types of workloads. Larger cache sizes additionally translate into increased manufacturing costs.
For at least these reasons, there exists a need for an improved method and system for managing a cache.
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