Multi-Chip Packages (MCPs) integrating multiple stacked semiconductor chips (such as DRAM devices) in a single package achieve higher density than individual chips packaged within dedicated packages.
U.S. Pat. No. 7,515,453 to Rajan describes an interface chip packaged with two or more DRAM die in a single package. The interface chip can communicate with multiple DRAM die over a shared data bus so that only a single die can be accessed at any given time. Alternately, each of the DRAM die may have a dedicated data bus to the interface die so that the multiple interfaces can be operated in parallel to provide higher bandwidth.
U.S. Pat. No. 7,386,656 to Rajan et al. shows a variety of configurations for stacked DRAM die with a buffer chip in the same package. The external command bus (address, control, and clock) may be buffered by the interface chip and provided on a common internal bus to all DRAM die, or it may be provided on separate internal busses to each DRAM die, or it may be provided on separate internal busses each to several DRAM die. The external data bus may be bidirectionally buffered by the interface chip and provided on a common internal bus to all DRAM die, or it may be provided on separate internal busses to each DRAM die, or it may be provided on separate internal busses each to several DRAM die.
Unfortunately, these and other prior art MCP implementations suffer from various drawbacks, including high power consumption. This can be problematic, particularly for mobile devices where battery power is a limited resource. It would therefore be desirable in the industry if an MCP with reduced power consumption could be devised.
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