Computer systems typically read and write data to and from a storage device in word units, each unit being made up of a multiple of eight bits (e.g., 16 bits).
Conventionally, in order to effectively use memory areas of the storage device when data made up of a number of bits equivalent to a fraction of the word unit are stored therein, the computer system packs the data into whole word units before writing.
A bit field manipulation circuit, such as that described in Patent Literature 1 and in Patent Literature 2. is an example of a device providing comparatively effective data packing to a computer system.
The bit field manipulation circuit described in Patent Literature 1 (hereinafter, bit field manipulation circuit A) performs bit field manipulation as indicated in FIG. 21.
As shown, bit field manipulation circuit A performs bit field manipulation operations on data A 2000 and B 2001, which are N-bit sequences input thereto. Data C 2002 is an N-bit sequence output from bit field manipulation circuit A upon performing the bit field manipulation operations.
When instructions indicating data A 2000, data B 2001, an offset length 2010, and a width 2011 are input thereto, the bit field manipulation circuit A performs bit field manipulation operations so as to generate data C 2002 by inserting a bit sequence that includes the least-significant bit of data B 2001 and is of width 2011 at a position within data A 2000 shifted leftward by the offset length 2010 from the least-significant bit position.
The bit field manipulation circuit described in Patent Literature 2 (hereinafter, bit field manipulation circuit B) performs bit field manipulation as indicated in FIG. 22.
As shown, bit field manipulation circuit B performs bit field manipulation operations on data A 2100 which is an N-bit sequence input thereto. Data B 2101 is an N-bit sequence output from bit field manipulation circuit B upon performing the bit field manipulation operations.
When instructions indicating data A 2100, an offset length 2110, and a shift length 2111 are input thereto, the bit field manipulation circuit B generates data B 2101 by inserting a bit sequence that includes the least-significant bit of data A 2100 and is of the length indicated by the offset length 2110 into the data A 2100 as logically shifted rightward by the shift length.
USPTO Backgrounds
USPTO Backgrounds