Research and development of commercially viable memory devices that are randomly accessed, have relatively low power consumption, and are non-volatile is ongoing. One ongoing area of research is in resistive memory cells where resistance states can be changed. One avenue of research relates to devices that store data in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied write voltages and/or current, which in turn changes cell resistance. For example, a memory controller may place a variable resistance material of a memory cell (sometimes referred to as phase change memory cells) into a crystalline phase by passing a crystallizing current through the variable resistance material, thus warming the variable resistance material of the memory cell to a temperature wherein a crystalline structure may grow. The memory controller may use a stronger melting current to melt the variable resistance material of the memory cell for subsequent cooling to the amorphous phase. The different phases of the variable resistance materials represent different binary values and allow the memory controller to write data to the memory cells.
However, writing to a memory cell may cause a write disturb phenomenon to neighbor memory cells (i.e., memory cells that are directly adjacent to a memory cell that is being written). In particular, writes to a memory cell may dissipate heat/thermal energy to neighbor memory cells. With sufficient accumulation of this heat/thermal energy from repeated writes (particularly over a relatively short period of time (e.g., 0-400 milliseconds) and/or with a high frequency), the states of neighbor memory cells are perturbed to the point that a memory controller may no longer be able to reliably determine the state of the neighbor memory cells (i.e., the memory controller may no longer be able to determine the binary value represented by a memory cell).
Further, changes to a physical property, or a phase change, of a memory cell is a transition. Within a population of memory cells, there exists a distribution of transition latencies. The tails/ends of this distribution is problematic as a clear set of read/demarcation voltages for reaching memory cells may be difficult to ascertain. Moreover, delaying accesses to accommodate the tails/ends of the distribution erodes the fundamental value proposition of phase change memory (i.e., read times may be lengthened). Consequently, writes may not only impact the ability to read neighbor memory cells (i.e., a write disturb phenomenon), but also the aggressor memory cell (i.e., resistivity drift).
USPTO Backgrounds
USPTO Backgrounds