A primary focus and application of the present invention is the field of radio frequency (RF) transmitters and power amplifier architectures capable of use in wireless telecommunication applications and particularly related to wide bandwidth, or instantaneous bandwidth (ISBW) signals for example when base stations simultaneously transmit multiple channels. Continuing pressure on the limited spectrum available for radio communication systems is forcing the development of spectrally-efficient linear modulation schemes. Since the envelopes of a number of these linear modulation schemes fluctuate, these result in the average power delivered to the antenna being significantly lower than the maximum power, leading to poor efficiency of the power amplifier. Specifically, in this field, there has been a significant amount of research effort in developing high efficiency topologies capable of providing high performances in the ‘back-off’ (linear) region of the power amplifier.
Linear modulation schemes require linear amplification of the modulated signal in order to minimise undesired out-of-band emissions from spectral re-growth. However, the active devices used within a typical RF amplifying device are inherently non-linear by nature. Only when a small portion of the consumed DC power is transformed into RF power, can the transfer function of the amplifying device be approximated by a straight line, i.e. as in an ideal linear amplifier case. This mode of operation provides a low efficiency of DC to RF power conversion. To achieve both linearity and efficiency, so called linearization techniques are used to improve the linearity of the more efficient amplifier classes, for example class ‘AB’, ‘B’ or ‘C’ amplifiers. A number and variety of linearizing techniques exist, which are often used in designing linear transmitters, such as Cartesian Feedback, Feed-forward, and Adaptive Pre-distortion.
The advent of deep-submicron CMOS has enabled the use of digital predistortion (DPD) techniques capable of compensating for non-linearity. In particular, DPD has enabled analog circuits and devices operating at low-current, with non-linear bias points to be employed. Such techniques are implemented at the cost of additional digital processing, but overall result in a net reduction on current consumption. Digital baseband predistortion circuits are typically located prior to the radio frequency amplifier stage(s) and arranged to compensate for the nonlinearity effects in the final amplifier stage(s), thereby allowing at least the final power amplifier stage to run close to its maximum output power whilst maintaining low spectral regrowth.
FIG. 1 illustrates a known circuit diagram 100, as shown in US2012/0154053 A1, for a power amplifier 110 that illustrates various energy storage elements (such as capacitors and inductors) whose electrical memory′ effects would affect the performance of a transmitter, should the power amplifier 110 be used in a DPD architecture. The circuit diagram 100 comprises an input network 120 comprising a pi-type arrangement of capacitors and inductors and an output matching network 130 that includes a blocking capacitor that forms part of a high quality factor radio frequency path of the output matching network 130. A bypass network that comprises a resistance-inductance-capacitance (R-L-C) arrangement 140 is coupled in parallel to the blocking capacitor to raise the resonant frequency of the envelope circuit and to attenuate any low frequency gain peak of a signal passing through the transmitter. The bypass network has a main function to increase the ISBW capability, by lowering the effective inductance seen at envelope frequencies, thereby raising the low-frequency resonance. The bypass capacitor Cbp in the R-L-C arrangement 140 is intended to act as a ground, and as such is a high-value capacitance all the way down to low frequencies.
Use of power amplifier circuits within a DPD architecture cause problems as the DPD algorithms use an initial assumption of the final amplifier stage(s) device(s) behavior, as well as knowledge of the device state in order to improve the final linearity of the PA after DPD correction. One of the challenges when designing DPD architectures is to correct so called ‘electrical memory’ effects of the circuits, particularly in high frequency, high power applications that employ multiple and various energy storage elements (such as capacitors and inductors). Such electrical memory effects are caused by energy storage elements that have to be charged or discharged, and where the residual charge affects the operational characteristic of the circuit that the energy storage element resides in. Such correction of electrical memory effects is considered to be a computational resource-intensive process.
USPTO Backgrounds
USPTO Backgrounds