The present invention relates generally to an apparatus and method for reducing the temperature gradient on a substrate, which may be an integrated circuit.
Cooling of electronic components is becoming increasingly significant. Performance of integrated circuit components has improved dramatically over the years. Both the clock speed and density of transistors on an integrated circuit have increased significantly. Coinciding with this increase in performance is the consumption of large amounts of power, which in turn increases the amount of heat dissipated by the integrated circuit. Failure to adequately conduct this heat away from the integrated circuit ultimately leads to reduced performance and reliability of the device.
Further complicating the cooling of electronic components is that often times power dissipation and distribution is not uniform over the die of an integrated circuit, thus generating temperature xe2x80x9chot spotsxe2x80x9d. For example, a microprocessor die may have distinct and separate areas for cache and switching. While a large amount of power is generated across the localized area of the die that performs switching, a relatively small amount of heat is generated across that portion of the die responsible for cache. As a result of this temperature gradient across an integrated circuit, signals across the die may propagate at different speeds, causing timing problems. To accommodate these timing problems, developers may be forced to reduce the temperature gradient across the die by slowing down the speed at which the integrated circuit runs.
Various cooling methodologies have been used historically to dissipate the heat generated by electronic devices. These include the use of heat sinks or cold plates, for example. Such devices typically have a planar bottom surface that makes thermal contact with the entire top surface of the integrated circuit. Consequently, the top surface of the integrated circuit is cooled in a generally uniform manner. Since design of a cooling system for an integrated circuit is typically based on the worst case surface temperature of the die, the existence of even a small number of hot spots on the die skew cooling requirements. These cooling requirements may not be achievable with these historic cooling methodologies, and typically result in a cooling implementation that is excessive for a large portion of the die.
In accordance with one embodiment of the invention, an active temperature gradient reducer is presented. The active temperature gradient reducer includes a heat dissipation structure having a contact surface. The contact surface encompasses an area for thermally contacting a substrate to be cooled. At least one thermoelectric device is incorporated into the heat dissipation structure, the thermoelectric device having at least one cooling surface for thermally contacting one or more subsections of the area.
In another embodiment of the invention, a method for actively reducing the temperature gradient of a substrate is presented. The method includes placing the substrate in thermal contact with a heat dissipation structure so as to dissipate heat from the substrate. A current is passed through a thermoelectric device incorporated into the heat dissipation device so as to provide cooling to at least one hot spot on the substrate.
In another embodiment of the invention, an active gradient temperature reducer includes a first means for dissipating heat thermally coupled to a substrate. A second means for dissipating heat is thermally coupled to at least one hot spot on the substrate, the second means for dissipating heat being thermoelectric.
USPTO Backgrounds
USPTO Backgrounds