1. Field of the Invention
The present invention relates to a semiconductor memory device having a refresh operation and its control method, and particularly relates to a semiconductor memory device able to realize the shortening of a refresh operation time by a low current consumption operation, and its control method.
2. Description of Related Art
In recent years, functions required in a portable device are increased as the portable device is spread. As a result, a semiconductor memory of larger capacity is required instead of a static random access memory (hereinafter abbreviated as an SRAM) conventionally mounted. Therefore, a DRAM having a refresh function therein and called a pseudo-SRAM begins to be used. In this DRAM, while highly integrated DRAM memory cells are used in comparison with an SRAM memory cell, no external control circuit of a refresh controller, etc. is required by building-in control relative to a refresh operation peculiar to the DRAM memory cell. The DRAM has a data access operation equal to that of the SRAM.
In the pseudo-SRAM, both a data access operation cycle externally controlled by setting a data access operation and a pre-charge operation subsequent to this data access operation to one-operation cycle, and a refresh operation cycle internally controlled by setting the refresh operation and a pre-charge operation subsequent to this refresh operation to one-operation cycle are independently executed at any time. Therefore, it is necessary that the refresh operation cycle concurs with the data access operation cycle, and the refresh operation cycle is interrupted in the continuous data access operation cycle. Namely, the refresh operation cycle is executed irrespective of the request of the data access operation cycle controlled by the exterior. Accordingly, it is necessary to shorten the refresh operation cycle to increase the speed of the data access operation or improve a data transfer rate.
Here, in the refresh operation cycle, the refresh operation is performed with respect to the memory cells corresponding to refresh address Add (I) outputted by a built-in address counter, etc. In the data access operation cycle, the data access operation is performed with respect to the memory cell corresponding to a data access address Add (O) inputted from the exterior.
FIG. 19 shows a prior art for shortening the refresh operation cycle. FIG. 19 shows a circuit block diagram having a redundancy judgment circuit 700c of a third embodiment disclosed in JP Laid-Open Patent Publication No. 11-120790. FIG. 19 shows a circuit block for selecting the data access address Add (O) or the refresh address Add (I), and supplying the selected address to an address decoder 300 through an address register 400.
The redundancy judgment circuit 700c has the following construction. The data access address Add(O) is inputted to an input terminal A of a selector circuit 760, and the refresh address Add(I) is inputted to an input terminal B. An internal command signal cpf is inputted to a selection-control-signal input terminal SB of the selector circuit 760. An output signal n00 of the selector circuit 760 is inputted to an accordance detector circuit 770 together with a redundant address. An output signal n100 of the accordance detector circuit 770 is inputted to an input terminal D of a flip-flop 780 and an input terminal A of a selector circuit 790. Operation timing of the flip-flop 780 is controlled in accordance with a clock signal CLK. The internal command signal cpf is also inputted to a load input terminal LD, and its output signal n200 is inputted to an input terminal B of the selector circuit 790. An internal command signal ref is inputted to the selection-control-signal input terminal SB of the selector circuit 790.
The address register 400 has the following construction. Each of the data access address Add(O) and the refresh address Add(I) is inputted to one end of a selection switch. Both the other ends of the selection switches are connected to a latch circuit constructed by an inverter gate, etc. An output from the latch circuit is connected to the address decoder 300 through an inverter gate for adjusting a logic level and arranged in accordance with necessity. The operation of the selection switch is controlled by an output signal of the redundancy judgment circuit 700c. 
FIG. 20 shows operational waveforms. When the internal command signal ref is changed to a high level after a first cycle of the clock signal CLK for starting the refresh operation cycle (Ref1) is started, the input terminal B of the selector circuit 790 is selected, and a signal n200 as the accordance detection result of a redundant judgment at an (A-1) address is outputted. In the case of the detection result in which the (A-1) address is not conformed to the redundant address, the operation of the selection switch of the address register 400 is controlled by the outputted signal n200 and an unillustrated control signal of a refresh operation mode, and the refresh address Add(I) is fetched.
After a second cycle of the clock signal CLK is started, the internal command signal ref is changed to a low level so that the selector circuit 790 is non-activated. Further, the internal command signal cpf is changed to the high level, and the input terminal B of the selector circuit 760 is selected. Thus, the refresh address Add(I) of the (A) address already counted up is fetched to the accordance detector circuit 770, and the accordance detection result is outputted as an output signal n100. The accordance detection result of the output signal n100 obtained at this time is a result with respect to the (A) address. This result is fetched to the flip-flop 780 in synchronization with the rise of a third cycle of the clock signal CLK. The accordance detection result of the refresh address Add(I) of the (A) address fetched to the flip-flop 780 is taken-out after the first cycle of the clock signal CLK as a starting cycle of the refresh operation (Ref2) of the next cycle is started.
Here, the internal command signal cpf is a signal for controlling which address of the data access address Add(O) and the refresh address Add(I) is selected in the redundancy judgment circuit 700c. In a low level state, the data access address Add(O) is selected. In a high level state, the refresh address Add(I) is selected. Accordingly, the internal command signal cpf is a signal for performing signal transition approximately in synchronization with each operation cycle. Namely, the internal command signal cpf is set to the low level state in the data access operation cycle, and is set to the high level state in the refresh operation cycle.
The accordance detection with the redundant address is performed prior to one-operation cycle with respect to the refresh address Add(I) provided by the refresh operation, and no accordance detection operation is performed at a refresh operation cycle time.
However, in the prior art shown in FIGS. 19 and 20, the selection switch within the address register 400 is selected by the high level transition of the internal command signal ref after the refresh operation is started. The address path of the refresh address Add(I) to the address register 400 is then established. Therefore, the rewriting of a latch section within the address register 400 is performed after there fresh operation is started. In a semiconductor memory such as the pseudo-SRAM, etc. having an operation specification in which the data access operation mode and the refresh operation mode are independently required, there is a case in which the data access operation cycle is set before the refresh operation cycle is started. In this case, it is necessary to perform the switching operation of the selection switch. No latch operation of the refresh address Add(I) to the address register 400 can be precedently performed although the refresh address Add(I) in the refresh operation cycle of the next cycle is precedently decided. Accordingly, a problem exists in that no time of the refresh operation cycle can be shortened.
When an operation request of the refresh operation mode and an operation request of the data access operation mode are simultaneously generated, the data access operation cycle is performed after the termination of the refresh operation cycle in the operation specification for preferentially performing the refresh operation cycle. Since no refresh operation cycle is shortened, a problem exists in that no data access time is shortened and no data access at high speed can be realized. Further, a cycle time constructed by the refresh operation cycle and the data access operation cycle as one pair, and a cycle time constructed by the refresh operation cycle and continuous plural data access operation cycles as one set cannot be shortened when the case of an operation specification for preferentially executing the data access operation cycle is included. Accordingly, a problem exists in that no data transfer rate can be improved.
In the flip-flop 780 of the redundancy judgment circuit 700c, the internal command signal cpf changed to the high level is received after the rise of the clock signal CLK of the second cycle in the refresh operation cycle (Ref1), and the fetch operation of the signal n100 is repeatedly performed every rising transition of the clock signal CLK of third to ninth cycles during a refresh operation period. In the refresh operation, the activation of a word line, the differential amplification of a bit line pair, the subsequent non-activation of the word line, and equalization of the bit line pair are performed. At this time, many memory cells are connected to the word line and the bit line to be operated, and wiring length is very long. Therefore, a large amount of load capacity must be charged and discharged as the sum total of parasitic capacity and wiring capacity, and a peak electric current at charging and discharging times becomes large. Since the fetch operation of the signal n100 is repeatedly performed, the possibility that the accordance detector circuit 770, the flip-flop 780, etc. are badly influenced by changes in power voltage, ground voltage, etc. due to the large peak electric current becomes large. Accordingly, changes in voltage level of the signal n100 and circuit threshold value level are caused. Therefore, a problem exists in that there is a fear of the generation of an error latch to the flip-flop 780.
In the prior art, to perform the data access operation at high speed, the internal command signal cpf becomes the low level in a pre-charge period (PRE) (the ninth cycle of the clock signal CLK) after the refresh operation cycle (Ref1) is terminated. The selector circuit 760 is changed to the selecting state of the data access address Add(O). The internal command signal ref is also maintained in the low level state. Thus, if discordance is detected in the accordance detector circuit 770, the data access address Add(O) is latched to the address register 400 through the selector circuit 790. However, the effective data access address Add(O) is inputted after the data access operation cycle is started. Hence, the data access address Add(O) in this case is not effective address information. Accordingly, when the next cycle is the data access operation cycle or the refresh operation cycle (Ref2) (see FIG. 20), it is necessary to rewrite the latch information of the address register 400 and again perform the accordance detection in the accordance detector circuit 770. The unnecessary accordance detecting operation with the redundant address and the address latch operation are performed by the invalid data access address Add(O) inputted during the effective operation period. Therefore, a problem exists in that no electric current consumption can be reduced. The unnecessary electric current consumption is inevitably increased by increases in address bit number and redundant construction. This problem is increasingly caused as an increase in capacity is developed.
Further, a semiconductor memory having a so-called thinning-out refresh function is proposed. In this semiconductor memory, a memory cell having preferable data storing characteristics is set such that no refresh operation is performed every refresh request, and one refresh operation is performed every predetermined number of times. The consumed electric current at the refresh operation time is reduced by reducing the number of refresh operation times per predetermined time. However, in the prior art, the accordance detection operation with the redundant address is also precedently performed with respect to the refresh address Add(I) at which the thinning-out is performed and no refresh operation is performed. Accordingly, a problem exists in that no electric current consumption can be reduced by the unnecessary circuit operation. Further, a problem also exists in that the unnecessary circuit operation is increased since the redundant construction is increased as the increase in capacity is developed.
USPTO Backgrounds
USPTO Backgrounds