1. Field of the Invention
The present invention relates to an improvement in a BBD (bucket brigade device) type charge transfer device.
2. Description of the Prior Art
The most simple prior BBD type charge transfer device is constituted, as shown in the equivalent circuit diagram of FIG. 1, wherein each unit cell comprises charge transfer MOS field effect transistors (hereinafter referred to as MOSFET) 1, 2 or 3 having a capacitance C.sub.b1, C.sub.b2 or C.sub.b3 between the gate and the drain. The unit cells are connected in series, and two-phase clock pulses .phi..sub.1 and .phi..sub.2 are impressed on the gates of odd order MOSFETs and even order, respectively.
As a BBD, wherein charge transfer efficiency in the low clock frequency region is improved without changing the total channel length of the charge transfer MOSFETs, what is called high transfer efficiency type BBDs having the following two configurations are well known in general.
The first high transfer efficiency BBD, as shown in the equivalent circuit diagram of FIG. 2, besides forming capacitances C.sub.b1, C.sub.b2 and C.sub.b3 between the gate and the drain of the charge transfer MOSFETs 1, 2 and 3, respectively, comprises a DC bias V.sub.GG impressed between the drain and the source of neighboring MOSFETs 1 and 2 or 2 and 3, through auxiliary MOSFETs M.sub.1, M.sub.2, . . . the gate of which is impressed with the DC bias V.sub.GG. The second high transfer efficiency BBD has the equivalent circuit diagram of FIG. 3 when the charge transfer MOSFETs 1, 2 and 3 are made in a two-gate construction, the first gate and the second gate are formed by the superposing of polycrystalline silicon film(s) or shadow etching of an aluminum electrode, thereby forming a capacitance C.sub.b1 between the first gate G.sub.1 (which is a charge transfer gate) neighboring the next drain and the said next drain. Therefore the drain and the source of the MOSFETs are connected in series. DC bias V.sub.GG is impressed on the second gate G.sub.2 (which is an auxiliary gate) neighboring to the source.
In the above-mentioned two types of high charge transfer efficiency type BBDs, the charge transfer efficiency is greatly improved in comparison with the conventional simple BBD such as shown in FIG. 1, but another driving power source V.sub.GG becomes necessary in the circuits of FIG. 2 and FIG. 3.
The reason that the conventional high charge transfer efficiency type BBD requires such a driving power source V.sub.GG is elucidated in detail taking a P-channel MOS type BBD as one example.
In the first conventional type high charge transfer efficiency type BBD, each MOSFET must be in the saturation state at the time of each finishing of the charge transfer. FIG. 4 is a schematic potential diagram for optimum operation of the BBD of FIG. 2, showing node potentials at the finishing of charge transfer, and the positions a, b, c, d, e, f, g, h, i and j respectively correspond to the points designated by the same marks in FIG. 2. As is shown in FIG. 4, the potential of the part under the MOSFET M.sub.1 is higher than that of the part under the MOSFET 2, and therefore the charge transfer is made efficiently. Transfer inefficiency R.sub.i is given by ##EQU1## where C.sub.b is the capacitance value of capacitance Cb.sub.1, Cb.sub.2 and Cb.sub.3,
C.sub.s is the stray capacitance value of the diffusion area between the MOSFET 1 and MOSFET 2, and PA0 .beta. is the transfer inefficiency in each MOSFET M.sub.1 and MOSFET 2. PA0 power source voltage . . . -15 V PA0 clock pulse low level voltage . . . -15 V PA0 clock pulse high level voltage . . . 0 V PA0 clock frequencies . . . 40 KHz, 100 KHz and 200 KHz.
The transfer inefficiency R.sub.i is given as a sum of (i) transfer inefficiency due to remaining of the transfer charge in the capacitance C.sub.b (representative of C.sub.b1, C.sub.b2 . . . ) given by ##EQU2## and (ii) transfer inefficiency due to remaining of the transfer charge in the stray capacitance C.sub.s given by ##EQU3##
FIG. 5 is a schematic potential diagram similar to the diagram of FIG. 4, for non-optimum operation of the BBD of FIG. 2, showing each anode potentials at the finish of charge transfer. In this case, as is well known, the incomplete ratio is .beta.. This means that, this case is equivalent to that where the potentials under the MOSFETs M.sub.1 and 2 are the same or where there is no MOSFET M.sub.1 provided. Accordingly, when the MOSFETs M.sub.1, M.sub.2 . . . , impressed with a DC bias at the gates, and the other MOSFETs 1, 2, 3 . . . , impressed with the clock pulse at the gates, are formed so as to have the same characteristics, then the gate bias voltage V.sub.GG impressed on the MOSFETs M.sub.1, M.sub.2 . . . must be smaller than the gate voltage V.sub.CPL of the MOSFETs 1, 2, 3 . . . , in order to attain improvement of the transfer efficiency. (in this case, since V.sub.CPL is a negative voltage, the actual relation must be .vertline.V.sub. GG .vertline.&lt;.vertline.V.sub.CPL .vertline..) In ordinary cases, the optimum condition is that .vertline.V.sub.GG .vertline. is almost equal to ##EQU4##
FIG. 6 shows the measured relations between values of the transfer efficiency and V.sub.GG of a P-channel type BBD under the condition that:
As is induced from the relations of FIG. 6, the secondary power source for .vertline.V.sub.GG .vertline. is needed besides the power source for the clock pulse .vertline.V.sub.CPL .vertline., and the former must be lower than the latter, in order to retain high transfer efficiency.
The same elucidation as above applies to the improved conventional circuit of FIG. 3.
USPTO Backgrounds
USPTO Backgrounds