The present invention refers to new techniques for taking advantage of the properties of certain known types of integrated circuits to obtain level shifts in binary data signals. In particular, it is known that the majority of very low power logic families of integrated circuits--such as complementary metal oxide semiconductor (C.MOS) or complementary symmetry C.MOS (COS/MOS) have wide range tolerances of recognition of logic one and zero signals which might suffer variations during use, thus providing high noise immunity.
These tolerances are exemplified by the following discussion of C.MOS circuits. Most standard C.MOS circuits operated between power supply potentials of V.sub.dd and V.sub.ss which vary from V.sub.dd -V.sub.ss =3 volts to V.sub.dd -V.sub.ss =15 volts or even 18 volts (see "Focus on C.MOS" by Edward Torrero, Electronic Design C, Mar. 15, 1974) or 20 volts. The logic output levels are substantially V.sub.dd and V.sub.ss, respectively, and any variations are so small as to be negligible. The logic input levels, however, may vary typically up to 30% and maximally up to 45% from the nominal values. Consequently logic input levels as low as V.sub.dd -0.3 (V.sub.dd -V.sub.ss) and as high as V.sub.ss +0.3 (V.sub.dd -V.sub.ss) are still recognized by a given integrated circuit as logic one and logic zero, respectively. When the logic input levels are between these two values, there is an intermediate region which should not be used. It should be emphasized that most known circuits work well with less noise immunity than the one mentioned.
For logic input levels, however, which exceed V.sub.dd or are less than V.sub.ss, there is a range of K volts through which the circuit can still satisfactorily operate. As a result, the following conditions define the permissible logic levels: EQU V.sub.dd +K.gtoreq.logic 1.gtoreq.0.7V.sub.dd +0.3V.sub.ss ( 1) EQU 0.7V.sub.ss +0.3V.sub.dd .gtoreq.logic 0.gtoreq.V.sub.ss -K (2)
"K" is a constant given by the manufacturer and for the particular type of integrated circuit being used throughout this specification, K=15 volts which means that all the C.MOS integrated circuits of the particular family and manufacturer can handle +15 V input signals beyond the logic levels defined without risk of damage.
It should be emphasized that the above information and equations represent the characteristics of known integrated circuits, as supplied by the manufacturers to define their noise immunity and their flexibility in terms of power supply potentials but that, to applicant's knowledge, they have not been used in the manner that will be described in this specification.
The above information has been considered by applicant in particular, although not exclusive, relation to the power consumption problem of luminous display circuits. Although the types of integrated circuits used in modern luminous displays belong in the most part to the very low power logic families, they are used to drive multi-segment Light Emitting Diodes (LED's) or other relatively high power consumption indicators. Thus we have that a typical C.MOS integrated circuit has a negligible power consumption in the order of microwatts whereas, depending on the brightness required, the current requirements of a typical LED vary between 2 mA/segment and 20 mA/segment for a forward voltage of typically 1.7 volts. Consequently a LED display system consisting of only four parallel connected seven segment LED's would typically consume (7.times.10).times.4=280 mA, or a maximum of 560 mA. It is, however, common to use up to ten or more LED's, for example in digital counter applications, resulting in much higher power consumption (up to 1.5 A). This higher consumption is so serious that very often, especially in portable instrument design, LED displays are not used. The use of LED's, however, results in higher precision readout and better visibility than any other known type of analog display or indicator or liquid crystal system that needs an external light source.
One way to limit the power consumption of single segment LED's (one anode, one cathode) is given by C. D. Patterson in "Driving LED's directly from C.MOS logic outputs" published in Electronics, page 116, July 25, 1974, in which a bipolar transistor between a C.MOS logic output and a LED indicator is used to control the latter. The bipolar transistors are connected in series so that the same current drives several LED's each of which is tied between the emitter and collector of the transistors.
USPTO Backgrounds
USPTO Backgrounds