This invention relates to electronic accounting systems, and is especially directed to an electronic postage meter having a microprocessor controlled electronic accounting unit with non-volatile random access memory.
An electronic postage meter having an accounting unit with a microprocessor, and nonvolatile memory for storing accounting data, is disclosed, for example, in U.S. Pat. No. 4,301,507. In this system the accounting data is stored in the random access memory and retrieved from the random access memory by way of common address and data lines of the microcomputer system. While in most instances it can be assured that the accounting data stored in the memory will be correct, there are certain conditions that can occur that can result in nondetectable errors in the data.
In order to overcome such problems, it has been proposed to employ redundant memories. The microprocessor program for the postal meter thus includes a subroutine for comparing the data stored in the redundant memories, to provide an error indication if the stored data in the two memories is different. While this technique increases the reliability of the stored data, there are certain conditions in which even this type of a redundant system will not enable the determination of an error. It must, of course, be emphasized that, in a postage meter, it is essential that the highest degree of reliability of the accounting data be obtained.
The present invention is therefore directed to the provision of an electronic postage meter having redundant memory in the nonvolatile accounting memory wherein the possibility of error conditions that are not detectable is minimized.
Briefly stated, in accordance with one aspect of the invention, redundant nonvolatile memories are provided in the accounting unit of an electronic postage meter, the accounting unit having a microprocessor controlled to store accounting data redundantly in the two memories. In order to minimize the possibility of nondetectable errors, the two redundant memories are interconnected with the microprocessor, i.e., the microcomputer bus, by way of entirely separate groups of data and address lines. As a result of the complete separation of the addressing and data, various error conditions, such as the shorting of a pair of address lines, will not result in the erroneous addressing of both of the memories. Accordingly, under such conditions, the shorting of a pair of address lines will not result in the storage of the same data in both of the memories, so that a comparison of stored data will result in the detection of the error condition.
In accordance with a further embodiment of the invention, corresponding data is applied redundantly to the redundant memories at different times. This may be effected by separately applying the data sequentially to the two memories. Alternatively, data may be simultaneously applied to or retrieved from the two memories, with the data transferred at any instant with respect to the two memories corresponding to different information. As a result, instantaneously occurring transients on the transmission lines will not be likely to affect the corresponding data stored in the two memories in the same fashion. This system thereby minimizes the possibility of nondetectable and/or noncorrectable errors resulting from transients.
In accordance with a still further embodiment of the invention, the redundancy of the accounting system may be increased by also employing redundant microprocessors for controlling the two memories.
In order to still further minimize the possibility of printing postage without accounting, the program of the microprocessor may be directed to the periodic testing of various critical parameters within the microprocessor, as part of a main routine, the testing routine only being interrupted, if necessary, during a conventional postage printing operation such as the printing of postage and accounting therefor. As a consequence, the routine of the postage meter enables the continuous testing of such parameters, so that the postage meter may be disabled as soon as a condition exists that threatens the integrity of the accounting data. The error checking on a periodic basis may test not only the physical parameters, such as positions of various mechanical elements, but also may effect the comparison of the data stored in the two memories, as well as performing control sum checks to determine if the data stored in each memory is in accordance with determined relationships.
USPTO Backgrounds
USPTO Backgrounds