1. Field of the Invention
The present invention relates generally to multilayer interconnection substrates and methods of manufacturing the same, and more particularly to a multilayer interconnection substrate in which interconnection patterns formed in different layers are connected by an interstitial via hole, and a method of manufacturing the same.
2. Description of the Related Art
In these years, LSIs are becoming finer, faster, and higher in frequency. Materials and structures suitable for high-speed transmission as well as higher density are also required for package substrates for packaging LSIs. Conventionally, a printed board in which build-up multilayer interconnections are formed is used as a package substrate for high-density packaging. However, in order to further increase interconnection density, it is necessary to increase the number of interconnection layers. Currently, build-up boards are manufactured by forming layer on layer in a sequential process, which is lengthy and results in an increase in costs. Therefore, a manufacturing method that shortens the process by forming the interconnections of the layers in parallel and thereafter stacking the layers simultaneously shows promise.
In substrates manufactured by such simultaneous layer stacking, it is necessary to form an interstitial via hole (IVH) that connects only specific layers. In a multilayer IVH substrate, the continuity between layers is established at the time of simultaneously stacking layers. Conventionally known methods of establishing continuity between stacked substrates include filling in with conductive paste that hardens an adhesive agent, diffusion bonding using low-melting metal, and performing solder plating on metal core balls and filling in with the balls.
Further, as methods of connecting conductors in a via or layers, there are proposed methods that achieve connection of metal particles in a via and interlayer connection with a land by sintering the metal particles by applying pulse current (see, for example, Japanese Laid-Open Patent Applications No. 11-186680, No. 2000-223836, and 11-251751). Further, a method that forms through holes and thereafter fills the through holes in the middle with metal balls equal in diameter to the through holes is also known (see, for example, Japanese Laid-Open Patent Application No. 3-87090).
Of the above-described conventional methods, the type of method that fills in with conductive paste that hardens an adhesive agent is lacking in connection reliability because the layers of a multilayer IVH substrate that are simultaneously stacked are connected only by bonding.
According to the method of performing diffusion bonding using low-melting metal, the temperature of heat treatment of a substrate, which is a temperature for stacking prepreg, is approximately 200° C. in most cases. Therefore, a low-melting metal having a melting point of approximately 200° C. is employed to fill in vias. However, the metal remelts at a temperature of 260° C. at which a lead-free solder material applied at the time of chip packaging is reflowed, thus causing problems such as corrosion of copper lands and breakage due to warping of a substrate.
According to the method of plating metal core balls with solder and filling via holes with the balls, it is difficult to control the thickness of plating on the surface of the balls. In particular, if the ball diameter is small, the thickness of plating is uncontrollable so that plating becomes thick. In this case, the solder remelts at the time of a heating process after joining, thus lacking in joining reliability. Further, since the via holes are filled with the balls, the via holes should be at least several times greater in diameter than the balls, thus making it difficult to make fine via holes.
According to the methods that achieve connection of metal particles in a via and interlayer connection with a land by sintering the metal particles by applying pulse current (Japanese Laid-Open Patent Applications No. 11-186680, No. 2000-223836, and 11-251751), the contacting portions of the particles merely neck (come into point contact), thus increasing conductor resistance. Further, pulse current is applied to a via through an interconnection line. Therefore, if the interconnection line is finer than the via, the interconnection line generates heat with Joule heat due to the current application, so that a desired current may not be applied to the via. Further, the interconnection line may be burned out. Thus, there are limitations on formation of interconnection lines.
According to the method that forms through holes and thereafter fills the through holes in the middle with metal balls equal in diameter to the through holes (Japanese Laid-Open Patent Application No. 3-87090), metal balls having the same diameter as the through holes are selected to fill in the through holes, which requires money and effort. Therefore, this method is not considered to be industrial.
USPTO Backgrounds
USPTO Backgrounds