The invention relates to random access memory. More specifically, the invention relates to non-volatile ferroelectric random access memory.
Desirable characteristics of computer random access memory include high storage density, low cost, high speed, low power and non-volatility. Dynamic random access memory ("DRAM") memory is small, inexpensive, fast, and expends little power, but it is volatile and has to be refreshed many times each second. Flash memory is non-volatile, but it is larger than DRAM, slower than DRAM, more expensive, and expends more power than DRAM.
Ferroelectric random access memory ("FeRAM") is a type of non-volatile memory that is presently being considered for use in computers. An FeRAM device includes an array of memory cells. A typical memory cell includes a single ferroelectric capacitor and a single access transistor. The ferroelectric capacitor has two stable polarization states, which correspond to binary values. Additionally, the ferroelectric capacitor retains its state without electric power. Therefore, it is non-volatile.
In comparison to flash memory, FeRAM is less expensive and it operates at lower voltages. Additionally, FeRAM is much faster than flash memory. Whereas flash type EEPROM cells can take microseconds to write and milliseconds to erase, FeRAM devices can take nanoseconds to read and write. In fact, access times of FeRAM rival those of DRAM.
In comparison to DRAM devices, FeRAM devices are larger and more expensive. If FeRAM is to become competitive with established DRAM, especially for computer memory, cost of the FeRAM will have to be reduced.
The cost can be reduced by reducing the size of the FeRAM device, since memory cell density has a direct influence on chip cost. However, as the size of an FeRAM device is made smaller, leakage of the access transistors is increased. The leakage can create problems when reading the memory cells. A read circuit of a typical FeRAM device is based on a charge-sharing technique similar to that used in DRAM devices. The charge-sharing technique is used to determine the polarization of the capacitors and, therefore, determine the binary values stored in the memory cells. The applicant of the present invention has found that as the size of the access transistors is reduced below 0.2 microns, off-leakage of the access transistors will increase to a point where simple charge-sharing read operations cease to work properly.
In addition to increasing access transistor leakage, reducing the size of the device also results in lower supply voltages. Thus, the voltage that can be pumped into the ferroelectric capacitors is reduced and the ability of the ferroelectric capacitors to maintain a charge is diminished. Consequently, detecting the charge on the capacitors becomes more difficult.
There is also a different problem associated with FeRAM devices: fatigue of ferroelectric film used in the ferroelectric capacitors. Each time the polarization of a ferroelectric capacitor is reversed, the film undergoes fatigue. Polarization reversals may occur during read and write operations. After a certain number of reversals, the film looses polarization. Due to film fatigue, the permitted number of accesses with respect to the rewrite and read of the information is limited in comparison to random access memories such as DRAMs. If FeRAM devices are to become competitive with DRAM devices, the permitted number of access will have to be increased.
USPTO Backgrounds
USPTO Backgrounds