1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device.
2. Description of the Related Art
In general, a semiconductor memory device such as a dynamic random access memory (DRAM) performs a write operation to store data or a read operation to read stored data.
The write operation may be performed in a stater in which a word line (WL) has been activated by an active command. In the write operation, data loaded on a global input/output line GIO is transferred to a local data input/output line (LIO) by a write driver (WD), the data loaded on the local input/output line (LIO) is transferred to a bit line (BL) selected based on a column selection signal, and then the data loaded on the bit line is stored in a memory cell by a bit line sense amplifier (BLSA).
Meanwhile, the read operation may also be performed in a state in which a word line (WL) has been activated by an active command. In the write operation, data stored in a memory cell is amplified through the bit line sense amplifier (BLSA) through a bit line (BL), the amplified data is transferred to the local input/output line (LIO) based on the column selection signal, and then the data on the local input/output line (LIO) is amplified and transferred to the global input/output line (GIO) by an input/output sense amplifier (IOSA).
As described above, to exchange the data between the local input/output line (LIO) and the bit line sense amplifier (BLSA), the column selection signal for selecting the corresponding bit line (BL) is used. That is, data access timing is determined by the column selection signal.
FIG. 1 is a configuration diagram of a column path control signal generation circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the column path control signal generation circuit 10 includes an inverter chain, and generates predetermined signals BWEN, YI_S, and IOSTBP after respective delay times in response to a source signal BCS. The source signal BCS is activated after each predetermined latency when a write command or a read command is applied.
The column path control signal generation circuit 10 generates a write enable signal BWEN by delaying the source signal BCS by a predetermined delay time in a write operation, and delays the write enable signal BWEN by a first delay time to generate a column source signal YI_S. The write enable signal BWEN is input to a write driver (not illustrated), and the write driver transfers data loaded on a global input/output line GIO to a local input/output line (LIO) based on the write enable signal BWEN. The column source signal YI_S is input to a column decoder (not illustrated), and the column decoder generates a column selection signal (not illustrated) based on the column source signal YI_S and a column address (not illustrated). Hereinafter, for the purpose of convenience, the column source signal YI_S is referred to as “a column selection signal”.
The column path control signal generation circuit 10 generates the column selection signal YI_S by delaying the source signal BCS by a predetermined delay time in a read operation, and delays the column selection signal YI_S by a second delay time to generate a read enable signal IOSTBP. The read enable signal IOSTBP is input to an input/output sense amplifier (not illustrated), and the input/output sense amplifier (IOSA) transfers data loaded on the local input/output line (LIO) to the global input/output line (GIO) based on the read enable signal IOSTBP.
Hereinafter, an operation of the column path control signal generation circuit 10 having the configuration as described above will be described with reference to FIG. 2A and FIG. 2B.
FIG. 2A is a timing diagram for explaining the operation of the column path control signal generation circuit 10 in the write operation, and FIG. 2B is a timing diagram for explaining the operation of the column path control signal generation circuit 10 in the read operation.
Referring to FIG. 2A, a write command (not illustrated) is applied and the source signal BCS is activated after predetermined latency. Then, the column path control signal generation circuit 10 generates the write enable signal BWEN by delaying the source signal BCS by a predetermined delay time, and delays the write enable signal BWEN by a first delay time D1 to generate the column selection signal YI_S.
Referring to FIG. 2B, a read command (not illustrated) is applied and the source signal BCS is activated after predetermined latency. Then, the column path control signal generation circuit 10 generates the column selection signal YI_S by delaying the source signal BCS by a predetermined delay time, and delays the column selection signal YI_S by a second delay time D2 to generate the read enable signal IOSTBP.
The aforementioned column path control signal generation circuit 10 in the conventional art sequentially controls column paths, thereby writing and reading valid data.
However, the column path control signal generation circuit 10 having the configuration as described above may have the following concerns.
The column selection signal YI_S generated by the column path control signal generation circuit 10 has not considered delay correction according to the arrangement location of a memory area. For example, when the memory area is assumed to include a plurality of unit memory regions (mats), as a mat is arranged far away from the write driver, driving force of data transmitted through the local input/output line (LIO) is reduced. This is because a delay factor (or line loading) to be reflected in the local input/output line (LIO) is increased in the mat arranged far away from the write driver. Thus, data to be written is delayed in the mat arranged far away from the write driver, but the column selection signal YI_S having reflected a constant delay time D1 regardless of the arrangement locations of the plurality of mats is generated. In such a case, since the column selection signal YI_S is generated later or earlier than a transmission time point of write data based on the arrangement location of the unit memory region, a write recovery time tWR may be lost or invalid data may be written.
Due to the aforementioned reason, the read enable signal IOSTBP may be also generated late or early. In such a case, an address access time tAA may be lost or invalid data may be read.
Furthermore, since the inverter chain typically includes transistors, the inverter chain is sensitive to a process, voltage, and temperature (PVT) variation. For example, in a high power supply voltage high VDD environment, a delay time through the inverter chain is reduced, and in a low power supply voltage low VDD environment, the delay time through the inverter chain is increased, so that the column selection signal YI_S may not be normally generated at a desired timing due to a change in a delay amount by a voltage variation. As a consequence, due to the PVT variation, invalid data may be written or read.
USPTO Backgrounds
USPTO Backgrounds