1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having an analog buffer circuit composed of TFTs (thin film transistors) including polycrystalline semiconductor layers. Also, the present invention relates to a semiconductor device as an image display device.
2. Description of the Related Art
In recent years, the demand for information communications equipment is increased in accordance with the outspread of information communications. Here, a display device for displaying an image is essential for the information communications equipment. As the display device, there are a liquid crystal display device using liquid crystal, an EL (electroluminescence) display device using an EL element and the like. However, in accordance with the attempt to upsize a display portion and to make it have higher resolution, an active matrix display device in which a TFT is arranged in each pixel is becoming the mainstream.
FIG. 8 is a block diagram of an active matrix display device. A source signal line driver circuit and a gate signal line driver circuit are located around a pixel portion. The pixel portion, the source signal line driver circuit, and the gate signal line driver circuit are integrally formed on a substrate. Signals outputted from the source signal line driver circuit are inputted to source signal lines and transmitted to respective pixels. Also, signals outputted from the gate signal line driver circuit are inputted to gate signal lines and transmitted to respective pixels. The pixel portion is constructed by using liquid crystal, an EL element or the like. Here, an example of a structure of a pixel in the case where EL element is used will be shown in FIG. 15.
Note that an EL element in this specification includes both an element for producing luminescence (fluorescence) from a singlet state and an element for producing luminescence (phosphorescence) from a triplet state.
The gate electrode of a switching TFT is connected with a gate signal line. One of a source region and a drain region is connected with a source signal line and the other is connected with one electrode of a capacitor and a gate electrode of an EL driver TFT. The other electrode of the capacitor, which is not connected with the switching TFT, is connected with a power source supply line. One of the source region and the drain region of the EL driver TFT is connected with the power source supply line and the other is connected with an EL element.
A method of driving a pixel with the above structure will be briefly described.
In the pixel of which gate signal line is selected, an analog signal voltage inputted from the source signal line is applied to the capacitor and the gate electrode of the EL driver TFT through a switching TFT which becomes to be in a conduction state. By this applied voltage, a current flows from the power source supply line to the EL element or in its reverse direction through the EL driver TFT. The EL element emits light with an intensity corresponding to the flowed current.
In order to miniaturize the display device and reduce a manufacturing cost, manufacturing a pixel portion and a driver circuit portion (source signal line driver circuit and gate signal line driver circuit) on a single substrate is attempted. At this time, TFTs composing the pixel portion and the driver circuit portion are manufactured using polycrystalline semiconductor layers.
Here, a structure of the source signal line driver circuit for outputting analog signals to the source signal lines will be described. Note that the source signal line driver circuit for outputting analog signals to x (x is natural number) source signal lines is assumed. As a drive method of the source signal line driver circuit, a point sequential drive and a line sequential drive are exemplified.
First, the point sequential drive will be described. In the point sequential drive, signals are inputted to the source signal lines in succession one by one. A block diagram of the source signal line driver circuit of the point sequential drive is shown in FIG. 9.
The source signal line driver circuit is composed of a shift register 901, an analog signal input line 903 and switching circuits 904 (SW.1 to SW.x), and outputs signals to source signal lines S1 to Sx.
In accordance with sampling signals from the shift register 901, an analog signal voltage inputted from the analog signal input line 903 is outputted to the source signal lines S1 to Sx in succession through the switching circuits 904 (SW.1 to SW.x).
At this time, when a length of an effective horizontal scan period is indicated by a symbol Hi (about 80% of a horizontal scan period) and the number of source signal lines (the number of pixels in a transverse direction) is indicated by a symbol N, a period which can be used for inputting a signal to one source signal line becomes H1/N.
This drive method has such an advantage to be able to simplify the structure of the driver circuit. However, in the display device having a large display portion and one having a high resolution, since N becomes larger, a signal output period per pixel H1/N is shortened, and thus cannot be sufficiently set. Therefore, the line sequential drive which will be described next is mainly made.
A block diagram of the source signal line driver circuit with the line sequential drive is shown in FIG. 10.
The source signal line driver circuit shown in FIG. 10 is composed of a shift register 101, an analog signal input line 103, a signal transfer line 106, retaining capacitors 105 and 108, first switching circuits (SW1.1 to SW1.x) 104, second switching circuits (SW2.1 to SW2.x) 107, and analog buffer circuits (AB.1 to AB.x) 109. In accordance with sampling signals from the shift register 101, an analog signal inputted from the analog signal input line 103 is sampled and retained in the retaining capacitors 105 through the first switching circuits 104. After the signals corresponding to one line is retained, these signals are retained in the next retaining capacitors 108 through the second switching circuits 107 in accordance with a signal inputted to the signal transport line 106. Here, the retained signals corresponding to one line are simultaneously outputted to the source signal lines S1 to Sx. Here, while the signals are outputted to the source signal lines S1 to Sx, that is, immediately after the signals are outputted to the second switching circuits 107, signals corresponding to next one horizontal line are retained in succession from the analog signal input line into the retaining capacitors 105 through the first switching circuits 104.
According to this drive method, in the source signal line driver circuit, output signals corresponding to one horizontal line are retained first, and then simultaneously outputted to the source signal lines. Thus, even in the case of a display device having a large number of pixels, a period for outputting the signals to the source signal lines can be sufficiently set.
Here, when a large size panel is used, a load applied to per source signal line is increased. In order to reduce the influence of round of a signal due to the load, a signal amplifying circuit is required. Thus, in the block diagram shown in FIG. 10, the analog buffer circuits (AB.1 to AB.x) 109 are located as signal amplifying circuits before the signals are outputted to the source signal lines. An example of the analog buffer circuit is shown in FIG. 5.
In FIG. 5, the analog buffer circuit is composed of a differential circuit 5501, a current mirror circuit 5502 and a constant current source 5503. The differential circuit 5501 is composed of TFTs 5505 and 5506. The current mirror circuit 5502 is composed of TFTs 5507 and 5508. The constant current source 5503 is composed of a TFT 5504.
The gate electrodes of the TFTs 5507 and 5508 are connected with each other. One of the source region and the drain region of the TFT 5507 and one of the source region and the drain region of the TFT 5508 are connected with a power source line Vdd. The other of the TFT 5507 is connected with one of the source region and the drain region of the TFT 5505. The other of the TFT 5508 is connected with one of the source region and the drain region of the TFT 5506. The source region or the drain region of the TFT 5507, which is not connected with the power source line Vdd, is connected with the gate electrode thereof. One of the source region and the drain region of the TFT 5506, which is connected with the TFT 5508, is connected with the gate electrode of the TFT 5506 and an output terminal. The gate electrode of the TFT 5505 is connected with an input terminal to which an input signal is inputted. One of the source region and the drain region of the TFT 5504 is connected with the source region or the drain region of the TFT 5505, which is not connected with the TFT 5507 and the source region or the drain region of the TFT 5506, which is not connected with the TFT 5508. The other of the TFT 5504 is grounded. A bias voltage is inputted to the gate electrode of the TFT 5504.
An analog signal voltage inputted to the input terminal is impedance-converted to increase its current capacity and then outputted from the output terminal. Thus, even if a load of the source signal line for outputting the signal is large, the signal can be transmitted while suppressing the influence of round.
Note that an example of the source signal line driver circuit for inputting an analog signal and outputting analog signals is shown in FIGS. 9 and 10. On the other hand, with regard to a source signal line driver circuit for inputting digital signals, converting the digital signals into analog signals by digital/analog converters (D/A converters), and outputting signals to the source signal lines, in the same manner as described above, in the case of a large size panel, a line sequential drive is applied and analog buffer circuits are provided. An example of the source signal line driver circuit is shown in FIG. 18.
Note that an example of the source signal line driver circuit having a structure for inputting digital signals of 4 bits in parallel and sampling the digital signals is shown in FIG. 18.
In FIG. 18, the source signal line driver circuit is composed of a shift register, a digital signal input line VD, a latch 1 (LAT1,1 to LAT1,x), a latch 2 (LAT2,1 to LAT2,x), a latch pulse line, D/A converters (DAC1 to DACx), and analog buffer circuits (AB.1 to AB.x).
In accordance with timing signals from the shift register, signals are sampled from the digital signal input line VD to the latch 1, and signals corresponding to one line period are held in the latch 1.
Note that the digital signal input line VD is indicated by four wirings in FIG. 18. The four wirings correspond to a first bit signal to a fourth bit signal. In accordance with timing signals from the shift register, for every signal corresponding to the respective source signal lines, the first bit signal to the fourth bit signal are simultaneously sampled in the latch 1.
After that, in accordance with a latch pulse inputted to the latch pulse line, the signals corresponding to one line period are transferred to the latch 2. The signals in the latch 2 are converted into analog signals by the D/A converters. The converted analog signals are simultaneously transferred to the source signal lines S1 to Sx through the analog buffer circuits. Thus, an image is displayed by the line sequential drive.
It is assumed that the analog buffer circuit shown in FIG. 5 is constructed by using a TFT in which the channel region is made from a polycrystalline semiconductor layer. In this specification, the TFT in which the channel region is made from a polycrystalline semiconductor layer is called a polycrystalline TFT.
Here, in order to normally operate the analog buffer circuit, it is required that two (a pair of) TFTs composing a differential circuit have the same characteristic and two (a pair of) TFTs composing a current mirror circuit have the same characteristic. The fact that two TFTs have the same characteristic indicates another fact that identical drain currents are flowed at the time of applying the identical gate voltages to the two TFTs. However, in fact, the characteristics of these TFTs are greatly varied. This is because the characteristic of the TFT is greatly dependent on, for example, a crystallization state of the polycrystalline semiconductor layer of the channel region.
Thus, since offset voltages are generated against input voltages in the analog buffer circuits, output voltages by the respective analog buffer circuits are varied by the offset voltages. Therefore, such attempts as to provide correction circuits to reduce variations in output voltages from the analog buffer circuits are made. This method is disclosed in Japanese Patent Application Laid-open Nos. Hei 2-1893 and Hei 7-162788.
An example of a correction circuit proposed so far will be shown, and its operation will be described.
It is assumed that, when a standard voltage Vo is inputted to the analog buffer circuit, an output voltage from the analog buffer circuit becomes (Vo+ÄV) and thus a difference of an offset voltage ÄV is produced. A correction circuit is added to the analog buffer circuit. The correction circuit detects a difference between the output voltage (Vo+ÄV) and the standard voltage Vo as the offset voltage ÄV in the case where the standard voltage Vo is inputted to the analog buffer circuit first. Thereafter, a voltage (V−ÄV) obtained by subtracting the offset voltage ÄV from an input signal voltage V is inputted to the analog buffer circuit. Thus, the offset voltage ÄV is cancelled, and the voltage V is outputted as the output voltage of the analog buffer circuit.
A specific example of such a correction circuit will be described. Note that an example of the correction circuit disclosed in Japanese Patent Application Laid-open No. Hei 7-162788 will be described here.
FIG. 6 shows an example of a circuit diagram of an analog buffer circuit 61 to which a correction circuit 62 is added. The correction circuit 62 is composed of a capacitor 63 and switching TFTs 64 to 68.
An input terminal 61a of the analog buffer circuit 61 is connected with a power source line Vo through the switching TFT 64 and one electrode of the capacitor 63 through the switching TFT 65 at the same time. The electrode of the capacitor 63, which is connected with the switching TFT 65, is connected with an input terminal 71a of the correction circuit-equipped analog buffer circuit through the switching TFT 66.
The other electrode of the capacitor 63 is connected with the power source line Vo through the switching TFT 68 and an output terminal 61b of the analog buffer circuit 61 through the switching TFT 67 at the same time. The output terminal 61b of the analog buffer circuit 61 corresponds to an output terminal 71b of the correction circuit-equipped analog buffer circuit.
It is assumed that signals Vg64 to Vg68 are respectively inputted to the gate electrodes of the switching TFTs 64 to 68.
The operation of FIG. 6 will be described using a timing chart shown in FIG. 7. Note that the timing chart shown in FIG. 7 corresponds to the case where n-channel TFTs are used as the switching TFTs 64 to 68. However, even when p-channel TFTs are used as the switching TFTs 64 to 68, there is no problem. In this case, the signals Vg64 to Vg68 have inverse phases as compared with the case where the n-channel TFTs are used.
First, at a time t1, Hi level signal voltages are inputted to the signals Vg64, Vg65 and Vg67. On the other hand, Lo level signals are inputted to the signals Vg66 and Vg68. Thus, the switching TFTs 64, 65, and 67 are in a conduction state, and the switching TFTs 66 and 68 are in a non-conduction state.
At this time, the voltage Vo on the power source line Vo is inputted to the input terminal 61a of the analog buffer circuit 61 through the switching TFT 64 and applied to the capacitor 63 through the switching TFT 65.
Next, at a time t2, the signals Vg64 and Vg67 are kept to be in the Hi level and the signal Vg68 is kept to be in the Lo level. However, when the level of the signal Vg65 is changed into the Lo level and that of the signal Vg66 is changed into the Hi level, the switching TFTs 64, 66, and 67 are in a conduction state, and the switching TFTs 65 and 68 are in a non-conduction state. Therefore, an input voltage V is inputted to the capacitor 63 through the switching TFT 66.
Thereafter, at a time t3, while the switching TFTs 64 and 67 are kept in a conduction state, the level of the signal Vg66 is changed into the Lo level and thus the switching TFT 66 becomes to be in a non-conduction state.
Next, at a time t4, the signal voltages of signals Vg64, Vg65 and Vg66 are not changed, the level of the signal Vg67 becomes the Lo level, and that of the signal Vg68 is changed into the Hi level. Then, the switching TFTs 64 and 68 are in a conduction state, and the switching TFTs 65, 66, and 67 are in a non-conduction state.
Therefore, the voltage Vo on the power source line Vo is applied to the electrode of the capacitor 63 through the switching TFT 68.
Thereafter, at a time t5, the signal voltages of signals Vg66 to Vg68 are not changed, the level of the signal Vg64 becomes the Lo level, and that of the signal Vg65 becomes the Hi level. Then, the switching TFTs 65 and 68 are in a conduction state, and the switching TFTs 64, 66, and 67 are in a non-conduction state.
Therefore, a voltage between the electrodes of the capacitor 63 is inputted to the input terminal 61a of the analog buffer circuit 61 through the switching TFT 65.
Here, the voltage between the electrodes of the capacitor 63 is (V−ÄV). Thus, when this voltage is inputted to the analog buffer circuit 61, the output of the analog buffer circuit becomes V.
As described above, by providing the correction circuit 62, a voltage except the offset voltage ÄV can be outputted from the analog buffer circuit 61.
However, there is the following problem. That is, a (t5−t1) period of time is required to correct the offset voltage ÄV. Also, new special signals are required to apply the signal voltages of signals Vg64 to Vg68. Therefore, a signal system is complicated and an increase in the number of elements is caused.
Note that not only the analog buffer circuit in which the correction circuit having the structure shown in FIG. 6 is provided but also an analog buffer circuit in which an correction circuit having another structure is provided are proposed. In any case, after an output of the analog buffer circuit is held once, an input voltage to the analog buffer circuit is changed based on the output voltage, and the offset voltage is removed from the output of the analog buffer circuit. Thus, there is a problem similar to the above matter.
USPTO Backgrounds
USPTO Backgrounds