1. Field of the Invention
This invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a super junction structure.
2. Background Art
The ON resistance of a power semiconductor device such as a vertical power MOSFET (metal oxide semiconductor field effect transistor) greatly depends on the electric resistance of its conduction layer (drift layer). The dopant concentration that determines the electric resistance of the drift layer cannot exceed a maximum limit, which depends on the breakdown voltage of a pn junction between the base layer and the drift layer. Thus there is a tradeoff between the device breakdown voltage and the ON resistance. Improving this tradeoff is important for enhancing the performance of low power consumption devices. This tradeoff has a limit determined by the device material. Overcoming this limit is the way to realizing devices with low ON resistance beyond existing power devices.
As an example MOSFET overcoming this limit, a MOSFET having a structure called a super junction structure is known, where p-pillar layers and n-pillar layers are alternately buried in the drift layer. In the super junction structure, a non-doped layer is artificially produced by equalizing the amount of charge (amount of dopant) contained in the p-pillar layer with the amount of charge contained in the n-pillar layer. Thus, while holding high breakdown voltage, a current is passed through the highly doped n-pillar layer. Hence low ON resistance beyond the material limit can be achieved.
In such a MOSFET with a super junction structure formed in the drift layer, the pillar layers can be completely depleted even at a low applied voltage by decreasing the repetition period of p-pillar layers and n-pillar layers, and high breakdown voltage can be achieved. Hence, with the decrease of the repetition period of pillar layers, the dopant concentration in the pillar layers can be increased, and the ON resistance can be decreased. However, unfortunately, the decrease of the repetition period of the super junction structure will increase processing difficulty.
Hence a structure is proposed where a trench is formed in the n-pillar layer and an insulating film and an electrode are buried in the trench (see, e.g., JP-A 2001-111050 (Kokai)). By burying the electrode in the n-pillar layer, the super junction structure is easily depleted at a lower voltage. Thus the pillar concentration can be further increased, and a lower ON resistance can be achieved.
However, upon application of high voltage, electric field concentration occurs at the bottom of the trench because of the electrode buried in the trench. When the electric field strength increases at the bottom of the trench and causes avalanche breakdown, holes generated by the breakdown are injected into the insulating film in the trench and degrade the insulation of the insulating film. Thus local electric field concentration degrades the long-term reliability of the device.
USPTO Backgrounds
USPTO Backgrounds