This invention relates to a semiconductor integrated circuit having a DLL (delay-locked loop) for outputting a clock signal synchronized to an input clock. More particularly, the invention relates to an interpolating circuit for performing a phase adjustment, a DLL having this interpolating circuit, and a semiconductor integrated circuit, such as a DDR-SDRAM, having a DLL.
A DLL (delay-locked loop) includes a delay circuit which receives a reference clock signal as an input and which has multiple taps for outputting clock signals exhibiting different delay times, a switch for selecting two clock signals by selecting taps of the delay circuit, an interpolating circuit for outputting a signal having a phase obtained by performing interior division of the phase difference between the two clock signals, a phase detector for detecting a phase difference between the output signal of the interpolating circuit and the reference clock, and a counter for counting up or counting xe2x80x94down based upon an output (UP/DN) of the phase detector, whereby an output clock signal synchronized to the reference clock signal is obtained. The basic structure of such a DLL will be described with reference to FIG. 3 used in describing the present invention.
As shown in FIG. 3, a delay circuit 10 is a delay circuit (termed also as delay line), to which a signal is input, for outputting a signal, which is obtained by delaying the input signal, from a tap selected from among a plurality of taps, the delay time thereof different from one another. A multiplexer 20o is a switch for selecting and outputting one odd-phase signal (odd) output from an odd-numbered tap of the delay circuit 10, and a multiplexer 20e is a switch for selecting and outputting one even-phase signal (even) output from an even-numbered tap of the delay circuit 10. The odd-phase signal (odd) and even-phase signal (even) that are output from the multiplexers 20o and 20e, respectively, are fed to a fine delay circuit 30, which is composed by an interpolating circuit. A phase detector 50 detects the phase difference between the output signal of the fine delay circuit (interpolating circuit) 30 and reference clock signal to deliver its output (UP/DN) to a counter 40. The multiplexers 20o and 20e select even- and odd-numbered taps of the delay circuit 10 based upon the output of the counter 40. Further, on the basis of the output from counter 40, the fine delay circuit (interpolating circuit) 30 changes the ratio of the interior division of the phase difference between the input signals.
A DLL is better suited to the low power consumption than a PLL (phase-locked loop) having a voltage-controlled oscillator because the DLL ceases operating and does not produce an output clock signal when a reference clock signal is not being applied thereto.
FIG. 12 is a diagram illustrating the structure of an interpolating circuit illustrated in the specification of Japanese Patent Kokai Publication JP-A-2001-56723. This specification discloses the interpolator circuit of a DLL used in a DDR (Double Data Rate)xe2x80x94SDRAM (Synchronous DRAM).
As shown in FIG. 12, the interpolating circuit receives internal clocks ACLK, BCLK (or /ACLK, /BCLK) and counter signals CNT3 to CNT0 and outputs an internal clock signal ABCLK (or /ABCLK) having a phase between the internal clocks ACLK, BCLK (or /ACLK, /BCLK). A buffer circuit adjusts the waveform of the internal clock signal ABCLK (or /ABCLK) output from the interpolating circuit and outputs an internal clock signal CLK1 (or /CLK1). The interpolating circuit includes switch circuits 74a, 74b, 74c, and 74d that receive the internal clock signal ACLK, switch circuits 76a, 76b, 76c, and 76d that receive the internal clock signal BCLK, four inverters 78 and resistors R2 and R3. A clocked inverter constitutes each switch and an inverter connected to a pMOS transistor of this clocked inverter. The counter signals CNT0 to CNT3 are supplied to control terminals of the switch circuits 74a, 74b, 74c, and 74d, respectively, via the inverters 78. The numerals shown in the clocked inverters of the switch circuits represent the ratios of the gate widths of the clocked inverters, and the ON resistance of each of the clocked inverters of switches 74a, 74b, 74c, and 74d is one-half of that of the preceding clocked inverter. These form variable resistors in which resistance is varied in conformity with the weighting of the counter signals CNT0 to CNT3. The internal clock signal ABCLK whose phase has a transition edge between the transition edge of the internal clock signal ACLK and the transition edge of the internal clock signal BCLK is formed between the resistors R2 and R3. The buffer circuit includes resistors R4 and R5 connected serially between power supplies VDD and VSS, a differential amplifier 80a that receives the divided potential of resistors R4 and R5, and the internal clock signal BCLK, and an inverter 80b that receives the output of the differential amplifier 80a and outputs the internal clock CLK1. The internal clock signal ABCLK having a phase conforming to the weighting of the counter signals CNT0 to CNT3. An arrangement of the kind shown in FIG. 14 is disclosed in the specification of Japanese Patent Kokai Publication JP-A-2001-56723 as another interpolating circuit.
As shown in FIG. 14, the interpolating circuit includes two sets of a constant-current source 168a, four P-channel MOS transistors 168b, 168c, 168d, and 168e of different gate widths for pulling current supplied by the constant-current source 168a and four N-channel MOS transistors 168f connected serially to the sources of respective ones of the P-channel MOS transistors, and two differential amplifier circuits 168g, and 168h whose outputs are connected to each other. The voltages at nodes v1 and v2 vary in accordance with the weighting of the counter signals CNT0 to CNT3, thereby changing the amplifying capability of the differential amplifier circuits 168g and 168h, as a result of which the internal clock signal CLK1 (or /CLK1) having a phase between the internal clocks ACLK and BCLK (or /ACLK and /BCLK) is produced as an output.
In the specification Japanese Patent Kokai Publication JP-A-2001-56723, the clock signals ACLK, /ACLK, BCLK, /BCLK supplied to the interpolating circuit shown in FIG. 12 are selected in switch circuits by shift registers 1060 and 1064 in the manner shown in FIG. 15. FIG. 15 is a diagram illustrating the structure of a clock delay generator that generates the clock signals ACLK and BCLK. The clock delay generator includes a delay circuit 1054, a delay-stage activating circuit 1056, a first switch circuit 1058, a first shift register 1060, a second switch circuit 1062 and a second shift register 1064.
In a case where a circuit for generating a tap control signal, which selects the switch that selects the tap of the delay circuit, is constituted by a shift register, the cycle necessary for locking lengthens, as will be described in detail later.
With a DDR (Double Date Rate)-II (the high-speed specification of a DDT SDRAM) having twice the operating frequency, it is necessary to raise the output timing precision. A high speed of 200 to 300 MHz (400 to 600 Mbps) is obtained with a DDR-II-SDRAM.
In a shift register for generating a tap control signal that selects the tap of the delay circuit, the step of setting a rough (coarse adjustment) initial value is at most a single stage of delay elements (delay elements 101, etc., in FIG. 3.).
In order to shorten lock time, it is required that the initial value of the tap (delay line) of the delay circuit be set to a median. However, locking will not necessarily be achieved in the shortest cycle. That is, the time it takes for the signal to propagate through the delay line becomes unnecessarily long and, hence, a variation in output timing increases proportionally and so does power consumption.
For example, in an arrangement for carrying out control for selection of a delay-circuit tap by a shift register, assume that the number of delay elements (D01, D02, etc., in FIG. 15) is 128, that the initial value of the shift register is the center tap, and that the lock point is at the initial stage or final stage (128th stage). In order to select a tap corresponding to the lock point in such case, a phase comparison must be performed 64 times and a cycle for phase adjustment in the interpolating circuit is required as well.
In order to satisfy the specification regarding the number of clock cycles and the minimum operating frequency, the number of delay-element stages cannot be increased and the propagation time per delay element, namely the interval between two signals interpolated (the phase difference of the two signals input to the interpolating circuit) cannot be shortened.
Furthermore, since control is performed by shorting the outputs of the inverters having different current drive capabilities in the interpolating circuit shown in FIG. 12, the range of linear operation is narrow. As a consequence, precision is not improved even if the setting resolution is raised.
In the circuit shown in FIG. 14, on the other hand, signals of opposite phase, namely the internal clock signals ACLK and /ACLK, are supplied to the differential amplifier circuits. It is necessary that these signals of opposite phase be supplied to the differential amplifier circuits at the same timing. In a case where the internal clock signal /ACLK is generated by inverting the signal ACLK in an inverter, interpolation is not performed correctly owing to the propagation delay time of the inverter.
As a delay element composing a delay circuit, a pair of delay circuits for delaying signals of mutually opposite phase is required, as a result of which area and operating current are doubled. This is also a source of error.
Further, in a case where the delay elements of the delay circuit are constituted by a differential amplifier circuit, standby current increases.
Accordingly, it is an object of the present invention to provide an interpolating circuit, a DLL and a semiconductor integrated circuit for implementing high-precision interpolation while reducing the scale of the circuitry and operating current.
The above and other objects of the invention are attained by an interpolating circuit, in accordance with one aspect of the present invention, which receives first and second signals, for generating an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a preset interior division ratio, comprising: a waveform synthesis unit that includes a first switch element inserted between a node, which is connected to an output terminal from which the output signal is delivered, and a first power supply; means for placing the first switch element in an ON state when the first and second signals are both a first logic value; a first series circuit composed by serial connection of a first constant-current source and a second switch element placed in the ON state when the first signal is a second logic value; and a second series circuit composed by serial connection of a second constant-current source and a third switch element placed in the ON state when the second signal is the second logic value; the first series circuit and the second series circuit being connected in parallel with each other between the node connected to the output terminal and a second power supply; and a bias control unit for setting values of current that flow through the first and second current sources of the waveform synthesis unit to values conforming to the interior division ratio.
In the interpolating circuit according to the present invention, the bias control unit has a plurality of circuits each comprising a constant-current source and a pair of switch elements composed of a switch element having one end connected to the constant-current source and a control terminal to which a control signal is input to turn this switch element on and off, and a switch element having one end connected to the constant-current source and a control terminal to which an inverted signal of the control signal is input to turn this switch element on and off; and means for performing control in such a manner that a total of currents that flow into a group of switch elements to the control terminals of which the control signal is input from among the pairs of switch elements in the plurality of circuits is made a first current value and so that a current value equal to the first current value will flow into the first current source, and in such a manner that the total of currents that flow into a group of switch elements to the control terminals of which the inverted signal of control signal is input among the pairs of switch elements in the plurality of circuits is made a second current value and so that a current value equal to the second current value will flow into the second current source.
In accordance with another aspect of the present invention, there is provided an interpolating circuit, which receives first and second signals from first and second input terminals, respectively, for generating, and delivering from an output terminal, an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a division ratio set by a control signal that enters from a control signal input terminal, comprising: a waveform synthesis unit that includes a logic circuit, to which the first and second signals are input, for outputting the result of a predetermined logic operation applied to the first and second signals; a first transistor, which is inserted between a node connected to the output terminal and a first power supply, having a control terminal to which an output signal from the logic circuit is input to turn the first transistor on and off; a first series circuit composed by serial connection of a first current source transistor and a second transistor having a control terminal to which the first signal is input to turn the second transistor on and off; a second series circuit composed by serial connection of a second current source transistor and a third transistor having a control terminal to which the second signal is input to turn the third transistor on and off; the first series circuit and the second series circuit being connected in parallel with each other between the node and a second power supply; and a bias control unit for performing control, based upon a control signal that decides the interior division ratio, in such a manner that current values conforming to the interior division ratio will flow into respective ones of the first and second current sources of the waveform synthesis unit; the bias control unit having a plurality of circuits each comprising a constant-current source transistor connected to the first power supply, a first switch transistor, which is inserted between the constant-current source transistor and a first node connected to the control terminal of the first constant-current source transistor, having a control terminal to which the control signal that decides the interior division ratio is input to turn the first switch transistor on and off, and a second switch transistor, which is inserted between the constant-current source transistor and a second node connected to the control terminal of the second constant-current source transistor, having a control terminal to which an inverted signal of the control signal that decides the interior division ratio is input to turn the second switch transistor on and off; wherein connection points between the group of first switch transistors and first nodes of the plurality of circuits are connected to a diode-connected fourth transistor, a control terminal of the diode-connected fourth transistor is connected in common with the control terminal of the first constant-current source transistor, connection points between the group of second switch transistors and second nodes of the plurality of circuits are connected to a diode-connected fifth transistor, and a control terminal of the diode-connected fifth transistor is connected in common with the control terminal of the second constant-current source transistor.
In accordance with another aspect of the present invention, the foregoing object is attained by providing a DLL circuit comprising: a delay circuit, to which an input reference signal is applied, for delaying the reference signal and outputting signals having different delay times from respective ones of a plurality of taps; first and second multiplexers for selecting and outputting signals from even-numbered taps and odd-numbered taps, respectively, of the delay circuit; a fine delay circuit, to which outputs from the first and second multiplexers are input as first and second signals, respectively, for outputting a signal of a finely adjusted delay time; a phase detector, to which the output of the fine delay circuit and the reference signal are input, for detecting a phase difference between these two signals; and a counter in which the count is varied based upon an output from the phase detector; the first and second multiplexers selecting even-numbered taps and odd-numbered taps, respectively, of the delay circuit based upon an output from the counter. The fine delay circuit comprises the above-described interpolating circuit according to the present invention.
In accordance with a further aspect of the present invention, there is provided a DLL circuit comprising: an input buffer circuit to which an input signal is applied; a delay circuit, to which an output signal from the input buffer circuit is input, for delaying the signal and outputting signals having different delay times from respective ones of a plurality of taps; first and second multiplexers for selecting and outputting signals from even-numbered taps and odd-numbered taps, respectively, of the delay circuit; a fine delay circuit, to which outputs from the first and second multiplexers are input as first and second signals, respectively, for outputting a signal of a finely adjusted delay time; a third multiplexer for selectively outputting input data using the output of the fine delay circuit as a changeover signal; an output buffer to which an output of the third multiplexer is input for being output as output data; a fourth multiplexer, to which the output of the fine delay circuit is input, having a delay time equivalent to that of the third multiplexer; a first buffer circuit, to which an output of the fourth multiplexer is input, having a dummy delay time equivalent to delay time of the output buffer; a second buffer circuit, to which an output of the first buffer is input, having a dummy delay time equivalent to delay time of the input buffer; a phase detector, to which the output signal of the second buffer circuit and the input signal are input, for detecting a phase difference between these two signals; and a counter in which the count is varied based upon an output from the phase detector; the first and second multiplexers selecting even-numbered taps and odd-numbered taps, respectively, of the delay circuit based upon an output from the counter. The fine delay circuit comprises the above-described interpolating circuit according to the present invention.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
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