For the past several decades, the scaling of features in integrated circuits has been a driving force behind the semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, leading to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The desire to optimize the performance of each device becomes increasingly significant.
A significant potential for enhanced performance of both P- and N-channel field effect transistors (FETs) is the use of channel materials with large lattice mismatches with respect to silicon. Devices formed in epitaxially grown semiconductor hetero-structures, such as in Group III-V material systems, for example, offer exceptionally high carrier mobility in the transistor channels due to low effective mass along with reduced impurity scattering by delta doping. These devices provide high drive current performance and appear promising for future low power, high speed logic applications. Along with a large lattice mismatch, however, is the problem of threading dislocation densities (TDDs) or defects that adversely impact device yield. For complementary metal oxide semiconductor (CMOS) implementation, the co-integration of lattice mismatched materials like Group III-V and germanium (Ge) based on a silicon or an SOI substrate is a big challenge.
USPTO Backgrounds
USPTO Backgrounds