The present invention pertains to generation of control signals for an active pixel sensor cell array. More particularly, the invention pertains to methods and circuitry for generating xe2x80x9cextended dynamic rangexe2x80x9d (XDR) reset pulses for causing each cell of an active pixel sensor cell array to operate with a piecewise linear transfer function.
Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting photons incident at individual pixel sensor cells (of a pixel sensor cell array) into electrical signals indicative of the intensity of light energy incident at each cell. In general, a CCD uses a photogate to convert light energy incident at a cell into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, including high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. These weaknesses include limited readout rates and dynamic range limitations, and notably, the difficulty in integrating CCDs with CMOS-based microprocessors.
The expression xe2x80x9cdynamic rangexe2x80x9d is used herein to denote the ratio of maximum detectable signal magnitude to minimum detectable signal magnitude. The present invention increases dynamic range of an active pixel sensor cell by increasing the maximum magnitude of the signal it can detect.
To overcome the limitations of CCD-based imaging circuits, imaging circuits have been developed which use active pixel sensor cells to convert light energy into electrical signals. An active pixel sensor cell typically includes a photodiode and a number of transistors which provide amplification, readout control, and reset control in addition to producing the electrical signal output from the cell.
FIG. 1 is an example of two identical CMOS active pixel sensor cells (10 and 11) having conventional design, connected along a column of an active pixel sensor cell array, and circuitry 20 for use in reading all cells connected along the column (and other columns not shown). As shown in FIG. 1, cell 10 includes photodiode d1 (connected as shown between ground and Node 3), and reset transistor N1. Transistor N1 is an NMOS transistor whose drain is connected to a power supply node (Node 1) maintained at potential Vcc, whose source is connected to Node 3, and whose gate is connected to Node 2. The gate of transistor N1 is controlled (in a manner to be described below) by a RESET signal supplied to Node 2. Alternatively, the reset transistor is a PMOS transistor.
Cell 10 also includes buffer transistor N2 and row select transistor N3, each of which is an NMOS transistor. Transistor N2 has a drain connected to Node 1, a source connected to Node 4, and a gate connected to Node 3. Transistor N3 has a drain connected to Node 4, a source connected to Node 6, and a gate connected to Node 5. The gate of transistor N3 is controlled (in a manner to be described below) by a ROW SELECT signal supplied to Node 5. Node 6 is a column readout line, and the FIG. 1 circuit typically includes several columns of cells, each having a column readout line.
As shown in FIG. 1, circuitry 20 includes detection and calculation circuit 21. Circuit 21 has an input terminal connected to Node 6, and other input terminals (not shown) connected to the column readout lines of the other columns of the cell array. Circuit 21 includes a sense amplifier for each column which outputs an analog voltage indicative of the light intensity incident at a cell along the column in response to voltages at Node 6 during a sampling period when each this cell is selected (typically, the sense amplifier outputs a sequence of analog voltages indicative of incident light intensity at each of a sequence of sequentially selected cells along the column). Circuit 21 typically implements correlated double sampling (xe2x80x9cCDSxe2x80x9d) on the voltage of each column readout line, typically performs post-processing on the output of each sense amplifier, and typically includes an analog-to-digital converter for generating digital data in response to the analog signal output from each sense amplifier (or from post-processing circuitry coupled to each sense amplifier). Circuitry 20 also includes a current mirror (comprising current source I1 and NMOS transistors N4 and N5 connected as shown, and NMOS transistors identical to transistor N5 for the other columns) which provides the necessary load for reading out the cells of the array.
In normal operation, circuit 21 receives a sequence of voltages at Node 6 (which node is common to all cells connected along the column), with each pair of consecutive voltages being indicative of light intensity incident at a different one of the cells along the column. Typically, circuit 21 receives a sequence of voltages from the column readout line of each column of cells, each pair of consecutive voltages on each column readout line being indicative of light intensity incident at a different one of the cells along a different column of the array. Circuit 21 typically includes a scan circuit which sequentially reads out analog signals indicative of light intensities of cells (of different columns) which are simultaneously generated (in parallel).
The operation of sampling (reading) each cell (e.g., cell 10) begins by briefly pulsing the gate of the cell""s reset transistor N1 with a high level (relative to the bottom rail) of reset voltage xe2x80x9cRESET.xe2x80x9d This high level pulse of the reset voltage RESET (typically equal to Vcc, where Vcc is typically 5 volts) is a xe2x80x9cfull resetxe2x80x9d signal (or xe2x80x9cfull resetxe2x80x9d pulse or xe2x80x9cfull resetxe2x80x9d potential) which resets the voltage on photodiode d1 to an initial integration voltage to begin an image collection cycle.
Immediately after assertion of such full reset pulse of the voltage xe2x80x9cRESET,xe2x80x9d the initial integration voltage on photodiode d1 (the voltage at Node 3) is Vini=VRESETxe2x88x92VTN1xe2x88x92VCLOCK, where VTN1 is the threshold voltage of transistor N1, VRESET is the high level of the voltage xe2x80x9cRESET,xe2x80x9d and VCLOCK is the voltage due to charge injection through transistor N1 from the pulsed reset voltage (assumed to be constant). Vini also contains kT/C noise which is not constant over time. Similarly, the initial integration voltage at Node 4 is VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2, where VTN2 is the threshold voltage of buffer transistor N2 (functioning as a source follower).
Next, for a selected time period, photons are allowed to strike photodiode d1, thereby creating electron-hole pairs. The photogenerated holes are attracted to the ground terminal of photodiode d1, while the photogenerated electrons are attracted to the positive terminal of photodiode d1, each additional electron reducing the voltage at Node 3. At the end of this image collection cycle, a final integration voltage will be present at Node 3. The final integration voltage is Vf=Vinixe2x88x92VS=VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VS, where VS represents the change in voltage (at Node 3) due to the absorbed photons. Similarly, the final integration voltage at Node 4 is VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2xe2x88x92VS.
At the end of the image collection cycle, the gate of transistor N3 is pulsed with a high level of row select voltage signal xe2x80x9cROW SELECTxe2x80x9d to cause the voltage at Node 4, which represents the final integration voltage of the cycle, to appear at Node 6. A CDS circuit within detection and calculation circuit 21 samples the value of the final integration voltage as it appears at Node 6.
Then, the gate of reset transistor N1 is again pulsed briefly with a high level of reset voltage xe2x80x9cRESETxe2x80x9d (a xe2x80x9cfull resetxe2x80x9d signal) which resets the voltage on photodiode d1 to the initial integration voltage to begin another image collection cycle. Immediately after assertion of such full reset signal, the initial integration voltage at Node 4 is VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2. At this time, the gate of transistor N3 is again pulsed with a high level of row select voltage signal xe2x80x9cROW SELECTxe2x80x9d to cause the voltage at Node 4, which represents the initial integration voltage of the cycle, to appear at Node 6. The CDS circuit within detection and calculation circuit 21 samples the value of the initial integration voltage as it appears at Node 6, and generates a difference signal indicative of the difference between the sampled final and initial integration voltages. The difference signal is an analog signal indicative of the voltage of interest (Vfxe2x88x92Vini=xe2x88x92VS) but not the threshold voltage VTN1 or VTN2. The kT/C noise is not compensated because the noise in the first sample (the sample of the final integration voltage) is not correlated to the noise in the second sample (the sample of the initial integration voltage)
Optionally, circuit 21 includes an inverter coupled and configured to invert the difference signal to generate an analog output indicative of the value: Vinixe2x88x92Vf=VS.
However, the conventional CMOS image sensor of FIG. 1 is subject to the serious limitation that its dynamic range is limited. As noted above, after a reset of each cell of the FIG. 1 sensor, photocurrent will slowly discharge the cell""s photodiode at a rate dependent on the incident light intensity during an integration time until a reading of the cell. The cell has a linear response in the sense that there is a fixed ratio between the incident light intensity and the output of the ADC employed to generate the system""s output (i.e., the ADC within circuit 21 of FIG. 1). Assuming a fixed integration time for each reading of each cell, each cell""s dynamic range (and thus the sensor""s dynamic range) depends on the maximum incident light intensity (Lmax) determined by Lmax=(Umax)/S, where S is the slope of each cell""s linear response curve and Umax is the maximum value of the output of the ADC employed to generated the system""s output. The dynamic range of a typical outdoor scene to be imaged can be much larger than the dynamic range of the voltage signal across each cell""s photodiode. As a result, operation of the sensor results in either a complete saturation of the bright regions of the image, or a loss of detail in the dark regions of the image.
A known technique, to be referred to as the xe2x80x9cextended dynamic rangexe2x80x9d (XDR) technique, for enhancing the dynamic range of an active pixel sensor cell (or array of cells), is described in S. Decker et al.: xe2x80x9cA 256xc3x97256 CMOS Imaging Array with Wide Dynamic Range Pixels and Column-Parallel Digital Output,xe2x80x9d IEEE Journal of Solid State Circuits, vol. 33, no. 12, December 1998, pp. 2081-2091. The XDR technique enhances the dynamic range of the cells of an active pixel sensor cell array by compressing the signal indicative of each pixel (and changing the pixel response curve for each cell from a linear curve to a piecewise linear curve). In describing the XDR technique, we use the term xe2x80x9cbreakpointsxe2x80x9d to denote the points along such a piecewise linear response curve at which adjacent linear sections of the curve intersect.
In accordance with the XDR technique, during each integration period (i.e., during integration of the photocurrents in the cells of a row), a pulse is applied to the gate of each of the reset transistors in the row. This pulse, referred to as an xe2x80x9cXDR reset pulse,xe2x80x9d has a different amplitude (a smaller amplitude, where the reset transistors are NMOS transistors) than the xe2x80x9cfull resetxe2x80x9d pulse asserted at the start of each integration period. The XDR reset pulse will affect only those cells on which a strong light signal is incident. Only if photocurrent has reduced the voltage across the cell""s photodiode to below a certain level at the time the XDR reset pulse is asserted, the voltage across the photodiode will be pulled up to Vdac=Vxdrxe2x88x92Vth, where Vxdr is the voltage on the reset line (the potential applied to the gate of the reset transistor) and Vth is the threshold voltage of the reset transistor (e.g., reset transistor N1 of FIG. 1). If the optical signal is small, the voltage across the photodiode is larger than the reset potential, Vdac, during assertion of the XDR reset pulse and the voltage across the photodiode is not changed by the XDR reset. This is illustrated in FIGS. 2 and 3, in which time T0 is the start of a first integration period (the time of assertion of a reset pulse having amplitude Vreset to Node 2), time T1 during the first integration period is the time of assertion of an XDR reset pulse (having amplitude Vxdr) to Node 2, and time T2 is the start of a second integration period.
FIG. 2 represents a dark cell (exposed to low intensity incident illumination), in which the photodiode voltage (the potential at Node 3 of FIG. 1) falls slowly from VINI (at time T0) to a value greater than Vxdr (at time T1). Assertion of the XDR reset (with potential Vxdr) to Node 2 at time T1 does not affect the photodiode voltage of this cell.
FIG. 3 represents a bright cell (exposed to high intensity incident illumination), in which the photodiode voltage (the potential at Node 3 of FIG. 1) falls rapidly from VINI (at time T0) to a value less than Vxdr (at time T1). Assertion of the XDR reset at time T1 does affect the photodiode voltage of this cell, by raising the photodiode voltage (at Node 3) to the value Vxdrxe2x88x92Vth at time T1, where Vth is the threshold voltage of transistor N1 of FIG. 1. During the rest of the integration period (between times T1 and T2), the photodiode voltage falls at the same rate as between times T0 and T1 to its final value at time T2.
By applying an XDR reset pulse during the integration period, the response curve of the image sensor is converted from a linear curve to a piecewise linear curve, as illustrated in FIG. 4. The vertical axis of FIG. 4 represents digital data output from circuit 21 (data output from the ADC within circuit 21) as a result of a read of one cell of FIG. 1 (data indicative of the difference between the final integration voltage at the end of an integration period and the initial integration voltage read at the start of the next integration period). The horizontal axis in FIG. 4 represents incident light intensity on the cell during the integration period. Curve A is the cell""s response curve, indicating the range of detectable incident light intensity (from zero to L1) corresponding to the full range of circuit 21""s output (from zero to Umax), when no XDR reset is asserted during the integration period. Curve B is the cell""s response curve, indicating the widened range of detectable incident light intensity (from zero to Lmax, where intensity Lmax is greater than L1) corresponding to the full range of circuit 21""s output, when an XDR reset is asserted during the integration period. The maximum detectable incident light intensity (Lmax) is Lmax=(Ubp1)/S+(Umaxxe2x88x92Ubp1)/Sxe2x80x2, where Ubpi is circuit 21""s output in response to incident light of intensity Lbpi (i.e., the output at the indicated breakpoint of the curve of FIG. 4), S is the slope of response curve B for values of incident light intensity less than Lbp1 (which is also the slope of linear response curve A), Sxe2x80x2 is the slope of response curve B for values of incident light intensity greater than Lbp1, and Umax is the maximum value of the output of the ADC employed to generate the system""s output.
FIG. 4 illustrates how the XDR technique extends the dynamic range of the image sensor, namely by increasing the maximum detectable light intensity from L1 to Lmax. The coordinates of the breakpoint (Lbp1, Ubp1) depend on the photodiode voltage immediately after an XDR reset (Vdac=Vxdrxe2x88x92Vth) and the time at which the XDR reset is performed during the integration period. It is possible to perform two or more XDR resets in a single integration period, which results in a piecewise linear sensor response curve having N+1 linear sections, and N breakpoints (one breakpoint for each of N XDR resets), and can (in some cases) increase the dynamic range beyond that achievable with only one XDR reset per integration period.
When implementing the XDR technique, the voltage (Vxdr) supplied to the reset line during an XDR reset can be generated using a DAC. This allows the user to control the breakpoint coordinates by programming the voltage level and the time at which each XDR reset is performed (by asserting control bits to the timing and control block of a CMOS image sensor system to cause the timing and control block to assert appropriate control bits to the DAC with appropriate timing).
Although it would be convenient for the user if the digital codes that are programmed into the DAC (and/or the timing and control block) to determine XDR breakpoints would result in a predetermined piecewise linear sensor response curve for each cell coupled to the DAC, until the present invention it had not been known how to accomplish this in a manner avoiding deviations in the actually implemented response curves relative to the desired response curves. The present inventors have recognized that several problems give rise to such deviations (errors).
One such problem is that an important parameter in programming the level of an XDR reset pulse is that the voltage to which the photodiode is reset in response to the XDR reset pulse is a reset transistor threshold voltage below the XDR reset potential (Vxdr) supplied to the reset line (e.g., the voltage across photodiode d1 of FIG. 1 just after the photodiode has been reset by an XDR reset is Vdac=Vxdrxe2x88x92Vth, where Vth is the threshold voltage of NMOS transistor N1 of FIG. 1 and Vxdr is the XDR reset potential asserted to the gate of transistor N1), and the threshold voltage is subject to variation due to variables in manufacture and varying operating parameters. An attempt to simply raise the XDR reset voltage Vout supplied to the reset line by a predetermined constant voltage above the desired resulting voltage across the photodiode would fail, because process variations in implementing the CMOS image sensor would cause variations in the threshold voltage of the reset transistor (e.g., transistor N1 of FIG. 1), and because temperature variations during operation would also affect the threshold voltage of the reset transistor. Such variations in the threshold voltage of the reset transistor would in turn cause errors in the breakpoint levels programmed into the sensor cells. The present invention solves this problem by matching the reset transistors inside the cells with a reference transistor in a new XDR reset pulse generating circuit (implemented as part of the same chip including the sensor cells), such that the threshold voltage of the reference transistor is added to the output of the DAC employed to control the level of each XDR reset pulse.
An attempt to simply raise the XDR reset voltage Vxdr supplied to the reset line by a predetermined constant voltage above the desired voltage across the photodiode would also fail because the so-called xe2x80x9cbody effectxe2x80x9d causes the threshold voltage of the reset transistor to be signal dependent, whereas the predetermined constant voltage would not be signal dependent. The present invention solves this problem by matching the biasing of the above-mentioned reference transistor to that of the reset transistors inside the cells.
U.S. Pat. No. 6,040,570, issued Mar. 21, 2000, teaches a CMOS imaging system which implements the XDR technique using two sets of CDS circuits: one set (comprising a CDS circuit for each column) for generating an output indicative of the difference between the voltage across each photodiode of a row at the beginning and the end of an integration period; the other set (also comprising a CDS circuit for each column) for generating an output indicative of the difference between the voltage across each photodiode immediately after an XDR reset pulse is asserted to the cell and at the end of the integration period. In order to read the cells of the row, the outputs of both sets of CDS circuits need to be combined. The present invention allows implementation of the XDR technique using simpler (and less expensive) circuitry using only a single set of CDS circuits (comprising only one CDS circuit for each column), and does not require circuitry for combining the outputs of two sets of CDS circuits.
In a class of embodiments, the invention is an active pixel sensor cell array including an XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels (with user-selected timing). The inventive XDR reset signal generation circuit includes a digital-to-analog converter (DAC) and a level shifting circuit coupled to the output of the DAC, and is programmed by asserting user-specified control bits to the DAC. In response to the control bits (which are a sequence of eight-bit control words in preferred embodiments), the circuit asserts a time-varying XDR reset potential which is a sequence of XDR reset pulses each having an amplitude determined by the control bits. The amplitude of the XDR reset potential as function of time (during each integration period) determines the breakpoints of the response curve of each cell. The level shifting circuit includes a reference transistor (matched to the reset transistors inside the cells), and the reference transistor is coupled so as to shift the potential at the DAC""s output upward by an amount equal to the reference transistor""s threshold voltage (which matches the threshold voltage of each reset transistor of the cell array), thus producing the XDR reset potential.
To establish a predetermined relationship between the control bits asserted to the DAC and the actually implemented piecewise linear response curve for each cell coupled to the DAC (i.e., to cause the control bits to establish breakpoints which in turn cause the internal analog-to-digital converter (ADC) of the image sensor array to assert (predictably) an expected set of digital output bits in response to each read of a cell exposed to light of known intensity), both the ADC and the DAC operate at the same reference voltage, and the biasing of the reference transistor (of the level shifting circuit) matches that of the reset transistors inside the cells of the array. Unless the XDR reset pulses are generated in accordance with the invention, the XDR reset pulses would result in ADC output codes which depend on the threshold voltages of transistors in the image sensor cell array (the array is typically implemented as an integrated circuit), and which thus depend on process and temperature variations in implementing the array and on variations in the potentials asserted to the array""s transistors during operation, which variations would result in deviations between the desired ADC output codes and those actually generated.
Other aspects of the invention are an XDR reset signal generation circuit including a digital-to-analog converter (DAC), a level shifting circuit coupled to the output of the DAC, and optionally also a timing and control block, for use with an active pixel sensor cell or cell array, and a method for generating XDR reset signals for enhancing the dynamic range of an active pixel sensor cell or cell array.
USPTO Backgrounds
USPTO Backgrounds