A typical integrated circuit may be formed by patterning or otherwise altering various layers according to particular masks. A collection of masks for forming an integrated circuit is often referred to as a mask set. An integrated circuit mask may take various forms. As one example, a mask may be a lithographic mask for selectively exposing a resist material to a radiation source, such as light having a particular frequency. In addition or alternatively, a mask may include a pattern that is programmed into a machine that may provide a beam of particles, such as electrons. Such a beam may raster a pattern across an integrated circuit layer according to such a programmed pattern.
While one particular mask set can be used in the production of an integrated circuit, such as mask set may be revised as changes to a device are made. In many cases, a mask revision may not substantially change the overall operation of an integrated circuit. Thus, it may not be possible to determine which particular mask set was used to fabricate an integrated circuit without deprocessing the device. Deprocessing can be time consuming, involve the use of various noxious chemicals, and can render a device non-operational.
At the same time, it is desirable to know the particular mask set for a device for reliability and other tracking reasons. Accordingly, in order to identify a mask set for an integrated circuit without having to resort to deprocessing, many integrated circuits include readable mask revision identification (ID) codes. By electronically reading values generated at a particular pin, or pins, it can be possible to identify a particular mask set.
One conventional approach to generating mask revision ID codes will now be described with reference to a number of diagrams.
Referring now to FIG. 7, a mask revision ID code circuit is shown in a block diagram and designated by the general reference character 700. A circuit 700 may include a number of mask ID bit circuits 702-0 to 702-n, where n is an integer. Each mask ID bit circuit (702-0 to 702-n) may receive two different voltages as inputs: VGND and VPWR. Such input voltages may be power supply voltages, as but one example. Each mask ID bit circuit (702-0 to 702-n) may also provide an output value SA0 to SAn. Output values (SA0 to SAn) may provide a mask revision ID code. Thus, mask ID bit circuits (702-0 to 702-n) may be configured so that each different mask revision can result in a different set of output values (SA0 to SAn).
FIG. 8 illustrates one example of a conventional mask ID bit circuit 800. A mask ID bit circuit 800 may include a number of links, shown as 802-0 to 802-4, arranged in series. Each link (802-0 to 802-4) may be formed from a different layer of an integrated circuit. As but one example, a link 802-0 may be formed from a layer comprising amorphous and/or polycrystalline silicon (polysilicon), while links 802-1 to 802-4 may be formed from increasingly higher levels of interconnect. That is, link 802-1 may be formed from a “metal 1” layer, link 802-2 may be formed from a “metal 2” layer, etc. An output value SAn may be provided at a sense node 804.
In FIG. 8, each link is represented as a double throw switch. In this way, a sense node may be connected to either a first potential (VGND) or a second potential (VPWR) according to the arrangements of the links.
Examples of conventional links are shown in FIG. 9. FIG. 9 includes a series of top plan views of links, starting with a lower integrated circuit layer link 802-0 and ending with a higher integrated circuit layer link 802-4. It is understood that each layer may be electrically connected with one another by way of a vertical contact and/or via. Such electrical connections between layers are shown as dashed lines in FIG. 9.
In the conventional approach of FIG. 9, each link (802-0 to 802-4) may include conductive lines 902-00/01 to 902-40/41. Each conductive line (902-00 to 902-41) may include a downward contact 904-00/01 to 904-40/41 and an upward contact 906-00/01 to 906-40/41. It is understood that a downward contact (904-00 to 904-41) may connect one layer with a lower layer. Similarly an upward contact (906-00 to 906-41) may connect one layer with a higher layer. For example, in the particular arrangement of FIG. 9, downward contacts 904-10 and 904-11 can correspond to upward contacts 906-00 and 906-01.
In FIG. 9, conductive line 902-00 may have a downward contact 904-00 to one potential (VGND), while conductive line 902-01 may have a downward contact 904-10 to another potential (VPWR). Further, in the example of FIG. 9, a conductive line 902-40 may provide an output value SAn at a sense node 804.
To better understand vertical connections between layers, a side cross sectional view is presented in FIG. 10. FIG. 10 shows a potential VGND connected to conductive line 902-00 by way of downward contact 904-00. Various connections between conductive lines 902-00, 902-10 and 902-20 are shown in the cross sectional view.
It is noted that the arrangement of FIGS. 8 and 9 can represent a mask bit ID circuit in an initial (unmodified) state. That is, such a mask bit ID circuit may represent an initial set of masks for an integrated circuit. In an unmodified state, an output value SAn will be low (e.g., VGND), as the series of links (802-0 to 802-4) provide a conductive path between VGND and a sense node 804. As a mask is revised, a change may also be made in the mask bit ID circuit to change the output value SAn provided by such a circuit. A revised mask bit ID circuit is shown in FIGS. 11 and 12.
In FIG. 11, a link 1102-2 has been modified to reflect a change in a mask set. As a result, if a link 1102-2 can be conceptualized as a double throw switch, once modified, the switch can be considered to be thrown to connect to a potential VPWR, rather than a potential VGND (the unmodified state). Once such a change is made, an output value SAn can be a logic high value, as a modified conductive path is created between a potential VPWR and a sense node 804.
FIG. 12 shows top plan views corresponding to the various links of FIG. 11. As shown, a modified link 1102-2 may include one conductive line 1202-20 that includes a single downward contact 904-20, and another conductive line 1202-21 that includes a single downward contact 904-21, but conductively connects to a higher link with upward contacts 906-20 and 906-21. In this way, a low logic value (VGND) can be isolated from a sense node 804, while a high logic value (VPWR) can be redirected to a sense node 804, thereby indicating a mask change/revision.
A drawback to conventional approaches, such as that described above, can be the limited number of mask revisions that may be expressed for a given set of mask bit ID circuits. In particular, for n mask ID bits, only n mask revisions may be expressed. Such a limitation can exist because once a change is made to a mask ID bit, the bit value may not be changed back unless the same mask layer is changed. Consequently, to account for higher numbers of mask revisions, it may be necessary to include more and more mask ID bit circuits.
It would be desirable to arrive at some way of providing a mask ID code circuit that can allow for an increased number of possible mask revision codes for a given number of mask ID bit circuits than conventional approaches. It would also be desirable that such a solution does not substantially increase the overall area required for such a mask ID code circuit.
USPTO Backgrounds
USPTO Backgrounds