Each time a new semiconductor technology is introduced, various challenges are presented. A semiconductor technology generally includes substrates and material specification, device specifics, ground rules, critical steps, levels of wiring, and other optional features. Each new technology generation incorporates both evolutionary and revolutionary improvements over the prior generation. Illustrative technologies include the use of deep and shallow trenches, planarization, copper wiring, and silicon-on-insulator (SOI) substrates.
The development of a semiconductor technology requires detailed characterization and optimization of the devices to be offered with the technology. For example, devices such as transistors, capacitors, resistors, diodes, etc., will have different electrical characteristics and properties depending on how they are implemented. For instance, layout differences such as spacing between devices, length of lines, size, etc., will impact device characteristics.
One method for characterizing devices involves the creation of “testsites”, which are essentially chips designed in the technology that include a large number of discrete instances of devices connected to pads in metallization which can be probed. A “macro” refers to a set of chip pads having a subset of related devices. For example, a macro may include 25 pads having six versions of transistor, with each transistor having a slight layout variation. The testsite will typically contain as many macros as possible to cover as many devices and device layout options as possible. Once a testsite chip is fabricated, probes can be used to send and receive electrical signals to and from the pads to characterize the discrete devices.
One of the limitations with using testsites is the fact that testsites often do not have enough space (e.g., total number of pads) to contain an inclusive set of all test macro configurations covering all possible device layout options. Accordingly, it is often the case that the testsite does not include all the particular device layout options that may be implemented in the given technology. This can be particularly problematic early in the technology development phase since the final design to be used is not always known.
Rebuilding a completely new testsite, including a complete set of masks, to change a device layout style being used in the current macros can be unacceptable due to cost and schedule. Accordingly, a need exists for a technique that would allow for the ability to cover more layout options in a testsite without significantly impacting cost and schedule.
USPTO Backgrounds
USPTO Backgrounds