The present invention relates generally to analog-to-digital converters (ADCs) and, more particularly, to a system to interface ADCs to inputs with arbitrary common-modes.
Analog input signals are generated using various sources including analog sensors, analog measurement equipment, and the like. Many modern day applications require the analog sources to interface with digital circuits. For example, a computer application that displays the temperature of a microprocessor requires interfacing an analog temperature sensor with digital circuitry of the processor. Typically, analog and digital systems interface using ADCs. ADCs convert analog input signals such as those generated by temperature sensors to equivalent digital output signals, which can then be used by the digital circuitry for further processing.
Analog input signals may be fully-differential, single-ended, uni-polar, or varying common mode. It is necessary for analog signals to have a common-mode voltage that matches with a common-mode range of the ADC. A mismatch between the analog signal common-mode and the ADC common-mode range leads to sub-par performance of the ADC, and therefore should be avoided. Conventionally, a power gain amplifier (PGA) circuit is used to sample and hold and/or amplify the input signal and additional circuitry is used to eliminate the common-mode voltage in the analog input signals and generate analog output signals that are differential around the common-mode range of the ADC.
FIG. 1 is a schematic diagram of a conventional PGA circuit 100. The PGA circuit 100 includes first through fourth capacitors 102a-102d and an operational amplifier (op amp) 104.
A first terminal of the first capacitor 102a (having capacitance CS) receives a first analog input signal (In+) around arbitrary common-modes (Vicm) and the arbitrary common-modes by way of first and second switches (S1 and S2), respectively. The arbitrary common-modes (Vicm) are detected and applied using well known circuitry. A second terminal of the first capacitor 102a receives a common-mode voltage (Vcm) by way of a third switch (S3). The arbitrary common-modes correspond to the common-mode voltage present in the first and second analog input signals and the common-mode voltage corresponds to a common-mode range of an ADC (not shown) to which the first and second output terminals are connected.
A first terminal of the second capacitor 102b (having capacitance CS) receives a second analog input signal (In−) around the arbitrary common-modes (Vicm) and the arbitrary common-modes by way of fifth and sixth switches (S5 and S6), respectively. A second terminal of the second capacitor 102b receives the common-mode voltage (Vcm) by way of a seventh switch (S7).
The second terminals of the first and second capacitors 102a and 102b are connected to negative and positive input terminals of the op amp 104, by way of fourth and eighth switches (S4 and S8), respectively. The negative and positive input terminals of the op amp 104 are connected to first terminals of the third and fourth capacitors 102c and 102d (having capacitance Cf), respectively. Second terminals of the third and fourth capacitors 102c and 102d are connected to first and second output terminals of the op amp 104, respectively. The negative and positive input terminals of the op amp 104 are connected to the first and second output terminals of the op amp 104 by way of ninth and tenth switches (S9 and S10), respectively.
The PGA circuit 100 operates in first and second operating phases that correspond to sampling and signal amplification phases of the ADC. The switches S1, S3, S5, S7, S9, and S10 remain closed in the sampling phase and the first terminals of the first and second capacitors 102a and 102b receive the first and second analog input signals, respectively, and the second terminals of the first and second capacitors 102a and 102b receive the common-mode voltage. The negative and positive input terminals of the op amp 104 are connected to the first and second output terminals of the op amp 104 and the first and second terminals of the third and fourth capacitors 102c and 102d are shorted together. The first and second analog input signals and the common-mode voltage charge the first and second capacitors 102a and 102b in the sampling phase.
Theoretically, the charges on the first capacitor 102a (Qcs+) and the third capacitor 102c (Qcf+) are given by equations (1a) and (2a),QCs+=(In+−Vcm)*Cs=(Vicm+Vid/2−Vcm)*Cs  (1a)QCf=0  (2a)
where,
In+=first analog input signal;
Vcm=common-mode voltage;
Vicm=arbitrary common-modes;
Vid=input differential-mode voltage; and
CS=capacitance of the first capacitor 102a and 102b. 
At the end of the sampling phase, the switches S1, S3, S5, S7, S8, and S10 are opened and the signal amplification phase is initiated in which the switches S2, S4, S6, and S8 are closed. This causes the arbitrary common-modes (Vicm) to be provided to the first terminals of the first and second capacitors 102a and 102b. The second terminals of the first and second capacitors 102a and 102b are connected to the negative and positive input terminals of the op amp 104, respectively. The charges QCs+ and Qcf+ are redistributed in the signal amplification phase, as given by equations (1b) and (2b),QCs+=(Vicm−Vcm)*CS  (1b)QCf+=[(Vicm=Vcm)*CS−(Vicm+Vid/2−Vcm)*CS]QCf+=Vid/2*CS  (2b)
The first output terminal of the op amp 104 generates a first analog output signal that is given by equation (3a),Vo+=QCf+/Cf=(CS/Cf)*Vid/2  (3a)
Similarly, the second output terminal of the operational amplifier 104 generates a second analog output signal give by equation (3b),Vo−=QCf−/Cf=(CS/Cf)*(−Vld/2)  (3b)Thus, Vo(diff)=(Vo+−Vo−)=(CS/Cf)*Vid  (4)
Equations (3a), (3b), and (4) show that arbitrary common-modes are eliminated from the first and second analog output signals Vo+ and Vo−.
To eliminate the arbitrary common-modes, the PGA circuit 100 requires input of the common-mode voltage and the arbitrary common-modes in the sampling and signal amplification phases, respectively. Conventionally, the arbitrary common-modes are generated using analog circuitry that needs to be precise and requires expensive electronic components with high fidelity and accuracy, which in turn increases the cost of the end-product. Additionally, the separate analog circuitry increases size and power-consumption of the end-product.
Therefore, it would be advantageous to have a circuit for generating arbitrary common-modes that is inexpensive, has low impact on size and power-consumption and overcomes the other above-mentioned limitations of conventional analog circuits.
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