This invention pertains to programmable logic devices (PLDs) in register and data path control operations.
Programmable devices are well known in the prior art and may be simply illustrated by the schematic diagram of FIG. 1. In FIG. 1, input bus 101 receives a plurality of input signals on leads 101-1 through 101-N. These input signals are inverted in order to form true and complement signals on leads 102-1 through 102-N and 103-1 through 103-N, respectively. Selected ones of these true and complement input signals are applied to the input leads of AND gates 104-1 through 104-M. This may be accomplished either by using a programming mask during the fabrication of a particular programmable logic device, or by fabricating a programmable logic device having a plurality of fuses which may be either programmed in order to form a connection between an input lead of a AND gate 104-1 through 104-M or left unprogrammed in order to avoid such a connection. The output leads of AND gates 104-1 through 104-M are selectively connected (again, for example by a programming mask or by the use of fuses) to selected ones of the input leads of OR gates 105-1 through 105-P. The output signals from OR gates 105-1 through 105-P may either be inverted or not, with resulting signals serving as the output signals of the programmable logic device.
In an alternative type of prior art PLD, connections between true and complement input signals and the input leads of AND gates 104-1 through 104-M remain programmable, but the connection between the output leads of AND gates 104-1 through 104-M are connected in a fixed pattern to the input lead of OR gates 105-1 through 105-P. While this alternative type of prior art PLD reduces the number of possible interconnections, it generally provides higher performance and, depending on the programming technique used, possibly simpler to program to perform a desired task. The functionality of this type of prior art PLD is similar to discrete devices connected to perform the same task, but provide better performance since the components are formed as a single integrated circuit. The performance of such prior art PLD's are comparable to custom integrated circuits designed and fabricated to perform similar functions, but such custom integrated circuits are not user programmable and are very expensive and time consuming to design.
Such a typical prior art programmable logic array is described in U.S. Pat. No. 3,949,370 and is used in order to provide addresses as a result of a code-to-control store address transformation. Address data is written into registers via the programmable logic array.
U.S. Pat. No. 4,482,953 describes a programmable logic array (PLA) used in a microprocessor. The PLA stores microcoded instruction sequences in order to test internal registers. The PLA does not provide dedicated input data to the registers, but rather the registers are loaded through the PLA.
U.S. Pat. No. 4,641,278 describes a register select circuit controlling specialized function circuitry contained within the register file. This select circuit is fixed, and not programmable, and is not arranged in an array.
U.S. Pat. No. 4,803,622 described the use of a PLA to store a program which controls a service table defining the operations of a bus sequencer. However, this PLA does not include a register file for control or decode circuitry.
U.S. Pat. No. 4,829,425 describes the use of a PLA bus sequencer similar to that described in the aforementioned U.S. Pat. No. 4,803,622.
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