NAND type EEPROMs (Electrically Erasable Programmable Read Only Memories) or flash memories have been developed for solid-state mass storage applications for portable music players, mobile telephones, digital cameras, and the like, as well as have been considered as a replacement for hard disk drives (HDDs). It is therefore desired that these device have larger capacities, lower cost, and reduced cell size for miniaturization and increased processing speed.
NAND device structures are typically designed such that: (1) each memory cell utilizes one transistor having a floating gate and a control gate; and (2) a single contact is provided between an array of memory cells arranged on a substrate to and a corresponding bit line. Therefore, as compared with the conventional EEPROM, the area occupied by memory cells is reduced and integration density can be improved, although cell spacing is typically limited by the selected photolithography process.
U.S. Pat. No. 5,050,125 (the '125 patent) discloses a non-volatile semiconductor memory where each bit line comprises a series array of FLASH memory cells (shown in the cross-sectional view of FIG. 4 of the '125 patent). Cell size or area is defined by the width of the floating gate and adjacent insulating region (X-direction of FIG. 4) and by the width of the associated control gate and adjacent insulating region (in the Y-direction), i.e., the overlapping area needed for the floating gate and control gates. The cell size of each cell of the '125 patent cannot be reduced beyond about 4F2-5F2, where “F” is the minimum dimension which can be imaged photolithographically, i.e., the minimum feature size or line width obtainable by a lithography technique used in the manufacturing process of the '125 patent. This minimum feature size is believed to be currently about 90 nm. This conclusion assumes that the minimum width of the floating gate is about 1F and the minimum width of the spacing between adjacent floating gates in an array of floating gates is also about 1F, while the minimum width of the control gate is about 1F and the minimum spacing between adjacent control gates is about 1F, meaning each cell occupies at least a minimum of 2F in the X-direction and 2F to 2.5F in the Y-direction.
A device having a reduced word line pitch is proposed in U.S. Pat. No. 6,580,120 to Haspeslagh, but utilizing a complex multi-group world line formation process.
It would be desirable, therefore, to increase the integration density of FLASH memory arrays while utilizing a process that can be readily integrated.
USPTO Backgrounds
USPTO Backgrounds