The invention relates to an integrated memory having a redundancy function.
In addition to the regular word lines and bit lines, integrated memories often have so-called redundant word lines and/or redundant bit lines. If there is a fault on one of the regular word lines or bit lines, this word line or bit line is replaced by the appropriate redundant line on an address basis. Therefore, such a memory can operate without faults.
Published, European Patent Application EP 0 612 074 A1 describes an integrated memory which has redundant columns. In order to allocate one of the redundant columns to a corresponding regular column, which has a plurality of bit lines, on an address basis, the memory has coding units. These can be used independently of block, with the result that, by programming a block address and a column address, each coding unit can be allocated to a redundant column in any memory block. In this way, fewer coding units are required for repairing faults than if each coding unit were allocated to only one particular memory block.
U.S. Pat. No. 4,051,354 describes a memory in which redundant word or bit lines are each subdivided into subregions which, independently of one another, can be allocated to corresponding subregions of the regular bit lines or word lines and replace these on an address basis. In this way, a plurality of faults on different regular bit lines can be repaired using only one redundant bit line, for example.
In U.S. Pat. No. 4,051,356 each subregion of the redundant line has associated coding elements allowing allocation to a regular subregion which is to be replaced. Hence, there is exactly the same number of groups of coding elements as subregions of all the redundant lines.
It is accordingly an object of the invention to provide an integrated memory having a redundancy function that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the number of coding units necessary for allocation to regular lines on an address basis can be reduced without significantly reducing the reparability of the memory. With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
addressable first lines having subregions;
addressable second lines intersecting said first lines;
memory cells disposed at intersections of the first lines and the second lines;
redundant lines each subdivided into subregions on an address basis for replacing the first lines and intersecting the second lines;
redundant memory cells connected to the redundant lines; and
coding units for allocating any one of the redundant lines at a time to any one of the first lines on the address basis, each of the coding units having a programmable activation unit whose programming state determines if an associated coding unit, when programmed, allocates a complete redundant line to a complete first line on the address basis, and if the associated coding unit, when programmed, allocates only one of the subregions of one of the redundant lines to a corresponding subregion of one of the first lines on the address basis.
In the integrated memory according to the invention, each coding unit has an associated programmable activation unit whose programming state affects the operation of the coding unit. In a first programming state of the activation unit, the associated coding unit, when programmed, allocates a complete redundant line to a complete first line on an address basis. In a second programming state of the activation unit, the associated coding unit, when programmed, allocates only one of the subregions of one of the redundant lines to a corresponding subregion of one of the first lines on an address basis.
Thus, the activation unit of each coding unit determines whether, as a result of the programming of the coding unit, either a complete first line is replaced by a complete redundant line or only a subregion of a first line is replaced by a corresponding subregion of one of the redundant lines. Since each coding unit can be allocated to any one of the redundant lines, the invention makes it possible for the coding units to be allocated to the redundant lines or to their subregions in such a way that the existing redundant lines and the existing coding elements are utilized in optimum fashion.
In accordance with an added feature of the invention, the first lines are bit lines and the second lines are word lines. Alternatively, the first lines can be word lines and the second lines are bit lines.
If a plurality of faulty subregions are disposed on a common first line, it may be beneficial for the relevant first line to be replaced completely by a redundant line, for which purpose, according to the invention, only one of the coding units is necessary. In practice, for example, faults on a complete line are relatively frequent. The invention makes it possible to repair such faults by using only one of the coding units. At the same time, the memory according to the invention affords the advantage that subregions, too, of the redundant lines can be used on an individual basis to repair corresponding subregions of the regular first lines by allocating one of the coding units at a time. This permits faulty subregions of a plurality of the first lines to be repaired using a plurality of subregions of only one of the redundant lines. Therefore, in the first instance, the number of redundant lines in the memory according to the invention can be kept small in comparison with memories in which only complete lines can be replaced. In the second instance, the number of coding units can also be kept relatively small in comparison with a memory in which each subregion of the redundant lines has a respective coding unit permanently associated with it, as is the case, for example, in U.S. Pat. No. 4,051,354, mentioned in the introduction. Since fewer redundant lines and/or coding units need to be provided for repairing faults in the memory according to the invention than in known memories, the memory according to the invention has a lower space requirement than known memories. This is because each additionally required redundant line and each additionally required coding unit increases the area required for producing the memory.
By way of example, the first lines can be bit lines and the redundant lines can be redundant bit lines. However, the first lines can also be word lines and the redundant lines can be redundant word lines. In other illustrative embodiments of the invention, each coding unit can also be used, by way of example, to allocate an appropriate redundant column to a regular column containing a plurality of bit lines.
In accordance with one development of the invention, the coding units of the integrated memory have, among other things, third subunits, which, when programmed, allocate the associated coding unit to a particular subregion of the redundant line associated with it via a first subunit and of the first line associated with it via a second subunit. The programming state of the third subunits is evaluated only if the activation unit associated with the respective coding unit has an appropriate programming state. This distinguishes whether the respective coding unit is allocating the associated redundant line to the associated first line completely or whether this is the case only for a subregion.
In accordance with one development of the invention, the subregions of the redundant lines and first lines are distinguished using a subaddress derived from second addresses, in which case the second addresses are used to address second lines intersecting the first lines. The memory cells of the memory are disposed at the intersections. If the respective coding unit is allocated to a complete redundant line, the subaddresses derived from the second addresses are not taken into account. However, if the coding unit is allocated to only a subregion of one of the redundant lines, this subregion is identified using the subaddresses derived from the second addresses.
In accordance with an additional feature of the invention, the coding units each have a first, a second and a third programmable subunit. The first programmable subunit when programmed allocates the associated coding unit to a particular one of the redundant lines. The second programmable subunit when programmed allocates the associated coding unit to a particular one of the first lines which is to be replaced on the address basis by a redundant line associated with the associated coding unit via the first programmable subunit. The third programmable subunit when programmed allocates the associated coding unit to a particular subregion of the redundant line associated with it via the first programmable subunit and of a first line associated with it via the second programmable subunit. And a programming state of the third programmable subunit is evaluated only if the programmable activation unit associated with the associated coding unit has an appropriate programming state.
In accordance with another feature of the invention, the first lines are addressed using first addresses and the second lines are addressed using second addresses. The coding units each have a first and a second comparison unit. The first comparison unit is supplied with the first addresses and with an address stored by the second programmable subunit and outputs a first result signal. The second comparison unit is supplied with subaddresses derived from the second addresses and with an address stored by the third programmable subunit and outputs a second result signal. The programmable activation unit has a first programming state in which the redundant line associated with the associated coding unit is activated on a basis of the first result signal output from the first comparison unit, but not from the second comparison unit. The programmable activation unit further has a second programming state in which the redundant line associated with the associated coding unit is activated on a basis of the first result signal and the second result signal from the first comparison unit and the second comparison unit, respectively.
In accordance with a concomitant feature of the invention, the number of the coding units is smaller than the number of the subregions of all of the redundant lines.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having a redundancy function, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
USPTO Backgrounds
USPTO Backgrounds