1. Technical Field of the Invention
The present invention relates to adjusting the timing within a communications system, and particularly to adjusting the clock timing between devices within the communications system.
2. Description of Related Art
Traditionally, synchronously clocked logic systems utilize a timing methodology requiring all logic elements to be clocked simultaneously, or at least with tolerable clock skew. This methodology is suitable for computers in which the entire central processing unit is disposed in a single integrated circuit so that delays can be well controlled. However, this methodology proves ineffective in the case of digital communications systems operating at higher speeds, such as ethernet and fiber optic data links. In these systems, data often flows through various data processing components in a somewhat asynchronous fashion. Typical data communication components in these systems include multiplexers/demultiplexers (also known as serializers/deserializers), error correction processors, and protocol/format converters. In some digital communications systems, there are many clocks having various phases relative to each other, and in many cases the clocks operate at different integer multiples of a clock frequency.
In addition, delays in digital communications systems are oftentimes longer than delays in traditional designs. For instance, delays in some digital communications systems are multiple clock periods in length. The delays in digital communications systems are oftentimes longer than delays in traditional designs because some data processing tasks require more than one clock period to execute. In addition, the delays are oftentimes longer than delays in traditional designs because the physical length of transmission lines connecting system components together are longer than transmission lines utilized in traditional designs. As can be understood, the longer delays can complicate data transfer between components in a system.
Further complicating data transfer between system components in digital communications systems is the fact that many system components generate internal clocks that are phase locked to an externally available clock and have indeterminate phase shifts, relative to the externally available clock. There is often no particular timing relationship between the time when the input data to a system component is sampled, when the output data of the component transitions, and the occurrence of the triggering edge of the internal clock(s). As a result, a need exists for adjusting the timing within systems, such as digital communications systems, so that data is sampled by the system components at the appropriate time.
Efforts to better control the timing between components in a system have met with limited success. Some systems and test equipment apply a repetitive test pattern to a system component while the output of the system component is observed with a high-speed sampling oscilloscope. During this time, the phase of the clock input to the system component can be manually adjusted until the system component under test produces the correct output data, based on the data going into the component. The oscilloscope is capable of effectively sampling at many different clock phases so that usually there is no problem synchronizing the oscilloscope to the output data. However, there are two serious limitations to employment of an oscilloscope in this manner. First, the oscilloscope limits the maximum data rate of the system to be the maximum speed observable on the fastest available oscilloscope. Second, in a system to be used outside the laboratory, it is not economically feasible to build an expensive oscilloscope into the system for the purpose of adjusting clock skew in the field.
A prior attempt to work around the shortcomings of the above-described oscilloscope-based system involves measuring the bit error rate (BER) of the data output generated by the system component under test as the clock skew is varied, and choosing the clock skew having the lowest BER. However, this approach is problematical because there are usually a number of cascaded system components involved in a BER test, all of which have to have the correct clock skew in order to obtain correct data at the output of the chain of cascaded components. This approach of measuring the BER of a system, therefore, requires a multi-dimensional search to arrive at a usable set of clock skews. In addition, the relationship between BER and clock skew is such that identifying a minimum BER is often difficult.
Based upon the foregoing, there is a need for a simple and accurate method for adjusting clock skew or other timing within a communications system.
Embodiments of the present invention overcome shortcomings in prior techniques for adjusting timing and satisfy a significant need for a method and device for relatively quickly and accurately adjusting clock signals for devices in a system. Clock skew and/or phase between the clock input to a device under test and a clock input to a data source is first adjusted to approximately 180 degrees. Thereafter, the 180 degree clock skew is shifted by approximately 180 degrees to obtain near zero clock skew. In particular, the clock skew is adjusted to approximately 180 degrees by applying an input data pattern to the device under test having a predetermined DC offset voltage, and measuring a DC offset voltage of the output of the device under test at a plurality of different clock skew amounts. The clock skew that produces the largest magnitude of DC offset at the data output of the device under test is the clock skew of 180 degrees.
Exemplary circuitry for effectuating the clock skew adjusting and shifting includes phase shifter circuitry connected to a clock input of one of the device under test and the data source, and a voltage measuring circuit connected to the output of the device under test.
Furthermore, the invention provides embodiments with other features and advantages in addition to or in lieu of those discussed above. Many of these features and advantages are apparent from the description below with reference to the following drawings.
USPTO Backgrounds
USPTO Backgrounds