The ever-growing demand for more functionality and higher performance has caused increased complexity in integrated circuit (IC) designs requiring more yet smaller transistors to be closely packed. As a result, the integrated circuit chip size has continually increased to accommodate the ever-increasing number of transistors. This continual demand for smaller features improves the performance of integrated circuits but also adversely impacts the interconnect performances. Smaller wire sizes and spacing and longer lines to traverse larger chip areas have increased the resistance, capacitance and, as a result, the R-C delay. Moreover, this interconnect delay becomes more significant and can no longer be ignored as the feature sizes continue to shrink into the deep submicron regime.
Another adverse impact of this continual increase in chip size as a result of the demand for more functionality and higher performance is the number of chips per wafer decreases and thus increases the manufacturing cost as well as the cost of ownership of integrated circuits.
Thus there arises the development of three dimensional integration of chip design and manufacturing to create multiple levels of Silicon ICs to reduce the size of the integrated circuits and to improve interconnect delays and feature packing density by vertically stacking multiple dies and interconnecting these multiple dies with interconnects such as a high density, low latency interconnect interface.
Several approaches have been investigated, yet various limitations have been identified for each approach. For example, one method of three dimensional integration of integrated circuits is to bond two or more pieces of fully processed wafers with vias or interconnections electrically connecting the integrated circuits on both wafers. Furthermore, the backside of the these wafers may be etched away for bonding additional pairs of wafers. The advantage of this method is in that it preserves all the material properties known today, with the exception of the bonding layer between the wafers. However, the limitation on this method is the precision, or lack thereof, of overlaying two processed wafers each of which has been manufactured with extremely high precision atop each other. Typically, the best alignment techniques today may only bring the two wafers within +/−2 microns, which is far less precise than what is required for integrated circuits. Such an misalignment may cause great difficulties in the interconnects between the two pieces of wafers being bonded or glued together. Moreover, the variation in the flatness of the processed wafers may prohibit such bonding. This effect of varying curvature of the processed wafers is especially profound as the pair of wafers are usually bonded in opposite directions with the silicon substrate facing outwards. Additional problems introduced by the different quality of the back side of the wafer as well as the typical high particle count on the back side and the lack of effective mechanisms to control the particle problems further exacerbates the practicability of these approaches.
Traditional epitaxial growth of single crystal silicon through CVD processes has been known for its high temperature (˜1000 degrees Celsius) and thus cannot be used in three-dimensional integration because it violates the thermal budget of an integrated circuit. Recent development of ultra-high vacuum CVD low temperature epitaxial processing technique has substantially reduced this thermal budget problem although manufacturability still has room for improvement.
Another method for forming a thin film transistor (TFT) is to deposit a thin film of polycrystalline silicon atop a substrate and then uses an intense energy source such as an electron beam or a laser to induce re-crystallization of the polysilicon film. This method may be improper for three-dimensional chip integration due to its high temperature process characteristics that may most likely exceed the thermal budget of a semiconductor device. It is not until the recent development of low temperature processing which has successfully demonstrated the fabrication of single crystal silicon TFTs.
Although the above technologies may be utilized for three-dimensional integrated circuit (IC) integration, they still have certain limitations and may even produce unsatisfactory results. For example, the resultant single silicon layer may not be sufficiently flat to accept subsequent semiconductor layers, and while it is theoretically possible to employ subsequent planarization processes to flatten the single silicon layer. The epitaxial growth process and the high energy re-crystallization process are known to be sensitive to, if not conformal to, the underlying interlayer dielectrics.
Other low temperature crystallization processes such as the metal induced lateral crystallization and low temperature deposition and crystallization of amorphous silicon may also be used in certain three-dimensional chip integration such as deep sub-micron polysilicon TFTs, stacked SRMA cells, and EEPROM cells have been successfully demonstrated.
However, all the above methods are sensitive to the topographical variations of the underlying film stack or even the substrate and thus severely limit the applicability and utility of three-dimensional integration. For example, the second semiconductor substrate atop the first film stack would limit the types of IC blocks because of the topographical variations/micro-roughness of the top surface of the second semiconductor substrate. Similarly, the variations in the flatness or the micro-roughness of the substrate may also cause problems in the fabrication and integration of modern integrated circuits. The surface variations or the micro-roughness will also continue to be a perturbation to lithographic tools.
USPTO Backgrounds
USPTO Backgrounds