1. Field of the Invention
The present invention relates generally to semiconductor fabrication, and more particularly, to a method for fabricating planar semiconductor wafers.
2. Description of the Related Art
Since the inception of the semiconductor industry, improved performance has generally resulted from: (i) the continued reduction in the size of transistors; and (ii) the use of different material to improve the switching speed of transistors. Generally speaking, a new generation of semiconductor fabrication technology is created approximately every two years. With each new generation, the feature size of the transistors are reduced, resulting in faster switching speeds. In addition, semiconductor process engineers are continually striving to use new and different materials to further increase performance. For example, for many years aluminum was used for metal interconnects. More recently, however, device engineers have started using higher conductivity metals, such as copper, and better dielectrics, to improve the signal propagation speed between transistors.
A copper metal interconnect layer is generally formed by the following steps: (i) applying a blanket dielectric layer over the wafer surface; (ii) patterning of the dielectric with vias and trenches which define an interconnect pattern; (iii) applying a barrier layer (e.g., Tantalum Nitride) over the wafer surface during a physical or chemical vapor deposition step. The barrier layer prevents migration of subsequently deposited copper into the dielectric layer; (iv) applying a blanket copper seed layer during another deposition step; (iv) depositing an additional copper film in an electrolytic copper plating bath to fill the vias and trenches and to provide additional bulk to the blanket copper layer; and performing a chemical-mechanical polishing (CMP) step on the wafer surface to smooth or planarize the wafer surface after the plating process and to create the intended interconnect scheme.
During the bath plating step, the wafer undergoes a sequence of conditions. The electrolytic bath is typically an acidic solution. When the wafer is first immersed, the bias applied to the wafer prevents the acid from attacking the copper seed layer. After the initial immersion, a “bottom-up” initiation condition occurs. Organic additives, such as accelerators and suppressors, are included in the plating solution. The accelerators tend to concentrate in the vias or trenches of the wafer. As a result, the copper plating occurs at a faster rate in the vias and trenches than on the planar surface areas of the wafer. This phase is called “gapfill”. Eventually the trenches and vias fill up with the plating metal. The end of the gapfill phase occurs when the smallest to moderate sized vias and trenches are completely filled. The moderate size cross over can range from 0.25 to 1.0 microns, depending on the waveforms of the bulk plating. Larger features will typically only be partially filled at the gapfill point. However, this typically is not problematic because the subsequent bulk plating is performed at higher rate, filling in these areas. The timing of the gapfill point is typically determined by analyzing empirical data that is generated from previous wafer runs. At the gapfill point, the bulk copper plating step begins, by changing the bias applied to the wafer. When the bulk plating is complete, the wafer is removed from the bath and the CMP step is performed.
The aforementioned process can potentially have a number of problems. The high concentration of the accelerant in the vias and trenches causes an over-plating condition in these same areas during the subsequent bulk plating. As a result, the bulk copper layer is often uneven, with bumps or humps in the areas of the smaller to moderate sized vias and trenches. This problem is exasperated as process technologies improve and feature sizes get smaller and smaller. One attempted solution to this problem is the inclusion of another suppressor, called a leveler, into the bath solution. The leveler is attracted to high copper concentration regions, i.e. over features where the gapfill (i.e., bottom-up) process is occurring. As a result, improved local planarity is achieved. However, since the leveler is a suppressor, the gapfill process is degraded for the very reason local planarity is improved. Another issue with the levelers is that they create additional oxidation and breakdown byproducts in the plating bath. As a consequence, the electrolyte plating solution has to be either regenerated and/or replaced to eliminate this build up. The use of levelers therefore increases costs, potentially decreases yields, and creates additional environmental concerns. It will therefore become more difficult to achieve good gapfill capability while maintaining good local planarity across the wafer surface in the future, and as a result, fabricating semiconductor wafers with multiple interconnect layers will become problematic.
Accordingly, there is a need for fabricating planar semiconductor wafers by introducing an equilibrium period after the gapfill point so that the high concentrations of accelerant can equilibrate in the plating solution before bulk plating, resulting in a smooth and even bulk copper plated layer, without impacting the gapfill capability.
USPTO Backgrounds
USPTO Backgrounds