When a Static Random Access Memory (SRAM) operates at a low power supply voltage (VDD), its write margin limits the minimum operable power supply voltage (VCCmin). In some conventional circuits, a negative bitline (BL) writing scheme (with negative boost voltage) is used when writing a logical 0 (write 0 operation) in a memory for write margin limited SRAM under low VDD operating design. However, the negative boost voltage level relies on the VDD magnitude, and does not provide enough driving voltage difference at lower VDD. Further, under nominal VDD, the negative boost can cause stress and reliability issues. Accordingly, new circuits and methods are desired to solve the above problems.
USPTO Backgrounds
USPTO Backgrounds