1. Field of Invention
This invention is related to communication devices, and in particular, to the manufacture of security tags often use, for example, as Radio Frequency Identification (RFID) circuits.
2. Description of Related Art
Chip bonding is costly. The two largest components of the cost of RFID tags today are the integrated circuit and the attachment of that circuit (otherwise known as silicon) to an antenna structure. While the increasing volume of the number of chips helps to drive the IC cost down, bonding is a mechanical process and does not benefit from the same technology advances or economic scale.
Current methods of chip bonding do not adequately address costs. A two-step approach of an intermediary chip strap achieves incremental costs improvement by relocating the costs. However, straps do not address the problem directly, as bonding is still required, but to a smaller tag. Moreover, straps add another step to bond the strap to the antenna structure. Current manufacturers, using standard bonding technology with straps, want straps to be like traditional bonding surfaces, as commonly found on circuit board technology that is, hard and inflexible. However, such straps do not lend themselves to easy integration into flexible tags (e.g., RFID tags). The standard bonding processes are all known strap-based solutions, and therefore less than ideal.
One related art attachment method, called Fluidic Self Assembly (FSA), provides insufficiently robust bonds. Because the chips find their own way into bonding sockets, the 25 chips cannot use adhesives or flux, since anything sticky prevents free motion of the chips into the sockets. With the fluid self assembly process, the bond is made at a tangent between the chip bonding pad and sides of the bonding cavity. This flat-to-edge bond is different than and less reliable than traditional bonds, which are made flat-to-flat. Fluidic self assembly also places restrictions on the type of substrate that can be used. Fluidic Self Assembly (FSA) does not create the bond, it only places tags into appropriate carrier for attachment. Current FSA method being practiced uses patterned cut out polyester and laminates another film on top of the web with chips in place. The back web then is laser cut leaving a hole in direct proximity and above the chip bonding pad area. This hole is filled with conductive ink and a trace is completed on the back side perpendicular to the hole creating a strap. The FSA process is slow and uses multiple steps and requires a high degree of accuracy with known technology products available today.
A known wire bonding process is disclosed in U.S. Pat. No. 5,708,419 to Isaacson, et al., the contents of which are incorporated by reference herein in its entirety. Isaacson discusses the bonding of an Integrated Circuit (IC) to a flexible or non-rigid substrate which generally can not be subjected to high temperatures, such as the temperature required for performing soldering processes. In this wire bonding process, a chip or dye is attached to a substrate or carrier with conductive wires. The chip is attached to the substrate with the chip front-side face up. Conductive wires are bonded first to the chip, then looped and bound to the substrate. The steps of a typical wire bonding process include:                1. advancing web to the next bond site;        2. stopping;        3. taking a digital photograph of the bond site;        4. computing bond location;        5. picking up a chip;        6. moving the chip to the bond site;        7. using photo feedback to adjust placement to the actual site location;        8. placing or depositing chip;        9. photographing the chip to locate the bond pads;        10. moving the head to the chip bond pad;        11. pressing down, vibrating and welding conductive wire to the bond pad;        12. pulling up and moving the chip to the substrate bond pad, trailing wire back to the chip bond        13. pressing down and welding that bond;        14. pulling up and cutting off the wire; and        15. repeating steps 10-14 for each connection.        
In contrast, the interconnection between the chip and substrate in flip-chip packaging is made through conductive bumps of solder that are placed directly on the chip's surface. The bumped chip is then flipped over and placed face down, with the bumps electrically connecting to the substrate.
Flip chip bonding, a current state of the art process, is expensive because of the need to match each chip to a tiny, precision-cut bonding site. As chips get smaller, it becomes even harder to precisely cut and prepare the bonding site. However, the flip-chip bonding process is a considerable advancement over wire bonding. The steps of a typical flip-chip bonding process include:                1. advancing web to the next bond site;        2. stopping;        3. photographing the bond site;        4. computing the bond location;        5. picking up the chip;        6. moving the chip to the bond site;        7. using photo feedback to adjust placement at the actual site location;        8. placing the chip;        9. ultrasonically vibrating the placement head to weld chip in place; and        10. retracting the placement head.        
Steps 1 through 8 of each of the above bonding processes are substantially the same. The web must stop to locate the conductive gap in the substrate and precisely place the IC. The related art processes require that the web is stopped and measured (e.g., photographing the bond site, containing the bond location, using photo feedback to adjust placement at the actual site location) so that the chip can be accurately placed as desired adjacent the gap and bonded.
An approach has been made to improve on the flip chip bonding process by using a multiple head pick-and-place system. However, this approach created other problems, such as it is very difficult to align all of the multiple heads to individually pick up and place the chips. That is, using a multiple head pick-and-place system, it was hard to consistently pick up and set all of the chips accurately.
During step 5 of the above bonding processes, the chip is picked up, typically from a chip wafer (e.g., semiconductor wafer) or intermediate structure holding the chips after they have been formed as a plurality of integrated circuits on the chip wafer. Generally, each chip wafer has dozens to hundreds of individual chips or dice formed thereon. As integration geometries decrease and the size of chip wafers increase, the number of integrated circuit dice formed on each wafer also increases. Once the chips or dice are formed on the chip wafer, the chips are tested to determine which chips are functional and which chips are not functional. In most testing procedures, each chip or die is probed using very costly probe equipment while the chips/dice are still in wafer form, typically by contacting each bonding pad on each individual chip with a separate probe needle. That is, while the chips are still in wafer form, each chip is probed in order to determine whether each chip passes a test for electrical opens or shorts. Preferably, a full functionality test and thorough reliability test are also provided for the probed chips. The purpose of the wafer level chip tests is to determine, as early as possible in the manufacturing process, which chips are defective. The earlier a defective chip is detected, the less money that is wasted on further processing of the defective chip.
FIG. 1 illustrates a chip wafer 10 (e.g., semiconductor wafer) in accordance with the prior art. The chip wafer 10 includes a wafer flat 12 having a plurality of chips 14 (e.g., integrated circuits, dice) which are formed thereon. The chips 14 are arranged in an array of rows and columns which are separated by a plurality of dicing lanes, such as horizontal dicing lanes 16 and vertical dicing lanes 18. In a typical chip wafer, about 50% to 75% of chips are good and about 25% to 50% of the chips are bad, that is, defective. The good or bad chips are marked in accordance with results of the wafer level chip tests. A known vision system maps the good chips, which enables single head pick-and-place systems to select and move only the mapped good chips. Unfortunately, the known multi-head pick-and-place systems have not been successful in selecting and placing only the good chips. Instead, these systems typically grab all of the chips, as it is difficult to align all of the multiple heads to only take the good chips from the wafer. It would thus be a benefit to selectively take only the good chips directly from the wafer, preferably in a rotary process. All references cited herein are incorporated herein by reference in their entireties.
Retracing a path during the bonding process takes time, causes vibration, and wears mechanical linkages. These linkages also create uncertainty in absolute position. Rotating or continuous devices are preferred over reciprocating devices, in part because stopping and starting the manufacturing line always slows the process down and reduces throughput. It would be beneficial to adjust tooling to operate in a process that is continuously advancing down the line.
USPTO Backgrounds
USPTO Backgrounds