1. Field of the Invention
Embodiments of the invention generally relate to an integrated processing system containing multiple processing stations and robots that are capable of processing multiple substrates in parallel.
2. Description of the Related Art
The process of forming electronic devices is commonly done in a multi-chamber processing system (e.g., a cluster tool) that has the capability to sequentially process substrates, (e.g., semiconductor wafers) in a controlled processing environment. Typical cluster tools used to deposit (i.e., coat) and develop a photoresist material, commonly known as a track lithography tool, or used to perform semiconductor cleaning processes, commonly described as a wet/clean tool, will include a mainframe that houses at least one substrate transfer robot which transports substrates between a pod/cassette mounting device and multiple processing chambers that are connected to the mainframe. Cluster tools are often used so that substrates can be processed in a repeatable way in a controlled processing environment. A controlled processing environment has many benefits which include minimizing contamination of the substrate surfaces during transfer and during completion of the various substrate processing steps. Processing in a controlled environment thus reduces the number of generated defects and improves device yield.
The effectiveness of a substrate fabrication process is often measured by two related and important factors, which are device yield and the cost of ownership (CoO). These factors are important since they directly affect the cost to produce an electronic device and thus a device manufacturer's competitiveness in the market place. The CoO, while affected by a number of factors, is greatly affected by the system and chamber throughput, or simply the number of substrates per hour processed using a desired processing sequence. A process sequence is generally defined as the sequence of device fabrication steps, or process recipe steps, completed in one or more processing chambers in the cluster tool. A process sequence may generally contain various substrate (or wafer) electronic device fabrication processing steps. In an effort to reduce CoO, electronic device manufacturers often spend a large amount of time trying to optimize the process sequence and chamber processing time to achieve the greatest substrate throughput possible given the cluster tool architecture limitations and the chamber processing times. In track lithography type cluster tools, since the chamber processing times tend to be rather short, (e.g., about a minute to complete the process) and the number of processing steps required to complete a typical process sequence is large, a significant portion of the time it takes to complete the processing sequence is taken up transferring the substrates between the various processing chambers. A typical track lithography process sequence will generally include the following steps: depositing one or more uniform photoresist (or resist) layers on the surface of a substrate, then transferring the substrate out of the cluster tool to a separate stepper or scanner tool to pattern the substrate surface by exposing the photoresist layer to a photoresist modifying electromagnetic radiation, and then developing the patterned photoresist layer. If the substrate throughput in a cluster tool is not robot limited, the longest process recipe step will generally limit the throughput of the processing sequence. This is usually not the case in track lithography process sequences, due to the short processing times and large number of processing steps. Typical system throughput for the conventional fabrication processes, such as a track lithography tool running a typical process, will generally be between 100-120 substrates per hour.
Other important factors in the CoO calculation are the system reliability and system uptime. These factors are very important to a cluster tool's profitability and/or usefulness, since the longer the system is unable to process substrates the more money is lost by the user due to the lost opportunity to process substrates in the cluster tool. Therefore, cluster tool users and manufacturers spend a large amount of time trying to develop reliable processes, reliable hardware and reliable systems that have increased uptime.
The push in the industry to shrink the size of semiconductor devices to improve device processing speed and reduce the generation of heat by the device, has reduced the industry's tolerance for process variability. To minimize process variability an important factor in the track lithography processing sequences is the issue of assuring that every substrate run through a cluster tool has the same “wafer history.” A substrate's wafer history is generally monitored and controlled by process engineers to assure that all of the device fabrication processing variables that may later affect a device's performance are controlled, so that all substrates in the same batch are always processed the same way. To assure that each substrate has the same “wafer history” requires that each substrate experiences the same repeatable substrate processing steps (e.g., consistent coating process, consistent hard bake process, consistent chill process, etc.) and the timing between the various processing steps is the same for each substrate. Lithography type device fabrication processes can be especially sensitive to variations in process recipe variables and the timing between the recipe steps, which directly affects process variability and ultimately device performance. Therefore, a cluster tool and supporting apparatus capable of performing a process sequence that minimizes process variability and the variability in the timing between process steps is needed. Also, a cluster tool and supporting apparatus that is capable of performing a device fabrication process that delivers a uniform and repeatable process result, while achieving a desired substrate throughput is also needed.
Therefore, there is a need for a system, a method and an apparatus that can process a substrate so that it can meet the required device performance goals and increase the system throughput and thus reduce the process sequence CoO.
USPTO Backgrounds
USPTO Backgrounds