The present invention relates to a technique of mounting plural memory modules, specifically to a technique effective for use in a memory system that mounts memory modules on a mother board through sockets and connects each of the memory modules with a memory controller in an equal distance.
The techniques relating to sockets or connectors for memory modules are disclosed, for example, in the Japanese Published Unexamined Patent Publication No. Hei 10 (1998)-3971, Hei 11(1999)-40294, Hei 10(1998)-335546, Hei 8(1996)-314800, Hei 4(1992)-144160 which corresponds to U.S. Patent Publication No. 5,191,404, and so forth.
The Japanese Published Unexamined Patent Publication No.Hei 10(1998)-3971 discloses a technique that when the wirings between the sockets for memory modules are lengthy, the wirings are easily influenced by noises from adjacent signal wirings, and the common signal is directly short-circuited between the sockets by using a short-circuiting plate to shorten the length of the wirings, thereby enhancing the immunity to noises.
The Japanese Published Unexamined Patent Publication No.Hei 11(1999)-40294 discloses a technique that reduces the number of through holes and contacts to be formed on a printed circuit board by using a common bar as a common signal line between the sockets for memory modules, to thereby achieve simplification of the connector structure and reduction of the mounting cost.
The Japanese Published Unexamined Patent Publication No.Hei 10(1998)-335546 discloses a technique that achieves the electrical connection and mechanical support of modules only by a socket member having plural connections in pursuit of a size reduction of the socket that mounts plural modules. The technique achieves the compatibility of the mechanical holding power of the socket member and the overcoat plating facility on the electric contacts of the socket member, by shifting the positions of the contacts of external connection terminals on the front and back sides of the module.
The Japanese Published Unexamined Patent Publication No.Hei 8(1996)-314800 discloses a module for connecting memory modules that possesses plural connection sockets in order to connect the memory modules whose number exceeds the number of the sockets for the memory modules in a computer.
The Japanese Published Unexamined Patent Publication No.Hei 4(1992)-144160 discloses a memory array mechanism that connects a multi-layer board having memory modules mounted thereon as a mutual connection member to the module board so as to face each other with a narrow gap through edge clips.
In a memory system mounting plural memory modules, the influence given to signal waveforms (deformations of waveforms by reflected waves due to the impedance mismatching) by the length of bus lines on a mother board and the number of the sockets for the memory modules on the bus lines has been an ignorable factor in a synchronous DRAM of which clock frequency exceeds 133 MHz.
Especially, in a bus having multiple slots, the degree of influence to the waveforms that the reflected waves give at the termination greatly differs at the socket near side or at the socket far side, which makes the timing design difficult. And, as the number of the sockets increases, the length of the bus wiring becomes longer, and the wiring capacity increases, which makes it unfit for a high speed operation. Therefore, a shorter bus wiring with a shorter distance between the sockets in addition will achieve a better characteristic.
Accordingly, in this type of memory system, it is essential to design the bus wirings for the memory modules as shorter as possible to comply with a higher speed operation. However, the length of the bus wiring is basically determined by the larger one of the thickness of the socket and that of the module and the number of the socket. As to the thickness of the module, the maximum thickness is settled by JEDEC, and as the result, if the specifications are the same, the widths of the buses will be virtually the same in any products.
Now, the inventor clarified the followings, through the examination of the memory system that mounts the plural memory modules as mentioned above. The technique of the memory system that the inventor examined will be discussed with reference to FIG. 12 illustrating the structure of the memory system as the premise of the invention, FIG. 13 illustrating the signal system of the memory system, and FIG. 14 (a), FIG. 14 (b) illustrating the signal waveforms that the memory modules receive.
As shown in FIG. 12, in the memory system, for example, a memory controller 101 is directly mounted on a mother board 108, and three memory modules 102 to 104 each having memory IC are mounted in parallel on the mother board 108 through sockets 105 to 107 each having plural socket pins. By way of the bus wirings on the mother board 108, each of the memory modules 102 to 104 is connected electrically to the memory controller 101 through the socket pins of each of the sockets 105 to 107.
In this type of the memory system, from the viewpoint of pursuing a high speed, the influence by the length of the bus wiring becomes ignorable; however, in the parallel arrangement of the memory modules 102 to 104 as shown in FIG. 12, there is a limit on the shortening of the bus wiring, from the thickness of the memory modules 102 to 104 or that of the sockets 105 to 107. Further, it is conceivable that the influences by the reflected waves being different depending on the positions of the sockets 105 to 107 (=bus wiring lengths) will create differences in the waveforms to make the timing design difficult. In other words, the following relation in the nearest memory module 102 and the farthest memory module 104 viewed from the memory controller 101 has been an ignorable factor:
(the difference of the lengths of the bus wirings due to the difference of the positions of the sockets) greater than  thickness of the memory modulexc3x97 (number of the socketsxe2x88x921)
As shown in FIG. 13, in the memory system of the memory modules 102 to 104 of the synchronous DRAM, since the signal from the one memory controller 101 with regard to the signal system common to the modules (address signal: A0 to A11, control signal: /RAS/CAS/WE, data signal: DQ0 to DQ63, data management signal: DQS0 to DQS15, DM0 to DM15) is connected to the bus connecting terminals on the plural boards through a single bus, the lengths of the bus wirings to the memory controller 101 are different with each of the sockets.
In such a signal system common to the modules, with regard to the one-way signals from the memory controller 101 to the memory modules 102 to 104 (address signal, control signal, data management signal) and the clock signal, it is necessary to make the time differences between the clock signal and each of the signals equal to any slots, by regulating the differences of the lengths to the slots.
However, with regard to the data signal that goes and returns, in case of the reverse direction to the clock signal (the readout from the memory modules 102 to 104), it is impossible to synchronize the data signal with the clock signal. That is, there occur shifts in the timings to the clock signal of the data signals for each slot arriving at the memory controller 101. Accordingly, a data strobe signal is required as another synchronization signal. When the data signal reads a data being reverse directional to the clock signal, the data strobe signal also advances in the reverse direction to the memory controller 101 from the memory modules 102 to 104, and serves for transmitting the synchronizing timing of the data signal to the memory controller 101.
With regard to the signal system independent to each module (clock signal: CK0 to CK8, clock management signal: CKE0 to CKE5, bank selecting signal: CS0 to CS5, power supply signal: Vdd, Vss), one signal pin and one bus connecting terminal are connected in a one-to-one correspondence. In the same manner as the common signal system, the signal system independent to each module establishes synchronization with the common signal system by giving differences in the wiring lengths to each of the sockets.
Thus, in the memory system as the premise of this invention, when the memory controller 101 sends a signal to each of the memory modules 102 to 104 as shown in FIG. 14(a), with the reflected waves taken into consideration, the signals received by each of the memory modules 102 to 104 become, for example, the waveforms as shown in FIG. 14(b). Therefore, it is conceivable that the differences of the distances to each of the memory modules 102 to 104 viewed from the memory controller 101 create the following problems on the bus wirings.
(1) creating the differences of the signal arrival times (skew) due to the differences of the distances to reduce the margin of the timing.
(2) except for the memory module at the termination, the modules have stepped waveforms formed by the times for awaiting the reflected waves; in a signal that defines the timing of a signal with the value of half the amplitude, the timing errors are created to thereby reduce the timing margin. In order to resolve the stepped waveforms, there is a method of connecting a terminating resistor at the termination of the bus line to let the reflected waves loose (escape). But then, the voltage increases by the reflected waves disappear, and there appear the demerits: (1) a decrease of the voltage amplitude, and (2) an increase of the current consumption, which cannot be a desirable method.
Then, the inventor came to an idea to resolve the above problems (1), (2), since, in the memory system using plural memory modules, all the memory modules will attain the waveform similar to that of the memory module (3) in FIG. 14 (a) and FIG. 14 (b), provided that the distances between each of the memory modules and the memory controller are all equal.
In the Japanese Published Unexamined Patent Publication No.Hei 10(1998)-3971, Hei 11(1999)-40294, Hei 10(1998)-335546, Hei 8(1996)-314800, Hei 4(1992)-144160 as mentioned above, any one of these does not intend to equalize the distances between all the memory modules and the memory controller in order to solve the above problems (1), (2).
It is therefore an object of the present invention to provide a memory system that connects a memory controller to each of plural memory modules in an equal distance through socket pins branched from wirings on a mother board, by a newly-devised structure of a module socket that mounts the plural memory modules.
The above and other objects and novel features of the invention will become apparent from the descriptions and accompanying drawings in this specification.
In accordance with one aspect of the invention, the memory system is a system that connects a memory controller and plural memory modules by way of wirings on a mother board in an equal distance. Using a socket having plural socket pins branched from one point, the memory system connects the wirings on the mother board to each of the plural memory modules, whereby the memory controller is made to connect to each of the memory modules in an equal distance.
In this configuration, each of the memory modules is mounted in a radial form on the mother board by way of the socket pins of the socket, or in parallel to the mother board.
Further, the one point (base point) from which the socket pins of the socket are branched is one point of the wiring on the mother board, or the one point is connected to a wiring on the mother board by way of the wirings inside the socket.
And, of the socket pins of the socket, the pins for an address signal, a control signal, a data signal, and a data management signal are common to each of the memory modules, and the pins for a clock signal, a clock management signal, a bank selecting signal, and a power supply signal are separated with each of the memory modules.
Also, termination resistors are connected to one ends of the wirings on the mother board, or they are connected to both ends of the wirings.
In accordance with another aspect of the invention, the memory system includes a memory controller and plural memory modules connected by way of wirings on a mother board, and satisfies the condition:
difference of a distance between the nearest memory module and the farthest memory module, viewed from the memory controller
 less than  (thickness of memory module board+thickness of mounted memory IC)xc3x97 (number of the memory modules xe2x88x921).
Thereby, the memory system is able to suppress differences of signal arrival times due to differences of distances, and timing errors by reflected waves.
In accordance with another aspect of the invention, the memory system includes a board, a memory controller laid out on the board, and a socket laid out on the board, on which plural memory modules can be mounted. Thereby, the memory controller is made to connect in an equal distance to each of the plural memory modules to be mounted on the socket.
In accordance with another aspect of the invention, the memory system includes a board, a memory controller laid out on the board, and a connecting member laid out on the board, which includes a first mounting slot having a plurality of first terminals and a second mounting slot having a plurality of second terminals. And, a first memory module can be mounted on the first mounting slot so as to connect a plurality of the first terminals of the first mounting slot to a plurality of a third terminals of the first module, and a second memory module can be mounted on the second mounting slot so as to connect a plurality of the second terminals of the second mounting slot to a plurality of a fourth terminals of the second module. And thereby, a wiring distance between the memory controller and one terminal of a plurality of the first terminals is made to be substantially equal to a wiring distance between the memory controller and one terminal of a plurality of the second terminals corresponding to the one terminal of the first terminals.
In accordance with another aspect of the invention, the memory system includes a board, a control device laid out on the board, having a first terminal, a connecting member laid out on the board, which includes a first mounting part having a second terminal and a second mounting part having a third terminal corresponding to the second terminal. Also, a first memory module can be mounted on the first mounting part, a second memory module can be mounted on the second mounting part, the first memory module has a fourth terminal, the second memory module has a fifth terminal, when the first memory module is mounted on the first mounting part, the second terminal is connected to the fourth terminal, and when the second memory module is mounted on the second mounting part, the third terminal is connected to the fifth terminal. Thereby, the shortest distance of wirings between the first terminal of the control device and the second terminal of the first mounting part is made to be substantially equal to the shortest distance of wirings between the first terminal of the control device and the third terminal of the second mounting part.
Further, the connecting member according to the invention includes a first mounting part having a first terminal, a second mounting part having a second terminal corresponding to the first terminal, and a third terminal. And, a first memory module can be mounted on the first mounting part, a second memory module can be mounted on the second mounting part, the first memory module has a fourth terminal, the second memory module has a fifth terminal corresponding to the fourth terminal, when the first memory module is mounted on the first mounting part, the first terminal is connected to the fourth terminal, when the second memory module is mounted on the second mounting part, the second terminal is connected to the fifth terminal, the third terminal is connected to the first terminal of the first mounting part by a first wiring member, and the third terminal is connected to the second terminal of the second mounting part by a second wiring member, whereby a length of the first wiring member is made equal to a length of the second wiring member.
USPTO Backgrounds
USPTO Backgrounds