1. Field of the Invention
The present invention relates to a differential transconductance amplifier, and more specifically to an accurate transconductance amplifier having all transistors of a same conductivity type.
2. Discussion of the Related Art
FIG. 1 schematically shows a conventional structure of an accurate transconductance amplifier. The amplifier includes a first pair of NPN transistors Q1 and Q2 whose collectors are coupled to a high supply voltage Vcc through respective current sources 10 and 11. The current sources 10 and 11 deliver each a same current I. A resistor R is connected between the emitters of transistors Q1 and Q2. The bases of transistors Q1 and Q2 respectively receive two components V1 and V2 of a differential input voltage.
Two NPN transistors Q3 and Q4 have their emitters connected to a low supply voltage Vee and their collectors respectively connected to the emitters of transistors Q1 and Q2. The bases of transistors Q3 and Q4 are respectively connected to the collectors of transistors Q1 and Q2 through two level shifters 13 and 14. The purpose of these level shifters is to drive the bases of transistors Q3 and Q4 at a suitable voltage from the collectors of transistors Q1 and Q2.
The output of this amplifier is a differential current i.sub.1-i.sub.2, where i.sub.1 and i.sub.2 designate the respective current variations in transistors Q3 and Q4. This differential output current is expressed by EQU i.sub.1 -i.sub.2 =-2(V1-V2)/R
with an error of the order of 1/.beta..sup.2, where .beta..sup.2 is the product of the gains of transistors Q1 and Q3 or Q2 and Q4.
The fact that transistors Q1 to Q4 are all NPN transistors increases the accuracy and speed with respect to structures using a combination of NPN and PNP transistors, since PNP transistors have substantially less gain and bandwidth than NPN transistors. A problem encountered in the structure of FIG. 1 is the difficulty in obtaining a high signal-to-noise ratio or high dynamic range. The low limit of the dynamic range is determined by the input noise of the amplifier, while the high limit is ideally determined by the supply voltage Vcc.
The highest possible value of voltages V1 and V2 depends on the structure of level shifters 13 and 14.
For voltages V1 and V2 to be able to reach the lowest possible value, the emitters of transistors Q3 and Q4 are directly connected to the low supply voltage Vee and their currents i.sub.1 and i.sub.2 are copied into respective NPN transistors Q5 and Q6. Transistors Q5 and Q6 are connected in parallel by their bases and emitters to transistors Q3 and Q4. The output currents i.sub.1 and i.sub.2 are then taken from the collectors of transistors Q5 and Q6.
With this structure, each of voltages V1 and V2 may reach a value as low as EQU Vee+Vces+Vbe
where Vces is the saturation collector-emitter voltage of transistors Q3 and Q4, and Vbe the base-emitter voltage of transistors Q1 and Q2.
The total noise at the input of the amplifier can be expressed by EQU N(V.sup.2 /Hz)=4kT(2r.sub.b +r.sub.e +R)+4kTZ.sub.s +2kTZ.sub.s.sup.2 /.beta.r.sub.e
where r.sub.b and r.sub.e are the base and emitter resistances of the input transistors Q1 and Q2, and Z.sub.s is the output impedance of the source which provides voltages V1 and V2.
Further, the base resistance may be expressed by EQU r.sub.e =kT/qI.sub.c
where I.sub.c is the collector current of the input transistors Q1 and Q2. (k, T, and q are the Boltzmann constant, the absolute temperature, and the charge of an electron, respectively.) This input noise has a minimum value for EQU r.sub.e =Z.sub.s / EQU or I.sub.c =kT/qZ.sub.s
which determines the optimum value of the collector currents of transistors Q1 and Q2, thus the optimum value Iopt of the currents provided by the sources 10 and 11.
The differential output current i.sub.1 -i.sub.2 may reach a maximum value of 2I. However, to avoid distortion, value 2I is chosen larger than the maximum desired value for i.sub.1 -i.sub.2. In many cases, especially when impedance Z.sub.s is high, it will not be possible to choose a value 2I which ensures both optimal input noise characteristics and a distortion-free maximum output signal.
FIGS. 2A and 2B both illustrate one half of the transconductance amplifier of FIG. 1, with two different examples of a level shifter 13.
In FIG. 2A, the level shifter 13 includes a PNP transistor Q7 whose base is connected to the base of transistor Q1. The emitter of transistor Q7 is connected to the collector of transistor Q1 and its collector is connected to the base of transistor Q3.
With this structure, the voltage at the collector of transistor Q1 is fixed to V1+Vbe, where Vbe is the base-emitter voltage of transistor Q7. Therefore, voltage V1 may not exceed the value Vcc-Vsat-Vbe, where Vsat is the saturation voltage of current source 10 (usually a transistor). Transistor Q7 has the drawback of adding significant input noise to the amplifier, since the base of transistor Q7 is connected to the input of the amplifier.
FIG. 2B shows an example of a level shifter 13 which does not add input noise to the amplifier. Level shifter 13 includes an NPN transistor Q8 whose base is connected to the collector of transistor Q1. The collector of transistor Q8 is coupled to voltage Vcc, and its emitter is coupled to the base of transistor Q3.
With this structure, voltage V1 may however not exceed value Vee+3Vbe-Vces, where Vces is the saturation collector-emitter voltage of transistor Q1. This value could be increased by inserting diodes between the emitter of transistor Q8 and the base of transistor Q3, but the supply voltage of the amplifier should then remain relatively high.
USPTO Backgrounds
USPTO Backgrounds