1. Field of the Invention
The present invention relates to a data processor such as a microprocessor, and more specifically, the present invention relates to an information processor capable of improved memory access speed and reduced operating power consumption.
2. Description of the Background
One of the main operations of processors is to gain access to a memory designated by an address and to read data of the memory. These functions encompass a significant factor in determining the performance of a processor. In general, the sum of values of two registers in a processor is used as the memory access address. The values obtained by accessing the memory are then stored in the registers, and the “registered values” (i.e., the values of the data in the registers) are used to calculate an address for the next memory access. Accordingly, the ability to repeat these functions: addition; access; and registration, is a main factor in the performance of the processor. Because the route from an accessed memory to the registers can be concealed by controlling a bypass from the accessed memory to the adder, the processing speed of the repetition of addition to calculate an address and access to a memory determines the performance of the processor.
Many of the recent processors are provided with a cache memory or a translation lookaside buffer (TLB) to raise the memory-accessing speed. A cache memory is a high-speed memory used to store part of the data in the main memory. The TLB is a high-speed memory used to store part of the data for address translation and memory protection information. In either case, the memory-accessing operation is governed by addresses generated by the operation of the addition mentioned above.
Some processors, which require high-performance memories, are provided with various memories such as memories for users' free use and memories specializing in the processing of digital signals in addition to cache memories and TLBs. These memories are arranged in an address space in each processor. A program gains access to a memory by means of an address indicating the specific space of a type of memory. In other words, the given address determines to which memory access should be made. In some high-speed processors, all of the types of memories are activated immediately after the addition for a memory-designating address, without waiting for the identification of the type of the memory in question, and data is thereafter read from only one relevant memory.
Japanese Patent Laid-open JP-A-76648/1992 discloses a method for quickly accessing a cache memory when the sum of values of two registers is used as a memory address. This method takes advantage of the fact that an entry address of a cache memory is determined by adding partial bits of the calculated address, and the method provides for access to such a memory by reading two successive entries, without waiting for the carry from addition of the lower bits, but by assuming the two cases in which the carry is “0” and “1.”
There are at least two main problems with these conventional methods. The first problem is electric power consumption. If all the memories of a processor with various types of memories are operated to increase the accessing speed, excess power is consumed. A requirement for a reduction in the power consumption of processors for battery-driven mobile equipment in particular has been increasing. Likewise, desktop equipment requires the reduction in the quantity of heat generated by the LSI as clock frequencies of processors increase. The power consumption can be reduced by determining the relevant memory type after calculating the memory-designating address, but this approach does not meet the requirement for high memory access speed.
The second problem is involved in the approach of JP-A-76648/1992. This approach raises the memory-accessing speed but cannot flexibly be applied to TLBs. To avoid a conflict of TLB entries under a plurality of processes, the results of addition are often hash processed by an address space identifier (ASID) and then used as entry addresses. An Exclusive OR (XOR) for each bit is often used in hash processing. In this case, two entry addresses do not necessarily turn out to be successive. A specific example will be described below, assuming that the entry addresses of a TLB are five bits long, an entry address obtained by addition is “00001”, and appointed ASIDs are “00000” and “00001.”
ASID0000000001Entry addresses (without0000100000carry)Entry addresses (with carry)0001000011
It is assumed in the conventional method disclosed in JP-A-76648/1992 that the entry address without carry and the entry address with carry turn out to be successive; therefore, this approach cannot be applied to the TLB of which the above entry addresses are hash processed. Additionally, it is suggested in the drawings of JP-A-76648/1992 to read out two pieces of data from a single memory mat. Accordingly, it is necessary to use a dual-port-type memory with a specialized address decoder. The area of the memory, therefore, increases, and the “specialty” nature of the memory confines its application to a relatively narrow range of products.
USPTO Backgrounds
USPTO Backgrounds