The present application relates to semiconductor device fabrication, and more specifically to the fabrication of an electrostatic discharge (ESD) protection structure containing vertically stacked diodes.
It is well known that extremely high voltages can develop in the vicinity of an integrated circuit due to the build-up of static charge. When the electrostatic energy is discharged, a high current is produced through devices of the integrated circuit. Electrostatic discharge (ESD) is a serious problem for semiconductor devices, since it has the potential to destroy the device and the entire integrated circuit. ESD protection devices are generally integrated into the integrated circuits to protect the circuits from ESD events. An ESD protection device can provide a current path so that when an ESD transient occurs, the ESD current is conducted through the ESD protection device without going through the devices to be protected.
Diodes are needed to form ESD protection devices. FIG. 1 illustrates a basic ESD protection circuitry 100 in which an I/O pin 102 accepts a high voltage or a high current discharge that could occur with an ESD event. In order to protect the integrated circuit (IC) 104 from negative effects of the ESD event, a first diode 106 discharges the excess voltage to a supply voltage Vdd. In some cases, and when a negative high voltage (or current) occurs, a second diode 108 discharges the excess voltage to ground Vss. Unfortunately, those diodes 106, 108 are implemented as planar diodes and thus take up a relatively large area of real estate on the chip. Therefore, there remains a need to provide ESD protection structures with reduced diode footprint (i.e., the total chip area occupied by the diodes).
USPTO Backgrounds
USPTO Backgrounds