The invention relates to a semiconductor device, and a method of manufacturing the same, and in particular, to a technology effective when applied to a semiconductor device with a nonvolatile memory mounted over the same silicon substrate where a logic semiconductor device is mounted.
For example, in Japanese Unexamined Patent Publication No. 2003-204003 (Patent Document 1), there has been disclosed a semiconductor integrated circuit memory comprising a boost circuit including a capacitive element comprised of a lower electrode, a capacitive insulating film, and an upper electrode, and nonvolatile memory cells. The lower electrode of the capacitive element is formed in a shape such that a surface area thereof is increased by working on the shape. Further, the lower electrode and the upper electrode of the capacitive element are formed in the step of forming a floating gate, and a control gate electrode of the nonvolatile memory cell, respectively.
Further, in Japanese Unexamined Patent Publication No. 2003-60042 (Patent Document 2), there has been disclosed a capacitive element wherein a semiconductor substrate is used as a first electrode, and second and third electrodes, each being made of polysilicon, are deposited over the first electrode. The capacitive element is structured such that a first capacitor is formed of the first electrode, and the second electrode while a second capacitor is formed of the second electrode, and the third electrode, thereby causing respective capacitances of the first and second capacitors to be directly decided.
Still further, in Japanese Unexamined Patent Publication No. 2006-019373 (Patent Document 3), there has been disclosed a split-gate MONOS memory cell having a gate electrode of a select type field effect transistor, and a gate electrode of a memory field effect transistor.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2003-204003    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2003-60042    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2006-019373
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