1. Field of the Invention
The present invention relates to a method of building an emulation system using a plurality of custom prototyping boards and, more particularly, to a method of building a scalable, high throughput emulation system using a plurality of custom prototype boards with FPGA devices.
2. Description of the Prior Art
Various semiconductor, circuit, and integrated circuit (“IC”) devices, such as system-on-chip (“SoC”) devices, are emulated or verified during their design and development processes. As an example, highly-integrated SoC devices may power or support a wide variety of products to facilitate various hardware, software, and/or device applications. To meet these demands, SoC devices continue to increase in size and complexity, and their capabilities and manufacturability are in part aided by advance semiconductor processing technologies and availability of verified and well-developed libraries, e.g. design or circuit intellectual property (“IP”) libraries. The development of SoCs or other circuits or devices in some cases nevertheless may increase the burden on design verification processes, methods, or systems. In some cases, verification may consume a significant amount of time or resources during an SoC development cycle.
Circuit design verification approaches can vary. Given the expectation for speed, the various approaches of software development, hardware development, or system validation may provide varying levels of observability and control. Field programmable gate array (“FPGA”) prototype systems, for example, can provide improved system execution time due to its hardware-based implementation. Some FPGA verification systems, nevertheless, lack the ability to isolate some of the root causes of discoverable errors for various reasons. For example, the lack of visibility regarding the multitude of signals within the design. Depending on the environment, software, and hardware constraints, in some cases, deficiencies in certain FPGA vendor-specific verification tools may include access to a limited number of signals, and limited sample capture depth. Even combined with an external logic analyzer, FPGA vendor-specific verification tools, in some instances, may lack sufficient capabilities to isolate root cause errors during design verification.
Verification systems may also support co-simulation and co-emulation using the FPGA devices. However, the FPGA device and devices are generally part of a closed vendor proprietary system, and such vendor-specific verification tools typically only work with their own FPGA device types and typically cannot be customized to other FPGA type devices. Therefore, users can not use or design their own FPGA-based prototyping systems.
How to verify or validate a complex IC or system design becomes a big challenge as the gate count and size of the IC or system design keep increasing. Normally, designers prefer to do their own prototyping during designing stage to filter out all possible design errors before the IC or system design is moved to a next stage for stress testing to validate the IC or the whole system design. However, by doing their own prototyping, when a bug is found or a failure is occurred during the debugging stage, it is difficult to trouble-shoot the bug due to the fact that there is a limited resources in the prototyping boards or system to bring out or trace all the relevant signals in order to analyze the cause of the bug. Conventionally, designers can use a dedicate emulation system such as Quickturn's Palladium for emulating the IC or system design; however, it is very costly and not suitable for some IC or system prototyping.
In addition, SoC design verification requires both software and hardware working together, which is usually tested on a prototype board in order to make sure the system behaves as expected. Conventional dedicated FPGA emulation system is very costly. Software based simulation has the advantages by putting everything together at system level to verify the system while monitoring all the internal signals; however, it is very slow and hence not practical for system level testing for a complicated SoC design.
Customer built prototype board based on software and hardware integration provides a simple way to verify the system design, but it has limited capability to isolate the root cause of discovered errors due to the lack of controllability and observability of the prototype board.
Therefore, what is needed is a debugging methodology to work with the customer prototype boards to verify a circuit design.
USPTO Backgrounds
USPTO Backgrounds