1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices and, more particularly, to a method for separating individual semiconductor chips from a semiconductor wafer and mounting such semiconductor chips in a semiconductor device package.
2. Description of the Related Art
Generally, a conventional semiconductor device fabrication process concludes with sawing, chip attaching, wire-bonding and molding processes. The sawing process is typically utilized to saw through predetermined portions of a semiconductor wafer to divide it into individual semiconductor chips. The chip attaching process will then typically separate the individual semiconductor chips and frequently attach them to a circuit substrate. The wire-bonding process is then typically used to form electrical connections between conductive regions on the individual semiconductor chips and corresponding conductive regions on the circuit substrate using a series of conductive bonding wires. The molding process will then typically be used to encapsulate the semiconductor chips, the bonding wires and a portion of the circuit substrate with a resin molding material to protect them from the external environment.
Semiconductor chips are conventionally attached to a circuit substrate using an adhesive that is applied to a mounting portion of the circuit substrate after which the semiconductor chip is pressed onto the adhesive covered portion of the circuit substrate. The adhesive may be a resin paste adhesive such as an Ag-epoxy adhesive and may be applied to the circuit substrate by a number of methods including, for example, stamping, dispensing or screen printing methods. Of the various methods, the dispensing method is still perhaps the most commonly used method for conventional attachment.
In the dispensing method the resin paste adhesive is typically stored in a syringe and then is discharged in controlled amounts onto a predetermined region of the circuit substrate by the dispenser mechanism. However, in instances in which the size of the semiconductor chip is relatively large, the dispensing method is more likely to experience difficulties in applying a uniform thickness of the resin paste adhesive on the predetermined region of the circuit substrate. In addition, voids may occur in an adhesive layer of the resin paste adhesive during the curing process that typically follows the chip attaching process.
Attempts to address these difficulties have included the method disclosed in Japanese Patent Laid-Open Nos. 63-289822 and 1-19735 in which an adhesive film is utilized to attach the semiconductor chip to the circuit substrate. This method, however, tends to introduce its own complications including, for example, the need to cut the adhesive film to correspond to the size of the semiconductor chip and the need for additional apparatus for arranging and attaching the cut film to the semiconductor chip.
An attempt to improve upon the initial adhesive film methods is disclosed in Japanese Patent Laid-Open No. 2000-104040 in which an adhesive tape is attached to the backside of a backlapped semiconductor wafer, typically by using a heat-compression method. The semiconductor wafer, which the attached adhesive tape, is then attached to a sawing tape and sawn to separated the semiconductor wafer into the individual semiconductor chips each of which includes a corresponding portion of the adhesive tape. The individual semiconductor chips and the portions of the adhesive tape provided on their backside may then be separated from the sawing tape and attached to a circuit substrate.
The heat-compression process used to attach the adhesive tape to the semiconductor wafer typically uses a combination of a press roller and a heat plate to heat the adhesive tape and press it against the backside surface of the semiconductor wafer. However, the risk of damage to the semiconductor wafer resulting from the thermal and mechanical stresses applied to the semiconductor wafer during the heat-compression method will tend to increase as the semiconductor wafer thickness is reduced and/or the semiconductor wafer diameter is increased. As a result, larger and/or thinner semiconductor wafers are more likely to be bent, warped or cracked when attached using the heat-compression method, rendering this technique is less suitable for such wafers. These complications associated with the heat-compression technique are only being exacerbated by the continuing trend toward thinner and smaller semiconductor devices formed on increasingly larger semiconductor wafers.
The semiconductor wafer may be formed in the shape of a disc with a thickness of as much as 700 μm or more to provide the mechanical strength necessary to survive the handling during the fabrication process. After the fabrication process has formed the semiconductor device structures, a passivation layer of predetermined thickness is typically formed on the active surface of the semiconductor wafer to protect the integrated circuits and may be formed from an inorganic insulator such as nitride or a polymeric material such as polyimide.
The coefficient of thermal expansion (CTE) of polyimide is, however, larger than the CTE of silicon so when a polyimide layer covering the active surface of the semiconductor wafer is cured, the polyimide may shrink and tend to warp the semiconductor wafer. When the semiconductor wafer is 700 μm thick, the silicon will tend to have sufficient stiffness to limit the extent of the warping, but when the thickness of the semiconductor wafer is reduced by backlapping, backgrinding or polishing prior to assembly, the extent of the warp will tend to increase. For example, if a 200 mm diameter semiconductor wafer is backlapped to a thickness of 200 μm or less, or a 300 mm diameter semiconductor wafer is backlapped to a thickness of 400 μm or less, the likelihood that a semiconductor wafer having a polyimide passivation layer formed on the active surface will warp increases and that the degree of the warp will be large enough to complicate or prevent the successful completion of subsequent semiconductor device manufacturing processes.
A method intended to reduce or to prevent warping of semiconductor wafers having a polyimide film or a metal film formed on the backside surface is disclosed in Korean Patent Laid-Open No. 2002-049720 and Japanese Patent Laid-Open Nos. 2000-133638 and 2001-093863. The disclosed method utilizes an additional resin paste adhesive during the semiconductor chip attaching process. Although the disclosed method may be successful in reducing or preventing the warping of a semiconductor wafer, it does not address or overcome the other problems associated with the use of the resin paste adhesive.
USPTO Backgrounds
USPTO Backgrounds