Integrated circuits produced by SOI technology exhibit a certain number of advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits also induce lower parasitic capacitances, which make it possible to improve switching speed. Moreover, the phenomenon of parasitic triggering (“latchup”) encountered by MOS transistors in Bulk technology can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC or MEMS type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiations and thus turn out to be more reliable in applications where such radiations may induce operational problems, in particular in space applications. SOI integrated circuits can in particular comprise random-access memories of SRAM type or logic gates.
The reduction in the static consumption of logic gates while increasing their toggling speed forms the subject of much research. Certain integrated circuits currently being developed integrate at one and the same time logic gates with low consumption and logic gates with high toggling speed. To generate these two types of logic gates on one and the same integrated circuit, the threshold voltage of certain transistors of the logic gates with fast access is lowered, and the threshold voltage of other transistors of the logic gates with low consumption is increased. In Bulk technology, the modulation of the threshold voltage level of transistors of the same type is performed by differentiating the doping level of their channel. However, in FDSOI (for “Fully Depleted Silicon On Insulator”) technology, the doping of the channel is almost zero (1015 cm−3). Thus, the doping level of the channel of the transistors therefore cannot exhibit any significant variations, thus preventing the threshold voltages from being differentiated in this way. A solution proposed in certain studies in order to produce transistors of the same type with distinct threshold voltages is to integrate different gate materials for these transistors. However, the practical production of an integrated circuit such as this turns out to be technically tricky and economically prohibitive.
In order to have distinct threshold voltages for different transistors in FDSOI technology, it is also known to use a biased ground plane disposed between a thin insulating oxide layer and the silicon substrate. By altering the doping of the ground planes and their bias, it is possible to define a range of threshold voltages for the different transistors. This will therefore yield transistors with low threshold voltage termed LVT (for “Low VT”, typically 400 mV), transistors with high threshold voltage termed HVT (for “High VT”, typically 550 mV) and transistors with medium threshold voltage termed SVT (for “Standard VT”, typically 450 mV) or RVT (for “Regular VT”).
To allow the operation of the different transistors, it is necessary to electrically insulate them from one another. Consequently, the transistors are generally surrounded by isolation trenches (designated by the acronym STI for “Shallow Trench Isolation”) which extend as far as the wells.
In a known manner, integrated circuits such as these also include devices for protection against accidental electrostatic discharges (ESD) that might impair these transistors.
The following documents are known from the prior art:                US 2009/134468 A1;        US 2007/063284 A1;        WO 2010/112585 A1;        J. P. Noel et al., “Multi-VT UTBB FDSOI Device 10 Architectures for Low-Power CMOS Circuit”; IEEE        
Transactions on Electron Devices, vol. 58, p. 2473-2482, 1st August 2011;                J. P. Noel et al., “UT2B-FDSOI device architecture dedicated to low power design techniques”; Proceedings of IEEE ESSDERC 2010.        WO 2011/089179 A1.        
There exists a need for protection against electrostatic discharges that is not detrimental to the compactness of the integrated circuit, capable of evacuating a localized discharge whatever its polarity, and inexpensive.
USPTO Backgrounds
USPTO Backgrounds