A major module in the architecture of computer systems is the memory system which works in conjunction with the main processor and which memory system holds and supplies the data and instructions necessary to operation of the system. One such type of memory system involves the use of PROM memory modules which involve programmable read-only memory units which are generally used to hold "fixed" data for use of the computer system. Alternatively, read-only memories or ROMs are also used for this purpose.
The information stored in the PROM/ROM memory is critical to the integrity of system operation and such system operation can run into problems of data corruption should the data from the memory chip be corrupted or altered.
As examples of important and significant data which may reside in a PROM or a ROM memory system, are such items as:
(i) low level "bootstrap" (start-up) program code which is used to initialize a system;
(ii) specialized and unique information for system identification and configuration functions;
(iii) data integrity value information such as encryption or decryption keys.
The integrity of the ROM/PROM data is especially critical since a system may not yet be sufficiently initialized (up) enough at the period of initialization before other higher and more sophisticated levels of error detection are functioning operationally.
The general and common method of error detection in memory systems, whether RAMs (random access memories) or ROMs/PROMs is the use of the "parity" data system for checking data integrity.
Parity is a method whereby "extra" data bits are stored along with the "real" data bits. These extra bits, called "parity" bits contain a value that is based upon the value of the actual data package under consideration. At such time as the data information is read-out from memory, the parity bits are read-out as well.
The parity value of the "actual data read out" is recalculated from the real data bits (via a parity logic circuit) and the calculated parity value is then compared to the parity bit or bits read out from the parity memory. If these two values are equal, then there is a high probability that the actual data read-out is valid and free from errors that may have been induced during the writing-in, the storage, and the reading-out of the data in the memory subsystem. In this parity checking system for memory chips, several factors are extant:
(a) Extra storage elements (ROM/PROM chips) are required to store the parity bit(s);
(b) A means of collecting and checking out the parity bits must be added to this system structure.
One example of a parity check system in the prior art is shown in U.S. Pat. No. 4,809,279 which is commonly assigned to the same ownership as the instant application. This type system is limited to only one type of parity operation (odd parity) while the instant application provides a choice factor for using odd or even parity plus other advantages in terms of cost, efficiency and uniformity of memory chips.
In the present commercial marketplace, standard parity-checking integrated circuit chips (IC's) are available. These devices use one parity bit for each eight bits of information (data). Thus it can be realized that one bit of extra memory must be added to the memory system for each eight bits (data) of system memory width. Since most functioning practical systems have requirements for memory wider than eight bits, this can lead to problems involving additional cost consideration and space requirements in the system.
Due to this impracticability, it would appear that few systems use data integrity schemes for PROM/ROM memory data structures. Thus the architectural arrangement presented herein provides a means for reducing the cost of parity schemes in PROM memory systems, permits uniformity of PROM/ROM chips or modules, and most importantly, permits means for insuring the integrity of the memory system by permitting the detection of data corruption errors in the PROM/ROM memory banks. Additionally, the memory structure described has the feature of permitting the choice of odd or even parity schemes at will.
Because of the use of fewer memory chips and the uniformity of using the same type of memory chips, it is now possible to provide considerable efficiencies in operation and cost reduction.
USPTO Backgrounds
USPTO Backgrounds