1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device comprising a combination of a bipolar and a CMOS (complementary metal oxide semiconductor).
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of a structure of a random access memory (RAM).
In FIG. 1, a plurality of word lines and a plurality of bit lines are arranged to intersect with each other in a memory cell array 50, memory cells being arranged at intersections of the word lines and the bit lines. A single word line in the memory cell array 50 is selected by an X address buffer decoder 52 and a single bit line in the memory cell array 50 is selected by a Y address buffer decoder 54, so that a memory cell provided at an intersection of the word line and the bit line is selected. Data is written into the selected memory cell or data stored in the memory cell is read out. Writing or reading of data is selected by a read/write control signal R/W applied to an R/W (read/write) control circuit 56. At the time of writing data, input data Din is inputted to the selected memory cell through the R/W control circuit 56. In addition, at the time of reading data, the data stored in the selected memory cell is detected and amplified by a sense amplifier 58, and provided to the exterior as output data Dout through a data output buffer 60.
The RAM generally includes a bipolar RAM comprising a bipolar transistor and an MOS.sup.. RAM comprising an MOS transistor. The bipolar RAM is suitable for high-speed operation but consumes much power, so that integration can not be increased. On the other hand, the MOS.sup.. RAM is slower in operating speed but consumes less power, as compared with the bipolar RAM, so that high integration can be obtained.
Recently, in order to obtain a large capacity memory capable of performing high-speed operation and having a reduced consumed power, a Bi-CMOS.sup.. RAM comprising a combination of a bipolar and a CMOS has been proposed. The Bi-CMOS.sup.. RAM is disclosed in, for example, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. SC-21, No. 5, October 1986, pp. 681-684. In the Bi-CMOS.sup.. RAM, a memory cell array comprises an MOS transistor, and a peripheral circuit such as an address buffer decoder comprises a bipolar transistor or a combination of the bipolar transistor and the MOS transistor.
FIG. 2 is a block diagram showing a structure of an address buffer decoder.
In FIG. 2, a plurality of address terminals 70 are connected to input terminals of a decoder circuit 78 through address buffer circuits 72, level converting circuits 74, and driver circuits 76, respectively.
Each of the address buffer circuits 72 comprises a bipolar ECL (emitter coupled logic) circuit, and an address signal at an ECL level (the potential at an "H" level=-0.9 V and the potential at an "L" level=-1.7 V) is inputted to each of the address terminals 70. Each of the level converting circuits 74 comprises a CMOS, and converts the address signal of the ECL level outputted from each of the address buffer circuits 72 into an address signal of an MOS level (the potential at an "H" level=0 V and the potential at an "L" level=-4.5 V). Each of the driver circuits 76 comprises a CMOS and a bipolar transistor having high driving ability. The decoder circuit 78 decodes a binary signal comprising a plurality of address signals and applies a selecting signal to one of a plurality of selecting lines 80. Therefore, a memory cell on the selecting line is selected.
According to the above described conventional address buffer decoder, in order to convert a signal of the ECL level into a signal of the MOS level at the high speed in each of the level converting circuits 74, gate capacitance of an MOS transistor receiving the signal must be rapidly charged or discharged. Therefore, current flowing through each of the level converting circuits 74 must be increased, so that consumed power is increased.
USPTO Backgrounds
USPTO Backgrounds