This invention relates generally to semiconductors and, more specifically, relates to reducing soft error rates in semiconductors.
Soft error rates in integrated circuits are caused by ionizing radiation, such as alpha particles passing through the semiconductor materials of the integrated circuit. Both logic and memory circuits may be affected. The errors are called “soft” because they generally only persist until the next cycle of the integrated circuit function. As an alpha particle passes through semiconductor material, a “cloud” of hole-electron pairs are generated in the vicinity of its path. Electric fields present in the integrated circuit can cause the holes and electrons to migrate in opposite directions, thus causing extra charge to reach particular circuit nodes and upset the function of the integrated circuit.
There are a few potential sources of alpha particles in a typical integrated circuit chip connected to its associated package using solder bumps (also known as controlled collapse chip connections or C4s). For example, in the case that the solder bumps are lead (Pb), tin (Sn) or a combination of Pb and Sn (or their alloys, such as Sn alloyed with silver, Ag), the solder bumps may contain radioactive polonium (Po) and Pb isotopes that may emit about 5.3 MeV (million electron-volt) alpha particles (that is, alpha particles having 5.3 MeV units of energy). While the quantities of radioactive Po and Pb may be in the parts-per-billion (ppb) range, the flux of alpha particles emitted may be sufficient to cause soft-error rates that exceed the allowable maximum for advanced integrated logic and memory circuits if the alpha particles are allowed to penetrate into the substrate or device levels of the integrated circuit. The substrate may include the silicon portions of active devices (examples of which include field effect and bipolar transistors) that can be sensitive to alpha particle-induced upsets, and device levels may include portions of the active devices above the surface of the substrate and containing semiconductor materials, such as polysilicon gates of field effect transistors.
As integrated circuit devices continue to be scaled, capacitor cell sizes and operating voltages continue to decrease while circuit density increases. This causes an increase in the probability of an integrated circuit experiencing a soft error. Therefore, there is a need for improved methods and structures for reducing soft error rates in integrated circuits.
USPTO Backgrounds
USPTO Backgrounds