In designing phase-locked loops ("PLLs") for semiconductor integrated circuits ("ICs"), a goal is to minimize "jitter" at the output of the PLL. Typically, in a PLL circuit that uses a voltage-controlled oscillator ("VCO") to generate the PLL's output signal, noise picked up by the VCO on the input control lines is a major cause of such jitter. Another goal in designing PLLs for semiconductor ICs, is to maximize the stability of the PLL's control circuit and, therefore, maximize the overall frequency stability of the PLL. Essentially, additional circuitry is needed in the PLL to reduce jitter and increase the frequency stability of the output signal. However, an overriding goal in designing PLLs for semiconductor ICs is to keep the size of the PLL circuit as compact as possible, which translates to a requirement to minimize the number of transistors and components used in the overall PLL circuit. Therefore, it has been difficult to implement an appreciable reduction in output jitter and increase in frequency stability in a compact PLL circuit design for a semiconductor IC.
An additional semiconductor IC design goal is to minimize power consumption of the PLL circuit during a "power down" situation when the circuit is not activated. Essentially, unless the PLL's transistors are actively and completely shut down during "power down," an excessive amount of current may be drawn from the circuit by an external load. Since additional circuitry is needed to turn off the PLL's transistors completely, it has long been difficult to implement such a "power down" capability in a compact circuit design.
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