1. Field of Invention
The present invention relates to an interconnect model-order reduction method. More particularly, the present invention relates to a rapid and accurate interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network for signal analysis.
2. Related Art
Complemented metal oxide semiconductor (CMOS) technology has heretofore advanced to be measured at a nano-level, and, thus, the parasitic effect to interconnects of the related semiconductor device cannot be neglected. Since the complexity of a circuit associated with the semiconductor device is increased, the order of the corresponding interconnect model is also increased. Consequently, an efficient interconnect model-order reduction has become a necessity of modeling and simulation of the interconnect network. Such methods may be referred to in, for example, U.S. Pat. Nos. 6,023,573, 6,041,170 and 6,687,658. These circuit model-order reduction methods set forth in recent years are herein summarized as follows. 1. Asymptotic waveform evaluation (AWE), which was set forth in an article by L. T. Pillage and R. A. Rohrer, entitled “Asymptotic waveform evaluation for timing analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 4, pp. 352-366, 1990. 2. Pade via Lanozos (PVL), which was set forth in an article by P. Feldmann and R. W. Freund, entitled “Efficient linear circuit analysis by Pad'e approximation via the Lanczos process,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14 pp. 639-649, 1995. 3. Symmetric Pad'e via Lanczos, which was set forth in an article set forth by P. Feldmann and R. W. Freund, entitled “The SyMPVL algorithm and its applications to interconnect simulation,” Proc. 1997 Int. Conf. on Simulation of Semiconductor Processes and Devices, pp. 113-116, 1997. 4. Block Arnoldi, which may be seen In U.S. Pat. No. 6,810,506. 5. Passive reduced-order interconnect macromodeling (PRIMA) method, which was set forth in an article by A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: passive reduced-order interconnect macromodeling algorithm,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17 pp. 645-653, 1998.
The above methods are performed essentially based on a Krylov Subspace projection method, in which state variables of an original system (original interconnect network for the above and original system will be used through this specification) is projected to obtain state variables of a reduced-order system (reduced interconnect model for the above and reduced-order system will be used through this specification) by use of a projection operand. The required projector may be obtained by performing the iteration-based Krylov algorithm, in which the iteration number required to be conducted is an “order” of the reduce-order system. In this case, the order of the reduced-order system has to be determined in execution of the projection-based interconnect model reduction in such a manner that essential dynamics of the original system may be accurately reflected. The iteration process may be conducted by taking a residual error between transfer functions of the original system and the reduced-order system, respectively, as a reference for an end of such iteration process, wherein the residual error is defined as an error between the transfer functions of the original and reduced-order systems after specific times of iterations.
An example of a deduction of the error E(s) between the transfer functions of the original and reduced-order systems may be seen in an article set forth by Z. Bai, R. D. Slone, W. T. Smith and Q. Ye, entitled “Error bound for reduced system model by Pad'e approximation via the Lanczos process,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18 pp. 133-141, 1999. However, the error E(s) involves complicated computations of a resolvent matrix (In−sA)−1 of the original system, making it difficult to be used in a real application.
In Light of the above, there are still some shortcomings inherent in the prior art and thus improvements therefor are in an urgent need. In this regard, after looking at the problems encountered in the prior art, an efficient interconnect model-order reduction method was successfully developed in the present invention.
USPTO Backgrounds
USPTO Backgrounds