The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure including a buried semiconductor channel region positioned between a portion of a raised source region and a portion of a raised drain region both raised regions having wall profiles that are tailored to control gate overlap and gate underlap. The present disclosure also provides a method of fabricating such a semiconductor structure.
In modern integrated circuit manufacture, semiconductor devices, such as field effect transistors (FETs), are typically formed on a Si-containing substrate. In a typical FET, a source and a drain are formed in an active region of the Si-containing substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
The FET contact resistance often limits device performance by decreasing speed, increasing Joule heating, and degrading device reliability. Contact resistance is often improved by heavily doping the source region and the drain region via ion implantation. Despite improving the contact resistance, the aforementioned technique causes crystal damage, gate dielectric degradation, and current leakage paths.
Selectively grown raised source regions and drain regions (oftentimes referred as “RSD”) are promising candidates for replacing ion implantations, however, RSD regions must contact the channel and they must overlap (underlap) the gate region.
In view of the above, there is a continued need to provide a semiconductor device such as a FET in which the contact resistance thereof is reduced without using ion implantations and conventional RSD regions to obtain the improvement in contact resistance.
USPTO Backgrounds
USPTO Backgrounds