The present invention relates to a digital variable capacitance circuit, a resonant circuit, an amplification circuit, and a transmitter.
Japanese Unexamined Patent Application Publication No. 2007-149925 discloses a digital variable capacitance circuit that includes a plurality of capacity cells. A switching MOS transistor is connected in series to the ground side of each of the capacity cells. A P-channel MOS transistor that gives a high-level potential and an N-channel MOS transistor that gives a low-level potential are connected to the gate terminal of the switching MOS transistor. Since the potential level of the gate terminal of the switching MOS transistor becomes a low level, the resistance value of the variable resistance element is increased.
In the digital variable capacitance circuit disclosed in Japanese Unexamined Patent Application Publication No. 2007-149925, however, when a signal having a large voltage amplitude is supplied to an output terminal, a problem of a breakdown voltage or a leak current may occur.
The other problems of the related art and the novel characteristics of the present invention will be made apparent from the descriptions of the specification and the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds