This invention relates to a digital communication system and, more particularly, to a synchronization arrangement for use in a digital communication system.
In a pulse code modulation (PCM) system, digital signals from each of a plurality of input sources commonly arrive at a digital multiplex circuit. Known multiplex circuits include equipment for buffering the input signals and for interleaving the signals into a digital bit or pulse stream for transmission over a digital transmission link to a receiver. In the interleaving, it is usual to equalize, or synchronize, the bit rates of the signals from the different sources with the bit rate used on the transmission link. Various synchronization arrangements are known in the art. One arrangement, called pulse stuffing, is disclosed in U.S. Pat. No. 3,461,245 issued to V. I. Johannes et al. on Aug. 12, 1969 and entitled "System for Time Division Multiplexed Signals From Asynchronous Pulse Sources by Inserting Control Pulses." In pulse stuffing, an extra bit is selectively inserted, or stuffed, into the transmitted pulse stream and removed, or destuffed, at the receiver. For example, the pulse stream is usually transmitted at a bit rate higher than the bit rate of any of the input sources. Hence, inasmuch as bits may be transmitted faster than bits arrive, the multplex circuit buffer may eventually empty. Responsive to the detection of such an impending event, known pulse stuffing arrangements add a bit to the pulse stream as frequently as needed to equalize the input signal bit rate with the usually fixed bit rate of the transmission link, the latter as set by a master clock within the multiplex.
Pulse stuffing is usually an anathema to a block, or word, oriented system. This occurs, in part, because pulse stuffing is done on a bit-by-bit basis whereas a block oriented system usually operates upon a plurality of bits, called a block. For example, in block stuffing, a block of say N bits rather than the single bit of a pulse stuffing system is stuffed at the transmitter and destuffed at the receiver.
Whether in a pulse or a block stuffing system, the stuffed, transmitted pulse stream is usually read from a receiver buffer responsive to a read clock signal provided by a phase-locked loop (PLL) circuit. As an aside, it is well known that the design of a PLL circuit usually involves a tradeoff between speed of acquisition and filtering performance. For example, rapid acquisition of frequency synchronization with an input signal usually requires a high gain, wideband PLL. On the other hand, a low gain, narrowband PLL provides good filtering performance by shielding the local reference signal from the noise and phase jitter of the input signal. Continuing, the PLL circuit usually responds to control information for identifying the presence of the stuffed pulses. Unfortunately, as the number of consecutively stuffed pulses increases, such as is typical of a block system, so the jitter to, and hence the distortion of, the destuffed signal increases. Of course, the increased jitter could be mitigated by using a narrower-band PLL in the block system than would be used in a pulse stuffing system. In particular, to avoid increasing the jitter, the design bandwidth of a PLL typically decreases as the block size increases. However, as aforementioned, a narrower-band PLL is slower in acquisition time than a wideband PLL.
Accordingly, a broad object of our invention is to provide an improved synchronization arrangement for a block oriented digital communication system.
USPTO Backgrounds
USPTO Backgrounds