1. Field of the Invention
The present invention relates to circuit simulation and in particular to an automatic, hierarchy-independent partitioning method for transistor-level circuit simulation.
2. Discussion of Related Art
A current very-large-scale integrated (VLSI) circuit may include several million transistors and other devices. Because of its large size and inherent complexity, verification of VLSI circuit operation prior to manufacture is important to minimize manufacturing cost. Computer simulation, which takes into account accurate device models, can be used in this verification.
One simulation technique called SPICE (Simulation Program with Integrated Circuit Emphasis) translates a netlist describing the circuit elements and their connections into equations to be solved. These equations (typically non-linear, differential-algebraic equations) can be solved using sparse matrix techniques.
Conventional SPICE simulations of VLSI circuits can undesirably exhibit a non-linearity when the size of the circuit design increases. For example, when a VLSI circuit design is doubled in size, the SPICE simulation of that larger circuit design can take more than twice as long and use more than twice as much memory as the original circuit design. Thus, simulation of a full VLSI circuit by using conventional techniques can be prohibitively expensive even on the latest computers due to time and memory constraints.
For these reasons, other simulation techniques use partitioning to decouple electrically weakly-connected circuit components to form circuit blocks and then simulate such circuit blocks independently. This partitioning reduces circuit complexity, which can have significant time savings (due to facilitating parallel processing) and minimize memory requirements.
For a reasonably simple design with an ideal power supply, this “divide-and-conquer” approach can yield dramatic simulation performance and memory improvements with an acceptable loss of accuracy. However, for a large number of advanced technology circuits (e.g. flash memory or other designs having non-rail bulk, low power circuits designed with switched or otherwise controlled power supplies, CMOS imager circuits, phase-locked-loops with charge-pump filters, and any other design having some form of non-ideal or internal power supply), the ability to partition without incurring loss of accuracy is minimized. Thus, simulation technology with partitioning of weakly-connected circuit components is slow, inaccurate, and/or frequently runs short of available computer memory.
In yet another simulation technique called Fast-SPICE, a trade-off of accuracy and performance is set in simulating large circuits. Typically, Fast-SPICE can run much faster than SPICE by partitioning a netlist of the VLSI circuit based on strong feed-forward (a pre-calibrated cause/effect) or feedback (an output used as a dynamic control input) but not both. For example, the voltage of an ideal power supply (e.g. an external voltage source) is independent of the current drawn and therefore exhibits a strong feed-forward. As a result, Fast-SPICE can partition all devices directly connected to that ideal power supply across their power supply nodes. In addition, the voltage/timing of a digital gate is weakly dependent on the current into a MOSFET gate if the gate capacitance is attached to the driver and therefore also exhibits a strong feed-forward. As a result, Fast-SPICE can place the load of the gate of such a device in a “driver block”, thereby allowing the “driven block” to effectively see an ideal MOSFET in which the gate is replaced by an input voltage.
Fast-SPICE partitioning produces clusters of devices that are electrically decoupled so that they can be simulated separately and asynchronously. Unfortunately, in a design having a non-ideal (e.g. internal) power supply, partitioning by low-impedance paths (also called partitioning by strongly-connected blocks or channel-connected blocks) often leads to very large partition sizes. Specifically, because the non-ideal power source voltages are affected by the current load from the circuits they drive, these circuits and the non-ideal power source voltages need to be solved as one system.
State-of-the-art technologies that attempt to partition large circuits with non-ideal power supplies have two major drawbacks. First, these technologies frequently need input from engineers to designate the “cut points” (nodes at which to partition). Second, these technologies require a synchronous evaluation of all the resulting sub-partitions (also called blocks herein). That is, all blocks whether synchronous or asynchronous (i.e. event-driven) must be evaluated in synchronous steps. For example, when one block is running fast, all blocks must be evaluated at small steps (to ensure accurate simulation of the block that runs fast), thereby resulting in a dramatic slowing of simulation time. Thus, even though such partitioning can enable the simulation of huge circuits having non-ideal power supplies without running out of memory, the synchronous simulation requirement prevents taking advantage of latency and hinders fast simulation. Moreover, accuracy can degrade if the netlist is over simplified and the effects of critical circuit components are ignored. Yet further, improper cuts can cause the simulation to run slowly, inaccurately, or both slowly and inaccurately.
Therefore, a need arises for a fast and accurate technique that can automatically partition a VLSI circuit including a non-ideal voltage supply, thereby allowing the resulting blocks to be asynchronously simulated.
USPTO Backgrounds
USPTO Backgrounds