Embodiments of the present invention relate to methods of forming low dielectric constant materials, such as air gaps, between adjacent raised features on substrates.
Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment is routinely used to produce devices having geometries as small as 28 nm and less, and new equipment designs are continually being developed and implemented to produce devices with even smaller geometries. As device geometries decrease, the impact of interconnect capacitance on device performance increases. To reduce interconnect capacitance, inter-layer materials that have traditionally been formed of silicon oxide are being formed using lower dielectric constant materials (low k materials). Some low k materials that have been used include fluorinated silicon oxide, carbonated silicon oxide, and various polymers and aerogels. Use of these low k materials often presents serious reliability, manufacturability, and/or integration challenges.
One of the challenges is filling spaces between adjacent raised features (e.g., trenches and/or metal lines) with the low k materials. This is becoming more difficult as device geometries decrease and aspect ratios increase. The low k materials often pinch off at a top before the spaces completely fill leaving voids. In smaller spaces, the low k materials may completely pinch off at the top sealing the voids. In larger spaces, the low k material may not completely pinch off at the top thus leaving openings into the voids. Because semiconductor devices include both smaller and larger spaces, shapes of the voids are difficult to control. This leads to additional reliability and/or integration challenges.
Thus, there is a need for low k materials that can fill spaces between adjacent raised features without leaving voids of different shapes.
USPTO Backgrounds
USPTO Backgrounds