1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more specifically, to a semiconductor memory device capable of fundamentally preventing an increase of a bit line precharge voltage (VBLP) that is inevitably generated when there are a large amount of charges charged into local I/O lines LIO, LIOb by a column reset voltage (VCORE).
2. Discussion of Related Art
Generally, FIG. 1 illustrates a bank configuration schematically shown to explain the structure of a DRAM memory device to which a common shared sense amplifier mode is applied.
As shown in FIG. 1, the common DRAM memory device consists of a number of banks. Each bank includes a number of bit line sense amplifier arrays BLSA0 to BLSAn, and matrix cell arrays MAT0 to MATn that are alternately positioned with the bit line sense amplifier arrays BLSA0 to BLSAn. The matrix cell arrays MAT0 to MATn are selected by a word line WL activated by a X-decoder 10 according to an address signal.
As shown in FIGS. 2 and 3, data selected by a column signal (Yi) outputted from a Y-decoder (not shown) are inputted to an I/O sense amplifier IOSA through a local I/O line LIO and a local I/O line bar LIOb, and a sense amplifier I/O line SIO and a sense amplifier I/O line bar SIOb. In order to increase the transfer speed of data, lots of the column signals are operated at a time depending on its use. FIG. 2 is a circuit diagram in which four data each sensed through the four-bit line sense amplifier BLSA are simultaneously transmitted to the sense amplifier I/O lines SIO, SIOb by a single column signal by way of example. Further, the I/O sense amplifier IOSA can be made to operate at a time (IOSA<0:n>) depending on its use.
For example, as shown in FIG. 2, four local I/O lines LIO(b)0 to LIO(b)3 correspond to the four sense amplifier I/O lines SIO(b)0 to SIO(b)3 one to one. Every two line sense amplifiers BLSA are positioned at upper and lower sides on the basis of each of the matrix cell arrays MAT0 to MATn. The bit lines BL, BLb connected to the bit line sense amplifier BLSA are electrically one-to-one connected to the sense amplifier I/O lines SIO, SIOb through transistors Q1 and Q2 controlled by the column signal (Y1). Further, the sense amplifier I/O lines SIO, SIOb are electrically one-to-one connected to the local I/O lines LIO, LIOb through transistors Q6 and Q7 controlled by a row matrix signal (Row_mat).
In the concrete, as shown in FIG. 3, connection between the sense amplifier I/O lines SIO, SIOb and the bit lines BL, BLb is controlled by the column signal (Yi). Connection between the sense amplifier I/O lines SIO, SIOb and the local I/O lines LIO, LIOb is controlled by the row matrix signal (Row_mat). The row matrix signal (Row_mat) is a coding signal of the matrix cell arrays MAT0 to MATn in an active operation ACT, which controls electrical connection between the sense amplifier I/O lines SIO, SIOb and the local I/O lines LIO, LIOb. On the contrary, the row matrix bar signal (Row_matb) makes the sense amplifier I/O lines SIO, SIOb equalized to have the same voltage level, while precharging them with the bit line precharge voltage (VBLP) level. The column reset bar signal (Col_RSTb) makes the local I/O lines LIO, LIOb equalized to have the same voltage level before the column signal (Yi) is activated, while precharging them with the column reset voltage (VCORE) level. In general, the column-reset voltage (VCORE) has an ideal value that is twice of the bit line precharge voltage (VBLP). If the bit line precharge voltage (VBLP) is higher or lower than a reference value, a fail may take place in a read operation after a reference refresh in sensing High or Low data. In other words, it may have a bad influence on the refresh characteristic.
Generally, the bit line precharge voltage (VBLP) is generated from the bit line precharge voltage generator 20. As shown in FIG. 5, the bit line precharge voltage (VBLP) is commonly supplied to the bit line sense amplifier BLSA and the sense amplifier I/O lines SIO, SIOb within a neighboring bank (for example, BANK0 and BANK1 shown). Accordingly, a supply line 22 for supplying the bit line precharge voltage (VBLP) of the bit line precharge voltage generator 20 is connected to an equalization circuit 12 in a mesh form within each of the banks BANK0 and BANK1. Though not shown in the drawing, the supply line 22 is connected to an equalization circuit for equalizing the bit lines BL, BLb.
As shown in FIG. 4, before the row matrix signal (Row_mat) shifts from a Low level to a High level after the active operation ACT command is issued, the potential of the sense amplifier I/O lines SIO, SIOb are precharged with the bit line precharge voltage (VBLP) by means of transistors Q3 to Q5 operated by the row matrix bar signal (Row_matb). Also the potential of the local I/O line LIO maintains the column-reset voltage (VCORE) since the column reset bar signal (Col_RSTb) is kept High in level and the transistors Q8 to Q10 of the equalization circuit 14 are driven accordingly.
Thereafter, if the row matrix signal (Row_mat) shifts from the Low level to the High level and the row matrix bar signal (Row_matb) shifts from the High level to the Low level, the sense amplifier I/O lines SIO, SIOb are slowly charged with the column reset voltage (VCORE) by means of the potential of the local I/O lines LIO, LIOb that maintains the column reset voltage (VCORE). In other words, the local I/O line LIO charged with the column reset voltage (VCORE) and the sense amplifier I/O lines SIO, SIOb charged with the bit line precharge voltage (VBLP) are electrically connected through the transistors Q6 and Q7 operated by the row matrix signal (Row_mat). Accordingly, the column-reset voltage (VCORE) that is a relatively high voltage is introduced into the bit line precharge voltage (VBLP) through the transistors Q6 and Q7. Thereby the bit line precharge voltage (VBLP) charged into the sense amplifier I/O lines SIO, SIOb becomes ‘VBLP>VCP’ by means of the column reset voltage (VCORE), as shown in FIG. 6. In the above, ‘VCP’ is a cell plate voltage, which is a half of the column reset voltage (VCORE).
Next, in a stand-by PCG operating command, the row matrix signal (Row_mat) becomes a Low level and the row matrix bar signal (Row_matb) becomes a High level. For this reason, the potentials of the sense amplifier I/O lines SIO, SIOb that are charged with the column reset voltage (VCORE) are both discharged with the bit line precharge voltage (VBLP). In other words, the local I/O line LIO and the sense amplifier I/O lines SIO, SIOb are electrically isolated by the row matrix signal (Row_mat) and the column reset voltage (VCORE) is no longer introduced into the sense amplifier I/O lines SIO, SIOb accordingly. Thereby the sense amplifier I/O lines SIO, SIOb are discharged with the bit line precharge voltage (VBLP).
In the above, how far is the amount of the column reset voltage (VCORE) introduced into the sense amplifier I/O lines SIO, SIOb from the local I/O lines LIO, LIOb problematic to the device operation, depends on whether the word line WL will be activated several times at a time. This phenomenon may frequently take place depending on the capacity of the memory or the amount of the bank works that are consecutively performed. In other words, upon the active operation ACT, the column-reset voltage (VCORE) is backward introduced into the output terminal of the bit line precharge voltage generator 20 through the sense amplifier I/O lines SIO, SIOb. Accordingly, the bit line precharge voltage (VBLP) outputted to the bit line precharge voltage generator 20 becomes increased. As a result, as shown in FIG. 4, the bit line precharge voltage (VBLP) that is applied in order to make the bit lines BL, BLb equalized is also increased due to the increase of the bit line precharge voltage (VBLP). Therefore, it hinders the sensing operation of the bit line sense amplifier BLSA. In other words, when the refresh operation is performed or the operation of the several banks is performed, degradation of a cell data caused by the increased bit line precharge voltage (VBLP) affects a value read after a refresh interval.
As described above, in order to preclude the introduction of the column reset voltage (VCORE), a method for discharging as much as an increased voltage level, i.e., an introduced column reset voltage (VCORE) using a sensor (not shown) is positioned at the output terminal of a bit line precharge voltage generator 20 (see FIG. 5) for generating the bit line precharge voltage (VBLP), may be considered. This method, however, may not be sufficient when the loading of the sense amplifier I/O lines SIO, SIOb is high. Therefore, there is a need for a new method for precluding the column reset voltage (VCORE) from being introduced into the bit line precharge voltage (VBLP).
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