1. Field of the Invention
The invention relates in general to a method for forming a capacitor, and more particularly to a method for forming a capacitor of a mixed-mode device.
2. Description of the Related Art
Recently, applications for semiconductor devices have become wider and wider. For example, computers, communication produces, and consumer electronics produces comprise semiconductor devices, which have different functions. Semiconductor devices fabricated for different requirements are called application specific integrated circuits (ASIC).
Furthermore, with the progress in semiconductor process technologies, necessary capital expenditure is rapidly decreasing. Applications in electronic devices have been developed toward variety so that devices with a single function such as logic devices no longer satisfy requirements. Therefore, semiconductor processes are gradually developed toward integrating a logical device and a memory device on the same wafer, which structure is called a system on chip (SOC). A mixed-mode device comprising a capacitor and a complementary metal oxide semiconductor (CMOS) is one kind of ASIC.
FIG. 1 is a diagram showing a conventional capacitor structure of a mixed-mode device. Referring to FIG. 1, the conventional capacitor structure comprises a N-type conductive region 102 formed in a substrate 100, a polysilicon layer 104 and a gate oxide layer 106. N-type conductive region 102 is formed by doping N-type impurities into substrate 100, polysilicon layer 104, which is doped with an N-type dopant, serves as electrodes, and gate oxide layer 106 serves as a dielectric film. Conductive regions 102a are formed at two sides of the conductive region 102 in the substrate 100. The conductive regions 102a are used to electrically connect to an external power source. The doped polysilicon layer 104 is simultaneously formed while forming a gate on the gate oxide layer 106.
The conventional capacitor is a planar capacitor. The amount of charge stored in the conventional capacitor does not satisfy the high-capacitance requirement.
USPTO Backgrounds
USPTO Backgrounds