(a) Fields of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same. In particular, the present invention relates to semiconductor devices having contact portions of conductor (referred hereinafter to as conductor contact portions) on an interconnect layer and methods for fabricating such a device.
(b) Description of Related Art
In recent years, miniaturization and high degree of integration of semiconductor integrated circuits have been rapidly proceeding. In accordance with the proceeding miniaturization of the circuit, delay time caused by transistor operation can be cut in the device while interconnect resistance and parasitic capacitance increase therein. This makes it difficult to cut delay time caused in an interconnect. In a measure to cut the interconnect delay time, in order to reduce the interconnect resistance, copper having a lower resistivity than aluminum used as a conventional interconnect material is employed as a substitute for aluminum. Moreover, in order to reduce the parasitic capacitance, an insulating film having a low dielectric constant is employed as a material for an interlayer insulating film and the like.
Copper is difficult to etch. Therefore, formation of an interconnect with copper is made by a damascene process: a hole pattern and a trench configuration are formed in an insulating film, after which the patterns are filled with copper.
In a chip of a semiconductor device, a trench configuration called a seal ring is formed to protect transistors and interconnects provided in the chip against outside moisture. The seal ring is formed to surround an area containing the transistors and the interconnects. The seal ring is formed simultaneously with the etching for forming a hole pattern (vias).
The hole pattern and the trench configuration serving as the seal ring are formed in the following manner.
First, to form the hole pattern and the trench configuration, an interlayer insulating film is halfway removed using photoresist as a mask. The reason why the removal is stopped halfway is that if an interconnect layer located below the hole pattern and the trench configuration is exposed therefrom during the removal, the interconnect layer corrodes during subsequent ashing for removing the photoresist and subsequent polymer removal. To avoid such a problem, ashing and polymer removal are performed with only part of the thickness of the interlayer insulating film remaining. Thereafter, using the resulting interlayer insulating film itself as a mask, the hole pattern and the trench configuration are made to reach the interconnect layer.
However, the conventional semiconductor device has caused the following problems.
Generally, during etching, the etching rate rises as the area of an opening increases. In this device, the opening area of the trench is greater than that of the hole. Thus, when the trench and the hole are formed at the same time by a single etching, the trench is formed deeper. Therefore, it might be unable to stop etching of the trench halfway through the interlayer insulating film, resulting in exposure of metal of the interconnect layer located therebelow. If the metal is exposed in this process, then the disadvantage arises that the metal corrodes by subjecting itself to subsequent photoresist removal by ashing and to subsequent polymer removal.
Such a disadvantage also arises when the interlayer insulating film is formed with multiple types of hole patterns. Specifically, the hole patterns have different pattern densities or the like, so that it is impossible, in forming the different hole patterns, to partly remove the insulating film to form the hole patterns with a uniform depth. This causes the disadvantage that the interconnect layer located below the hole patterns is exposed.
USPTO Backgrounds
USPTO Backgrounds