1. Technical Field
Embodiments relate to a semiconductor apparatus, and more particularly to a sense amplifier of the semiconductor apparatus.
2. Related Art
Semiconductor apparatuses particularly memory devices include memory cells and data input/output (I/O) lines to perform the data I/O operations. The types of data I/O lines for data input/output include bit lines, local I/O lines, global I/O lines, etc. In a circuit layout, the data I/O line paths for data input/output tend to be very long, and the loads between the electrically connected data I/O lines are different from each other. To prevent the problems that may be caused by the above and in order to ensure reliable and consistent data transfer, the semiconductor memory apparatuses utilize sense amplifiers for amplifying the data signal strength.
FIG. 1 shows a conventional semiconductor memory apparatus. When data is to be outputted, the data stored in a memory cell (not shown) is loaded on the bit lines BL, BLB and amplified by the bit line sense amplifier BLSA. Then, the data on the bit lines BL, BLB is transferred to the segment I/O lines SIO, SIOB by a column selection signal CSL. The data transferred to the segment I/O lines SIO, SIOB is amplified by a local sense amplifier LSA 10 and transferred to local the I/O lines LIO, LIOB. The data transferred to the local I/O lines LIO, LIOB can then be transferred to a global I/O line (not shown), and the data on the global I/O line are transferable via a data pad (not shown) to an external device. When data is to be inputted, the data input path is in the reverse order of the data output path described above.
FIG. 2 shows the local sense amplifier LSA 10 of FIG. 1. The local sense amplifier 10 includes first to seventh transistors N1-N7. The first and second transistors N1, N2 couple the segment I/O lines SIO, SIOB and the local I/O lines LIO, LIOB to each other respectively in response to an internal write signal WE. The third and fourth transistors N3, N4 are coupled to the local I/O lines LIOB, LIO, respectively, in response to an internal read signal RD, and the fifth and sixth transistors N5, N6 are coupled to the segment I/O lines SIO and SIOB, respectively, and the seventh transistor N7 is turned on in response to the internal read signal RD and then enables a current to flow to a ground voltage terminal VSS. The internal read signal RD can be referred to as a sense amplifier enable signal LSAEN since the internal read signal RD enables the local sense amplifier 10 to differentially amplify the segment I/O lines SIO, SIOB. The conventional local sense amplifier 10 of FIG. 2 can discriminate read vs. write operations and perform the respective read/write operations. In particular, in a write operation, the local sense amplifier 10 allows the appropriate data transfer by coupling the local I/O lines LIO, LIOB to the respective segment I/O lines SIO, SIOB; and, in a read operation, the conventional local sense amplifier differentially amplifies data on the segment I/O lines SIO, SIOB to transfer the respective amplified data to the local I/O lines LIO, LIOB. That is, the conventional local sense amplifier 10 of FIGS. 1-2 can couple the segment I/O lines SIO, SIOB to the respective local I/O lines LIO, LIOB only when the internal write signal WE or the internal read signal RD is applied.
USPTO Backgrounds
USPTO Backgrounds