1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
A single transistor DRAM (Dynamic Random Access Memory) using an FBC (Floating Body Cell) has so far been known as a node for storing data. In such single transistor DRAM, the FBC is formed on an SOI (Silicon On Insulator) wafer having a thin semiconductor layer formed on a support substrate with an insulating layer called a BOX (Buried Oxidation) layer formed therebetween.
The single transistor DRAM, when the transistor is of an N-channel type, stores data by utilizing the variation of the threshold value of the transistor depending on the number of holes confined and accumulated in the body of the transistor surrounded by a source region and a drain region and electrically floated.
Writing data is performed by selecting the gate voltage to operate the transistor in such a way that hole-electron pairs are formed in larger number than the holes removed.
Erasing data is performed by selecting the gate voltage to operate the transistor in such a way that holes are removed at a higher rate than that at which hole-electron pairs are formed.
However, a single transistor DRAM using FBC as a node for storing data receives a smaller amount of signals as compared to a DRAM using a capacitor as a node for storing data. Therefore, the single transistor DRAM using FBC has a problem of having a low signal margin, resulting in a low writing speed.
In this regard, a single transistor DRAM having improved reading and writing speeds has been known (refer to, for example, the specification of U.S. Pat. No. 6,861,689).
The single transistor DRAM disclosed in the specification of U.S. Pat. No. 6,861,689 includes, between the drain region and the body, a region, which aids in impact ionization and thus electron/hole pair formation during writing, that is the same conductivity type as the body but of a higher concentration than the body.
The single transistor DRAM includes, adjacent to the source region and to the body, a region, which aids in diode current during erase, that is the same conductivity type as the source region but of a lower concentration than the source region.
However, the single transistor DRAM disclosed in the specification of U.S. Pat. No. 6,861,689 has a problem of having a complicated structure and increasing the number of processes of forming a region having a concentration higher than that of the body and a region having a concentration lower than that of the source region.
As a result, there are problems of reducing the productivity and increasing the production cost of the semiconductor memory device.
USPTO Backgrounds
USPTO Backgrounds