1. Field of the Invention
The invention relates generally to the field of Built-in Self-tests. More particularly, the invention relates to a Built-in Self-test for detecting faults in a memory.
2. Discussion of the Related Art
Memory Built-in Self-tests (BIST) are typically used to deliver a sequence of tests to memory modules for fault detection. Generally, a state machine can translate a test algorithm into a sequence of commands, data, and addresses to be applied to the memory modules being tested. However, under at-speed (functional) testing conditions, a state machine BIST circuit cannot operate fast enough to deliver the complex algorithms sometimes needed to intensively test the memory module. Several programmable/configurable BIST controllers have been developed to overcome these limitations.
A BIST controller can be used to screen defects in synchronous Static Random Access Memory (SRAM) devices embedded in digital designs. Running at a functional speed (at-speed), a BIST controller can implement, for example, a March C+ algorithm. March algorithms are well known in the art of Built-in Self-tests.
A problem with current BIST technology utilizing March algorithms is that in memories with automatic write through, new data written into the memory can supersede a previous read's failing data before the BIST controller can report the failing data for bitmapping. Bitmapping capability can be an important mechanism in failure analysis and yield enhancement.
An unsatisfactory approach, in an attempt to solve the above-discussed problem, involves adjusting the BIST controller to allow dead cycles between consecutive operations. Disadvantages of this approach include causing the testing algorithm to run at speeds lower than the functional speed and increasing test time. Another approach involves adding register banks to mirror the data output port of the SRAM. However, this approach causes a significant increase of the design area.
Yet another unsatisfactory approach involves implementing a control structure to allow direct observation of memory outputs during bitmapping operation. A disadvantage of this approach includes the necessity for multiple runs of the BIST controller for each memory to produce a complete bitmap, thus increasing debug and yield enhancement times.
Until now, the requirements of providing a method and/or apparatus for at-speed memory BIST data logging, which decreases design debug and yield enhancement time and minimizes design area impact have not been met.
USPTO Backgrounds
USPTO Backgrounds