The present invention relates to FLASH, electrically erasable, programmable read only memory (EEPROM) and nitride, programmable read only memory (NROM) cells in general and to secondary injection therein in particular.
Floating gate memory cells are used for electrically erasable, programmable read only memory (EEPROM) and Flash EEPROM cells. As shown in FIG. 1 to which reference is now made, floating gate cells comprise source and drain portions 102 and 104 embedded in a substrate 105, between which is a channel 100. A floating gate 101 is located above but insulated from channel 100 and a gate 112 is located above but insulated from floating gate 101.
For most floating gate cells, the standard electron injection mechanism (for programming) is channel hot electron injection, in which the source to drain potential drop creates lateral field that accelerates channel electrons e1 from source 102 to drain 104. This is indicated by arrow 10. Near drain 104, a vertical field created by the gate voltage allows hot channel electrons e1 to be injected (arrow 12) into floating gate 101.
There is another injection mechanism, known as xe2x80x9csecondary electron injectionxe2x80x9d. As indicated by arrow 14, some of the channel electrons e1 create hole and electron pairs through ionization of valence electrons in channel 100 or drain 104. The probability of the ionization is labeled M1 and it indicates the ratio between the channel current and the hole substrate current.
Due to the positive potential of drain 104, generated electron e2 is collected (arrow 16) by drain 104. However, as indicated by arrow 18, hole h2 accelerates towards the low substrate potential of substrate 105. On the way, another impact ionization event may occur, creating another electron-hole pair e3-h3, with probability M2. Hole h3 is pulled (arrow 20) further into substrate 105 and is of no concern. However, electron e3 (known as the xe2x80x9csecondary electronxe2x80x9d) is accelerated (arrow 22) toward positive gate 112 where, if it has gained sufficient energy, it is injected into floating gate 101. The probability of this occurring is labeled T.
The current for secondary injection is defined as:
Ig=Ids*M1*M2*T
where Ids is the channel current from source to drain.
Because this current is significant, some floating gate devices have been built to enhance it, thereby reducing programming time and programming voltages. The following articles discuss some possible methods to enhance the secondary injection:
J. D. Bude, et al., xe2x80x9cSecondary Electron Flashxe2x80x94a High Performance, Low Power Flash Technology for 0.35 xcexcm and Belowxe2x80x9d, IEDM 97, pp. 279-282;
J. D. Bude, et al., xe2x80x9cEEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writingxe2x80x9d, IEDM 95, pp. 989-992; and
J. D. Bude and M. R. Pinto, xe2x80x9cModeling Nonequilibrium Hot Carrier Device Effectsxe2x80x9d, Conference of Insulator Specialists of Europe, Sweden, June 1997. These references enhance the secondary generation and injection in two ways as shown in FIGS. 2A and 2B to which reference is now made, by implanting (FIG. 2A) substrate 105 with Boron pockets 116 and by applying a negative substrate bias VB to substrate 105 (FIG. 2B).
Boron pockets 116 (FIG. 2A), when implanted with relatively high energy, enhance the field in the substrate and hence, enhance the probability M2 of secondary generation. This higher Boron concentration is effective also in accelerating secondary electrons and hence, enhances their probability T of injection.
The potential drop Vdb from drain 104 to substrate 105 is larger by 1V than the potential drop Vds from drain to source due the built-in potential in the n+/pxe2x88x92 substrate junction. This enhances both the probability M2 of a secondary impact and the probability T of injection. To further enhance secondary injection, a negative substrate bias VB can be applied, as shown in FIG. 2B.
It will be appreciated that the energy balance for secondary injection is a function of the drain voltage Vd (which defines the voltage in the channel), the built-in potential Vbi, the substrate voltage Vsub and the energy Desec after impact ionization. This compares to the primary electron injection mechanism (of channel hot electron injection) which is a function of the drain to source voltage Vds.
Typically, if the drain to source voltage Vds is of 3V and the substrate voltage is at 0V, the primary electrons are accelerated by 3V while the secondary electrons are accelerated by 4V. If the substrate voltage is decreased to xe2x88x921V, then the secondary electrons are accelerated by 5V. Thus, applying negative voltage to the substrate increases the secondary injection mechanism. This is illustrated in FIG. 2B which shows the potential energy across channel 100 (from drain 104 (at point A) to source 102 (point B) and into the substrate 105 (point C is at the electrode of substrate voltage Vb). In FIG. 2B, the drain/source voltage Vds is 3V, the gate/source voltage Vgs is 2V and the channel length is 0.25 xcexcm.
The solid line, labeled 120, indicates the potential energy in a standard situation where source/substrate voltage Vbs is 0.0V. The potential energy drops from drain 104 to source 102 and then increases into substrate 105. Thus, the total potential drop from drain (point A) to substrate (point C) is about 1 eV higher than that of the drain to source (point A to point B). A generated hole h2 will escape the drain 104 and will create a secondary electron e3 with energy of about 0.2-0.7 eV.
This energy, when combined with the acceleration of secondary electron e3 over several volts of substrate to channel potential towards gate 112, makes the probability of injection T of secondary electron e3 higher than that of primary electron e1. However, there are many more primary electrons e1 available than secondary electrons e3 and thus, most of the injection remains the primary electrons e1. Since the injected electrons (primary and secondary) spread out in floating gate 101, there is no way to tell where injection occurred.
When the source/substrate voltage Vbs is decreased to xe2x88x921.0V, shown with the dashed line 122, the potential energy into substrate 105 increases, although the potential energy in the drain and across the channel does not change. The increased substrate potential provides additional energy to secondary electrons e3 while not affecting the energy of channel electrons e1.
Secondary injection adds to the primary injection mechanism to provide a faster and/or lower voltage injection into a floating gate cell. Unfortunately, secondary injection is not good for all types of cells. There are some cells, such as nitride, programmable read only memory (NROM) cells, for which enhancing secondary injection appears not to enhance the operation of the cell.
NROM cells are described in Applicant""s copending U.S. patent application Ser. No. 08/905,286, entitled xe2x80x9cTwo Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trappingxe2x80x9d which was filed Aug. 1, 1997. The disclosure of the above-identified application is incorporated herein by reference.
FIGS. 3A, 3B and 3C, to which reference is now made, schematically illustrate the dual bit NROM cell. Similar to the floating gate cell of FIG. 1, the NROM cell has channel 100 between two bit lines 102 and 104 but, unlike the floating gate cell, the NROM cell has two separated and separately chargeable areas 106 and 108. Each area defines one bit. For the dual bit cell of FIGS. 3, the separately chargeable areas 106 and 108 are found within a nitride layer 110 formed in an oxide-nitride-oxide (ONO) sandwich (layers 109, 110 and 111) underneath gate 112.
To read the left bit, stored in area 106, right bit line 104 is the drain and left bit line 102 is the source. This is known as the xe2x80x9cread throughxe2x80x9d direction, indicated by arrow 113. To read the right bit, stored in area 108, the cell is read in the opposite direction (a xe2x80x9creverse readxe2x80x9d), indicated by arrow 114. Thus, left bit line 102 is the drain and right bit line 104 is the source.
FIG. 3B generally indicates what occurs within the cell during reading of the left bit of area 106. An analogous operation occurs, when reading the right bit of area 108.
To read the left bit in area 106, the left bit line 102 receives the source voltage level Vs, typically on the order of 0V, and the right bit line 104 receives the drain voltage Vd, typically of 1-2V. The gate 112 receives a relatively low voltage Vg, which typically is a low voltage of 2.5-3V.
The presence of the gate and drain voltages Vg and Vd, respectively, induce a depletion layer 54 and an inversion layer 52 in the center of channel 100. The drain voltage Vd is large enough to induce a depletion region 55 near drain 104 which extends to the depletion layer 54 of channel 100. This is known as xe2x80x9cbarrier loweringxe2x80x9d and it causes xe2x80x9cpunch-throughxe2x80x9d of electrons from the inversion layer 52 to the drain 104. The punch-through current is only minimally controlled by the presence of charge in right area 108 and thus, the left bit can be read irrespective of the presence or absence of charge in right area 108.
Since area 106 is near left bit line 102 which, for this case, acts as the source (i.e. low voltage level), the charge state of area 106 will determine whether or not the inversion layer 52 is extended to the source 102. If electrons are trapped in left area 106, then the voltage thereacross will not be sufficient to extend inversion layer 52 to the source 102 and a xe2x80x9c0xe2x80x9d will be read. The opposite is true if area 106 has no charge.
For NROM cells, each bit is programmed in the direction opposite that of its reading direction. Thus, to program left bit in area 106, left bit line 102 receives the high programming voltage (i.e. is the drain) and right bit line 104 is grounded (i.e. is the source). This is shown in FIG. 3C. The opposite is true for programming area 108.
The bits are erased in the same directions that they are programmed. However, for erasure, a negative erasure voltage is provided to the gate 112 and a positive voltage is provided to the bit line which is to be the drain. Thus, to erase the charge in left area 106, the erase voltage is provided to left bit line 102. The highly negative erase voltage creates holes in the n+ junction (near left bit line 102) through band-to-band tunneling. These holes are accelerated by the lateral field near the drain (left bit line 102) and the ONO surface. Some holes gain enough energy to be injected through the bottom oxide 109 in a process known as xe2x80x9ctunnel assisted hot hole injectionxe2x80x9d.
Typically, programming and erasure are performed with pulses of voltage on the drain and on the gate. After each pulse, a verify operation occurs in which the threshold voltage level of the cell (i.e. the gate voltage level at which the cell becomes significantly conductive) is measured. During programming, the threshold voltage level Vtp is steadily increased until the cell will not pass any significant current during a read operation. During erasure, the opposite is true; the threshold voltage level Vte is decreased until a significant current is present in the cell during reading. Should the cell not meet the erase specification (typically defined by a maximum number of pulses to achieve erasure), it is no longer considered functional.
The enhancements for secondary injection are indirectly implemented in the NROM cell as well. In some arrays, the NROM cell has an inherent back bias, due to voltage drops in the array. This results in a positive source voltage Vs, which requires a higher drain voltage Vd to meet the required drain-to-source voltage Vds, for a desired programming speed. As discussed hereinabove with respect to FIG. 2, the increased drain voltage Vd enhances the secondary injection since the drain to bulk potential is increased accordingly. And, since the source voltage Vd is more positive than desired, the drain-to-source voltage Vds is lower than desired which, in turn, reduces the drive for the primary injection mechanism. Unfortunately, as indicated in FIGS. 4A and 4B to which reference is now made, the secondary injection effect degrades the operation of the NROM cell.
FIGS. 4A and 4B illustrate the results of an experiment where one of the bits was programmed and then erased, once with substrate 105 at 0V and once with substrate 105 at xe2x88x922V. The remaining voltages stayed the same. If programming occurred properly, then the programmed bit should change threshold voltage during programming, while the unprogrammed bit should not change at all. If programming occurred properly, then during erasure, the threshold voltage of the programmed bit should quickly return to the unprogrammed level.
In FIG. 4A, the threshold voltage is graphed against the programming time. Programming ends when the threshold level of the bit being programmed has increased by 2.0V.
Curves 134 and 136 show the results for programming with the standard source/substrate voltage Vsb of 0.0V, for the bit being programmed and the unprogrammed bit, respectively. As can be seen in curve 134, the threshold level of the bit being programmed increases steadily until, at 100 xcexcsec, the bit reaches the programmed level. At the same time, the voltage level of the unprogrammed bit increases to slightly above 0.2V (curve 136).
Curves 138 and 140 show the results for programming with the negative source/substrate voltage Vsb of xe2x88x922V, for the bit being programmed and the unprogrammed bit, respectively. In curve 138, the threshold level of the bit being programmed increases faster and becomes programmed by 10 xcexcsec. At the same time, the voltage level of the unprogrammed bit (curve 140) grows to 0.5V. This threshold level reduces the operating window for two bits. In other words, the punchthrough read of one bit is affected by the information in the other bit.
In FIG. 4B, the threshold voltage is graphed against the erase time. Curves 144 and 146 show the results for erasure of the bit programmed with the standard source/substrate voltage Vsb of 0.0V, for the programmed and unprogrammed bits, respectively. The threshold level of the programmed bit drops sharply (curve 144) until, at 1.0 sec, the bit is unprogrammed. At the same time, the voltage level of the unprogrammed bit drops back to 0.0V (curve 146).
Curves 148 and 150 show the results for erasure of the bit programmed with the negative source/substrate voltage Vsb of xe2x88x922V, for the programmed and unprogrammed bits, respectively. The unprogrammed bit is further erased, back to almost 0.0V However, the programmed bit erases slowly and still has a significant threshold voltage level even after 1.0 sec of erasure.
Thus, using a negative substrate voltage VB, whether to solve a back bias or to enhance secondary injection for NROM cells, does not improve their performance. To the contrary, it greatly degrades their performance. Similarly, adding a pocket implant improves their primary performance but may adversely affect their endurance by enhancing the secondary injection.
U.S. Ser. Nos. 09/082,280 and 09/413,408, assigned to the common assignees of the present invention and incorporated herein by reference, describe using pocket implants, such as enhance primary injection, in an NROM cell to shape the lateral field such that charge is injected in an area from which it can be erased. This dramatically improves the operation of the cell with respect to the primary injection.
Applicant has realized that the secondary injection reduces the performance of NROM cells. Furthermore, as will be described in more detail hereinbelow, Applicant has realized that the cause is the secondary electrons s that are injected far from the bit line junctions. These secondary electrons are not removable during erasure and thus, reduce the ability of the NROM cell to separate between the two charge areas.
Therefore, the present invention seeks to decouple the primary injection mechanism from other injection mechanisms, like the secondary one, enhancing the primary mechanism while reducing the other injection mechanisms.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer . The step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons.
Additionally, in accordance with a preferred embodiment of the present invention, the step of injection minimization includes at least one of the following steps: minimizing the concentration of Boron deep in the substrate, implanting a shallow threshold voltage implant, implanting deep bit lines and making the channel to be shorter than a standard length.
Furthermore, in accordance with a preferred embodiment of the present invention, the NROM cell has at least one Boron pocket implants and the step of Boron concentration reduction includes the step of implanting Arsenic or Phosphorous pocket implants deeper than the Boron pocket implants.
Still further, in accordance with a preferred embodiment of the present invention, the threshold voltage implant step includes the step of implanting two threshold voltage implants, a first surface implant of Boron and a second deeper implant of Arsenic or Phosphorous. Additionally, Boron pockets can be implanted.
Additionally, in accordance with a preferred embodiment of the present invention, the step of generation minimization includes at least one of the following steps: minimizing the concentration of Boron deep in the substrate, implanting a shallow threshold voltage implant and making the channel to be shorter than a standard length.
Alternatively, in accordance with a preferred embodiment of the present invention, the NROM cell can include a shallow threshold voltage implant at least of Boron into the channel. The concentration of the Boron is reduced by a factor of 2 at least a distance of 10-20, 20-30, 30-40 and 50-100 nm from a surface of the channel.
Moreover, in accordance with a preferred embodiment of the present invention, the shallow threshold implant has a first implant of Boron and a counterdoping implant of one of Arsenic and Phosphorous, wherein the counterdoping implant is deeper in the channel than the first implant.
Further in accordance with a preferred embodiment of the present invention, the cell also includes a pocket implant near at least one of the bit lines.
In accordance with a further preferred embodiment of the present invention, the NROM cell can include a double pocket implant near at least one of the bit lines wherein the double pocket implant is formed of two pocket implants, a p+ implant near a surface of the substrate and an nxe2x88x92 implant below the p+ implant.
In accordance with a still further preferred embodiment of the present invention, the NROM cell can include a substrate having two bit lines and a channel therebetween, wherein the channel is no longer than 0.2 xcexcm, and an ONO layer at least above the channel.
Further, in accordance with a preferred embodiment of the present invention, the channel is no longer than 0.15 xcexcm. Alternatively, it is no longer than 0.1 xcexcm.
Moreover, in accordance with a preferred embodiment of the present invention, the NROM cell can include a substrate having two bit lines and a channel therebetween, wherein the bit lines have a depth of no less than 0.3 xcexcm into the substrate, and an ONO layer at least above the channel.
There is also provided, in accordance with a preferred embodiment of the present invention, a method of creating nitride, programmable read only memory cell, the method comprising the steps of having a high ratio of surface injection to deep injection of electrons into a charge trapping layer of the NROM cell.
Moreover, in accordance with a preferred embodiment of the present invention, the NROM cell has at least Boron pocket implants and the method includes at least one of the following steps: implanting a shallow threshold voltage implant, implanting pocket implants of one of Arsenic and Phosphorous deeper than the Boron pocket implants or implanting two threshold voltage implants, a first surface implant of Boron and a second deeper implant of one of Arsenic and Phosphorous.
There is further provided, in accordance with a preferred embodiment of the present invention, a method of creating a nitride, programmable read only memory (NROM) cell, comprising the steps of generating a zero substrate potential at a distance no less than 45-55 nm into said substrate.
Additionally, in accordance with a preferred embodiment of the present invention, the step of generating includes the steps of minimizing the concentration of Boron deep in the substrate by implanting pocket implants of one of Arsenic and Phosphorous deeper than said Boron pocket implants, implanting two threshold voltage implants, a first surface implant of Boron and a second deeper implant of one of Arsenic and Phosphorous or implanting a shallow threshold voltage implant with or without Boron pockets.
Moreover, in accordance with a preferred embodiment of the present invention, the NROM cell has a channel and the step of generation includes the step of making the channel to be shorter than a standard length.
Finally, there is provided, in accordance with a preferred embodiment of the present invention, a method of operating a nitride, programmable read only memory (NROM) cell to have minimum injection from non-channel electrons. The cell has bit lines serving as source and drain to the cell and the method includes the step of providing the lowest source voltage Vs which provides a desired drain to source voltage Vds to the well.
USPTO Backgrounds
USPTO Backgrounds