High-speed data received at a data rate FDATA are sampled in serial link receivers by a set of samplers and these samples are then generally sent to a digital section that interprets these samples as being a ‘data’ sample (D) and then an ‘edge’ sample (E). For example, if the data rate FDATA matches the sampling clock frequency FSCLK, two samples per data unit interval (UI) can be acquired by taking one sample at the rising edge of FSCLK and another sample at the falling edge of FSCLK (or, alternatively, on the rising edge of FSCLK). These D and E samples can be used by a delay-locked loop (DLL) to select the appropriate sampling phase and to track jitter that randomly shifts the input data. The setup with FSCLK=FDATA is referred to as “full-rate” mode, since the sampling clock (using the edges of both FSCLK and FSCLK) is matched ‘in full’ to the data rate.
As the input data rate increases, “full rate” mode operation becomes more difficult due to the difficulty in designing a sampler block that can operate at these higher frequencies. This situation may be alleviated, for example, by doubling the number of samplers and having each sampler work at half the data rate FDATA. This is referred to as “half-rate” mode. If the data rate FDATA is still too high for the samplers and the speed of a given sampler cannot feasibly be increased further, then the number of samplers may again be doubled, so that each sampler would run at an even lower sampling clock frequency FSCLK, e.g. in “quarter-rate”mode. However, it then becomes more and more difficult to ensure that the sampling paths, starting from some single high-speed distribution point, can generate, buffer and distribute these sampling clocks while maintaining the initial phase relationships.
It would therefore be desirable to provide a method to efficiently align the sampling clocks of multiple independent samplers in order to extend the effective data rate that can be processed by each sampler, without changing the sampling rate at which each sampler can reliably operate.
USPTO Backgrounds
USPTO Backgrounds