1. Field of the Invention
The present invention relates to a fully-differential amplifier circuit.
2. Description of the Related Art
A wideband fully-differential amplifier with a two-stage amplification configuration is applied to a switched capacitor circuit such as an S/H. When this amplifier includes a class A amplifier with a high cutoff frequency in the first stage, and a common-source class AB amplifier in the second stage, it is possible to obviate the need for phase compensation and to reduce power consumption.
Moreover, when a dynamic bias circuit which performs not a continuous time operation but a clock operation is adopted as a bias circuit in the common-source class AB amplifier in the second stage, it is possible to simplify the overall circuit and to further reduce power consumption (see “A 14b 74 MS/s CMOS AFE for True High-Definition Camcorders” (2006 ISSCC)).
A fully-differential amplifier requires that the output common mode potential is set to a desired reference signal such as a signal common mode voltage (to be referred to as Vcm hereinafter). This function is realized by a common mode feedback circuit (to be referred to as a CMFB circuit hereinafter), which detects the common mode components of all output signals and provides feedback signals to the fully-differential amplifier in accordance with the differences between the detection results and Vcm.
FIG. 1 in Japanese Patent Laid-Open No. 6-29761 describes a differential amplifier 20 in which a common mode feedback circuit 50 detects the common mode components of a plurality of signals output from a differential portion 30, and feeds back feedback signals proportional to the detected differences to the differential portion 30. According to Japanese Patent Laid-Open No. 6-29761, this makes it possible to prevent a common mode voltage from drifting from a predetermined reference voltage.
In the differential amplifier described in Japanese Patent Laid-Open No. 6-29761, the common mode feedback circuit 50 feeds back feedback signals to the differential portion 30. For this reason, an additional inverting amplifier 54 is required to invert the feedback signals, which may increase power consumption. Also, three phase delay factors (three pairs of capacitance elements and resistance elements) are present in the path of the common mode feedback circuit 50. For this reason, a design burden to satisfy a given stability of a feedback operation may increase and power consumption may increase. Furthermore, an autozeroing technique is necessary to eliminate any flicker noise of the amplifier in the first stage, and this inevitably increases power consumption to meet a given stability.
USPTO Backgrounds
USPTO Backgrounds