1. Field of the Invention
This invention relates to an address determination circuit for making an address determination of an optical packet to which a destination address and a source address thereof are assigned on a bit-by-bit basis, and an optical communication system for transmitting the optical packet. The invention more particularly relates to an address determination circuit and an optical communication system capable of performing address processing of an optical packet at high speed while suppressing an increase in the circuit scale.
2. Description of the Related Art
In recent years, an optical communication system of conducting data communications using an optical signal has become widespread. In such an optical communication system, packet communications with using an optical signal are conducted as with data communications using an electric signal. The packet communications are communications of transmitting and receiving data divided into small pieces called packets, and it becomes very important to perform routing control of the packets.
FIG. 11 is a drawing to show the configuration of an optical communication system in a related art. (For example, refer to JP-A-2003-69495 and JP-A-2004-120696.) In FIG. 11, an optical packet 1 is transmitted over an optical transmission line 100 (for example, an optical waveguide of an optical fiber, etc.,) and is input to a repeater 10(1). The repeater 10(1) references the destination address and the source address contained in the header part of the optical packet 1, and selects a route for transmitting the optical packet 1. For example, the repeater 10(1) selects an optical transmission line 101 and outputs the optical packet 1 to a repeater 10(2) at the following stage or selects an optical transmission line 102 and outputs the optical packet 1 to a repeater 10(3) at the following stage. FIG. 11 illustrates an example wherein an optical packet 2 is transmitted to the repeater 10(3) over the optical transmission line 102. The repeaters 10(1) to 10(3) for performing destination control of the optical packets 1 and 2, namely, performing route switching are also called network switches.
Subsequently, the repeaters 10(1) to 10(3) will be discussed. FIG. 12 is a drawing to show the configuration of the repeater in the related art. (For example, refer to JP-A-2004-120696.) The repeater 10(1) in FIG. 11 to which the optical transmission lines 100 to 102 are connected will be discussed by way of example. In FIG. 12, a plurality of optical ports 11 are provided and the optical transmission lines 100 to 102 are connected thereto. A packet processing section 12 is interconnected to the optical ports 11. A storage area (for example, RAM) 13 is interconnected to the packet processing section 12.
The operation of the repeater 10(1) shown in FIG. 12 is as follows: The optical packet 1 is input from the optical transmission line 100 to the optical port 11. The optical port 11 converts the received optical packet 1 of an optical signal into a packet of an electric signal and outputs the packet of an electric signal to the packet processing section 12. The packet processing section 12 determines the optical port 11 to which the packet is to be transferred based on the destination address (and the source address as required) contained in the header part of the packet converted into the electric signal. The packet processing section 12 may once store the packet in the storage area 13 and then again read the packet and select the optical port 11 or may transfer the packet directly to the optical port 11 without storing the packet in the storage area 13. For example, the optical port 11 to which the optical transmission line 102 is connected is selected and the packet of the electric signal is output to the optical port 11. Further, the optical port 11 converts the packet of the electric signal into the optical packet 1 of an optical signal and outputs the optical packet 1 to the optical transmission line 102. Thus, the optical packets 1 and 2 are transferred to the optical transmission lines 100 to 102 selected by the repeater 10(1).
JP-A-2003-69495 and JP-A-2004-120696 (paragraph numbers 0008 to 0016, FIG. 8) are referred to as related art.
The transfer capability of the repeater 10(1), 10(2), 10(3) depends largely on the time taken for reading the destination address, etc., in the optical packet 1, 2 and determining the optical port 11 to which the packet is to be transferred, namely, the route selection of the optical transmission line 101, 102 from the destination address, etc.; particularly the processing speed of address processing of making address determination of the destination address and the source address is very important.
However, in the repeater 10(1), 10(2), 10(3) in the related art, since the packet processing section 12 and the storage area 13 perform packet processing by electric processing, it is indispensable to convert an optical signal into an electric signal and convert an electric signal into an optical signal in the optical port 11.
Generally, the speed of the electric processing is substantially low as compared with the transmission speed of optical communications. A delay occurs because the optical packet 1, 2 of the optical signal is converted into an electric signal and electric processing is performed as described above. Therefore, if the optical packet 1, 2 passes through the repeaters 10(1) to 10(3), a delay occurs in each of the repeaters 10(1) to 10(3) and the time involved in relaying is prolonged, causing a large delay to occur; this is a problem.
Of course, it is also possible to increase the electric processing speed so as to be able to follow the transmission speed of optical communications, but the circuitry and devices for performing the electric processing become remarkably large-scaled and it is very difficult to put them to use.
On the other hand, an attempt is made to execute address recognition with the optical packet 1, 2 of the optical signal intact without converting the optical signal into an electric signal. (For example, refer to JP-A-2003-69495.) However, there is a bottleneck such that the circuit scale becomes large, and it is difficult to make the attempt practical.
USPTO Backgrounds
USPTO Backgrounds