The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors.
A MOS transistor includes a gate electrode as a control electrode, and a pair of spaced apart source and drain electrodes. A control voltage applied to the gate electrode controls the flow of a drive current through a channel that is established between the source and drain electrodes. When a MOS transistor is operating in its linear region (i.e., when the gate-to-source voltage (VGS) is greater than a threshold voltage (Vth) and the drain-to-source voltage (VDS) is less than the difference between the gate-to-source voltage and the threshold voltage (VGS−Vth)), the MOS transistor turns on and a channel is created which allows the drive current to flow between the drain and source. The MOS transistor operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The drive current (ID) from drain to source can be modeled in equation (1) as:
                              I          D                =                  μ          ⁢                                          ⁢                      C            ox                    ⁢                      W            L                    ⁢                      (                                                            (                                                            V                      GS                                        -                                          V                      th                                                        )                                ⁢                                  (                                      V                    DS                                    )                                            -                                                V                  DS                  2                                2                                      )                                              Equation        ⁢                                  ⁢                  (          1          )                    
where μ is the charge-carrier effective mobility, W is the gate width, L is the gate length and Cox is the gate oxide capacitance per unit area. When the MOS transistor is operating in its saturation region (i.e., when the gate-to-source voltage (VGS) is greater than a threshold voltage (Vth) and the drain-to-source voltage (VDS) is greater than the difference between the gate-to-source voltage and the threshold voltage (VGS−Vth)), the MOS transistor turns on and a channel is created which allows the drive current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, a portion of the channel is turned off. The onset of this region is also known as pinch-off. The drain current is now relatively independent of the drain voltage. The drive current (ID) from drain to source is controlled by the gate-to-source voltage (VGS) and can be modeled in equation (2) as:
                                          I            D                    =          μ                ⁣                              C            ox                    2                ⁣                              W            L                    ⁢                                                    (                                                      V                    GS                                    -                                      V                    th                                                  )                            2                        .                                              Equation        ⁢                                  ⁢                  (          2          )                    
The complexity of ICs and the number of devices incorporated in ICs are continually increasing. As the number of devices in an IC increases, the size of individual devices decreases. Device size in an IC is usually noted by the minimum feature size; that is, the minimum line width or the minimum spacing that is allowed by the circuit design rules. As the semiconductor industry moves to a minimum feature size of 45 nanometers (nm) and even smaller, the gain of performance due to scaling becomes limited. As new generations of integrated circuits and the MOS transistors that are used to implement those ICs are designed, technologists must rely heavily on non-conventional elements to boost device performance.
As noted above, the performance of a MOS transistor, as measured by its current carrying capability, is proportional to the mobility of a majority carrier in the transistor's channel. By applying an appropriate uniaxial stress to the channel of the MOS transistor, the mobility of the majority carrier in the channel can be increased which increases drive current thereby improving performance of the MOS transistor. For example, applying a compressive uniaxial stress to the channel of a P-channel MOS (PMOS) transistor enhances the mobility of majority carrier holes, whereas applying a tensile uniaxial stress to the channel of an N-channel MOS (NMOS) transistor enhances the mobility of majority carrier electrons. The known stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance.
It is desirable to provide improved stress enhanced semiconductor devices and methods for fabricating such stress enhanced semiconductor devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
USPTO Backgrounds
USPTO Backgrounds