Read-only-memories (ROMs) are memories into which information is permanently stored during fabrication. Such memories are considered “non-volatile” as only read operations can be performed.
Each bit of information in a ROM is stored by the presence or absence of a data path from the word (access) line to a bit (sense) line. The data path is eliminated simply by insuring no circuit element joins a word and bit line. Thus, when the word line of a ROM is activated, the presence of a signal on the bit line will mean that a 1 is stored, whereas the absence of a signal indicates that a 0 is stored.
If only a small number of ROM circuits are needed for a specific application, custom mask fabrication might be too expensive or time consuming. In such cases, it would be faster and cheaper for users to program each ROM chip individually. ROMs with such capabilities are referred to as programmable read-only-memories (PROMs). In the first PROMs which were developed, information could only be programmed once into the construction and then could not be erased. In such PROMs, a data path exists between every word and bit line at the completion of the chip manufacture. This corresponds to a stored 1 in every data position. Storage cells during fabrication were selectively altered to store a 0 following manufacture by electrically severing the word-to-bit connection paths. Since the write operation was destructive, once the 0 had been programmed into a bit location it could not be erased back to a 1. PROMs were initially implemented in bipolar technology, although MOS PROMs became available.
Later work with PROMs led to development of erasable PROMs. Erasable PROMs depend on the long-term retention of electric charge as the means for information storage. Such charge is stored on a MOS device referred to as a floating polysilicon gate. Such a construction differs slightly from a conventional MOS transistor gate. The conventional MOS transistor gate of a memory cell employs a continuous polysilicon word line connected among several MOS transistors which functions as the respective transistor gates. The floating polysilicon gate of an erasable PROM interposes a localized secondary polysilicon gate in between the continuous word line and silicon substrate into which the active areas of the MOS transistors are formed. The floating gate is localized in that the floating gates for respective MOS transistors are electrically isolated from the floating gates of other MOS transistors.
Various mechanisms have been implemented to transfer and remove charge from a floating gate. One type of erasable programmable memory is the so-called electrically programmable ROM (EPROM). The charge-transfer mechanism occurs by the injection of electrons into the floating polysilicon gate of selected transistors. If a sufficiently high reverse-bias voltage is applied to the transistor drain being programmed, the drain-substrate “pn” junction will experience “avalanche” breakdown, causing hot electrons to be generated. Some of these will have enough energy to pass over the insulating oxide material surrounding each floating gate and thereby charge the floating gate. These EPROM devices are thus called floating-gate, avalanche-injection MOS transistors (FAMOS). Once these electrons are transferred to the floating gate, they are trapped there. The potential-barrier at the oxide-silicon interface of the gate is greater than 3 eV, making the rate of spontaneous emission of the electrons from the oxide over the barrier negligibly small. Accordingly, the electronic charge stored on the floating gate can be retained for many years.
When the floating gate is charged with a sufficient number of electrons, channel function is inhibited. The presence of a 1 or 0 in each bit location is therefore determined by the presence or absence of a conducting floating channel gate in each program device.
Such a construction also enables means for removing the stored electrons from the floating gate, thereby making the PROM erasable. This is accomplished by flood exposure of the EPROM with strong ultraviolet light for approximately 20 minutes. The ultraviolet light creates electron-hole pairs in the silicon dioxide, providing a discharge path for the charge (electrons) from the floating gates.
In some applications, it is desirable to erase the contents of a ROM electrically, rather than to use an ultraviolet light source. In other circumstances, it would be desirable to be able to change one bit at a time, without having to erase the entire integrated circuit. Such led to the development of electrically erasable PROMs (EEPROMs). Such technologies include MNOS transistors, floating-gate tunnel oxide MOS transistors (FLOTOX), textured high-polysilicon floating-gate MOS transistors, and flash EEPROMs. Such technologies can include a combination of floating gate transistor memory cells within an array of such cells, and a peripheral area to the array which comprises CMOS transistors.
A prior art EPROM device is described with reference to semiconductor wafer fragment 10 of FIGS. 1–3. FIG. 1 is a top view of wafer fragment 10, and FIGS. 2 and 3 are cross-sectional side views along the lines labelled X—X and Y—Y, respectively, in FIG. 1. Wafer fragment 10 comprises a substrate 12, having field oxide regions 14 formed thereover. Substrate 12 can comprise, for example, lightly doped monocrystalline silicon. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Field oxide regions 14 can comprise, for example, silicon dioxide. An active region 15 extends over and within substrate 12 between field oxide regions 14. A floating gate 16 and a control gate 18 are formed over the active region. Gates 16 and 18 can comprise, for example, conductively doped polysilicon.
Floating gate 16 is separated from substrate 12 by a tunnel oxide 11 layer 20. Gates 16 and 18 are separated from one another by an insulative layer 22 which can comprise, for example, a combination of silicon dioxide and silicon nitride, such as the shown ONO construction wherein a silicon nitride layer 17 is sandwiched between a pair of silicon dioxide layers 19. The silicon nitride comprises Si3N4, although other forms of silicon nitride are known. Such other forms include silicon enriched silicon nitride layers (i.e., silicon nitride layers having a greater concentration of silicon than Si3N4, such as, for example, Si4N4). An advantage of silicon-enriched silicon nitride layers relative to Si3N4 is that the silicon-enriched silicon nitride layers frequently do not require separate, discrete antireflective coatings formed between them and a photoresist. However, silicon enriched silicon nitride is difficult to pattern due to a resistance of the material to etching. Silicon enriched silicon nitride layers are formed to have a substantially homogenous composition throughout their thicknesses, although occasionally a small portion of a layer (1% or less of a thickness of the layer) is less enriched with silicon than the remainder of the layer due to inherent deposition problems.
Wafer fragment 10 further comprises silicon dioxide layers 24 and 26 extending along sidewalls of gates 16 and 18, and comprises a silicon dioxide layer 28 over control gate 18. Layers 24, 26 and 28 can electrically insulate gates 16 and 18 from other circuitry (not shown) that may be present on substrate 12.
The gate assembly shown in FIGS. 1–3 can be formed as follows. Initially, a portion of substrate 12 within the active region is oxidized to form an oxide layer which will ultimately be patterned into tunnel oxide 20. Next, a polysilicon layer is formed over the silicon dioxide layer, with the polysilicon layer ultimately being patterned to form floating gate 16. An antireflective coating is formed over the polysilicon layer, and a layer of photoresist formed over the antireflective coating.
After the photoresist is formed, it is patterned by selectively exposing portions of the photoresist to light to render the portions either more soluble or less soluble in a solvent than portions which are not exposed to the light. The antireflective coating absorbs light that penetrates the photoresist to prevent such light from reflecting back to either constructively or destructively interfere with other light passing through the photoresist. The photoresist is then exposed to the solvent to remove the more soluble portions of the photoresist and leave a patterned photoresist block over a portion of the polysilicon layer that is to become floating gate 16.
The patterned photoresist block protects the portion of the polysilicon layer it covers, while uncovered portions of the antireflective coating, polysilicon layer, and silicon oxide layers are removed with an etch. The portions of the polysilicon layer and oxide layer which remain are in the shape of floating gate 16 and tunnel oxide 20.
After the etch of the antireflective coating, polysilicon and oxide, the photoresist and antireflective coating are removed from over floating gate 16. The polysilicon of floating gate 16 is then exposed to oxygen under conditions which form a silicon dioxide layer over exposed surfaces of the polysilicon to create oxidized sidewalls 24 and 26, and a portion of insulative layer 22. Subsequently, layers of silicon nitride and silicon dioxide are provided to complete formation of insulative layer 22. Next, a second polysilicon layer is provided and patterned to form control gate 18. The second polysilicon layer is then exposed to oxygen to form silicon dioxide layers 24 and 26 at the sidewalls of control gate 18, and to form silicon dioxide layer 28 over a top of control gate 18.
Source and drain regions can be provided within active area 15 and operatively adjacent floating gate 16. The source and drain regions can be provided by implanting a conductivity enhancing dopant into substrate 12 after forming floating gate 16 and before oxidizing sidewalls of floating gate 16.
A continuing goal in semiconductor device fabrication is to minimize the number of fabrication steps required to form a semiconductor device. Accordingly, it would be desired to eliminate one or more of the above-discussed steps in forming a gated semiconductor assembly.
USPTO Backgrounds
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