A pervasive trend in modern integrated circuit manufacture is to downscale memory devices so as to increase the amount of data stored per unit area on an integrated circuit memory device, such as a flash memory device. Memory devices often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, is capable of storing two bits of data in a double-bit arrangement. That is, one bit can be stored using a first charge storing region on a first side of the memory device and a second bit can be stored using a second charge storing region on a second side of the memory device.
As shown in FIG. 1, a conventional charge trapping dielectric memory device 10 includes a pair of buried bitlines 12 disposed within a semiconductor substrate 14. A charge trapping dielectric stack, which typically includes a non-conductive charge trapping layer 20 disposed between a bottom dielectric layer 22 and a top dielectric layer 24, is disposed over the semiconductor substrate 14. The charge trapping layer 20 typically includes a pair of charge storing regions on opposite sides of the layer. Over the top dielectric layer 24 is a gate electrode 26. In such a configuration, the buried bitlines function as a source (i.e., a source of electrons or holes) and a drain with an active channel region defined therebetween. Each memory device can be programmed, read and erased by applying appropriate voltages to the source, drain and gate electrode.
Where possible, it is desirable to downscale such memory devices, while still maintaining desirable qualities, such as adequate data retention, and optimizing performance. However, memory device downscaling can result in a number of performance degrading effects. This is especially true when the width (i.e., the lateral dimension) of the gate electrode is comparable to the width of the buried bitlines. Such a memory device is not efficient from a channel length scaling point of view. In other words, the channel length and effective channel length end up being relatively short. Memory devices having a relatively short channel length can experience a number of undesirable electrical characteristics referred to as short channel effects (SCE). SCE generally occur when the gate electrode does not have adequate control over the active channel region. As the physical dimensions of the device decrease, SCE can become more severe.
In view of the foregoing, there is a need in the art for improved memory devices, such as charge trapping dielectric flash memory devices, that optimize scale and performance.
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