1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed in microelectronics fabrication. More particularly, the present invention relates to methods for forming gap filling trench fill layers within trenches within substrates employed in microelectronics fabrication.
2. Description of the Related Art
In the art of microelectronics fabrication, integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes, capacitors and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by patterned and/or blanket dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ electrical isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within a trench. Within the chemical mechanical polish (CMP) planarizing methods, means and materials are required to insure that when the desired degree of planarization is achieved the planarizing process is brought to completion without damage to underlying regions of the microelectronics fabrication.
Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar regions, the limited depth of focus typically obtained with advanced photoexposure tooling employed in the microelectronics fabrication art.
When forming within advanced integrated circuits trench isolation regions within isolation trenches, it has become common to employ as trench fill dielectric layers gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods. Silicon oxide layers formed employing such methods are desirable since such silicon oxide layers typically possess the inherently superior gap filling characteristics desirable for trenches of limited dimensions typically encountered in advanced integrated circuit microelectronics fabrication.
While gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are desirable as trench fill layers within trenches within advanced integrated circuit microelectronics fabrications, methods through which are formed such gap filling silicon oxide layers are not entirely without problems. Specifically, it is known in the art of integrated circuit microelectronics fabrication that gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit a surface sensitivity dependent upon the substrate layers upon which are formed those gap filling silicon oxide layers. In particular, when employing as substrate layers thermally grown silicon oxide layers formed within silicon semiconductor substrates, gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit inhibited formation rates in comparison with otherwise equivalent gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon substrate layers other than thermally grown silicon oxide layers. The gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon the thermally grown silicon oxide layers also typically exhibit inferior bulk quality (as determined by wet etch rates in dilute hydrofluoric acid) in comparison with otherwise equivalent gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon substrate layers other than thermally grown silicon oxide layers.
Inhibited formation rates within isolation trenches within semiconductor substrates of gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are undesirable since there is then formed within those isolation trenches gap filling silicon oxide layers which are particularly susceptible to dishing when subsequently planarized employing chemical mechanical polish (CMP) planarizing methods.
The planarizing methods typically remove not only silicon oxide trench fill layer material but any other silicon oxide materials such as thermal silicon oxide, conformal silicon oxide, etc. Therefore, it is customary to interpose a non-reactive substance such as silicon nitride between the underlying layers and such gap filling silicon oxide trench fill layers to act as a barrier or stop layer to prevent further removal of material as a consequence of the planarizing process, thus adding cost and complexity to the microelectronics fabrication. Also, inferior bulk quality of such gap filling silicon oxide trench fill layers often compromises the dielectric properties of such gap filling silicon oxide trench fill layers. Finally, enhanced surface roughness of such gap filling silicon oxide trench fill layers is undesirable since enhanced surface roughness of such gap filling silicon oxide trench fill layers often provides gap filling silicon oxide trench fill layers of enhanced porosity.
It is thus towards the goal of forming within advanced integrated circuit microelectronics fabrications gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods with enhanced bulk quality while attenuating a surface sensitivity when forming those gap filling silicon oxide trench fill layers, that the present invention is generally directed.
Methods and materials through which silicon oxide layers may be formed with desirable properties within integrated circuit microelectronics fabrications are known in the art of integrated circuit microelectronics fabrication.
For example, Jang et al., in U.S. Pat. No. 5,731,241, disclose a method for protecting a trench fill silicon oxide layer from excessive etching during multiple etching steps when forming the trench fill silicon oxide layer. The method employs a sacrificial silicon oxide layer formed selectively, while employing a sub-atmospheric pressure chemical vapor deposition (SACVD) method, upon a silicon oxide trench fill layer within a trench within a silicon substrate, wherein the sacrificial silicon oxide layer has a greater differential etch rate over the trench fill region and functions as a sacrificial layer to protect the trench fill silicon oxide.
Further, Jang et al., in U.S. Pat. No. 5,726,090, disclose a method for enhancing gap filling characteristics of ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layers formed upon thermal silicon oxide trench liner layers within semiconductor substrates within semiconductor integrated circuit microelectronics fabrications. The method employs an intermediate silicon oxide trench liner layer formed upon the thermal silicon oxide trench liner layer prior to forming the ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layer over the thermal silicon oxide trench liner layer, where the intermediate silicon oxide trench liner layer is treated with a nitrogen plasma prior to forming the ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layer thereupon.
Still further, Fahey, in U.S. Pat. 5,447,884, discloses a method for minimizing voids in a trench fill layer by forming an isolation trench liner layer of silicon nitride within a silicon isolation trench, while forming the silicon nitride layer as thin as 5 nanometers and by densification of a trench fill silicon oxide layer in a pyrogenic oxide annealing step carried out at 800 degrees centigrade.
Finally, Fulton, in U.S. Pat. No. 4,666,556, discloses a method for forming a conformal etch resistant layer of silicon dioxide within a trench wherein first a conformal layer of polysilicon is formed within the trench. Then the polysilicon layer is converted to a layer of silicon dioxide by thermal oxidation, thus filling the trench with silicon dioxide.
Desirable in the art are additional methods through which trenches within substrates employed within integrated circuit microelectronics fabrications may be filled with gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods, while: (1) attenuating a surface sensitivity when forming those gap filling silicon oxide trench fill layers; and (2) providing gap filling silicon oxide trench fill layers with enhanced bulk quality (as determined, for example, employing etch rates in dilute hydrofluoric acid). It is towards these goals that the present invention is more specifically directed.
A first object of the present invention is to provide a method through which a trench within a substrate employed in integrated circuit microelectronics fabrication may be filled with a gap filling silicon oxide trench fill layer formed employing a sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where there is attenuated a surface sensitivity when forming the gap filling silicon oxide trench fill layer.
A third object of the present invention is to provide a method in accord with the first object of the present invention or the second object of the present invention, where there is provided the gap filling silicon oxide trench fill layer with enhanced bulk quality (as determined by etch rate in dilute hydrofluoric acid).
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention or the third object of the present invention, where the substrate is a semiconductor substrate and the trench is an isolation trench within the semiconductor substrate.
A fifth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention, the third object of the present invention, or the fourth object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming within a trench within a silicon substrate employed in microelectronics fabrication a gap filling silicon oxide trench fill layer. To practice the method of the present invention, there is first provided a trench within a silicon substrate. There is then formed upon the silicon substrate and within the trench a gap filling silicon oxide trench fill layer formed employing an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method. There is then employed an annealing step in an oxidizing environment at an elevated temperature to density the gap filling silicon oxide trench fill layer. There is then performed a chemical mechanical polish (CMP) planarizing method wherein the silicon substrate acts as a stop layer to produce within the trench a densified gap filling silicon oxide trench fill layer with attenuated surface roughness and enhanced bulk quality and reduced trench recesses at corners.
The present invention provides a method through which there may be formed within a trench within a substrate employed in integrated circuit microelectronics fabrication a gap filling silicon oxide trench fill layer formed employing a sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method, where there is attenuated a surface sensitivity when forming the gap filling silicon oxide trench fill layer and where there is provided a gap filling silicon oxide trench fill layer with enhanced bulk quality (as determined employing etch rate in dilute hydrofluoric acid). The method of the present invention realizes these objects by forming within a silicon substrate a trench which is then subsequently filled with a gap filling silicon oxide trench fill layer formed employing an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
The method of the present invention may be employed where the substrate is a semiconductor substrate and where the trench is an isolation trench within the semiconductor substrate. Provided that the semiconductor substrate is a silicon semiconductor substrate, the method of the present invention does not discriminate with respect to the nature of a trench which is formed within the substrate. Thus, the method of the present invention may be employed where the substrate is a semiconductor substrate and the trench is an isolation trench within the semiconductor substrate.
The method of the present invention is readily commercially implemented. The method of the present invention provides a novel ordering of integrated circuit microelectronics fabrication methods such as silicon deposition, silicon oxide chemical vapor deposition, patterning, and similar methods which are otherwise generally known in the art of microelectronics fabrication. Thus, the method of the present invention is readily commercially implemented.
USPTO Backgrounds
USPTO Backgrounds