Error protection mechanisms are often used to ensure the integrity of the data stored in a solid-state drive. FIG. 1A illustrates a block diagram 100 of data stored in a prior art NAND flash memory page 110. The prior art NAND flash memory page 110 has sector 0 112, sector 1 114, sector 2 116, and sector 3 118 that are protected by the Error Correcting Code 0 (ECC 0) check bytes 120. Similarly, the ECC 1 check bytes 130 protects the sector 4 122, sector 5 124, sector 6 126, and sector 7 128 of the prior art NAND flash memory page 110.
Depending on the severity of the errors in each sector, the ECC 0 check bytes 120 and ECC 1 check bytes 130 can facilitate the detection of errors in the sectors and allow data recovery of the error(s) in the sectors. FIG. 1B illustrates a block diagram 150 of the data stored in a prior art NAND flash memory page 160. The prior art NAND flash memory page 160 has the sector 0 162, sector 1 164, sector 2 166, and sector 3 168 that are protected by the ECC check bytes 170. FIG. 1C illustrates a block diagram 180 of the code words stored in a prior art NAND flash memory page 190. The prior art NAND flash memory page 190 has four code words (CW) 1-4 192, 194, 196, and 198 that are protected by the ECC 0-3 check bytes 193, 195, 197, and 199 respectively.
USPTO Backgrounds
USPTO Backgrounds