1. Field of the Invention
The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device that adopts a frame readout method.
2. Description of Related Art
In video cameras and digital still cameras, a solid-state imaging device of a charge coupled device (CCD) type using a CCD register in a charge transfer portion has been used (see, for example, Japanese Unexamined Patent Application Publication No. 2004-96546 (hereinafter referred to as “patent document 1”).
The CCD-type solid-state imaging device includes a plurality of pixels arranged in a two-dimensional matrix in an imaging area on a semiconductor substrate, each pixel having a photoelectric conversion means (photodiode; PD). The incident light into each pixel is converted into an electric charge by the photodiode, and the electric charge is transferred through a vertical transfer portion and a horizontal transfer portion to a floating diffusion (FD) region formed in an output amplifier. The potential change in the FD region is detected by a MOS transistor, converted into an electrical signal, and amplified the converted electrical signal to output an image signal.
FIG. 5 is a diagrammatic view for explaining a known CCD-type solid-state imaging device. The CCD-type solid-state imaging device 101 shown in the figure essentially includes an imaging portion 104a, an optical black region 104b, a horizontal transfer portion 105, and an output portion 107. The imaging portion includes light receiving portions 108 arranged in a matrix of rows and columns, and vertical transfer portions 109, formed for each column (vertical lines) of the light receiving portions, for transferring charges from each of the light receiving portions.
In the CCD-type solid-state imaging device configured as the described above, by applying vertical transfer clocks Vφ to the vertical transfer portions from a timing signal generating circuit 103, electrical charges output from the light receiving portions to the vertical transfer portions are transferred in the vertical direction. Furthermore, by applying horizontal transfer clocks Hφ to the horizontal transfer portion from the timing signal generating circuit, the electrical charges transferred to the horizontal transfer portion are transferred in the horizontal direction, and converted in an FD region to a voltage to thereby be readout as a light receiving signal from an output portion.
The CCD-type solid-state imaging device is required to take a still image with high resolution, and hence it is necessary that all pixel signals are outputted without mixing. Therefore, as an output method for the CCD-type solid-state imaging device, (1) a method in which all pixels are simultaneously outputted and the individual pixels are independently transferred (all-pixel readout mode, so-called “progressive scan readout method”) or (2) a method in which charges of odd lines and even lines are alternately outputted per field and the individual pixels are independently transferred (frame readout method which means a two-field readout method here) has been used.
The frame readout method more advantageously secures a satisfactory amount of charges processed by the vertical transfer portions than the progressive scan method, and facilitates the reduction of cell size (size per one pixel), and therefore the frame readout method has been used in the CCD-type solid-state imaging device which is especially required to be reduced in size or increased in pixels. That is, the progressive scan method is required to form a packet of the vertical transfer portions for each pixel, whereas, in the frame readout method, one pixel of the two pixels is outputted in one field and therefore a packet of the vertical transfer portions is formed for the two pixels. Accordingly, the frame readout method more advantageously secures a satisfactory amount of charges processed by the vertical transfer portions than the progressive scan method, thereby facilitating the reduction of cell size.
FIGS. 6A-6D are diagrams for explaining frame readout (two-field readout) used for obtaining a still image with high resolution, wherein FIG. 6A is a diagram of frame readout (two-field readout) in which output (readout) is individually performed in two separate fields, i.e., the first field and the second field, FIG. 6B is a vertical synchronizing timing chart, FIG. 6C is a horizontal synchronizing timing chart, and FIG. 6D shows the transfer state of charges of the vertical transfer portions.
In the vertical transfer portions, a transfer electrode is formed to apply a readout clock for readout of the charges accumulated in the light receiving portions or a vertical transfer clock for vertical transfer by driving the vertical transfer portion. In the two-field readout method, in order to realize a drive of reading out one pixel of the two pixels (pixels of 1st line, 3rd line, 5th line, 7th line, 9th line, . . . shown in FIG. 6A) in the first field, and reading out the remaining one pixel of the two pixels (pixels of the 2nd line, 4th line, 6th line, 8th line, . . . shown in FIG. 6A) in the second field, readout clock separated from the pixel outputted in the first field and the pixel outputted in the second field needs to be applied. Furthermore, it is necessary to form another transfer electrode between the transfer electrodes to which the readout clocks is applied to prevent color mixing. Therefore, four transfer electrodes (V1 to V4) are needed in the two-field readout method.
In FIG. 6A, only the transfer electrodes V1, V3 to which the readout clocks are applied are shown, however transfer electrodes V2 are formed between the 2nd line and the 3rd line, between the 4th line and the 5th line, between the 6th line and the 7th line, and between the 8th line and the 9th line, and transfer electrodes V4 are formed between the 1st line and the 2nd line, between the 3rd line and the 4th line, between the 5th line and the 6th line, and between the 7th line and the 8th line.
In recent years, the cell size tends to be further miniaturized to improve the resolution (increase the number of pixels) or to reduce the device size, and, with respect to the frame readout method, in addition to the two-field readout method in which output (readout) is individually performed in two separate fields, a three-field readout method shown in FIGS. 7A-7F (FIG. 7A is a diagram of a three-field readout method, FIG. 7B is a vertical synchronizing timing chart, FIG. 7C is a horizontal synchronizing timing chart (1), FIG. 7D is a horizontal synchronizing timing chart (2), FIG. 7E shows the transfer state of charges of the vertical transfer portions corresponding to the horizontal synchronizing timing chart (1), and FIG. 7F shows the transfer state of charges of the vertical transfer portions corresponding to the horizontal synchronizing timing chart (2)), a four-field readout method shown in FIGS. 8A-8D (FIG. 8A is a diagram of a four-field readout method, FIG. 8B is a vertical synchronizing timing chart, FIG. 8C is a horizontal synchronizing timing chart, and FIG. 8D shows the transfer state of charges of the vertical transfer portions), a not shown five-field readout method, and a six-field readout method shown in FIGS. 9A-9D (FIG. 9A is a diagram of a six-field readout method, FIG. 9B is a vertical synchronizing timing chart, FIG. 9C is a timing chart for the readout portion and vertical transfer portions, and FIG. 9D shows the transfer state of charges of the vertical transfer portions) have been put into practical use.
In the three-field readout method, in order to realize a method of reading out one pixel of the three pixels (pixels of the 2nd line, 5th line, 8th line, . . . shown in FIG. 7A) in the first field, reading out the remaining two pixels of the three pixels (pixels of the 3rd line, 6th line, 9th line, . . . shown in FIG. 7A) in the second field, and reading out the remaining one pixel of the three pixels (pixels of the 1st line, 4th line, 7th line, . . . shown in FIG. 7A) in the third field, readout clock separated from the pixel outputted in the first field, the pixel outputted in the second field, and the pixel outputted in the third field needs to be applied needs to be applied. Furthermore, it is necessary to form another transfer electrode between the transfer electrodes to which the readout clocks are applied to prevent color mixing. Therefore, the three-field readout method needs six transfer electrodes (V1 to V6).
In FIG. 7A, only the transfer electrodes V1, V3, V5 to which the readout clocks are applied are shown, however, transfer electrodes V2 are formed between the 2nd line and the 3rd line, between the 5th line and the 6th line, and between the 8th line and the 9th line, transfer electrodes V4 are formed between the 1st line and the 2nd line, between the 4th line and the 5th line, and between the 7th line and the 8th line, and transfer electrodes V6 are formed between the 3rd line and the 4th line and between the 6th line and the 7th line.
In the four-field readout method, in order to realize a drive method of reading out one pixel of the four pixels (pixels on the 2nd line, 6th line, . . . shown in FIG. 8A) in the first field, reading out one pixel of the remaining three pixels of the four pixels (pixels on the 3rd line, 7th line, . . . shown in FIG. 8A) in the second field, reading out one pixel of the remaining two pixels of the four pixels (pixels of the 4th line, 8th line, . . . shown in FIG. 8A) in the third field, and reading out the remaining one pixel of the four pixels (pixels of the 1st line, 5th line, 9th line, . . . shown in FIG. 8A) in the fourth filed, readout clock separated from the pixel outputted in the first filed, the pixel outputted in the second field, the pixel outputted in the third field, and the pixel outputted in the fourth field needs to be applied. Furthermore, it is also necessary to form another transfer electrode between the transfer electrodes to which the readout clocks are applied to prevent color mixing. Therefore, the fourth-field readout method needs eight transfer electrodes (V1 to V8).
In FIG. 8A, only the transfer electrodes V1, V3, V5, V7 to which the readout clocks are applied are shown, but, transfer electrodes V2 are formed between the 3rd line and the 4th line and between the 7th line and the 8th line, transfer electrodes V4 are formed between the 2nd line and the 3rd line and between the 6th line and the 7th line, transfer electrodes V6 are formed between the 1st line and the 2nd line and between the 5th line and the 6th line, and transfer electrodes V8 are formed between the 4th line and the 5th line and between the 8th line and the 9th line.
In the six-field readout method, in order to realize a drive method of reading out one pixel of the six pixels (pixels on the 2nd line, 8th line, . . . shown in FIG. 9A) in the first field, reading out one pixel of the remaining five pixels of the six pixels (pixels on the 3rd line, 9th line, . . . shown in FIG. 9A) in the second field, one pixel of the remaining four pixels of the six pixels (pixels on the 4th line, 10th line, . . . shown in FIG. 9A) in the third field, one pixel of the remaining three pixels of the six pixels (pixels on the 5th line, 11th line, . . . shown in FIG. 9A) in the fourth field, and one pixel of the remaining two pixels of the six pixels (pixels on the 6th line, 12th line, . . . shown in FIG. 9A) in the fifth field, and the remaining one pixel of the six pixels (pixels on the 1st line, 7th line, 13th line, . . . shown in FIG. 9A) in the sixth field, readout clock separated from the pixel outputted in the first field, the pixel outputted in the second field, the pixel outputted in the third field, the pixel outputted in the fourth field, the pixel outputted in the fifth field, and the pixel outputted in the sixth field needs to be applied. Furthermore, it is necessary to form another transfer electrode between the transfer electrodes to which the readout clocks are applied to prevent color mixing. Therefore, the six-field readout method needs twelve transfer electrodes (V1 to V12).
In FIG. 9A, only the transfer electrodes V1, V3, V5, V7, V9, V11 to which the readout clocks are applied are shown, but, transfer electrodes V2 are formed between the 5th line and the 6th line and between the 11th line and the 12th line, transfer electrodes V4 are formed between the 4th line and the 5th line and between the 10th line and the 11th line, transfer electrodes V6 are formed between the 3rd line and the 4th line and between the 9th line and the 10th line, transfer electrodes V8 are formed between the 2nd line and the 3rd line and between the 8th line and the 9th line, transfer electrodes V10 are formed between the 1st line and the 2nd line and between the 7th line and the 8th line, and transfer electrodes V12 are formed between the 6th line and the 7th line and between the 12th line and the 13th line.
In the above-described multi-field readout method (three-field readout method, four-field readout method, five-field readout method, or six-field readout method), the amount of charges processed by the vertical transfer portions may be increased, as compared to that in a known two-field readout method.
Namely, in the known two-field readout method, one pixel of the two pixels is outputted in one field (see FIG. 6A), so that a packet of the vertical transfer portions is constituted by the two pixels (V1 to V4) (see FIG. 6B). By contrast, in the three-field readout method, only one pixel of the three pixels is outputted in one field (see FIG. 7A), so that a packet of the vertical transfer portions is constituted by the three pixels (V1 to V6) (see FIG. 7B). The on-state gates (the number of gates to which a high-level potential is applied) of the vertical transfer portions in the two-field readout method are two gates, whereas the number in the three-field readout method is four, which indicates that the amount of charges processed by the vertical transfer portions may be increased in the three-field readout method. Similarly, in the four-field readout method, only one pixel of the four pixels is outputted in one field (see FIG. 8A), so that a packet of the vertical transfer portions is constituted by the four pixels (V1 to V8) (see FIG. 8B). Therefore, the on-state gates of the vertical transfer portions in the four-field readout method are six gates. In the six-field readout method, only one pixel of the six pixels is outputted in a single field (see FIG. 9A), so that a packet of the vertical transfer portions is constituted by the six pixels (V1 to V12) (see FIG. 9B). Therefore, the on-state gates of the vertical transfer portions in the six-field readout method are eight gates. From the above, the amount of charges processed by the vertical transfer portions may be further increased in the multi-field readout method.
Accordingly, the multi-field readout method secures a satisfactory amount of charges processed by the vertical transfer portions even if the cell size is reduced, and whereby it may be applied to the CCD-type solid-state imaging device which is required to be improved in resolution or reduced in size.
In the three-field readout method (V1 to V6 six-phase transfer) shown in FIGS. 7A-7F, FIG. 7E shows a potential of the transfer state of charges of the vertical transfer portions corresponding to the horizontal synchronizing timing chart (1) (see FIG. 7C), and FIG. 7F shows a potential of the transfer state of charges of the vertical transfer portions corresponding to the horizontal synchronizing timing chart (2) (see FIG. 7D), and both operations may be used according to the horizontal synchronizing timing chart, but, when the forward gate in the transfer direction of charges is in the on state (state in which a high-level potential is applied) and simultaneously the backward gate in the transfer direction of charges is in the off state (state in which a low-level potential is applied), the number of clock changing points and the number of transfer cycles may be reduced in the operation shown in FIGS. 7D and 7F, as compared to those in the operation shown in FIGS. 7C and 7E. Especially, if a higher priority is given to the transfer speed or there is a demand for extending an overlap period of the vertical transfer clock (a period of time between a changing point of the vertical transfer clock and the next changing point) in the same period, the operation shown in FIGS. 7D and 7F is used. Further, if a four- or more multi-field readout method is employed as a readout method, the number of clock changing points is likely to be too large, and therefore a transfer method in which the forward gate in the transfer direction is turned on and simultaneously the downward gate is turned off is employed actively.
USPTO Backgrounds
USPTO Backgrounds