1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved shallow trench isolation structure having rounded trench upper corners.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves forming numerous devices in active areas of a semiconductor substrate. Select devices are interconnected by conductors which extend over a dielectric that separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit involves selectively connecting devices which are isolated from each other. When fabricating integrated circuits, it is therefore necessary to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for a MOS integrated circuit is a technique known as the "shallow trench process". Conventional trench processes involve the steps of etching a silicon-based substrate surface to a relatively shallow depth (e.g., between 0.2 to 0.5 microns) and then refilling the shallow trench with a deposited dielectric. The trench dielectric is then planarized to complete formation of a trench isolation structure in field regions of the substrate. The trench isolation structure is formed during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. Trench isolation processing serves to prevent the establishment of parasitic channels in the field regions between active areas. The trench process is becoming more popular than the local oxidation of silicon process ("LOCOS"), another well known isolation technique. The shallow trench process eliminates many of the problems associated with LOCOS, such as bird's-beak and channel-stop dopant redistribution problems. In addition, the trench isolation structure is fully recessed, offering at least a potential for a planar surface. Yet further, field-oxide thinning in narrow isolation spaces is less likely to occur when using the shallow trench process.
FIG. 1 is a cross-sectional view of a conventional STI structure disposed within a silicon substrate 102. Generally, once a trench is etched into substrate 102, a dielectric such as silicon dioxide (SiO.sub.2) or "oxide" 104 is deposited into the trench until it is completely filled. After the oxide has been deposited, a chemical mechanical polishing operation (CMP) may be performed in order to remove any excess oxide 104 from the surface of substrate 102 outside the trench area. As shown, the resulting trench has very sharp upper corners 106 near the surface of substrate 102. Sharp corners are those defined by a sidewall surface (or perimeter) of the trench near the upper surface of the trench being substantially perpendicular to the substrate surface. These sharp upper corners 106 are typically a result of the methodology by which the trench is formed--i.e., etched. A popular trench etchant is directional, whereby fine-line demarcation is a desired outcome brought about by, e.g., a plasma etch. This assumes the sidewalls of the trench are virtually vertical, and perpendicular to the substrate surface. The fill material merely maintains those sharp corners and is intended not to modify the position and/or angle at or near the trench upper corners.
Sharp upper corners 106 may introduce certain undesirable effects during subsequent processing steps which may have an impact on an integrated circuit's operation. One problem that results from sharp upper corners 106 is "structural stresses" in the silicon structure of substrate 102 when subsequent layers are deposited over and into a previously defined trench. The structural stresses are caused by stress mismatches between the substrate bulk material (single crystal lattice) near the edge of the active area and the overlying dielectric or conductive layers placed proximate to the active area edge or periphery. Any stress within the lattice may cause a number of dislocations in the silicon crystal near and around upper corners 106. These dislocations usually migrate deeper into lower portions of the substrate during subsequent thermal processing steps (e.g., annealing). As these dislocations migrate away from upper corners 106, the dislocations may form convenient paths for leakage currents. As a result, dislocations 106 may provide an electrical conduction bridge that allows currents flowing through one device to "leak" into the substrate.
In further processing, a dielectric layer 110 is typically deposited over the planarized surface. As shown, a conductive pattern 108 may be deposited and patterned over dielectric layer 110. Conductive pattern 108 is usually a polysilicon line, doped in situ or after patterning, acting as a transistor gate. Sharp corners 106 tend to congregate the electric fields in dielectric layer 110 which causes bunching of electric fields in the corner area. As a result of this bunching of the electric field, the corner has a lower breakdown voltage for the gate oxide. As a consequence, gate oxide reliability will suffer, i.e., the gate may short with the channel area before the devices projected life span has been reached (typically 10 years).
It would therefore be desirable to develop a technique for forming a trench isolation structure which would reduce substrate dislocations, and more evenly disperse electric fields among the active area and particularly at the active area edges.
USPTO Backgrounds
USPTO Backgrounds