1. Field of the Invention
The present invention is generally in the field of semiconductor fabrication. More specifically, the invention is in the field of fabricating deep N wells and triple well structures in semiconductor dies.
2. Background Art
High performance semiconductor devices include a high density of various mixed signal and RF circuits. The transistors in these circuits often require isolation from each other to prevent exposure to unwanted noise. As is known in the art, N type field effect transistors (“NFETs”) are typically fabricated in a P type substrate (“P substrate”). Also, it is common to fabricate P type field effect transistors (“PFETs”) in N type wells (“N wells”) situated within the same P substrate. In this commonly known technique, the PFETs generally have adequate isolation from noise from the substrate or adjacent NFETs since the PFETs are situated within small, local, and isolated N wells which are typically reverse biased or otherwise isolated from the P substrate. However, as compared with the PFETs, the NFETs are generally subject to more noise since the NFETs are situated within, and are not isolated from, the large P substrate which itself is subject to noise from various sources, such as ground noise.
Some conventional isolation structures, such as triple well structures, use deep N wells to isolate transistors from noise from the substrate or adjacent transistors. An exemplary triple well structure comprises an isolated P well surrounded by a lateral isolation N well and a deep N well, all situated within the P substrate. The deep N well must be situated in the P substrate at sufficient depth, for example at approximately 2.0 microns below the surface of the P substrate, in order to preserve proper NFET characteristics and to, for example, prevent leakage. The lateral isolation N well laterally surrounds the isolated P well and is in contact with the deep N well. Thus, the isolated P well is enclosed by the deep N well below and the lateral isolation N well around. The NFETs are fabricated within the isolated P wells while the PFETs are, as before, fabricated in the isolated N wells. The isolated P well is electrically isolated from the P substrate by the lateral isolation N well and the deep N well when the isolated P well is reverse biased in relation to the lateral isolation N well and the deep N well. Thus, the triple well structure helps prevent noise from adversely affecting the NFETs fabricated within the isolated P well and the devices fabricated outside the isolated P well.
Disadvantageously, conventional deep N well fabrication techniques require high energy implants in order to achieve the deep implanted N well while, by the same token, requiring thick photoresist masks to prevent the high energy implants from reaching the P substrate underlying the masked regions. The substantial depth of implant, and use of high energy implant and thick photoresist result in longer fabrication times and reduced precision in controlling the exact depth and geometry of the deep implanted N well regions; such requirements being significant drawbacks in conventional triple well isolation structures.
Therefore, a need exists for a triple well technology which requires lower energy implants, thinner photoresist, and which results in reduced fabrication time and increased precision of the depth and geometry of the deep N well regions.
USPTO Backgrounds
USPTO Backgrounds