1. Field of the Invention
The present invention relates generally to electronic imaging devices and, more particularly, to low noise CMOS image sensors having increased optical area within each pixel.
2. Description of the Related Art
Significant advances in photosensor image processing for camera and video systems are now possible through the emergence of CMOS pixel sensors. CMOS-based imaging sensors have distinct manufacturing cost savings and consume much less power than other technologies such as charge coupled devices (CCD). A CMOS image sensor's performance, however, is often limited by the noise generated by resetting each of its photodiodes to a known potential after each electronic image, or picture, is read out. Such noise is readily suppressed in CCD-based cameras because CCD reset noise is generated on only one capacitance, i.e., the sense diffusion diode that converts the photo-generated charge to a voltage. Also, full-frame memory is not needed to post-process the video to remove the reset noise because each pixel's reset and signal levels are successively read and the reset noise is conveniently removed by using only one memory element.
Similarly, the reset noise (kTC) in a CMOS sensor causes uncertainty about the voltage on each photodetector following the reset, but each pixel's reset signal is not normally available. Because the reset noise of CMOS imagers is often the dominant source of temporal noise and is critical to overall imager performance, there is a need for a pixel-based preamplifier that suppresses reset noise without requiring separate readout of all the reset and signal levels, in order to subsequently subtract the correlated reset noise using full-frame memory. In addition, the preamplifier must be as compact as possible to maximize the fraction of pixel area that is used for collecting the light. Simultaneously maximizing the light-gathering area and minimizing the reset noise maximizes sensor performance so that it can operate with usable fidelity even at low levels of light.
Mendis et al., discloses a single-stage, charge coupled device (CCD) type of image sensor in an article entitled, “A 128×128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems”, IEEE Electron Devices Meeting, p. 583, 1993. The overall imager is customarily considered a CMOS imager due to the co-integration of ancillary CMOS electronics that support the pixel preamplifier—even though the scheme requires process enhancements that significantly depart from conventional CMOS technologies. For example, the photogate must be optically transparent in the visible part of the electromagnetic spectrum. A transparent gate electrode must preferably be used to provide reasonable sensitivity in the blue part of the visible spectrum as is commonly done in CCDs, e.g. a thin indium tin oxide (ITO) gate electrode (e.g. U.S. Pat. No. 6,001,668). No CMOS foundry processes support integration of ITO electrodes due to possible wafer contamination and concomitant yield loss. Nevertheless, Mendis' charge-based preamplifier ideally provides a storage site at each pixel that readily facilitates both snapshot image formation and in-pixel correlated double sampling. Another key issue related to incompatibility with standard CMOS technology is the difficulty in optically isolating this storage site to eliminate image smear.
U.S. Pat. No. 5,898,168 teaches a compact CMOS pixel-based preamplifier that uses only three transistors, reproduced as FIG. 1, by providing a row-based circuit and method for successively reading the reset and signal levels. The system requires that the column buffer supporting each column of pixels preferably dwells on each specific row (c.f., FIGS. 5 and 6 of U.S. Pat. No. 5,898,168) in order to optimally perform the correlated double sampling required for suppressing reset noise by successively reading each video line's reset and signal levels. Alternatively, a full page of memory must be allocated either on-chip or in the external camera electronics to subtract each pixel's reset value from its final signal value on a frame-by-frame basis. Further, the image formation process should preferably be performed on a row-by-row basis in order to minimize inaccuracy in measuring the reset and signal levels for each pixel. The basic three transistor circuit thus generates large motion artifacts because of the need to successively read the reset and signal levels during each line of video. Minimizing such artifacts results in an alternative embodiment comprising five transistors per pixel, as illustrated in FIG. 1S of the '168 patent.
FIG. 2 is reproduction of the timing diagram for operating the three transistor pixel of the '168 patent. Each line of video in the imager is separately reset (47), signals are separately integrated (39, 41 and 43), separately read (49), and then reset again to prepare for the next frame time. An imager comprising N rows thus forms an electronic image over N separate integration times.
In view of the foregoing, it would be desirable to have a pixel cell comprising only three transistors, to maximize the optical area, while still having low-noise and minimizing motion artifacts.
USPTO Backgrounds
USPTO Backgrounds