The present invention relates to a package board on which an IC chip is to be mounted, more particularly, a package board provided with soldering pads on its top and bottom surfaces. The soldering pads are connected to the IC chip, as well as to boards such as a mother board, a sub-board, etc.
A highly integrated IC chip is mounted on the package board and connected to a mother board, a sub-board, etc. Hereunder, a configuration of this package board will be described with reference to FIG. 23, which is a cross sectional view of the package board 600 provided with an IC chip 80 and mounted on a mother board 90. The package board 600 includes conductor circuits 658A and 658B formed on both surfaces of its core board 630. Furthermore, conductor circuits 658C and 658D are formed in the upper layer of the conductor circuits 658A and 658B with an interlaminar resin insulating layer 650 therebetween respectively. On the upper layer of the conductor circuits 658C and 658D is formed an interlaminar resin insulator 750. In the interlaminar resin insulating layer 650 are formed via-holes 660A and 660B and in the interlaminar resin insulator 750 are formed via-holes 660D and 660C respectively. On the other hand, on the top surface of the package board on which the IC chip 80 is mounted are formed soldering bumps 676U connected to the pads 82 formed on the IC chip 80 side surface of the package board. On the bottom surface of the package board 600 on which a sub-board 90 is mounted are formed soldering bumps 676D connected to the pads 92 formed on the mother board 90 side surface of the package board 600. Each of the soldering bumps 676U is formed on a soldering pad 675U. Each of the soldering bumps 676D is formed on a soldering pad 675D. In order to more improve the connection reliability of the soldering bumps 676U and 676D, resin 84 is sealed in a clearance between the IC chip 80 and the package board 600. In the same way, resin 94 is sealed in a clearance between the package board 600 and the mother board 90.
As described above, the package board 600 is used to connect the highly integrated IC chip 80 to the mother board 90. The pads 82 formed on the IC chip 80 side surface are as small as 133 to 170 xcexcm in diameter and the pads 92 formed on the mother board 90 side surface are as large as 600 xcexcm in diameter. Consequently, the IC chip 80 cannot be attached directly to the mother board 90. This is why the package board 600 is disposed between the IC chip 80 and the mother board 90.
The package board 600 is formed so as to match both IC chip side soldering pads 675U and mother board side soldering pads 675D with both IC chip side pads 82 and mother board side pads 92 in size respectively. Consequently, the rate of the area occupied by the soldering pads 675U on the IC chip side surface of the package board 600 differs from the rate of the area occupied by the soldering pads 675D on the mother board side surface of the package board 600. And, both interlaminar resin insulator 650 and core board 630 are made of resin and the soldering pads 675U and 675D are made of a metallic material such as nickel. Consequently, when the resin portions of the interlaminar resin insulating layers 650 and 750 are shrunk due to curing, drying, etc. in the manufacturing process, the package board is warped toward the IC chip side sometimes. This is because of a difference in the rate of the area occupied by the soldering pads between 675U on the IC chip side surface and 675D on the mother board side surface of the package board 600 as described above. In addition, when in an actual usage of the package board 600 on which an IC chip is mounted, the heat generated from the IC chip makes the package board expand and shrink repetitively, causing a difference of shrinkage factor between the resin portion and the metallic portion of those soldering pads. And, this results in warping of the package board 600 sometimes.
In the case of a multi-layer board used as such a package board, one of a plurality of conductor circuit layers is generally used as a ground layer or a power supply layer to reduce noise or for other purposes. In the case of a multi-layer wiring board manufactured by a conventional technology as shown in FIG. 23, however, the ground layer (or the power supply layer) is connected to an external terminal via a wire. In other words, wires 658A and 658B (conductor circuits) used as ground layers are formed on the upper layer of the board 630. The wiring (ground layer) 658B is connected to the wiring 658D-S through a via-hole 660B and the wiring 658D-S is connected to the soldering bump 676U through a via-hole 660D.
Since the ground layer 658D is connected to the soldering bump 676U via the wiring 658D-S in this case, the wiring 658D-S is apt to generate noise and the noise causes malfunctions in electric elements such as an IC chip connected to the multi-layer wiring board. In addition, such the multi-layer wiring board needs a space for wiring in itself and this makes it difficult to realize higher integrated printed wiring boards.
On the other hand, a package board generally includes capacitors therein used to reduce noise from signals transmitted between the IC chip and the mother board. In an embodiment as shown in FIG. 23, inner layer conductor circuits 658A and 658B provided on both surfaces of the core board 630 are used as a power supply layer and a ground layer, so that capacitors are formed between the core board 630 and the power supply layer and the ground layer respectively.
FIG. 24A is a top view of the inner conductor circuit layer 658B formed on the top surface of the core board 630. On the inner conductor circuit layer 658B are formed a ground layer 638G, as well as land-pads 640 for connecting the top layer to the bottom layer. And, around each of the land-pads 640 is formed an insulating buffer 642.
Each of the land-pads 640 consists of a land 640a of a through-hole 636 of the core board 630 shown in FIG. 23, a pad 640b connected to a via-hole 660A going through the upper interlaminar resin insulating layer 650, and a wire 640c connecting the land 640a to the pad 640b. 
In the case of a package board manufactured by the conventional technology, the land 640a is connected to the pad 640b via the wiring 640c. Consequently, the transmission path provided between the upper conductor layer and the lower conductor layer is longer, so that the package board has confronted with problems that the signal transmission slows down and the connecting resistance increases.
Furthermore, as shown in FIG. 24A, a corner K is formed at a joint between the wiring 640c and the land 640a, as well as at a joint between the wiring 640c and the pad 640b respectively. And, stress is concentrated on each of those corners K due to a difference of thermal expansivity between the core board 630/interlaminar resin insulating layer 650 made of resin and the landpad 640 made of a metallic material (copper, etc.). This causes a crack L1 to be generated sometimes in the interlaminar resin insulating layer 650 as shown in FIG. 23, resulting in breaking of a wire in the conductor circuit 658D or the via-hole 660D formed in the interlaminar resin insulating layer 650.
On the other hand, the mother board 90 side soldering bumps 676D are connected to the inner conductor circuit layer 658C through the via-holes 660D, the wiring 678, and the soldering pads 675. FIG. 24B shows an expanded view (C direction) of both via-hole 660D and soldering bump 675D shown in FIG. 23. A soldering bump 675 on which a soldering bump 676D is mounted is formed circularly and connected to a circularly-formed via-hole 660D through the wiring 678.
The IC chip 80 repeats the heat cycle between high temperature during an operation and cooling down up to the room temperature at the end of an operation. Since the thermal expansivity differs significantly between the IC chip 80 made of silicon and the package board 600 made of resin, stress is generated in the package board in the heat cycle, causing a crack L2 to be generated in the sealing resin 94 provided between the package board 600 and the mother board 90. And, such a crack L2 is extended thereby to disconnect the via-hole 660D from the soldering bump 675D of the package board 600 sometimes. In other words, as shown in FIG. 24C for an expanded view (D direction) of the via-hole 660D and the soldering bump 675 shown in FIG. 23, sometimes a crack L2 causes breaking of the wiring 678 connecting the via-hole 660D to the soldering bump 675D on which the soldering bump 676D is mounted.
Under such circumstances, it is an object of the present invention to provide a package board provided with soldering bumps, which can solve the above conventional problems and never be warped.
It is another object of the present invention to provide a multi-layer wiring board and a multi-layer printed wiring board that are not affected by noise easily.
It is also another object of the present invention to provide a package board that can shorten a transmission path formed between the upper conductor wiring layer and the lower conductor wiring layer.
It is also another object of the present invention to provide a package board that will never cause breaking of a wire between soldering bump and via-hole.
In a package board according to a first aspect of the invention, the soldering pads on the IC chip side surface of the package board are small, so the rate of the metallic portion occupied by those soldering pads is also small. On the other hand, the soldering pads on the mother board side surface of the package board are large, so the rate of the metallic portion occupied by those soldering pads is also large. This is why a dummy pattern is formed between conductor circuit patterns on the IC chip side surface of the package board thereby to increase the metallic portion and adjust the rate of the metallic portion between the IC chip side surface and the mother board side surface of the package board so as to protect the package board from warping. The dummy pattern mentioned above does not have any functional meaning such as an electrical connection and a capacitor. It just means a pattern formed mechanically.
In a package board according to a second aspect of the invention, the soldering pads on the IC chip side surface of the package board are small. Thus, the metallic portion occupied by the soldering pads is less than that of the mother board side surface of the package board, where the soldering pads are large and the metallic portion occupied by the soldering pads is large. This is why a dummy pattern is formed at the outer periphery of each conductor circuit on the IC chip side surface of the package board thereby to increase the metallic portion thereon and adjust the rate of the metallic portion on the package board surface between the IC chip side and the mother board side. This metallic dummy pattern is also effective to improve the mechanical strength of the outer periphery of the package board, as well as protect the package board from warping.
In a package board according to a third aspect of the invention, a power supply layer and/or a ground layer is formed as an inner layer conductor circuit formed under an insulating layer that supports the outermost layer conductor circuits. Then, a via-hole is connected directly to the second conductor circuit and a solder bump is formed in the via-hole. It is therefore not necessary to provide a wire for connecting the power supply layer or the ground layer to the soldering bumps. Consequently, the package board is free of any noise to be mixed in wires.
In a package board according to a fourth aspect of the invention, a power supply and/or a ground layer is formed as the second conductor circuit disposed under the second interlaminar resin insulating layer that supports the conductor circuits formed in the outermost layer. A via-hole is connected directly to the second conductor circuit and a soldering bump is formed in the via-hole. It is therefore not necessary to provide a wire for connecting the power supply layer or the ground layer to the soldering bumps. Consequently, the package board is free of any noise to be mixed in wires.
In a package board according to a fifth aspect of the invention, each land and each pad are formed integrally and connected directly to each other without using a wire. It is thus possible to shorten the transmission path provided between upper and lower conductor layers, as well as to reduce the connecting resistance significantly. In addition, since the land and the pad are connected directly to each other without using a wire, no stress is concentrated at a joint between wiring and land, as well as at a joint between wiring and pad. It is thus possible to protect the package board from breaking of a wire to be caused by a crack generated by such concentrated stress.
In a package board according to a sixth aspect of the invention, a soldering bump is formed in a via-hole, so that each soldering bump is connected directly to a via-hole. Therefore, even when the package board is cracked, it is prevented that breaking of a wire occurs between the soldering bump and the via-hole. In other words, the conventional package board, where a soldering pad is connected to a via-hole through a wire and a soldering bump is formed on a soldering pad, cannot avoid crack-caused breaking of a wire connecting via-holes to soldering pads. A soldering bump is thus disconnected from a via-hole due to such a crack generated inside the package board. The package board defined in this aspect of the invention, however, is completely protected from breaking of a wire caused by such a crack.
In a package board according to a seventh aspect of the invention, a soldering bump is formed in a via-hole, so that each soldering bump is connected directly to each via-hole. It is thus possible to prevent breaking of a wire between a soldering bump and a via-hole even when the package board is cracked. Such a soldering bump is also formed in a plurality of via-holes respectively in this case. It is possible to utilize a fail-safe, since the soldering bump can be connected to another via-hole when one of the via-holes is disconnected from the soldering bump. In addition, since a soldering bump is formed on a plurality of via-holes, a soldering bump can be formed larger to each via-hole.
In the present invention, a dummy pattern may be electrically connected to a power supply layer or a ground layer, or may be the power supply layer or a ground layer, for reducing noise in signal lines.
USPTO Backgrounds
USPTO Backgrounds