Active pixel sensor (APS) imaging devices are described in U.S. Pat. No. 5,471,515. These imaging devices include an array of pixel cells, arranged in rows and columns, that convert light energy into electric signals. Each pixel includes a photodetector and one or more active transistors. The transistors typically provide amplification, read-out control and reset control, in addition to producing the electric signal output from the cell. Providing amplification at each pixel may help to reduce noise and distortion levels.
Main sources of image sensor noise include fixed pattern noise (FPN) or temporal noise. FPN may manifest as a stationary background pattern in the image which is caused by mismatches in device parameters. Temporal noise is the temporal variation in pixel output values under uniform illumination due to device noise. Row-wise temporal noise (RTN) may manifest as stripes of different intensity in an image produced by an object with uniform intensity. Both FPN and RTN may be caused by voltage fluctuations in the sensor.
A sensor includes a pixel array with pixels arranged in rows and columns. Analog signals produced by the pixels during an exposure are passed to a read-out chain. The read-out chain includes a sample-and-hold (S/H) block and an analog-to-digital converter (ADC). A reference voltage generator provides a reference voltage to capacitors in each of the S/H units in the S/H block (one per column) during a pixel read-out operation. The reference voltage generator provides another reference voltage to capacitors in the ADC during a digitization operation.
The reference voltage generator includes a variable voltage generator, e.g., a resistor ladder with a current source and multiple switches which may be selected in different numbers to generate different voltages. The reference voltage generator also includes a sample-and-hold circuit to sample a reference voltage prior to the pixel read-out operation or the digitization operation and a buffer amplifier to drive the appropriate reference voltage to the relatively high impedance load presented by the S/H block and the variable impedance load provided by the ADC.
USPTO Backgrounds
USPTO Backgrounds