As known, an impedance effect frequently causes an inaccurate signal measurement for a circuitry system. The impedance effect may be resulted from various factors, including, for instances, an improper measuring operation on testing tool, a hetero-metal junction between the testing tool and a device under test, a circumstance interference, an environmental variation, and so on. Presently, it is regarded as one of the important performance indicators for a circuitry system to provide a capability of accurate calibration of a signal measurement with violation of an impedance effect.
FIG. 1A illustrates a conventional light-driving circuitry system including an automatic power control (APC) circuit 108, a working signal generator 101, a feedback unit 105 and a plurality of measured pads 106, 107, 109, 110 formed on the system 1. The working signal generator 101 contains a light-radiating device (i.e. a Laser Diode, LD) and a power detector (e.g. a Photodiode, PD) for monitoring a power output of a light emitted from the light-radiating device and then gradually output a working voltage “Vin” based on said power output. The automatic power control (APC) circuit 108 further contains a comparative unit 102 and a digital to analog converter 103 wherein the digital to analog converter 103 is used for setting a reference voltage “Vref” on demands. The comparative unit 102 as a comparator has two inputs 1020, 1021 for receiving the working voltage “Vin” and the reference voltage “Vref”, an output 1023 for outputting a target voltage “Vtarget” to a Laser Diode Output (“LDO”) depending upon a comparison result between the working voltage “Vin” and the reference voltage “Vref”, and a node 1022 individually connected to the two measured pads 106 and 107 for the signal measurement. Due to a circuit layout of connection of the couple of measured pads 106, 107 to the node 1022 of the comparative unit 102, a couple of trace resistances as two resistors “Rin1” and “Rin2” will be inherently produced therebetween.
The feedback unit 105 receives the target voltage “Vtarget” from the comparative unit 102, and then generates a current control signal to adjust the logic level of the working voltage output of the working signal generator 101, based on level variation of the target voltage “Vtarget”. If the working voltage reaches a specific condition, for example, having the same value/level as the reference voltage “Vref”, the target voltage “Vtarget” output of the comparative unit 102 might be inverted into a first logic-level (e.g. a logic low) to keep the level of the working voltage output of the working signal generator 101 unchanged for a next operating cycle; Otherwise, the target voltage “Vtarget” of the comparative unit 102 might be at a second logic-level (e.g. a logic high) to order/switch the feedback unit 105 to gradually modify the level of the working voltage output of the working signal generator 101 for a next operating cycle.
Before the automatic power control (APC) circuit 108 is electrically connected with the working signal generator 101 and the feedback unit 105, a calibration of a signal measurement for diminishing the impedance effect predicted on the automatic power control (APC) circuit 108 is required. A test instrument 104 such as a parameter measuring unit (PMU) or a voltmeter provides a plurality of probes connected thereon, including two probes (not shown) which are respectively utilized to contact the pads 106 and 107 for indicating a voltage of the pad 107 for signal calibration. If there is a non-ideal contact established between the probes and the respective measured pads 106, 107, a couple of contacting resistances such as two resistors “Rin3” and “Rin4” will be inherently produced therebetween. A high-impedance input will be generated in the test instrument 104. Beside, one of the probes connected with the measured pad 106 is grounded. Nevertheless, on the circuitry system, an using area occupied by each of the measured pads 106, 107 is limited in approximate 50 μm 50 μm, and a pitch between the probes remains at approximate 40 μm.
Further referring to FIG. 1B, the automatic power control (APC) circuit 108 is being in form of an integrated circuit (IC) chip. The APC circuit chip 108 contains the comparative unit 102, the digital to analog converter 103 (as shown in FIG. 1A), and a plurality of pins extended from the APC circuit chip 108 including, for example, a power pin “VDD”, a Monitor Diode Input (“MDI”) pin, a Laser Diode Output (“LDO”) pin, and a ground pin 1022 (as the node 1022 of the comparative unit 102 shown in FIG. 1A).
Similarly, the ground node 1022 of the APC circuit chip 108 is individually connected to the couple of measured pads 106, 107 thereby producing a couple of trace resistances as the two resistors “Rin1” and “Rin2”. In such a circuitry layout, the location of pad 106 is more far from the APC circuit chip 108 for a grounding usage after the APC circuit 108 is packaged, rather than the pad 107 that is more adjacent to a trimming circuit. This would cause the difference trace resistances (i.e. Rin2<Rin1) for both pads 106, 107. Beside, due to a non-ideal contact between the probes and the pads 106, 107, the couple of contacting resistances as the two resistors “Rin3” and “Rin4” are produced as well as forming a high-impedance input during the signal measurement of the test instrument 104. The two resistors “Rin3” and “Rin4” derived from contacts of the probes will greatly contribute a voltage potential “VGS” on the ground node 1022 of the APC circuit chip 108. When the APC circuit chip 108 is turned on, the voltage potential “VGS” on the ground node 1022 will increase a potential offset of the working voltage “Vin” input of the APC circuit chip 108. The result of the signal measurement for the working voltage “Vin” input of the APC circuit chip 108 would be inaccurate. Thus, it is essential that the potential offset of the working voltage “Vin” input of APC circuit chip 10 must be properly pre-trimmed with reference to this voltage potential on the pad.
For measuring the voltage potential “VGS” on the ground node 1022, the test instrument 104 (like a PMU) only needs to directly measures a voltage potential “VP107” on the pad 107 to serve as a voltage value “VGS” of the ground node 1022, thereby indicates a measured voltage “VPMU” thereon (i.e. VPMU=VP107=VGS), with utilization of a minimum current “I2” (approaching zero) flowing through the resistors “Rin2” and “Rin4”, regardless of resistance values on the resistors “Rin2” and “Rin4”. After such an APC circuit chip 108 is packaged, only the pad 106 is grounded and the resistance value of the resistor “Rin3” might become zero. A voltage difference of approximate 14 mv from the pad 106 to the ground node 1022 would be caused. For this case, if it is desirable that a required potential level of the working voltage “Vin” input of the APC circuit chip 108 is kept at 185mv after the APC circuit chip 108 is packaged, a ramping voltage “Vin” output to the APC circuit chip 108 before packaged needs to be pre-adjusted to reach “185 mv+(VP107−14 mv)” by a trimming circuit.
In another case, as soon as a poor contact occurring between the probe and pad 106, a resistance of the resistor “Rin3” would become enlarged to raise the voltage “VGS” of the ground node 1022 to reach a range of 70 mv˜80 mv. Correspondingly, the ramping voltage “Vin” output of the APC circuit chip 108 should be adjusted into a voltage range of 241 mv˜251 mv. As this result, the ramping voltage “Vin” which has been adjusted within the range of 241 mv˜251 mv, greatly exceeds a predetermined target voltage value in level. Therefore, if the voltage “VGS” of the ground node 1022 becomes raised greatly in approaching 40 mv, a calibration of the reference voltage “Vref” input (as shown in FIG. 11A) of the APC circuit chip 108 would be required. Oppositely, if the voltage “VGS” of the ground node 1022 becomes raised greatly in exceeding 40 mv, it is necessary that the grounding pin (as the ground node 1022) of the APC circuit chip 108 would be fixed.
Due to usage of only one grounding path, the conventional APC circuit chip would need pin fixing as long as a poor contact between the probe and the ground pin 1022 frequently occurs. This results in a lower chip yield and a higher manufacturing expense during a process of mass manufacture.
Another conventional method for measuring wafer yield disclosed in U.S. Pat. No. 6,784,674 introduces a probe board having signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. Hence, a failure occurs under circumstances, such as an improper contact with the measure pad, will cause a connecting resistance with the probe.
Therefore, it is essential to design a method and a mechanism for accurately calibrating signal measurement of a circuitry system, capable of reducing the impedance effect which may be resulted from electrical contact of a probing head of a test instrument with a testing pad located in the circuitry system during this signal measurement process.
USPTO Backgrounds
USPTO Backgrounds