Many audio devices, such as audio analog to digital converters (ADCs), digital to analog converters (DACs), and audio encoder-decoders (CODECs), are configured to support multiple clock modes and/or different data formats. For discussion purposes, consider a typical audio device, such as an ADC or CODEC, operating on pulse code modulated (PCM) data and utilizing a serial audio output port. A typical audio serial data port outputs bits of a serial audio data (SDOUT) stream in response to an associated serial clock (SCLK) signal. In a stereo system, two channels of audio data are time-multiplexed onto the SDOUT stream with a left-right clock (LRCK) signal at the audio data sampling frequency (rate). Overall timing is controlled by an external master clock (MCK) signal, which is then often divided in frequency to generate an internal master clock (MCLK) signal for timing internal device operations, for example, filter operations. In the master mode, the SCLK and LRCK clock signals are generated internally, in response to the received MCK signal, and output to the source or destination of the SDOUT stream. In the slave (asynchronous) mode, the SCLK and LRCK clock signals are received from the source or destination of the SDOUT stream, along with the MCLK signal.
Many audio devices support different ratios between the internal master clock (MCLK) signal frequency and the data sampling frequency, which is set by the frequency of a data clock (DCK) signal. (In the PCM audio system described above, the LRCK signal is the DCK signal). One particular desirable feature in DACs is therefore the capability of detecting the data sampling frequency of the incoming digital data stream and subsequently automatically selecting the proper divisor for generating an MCLK signal having a frequency in a desired divide ratio with respects to the DCK signal frequency. In ADCs, the digital output data sampling frequency is often based on the specific system application, and hence it is often desirable to automatically set the proper MCLK rate that produces that output data sampling frequency.
Some existing audio devices require that the user specify whether the DCK signal frequency corresponds to a “single speed”, “double speed”, or “quad speed” mode. For example, in one typical audio system, if the DCK signal frequency in the single speed mode is up to 48 kHz, then the DCK signal frequency in the double speed mode is between 48 kHz and 96 kHz, and the quad speed mode encompasses all supported DCK signal frequencies above 96 kHz. Once the speed mode is set by the user, a divide ratio for dividing the external MCK signal is selected to produce a corresponding internal MCLK signal frequency having a desired frequency ratio with respect to the DCK signal frequency. For example, in the single speed mode, the MCK frequency to DCK signal frequency divide ratio may be set at a 256×, the divide ratio for the double speed mode set at 128×, and the divide ratio for the quad speed mode set at 64×. Disadvantageously, this conventional technique requires user intervention and/or additional pins on the device for indicating the current speed mode such that an appropriate divisor is selected to divide the MCK signal frequency to produce the desired MCLK signal frequency to DCK signal frequency ratio.
Other currently available devices operate with a single speed mode, and then select the appropriate MCK divide ratio. A significant drawback to this second approach is the limited number of DCK signal frequencies that can be detected when minimizing the size and complexity of the required on-chip circuitry.
Co-assigned U.S. Pat. Nos. 6,492,928 and 6,281,821 to Rhode et al., incorporated herein by reference, utilize both a master clock (MCK) signal and a data clock (DCK) signal, which separates a stream of data samples into at least two (2) channels (i.e. the LRCK signal in the case of a stream of stereo audio PCM data). However, the technique disclosed in the Rhode et al. patents does not measure the absolute rate of the MCK signal, and is therefore is limited in the range of clock modes that can be supported.
Another technique is taught by U.S. Pat. No. 6,556,157 to Itani et al., which is also co-assigned and incorporated herein by reference. The Itani et al. patent describes a clock mode selection circuit that measures the ratio between the LRCK signal frequency and the MCK signal frequency by successively pre-dividing the MCK signal frequency and then checking the resulting frequencies against the LRCK frequency for a valid frequency ratio. Then, the absolute frequency of the MCK signal is measured by pre-dividing it and checking the resulting frequency against an internally generated ramp time. The mode mapping requires that the measurement of the LRCK frequency to MCK frequency ratio to be performed before measuring the absolute MCK signal frequency and utilizes a pre-divide factor common to both measurements. In this case, the output frequency of the pre-divide operation also serves as the internal master clock (MCLK) signal.
U.S. Pat. No. 6,667,704 to Grale et al., incorporated herein by reference, also describes mode control circuits that measure the absolute frequency of the MCK signal by pre-dividing the MCK signal frequency and then checking the resulting divided frequency against an internally generated ramp time. Disadvantageously, the linear components, such as resistors, current sources, and capacitors, utilized in these circuits often vary with such factors as changes in fabrication process and temperature, although the Itani et al. patent briefly mentions that the values of these linear components can be trimmed by calibration.
Given the disadvantages of the existing approaches to selecting the correct operating mode for different data sampling frequencies, improved techniques are required. Such techniques should reduce the amount and complexity of the required on-chip circuitry. Furthermore, these techniques should support a wide range of possible data sampling frequencies and divide ratios across a range of device operating conditions.
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