1. Field of the Invention
The invention relates to an extreme level circuit, i.e., a circuit for detecting an extreme level (maximum or minimum value) of a plurality of input signals.
2. Description of the Related Art
EP-A-0,430,707 corresponding to U.S. Pat. No. 5,159,211 describes such an extreme level circuit for detecting an extreme level of two input signals. Starting from a well-known circuit comprising a pair of differential transistors with interconnected emitters from which the output extreme level can be taken, an improvement is presented to prevent distortions from occurring. This improvement comprises a pair of bias generating circuits which are crossconnected to the collectors of the differential transistors. This cross-connection makes it very difficult to expand the circuit to a circuit suitable for determining the extreme level of more than two input signals.
USPTO Backgrounds
USPTO Backgrounds