1. Field of the Invention
The present invention relates to, for example, a NAND flash memory and, more particularly, to a semiconductor memory device in which multilevel data can be stored in a memory cell.
2. Description of the Related Art
In a NAND flash memory, a plurality of cells arranged in a column direction are connected in series so as to constitute NAND cells, and the drain side of each of the NAND cells is connected to a bit line through a selector gate. Each bit line is connected to a latch circuit for writing and a latch circuit for reading. A data write operation or a data read operation is collectively performed with respect to all the cells or half the cells (for example, cells of 2 to 4 kB) arranged in the row direction.
Further, in an erase operation, a threshold voltage of the memory cell is set at a negative value, and electrons are injected into the memory cell by a write operation, whereby the threshold voltage is set at a positive value. However, in the NAND cells, a plurality of memory cells are connected in series. Thus, at the time of a read operation, unselected cells must be set in an on-state. Accordingly, a read voltage (Vread) higher than the threshold voltage is applied to the gate of the memory cell. On the other hand, in the write operation, the threshold voltage to be written to the memory cell must not exceed Vread. For this reason, in the write operation, program, and program/verify/read are repeatedly performed for each bit, and the threshold voltage is controlled such that the threshold voltage does not exceed Vread.
Further, recently, an increase in the memory capacity has rapidly been advanced, and a multilevel memory in which data of two bits or more is stored in a cell has been developed. For example, when two-bit data is stored in a cell, four threshold voltages must be set, and it is necessary to make the distribution of the threshold voltage per one threshold voltage narrower than a memory in which one-bit data is stored in a cell. This write operation is performed with high accuracy, and hence there is a problem that the write speed becomes low.
On the other hand, when the voltage level of Vread is raised, a high Vread is applied to the cell at the read time. Thus, there arises a problem that a miswrite occurs. Further, when it is tried to write a high level to the memory cell, a high write voltage is required. When data is collectively written to all the cells or half the cells arranged in the row direction, a high voltage is applied to a gate of a cell in a non-written state depending on the data. Thus, there is a problem that a miswrite occurs. Accordingly, within a limited range of the threshold voltage, for example, −2 V to 5 V, four threshold voltages must be set in the case of four values, eight threshold voltages must be set in the case of eight values, and sixteen threshold voltages must be set in the case of sixteen values. In order to set such threshold voltages, many program operations and verify operation must be repeated, and the write time is increased.
Thus, in order to enhance the write performance, the number of cells to which data is written at a time is increased. However, at the beginning of the program operation, all the bit lines must be charged. Further, it is also necessary to charge all the bit lines or determine a cell of a large current at the beginning of the verify/read operation. When the number of cells to which data is written at a time is increased, the number of bit lines to be charged simultaneously is also increased. Thus, in the early stage of the program operation or the verify/read operation, a very large current is required, and hence a peak current occurs. Particularly, depending on the pattern of the write data, a large peak current occurs.
Heretofore, a technique for reducing a peak current at the write time or the verify time has been developed (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-163976 or Jpn. Pat. Appln. KOKAI Publication No. 2000-276887). However, it is demanded to securely suppress the peak current regardless of the pattern of the write data.
USPTO Backgrounds
USPTO Backgrounds