The present invention relates to memory access methods for use in a unified memory system, especially, to the technology applicable to a computer system capable of performing arithmetic operations, creating video data, and presenting it on a display unit.
In conventional display and processing equipment using an unified memory, as set forth in Published Japanese Translations of PCT International Publications for Patent Application, Hei-510620 (1999), when the main storage and the image memory are integrated into a single memory, the CPU and the image memory are separated via a memory control feature called the “core logic”. A similar equipment configuration is also disclosed in U.S. Pat. No. 5,790,138.
The prior art mentioned above is merely an integrated version of main storage and display areas. In this case, access from the instruction processing unit to the unified memory uses a system controller that constitutes the instruction processing unit and the chipset, and, for this reason, the latency increases. Since this is not allowed for in the prior art, the instruction processing time tends to increase. That is to say, the prior art has poses the inherent problem that the system performance deteriorates.
USPTO Backgrounds
USPTO Backgrounds