Cathode ray tube displays are used to display video information in a variety of applications including desktop computers, televisions, and the like. While CRT displays can advantageously provide high resolution images at relatively low cost, like nearly all electronic systems, such displays generate electromagnetic interference ("EMI"). Because EMI adds signals to an already congested radio spectrum, the amount of permissible EMI is subject to applicable governmental regulations.
The EMI-radiating performance of a system may be evaluated by measuring equipment emissions within a narrow frequency reference window at individual frequencies. In the United States, applicable Federal Communications Commission regulations dictate using a 120 KHz wide (e.g., f.sub.m =120 KHz) standard reference measurement window that is swept from about 30 MHz to 1 GHz for purposes of making EMI measurement. Measurement involves a time integration of the spectral energy of the emissions occurring within the reference measurement window. The measured average emission magnitude at each frequency window is compared to published pre-specified limits, and a determination is made as to whether excessive EMI is being radiated. If excessive radiation is present, measures must be taken to bring the EMI-emitting system into compliance within acceptable emission limits.
It is known in the prior art to absorb or otherwise attenuate emitted EMI. It is also known to generate signals that have less spectral energy falling within the bandwidth of the EMI reference measurement window. These prior art techniques will now be reviewed with respect to reducing EMI in a video CRT display system.
FIG. 1 depicts a CRT display 10 and its display generator system 20, as well as several prior art techniques commonly used to reduce EMI-emissions 30 from the CRT display. CRT 10 frequently typically can display combinations of red, blue, green colors to form color images, or may in fact be a monochrome display tube.
Display generator system 20 comprises a main oscillator 40 whose frequency is normally crystal controlled and whose output signal is input to a digital timing generator 50. Timing generator 50 produces a pixel clock signal ("CLOCK") as well as horizontal and vertical synchronization signals, 60, 70 ("HSYNC", "VSYNC"). Generator 50 typically includes separate counters that count oscillator clock cycles to determine when to output the synchronization signals that clock the data signals. This technique permits consistent self-aligning of the horizontal and vertical synchronization signals 60, 70.
The horizontal synchronization signal 60 determines the length of a scanned horizontal line of video data, and the vertical synchronization signal 70 determines how many such horizontal scanned lines of data shall be displayed. Thus, the HSYNC and VSYNC synchronization signals 60, 70 allow CRT 10 to determine the horizontal and vertical size boundaries of the image that is displayed. Further, these synchronization signals permit CRT display 10 to align incoming analog video pixel data received via a data bus 80 with a particular (x, y) display location on the CRT screen. As such, all system clocking is provided by oscillator 40 and generator 50, and CRT 10 has no internal clocks or other time dependent element, and no inherent time dependencies.
Graphics generator 60 outputs a signal to video frame buffer memory unit 90, frequently referred to as video random access memory or "VRAM". As shown in FIG. 1, the horizontal and vertical synchronization signals are coupled to the video memory 90 as well as to the CRT 10. The stored or buffered graphics (e.g., pixel data) information is clocked out of memory 90, relative to the horizontal and vertical synchronization signals 60, 70, into a digital-to-analog ("D/A") converter 100. Converter 100 outputs an analog video signal that is carried by the data bus 80 to CRT 10 for display.
To preserve good integrity of the video signal, the rise and fall times of the clocked pixel data on bus 10 is typically very short, e.g., &lt;10 ns. As such, signals on bus 80 are rich in high frequency harmonics, and tend to radiate substantial EMI. The video data on bus 90 is displayed sequentially line-by-line on CRT 10, with the displayed position of each pixel being determined by the number of clock pulses from the relevant horizontal and vertical synchronization signal.
It is known in the art to provide the system of FIG. 1 with an EMI-reducing module 110 that can include one or more low pass filters 120, and/or ferrite beads or other energy absorbing components 130. Such low pass filters and energy absorbing components may be useful in reducing differential mode and common mode EMI, respectively. Low pass filter 120 may be implemented with conventional components such as operational amplifiers, resistors, capacitors, inductors. These filters typically have a cutoff frequency of about twice the relevant fundamental frequency. As such, the lowpass filters attenuate some high frequency components from the panel clock and data bus signals, and can reduce EMI to a limited degree.
But low pass filtering can only be truly effective when the EMI signals are in a differential mode, e.g., where EMI is present on the pixel clock and/or data bus signal wires, but is absent from the system ground 140. Reducing the effective impedance of the system ground return 140 will reduce the EMI voltage drop resulting from EMI signal currents. Reducing the ground impedance can be a very effective method of reducing EMI.
In some application the EMI is common mode, e.g., carried on the wire, the data bus wire(s), and also on ground. It is known in the art to reduce common mode EMI by placing energy dissipating elements such as ferrites 130 around such wires. The dissipating elements absorb the electromagnetic energy from the EMI, converting the energy into heat. The use of ferrite beads, cores, or other dissipating elements can effectively contain EMI to limited areas within an enclosure. However, the amount of EMI attenuation is relatively small, and other EMI-reducing techniques must also be used.
It is also known in the art to surround EMI-radiating equipment with a metal shield 150 that confines the radiation to the equipment. Shielding can be effective but can be costly and add to the system size. Further, effective shielding may impair system cooling, for example by reducing or eliminating ventilation openings.
FIG. 2A depicts a CRT screen raster, and demonstrates the manner of scanning an electron beam across lines (e.g., lines 1, 2, 3, . . . ) onto the phosphors of CRT 10 to display video data from bus 80. For ease of illustration, FIG. 2A depicts only 18 horizontal scan lines. However in actual display systems, the number of scan lines is substantially higher, 768 for example in a conventional computer monitor.
In so-called non-interlaced scanning system, scan line 1 is traced rapidly to the right and slightly downward by the CRT electron beam, whereupon the beam rapidly retraces horizontally right-to-left. (The horizontal retrace is shown in phantom in FIG. 2A.) Scan line 2 is then traced right and slightly downward, then a rapid right-to-left horizontal retrace. This pattern is continued until at the bottom of the CRT display, the last scan is made, whereupon the first "field" of scan lines (768 for a conventional computer monitor) is complete.
In a computer video monitor display system, the horizontal scanning rate (f.sub.horiz) is commonly a frequency within the range of about 32 KHz for lower resolution displays to about 82 KHz for high resolution workstation displays. If f.sub.horiz .apprxeq.82 KHz, then each horizontal scan will occupy about 1/82,000 second, or about 12.2 .mu.s. The vertical retrace time for computer video monitor displays typically is in the range of about 60 Hz to about 77 Hz.
Upon completion of the first field, the electron beam rapidly retraces vertically, and the next field of scan lines 1, 2, 3, . . . is traced out. When this second field of scan lines is completed, the third field is traced, and so forth. In a system where each field is scanned at a rate of 60 Hz, the vertical retrace time will be 1/60 second or 16.66 ms. (In a so-called interlaced scanning system, alternating fields of even scan lines and odd scan lines would be traced.)
During times of horizontal and vertical retrace, the scanned electron beam is inactive in that video circuitry associated with CRT 10 blanks-out the effect of the electron beam upon the phosphors of the CRT. Typically, horizonal retrace time is about 2 .mu.s, and vertical retrace time is about 300 .mu.s. During active scan times, whether portions of each scan line are light or dark (or colored), bright or dim, is determined by the voltage magnitude of the analog video signal present on video data bus 80.
FIGS. 2B and 2C depict the relationship between the video signal on data bus 80, and horizontal synchronization signal 60. In FIG. 2B, time interval T.sub.1 represents the active portion of each horizontal scan, about 12.2 .mu.s for a computer video signal having f.sub.horiz .apprxeq.82 KHz. Following the active scan, the electron beam remains at the right side of the screen for a period of time T.sub.2, known as the "front porch", a time that typically is about 0.5 .mu.s in a computer video system. Following time T.sub.2, the horizontal synchronization signal (shown in FIG. 2C) goes high for a time interval T.sub.3 (about 0.5 .mu.s for a computer video system) and then goes low again.
It is the low-to-high transition of the horizontal synchronization signal following time T.sub.2 that initiates the electron beam horizontal flyback to the left side of the CRT screen, to begin the next scan. The flyback occupies time T.sub.4 and is typically about 2 .mu.s for a computer video system. During time T.sub.4, the electron beam is still scanning from left to right, but there is no new video signal and no display is seen until the video signal begins at the end of interval T.sub.4. But if there is no new video data, the electron beam will scan existing video information across the CRT screen, which makes the video image appear to be stretched-out horizontally. By contrast, if the onset of video were delayed by N pixel clock cycles, e.g., by (T.sub.4 +N), the displayed image would appear right-shifted by N pixels.
After a number of scans corresponding to a field, the vertical synchronization signal occurs, which returns the electron beam from the screen bottom to the screen top. The vertical synchronization pulse will occur after a number of horizontal scans of video data, e.g., after about 768 scans in a typical non-interlaced computer video system.
FIG. 3 depicts the timing relationship between the main oscillator signal, a frequency divide-by-2 version of the main oscillator signal, the synchronization signal, and the video data signal for the prior art system of FIG. 1. The divide-by-2 version of the main oscillator signal is included for ease of comparison with corresponding signals for the present invention, depicted later herein as FIG. 7. It is understood that the pulse trains in FIG. 3 (and indeed FIG. 7 as well) are illustrative and that a great many more pulses are present in the actual waveforms than may be depicted in these figures.
FIG. 4A depicts the clock signal provided by timing generator 50. The clock signal typically is a periodic square wave pulse train, with a repetition frequency f.sub.c of about 100 MHz), and rise and fall transition times on the order of 1-2 ns. As shown by FIG. 4B, in most applications, the pixel data from video frame buffer 90 is clocked over the data bus 80 to CRT panel display 10 on each rising edge of the clock signal. Clocked video data may consist of a single bit or an entire word of data whose bits are clocked simultaneously. As shown, the rising edge of each panel clock signal is equidistant in time from the previous rising edge.
FIG. 4C is a frequency domain representation of the frequency spectra of the clock signal shown in FIG. 4A. As such, FIG. 4C represents the Fourier transform of the corresponding square-wave clock signal whose repetition frequency is f.sub.c. Because the clock signal has relatively fast rise and fall times, the corresponding spectral amplitude will, unfortunately, be rich in harmonics, centered about odd multiples of the base frequency f.sub.c.
Shown in phantom in FIG. 4C is the bandwidth of the reference window used for EMI-compliance testing. As shown in FIG. 4C, the amplitude of each harmonic of f.sub.c is reduced because the total electromagnetic energy represents the root-mean-square of ever smaller components.
As noted, rapid clock transition times mean that the time domain waveforms of FIG. 4A will be rich in EMI, as shown by the spectra at 1f.sub.c, 3f.sub.c, 5f.sub.c, etc. As a result, as the EMI standard reference window sweeps back and forth horizontally along the frequency axis of FIG. 4C, there will be spectral energy at relatively high harmonics of 1f.sub.c, for example, at 3f.sub.c, 5f.sub.c, etc. In FIG. 4C, in the immediate vicinity of 1f.sub.c, the reference window will capture a component of EMI having amplitude A1. In the vicinity of the third harmonic 3f.sub.c, an EMI component of amplitude A3 will be present, and so forth.
The amount of electromagnetic interference is a function of the amount of signal (e.g., EMI spectra) encompassed within the narrow reference window bandwidth f.sub.m. Interference is reduced if at least part of the interfering signal components (e.g., some EMI spectra components) are caused to fall outside the narrow bandwidth f.sub.m.
For example, it is apparent from FIG. 4C that if all frequency components higher than 1f.sub.c were removed, e.g., by an ideal low pass filter 120, relatively little EMI energy would remain within the reference window bandwidth as it sweeps higher than 1f.sub.c. Unfortunately, however, such excessive low pass filtering would slow the pixel clock and pixel data signals, compromising the ability of CRT 10 to provide a meaningful display.
Theoretically, a more sophisticated approach to reducing EMI would be to replace the crystal controlled main oscillator 40 generator with a frequency slewable clock unit. A clock whose frequency slewed sufficiently rapidly would reduce the amount of time that frequency components fell within the narrow EMI-compliance reference bandwidth. Since EMI measurements represent an integration of spectral energy over time, reducing the time that spectral components fall within the reference bandwidth will reduce their EMI contribution.
Unfortunately, the use of a slewable clock signal is not suitable for CRT video pixel clock generation because changes in the clock frequency would be visible on the CRT screen as size and position distortion.
There is a need for a technique for reducing differential mode and common mode EMI in a display system that effectively reduces EMI without significant impact upon display performance. Preferably such technique should be implementable using off-the-shelf components that do not add significantly to the cost of manufacturing a video display system. Further, such technique should not add significantly to the package size of the video display system, and should not hamper system cooling.
The present invention discloses such a technique.
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