1. Field of the invention
The present invention generally relates to a receiver and, more specifically to a diversity receiver with either time-domain or frequency-domain channel state estimation.
2. Description of the Related Art
In an orthogonal frequency division multiplexing system, there are multiple orthogonal subcarriers that are usually modulated independently. For a time-varying channel, inter-channel-interference significantly degrades the system performance and causes an error floor in bit error rate performance even when the channel is estimated and equalized.
Diversity reception is a technique that has been widely used, especially in mobile reception. Generally, a diversity receiver comprises at least two antennas and the successive signal processing to combine input signals from separate branches. The two antennas are spaced apart so as to receive different versions of a transmitted signal.
U.S. Pat. No. 6,151,372 discloses a diversity receiver, comprising two identical branches for receiving and processing input signals. There are two different circuit architectures for a diversity processing unit 120 located between Fourier transform circuits 111, 112 and parallel-serial conversion circuit 130. They are signal combining and signal selecting architectures. FIG. 1A is a diagram showing a signal combining architecture of a diversity processing unit. Referring to FIG. 1A, the diversity processing unit 120 having two propagation paths P1, P2 comprises two propagation path characteristic estimating units 121a, 121b, two complex conjugate sections 122a, 122b, two complex multipliers 123a, 123b and a combiner 124. Take the propagation path P1, for example. The propagation path characteristic estimating unit 121a estimates a channel frequency response H1(.) of the propagation path P1. The complex conjugate section 122a generates H1*(.), which is complex conjugate of the channel frequency response H1*(.). The complex multiplier 123a complex multiplies the output from the Fourier transform circuit 111 by H1*(.), which is complex conjugate generated at the complex conjugate section 122a. The combiner 124 combines the multiplication results from complex multipliers 123a, 123b to be provided to the parallel-serial conversion circuit 130.
FIG. 1B is a diagram showing a signal-selecting architecture of a diversity processing unit. The diversity processing unit comprises two propagation path characteristic estimating units 121a, 121b, a comparator 125, a selector 126. The comparator 125 provides a selection signal for selecting a signal received through a propagation path exhibiting a high amplitude based on two channel frequency responses H1(.), H2(.). According to the selection signal, the selector 126 selects a signal from outputs of the Fourier transform circuits 111, 112, and then sends the selected signal to the parallel-serial conversion circuit 130.
FIG. 2 is a block diagram of a diversity receiver according to the prior art. U.S. Pat. No. 6,792,258 describes a diversity receiver 200, comprising two antennas 201a, 201b, two tuners 202a, 202b, two demodulators 203a, 203b, two pre-processors 204a, 204b, a channel state qualified soft decision combiner 205, a Viterbi decoder 206, a post-processor 207 and a diversity controller 208. The diversity controller 208 receives the outputs from two pre-processors 204a, 204b, and the Viterbi decoder 206 for measuring the signal quality of two propagation paths P1, P2, and then dynamically programs tuners 202a, 202b. The diversity controller 208 is not only responsible for selecting two diversity sources which provide the best signals to present to tuners 202a, 202b, but also adapted to operate in one or more diversity modes in accordance with four diversity types comprising frequency diversity, antenna spatial diversity, antenna polarization diversity and antenna pattern diversity, therefore ensuring the signal quality of the diversity receiver 200.
FIG. 3 is a block diagram of another diversity receiver according to the prior art.
U.S. Patent Application No. 2002/0021773 describes another diversity receiver. Referring now to FIG. 3, a diversity receiver 300 comprises two fast Fourier transform (FFT) circuits 311, 312, two soft bit generators 301a, 301b, two channel estimators 302a, 302b, two filters 303a, 303b, a router 304 and a combiner 124. The diversity receiver 300 has two identical branches 310, 320, which are functionally equivalent. As for the branch 310, the channel estimator 302a generates and applies channel estimates (e.g. channel frequency response H1(.)) to both the soft bit generator 301a and the filter 303a for improving the channel distortion and increasing the stability of channel estimates. The router 304 receives two output values from two filters 303a, 303b to compare the signal qualities of two branches 310, 320 and then decides whether to route one or both of the signals from branches 310, 320. Next, the combiner 124 performs signal combining or signal selecting operations according to the output signal from the router 304. Wherein, the router 304 uses two signal combining methods. They are maximal ratio combining (MRC) and equal gain combining (EGC).
However, the previously discussed three diversity receivers merely refers to the channel frequency response estimate H(.) before signal combining is performed, thus revealing unqualified signal quality under some channel environments. The diversity receiver of the invention fully utilizes all the channel information available to derive all related parameters required for diversity combining, therefore enhancing the quality and stability of signal for combining.
USPTO Backgrounds
USPTO Backgrounds