FIG. 31 shows a conventional configuration of a gate driver whose scanning direction is switchable. The gate deriver includes an INITB (inversion initialization signal) line, a GCK1B (first inverted gate clock) line, a GCK2B (second inverted gate clock) line, A UD (shift direction signal) line, a UDB (inverted shift direction signal) line, and a shift register 100 (conventional shift register) constituted by unit circuits of first to mth stages (m is an integer of 2 or greater). The INITB (inversion initialization signal) is “Low” when it is in an active state.
For example, a unit circuit Cn of the nth stage (n is an integer of 2 or greater) includes a flip-flop fn, two analog switches SWn and swn, an inverter IBn, and a driving terminal Un serving as a connection terminal for connection with a scanning signal line. The flip-flop fn has A to D terminals and X and Y terminals which serve as input terminals, and has a Q terminal (output terminal) and a QB terminal (inverting output terminal) which serve as output terminals. Each of the analog switches SWn and SWn is a CMOS switch constituted by a single P channel transistor and a single N channel transistor, and has a P terminal which is a gate terminal of the P channel transistor, an N terminal which is a gate terminal of the N channel transistor, and two conducting terminals.
The unit circuit Cn is configured such that: the Q terminal of the flip-flop fn, the N terminal of the analog switch SWn, and the P terminal of the analog switch swn are connected with one another; the QB terminal of the flip-flop fn, the P terminal of the analog switch SWn, and the N terminal of the analog switch swn are connected with one another; one of the conducting terminals of the analog switch SWn, one of the conducting terminals of the analog switch swn, and an input terminal of the inverter IBn are connected with one another; an output terminal of the inverter IBn is connected with the driving terminal Un; the other of the conducting terminals of the analog switch swn is connected with the INITB line; and the other of the conducting terminals of the analog switch SWn is connected with the GCK2B line.
The A terminal of the flip-flop fn is connected with a driving terminal Un−1 of a previous stage Cn−1, the B terminal of the flip-flop fn is connected with an input terminal of an inverter IBn−1 of the previous stage Cn−1, the C terminal of the flip-flop fn is connected with a driving terminal Un+1 of a subsequent stage Cn+1, the D terminal of the flip-flop fn is connected with an input terminal of an inverter IBn+1 of the subsequent stage Cn−1, the X terminal of the flip-flop fn is connected with the UD line, and the Y terminal of the flip-flop fn is connected with the UDB line.
FIG. 32 shows a specific circuit configuration of the flip-flop fn. As illustrated in FIG. 32, the flip-flop fn includes four analog switches 71 to 74 (each of which has the same configuration as in the analog switch SWn), a P channel transistor 78, an N channel transistor 79, and two inverters 75 and 76. The flip-flop fn is configured such that: the B terminal is connected with a gate terminal of the transistor 78 via the analog switch 71; the D terminal is connected with the gate terminal of the transistor 78 via the analog switch 72; the A terminal is connected with a gate terminal of the transistor 79 via the analog switch 73; the C terminal is connected with the gate terminal of the transistor 79 via the analog switch 74; an N terminal of the analog switch 71, a P terminal of the analog switch 72, a P terminal of the analog switch 73, an N terminal of the analog switch 74, and the X terminal are connected to one another; a P terminal of the analog switch 71, a P terminal of the analog switch 74, and the Y terminal are connected with one another; a source terminal of the transistor 78 is connected with a high-voltage power supply VDD; and a source terminal of the transistor 79 is connected with a low-voltage power supply VSS. Further, a drain terminal of the transistor 78, a drain terminal of the transistor 79, an input terminal of the inverter 75, and an output terminal of the inverter 76, and the Q terminal are connected with one another. An output terminal of the inverter 75, an input terminal of the inverter 76, and the QB terminal are connected with one another. The inverters 75 and 76 constitute a latch circuit.
FIG. 33 is a timing chart showing operations of the gate driver shown in FIG. 31. In FIG. 33, the UD is “High” (hereinafter referred to as “H” for short) and the UDB is “Low” (hereinafter referred to as “L” for short). Therefore, the analog switches 72 and 73 are in an OFF state, and the analog switches 71 and 74 are in an ON state. When On−1 becomes “H” while On+1 is “L” at t0, the B terminal is “L” and the C terminal is also “L”. This updates the latch circuit, and the Q terminal becomes “H” and the QB terminal becomes “L”. This turns ON the analog switch SWn and turns OFF the analog switch swn. From this point in time, an inverted version (GCK2) of the GCK2B is outputted as On. That is, the On rises to “H” at t2, and falls to “L” at t3.
When On+1 becomes “H” while On−1 is “L” at t4, the B terminal is “H” and the C terminal also is “H”. This updates the latch circuit, and the Q terminal becomes “L” and the QB terminal becomes “H”. This turns OFF the analog switch SWn and turns ON the analog switch swn. From this point in time, an inverted version of the INITB is outputted as On. That is, the On is “L” at and after the t4. As described above, according to FIG. 33, On−1, On, and On+1 become active “H” in this order, thereby enabling forward scanning. Note that, in FIG. 34, since the UD is “L” and the UDB is “H”, On+1, On, and On−1 become active “H” in this order, thereby enables reverse scanning.
USPTO Backgrounds
USPTO Backgrounds