1. Field of the Invention
The present invention relates to a method for leading a power line in a field of a semiconductor device using a semiconductor element.
2. Description of the Related Art
A driver circuit such as a source driver or a gate driver constituting a display device includes a logic circuit (hereinafter referred to as a logic portion) which sequentially outputs pulses according to desired timing and performs arithmetic processing such as capture of data, such as a shift resister circuit or a latch circuit, and a circuit (hereinafter referred to as a buffer portion) which amplifies signal amplitude such as a buffer circuit or a level shifter circuit.
Such a driver circuit has been developed as a control portion in a display device having a liquid crystal element (hereinafter referred to as a liquid crystal display device) or a display device having a self-luminous element (hereinafter referred to as a light emitting device).
Conventionally, a power line supplying the same potential to a logic portion and a buffer portion is shared by the logic portion and the buffer portion, and the potential is applied to a necessary part in the logic portion and the buffer portion by the same wiring. In particular, a power line for supplying a ground potential is usually shared by a logic portion and a buffer portion. By sharing a wiring in this way, an area occupied by the wiring can be decreased, and a frame of a display device is narrowed.
As shown in FIG. 6, conventionally, a power line 601 supplying the same potential to a logic portion 105 and a buffer portion 108 is led from one FPC (flexible printed circuit) terminal 600 for power, so that the logic portion 105 and the buffer portion 108 share the power line 601 led from the FPC terminal 600 for power up to near the logic portion and the buffer portion. This is because leading of the power line is easy and a space for layout can be small when the power line is shared up to near the circuit portions.
However, when the FPC terminal 600 for power and the power line 601 led from the FPC terminal 600 for power are shared by the logic portion 105 and the buffer portion 108, there is a possibility that an instantaneous high-current consumed by the buffer portion 108 at the time of writing into a pixel causes a voltage drop of the power line 601, and noise is generated, which leads to malfunction of the logic portion 105 affected by the noise.
This results from the fact that the logic portion which is a circuit for outputting a pulse consumes less current compared to the buffer portion, and the buffer portion which amplifies signal amplitude consumes more current compared to the logic portion.
In a case of a source driver, the above-described problem is more serious, since a source driver operates faster than a gate driver and has a higher load than a gate driver. In a source driver, an instantaneous high-current is consumed at the time of data writing, and the larger a current value is, the larger a voltage drop of a power line becomes. Therefore, when a logic portion and a buffer portion of the source driver share the power line, there is a high possibility that the logic portion is affected by noise generated due to a voltage drop of the power line of the buffer portion, and that the logic portion malfunctions.
In addition, particularly in a case of line-sequential driving, the above-described problem is serious, since a source driver writes data for one line at a time in a case of the line-sequential driving. Therefore, when a logic portion and a buffer portion of a source driver performing line-sequential driving share the power line, there is a high possibility that the logic portion is largely affected by noise generated due to a voltage drop of the power line of the buffer portion, and that the logic portion malfunctions.
As is clear from Ohm's law, a voltage drop is expressed by V=IR. V [V] represents a voltage (a value of a voltage drop); I [A], a current; and R [Ω], resistance. In this case, R [Ω] is wiring resistance and the value thereof is the same in the logic portion and the buffer portion, but I [A] is different between the logic portion and the buffer portion. For example, a low potential side of a power line which is led from an FPC terminal for power and connected to each of the logic portion and the buffer portion is set to be the same, and different potentials are applied to the logic portion and the buffer portion for a high potential side. Generally, high output amplitude is necessary in a buffer portion, so that a potential to be applied to the buffer portion is set to be higher than the logic portion, and output load capacitance of the buffer portion is higher than the logic portion.
Therefore, a large voltage drop can occur in the power line in the buffer portion where an instantaneous high-current is consumed. At this time, in a case where the logic portion and the buffer portion share the power line supplying the same potential, there is a possibility that the logic portion is affected by noise generated due to a large voltage drop of the power line of the buffer portion, and accurate data is not captured when capturing data; thus causing a problem such as a display defect.
USPTO Backgrounds
USPTO Backgrounds