The present disclosure relates to semiconductor structures and, more specifically, to semiconductor structures comprising at least one field effect transistor (FET) having a low-resistance source/drain contact and methods of forming these semiconductor structures.
Integrated circuit design decisions are often driven by device scalability, device density, manufacturing efficiency and costs. In semiconductor structures comprising field effect transistors (FETs), such as planar FETs or multi-gate non-planar FETs (e.g., fin-type FETs (FINFETs), also referred to herein as a dual gate FETs, and tri-gate FETs), size scaling reduces the width of contacts and, thereby increases contact resistance. Size scaling also reduces the separation distances between source/drain contacts and gates and, thereby increases gate-to-source/drain contact capacitance. Increases in the source/drain contact resistance and in the gate-to-source/drain contact capacitance can negatively impact device performance. Therefore, there is a need in the art for improved semiconductor structures and methods of forming these structures with one or more field effect transistors each having a source/drain contact with relatively low resistance and/or having relatively low gate-to-source/drain contact capacitance in order to optimize device performance.
USPTO Backgrounds
USPTO Backgrounds