A fundamental building block of integrated circuit-configured signal processing architectures is the constant current-biased, differentially coupled, transistor pair, diagrammatically illustrated in FIG. 1 as comprising first and second bipolar transistors 11 and 21, the emitters 12 and 22 of which are coupled to a constant bias current source 30 and the bases 13, 23 of which are coupled across an input voltage source 40. Collectors 14, 24 are coupled to a collector bias voltage (not shown) and respectively couple a first collector current Il and a second collector current 12 in accordance with the following simplified expressions (1) and (2). Specifically, EQU I1=Ic/(1+(A2/A1)exp(-V40/VT)) (1) EQU and EQU I2=Ic(1-1/(1+(A2/A1)exp(-V40/VT)) (2)
where A1 and A2 are the emitter areas of transistors 11 and 12, respectively. VT=KT/q
As can be seen from expressions (1) and (2), if the differential input voltage V40&gt;&gt;KT/q, I1 approaches Ic and I2 approaches zero. Conversely, if V40&lt;&lt;-KT/q, then Il approaches zero and I2 approaches Ic. In other words, when the differential input voltage lies outside these limits, one of transistors 11 or 21 will be conducting, while the other will not. This imbalance in current flow causes a relative change in temperature due to the difference in power dissipation. (Assuming matched devices), when both transistors are at the same temperature and the differential input voltage drops to zero, each of I1 and I2=Ic/2. However, if there is a difference in temperature of the two transistors, their collector currents will differ when the differential input voltage drops to zero. Because the bias current Ic is fixed, there exists an inherent differential power and temperature problem that relaxes only for prescribed sets of conditions.
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