The present disclosure relates to a metal interconnect structure, and particularly to a metal interconnect structure including a borderless interconnect line structure that is self-aligned to upper and lower metal contact vias, and methods of manufacturing the same.
Lithographic capabilities are one of the significant technological limitations that constrain the continued scaling of semiconductor devices. Lithographic capabilities limit the scaling in two ways. First, the feature size that can be lithographically defined in a single lithographic exposure and development is limited to a minimum dimension that a lithography tool can print, which is typically called a critical dimension. Even with the most advanced lithography tools, the critical dimension achievable as of 2010 is about 30 nm. In other words, dimensions less than 30 nm cannot be printed through conventional lithography techniques.
Second, overlay variations inherent in any alignment process that lithographically defines a new pattern in spatial registry with an existing pattern causes misalignment between existing elements and newly formed elements. The effect of such overly variations can be illustrated with a prior art metal interconnect structure such as the structure shown in FIG. 1 and formed by conventional methods. Mx level metal lines and V(x−1) level metal vias can be formed in a dielectric material layer by employing a first lithographic exposure that defines the location of the V(x−1) level metal vias and a second lithographic exposure that defines the location of the Mx level metal lines followed by appropriate etch processing steps, a metal deposition step, and a planarization step. The ideal interline spacings between an adjacent pair of Mx level metal lines can be effectively reduced by a finite overly variation between the V(x−1) level metal vias and the Mx level metal lines. Specifically, if a lateral protrusion of a V(x−1) level metal via is δ1, the effective spacing between a metal line including a V(x−1) level metal via and an adjacent metal line can be s−δ1. Likewise, the ideal interline spacing s between an adjacent pair of Mx level metal lines can also be effectively reduced by a finite overly variation between Vx level metal vias and the Mx level metal lines. Specifically, if a lateral protrusion of a Vx level metal via is δ2, the effective spacing between a metal line including a Vx level metal via and an adjacent metal line can be s−δ2.
Such misalignments between a metal line and a metal via in the level directly below the metal line and between the metal line and a metal via in the level directly above the metal line can cause direct electrical short, or can cause a reliability failure through time dependent dielectric breakdown (TDDB). In a TDDB failure, the electrical isolation of a dielectric material portion between two conductive elements deteriorates in time due to at least one mechanism such as electromigration, impurity penetration, or material degradation so that a conductive path is formed between the two conductive elements in time. In order to prevent outright electrical shorts and TDDB failures, therefore, it is necessary to maximize the effective lateral spacing between adjacent metal lines while allowing sufficient electrical contact between the metal lines and the contact vias located above and below.
USPTO Backgrounds
USPTO Backgrounds