1. Field of the Invention
The present invention relates to a display apparatus for inputting digital video signals and for displaying pictures. The display apparatus includes a liquid crystal display apparatus using liquid crystal elements as pixels and a display apparatus using light-emitting elements such as electroluminescence (EL) elements.
The present invention also relates to an electric circuit and, in particular, to a latch circuit for holding data.
2. Description of the Related Art
Recently, an active matrix type display apparatus is used in many products and is widely spread. The active matrix type display apparatus includes a display apparatus including a semiconductor thin film on an insulator such as a glass substrate and, especially, a liquid crystal display (LCD) using thin film transistors (called TFT, hereinafter). The active matrix type display device has several hundred thousands to several millions of pixels provided on matrix. The brightness of pixels is controlled by TFT's provided in pixels so as to display pictures.
Furthermore, recently, a technology has developed for forming pixels and peripheral circuits integrally on a same substrate by using polysilicon TFT's. This kind of technologies greatly contributes to the reduction in display apparatus size and in power consumption. Recently, the mobile information terminals expand the application field significantly. The display apparatus is required as a display portion of each of the mobile information terminals.
FIG. 2 shows a conventional example (conventional data latch) of a circuit for capturing and holding video data sequentially by using pulses from a shift register. The circuit includes a first clocked inverter 1000, an inverter 1010 and a second clocked inverter 1020. The first clocked inverter 1000 has four TFT's including P-type TFT's 1001 and 1002 and N-type TFT's 1003 and 1004. In FIG. 2, the second clocked inverter 1020 is indicated by a generally used circuit symbol. The construction of the second clocked inverter 1020 is the same as that of the first clocked inverter 1000 shown in FIG. 2. A latch signal (LAT) is input to a gate electrode of the P-type TFT 1001. A high potential power supply (VDD) is connected to a source electrode of the P-type TFT 1001. A source electrode of the P-type TFT 1002 is connected to a drain electrode of the P-type TFT 1001. A data signal (DATA) is input to a gate electrode of the P-type TFT 1002. An output terminal (OUTPUT) of the first clocked inverter 1000 is connected to the drain electrode of the P-type TFT 1002.
On the other hand, an inverse latch signal (LATB) is input to a gate electrode of the N-type TFT 1004. A low potential power supply (VSS) is connected to a source electrode of the N-type TFT 1004. One of a source electrode and drain electrode of the N-type TFT 1003 is connected to a drain electrode of the N-type TFT 1004 on the other hand. A data signal (DATA) is input to a gate electrode of the N-type TFT 1003. An output terminal (OUTPUT) of the first clocked inverter 1000 is connected to a drain electrode of the N-type TFT 1003.
An input terminal of the inverter 1010 is connected to an output terminal (OUTPUT) of the first clocked inverter 1000. An input terminal of the second clocked inverter 1020 is connected to an output terminal of the inverter 1010. An output terminal (OUTPUT) of the first clocked inverter 1000 is connected to an output terminal of the second clocked inverter 1020. A latch signal and the inverse signal (not shown) are connected to the second clocked inverter.
Details of an operation of the circuit shown in FIG. 2 will be described. A digital circuit is used herein. Therefore, input and output potentials are expressed in binary of HIGH and LOW, respectively. Signal potentials of a data signal (DATA), a latch signal (LAT) and an inverse latch signal (LATB) to be input to the circuit are usually the same as the power supply potential of the circuit (HIGH and LOW potentials of input and output potentials are VDD and VSS, respectively). However, the HIGH/LOW potentials do not have to be always the same as the power supply potential (VDD/VSS). The HIGH/LOW potentials may be the same as the power supply potential (VDD/VSS) when they are dealt in binary. For example, the HIGH potential includes a potential lower than VDD and is reduced by the N-type transistor by a threshold value. Potentials, which can return to VDD/VSS by using an amplitude compensating circuit or the like, can be the same HIGH/LOW potential.
An operation will be described where a latch signal (LAT) is LOW while an inverse latch signal (LATB) is HIGH. Here, the P-type TFT 1001 and the N-type TFT 1004 are turned ON. Therefore, VDD is output from the drain electrode of the P-type TFT 1001. VSS is output from the drain electrode of the N-type TFT 1004.
A Data signal (DATA) is input to the gate electrodes of the P-type TFT 1002 and the N-type TFT 1003. Here, when an input potential of the data signal (DATA) is HIGH, the N-type TFT 1003 of the P-type TFT 1002 and the N-type TFT 1003 is turned ON. Therefore, VSS is output to the output terminal (OUTPUT).
On the other hand, when an input potential of the data signal (DATA) is LOW, the P-type TFT 1002 of the P-type TFT 1002 and the N-type TFT 1003 is turned ON. Therefore, VDD is output to the output terminal (OUTPUT).
Here, when a latch signal (LAT) is LOW and an inverse latch signal (LATB) is HIGH, the second clocked inverter 1020 is in a high-impedance state. Therefore, the output of the second clocked inverter 1020 does not conflict with the output of the first clocked inverter 1000.
Next, an operation will be described when a latch signal (LAT) is HIGH and an inverse latch signal (LATB) is LOW. Here, the P-type TFT 1001 and the N-type TFT 1004 are turned OFF. Then, the first clocked inverter 1000 enters into the high-impedance state. The second clocked inverter 1020 functions as an inverter and establishes a loop together with the inverter 1010. Thus, a video signal is captured and is held when a latch signal (LAT) is LOW.
A power supply potential of a TFT circuit needs to be generally about 10 V. On the other hand, a controller IC for generating a data signal outside of the panel operates at a power supply potential lower than that of the TFT circuit. Therefore, the controller IC generally generates signals at a voltage of 3.3 V. When a signal is generated at the low voltage and is input to the TFT circuit as shown in FIG. 2, a level-shift circuit outside or inside of the panel raises the voltage to about 10 V. Then, the signal at 10 V is input to the circuit in FIG. 2. When the voltage is level-shifted outside of the panel, the number of parts of the level-shift IC, the power supply IC and the like are increased. Furthermore, the power consumption is increased. When the voltage is level-shifted inside of the panel, the size of the layout area, power consumption and difficulty in high frequency operation are increased disadvantageously.
The signal at 3.3 V may be directly input to the circuit in FIG. 2 without being level-shifted. However, problems may occur as described below.
For example, the circuit in FIG. 2 may operate at VSS of 0V, VDD of 9V, and LOW and HIGH potentials of data signals (DATA) of 3V and 6V, respectively. Also, HIGH and LOW potentials of the latch signal (LAT) and the inverse latch signal (LATB) are 9V and 0V, respectively. In this case, the HIGH potential is the same as the power supply potential. The threshold values of all of the N-type TFT's are 2V. The threshold values of the P-type TFT's are −2V.
Here, when the latch signal (LAT) is the LOW potential and the inverse latch signal (LATB) is the HIGH potential, the P-type TFT 1001 and the N-type TFT 1004 are completely turned ON. The potential of one of the source electrode and the drain electrode of the P-type TFT 1001 is 9V. The potential of one of the source electrode and drain electrode of the N-type TFT 1004 is 0V. Here, when a data signal (DATA) at the HIGH potential (6V) is input, the N-type TFT 1003 is turned ON. Because the input voltage is low, the P-type TFT 1002 does not enter into the OFF region operation and is therefore turned ON. However, differences between the gate-source voltages of the P-type TFT 1002 and the N-type TFT 1003 and the threshold value are −1V and 4V, respectively. Generally, a current ability of the P-type TFT and a current ability of the N-type TFT are calculated from the mobility and the size of the TFT's. Therefore, the current abilities of the P-type TFT and N-type TFT are designed substantially equal. In this case, the N-type TFT 1003 has a larger absolute value of the difference between the gate-source voltage and the threshold value. Therefore, the N-type TFT 1003 has lower effective resistance than that of the P-type TFT 1002. As a result, a value near 0V is expected from the output terminal (OUTPUT). In this case, a proper operation may be performed logically. However, the P-type TFT 1002 is expected to turn OFF but is turned ON. Therefore, flow-through current flows between the power supplies VDD to VSS. As a result, the current consumption is increased disadvantageously.
The proper operation may not be performed disadvantageously in a following case. For example, a threshold value of the N-type TFT is 5 V and a threshold value of the P-type TFT is −1 V. The latch signal (LAT) is at LOW potential while the inverse latch signal (LATB) is at HIGH potential. In this case, as described above, the P-type TFT 1001 and the N-type TFT 1004 are completely turned ON. The potential of the output electrode of the P-type TFT 1001 is 9V. The potential of the output electrode of the N-type TFT 1004 is 0V. When a data signal (DATA) at the HIGH potential (6V) is input, the difference between the gate-source voltage of the P-type TFT 1002 and the threshold value is −2V. The difference between the gate-source voltage of the N-type TFT 1003 and the threshold value is 1V. When βP=βN, the P-type TFT 1002 has a large absolute value for the difference between the gate-source voltage and the threshold value. Therefore, the P-type TFT 1002 has effectively lower resistance than that of the N-type TFT 1003. As a result, VDD is output from the output for the HIGH data input. Therefore, the proper operation may not be performed.
The threshold values of TFT's may vary in accordance with the process of producing the TFT's. Therefore, when a signal at a lower voltage than the power supply potential is directly input to the circuit in FIG. 2, the threshold values of the opposing P-type TFT 1002 and N-type TFT 1003 may be largely different from a predetermined value. In this case, the operation may not be performed properly.
USPTO Backgrounds
USPTO Backgrounds