1. Field of the Invention
This invention generally relates to methods and systems for semiconductor fabrication processes. Certain embodiments relate to a method and a system for evaluating and/or controlling a semiconductor fabrication process by determining at least two properties of a specimen.
2. Description of the Related Art
Fabrication of semiconductor devices such as logic and memory devices typically includes a number of processes that may be used to form various features and multiple levels or layers of semiconductor devices on a surface of a semiconductor wafer or another appropriate substrate. For example, lithography is a process that typically involves transferring a pattern to a resist arranged on a surface of a semiconductor wafer. Additional examples of semiconductor fabrication processes may include chemical-mechanical polishing, etch, deposition, ion implantation, plating, and cleaning. Semiconductor devices are significantly smaller than a typical semiconductor wafer or substrate, and an array of semiconductor devices may be formed on a semiconductor wafer. After processing is complete, the semiconductor wafer may be separated into individual semiconductor devices.
Semiconductor fabrication processes, however, are among the most sophisticated and complex processes used in manufacturing. In order to perform efficiently, semiconductor fabrication processes may require frequent monitoring and careful evaluation. For example, semiconductor fabrication processes may introduce a number of defects (e.g., non-uniformities) into a semiconductor device. As an example, defects may include contamination introduced to a wafer during a semiconductor fabrication process by particles in process chemicals and/or in a clean room environment. Such defects may adversely affect the performance of the process to an extent that overall yield of the fabrication process may be reduced below acceptable levels. Therefore, extensive monitoring and evaluation of semiconductor fabrication processes may typically be performed to ensure that the process is within design tolerance and to increase the overall yield of the process. Ideally, extensive monitoring and evaluation of the process may take place both during process development and during process control of semiconductor fabrication processes.
As features sizes of semiconductor devices continue to shrink, a minimum feature size that may be fabricated may often be limited by the performance characteristics of a semiconductor fabrication process. Examples of performance characteristics of a semiconductor fabrication process include, but are not limited to, resolution capability, across chip variations, and across wafer variations. In optical lithography, for example, performance characteristics such as resolution capability of a lithography process may be limited by the quality of the resist application, the performance of the resist material, the performance of the exposure tool, and the wavelength of light used to expose the resist. The ability to resolve a minimum feature size, however, may also be strongly dependent on other critical parameters of the lithography process such as a temperature of a post exposure bake process and an exposure dose of an exposure process. As such, controlling the parameters of processes that may be critical to the resolution capability of a semiconductor fabrication process such as a lithography process is becoming increasingly important to the successful fabrication of semiconductor devices.
As the dimensions of semiconductor devices continue to shrink with advances in semiconductor materials and processes, the ability to examine microscopic features and to detect microscopic defects has also become increasingly important to the successful fabrication of semiconductor devices. Significant research has been focused on increasing the resolution limit of metrology and/or inspection tools used to examine microscopic features and defects. There are several disadvantages, however, in using the currently available methods and systems for metrology and/or inspection of specimens fabricated by semiconductor fabrication processes. For example, multiple stand-alone metrology/inspection systems may be used for metrology and/or inspection of specimens fabricated by such processes. As used herein, “stand-alone metrology/inspection system” may generally refer a system that is not coupled to a process tool and is operated independently of any other process tools and/or metrology/inspection systems. Multiple metrology/inspection systems, however, may occupy a relatively large amount of clean room space due to the footprints of each of the metrology and/or inspection systems.
In addition, testing time and process delays associated with measuring and/or inspecting a specimen with multiple metrology/inspection systems may increase the overall cost of manufacturing and the manufacturing time for fabricating a semiconductor device. For example, process tools may often be idle while metrology and/or inspection of a specimen is performed such that the process may be evaluated before additional specimens are processed thereby increasing manufacturing delays. Furthermore, if processing problems can not be detected before additional wafers have been processed, wafers processed during this time may need to be scrapped, which increases the overall cost of manufacturing. Additionally, buying multiple metrology/inspection systems increases the cost of fabrication.
In an additional example, for in situ metrology and/or inspection using multiple currently available systems, determining a characteristic of a specimen during a process may be difficult if not impossible. For example, measuring and/or inspecting a specimen with multiple currently available systems during a lithography process may introduce a delay time between or after process steps of the process. If the delay time is relatively long, the performance of the resist may be adversely affected, and the overall yield of semiconductor devices may be reduced. As such, there may also be limitations on process enhancement, control, and yield of semiconductor fabrication processes due to the limitations associated with metrology and/or inspection using multiple currently available systems. Process enhancement, control, and yield may also be limited by an increased potential for contamination associated with metrology and/or inspection using multiple currently available metrology/inspection systems. In addition, there may be practical limits to using multiple metrology/inspection systems in semiconductor manufacturing processes. In an example, for in situ metrology and/or inspection using multiple currently available systems, integrating multiple metrology/inspection systems into a process tool or a cluster tool may be difficult due to the availability of space within the tool.
USPTO Backgrounds
USPTO Backgrounds