Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls.
Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. A UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Recently, copper interconnect post technology is proposed. Instead of using solder bump, the electronic component is connected to a substrate by means of copper post. The copper interconnect post technology achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits and allows the electronic component to perform at higher frequencies. A solder alloy is still necessary for capping the bump structure and jointing electronic components as well.
The physical stresses in WLCSP and related flip-chip packages depend upon a combination of several factors, such as device size, architecture, and operating conditions, as well as the actual package design and materials of construction. However, the use of low-k materials makes a critical issue of the stress imposed on the device by the package. Also, the introduction of Cu post induces a higher stress than solder bump does, which requires a stress buffer or re-distribution layer. Polyimide (PI) can act a stress buffer to reduce the maximum stress at the low-k dielectric layer under the metal bump region, but adversely impacts the device performance. For example, the PI layer needs a high-temperature and long-time curing process, which causes a large volume PI shrinkage to induce a great residual stress to silicon. The common failure mode is delamination or cracking around the die corner or the interface between the PI layer and an underfill material.
USPTO Backgrounds
USPTO Backgrounds