Semiconductor devices are fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon. A common conductive material used in the past for conductive lines was aluminum, which can be directly etched. For example, a layer of aluminum or aluminum alloy is deposited, a photoresist layer is deposited over the aluminum, the photoresist is patterned and developed, and the photoresist is used as a mask while exposed areas of the aluminum layer are etched away.
There is a trend in the semiconductor industry towards the use of copper for conductive lines and metallization layers. Copper introduces new challenges in semiconductor device fabrication. While copper is more conductive than aluminum, which is an advantage, it has a tendency to diffuse through dielectric layers, causing shorts and device failures. Therefore, liners are used to prevent this diffusion. Also, copper cannot be directly etched, particularly in small minimum feature sizes, which leads to the use of damascene methods to form copper conductive lines.
In a damascene method of forming conductive lines, an insulating layer is deposited over a semiconductor substrate, and the insulating layer is patterned, e.g. by depositing a photoresist, patterning and developing the photoresist, and using the photoresist as a mask for the insulating layer while exposed portions of the insulating layer are etched away. A conductive material (such as copper) is deposited over the patterned insulating layer, e.g. by chemical vapor deposition (CVD), electroplating or electro-less plating, or other deposition methods. The semiconductor substrate is chemically-mechanically polished (CMP) to remove excess conductive material from over the top surface of the insulating layer, leaving conductive lines or regions formed in the insulating layer.
If one pattern is formed in the insulating layer, the process is referred to as a single damascene process. However, two patterns may also be formed in the insulating layer, with one pattern typically being etched deeper into the insulating layer than the other pattern. The two pattern process is referred to in the art as a dual damascene process. A dual damascene process may be used to form a first layer of vias to connect to underlying conductive lines or elements, for example, and a second layer of conductive lines or regions may be formed over the vias.
In the prior art, typically either the vias are first patterned in the insulating layer through the entire thickness of the insulating layer, and then the conductive lines are patterned in a top portion of the insulating layer, often referred to as a “via-first” dual damascene patterning method. Or, the conductive lines may alternatively be patterned in a top portion of the insulating layer first, followed by the patterning of the vias through the entire thickness of the insulating layer, called a “line-first” dual damascene method.
As semiconductor device sizes decrease and the minimum feature size of the electrical components and conductive lines decrease, patterning an insulating layer in a dual damascene process becomes more and more difficult. In a dual damascene patterning process, one of the patterning steps etches through the entire thickness of the insulating layer (forming the vias, for example), and the other patterning step etches only through part of the insulating layer (forming the conductive lines), using a timed etch, for example. There is a trend in the semiconductor industry towards the use of low-dielectric constant (low-k) dielectric materials, particularly used in conjunction with copper conductive lines, to reduce the RC time delay of the conductive lines. Some low-k dielectric materials are porous and/or etch very quickly, and it can be difficult to adequately control the etch process, particularly in a dual damascene structure and process.
Another problem in dual damascene patterning is photoresist poisoning, which can occur during a patterning process when etch chemistries containing nitrogen are used to pattern insulating layers comprising SiCOH-type (materials containing silicon, carbon, oxygen, and/or hydrogen) materials, which are often used as insulators. The nitrogen-containing etch chemistries, in conjunction with the SiCOH-type materials, liberate amines that can interact with or migrate into the photoresist during a subsequent lithography step. Photoresist poisoning causes depth of focus problems and/or delamination of the photoresist, resulting in loss of control of the critical dimensions and the inability to print, which leads to device failures and decreased yields. Photoresist poisoning tends to be a problem in via-first dual damascene patterning methods and also in line-first dual damascene patterning methods because the subsequent application of photoresist is exposed to the amines generated during the previous etch process.
Therefore, what is needed in the art is a dual damascene structure and method with improved control of patterning a damascene structure that avoids photoresist poisoning.
USPTO Backgrounds
USPTO Backgrounds