The present invention relates to a buffer circuit for generating signals of the same and opposite polarities with respect to that of the input signal.
Hitherto, in the case of obtaining two output signals having different polarities, for example, as shown in FIG. 1, a buffer circuit using two CMOS inverter circuits is used. Namely, an input signal D.sub.in is supplied to and inverted by a first inverter circuit 11 from which, an output D.sub.out is generated as a first signal, and the output of inverter circuit 11 is inverted by a second inverter circuit 12, thereby causing an output D.sub.out of the same polarity as input signal D.sub.in to be generated as a second signal.
Suppose that inverter circuits 11 and 12 are constituted by CMOS circuits and the transfer delay times by inverter circuits 11 and 12 respectively assume t.sub.pdA and t.sub.pdB. Then, delay times 66 D.sub.out and .DELTA.D.sub.out of output signals D.sub.out and D.sub.out for input signal D.sub.in will become equal to t.sub.pdA and (t.sub.pdA +t.sub.pdB), respectively. Therefore, there is a drawback that the time difference equal to transfer delay time t.sub.pdB due to the presence of inverter circuit 12 occurs between output signals D.sub.out and D.sub.out.
As mentioned above, the time difference corresponding to the delay time of the CMOS inverter circuit of the post stage occurs between the outputs of both polarities in the conventional CMOS buffer circuits to obtain the outputs of both polarities.
USPTO Backgrounds
USPTO Backgrounds