1. Field of the Invention
The present invention relates to a Charge Coupled Device (CCD) type solid-state imaging device and a Metal Oxide Semiconductor (MOS) type solid-state imaging device.
2. Description of the Related Art
In recent years, there is an increasing demand for a solid-state imaging device as an imaging device for use in digital still cameras and digital camcorders. Also, mobile terminal devices, such as a mobile telephone and the like, are expected to additionally have a camera function. Therefore, there is also an increasing demand for a solid-state imaging device as an imaging device for use in such mobile terminal devices. The number of pixels of a solid-state imaging device tends to increase year after year to achieve higher-quality images. The solid-state imaging device is also desired to have a higher sensitivity and a higher S/N ratio so as to respond to a request for an increase in sensitivity of digital still cameras, digital camcorders, and mobile terminal devices.
Here, a structure common to conventional CCD solid-state imaging devices and conventional MOS solid-state imaging devices will be described with reference to FIG. 12 and FIGS. 13A and 13B.
FIG. 12 is a plan view showing a schematic structure of a conventional solid-state imaging device.
As shown in FIG. 12, an internal circuit region 101 having a light receiving portion and a drive circuit portion is provided at a middle portion of a semiconductor substrate 100, and a peripheral circuit region 102 having a pad portion and a protective circuit portion is provided at a peripheral portion of the semiconductor substrate 100. The internal circuit region 101 and the peripheral circuit region 102 are connected to each other via a wiring line L.
FIGS. 13A and 13B are diagrams showing a structure of a region a of FIG. 12 that is a main portion the conventional solid-state imaging device. Specifically, FIG. 13A is a plan view taken along line XIIIa-XIIIa of FIG. 13B, and FIG. 13B is a cross-sectional view taken along XIIIb-XIIIb of FIG. 13A.
As shown in FIGS. 13A and 13B, a P-type semiconductor layer 112 is formed in a semiconductor substrate 111 made of N-type silicon, and an N+-type semiconductor layer 113 is formed in a surface layer portion of the P-type semiconductor layer 112. On a surface of the semiconductor substrate 111, an insulating film 114 covering the P-type semiconductor layer 112 and the N+-type semiconductor layer 113 and having an opening portion through which a portion of the N+-type semiconductor layer 113 is exposed, is formed. Note that a plurality of light receiving portions arranged two-dimensionally, vertical transfer portions (vertical CCDs) arranged along respective vertical columns of the light receiving portions, and a horizontal transfer portion (horizontal CCD) provided adjacent to an end row of the light receiving portions are provided in the P-type semiconductor layer 112. The light receiving portion, which is a photodiode made of the N+-type semiconductor layer 113 formed in the P-type semiconductor layer 112, accumulates electric charges, depending on the intensity of received light. The peripheral circuit, the protective circuit and the like are also formed in the P-type semiconductor layer 112.
A through hole 116 penetrating through the insulating film 114, the semiconductor substrate 111 and the P-type semiconductor layer 112 is formed in the insulating film 114 and the semiconductor substrate 111. An insulating film 117 is formed on a sidewall portion of the through hole 116 and on a rear surface of the semiconductor substrate 111. A through electrode 118 is formed, filling an inside of the insulating film 117. A pad portion 115 that is connected to the N+-type semiconductor layer 113 and the through electrode 118 via the opening portion of the insulating film 114 is formed on a front side of the semiconductor substrate 111, specifically on the insulating film 114 and the insulating film 117. The pad portion 115 is connected via the wiring line L to the internal circuit region 101 (see FIG. 12). On the other hand, on a rear side of the semiconductor substrate 111, a rear surface electrode 119 that is connected to the through electrode 118 is formed on the insulating film 117, and an insulating resin layer 120 is formed, covering the rear surface electrode 119 while exposing a portion thereof. A protruding electrode 121 that is connected to the rear surface electrode 119 is formed in the opening portion of the insulating resin layer 120.
Incidentally, in the above-described structure of the conventional solid-state imaging device, when the through hole 116 is formed by etching, the through hole 116 penetrates through a PN junction region of the semiconductor substrate 111. Therefore, since the etching rate differs between the P-type semiconductor layer and the N-type semiconductor layer due to a difference in crystal face, etching damage or substrate roughness may occur, leading to an increase in leakage current at the PN junction or an increase in dark current that is particularly more significant during an operation at high temperature. If a dark current increases, the circuit operation of the drive circuit portion is interfered, depending on the arrangement of the light receiving portion and the drive circuit portion.
Specifically, the pad portion 115 has a layered structure of Ti/TiN/Al, and accordingly, the through hole 116 is formed by chipping a part of the Ti/TiN/Al layer of the pad portion 115. The chipped metals serve as metal contamination and remain on the exposed surface of the PN junction to invite an increase in leakage current at the PN junction and an increase in dark current.
The leakage current and the dark current invite malfunction in the circuit operation of the drive circuit portion. The increase in dark current also invites defects in the image, such as white flaws, which are critical in imaging devices.
These problems may become apparent after long-term use.
USPTO Backgrounds
USPTO Backgrounds