1. Field of the Invention
The invention generally relates to fin-type field effect transistors (FinFETs) and more particularly to FinFETs that include a heat dissipating structural feature (such as a recess in the insulator layer or a thermal conductor extending through the insulator layer) adjacent the fin.
2. Description of the Related Art
As silicon devices are made smaller and smaller, higher circuit density, increased device current, and increased operational frequency lead to increased heat generation inside the chips. Significant technological improvements have been made in terms of chip packaging technologies that allow for chip cooling, but there are several device level technologies which exacerbate the thermal problems. For example in silicon-on-insulator (SOI) technology, since the device layer is thermally isolated from the substrate and the top part of the chip is also covered with insulator, there is significantly higher thermal resistance. One recent advance in transistor technology is the introduction of fin type field effect transistors that are known as FinFETs, which are disclosed in U.S. Pat. No. 6,413,802 to Hu et al. (hereinafter “Hu”), which is incorporated herein by reference. Hu discloses a FinFET structure that includes a center fin that has a channel along its center and source and drains at the ends of the fin structure. In fin-type field effect transistor (FinFET) technology, the current density is higher and the high current region is both further away from the substrate, and is surrounded on all sides by the gate. Therefore, FinFETs present very unique and sophisticated cooling problems that do not affect other types of transistors. The current invention involves a method and structure for improving the thermal conductivity of FinFETs on SOI.
USPTO Backgrounds
USPTO Backgrounds