1. Technology Field
The present invention relates to a method for transmitting data between memory dies. Specifically, the present invention relates to a memory storage device and a memory controller thereof using the aforementioned method.
2. Description of Related Art
Rewritable non-volatile memory is one of the most adaptable memories for electronic products due to its data non-volatility, low power consumption, small volume, and non-mechanical structure. Solid State Drive (SSD) is an example of utilizing the rewritable non-volatile memory as the storage media, and has been widely applied in the host computer as a main hard disk.
Most SSD on the market has the multiple channels (i.e., data input/output bus) structure, and each channel will be coupled with multiple memory dies. FIG. 1 is the internal schematic view of a prior art of a SSD which supports the NAND flash interface. The SSD 100 includes N channels (i.e., the channels CH1 to CHN), and each channel is coupled to M memory dies. Take all the memory dies F1-1 to F1-M that are coupled to the channel CH1 as example, because the memory dies F1-1 to F1-M share the same read signal RE1, the write signal WE1 and the data input/output bus D1, for the channel CH1, only one of the memory dies F1-1 to F1-M may execute data transmission at the same time. Accordingly, when the different memory dies coupled to the same channel need to conduct data transmission, the time for each memory die to transmit data cannot overlap.
For example, to copy a data in the memory die F1-1 to the memory die F1-2, under the structure illustrated in FIG. 1, the memory die F1-1 needs to be first enabled, and use the read signal RE1 and the write signal WE1 to control the memory die F1-1 to read out the data. In addition, the data is stored to an external memory space through the data input/output bus D1. Such external memory space may be the buffer memory 1105 of the memory controller 1100, and etc. After the data read operation is complete, use the read signal RE1, the write signal WE1 and the data input/output bus D1 to write the data in the buffer memory 1105 back to the memory die F1-2. Because the read signal RE1 and the write signal WE1 are in different states when controlling the memory die to read or write the data, when conducting data transmission between the memory die F1-1 and memory die F1-2 using the same read signal RE1 and the write signal WE1, the data transmission time for reading out data from the memory die F1-1 and for writing data to the memory die F1-2 cannot overlap.
For the SSD applying the open NAND flash interface (ONFI) or the toggle NAND flash interface, only one at a time of all the memory dies coupled to the same channel can conduct data transmission. Accordingly, more time will be wasted when conducting data transmission among the aforementioned memory dies.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.
USPTO Backgrounds
USPTO Backgrounds