1. Technical Field
Embodiments relate to a semiconductor memory apparatus, and more particularly, to a data read circuit of the semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus transfers/receives multi-bit data to/from an external memory control device in a serial manner. On the other hand, the semiconductor memory apparatus internally includes a plurality of global data buses GIO in order to transfer/receive the multi-bit data to/from a core region, and the multi-bit data transferred via the global data buses are configured in a parallel manner. Therefore, since the multi-bit data are transferred in the parallel manner inside the semiconductor memory apparatus and are transferred in the serial manner outside the semiconductor memory apparatus, a data read circuit of the semiconductor memory apparatus performs an operation for aligning the parallel data transferred from the core circuit region via the global data bus in series. Afterwards, the data read circuit performs an operation for driving the data aligned in series to output the driven data through a pad.
In general, a semiconductor memory apparatus includes a circuit configuration to detect an error of input data, and discriminates whether an error bit is included in the data or not by using a technique such as a Cyclic Redundancy Check (CRC) technique. On the other hand, the data bits outputted through the pad via the global data buses do not include such an error detection information. That is, a conventional semiconductor memory apparatus may not include a configuration to output the error detection information together with output data, and thus is lacking in reliability of the data, thereby having a difficulty in realizing a high-speed semiconductor memory apparatus.
USPTO Backgrounds
USPTO Backgrounds