This invention relates to a semiconductor device fabricating technology and, more particularly, to a method for mounting a flip chip on a circuit board.
Electronic devices have been continuously miniaturized, and high-density assembling technologies are being still developed. A flip chip mounting technology is one of the high-density assembling technologies, and is attractive to the manufacturers from the viewpoint of simplification.
In order to mount flip chips on a substrate, various methods have been proposed. The prior art methods disclosed in Japanese Patent Nos. 1689504 and 2770821 are categorized in the pressure mounting technology. The pressure mounting technology requires neither solder nor conductive resin. A flip chip is mounted on a printed circuit board in such a manner that the electrodes of the flip chip are held in contact with the conductive pads on the printed circuit board. Sealing resin has been already spread over the printed circuit board, and heat and pressure are applied so as to cure the sealing resin. The sealing resin is shrunk, and the shrunk sealing resin presses the electrodes to the pads. Thus, the flip chip is fixed onto the printed circuit board without any solder or conductive resin.
Description is hereinbelow made on the prior art method disclosed in Japanese Patent No. 1689504 with reference to FIGS. 1A and 1B. The method starts with preparation of a printed circuit board 1 and a semiconductor element 4. A conductive wiring pattern 10 has been already formed on the printed circuit board 1, and the semiconductor element 4 has metal bumps 11. Synthetic resin 12 is spread over an area on the printed circuit board 1 where the semiconductor element 4 is to be mounted. The conductive wiring pattern 10 and an exposed surface of the printed circuit board 1 are covered with the synthetic resin layer 12. The synthetic resin may be spread over the lower surface of the semiconductor element 4. The synthetic resin is, by way of example, epoxy resin, and is provided in either liquid or a piece of foil. The synthetic resin is insulating, and is of the type thermally cured or photo-cured.
Subsequently, the semiconductor element 4 is conveyed to the space over the printed circuit board 1, and the bumps 11 are aligned with the conductive wiring pattern 10 as shown in FIG. 1A.
The semiconductor element 4 is downwardly moved. The metal bumps 11 penetrate through the synthetic resin layer 12, and reach the conductive wiring pattern 10. Thus, the metal bumps 11 are brought in contact with the conductive wiring pattern 10.
Heat is applied to the synthetic resin layer 12, or light is radiated to the synthetic resin layer 12. Then, the synthetic resin layer 12 is cured, and is shrunk as shown in FIG. 1B. The synthetic resin thus cured presses the semiconductor element 4 downwardly, and the metal bumps 11 are pressed against the conductive wiring pattern 10.
Although the semiconductor element 4 is mounted on the printed circuit board 1 without any solder or conductive resin through the prior art method as described hereinbefore, a problem is encountered in the resultant semiconductor device in that disconnection is liable to take place between some metal bumps 11 and the conductive wiring pattern 10. The disconnection is due to a small amount of synthetic resin left on the conductive wiring pattern 10 as indicated by reference numeral 13 in FIG. 1B. While the semiconductor element 4 is being downwardly moved, the metal bumps 11 push the synthetic resin aside. When the metal bumps 11 reach the conductive wiring pattern 10, most of the synthetic resin is evacuated from the upper surface of the conductive wiring pattern 10. However, there remains a small amount of synthetic resin, and the small amount of synthetic resin forms an extremely thin synthetic resin layer 13 between the conductive wiring pattern and some metal bumps 11. The synthetic resin is insulating, and the disconnection takes place between the bumps 11 and the conductive wiring pattern 10.
A solution is proposed in Japanese Patent No. 2770821. According to the prior art method disclosed in the Japanese Patent, sharp tails have been formed on the lower surfaces of the metal bumps 11 before mounting the semiconductor element on the printed circuit board.
While the semiconductor element 4 is being downwardly moved, the sharp tails proceed through the synthetic resin layer. The sharp tails firstly reach the conductive wiring pattern 10. The semiconductor element is further moved downwardly, and the sharp tails are crushed on the conductive wiring pattern. When the sharp tails expand on the conductive wiring pattern, the synthetic resin is perfectly evacuated from the conductive wiring pattern, and the metal bumps are surely held in contact with the conductive wiring pattern. Thus, the sharp tails permit the metal bumps to form the electrical connections between the metal bumps and the conductive wiring pattern.
Finally, the synthetic resin is thermally cured or photo-cured, and the metal bumps are pressed against the conductive wiring pattern by virtue of the shrinkage of the synthetic resin.
Thus, the semiconductor element is electrically connected to the conductive wiring pattern without any solder or conductive resin, and the probability of disconnection between the metal bump and the conductive wiring pattern is little. However, a problem is encountered in the prior art semiconductor devices mounted through the prior art methods in a narrow field of application and a low reliability. Since the compressive force produced through the shrinkage of the synthetic resin keeps the metal bumps and the conductive wiring pattern held in contact with one another, the expansion of the synthetic resin due to high temperature environment removes the pressure from the contacts between the metal bumps and the conductive wiring pattern. When the pressure is removed from between the metal bumps and the conductive wiring pattern, the contact resistance therebetween is increased, and, accordingly, the amount of allowable current passing therethrough is decreased. Thus, the allowable current is smaller than that passing through a contact produced through an alloying. This means that the prior art methods are merely applicable to semiconductor devices, which operate on condition of a small current density at the contacts to the conductive wiring pattern. Further, the prior art methods are hardly applied to semiconductor devices, which are expected to operate in the high temperature environment. As a result, the field of application is narrowed.
The low reliability is due to aged deterioration of the synthetic resin. Even if the semiconductor devices mounted through the prior art methods are not expected to operate in the high temperature environment, the synthetic resin may be periodically subjected to a heat cycle. In this situation, the thermal stress is repeatedly exerted on the synthetic resin, and tends to lose the resiliency. This results in removal of the pressure from between the metal bumps and the conductive wiring pattern. The contact resistance is drastically increased, and some bumps are disconnected from the conductive wiring pattern.
It is therefore an important object of the present invention to provide a mounting method, which is applicable to a wide variety of application products at high reliability.
To accomplish the object, the present invention proposes to complete electrical connections through alloying.
In accordance with one aspect of the present invention, there is provided a method for mounting a semiconductor chip on a substrate comprising the steps of a) preparing a semiconductor chip having conductive electrodes and a substrate having conductive layers, the conductive electrodes and the conductive layers being formed of material capable of being alloyed with one another, b) pressing the conductive electrodes against the conductive layers by shrinking a sealing layer covering at least the conductive electrodes and the conductive layers, and c) alloying the material with each other for completing electrical connection between the conductive electrodes and the conductive layers.
USPTO Backgrounds
USPTO Backgrounds