1. Field of the Invention
The present invention relates to a timed bistable circuit (latch), advantageously usable in a comparator circuit having a high frequency response.
2. Discussion of the Related Art
As is known, the most typical function of a comparator circuit is that of comparing between voltages applied to its inverting and non-inverting input terminals. The output of the comparator is either a voltage at logic level 1 when the voltage on the non-inverting input is greater than that on the inverting input or a voltage at logic level 0 when the voltage on the non-inverting input is less than that on the inverting input.
In order to obtain high comparison speeds, where high frequency response characteristics are required, comparators are used which incorporate timed bistable circuits (latches) that have a high commutation speed due to the positive feedback on which their operation is based.
A typical comparator of this type is constituted, as shown in FIG. 1, by a differential preamplifier stage DIF, a latch LAT timed by a clock circuit CK and an output stage FF constituted by a "master-slave" RS-type flip-flop. The inputs Vin and Vref of the differential stage are the inputs of the comparator and one of the outputs of the flip-flop, Q or Q, is the output of the comparator. The differential preamplifier stage DIF must have a gain such that the smallest difference Vin-Vref which must be sensed is amplified by a factor sufficient to obtain at the input to the latch a signal with an amplitude higher than the offset referred to the input. As is known, the input offset voltage of a differential circuit is the voltage which must be applied to the inputs to have a voltage difference equal to zero between the outputs of the circuit and is a quantity which depends on asymmetry and unbalancing of the components of the circuit. For the comparator of FIG. 1 the offset voltage referred to the input is expressed by ##EQU1##
where V.sub.OSDIF is the offset of the differential stage DIF, V.sub.OSL is the offset of the latch LAT and A.sub.DIF is the gain of the differential preamplifier stage DIF.
In order to obtain a comparator having output levels which are as sharp, stable and in the case of integrated circuit structures, as reproducible as possible from one example to another it is necessary to minimize the input offset voltage. Moreover, in order to obtain comparators which have the most uniform possible response even at high comparison frequencies, it is necessary that the offset voltage does not depend on frequency. In practice, however, known latches have an offset voltage V.sub.OSL which increases considerably with an increase in the frequency at which they are operated. Consequently, the increase in offset voltage limits the response of the comparator at high frequencies.
USPTO Backgrounds
USPTO Backgrounds