1. Field of the Invention
The present invention relates to multi-chip modules and, more specifically, to multi-chip modules including semiconductor devices that are mounted to one another in a back-to-back relationship. The present invention also relates to chip-on-board assemblies. Particularly, the present invention relates to bare and minimally packaged semiconductor devices which are mountable substantially perpendicularly to a carrier substrate such as a printed circuit board. All of the bond pads of the semiconductor devices are disposed proximate a single edge or side thereof. The present invention also relates to methods and devices for securing back-to-back mounted semiconductor devices perpendicularly relative to a carrier substrate and for establishing electrical connections between the semiconductor devices and the carrier substrate to fabricate a multi-chip module.
2. Background of Related Art
The direct attachment of an unpackaged semiconductor device to a circuit board is known in the art as chip-on-board technology. Semiconductor devices that are directly (i.e., without packaging) mountable to a circuit board typically include peripherally disposed bond pads that are adjacent more than one edge thereof or in an area array over the active surface of the semiconductor device. Methods for attaching unpackaged or minimally packaged (such as the so-called xe2x80x9cchip scale packagexe2x80x9d) semiconductor devices directly to a circuit board include wire bonding, flip-chip technology and tape automated bonding. Typically, when such techniques are employed, a semiconductor device (typically a singulated semiconductor die) which includes bond pads on an active surface thereof is oriented over the circuit board, either active surface up or active surface down, and substantially parallel thereto, in order to establish an electrical connection between the semiconductor device and the circuit board by one of the aforementioned techniques. After electrically connecting such a semiconductor device to a circuit board, a protective coating may be applied over the semiconductor device.
However, the active surface-down placement of a semiconductor device directly against a circuit board is somewhat undesirable in that, due to the substantially parallel orientation of the semiconductor device relative to the circuit board and the location of an integrated circuit on the active surface of the semiconductor device against the circuit board, heat must pass through the circuit board or through the substrate of the semiconductor device in order to dissipate from the active surface of the semiconductor device. Thus, the transfer of heat away from the semiconductor device is relatively slow and may result in the generation of damaging ambient temperatures at the active surface during prolonged operation of the semiconductor device. A horizontal (parallel) orientation of the semiconductor device relative to the circuit board also causes the semiconductor device to consume a great deal of area or xe2x80x9creal estatexe2x80x9d on the circuit board. Moreover, conventional chip-on-board attachments as previously referenced are typically permanent, making them somewhat undesirable from the standpoint that they are not readily user-upgradable by substitution of different, higher-performance semiconductor devices.
Various multi-chip module arrangements have been developed to conserve xe2x80x9creal estatexe2x80x9d on a carrier substrate. Some multi-chip modules include a plurality of mutually parallel bare semiconductor devices that are secured in a stack, one above another. The semiconductor devices of stacked multi-chip modules are typically substantially parallel to the carrier substrate to which they are secured. Multi-chip modules with vertically oriented dice are also known. Exemplary device stack arrangements are described in the following U.S. Pat. Nos. 5,291,061, issued to Ball on Mar. 1, 1994; and 5,323,060 issued to Fogal et al. on Jun. 21, 1994. Exemplary vertical dice arrangements are described in U.S. Pat. Nos. 5,362,986, issued to Angiulli et al. on Nov. 8, 1994; and 5,397,747, issued to Angiulli et al. on Mar. 14, 1995.
While multi-chip modules successfully conserve some of the xe2x80x9creal estatexe2x80x9d on a carrier substrate, the horizontal (i.e., substantially parallel to the carrier substrate) orientation of some such devices still consumes a significant area thereof. Moreover, the stacking of many such semiconductor devices inhibits the dissipation of heat from the devices of the stack, which may, as noted above, adversely affect the performance of the semiconductor devices, and may even damage them. Finally, many known multi-chip modules are electrically connected to a carrier substrate with solder or other permanent means, such as wire bonds or TAB (tape automated bonding or flex circuit) connections, and are also permanently mechanically attached by solder, epoxy or another bonding agent. Thus, such semiconductor devices are not readily removable from the carrier substrate or readily replaceable thereupon (i.e., they are not userupgradable).
Similarly, vertical surface mount packages are known in the art. When compared with traditional, horizontally mountable semiconductor packages and chip-on-board devices, many vertical surface mount packages have a superior ability to transfer heat away from the semiconductor device due to exposure of both major surfaces of the package. Vertical surface mount packages also consume less area on a circuit board than a horizontally mounted package of the same size. Thus, many skilled individuals in the semiconductor industry are finding vertical surface mount packages more desirable than their traditional, horizontally mountable counterparts. The following U.S. patents disclose various exemplary vertical surface mount packages: Re. 34,794, issued to Warren M. Farnworth on Nov. 22, 1994; 5,444,304, issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep. 12, 1995; 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
Many vertical surface mount packages are somewhat undesirable in that they include leads which operatively connect a semiconductor device to a circuit board. The leads of such devices tend to increase the impedance and decrease the overall speed with which such devices conduct electrical signals. Moreover, the required packaging of many such devices adds to their undesirability. Typically, packaging requires multiple additional materials and manufacturing steps, which translate into increased production costs, which are further increased due to the potential for package and connection defects and resulting lower final yields. The packaging of many vertical surface mount packages, and thus thickness in excess of that of the packaged die, also tends to consume additional area or xe2x80x9creal estatexe2x80x9d on the circuit board to which they are attached. Further, the materials of most semiconductor device packages tend to inhibit the transfer of heat from the semiconductor device contained therein. Moreover, many vertical surface mount packages are not readily user-upgradable due to permanent connections to the carrier substrate.
Accordingly, the inventor has recognized a need for a semiconductor device configuration that has low impedance, provides improved heat transfer and conserves xe2x80x9creal estatexe2x80x9d on a carrier substrate. There is also a need for user-upgradable semiconductor devices, which is addressed by some embodiments of the invention.
The back-to-back semiconductor device module according to the present invention addresses each of foregoing needs.
The back-to-back semiconductor device module of the present invention includes two semiconductor devices, each having a plurality of bond pads disposed proximate a single edge thereof. The back surfaces, or bases, of the adjoined semiconductor devices are bonded together with an adhesive material to form the back-to-back semiconductor device module. The bond pads of each semiconductor device are positioned adjacent a mutual or common edge of the semiconductor device module.
The present invention also includes methods and devices for securing the back-to-back semiconductor device module substantially perpendicular relative to a carrier substrate.
An embodiment of a method for securing the module substantially perpendicular to a carrier substrate employs the disposition of solder bricks on the terminals of the carrier substrate that correspond to the locations of the bond pads of the semiconductor devices of the module and the use of solder reflow techniques to establish an electrically conductive joint therebetween.
An embodiment of a module-securing element that orients the module substantially perpendicular to the carrier substrate comprises an alignment device including one or more receptacles having a plurality of intermediate conductive elements therein. Upon insertion of the module into the socket, the intermediate conductive elements establish an electrical connection between bond pads of each of the semiconductor devices and their corresponding terminals or traces on the carrier substrate.
Another embodiment of a module-securing element for orienting the module substantially perpendicularly relative to a carrier substrate includes a leaf spring clip-on lead that establishes a biased, interference-type electrical connection with a bond pad on at least one of the semiconductor devices and a conductive extension which may be electrically connected to a corresponding terminal or trace on the carrier substrate.
The present invention also includes assemblies wherein the back-to-back semiconductor device module of the present invention is oriented substantially perpendicular to a carrier substrate with conductive joints, with an alignment device, with clip-on leads, or with another electrically conductive element. An electronic system with which the back-to-back semiconductor device module is associated is also within the scope of the present invention.
Advantages of the present invention will become apparent to those of ordinary skill in the art through a consideration of the appended drawings and the ensuing description.
USPTO Backgrounds
USPTO Backgrounds