This invention relates generally to semiconductor devices and more particularly to a method of fabricating a coplanar, self-aligned contact structure in a semiconductor device.
In recent years the advancement of very large scale integration ("VLSI") technology has resulted in a need to fit more and more individual semiconductor devices such as transistors into smaller and smaller areas of an integrated circuit chip. The dimensions of these devices have reached the submicron range, and it has become increasingly difficult to make low-resistance contacts for interconnecting such devices. Among the difficulties which have been encountered are spiking through shallow source and drain junction regions and various contact etch stop problems.
An integrated circuit semiconductor fabricated according to typical prior art methods is shown in FIG. 1. A device such as a MOSFET transistor generally designated 10 is constructed on a silicon substrate 11. Spaced-apart first and second field oxide layers 12 and 13 are formed on the substrate 11. Between the layers 12 and 13, a source diffusion region 14 of the substrate 11 abuts the first layer 12 and a drain diffusion region 15 abuts the second layer 13. A gate 16, for example of polysilicon, overlies parts of the source and drain regions 14 and 15 and another portion of the substrate 11 which lies between said regions.
A first extremity of a polysilicon layer 17 overlies a portion of the field oxide layer 13, the layer 17 having a second extremity which extends out of the field of view of FIG. 1, for example to define a gate of an adjacent semiconductor. A passivation layer 20 such as phosphosilicate glass overlies the entire structure. During the manufacturing process, source and drain contact holes 21 and 22 are etched through the passivation layer 20 to the source and drain diffusion regions 14 and 15, respectively, and a contact hole 23 is etched through the layer 20 to the polysilicon layer 17.
Next, a metal layer such as an aluminum alloy is deposited on top of the device of FIG. 1, resulting in the device shown in FIG. 2. The metal layer is deposited over the device and then etched to provide a first contact 24 through the hole 21 to the source region 14 and a second contact 25 through the holes 22 and 23 to establish a direct connection between the drain region 15 and the polysilicon layer 17.
As the overall dimensions of devices such as the transistor 10 became smaller, defects which could result from lithographic misalignment and undercutting during contact etch were avoided by increasing the spacing between the contact holes 21 and 22 and the edges of the gate 16 and the oxide regions 12 and 13. Not only did this increased spacing limit the number of devices which could be placed on a chip but it also increased the junction capacitances and contact resistances, thereby degrading performance of the device.
Efforts to improve device performance by reducing these spacings led to very shallow junctions at the diffusion regions 14' and 15 and often resulted in spiking problems in which the metal 24 and 25 penetrated through the diffusion regions to the substrate 11 below. Etch stop problems arose from tighter controls of the device geometry and a need for planarization of the tops of the metal contacts.
Methods such as reflow, salicide and planarization have been tried in a continuing effort to solve these problems. However, as the device dimensions have shrunk into the submicron range, these methods have been inadequate to solve all of the problems simultaneously. Accordingly there remains a need for a way to fabricate low-resistance contacts in semiconductor devices having dimensions in the submicron range without suffering the ill effects of junction spiking, high junction capacitance and contact etch stop problems.
USPTO Backgrounds
USPTO Backgrounds