Electronic designs generally consist of components that communicate with one another through signals. A portion of an electronic design is called a “subsystem”. A subsystem is “synchronous” provided it operates at a single rate or at several rates that are related to one another in a predictable way. In hardware, rates for a synchronous subsystem are often achieved by using a combination of clocks and clock enables. The particular combination varies with design goals and the capabilities of the underlying hardware. At one extreme, a different clock may be used for each rate without clock enables or with clock enables that are tied high; at the other extreme, a single clock is employed and the rates are achieved by “stepping down” the clock with various clock enables. Often, a mixture of these approaches is used.
An entire design may be synchronous, such as when all rates in the design are related. Often, however, a design is “asynchronous”, i.e., some rates are unrelated to others. We use the term “clock domain” to describe a synchronous subsystem of a design. This means that within a given clock domain, all rates are related. Typically, a clock domain is a maximal synchronous subsystem of the design, such that no two different clock domains have related rates. Thus, a synchronous design consists of a single clock domain and an asynchronous design consists of at least two clock domains. Special “synchronizer” components are usually employed to communicate between clock domains. Synchronizer components must be rate insensitive or at least have less rate sensitivity than a typical component. So-called asynchronous FIFOs and shared memories are examples of such synchronizer components.
Simulators for electronic designs usually support both synchronous and asynchronous designs. This, for example, is the case in the hardware simulator known as ModelSim (sold by ModelTech, Inc.). When a design is known to be purely synchronous, specialized simulation strategies may be employed including cycle-based simulation and cycle-based hardware co-simulation. Such specialized simulation strategies may provide significantly increased simulation speed. However, such specialized simulation strategies may not be applicable to asynchronous designs.
The present invention may address one or more of the above issues.
USPTO Backgrounds
USPTO Backgrounds