The present invention concerns so-called voltage booster circuits, in particular for use in integrated circuits such as semiconductor memories and especially non-volatile memories, for example Flash memories. More specifically, the invention concerns voltage booster circuits of the charge pump type.
Over the last ten years, the progressive reduction in size of MOS transistors in monolithic integrated circuits has encouraged the use of ever lower supply voltages. In fact, the increase in integration density is based on the principle of reduction in scale (xe2x80x9cscalingxe2x80x9d) with a constant electric field, owing to which it is possible to retain the functional characteristics of an MOS device while reducing all the dimensions by the same factor including those orthogonal to the surface of the integrated circuit (and therefore the thicknesses of the various layers, among these the gate oxides of the transistors), and the applied voltages, and increasing the doping concentrations of the active areas by the same factor.
At the present time, integrated circuits are available, in particular non-volatile semiconductor memories, that are able to operate with a supply voltage (VDD) nominally equal to 3 V or even lower.
Moreover, compared to normal MOS transistors used for example to construct logic gates, non-volatile memory cells, and in particular Flash memory cells, have special characteristics.
In fact, in Flash memory cells, the thickness of the gate oxide cannot be scaled down to below a certain value, typically 8 nm, in order to guarantee retention of the data stored in the cells for a sufficient period of time, typically 10 years.
In addition, the physical phenomena that permit programming and erasing of Flash memory cells only exist in the presence of high electric fields across the oxide.
For these reasons, at least during the operations of programming and erasing the cells, it is necessary to have voltages available that are higher, in absolute value, than the supply voltage currently used.
In non-volatile memories, in particular in multi-level Flash memories, it is therefore necessary to provide a voltage that is higher than the supply voltage currently used, not only for program and erase operations, but also for the operation of reading the contents of the memory cells.
Therefore, unless the required voltages are supplied to the integrated circuit from outside, they must be generated internally within the integrated circuit itself, this is typically the case for an integrated circuit with a single supply voltage (Single Power Supply). From this arises the requirement to provide voltage booster circuits on board the integrated circuit.
The most commonly used voltage booster circuits in integrated circuits are those based on the principle of the so-called charge pump, and for this reason they are called charge pump circuits or, more briefly, charge pumps. These circuits make available at their output a voltage with an absolute value that is higher than the voltage with which they are powered. In the field of charge pumps, a distinction can be made between positive charge pumps, that provide a positive voltage at their output, of the same polarity as the supply voltage, and negative charge pumps, that provide a negative voltage at their output, of opposite polarity to that of the supply voltage.
A problem that afflicts charge pumps is their limited capacity to supply an output current or, stating the problem differently, their high output resistance. In other words, charge pumps behave as poor voltage generators. That means that when the charge pump is required to deliver a large, sustained, or other significant current, the output voltage value drops drastically, in absolute value, with respect to the target value.
This aspect is especially critical for the use of charge pumps integrated with electrically programmable non-volatile memories such as, for example, Flash memories, in which charge pumps are used to generate bias voltages for the memory cells in order to perform the various operations which can be carried out on the memory. In particular, the generation of voltages to be applied to the drain of the memory cells during programming thereof becomes critical: in this case, the amount of current that the charge pump is able to deliver without the output voltage falling excessively below the target value places a limit on the number of cells that can be programmed in parallel.
Other critical aspects of charge pumps, although in some ways associated with the foregoing, are the recovery time, or the time required for the charge pump to restore the target voltage value output by the charge pump after the actual output voltage has fallen in absolute terms because of excessive current consumption, and the settling time for the voltage value at the output of the pump at the firing of the charge pump.
In view of the prior art described, one object of the present invention is therefore to provide a charge pump voltage booster circuit that is not affected by the problems mentioned, and in particular has a low output resistance.
In accordance with the present invention, this object is achieved by means of a charge pump voltage booster circuit as described in the independent claim 1 attached.
USPTO Backgrounds
USPTO Backgrounds