In a typical computer system there is generally some form of mass storage interconnected to the central processing unit (CPU). Mass storage devices, while being varied in number and form, are typically used to store data files and program data until their use is required by the CPU or alternatively are used for long term backup of a primary mass storage device. One example of a mass storage device is the hard disk drive which is most commonly used because of its extended storage capacity and its expedient data recall. When the operator requests the CPU to initiate program execution or when a program requires data not in memory, the CPU attempts to retrieve that data from the hard drive. The hard drive responds to that request by determining where the data is located on the disk, recalling that data, and then transferring it to the CPU. A second example of a mass storage device is the floppy or removable disk. This storage media is typically used for temporary or short term backup or to enable users to transport programs or data from one computer to another, but may be, and often is, the only mass storage device. Floppy disks provide the user greater flexibility as they are easier to transport than the hard drive which is usually integral to the computer system and is not easily removed for transportation. However, the floppy disk is limited by its storage capacity, which is usually much smaller than the hard disk, and is also limited by its speed as its read and write access time is significantly larger than that of a hard disk drive. A third example of a mass storage device is the streaming tape drive. These drives are used for high speed backup of portions of or an entire hard disk or even a series of hard disks. The advantage of the streaming tape drive is that because of its extended storage capacity, it enables backup with a minimum of operator interaction, and they may be transported more easily than hard disk drives for off-site from the primary computer system archival for protection. One additional storage device which should be noted is the optical disk drive. The optical disk is characterized by an extremely large storage capacity and also by its extremely fast data retrieval. However, it is limited in that the end user may only read from the disk and is unable to write to it. Thus, while being extremely useful for the purpose of data storage and look-up, it is limited in its range of applications as a data storage device.
For the above described devices, except for the optical disk, a write operation occurs when the CPU sends data and the data file to which the data should be written to the input/output controller for that particular device. As the media on a magnetic mass storage device generally is capable of assuming one of two states, it is those two states that define data in terms of logic 1 or a logic 0. However, state transitions on the magnetic media occur over the space domain of the media while data transitions within digital control circuitry occur over the time domain. There is then required a method of encoding a translation between the digital data within computer memory and actual flux transitions. Accordingly, there are several data formatting schemes which translate data bytes existing within the time domain into a series of state transitions within the space domain upon the storage media, yet retain the timing information for read back operations. Some examples of these formatting schemes are: FM, MFM, M.sup.2 FM, GCR, RLL.sub.1,7 and RLL.sub.2,7 all of which are well known in the prior art. These data formatting schemes are often inherent to the controller, and are generally predetermined based on a number of efficiency considerations which include minimizing the number of flux transitions while effectuating a sufficient number of flux transitions to effectively determine a clock signal for discerning data from the stream of state transitions. After the data has been formatted, the controller then directs the write head to effectuate the appropriate state transition upon the storage media. The state transitions on magnetic media are encoded when the device controller sends to a write circuit the encoded data and a write clock signal. The write circuit energizes a write head in accordance with the data to be written to effectuate the appropriate magnetic flux transitions upon the magnetic media.
Data reads from the magnetic media occur in effectively the reverse process used to write data. As the magnetic media passes by the read head of the storage device, flux transitions on the media are detected. The flux transitions generate an analog signal at the read head. It is thus necessary to convert the analog representations of the flux transitions into digital representations. This yields a series of pulses of a varying frequency. The pulses combine both clock and data information which relate directly to the formatting scheme used during the write operation. Thus, because a predetermined formatting scheme is used by the device controller to effect a write operation, the state transitions read from the magnetic media are decoded based upon both clock and data information contained within the pulses into the actual data byte which was sent to it by the CPU. Using techniques well known within the prior art, this formatted data is then separated into a timing signal or window in which data may be read, known as a data separator window, and also into data transitions. Circuitry then determines if a transition occurs within the data separator window. By determining where data transitions occur within a series of data separator windows, the initial data encoded by the device controller may be recovered. The controller then translates this encoded data back to the original non-encoded data which was sent to the controller by the CPU.
This invention is directed at measuring the occurrence of data transitions within the data separator window. Because transitions upon the magnetic media are decoded into a data separator window and possibly a data transition (if indeed there is one), it is imperative that the data transition fall within the proper data separator window to maintain the timing relationships within the data stream. Data transitions outside of their proper window will alter the recovered data from the original and lead to erroneous read backs.
In a number of systems, the data transition occurs ideally within the center of the data separator window. However, there are any number of factors which may cause a data transition to shift within the data separator window. Factors that contribute to a shift in the data transition within the data separator window include noise at the read and/or write heads, cross-talk from the read head, magnetic interaction between the flux transitions on a magnetic media, jitter within the phase lock loop circuitry, circuit component noise, and inherent component delay. The cumulative effect of the above factors contribute to the shift of the data transition within the data separator window. If the data transition shifts significantly, it is possible that it may move outside the boundary of the data separator window. It is the goal of device driver designers and manufacturers to quantify the probability of such an error, as it would yield a general indicator of the reliability of the device.
In order to obtain an accurate measure of the probability of a data transition falling outside of the data separator window, the error rates typically discussed are on the order of the number of data errors per 10.sup.10 data bits. In order to achieve a valid statistical analysis, it is not only necessary to determine the number of errors for every 10.sup.10 bits read, it is also necessary to repeat this test a sufficient number of times, approximately 10. The cumulative effect of having to generate an error rate per 10.sup.10 reads and have that error rate be statistically significant would require reading approximately 10.sup.11 data bits. The time required to test that number of bits effectively makes such a test preclusive for both system designers and system manufacturers. Thus, there is a need for a time efficient method and apparatus for obtaining statistically significant read error rates.
One time efficient method is to develop a measure of the allowable time interval between the leading and trailing edges of the data separator window and the data transitions for a given error rate, called the window margin. The window margin is a measure of the safety margin from the leading and trailing edges of the data separator window for a given error rate. These time margins effectively define a sub region of the data separator window into which the data transitions may fall to ensure that the stated error rate is achieved.
Window margin analysis is based on the known concept within the prior art that data transitions tend to occur substantially about a particular point within a data separator window, ideally the center of the data separator window. However, noise and other phenomena cause data transitions to occur on both sides of this center point. If a plot were developed representing where data transitions occur within the data separator window, a given distribution would result. This resulting distribution is integral to the development of the tests to determine the error rate of a mass storage device. If the shape of the distribution curve is known and the curve could be shifted to produce a given error rate located on the distribution curve, the location of the curve within the data separator window could be determined. Once that curve is determined, any number of error rates can be extrapolated based on the known location of the curve and also the known shape of the curve. This invention is ultimately directed at a circuit for determining if a shift of the data transitions within the data separator window has occurred.
There are several techniques for determining whether a shift relative to the center of the data separator window has occurred. One technique is called the compressed window method. This method is carried out by shifting both edges of the data separator window toward its center to artificially increase the data error rate. The PLL circuit receives the incoming data signal at the decoding stage of read back and generates a timing signal which is used to divide the data signal into segments. The PLL is effectively taken out of the circuit when the window is compressed so that the measured error rate is not a true reflection of the actual error rate of the entire device circuitry because the PLL has been significantly altered. A second method for measuring the shift within the data separator window is to measure the transition-to-transition arrival time. After a significant number of transitions have been read, the arrival times are input into a software PLL to construct a data separator window. The software then determines the position of the data transition within a data separator window. This method has a similar drawback to that of the first method in that it does not accurately measure the performance of the PLL. In fact, this method simulates the PLL and does not truly account for its performance in its measurements. A third method is called the sliding window technique. In order to effectuate this technique, over a series of data transitions, the data separator window is first shifted right or delayed in time, causing the leading edge to move toward the nominal center of the data separator window. The right shift is varied until a desired error rate occurs. Next, the data separator window is shifted left or advanced in time, causing the trailing edge of the window to move toward the center of the unshifted data separator window. The left shift also continues until the desired error rate is obtained. The major disadvantage of this method is that it is necessary to slide the data separator window in both directions. Thus, it is not possible to simultaneously test the window margins at both the leading and trailing edges of the data separator window, as it is first necessary to slide the window right or left in order to test one edge of the data separator window, then slide the data separator window in the opposite direction to increase the error rate at the other edge of the data separator window. This increases the test time by a factor of two and if it were desired to perform both shifts simultaneously, there would be a substantial increase the hardware requirement of the circuit.
USPTO Backgrounds
USPTO Backgrounds