The present invention relates to a multiport semiconductor memory device.
In terms of realizing high-speed access, SRAMs (static random access memories) are suitable as cache memories in microprocessors or the like. Two-port SRAMs are particularly suited for high-speed operation, because their two ports can be operated independently at the same time.
In a prior art two-port SRAM, a selector is provided outside first- and second-port input/output circuits. When requests to read data from the same memory cell are made at a time, the data is read through the first port, while the selector makes the second port also output the data read through the first port, thereby preventing decrease in data read speed and malfunctions (see Japanese Laid-Open Publication No. 10-21687).
In this prior art, however, how to deal with column addresses is unknown. More specifically, when data in memory cells in the same row but in different columns of the memory cell array in the two-port SRAM are requested to be read at the same time, it is not ensured that the correct data is output from each port.
USPTO Backgrounds
USPTO Backgrounds