Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk MOSFET devices below the 0.1 μm process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.
Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, the use of two gates to control the channel significantly suppresses short-channel effects. A FinFET is one example of a recent double-gate structure that includes a channel formed in a vertical fin. The FinFET is similar to existing planar MOSFET in layout and fabrication. The FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.
Existing FinFET structures have relatively severe topographies. The severe topography associated with the FinFET structure has conventionally limited the ability to print and pattern small features for the FinFET gate. Therefore, there exists a need for methods for forming a gate of a FinFET that permits a wide photo margin, thus, increasing the ability to print and pattern the small features of the FinFET gate.
USPTO Backgrounds
USPTO Backgrounds