1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving characteristic of the device.
2. Discussion of the Related Art
A background art semiconductor device will be described with reference to the accompanying drawings.
FIG. 1A is a cross-sectional view illustrating a semiconductor device according to the background art. FIG. 1B is a cross-sectional view illustrating a pre-amorphijation (P-A) processed semiconductor device to have a small junction depth according to the background art. FIG. 1C is a cross-sectional view illustrating a semiconductor device having a Halo structure according to the background art.
Generally, a field effect transistor (FET) has a gate electrode formed on a gate insulator having the same dielectric constant in the overall region. As shown in FIG. 1, the FET according to background art includes a semiconductor substrate 1, a gate insulator 2, a gate electrode material layer 3, and source/drain regions 4a and 4b. The gate insulator 2 constituting one material layer which has a particular dielectric constant is formed on the semiconductor substrate 1. The gate electrode material layer 3 is formed on the gate insulator 3. The source/drain regions 4a and 4b are formed in a surface of the semiconductor substrate 1 at both sides of the gate electrode material layer 3.
In such a FET, a device is formed using the gate insulator 2 having a particular dielectric constant, and a channel inversion region is formed below the gate insulator 2 when a voltage is applied to the gate electrode, thereby moving carriers between the source/drain regions 4a and 4b.
Electrical characteristic of the FET can be defined as follows. EQU Id(sat).varies.Cox=(.epsilon.i.S)/Tox,
where, Id(sat) is a drain saturation current, Cox is a gate capacitance, .epsilon.i is a dielectric constant of the gate insulator, Tox is a gate thickness, and S is a cross-sectional area. Here, the dielectric constant of the gate insulator is obtained by multiplying a free space dielectric constant by a semiconductor specific inductive capacity.
A variable value of a threshold voltage is expressed as .DELTA.V.sub.T =(V.sub.T S.C -V.sub.T L.C).varies.1/Cox=(Tox.times.S)/.epsilon.i, where V.sub.T S.C is a threshold voltage of a short channel, V.sub.T L.C is a threshold voltage of a long channel, and .varies.1/Cox is a serve threshold value factor.
To prevent damage of the device due to a short channel effect and a punchthrough in the above-described FET, semiconductor devices shown in FIGS. 1B and 1C have been suggested.
In FIG. 1B, P-A process is performed to realize a small junction depth in the surface of the semiconductor substrate 1 where the source/drain regions 4a and 4b will be formed. An ion-implantation process is formed thereafter, so that the device is formed to have the gate insulator 2 having one level of dielectric constant.
If a voltage is applied to the gate electrode material layer 3, an inversion layer is formed in a channel region below the gate insulator 2, thereby flowing a current between the source/drain regions 4a and 4b.
Before forming the source/drain regions 4a and 4b, the P-A process is performed to avoid an ion channeling. Therefore, the source/drain regions 4a and 4b are formed to have a small junction depth, thereby reducing a punchthrough.
In FIG. 1C, the FET having a Halo structure is demonstrated to eliminate a punchthrough. A short channel effect, which is undesirable to the device, occurs frequently as a channel length of a semiconductor device becomes shorter, especially in a metal oxide semiconductor field effect transistor (MOSFET). To solve such a problem, among various methods, there is a method for reducing a short channel effect by varying doping profile in a channel region using a Halo doping.
To form a Halo structure, a gate electrode material layer 3 is formed on the gate insulator 2 and impurity ions opposite to the source/drain regions are implanted into the semiconductor substrate at an angle of 0-45.degree.. Alternatively, a gate sidewall spacer is formed and then impurity ions are tilted-implanted into the semiconductor substrate at an angle of 0-45.degree.. In this process, B or BF.sub.2 is used as the impurity ions for an n-MOS transistor.
In a transistor having such a Halo structure, a depletion region due to a drain bias is prevented from being expanded since a drain region is surrounded by a heavily doped region of a conductivity type opposite to the drain region. Thus, a punchthrough can be prevented from occurring in the short channel and drain induced barrier lowering (DIBL) can be reduced. Nonetheless, the aforementioned FET has several problems as follows.
In the background art FET, it is difficult to improve an on-off current characteristic and to reduce a short channel effect at the same time. Although the short channel effect can be reduced in the background art FET, there still remains a problem that a current is reduced as a resistance of source/drain increases.
Further, since a heavily doped region surrounds the source/drain region, a junction capacitance increases, thereby deteriorating characteristics of the device.
For the transistor of Halo structure, since a threshold voltage is varied depending on tilt-ion implantation, it is difficult to ensure a uniformity of the threshold voltage.
In particular, in reducing a thickness of the gate insulator to reduce a short channel effect, a gate breakdown, grid, and impurity scattering are caused, which deteriorate a current characteristic.
USPTO Backgrounds
USPTO Backgrounds