To interface bare semiconductor dies to a support surface such as a printed circuit board, there is a need for an appropriate package substrate to interface and route the semiconductor dies within a package, such as a ball grid array (BOA) package, chip scale package (CSP), or system-in-package (SiP), to the printed circuit board. A conventional interface substrate may start with a core material with laminate film layers built up on both sides of the core material. A flip-chip die may then be coupled to the interface substrate using solder bumps.
Demand for higher performance, power efficiency, and reduced form factor have driven successive generations of die shrinks, resulting in flip-chip dies with very high density interconnect features. As the solder bump interconnects are also required to become increasingly dense, the manufacturability, cost, and reliability requirements for interface substrates have gradually become more difficult to meet. Moreover, with shrinking die sizes, effective thermal dissipation from the smaller available die surface area has also become a greater concern.
USPTO Backgrounds
USPTO Backgrounds