The invention relates to a refresh drive circuit for feeding refresh signals to a memory device. The refresh drive circuit has a refresh signal generator for generating a continuous sequence of refresh signals with a predetermined frequency.
In the case of dynamic random access memories (DRAMs), it is necessary for the information stored in the memory cells to be refreshed at cyclic intervals. Since, in the DRAM memory cells, the information is stored as capacitor charges and the capacitors effect self-discharge, due to leakage currents, in particular at high temperatures, the storage charges of the capacitors have to be repeatedly renewed.
The refreshing of the memory contents of the cell array in the DRAM is generally carried out row by row by an internal refresh drive configuration. To that end, with the aid of a refresh signal generator, a continuous sequence of refresh signals with a predetermined frequency is generated, which are applied to the memory cells. In modern memory modules, refresh cycles of at least 4096 refresh operations per 64 ms (refresh rate 4k/64 ms) are customary. The number of refresh operations must be chosen in such a way that even at the high operating temperature of the computer containing the DRAM and with the large leakage currents of the capacitors which are produced as a result, the capacitors in the DRAM are regularly recharged. The refresh operations therefore lead to a high current consumption of the memory modules and thus shorten, in particular, the operating duration of accumulator or battery-operated computers.
U.S. Pat. No. 5,278,796 discloses a refresh drive circuit. In the case of the drive circuit, the refresh frequency is adapted in discrete steps to the respective operating temperatures in the DRAM, in order to reduce, in particular, the current consumption in the standby mode. U.S. Pat. No. 5,539,703 discloses a further refresh signal generator for a DRAM, in which the refresh frequency is set as a function of the respective operating voltage in order to reduce the current consumption in the DRAM in the standby mode.
It is accordingly an object of the invention to provide a refresh drive circuit for a DRAM which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which reduces the current consumption of dynamic random access memories.
With the foregoing and other objects in view there is provided, in accordance with the invention, a refresh drive configuration for feeding refresh signals to a memory device. The refresh drive configuration contains a refresh signal generator for generating a continuous sequence of the refresh signals with a predetermined frequency and the refresh drive configuration is connected to the memory device. The refresh signal generator is configured such that the predetermined frequency of the refresh signals generated decreases as a temperature falls in the memory device. The refresh signal generator contains a voltage-controlled oscillator and a circuit having a diode with a temperature-dependent anode voltage connected to the voltage-controlled oscillator. The voltage-controlled oscillator receives applied control voltages that are dependent on the temperature-dependent anode voltage of the diode.
In the refresh drive configuration for feeding the refresh signals to a memory device, the refresh signal generator for generating the continuous sequence of refresh signals is configured such that the frequency of the refresh signals generated decreases as the temperature decreases.
The configuration of the refresh drive circuit reduces the number of refresh cycles when the temperature decreases in the memory modules, i.e. when the memory modules in the computer change from the full-load mode to the standby mode. The reduction of the refreshed cycles in turn ensures a significant reduction of the current consumption of the DRAMs. This is particularly advantageous in the case of accumulator- or battery-operated computers with DRAMs, in which the reduced power consumption of the DRAMs in the standby mode through a reduction of the number of refresh cycles of the capacitors of the DRAMs enables the maximum operating duration of the computers to be significantly prolonged.
In accordance with a preferred embodiment, the refresh signal generator is configured such that the frequency of the refresh signals is halved in the event of a temperature drop of approximately 100xc2x0 C. This both ensures reliable recharging of the capacitors in the DRAM memory cells and at the same time provides for an optimal reduction of the current consumption of the cell array.
In accordance with a further preferred embodiment, the refresh signal generator is a voltage-controlled oscillator, the control voltage used being the anode voltage of a diode which decreases as the temperature of the diode increases. This embodiment of the refresh drive circuit makes it possible to set an optimal temperature response of the frequency of the refresh cycle of the capacitors in the DRAM.
In accordance with an added feature of the invention, the circuit has differential amplifiers connected to and between the diode and the voltage-controlled oscillator, the temperature-dependent anode voltage of the diode is amplified by a factor of 2-10 by the differential amplifiers.
In accordance with an additional feature of the invention, the applied control voltages of the voltage-controlled oscillator are determined by the temperature-dependent anode voltage of the diode.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a refresh drive circuit for a DRAM, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
USPTO Backgrounds
USPTO Backgrounds