This application claims the priority of Korean Patent Application No. 2002-46574, filed Aug. 7, 2002 in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC), and more particularly, to a signal buffer for high-speed signal transmission and a signal line driving circuit including the same.
2. Description of the Related Art
As shown in FIG. 1, when the load capacitance of a signal line 11, which transmits a signal in a semiconductor IC, is large, and when the parasitic resistance and the parasitic capacitance of the signal line 11 are large, the transmission speed of the signal transmitted through the signal line 11 is reduced, and signal distortion may occur.
In a conventional approach for addressing this issue, as shown in FIG. 2, inverter-type signal buffers 24 and 25 are installed at predetermined locations along a a signal line 21 in order to prevent the signal distortion and in order to improve signal transmission speed.
However, when the inverter-type signal buffers 24, 25 are employed, the inverter causes an additional propagation delay along the signal line. In addition, the signal buffers 24, 25 increase the occupied surface area of the integrated circuit.
The present invention provides a signal buffer for improving the transmission speed of a signal on a signal line while occupying a relatively small area of an integrated circuit.
The present invention also provides a signal line driving circuit including a signal buffer, which improves the transmission speed of a signal while occupying a relatively small area of an integrated circuit.
According to a first aspect of the present invention, there is provided a signal buffer comprising a pull-up driver for pulling up an input/output terminal in response to a first control signal, and a control circuit for detecting a rising transition of a signal applied to the input/output terminal in response to a second control signal applied to the control terminal in order to generate the first control signal.
Here, the pull-up driver comprises a PMOS transistor having a source receiving a power voltage, a gate receiving the control signal, and a drain connected to the input/output terminal.
The control circuit comprises a PMOS transistor having a source coupled to a voltage supply, a gate connected to the control terminal, and a drain outputting the first control signal; a first NMOS transistor having a drain connected to the drain of the PMOS transistor and a gate connected to the input/output terminal; and a second NMOS transistor having a drain connected to the source of the first NMOS transistor, a gate connected to the control terminal, and a source coupled to a ground supply.
According to a second aspect of the present invention, there is provided a signal buffer comprising a pull-down driver for pulling down an input/output terminal in response to a first control signal, and a control circuit for detecting a falling transition of a signal applied to the input/output terminal in response to a second control signal applied to a control terminal in order to generate the first control signal.
Here, the pull-down driver comprises an NMOS transistor having a drain connected to the input/output terminal, a gate receiving the first control signal, and a source coupled to a ground supply.
The control circuit comprises a first PMOS transistor having a source coupled to a voltage supply and a gate connected to the control terminal; a second PMOS transistor having a source connected to a drain of the first PMOS transistor, a gate connected to the input/output terminal, and a drain outputting the first control signal; and an NMOS transistor having a drain connected to the drain of the second PMOS transistor, a gate connected to the control terminal, and a source receiving a ground supply.
The signal buffer according to the first and second aspects of the present invention may further comprise an inversion delay for inverting and delaying the signal applied to the input/output terminal and for providing the inverting delayed signal to the control terminal, and a latch circuit for latching the first control signal.
According to another aspect of the present invention, a signal line driving circuit comprises an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer.
Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal.
The first signal buffer, corresponding to the signal buffer according to the first aspect of the present invention, has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal.
The second signal buffer, corresponding to the signal buffer according to the second aspect of the present invention, has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.
The signal line driving circuit may include any one signal buffer of the first and second signal buffers. In addition, the signal line driving circuit may include an inversion buffer rather than the pulse generator. Here, the inversion buffer performs inversion buffering of the input signal and generates an inverted signal which is applied to the control terminals of the first and second signal buffers.
According to a third aspect of the present invention, there is provided a signal line driving circuit comprising an inversion buffer, an inversion delay, a first signal buffer, and a second signal buffer.
Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The inversion delay has an input terminal connected to a node of the signal line to invert and delay a signal propagating on the signal line at the node to provide a first control signal.
The first signal buffer, corresponding to the signal buffer according to the first aspect of the present invention, has a control terminal that receives the first control signal and an input/output terminal coupled to the node of the signal line. The first signal buffer reduces the rising transition time of the signal propagating on the signal line at the node in response to the first control signal.
The second signal buffer, corresponding to the signal buffer according to the second aspect of the present invention, has a control terminal that receives the first control signal and an input/output terminal coupled to the node of the signal line. The first signal buffer reduces the rising transition time of the signal propagating on the signal line at the node in response to the first control signal.
The signal line driving circuit according to the third aspect of the present invention may optionally include any one signal buffer of the first and second signal buffers.
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