The present invention relates generally to integrated circuit (IC) devices and, more particularly, to structure and method for improving storage latch susceptibility to single event upsets (SEUs).
The effects of radiation on integrated circuits have been known for many years. These effects may be broken down into two broad categories, namely “total dose effects,” in which an integrated circuit gradually deteriorates due to the accumulated effect of all the damage done to the crystal structure by the many particles incident thereupon, and “single event effects” in which a single particle (either through its exceptionally high energy or through the accuracy of its trajectory through a semiconductor) is capable of affecting a circuit. Single event effects are varied, and most of the effects can be mitigated by proper layout techniques. One type of single-event effect that requires more effort to eliminate is the single event upset, or SEU, in which the contents of a memory cell are altered by an incident particle.
SEUs belong to a class of errors called “soft-errors” in that they simply reverse the logical state of devices such as storage latches. Although SEUs do not, in and of themselves, physically damage a circuit, they are capable of propagating through combinational logic and being stored in memory. In turn the operation of a circuit may be altered in such a way so as to cause an error in logic function, potentially crashing a computer system. SEUs present significant reliability concerns in terrestrial and space environments.
A number of SEU-hardening techniques have thus been developed. These techniques may be categorized into three general types: (1) technology hardening, in which changes are made to the fabrication processes of the chip such that a circuit is less likely to collect the critical charge required to reverse its state (e.g., using Silicon-on-Sapphire or SOS substrates to reduce the charge build-up due to incident particles); (2) passive hardening in which passive components such as capacitors or resistors are added to a circuit to either slow it down or to increase the charge required to reverse its state; and (3) design hardening in which redundancy and feedback elements are added to a circuit to make it more immune to single events.
Technology hardening is generally not commercially viable due to the expense associated with designing and improving existing fabrication methods, which can cost billions of dollars to develop in the first place. Moreover, passive hardening is not efficient. Although it is a workable solution, it represents a deliberate slowing-down of information processing, which is at odds with the clear industry objective to speed up processing. Passive hardening is also not scalable, meaning that fabrication changes necessarily result in passive hardening redesign and re-testing.
With respect to design hardening, various circuit solutions exist to reduce SEU sensitivity in SRAM cells and sequential logic circuits, such as adding series resistance to the cross-coupling, adding capacitance to internal storage nodes, and storing the data state on multiple internal nodes. However, all known architectural and circuit SEU mitigation techniques have area, performance and power penalties. Each application thus requires careful analysis to determine the tradeoff between the level of SEU protection and acceptable cost. There is great interest in SEU mitigation solutions with reduced area penalty (to avoid increases in chip cost) and power penalty (e.g. in mobile and space applications, where power consumption is a primary concern). However, conventional approaches to adding internal node capacitance have resulted in write performance degradation and/or circuit area penalties. Accordingly, there is a need to provide increased internal node capacitance of SRAM cells, latches, and other sequential logic circuits for SEU robustness, while at the same time minimizing degradation in performance due to the presence of the increased capacitance.
USPTO Backgrounds
USPTO Backgrounds