1. Field of the Invention
This invention relates to an output buffer circuit for semiconductor integrated circuits.
2. Prior Art
In general, an LSI (Large Scale Integrated Circuit) has a large load connected to an output terminal thereof. Therefore, in order to drive such a large load, an output buffer circuit having a large drive power is usually provided in the output block of the LSI.
FIG. 1 shows the construction of a conventional output buffer circuit.
As shown in the figure, the output buffer circuit is comprised of a two-input NAND gate NAN1, an inverter IN1, a two-input NOR gate NOR1, a P-channel MOS transistor MP1, and an N-channel MOS transistor MN1.
The P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 provide a sufficient drive power for driving an external load.
In the output buffer circuit constructed as above, if an input signal i changes from a low level to a high level when an enable signal en is at a low level, an output signal na1 from the two-input NAND gate NAN1 changes from a high level to a low level, and an output signal nr1 from the two-input NOR gate NOR1 also changes from a high level to a low level. Accordingly, the P-channel MOS transistor MP1 is switched from an OFF-state to an ON-state, while the N-channel MOS transistor MN1 is switched from the ON-state to the OFF-state. As a result, an output signal x changes from a low level to a high level.
During this transition of the output signal from the low level to the high level, there occurs a time period when the P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 are both held in the ON-state simultaneously. During this time period, a large current (through current) flows between a power supply VDD and ground GND, which generates noise on the power line and the ground line, and can lead to erroneous operation of the LSI.
The above problem will be described more in detail with reference to FIG. 2.
FIG. 2 shows the P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 each having an inductance L connected thereto.
These inductances L are parasitic inductances interposed, respectively, between the power supply VDD outside the LSI and the source of the MOS transistor MP1 inside the LSI and between the ground GDN outside the LSI and the source of the MOS transistor MN1 inside the LSI. When the through current i flows between the P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 each connected to the corresponding inductance L, a spike noise is generated across each of the inductances L.
The noise level of the spike noise can be expressed in terms of a spike voltage (xcex94V) by the following equation (1):
xcex94V=xe2x88x92Lxc2x7di/dtxe2x80x83xe2x80x83(1)
In the output buffer circuit, since the P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 each have a large load-driving power, a large through current i flows between them, which generates a large spike noise.
The generation of the big spike noise leads to erroneous operations of other circuits within the LSI.
Further, the FIG. 1 output buffer circuit suffers from a problem that the through current causes an increased current consumed by the buffer circuit.
An output buffer circuit intended for preventing generation of the through current and noise described above has been proposed e.g. by Japanese Laid-Open Patent Publication (Kokai) No. 05-327444.
FIG. 3 shows the construction of the proposed output buffer circuit.
The output buffer circuit is comprised of an input terminal 1, an output terminal 2, a pre-driver 3, a delay circuit block 4, and a final driver 5.
The final driver 5 is comprised of P-channel MOS transistors P1, P2, and N-channel MOS transistors N1, N2. The P-channel MOS transistors P1, P2 each have a source thereof connected to a positive power supply VDD, while the N-channel MOS transistors N1, N2 each have a source thereof grounded. The P-channel MOS transistors P1, P2 and the N-channel MOS transistors N1, N2 each have a drain thereof connected to the output terminal 2.
The delay circuit block 4 is interposed between the input terminal 1 and the final driver 5 and composed of a delay block 6, a two-input NAND gate 11, and a two-input NOR gate 12. The delay block 6 delays an input signal thereto by a predetermined delay amount td. An output signal from the delay block 6 is delivered to one of the input terminals of the two-input NAND gate 11 and one of the input terminals of the two-input NOR gate 12. The other input terminal of the two-input NAND gate 11 and that of the two-input NOR gate 12 are each supplied with an input signal i. The two-input NAND gate 11 supplies an output signal to the gate of the P-channel MOS transistor P2 of the final driver 5, while the two-input NOR gate 12 supplies an output signal to the gate of the N-channel MOS transistor N2 of the same.
The pre-driver 3 is interposed between the input terminal 1 and the final driver 5. The pre-driver 3 delivers a signal formed by inverting the polarity of the input signal i to the respective gates of the P-channel and N-channel MOS transistors P1 and N1 of the final driver 5.
Next, the operation of the above output buffer circuit will be described with reference to FIGS. 4A to 4J.
FIGS. 4A to 4J collectively form a timing chart which is useful in explaining the operation of the FIG. 3 output buffer circuit.
First, assuming that the input signal i changes from a low level to a high level at a time t01, the output signal from the pre-driver 3 changes from a high level to a low level (see FIGS. 4A, 4B). As a result, the P-channel MOS transistor P1 is switched from the OFF-state to the ON-state, while the N-channel MOS transistors N1 is switched from the ON-state to the OFF-state (see FIGS. 4F, 4G). Accordingly, an output signal from the final driver starts changing from a low level to a high level (FIG. 4J).
After the lapse of a delay time td from the time t01 (i.e. at a time t02), the output signal from the delay block 6 changes from a low level to a high level (see FIG. 4C). At the same time, the output signal from the two-input NAND gate 11 changes from a high level to a low level (see FIG. 4E), whereby the P-channel MOS transistor P2 is switched from the OFF-state to the ON-state (see FIG. 4H).
Consequently, the P-channel MOS transistors P1 and P2 perform additional driving operation to cause an output signal level to rise sharply.
In the output buffer circuit described above, between the time t01 at which the input signal i changes and the time t02 after the lapse of the delay time td from the time t01, there exists no time period over which the P-channel MOS transistor P2 and the N-channel MOS transistor N2 are both held in the ON-state simultaneously (see FIGS. 4H, 4I), which prevents a through current from flowing between the two transistors P2 and N2.
However, when a large capacity load connected to the output buffer circuit is to be charged or discharged, a large drive power is required upon switching between the charge and the discharge. In the above output buffer circuit, when the input signal i changes from the low level to the high level, one of the P-channel MOS transistors parallel-connected to the load, i.e. the P-channel MOS transistor P1, is switched from the OFF-state to the ON-state (see FIG. 4F), while the P-channel MOS transistor P2 is switched from the OFF-state to the ON-state after the lapse of the delay time td (see FIG. 4H).
That is, immediately after the input signal i changes as described above, the P-channel MOS transistor P1 alone can provide a drive power. Therefore, it is impossible to obtain a sufficient drive power for charging or discharging the large capacity load, which results in delayed response.
It is an object of the present invention to provide an output buffer circuit which is capable of obtaining a large drive power when the level of an input signal changes, while allowing a through current to flow in suppressed amounts.
Further, since the output signal x is at the low level, the output signal x2 from the delay block 210 is held at a high level, and the output signal a2 from the AND gate AND1 and the output signal r2 from the OR gate OR1 are also each held at a high level.
To attain the above object, there is provided an output buffer circuit comprising a pair of first and second switching elements that are connected with each other at a common junction and connected in series with a power supply, for being exclusively switched on and off in response to an input signal such that the first and second switching elements are not simultaneously on or off, to deliver an output signal corresponding to the input signal, from the common junction, a first auxiliary switching device that is connected in parallel with the first switching element, a second auxiliary switching device that is connected in parallel with the second switching element and a drive switching control block that operates when a change occurs in level of the input signal and one of the first and second switching elements is switched from an OFF state to an ON state in response to the change in level of the input signal, to deliver auxiliary drive control signals to the of the first and second auxiliary switching devices which is connected in parallel with the switched one of the first and second switching elements, for holding the one of the first and second auxiliary switching devices in an ON state over a predetermined time period.
More preferably, the first and second auxiliary switching devices are each formed by a plurality of switching elements, the output buffer circuit including a selection control signal supply device that supplies the drive switching control block with selection control signals for selecting or not selecting at least one of the plurality of switching elements to be supplied with auxiliary drive control signals, and when the level of the input signal changes to switch one of the first and second switching elements from an OFF state to an ON state, the drive switching control block delivers auxiliary drive control signals to the selected at least one of the plurality of switching elements of one of the first and second auxiliary switching devices which is connected in parallel with the switched one of the first and second switching elements, for holding the selected at least one off the plurality of switching elements in the ON state over the predetermined time period.
More preferably, the selection control signal supply device supplies selection control signal such that more of the plurality of switching elements are selected to be supplied with auxiliary drive control signal to thereby increase a speed of rise of the output signal.
Preferably, the drive switching control block includes a delay circuit that delays the output signal delivered from the common junction between the first and second switching elements, and wherein the drive switching control block delivers auxiliary drive control signal over a time period during which a level of an output signal from the delay circuit and the level of the input signal are the same as each other.
Alternatively, the drive switching control block includes a delay circuit that delays the input signal, and the drive switching control block delivers auxiliary drive control signals over a time period during which a level of an output signal from the delay circuit and the level of the input signal are the same as each other.
More preferably, the delay circuit delays the output signal delivered from the common junction between the first and second switching elements by a delay time dependent on a speed of switching operation demanded of the output buffer circuit.
More preferably, the delay circuit delays the input signal by a delay time dependent on a speed of switching operation demanded of the output buffer circuit.
The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
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