The present invention relates to semiconductor memory devices and, more particularly, to phase change memory devices and memory cell arrays thereof.
A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application 2005-120603 filed on Dec. 9, 2005, the entire contents of which are hereby incorporated by reference.
Generally, semiconductor memory devices are categorized as random access memories (RAMs) or read-only memories (ROMs). ROMs are non-volatile memory devices such as PROMs (programmable ROMs), EPROMs (erasable PROMs), EEPROMs (electrically EPROMs), and flash memory devices, which retain their stored data even when their power supplies are interrupted. Meanwhile, RAMs are traditionally volatile memory devices such as dynamic RAMs (DRAMs) and static RAMs (SRAMs), which lose their stored data when their power supplies are interrupted.
However, new types of RAMs containing nonvolatile memory devices have recently been introduced or proposed. Examples includes ferroelectric RAMs (FRAMs) employing ferroelectric capacitors, magnetic RAMs (MRAMs) employing tunneling magneto-resistive (TMR) films, and phase change memories (PRAMs) using chalcogenide alloys. Among these, the phase change memory devices are relatively easy to fabricate, and thus phase change memory devices may provide the best opportunities in the actual implementation of high-capacity, low cost nonvolatile RAMs.
FIG. 1 illustrates an example of a memory cell 10 of a phase change memory device. As shown, the memory cell 10 includes a memory element 11 and a select element 12 connected between a bitline BL and a ground voltage. In this example, the select element 12 is an NMOS transistor NT having a gate connected to a wordline WL.
The memory element 11 includes a phase change material such as germanium-antimony-tellurium (Ge—Sb—Te, also referred to as “GST”), which functions as a variable resistor (i.e., resistance being variable with heat). The phase change material is conditioned in one of two stable states, i.e., a crystalline state or an amorphous state. The phase change material changes into the crystalline state or the amorphous state, based on current supplied through the bitline BL. The phase change memory programs data therein by means of such a characteristic of the phase change material.
When a predetermined voltage is applied to the wordline WL, the NMOS transistor NT is turned on to enable the memory element 11 to receive the current supplied through the bitline BL.
In FIG. 1, the memory element 11 is coupled between the bitline BL and the select element 12. However, the select element 12 may instead be coupled between the bitline BL and the memory element 11.
FIG. 2 illustrates another example of a memory cell 20 of a phase change memory device. The memory cell 20 includes a memory element 21 and a select element 22 connected between a bitline BL and a wordline WL. The select element 22 of this example includes a diode D having an anode to which the memory element 21 is connected and a cathode to which the wordline WL is connected. When a voltage differential between the anode and the cathode of the diode D becomes higher than a threshold voltage of the diode D, the diode D is turned on to enable the memory element 21 to receive the current supplied through the bitline BL.
In FIG. 2, the memory element 21 is coupled between the bitline BL and the select element 22. However, the select element 22 may instead be coupled between the bitline BL and the memory element 21.
FIG. 3 is a graph showing temperature characteristics during programming of the phase change material (GST) illustrated in FIG. 1 and FIG. 2. In FIG. 3, a reference number 1 denotes the GST temperature characteristic during programming to the amorphous state, while a reference number 2 denotes the GST temperature characteristic during programming to the crystalline state.
As illustrated in FIG. 3, the phase change material (GST) turns to the amorphous state when it is rapidly quenched after being heated over its melting point Tm by supplied current during a time T1. The amorphous state is usually referred to as a reset state, storing data ‘1’. On the other hand, the phase change material is settled in the crystalline state when it is slowly quenched after being heated within a temperature window that higher than a crystallization temperature Tc and low than the melting point Tm during a time T2 which is longer than T1. The crystalline state is usually referred to as a set state, storing data ‘0’. The resistance in the memory cell is relatively high in the amorphous state, and relatively low in the crystalline state.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
The phase change memory cell is programmed in the reset state or set state in accordance with the magnitude and duration of a programming current applied to the cell. Generally, the phase change memory is configured to supply a predefined “reset current” for programming the memory cell in the reset state, and a predefined “set current” for programming the memory cell in the set state.
As illustrated in FIG. 3, in order to change a phase change material (GST) into a crystalline state, the magnitude and duration of set current should achieve a GST temperature ranging from Tc to Tm during a time T2. In order to change a phase change material into an amorphous state, the magnitude and duration of the reset current should achieve a GST temperature exceeding Tm during a time T1. Generally, the magnitude of the reset current is greater than that of the set current, while the duration of the reset current is less than that of the set current.
A typical phase change memory device includes a memory cell array and a writer driver. The memory cell array is connected to a wordline decoder through a wordline and to a global bitline select circuit through a global bitline. The memory cell array includes a cell region and a select region. The cell region has a plurality of memory cells, and the select region has an NMOS transistor connecting global bitlines with local bitlines. A number of memory cells are connected with a local bitline.
The write driver supplies a program current (i.e., a set current or a reset current) to a selected memory cell through a global bitline and a local bitline in a program operation. Unfortunately, parasitic resistance and parasitic capacitance present on the local bitline may prevent the write driver from supplying a sufficient program current to a selected memory cell. For this reason, programming reliability of the phase change memory device may be degraded.
USPTO Backgrounds
USPTO Backgrounds