This invention relates to programmable logic devices, and more particularly, to programmable logic devices containing programmable memory regions.
Programmable logic devices are integrated circuits that may be configured by a user to perform custom logic functions. At their most basic level, programmable logic devices are based on programmable switches or connectors. Such programmable components may be based on random-access memory, read-only memory, erasable programmable read-only memory, electrically-erasable programmable read-only memory, fuses, antifuses, ferro-electric elements, or other suitable programmable component technology.
Programmable components are typically organized as groups or regions of logic. A typical programmable logic device contains many such logic regions. In some programmable logic devices, such as the FLEX 10K programmable logic devices of Altera Corporation, these programmable logic regions are referred to as "logic array blocks." Programmable logic regions may also be referred to as "complex logic blocks." This terminology is used by Xilinx, Inc. in referring to the logic regions in their XC4000 family of programmable logic devices, as described in the 1996 Xilinx Data Book (entitled "The Programmable Logic Data Book"), which is hereby incorporated by reference herein in its entirety.
Programmable logic regions are typically arranged on a programmable logic device in a regular pattern. For example, programmable logic regions may be arranged in rows and columns. Vertical interconnections in each column are used to convey signals between the logic regions in that column. Horizontal interconnections in each row are used to convey signals between the logic regions in that row. Additional circuitry is provided to convey signals between the horizontal and vertical interconnections and to convey signals between the logic regions and the interconnections.
Logic regions may contain look-up table logic or product term logic, register logic, and other logic circuitry that allows users to create medium-sized blocks of logic such as counters, address decoders, and state machines. Multiple logic regions may be combined to create larger logic blocks. Special interconnections between adjacent logic regions facilitate the implementation of logic circuits built from chains of neighboring logic regions such as adders and multipliers.
Another type of resource available on programmable logic devices such as the FLEX 10K programmable logic device of Altera Corporation is programmable memory. Programmable memory regions are similar to programmable logic regions in that they can be configured by a user to perform various functions. Programmable memory regions may be used to perform the functions of random-access memory, read-only memory, first-in-first-out memory, and dual-port memory. Programmable memory regions may also be used to implement complex logic functions for applications such as multipliers, microcontrollers, state machines, and digital signal processors.
If desired, programmable memory regions can be programmed with a read-only pattern to create a large look-up table. This arrangement allows programmable memory regions to perform certain combinatorial functions quickly by looking up results in the look-up table, rather than by computing results using programmable logic regions.
However, the number of input and output lines to the programmable memory regions is limited. For example, the data ports of the memory regions in the FLEX 10K programmable logic devices of Altera Corporation can support data signals up to eight bits wide. If a user desires to handle signals with data widths larger than eight bits, such a device cannot be used without combining multiple programmable memory regions in parallel, which requires that address signals be routed to each of the multiple programmable memory regions that are combined. Moreover, the maximum data width that can be supported is limited to eight bits times the total number of programmable memory regions on the device.
Although the data port size of a standard programmabe memory region on a programmable logic device could be scaled up to handle larger data widths, doing so would be costly. For example, scaling up a standard eight-bit programmable memory region to handle 32 bit data would require the addition of 24 input lines and 24 output lines to the data ports. As a result, many resources would be allocated to providing the larger data ports, even though many users might not require such large data ports.
It is therefore an object of the present invention to provide a programmable logic device in which a user can effectively increase the size of the data ports of a programmable memory region using input and output resources from nearby programmable logic regions.
USPTO Backgrounds
USPTO Backgrounds