Microelectronic devices are fabricated on semiconductor wafers using a variety of techniques, e.g. including deposition techniques (CVD, PECVD, PVD, etc) and removal techniques (e.g. chemical etching, CMP, etc). During the fabrication process, various layers of metal and/or dielectric material are formed as a structure on a semiconductor wafer base, for example on a silicon wafer base.
The surface on which a given layer of metal or dielectric material is formed may have a number of topographical features which need to be coated by that layer. These topographical features may be due to the underlying topography of the semiconductor wafer, or topographical features formed on a previous layer. Examples of topographical features that may need to be coated include trenches and vias.
When a layer is formed on a surface having topographical features such as a trench or a via, voids may be formed in the resulting structure. For example, when a layer of a material is deposited on a surface having a trench, the deposited material may build up on the elongate sides of the trench until material on opposing sides of the trench meet along a centre-line of the trench, forming a seam, i.e. a line along which the regions of material on opposing sides of the trench contact each other. Voids may be formed within the trench under this seam. A plurality of voids may be distributed along the seam. Voids may be more likely to occur where the walls of the trench are not uniformly flat, e.g. where there is a protruding lip along one or more upper edges of the trench.
FIG. 1 schematically shows a cross-section through a structure formed on a semiconductor wafer base. A layer of material 1, for example copper, has been deposited on a silicon wafer base 3. The deposited layer 1 covers a trench 5 on the surface 7 of the silicon wafer base 3. During the deposition process, material 1 has built up on the elongate sides 9 of the trench 5 until material on opposing sides 9 of the trench 5 has met along a seam 11. A void 13 has been formed in the trench beneath the seam 11.
FIG. 2 schematically shows a cross-section through a structure formed on a semiconductor wafer base. Features in common with the arrangement shown in FIG. 1 are given the same reference numbers and description thereof is not repeated. A via 15 is located within the trench 5. When the layer of material 1 was deposited on the surface 7 of the silicon wafer base 3, a void 17 was formed within the via 15.
Voids such as those shown in FIGS. 1 and 2 can be detrimental to semiconductor reliability. Such voids can give rise to electrical failures during operation of a semiconductor device. Where there is a void, there may be insufficient material to allow electrical conduction, thereby producing a short in the wiring of the semiconductor device. Also, voids might give rise to current going through a smaller conductive area, which may lead to heating and eventual failure of the semiconductor device. At present, it is not possible to tell how many voids there are in a structure formed on a silicon wafer base, or to determine information about any such voids, e.g. their size or distribution within the layer or structure.
Voids formed in the structure, such as those shown in FIGS. 1 and 2, may contain liquid or gas. The liquid or gas may be material which was present when the layer was deposited on the semiconductor wafer. For example, where a layer is deposited by plating, e.g. plating of copper, a liquid is applied to the surface to be coated. In the case of copper plating, this liquid may contain sulphuric acid. Thus, when a layer of copper is plated on a semiconductor wafer it is possible that voids containing liquids such as sulphuric acid may be present in the resulting structure.
In some circumstances, pores and/or voids are preferentially introduced into a coating layer on a semiconductor wafer. When fabricating a microelectronic device it is known to apply a coating layer of a material having a lower dielectric constant relative to the dielectric constant of silicon dioxide, for example a layer of SiOC (carbon doped silicon oxide). These materials are commonly referred to as low-K (or low-k) materials. The dielectric constant of silicon dioxide is 3.9. Air has a dielectric constant of approximately 1.00005. Thus, it is possible to reduce the dielectric constant of a porous coating layer relative to the dielectric constant of silicon dioxide by increasing the porosity of the coating layer, i.e. by reducing the average density of the material in the coating layer.
Known forms of porous dielectric material used when fabricating microelectronic devices include aerogels and xerogels. A xerogel is a solid formed from a gel by drying the gel with unhindered shrinkage. Xerogels can have porosity as high as 25% or greater. An aerogel is formed when solvent is removed from a wet gel under supercritical conditions, i.e. at a temperature and pressure above the critical point of the solvent. Due to the supercritical drying, aerogels retain the highly porous structure that the gel had in the wet stage, resulting in a structure with a very low density and high porosity.
The porosity of such layers may be further increased through the use of porogens. A porogen is a piece of material incorporated into the structure of the coating layer which can subsequently be removed, e.g. by thermal treatment, to leave behind a void in the coating layer. By artificially introducing voids into the coating layer in this manner, the porosity of the coating layer is increased and the dielectric constant of the material is reduced.
Scanning electron microscopy techniques, Rutherford back-scattering spectroscopy, small-angle neutron scattering (SANS) and ellipsometric porosimetry have been used to determine the mean pore size of porous dielectric materials. It is known to evaluate the pore content of a porous material based on the adsorption/condensation of an appropriate adsorptive in the pores. From the isotherm of adsorption, i.e. a plot of the amount of adsorbed/condensed adsorptive versus the relative pressure of the adsorptive at a constant temperature, it is possible to calculate an estimate of the porosity and the porous size distribution of the porous material. Such techniques require the porous material to be exposed to an adsorptive vapour while the porous material is in a vacuum.
With porous dielectric layers, it is possible that the voids may contain solid material lining the void, liquid material or gas, for example moisture or some remaining porogen material.
In some circumstances, an air gap is preferentially introduced into a semiconductor device, e.g. to provide a layer of air between a coating layer and the semiconductor wafer. Such air gaps may contain solid material, liquid material or gas, e.g. by-products of the process used to produce the air gap.
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