1. Field of the Invention
This invention is generally directed to enhanced wafer level integrated interconnects and testing. More particularly, the invention relates to testing and packaging a fabricated wafer through a removable dielectric layer overlying chip pads on the wafer and a pattern of electrical conductors.
2. Description of the Related Art
Multi-chip modules (MCMs) and certain assemblies of single chips which are difficult to package require the availability of unpackaged integrated circuits (ICs) with a very high yield because the overall module yield is proportional to the average component yield raised to the power of components in the MCM and the MCM fabrication yield. Currently, few, if any, unpackaged ICs are commercially available that are fully tested and burned in at the wafer level or after dicing. Though ICs are tested at the wafer level, this test is usually conducted at reduced speed using a limited test set. Typically, infant mortality (i.e., failure of newly-fabricated chips) cannot be eliminated due to the lack of burn-in fixturing. An additional problem occurs when ICs are contacted using probe-cards, since the cards may cause damage to the IC pads which may render them unusable in an MCM assembly.
Interconnection is a key to the success of wafer scale integration, but as wafer size gets increasingly larger, the run lengths required to accomplish a final interconnect get very long and very resistive. This greatly reduces the speed of the IC processed, devaluing the whole wafer scale integration premise. Wafer scale integrated circuits generally incorporate redundancy in order to improve yields, and current art uses switches to select the desired sub-circuits. These switches occupy valuable space and create switch losses and a lack of uniformity of conductor path length between sub-circuits among different wafers, which causes variations in phase among circuits.
Thermal stress in wafers requires a very near temperature coefficient of expansion match to the mounting surface. Materials such as silicon packages are possible but are costly and not mechanically strong. Other materials can be used, but the fact that many pin outs are needed for a wafer scale integration design limits the options. The integration of components using different base materials, e.g., GaAs, Ge, InSb, etc., is desirable for radio frequency (RF) operation, but is difficult with generic silicon processing.
The added weight of three-dimensional HDI (high density interconnect) modules with individual substrates attached to each module is another problem. In the aforementioned U.S. Ser. No. 07/962,379, thinned stacks of HDI circuits have their substrates ground off or otherwise removed. This allows stacking of thinned layers to form a multi-level thin three-dimensional assembly that has minimal weight and volume. If the assembly is not thinned, the ability to place vias through the assembly at random is greatly limited, due to the normal thickness of the chips requiring an assembly with via holes greater than 20 mils deep. The use of unmodified ICs in a unique interchangeable layer three-dimensional HDI format is desirable.
USPTO Backgrounds
USPTO Backgrounds