Problems arise in the carrying out of level sensitive scan design (LSSD) techniques for testing integrated circuits having cross-coupled, latch-type clock driver circuits. In the test mode, the clock driver's latching function must be transparent to the test inputs so that the internal shift circuitry can be tested during the LSSD testing techniques. LSSD testing techniques have been described, for example, in U.S. Pat. No. 3,761,695 to E. D. Eichelberger, assigned to the instant assignee.
Attempts have been made in the past to provide logic circuits which are selectively transparent or which can be bypassed under certain conditions. For example, U.S. Pat. No. 4,286,173 to Oka, et al. discloses logic circuit inputs to a logic block, which can bypass the logic block by selectively turning on a control line to enable a first AND gate and disable the AND gate. Other attempts to selectively bypass logic circuits include those described in U.S. Pat. Nos. 4,241,307; 3,882,390; and 3,815,025. However none of these examples of prior art provides a selectively transparent clock driver latching circuit which is compatible with level sensitive scan design testing techniques.
USPTO Backgrounds
USPTO Backgrounds