The rapid growth and technological innovation in the semiconductor industry over the last several years has created a severe demand for testers capable of rapidly and accurately testing and evaluating the operation of semiconductor. components. The demand has been particularly acute in the testing of state-of-the-art integrated circuits, where the functional complexity and component density on such chips have grown to dimensions thought to be impossible only a few years ago.
The demand for reliable, accurate, flexible, speedy and cost effective testing of integrated circuits exists throughout the entire semiconductor industry, and exists at all levels of the design and development, manufacture, and use of such circuits in the industry. The designer requires accurate integrated circuit test equipment to evaluate his new innovations and changes made to existing circuitry. The manufacturer requires accurate, repeatably, reliable and efficient test equipment to evaluate his integrated circuits at various stages of production, both in an unpackaged (i.e. "wafer") form as well as in the finally packaged form. The integrated circuit user requires test equipment that has the flexibility to rapidly adapt to the testing of a number of different integrated circuits, yet one that is cost effective, for evaluating, selecting and sorting the integrated circuits he receives from his suppliers and for analyzing integrated circuits that are damaged, degrade or otherwise malfunction in the particular structure or environment in which the circuits are used.
A number of different types of integrated circuit testers currently exist, which are for the most part, individually designed to accommodate the demands of a specific user. For example, very expensive test systems are available for integrated circuit manufacturers, who can justify the expense of the testing apparatus in their large-scale production facilities. On the other hand, an end user of the integrated circuit, who may use a large number of different types of such circuits, with a relatively low volume of each, has been forced to accept less expensive test equipment having significantly reduced test capability, as comared to that used by the large manufacturer. In general, an integrated circuit test apparatus universally acceptable for the demands of a designer, a manufacturer and an end user, does not presently exist in the art.
The basic function of an integrated circuit test system is to provide a test "stimulus" to the circuit being tested, and to determine or measure the "response" of that circuit to the stimulus. Such "stimulus/response" testing of integrated circuits basically takes three forms: that of DC (direct current) parametric testing; that of AC (alternating current) parametric testing; and that of functional or dynamic functional testing. A separate set of problems and considerations are present for each of the basic types of parametric and functional testing.
With regard to DC parametric testing, the stimulus/response functions that are involved operate over a broad dynamic signal range, but at relatively slow speeds (i.e. such testing is typically not speed-sensitive). The primary problems that have been associated with DC parametric testing have related to the transmission of the DC parametric signals themselves, and involve such factors as line losses, extraneous signal pickup and ground and temperature differentials. Also, simultaneous, parallel DC testing has not generally been available.
With respect to AC parametric testing, the stimulus/response functions that are involved operate across a relatively narrow dynamic range, and at high speeds. The primary problems that have been associated with AC parametric testing have involved the transmission of such signals over any appreciable distance, and include such factors as line loading and impedance effects and difficulty in minimizing skew (i.e. non-simultaniety of signals due to minute differences in signal path delays).
As integrated circuit complexity and component density have increased, so have the requirements for testing such circuits. State-of-the-art integrated circuit testers now typically test the integrated circuits under computer of microprocessor control. In such processor-controlled testing apparatus the circuitry for generating the "high integrity" test signals required for performing the DC and AC parametric testing, have generally been physically located at a position significantly remote from the actual integrated circuit being tested (referred to as the "device under test"). Typically, the DC and AC parametric signal generating circuitry is physically located in the same large console as the computer or processor which directs the testing procedures. Such testers generally use a relatively few number of circuits for generating the "high integrity" DC and AC parametric signals and "share" those circuits when testing an integrated circuit, by multiplexing the high integrity test stimuli among the plurality of pins to be tested, all under computer or microprocessor control. Due to the multiplexing nature of such test systems, they generally do not lend themselves to the simultaneous testing of multiple pins of an integrated circuit, particularly with regard to multiple pin testing of analog stimulus/response functions.
Such integrated circuit testers as described in the preceeding paragraph which have their high integrity signal producing circuitry located at a position remote from the device under test, are extremely difficult to manufacture, and are plagued by a number of problems in transmission of the high integrity signal stimulus and the response thereto, to and from the device under test. The length of cables over which such high integrity signals must pass in traveling from the remotely located console, to the situs of the device under test, significantly amplifies the previously described signal transmission problems such as line losses, extraneous signal pickup, ground and temperature differentials, line loading and impedence effects and skew minimization. In attempts to minimize the signal transmission problems, tester manufacturers use expensive end connectors and cabling and have resorted to the use of expensive materials for such cabling to reduce detrimental temperature and thermo-electric effects of the cables. Such manufacturers have typically used bulky and expensive coaxial cables and connectors for each conductor carrying a high integrity signal. Besides being expensive, such cables are difficult to work with and require considerable space and care in their use and maintenance. The manufacturers of such testers have also been required to hand-trim and accurately match large numbers of lines (conductors/cables), between the remotely located circuitry and the device under test, in an attempt to minimize skew distortion. Further, due to the length of cable over which a high integrity signal is required to travel during a testing operation, additional signal amplification and restoring circuitry often becomes necessary to restore the high integrity signals as close as possible to their initial conditions. Each time a high integrity signal of such test systems is acted upon or modified by such restoring or filtering circuitry, the probability of introducing inaccuracies into the signal (i.e diminishing its integrity) significantly increases, thereby reducing the overall effectiveness, accuracy and test repeatability of the entire test system.
The present invention overcomes most of the abovementioned shortcomings of prior art integrated circuit test systems, and is suitable for use in testing integrated circuits either in their "wafer" or packaged "chip" form. The integrated circuit tester apparatus of the present invention provides flexibility of use for all phases of the semiconductor industry (i.e designers, manufacturers and end users). The test apparatus of the present invention retains the complex test programing capabilities offered by computerized testing, while practically eliminating the problems heretofore associated with the transmission and handling of high integrity test signals during the testing operation. The present invention enables the manufacturer of integrated circuit testers to use conventional, readily available and relative inexpensive connector and circuit board technology in the manufacture of the integrated circuit tester, in a manner that significantly reduces the cost of the testing apparatus and provides repeatability of signal integrity not only during a particular test sequence, but from tester to tester. The present invention generates and uses high integrity DC and AC parametric signals "at" the integrated circuit test site itself, thus minimizing signal transmission problems that have heretofore hampered integrated circuit tester apparatus, providing significantly improved performance in each of the areas of accuracy, line leakage, line losses, line impedence miss-match, crosstalk, noise rejection and skew.
USPTO Backgrounds
USPTO Backgrounds