The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes.
The complexity of ICs and the number of devices incorporated in ICs are continually increasing. As the number of devices in an IC increases, the size of individual devices decreases. Device size in an IC is usually noted by the minimum feature size, that is the minimum line width or the minimum spacing that is allowed by the circuit design rules. As the semiconductor industry moves to a minimum feature size of 45 nanometers (nm) and even smaller, the performance of individual devices degrades as the result of scaling. As new generations of integrated circuits and the transistors that are used to implement those integrated circuits are designed, technologists must rely heavily on non-conventional elements to boost device performance.
The performance of an MOS transistor, as measured by its current carrying capability, is proportional to the mobility of the majority carrier in the transistor channel. It is know that applying a longitudinal stress to the channel of an MOS transistor can increase the mobility; a compressive longitudinal stress enhances the mobility of majority carrier holes and a tensile longitudinal stress enhances the mobility of majority carrier electrons. It is known, for example, to create a longitudinal compressive stress to enhance the mobility of holes in P-channel MOS (PMOS) transistors by embedding silicon germanium (eSiGe) adjacent the transistor channel. To fabricate such a device a trench or recess is etched into the silicon substrate in the source and drain areas of the transistor and the trench is refilled by using selective epitaxial growth of the SiGe. Simply increasing the germanium content of the eSiGe to increase the stress, however, is not entirely successful as increased germanium content results in increased SiGe loss from the surface of the embedded region, agglomeration of the metal silicide formed on the embedded region to reduce contact resistance to the source and drain areas, and increased stress relaxation of the embedded material as the transistor undergoes the more conventional steps encountered in fabricating the IC.
Accordingly, it is desirable to optimize methods for fabricating stress enhanced MOS transistors. In addition, it is desirable to provide an optimized stress enhanced MOS transistor that avoids the problems attendant with conventional transistor fabrication. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
USPTO Backgrounds
USPTO Backgrounds