The present invention relates to a data retrieval system. More specifically, the invention provides a system for retrieving data from a data storage device by providing different portions of the data address during different clock cycles.
Various cache memory systems are known that retrieve data from a data storage device using a tag memory. The data storage device stores data that may be requested by a central processing unit (CPU) or other processing device. The tag memory stores the addresses of the data contained in the data storage device. Additionally, comparison logic or a controller is used to determine whether a particular address is contained in the data storage device by analyzing the information stored in the tag memory.
Different types of mapping methods may be used in a cache memory system, such as direct mapping, fully associative mapping, and set-associative mapping. In direct-mapped cache memory, each location at a data source can be mapped to a single, unique location in the cache memory. In a fully associative cache memory, each location at a data source may be mapped to any location in the cache memory. In a set-associative mapping, the cache memory is divided into a number of xe2x80x9cwaysxe2x80x9d, each way having a predetermined number of entries. A location at a data source may be mapped to any one entry of a xe2x80x9csetxe2x80x9d of entries, each entry of the set being located in a different way. For example, in a 4-way, set-associative cache memory, a location X at the data source may be mapped to the Mth entry of any one of ways 0, 1, 2, or 3, depending on availability.
As processing requirements increase, clock frequencies in various types of data processing systems also increase. Increased clock frequencies result in shorter time periods for each clock cycle. Thus, an activity or procedure that was previously performed in one clock cycle may require two or more clock cycles to complete if the clock frequency is increased significantly. To maintain a single clock cycle execution time, the affected device may select a newer manufacturing process technology that provides faster execution (e.g., faster data access from a memory array). However, newer manufacturing process technologies may be expensive to implement.
It is therefore desirable to provide a system that allows for increased clock frequencies while maintaining the same number of execution cycles and using the same manufacturing process technology.
Embodiments of the present invention provide a data retrieval system that receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device.
USPTO Backgrounds
USPTO Backgrounds