1. Field of the Invention
The present invention relates to a structure of a semiconductor wafer and methods of making integrated semiconductor chips.
2. Background of the Related Art
FIG. 1 is a plan view of a semiconductor wafer. As shown therein, a plurality of semiconductor chips 12 are formed in the wafer 10 at regular intervals. The wafer 10 is divided into a plurality of semiconductor chips 12 by a cutting process.
FIG. 2 is an enlarged diagram of the circled area shown in FIG. 1. As shown in FIG. 2, chip scribe lanes 14 are formed between the areas of the wafer 10 that will become semiconductor chips 12. Each of the chip scribe lane 14 has a minimum width that must be maintained so that the semiconductor chip portions are not damaged when the wafer 10 is cut into a plurality of chips 12. Typically, each chip scribe lane 14 has a width of approximately 150 .mu.m.
On each of the semiconductor chips 12, there are a plurality of bonding pads 16, which may be electrically connected to external pins or leads of a lead frame (not shown). Also, a plurality of wafer probing pads 18 are also formed on each chip 12. The bonding pads 16 and probing pads 18 typically have dimensions of approximately 100 .mu.m.times.100 .mu.m. The wafer probing pads 18 are for testing the semiconductor chip portions of a wafer before the wafer is cut into a plurality of semiconductor chips 12.
On a background art wafer 10, both the chip bonding pads 16 and the wafer probing pads 18 are formed on the areas of the wafer 10 corresponding to each of the semiconductor chips 12. The pads 16, 18 cannot be made smaller than a predetermined size. This makes it difficult to plan the layout of a highly integrated chip having many bond pads. The more bond pads one attempts to provide on the semiconductor chip, the harder it becomes to fit all the bond pads on the available area. This task is made even more difficult if the chip must also have a plurality of probing pads 18. Also, in a background art wafer 10, the wafer probing pads 18 are formed over internal circuits of the semiconductor chips 12. When a probing tip contacts a probing pad 18 to test a condition of a semiconductor chip, the internal circuits below the probing pad may be affected.
USPTO Backgrounds
USPTO Backgrounds