In electronic circuits, designers are faced with the challenge of transmitting signals over long distances on integrated circuits for instance. This problem is exacerbated by the increasing clock speed of integrated circuits and the increased complexity of the circuits. One example of this problem is the read path signals of a memory core integrated circuit.
FIG. 1 shows an exemplary embodiment of conventional solution 10 to the read path problem in a memory core. The diagram shows the signal path of a strobe global word line input (gwlstrobe) 12 through a number of RC (resistance capacitance) delays 14, 16 to a buffer 18. The output 20 of the buffer 18 is the global strobe buffer signal (gwlstrbuf). This signal 20 is distributed to the memory array and used as a timing signal for the local amplifiers 22, 24, 26. The rising edge of the global strobe buffer signal 20 causes the local amplifier strobe circuits 28, 30, 32 to trigger and enable on the local amplifiers 22, 24, 26. The local amplifiers 22, 24, 26 store the correct logic level based on the bit line differential bl 34 and blb 36. The local amplifiers 22, 24, 26 then drive the gdrd (global read data) lines 38, 40. The output register 42 must latch before the equalization circuit 44 resets the values on the gdrd lines 38 & 40 and before the local amplifier 22, 24, 26 are turned off by the falling edge of the global strobe buffer 20 signal. Failure of these timing requirements can cause virtual data or a crowbar situation for the local amplifiers 22, 24, 26. One solution is to increase the time the local amplifiers have to present the data to the gdrd lines, however this slows down the read access time.
Thus there exists a need for a read path acceleration system that allows fast access of the data without the risk of virtual data or crowbar situations.
USPTO Backgrounds
USPTO Backgrounds