The present invention relates generally to a method of dividing a wafer and a method of manufacturing a semiconductor device, and more particularly to manufacturing steps of dicing semiconductor elements formed in a wafer into chips and sealing the chips in packages, thereby miniaturizing and thinning semiconductor packages and increasing the diameter of the wafer to be used.
The manufacturing steps for semiconductor devices are generally classified into steps for patterning various semiconductor elements in a wafer (semiconductor substrate) and steps for dicing the respective semiconductor elements formed in the wafer into chips and sealing the chips in packages. Recently, the diameter of a wafer has been increased to reduce the manufacturing cost, and there has been a demand for a decrease in size and thickness of packages in order to enhance the packaging density. In the prior art, in order to seal a semiconductor chip in a thinned package, a bottom surface of a wafer, which is opposite to a pattern formation surface (major surface) of the wafer, is lapped by a grindstone and polished by free grind grains to thin the wafer prior to dicing the wafer into chips. Then, the wafer is diced. At the time of lapping, an adhesive sheet or a resist is coated to the pattern formation surface of the wafer in order to protect the pattern formation surface. Thereafter, grooves are formed in dicing line areas provided on the major surface of the wafer. These grooves are formed by means of a diamond scriber, a diamond blade, a laser scriber, etc. The dicing step is carried out by a half-cut method in which the wafer, as a single body, is diced to 1/2 of the thickness of the wafer or diced until the remaining wafer becomes about 30 .mu.m thick; a half-cut method in which the wafer is diced similarly, with an adhesive sheet attached to the bottom surface of the wafer; or a full-cut method in which the wafer is diced throughout the thickness thereof while the adhesive sheet is cut to a depth of 20 to 30 .mu.m. The half-cut method requires another dividing step. When the wafer, as a single body, is used, the wafer is sandwiched between soft films, and an external force is applied by a roller or the like, thus dividing the wafer. When the wafer is attached to the adhesive sheet, an external force is applied on the sheet, thus dividing the wafer. The divided chips are separated from the sheet in the following manner. The bottom surface of the sheet is pushed up by a pickup needle provided on a die bonding device. The needle penetrates the sheet and comes in direct contact with the bottom surface of each chip. The needle is further raised and the chip is separated from the sheet. The surface of the separated chip is held by a tool called "collet" and the chip is mounted on an island of a lead frame. Then, the pads of the chip are electrically connected to inner lead portions of the lead frame by means of wire bonding, and the chip is sealed in a package. The chip may be mounted on the island, for example, by a method in which a conductive paste is coated on the island in advance, a method in which a gold-silicon eutectic is used, or a method in which a thin film is deposited on the bottom surface of the wafer and the chip is mounted by using solder.
FIGS. 1 to 7 illustrate in detail an example of the above-described conventional wafer dividing method and semiconductor device manufacturing method. FIG. 1 illustrates a step of attaching a surface protection tape on a wafer; FIG. 2 a step of lapping and polishing the bottom surface of the wafer; FIG. 3 a step of separating the surface protection tape; FIGS. 4A and 4B steps of fixing the wafer on a fixing sheet; FIG. 5 a step of dicing the wafer; FIG. 6 a step of picking up separated chips; and FIG. 7 a die bonding step.
As is shown in FIG. 1, the bottom surface of a wafer 1 is fixed on a porous chuck table 2. By rotating and moving an attachment roller 4 in the direction indicated by the arrow, a protection tape 3 is attached on a pattern formation surface (major surface of wafer 1) 1' of the wafer 1. Various semiconductor elements are formed in the pattern formation surface 1' of wafer 1. Subsequently, as shown in FIG. 2, the pattern formation surface 1', on which the protection tape 3 is attached, is situated downward and fixed on a chuck table 5. The bottom surface of the wafer 1 is lapped and polished to a predetermined thickness (i.e. a thickness of a finished chip) by means of a grindstone 6. As is shown in FIG. 3, a tape 7 for separating the protection tape 3 is attached to the protection tape 3, and the protection tape 3 is separated from the pattern formation surface 1'. A flat ring 8 is fixed on a wafer fixing sheet 9, as shown in FIG. 4A. With the slack or wrinkles of the sheet 9 removed, the wafer 1 is fixed on the sheet 9 within the opening of the flat ring 8, as shown in FIG. 4B. The sheet 9 on which the wafer 1 is fixed and the flat ring 8 are fixed on a dicing chuck table 10. The wafer 1 is diced (full-cut) by a dicing blade 11 into individual chips 12 (see FIG. 5). As is shown in FIG. 6, a pickup needle 13 is penetrated through the sheet 9 from the bottom thereof and put in contact with the bottom surface of each chip 12. The chip 12 is pushed by the needle 13 and separated from the sheet 9. The separated chip 12 is mounted on an island 14 of a lead frame, as shown in FIG. 7, by using a die bonding adhesive such as a conductive paste. Thereafter, although not shown, inner lead portions of the lead frame are wire-bonded to pads of the chip 12, and the resultant structure is sealed in a package formed of a resin or ceramic. Thus, the manufacture of a semiconductor device is completed.
The above-described wafer dividing method and semiconductor device manufacturing method, however, have the following problems (a) to (c).
(a) The wafer tends to be broken while it is thinned by lapping. Even if the wafer is lapped with the protection tape being attached, the wafer may warp due to distortion in the lapping. As a result, the wafer may be caught during transfer within the lapping apparatus and may be broken. Since the strength of the wafer decreases as the thickness of the wafer decreases or the diameter thereof increases. If the wafer body, after it is thinned, is transferred for various processes as in the prior art, the possibility of breakage increases. For example, when the wafer is 400 .mu.m thick, it can withstand a load of about 1.6 Kgf/mm.sup.2. However, if the thickness is decreased to 200 .mu.m, the breaking strength of the wafer decreases to 1/4 or 0.4 Kgf/mm.sup.2.
(b) Since the two sheets, one for protecting the pattern formation surface and the other for fixing the wafer at the time of dicing, are used, the attaching and separating steps for the two sheets are required. Consequently, the cost for material increases and the number of manufacturing steps also increases.
(c) The degree of chipping on the bottom side of the wafer increases when the wafer is diced, resulting in a decrease in the breaking strength of the chip. Conventionally, transistors, resistors and capacitors for monitoring various characteristics (hereinafter referred to as "TEG" (Test Element Group)) are arranged within the chip. Recently, however, the TEG is arranged on dicing lines for the purpose of a higher integration density. As is well known, the devices of the TEG are formed of oxide films, aluminum, etc. When the devices of TEG are diced by using a diamond blade, the binding of the grindstone of the blade tends to easily occur and the cutting performance deteriorates. Thus, when the TEG is arranged on the dicing lines, the degree of chipping on the bottom side of the wafer further increases. In general, the semiconductor substrate is formed of a fragile material such as silicon or GaAs. If a crack occurs, the breaking strength of the wafer decreases.
As has been described above, the conventional wafer dividing method and semiconductor device manufacturing method have the problem in that the wafer tends to be broken while it is being thinned by lapping or transferred. In addition, since the two sheets for protecting the pattern formation pattern and holding the wafer are required, the cost for material increases and the number of manufacturing steps increases. Moreover, the degree of chipping on the bottom side of the wafer increases when the wafer is diced, and the breaking strength of the chip decreases.
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