1. Technical Field
The disclosed embodiments relate to symmetric load delay cells such as are found in voltage-controlled oscillators (VCO) and current-controlled oscillators (ICO).
2. Background Information
Current-Controlled Oscillators (ICOs) see use in many circuits such as, for example, Phase-Locked Loops (PLL) within clock signal generators that supply clock signals to digital processors. ICOs sometimes also see use in local oscillators of radio receivers and radio transmitters and in other circuits. FIG. 1 (Prior Art) is a simplified diagram of one example of a simple PLL 1. PLL 1 includes a Voltage-Controlled Oscillator (VCO) 2 that in turn includes a voltage-to-current converter 3 and an ICO 4. The local oscillator (LO) signal output by ICO 4 is frequency divided by a loop divider 5. The resulting divided-down feedback signal 6 is phase-compared with respect to a reference clock signal XO by a phase detector 7. Phase detector 7 outputs an error signal that is processed by a charge pump 8 and loop filter 9 to generate a signal 10 that controls VCO 2. The feedback control loop operates to phase-lock the feedback signal 6 to the reference clock signal XO. By setting the frequency control value by which loop divider 5 divides, the frequency of the local oscillator signal LO can be set to have a desired frequency over a frequency tuning range.
FIG. 2 (Prior Art) is a simplified diagram of ICO 4 of FIG. 1. ICO 4 actually includes two current-controlled oscillators ICO#1 11 and ICO#2 12 because a single current-controlled oscillator of this type would not have an adequately wide tuning range. ICO 4 also includes two VCO buffer circuits 13 and 40 and a two-to-one digital logic multiplexer 41. Each VCO buffer circuit converts a differential ICO output signal into a single-ended digital signal. In the example of FIGS. 1 and 2, the overall ICO 4 is tunable to generate an output signal LO that ranges from approximately 400 MHz to 1.3 GHz. ICO#1 11 and VCO buffer circuit 40 are used when the LO signal is to be of a frequency in the 400 MHz to 800 MHz range, whereas ICO#2 12 and VCO buffer circuit 13 are used when the LO signal is to be of a frequency in the 800 MHz to 1.3 GHz range. Depending on the frequency of the desired output signal LO, one of the ICO 11 or 12 is enabled and other is disabled. Multiplexer 41 is controlled to output the output signal of the appropriate VCO buffer circuit as the single-ended local output signal LO.
FIG. 3 (Prior Art) is a more detailed diagram of ICO#1 11 of FIG. 2. This particular ICO circuit is ring oscillator and involves a bias control circuit 14, and a plurality of delay cells 15-19. The delay cells have differential signal inputs and differential signal outputs. ICTL signal 37 is input control signal ICTL 20 received via transistor 38 of FIG. 2 from the voltage-to-current converter 3 of FIG. 1.
FIG. 4 (Prior Art) is a diagram that illustrates bias control circuit 14 and delay cell 15 in further detail. All the delay cells of FIG. 3 are of similar topology. Delay cell 15 includes a pair of circuits 21 and 22 referred to as “symmetric loads”. The first symmetric load 21 includes a current source-connected transistor (CSCT) 23 and diode-connected transistor (DCT) 24. The second symmetric load 22 includes a current source-connected transistor (CSCT) 25 and diode-connected transistor (DCT) 26. Delay cell 15 also includes a tail current source transistor 28 and two current steering switching transistors 29 and 30. Tail current transistor 28 pulls a substantially fixed control current ICTL from node N3. As the differential input signal (VIP minus VIN) between inputs nodes 31 and 32 switches, current ICTL is steered to flow through the first symmetric load, and then through the second symmetric load, and back again. The differential output signal VOP minus VON present between nodes N2 34 and N1 33 is output via leads 36 and 35 to the next delay cell in the ring of delay cells.
FIG. 5 (Prior Art) illustrates operation of delay cell 15 during a first portion of a switching cycle. Switching transistor 29 is relatively conductive and switching transistor 30 is relatively nonconductive. The voltage on node N1 is pulled down to be lower than the voltage on node N2. The voltage of the output signal therefore increases as capacitor 39 charges. Resistor symbol R1 represents the parallel equivalent effect resistance of the first symmetric load 21. Resistor symbol R2 represents the parallel equivalent effect resistance of the second symmetric load 22.
FIG. 6 (Prior Art) illustrates operation of delay cell 15 during a second portion of the switching cycle. Switching transistor 29 is relatively nonconductive and switching transistor 30 is relatively conductive. The voltage on node N2 is therefore pulled down to be lower than the voltage on node N1. The voltage of the output signal therefore decreases as capacitor 39 discharges.
FIG. 7 (Prior Art) is a simplified waveform diagram that illustrates how the differential output signal between nodes N2 and N1 oscillates up and down as the switching transistors 29 and 30 are controlled to be on and off from cycle to cycle. The lower swing limit of the output signal is referred to as the Lower Swing Limit Voltage (LSLV). The upper swing limit of the output signal is approximately the high supply voltage VDD of the circuit. For additional information on a delay cell of this type involving symmetric loads see the article “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, by John G. Maneatis.
The frequency of oscillation of the ring oscillator is changed by changing the input control current ICTL. The circuit is therefore referred to as a current-controlled oscillator.
If control current ICTL supplied to bias control circuit 14 is increased, then the current ICTL pulled through the tail transistor 28 increases. Also, the PBIAS control voltage decreases. The decrease in the PBIAS control signal reduces the effective resistance REFF of the first and second symmetric loads 21 and 22. The reducing of the effective resistance REFF reduces the RC delay through the delay cell, thereby increasing the frequency of oscillation FOSC. Similarly, decreasing control current ICTL supplied to bias control circuit 14 causes a decrease in the frequency of oscillation FOSC.
Although a ring oscillator of this type works well in certain applications, it may have an undesirably narrow frequency tuning range. As the input control current ICTL increases, the voltage swing of the output signal between nodes N2 and N1 increases. The lower swing limit voltage LSLV drops lower and lower as ICTL increases and increases. Because the lower voltage limit of the output signal has a lower voltage limit, the frequency tuning range of the ring oscillator circuit is effectively limited.
FIG. 8 (Prior Art) is a chart that illustrates how ICO#1 is only usable over a limited frequency tuning range up to 800 MHz because at the upper input control current limit of ICTLMAX the voltage swing of its output signal has reached its maximum allowable voltage swing. Note in FIG. 8 that the dashed line representing the voltage swing has reached the MAX ALLOWABLE VOLTAGE SWING value. As a result, if the frequency tuning range of the overall ICO 4 of FIG. 1 is to extend above 800 MHz, then a second ICO#1 must be provided. The circuit of FIG. 2 therefore includes ICO#2. In addition, as FIG. 8 illustrates, the change in frequency of oscillation FOSC is significantly non-linear with respect to changes in input control current ICTL. Note that the solid line representing the relationship of FOSC to ICTL is not a straight line, but rather is curved. At the upper end of frequency operation of an ICO of this type, the input control current ICTL must be increased a relatively large amount in order to increase the oscillation frequency FOSC a relatively small amount. An improved circuit is desired.
USPTO Backgrounds
USPTO Backgrounds