1. Field of the Invention
The present invention relates to a lead frame for mounting a semiconductor chip. More particularly, the invention relates to marks to be used for ascertaining the position of a semiconductor chip when the chip has been mounted on a lead frame.
2. Background Art
A lead frame is one type of semiconductor packaging material. A lead frame is constituted of a die pad on which a semiconductor chip is to be mounted, and a plurality of lead patterns to be used for electrically connecting the semiconductor chip with a circuit disposed outside a package. A semiconductor package is completed by the steps of: mounting a semiconductor chip on a die pad of a lead frame; bonding the chip to the die pad of the lead frame with an adhesive, such as resin or solder, to thereby connect leads with electrodes of the semiconductor chip by means of bonding wires; and filling the lead frame with resin sealing material after the leads have been processed.
In order to facilitate bonding operation, a semiconductor chip is desirably placed as accurately as possible in a specified position on a die pad. To this end, an operator aligns a semiconductor chip with a position while viewing a distance between the edge of the die pad and the semiconductor chip by use of a microscope. In order to facilitate the work, there has been proposed a method of forming dot-shaped marks in the neighborhoods of locations where the four corners of a semiconductor chip are to be positioned. The inventors who have filed Japanese Patent Application Laid-Open No. 291241/1994 propose a method of mark a die pad with mesh-shaped lines.
The position of a semiconductor chip is checked not only when a semiconductor chip is to be mounted on a die pad, but also in an inspection process after the semiconductor chip has been fixed to the die pad. When a mounted position is checked in the inspection process, a determination must be made as to whether or not positional accuracy has satisfied a predetermined specification. FIG. 10 is a view for describing the determination method, showing a semiconductor chip 3 mounted on a die pad 5 of a lead frame 2 when viewed from the top. As illustrated, according to the conventional method, after the semiconductor chip 3 has been mounted, an inspection operator uses a microscope to determine a distance L1 between the edge of the die pad 5 and the edge of the semiconductor chip 3 with respect to direction Y, and a distance L2 between the edge of the die pad 5 and the edge of the semiconductor chip 3 with respect to direction X. On the basis of the thus-determined distances, the inspection operator makes a determination as to whether or not the accuracy of a mounted position of the semiconductor chip has satisfied a predetermined specification.
The above-described measurement imposes a great workload on the inspection operator and is unsuitable for a mass-production process. Moreover, a measurement method varies according to the geometry of a die pad, so that an inspection operator must learn a new measurement method for each type of die pad.
Measurement of a distance relative to the edge of the die pad is based on the premise that a semiconductor chip is smaller than a die pad. For this reason, if a semiconductor chip is mounted on a die pad which is smaller in width than the chip, appropriate inspection and evaluation operations cannot be performed.
USPTO Backgrounds
USPTO Backgrounds