The present invention relates to a clock signal generation circuit. In particular, the present invention relates to a clock signal generation circuit capable of generating a plurality of clock signals having frequencies different to each other.
In general, a signal processing circuit disposed in a semiconductor integrated device (referred to as an LSI) is operated at a clock signal with a high frequency when the signal processing circuit needs to perform a high speed processing. On the other hand, when the signal processing circuit does not need to perform a high speed processing, the signal processing circuit is operated at a clock signal with a low frequency. Accordingly, it is possible to perform the high speed processing or reduce power consumption.
Further, an oscillation circuit is disposed in the LSI for generating the clock signal described above. The oscillation circuit may include a crystal ceramic oscillation circuit, a PLL (Phase Locked Loop) oscillation circuit, and a CR (Capacitor Resistor) oscillation circuit formed of a capacitor and a resistor. The CR oscillation circuit is characterized to have a shorter waiting period, from when the CR oscillation circuit is turned on to when the oscillation frequency of the CR oscillation circuit is stabilized, as compared to the crystal ceramic oscillation circuit or the PLL oscillation circuit.
Although the PLL oscillation circuit has a longer waiting period as compared with the CR oscillation circuit, the PLL oscillation circuit is characterized to be capable of generating a clock signal with a higher frequency. In the crystal ceramic oscillation circuit, the characteristics of a crystal determines the oscillation frequency thereof. Accordingly, it is difficult to change the oscillation frequency. However, the crystal ceramic oscillation circuit is characterized to be capable of generating a clock signal with a higher frequency.
Patent Reference has disclosed a conventional clock signal generation circuit. In the conventional clock signal generation circuit, the CR oscillation circuit, the PLL oscillation circuit, and the crystal ceramic oscillation circuit described above are combined, so that the characteristics thereof are effectively utilized. Accordingly, it is possible to reduce the waiting period and power consumption.
Patent Reference Japanese Patent Publication No. 2001-344039
In the conventional clock signal generation circuit disclosed in Patent Reference, the crystal oscillation circuit is provided for generating a clock signal CLK1 with a low frequency, so that the clock signal CLK1 is supplied to the signal processing circuit described above. The CR oscillation circuit is provided for generating a first clock signal CLK11 with a high frequency. Further, the PLL oscillation circuit is provided for generating a second clock signal CLK12 with a high frequency according to the clock signal CLK1 with the low frequency generated with the crystal oscillation circuit.
When the conventional clock signal generation circuit disclosed in Patent Reference starts operating, it is configured such that the first clock signal CLK11 generated by the CR oscillation circuit with the relatively short waiting period is supplied to the signal processing circuit. After the oscillation state of the PLL oscillation circuit is stabilized, instead of the first clock signal CLK11, the second clock signal CLK12 generated by the PLL oscillation circuit is supplied to the signal processing circuit.
In the conventional clock signal generation circuit disclosed in Patent Reference, the crystal oscillation circuit has the long waiting period of the long oscillation stabilization period of about a few hundreds ms, from when the crystal oscillation circuit is turned on to when the oscillation operation of the crystal oscillation circuit is stabilized. Accordingly, it is necessary to provide a long startup time to a circuit block that is operated with the clock signal CLK1 with the low frequency.
In the conventional clock signal generation circuit disclosed in Patent Reference, the crystal oscillation circuit includes a crystal oscillation element externally connected to the LSI for operating the crystal oscillation circuit. It has been known that the crystal oscillation element tends to be susceptible to an external noise such as an electromagnetic wave, vibration, and the like, or an external disturbance effect such as moisture, dust, a foreign matter, and the like. When the crystal oscillation element stops operating due to the external noise or the external disturbance, the PLL oscillation circuit stops generating the second clock signal CLK12. As a result, when the clock signal to be supplied to the signal processing circuit is switched from the first clock signal SLK11 to the second clock signal SLK12, the signal processing circuit stops operating.
In view of the problems described above, an object of the present invention is to provide a clock signal generation circuit capable of solving the problems of the conventional clock signal generation circuit. In the present invention, it is possible to quickly startup after the clock signal generation circuit is turned on, and to continuously generate a clock signal even when the external noise or the external disturbance occurs.
Further objects and advantages of the invention will be apparent from the following description of the invention.
USPTO Backgrounds
USPTO Backgrounds