1. Field of the Disclosure
The present disclosure relates to electronic devices, more particularly, to electronic devices that include insulating layers having different strains and process for forming them.
2. Description of the Related Art
Semiconductor-on-insulator (“SOI”) architectures are becoming more common as electronic and device performance requirements continue to be more demanding. Carrier mobility within the channel regions of the n-channel and p-channel transistors is an area for continued improvement. Many approaches use a dual stressor layer before forming a premetal dielectric (“PMD”) layer. The dual stressor layer can be incorporated into an electronic device as an etch-stop layer before forming the PMD layer. For the dual stressor layer, the etch-stop layer includes a tensile layer over n-channel transistor structures and a compressive layer over the p-channel transistor structures.
Some of the attempts have focused on changing the stress within the active region along the channel length direction of the transistor structure to affect drain current and transconductance of the transistor.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention. The use of the same reference symbols in different drawings indicates similar or identical items.
USPTO Backgrounds
USPTO Backgrounds