Typically a modem implements two layers of the network reference model as defined by the International Standards Organization (ISO): the physical layer and the data-link layer. A modem typically uses either one or two processors to process the physical layer and the data-link layer. A two processor arrangement is illustrated in FIG. 1, where a controller 101 performs the Data-Link layer functions and a data-pump 102 performs the Physical layer functions. Typically the controller 101 is implemented using a microprocessor, while the data-pump 102 is implemented using a Digital Signal Processor (DSP).
In both the single and two processor implementations, the cost of a modem is dependent on memory organization. The disposition of memory is often referred to as the memory hierarchy. The memory hierarchy refers to a memory system that contains both fast and slow memory. Usually the amount of fast memory is relatively small in proportion to the slow memory.
The memory system is designed so that the fast memory is referenced proportionally more often than the slower memory, substantially giving the overall modem the speed characteristics of a fast memory system. For a constant level of performance, a modem with a well-designed memory hierarchy is less expensive than a modem without this memory design.
General-purpose processors (GPP) typically are designed to work in a modem utilizing a memory hierarchy. They can have a small amount of fast cache memory that dynamically saves code and data the program is using. In comparison, DSPs do not typically employ dynamic cache memories, using, instead, dedicated RAM for memory storage. However, DSPs using dedicated RAM process data faster than GPPs, since no cycles are wasted in fetching instructions and data from slower memory.
A single-processor modem implementation that executes on a DSP typically has all of the memory high in the memory hierarchy. This provides the required speed but is expensive. In comparison, a single-process modem implementation that executes on a general-purpose processor use memory efficiently, but is slower and requires more processing cycles due to repeatedly loading/unloading fast memory with the required instructions and data located in slower memory.
USPTO Backgrounds
USPTO Backgrounds