Various applications sample signals to ascertain information from the signal. In microprocessors and other VLSI technology, for example, it is common to sample an input system clock signal for synchronization purposes. Typically, such synchronization systems employ phase locked loop (PLL) circuitry for synchronizing an internal or chip clock signal to a desired frequency. Two such synchronization approaches are a common clock input/output (I/O) system and a source synchronous I/O system. A traditional common clock distribution architecture utilizes a common clock source that supplies a clock signal for timing and latching of data. In a typical source synchronous I/O system, strobe information may be sent with data to provide a clock edge for instructing the recipient of the data when to clock or latch the data.
USPTO Backgrounds
USPTO Backgrounds