1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of designing integrated circuits.
2. Description of the Prior Art
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected. A netlist is a list of nets for a chip.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Currently, the minimum geometric feature size of a component is on the order of 0.2 microns. However, it is expected that the feature size can be reduced to 0.1 micron within the next few years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
A. IC Configuration
An exemplary integrated circuit chip is illustrated in FIG. 1 and generally designated by the reference numeral 26. The circuit 26 includes a semiconductor substrate 26A on which are formed a number of functional circuit blocks that can have different sizes and shapes. Some are relatively large, such as a central processing unit (CPU) 27, a read-only memory (ROM) 28, a clock/timing unit 29, one or more random access memories (RAM) 30 and an input/output (I/O) interface unit 31. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries.
The integrated circuit 26 further comprises a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells 32. Each cell 32 represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
The cells 32 and the other elements of the circuit 26 described above are interconnected or routed in accordance with the logical design of the circuit to provide the desired functionality. Although not visible in the drawing, the various elements of the circuit 26 are interconnected by electrically conductive lines or traces that are routed, for example, through vertical channels 33 and horizontal channels 34 that run between the cells 32.
B. Layout Design Process
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
1. Partitioning
A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore, the layout is normally partitioned by grouping the components into blocks such as subcircuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks.
The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks.
2. Floor planning and placement
This step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor planning is a critical step as it sets up the ground work for a good layout. During placement, the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
3. Routing
The objective of the routing phase is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel.
Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space.
Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes the exact channel routing of wires.
However, because of the complexity of today""s VLSI circuits, initial silicon and early revisions normally have functional and/or timing problems that require correction before the circuit can go into production. ASIC (application specific integrated circuits) layouts are typically started before the complete simulation of the design is completed. Thus, design problems may be found after silicon masks and devices have been manufactured. This is especially true in standard cell designs where the functionality of the ASIC is implemented with pre-designed cells called standard cells that each implement a logic function. To reduce the cost of fixing later discovered problems, extra standard cells called revision cells or spare cells are inserted into the design to allow logic to be changed by connecting the revision cells to the standard cells of the ASIC. These cells would be a collection of logic gates, buffers and memory elements, which would be included into the netlist and layout for the purpose of allowing future fixes via metal only changes. The benefit of this approach is that the lower mask layers do not have to be recreated and thus saves the cost of recreating new masks. In addition, this approach saves time because the approach allows wafers to be processed up to the beginning point of metal processing until the new upper level masks are recreated.
One problem with the above revision approach is that it relies on the designer to incorporate the correct mix of revision cells into the original ASIC layout. If a function is needed that is not in the original ASIC layout, then this function must be synthesized from the available revision cells. However, if the designer failed to provide the original ASIC layout with revision cells suitable for implementing the needed function, then the ASIC layout and masks may have to scrapped and new masks implementing a new ASIC layout may need to be designed. Another problem with this approach is that the designer has little or no control over the placement of the spare cells within the layout.
To address the problems listed above with the revision cell approach, a method using a small array of metal-programmable transistors created as a standard cell on the ends of cell rows has been proposed as described in U.S. patent application Ser. No. 09/019,263, entitled xe2x80x9cIntegrated Circuit and Method of Revising Integrated Circuit Functionxe2x80x9d by David M. Weber and filed on Feb. 5, 1998, incorporated herein by reference (hereinafter ""263 application).
However, the above approach is limited to placing the metal-programmable transistors on predetermined places. Therefore, a new method that provides a flexible set of revision cells which are not limited to cells chosen at layout time and not constrained to typical cell dimension is needed.
It is an object of the present invention to provide methods for designing an integrated circuit, which obviate for practical purposes the above mentioned limitations.
According to an embodiment of the present invention, an integrated circuit is first created by placing and routing standard cells of the integrated circuit. After routing the standard cells, empty spaces unused by the standard cells are extracted. After extracting the unused areas, clusters of metal-programmable transistors are inserted into the unused areas by an area-based placement/routing tool to form xe2x80x9cpondsxe2x80x9d of gates (POGs).
When design changes are desired after the formation of the integrated circuit, the metal-programmable transistors are programmed to form desired spare cells to implement the desired design changes by making changes to the upper layer masks for the integrated circuit.
The cost to implement the POGs are very minimal since the POGs are placed into the integrated circuit after placing and routing the standard cells.
USPTO Backgrounds
USPTO Backgrounds