1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method. More particularly, the present invention is used to form, for example, a bit-line contact connected to a diffusion layer of a selected transistor in a NAND cell unit.
2. Description of the Related Art
In a semiconductor device, forming a pattern with high density is important for higher integration. To this end, it has been proposed, in relation to, for example, a NAND flash memory, to arrange a plurality of contact holes for bit-line contact in a staggered form (see, for example, Japanese Patent No. 3441140).
However, opening patterns are “dense” in an oblique direction in a mask pattern for the formation of the contact holes. The reason is that openings (transparent regions) for the formation of the contact holes are arranged in a staggered form. Thus, an exposure allowance and the depth of focus are reduced, and it is difficult to hold down dimensional errors in an exposure process. That is, the NAND flash memory requires the formation of a micropattern which is a dense hole pattern having regularly arranged opening patterns and in which the holes are not orthogonally arranged in the form of a lattice. However, there has heretofore been difficulty in highly accurately forming the micropattern.
USPTO Backgrounds
USPTO Backgrounds