The present invention relates to control of separating an error portion in processors capable of simultaneously executing instruction processing procedures.
In the present field of processors, a multi-core processor implementing a plurality of cores within a single processor in order to improve a throughput and a processor capable of simultaneously executing a plurality of threads by the single core, are on the way of becoming a mainstream at the present.
Further, the high-end server is employed for an operation that is not permitted to stop in many cases, and is, if a fault occurs, required to resume the operation by quickly separating the fault-occurred element.
Moreover, there are an increased number of high-end servers which include a system controller dedicated to controlling and monitoring the whole system in many cases, and the processor is equipped with a command/interface etc as an extended version of a JTAG (Join Test Action Group) interface for the IEEE 1149.1 standard entitled Standard so that an interrupt signal to the system controller can be controlled from within the system controller.
In a conventional error process, if an error occurs in the hardware, the software (OS) is notified of the occurrence of the error through high-level interrupt, and the OS switches over to an error processing routine from the normal process. The OS executes a so-called separating process (degenerating process) of specifying the fault-occurred element by repeating an access to the hardware, setting a flag showing the fault-occurred element and disabling the fault-occurred element from being used.
USPTO Backgrounds
USPTO Backgrounds