Field of the Invention
The present disclosure relates to underfill for chip packages, and more particularly to adhesive electronics materials for integrated circuit chip packages.
Description of Related Art
Integrated circuits are generally constructed as a monolithic silicon chip. In certain constructions, interconnects attach to metalized pads arranged on the surface of the chip to electrically access electronic devices constructed within the chip, thereby realizing the benefit of circuitry within the chip.
The interconnect is typically a conductive structure formed from solder or similar material extending between metalized pads defined on the exterior surface of the chip and complementing connectors on external circuitry. Such interconnects are generally formed using the flip chip processes, e.g. controlled collapse chip connection (C4) process. Solder bumps are formed on the metalized pads on the chip top surface. The chips are then ‘flipped’ such that the solder bumps are facing the external circuitry. The chip is then aligned with the external circuitry such that the solder bumps are adjacent respective corresponding connectors on the external circuitry. The solder balls are then melted, forming electrical interconnects extending between a gap defined between the chip and external circuitry. Once the electrical interconnects are formed, an underfill composition is introduced into the gap between the chip and external circuit.
Integrated circuits and their interconnects generate heat. This heat induces thermal expansion in the chip, interconnects, and external circuitry. Since these structures are typically formed from different materials with different coefficients of thermal expansion, stresses can develop between the chip and external circuitry. Conventional underfill materials are generally polymer composites or epoxy resins that operate to buffer the electrical interconnects between chip and external circuitry from these stresses. They can include inorganic particles in a polymer matrix such as silica (SiO2) to modify the coefficient of thermal expansion (CTE) of the underfill. This allows for more closely matching the CTE of the underfill to the material used to form the electrical interconnects, thereby reducing stress within interconnects due to thermal expansion.
Conventional underfill composition and methods of packaging chips have generally been considered satisfactory for their intended purpose. However, next generation electronic applications require improved materials and chip construction. Thus, there is a need in the art for improved underfill materials and underfilling methods that have low CTE, high thermal conductivity, moderate modulus, adequate flow properties prior to cure, and tunability of the glass transition temperature of the cured composition. There also remains a need in the art for improved electronics materials, such as underfill compositions, and methods of underfilling gaps between chips and external circuit substrates that are easy to make and use. The present disclosure provides a solution for these problems.
USPTO Backgrounds
USPTO Backgrounds