1. Field of the Invention
The invention relates to a semiconductor memory device, and particularly to semiconductor memory devices, in which interconnections between a plurality of banks are reduced in number, timing of input/output of data to and from a plurality of banks is adjusted, a burn-in test using a plurality of power supply voltages at different levels can be performed, and/or an internal voltage activating word lines can be stably supplied.
2. Description of the Background Art
Referring to FIG. 45, a conventional semiconductor memory device 1000 such as a DRAM (Dynamic Random Access Memory) includes banks 1010-1013 and predecoders 1014-1017.
Each of banks 1010-1013 includes a plurality of memory cells disposed in rows and columns, a plurality of bit line pairs, a plurality of word lines, a column decoder, a row decoder and a sense amplifier.
Predecoders 1014-1017 are disposed corresponding to banks 1010-1013, respectively. Predecoders 1014 and 1016 are disposed between banks 1010 and 1012, and predecoders 1015 and 1017 are disposed between banks 1011 and 1013. Predecoders 1014-1017 produce predecode signals for selecting banks 1010-1013 based on the address input through address terminals, respectively, and output the predecode signals thus produced to banks 1010-1013, respectively. Further, predecoders 1014-1017 receive addresses AYA less than 3:0 greater than , AYB less than 3:0 greater than , AYC less than 3:0 greater than  and AYD less than 3:0 greater than , and output received addresses AYA less than 3:0 greater than , AYB less than 3:0 greater than , AYC less than 3:0 greater than  and AYD less than 3:0 greater than  to corresponding banks 1010-1013, respectively.
Banks 1010-1013 are selected by the predecode signals applied from predecoders 1014-1017. In the selected bank (one of banks 1010-1013), data is input/output to or from the memory cells designated by the addresses received from corresponding one of predecoders 1014-1017.
As described above, the conventional semiconductor memory device is provided with the plurality of predecoders corresponding to the plurality of banks, respectively. The plurality of predecoders are concentratedly arranged in one position.
Referring to FIG. 46, a conventional semiconductor memory device 1100 such as an SDRAM (Synchronous DRAM), in which data is input/output to and from the memory cells in synchronization with a clock, includes banks 1010-1013, a driver 1018 and a repeater 1019. Banks 1010-1013 are the same as those already described.
Driver 1018 receives a clock CLK from an external terminal, and produces a clock CLKQ used for output of data from received clock CLK. Driver 1018 outputs clock CLKQ thus produced to repeater 1019.
Repeater 1019 is disposed in a central portion of semiconductor memory device 1100. Repeater 1019 supplies clock CLKQ received from driver 1018 to banks 1010-1013. In this case, repeater 1019 supplies clock CLKQ to banks 1010-1013 through paths of the substantially same length. Thereby, each of banks 1010-1013 can output the data substantially in accordance with the same timing as the other banks.
Banks 1010-1013 output the data, which is read from the memory cells, to the input/output terminals (not shown) in synchronization with clock CLKQ received from repeater 1019.
In the conventional semiconductor memory device, as described above, the timing of data output from the plurality of banks is adjusted or controlled by supplying a clock produced by a driver to the respective banks via the one repeater.
For inputting or outputting data to or from each of the plurality of memory cells disposed in rows and columns, the word line disposed in the row direction must be activated, and an internally boosted voltage prepared by boosting the power supply voltage is used for this activation of the word line. A pump capacitor is used for boosting the power supply voltage to the internally boosted voltage.
FIG. 47 is a plan showing a pump capacitor, and shows, on an enlarged scale, a region A of the pump capacitor. Aluminum interconnections 1022-1027 are disposed at a first layer under aluminum interconnections 1020 and 1021 at a second layer. Bit lines BL (not shown) are disposed under aluminum interconnections 1022-1027 at the first layer, and transfer gates TG (not shown) are disposed under bit lines BL. Further, a field diffusion layer FL (not shown) is disposed under transfer gates TG. Insulating layers are interposed between aluminum interconnections 1020 and 1021 and aluminum interconnections 1022-1027, between aluminum interconnections 1022-1027 and bit lines BL, between bit lines BL and transfer gates TG, and between transfer gates TG and field diffusion layer FL.
Bit lines BL are connected through contact holes to transfer gates TG and field diffusion layer FL, and aluminum interconnections 1022-1028 at the first layer are connected to bit lines BL through contact holes 1029, 1030, 1033, 1034, 1035, 1038, 1039, 1042 and 1043. Aluminum interconnection 1020 at the second layer is connected to aluminum interconnection 1026 at the first layer through contact holes 1036. Aluminum interconnection 1021 at the second layer is connected through contact holes 1031, 1032, 1040 and 1041 to aluminum interconnections 1024, 1025, 1027 and 1028 at the first layer.
Accordingly, aluminum interconnection 1020 at the second layer is connected to transfer gate TG, which forms one of two electrodes forming the pump capacitor, and aluminum interconnection 1021 at the second layer is connected to field diffusion layer FL forming the other electrode of the pump capacitor. Thereby, the internally boosted voltage boosted by the pump capacitor is supplied via aluminum interconnections 1020 and 1021 at the second layer to the word line drivers (not shown), and the word line driver supplies the internally boosted voltage to the word line, which is designated by a row address applied from the row decoder, so that the word line designated by the row address is activated.
FIG. 48 is a plan showing one of the plurality of pump capacitors. A bit line 1051 is disposed on a transfer gate 1045 with an insulating layer (not shown) therebetween, and bit line 1051 is connected to transfer gate 1045 via eighteen contact holes 1046. Twelve contact holes 1047 are provided for connecting bit line 1051 to the aluminum interconnection (not shown), which is located at the first layer, and is formed on bit line 1051 with the insulating layer (not shown) therebetween.
Field diffusion layer 1044 is formed over transfer gate 1045, and bit lines 1049, 1050, 1054 and 1055 are arranged over a portion of the field diffusion layer not overlapping with transfer gate 1045. Each of bit lines 1049 and 1050 is connected to field diffusion layer 1044 through fourteen contact holes 1053, and each of bit lines 1054 and 1055 is connected to field diffusion layer 1044 via fourteen contact holes 1057. Twenty contact holes 1052 are provided for connecting bit lines 1049 and 1050 to aluminum interconnections (not shown), which are located at the first layer, and are formed on bit lines 1049 and 1050 with the insulating layer (not shown) therebetween. Twenty contact holes 1056 are provided for connecting bit lines 1054 and 1055 to aluminum interconnections (not shown), which are located at the first layer, and are formed on bit lines 1054 and 1055 with the insulating layer (not shown) therebetween.
Referring to FIG. 49, conventional semiconductor memory devices 1000 and 1100 include internal voltage generating circuits 1060-1065, terminals 1066-1077, switches 1078-1083, a control circuit 1084 and a switching circuit 1085.
Internal voltage generating circuits 1060-1062 lower the power supply voltage to generate internal voltages VREFS, VREFP and VREFD, respectively. Internal voltage generating circuit 1063 lowers the power supply voltage to generate internal voltage VBL for precharging the bit line pair. Internal voltage generating circuit 1064 lowers the power supply voltage to generate an internal voltage VCP, which is a cell plate voltage. Internal voltage generating circuit 1065 boosts power supply voltage to generate internal voltage VPP for activating the word line.
In a normal operation, switch 1078 is connected to terminal 1066 in accordance with a switching signal applied from a switching circuit 1085, and supplies internal voltage VREFS, which is generated by internal voltage generating circuit 1060, to the internal circuit. In a burn-in test, switch 1078 is connected to terminal 1067 in accordance with the switching signal applied from switching circuit 1085, and supplies an external voltage, which is received from the terminal for receiving a data mask signal DQM0, to the internal circuit.
In the normal operation, switch 1079 is connected to terminal 1068 in accordance with the switching signal applied from switching circuit 1085, and supplies internal voltage VREFP, which is generated by internal voltage generating circuit 1061, to the internal circuit. In the burn-in test, switch 1079 is connected to terminal 1069 in accordance with the switching signal applied from switching circuit 1085, and supplies the external voltage, which is received from the terminal for receiving data mask signal DQM0, to the internal circuit.
In the normal operation, switch 1080 is connected to terminal 1070 in accordance with the switching signal applied from switching circuit 1085, and supplies internal voltage VREFD, which is generated by internal voltage generating circuit 1062, to the internal circuit. In the burn-in test, switch 1080 is connected to terminal 1071 in accordance with the switching signal applied from switching circuit 1085, and supplies the external voltage, which is received from the terminal for receiving data mask signal DQM0, to the internal circuit.
In the normal operation, switch 1081 is connected to terminal 1072 in accordance with the switching signal applied from switching circuit 1085, and supplies internal voltage VBL, which is generated by internal voltage generating circuit 1063, to the internal circuit. In the burn-in test, switch 1081 is connected to terminal 1073 in accordance with the switching signal applied from switching circuit 1085, and supplies the external voltage, which is received from the terminal for receiving data mask signal DQM0, to the internal circuit.
In the normal operation, switch 1082 is connected to terminal 1074 in accordance with the switching signal applied from switching circuit 1085, and supplies internal voltage VCP, which is generated by internal voltage generating circuit 1064, to the internal circuit. In the burn-in test, switch 1082 is connected to terminal 1075 in accordance with the switching signal applied from switching circuit 1085, and supplies the external voltage, which is received from the terminal for receiving data mask signal DQM0, to the internal circuit.
In the normal operation, switch 1083 is connected to terminal 1076 in accordance with the switching signal applied from switching circuit 1085, and supplies internal voltage VPP, which is generated by internal voltage generating circuit 1065, to the internal circuit. In the burn-in test, switch 1083 is connected to terminal 1077 in accordance with the switching signal applied from switching circuit 1085, and supplies the external voltage, which is received from the terminal for receiving data mask signal DQM0, to the internal circuit.
Referring to FIG. 50, control circuit 1084 includes mode signal generating circuits 1086-1089 and an AND gate 1090. When an externally applied address designates a VREF force mode, mode signal generating circuit 1086 generates a test mode signal for shifting to the VREF force mode, and outputs the generated test mode signal to AND gate 1090 and the internal circuit.
When the externally applied address designates a VPP force mode, mode signal generating circuit 1087 generates a test mode signal for shifting to the VPP force mode, and outputs the generated test mode signal to AND gate 1090 and the internal circuit.
When the externally applied address designates a multi-bit test mode, mode signal generating circuit 1088 generates a test mode signal for shifting to the multi-bit test mode, and outputs the generated test mode signal to AND gate 1090 and the internal circuit.
When the externally applied address designates an all-bank test mode, mode signal generating circuit 1089 generates a test mode signal for shifting to the all-bank test mode, and outputs the generated test mode signal to AND gate 1090 and the internal circuit.
AND gate 1090 receives the test mode signals from mode signal generating circuits 1086-1089, and outputs the burn-in test mode signal at H-level (logical high level) to switching circuit 1085 when all the received test mode signals are at H-level. Thus, control circuit 1084 generates the burn-in test mode signal after the operation shifted to the VREF force mode, VPP force mode, multi-bit test mode and all-bank test mode.
The VREF force mode, VPP force mode, multi-bit test mode and all-bank test mode are employed as various test modes, in which the semiconductor memory device can operate. In the VREF force mode, the test is performed by changing a reference voltage applied to internal circuits of the semiconductor memory device such as a memory cell array, a column decoder, a row decoder and a sense amplifier. In the VPP force mode, the test is performed by changing a voltage used for activating the word line. In the multi-bit test mode, the test is simultaneously made on input/output of data of the plurality of bits. In the all-bank test mode, the test is simultaneously made on all the banks. In the burn-in test mode, the test is performed with a voltage and a temperature higher than those in the normal operation.
Referring to FIG. 49 again, when switching circuit 1085 receives the burn-in test mode signal at H-level from control circuit 1084, switching circuit 1085 outputs switching signals to switches 1078-1083 for connecting switches 1078-1083 to terminals 1067, 1069, 1071, 1073, 1075 and 1077, respectively. When switching circuit 1085 receives the burn-in test mode signal at L-level (logical low level) from control circuit 1084, switching circuit 1085 outputs switching signals to switches 1078-1083 for connecting switches 1078-1083 to terminals 1066, 1068, 1070, 1072, 1074 and 1076, respectively.
Accordingly, the conventional semiconductor memory device enters the burn-in test mode after operating in the VREF force mode, VPP force mode, multi-bit test mode and all-bank test mode, and is supplied with an external voltage from one terminal, which is provided for receiving data mask signal DQM0, to conduct the burn-in test.
Referring to FIG. 51, each of conventional semiconductor memory devices 1000 and 1100 includes a pump circuit 1200. Pump circuit 1200 boosts the power supply voltage to generate internally boosted voltage VPP for activating the word lines. Pump circuit 1200 includes a ring oscillator 1201, buffers 1202 and 1207, delay circuits 1203 and 1208, pump capacitors 1204 and 1209, N-channel MOS transistors 1205 and 1210, a power supply interconnection 1212 and a gate control circuit 1214.
Ring oscillator 1201 outputs pulse signals A and /A, which have phases shifted by 180 degrees from each other, to buffers 1202 and 1207, respectively. Pulse signals A and /A have voltage levels, which vary periodically between a ground voltage GND and a power supply voltage VDD. Buffer 1202 latches and outputs pulse signal A to delay circuit 1203 and one of electrodes of pump capacitor 1204. Delay circuit 1203 delays the pulse signal received from buffer 1202 by a predetermined amount, and outputs the same to the other electrode of pump capacitor 1204. Based on the pulse signal applied from buffer 1202 and the pulse signal applied from delay circuit 1203, pump capacitor 1204 boosts power supply voltage VDD to internally boosted voltage VPP, and outputs the same to a source terminal of N-channel MOS transistor 1205. N-channel MOS transistor 1205 receives on its gate terminal a signal g from gate control circuit 1214, and supplies internally boosted voltage VPP, which is boosted by pump capacitor 1204, to power supply interconnection 1212 when signal g is at H-level.
Buffer 1207, delay circuit 1208, pump capacitor 1209 and N-channel MOS transistor 1210 perform the same operations as buffer 1202, delay circuit 1203, pump capacitor 1204 and N-channel MOS transistor 1205. N-channel MOS transistor 1210 receives on its gate terminal a signal /g from gate control circuit 1214.
Gate control circuit 1214 produces signals g and /g, which determine the timing of supply of internally boosted voltage VPP to power supply interconnection 1212, based on a control signal applied from a control circuit (not shown), and supplies signals g and /g to the gate terminals of N-channel MOS transistors 1205 and 1210, respectively. Capacitors 1206, 1211 and 1213 are parasitic capacitors.
Referring to FIG. 52, description will now be given on an operation of pump circuit 1200. Ring oscillator 1201 generates pulse signals A and /A having phases shifted by 180 degrees from each other, and outputs signals A and /A to buffers 1202 and 1207, respectively. Buffer 1202 latches and outputs pulse signal A, and delay circuit 1203 delays the pulse signal applied from buffer 1202 by a predetermined amount, and outputs the delayed signal as a signal a0 to the other electrode of pump capacitor 1204. Thereby, signal a is boosted to a maximum level of VPP ( greater than VDD) by a bootstrap effect of delay circuit 1203 and pump capacitor 1204. When N-channel MOS transistor 1205 receives signal g from gate control circuit 1214, N-channel MOS transistor 1205 is turned on to supply internally boosted voltage VPP to power supply interconnection 1212 only while signal g is at H-level.
Buffer 1207, delay circuit 1208 and pump capacitor 1209 perform the same operations as buffer 1202, delay circuit 1203 and pump capacitor 1204, respectively, and more specifically, operate to boost power supply voltage VDD of pulse signal /A to internally boosted voltage VPP, and supply signal /a to a source terminal of N-channel MOS transistor 1210. When N-channel MOS transistor 1210 receives signal /g from gate control circuit 1214, N-channel MOS transistor 1210 is turned on to supply internally boosted voltage VPP to power supply interconnection 1212 only while signal /g is at H-level. As a result, power supply interconnection 1212 is supplied with the internally boosted voltage formed of a waveform of a signal p.
According to a recent technology, semiconductor memory devices using a power supply voltage of 2.5 V are coexistent with semiconductor memory devices using a power supply voltage of 3.3 V. Also, semiconductor memory devices employing word structures of 8 bits, 16 bits and 32 bits are coexistent. Accordingly, various semiconductor memory devices employing different power supply voltages and/or different word structures have been produced in accordance with user""s requests.
In the conventional semiconductor memory devices, however, a plurality of predecoders are provided for a plurality of banks, and further are concentratedly disposed in a central portion of the semiconductor memory device. Also, the conventional semiconductor memory device is provided at its central portion with a repeater for supplying a clock received from a driver to each of the plurality of banks. These structures disadvantageously increase the number of interconnections arranged in the central portion of the semiconductor memory device.
In the prior art, the semiconductor memory devices using the power supply voltage of 2.5 V are produced independently of the semiconductor memory devices using the power supply voltage of 3.3 V. Therefore, such a semiconductor memory device has not been present that can be adapted to the plurality of power supply voltages without changing the type.
Further, if a pump capacitor for boosting the power supply voltage is formed of a plurality of layers stacked together, contact holes for connecting these layers must be formed in many portions for reducing a contact resistance. Further, contact portions of two layers, which are in contact with each other, must be wide or large for ensuring a sufficient capacity of supplying electric charges. Due to these two reasons, it is necessary to increase a width of the aluminum interconnection, which supplies the boosted voltage supplied from the pump capacitor to the internal circuit. This results in a problem that an empty region not occupied by the aluminum interconnections is too small to arrange other interconnections therein.
When the burn-in test is conducted in the conventional semiconductor memory device, a single voltage is externally supplied instead of a plurality of internal voltages at different voltage levels. Therefore, a defective semiconductor memory device is liable to be determined as a non-defective semiconductor memory device and vice versa so that correct determination is impossible.
Further, the conventional semiconductor memory device can enter the burn-in test mode only after passing through the VREF force mode, VPP force mode, multi-bit test mode and all-bank test mode. Therefore, a disadvantage occurs in such a case that various types employing different specifications are present although these types are prepared in accordance with type development by effecting minor changes on a single core type or in accordance with a master slice development or the like, and therefore are similar to each other. The above disadvantage is that defective modes, which are equal in number to the types, cannot be detected under common burn-in test conditions.
Furthermore, in the conventional semiconductor memory device, the pump capacitor for producing the internally boosted voltage to be used for activating the word line can be used in the semiconductor memory device formed of a single-word structure without causing a problem in capacity. For using the pump capacitor in the semiconductor memory device adaptable to multiple word structures, however, the pump capacitor designed in accordance with only one word structure among the plurality of word structures has the capacity, which may become excessively large or small when switched to another word structure.
Accordingly, an object of the invention is to provide a semiconductor memory device, which can reduce interconnections arranged in a central portion.
Another object of the invention is to provide a semiconductor memory device, which allows adaptation of a single type to a plurality of power supply voltages.
Still another object of the invention is to provide a semiconductor memory device, which allows adaptation of a single type to a plurality of word structures.
Yet another object of the invention is to provide a semiconductor memory device, in which many interconnections can be arranged in a region including a pump capacitor producing an internally boosted voltage.
Further another object of the invention is to provide a semiconductor memory device, in which a burn-in test can be conducted with a plurality of voltages at different voltage levels.
A further object of the invention is to provide a semiconductor memory device, in which a burn-in test can be performed under a plurality of conditions.
A further object of the invention is to provide a semiconductor memory device, in which a capacity of a pump capacitor can be switched in accordance with a word structure.
According to one aspect of the present invention, a semiconductor memory device includes banks of n (n is a natural number) in number each including a plurality of memory cells; and predecoders of m (m is a natural number satisfying (m less than n)) in number for producing a select signal for selecting each of the n banks, each of the m predecoders outputting the select signal to the banks of k (k is a natural number satisfying (n=kxc3x97m)) in number among the n banks.
The semiconductor memory device according to the invention employs the predecoders smaller in number than the banks. According to the invention, therefore, interconnections for the banks can be reduced in numbers.
According to another aspect of the present invention, a semiconductor memory device for operating in synchronization with a clock by being driven by a first power supply voltage having a first voltage level or a second power supply voltage having a second voltage level lower than the first voltage level, includes a memory cell array including a plurality of memory cells for inputting and outputting data; a peripheral circuit for inputting and outputting the data to and from the memory cells in synchronization with the clock; an internal voltage generating circuit for generating an internal voltage based on the first or second power supply voltage, and supplying the generated internal voltage to the memory cell array and the peripheral circuit; and a voltage producing circuit for producing the first and second power supply voltages based on an external power supply voltage, selecting the produced first or second power supply voltage based on a voltage switch signal, and supplying the selected first or second power supply voltage to the internal voltage generating circuit.
According to the semiconductor memory device of the invention, even when the voltage level of the power supply voltage is switched, the internal voltage is generated based on the supplied power supply voltage for inputting or outputting the data to or from the memory cell. According to the invention, therefore, a single kind of semiconductor memory device can be adapted to the two power supply voltages at different voltage levels.
According to still another aspect of the present invention, a semiconductor memory device for inputting and outputting data to and from a memory cell by selecting one word structure from a plurality of word structures, includes a memory cell array including a plurality of memory cells, a peripheral circuit for inputting and outputting the data to and from the memory cell, and a control circuit for producing and outputting to the peripheral circuit a word structure select signal for selecting the one word structure from the plurality of word structures. The peripheral circuit selects the one word structure in accordance with the word structure select signal, and performs the input/output of data to and from the memory cell in accordance with the selected word structure.
According to the semiconductor memory device of the invention, the data is input and output to and from the memory cell in accordance with the one word structure selected from the plurality of word structures. According to the invention, therefore, it is possible to produce the semiconductor memory device, which allows adaptation of a single type to a plurality of word structures.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds