1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor device equipped with MOSFETs for Dual Gate electrodes.
2. Background Art
With advances in scale-down, high integration and speeding up of a device, a reduction in the resistance of the gate electrode in an element has recently been of importance. As a method of reducing the resistance of the gate electrode, there is known a method of forming a low-resistance metal film such as a tungsten (W) film on a polycrystalline silicon film. However, when the metal film is directly stacked or layered on the polycrystalline silicon film, the polycrystalline silicon film and the metal film are brought into silicidation upon subsequent heat treatment, thus causing a problem on the reliability of an oxide film. Therefore, a barrier metal film such as a tungsten nitride (WN) film has been formed at an interface surface between the polycrystalline silicon film and the tungsten film.
FIG. 19 is a schematic cross-sectional view showing the neighborhood of a border part between an N channel region and a P channel region of a MOS transistor having dual gate electrodes. In the drawing, a silicon substrate 100 is separated into elements by an element isolation oxide film 103. Polycrystalline silicon film is formed on a P well 201 in the N channel region and an N well 202 in the P channel region as gate electrode. Thereafter, an N type impurity and a P type impurity are respectively introduced into the polycrystalline silicon film in the N channel region and the polycrystalline silicon film in the P channel region to thereby form polycrystalline silicon film 207, 208 containing dopants.
In order to achieve a reduction in the resistance of the gate electrode, a tungsten film used as a metal film 211 is formed over the polycrystalline silicon film 207, 208. Further, a tungsten nitride film (WN) used as a barrier metal film 1310 is formed at a boundary face between the polycrystalline silicon film 207, 208 and the metal film 211. The formation of the barrier metal film 1310 at the boundary face between the polycrystalline silicon film 207, 208 and the metal film 211 in this way makes it possible to prevent the polycrystalline silicon film and the metal film from being silicidized, whereby the reliability of the oxide film can be enhanced.
However, a problem arises in that while the reliability of the oxide film can be satisfied when the barrier metal film 1310 such as the tungsten nitride (WN) is formed at the boundary face between the polycrystalline silicon film 207, 208 and the metal film 211 as shown in FIG. 19, the boundary face between the polycrystalline silicon film 207, 208 and the metal film 211 is brought to a non-ohmic junction, thereby increasing interface resistance.
FIG. 20 shows the manner in which a barrier metal film is constituted of a structure wherein a tungsten silicide (WSi) film used as a first barrier metal film 1409 is layered or stacked on a tungsten nitride (WN) film used as a second barrier metal film 1410, in order to avoid an increase in the interface resistance. In such a constitution, a problem arises in that while interface resistance is reduced due to an ohmic junction, dopants in polycrystalline silicon films 207 and 208 are interdiffused between an N channel region and a P channel region through the first barrier metal film 1409 by heat treatment corresponding to a subsequent process step, thereby shifting the threshold of a MOS transistor.
The present invention aims to provide a semiconductor device having a dual gate electrode structure, wherein in a device using polymetal gates, a first barrier metal on polysilicon is etched at the boundary between an N-ch region and a P-ch region, followed by deposition of a second barrier metal, whereby interface resistance and interdiffusion can be restrained.
The present invention has been made to solve the above problems. A first object of the present invention is to prevent a dopant for a polycrystalline silicon film in an N channel region and a dopant for a polycrystalline silicon film in a P channel region from being interdiffused through a first barrier metal film, restrain a change in the threshold of a transistor and reduce interface resistance between a metal film and the polycrystalline silicon film.
A second object of the present invention is to reliably inhibit the diffusion of dopants through a boundary face between a second barrier metal film and a polycrystalline silicon film.
A third object of the present invention is to prevent a resistance value of a gate electrode from being shifted from a reference value due to the formation of a portion with reverse conduction-type dopants mixed therein or a non-doped portion in the polycrystalline silicon film at a border part.
According to one aspect of the present invention, a semiconductor device comprises element active regions for an N channel region and a P channel region. The element active regions are formed so as to adjoin each other; and gate electrode is formed so as to stride over both channel regions and an element isolation oxide film for separating both channel regions from each other. The gate electrode comprises a structure in which a polycrystalline silicon film, a first barrier metal film, a second barrier metal film and a metal film which are laminated in order from below. And the first barrier metal film is removed at a border part between the N channel region and the P channel region.
According to another aspect of the present invention, a method of manufacturing a semiconductor device, an element isolation oxide film is formed on the surface of a semiconductor substrate to define element active regions firstly. Secondly, P type and N type impurities are respectively introduced in the element active regions adjacent to each other, thereby a P well and an N well are respectively formed. A gate oxide film is formed on the surfaces of the P and N wells thirdly. Polycrystalline silicon film is formed over the semiconductor substrate including the P well, the N well and the element isolation oxide film provided thereon fourthly. A first barrier metal film is formed on the polycrystalline silicon film fifthly. The first barrier metal film is removed at a border part between the P well and the N well sixthly. A second barrier metal film is formed on the first barrier metal film and at the border part seventhly. A metal film is formed on the second barrier metal film eighthly.
According to the present invention, the removal of a first barrier metal film at the border part between an N channel region and a P channel region makes it possible to restrain a dopant for a polycrystalline silicon film on the N channel region and a dopant for a polycrystalline silicon film on the P channel region from being interdiffused through the first barrier metal film. Thus, a variation in the threshold of a transistor can be reduced to the minimum. Since the first barrier metal film and a second barrier metal film are formed between a metal film and the polycrystalline silicon film, interface resistance therebetween can be reduced.
Since the upper surface of polycrystalline silicon film is removed by a predetermined amount to dig a trench at the border part between the N channel region and the P channel region, it is possible to reliably restrain the diffusion of dopants through a boundary face between the second barrier metal film and the polycrystalline silicon film. Since the trench is defined, the thickness of the metal film can be increased at the border part. Thus, the effective thickness of the gate electrode can be increased and hence the resistance of the gate electrode per se can be reduced.
The removal of the polycrystalline silicon film together with the first barrier metal film at the border part between the N channel region and the P channel region makes it possible to restrain the diffusion of dopants due to high-temperature heat treatment in a subsequent process step and prevent the occurrence of a portion with reverse conduction-type dopants mixed therein or a non-doped portion in the polycrystalline silicon film at the border part. Thus, the resistance value of the gate electrode can be prevented from being shifted from a reference value.
Since an element isolation oxide film can be removed by a predetermined amount from its upper surface at a portion where the second barrier metal film is brought into intimate contact with the element isolation oxide film, dopants can more reliably prevented from being diffused through the boundary face between the second barrier metal film and the polycrystalline silicon film.
USPTO Backgrounds
USPTO Backgrounds