This invention relates to semiconductor memory devices and more particularly to an improved sense amplifier for a CMOS dynamic read/write memory.
Dynamic MOS memory devices have heretofore used bistable differential sense amplifiers which have inputs connected to balanced bit lines, each bit line being half of a column. Dummy cells establish a reference voltage on the unselected bit line. Sense amplifiers of this type are shown in U.S. Pat. No. 4,239,993 issued to McAlexander, White and Rao (a 64K-bit device), U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine (a 16K-bit device), and U.S. Pat. No. 3,940,747, issued to Kuo and Kitagawa (a 4K-bit device), all assigned to Texas Instruments.
The differential sense amplifiers previously used have required that the bit lines, latch transistors, dummy cells, active pull-up circuits, precharge devices, and all other elements associated with the bit lines and sense latch, be almost perfectly balanced. A slight imbalance in electrical or physical characteristics can result in unreliable data. For example, if the latch transistors are not balanced in threshold voltage and conduction factor, false data can be read.
A single-ended sense amplifier is disclosed in pending application Ser. No. 741,205, filed June 4, 1985 by David J. McElroy, assigned to Texas Instruments, which is a continuation of Ser. No. 445,813, now abandoned. It is the principal object of this invention to provide an improved sense amplifier for a low-power high-speed random access read/write memory, particularly for an array of dynamic one-transistor cells. Another object is to provide a sense amplifier which may be used in a dynamic memory array wherein the bit lines and sense amplifier elements are not required to be balanced and matched.
USPTO Backgrounds
USPTO Backgrounds