The object of the invention comprises a timepiece including a low frequency oscillator acting as time base arranged and adapted to feed a first chain of frequency dividers having an adjustable division rate in order to display the time and a high frequency oscillator feeding a second chain of frequency dividers.
Such an arrangement is known from the European Patent Office publication No. 0 015 873 (corresponding U.S. Pat. No. 4,344,046). In this publication there is claimed a high frequency quartz oscillator which with the purpose of lowering the current consumption thereof includes a circuit equipped with a low frequency quartz oscillator, means for producing a correction signal which serves to control a programmable frequency divider and an electronic switch in order to periodically interrupt the high frequency quartz oscillator.
Effectively it is known that a high frequency quartz oscillator having a frequency of 1 MHz or more provides a temperature and aging stability which is better than that of a low frequency quartz oscillator operating at the usual frequency of 32 kHz. On the other hand the high frequency oscillator having a frequency divider coupled thereto will have a current consumption substantially greater thereby requiring more frequent replacements of the battery. Thus the invention mentioned herein above proposes a oscillator having all the advantages of a high frequency oscillator but wherein consumption does not go beyond that normally exhibited by a low frequency oscillator. In order to achieve such result the cited publication suggests the use of an electronic switch which energized the high frequency oscillator periodically (every 15 minutes) during a relatively short time period (16 seconds). The signals provided by the high frequency and low frequency oscillators fed respectively secondary frequency dividers which each produced at their output a signal of which the period had a value of around 16 seconds. These two signals fed a beat frequency generator of which the resultant output corresponded to the spread between the low frequency period to be controlled and the high frequency reference period. This spread or variant was then used in order to correct the rate of division of the principal frequency divider. Thus, in this system, every 15 minutes the rate of division of the principal divider was questioned or interrogated and, in the case where the frequency of the low frequency oscillator had varied, the rate of division was corrected by a signal provided by a learning circuit formed by a beat frequency generator.
Such system for which the basis of its function has just been described has several disadvantages. Initially several secondary frequency dividers are required thereby complicating construction and manufacture. Additionally it is necessary to transform the signals coming from the high and the low frequency oscillators in order to produce the beat frequency instead of using such signals directly such as they exist in the binary form thereby the result being to diminish the precision. Finally no consideration has been taken in the fact that for reason of the manufacturing price the high frequency quartz may be coarsely adjusted about the nominal frequency range in which case means must be provided in order to memorize the existing variant or spread.
In order to avoid the above-mentioned disadvantages the present invention proposes to regulate the running of the timepiece of the invention by utilizing a low frequency oscillator serving as a time base and arranged to feed a first frequency divider having an adjustable division rate in order to display time. The timepiece further includes a high frequency oscillator arranged to feed a second chain of frequency dividers, with a slave logic circuit being connected between the first and second chains of frequency dividers. The slave logic circuit periodically activates and deactivates the second chain of frequency dividers in response to particular counted pulses from the first chain. Thus, the second chain provides a binary count of the number of reference pulses counted by the second chain of frequency dividers during a period established by the first chain of frequency dividers. This binary count of the second chain is representative of a running variation of the first chain relative to a reference. A first memory means is arranged to receive and store the binary count of the second chain. This binary count in the first memory is then used to correct the division rate of the first chain by use of an inhibition circuit associated with the first chain.
In the preferred embodiment, the binary count of the second chain which is stored in the first memory is compared with a standard value stored in a second memory before using this count for correcting the division rate of the first chain. In this respect, the high frequency oscillator provides a signal having a real frequency coarsely adjusted to approximate a nominal value, while the standard value stored in the second memory represents the binary value of the spread between the real frequency and the nominal value.
USPTO Backgrounds
USPTO Backgrounds