An electronic component package refers to package technology for electrically connecting an electronic component to a printed circuit board (PCB), such as a main board of an electronic device, and protecting the electronic component from external impacts. Recently, one major trend of technical development regarding electronic components is reducing a size of components, and in line with this, in a package field, realization of a plurality of pins with a reduced size is required to meet the rapid demand for miniaturized electronic components.
A wafer level package (WLP) using a redistribution line (RDL) of an electrode pad of an electronic component formed on a wafer has been proposed as a package technique to meet the aforementioned technical requirements. The WLP includes a fan-in WLP and a fan-out WLP, and in particular, the fan-out WLP, advantageous for realizing a plurality of pins with a reduced size, has been actively developed in recent years.
The present disclosure aims at providing an electronic component package in which concentration of stress or curving (or warpage) is significantly alleviated.
USPTO Backgrounds
USPTO Backgrounds