For semiconductor integrated circuit manufacturing, in order to increase density of devices, size of semiconductor devices in an integrated circuit such as transistor, resistor, capacitor or other existing semiconductor components has been continually reduced. Therefore, in order to electrically connect each semiconductor device, a multi-layer interconnect structure is often required.
In a back-end interconnection process during semiconductor device manufacturing, an electrical connection needs to be formed between a first metal layer (M1) and an active device structure in a lower layer (containing a source region, a drain region and a gate structure region). Therefore, before the first metal layer is formed, a local interconnect structure of a semiconductor device needs to be formed in advance. The local interconnect structure includes contact vias used for connecting the first metal layer with the source region, the drain region and the gate structure region. A zeroth metal layer (M0) is formed in the contact vias.
However, because the contact vias in the source region and the drain region often do not have the same depth as the contact via in the gate structure region, it becomes difficult to etch contact vias in different regions of the local interconnect structure and to deposit conductive material.
In order to solve the problem of unequal depths of the contact vias, existing process for forming an interconnect structure is often complicated, and production efficiency is often low. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.
USPTO Backgrounds
USPTO Backgrounds