As MOSFETs are scaled down to channel lengths below 100 nm, interactions between the source and drain regions of the MOSFET begin to degrade the ability of the gate to switch the transistor on and off. This phenomenon, known in the art as the short channel effect, represents a significant challenge to CMOS scaling.
One approach which has been developed in the art for mitigating the short channel effect utilizes a double implant process to define the source and drain regions of the transistor. In this approach (which is typically implemented after the gate structure is defined on a semiconductor substrate), a dopant is implanted into a thin region just below the top surface of the substrate to form ultra-shallow source/drain extension regions. This implant step also forms a portion of the source/drain regions.
After the extension regions are defined, spacers are formed on the substrate such that they are adjacent to the sides of the gate structure and extend over the source and drain extension regions. Such spacers may be formed by depositing a conformal layer of silicon nitride or silicon oxide, and then subjecting the conformal layer to an anisotropic etch. The substrate is then subjected to a second implant to deepen the source and drain regions. The source and drain extensions are shielded from further doping during this process due to the presence of the spacers. The structure may then be subjected to a thermal anneal to induce dopant diffusion.
USPTO Backgrounds
USPTO Backgrounds