The performance of IC devices for microwave frequencies has often not been as good as indicated by device specifications using standard DC current-voltage measurements. In the case of GaAs metal-semiconductor field-effect transistors (MESFETs), the device performance exhibits frequency dispersion in low frequency ranges (below a few MHz) which is associated with detrimental effects on its electrical characteristics, such as drain current drift, looping of current-voltage characteristics, degradation of output power, gate leakage current increase, frequency dependence of the gate input admittance, and other anomalies.
Recent research on the I-V characteristics of MESFETs have noted the problems of frequency dispersion due to charge trapping effects in the surface access regions of the device, instead of to deep level trapping in the active layer-substrate interface, as previously thought. See, e.g., "Surface Influence On The Conductance Of DLTS Spectra Of GaAs MESFET's", by Stephen Blight, et al., IEEE Transactions On Electron Devices, Vol. ED-33, No. 10, October 1986; "Analysis Of Capacitance And Transconductance Frequency Dispersions in MESFETs for Surface Characterization", by J. Graffeuil, et al., Solid-State Electronics, Vol. 29, No. 10, pp. 1087-1097, 1986 (published in Great Britain); "Frequency Domain Detection of Deep Levels in GaAs MESFETS", by Jian-ren Li, Semiconductor Science and Technology 2, pages 337-339, January 1987 (published in the UK); and "Mechanisms For Low-Frequency Oscillations In GaAs FET's", by Daniel Miller, et al., IEEE Transactions On Electron Devices, Vol. ED-34, No. 6, June 1987.
As a result, various structures have been proposed to measure the effects of frequency dispersion on transconductance and other I-V characteristics of GaAs MESFETs. Also, alternative designs have been proposed attempting to reduce the frequency dispersion effects, including the use of passivating layers, large gate width to source-drain length ratios, buried channels, and notched gates.
In view of the prior work, it would be extremely useful to have an early indication whether or not a particular design or a sample of an IC device will have acceptable performance characteristics in contrast to unacceptable designs or nonconforming units. In the production process, IC devices are formed on wafers and subjected to successive forming and treatment steps to yield the final, packaged product. Since some of the wafers, as fabricated, will not meet the desired performance criteria, a predictive testing system would allow selection of the good wafers early in the production process, in order to increase production yields and avoid the time and expense of finishing, backend processing, packaging, and final testing of nonconforming wafers. Also, in the design and development of IC device structures, a predictive testing capability would allow performance characteristics to be conveniently assessed and compared for experimentation prior to final fabrication.
USPTO Backgrounds
USPTO Backgrounds