1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming gate structures above elevated isolation structures and integrated circuit products having such elevated isolation structures.
2. Description of the Related Art
Field Effect Transistors (“FETs”) come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, vertical transistors, nanowire devices, etc. There are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. In general, a FinFET semiconductor device includes one or more vertically oriented fins having a three-dimensional configuration: a vertical height, a lateral width and an axial length. Such a device also includes a gate structure that wraps the two sidewalls and the upper surface of the fin(s) at a location along the axial length of the fin(s). The axial length of the fin(s) corresponds to the gate length of the device, i.e., the direction of current transport in the device 10 when it is operational. The portion of the fin(s) covered by the gate structure is the channel region of the FinFET device.
For many FET devices, the gate structures are initially formed as continuous line-type structures that extend across the entire substrate, including across both active regions and isolation regions. The gate structures for such devices may be manufactured using well-known gate-first or replacement gate (or “gate-last”) manufacturing techniques. The gate structures (final gate structures in a gate-last process or sacrificial gate structures in a replacement gate process) are initially formed as continuous line-type structures that extend across the entire substrate, including across both active regions and isolation regions. As device scaling continues, the vertical height of the gate structures has increased, while the lateral width (i.e., gate length or critical dimension) of the gate structures has decreased. As a result, the aspect ratio (height/lateral width) of the gate structures has increased. In some cases, due to this increased aspect ratio, at least a portion of the axial length of the gate structure may actually tilt or “flip-over,” from their desired substantially vertical orientation. For example, portions of a gate structure that are not positioned above one or more of fins, i.e., portions of a gate structure positioned above a device isolation region formed in the substrate, may be susceptible to such tilting. Such tilting of the gate structures, if sufficient, may lead to significant degradation of the performance of the IC product.
The present disclosure is directed to various methods of forming gate structures above elevated isolation structures and integrated circuit products having such elevated isolation structures that may eliminate or at least reduce one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds