1. Field of the Invention
This invention relates to a chip mis-position detection method for detecting a mis-position of a semiconductor chip on a dicing tape when an electrical characteristic inspection, of the semiconductor chips fixed to the dicing tape, is carried out.
2. Description of the Related Art
A large number of semiconductor devices (chips), forming the same electrical chip circuits, are formed on a surface of a wafer, and an approval/rejection judgment is made by using a prober to inspect electrical characteristics of each electrical chip circuit before the wafer is diced into discrete semiconductor devices (semiconductor chips). The prober generally has a construction in which a probe card having a probe corresponding to each semiconductor device of the wafer and connected to a tester is allowed to serially correspond to each semiconductor chip, brings its probes into contact with electrode pads of the semiconductor device and conducts electric measurement.
To reduce size, weight and thickness of electronic appliances such as cellular telephone units, digital cameras and mobile information terminals, a packaging technology for semiconductor integrated circuitry has now reached the stage of a chip size package (CSP) or a wafer level chip size package (WCSP). The CSP uses semiconductor chips arranged in a stack.
Therefore, a wafer having a reduced thickness of 100 μm or below has been required. In such thin wafers, the possibility of defect has become high during the process in which the wafer is diced into discrete semiconductor chips in a dicing step after the electrical characteristic test by using a prober. The demand is also high that the electrical characteristic test be conducted as much as possible in the last stage of the production of the semiconductor chips to reduce the percentage of defectives in the packaged products.
The electrical characteristic test of the semiconductor chips in the chip state has been made in the past by using a frame-carrying prober. In this case, to prevent the semiconductor chips diced during the dicing step from scattering, a dicing tape is bonded to a surface of the wafer on which the electronic chip circuits are not formed, and the wafer is then diced. The dicing tape has a round shape the same as the wafer and after the wafer is diced, the dicing tape is stretched in such a manner as to increase its diameter and is held under the stretched state by a ring-like metal frame. In other words, the discrete semiconductor chips diced are held as bonded to the dicing tape while the gaps (breaks) between the semiconductor chips are somewhat expanded. The semiconductor chips are carried under such a state by the frame and the electrical characteristic test of the discrete semiconductor chips is conducted while the semiconductor chips are held on the stage of the frame-carrying prober.
According to the prior art method described above, however, some semiconductor chips peel from the dicing tape from time to time. When the electrical characteristic test is started under this state, the semiconductor chips that are about to peel come into contact with probes of a probe card of the frame-carrying prober and breaks the probes and the chips. When alignment is conducted to position the semiconductor chips, the peeling semiconductor chips impinge against an alignment camera and break the alignment camera and the semiconductor chips.
USPTO Backgrounds
USPTO Backgrounds