1. Field of the Invention
The invention relates to semiconductor devices, and more particularly to complementary metal oxide semiconductor (CMOS) devices with dual-metal gate structures and fabrication methods thereof.
2. Description of the Related Art
Conventional complementary metal oxide semiconductor devices are manufactured with polysilicon gate structure. Polysilicon, however, is susceptible to a depletion effect, which can add to the overall gate dielectric thickness in CMOS devices. Scaled CMOS devices require metal gates which eliminate polysilicon depletion effects due to their allowance for excellent current flow and less voltage depletion problems. When a metal gate is inverted, there is no substantial depletion of carriers at the interface between the metal gate and gate dielectric. Accordingly, transistor performance does deteriorate because the electrical thickness of the gate stack is decreased. The integration of semiconductor transistors having dual work function metal gates, however, is troublesome. For example, it is difficult to manipulate the work function of metals.
Dual work function gates are advantageously used in semiconductor devices having both PMOS and NMOS transistors. Some work functions that enable optimal operation of both PMOS and NMOS transistors are required. The optimal work function for a metal gate electrode will differ depending upon whether it is used to form an NMOS transistor or a PMOS transistor. For this reason, when the same material is used to make metal gate electrodes for NMOS and PMOS transistors, the gate electrodes do not demonstrate the desired work function for both types of devices. It may be possible to address this problem by separately forming metal gate electrode of the NMOS transistor from a first material and metal gate electrode of the PMOS transistor from a second material. The first material may ensure an acceptable work function for the NMOS gate electrode, while the second material may ensure an acceptable work function for the PMOS gate electrode. Processes for forming such dual metal gate devices may, however, be complex and expensive.
FIG. 1 is a cross section of a conventional CMOS transistor incorporating dual metal gate structures thereon. The CMOS transistor includes a PMOS transistor 10P that is typically formed in an n-well (not shown) and an NMOS transistor 10N that is formed in a p-well (not shown). The substrate 1 has a first well of the first conductivity type and a second well of the second conductivity type. The first well and the second well are isolated from one another by shallow trench isolation (STI) 13 in the substrate to separate PMOS transistor 10P from NMOS transistor 10N. Gate dielectric 15 is deposited on the surface of the semiconductor substrate 1 over both the PMOS transistor 10P and the NMOS transistor 10N. As suggested above, CMOS transistor also incorporates a dual-metal gate conductor in the form of first metal gate conductor 16a and second metal gate conductor 16b. First metal gate conductor 16a is deposited and formed on gate dielectric 15 over PMOS region 10P. Second metal gate conductor 16b is separately deposited and formed on gate dielectric 16b over NMOS region 10N. Polysilicon electrode 17 is deposited and formed on the first and second metal gate conductors 16a and 16b. Processes for forming such dual metal gate devices may, however, be complex and expensive.
Methods for fabricating a semiconductor device having a metal gate electrode are also disclosed in, for example, U.S. Pat. No. 6,974,764, the entirety of which is hereby incorporated by reference. That method comprises forming a dielectric layer on a substrate, and forming a first metal layer on a first part of the dielectric layer, leaving a second part of the dielectric layer exposed. After a second metal layer is formed on both the first metal layer and the second part of the dielectric layer, a masking layer is formed on the second metal layer.
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