This invention relates to memory systems. More particularly, the invention relates to an adaptable high speed arrangement for accessing individual storage locations among an arbitrary plurality of memory modules in an interleaved memory system.
Fast accessing of memory is essential to realize the full benefit of high speed central processing units (CPUs). A common technique to increase the quantity of information or data available in a given unit of time is to use parallel memory architecture. Since there are a plurality of memory units in such memories, it enables access to a number of storage locations each in different memory modules at the same time or in rapidly successive intervals. Because addresses are usually in binary form, it is most convenient to constrain the number of modules in a parallel organized memory to a power of two. To gain access to individual storage locations, the logical addresses supplied by the CPU may then be simply partitioned to identify a module and a particular storage location. However, a failure of one memory module reduces the address space to half of the original memory size with a corresponding decrease in the number of available memory modules for storage.
A possible variation in this approach is to perform some kind of address translation so that the number of memory modules may be any arbitrary number rather than being limited to a power of two. However, since access to the individual storage locations requires its own particular address translation, the time required for such a translation is critical. In other words, the translation arrangement should operate at a high enough speed so that the limiting factor in providing access to the memory is primarily the memory cycle time rather than the speed of the translation arrangement. In an interleaved memory system, a fast acting address translator is able to access successive locations in different memory modules rapidly to provide a pipelining effect wherein the total access time of the memory is essentially that of one memory cycle time although a plurality of storage locations each in a different memory module are being individually accessed.
An object of this invention is to provide an address translator readily adaptable to high-speed circuit techniques.
Another object is to provide an address translator adaptable to any arbitrary number of memory modules not constrained to being any exponential value.
Another object is to provide an address translator and associated memory accessing circuitry of minimal complexity and low cost.
USPTO Backgrounds
USPTO Backgrounds