1. Field of the Invention
The present invention relates in general to a shift-register unit and a shift-register circuit comprising the shift-register units. In particular, the present invention relates to a shift-register unit using single-type transistors, such as P-type transistors or N-type transistors.
2. Description of the Related Art
A frame of a liquid crystal display (LCD) is generated by a plurality of pixels of the matrices. Thus, sequential pulses provided to the gate driver and data driver are basic signals for driving the LCD. In addition, the sequential pulses are generated by a shift-register circuit, so the shift register circuit is a general unit for the driving circuit of an LCD.
FIGS. 1A and 1B show a conventional shift-register circuits. FIG. 1C shows the output signals out1, out2, out3 and out4 when the input signals Sin, clk1, clk2 and clk3 are input to the conventional shift-register circuit shown in FIGS. 1A and 1B.
In FIG. 1A, the transistors 101 and 103 of the first-stage shift-register unit 100 are turned on when the signal clk3 is at low voltage level. The transistor 102 is turned on when the signal Sin is at low voltage level. Thus, the waveform of the signal output from the output terminal out1 is the same as the clock signal clk1. The operation of others shift-register units are similar to the first-stage shift-register unit 100, thus, the description is omitted to simplify the description.
The voltage level of the output terminal out1 of the first-stage shift-register unit 100 maintains a high voltage level, thus, the signal Sin remains at a high voltage level. In addition, the transistor 103 is turned on when the clock signal clk3 drops to low voltage level, the output terminal is at high voltage level. Contrarily, the transistor 103 is turned off when the clock signal clk3 rises to high voltage level, the voltage level of the output terminal is floating.
The voltage level of the output terminal out1 does not maintain a high voltage level when the output terminal out1 is floating. Thus, error operation of the shift-register circuit occurs. The dotted lines of out1, out2, out3, and out4 in FIG. 1C represent error operation.
FIG. 2 shows another conventional shift-register circuit, which solves the floating problem mentioned above. However, the size of the shift-register circuit is large because more transistors are required.
Thus, the disadvantages of the conventional shift-register circuits are that error operation occurs due to the unstable signal level caused by floating, and the layout is complicated and the cost of the circuit is increased because more transistors are required.
The object of the present invention is to provide a shift-register circuit comprising single-type transistors to decrease the number of transistors, semiconductor process steps and layout area. Thus, the complication and cost of a circuit is reduced.
Another object of the present invention is thus to provide a shift-register circuit comprising thin film transistors to transmit full swing signals.
To achieve the above-mentioned object, the present invention provides a shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.
In addition, the present invention provides a shift-register circuit. The first-stage shift-register unit, the final-stage shift-register unit and a plurality of middle-stage shift-register units connected between the first-stage shift-register unit and the final-stage shift-register unit are connected in serial and each shift-register unit outputs a pulse signal in sequence after the first-stage shift-register unit receiving an initial setting signal. The clock terminal for receiving a clock signal. The setting terminal receives a setting signal for trigging the shift-register unit to output the clock signal as the pulse signal. The reset terminal receives a reset signal to reset the shift-register unit to stop outputting the pulse signal. The reset terminals of the first-stage and the middle-stage shift-register units are respectively connected to the output signal of the subsequent stage shift-register unit, the reset terminal of the final-stage shift-register unit is connected to the output signal of the first-stage shift-register unit, the setting terminal of the middle-stage and the final-stage shift-register units are respectively connected to the output signal of the previous stage shift-register unit, the setting terminal of the first-stage shift-register unit is connected to the initial setting signal, the clock terminals of the odd stage shift-register units are connected to a first clock signal as the clock signal and the clock terminals of the even stage shift-register units are connected to a second clock signal as the clock signal.
In addition, the present invention provides another shift-register circuit. The first-stage shift-register unit, the second-stage shift-register unit, and the third-stage shift-register unit are connected in serial. Each shift-register unit outputs a pulse signal in sequence after the first-stage shift-register unit receiving an initial setting signal. The clock terminal receives a clock signal. The setting terminal receives a setting signal for trigging the shift-register unit to output the clock signal as the pulse signal. The reset terminal receives a reset signal to reset the shift-register unit to stop outputting the pulse signal. The reset terminals of the first-stage and the second-stage shift-register units are respectively connected to the output signal of the subsequent stage shift-register unit. The setting terminal of the second-stage and the third-stage shift-register units are respectively connected to the output signal of the previous stage shift-register unit. The setting terminal of the first-stage shift-register unit is connected to the initial setting signal, the clock terminal of the first-stage shift-register unit is connected to a first clock signal as the clock signal, the clock terminal of the second-stage shift-register unit is connected to a second clock signal as the clock signal and the clock terminal of the third-stage shift-register unit is connected to a third clock signal as the clock signal.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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USPTO Backgrounds