1. Field of Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method of forming a damascene structure.
2. Description of Related Art
In semiconductor manufacturing, damascene processes are a frequently employed technique for forming interconnects such as conductive lines, contacts or vias. By embedding conductive material within a dielectric layer to form conductive connections, the technique for forming a damascene structure remains unchanged even when a different conductive material is selected. Furthermore, familiar methods such as plasma etching or reactive ion etching (RIE) can be used to form an opening in the dielectric layer and the dielectric layer can be globally planarized by chemical-mechanical polishing (CMP).
To form a conventional damascene structure, a dielectric layer is formed over a substrate having a conductive region thereon and then a polishing stop layer is formed over the dielectric layer. An opening is formed in the polishing stop layer and the dielectric layer. The opening can be a contact opening, a via opening, a conductive line trench or a damascene opening. The opening exposes a portion of the conductive region in the substrate. A metallic layer is formed over the substrate and completely fills the opening. Finally, chemical-mechanical polishing is conducted to remove excess metallic material outside the opening.
However, difference in polishing rate between the polishing stop layer and the metallic layer in chemical-mechanical polishing is generally small. Due to their closeness in polishing rate and pattern density effect, dielectric material loss, metallic layer erosion and dishing effect will occur in the high-density pattern regions of a silicon wafer.
Accordingly, one object of the present invention is to provide a method of forming a damascene structure such that a dielectric layer having a high polishing selectivity ratio relative to the metallic layer is used. Hence, there is no need for forming a polishing stop layer.
A second object of this invention is to provide a method of forming a damascene structure capable of preventing dielectric material loss, metallic erosion and dishing effect due to chemical-mechanical polishing of a metallic layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a damascene structure. First, a substrate is provided. A dielectric layer is formed over the substrate. The dielectric layer is a silicon oxynitride layer having a refractivity between about 1.55 and 1.74 for a light beam having a wavelength of about 673 nm. Furthermore, this dielectric layer has a high polishing selectivity ratio relative to a subsequently formed metallic layer. An opening is formed in the dielectric layer. The opening can be a contact opening, a via opening, a conductive line trench or a damascene opening according to design requirements. A metallic layer that covers the substrate and completely fills the opening is formed. Finally, a chemical-mechanical polishing operation is conducted to remove excess metallic material outside the opening using the dielectric layer as a polishing stop layer.
In this invention, one major aspect is the selection of a material having a high polishing selectivity ratio relative to the metallic layer to serve as the material for forming the dielectric layer in the damascene structure. Due to the high intrinsic polishing selectivity ratio with respect to the metallic layer, no extra polishing stop layer is required. Hence, the process is very much simplified.
Furthermore, the polishing selectivity ratio of the dielectric layer relative to the metallic layer is much higher than the polishing selectivity ratio between a conventional polishing stop layer and the metallic layer. Therefore, dielectric material loss, metallic erosion and dishing effect are considerably reduced after a chemical-mechanical polishing of the metallic layer down to the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
USPTO Backgrounds
USPTO Backgrounds