1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same in which one of the electrode region is formed in a recess or a trench of a substrate.
2. Background of the Related Art
As the integration of semiconductor devices increases, the width of a gate becomes narrower, and thus, the length of a channel shortens. Therefore, the electric field in the vicinity of a drain is increased to accelerate carriers of the channel region in a depletion layer near the drain during the operation of a device, thereby causing a hot-carrier effect of injecting the carriers into a gate oxide film. The carriers injected into the gate oxide film create static charges in the interface between a semiconductor substrate and the gate oxide film, thereby varying a threshold voltage (VTH), or reducing a mutual inductance to deteriorate the device characteristics. Accordingly, in order to decrease the degradation of the device characteristics caused by the hot-carrier effect, a lightly doped drain (LDD) structure is used.
FIG. 1 is a cross-sectional view of a related art semiconductor device in which, on a predetermined part of a P-type semiconductor substrate 11, a device isolation region 13 for defining an active region of the device is formed by a local oxidation of silicon (LOCOS) method. A gate 17 is formed on a predetermined part of the active region of semiconductor substrate 11, with a gate insulating film 15 imposed therebetween. A capping oxide film 19 is formed on gate 17. A sidewall 23 is formed on the sides of both gate 17 and capping oxide film 19.
The semiconductor substrate 11 is doped on both sides of gate 17 with a low concentration of N-type impurity, thereby forming a low concentration region 21 for the LDD structure. Further, the semiconductor substrate is doped with a high concentration of N-type impurity so as to be partially overlapped with low concentration region 21, thereby forming source and drain regions 25 and 27, respectively. Source and drain regions 25 and 27 are formed using capping oxide film 19 and sidewall 23 as a mask. Low concentration region 21 is located between source and drain regions 25 and 27 and gate 17.
However, according to the aforementioned related art semiconductor device, low concentration region 21 for the LDD structure is formed in source region 25 as well as in drain region 27, so that the source resistance is increased thereby causing the current characteristics of the device to deteriorate. Further, if the bias of drain region 27 increases, a depletion region is increased, thereby causing a drain-induced barrier lowering (hereinafter, referred to as xe2x80x9cDIBLxe2x80x9d) phenomenon that reduces the potential barrier of the source. In addition, due to the limitations of a photolithographic methods, reduction of the gate width is difficult.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
An object of the present invention is to obviate one or more of the problems of the related art.
Another object of the present invention is to reduce the source resistance.
Another object of the present invention is to suppress the occurrence of the DIBL phenomenon even if the channel length is short.
A further object of the present invention is to provide a narrow gate.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device of the present invention comprises: a semiconductor substrate of a first conductivity type; a device isolation region formed on a predetermined part of the surface of the semiconductor substrate to define an active region of the device; a trench formed on a predetermined part of one side of the active region on the semiconductor substrate; a gate oxide film formed on predetermined parts of the side and the lower part of the trench; a gate formed such that the lower part and a first side thereof are in contact with the surface of the gate oxide film and the second side of the gate is exposed; a sidewall formed so as to be in contact with the second side of the gate; a low concentration region formed by doping an impurity of a second conductivity type opposite, to that of the semiconductor substrate, with a low concentration of dopant in the lower part of the sidewall; and source and drain regions formed by doping an impurity of the second conductivity type with a high concentration of dopant, using the gate and the sidewall as a mask.
In another aspect, the present invention provides a semiconductor device comprising: a semiconductor substrate of a first conductivity type; a device isolation region formed on a predetermined part of the surface of the semiconductor substrate to define an active region of the device; a trench formed on a predetermined part of one side of the active region on the semiconductor substrate; a gate oxide film formed on a predetermined part of the lower surface of the trench so as to be spaced apart from the side of the trench by a predetermined distance; a gate formed on the gate oxide film and having first and second sides; a low concentration region formed by doping an impurity of a second conductivity type, opposite to that of the semiconductor substrate, at a low concentration in the lower surface between the first side of the gate and the side of the trench; and source and drain regions formed by doping an impurity of the second conductivity type at a high concentration in a part of the semiconductor substrate in the direction of the first side of the gate not doped at a low concentration and a part of the semiconductor substrate in the direction of the second side of the gate.
In another aspect, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: forming a trench in a predetermined part of one side of a semiconductor substrate of a first conductivity type; forming a gate oxide film on the surface of the semiconductor substrate including the inner surface of the trench; depositing a polycrystalline silicon material on the upper part of the gate oxide film and etching back the polycrystalline silicon material to form a gate such that the first side thereof is in contact with the side of the trench and the second side of the gate is exposed; ion-implanting an impurity of a second conductivity type, opposite to that of the semiconductor substrate, using the gate as a mask to thereby form low concentration regions on both sides of the gate; forming a sidewall on the second side of the gate; and ion-implanting a high concentration of an impurity of the second conductivity type, using the gate and the sidewall as a mask, to thereby form source and drain regions in the semiconductor substrate in the direction of the first side of the gate and in the semiconductor substrate excluding the lower part of the sidewall in the direction of the second side of the gate.
In another aspect, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: forming a trench in a predetermined part of one side of a semiconductor substrate of a first conductivity type; forming a gate oxide film on the surface of the semiconductor substrate including the inner surface of the trench; forming a sidewall such that a first side thereof is in contact with a side or inner wall of the trench and the second side of the sidewall is exposed, with the gate oxide film imposed between the side of the trench and the first side of the sidewall; forming a gate such that the first side thereof is in contact with the second side of the sidewall and the second side of the gate is exposed; ion-implanting a high concentration of an impurity having a second conductivity type, opposite to that of the semiconductor substrate, using the sidewall and the gate as a mask, to thereby form source and drain regions, respectively, in the directions of the first side and the second side of the gate excluding the lower part of the sidewall; removing the sidewall; and ion-implanting an impurity of the second conductivity type using the gate as a mask, to thereby form a low concentration region in the direction of the first side of the gate where the sidewall is removed.
The present invention may be achieved in part or in whole by a semiconductor device, comprising a semiconductor substrate of a first conductivity type; a recess formed in a surface of the semiconductor substrate; a first region of a second conductivity formed in the recess; a second region of the second conductivity formed on the surface of the semiconductor substrate; a gate formed in the recess, between the first and second regions, and insulated from the semiconductor substrate, first region and second region; and a channel formed between the first and second regions and beneath the gate in the semiconductor substrate.
The present invention may also be achieved in whole or in part by a semiconductor device comprising: a semiconductor substrate of a first conductivity type; a trench formed in a surface of the semiconductor substrate, the trench having a side wall surface and a lower surface; an insulating film formed on the sidewall and a prescribed area of the lower surface; a gate formed on the insulating film; a first doped region of a second conductivity formed in the trench; a second doped region of the second conductivity formed on the surface of the semiconductor substrate and adjacent to the insulating film on the sidewall of the trench; and a third doped region formed on the lower surface of the trench and between the gate and the first region; and a channel formed between the second and third regions.
The present invention may be achieved in whole or in part by a semiconductor substrate of a first conductivity type; a trench formed in a surface of the semiconductor substrate; a first doped region of a second conductivity formed in the trench; a second doped region of the second conductivity formed on the surface of the semiconductor substrate; a third doped region of the second conductivity formed adjacent to the second doped region; an insulating film formed between the first and third doped regions; a gate formed on the insulating film; and a channel formed between the first and third regions in the semiconductor substrate and beneath the insulating film.
To achieve at least the above objects and advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing a semiconductor device, including the steps of forming a trench in a top surface of a semiconductor substrate, wherein the trench comprises at least one vertical wall, implanting ions into the top surface of the semiconductor substrate and into a bottom surface of said trench, forming an oxide film on the top surface of the semiconductor substrate, on the at least one vertical wall and on the bottom surface of the trench, forming an oxide sidewall in the trench in contact with the oxide film on the at least one vertical wall and partially covering the bottom surface of the trench, forming a gate in the trench in contact with the oxide sidewall and partially covering the bottom surface of the trench, forming a first doped region in the top surface of the semiconductor substrate, forming a second doped region in the bottom surface of the trench, forming a recess by removing at least the oxide film on the at least one vertical wall and by removing at least the oxide sidewall, and forming a third doped region in the bottom of the recess.
To further achieve at least the above objects and advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing a semiconductor device, including the steps of forming a trench in a top surface of a semiconductor substrate with at least one sidewall, forming a gate oxide film over the semiconductor substrate so that the gate oxide film covers at least a portion of a bottom surface of the trench and covers the at least one sidewall of the trench, forming a gate on the gate oxide film on the bottom of the trench such that a first side of the gate is exposed and a second side of the gate contacts the gate oxide film covering the at least one sidewall of the trench and such that a top surface of the gate is at approximately the same height as the top surface of the semiconductor substrate, forming a first doped region having the first dopant concentration in the top surface of the substrate, forming a second doped region having a first dopant concentration on the bottom surface of the trench adjacent the exposed side of the gate, forming a recess between the gate and the at least one sidewall by removing at least the gate oxide film, and forming a third doped region at the bottom of the recess having a second dopant concentration.
To further achieve at least the above objects and advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing a semiconductor device, including the steps of forming a trench in a top surface of a semiconductor substrate, forming a gate oxide film on the surface of the semiconductor substrate so that the gate oxide film covers at least a portion of a bottom surface of the trench, forming a spacer on the gate oxide film on the bottom of the trench such that a first side of the spacer is adjacent a side surface of the trench and such that a second side of the spacer is exposed, forming a gate on the gate oxide film on the bottom of the trench such that a first side of the gate is adjacent the second side of the spacer and a second side of the gate is exposed, forming a second doped region in the top surface of the substrate adjacent the first side of the spacer, forming a first doped region on the bottom surface of the trench adjacent the second side of the gate, removing the spacer to create a recess, and forming a third doped region on the bottom surface of the recess between the gate and the second doped region.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
USPTO Backgrounds
USPTO Backgrounds