As is well known, the solid state storage devices using NAND-based flash memories are widely used in a variety of electronic devices. For example, a SD card or a solid state drive (SSD) is a solid state storage device that uses a NAND-based flash memory to store data.
According to the data amount to be stored, the NAND-based flash memories may be classified into three types, i.e. a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory and a triple-level cell (TLC) flash memory. The SLC flash memory can store only one bit of data per cell. The MLC flash memory can store two bits of data per cell. The TLC flash memory can store three bits of data per cell.
FIG. 1 schematically illustrates the architecture of cells of a flash memory. As shown in FIG. 1, the flash memory comprises plural cells. Each cell comprises a floating gate transistor. The flash memory is a SLC flash memory, a MLC flash memory or a TLC flash memory. Moreover, these cells of the flash memory are arranged in several columns. The cells arranged in the same column are connected with each other. Moreover, the cells arranged in the same row are connected with a corresponding word line.
Generally, the floating gate transistor of each cell has a floating gate to store hot carriers. A threshold voltage (VTH) of the floating gate transistor is determined according to the amount of the stored hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the flash memory, the threshold voltage of the floating gate transistor may be changed by controlling the amount of hot carriers to be injected into the floating gate. During a read cycle, a sensing circuit of the flash memory may judge the storing status of the floating gate transistor according to the threshold voltage of the floating gate transistor.
FIG. 2 schematically illustrates the threshold voltage distribution curves of a MLC flash memory in different storing states. Each cell of the MLC flash memory has four storing states E, A, B and C. Before the hot carriers are injected into the cell, the cell is in a storing state E (e.g. the logic state is 11). As the number of hot carriers injected into the cell is gradually increased, the cell is sequentially switched to the storing state A (e.g. the logic state is 10), the storing state B (e.g. the logic state is 00) and the storing state C (e.g. the logic state is 01). Moreover, the voltage level in the storing state C>the voltage level in the storing state B>the voltage level in the storing state A>the voltage level in the storing state E. After an erase cycle, the cell is restored to the storing state E.
In practice, even if many cells are programmed to have the same storing state during the program cycle, the threshold voltages of these cells are not all identical. That is, the threshold voltages of these cells are distributed in a specified distribution curve with a median threshold voltage. For example, as shown in FIG. 2, the cells in the storing state E have a median threshold voltage VTHE (e.g. 0V), the cells in the storing state A have a median threshold voltage VTHA (e.g. 10V), the cells in the storing state B have a median threshold voltage VTHB (e.g. 20V), and the cells in the storing state C have a median threshold voltage VTHC (e.g. 30V). For example, according to statistics, the greatest number of cells in the storing state C has the median threshold voltage VTHC (e.g. 30V).
Consequently, during the read cycle, a first slicing voltage Vs1, a second slicing voltage Vs2 and a third slicing voltage Vs3 are provided for detecting the four storing states of the MLC flash memory.
Moreover, due to the characteristic difference between different cells, after the program cycle, the threshold voltages of some cells are possibly shifted to be higher than the pre-defined slicing voltage. Under this circumstance, the storing states of the cells may be erroneously judged during the read cycle.
Hereinafter, the threshold voltage distribution curves of the MLC flash memory in the storing state B and the storing state C will be illustrated in order to explain the reason why the storing states of the cells may be erroneously judged during the read cycle. As shown in FIG. 2, the threshold voltage of the area b under the distribution curve of the storing state B is higher than the third slicing voltage Vs3. If the third slicing voltage Vs3 is employed to judge the storing state, the cells of the area b are erroneously judged to be in the storing state C. Similarly, the threshold voltage of the area c under the distribution curve of the storing state C is lower than the third slicing voltage Vs3. If the third slicing voltage Vs3 is employed to judge the storing state, the cells of the area c are erroneously judged to be in the storing state B.
Since two storing states of the SLC flash memory and eight storing states of the cells of the TLC flash memory are distinguished according to the above approaches, the above situations of erroneously judging the storing states of the cells during the read cycle also exist.
From the above discussions, in the threshold voltage distribution curve of each storing state, the threshold voltages of some cells are obviously shifted. Under this circumstance, the misjudgment probability is increased, and the data error rate is also increased. Therefore, there is a need of investigating the relationships between the cells and the corresponding threshold voltage shifts in various situations in order to reduce the data error rate of the flash memory during the read cycle.
USPTO Backgrounds
USPTO Backgrounds