1. Field of the Invention
This invention, generally, relates to semiconductor fabrication, and more specifically, to doping of semiconductor materials.
2. Background Art
Semiconductor devices are used in a wide variety of applications including diodes, photodetectors, photocells, transistors, and integrated circuits. Silicon and germanium are commonly used in such electronic devices. In particular, silicon is the most widely used material in semiconductor devices due to its low cost, relatively simple processing, and useful temperature range. Further, the electronic properties and behavior of silicon and germanium can be relatively easily controlled by the addition of doping elements, for example, in the manufacture of P-I-N and N-I-P diodes.
In a conventional practice, semiconductor fabrication begins with the provision of a semiconductor wafer, comprising silicon formed in a regular, crystalline structure. A circuit pattern is devised in which regions of the semiconductor wafer are intended to support NMOS and PMOS semiconductor components. These regions are isolated from each other with the formation of electronically inert isolation trenches. Each region is then doped with a type of dopant opposite the electronic nature of the components to be created thereupon. For instance, the dopant may be introduced through ion implantation, in which charged ions of the dopant material are fired at the semiconductor wafer at high speeds, thereby physically injecting them into the substrate. In the past, doping has also been achieved by utilizing conventional thermal diffusion in furnace, and Chemical or Physical Vapor Deposition (CVD, PVD), such as sputtering.
Following doping, electronic components are then formed upon the semiconductor wafer, which typically involves doping (via ion implantation or another suitable method) the electronically active areas of the semiconductor wafer with the desired type of dopant. For instance, NMOS components are formed by placing a p-type dopant in a region of the semiconductor, and then forming the components by placing an n-type dopant in order to create the electronically active regions of the NMOS component. Each dopant is exposed to a thermal anneal, which restores the crystalline lattice structure of the semiconductor wafer (since some physical placement processes, such as ion implantation, can disrupt the crystalline lattice), and also electronically “activates” the dopant ions by positioning them within the same lattice structure. The components may then be connected through a metallization step, in which metal paths are formed to connect the electronically active areas of the components into a fully interconnected circuit.
It will be appreciated that the placement of the dopant is a key step in semiconductor component fabrication. For many semiconductor components, the characteristics of doping, such as the choice of dopant, the placement method, and the resulting concentration and area of the dopant, dopant concentration vertical and lateral gradient, bear critically on the resulting performance and reliability of the components. One scenario, for example, that requires precise placement is in the formation of source/drain regions of a MOSFET transistor. A typical transistor comprises two electronically active areas that serve as the source and drain regions of the transistor, which are bridged by a gate. When the gate is powered above a certain threshold voltage, a conductive channel is formed between the source and drain regions to close the circuit; but when the gate is unpowered, the channel resists such electronic flow.
In this context, the characteristics of the source/drain region doping relate to the threshold voltage of the gate and the resistance of the channel in powered and unpowered states. If the dopant concentration is too low, or if the source and drain are too distant, the threshold voltage will be undesirably high. If the dopant concentration is too high, or if the source and drain regions are too close, the threshold voltage will be undesirably low, and the resistance in the unpowered state may be insufficient to prevent electron flow. With prior art techniques, it is extremely difficult to achieve uniform doping across a large substrate due to dose variation. In addition, it is difficult to control the doping profile.
In order to improve large scale integrated circuit (LSI) performance, the integrated density or miniaturization of the elements used to configure an LSI has been enhanced. In order to miniaturize elements, reduction in the area of an impurity diffusion region, as well as formation of a shallower diffusion region along the depth of the diffusion are required.
With miniaturization of silicon devices, controlled doping of the silicon devices either for contacts or channel materials becomes very important. The Standard approach for doping through high energy implantation sometimes produces problems like amorphization of the silicon. Another approach which has been reported in the literature is doping through self-assembly of phosphorous containing organic compounds on silicon and anneal the capped substrate at high temperatures. In this approach, although the extent of doping can be controlled, the presence of carbonaceous materials in the silicon results in diffusion of carbon in the silicon and formation of unwanted carbides.
USPTO Backgrounds
USPTO Backgrounds