In general, semiconductor devices are classified into lateral semiconductor devices, wherein electrodes are formed on one surface of a semiconductor substrate, and vertical semiconductor devices, which have electrodes on both surfaces of a semiconductor substrate. In the vertical semiconductor device, a direction in which a drift current flows in an on-state, and a direction in which a depletion layer caused by a reverse bias voltage extends in an off-state, are the same. In a conventional planar n-channel vertical MOSFET (MOSFET: metal oxide semiconductor field effect transistor), a high resistivity n− drift layer works as a region that makes a drift current flow in the vertical direction in the on-state. Consequently, as the drift resistance is reduced by shortening the current path of the n− drift layer, an advantage lowering the on-resistance of the MOSFET is obtained.
Meanwhile, the high resistivity n− drift layer is depleted in an off-state in order to increase a breakdown voltage. Therefore, when the n− drift layer becomes thinner, the width of a drain-to-base depletion layer spreading from a p-n junction between a p-base region and the n− drift layer becomes smaller, and the breakdown voltage decreases. Conversely, as the n− drift layer is thick in a semiconductor device with high breakdown voltage, the on-resistance increases and the conduction loss increases. In this way, there is a trade-off relationship between on-resistance and breakdown voltage.
It is known that this trade-off relationship is also established in the same way in a semiconductor device such as an IGBT (insulated gate bipolar transistor), bipolar transistor, or diode. Also, the trade-off relationship is also the same in a lateral semiconductor device, wherein a direction in which a drift current flows in the on-state, and a direction in which a depletion layer caused by a reverse bias extends in the off-state, are different.
In the specification and attached drawings, a layer or region being prefixed by n or p means that a large number of electrons or positive holes respectively are carriers. Also, + or − appended to n or p means that there is a higher impurity concentration or lower impurity concentration than in a layer or region to which + or − is not appended.
FIG. 39 is a sectional view showing a heretofore known superjunction semiconductor device. As a method of solving, the problem caused by the heretofore described trade-off relationship, a superjunction (SJ) semiconductor device is commonly known, wherein the drift layer is a parallel p-n layer 120 with an n-type region 101, with an increased impurity concentration, and a p-type region 102 are repeatedly alternately joined. A p-base region 103, an n-type surface region 104, a p contact region 105, an n source region 106, a gate insulating film 107, a gate electrode 108, an interlayer insulating film 109, and a source electrode 110 are provided as a surface structure in an active portion. A drain electrode 112 in contact with an n+ drain region 111 is provided on a second main surface (for example, refer to Patent Document 1, Patent Document 2, and Patent Document 3). The parallel p-n layer 120 is provided between the surface structure and the n+ drain region 111.
FIG. 40 is a diagram showing impurity concentration distributions of the superjunction semiconductor device shown in FIG. 39. FIG. 40 shows an n-type impurity concentration distribution (along a cut line AA-AA′) in the second main surface side direction (hereafter referred to as the depth direction) from an end portion (hereafter referred to as the upper end) on the first main surface side of the n-type surface region 104, and a p-type impurity concentration distribution (along a cut line of BR-RW) in the depth direction from the upper end of the p+ contact region 105. A first depth d0 is the depth from the upper end of the p-base region 103 to an end portion (hereafter referred to as the lower end) on the second main surface side of the p-base region 103. A second depth d10 is the depth from the lower end of the p-base region 103 to the lower end of the p-type region 102. In FIG. 39, the impurity concentrations of the n-type region 101 and p-type region 102 are even in the depth direction.
In a semiconductor device with this kind of structure, as a depletion layer spreads in a lateral direction from each p-n junction extending in the vertical direction of the parallel p-n layer when in an off-state, depleting the whole drift layer, even when the impurity concentration of the parallel p-n layer is high, it is possible to achieve a high breakdown voltage.
Also, the following kind of device is proposed as another superjunction semiconductor device that achieves an improvement in breakdown voltage and a reduction in on-resistance. The device has a superjunction structure formed by cyclically and alternately disposing a first n-type pillar layer, a p-type pillar layer, and a second n-type pillar layer on an n+ type drain layer. The p-type pillar layer and second n-type pillar layer are such that the impurity concentration on a source electrode side is higher than that on a drain electrode side (for example, refer to Patent Document 4).
Also, as another device, the following kind of device is proposed. The device has a first conductivity type first semiconductor pillar layer formed on a main surface of a first conductivity type first semiconductor substrate, a second conductivity type second semiconductor pillar layer adjacent to the first semiconductor pillar layer, a first conductivity type third semiconductor pillar layer adjacent to the second semiconductor pillar layer, and a second conductivity type semiconductor base layer provided on an upper surface of the second semiconductor pillar layer, and a MOS transistor is formed on the semiconductor base layer. The carrier concentration in an upper side region of the first to third semiconductor pillar layers is set to be higher than the carrier concentration in a lower side region (for example, refer to Patent Document 5).
Also, as another device, the following kind of device is proposed. There is a parallel p-n structure portion wherein an n-type drift region and a p-type partition region are alternately disposed on an n+ drain region, a p-base region is formed on the p-type partition region, and an n+ source region and p+ contact region are formed selectively on a surface layer of the p-base region. A surface n-type drift region with a high impurity concentration is formed above the n-type drift region. A gate electrode is provided across a gate insulating film on the front surface of a p-base region sandwiched by the surface n-type drift region and source region. A source electrode is provided in contact with the front surfaces of both the n+ source region and p+ contact region, and a drain electrode is provided in contact with the backside surface of the n+ drain region. An insulating film is provided in order to isolate the gate electrode and source electrode (for example, refer to Patent Document 6).
Also, as another device, the following kind of device is proposed. A vertical power MOSFET includes a) a drain contact provided on one surface of the MOSFET, including a first conductivity type substrate doped to a high level on the drain contact, b) a blocking layer provided on the opposite side of the substrate to the drain contact, including i) a first plural vertical sections, being parallel hexahedrons having six quadrilateral surfaces, that have a horizontal direction thickness shorter than a vertical direction thickness of the blocking layer, wherein ii) P-conductivity type vertical sections and N-conductivity type vertical sections are alternately disposed on the first plural vertical sections, c) a second plural well regions of a second conductivity type opposite to the first conductivity type provided on one surface of the blocking layer on the side opposite to the substrate, d) a first conductivity type third plural source regions doped to a high level, wherein two of the source regions are disposed inside each of the second plural well regions, e) a fourth plural regions of the first conductivity type provided on one surface of the blocking layer on the side opposite to the substrate, wherein each region extends between two well regions of the second plural well regions, and f) a fifth plural gate poly regions, wherein each gate poly region stretches over one source region inside two adjacent well regions and one of the fourth plural regions (for example, refer to Patent Document 7).
Also, as another device, the following kind of device is proposed. The device includes a first conductivity type first semiconductor layer, a first main electrode electrically connected to the first semiconductor layer, a second conductivity type second semiconductor layer formed inside the first semiconductor layer, disposed cyclically in a lateral direction, wherein the distribution of an amount of impurity in a vertical direction differs from the distribution of an amount of impurity in the vertical direction inside the first semiconductor layer, a second conductivity type third semiconductor layer formed selectively on the surfaces of the first semiconductor layer and second semiconductor layer, a first conductivity type fourth semiconductor layer formed selectively on the surface of the third semiconductor layer, a second main electrode formed so to be joined to the surfaces of the third semiconductor layer and fourth semiconductor layer, and a control electrode formed across a gate insulating film on the surfaces of the first semiconductor layer, third semiconductor layer, and fourth semiconductor layer. The first semiconductor layer has a distribution such that the impurity concentration increases in a vertical direction from the second main electrode toward the first main electrode, while the second semiconductor layer has a distribution such that the impurity concentration is even in a vertical direction from the second main electrode toward the first main electrode (for example, refer to Patent Document 8).
Also, as another device, the following kind of device is proposed. A semiconductor includes first and second main surfaces, main electrodes provided on each of the first and second main surfaces, a first conductivity type low resistance layer between the first and second main surfaces, and a parallel p-n layer wherein a first conductivity type region and a second conductivity type region are alternately disposed, wherein the impurity concentration in the second conductivity type region on the first main surface side is higher than the impurity concentration in the adjacent first conductivity type region, and the impurity concentration in the second conductivity type region on the second main surface side is lower than the impurity concentration in the adjacent first conductivity type region. The impurity concentration in the second conductivity type region is even in the depth direction, and the impurity concentration in the first conductivity type region on the first main surface side is lower than the impurity concentration in the first conductivity type region on the second main surface side (for example, refer to Patent Document 9).
Also, as another device, the following kind of device is proposed. The device includes first conductivity type second semiconductor layers and second conductivity type third semiconductor layers alternately disposed on a first conductivity type first semiconductor layer. The device further includes second conductivity type fourth semiconductor layers disposed so as to be in contact with an upper portion of each third semiconductor layer between the second semiconductor layers, and first conductivity type fifth semiconductor layers formed on the surface of each fourth semiconductor layer. The first semiconductor layer is such that a first conductivity type impurity concentration is lower than that of the second semiconductor layers. The third semiconductor layers include a base portion, and portions with a high amount of impurity locally formed in such a way that the amount of impurity in the depth direction is greater than that of the base portion (for example, refer to Patent Document 10).
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