1. Field of the Invention
The present invention relates to a data processing apparatus having error code generation circuitry configured to generate an error code associated with a data value. More particularly, this invention relates to such a data processing apparatus wherein the error code is constructed such that a bit change in the data value can be known about by reference to the error code.
2. Description of the Prior Art
In a data processing apparatus which stores data values, it is known to provide error code generation circuitry which generates an error code associated with a data value, the error code being constructed such that a bit change in a data value can be known about by reference to the error code. This error code may be configured as a error detection mechanism, for example where the error code is a parity value generated from the bits of the data value, which enables a bit change in the data value to be detected, although not corrected. Alternatively it is also known to provide more extensive error codes which allow not only the detection of an error in the data value but the correction of that error as well (as long as the error is not too extensive). Many of these error detection and correction techniques refer back to the seminal paper “Error detecting and correcting codes”, R. W. Hamming, Bell Systems Technical Journal, 29 (2): 147-163, 1950. An overview of the relevant error coding techniques can be found in “Architecture Design for Soft Errors”, Elsevier Inc, 2008 by S Mukherjee in Chapter 5, pages 161-178.
As one example, it is known to provide error detection and correction (EDC) codes which are generated according to a “single error correction double error detection” (SEC-DED) code, for example a (72, 64) SEC-DED code for protecting a 64 bit data value. Such SEC-DED codes are known for example from “A class of optical minimum odd-weight-column SEC-DED codes”, M. Y. Hsiao, IBM Journal of Research and Development, v.14 n.4, pages 395-401, July 1970. The SEC-DED codes are based on parity matrices which define a number of syndromes which are to be calculated from a data value wherein each syndrome comprises a parity calculation using a different subset of bits from the data value, together with a bit taken from an error code previously generated in association with the data value (and itself generated in accordance with the same subset of bits of the data value), such that a bit pattern generated from the defined syndromes allows a determination of whether no error is present in the data value (with respect to the value its had when the error code was generated), whether a single bit value has changed (and the bit location of that change, thus enabling the bit change to be corrected), or whether a double bit error has occurred, but not enabling this double bit error to be corrected. More complex error correction codes are also known, which for example allow double error correction and triple error detection, at the cost of an increased number of error code bits.
The protection of data stored in a data processing apparatus against bit changes that may occur is clearly a desirable technique. Such bit changes may for example result from particle strikes as described in “Accelerated testing for cosmic soft-error rate”, J. F. Ziegler, et al., IBM J. Res. Dev. 40, 1 (January 1996), 51-72, 1996.
The above mentioned error detection and correction techniques have established themselves as useful and reliable mechanisms for protecting data stored in a data processing apparatus against bit changes which may result from natural causes such as particle strikes, or may alternatively result from an invasive attack by an attacker seeking to disrupt the operation of the data processing apparatus or to derive information about the data processing activities which it is carrying out or the data values stored within it.
USPTO Backgrounds
USPTO Backgrounds