1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, the present invention is suitable for use in a self-timing semiconductor memory device that internally performs operation timing control.
2. Description of the Related Art
Conventionally, in a semiconductor memory such as a SRAM (static random access memory), process variation (variation among memory macros and variation among adjacent transistors, and so on) occurring in fabrication processes sometimes influenced the operation of the semiconductor memories.
A possible method for alleviating the influence given by the process variation to the operation of a semiconductor memory is a method of operating the semiconductor memory at a fixed operation timing with a sufficient timing margin, but the use of this method hinders a high-speed operation of the semiconductor memory.
In view of the above, there have been such semiconductor memories as described in, for example, Japanese Patent Laid-open No. Hei 7-93972 and Japanese Patent Laid-open No. Hei 11-339476. In these semiconductor memories, provided is a dummy bit line pair to which dummy memory cells are connected, and the operation timing is internally controlled through the use of the dummy bit line pair, thereby solving the above-stated problem. These semiconductor memories, which are called “self-timing memories”, have achieved the alleviation of the influence given by the process variation to the operation while preventing the decrease in the operating speed.
FIG. 8 is a block diagram showing the configuration of a conventional self-timing memory. In FIG. 8, 81 denotes a memory cell array constituted of a plurality of memory cells, 83 denotes a decoder, 84 denotes a read/write amplifier, and 85 denotes a timing control circuit. The memory cell array 81 has at an end portion thereof a dummy memory cell column 82 constituted of dummy memory cells connected to a set of dummy bit lines (one dummy bit line pair).
For example, when an input signal INS including an address signal and so on is inputted from an external part and a read demand of data stored in a memory cell is given, the timing control circuit 85 outputs a control signal CTLA including address information for the selection of the memory cell to the decoder 83 based on the input signal INS. The timing control circuit 85 also outputs a control signal CTLB including a sense amplifier activating signal to the read/write amplifier 84.
The decoder 83 selectively activates a word line WLm (m, which is a suffix, is a natural number) according to the control signal CTLA supplied thereto. Consequently, the action of the memory cell selected by the activated word line WLm causes a change in potential of a bit line pair BLn, /BLn (n, which is a suffix, is a natural number). Here, the bit line /BLn is a bit line complementary to the bit line BLn.
Further, the read/write amplifier 84 activates, according to the control signal CTLB supplied thereto, a not-shown sense amplifier provided therein to amplify the potential read to the bit line pair BLn, /BLn, and outputs it to an external part as data DT.
The self-timing memory is so configured that, in the above-described operation, the timing control for driving the word line WLm and the timing control for activating the sense amplifier in the read/write amplifier 84 are performed based on a signal DS supplied by one dummy bit line pair to which the dummy memory cells are connected.
For example, when it is judged based on the supplied signal DS that a potential in the dummy bit line pair has reached a predetermined potential, the activated sense amplifier activating signal is outputted to activate the sense amplifier in the read/write amplifier 84. Further, for example, after a predetermined period has passed after the potential in the dummy bit line pair has reached a predetermined potential, the activated word line WLm is inactivated to bring all the word lines WLm into a inactivated state.
Here, only one dummy bit line pair to which the dummy memory cells are connected is provided in the conventional self-timing memory, as shown in FIG. 8. Further, in recent years, the process variation in semiconductor memories has been giving a more significant influence to the operation of the semiconductor memories as the memory capacity is becoming larger and process technology is becoming more microscopic in response to the demand for higher performance.
Therefore, when the operation timing in a semiconductor memory is controlled through the use of one dummy bit line pair as in the conventional self-timing memory, the influence given by the process variation to the operation cannot be alleviated due to a large process variation and arbitrary (random) distribution thereof in the semiconductor memory. As a result, the influence of the process variation may possibly become significant.
Especially when a large number of bit line pairs are provided and the number of dummy memory cells acting on the dummy bit line pairs is extremely small (for example, two or the like) compared with the number of memory cells connected to each of the bit line pairs, it is very difficult to reliably alleviate the influence given by the process variation to the operation through the use of only one dummy bit line pair.
USPTO Backgrounds
USPTO Backgrounds