The desire for improved performance and reduced cost of manufacture has driven integrated circuit designs to extreme integration densities and small feature sizes. High density of integration provides reduced signal propagation time and potentially higher clock speeds as well as reduced susceptibility to noise. High density of integration also provides for increased functionality to be provided on a semiconductor chip of a given size and thus supports economy of manufacture since additional functionality can often be achieved with a given sequence of material deposition and etching processes. However, higher integration density can also compromise resistance to breakdown between closely spaced structures at a given voltage and can also cause increased heating while potentially reducing the capacity of the chip to dissipate the heat generated thereon, particularly at higher clock speeds.
Accordingly, recent trends in integrated circuit designs have attempted to reduce heat generation by operation at lower voltages. However, at such lower voltages it is more difficult to control conduction in the channels of FETs of conventional designs where the conduction channel is formed in the substrate or even in a thin layer of semiconductor material such as so-called semiconductor on insulator (SOI) layers. Thus the use of low voltage compromises the on/off resistance ratio and operating margins and increases noise susceptibility of Field Effect Transistors (FETs) of conventional designs.
Accordingly, there has been much recent interest in so-called finFET designs where the conduction channel is formed as a raised fin. This type of structure can provide not only a very thin conduction channel but also allows the gate structure to be provided on two or three sides thereof so that the conduction channel can be more fully controlled at low voltage.
However, due to the small size of finFETs, it is necessary to apply sidewalls to the gate structure to facilitate location of impurity implants in the conduction channel. It is also necessary to be able to make connections to the ends of the fins which form the source and drain regions of the finFET. Therefore, the ends of the fins must be free of sidewall material. As is familiar to those skilled in the art, sidewalls are generally formed, particularly at sizes or thicknesses which are smaller than can be resolved lithographically, by applying an isotropic deposit or blanket layer of sidewall material (usually a mechanically robust and selectively etchable insulator such as a nitride) and then etching that layer with an anisotropic etch. Such a technique also deposits sidewall material on the fins and the anisotropic etch thus leaves sidewalls on at least the fin sides, as well. Since selectivity of etching is not possible in such circumstances and the sidewall thicknesses are below that which can be resolved lithographically, one known technique for removing sidewall material from the fins while leaving some sidewall material on the sides of the gate stack was to form the gate stacks of increased height (which, itself, may compromise manufacturing yield) and to perform an aggressive spacer over-etch; which operations clearly introduce severe process criticalities and may damage the gate stack spacers and/or the fins. Conversely, relatively slight changes in process parameters that reduce the over-etch may leave spacer material in place on the fins. Therefore, it can be readily appreciated that such an aggressive over-etch technique for removing spacer/sidewall material from the fins of a finFET while retaining spacer/sidewall material on the gate stack has an extremely small and critical process window and is of marginal reliability while clearly compromising manufacturing yield.
USPTO Backgrounds
USPTO Backgrounds