1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device using an SOI (Silicon on Insulator) substrate and a method of manufacturing the same.
2. Description of the Related Art
Recently an LSI (Large Scale Integrated Circuit) wherein a large number of transistors, resistors, etc. are formed integrally on a single chip to constitute an electric circuit, has recently been used widely in portions essential to a computer and a communication apparatus. Thus, the performance of the entire computer or apparatus greatly depends upon that of an LSI included therein.
The performance of an LSI itself can be improved by the use of, e.g., an SOI substrate which is excellent in element separation. If an element separating groove is formed in the vicinity of an element forming region to such a depth as to reach a silicon oxide layer (buried oxide layer) of the SOI substrate, the element separation can be greatly improved and the parasitic capacitance can be greatly diminished, as compared with the case of using a silicon substrate.
However, a conventional MOS transistor wherein a mesa element separation is performed using an SOI substrate, has the following drawbacks.
That is, since electric fields are concentrated on a thin silicon oxide layer at the end of an element separating or isolation region at the edge of a channel region of the MOS transistor in the direction of the channel width by the voltage (gate voltage) applied to the gate of the transistor, a parasitic transistor occurs and thus a sub-threshold coefficient (S coefficient) varies. The concentration of electric fields causes a breakdown on the silicon oxide layer.
To resolve the above drawbacks, a technique of forming a thicker side-wall insulating layer at the end of an element separating region is developed (it is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 6-268224). According to this technique, since a monocrystal silicon layer formed at the end of the element separating region is covered with a thicker silicon oxide layer (side-wall insulating layer), a parasitic transistor and an insulation breakdown can be prevented from being caused due to the concentration of electric fields, unlike the case where the monocrystal silicon is covered with a thin silicon oxide layer.
The inventors have found that the above technique has the following problems.
It is desirable to normally use a silicon oxide layer as a buried insulating layer and also do a silicon oxide layer having a small dielectric constant as a side-wall insulating layer in order to mitigate the concentration of electric fields. In the step of etching the entire surface of the structure, therefore, the silicon oxide layer serving as a side-wall insulating layer and the silicon oxide layer serving as a buried insulating layer are etched at the same time, and a large underlying layer step is formed. It is thus difficult to form an upper wiring layer such as a gate wiring in the subsequent step. To put it in an extreme way, the silicon oxide layer is etched to the surface of a silicon substrate and, in this case, there is danger that the upper wiring layer will be short-circuited.
Since, furthermore, a gate section is formed after the side-wall insulating layer is formed, the silicon oxide layer is etched in the same step of removing a nature oxide layer from the surface of the monocrystal silicon layer, with the result that the silicon oxide layer is decreased in thickness and the concentration of electric fields cannot be reduced to a desired extent.
USPTO Backgrounds
USPTO Backgrounds