Advances in the fields of graphics imaging and video processing have generated a demand for high performance data processing systems with increased processor speeds and high performance memory architectures. Traditionally, processor speeds exceeded access speeds of random access memory (RAM) devices. As a result, while the processor ran synchronously with the system clock signal, RAM operated "asynchronously" with the system clock signal. This implied that the RAM device operated at a clock signal that was independent of, and slower, than the system clock signal. In such systems, even though the processor operated at increased speeds, the efficiency of data processing operations was limited by the slow speed of asynchronous memory operations.
The advent of synchronous high performance memory architectures has greatly reduced memory access times. In synchronous memory architecture systems the processor and RAM devices operate "synchronously" in response to a common system clock signal. This implies that both the processor and synchronous memory device are clocked by the same system clock signal. The use of the system clock increases the memory bandwidth and also decreases the memory access time.
FIG. 1 depicts a typical prior art data processing system 100 incorporating a high performance synchronous memory architecture. As shown in FIG. 1, data processing system 100 mounted on PC board 102 comprises processor 104 coupled to memory controller 106, which in turn is coupled to synchronous RAM 108.
Processor 104, memory controller 106 and synchronous memory 108 work synchronously with system clock signal "sysclk" 110 generated by system clock 112.
Processor 104 receives memory access requests which are then forwarded to memory controller 106. Memory controller 106 controls access to synchronous memory 108 and is responsible for processing memory access requests received from processor 104. Memory controller 106 comprises controller clock circuit 114 which receives the "sysclk" system clock signal 110 generated by system clock 112, control signal logic circuit 116 which receives control signals 122 generated by processor 104 in response to a memory read/write command, address buffer 118 to store the memory address whose contents are to be read from or written to and data buffer 120 to store data read from synchronous memory 108. Due to the synchronous nature of the memory architecture, controller clock circuit 114 provides the system clock signal "sysclk" 110 to control signal logic circuit 116 , address buffer 118 and data buffer 120 without any modification. Control signals 122 include signals such as the row address strobe (RAS), the column address strobe (CAS) and the read/write enable (RWEN/WEN) signals which are required to perform memory access operations. "Sysclk" system clock signal 110, control signals 122 and the memory address are routed to synchronous RAM 108 via pads 124a, 124b and 124c, respectively.
Synchronous memory 108 comprises memory clock circuit 126 which receives the "sysclk" system clock signal 110 from memory controller 106 via pads 124a and 134a, memory control signal logic circuit 128 which receives control signals from memory controller 106 via pads 124b and 134b, address decoder 130 which receives the memory address from memory controller 106 via pads 124c and 134c, and memory data buffer 132 which stores the memory contents. Due to the synchronous nature of the memory architecture, memory clock circuit 126 provides "sysclk" signal 110 to memory control signal logic circuit 128, address decoder 130 and memory data buffer 132 without any modification. Address decoder 130 parses the memory address into a row address component and a column address component. The row and column address components, along with the control signals received by memory control signal logic circuit 128, are forwarded to memory data buffer 132. In the case of a "read" control signal, data read from memory data buffer 132 corresponding to the row and column addresses is routed to data buffer 120 of memory controller 106 via pads 134d and 124d.
Although the synchronous RAM architecture depicted in FIG. 1 presents substantial improvements over asynchronous memory devices in the time required to access RAM, synchronous RAM devices are difficult to implement because the high system clock frequency greatly reduces the time available to complete a memory "read" operation. Due to the increased "sysclk" frequency, the time period (t.sub.sysclk) which is the inverse of "sysclk" frequency, allocated for completion of a memory "read" command is very small. FIG. 2 depicts a "sysclk" system time signal timing diagram illustrating the time period (t.sub.sysclk) available for completion of a synchronous memory "read" operation in a prior art system. In FIG. 2, the "read" command is issued by memory controller 106 at rising edge 134 of "sysclk" system clock signal 110. Memory controller 106 expects valid data read from synchronous memory 108 to be available at rising edge 136 of "sysclk" 110. The time interval between rising edge 134 and rising edge 136 represents the time period (t.sub.sysclk) available for completion of the "read" operation.
Time period "t.sub.sysclk " includes "routing access time" (t.sub.rac) which represents the time required for the propagation of the "read" command signals through the various memory architecture components and "data valid window time" (t.sub.dv) which represents the window of time when valid data read from memory data buffer 132 is available to be clocked in by memory controller 106 into data buffer 120. As shown in FIG. 2 (and FIG. 1), routing access time "t.sub.rac " in turn is comprised of the following time delays summarized in Table 1:
TABLE 1 ______________________________________ "Routing access time" delays Delay Period Delay Name Description of Delay ______________________________________ t.sub.mcd Memory controller This represents the time delay required routing delay to route the "read" command signals from memory controller 106 to pads 124a,b,c. t.sub.pcrd PC board routing This represents the time delay required delay to route the "read" command signals on PC board 102 from pads 124a,b,c to pads 134a,b,c. t.sub.mrd Memory routing This represents the time delay required delay to route the "read" command signals from pads 134a,b,c to memory clock circuit 126, memory control signal logic circuit 128 and address decoder 130, respectively. t.sub.macd Memory access This represents the time delay required delay to access the contents of memory data buffer 132 in response to the row and column addresses provided by address decoder 130 and time delay required to route the data to pad 134d. t.sub.pcrd PC board routing This represents the time delay required delay to route the data read from synchronous memory 108 from pad 134d to pad 124d on PC board 102. t.sub.dbrd Data buffer routing This represents the delay required to delay route the data from pad 124d to data buffer 120 in memory controller 106. ______________________________________
Due to the high frequency of system clock signal "sysclk" 110, the aggregate effect (t.sub.mcd +t.sub.pcrd +t.sub.mrd +t.sub.macd +t.sub.pcrd +t.sub.dbrd) of the time delays, which represents the total time required for the propagation of the "read" command signal through the various memory architecture components, becomes quite substantial with respect to overall time period "t.sub.sysclk " available for the "read" command. Consequently, as shown in FIG. 2, the "data valid window time" (t.sub.dv) is greatly reduced and does not represent enough setup and hold time for memory controller 106 to clock in the data. As a result, the validity of data read from synchronous memory device 108 by memory controller 106 cannot be assured.
For example, a 100 Mhz synchronous memory running synchronously with a 100 Mhz system clock has a time period (t.sub.sysclk) of 10 nanoseconds to complete the "read" operation. The typical access time (t.sub.mrd +t.sub.macd) for such a memory device not including routing is approximately 9 nanoseconds. For example, the access of Synchronous Graphics RAM ("SGRAM") about 9 nanoseconds. With such latency, the memory controller has less than 1 nanosecond left for setup and hold time (t.sub.dv) on the data read from memory. Memory designers cannot guarantee the correctness of data at such reduced data valid window times. Typically, at least a 3 nanosecond data valid window time value (t.sub.dv) is required to assure correctness of data. The problems are further aggravated when memory controller 106 interfaces with multiple synchronous memory modules or SIMMS. As the "load" of the memory system increases, the routing access delays (t.sub.rac) become more pronounced, thus further reducing the data valid window time.
Prior art solutions to the above problem include using faster synchronous memory devices with slower system clock frequencies. For example, a 125 Mhz synchronous memory with a routing access time of 8 nanoseconds is used to run at 100 Mhz system clock. However, faster memories are expensive and consequently a price premium is imposed on the whole data processing system. Furthermore, using faster memories defeats the purpose of synchronous memories which is to provide a memory architecture which can operate synchronously with the system clock. Thus, it is desirable to provide an apparatus and method which guarantees validity of data accessed from synchronous memory operating at a high system clock frequency.
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USPTO Backgrounds