Solid state memories (SSMs) often comprise one or more arrays of individually programmable memory cells configured to store data by the application of write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read operation by applying suitable read currents and sensing voltage drops across the cells.
A continued trend is to provide SSM arrays with larger data capacities and smaller manufacturing process feature sizes. While operable in providing greater data storage capacity and density levels, the use of increasingly larger arrays and/or smaller feature sizes can lead to significant increases in inadvertent operational variance, such as variations in the sensing of logical states in cross-point arrays of memory.
With increasing usage of bi-polar memory cells in SSM, it has been found that unwanted current can be induced along various control lines. Such unwanted current can be great enough to cause the inadvertent programming of memory cells. This can make it difficult to accurately write or read a programmed state of a particular memory cell, particularly when relatively small magnitudes of sense voltages are used. Therefore, there is a need for more efficient anti-parallel diode designs.
USPTO Backgrounds
USPTO Backgrounds