This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-185119, filed Jun. 30, 1999; and No. 2000-189937, filed Jun. 23, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to an integrated circuit device, its manufacturing method, a circuit board and a method of manufacturing the same.
A monolithic IC having an active element such as a transistor and a passive element such as a resistor, a capacitor or an inductor integrated on a semiconductor substrate is low in manufacturing cost, permits suppressing the power consumption, and can be miniaturized, and thus, the monolithic IC can be formed as a one chip.
However, where an inductor is formed on a semiconductor substrate, a parasitic capacitance and a parasitic resistance (eddy current loss) are generated between the conductor forming the inductor and the semiconductor substrate. Therefore, in order to obtain an inductor having a high Q factor, it is necessary to lower the parasitic capacitance and the parasitic resistance.
As a method for lowering the parasitic capacitance and the parasitic resistance, proposed is a method of forming an inductor above a groove formed on the surface of a semiconductor substrate. To be more specific, it is proposed in, for example, U.S. Pat. No. 5,539,241, that an inductor is formed in an air-floating wiring structure so as to increase the distance between the inductor and the semiconductor substrate and, thus, to lower the parasitic capacitance and the parasitic resistance.
In the conventional structure exemplified above, however, it was impossible to ensure a sufficient mechanical strength because the inductor is floating in the air.
It is also proposed to form an active element such as a transistor and a passive element such as a capacitor or an inductor on different substrates, followed by bonding these elements by using a bump, as disclosed in, for example, ISSCC98/SESSION 16, DIGEST OF TECHNICAL PAPERS, pp 248-249.
However, the substrate having an active element formed thereon and the substrate having a passive element formed thereon are arranged such that the element-forming surfaces are allowed to face each other. It follows that the semiconductor substrate having, for example, a transistor formed thereon is apart from the inductor by only a distance determined by the bump. As a result, it was difficult to lower sufficiently the influence of the semiconductor substrate having the transistor formed thereon.
Also, a circuit board having a conductive connecting portion formed within an insulating layer is known to the art. In the conventional technology, however, it is difficult to control the shape of the conductive connecting portion, and the step for forming the conductive connecting portion is made complex.
A first object of the present invention is to provide an integrated circuit device having an active element and a passive element formed on a single semiconductor substrate, in which the parasitic capacitance and the parasitic resistance can be lowered sufficiently and a sufficient mechanical strength can be obtained, and a method of manufacturing the particular integrated circuit device.
A second object of the present invention is to provide an integrated circuit device prepared by connecting by a suitable means a semiconductor substrate having an active element formed thereon and another substrate having a passive element formed thereon, in which the influence of the semiconductor substrate can be sufficiently lowered, and a method of manufacturing the particular integrated circuit device.
Further, a third object of the present invention is to provide a circuit board having a conductive connecting portion extending through an insulating layer, in which the shape of the conductive connecting portion can be controlled easily or the process for forming the conductive connecting portion can be simplified, and a method of manufacturing the particular circuit board.
According to a first aspect of the present invention, there is provided an integrated circuit device, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 xcexcm, and a passive element formed directly or indirectly on the insulating region.
According to a second aspect of the present invention, there is provided a method of manufacturing an integrated circuit device, comprising forming a groove having a depth of at least 20 xcexcm on the side of one main surface of a semiconductor substrate; forming an active element on the side of the main surface of the semiconductor substrate; burying an insulating material in the groove to form an insulating region; and forming a passive element directly or indirectly on the insulating region.
In each of the first and second aspects of the present invention, it is desirable for the passive element to be an inductor, particularly, a spiral inductor. It is desirable for the conductive material forming the inductor to contain as a main component Cu, Au, Ag or Al.
According to the first and second aspects of the present invention, an insulating material is buried in a groove having a depth of at least 20 xcexcm formed on the side of the main surface of the semiconductor substrate, and a passive element is formed directly or indirectly on the insulating region formed by burying the insulating material. It follows that it is possible to lower sufficiently the parasitic capacitance and the parasitic resistance and to ensure a sufficient mechanical strength.
In the first and second aspects of the present invention, it is desirable to form the groove by an anisotropic etching. It is desirable for the anisotropic etching to be performed by a reactive ion etching, particularly, a high density plasma etching, using a gas containing fluorine. In the present invention, formed is a groove having a depth of at least 20 xcexcm. By employing the anisotropic etching, it is possible to form a groove having a side wall substantially perpendicular to the substrate. Therefore, even in the case of forming a deep groove having a depth of at least 20 xcexcm, the area of the groove-forming region can be diminished to a minimum level. Also, since a deep groove having a depth. of at least 20 xcexcm is formed, it is desirable for the anisotropic etching rate to be higher than the ordinary etching rate. In the present invention, the etching can be performed at a high etching rate because a reactive ion etching is performed by using a fluorine-containing gas.
In the present invention, it is desirable for the insulating region to be formed by pouring an insulating fluid into the groove, followed by solidifying the insulating fluid. Since a deep groove having a depth of at least 20 xcexcm is formed in the present invention, a long time is required for forming the insulating material if the insulating material is formed by a deposition method. The insulating material can be formed efficiently by burying an insulating fluid in the groove, followed by solidifying the insulating fluid, i.e., by using a coated film.
In the first and second aspects of the present invention, it is desirable for the groove to be formed after formation of the active element. In general, a high temperature of about 1,000xc2x0 C. is required for forming the active element. Where the active element is formed in advance before formation of the groove, it is possible to use an insulating film, e.g., an organic coated film, having a low resistance to heat as an insulating material buried in the groove so as to form the insulating material efficiently.
According to a third aspect of the present invention, there is provided an integrated circuit device, comprising a first substrate consisting of a semiconductor substrate and having an active element formed on the side of one main surface; a second substrate having a passive element formed on the side of a first main surface and arranged such that a second main surface opposite to the first main surface faces the main surface of the first substrate; and an electrode extending through the second substrate so as to electrically connect the passive element to the active element.
According to a fourth aspect of the present invention, there is provided a method of manufacturing an integrated circuit device, comprising forming an active element on the side of one main surface of a first substrate; forming a passive element on the side of a first main surface of a second substrate; and allowing a second main surface opposite to the first main surface of the second substrate to face the main surface of the first substrate so as to allow the active element and the passive element to be connected to each other via an electrode extending through the second substrate.
In each of the third and fourth aspects of the present invention, it is desirable for the passive element to be an inductor, particularly, a spiral inductor. It is desirable for the conductive material forming the inductor to contain as a main component Cu, Au, Ag or Al.
According to the third and fourth aspects of the present invention, the distance between the semiconductor substrate having the active element formed thereon and the passive element is larger than at least the thickness of the substrate having the passive element formed thereon, making it possible to lower the influence given by the semiconductor substrate having the active element formed thereon to the passive element.
In the third and fourth aspects of the present invention, it is possible to use a semiconductor substrate as the second substrate. In this case, it is desirable for the resistivity of the semiconductor substrate constituting the second substrate to be higher than the resistivity of the semiconductor substrate constituting the first substrate. It is possible to use a high resistivity Si substrate or a GaAs substrate as the semiconductor substrate constituting the second substrate.
In the third and fourth aspects of the present invention, it is also possible to use an insulating substrate as the second substrate. The insulating substrate used in the present invention includes, for example, an insulating resin substrate (organic insulating substrate) such as a polyimide substrate, a BCB (benzocyclobutane) substrate or an epoxy resin substrate, as well as a quartz substrate or a ceramic substrate.
In the third and fourth aspects of the present invention, the electrode extending through the second substrate can be formed by loading a conductive material in a connection hole made through the second substrate. Alternatively, a projection-like electrode formed on the side of the main surface of the first substrate can be used as the electrode extending through the second substrate.
In the third and fourth aspects of the present invention, it is possible for the active element and the passive element to be electrically connected to each other via the electrode extending through the second substrate and a bump connected to the electrode. By forming the bump, the distance between the semiconductor substrate having the active element formed thereon and the passive element is made larger than the sum of the height of the bump and the thickness of the substrate having the passive element formed thereon so as to further diminish the influence given by the semiconductor substrate having the active element formed thereon.
According to the third and fourth aspects of the present invention, it is possible for an insulating material to be loaded between the main surface of the first substrate and the second main surface of the second substrate. Where the warping of the substrate having a passive element formed thereon generates a problem, the problem can be effectively resolved by the loading of the insulating material.
Further, in the third and fourth aspects of the present invention, it is desirable for the inductor to be formed selectively by a plating treatment or by pattering a metal foil.
According to a fifth aspect of the present invention, there is provided a circuit board, comprising an insulating layer, a conductive connecting portion consisting of a conductive material prepared by solidifying a conductive paste having magnetic properties and extending through the insulating layer, and a conductive pattern formed on at least one main surface of the insulating layer and connected to the conductive connecting portion.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a circuit board, comprising forming a pattern of a conductive paste having magnetic properties on a conductive sheet, followed by solidifying the conductive paste to form a conductive connecting portion; forming an insulating layer on that surface of the conductive sheet on which the conductive connecting portion is formed; and forming a conductive pattern by patterning the conductive sheet in a desired shape.
According to the fifth and sixth aspects of the present invention, the conductive paste has magnetic properties, making it possible to form a pattern of the conductive paste accurately as desired by utilizing the magnetic function. It follows that a conductive connecting portion can be formed easily and accurately by a simple step.
According to a seventh aspect of the present invention, there is provided a method of manufacturing a circuit board, comprising forming a resist pattern having an opening on a conductive sheet; selectively forming a conductive connecting portion within the opening by a plating treatment; removing the resist pattern; forming an insulating layer on that surface of the conductive sheet on which the conductive connecting portion is formed; and forming a conductive pattern by patterning the conductive sheet in a desired shape.
According to the seventh aspect of the present invention, a conductive connecting portion is selectively formed by a plating method within an opening, making it possible to form the conductive connecting portion by a simple step and to improve the bonding strength of the conductive connecting portion.
According to the fifth, sixth and seventh aspects of the present invention, it is desirable for the insulating layer to be formed of a composite material containing polyimide. Particularly, it is desirable to use a composite material containing polyimide having a low elastic modulus of less than 10 GPa. By using a composite material containing such a polyimide, an insulating layer having an excellent adhesivity can be formed easily by, for example, a plating treatment without using an adhesive layer, leading to simplification of the manufacturing process.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
USPTO Backgrounds
USPTO Backgrounds