1. Field of the Invention
The present invention relates to programmable integrated circuit structures and methods for fabrication thereof, and more particularly to amorphous silicon antifuses and circuits and routing structures incorporating antifuses, and methods for fabrication thereof.
2. Description of Related Art
Programmable semiconductor devices include programmable read only memories ("PROMs"), programmable logic devices ("PLDs"), and programmable gate arrays. Programmable elements suitable for one or more of these device types include fuses and antifuses.
A fuse is a structure which electrically couples a first terminal to a second terminal, but which, when programmed by passage of sufficient current between its terminals, electrically decouples the first terminal from the second terminal.
An antifuse is a structure which when unprogrammed does not electrically couple its first and second terminals, but which, when programmed by applying sufficient voltage between the first and second terminals, permanently electrically connects the first and second terminals. One type of antifuse comprises an amorphous silicon which forms conductive polysilicon when heated.
FIG. 1 illustrates an example of antifuse technology for a CMOS circuit. Antifuses 10a and 10b are part of an array of such antifuses that are formed on a silicon semiconductor substrate 14 over an oxide layer 16 using the following process steps. The first layer 18 of TiW is deposited over the entire surface of the substrate 14 and over one or more circuit elements (not shown) which are formed on the substrate 14 by standard CMOS process including steps up to the first metal deposition. The first TiW layer 18 serves two purposes: one, as a protective cover for CMOS transistors (not shown) while antifuses 10 are being formed, and the other is to provide the bottom electrode for antifuses 10. Portions of the first TiW layer 18 are appropriately masked, and the first etch of TiW 18 is performed to define the protective cover and the bottom electrodes.
A layer of dielectric material 20 such as 2000 angstroms of oxide is formed over the TiW layer 18 and then masked and etched to define antifuse vias 22a and 22b. The dielectric 20 is removed over those portions of the first TiW layer 18 which cover and protect the CMOS circuit elements.
A layer 25 of 1500 angstroms of amorphous silicon is deposited over the substrate 14. A second layer 26 of TiW is deposited over the amorphous silicon layer 25. The two layers are masked and etched to define the array of antifuses such as typically shown as 10a, 10b.
Then the structure is masked, and a second etch of the TiW layer 18 is performed to remove the portion of TiW layer 18 that has served as a protective cover for the CMOS circuit elements.
Then first-metal aluminum 27 is formed on the second layer 26 of TiW for each respective antifuse structure 10 when the first metallization for the integrated circuit components is formed. Metal layers 26, 27 provide the top electrodes to antifuses 10.
A standard intermetal dielectric layer 28 is formed over the wafer. Vias like via 29 are etched through dielectric layers 28 and 20 to the first TiW layer 18. A conductor 30 of second-metal aluminum is formed over the dielectric layer 28 and in vias 29. Portions of conductor 30 in vias 29 provide connections between the bottom electrodes 18 and the second metal 30 so as to reduce the connection resistance to the antifuses 10. See generally U.S. Pat. No. 4,914,055 issued Apr. 3, 1990 to Gordon et al.
It is generally desirable to provide a good step coverage when metal is deposited in vias. It is also desirable to protect the structure elements from high temperatures present during manufacturing. Further, it is desirable to maintain the number of etch steps as low as possible. It is also desirable to reduce the circuit capacitance in order to increase the circuit speed.
USPTO Backgrounds
USPTO Backgrounds