All-digital phase locked loop (ADPLL) circuits are in wide spread use today. An ADPLL incorporates a digital phase detector, filter and oscillator. Some ADPLLs utilize a delay line based time to digital converter (TDC) in determining the phase error. Traditional ADPLL implementations, however, tend to consume a considerable amount of power, since the TDC has to cover at least one variable clock period. As an example, if the minimum variable clock frequency is 1 GHz then the time-to-digital converter (TDC) has to cover 1000 ps, which corresponds to 100 inverters at the fastest delay of 10 ps. Simulations indicate that at the maximum frequency end of 2 GHz, a 100-inverter TDC chain consumes 10 mW at 2 GHz, which may comprise the entire ADPLL power budget.
There is thus a need for a circuit that solves the problem of increased power consumption of the TDC circuit in ADPLLs.
Further, another problem associated with conventional ADPLL circuits that utilize delay line TDCs is that they generate fractional spurs in the output. These spurs are particularly visible at near-integer channels and deteriorate the synthesizer performance expressed by the integrated phase noise. For high capacity modulation schemes in wireless communication, a low integrated phase noise (IPN) is required and near-integer channels cannot be avoided in highly reconfigurable ADPLLs that are to be used in software defined radios (SDR).
There is thus a need for an ADPLL circuit that is capable of reducing fractional spurs of the output spectrum in near-integer channels while maintaining desired performance levels.
USPTO Backgrounds
USPTO Backgrounds