1. Field of the Invention
The present invention is related to memory access management, and in particular, to an architecture using a memory frame proxy for accesses to instruction memory in a simulation environment.
2. Description of Related Art
Simulators, debuggers and accelerators that can be implemented in hardware, software or a combination of both, are typically used in verification of program code as well as verification of designs of processor integrated circuits (ICs) and other large-scale logic.
The simulation of instruction fetches and decodes is a compute-intensive task, since each time an access to instruction memory is made by simulated pipeline, if the instruction must be fetched from the simulated instruction memory, the instruction must be decoded, and checks must be performed if there are any associated with the instruction location or operands implicated by the instruction.
Caching of simulations of instruction memory is not a viable technique where instruction memory may be moved by another process, or where self-modifying code may alter the values stored in instruction memory. Therefore, the fetching and decoding of instructions represents a serious bottleneck in simulation throughput and it is desirable to improve the performance simulators, debuggers and the link.
USPTO Backgrounds
USPTO Backgrounds