1. Field of the Invention
This invention relates to a semiconductor switching circuit device to be used for high-frequency switching applications and particularly to a semiconductor switching circuit device with improved isolation at high frequencies.
2. Description of the Related Art
Portable telephones and other mobile communication equipment use microwaves of the GHz band in many cases and switching elements for switching such high frequency signals are often used in a switching circuit for antennas and a circuit switching between transmitting and receiving, such as the ones described in Japanese Laid-Open Patent Publication No. Hei-9-181642. A field effect transistor (referred to hereinafter as “FET”) formed on a substrate made of gallium arsenide (GaAs), which has many excellent characteristics for high frequency signal circuits, is used as the switching element in many cases. Monolithic microwave integrated circuits (MMIC), in which these switching elements are integrated, are being developed accordingly.
FIG. 10A shows a sectional view of a GaAs-based MESFET (metal-semiconductor field effect transistor). An N-type channel region 2 is formed by doping a surface part of an undoped GaAs substrate 1 with an N-type impurity, a gate electrode 3 is placed to be in Schottky contact with the channel region 2 surface, and source and drain electrodes 4 and 5, which are in ohmic contact with the GaAs surface, are placed at both sides of gate electrode 3. With this transistor, the potential of gate electrode 3 is used to form a depleted layer in the channel region 2 immediately below, and the channel current between the source electrode 4 and the drain electrode 5 is controlled thereby.
FIG. 10B is a basic circuit diagram of a compound semiconductor switching circuit device, which is called an SPDT (Single Pole Double Throw) and uses a GaAs FET.
The sources (or drains) of first and second FET's, FET1 and FET2, are connected to a common input terminal IN, the gates of FET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2, respectively, via resistors R1 and R2, respectively, and the drains (or sources) of FET1 and FET2 are connected to first and second output terminals OUT1 and OUT2, respectively. The signals that are applied to first and second control terminals Ctl-1 and Ctl-2 are complementary signals and the FET to which the H level signal is applied turns on to allow the signal applied to the input terminal IN to reach one of the output terminals. Resistors R1 and R2 are placed to prevent the high-frequency signal from leaking via the gate electrodes to the DC potential of the control terminals Ctl-1 and Ctl-2, which are AC grounded.
FIG. 11 shows an example of a compound semiconductor chip in which the compound semiconductor switching circuit device shown in FIG. 10 is integrated.
FET1 and FET2, which perform switching, are placed at the central parts of a GaAs substrate and resistors R1 and R2 are connected to the respective gate electrodes of the FET's. Also, electrode pads INPad, OUT1Pad, OUT2Pad, Ctl-1Pad, and Ctl-2Pad, corresponding to the common input terminae output terminals and the control terminals, respectively, are placed at peripheral parts of the substrate. A gate metal layer (Ti/Pt/Au) 20, which is formed at the same time as the forming of the gate electrodes of the respective FET's, is a second-layer wiring, indicated by dotted lines, and a pad metal layer (Ti/Pt/Au) 30, which connects the respective elements and forms the pads, is a third-layer wiring, indicated by solid lines. An ohmic metal layer (AuGe/Ni/Au), which is in ohmic contact with the substrate, is a first-layer wiring, and forms the source electrodes and drain electrodes of the respective FET's and take-out electrodes of the respective resistors. This layer is not illustrated in FIG. 11 as it overlaps with the pad metal layer.
FIG. 12A is an enlarged plan view of the FET1 shown in FIG. 11. The rectangular region surrounded by alternate long and short dash lines is a channel region 12 that is formed on the substrate 11. The third-layer pad metal layer 30, which takes on the form of comb teeth that extend from the left side, is a source electrode 13 (or drain electrode) that is connected to output terminal OUT1, and a source electrode 14 (or drain electrode), formed by the first-layer ohmic layer 10, is placed below the electrode 13. Also, the third-layer pad metal layer 30 part, which takes on the form of comb teeth that extend from the right side, is a drain electrode 15 (or source electrode) that is connected to common input terminal IN, and a drain electrode 16 (or source electrode), formed by the first-layer ohmic layer 10, is placed below the electrode 15. These electrodes are interdigitated and a gate electrode 17, formed on the channel region 12, is placed in between in the two electrodes.
A sectional view of a part of this FET is shown in FIG. 12B. An n-type channel region 12 and n+-type high concentration regions, which form a source region 18 and a drain region 19 at both sides of channel region 12, are formed on the substrate 11. The gate electrode 17 is placed on channel region 12, and the drain electrode 14 and the source electrode 16, which are made of the first-layer ohmic metal layer 10, are placed on the respective high concentration regions. The pad metal layer 30, which is the third and top layer wiring, also provides connection between the device elements.
FIGS. 13A and 13B show a section of a packaging structure for the semiconductor chip of FIG. 11. FIG. 13A shows a sectional view of the package, and FIG. 13B is a schematic magnified sectional of the packaged FET. A nitride film 50 is formed as a protective film over the entire surface of the chip except above the electrode pad used as the terminals. The compound semiconductor chip 63 is mounted on an island of lead 62 using a conductive paste 65, and the electrode pads of compound semiconductor chip 63 are connected to leads 62 by bonding wires 64. The semiconductor chip 63 is covered by a resin layer 80 using a mold die corresponding to the shape of the packaging. The tip parts of leads 62 extend out of the resin layer 80.
Because of the requirements for wireless networks that enable information transmission at higher density, the operation frequency of those switching circuits is shifting from the 2.4 GHz band to the 5 GHz band. However, it has become known that when the conventional compound semiconductor switching circuit device is used, the isolation becomes less than the designed value. In the conventional switching circuit shown in FIGS. 11 and 13B, when FET1 is on, FET2 is off. In other words, the high-frequency signal that is input into FET2 is not supposed to pass between the source and drain electrodes of FET2, that is, between the common input terminal IN and the output terminal OUT2. However, this is not the case in the conventional device. Because the source electrode—drain electrode distance is extremely fine, for example 3 μm, the high frequency signals pass between the two electrodes through the mold resin layer. Accordingly, the isolation is less than the designed value of the switching circuit.
This leakage of the high frequency signals is not much of problem at the frequency band of 2.4 GHz, as in the case of 2.4 GHz-band wireless LAN and Bluetooth applications, among other applications. However, the degradation of isolation becomes a major a problem at the high frequency band of 5 GHz or higher.
USPTO Backgrounds
USPTO Backgrounds