The present invention relates to a memory card having a non-volatile memory mounted thereon, and a memory controller which is applied to a non-volatile memory card, and in particular to a technology which is effective to apply to a memory card having a hard disc compatible flash memory mounted thereon.
A memory card using an electrically erasable and writable non-volatile memory such a flash memory comprises a non-volatile memory and a memory controller which performs an access control for the memory and an external interface control, which are mounted on a card substrate. Although the number of bits of data transferred between the non-volatile memory and the memory controller may be equal to the number of bits of data of the input and output of the non-volatile memory, the efficiency of the data transfer may be low. Accordingly, it is possible to connect a plurality of non-volatile memories to a memory controller in parallel for increasing the number of parallel bits of data to be transferred. Prior art which focuses on this includes a parallel-writing technique disclosed in JP-A-6-342399 and JP-A-7-36787, and an interleave-writing technique for two flash memories which is disclosed in JP-A-10-187359.
The present inventors have searched a parallel access technique using a plurality of non-volatile memories. The first matter which has been considered is a relation between the storage areas and the alternate control function when an access error has occurred. When an access error such as write error has occurred in, for example, a hard disc compatible memory disc, the alternation (substitution) of storage areas is performed in unit of sector. If the alternation is performed in unit of sector when data of one sector is distributed over a plurality of non-volatile memories, the storage area of a flash memory in which no writing error has occurred may be alternated. This wastes the storage area of the non-volatile memories, resulting in a shortened period of time which is taken for the memory to become non-alternative.
The second matter which has been considered is a relation between the operation of the memory and an error detecting and correction operation which is performed by an ECC and the like. A technique like ECC usually performs addition of an error detection code to write data, and error detection and correction for read data. It has been found from the study of such an error detection and correction that only parallel access to non-volatile memory by the memory controller is insufficient. Even when data is read at a high rate by a memory controller accessing to the plurality of non-volatile memories in a parallel manner, speeding up of access as a whole of a memory card could not be achieved unless the operation of the ECC circuit which conducts the error detection and correction for the read data follow the parallel access operation and/or unless the generation of an error detection code to be added to write data is not fast.
USPTO Backgrounds
USPTO Backgrounds