Various imager circuits have been proposed including charge coupled device (CCD) arrays, complementary metal oxide semiconductor (CMOS) arrays, arrays combining both CCD and CMOS features, as well as hybrid infrared focal-plane arrays (IR-FPAs). Conventional arrays have light-sensing elements, typically referred to as “pixels” and readout circuitry that provides signals indicating light sensed by the pixels.
For example, a CMOS imager includes a focal plane array of pixel cells; each cell includes a photodetector, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photodetector is sent to the floating diffusion node. The imager may also include a transistor for transferring charge from the photodetector to the floating diffusion node and another transistor for resetting the floating diffusion node to a predetermined charge level prior to charge transference.
FIG. 1 illustrates a block diagram of a CMOS imager device 908 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row selected line, and the pixels of each column are selectively output by respective column select lines. A plurality of rows and column lines are provided for the entire array 200. The row lines are selectively activated in sequence by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated in sequence for each row activation by the column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210, 260 which apply driving voltage to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal, Vrst taken off of the floating diffusion node when it is reset and a pixel image signal, Vsig, which is taken off the floating diffusion node after charges generated by an image are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267, which produces a signal Vrst−Vsig for each pixel representing the amount of light impinging on the pixel. This difference signal is digitized by an analog to digital converter 275. The digitized pixel signals are then fed to an image processor 280 to form a digital image.
A type of amplifier commonly used in active pixel sensors (APS) is the source follower, an example of which is illustrated in FIG. 1A. Array 100 includes pixels in rows and columns, with four pixels shown. Each pixel includes a photodetector and a source follower transistor. In pixel 102, for example, photodetector 110 illustratively shown as a photodiode, is connected to source follower transistor 115 which is in turn connected to column readout line 116 by a row select signal on line 118. Load transistor 120 responds to bias voltage Vin, and functions as a current source. As a result, source follower transistor 115 provides a voltage level on line 116 that reflects or follows the voltage level received at its gate from photodetector 110, optionally through a transfer transistor (not shown).
Source follower amplifiers have a number of limitations when used in an APS. For example, typical gains for source follower amplifiers are on the order of 0.8 or lower. In FIG. 1A, source follower 115 senses voltage across photodetector 110, and the conversion gain depends on the capacitance of photodetector 110. If the sensor area of photodetector 110 is increased for high sensitivity, conversion gain decreases accordingly, leaving the output voltage on line 116 substantially unchanged.
Source follower amplifiers also have limited output swing and linearity. For example, the output voltage of source follower transistor 115 is limited because the current source transistor 120 drops out of saturation causing the gain to drop even lower. In addition, the output voltage swing is limited on the downward side when the photodiode loses its reverse bias. Also, the signal collected across the diode capacitance is nonlinear because the capacitance of the PN-junction varies with the voltage across it. The dynamic range of an APS imager with source follower amplifiers is usually limited by the source follower.
For these and other reasons, other amplifiers have been proposed for APS imagers. For example, capacitive transimpedance amplifiers (CTIAs) have been used for reading out hybrid infrared focal-plane arrays (IR-FPAs). The basic CTIA circuits for a single ended amplifier and a differential input are illustrated in FIGS. 2 and 3 respectively.
In a single ended CTIA configuration, illustrated in FIG. 2, an input signal Vpd produced by photodetector 150 is provided to the input of CTIA 152. Capacitor 156 provides a feedback path for amplifier 152. Reset switch 154 resets photodetector 150 when closed, and select switch 160 provides an output path to column bus 158 when closed.
In a differential configuration illustrated in FIG. 3, an input signal Vpd produced by photodetector 162 is provided to the “−” input of amplifier 168. A reference voltage REF is provided to the “+” input of amplifier 168. Capacitor 166 provides a feedback path for amplifier 168. Reset switch 164 resets photodetector 162 when closed, and select switch 170 provides an output path to column bus 172 when closed. A CTIA with a differential input is advantageous as opposed to a single ended input because it provides increased noise immunity and can directly control a detector bias voltage maintaining Vpd at the REF level.
Hybrid IR-FPAs include two chips. A detector chip is made of an infrared-sensitive material such as HgCdTe, InGaAs or InSb. A readout chip connected to the detector chip is typically a CMOS circuit containing an array of pixel readout circuits. These readout circuits, however, are designed for infrared detectors, which are characterized by sizeable background signals, considerable dark current, and relatively low resistance.
CTIAs are used with IR-FPAs because they provide a stable bias for a detector during an integration period, as well as a known integration capacitance and reduced noise. However, fixed pattern noise (FPN) is a critical issue in some applications, and an array with a CTIA in each pixel is highly susceptible to FPN due to offsets in the amplifier and output stages.
A critical issue for most image sensors is power consumption. For example, in a 1.3 megapixel sensor with an upper limit of 65 milliwatts for pixel power dissipation, the average power per cell must be below 50 nanowatts. At a bias of 3.3 volts, for example, this implies a maximum average current of 15 nanoamps. At such a low current, a CTIA would have a slow slew rate under reset conditions, making it inappropriate for applications requiring higher readout rates.
It would be advantageous to have improved amplification techniques for image sensors.
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