The present invention is directed, in general, to processing systems and, more specifically, to a data processor implementing a unified memory architecture design that is accessible by external processor(s).
The number of electronic systems which contain microprocessors continues to grow as the prices of microprocessors and memory continue to fall. Microprocessors are implemented not only in traditional desktop personal computers (PCs), but also in a wide variety of consumer electronic devices, including home appliances, and wireless communication devices. Increasingly, many of these systems contain more than one processor. For example, some PC designs contain a main central processing unit (CPU) and a second processor (or xe2x80x9ccoprocessorxe2x80x9d or xe2x80x9cperipheral processorxe2x80x9d) that performs a specific secondary function, such as a digital signal processor (DSP) that handles digital subscriber line (DSL) communications.
The use of more than one processor in a system, however, has numerous drawbacks. Not only does each additional processor increase the overall cost of, for example, a personal computer, but in conventional processing architectures, each additional processor requires its own memory and memory interface to store data and instructions used by that processor. This increases the overall chip count and pin count of the system and further increases the cost of the system.
Therefore, there is a need in the art for improved processing systems that minimize the cost and the complexity of multiprocessor systems. In particular, there is a need in the art for improved processing systems that minimize the amount of memory used in a processing system containing a main processor and at least one additional processor.
The limitations inherent in the prior art described above are overcome by an advantageous embodiment of the present invention, which provides a processing system comprising: 1) a first data processor comprising a unified memory architecture capable of receiving memory access requests from an external bus coupled to the first data processor; 2) a memory coupled to the first data processor and controlled by the unified memory architecture, the memory capable of storing a first plurality of instructions executable by the first data processor; and 3) a second data processor coupled to the external bus and capable of sending the memory access requests to the first data processor, wherein the memory access requests access data used by the second data processor stored in the memory.
According to one embodiment of the present invention, the data used by the second data processor comprises a second plurality of instructions executable by the second data processor.
According to another embodiment of the present invention, the second data processor further comprises an on-chip memory capable of storing a third plurality of instructions executable by the second data processor.
According to still another embodiment of the present invention, the second processor is capable of controlling the external bus.
According to yet another embodiment of the present invention, the external bus is a peripheral component interconnect (PCI) bus.
According to a further embodiment of the present invention, the second data processor is disposed in a peripheral device associated with the first data processor.
According to a still further embodiment of the present invention, the peripheral device is a communication device and the second data processor is a digital signal processor.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
USPTO Backgrounds
USPTO Backgrounds