1. Field of the Invention
The present invention relates to the structure and process for making semi-conductor devices and particularly self-aligned Schottky metal semi-conductor Field Effect Transistors (SASMESFET).
2. Prior Art
In the past, SASMESFET's were accomplished by an etching step that defined source-drain-gate separations as described in the IEEE proceedings Vol. 59, pp. 1244-5, August 1971, or facet-growth where epitaxial growth defined the channel as described in U.S. Pat. No. 3,943,622, March 1976. Both of the above, even with the use of self-aligning as in the former case, use processes that are relatively difficult to control thus structure geometries approaching anything like VLSI cannot be very small without sacrificing yield. Also, the operating frequency is not as high and series resistance is not as relatively low as might be desired. As such, there existed a need for a high-speed SASMESFET structure and process therefore that was process controllable at the desired relatively high operating frequency and low series resistance yet have a reasonable yield in mass quantities.
USPTO Backgrounds
USPTO Backgrounds