The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
Self-aligned double patterning or multiple patterning techniques are used to define conductive lines. However, the existing metal line forming techniques have tight process window and can result in the formation of relatively short dummy conductive lines that lead to increased parasitic capacitance. Accordingly, improvements in these areas are desired.
USPTO Backgrounds
USPTO Backgrounds