The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
The fabrication of semiconductor devices may involve one or more testing processes. A plurality of test units and test pads may be used to carry out the testing. For traditional testing methods, the available number of test units is constrained by the available number of test pads. As semiconductor device continue to shrink, available space on a wafer becomes a valuable resource. As a result, the number of test pads on the wafer may be limited (e.g., less than 30) due to chip area consumption concerns, and that in turn limits the number of test units that can be implemented. As IC technologies continue to advance, the limited number of test units and test pads may not be sufficient to allow effective and efficient execution of the testing processes. Furthermore, electrical noise such as parasitical leakage may also adversely affect test measurement accuracy.
Therefore, while existing testing apparatuses and methodologies are generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.
USPTO Backgrounds
USPTO Backgrounds