A memory device, such as an SRAM device, comprises one or more bit cell arrays. A bit cell array comprises one or more bit cells. A bit cell can store a logical “1” (e.g., a relatively high voltage) or a logical “0” (e.g., a relatively low voltage). The bit cell is governed by an internal voltage level, such as a CVDD internal voltage level, that is supplied to the bit cell. A write operation to the bit cell can be successfully performed by overcoming the internal voltage level associated with the bit cell so that the write operation can store data within the bit cell. Success of the write operation can be enhanced by lowering the internal voltage level associated with the bit cell so that the write operation has less voltage potential to overcome. In addition, a minimum operational voltage of the memory device is improved (e.g., a lower VCCmin can be used to power the memory device) by enhancing the write operation.
USPTO Backgrounds
USPTO Backgrounds