1. Field of the Invention
This invention generally pertains to semiconductor processing, and, more particularly, to the polishing of process layers formed above a semiconducting substrate.
2. Description of the Related Art
The manufacture of semiconductor devices generally involves the formation of various process layers, selective removal or patterning of portions of those layers, and deposition of yet additional process layers above the surface of a semiconducting substrate. The substrate and the deposited layers are collectively called a "wafer." This process continues until a semiconductor device is completely constructed. The process layers may include, by way of example, insulation layers, gate oxide layers, conductive layers, and layers of metal or glass, etc. It is generally desirable in certain steps of the wafer process that the uppermost surface of the process layers be planar, i.e., flat, for the deposition of subsequent layers.
FIGS. 1A and 1B illustrate a general process for providing such a planar uppermost surface. FIG. 1A illustrates a portion of a wafer 10 during the manufacture of a semiconducting device. A layer of insulative material is deposited on the wafer 10 over the substrate 11 and partially etched away to create the insulators 12. A layer of conductive material 14, e.g., a metal, is then deposited over the wafer 10 to cover the insulators 12 and the substrate 11. The layer of conductive material 14 is then "planarized." FIG. 1B illustrates the wafer 10 after the layer of conductive material 14 is planarized to create the interconnects 16 between the insulators 12.
One process used to planarize process layers is known as "chemical-mechanical polishing," or "CMP." In a CMP process, a deposited material, such as the conductive material 14 in FIG. 1A, is polished to planarize the wafer for subsequent procession steps. Both insulative and conductive layers may be polished, depending on the particular step in the manufacture.
In the case of metal CMP, a metal previously deposited on the wafer is polished with a CMP tool to remove a portion of the metal to form insulator interconnects such as lines and plugs, e.g., the interconnects 12 in FIG. 1B. The metal process layer is removed by an abrasive action created by a chemically active slurry and a polishing pad. A typical objective is to remove the metal process layer down to the upper level of the insulative layer, as was the case for the example of FIGS. 1A and 1B.
Such a CMP process is more particularly illustrated in FIGS. 2A and 2B. A wafer 20 is typically mounted upside down on a carrier 22. A force (F) pushes the carrier 22 and the wafer 20 downward. The carrier 22 and the wafer 20 are rotated above a rotating pad 24 on the CMP tool's polishing table 26. A slurry (not shown) is generally introduced between the rotating wafer 20 and the rotating pad 24 during the polishing process. The slurry may contain a chemical that dissolves the uppermost process layer(s) and/or an abrasive material that physically removes portions of the layer(s). The wafer 20 and the pad 24 may be rotated in the same direction or in opposite directions, whichever is desirable for the particular process being implemented. In the example of FIGS. 2A and 2B, the wafer 20 and the pad 24 are rotated in the same direction as indicated by the arrows 28. The carrier 22 may also oscillate across the pad 24 on the polishing table 26, as indicated by the arrow 29.
The point at which the excess conductive material is removed and the embedded interconnects remain is called the "endpoint" of the CMP process. The CMP process should result in a planar surface with little or no detectable scratches or excess material present on the surface. In practice, the wafer, including the deposited, planarized process layers, are polished beyond the endpoint to ensure that all excess conductive material has been removed. Polishing too far beyond the endpoint increases the chances of damaging the wafer surface, uses more of the consumable slurry and pad than may be necessary, and reduces the production rate of the CMP equipment. The window for the polish time endpoint can be small, e.g., on the order of seconds. Also, variations in material thickness may cause the endpoint to change. Thus, accurate in-situ endpoint detection is highly desirable.
Current techniques for endpoint detection may be classed as optical reflection, thermal detection, and friction based techniques. Optical reflection techniques encounter higher levels of signal noise as the number of process layers increase, thereby decreasing the accuracy of endpoint detection outside the range where the endpoint can be detected. Optical reflection techniques may also require that the wafer be moved off the edge of the polishing table. This frequently interrupts the polishing process. This may also cause the endpoint to be missed and its detection delayed by perhaps as much as a few seconds, depending on oscillation speed and distance. Thermal techniques suffer from thermal noise caused by variations in the wafer production rate, variations in the slurry, or changes in the pad. Thermal techniques are also adversely impacted by complexity in the thermal variations as the CMP tool warms and cools over the operation cycle and carrier arm oscillations.
Friction-based techniques detect the endpoint by monitoring the power consumed by the CMP tool's carrier motor(s) and detect the endpoint from the changes therein. The electrical current required to rotate the carrier at a given, specified speed is directly affected by the drag of the wafer on the pad. The coefficient of friction is different for a metal sliding on the pad versus an insulating oxide on the pad, and this difference appears as a change in the carrier motor current, and hence the carrier motor power consumption. The carrier motor current is monitored using Hall effect probes or mechanically clamping sensors. Friction-based techniques detect the endpoint from the change in the current or from the slope of the current profile.
Friction-based techniques also have their drawbacks. The power signals from which the endpoint is detected in a friction-based technique are highly susceptible to noise. Noise may be induced by electromagnetic fields emanating from nearby equipment. Also, where the carrier radially oscillates, the rotation of the carrier(s) and the table introduce noise. This noise must be filtered from the power signal. Even with filtering, however, the power signals may have complex shapes that mask the relatively simple change in the current or power caused when the endpoint is reached. When the carrier current profile is complicated, techniques based on a change in the current or slope of the current profile frequently fail due to variations in the profile from run to run or the large amount of noise inherent in the polishing process.
The present invention is directed to a semiconductor processing method and apparatus that addresses some or all of the aforementioned problems.
USPTO Backgrounds
USPTO Backgrounds