1. Field
Example embodiments relate to a semiconductor integrated circuit and/or method thereof, and for example, to a duty detector that may detect the duty cycle of an input clock signal and/or a duty detection/correction circuit including the duty detector and/or a method thereof.
2. Description of Related Art
A duty cycle of a clock signal represents the ratio of a pulse width to a pulse cycle of the clock signal. In general, devices using a digital clock signal, for example, semiconductor integrated circuits, use a clock signal having a 50% duty cycle. The 50% duty cycle means that the width of a high level period of the clock signal is identical to the width a low level period of the clock signal. A duty detection/correction circuit converts a clock signal with a duty cycle that is not 50% into a clock signal having a 50% duty cycle.
A goal of semiconductor devices is to accurately control the duty cycle of a clock signal in digital clock applications. Accurate control of the duty cycle of a clock signal in digital clock applications is generally more important for synchronous semiconductor devices that input and output data in synchronization with a clock signal because the data may be distorted if the duty cycle of the clock signal is not correctly controlled.
A double data rate (DDR) synchronous semiconductor device has been more recently used in order to improve an operating speed. In a DDR synchronous semiconductor device, data is input/output at falling edges as well as rising edges of a clock signal, and the duty cycle of the clock signal is generally one important feature of the DDR synchronous semiconductor device.
FIG. 1 is a circuit diagram of a conventional duty detection/correction circuit. Referring to FIG. 1, the conventional duty detection/correction circuit includes a duty corrector 11 and a duty detector 13. The duty corrector 11 corrects the duty cycle of an input clock signal IN and a complementary input clock signal INB in response to a duty detection signal DCC and a complementary duty detection signal DCCB output from the duty detector 13. In general, the duty corrector 11 is configured in the form of a differential amplifier and controls a duty cycle according to a DC offset applied to the differential amplifier. The duty detector 13 is configured in the form of a differential charge pump circuit, detects the duty cycle of an output clock signal OUT and a complementary output clock signal OUTB of the duty corrector 11, and outputs the duty detection signal DCC and the complementary duty detection signal DCCB. A capacitor CP is coupled between the outputs of the duty detector 13.
FIG. 2 illustrates the waveform of the duty detection signal DCC and the complementary duty detection signal DCCB illustrated in FIG. 1. The duty detector 13 determines whether the duty cycle of the output clock signal OUT and the complementary output clock signal OUTB of the duty corrector 11 is higher or lower than 50% and outputs the duty detection signal DCC and the complementary duty detection signal DCCB. If the output clock signal OUT and the complementary output clock signal OUTB do not have a 50% duty cycle, a split is generated between the duty detection signal DCC and the complementary duty detection signal DCCB. The splitting operation is stopped if the duty cycle becomes 50%.
FIG. 3 is a circuit diagram of a differential charge pump circuit 13A using a cross-coupled load implemented as the duty detector 13. Referring to FIG. 3, the differential charge pump circuit 13A uses cross-coupled transistors CCT as a load. The cross-coupled load, which is connected between a power supply VDD and output terminals OT1 and OT2, is used to supply a uniform load current to the output terminals OT1 and OT2 through which the duty detection signal DCC and the complementary duty detection signal DCCB are respectively output at any time. A capacitor CP is connected between the output terminals OT1 and OT2. Input transistors IT1 and IT2 receive the output clock signal OUT and the complementary output clock signal OUTB, respectively, and are respectively coupled between the output terminals OT1 and OT2 and a bias transistor BT receiving a bias signal BIAS. The bias transistor BT receiving the BIAS signal may be coupled between each of the input transistors IT1 and IT2 and a ground voltage VSS.
However, a drain-source voltage of the cross-coupled transistor connected to the output terminal OT1 outputting the duty detection signal DCC becomes different from a drain-source voltage of the cross-coupled transistor connected to the output terminal OT2 outputting the complementary duty detection signal DCCB if a split is generated between the duty detection signal DCC and the complementary duty detection signal DCCB because the output impedances of the cross-coupled transistors CCT used as a load are not infinite. Therefore, a load current supplied to the duty detection signal output terminal OT1 becomes different from a load current provided to the complementary duty detection signal output terminal OT2.
Accordingly, a split is not further generated between the duty detection signal DCC and the complementary duty detection signal DCCB after the duty detection signal DCC and the complementary duty detection signal DCCB are split from each other to some degree even if the output clock signal OUT and the complementary output clock signal OUTB do not have a 50% duty cycle. For example, if an input clock signal IN with a 45% duty cycle is input to the duty detection/correction circuit illustrated in FIG. 1, the duty detector 13A must continuously carry out the splitting operation until the duty cycle of the output clock signal OUT becomes 50%. However, the duty detector 13A stops the splitting operation although the output clock signal OUT do not have a 50% duty cycle. Accordingly, the performance of the duty detector 13A is deteriorated, and the duty correction capability of the duty detection/correction circuit illustrated in FIG. 1 is decreased.
FIG. 4 is a circuit diagram of a differential charge pump circuit 13B using a common mode feedback bias as another implementation of the duty detector 13 illustrated in FIG. 1. However, this differential charge pump circuit is difficult to design and has a restricted operating range because it uses the common mode feedback bias.
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