1. Field of the Invention
The present invention relates to a package process and a package structure, and more particularly, to a package process for configuring a relatively large chip onto a relatively small chip and a package structure with a relatively large chip stacked on a relatively small chip.
2. Description of Related Art
In today's information society, users all seek after electronic products with high speed, high quality and multiple functions. In terms of the product exterior appearance, electronic product designs reveal a trend of light weight, thinness and compactness. Therefore, it is develops various chip package techniques such as stacked-type chip package technique.
In the stacked-type chip package technique, several chips are perpendicularly stacked together in the same package structure so that the package density is improved and the dimension of the package is decreased. Furthermore, by using 3-dimensional chip stacking method to decrease the path length of the signal transmission between the chips, rate of the signal transmission is improved and the chips with different functions can be combined in the same package.
In the conventional stacked-type chip package technique, several chips are flip-chip bonded on a wafer, and then the wafer is cut along the gaps between the chips to form several chip stacked structures. Thereafter, the chip stacked structures are configured on a circuit substrate, and a molding compound is formed on the circuit substrate to protect the chip stacked structures.
Since, in the conventional stacked-type chip package technique, the chip stacked structures are formed by cutting the wafer, in the chip stacked structures, the chips formed from cutting the wafer are larger than the chips flip-chip bonded onto the wafer. Hence, the conventional stacked-type chip package technique is used to form the package structure with the small chip stacked onto the large chip.
Furthermore, in the conventional technique, in order to decrease the whole thickness of the stacked-type chip package, the wafer is polished to decrease the thickness of the wafer before the chips are flip-chip bonded on the wafer. However, the process capacitance of the flip-chip bonding technique still has its limit value. When the thickness of the wafer is smaller than the limit value of the process capacitance, fracture often results in the flip-chip bonding technique. Thus, the production yield rate is decreased. Moreover, the fracture of the wafer with a relatively small thickness easily happens during the wafer cutting process. Hence, the production yield rate is decreased.
USPTO Backgrounds
USPTO Backgrounds