In modems implementing loop-back timing (e.g., G.992.x ADSL modems), the remote receiver is synchronized to the network clock timing from the downstream signal and adjusts its transmitter such that the transmitted upstream signal arrives at the central site receiver at the same rate as the network clock. In host processor based modems where signal processing functions (including clock recovery) are done in software running on a host processor, it is desirable to keep the local analog-to-digital (A/D) and digital-to-analog (D/A) sample clock free-running. This is because any adjustment made to the hardware sampling clock is subject to operating system response delay, which is typically large in a host processing environment where the host processor is not dedicated to the modem function. In such systems, since the A/D converter and D/A converter sampling clock is not synchronized to the network clock, it is necessary to re-sample in the digital domain.
When the modulation format is Discrete Multi-Tone (DMT), samples are processed a block at a time where a block of samples forms a DMT symbol. Timing adjustments are typically done via time domain sample stuffing/deletion in conjunction with frequency domain rotation. Although computationally efficient, adjusting the transmit signal timing in such a manner often results in incorrect samples, especially for the samples at the boundary of two DMT symbols, causing a glitch in the far end modem's received signal. For example, consider a small (relative to sampling period) timing adjustment that results in the deletion of a sample from the current symbol. The current symbol will then be shortened by one sample. The shortened symbol will cause a glitch in the far-end modem's received signal. Therefore a need exists for a method and apparatus for timing adjustment in a host-processor-based modem that does not cause glitches in a far-end modem's received signal.
USPTO Backgrounds
USPTO Backgrounds