CMOS (“complementary metal-oxide semiconductor”) compatible wafer-wafer bonding is desirable for wafer-level-packaging. Its use has been demonstrated in a variety of different technologies, however solutions are limited by large bond size and high parasitic capacitance. For example, larger bonds such as microbumps occupy a large amount of space. As a result, the number of connections between wafers may be limited for direct wafer-wafer stacking. Therefore, a need remains for a robust wafer level integration that can allow for simultaneous wafer-level-packaging and high density electrical interconnects which optimize power, performance, and size of stacked solutions.
USPTO Backgrounds
USPTO Backgrounds