In recent years, the digitalization of broadcasting allows mobile terminals to receive the broadcasting. VCO circuits for use in the mobile terminals for receiving are required to receive the broadcasting signals within a wide frequency range and stably operate even in an environment such as in the vehicles having a wide operating temperature range, in addition to having the characteristics of compactness, a low power consumption and so on. In response to these requirements, a Patent Document 1 discloses a phase locked loop circuit (referred to as a PLL (Phase Locked Loop) circuit hereinafter) employing a VCO circuit having a wide oscillation frequency range.
FIG. 11 is a block diagram showing a configuration of a PLL circuit 100 according to the prior art described in the Patent Document 1. In a VCO circuit 200 of the PLL circuit 100 of FIG. 11, a resonance circuit configured by including a varactor diode CV, capacitors C2 and C3, and an inductor L1 connected in parallel with each other, has a predetermined resonance frequency determined by the respective values of the varactor diode CV, the capacitors C2 and C3 and the inductor L1. An oscillator 6 generates an oscillation signal having an oscillation frequency corresponding to the resonance frequency using the resonance circuit, and outputs the same signal. First of all, the resonance frequency of the VCO circuit 200 is coarsely adjusted by applying an output voltage V1 of a constant voltage source 18 to the varactor diode CV via a switch SW3, and controlling switches SW1 and SW2 to select a band, and thereafter, finely adjusted by the PLL circuit 100 by applying a voltage from a low-pass filter (referred to as a LPF hereinafter) 11 to the varactor diode CV via a voltage application terminal Tin and the switch SW3.
FIGS. 12 and 13 are characteristic diagrams showing relations between an application voltage VT (referred to as a varactor application voltage VT hereinafter) to the varactor diode CV and an oscillation frequency fOSC, showing temperature changes from a low temperature to a high temperature, and from a high temperature to a low temperature, respectively, in the PLL circuit 100 of FIG. 11. Generally speaking, the oscillation circuit has a temperature characteristic, and therefore, an initial locking range is set. In this case, the initial locking range is a voltage range at an initial timing when the PLL circuit 100 is locked to the oscillation frequency fOSC fallen within a desired frequency range based on the temperature characteristic. Referring to FIG. 12, fBL1 to fBL5 indicate lower-limit or upper-limit oscillation frequencies in bands B1 to B4. At a low temperature, for example, when the varactor application voltage VT has an upper limit value V2 in the initial locking range, the PLL circuit 100 is locked at a low temperature locking position P11. Subsequently, the characteristic of the oscillation frequency fOSC is lowered as a whole when the temperature increases, whereas the locked state is held by the PLL circuit 100 to a high temperature locking position P12 where the varactor application voltage VT becomes a voltage VH. In addition, referring to FIG. 13, fBH1 to fBH5 indicate lower-limit or upper-limit oscillation frequencies in the bands B1 to B4. At a high temperature, for example, when the varactor application voltage VT has a lower limit value V1 in the initial locking range, the PLL circuit 100 is locked at a high temperature locking position P13. Subsequently, the characteristic of the oscillation frequency fOSC is raised as a whole when the temperature decreases, whereas the locked state is held by the PLL circuit 100 to a low temperature locking position P14 where the varactor application voltage VT becomes a voltage VL.    Patent Document 1: Japanese patent No. 3488180.
USPTO Backgrounds
USPTO Backgrounds