The present invention relates to a flash memory device and an erase method thereof and, more particularly, to a flash memory device in which threshold voltage distributions of erased memory cells can be narrowed and an erase method thereof.
FIG. 1 is a circuit diagram illustrating an erase method of a conventional flash memory. The flash memory device includes a memory cell array 10, a block switch 20 and a X-decoder 30. The memory cell array 10 includes a plurality of memory cell blocks 11 (only one memory cell block is illustrated for convenience sake). Each of the memory cell blocks 11 includes a plurality of cell strings S0 to Sn. Each of the cell strings S0 to Sn includes a drain select transistor DST, a plurality of memory cells F0 to Fi and a source select transistor SST all of which are connected in series. The drain select transistors DST included in the respective cell strings S0 to Sn are connected to corresponding bit lines BL0 to BLn, and the source select transistors SST included in the respective cell strings S0 to Sn are connected in parallel to a common source line CSL.
The X-decoder 30 outputs a block select signal BSLk to select one of the plurality of memory cell blocks according to an address signal ADD.
The block switch 20 includes a plurality of NMOS transistors M0 to Mi+2. The plurality of NMOS transistors M0 to Mi+2 operate according to the block select signal BSLk of the X-decoder 30, and transfer voltages, applied through global word lines GWL and global select lines GDSL and GSSL, to the drain select line DSL, the word lines WL0 to WLi and the source select line SSL of a selected memory cell block 11.
An erase method of the conventional flash memory is described in detail below. An erase operation is carried out per memory cell block. One memory cell block 11 of the plurality of memory cell blocks is selected according to the address signal ADD applied to the X-decoder 30. 0V is applied to the word lines WL0 to WLi of the selected memory cell block 11, and a high voltage of about 20V is applied to a well of the memory cell block 11 for about 1.4 ms. Thus, the voltages of the drain select line DSL and the source select line SSL are boosted to about 20V due to capacitance coupling with the well. Further, threshold voltage distributions for the memory cells within the memory cell block 11 are moved from positive distributions to negative distributions by means of a high voltage difference between the word lines WL0 to WLi and the well.
An erase verify operation is performed once per memory cell block. To this end, an erase pulse should be long enough to sufficiently erase all cells F0 to Fi within the memory cell block 11. However, the memory cells erase at different speeds within the memory cell block 11, and threshold voltages after erase can vary widely. Further, an erase operation time can become long, and an interference influence occurring due to capacitance coupling between cells. In particular, it serves as an obstacle to degrade reliability of the operation in devices requiring narrow threshold voltage distributions as in multi-level cells.
USPTO Backgrounds
USPTO Backgrounds