Conventionally, in a semiconductor device, there has been used a method for depositing and planarizing an interlayer insulating film after a wiring has been formed. As an idea different from this, there is a dual damascene structure in which a wiring trench and a via hole are formed simultaneously. In this structure, since the via hole can be formed of a same material as that of the wiring trench, an interface resistance of a contact hole can be reduced, and an electro-migration tolerance can be enhanced. Especially, in the dual damascene structure, hitherto demands for enhancing a film coatability to prevent a void from being formed between wirings become unnecessary, because the interlayer insulating film is always deposited on a planar surface.
A fabrication process of this dual damascene structure includes a process for cleaning the surface of the conductive layer exposed through the bottom portion of the via hole. In many cases, etching residue of organic materials such as photoresist or the like lies on the surface of the conductive layer beneath the bottom portion of the via hole. Further, a native oxide film is inevitably formed on the surface of the conductive layer. For example, in case the conductive layer is copper, copper oxide (CuO) is formed on the surface of the copper. Such residual organic material or oxide causes a problem in that it causes an electric resistance of a vie hole portion to increase.
It is known that the increase in the electric resistance of the via hole portion can be prevented by plasma processing a surface of a low-k film to form a detailed surface modification layer (see, for example, Japanese Patent Laid-Open application No. 2002-26121, Paragraph [0031] and FIG. 6).
Further, as a conventional method other than that disclosed in the above-mentioned document, there is a method for cleaning the surface of the conductive layer exposed through the bottom portion of the via hole. In this method, although the residual organic material is decomposed to be removed by injecting argon ions, since injecting the argon ions does not involve an ashing, residual organic material cannot be removed completely. Hence, the surface cannot be cleaned sufficiently. Further, native oxide cannot be removed. In addition, a damage is inflicted on an insulating film on a side wall of the via hole when the argon ions are injected, thus causing an adverse effect on the dielectric constant (k value).
USPTO Backgrounds
USPTO Backgrounds