An active matrix type liquid crystal display (LCD) device has thin film transistors (TFTs) to control pixels to read data signals. Where amorphous silicon TFTs are used in LCD devices, tape carrier packages (TCPs) are connected to the LCD devices to drive the pixels. The TCP includes integrated circuits provided on flexible printed circuit boards to drive signal lines and scanning lines. Where this TCP is connected to terminals of a TFT array substrate, the integrated circuits to drive the signal and scanning lines are connected to the pixels corresponding to the TFTs provided on the TFT array substrate, respectively.
FIG. 6 is a circuit diagram of a prior art amorphous silicon TFT LCD. FIG. 7 is its block diagram to show schematically the relationship between divided display regions and signal line control circuits.
A TFT LCD basically consists of a TFT array substrate, a counter substrate provided opposite to the TFT array substrate and a liquid crystal layer held between the TFT array and counter substrates. With reference to FIG. 6 the TFT array substrate 100 includes a display area 101 in which scanning lines G1, G2, G3, . . . , Gm (collectively called “G”) and signal lines S1, S2, S3, . . . , Sn (collectively called “S”) are disposed in a matrix form and a pixel TFT 102 and a pixel electrode 103 are provided in the vicinity of intersection of the matrix. The counter substrate includes a counter electrode 104 facing the pixel electrode 103. The liquid crystal layer 105 is provided between the pixel and counter electrodes 103 and 104. Further, the pixel electrode 103 is connected in parallel to an auxiliary capacitor 106 to which an operating voltage is supplied through an auxiliary capacitor line.
The display area 101 is coupled to signal line control circuits 111, and integrated circuits 115 for driving scanning lines. The display area 101 is divided into 4 blocks LL, LR, RL and RR as shown in FIG. 7. A predetermined number of the signal lines S are assigned to each block to which data signals are supplied from the signal line control circuit 111. For the sake of simplicity FIG. 7 schematically shows signal line driving integrated circuits and analog switch control signal lines 107 and 108.
As shown in FIG. 6, the signal line control circuit 111 has the signal line driving circuit 112 and a signal line switching circuit 113. The signal line driving circuit 112 serially supplies data signals to a group of signal lines S allocated to each block. The signal line switching circuit 113 sends a data signal to each signal line in the group of signal lines during one horizontal scanning period. The signal line driving circuits 112 are provided in TCPs 120-1, 120-2, 120-3 and 120-4. The signal line switching circuits 113 are, however, formed on the TFT array substrate 100. The TCPs 120-1, 120-2, 120-3 and 120-4 each are connected between the terminals of the TFT array substrate 100 and an outer printed circuit board 200.
The integrated circuits 115 for driving the scanning lines sequentially output scanning signals to turn on the pixel TFTs 102, so that the data signals are read in the pixels from the signal lines S
The integrated circuits 115 are provided in TCPs 130-1 and 130-2, which are, in turn, connected between the terminals of the TFT array substrate 100 and an outer printed circuit board 300.
The outer printed circuit board 200 includes a control integrated circuit 201, interface circuits, a power source, etc. The control integrated circuit 201 outputs control signals at various timings and data signals in synchronization with such control signals in response to clock, timing and digital data signals, etc. supplied from outside application devices. The control and data signals and a power source voltage from the control integrated circuit 201 are not shown but also provided to the integrated circuits 115.
The TFT array substrate 100 is provided opposite to the counter substrate, not shown, with a predetermined gap, the TFT array and counter substrate are tightly put together, their peripheral portions are sealed by sealant, and a liquid crystal material is injected into the gap to complete an LCD device.
FIG. 8 is a circuit diagram of the signal switching circuit 113 for the block LL, LR, RL or RR. Two adjacent signal lines S1 and S2 are commonly connected to a signal line D1 through analog switches ASW1 and ASW2. Similarly, two adjacent signal lines Si-1 and Si are commonly connected to a signal line Dj, (collectively called “D”, “j”=1, 2, . . . , and i/2, and “i”=the number of signal lines assigned to each block LL.LR.RL or RR), through analog switches ASWi-1 and ASWi, (collectively called “ASW”, “i”=1, 2, . . . , and n/4, and “n”=the number of total signal lines). The analog switches ASW are controlled by signal line control signals ASW1U and ASW2U provided from the control integrated circuit 201 through the signal line driving circuits 112. When the analog switch ASWi turns on, a DATA SIGNAL j supplied to signal line Dj is transferred to the pixel PIX i through the signal line Si. Control electrodes of the analog switches ASW1, ASW3, . . . , and ASWi-1 are connected to an analog switch control signal line 107 but those of the analog switches ASW2, ASW4, . . . , and ASWi are connected to another analog switch control signal line 108. The analog switches ASW are controlled in response to the control signal ASW1U or ASW2U.
FIG. 9 is a timing chart of a driving scheme of the signal line switching circuit 113 for the block LL, LR, RL or RR. During the former half of a horizontal scanning period the control signal ASW1U becomes a level to turn on the analog switches ASW2, ASW4, . . . , and ASWi and data signal DATA2, DATA4, . . . , and DATAj (collectively called “DATA A”) are read in the pixels PIX2, PIX4, . . . , and PIXi, respectively. During the latter half of the horizontal scanning period, however, the control signal ASW2U becomes such a level to turn on the analog switches ASW1, ASW3, . . . , and ASWi-1 and data signal DATA1, DATA3, . . . , and DATAj-1 (collectively called “DATA B”) are read in the pixels PIX1, PX3, . . . , and PIXi-1, respectively. Here, for convenience PIX1, PIX2, PIX3, PIXi are collectively called “PIX”. Further, this driving scheme is called a signal line selection system. It can reduce the number of signal lines S connected between the outer application device and the TFT array substrate 100. Further, the number of signal control lines is not only limited to two but also can be three or more.
The control signals ASW1U and ASW2U are supplied to the analog switches ASW from the control integrated circuit 201 in the outer printed circuit board 200 through connecting lines including the analog switch control signal lines 107 and 108. Since the analog switch control signal lines 107 and 108 formed on the TFT array substrate 100 are made of metal, such as MoTa, Cr, MoW, Alzr, Al, or the like and have narrow, complicated layout requirements, the lines have much higher electrical resistance than those connected to the control integrated circuits 201 and signal line driving circuits 112. Thus, electrical path lengths of points A and B shown in FIG. 7 from the signal line driving circuits 112 are different from each other. As a result, signal delays at the points A and B cause the pixels to read distorted data. In other words, the analog switches ASW for adjacent pixels are distinctively different in conductive state in the boundary region between the blocks LL and LR, for example, so that such different conductive states lead to lack of uniform display.
USPTO Backgrounds
USPTO Backgrounds