This invention relates primarily to an electronic timing device and more specifically to a highly accurate time of event recorder for precisely measuring the elapsed time between two or more successively occurring events.
In many scientific experiments, it is desirable to measure with a high degree of accuracy the time of occurrence of an event with respect to a first point in time or the difference between two successively occurring events, which events may be taking place practically simultaneously, i.e., with an extremely short elapsed time therebetween. For example, in testing and debugging complex electronic equipment such as a digital computer, it is often desirable to know precisely the elapsed time between two successive pulses appearing in the system so that proper synchronization of separate logic arrays used in the system can be obtained. Also, it is often necessary to record the time of occurrence of several events and provide a means of determining the elapsed time between a first event and any one of a number of later events occuring within a predetermined time span.
Known prior art arrangements commonly use a stop-watch approach wherein a first event turns on a source of regularly occurring timing pulses which are accumulated in a counter and a second event is used to turn off the timing pulse source so that the elapsed time is represented by the contents of the counter. Where several events are to be compared, this approach becomes unsatisfactory from a cost standpoint in that several synchronized clock sources and counter banks are required.
The present invention provides an extremely efficient and highly accurate means for recording for a predetermined duration, the time of occurrence of a plurality of events along with means for reading out a numerical quantity indicative of the time elapsed between the occurrence of any two of said plural events. More specifically, the preferred embodiment to be described allows the time of occurrence of 32 separate events to be recorded, provided they occur within a predetermined time span. The device is constructed such that elapsed time intervals as short as 1 nanosecond (10.sup.-.sup.9 seconds) can be reliably determined.
In accordance with the teachings of the preferred embodiment, there is provided a first array of MATED FILM storage elements which may have 16 digit lines and 32 word lines. Coupled individually to the 16 digit lines is one stage of a 16 stage Gray Code counter, which is connected to receive as its input, pulses from a temperature compensated crystal controlled oscillator. The count in the Gray Code counter may be advanced every 10 nanoseconds, for example.
Also included is a second array of MATED FILM elements having 10 digit lines and 32 word lines, said word lines being a continuation of the word lines in the first array. While for ease of understanding, the storage arrays may be considered as being divided into two parts, in practice the two arrays may be integrally formed in a single manufacturing process. The output from the crystal clock is coupled directly to a first digit line in the second array and each succeeding digit line is coupled through a 1 nanosecond delay element to the preceding digit line. Hence, between each advance of the Gray Code counter, the digit lines in the second array are energized in sequence and at 1 nanosecond intervals to, in effect, break the basic clock period into ten equal parts or time intervals.
Upon detection of an event to be recorded, the word line associated with that event is energized, causing the storage elements located at the intersections of that word line with the digit or bit lines in the first and second arrays to record the contents of the Gray Code counter and a value equal to the number of one nanosecond periods which elapsed since the counter was last toggled. Later events caused other word lines in the two arrays to be energized for storing the then contents of the Gray Code counter and the submultiple of the clock pulse period.
To read out the information, a desired word line is addressed and a read current is applied thereto, causing signals to be induced on the digit lines in parallel, indicative of the information stored in the storage elements linked by said addressed word line. The data in the first array is inserted in a first output register. It then may be converted to a decimal representation, multiplied by 10 nanoseconds and the direct decimal representation of the submultiple count from the second array then may be added to the product to provide the time figure. The process then may be repeated for a second event and the result may be subtracted from the first time figure to indicate the elapsed time between the two events.
USPTO Backgrounds
USPTO Backgrounds