FIG. 1 illustrates a simplified block diagram of the basic elements of a prior art multi-port memory similar to the memory described in U.S. Pat. No. 4,891,794 issued to Hush et al. entitled "Three Port Random Access Memory" which is incorporated herein by reference. Multi-port random access memories (RAM) are substantially faster than standard RAM and commonly referred to as video random access memories (VRAM) because of their effectiveness in video systems.
In its simplest form, the multi-port memory includes a dynamic random access memory (DRAM) 100 having input/output lines 101, a DRAM controller 102, two serial access memories (SAM) 104 and 106 and a SAM controller 108. Each SAM is essentially a long shift register which can receive a block of data from the DRAM and serially shift the data out through data port 107 or 109. Each SAM can also serially shift data in through the serial ports and transfer the data to the DRAM. Other multi-port memories may include a different number of serial access memories. For example, a dual port memory incorporates one input SAM and a DRAM.
The DRAM is a dynamic array for storing multiple bit registers in multiple two dimensional planes each having rows and columns. Each bit register is defined by the same row and column addresses in each of the planes. Each SAM has a bit register row associated with one of each of the planes of the DRAM such that the columns of the DRAM correspond to the bits of the register row.
In general, the DRAM and SAM's can operate either independently or in limited combinations for internal transfers of data. When operating in combination, the SAM's are structured to allow each SAM to access one row of the DRAM. Assuming, in a DRAM having 512 column addresses in each row, SAM 104 can read or write to addresses 0-511 of one row of the DRAM and SAM 106 can read or write to addresses 0-511 of one row of the DRAM. This configuration allows for both bi-directional internal transfer of data between the DRAM and the SAM's and independent access to each of the three memories.
Transferring data from a SAM to the DRAM requires the addressing of a given row of the DRAM in which the data is to be transferred. Addressing a row, as known to one skilled in the art, requires pre-charging the row. Once data has been transferred to cells in a row, prior art teaches that the row must be inhibited or closed, see U.S. Pat. No. 4,689,741 to Redwine et al., entitled "Video System having Dual-port Memory with Inhibited Random Access During Transfer Cycles", and U.S. Pat. No. 4,667,313 to Pinkham et al., entitled "Serially Accessed Semiconductor Memory with Tapped Shift Register." If the newly transferred data is to be randomly accessed, the row must therefore be pre-charged and re-addressed. The re-addressing of newly transferred data is time consuming and prevents real time editing of that data.
Further, the row access signal used to access a given row of the DRAM is used to trigger functions other than data transfers. These functions include functions not directly related to a row of memory, for example loading either a mask or color register. To perform these functions, however, a DRAM row must be accessed. The row is then closed upon completion of the function. To speed the operation of the memory, it would be advantageous to access a row of the DRAM, perform a function (related or not related to the accessed row), and then perform a function related to the row without being required to close the row.
To transfer data from a DRAM to a SAM requires the addressing of a given row of the DRAM in which the data is to be transferred. Again, addressing a row requires that the row be pre-charged. If the DRAM data needs to be manipulated in some manner prior to transferring the data to the SAM, a separate write operation is required. For example, if parity data needs to be generated for data stored in a row of the DRAM, the data must first be read from the memory. Parity data is then generated by external circuitry and the parity data can then be stored in a separate location in the same memory row. These read and write operations can be performed using page mode operations. That is, the row of memory remains addressed while the column address is changed to allow random access for these different operations. When the parity data has been stored in the DRAM, the memory row is closed. The memory row must be pre-charged and addressed again to transfer this newly manipulated data from the DRAM memory row to a SAM register.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory circuit which can perform multiple functions while a row of the memory is accessed. There is also a need for a multi-port memory which can transfer data from a DRAM to a SAM immediately following real-time random access to the data.
USPTO Backgrounds
USPTO Backgrounds