The present invention relates to a technique for reading data from a memory, suitable for applying the technique to a data readout circuit of, for example, a dynamic memory.
In a data readout operation of a general dynamic memory, a memory readout circuit supplies address signals twice in response to two address strobe signals including a row address strobe signal and a column address strobe signal. Specifically, a row address is supplied via an address bus to the memory synchronously with a fall of the row address strobe signal. Next, a column address is supplied synchronously with a fall of the column address strobe. The row address selects memory cells of one row in the word line direction. When the column address is supplied and a corresponding memory cell is selected, data starts being outputted to a data bus. When the column address strobe signal rises, the data output is stopped. The memory is so designed that the data output terminal takes a high impedance state until the next data is outputted after the data output is stopped.
Because of this design, the memory readout circuit is required to fetch data outputted from the memory during the time period from the time a data output is ensured after the column address strobe signal falls to a time when the column address strobe signal rises. In other words, designers have not intended to generate a timing signal for the memory readout circuit to fetch data during the data non-asserted period after a column address strobe signal rises. Namely, in a conventional memory system, data is valid during the period while a column address strobe signal is active, and it is difficult to generate a timing signal for reliably receiving data (refer to FIG. 2 of JP-A-56-41575). If a rise of a column address strobe signal is delayed in order to have a longer data valid time and in order for the data readout circuit to reliably fetch data, a cycle time of the whole system is prolonged so that a high speed operation of a data processor which accesses a dynamic memory has been restricted.
In a conventional system using a dynamic memory, a pullup or pulldown resistor is connected to a data bus interconnecting the dynamic memory and a memory readout circuit in order to prevent the data bus from taking an uncertain level value in the high impedance state. In FIG. 3 of JP-A-56-41575, an example of using a pulldown resistor is shown.
Under the present conditions of increased information amount and advanced semiconductor technology, there is a very high need for reading data from, and writing data to, a large capacity semiconductor memory at high speed. There is a problem associated with shortening a read cycle time of a general dynamic memory. A readout data asserted period is a period from after a lapse of an access delay time after a column address strobe signal falls to a time when the column address strobe signal rises. The problem resides in that in order for the memory readout circuit to reliably fetch data during this period, it becomes necessary to delay a rise timing of a column address strobe signal to some degree. The memory data readout cycle time is a sum of the access delay time, data fetch asserted time, and column address precharge time.
USPTO Backgrounds
USPTO Backgrounds