After a semiconductor chip has been manufactured, it undergoes a testing sequence to determine if the chip is functioning correctly. The testing can be performed using an automatic test pattern generation (ATPG) technique in which an ATPG pattern is generated specifically to test the functionality of this particular type of chip. However, this technique has the disadvantage that the ATPG patterns are large and the time required to test the chip is quite long. This problem is exacerbated in Multi-Chip Modules (MCM) and System-In-Package (SIP) components which include two or more chips to be tested. The long testing times required ultimately increase the cost of producing the chip or module.
Large test patterns also require a larger tester memory to store the patterns. Therefore, the tester resources required is increased and also increases complexity and the total cost of testing and manufacturing the chip or module.
USPTO Backgrounds
USPTO Backgrounds