The present invention relates to a digital interface apparatus, and more particularly, to a digital interface apparatus for transmitting and receiving non-compressed digital data.
Due to remarkable developments in the field of information communication, the data interface between image apparatuses has become the subject of brisk study. According to the specification of a standard definition (SD) digital video cassette recorder (VCR), a digital VCR should transmit compressed image data, audio data and subcode data via an IEEE 1394 serial bus. A data interface between digital image apparatuses 1 and 2 such as a digital VCR and a digital camcorder will be described with reference to FIG. 1. As shown in FIG. 1, the digital image apparatuses 1 and 2 have the same structure. Data transmission operation proceeds as follows when the first digital image apparatus 1 is used as an image input apparatus for the second digital image apparatus 2. In the first digital image apparatus 1, an image signal picked up by a camera 11 or an image signal input via an input end 19 is input to a source data processor 12. The source data processor 12 compresses the input image signal via a compression procedure according to the SD specification. The data compressed by the source data processor 12 is applied to a digital interface circuit 17 in order to be transmitted to the second digital image apparatus 2.
FIG. 2 is a circuit diagram of a conventional digital interface circuit. Digital interface apparatuses 17 and 27 which are contained in the digital image apparatuses 1 and 2, respectively, have the same structure. Hereinafter, the digital interface circuit 17 in the digital image apparatus 1 will be described below as an example.
In FIG. 2, an input/output controller 101 receives the data applied from the source data processor 12 as data to be transmitted. A transmission timing controller 102 receives an external frame signal in synchronization with the data to be transmitted. The transmission timing controller 102 uses the received frame signal to generate a write timing signal. The write timing signal is used as a control signal for writing data in a transmission first-in-first-out (FIFO) memory 103. When a write timing signal is applied from the transmission timing controller 102, data transmitted from the input/output controller 101 is subsequently stored in the transmission FIFO memory 103 in synchronization with an externally-supplied transmission system clock T.sub.-- SYS CLK. The transmission data stored in the transmission FIFO memory 103 is output to a controller 104 at the time when the controller 104 desires. For doing so, the transmission timing controller 102 generates a read timing signal using the frame signal. The controller 104 generates clock CLK and supplies the generated clock to the transmission FIFO memory 103. When a read timing signal is applied from the transmission timing controller 102, the transmission data stored in the transmission FIFO memory 103 is read out in synchronization with the clock CLK supplied from the controller 104. The transmission timing controller 102 supplies the received frame signal to the controller 104. The controller 104 adds a cyclic redundancy code and a header to the transmission data read from the transmission FIFO memory 103. Information on the frame signal supplied from the transmission timing controller 102 and a transmission channel number is loaded on the header in order to restore the frame signal at a receiving end. The controller 104 outputs the transmission data on which the additional information is loaded, to a data transmission/reception portion 105. The data transmission/reception portion 105 converts the transmission data output from the controller 104 into an electrical signal to be output via a transmission channel. Also, the data transmission/reception portion 105 transmits the electrical signal to the second digital image apparatus 2 via a transmission channel in an IEEE 1394 serial bus.
An operation for transmitting the signal reproduced from a recording medium 14 in the first digital image apparatus 1 in order to be displayed on a monitor 26 in the second digital image apparatus 2 is as follows. The data read from the recording medium 14 is input to a channel data processor 13 and amplified by a predetermined amplification factor. The channel data processor 13 detects information data from the amplified data and corrects an error of the information data using an error correction code added during recording. The error-corrected data in the channel data processor 13 is applied to the digital interface circuit 17 and is transmitted to the second digital image apparatus 2 in the same manner as described above.
When data is transmitted from a digital interface circuit 27 in the second digital image apparatus 2, the digital interface circuit 17 receives the data transmitted via a reverse procedure of the above-described data transmission operation. In this case, when the received data is stored in a reception FIFO memory 107, the clock CLK supplied from the controller 104 is used, while when the received data is read from the reception FIFO memory 107, a reception system clock R.sub.-- SYS CLK is used. The reception system clock R.sub.-- SYS CLK is produced by a phase locked loop (PLL) 18 for receiving a frame signal. In the case where the data received by the digital interface circuit 17 is a signal output from a camera 21 or an input end 29 in the second digital image apparatus 2, the received data is applied to the channel data processor 13. The channel data processor 13 adds an error correction code to the received data and performs a 24/25 modulation. The modulated signal is recorded in recording medium 14. On the other hand, in the case where the received data is a signal read from a recording medium 24 in the second digital image apparatus 2, the received date is applied to a source data processor 12. The source data processor 12 expands (or decompresses) the received data. The expanded data is digital-to-analog-converted in a digital-to-analog (D/A) converter 15. The analog-converted signal is displayed on a monitor 16.
Such digital interface apparatuses are directed to the data interface between digital VCRs. However, the advent of multimedia permits a digital VCR to be linked with a computer. In this case, when a digital VCR is connected to a computer, data which is transmitted after being compressed cannot be used in the computer. Thus, in order to allow the computer to use the compressed data, a circuit for expanding the compressed data is added in the computer or the compressed data should be expanded by software. The former case requires an additional cost to be incurred, and the latter case causes the data not to be processed on a real-time basis.
USPTO Backgrounds
USPTO Backgrounds