1. Field of the Invention
The present invention relates to a system enhancing the performance of a circuit by reducing the channel length of one or more transistors in the circuit.
2. Description of the Related Art
There has been a constant effort to increase the speed of integrated circuits by increasing the switching speed of the transistors in the integrated circuits. One means for increasing the speed of a transistor is to shorten the channel length of the transistor. FIG. 1 illustrates the cross section of a CMOS transistor 10 having a source 12, drain 14 and gate 16. In one configuration, the substrate includes a highly doped p region 18 and a lightly doped p region 20. Between gate 16 and lightly doped P region 20 is a gate dielectric or oxide 22. The area below gate 16 and between source 12 and drain 14 is called the channel.
MOS transistors with small channel lengths are prone to hot carrier injection (HCI). HCI occurs as a result of a large electric field developed in substrate 20 near the drain 14 when the transistor is operated in a saturated condition. The large electric field at the edge of drain 14 provides sufficient potential to force carriers into gate dielectric 22. The injected carriers increase the amount of trapped charge in gate dielectric 22 and change the charge distribution causing a shift in the threshold voltage. Over a period of time the amount of trapped charge in gate dielectric 22 increases as the transistors are repeatedly brought to a condition of saturation. Eventually, the threshold is shifted to a point where the circuit slows down.
One solution to the problem of hot carrier injection is to form a lightly doped drain (LDD) structure. The LDD structure consists of-a-lightly doped drain region 26a adjacent to the gate with a heavily doped drain region 26b laterally displaced from the gate electrode. The LDD structure also includes a lightly doped source region 28a adjacent to the gate with a heavily doped source region 26b laterally displaced from the gate. The lightly doped region is diffused under the gate dielectric and produces a small electric field near the edge of the drain, thus reducing carrier injection into the dielectric. The heavily doped source/drain regions provide a low resistance region where an ohmic contact can be made.
In some cases, it is desirable to augment the protection against device degradation that the LDD structure provides. For example, to increase the speed of the circuit it may be desired to utilize a transistor having a channel length smaller than otherwise acceptable even with the LDD structure. In such a case, LDD does not provide proper protection from HCI.
In other cases, it is desirable to avoid the increased processing complexity that the LDD structure requires, while still providing for device protection against excessive operating fields and HCI.
Therefore, a system is needed to reduce the channel length of at least some of the transistors in a circuit in order to increase the speed of the circuit without suffering from the effects of HCI.
USPTO Backgrounds
USPTO Backgrounds