This invention relates to full wave envelope detectors, and more particularly to a low power consumption envelope detector suitable for detection of low level signals over a broad range of frequencies.
A simple and common method of detecting the envelope of an input signal is with a diode detector. It has been found that the conventional diode envelope detector is inappropriate for use in detecting low level signals because it is necessary for the input signal to overcome a threshold voltage to forward bias the diode. Moreover, at low signal levels, the current/voltage transfer characteristic of a diode is highly non-linear. A known solution to the problem of non-linearity is to substantially amplify the low level input signal so that the diode operates on the more linear portion of its transfer curve. It will be appreciated that this solution is costly in terms of power consumption.
Another known method of detecting the envelope of an input signal involves using an operational amplifier instead of a diode. This method permits the detection of relatively low level signals; however, at higher frequencies this method requires high speed op-amps capable of following the waveforms. High speed op-amps consume a considerable amount of power rendering this method inappropriate for low power consumption applications.
Accordingly, there remains a need for an envelope detector capable of detecting low level signals in the millivolt range and consuming a minimal amount of power. Such a device is especially desirable for industrial applications in which 4-20 milliampere communication wiring is commonplace and the costs of additional wiring over the dispersed area of an industrial plant can be prohibitive.
The present invention provides a low power consumption envelope detector for low level signals which addresses the shortcomings associated with known envelope detectors.
The present invention comprises an input port for receiving the input signal; a first inverter for inverting the input signal and generating an inverted input signal; an offset stage for offsetting the input signal and the inverted input signal such that peaks in the signals are aligned at zero volts and generating an offset input signal and an offset inverted input signal; and a summer circuit for summing the offset input signal and the offset inverted input signal to generate, at an output port, a resultant signal corresponding to the envelope of the input signal.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
USPTO Backgrounds
USPTO Backgrounds