1. Field of the Invention
The invention relates to a design evaluation system and a design evaluation method for a system LSI, and more particularly to the apparatus and the method for assisting in design of the system LSI such as the system on chip using the electric design automation (EDA).
2. Description of the Related Art
To manufacture a semiconductor integrated circuit having a few tens of thousands of gates, design departments have provided register transfer level (RTL) data to manufacturing departments. By providing the RTL data, it has been possible to manufacture the semiconductor integrated circuit, which works expectedly, until the scheduled date of delivery. In the case where a semiconductor integrated circuit including a few hundreds of thousands of gates is designed, a physical synthesis system of an EDA tool is generally utilized to use an abstract design description language as described in Japanese Patent Laid-Open Publication No. Hei11-3367. In the SoC (system on chips), software and hardware are closely related to each other. Therefore, the degree of difficulty in designing system is increased. To solve the difficulty, a method using object-oriented analysis and design has been proposed. The method is applied to improve the efficiency of a process for designing software and hardware based on requirements definitions of the SoC.
However, a finer design rule of a semiconductor integrated circuit often makes it difficult to improve a yield rate of the system LSI, because of involving an additional aligner, mechanical stress on a wafer, contaminations of materials, and the complexity of the overall manufacturing process. In addition, designers are skeptical about whether state-of-the-art technique complies with the cost of production of chips. Therefore, a system and method for designing a system LSI are considerably affected by the success or failure of mass production of chips and the cost of mass production of the chips.
Moreover, proposed methods have not evaluated about utilization of patterns of a component such as a macro cell, since the proposed methods have not defined reliability planning and management or quality metrics which permit judging the quality of logic design of a system LSI.
Furthermore, designing the system LSI often involves redesign. The reason is as follows. Addition of module parallelism, design constraints, and channel definition information, which take place as a design process proceeds, result in generation of a system LSI that does not meet initial LSI specifications. Therefore, it has been required to resume an initial process even after downstream process has been accomplished.
USPTO Backgrounds
USPTO Backgrounds