Successive approximation is one of the basic principles for analog-to-digital conversion. The general functionality and operation of successive approximation register (SAR) analog-to-digital converters (ADCs) is well known in the art. SAR ADCs compare the analog input voltage to reference voltage levels, which can be generated by a digital-to-analog converter (DAC). During a first clock cycle, the sampled input voltage may be compared to half the reference voltage output by the DAC. If the result of the comparison indicates that the input voltage is greater than half the reference voltage, then a respective bit decision relating to the most significant bit (MSB) is made. During the next clock cycle, the input voltage is compared to three quarters or one quarter of the reference voltage in accordance with the preceding MSB decision, and a further bit decision is made relating to the next less significant bit (MSB-1). The conversion procedure carries on accordingly, and the DAC output voltage converges successively to the analog input voltage, while evaluating one bit during each clock cycle. The SAR ADC is arranged such that, when the conversion is completed, the digital number input to the DAC represents the digitized input voltage.
Since precise DAC voltages are used, capacitive DACs (CDACs) are often used, which include a plurality of capacitors. Such a known analog-to-digital converter stage having a CDAC is shown in FIG. 1. The CDAC has a positive side with sampling capacitors C1p-CNp and a negative side with capacitors C1n-CNn. The capacitors C1p and C1n are adapted to evaluate the most significant bit (MSB) and the capacitors CNp and CNn are adapted to evaluate the least significant bit (LSB). The common nodes VCPOS and VCNEG of each of the capacitors C1p-CNp and C1n-CNn can be coupled to a common mode voltage VCM by sample and hold switches SWHp, SWHn. The other side of each of the capacitors C1p-CNp and C1n-CNn can be coupled to a positive reference voltage +REF, a negative reference voltage −REF or a symmetric input voltage INp, INn.
The analog input voltage can be sampled directly on the capacitors C1p-CNp and C1n-CNn by closing (switches are conducting) the switches SWHn, SWHp and coupling INp and INn to the other side of some or all capacitors, such that a charge corresponding to the size of the capacitors and proportional to the amplitude of the input voltage is present on the sampling capacitors. The sampled charge is redistributed stepwise among the capacitors of the CDAC. The magnitude of the input voltage is basically determined by selectively and consecutively switching the other sides of the capacitors between the different reference voltage levels +REF and −REF and comparing the established voltage level on the common nodes VCPOS, VCNEG. The switching of the other side of each of the plurality of capacitors is performed through numerous switches S1n-SNn, S1p-SNp, which are controlled by control signals CDACCNTL provided by control stage SAR-CNTL in response to the comparator output COMPOUT at each step of the conversion process. The capacitors having the largest capacitance C1p, C1n can be the first to be connected to a specific reference voltage level, while the remaining capacitors C2p-CNp, C2n-CNn are connected to another reference voltage level. Then the voltage on the common nodes VCPOS, VCNEG, which are connected to respective positive and negative inputs of a comparator CMP, is compared, and the output ADCOUT of the comparator CMP represents the bit values of the digital output word DOUT bit by bit, starting with the most significant bit (MSB). In accordance with the signal at the output ADCOUT of the comparator CMP (i.e. the comparison result), the capacitors C1p-CNp and C1n-CNn are consecutively connected one-by-one to either the first or the second reference voltage level +REF or −REF and remain in the position during the subsequent conversion steps. The intermediate results are stored in a register (successive approximation register) which resides together with other logic for controlling the analog-to-digital conversion process in a control stage referred to as successive approximation register control stage SAR-CNTL. The control stage SAR-CNTL may have an input for receiving a clock signal CLK and an input for receiving a start signal START which indicates that conversion is to be started. The control stage SAR-CNTL provides the digital output word which represents the digital value of the sampled input voltage at output node DOUT.
Up-to-date apparatuses, and corresponding semiconductor manufacturing processes, typically use supply voltages of 5 V or less in order to save power and to gain speed. The supply voltage limits the input signal range of the ADCs. In order to convert a +/−10 V input signal, which is a typical industrial standard, the signal is divided either with a resistive divider or with a capacitive divider, so as to fit the input signal voltage range into the comparator's input voltage range, which can basically be between ground and the supply voltage level. However, the division of the input signal decreases the signal-to-noise ratio (SNR) of the ADC. With a 5 V supply voltage range and an input range of, for example, +/−10 V (i.e. a division by 4 is used for an input range of +/−10 V), the least significant bit (LSB) of a 16 bit converter corresponds to 76 μV, although it could amount to 305 μV if the signal was not divided. The input range could also be +/−5 V or +/−12 V, etc., for example. A typical up-to-date 16 bit SAR converter has a noise level that corresponds to 2 to 6 LSB at the output for any DC input voltage. In order to handle the relatively large input voltage range, high-voltage transistors are used. Typical 5 V semiconductor manufacturing processes provide high-voltage transistors so that ADCs are available that have a high input voltage range even on a low voltage core that runs, for example, with the 5 V supply voltage. However, dividing the input signal is used, thereby decreasing the achievable SNR.
Furthermore, the analog cores of conventional analog-to-digital converters usually operate with single ended low voltage supply. The maximum voltage swing of high impedance nodes VCNEG, VCPOS inside the SAR ADC which are based on charge redistribution principal is limited by the maximum supply voltage range. The hold switches SWHp, SWHn that serve to store charge on the capacitors usually include NMOS and PMOS transistors, typically in form of transmission gates. The bulk of the NMOS transistors are usually connected to the lowest potential which is ground for single ended supplies. The bulk of PMOS transistors are typically connected to the supply voltage level. If the high impedance nodes (common nodes VCNEG, VCPOS) leave the admissible voltage range, the bulk diodes can be forward biased. The loss of charge on the high impedance nodes may decrease the performance dramatically. To avoid a leakage through parasitic diodes, a common mode voltage VCM is used. With single ended power supplies the common mode voltage level VCM is somewhere between ground and supply voltage level (i.e. higher than ground). Furthermore, in order to ensure good performance (i.e. for example good total harmonic distortion THD) a fast voltage buffer BU is used. However, this buffer BU continuously consumes power during the sampling phase. If very short acquisition time is used, the total power consumption of active components (in particular the power consumption of buffer BU) may be substantially increased.
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