1. Field of the Invention
The present invention relates generally to data processing systems, and in particular, relates to a data synchronization methodology for use with a data processing system.
2. Background Information
Several independent clocks running at different frequencies are often necessary within a digital system. For example, a processor may have a different clock frequency than a system bus. However, clock skew caused by phase variances between different high frequency clocks can result in hardware lock up and data errors or the inability to translate data from one clocked system to another. Clock skew between clocks of the same frequency occurs when the rising edges are not closely aligned. A common solution to clock skew in digital systems is the application of a phase-locked loop (PLL) circuit. A phase locked loop circuit reduces clock skew to levels that allow a system to function properly.
FIG. 1 illustrates a method for data synchronization between two frequency domains. Unit A is clocked using “clkl.” Unit B is clocked using “clkh.” Generally, “clkl” is a lower frequency than “clkh.” A PLL circuit placed in a feedback loop is used to control clock skew by tightly coupling “clkl” with “clkh.” Generally, the leading edges of the clocks are aligned to provide the tight coupling. Clock skew is kept near zero using the PLL method so that data transferred directly from unit A to unit B and from unit B to unit A occurs with minimal error.
A disadvantage to phase lock loops is the complexity and additional circuitry required to implement them in a digital system. Additionally, a phase locked loop is only effective when then clock frequencies can be correlated. Generally, the skew between the clocks must be small enough to still couple the leading edges with a PLL circuit. However, when clocks are distributed, clock skew increases as a consequence of distribution. Accumulated skew will eventually render data synchronization between two clocks impossible. Placing PLLs at each distribution node is one solution to skew problems with distributed clocks, but it is expensive in terms of area and harder to implement in large circuits.
Another limitation of direct data synchronization techniques, as in FIG. 1, is the inability to correlate clocks of fractional frequencies. Generally, it is a trivial matter to divide or multiply a clock by integer frequencies, but correlating data at non-integer frequency requires both clock multiplier and clock dividers. However, when clock multipliers and clock dividers are used together, the clock skew may reach levels that cannot be corrected by a PLL circuit.
USPTO Backgrounds
USPTO Backgrounds