1. Field of the Invention
The present invention relates to a semiconductor device fabrication method, and more particularly, to a transistor fabrication method capable of reducing both short channel effect and reverse short channel effect.
2. Description of the Prior Art
A semiconductor device based upon a silicon wafer includes device isolation regions for electrically isolating individual circuitry patterns. Since the device isolation regions are formed in an initial stage of a fabrication process and determine the magnitude of active areas and process tolerance of post-processing, research has been actively pursued to reduce isolation regions while reducing the size of a device, as semiconductor devices are gradually getting more highly integrated and ultrafine.
An isolation method via local oxidation of silicon (LOCOS) is widely used in fabrication of semiconductor devices since it advantageously has a simple process. However, in a highly integrated semiconductor device such as a 256M or higher level DRAM, as isolation regions are reduced in width, thickness of a device isolation film is decreased and punch through occurs owing to xe2x80x9cbird""s beakxe2x80x9d effect, thereby deteriorating effectiveness of the LOCOS method.
Another device isolation method using a trench, e.g., Shallow Trench Isolation (hereinafter referred to as STI) has been proposed as an adequate technique for device isolation of high-integrated semiconductor devices.
However, as the integrity of semiconductor devices gradually increases, the channel length of a gate gradually decreases. This disadvantageously increases reverse short channel effect as well as short channel effect.
The present invention has been made to solve the foregoing problems and it is therefore an object of the present invention to provide a transistor fabrication method capable of reducing both short channel effect and reverse short channel effect.
According to an aspect of the invention for realizing the above object, a transistor fabrication method comprises the following steps of: sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate while exposing at least a portion thereof; etching the substrate to form a trench, using the pad oxide film and the silicon nitride film as a mask; sequentially forming a first oxide film within the trench and a cylindrical insulation spacer at a lateral portion of the first oxide film; forming an insulation pattern for covering the inside of the trench, the first insulation film and the insulation spacer; etching the silicon nitride film, the insulation pattern and the insulation spacer to expose the pad oxide film; removing the pad oxide film; removing the insulation spacer and the first oxide film; sequentially forming source/drain regions and LDD regions on the underlying substrate at both sides of the trench, under the remaining insulation pattern; forming a second oxide film on the substrate including the source and drain regions; sequentially forming a channel stop layer between the LDD regions and a punch stop layer under the channel stop layer; and sequentially forming a gate insulation film and a gate region within the trench and the second oxide layer.
USPTO Backgrounds
USPTO Backgrounds