The invention relates, in general, to a non-volatile memory device and, more particularly, to a non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure with an improved erase speed, and a manufacturing method thereof.
Nonvolatile Semiconductor Memories (NVSM) are largely classified into floating gate series and Metal Insulator Semiconductor (MIS) series in which two or more kinds of dielectric layers are laminated doubly or triply in terms of the process technology.
The floating gate series implements a memory characteristic by employing a potential well. A representative example of the floating gate series is an EPROM Tunnel Oxide (ETO) structure that has been widely used as flash Electrically Erasable Programmable Read Only Memory (EEPROM). The MIS series performs a memory function by employing traps existing at the dielectric layer bulk, the dielectric layer-the dielectric layer interface, and the dielectric layer-semiconductor interface. A representative example of the MIS series is a Metal/Polysilicon Oxide Nitride Oxide Semiconductor (MONOS/SONOS) that has been widely used as flash EEPROM.
A difference between the SONOS and general flash memory is that in the general flash memory, charges are stored in the floating gate, whereas in the SONOS, charges arc stored in the nitride layer in terms of the structure.
Furthermore, in the general flash memory, the floating gate is formed using polysilicon. Thus, if any one defect exists in polysilicon, the retention time of charge is significantly lowered. In contrast, in the SONOS, the nitride layer is used instead of polysilicon as described above. Accordingly, the sensitivity to defect in process is relatively small.
In addition, in the flash memory, tunnel oxide having a thickness of about 70 Å is formed under the floating gate. There is a limit to the implementation of a low-voltage and high-speed operation. However, in the SONOS, direct tunneling oxide is formed under the nitride layer. It is therefore possible to implement a memory device having a lower voltage, lower power and high-speed operation.
A conventional flash memory device having a SONOS structure described below with reference to FIG. 1.
Referring to FIG. 1 a tunnel oxide layer 11, a nitride layer 12, a blocking oxide layer 13, a polysilicon layer 14, and a gate electrode 15 are sequentially formed over a semiconductor substrate 10. Word line patterns are then formed by an etch process.
In the flash memory device having a the SONOS structure, a different electric field (E-field) cannot be applied to an insulating layer because the same E-field cannot be applied to the whole complex layer of the blocking oxide layer 13 (i.e., an insulating layer), the nitride layer 12 (for storing charges) and the tunnel oxide layer 11.
In this case, if a voltage is applied to the gate electrode 15 so as to erase charges stored in the nitride layer 12, the charges stored in the nitride layer 12 are moved to the semiconductor substrate 10 by a Fowler-Nordheim (F-N) tunneling current through the tunnel oxide layer 11 and are then erased. However, since the same E-field is applied to the blocking oxide layer 13 over the nitride layer 12, the charges are moved from the gate electrode 15 to the nitride layer 12 through the blocking oxide layer 13 and are then programmed again, so that the erase speed is slowed.
To prevent the charges from being injected from the gate electrode 15 at the time of the erase operation, a material having a high work function is used in the gate electrode 15. However, this method is limited in terms of its improvement of the erase speed.
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