Systems where a plurality of processor cores share a main memory, in particular, systems such as SMP (Symmetric Multi Processing) and ccNUMA (cache-coherent Nonuniform Memory Access) maintaining cache coherence, often have problems resulting in a drop in performance caused by the plurality of processor cores simultaneously competing for one cache line. One such problem, “false sharing”, occurs when updating different stored words inside the same cache line.
If the unit of management (size of a cache line) of cache data is a word, there will be no competition for a cache line. However, a cache line normally handles units far larger than the size of words, so competition occurs. The same false sharing problem occurs in system controllers or memory controllers even in a cache-less system when the unit of management is larger than a word.
As a known hardware level false sharing countermeasure, there is a system that switches the cache protocol between a write invalidate scheme and a write broadcast scheme so as to control writing to a cache 12 depending on whether there is false sharing (Patent Literature 1). Further, there is known a system that keeps, for each word in a block, information on whether a word is exclusive or shared when all words in a cache block are valid and information on whether a word is valid or invalid when not all words in a cache block are valid (Patent Literature 2). However, it does not resolve false sharing.
Patent Literature 1: Japanese Laid-Open Patent Publication No. 2002-149489
Patent Literature 2: Japanese Patent No. 3226557
USPTO Backgrounds
USPTO Backgrounds