A conventional MOS device with sub-micron dimensions is illustrated in FIG. 1A. Illustratively, the device 10 of an integrated circuit (IC) is formed in a P-well region 12 of an N-type silicon substrate. N.sup.+ -type source and drain regions 14 and 16 are formed in the P-well 12. Field oxide (FOX) regions 15, 17, which are relatively thick oxide regions, separate the device 10 from adjacent devices formed on the substrate. The gate 18 is made from polysilicon. The gate 18 is separated from the P-well surface by the thin gate oxide 19 and has dielectric spacers 20, which also may be oxide formed on its laterally adjacent sides.
The device 10 is covered by a pre-metal dielectric (PMD) layer 30 having a thickness of 6000.about.9000 Angstroms. Illustratively, the PMD layer 30 has a lower layer 32 covered by an upper layer 34. The lower layer 32 is a layer of undoped oxide such as TEOS (Tetraethylorthosilicate) oxide or siloxane based oxide. The upper layer 34 is BPSG (borophosphosilicate glass) or PSG (phosphosilicate glass). The PMD layer 30 is formed using a low pressure chemical vapor deposition system or atmospheric pressure chemical vapor deposition system.
The subject of the present invention is the formation of contact openings 40 over the source and drain regions 14 and 16. A metallization process deposits metal in the contact openings 40 to form metal contacts 50. The contact openings 40 are formed by etching the PMD layer 30. The etching involves two steps, a BHF wet etch followed by anisotropic dry etch, in which steps the PMD layer 30 is 40% and 60% etched, respectively. Typically, the vertical contact opening aspect ratio (depth/width) is about 1.4.about.1.7.
Prior to the metallization process that forms the metal contact 50 shown in FIG. 1A, and after etching the PMD layer 30 to form the contact openings 40, a second wet etching step is performed to remove native oxides from the contact openings 40. Native oxides are undesirable as they cause discontinuity between the metal contact 50 and the substrate. This increases contact resistance and degrades performance of the IC. The second wet etch that removes the native oxides results in a vertical contact opening 40A shown in FIG 1B.
A reflow step may be performed to round off the top of the contact opening 40 .ANG. before the second wet etch process. The vertical contact opening 40A may be shaped into a champagne glass shape opening. FIG. 1C shows a champagne glass shape opening 40B formed by a reflow step that tapers and rounds off the top of the vertical contact opening 40A (FIG. 1B).
After removing the native oxides, the metal contacts 50 are formed in the openings 40 according to a so-called metal (I) process. A variety of processes have been suggested in the prior art for the metal (I) process and these are reviewed below. In general, the metal (I) process is used to form metal (I) contacts 50 in the contact openings 40. However, in order to interconnect devices formed on the surface of the same substrate, it is necessary to form vias which extend horizontally on the substrate surface (not shown in FIG. 1). To form the vias, an inter-metal dielectric (IMD) involving a PECVD/SOG/PECVD (plasma enhanced chemical vapor deposition oxide/spin-on glass/plasma enhanced chemical vapor deposition oxide) sandwich is formed on the substrate surface. Openings for the vias are then etched in the inter-metal dielectric. Then, metal is formed in the via openings using a metal (II) process.
In a MOSFET device with submicron dimensions, sub-micron metallization has been formed using the conventional W(tungsten)-CVD plug process. Alternatively, a conventional Al-based metallization process may be used.
The conventional aluminum process for forming the metal (I) contact may be understood in connection with FIG. 2. A conventional sputtering machine is used.
The steps for forming the metal (I) contact 50 in the opening 40 are as follows:
This completes the metal (I) deposition process.
Then, the inter-metal dielectric (IMD) layers are formed. Next, the wafer is subjected to lithography to pattern the IMD to form via openings for the vias formed by a metal (II) process.
The purpose of the Ti/TiN layers is to prevent aluminum from diffusing into the silicon substrate. The Ti/TiN layers serve as a barrier for aluminum diffusion. If the Ti/TiN barrier is not good enough and Aluminum diffuses through the barrier into the silicon substrate, there will be junction leakage and device failure. The purpose of the vacuum break and anneal steps is to stuff the grain boundaries of the Ti/TiN layers so that the aluminum and silicon do not diffuse together in the subsequent aluminum deposition step.
An important problem with conventional formation of the opening 40 is widening of the bottom of the opening 40. During the etching steps that form and clean the opening 40, in both the vertical and the champagne glass shape openings 40A, 40B (FIGS. 1B, 1C), the bottom of the contact opening widens due to different etch rates of the lower and upper layers 32, 34. Thus, as shown in FIGS. 1B, 1C, and 2, the width 60 at the base or bottom of the contact openings 40, 40A, 40B, which is in the lower oxide layer 32, is larger than the width 62 of the contact openings 40, 40A, 40B, at the upper BPSG layer 34. The wide or "negative profile" of the bottom of the openings 40, 40A, 40B results in poor step coverage during the metal (I) process.
As shown in FIG. 2, the side wall thickness of the aluminum based layer 86 approaches zero at the lower portion of the contact opening 40. The thickness "a" of the Ti/TiN/Al layers 82, 84, 86 near the top of the opening 40 is more than the thickness "b" near the bottom of the opening 40. This results in poor step coverage SC, where SC equals: SC=(b/a).times.100% . The poor step coverage during the metal (I) process may lead to less metal continuity, higher contact resistance, and even lower device reliability and an increased failure rate.
Accordingly, it is an object of the invention to provide a special etch to form a positive profile at the bottom of the contact opening to overcome the shortcomings of the prior art.
In particular, it is an object of the invention, to provide an etching solution so that etching is faster in the BPSG layer than in the TEOS oxide under layer of the PMD layer.
USPTO Backgrounds
USPTO Backgrounds