1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to partially accessing a dynamic random access memory (DRAM), and more particularly, to partially accessing a DRAM to efficiently perform a memory access processing.
2. Description of the Related Art
DRAMs are widely used as main memories of digital systems. Particularly, as demands for a large system bandwidth for processing various functions continuously increase, the operating frequencies of DRAMs also gradually increase.
Generally, if the operating frequencies of DRAMs increase, the demands for a large system bandwidth are satisfied. However, the operating frequencies of a large number of master modules connected to a system bus must also increase in order to raise a data transfer rate by increasing the operating frequency of a memory, and thus it is very difficult or impossible to design the system.
While high-speed memories such as DDR2 SDRAM, DDR3 SDRAM and Rambus DRAM have recently been developed and form the basis for increasing system performance, the operating frequency of a system bus has to be increased in order to use a memory having a higher clock frequency. This may result in excessive overhead for a chip size, high power consumption and an increase in the manufacturing cost.
FIG. 1 is a block diagram of a related art apparatus for accessing a DRAM. Referring to FIG. 1, the related art DRAM accessing apparatus includes a memory controller 102. The memory controller 102 includes a single memory interface 103 and is connected to first and second DRAMs 104 and 105 through the memory interface 103. The memory interface 103 transmits the same control signal of the memory controller 102 to first and second DRAMs 104 and 105.
The first and second DRAMs 104 and 105 are connected in parallel with each other through the single memory interface 103 of the single memory controller 102. Thus, the first and second DRAMs 104 and 105 share the control signal transmitted from the memory controller 102 and respectively write and read data.
FIG. 2 is a timing diagram illustrating the generation of a garbage cycle, which is a cycle that wastes a data transfer bandwidth, when data is read at a double data rate (DDR) in the related art DRAM accessing apparatus illustrated in FIG. 1. Referring to FIG. 2, it is assumed that the length of requested data is smaller than the burst length of the DRAMs 104 and 105 (Refer B data in FIG. 2). Data requested to be read through a system bus 101 includes data B0, B1, B2 and B3 each having 16 bits. The data B0, B1, B2 and B3 read from the DRAMs 104 and 105 is rearranged as 64-bit data B(3210) in the memory controller 102 and output to the system bus 101.
The memory controller 102 reads data DQ of the DRAMs 104 and 105 in response to a single control signal, and thus the data DQ should be read in the order of DQ1 (B0), DQ2 (B1), DQ1 (B2) and DQ2 (B3). Accordingly, unnecessary data B4, B5, B6 and B7 corresponding to the burst length of the DRAMs 104 and 105 have to be read.
As described above, the related art DRAM accessing apparatus generates a garbage cycle that wastes a data transfer bandwidth when the length of data requested to be read from the DRAMs 104 and 105 is shorter than the burst length of the DRAMs 104 and 105 because the DRAMs 104 and 105 are controlled in response to a single control signal.
Furthermore, when a request from a video CODEC is processed, data is processed for each block of a frame. In this process, a request to read data having a length less than the burst length of a DRAM is frequently generated. Accordingly, a solution for reducing waste of the data transfer bandwidth when data is requested is desired.
USPTO Backgrounds
USPTO Backgrounds