There are a number of approaches to solving the problem of modulating radio frequency (RF) carrier phase and frequency. The translational loop (TL), or offset phase-locked loop (PLL) uses a mixer in the feedback path of a transmit PLL to offset the output carrier frequency and an analog baseband I/Q data modulator in either the reference or feedback path of the transmit PLL to apply modulation. The primary drawback to the TL is that it requires well matched IF circuits that can occupy much more area than a design comprised primarily of digital blocks.
Another approach to modulating the output RF carrier is to apply the modulation via the feedback divider in a fractional-N PLL synthesizer. In this case a sigma-delta programmed multi-modulus divider is typically used to vary the loop output frequency and/or phase. The primary drawback to this architecture is that it requires careful calibration of the loop components and pre-emphasis filtering of the digital data in order to mitigate the distortion caused by the filtering in the PLL when the data bandwidth is greater than or comparable to the loop bandwidth. In some cases, this calibration can be more difficult by the fact that the fractional-N PLL bandwidth must be made narrower than the signal bandwidth in order to reject the shaped sigma-delta quantization noise and reference source noise.
In an integrated circuit with an integrated power amplifier (PA) in the modulation path, which causes temperature drift of loop components during a burst, the design requires either an adaptive pre-emphasis filter or a technique for adaptively adjusting the loop gain, both of which are non-optimal.
USPTO Backgrounds
USPTO Backgrounds