1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
In recent years, with the view of achieving an even higher degree of package that is formed of a semiconductor chip in a longitudinal direction, development of three-dimensional implementation of semiconductor chips such as an LSI has lately been vigorously carried out. Such attempts include a technique disclosed in JP-A Laid Open No. 2003-101,000. A semiconductor device described therein is shown in FIG. 11. FIG. 11 is a schematic cross-sectional view showing a multi-chip stack structure based on a conventional silicon spacer.
A semiconductor device 1100 comprises a semiconductor chip 1104 and a semiconductor chip 1106 on a substrate 1102. A silicon spacer 1108 is interposed between the semiconductor chip 1104 and the semiconductor chip 1106.
The semiconductor chip 1104 is provided with electrode pads 1114a and 1114b on the upper surface thereof, and is connected to electrode pads 1112b and 1112c, which are provided on the upper surface of the substrate 1102, through wires 1120c and 1120b, respectively.
The semiconductor chip 1106 is provided with electrode pads 1116a and 1116b on the upper surface thereof, and is connected to electrode pads 1112a and 1112d, which are provided on the upper surface of the substrate 1102; through wires 1120d and 1120a, respectively.
JP-A Laid Open No. 2003-101,000 describes that a gap or a space can be provided between the lower semiconductor chip 1104 and the upper semiconductor chip 1106 due to a presence of a silicon spacer 1108, and consequently, a wire bonding can be performed on the lower semiconductor chip 1104.
JP-A Laid Open No. 2003-101,000 also describes that such structure is particularly effective in a case where the upper semiconductor chip 1106 is larger than the lower semiconductor chip 1104, or in a case where the chip sizes of both are nearly equivalent.
In addition, another example of such technique is disclosed in JP-A Laid Open No. 2000-252,408. A semiconductor device disclosed therein is shown in FIG. 12. FIG. 12 is a schematic cross-sectional view showing a conventional chip-on-chip structure employing insulating films.
The chip-on-chip structure includes a first semiconductor chip 411 and a second semiconductor chip 417. Between the first semiconductor chip 411 and the second semiconductor chip 417, an insulating film 414 is interposed. The insulating film 414 includes a structure that an interconnect pattern 416 and an interconnect pattern 420 are provided on a film 415.
The interconnect pattern 416 is provided with a connection portion 423 at a lower surface thereof. The connection portion 423 is connected to a bump 413a of the first semiconductor chip, formed on a surface 412 of the first semiconductor chip. The interconnect pattern 416 is also provided with a connection portion 424 on an upper surface thereof. The connection interface 424 is connected to a bump 419a of the second semiconductor chip, formed on a surface 418 of the second semiconductor chip.
The interconnect pattern 416 is provided with a connection portion 423 at a lower surface thereof. The connection portion 423 is connected to a bump 413a of the first semiconductor chip, formed on a surface 412 of the first semiconductor chip. The interconnect pattern 416 is also provided with a connection portion 424 on an upper surface thereof. The connection portion 424 is connected to a bump 419a of the second semiconductor chip, formed on a surface 418 of the second semiconductor chip.
According to JP-A Laid Open No. 2000-252,408, the described structure enables stacking and connecting semiconductor chips that have different intervals between electrodes and/or different electrode positions, thereby offering a higher degree of freedom in designing a chip-on-chip type semiconductor device.
USPTO Backgrounds
USPTO Backgrounds