The present process relates to an exemplary method for fast growth (over 100 nm/m) and thickness (over 10 micron) of epitaxial Si at substrate temperatures above 570° C., or above the surface dehydrogenation temperature of the silicon surface, but less than 700° C. at base pressure, preferably about 10−6 Torr, using hot wire chemical vapor deposition (HWCVD). The film produced is used primarily for photovoltaic applications; however, these epitaxial Si films are also applicable to other semiconductor devices. The surface morphology can be controlled during the growth from smooth to a pyramidal shape, which is ideal for light trapping in film—Si photovoltaics. Further, the method of growth of epitaxial Si is possible with undoped, n- and p-type doping and on several orientations of the substrate crystalline silicon (c-Si), including the difficult <111> surface or face.
U.S. Pat. No. 6,210,991 B1 discloses A1 induced epitaxial growth of Si at elevated temperature to make a thin (<1 micron), heavily-doped contact to c-Si. In this epitaxial growth, Al diffuses thru Si and makes c-Si.
The growth of a diamond-like carbon film using controlled nuclei is disclosed in U.S. Pat. No. 6,506,451 using the growth technique of hot-wire CVD.
U.S. Pat. No. 6,902,973 discloses hemi-spherical grain silicon enhancement by forming epitaxial silicon on hemi-spherical grain Si for a semiconductor device. The epitaxial Si film was formed by a multi-step, multi-gas thermal CVD process at high temperature from 750° C. to 900° C. The thickness is only about 10 nm and the localized epi-Si growth is used to form small size grains.
Epitaxial and polycrystalline growth of Si 1-x-y GexCx and Si 1-xCy alloy layers on a Si by UHV-CVD is disclosed in U.S. Pat. No. 6,908,866. In particular, the process relates to heteroepitaxial growth of Si—C and SiGe—C on c-Si growth by Ultra-High Vacuum (below 10−8 Torr) CVD at low temperatures (475° C.-850° C.). The method is limited to a certain thickness of epitaxial growth of less than 1 micron before epitaxy breaks down into polycrystalline growth.
U.S. Pat. No. 5,906,680 discloses CVD silicon epitaxy and its growth system requires a temperature (800° C.) that would melt borosilicate and other glasses at its low base pressure of about 10−9 Torr.
A process for forming a trench power MOS device suitable for large diameter wafers is disclosed in U.S. Pat. No. 6,974,750B2. The process includes the use of a standard high temperature (˜800° C.-1200° C.) CVD epitaxial growth of c-Si from SiH4-over a 6 inch c-Si wafer to form a trench power MOS. This epitaxy step is at high temperature, and quite standard.
A method of forming a contact plug in a semiconductor device is disclosed in U.S. Pat. No. 7,049,230. The method entails heat treatment of deposited amorphous Si into epitaxial Si, namely solid phase epitaxial (SPE) growth at 550° C.˜650° C. to produce epitaxial layers less than 0.2 microns thick.
U.S. Patent Application 2003/0045075 discloses a method of selective epitaxial growth for semiconductor devices, which was an improved selective epitaxial growth using a cyclical approach, in which epitaxial growth has been interrupted periodically. The epitaxy is done at 750° C. by CVD, with various gases used in selective etching through a mask layer.
De Boer et al. in “Low Temperature Epitaxial Silicon Film Growth Using High Vacuum Electron-Cyclotron-Resonance Plasma Deposition,” Appl. Phys Lett. 66(19), 8 May 1995, Pages 2528-2530 discloses epitaxial Si growth at low temperature for a maximum of about 2 microns using electron-cyclotron-resonance (ECR-CVD) plasma deposition in a system with a base pressure of just below 107 Torr and at low temperatures (450° C.-525° C.).
U.S. Pat. No. 6,251,183 discloses a process for depositing an epitaxial layer on a crystalline substrate, comprising providing a chamber having an element capable of heating, introducing the substrate into the chamber, heating the element at a temperature sufficient to decompose a source gas, passing the source gas in contact with the element, and forming an epitaxial layer on the substrate. The low temperature region in this process is below 400° C. and no reference to the use of a temperature above 600° C. is disclosed.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.
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