This invention relates to programmable logic array integrated circuit devices, and more particularly to improved features for such devices (e.g., improved programmable interconnectivity between the programmable logic regions of such devices).
Programmable logic array integrated circuit devices are well known, as shown, for example by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611. Such devices often include a large number of regions of programmable logic disposed on the device in a two-dimensional array of intersecting xe2x80x9crowsxe2x80x9d and xe2x80x9ccolumnsxe2x80x9d of such regions. Each region is programmable to perform any of several logic functions on signals applied to the region. Each row may have associated xe2x80x9chorizontalxe2x80x9d conductors for conveying signals to, from, and/or between the regions in the row. Each column may have associated xe2x80x9cverticalxe2x80x9d conductors for conveying signals from row to row. Programmable connections may be provided for selectively connecting the conductors adjacent to each region to the inputs and outputs of the region, and also for selectively connecting various conductors to one another (e.g., connecting a horizontal conductor to a vertical conductor). Interconnection of regions through the above-mentioned conductors and programmable connections makes it possible for the programmable logic array device to perform much more complicated logic functions than can be performed by the individual regions.
Advances in integrated circuit fabrication technology have made it possible to produce programmable logic array devices with very large numbers of logic regions. As the number of logic regions increases, however, it becomes increasingly important to select the numbers and arrangements of the interconnection conductors and the programmable connections between those conductors and the regions. Complete generality of these interconnection resources (i.e., so that any desired interconnection can be made no matter what other interconnections are made) would lead to exponential growth in the chip area occupied by those resources as the number of logic regions increases. This is especially disadvantageous in the case of reprogrammable devices because of the larger size and greater circuit loading and signal propagation delay of reprogrammable interconnection elements as compared to one-time-only programmable interconnection elements. (One-time-only programmable devices are shown, for example, El Gamal et al., xe2x80x9cAn Architecture for Electrically Configurable Gate Arrays,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, June 1989, pp. 394-98; El-Ayat et al., xe2x80x9cA CMOS Electrically Configurable Gate Array,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, June 1989, pp. 752-62; and Elgamal et al. U.S. Pat. No. 4,758,745.) Moreover, most of any completely general interconnection resources would be unused and therefore wasted in virtually all applications of the device. On the other hand, many applications of the device may require substantial interconnection resources, and because the device is intended to be a general-purpose device, it is extremely important to commercial success that the device be capable of satisfying a very wide range of potential applications, many of the requirements of which cannot be known in advance by the designer of the programmable logic array device.
Considerations such as the foregoing make it essential to provide increasingly sophisticated interconnection resources in programmable logic array devices, and especially in reprogrammable logic array devices. The aim is to hold down the fraction of the xe2x80x9creal estatexe2x80x9d of the chip that is devoted to interconnection resources, e.g., by optimizing various features of those resources, by increasing the flexibility with which those resources can be used, etc. Moreover, this is preferably done without undue circuit loading and speed penalties due to passing signals through excessive numbers of switches or tapping conductors to large numbers of switches. (Compare the above-mentioned El Gamal, El-Ayat, and Elgamal references, as well such other references as Freeman U.S. Pat. No. Re. 34,363 and Carter U.S. Pat. No. 4,642,487, all of which rely heavily on programmably piecing together relatively short conductor segments when longer conductors are needed.)
In view of the foregoing it is an object of this invention to provide improved programmable logic array devices.
It is a more particular object of this invention to provide improved arrangements of interconnection resources on programmable logic array integrated circuits.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices having the traditional two-dimensional array of programmable logic regions with horizontal conductors associated with each row and vertical conductors associated with each column, but with the difference that some of the horizontal conductors associated with each row extend continuously or substantially continuously along only approximately half the length of the row. Thus each row is divided into two mutually exclusive halves, with some xe2x80x9chalf-horizontalxe2x80x9d conductors extending along each of the two halves. In this way a half-horizontal conductor can be used to make connections to, from, and/or between logic regions in a half of the row without having to use a much longer than necessary full-horizontal conductor for this purpose. The full-horizontal conductors (which extend continuously or substantially continuously along the entire length of a row, and which are sometimes also referred to as global horizontal conductors) can be saved for signals that must be transmitted beyond either half of the row. Because two end-to-end half-horizontal conductors occupy the same space as one full-horizontal conductor, the provision of half-horizontal conductors makes more efficient use of the horizontal conductor real estate on the chip. In particular, the half-horizontal conductors allow the number of full-horizontal conductors to be reduced. Reducing the number of horizontal conductors also helps reduce the size of the programmable switch arrays used to programmably connect the horizontal conductors to the inputs of each logic region. Axially aligned and adjacent half-horizontal conductors are preferably not directly connectable to one another. Thus there is preferably no possibility of programmably optionally piecing together axially aligned half-horizontal conductors to make longer horizontal conductors. Instead, that longer horizontal conductor resource is the global horizontal conductors, which are preferably continuous or substantially continuous and not made up of pieced-together shorter conductors.
Each logic region output signal is preferably programmably connectable to one full-horizontal conductor and one half-horizontal conductor. Each full- and half-horizontal conductor associated with a row is drivable by either of two outputs of logic regions in that row. Each logic region output is also programmably connectable to a vertical conductor. Having two logic region outputs share each full- and half-horizontal conductor also helps to reduce the number of horizontal conductors that must be provided. Again, this helps reduce the size of the programmable switch arrays used to programmably connect the horizontal conductors to the inputs of each logic region.
Both the half-horizontal and the full-horizontal conductors are programmably output-connectable to so-called xe2x80x9chorizontalxe2x80x9d input/output (xe2x80x9cI/Oxe2x80x9d) pins for purposes of outputting signals from the chip. For purposes of inputting to the chip, both the half-horizontal and the full-horizontal conductors could be programmably input-connectable to the horizontal I/O pins, but in the preferred embodiments only the full-horizontal conductors are thus programmably input-connectable.
Certain full-horizontal conductors (e.g., those that can receive inputs from the horizontal I/O pins) are programmably connectable to drive certain vertical conductors. These vertical conductors are programmably connectable to drive other horizontal conductors in other rows. This gives the device the ability to route any horizontal input to any logic region in the device.
Each output of each logic region is programmably connectable to a half-horizontal conductor adjacent to the region, to a full-horizontal conductor adjacent to the region, and to two vertical conductors adjacent to the region. In addition, regions in adjacent columns are paired so that each output of each logic region in such a pair can alternatively use the output connections (to the above-mentioned half-horizontal, full-horizontal, and vertical conductors) of the corresponding output of the other region in the pair. This gives each output of a region two different sets of conductor destinations, thereby increasing interconnection flexibility without increasing the number of conductors that must be provided. Because these conductors are connectable to input/output (xe2x80x9cI/Oxe2x80x9d) pins of the device, the number of I/O pins that each logic region output can reach is also doubled.
In the preferred embodiments each logic region includes several logic modules. Each logic module has several input signals and is programmable to produce a combinational signal which is a desired logical combination of the inputs. Each logic module also includes a register (e.g., a flip-flop). The combinational signal can be passed to the output of the logic module either directly or via the register. To make a register usable, even when it is not being used to register the combinational signal of the logic module, programmable switches are provided for allowing one of the logic module inputs to be applied to the register. Additional programmable switches are provided for allowing either the combinational signal (which is bypassing the register) or the register output signal to be applied to feedback circuits within the logic region. These additional switches also allow the signal which is not being applied to these feedback circuits to be applied to the above-mentioned conductors that go beyond the region. In other words, either the combinatorial or registered output signal can be used for either local feedback or region output. This is a greater degree of flexibility in the simultaneous use of a combinational signal and a so-called xe2x80x9clonely registerxe2x80x9d signal than is possible in the known prior devices.
Another feature that may be provided in accordance with this invention is an input-pin-driven global clear function for resetting all registers in the device.
Circuitry is added to each logic module and to I/O registers to make it possible to do clock enables more efficiently. A clock enable now requires only two logic module inputs, and dedicated clock enables are provided in the peripheral I/O cell logic.
The I/O cells are enhanced to include the following features: (1) an open drain option, (2) clock enables (mentioned above), (3) a pin-controlled global output enable, and (4) dedicated clocks. Each I/O cell also has dedicated output enable circuitry which is controlled directly from the horizontal conductors for horizontal I/O pins or from the vertical conductors for vertical I/O pins.
It is known to provide carry chain connections from one logic module to another in a logic region and from one logic region to another. Such carry chain connections facilitate the performance of arithmetic functions such as adders and counters. In accordance with the present invention carry chain connections are not made between adjacent logic regions. Rather, the carry chain connection from each logic region skips the immediately adjacent logic region and goes to the next most nearly adjacent logic region. This spreads out an arithmetic chain to ease the fitting problems encountered, for example, by having a 16-bit counter all bunched together.
It is also known to provide cascade chain connections from one logic module to another in a logic region and from one logic region to another. Such cascade chain connections facilitate the performance of wide fan-in functions, for example. In accordance with this invention cascade chain connections are made in a similar fashion to carry chain connections. Thus cascade connections are not made between adjacent logic regions. Rather, the cascade connection from each logic region skips the immediately adjacent region and goes to the next most nearly adjacent logic region. This also eases fitting problems associated with wide fan-in functions.
So-called fast conductors are provided which extend to every logic region on the device. Such conductors are useful for purposes such as providing a global clock signal. To facilitate generation of a fast line signal by the device itself certain other conductors such as full-horizontal conductors are programmably connectable to the fast line conductors.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
USPTO Backgrounds
USPTO Backgrounds