1. Field of the Invention
The present invention generally related to a charge pump circuit for generating a charge current and a discharge current, and more particularly, to a charge pump circuit which is used as a charge/discharge current generation circuit in a PLL (Phase-Locked Loop) circuit, to a PLL circuit, and to a pulse-width modulation (PWM) circuit which utilizes the PLL circuit.
2. Background Art
FIG. 21 shows a conventionally-known charge pump circuit to be used with a PLL circuit.
In FIG. 21, reference numeral 200 designates a phase-difference comparison circuit which produces an "UP" and "DOWN" signal on the basis of a phase difference between the reference clock signal and a clock signal to be compared, and 100 designates a charge pump circuit which outputs a charge or discharge current to a low-pass filter upon receipt of the "UP" and "DOWN" signal from the phase-difference comparison circuit.
The charge pump circuit 100 comprises an inverter circuit "In", a P-type MOS transistor "Tp", and an N-type MOS transistor "Tn". The inverter circuit "In" inverts an "UP" signal received from the phase-difference comparison circuit 200. The transistor "Tp" is connected between a supply voltage node to which a supply voltage (Vcc) is applied and an output node which outputs a charge or discharge current. The gate electrode of the transistor "Tp" receives the "UP" signal that is inverted by the inverter circuit "In". In contrast, the transistor "Tn" is connected between a ground potential node to which a ground potential is applied and the output node. The gate electrode of the transistor "Tn" receives the "DOWN" signal from the phase-difference comparison circuit 200.
With the foregoing configuration, the phase-difference comparison circuit 200 outputs an "UP" and "DOWN" signal on the basis of the phase difference between the reference clock signal and a clock signal to be compared.
When the phase-difference comparison circuit 200 outputs a high-level pulse signal as an "UP" signal, the pulse signal is inverted to a low-level pulse signal by the inverter circuit "In" and is input to the transistor "Tp". Upon receipt of the low-level pulse signal, the transistor "Tp" is brought into conduction, so that a charge current "i1" is output from the output node.
In contrast, when the phase-difference comparison circuit 200 outputs a high-level pulse signal as a "DOWN" signal, the high-level pulse signal is applied to the transistor "Tn". Upon receipt of the high-level pulse signal, the transistor "Tn" is brought into conduction, so that a discharge current "i2" is output from the output node.
In this way, the charge current "i1" or the discharge current "i2" is output from the output node.
In the charge pump circuit having the foregoing configuration, in order to prevent a dead band being formed, when there is no phase difference between the reference clock signal and a clock signal to be compared, the phase-difference comparison circuit 200 outputs the "UP" and "DOWN" signals in the form of a high-level pulse signal for a short period of time within one cycle of the reference clock signal. When the charge pump circuit 100 receives the "UP" and "DOWN" signals having high-level, both the transistors "Tp" and "Tn" are brought into conduction, so that the charge current "i1" and the discharge current "i2" flow through the transistors.
At this time, so long as the transistors "Tp" and "Tn" are designed in such a way that the charge current "i1" and the discharge current "i2" are the same value, the charge current output from the output node to the low-pass filter or the discharge current output from the low-pass filter to the output node, namely, the output current of the charge pump circuit 100 becomes zero. In short, so long as the transistors "Tp" and "Tn" are designed in such a way discussed above, the output current becomes zero when the phase difference between the reference clock signal and a clock signal to be compared is zero as depicted by line A provided in FIG. 22.
In FIG. 22, the horizontal axis represents a phase difference between the reference clock signal and a clock signal to be compared, and the vertical axis represents an output current which includes a mean current output from or received by the output node during one cycle of the reference clock signal. The area where the phase difference takes a positive value exhibits a situation where the clock signal to be compared leads the reference clock signal. In contrast, the area where the phase difference takes a negative value exhibits a situation where the clock signal lags behind the reference clock signal. Further, the area where the output current takes a positive value exhibits a situation where a charge current is output to the low-pass filter from the output node. In contrast, the area where the output current takes a negative value exhibits a situation where a discharge current flows into the output node from the low-pass filter.
However, even if the transistors "Tp" and "Tn" are designed in such a way that output currents from the transistors become zero when the phase difference between the reference clock signal and a clock signal to be compared is zero, the transistors "Tp" and "Tn" may vary from their design values because of variations in manufacturing processes.
For example, if the channel length of the transistors "Tp" and "Tn" becomes shorter than a design value, an electric current flowing through the transistors "Tp" and "Tn" when the transistors are in conduction becomes greater than an electric current which would otherwise flow through the transistors if the transistors were designed in accordance with the design value. Generally, in this case, the transistor "Tp" makes the current grater with a higher ratio than the transistor "Tn" does. In short, when the transistors "Tp" and "Tn" are in conduction, the current flowing through the transistor "Tp" becomes greater than that flowing through the transistor "Tn". As a result, as depicted by line B provided in FIG. 22, an output current (or a charge current) flows through the output node when the phase difference between the reference clock signal and a clock signal to be compared is zero, and the output current becomes zero when the clock signal to be compared lags behind the reference clock signal by the offset width W1.
In contrast, if the channel length of the transistors "Tp" and "Tn" becomes longer than a design value, an electric current flowing through the transistors "Tp" and "Tn" when the transistors are in conduction becomes smaller than an electric current which would otherwise flow through the transistors if the transistors were designed in accordance with the design value. Generally, in this case, the transistor "Tp" makes the current smaller with a higher ratio than the transistor "Tn" does. In short, when the transistors "Tp" and "Tn" are in conduction, the current flowing through the transistor "Tp" becomes smaller than that flowing through the transistor "Tn". As a result, as depicted by line C provided in FIG. 22, an output current (or a discharge current) flows through the output node when the phase difference between the reference clock signal and a clock signal to be compared is zero, and the output current becomes zero when the clock signal to be compared leads the reference clock signal by the offset width W2.
Relative to the supply voltage (Vcc) applied to the supply voltage node, characteristics of the charge pump circuit 100 must be compensated for within a certain range of supply voltage. When the charge pump circuit is used in a condition where the supply voltage is higher or lower than a specified value, the characteristics of the charge pump circuit 100 depicted by line A provided in FIG. 22 shift toward the line B or the line C, so that the offset of the phase difference is provided.
Relative to the operating temperature of the charge pump circuit 100, the characteristics of the charge pump circuit 100 must be compensated for within a range of, e.g., 0 to 70.degree. C. Depending on the operating temperature, the characteristics of the circuit 100 depicted by line A provided in FIG. 22 shift toward the line B or C, so that the offset of the phase difference is provided as well.
As mentioned above, the offset of the phase difference corresponding to the zero output current is provided because of variations in the processes of manufacture of the transistors "Tp" and "Tn", of variations in the supply voltage (Vcc) applied to the supply voltage node, and of variations in the operating temperature.
In a case where the foregoing charge pump circuit 100 is used with a PLL circuit, the presence of such an offset signifies that a phase difference constantly arises in a steady state in which the PLL circuit is locked. In short, the presence of such an offset signifies a lag in a timing of the output from the PLL circuit, eliminating a margin of timing design.
Such an offset poses little problem for a charge pump circuit which operates at a PLL circuit at low speed, or a charge pump circuit using the low-frequency reference clock signal and a low-frequency clock signal to be compared. In contrast, in the case of a charge pump circuit which operates at high speed, or a charge pump circuit using the high-frequency reference clock signal and a high-frequency clock signal to be compared, the offset eliminates a margin of timing design, thus posing a very serious problem.
USPTO Backgrounds
USPTO Backgrounds