In an information handling system using subsystems which are operating at different clock frequencies, the rate of flow of information transfer between the subsystems is not the same and data cannot be effectively transferred because the subsystems are out-of-phase or out-of-time with one-another. A disadvantage to operating subsystems with different clock frequencies is that synchronization circuitry must be added to compensate for differences in the rate of flow of information between the different subsystem clock environments. A "subsystem clock environment" is that part of an information handling system in which the data processing resources are operating at the same clock frequency. Once the data signals of the multiple subsystem clock environments are synchronized, information may then pass between the multiple subsystems over a data bus.
When using the prior art synchronization circuit and method to compensate for differences in the data transfer rate between asynchronous subsystems, the signal being synchronized arrives at the synchronization circuit flip-flop asynchronous relative to the synchronization clock. This condition results in an inability to guarantee that the setup time and hold time specifications of the synchronization circuitry have been met. Thus, the prior art synchronization circuit and method require that the signal being synchronized be clocked initially by at least one synchronization clock to remove any metastability that might result on the subsystem side due to the inability to guarantee that the proper setup time and hold time have been met for the signal to be synchronized, and must be clocked subsequently to produce a final synchronization signal.
The prior art synchronization inherently introduces delays in data transfer across subsystem clock environments, contributes to an overall loss of system performance, and causes the information handling system's performance to be non-competitive when compared to systems using synchronous subsystem design. Therefore, there is a need to be able to reduce synchronization delays incurred when an information handling system uses an asynchronous subsystem design.
USPTO Backgrounds
USPTO Backgrounds