1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and storage apparatus, and is particularly suitable for use in a semiconductor integrated device enabling normal device operation even when a failure occurs in a large scale integrated circuit, by using another programmable large scale integrated circuit, and a semiconductor integrated circuit device having such a semiconductor integrated circuit device.
2. Description of Related Art
With the development in semiconductor technology, manufacturing processes for semiconductor integrated circuits called LSI (Large Scale Integration circuit) or ASIC (Application Specific Integrated Circuit) have been subdivided to enhance the integration, speed, and performance of the semiconductor integrated circuits. In the case of an ASIC, once it is manufactured, no modification can be made for a change in the specifications or for a bug in the logical circuit, so the ASIC has to be reproduced using a new logical circuit. In recent years, the cost and time required for the development of ASICs have increased due to the subdivided processes, accordingly, the cost for reproducing ASICs is extremely high.
Known as a method for solving the above problem is a technique whereby the reproduction of ASICs becomes unnecessary because FPGAs (Field Programmable Gate Array) are used in combination with ASICs. With this technique, when a bug is found in one of the logical blocks in an ASIC or when it is necessary to change a logical block in accordance with a change in the specifications, the function of that logical block is implemented in the FPGA to enable a bug patch or response to the specification change without reproducing the ASIC, and this technique is disclosed in, for example, JP2001-177058 A.
There is another technique whereby a failure in an ASIC is detected by its self-test function and the faulty part is replaced with a FPGA so that the ASIC can keep on operating without being replaced.
With the conventional techniques, logical blocks that can be replaced with FPGAs are fixed. For example, where a block with a bug or a block subject to a specification change is already identified in an ASIC, the function of that block is previously implemented in a FPGA, and that block on the ASIC is not used.
Moreover, regarding a self-test function, self-test and replacement of a faulty logical block with a FPGA are performed only when an ASIC is not operating, for example, when the ASIC is powered on, so the replacement target logical block cannot be changed during operation of the ASIC.
Due to the subdivided manufacturing processes for semiconductor integrated circuits, minute dust attached to ASICs during manufacture can be the cause of a failure. Due to the subdivided manufacturing processes, the degree of integration of transistors and wires in ASICs has been raised and minute dust, which could not be a problem in the conventional processes, can cause a failure in the ASICs.
Furthermore, some failures in ASICs may be caused due to the situation where although the ASICs are operating normally in the beginning, after power being applied for a while, a short or break in the wiring in the ASICs occurs. It is difficult to detect such age deterioration as the above only by a self-test function. For example, there may be some cases where no defect was found in a self-test but was found immediately after that. In that case, the result of the self-test is normal, but in fact a failure has occurred. Age deterioration may be found by performing self-test at regular time intervals; however, in order to enhance reliability, it has to be performed more frequently. However, the ASICs cannot perform normal operation during self-test, so they have to halt normal operation to enable their self-test functions. Moreover, when they halt normal operation, they have to store required information so that they can restart normal operation after the self-test.
Accordingly, frequent performance of self-test during ASIC operation may cause performance deterioration in ASICs. For example, the ASICs arranged in storage apparatuses are mainly in charge of data transfer and, if a self-test is performed during data transfer, performance deteriorates, i.e., transfer speed slows down. Consequently, the entire performance of the storage apparatuses degrades. To the storage apparatuses, data transfer speed is very important and any slow-down of the data transfer speed is a crucial matter. Accordingly, stopping the operation of ASICs to perform self-test is not realistic.
Also, because the self-test function is not perfect, some existing failures may be missed. For example, some failures occur only when data is transferred with special timing or when a special pattern is transferred, and the self-test function cannot detect those failures.
With the conventional techniques, a failure in an ASIC sometimes cannot be detected in advance and so a semiconductor integrated circuit device having that ASIC has to be stopped temporarily to replace the ASIC with a new one.
It is an object of the invention to provide: a semiconductor integrated circuit device capable of continuing its operation even when a failure is detected in its logical block(s) during the operation of a first large scale integrated circuit; and a storage apparatus systems including that semiconductor integrated circuit device.
Note that, in the embodiments described below, an ASIC serves as a first large scale integrated circuit and a FPGA serves as a programmable second large scale integrated circuit connected to the first large scale integrated circuit. However, the invention is not limited to this case and there is nothing wrong if an ASIC is a general purpose LSI (Large Scale Integrated circuit) and a FPGA is a CPLD (Complex Programmable Logic Device).
USPTO Backgrounds
USPTO Backgrounds