1. Field of the Invention
The present invention relates to the field of data processing and in certain preferred embodiments to the field of voltage level control.
2. Description of the Prior Art
Many data processing circuits burn power even when they are not doing anything, this is referred to as static power leakage. Static power leakage is a particular problem in circuits where the components are manufactured to be as small as possible. To reduce power leakage, many circuit designs are now making use of power gating which helps reduce power leakage during sleep mode. This power gating is achieved by inserting power transistors between any circuit element and Vdd creating a “virtual” Vdd rail, or by inserting power transistors between any circuit element and Vss creating a “virtual” Vss rail. These transistors are placed in series with the circuit either between the high voltage rail Vdd and the circuit or between the low voltage rail Vss (usually ground) and the circuit.
FIG. 1A shows an NMOS power transistor connected between the lower voltage rail Vss, usually ground and some circuitry. FIG. 1B shows an alternative where a PMOS power transistor is connected between the higher voltage rail Vdd and the circuitry. Generally during active mode the transistors of FIGS. 1A and 1B are turned on and they are conducting. Thus, almost the entire voltage difference Vdd−Vss falls across the circuitry. To enter a low leakage or sleep mode, the power transistors 10, 15 are turned off in response to a sleep signal and the leakage of the circuit is then limited by the leakage of the power transistors. Since the power transistors can be made to be high Vt (threshold voltage) or thick oxide devices, and since the width of the power transistors can be much less than the total width of the active devices in the design, leakage currents can be dramatically reduced. However, when the power transistors are turned off the virtual power rail at their output floats to approximately that of the other power rail and as a result of this a loss of state is experienced within the circuitry.
In order to overcome this problem, data retention circuitry such as data retention flops can be used within the design. A disadvantage of this is that such data retention components require circuit area and a redesign of any standard cell latches.
One other known way of addressing this problem is with the use of a diode placed in parallel with the power transistor. This diode is arranged such that when the power transistor is turned off, its output starts to float and when it reaches a value large enough to overcome the forward bias voltage of the diode, the diode starts to conduct, thus the voltage is clamped at the forward bias voltage of the diode. A drawback of this is that diodes only turn on at 0.7 V which may be too high a voltage to save data in some circuits.
Further data processing apparatus in this field are disclosed in http://www.imec.be/esscirc/ESSCIRC2002/presentations and http://konteret.webmaster.se/dockeeperfiles/340/998/DrazdziulisM.pdf
USPTO Backgrounds
USPTO Backgrounds