The present invention relates to an image sensor and a method for fabricating the same, and more particularly, to an image sensor fabricated by employing complementary metal-oxide semiconductor (CMOS) technology (hereinafter, referred to as CMOS image sensor) and a method for fabricating the same.
A CMOS image sensor includes two regions, of which one is a pixel region having a photodiode and the other is a logic circuit region having circuits for processing pixel signals. A substrate structure of the pixel region will be described hereafter. A photodiode is formed over a substrate, a plurality of insulation layers is formed over the photodiode in order to insulate layers therebetween and passivate a device. Furthermore, a color filter for absorbing a color and a micro lens for collecting light are formed over the plurality of the insulation layers.
Generally, when an amount of light incident on a photodiode in a pixel region is increased, light-sensitivity of an image sensor is improved. Thus, in order to improve characteristics of light-sensitivity, an area of a photodiode should be great or a focus length should be adjusted so as to focus the maximum amount of light on the photodiode. Furthermore, a distance from a photodiode to a micro lens should be decreased so as to decrease a loss of light to be incident on the photodiode.
However, since an area of a photodiode is decreased according to increasing of the number of pixels and a metal interconnection layer is formed of a multilayer, the thickness of an insulation layer over the photodiode is increased.
Therefore, a method for selectively etching an insulation layer in a pixel region has been employed in order to decrease a distance from a photodiode to a micro lens. That is, a mask pattern opening a pixel region and covering a logic circuit region has been used to merely etch an insulation layer in the pixel region.
A method for decreasing a distance from a micro lens to a photodiode by reducing unnecessary insulation layers over the photodiode is disclosed in U.S. Patent Application Publication No. 2006/0183265, entitled to “Image sensor having improved sensitivity and method for making same”.
However, when an insulation layer is selectively etched by using a selective etching process according to the prior art, a slope having a large angle of approximately 70 degrees is formed in an etching interfacial region after the etching process, wherein the term “etching interfacial region” represents an interfacial region between a pixel region and a logic circuit region.
FIG. 1 illustrates a cross-sectional view showing a slope of an etched insulation layer in an interfacial region between a pixel region and a logic circuit region. A photoresist pattern (PR) 120 opens the pixel region while covering the logic circuit region. An insulation layer 110 in the pixel region is etched to a given depth. At this time, although a slope etch process is performed in the interfacial region, an angle of a slope in the interfacial region becomes approximately 70 degrees.
In this matter, when an angle of a slope is as great as the above mentioned case, a subsequent color filtering layer is formed with bad uniformity. Furthermore, when in a color filtering process an exposure and developing process is used after applying a photoresist for the filtering, diffused reflection is remarkably often originated from a steep slope region during the exposure process, which badly affects a photo-lithography process as well.
In the meantime, a slop etching process may be performed by using dry etching conditions that generate much polymer during etching an insulation layer in order to decrease an angle of a slope. However, it is hard to get a desired angle which is decreased, as much as accomplishing smooth progress of subsequent processes and the generated much polymer becomes particles not to be easily removed in a subsequent cleaning process, so that characteristics of a device and a process yield may be deteriorated.
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