Monolithically integrated photonic circuits are useful as optical data links in applications such as, but not limited to, optical communications, high performance computing and data centers. For mobile computing platforms too, a PIC is a useful means of I/O to rapidly update or sync a mobile device with a host device and/or cloud service where a wireless link has insufficient bandwidth. Such optical links utilize an optical I/O interface that includes an optical transmitter and an optical receiver. One challenge with the optical I/O interface is coupling light between monolithically integrated photonic circuits, which are fabricated on a micrometer scale, and separately packaged components (e.g., optical fiber, etc.) which are assembled on the millimeter scale. A PIC may utilize vertical or edge-based optical I/O coupling techniques. The edge coupling technologies have a substantial drawback in that device testing requires an edge to be provided, typically by singulating the substrate upon which the PIC was fabricated into individual PIC chips. The vertical coupling technologies, while advantageously amenable to “wafer-level” PIC testing, typically have lower coupling efficiency than do the edge technologies. For example, a surface coupled PIC may have an emission efficiency in the range of about 50%.
Another limitation with vertical coupling techniques is that the presence of optical I/O on a top side of the PIC is generally incompatible with advanced flip-chip or controlled collapse (C4) packaging techniques in which the top side of an IC is affixed to a package substrate (e.g., by bumps and solder balls). For such flip-chip techniques, it is difficult to provide a package substrate that doesn't occlude the vertical optical coupling.
As such, a vertical coupling technique that offers improved coupling efficiency and is amendable to flip-chip packaging would be highly advantageous in the provision of PICs, such as optical transmitters.
USPTO Backgrounds
USPTO Backgrounds