1. Field of the Invention
The invention relates to a structure of an electrostatic discharge (ESD) protective circuit for SRAM, and in particular to a structure of an electrostatic discharge protective circuit, which is formed on the bottom of a bonding pad and provides a large drain node for SRAM.
2. Description of the Related Art
In the IC process, an electrostatic discharge is a main factor to cause IC damage. In other words, the problem of the electrostatic discharge always leads to sub-micron IC breakdown. In order to overcome the above-mentioned problem, on-chip electrostatic discharge protective circuits are used to dispose on input/output bonding pads of a CMOS IC. However, the protective function of the electrostatic discharge protective circuits is seriously declined in line with the development of the IC process. Consequently, how to efficiently enhance the function of electrostatic discharge protective circuits is urgently expected by semiconductor industry.
SRAM is a memory with a highest operation speed in all current memories, and widely applied, for example, in computer data accesses, microcomputers and microprocessors. Therefore, the structure of electrostatic discharge protective circuits used in SRAM urgently needs to be improved.
Referring to FIG. 1A, electrostatic charges inputted to an input port INP are discharged to ground V.sub.ss via an N-type MOS transistor N1, thereby protecting an internal circuit 10. Referring to FIG. 1B, electrostatic charges inputted to an input port INP are discharged to ground V.sub.ss via an N-type MOS transistor N1 or to a voltage source V.sub.DD via a P-type MOS transistor, thereby protecting an internal circuit 10.
Referring to FIG. 2, a MOS transistor N1 includes a substrate 20, a drain 22 coupled to an internal line I/P by a first via 24, a source 26 coupled to ground V.sub.ss by a second via 28. In addition, a gate 29 is positioned between the source 26 and the drain 22.
Furthermore, referring to FIG. 3, a metal bonding pad 30 is formed on the input line I/P. FIG. 2 is a cross-sectional view along line I-I' of FIG. 3. In FIG. 3, reference numbers 24 and 28 designate a first via 24 and a second via 28; and reference number 29 designates a gate. The source 26 and the gate 29 all are coupled to ground Vss. The drain 22 is coupled to the input line I/P. The input line I/P is coupled to the metal bonding pad 30.
To the structure of an electrostatic discharge protective circuit, the capability of electrostatic discharge depends on the sizes of drain nodes, the number of nodes, the pitches between nodes and gates and the thickness of conductors which determine whether or not heat dissipation is completed in a short time. As can be known from FIG. 3, metal connections for drain and source regions are finger-shaped. Due to small areas of the metal connections, power consumption is unstable. Furthermore, since the metal connections are finger-shaped, the structure of an electrostatic discharge protective circuit is unable to be formed on the bottom of a bonding pad to efficiently reduce the use area of SRAM; source is unable to directly connect to gate; and the layout of the structure of an electrostatic discharge protective circuit for SRAM needs additional metal connections. Furthermore, due to the small areas of drains, a large number of nodes, short pitches between nodes and gates and thin conductors, the heat dissipation of the structure is poor.
USPTO Backgrounds
USPTO Backgrounds