1. Field of the Invention
The present invention relates to an apparatus of the fabrication of integrated circuits, and the present invention especially relates to an apparatus of the fabrication of integrated circuits which is capable of reducing gate oxide damage in a high density plasma chemical vapor deposition process to which a bi-polar electrostatic chuck is applied.
2. Description of the Prior Art
After the fabrication of the active device of a MOS (metal-oxide semiconductor) device is accomplished, the following work is to proceed the fabrication of the multilevel interconnects above the MOS device. As the process technology progresses and scales of MOS devices get more and more smaller, gaps between metal conductors also become more and more narrower. Accordingly, gaps of high aspect ratio between metal conductors are formed. The gaps of high aspect ration will let the deposition of dielectric layers become incomplete and form voids in the dielectric layers. These voids in the dielectric layers will damage electric properties of MOS devices and lead to scraped wafers.
In order to solve the problem of the incomplete deposition of dielectric layers, a HDPCVD (high density plasma chemical vapor deposition) process is proposed to deposit dielectric layers between metal conductors in U.S. Pat. No. 6,239,018 and U.S. Pat. No. 6,218,284. The detailed description of a HDPCVD process is also contained in U.S. Pat. No. 6,117,345. The main reason a HDPCVD process can solve the problem of the incomplete deposition of dielectric layers is that a HDPCVD process is capable of both proceeding chemical vapor deposition process and anisotropic etching process. As shown in FIG. 1A, the etching function results from the following steps: an AC (alternating current) plasma generating source 12 of the HDPCVD equipment 10 generates plasma 16, the voltage potential difference between the plasma 16 and the electrostatic chuck 20 attracts the ions of the plasma 16 to bombard the wafer 18. The ions of the plasma 16 will anisotropically etch the excess dielectric layers above the metal conductors of MOS devices to deposit void-free dielectric layers. Because the voltage potential difference between the plasma 16 and the electrostatic chuck 20 distributes non-uniformly in the process of ion-bombardment on the wafer 18, currents are produced on the wafer 18 surface. If the voltage potential difference between the plasma 16 and the electrostatic chuck 20 distributes extremely non-uniformly, the produced currents will damage gate oxides of MOS devices.
The non-uniform distribution of the voltage potential difference between the plasma 16 and the electrostatic chuck 20 possibly results from the non-uniform distribution of the voltage potential on the electrostatic chuck 20. In HDPCVD equipment, the type of an electrostatic chuck 20 includes mono-polar and bi-polar. The electrostatic chuck 20 secures the wafer 18 by means of the electrostatic force. If the electrostatic chuck 20 has only one electrode, the distribution of the voltage potential on the electrostatic chuck 20 can be deemed uniform distribution and will not cause the aforementioned non-uniform distribution of the voltage potential difference between the plasma 16 and the electrostatic chuck 20. However, the electrostatic chuck 20 of the mono-polar type does not have a discharging circuit. When the HDPCVD process is over, the wafer 18 cannot be moved until the electric particles in the plasma 16 neutralize the inductive electric particles on the wafer 18. The neutralization process delays the throughput of mass production and if the wafer 18 is moved before the neutralization process is completed, the wafer 18 may be broken into fragments.
A bi-polar electrostatic chuck 201 is as shown in FIG. 1B. If a bi-polar electrostatic chuck 201 is used in the HDPCVD process, after the HDPCVD process is over, the electrostatic force on the wafer 18 will be removed more rapidly by virtue of the discharging circuit created by the double electrodes. The discharging circuit created by the double electrodes can avoid delaying the throughput of mass production and prevent the wafer 18 from being broken into fragments. However, as shown in FIG. 1C, the AC bias source 22 of producing ion-bombardment also connects to the inner electrode 28 and outer electrode 30 of the bi-polar electrostatic chuck 201 to produce the voltage potential difference between the plasma 16 and the bi-polar electrostatic chuck 201. Accordingly in the process of the transmission of high frequency AC currents, the inner electrode 28 power output always differs from the outer electrode 30 power output because of the impedance difference of the transmitting lines between the inner electrode 28 and the outer electrode 30 causing the non-uniform voltage potential distribution on the bi-polar electrostatic chuck 201. As shown in FIG. 2A, after ions bombard the inner side and outer side of the wafer 18, different voltage potential on the wafer 18 will be generated to produce surface currents on the wafer 18. As shown in FIG. 2B, the surface currents on the wafer 18 will cause the accumulated electric particles on the conductive polysilicon layer 36. The gate oxide 38 on the silicon substrate 40 will be damaged by the accumulated electric particles passing through the gate oxide 38.
In order to solve the problem of the gate oxide damage, process steps are added to change the structure of the MOS device in the U.S. Pat. No. 5,913,140 and U.S. Pat. No. 5,843,827. However, the problem of the non-uniform voltage potential difference between the plasma 16 and the bi-polar electrostatic chuck 201 is not mentioned in these patents. Accordingly, how to avoid the non-uniform voltage potential difference between the plasma 16 and the bi-polar electrostatic chuck 201 is an important issue to be solved.
USPTO Backgrounds
USPTO Backgrounds