1. Field of the Invention
The present invention relates to a gate array integrated circuit device incorporating memories. More particularly, it relates to a gate array integrated circuit device and a method of production which can realize various bit/word constructions according to customer requests.
2. Description of the Related Art
A gate array integrated circuit device is a semicustom LSI comprising a semiconductor chip which is prepared in advance by forming a number of basic cells in an array on the semiconductor chip. These basic cells, such as the basic cells disclosed in Japanese patent application publication No. 54-93375, form a basic unit of a logic circuit. For a semicustom LSI, when a customer requests a certain circuit, only the wiring between the basic cells need be changed, thereby enabling various logic circuit LSIs to be supplied with little delay.
When an arithmetic circuit such as an ALU is prepared from such a gate array integrated circuit device, a memory circuit is needed in addition to the logic circuit. One method of realizing the memory in the gate array integrated circuit includes forming the memory by combining basic cells. However, many basic cells are necessary for forming the memory so that the service efficiency of the basic cells is deteriorated, and the memory area tends to increase.
To cope with the above problem, there has been proposed a gate array integrated circuit device in which a basic cell array and a memory exclusive region are provided together on the same semiconductor chip.
However, it is difficult for the prior art gate array integrated circuit device mentioned above to form a plurality of memories having different bit/word constructions, because the bit/word constructions of a memory cell matrix M of the prior art device is fixed. Supposing a memory cell matrix M of 16 words.times.32 bits is prepared in advance. In this case, a memory such as a memory of 16 words.times.24 bits, in which a word is less than 32 bits, may be formed without using a part of the memory cell matrix M. However, if a memory of 16 words.times.24 bits and a memory of 16 words.times.8 bits are required, one of the memories will be formed by using the memory cell matrix M with all the address register AB, word decoder DEC, and clock buffer CB so that the other memory is formed by combining many of the basic cells BC.
As mentioned above, the prior art gate array integrated circuit device cannot completely realize a memory having a bit/word construction satisfying the requirement of a customer, even if a memory exclusive region is provided therewith.
USPTO Backgrounds
USPTO Backgrounds