Memory controllers communicate signals containing data, addresses or commands, to one or more memory devices through signal lines. For the command/address signal lines, many memory systems (such as double-data-rate memory systems) use a daisy-chain or a fly-by topology, in which memory devices are coupled in parallel to multiple signal lines that are each terminated by a corresponding termination impedance. When communicating signals on a given command/address signal line in these memory systems, a separate termination voltage is often applied to the termination impedance (this is sometimes referred to as ‘stub series terminated logic’ or SSTL). This separate termination voltage is used because multiple memory devices share the given command/address signal line, and the impedances of these memory devices, which are coupled in parallel with the termination impedance, can modify the effective impedance of the given command/address signal line and, thus, the communicated electrical signals. Typically, the termination voltages are provided by an additional voltage regulator, which increases the cost of these memory systems.
USPTO Backgrounds
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