A phase-locked loop or phase lock loop (PLL) is a negative feedback control system where an oscillator-generated signal is phase and frequency locked to an input reference signal. Embodiments comprise an electronic circuit including a phase detector, a charge pump, a filter including an integral capacitor C1 and a resistor R1, and a variable frequency oscillator. The phase detector compares the phase of the input reference signal with the phase of the signal derived from the output of the oscillator and generates an error signal. The charge pump converts the error signal to an error current and the integral capacitor C1 and the resistor R1 act upon the error current to generate an oscillator control voltage. The integral capacitor C1 integrates the error current (integral path) to set an average oscillator frequency and the resistor R1 provides instantaneous phase correction (proportional path). The oscillator control voltage adjusts the frequency of the oscillator to keep the phases matched.
Stability is one of the important issues in designing a phase lock loop. The damping factor, a measure of the overshoot and ringing in the output of the PLL, is shown in equation 1 and the open loop bandwidth, the frequency at which the loop gain equals one, is shown in equation 2.
                    ζ        =                                            R              1                        2                    ⁢                                                                      K                  cp                                ⁢                                  K                  vco                                ⁢                                  C                  1                                            N                                                          Equation        ⁢                                  ⁢        1            
                              f          u                =                                            K              cp                        ⁢                          K              vco                        ⁢                          R              1                                            2            ⁢            π            ⁢                                                  ⁢            N                                              Equation        ⁢                                  ⁢        2            
While several factors can be increased to improve the damping factor, increasing the capacitance C1 of the integral capacitor increases the stability without affecting the bandwidth. In many low bandwidth phase lock loop embodiments, a large capacitor, up to several nanofarads (nF) for example, can be used to achieve an acceptable damping factor. However, it is very difficult to integrate a large capacitor on an integrated circuit (IC). Capacitance multiplication is used to achieve an acceptable damping factor with a smaller capacitor.
Embodiments of PLLs with capacitance multiplying use a dual path loop filter comprising an integral charge pump and a proportional charge pump. The integral charge pump generates an amount of charge based on the integration of the error signal from the phase detector to the integral capacitor C1, and similarly, the proportional charge pump generates a proportional amount of charge based on the error signal from the phase detector to the resistor R1. The outputs of the integral and proportional charge pumps are added and the resulting voltage is applied to a voltage controlled oscillator (VCO). The current of the proportional charge pump is usually several times that of the integrator charge pump. When the current of the proportional charge pump is N times that of the integral charge pump, it takes N times the time for the integral capacitor C1 to accumulate a certain amount charge, making it appear that the capacitance of the integral capacitor C1 is multiplied by a factor of N.
However, such embodiments use two charge pumps to employ capacitance multiplication. The second charge pump uses additional IC area, and results in increased power consumption and increased costs. Further, due to mismatches between the two charge pumps, the capacitance multiplication factor, and thus, the PLL damping factor cannot be precisely controlled. Further yet, the second charge pump will contribute additional noise to the PLL circuit.
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