1. Field of the Invention
This present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to various methods of forming conductive through-wafer vias.
2. Description of the Related Art
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked transistors. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
As integrated circuit technology progresses, there is a growing desire for a “system on a chip.” Ideally, a computing system would be fabricated with all the necessary integrated circuits on one wafer, as compared with today's method of fabricating many chips of different functions and packaging them to assemble a complete system. Such a structure would greatly improve integrated circuit performance and provide higher bandwidth. In practice, it is very difficult with today's technology to implement a truly high-performance “system on a chip” because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. Thus, what is needed is an improved method and structure which continues to approach the ideal set-up of a “system on a chip” and thus improves the integration of different chips in an integrated circuit.
As a result, there are economic advantages associated with forming a module or system from an interconnected group of different types of previously-tested integrated circuits (i.e., known good die). Further advantages can result from mounting the different types of integrated circuits in die form on a common substrate and then encapsulating the composite assembly in a package common to all of the die to form a module, known as a multichip module or MCM. In MCMs, the die are interconnected to wiring formed on the common substrate, also known as an interposer, using conventional interconnection technology.
As the area of each die in an MCM increases, a mismatch between the thermal coefficient of expansion of the die and the interposer becomes increasingly critical, at least in part because the thickness of the material forming the die is not increased as the area of the die is increased. One solution to this problem is to make the interposer from the same material that the die are made from, e.g., silicon. This allows increasingly complex integrated circuits to be interconnected without exaggerating thermal coefficient of expansion mismatch problems that could occur either during packaging or as a result of thermal cycling in normal use. Additionally, passive components may be formed or mounted on the interposer.
FIG. 1 is a simplistic, cross-sectional view of an illustrative prior art packaging assembly 11. As shown therein, a silicon interposer 10 is positioned within an integrated circuit package 13. An insulating layer 10A is formed on the exposed surfaces of the silicon interposer 10. A plurality of metal connectors 17 are formed on the interposer 10. A plurality of conductive contacts 12 extend through openings formed in the interposer 10. The interconnects 17 on the package 13 may be coupled to the interconnects 17 on the interposer 10 by, for example, a wire bond 19. A plurality of integrated circuit devices 15A, 15B, 15C may be operatively coupled to one another via the interconnects 17 formed on the interposer 10. For example, the integrated circuits 15A, 15B and 15C may be, respectively, a microprocessor, a capacitor and a memory device (e.g., a DRAM, an SRAM, etc.).
One illustrative prior art technique for forming such through-hole contacts will now be described with reference to FIGS. 2A-2D. As shown in FIG. 2A, a plurality of openings 22 are formed in a semiconducting substrate 20, such as silicon. The openings 22 may be formed using known photolithography and etching processes. Next, a layer of insulating material 21 may be formed on the exposed surfaces of the substrate 20. The layer 21 may be formed by a thermal oxidation process or a chemical vapor deposition process. Thereafter, if desired, a barrier metal layer, such as tantalum, may be formed above the layer of insulating material 21 and in the openings 22. For purposes of clarity, the barrier metal layer is omitted from the referenced figures.
The next process involves the formation of a seed layer 24, e.g., a copper seed layer. The copper seed layer 24 may be conformally formed on the substrate 20 and in the openings 22. The copper seed layer 24 may have a thickness of approximately 20-100 nm, and it may be formed by, for example, a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. Thereafter, an electrical (electroplating) or chemical (electroless) process may be performed to deposit the bulk copper layer 26 above the substrate 20 and in the openings 22, as indicated in FIG. 2C. Then, one or more chemical mechanical polishing (CMP) operations are performed to remove the excess bulk copper layer 26, thereby leaving the through-hole contacts 25 in the openings 22, as shown in FIG. 2D. Additional processing operations may be performed to couple one or more integrated circuit devices, e.g., memory devices, logic devices, etc., to the desired contacts 25.
The above-referenced process flow may be problematic in many respects for future technologies. For example, the aspect ratio of the openings 22 will tend to increase in future generation products. As a result, the conformal deposition of the copper seed layer 24 may be more difficult to achieve. Such difficulties may lead to the formation of voids in the contacts 25, all of which will reduce the efficiency of the contacts 25.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
USPTO Backgrounds
USPTO Backgrounds