1. Field of the Invention
The present invention relates to a circuit which generates a clock signal serving as a basic signal of circuit operations, and more particularly to a clock switch circuit capable of switching the frequency of a clock signal by selecting a desired frequency from among a plurality of frequencies which can be set.
A reduction in the operation speed of a circuit of an information processing apparatus contributes to decreasing power consumed in the circuit. Such a reduction in the operation speed can be achieved by decreasing the frequency of the clock signal which operates the circuit. A clock switch circuit is used to select a clock signal having a desired frequency from among predetermined clock signals having mutually different frequencies.
2. Description of the Related Art
FIG. 1 illustrates a first conventional clock switch circuit, which is made up of a clock generating circuit 51, a setting register 52 and a selector 53. The clock generating circuit 51 generates clock signals CLK0-CLK3 of different frequencies, which are applied to the selector 53. The setting register 52 stores n-bit data, which has a value corresponding to the target clock frequency. The selector 53 selects the clock signal of the target frequency indicated by the n-bit data stored in the setting register 52 from among the clock signals CLK0-CLK3.
Since the clock generating circuit 51 used in the configuration shown in FIG. 1 generates four clock signals CLK0-CLK3, the setting register 52 stores 2-bit data.
FIG. 2 is a time chart of the operation of the first conventional clock switching circuit shown in FIG. 6. A switching operation will be described in which the clock signal is switched from CLK1 to CLK2 and from CLK2 to CLK1.
As long as the 2-bit data stored in the setting register 52 indicates "00" corresponding to the clock signal CLK1, the selector 53 continues to select the clock signal CLK1. A request to switch the clock signal is issued by, for example, the user or a CPU (not shown). If a request to change the clock signal from CLK1 to CLK2 is issued, 2-bit data "01" corresponding to CLK2 is written into the setting register 52. Hence, the selector 53 selects the clock signal CLK2 in response to the change of the 2-bit data stored in the setting register 52.
If a request to return the clock signal from CLK2 to CLK1 is issued, the 2-bit data stored in the setting register 52 is changed to "00" from "01".
The configuration shown in FIG. 1 switches the clock signal at the moment the value of the 2-bit data stored in the setting register 52 is changed. Hence, a hazard may be superimposed on the output signal of the selector 53 when the 2-bit data registered in the setting register 52 is changed, and a circuit which responds to the output signal of the selector 53 may malfunction. For example, if the 2-bit data stored in the setting register 52 is changed to the value corresponding to the target clock signal immediately before the pulse of the above target clock signal falls, a pulse (hazard) having a very short duration will be superimposed on the clock signal selected by the selector 53, as shown in FIG. 2.
There is another problem in the conventional configuration shown in FIG. 1. If an increased number of selectable clock signals is prepared, the clock generating circuit 51 is required to have a larger circuit size. Further, the selector 53 will be required to have a larger size and a complex configuration.
In order to avoid the above-mentioned problems, an improved clock switch circuit capable of generating a desired clock frequency has been proposed in which the pulse of a master clock signal of a constant frequency is extracted each time a given time passes.
FIG. 3 illustrates such an improved clock switch circuit as a second conventional clock switch circuit. The circuit shown in FIG. 3 is made up of a master clock generating circuit 61, a counter 62, a setting register 63 and an AND circuit 64. The master clock generating circuit 61 generates a master clock signal of a given constant frequency. The counter 62 counts the pulses of the master clock signal generated by the master clock generating circuit 61. A value corresponding to the desired clock frequency is stored in the setting register 63. The counter 62 counts the pulses until the number of pulses becomes equal to the value stored in the setting register 63. When the counter 62 counts the number of pulses indicated by the value stored in the setting register 63, the counter 62 outputs a carry signal. The AND circuit 64 performs an AND operation on the carry signal and the clock pulse generated by the master clock generating circuit 61.
Hence, the clock switch circuit shown in FIG. 3 extracts the pulses output by the master clock generating circuit 61 at given intervals based on the value stored in the setting register 63, so that the clock signal having the desired frequency can be generated.
In the configuration shown in FIG. 3, it is enough to generate only one clock signal (master clock signal) of the given constant frequency. Hence, down sizing of the clock switch circuit is achieved. The timing at which the clock signal is switched does not depend on the timing at which the value stored in the setting register 63 is rewritten but is synchronized with the master clock signal.
However, as shown in FIG. 4, the rising and falling edges of the carry signal output by the counter 62 slightly lags behind the rising edges of the pulses of the master clock signal. Hence, the pulses extracted have a slightly reduced width. Further, the pulses to be decimated overlap the carry signal for a very short time. Hence, hazards occur as shown in FIG. 4 even using the improved configuration shown in FIG. 3.
USPTO Backgrounds
USPTO Backgrounds