1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for driving the same, and a camera. More specifically, the present invention relates to a solid-state imaging device which uses a MOS-type image sensor or the like, and used in, for example, a video camera, an electron camera and an image input camera, a scanner, a facsimile machine, or the like, a method for driving the same, and a camera using such a solid-state image sensing device.
2. Description of the Related Arts
Conventionally, a semiconductor image sensor such as a CCD type image sensor, a MOS-type image sensor and the like have been used as image input devices in various electronic devices, such as, a video camera, an electron camera, an image input camera, a scanner, a facsimile machine, or the like.
In recent years, a MOS-type image sensor has been drawing attention once again because of its benefits. The power consumption is low, and it can be produced using a CMOS technique which is the same an that for the surrounding circuits. Further, in order to compensate for lower image quality than that of the CCD-type image sensor, it is becoming popular to employ a structure called an embedded-type photodiode structure. This is used in a MOS-type image sensor instead of a surface photodiode structure which had been initially used. The embedded-type photodiode structure is the structure used in a CCD-type image sensor. Such a structure is employed to reduce a dark current component and it is becoming possible to achieve a high-quality image.
Hereinafter, a conventional MOS-type image sensor employing such an embedded-type photodiode structure will be described with reference to FIGS. 12 through 14,
First, a structure of a unit pixel of a MOS-type image sensor will be described with reference to FIGS. 12 and 13.
FIG. 12 is a circuit diagram showing a structure of a unit pixel portion (address (k, j)) in a conventional MOS-type image sensor 200. FIG. 13 is a cross-sectional view showing a semiconductor layer structure which corresponds to the unit pixel portion in FIG. 12.
The MOS-type image sensor 200 includes an imaging section containing a plurality of unit pixel portions (pixel cells), and a vertically scanning circuit 207 for vertically scanning the plurality of unit pixel portions. Each of the unit pixels includes a photodiode 201, a transfer transistor 202, a signal storage section 203, a reset transistor 204, an amplification transistor 205, and a selection transistor 206.
Each of the unit pixel portions includes four transistors (i.e., the transfer transistor 202, the reset transistor 204, the amplification transistor 205, and the selection transistor 206). A plurality of the unit pixel portions are arranged along a row direction and a column direction in two dimensions. FIG. 12 shows only one of the plurality of unit pixels, which is specified by address (k, j).
As shown in FIG. 13, the photodiode 201 has an embedded-type structure. The photodiode 201 includes an N-type (N−) impurity region 221 provided on a P-type well region 220 with a P-type impurity region 222 provided on the N-type impurity region 221. The N-type (N−) impurity region 221 serves as a light receiving portion. By irradiating the N-type impurity region 221 with light, a charge is generated in an amount corresponding to an amount of the irradiation of light. Such a charge may also be referred to as a signal charge herein.
The transfer transistor 202 is provided between the photodiode 201 and the signal storage section 203. The transfer transistor 202 includes the N-type impurity region 221, which serves as a source region, an N-type (N+) impurity region 223a, which serves as a drain region, and a gate electrode 202a which to provided on the P-type well region 220 therebetween.
The gate electrode 202a is connected with a transfer control line 210 which is connected to an output terminal of the vertically scanning circuit 207. From the vertically scanning circuit 207, a transfer control signal TRN (j) is supplied to the gate electrode 202a. In the entire imaging section, the transfer transistors 202 are controlled to be ON/OFF on a row basis. The transfer transistor 202 transfers a charge stored in the photodiode 201 to the signal storage section 203.
The signal storage section 203 is the N-type impurity region 223a of a floating diffusion layer which is provided on the P-type well region 220. The signal storage section 203 stores a signal charge from the photodiode 201 which is transferred by the transfer transistor 202.
The reset transistor 204 is provided between a power supply line 213 and the signal storage section 203. To the power supply line 213, a power supply voltage VDD is applied. The reset transistor 204 includes the N-type impurity region 223a, which serves as a source region, an N-type (N+) impurity region 223b, which serves as a drain region, and a gate electrode 204a which is provided on the P-type well region 220 therebetween.
The gate electrode 204a is connected with a reset control line 209 which is connected to an output terminal of the vertically scanning circuit 207. Prom the vertically scanning circuit 207, a reset control signal RST (j) is supplied to the gate electrode 204a. In the entire imaging section, the reset transistors 204 are controlled to be ON/OFF on a row basis. The reset transistor 204 resets the signal storage section 203.
The amplification transistor 205 is provided between the power supply line 213 and the selection transistor 206. The amplification transistor 205 includes the N-type impurity region 223b, which serves as a drain region, an N-type (N+) impurity region 223c, which serves as a source region, and a gate electrode 205a which in provided on the P-type well region 220 therebetween.
The gate electrode 205a is connected to the signal storage section 203, which is the N-type impurity region 223a. Thus, a potential that is the same as that of the signal storage section 203 in conveyed to the gate of the amplification transistor 205. The amplification transistor 205 outputs a signal corresponding to an amount of a charge stored in the signal storage section 203.
The selection transistor 206 is provided between a signal line (k) 211 and the amplification transistor 205. The signal line (k) 211 is connected to a constant-current source 212 and a signal is read out therethrough. The selection transistor 206 includes the N-type impurity region 223a, which serves as a drain region, an N-type (N+) impurity region 223d, which serves as a source region, and a gate electrode 206a which is provided on the P-type well region 220 therebetween.
The gate electrode 206a of the selection transistor 206 is connected with a vertical selection line 208 which is connected to the output terminal of the vertically scanning circuit 207. From the vertically scanning circuit 207, a vertical selection signal SEL (j) is supplied to the gate electrode 206a. In the entire imaging section, the selection transistors 206 are controlled to be ON/OFF on a row basis. In the entire imaging section, the unit pixels are selected on a row basis, based on the vertical selection signal SEL (j) applied to the selection transistor 206. A signal is read out through the signal line (k) 211.
In such a MOS-type image sensor 200, the transfer transistor 202 and the reset transistor 204 are often a depletion type transistor, and the amplification transistor 205 and the selection transistor 206 are often an enhancement type transistor.
Next, a method for driving the conventional MOS-type image sensor 200 having a structure as shown in FIGS. 12 and 13 will be described.
FIG. 14 is a signal waveform diagram showing timings to drive the MOS-type image sensor 200.
A basic operation for reading out a signal corresponding to a charge stored in the photodiode 201 of the MOS-type image sensor 200 is as follows.
As shown in FIG. 14, during time period t1, the reset control signal RST (j) to be applied to the gate electrode 204a of the reset transistor 204 is raised to a high level for all the unit pixel portions of selected line j to turn on the reset transistor 204. Thus, a potential of the signal storage section 203 is reset to the power supply voltage VDD via the reset transistor 204.
Next, during time period t2, the vertical selection signal SEL (j) to be applied to the gate electrode 206a of the selection transistor 206 is raised to the high level to turn on the selection transistor 206. Thus, the amplification transistor 205 and the constant-current source 212 provided for every column (k) form a source follower circuit. A signal is output to the signal line (k). The signal which is output represents a signal corresponding to an amount of a charge stored in the signal storage section 203 which has been reset.
Further, during time period t3, the transfer control signal TRN (j) to be applied to the gate electrode 202a of the transfer transistor 202 is raised to the high level to turn on the transfer transistor 202. Thus, a charge corresponding to a light signal which is photoelectrically converted by the photodiode 201 is completely transferred to the signal storage section 203 via the transfer transistor 202.
Immediately after, during time period t4, the vertical selection signal SEL (j) to be applied to the gate electrode 206a of the selection transistor 206 is again raised to the high level to turn on the selection transistor 206. Thus, the amplification transistor 205 and the constant-current source 212 provided for every column (k) form a source follower circuit. A signal is output to the signal line (k). The signal which is output represents a signal corresponding to an amount of a charge corresponding to the light signal.
Then, a clamp circuit, a differential amplification circuit, or the like (not shown) are used to detect a difference between the signal corresponding to the amount of the charge and the signal, upon the reset. By utilizing the detected results, variances in offsets of transistors among the pixels can be cancelled out. Further, since the light signal can be completely transferred from the photodiode 201 to the signal storage section 203, no random noise is generated and a high quality image can be obtained.
In this example, the reset signal RST (j), the vertical selection signal SEL (j), and the transfer control signal TRN (j) are pulse signals having a binary level of the power supply voltage VDD and the ground voltage GND. In general, these signals are supplied from the vertically scanning circuit 207 located around the imaging section.
In the conventional MOS-type image sensor 200 having the embedded-type photodiode structure as shown in FIGS. 12 and 13, four transistors are required for each unit pixel. In the MOS-type image sensor employing the conventional surface photodiode structure, three transistors are required for each unit pixel. Thus, the number of transistors increases by one by employing the embedded-type photodiode structure. This means that the size of the photodiode is reduced by the size of one transistor in each unit pixel. This results in a decrease in the sensitivity.
In order to solve such a problem of the decrease in the sensitivity due to the increase of the transistors, Japanese Laid-Open Publication No. 11-355668, for example, proposes a structure having three transistors for each unit pixel.
Now, the structure of the MOS-type image sensor disclosed in Japanese Laid-Open Publication No. 11-355668 will be described.
First, a structure of a unit pixel of the MOS-type image sensor will be described with reference to FIGS. 15 and 16.
FIG. 15 in a circuit diagram showing a structure of two unit pixel portions in a conventional MOS-type image sensor 300 disclosed in Japanese Laid-Open Publication No. 11-355668. These unit pixel portion, are specified by address (k, j) and (k, j+1). FIG. 16 is a croon-sectional view showing a semiconductor layer structure which corresponds to one of the unit pixel portions in FIG. 15.
As shown in FIG. 15, the MOS-type image sensor 300 includes an imaging section containing a plurality of unit pixel portions (pixel cells) and a vertically scanning circuit 307. The vertically scanning circuit 307 vertically scans the unit pixel portions. Each unit pixel portion includes one embedded-type photodiode 301, a transfer transistor 302, a signal storage section 303, a reset transistor 304, and an amplification transistor 305. In the MOS-type image sensor 300, each unit pixel portion includes three transistors (i.e., the transfer transistor 302, the reset transistor 304, and the amplification transistor 305). A plurality of the unit pixel portions are arranged along a row direction and a column direction in two dimensions.
The MOS-type image sensor 300 disclosed in the Japanese Laid-Open Publication No. 11-355668 is different from the conventional MOS-type image sensor 200 shown in FIGS. 12 and 13 on the following points.
An N-type (N+) impurity region 323e serves as a drain region of the reset transistor 304. An N-type (N+) impurity region 323f serves as a drain region of the amplification transistor 305. Between the N-type impurity region 323e and the N-type impurity region 323f, a P-type (P+) impurity region 322a is provided to separate them from each other. A drain voltage of the reset transistor 304 is controlled by a vertical selection signal SEL (j) supplied from the vertically scanning circuit 307.
Further, in the MOS-type image sensor 300, the selection transistor 206 shown in FIG. 12 is not provided. An N-type (N+) impurity region 323g, which serves as a source region of the amplification transistor 305, is directly connected with a signal line 311.
The reset transistor 304 is of the depletion type, and the transfer transistor 302 and the amplification transistor 305 are of the enhancement type.
Next, a method for driving the MOS-type image sensor 300 disclosed in Japanese Laid-Open Publication No. 11-355668 will be described.
FIGS. 17A and 17B are signal waveform diagrams showing timings to drive the MOS-type image sensor 300. FIG. 17A shows a signal waveform at line j. FIG. 17B shows a signal waveform at line j+1.
As shown in FIGS. 17A and 17B, for the selected line J, through which a signal is output, the same operation as that for the selected line in the MOS-type image sensor 200 shown in FIG. 12 is performed.
On the other hand, at a non-selected line, when the drain voltage of the reset transistor 304 is maintained at a low level, for example, 0V, the depletion-type reset transistor 304 fixes a potential at the signal storage section 303, to the 0V level. The signal storage section 303 is connected to a gate electrode 305a of the amplification transistor 305. Thus, the gate voltage of the amplification transistor 305 becomes 0V, and the drain and the source of the amplification transistor 305 at the non-selected line are blocked.
Therefore, in the entire imaging section, the drain voltages of the react transistors 304 can be controlled on a row basis to allow the gate voltages of the amplification transistors 305 at the non-selected line to be controlled. For example, as described above, a line, for which the drain voltage of the reset transistor 304 is set to 0V, becomes a non-selected line which is not is operated. As a result, it is not necessary to provide the selection transistor 206 (see FIG. 12) which has been required conventionally.
As described above, in the conventional MOS-type image sensor 200 having the embedded-type photodiode structure as shown in FIGS. 12 and 13, an amount of a dark current is small. However, four transistors are required for each pixel, thereby causing a problem of a decrease in sensitivity due to a reduction in the size of the photodiode area. Therefore, in the MOS-type image sensor 200, there is a trade-off between the suppression of the dark current and the decrease in sensitivity.
As disclosed in Japanese Laid-Open Publication No. 11-355668, the MOS-type image sensor 300 including three unit pixel portions has been proposed. By comparing the MOS-type image sensor 200 (FIG. 13) and the MOS-type image sensor 300 (FIG. 16), it is apparent that, the number of transistors is reduced by one, more specifically, the selection transistor 306 is omitted in the MOS-type image sensor 300. However, the P-type impurity region 322a is required as a drain separation region for separating the power supply voltage VDD of the unit pixel portion and a drain voltage of the reset transistor 304. Thus, the size of the area is not reduced.
USPTO Backgrounds
USPTO Backgrounds