Goals for integrated circuit design include scaling the design to achieve smaller feature sizes, and using progressively faster clock frequencies. Problems encountered in achieving these goals include increasing voltage droop and inductive noise of active switching nodes, and further include increasing power supply oscillations and the resulting noise that is generated and transmitted across the chip.
These problems are addressed by incorporating on-chip decoupling capacitors into integrated circuit design. Many digital circuits or modules use a decoupling capacitor to reduce electrical noise. On-chip decoupling capacitors provide a uniform power supply voltage to fast switching nodes and offset the voltage droops caused by resistive and inductive losses in the integrated circuit load. Capacitors currently used for that purpose use a large amount of chip area or add topography by stacking capacitor layers on top of each other. This additional area used for decoupling can negatively impact chip cost and circuit operational performance. Improved decoupling capacitors and methods are needed.
USPTO Backgrounds
USPTO Backgrounds