1. Field of the Invention
This invention relates to a composite semiconductor device which constitutes a DC-DC converter or the like that is installed in portable electrical equipment or the like. More particularly, this invention relates to a composite semiconductor device of a small-sized-type and a thin-type, in which a thin-type capacitor or the like is stacked on a semiconductor substrate (semiconductor chip) formed with an integrated circuit (IC).
2. Background of the Related Art
A DC-DC converter which is used in portable electronic equipment exemplified by a portable telephone, a digital camera or a digital video camera, is so configured that an inductor, a capacitor, etc. are externally mounted separately from a power source IC. For the purpose of coping with the requirements of such portable electronic equipment, whose size has been reduced year by year, a PCB (Printed Circuit Board) on which the DC-DC converter is packaged also needs to be made smaller in area.
A power source IC having multiple channels, in which control circuits for driving a large number of DC-DC converters, respectively, are integrated, has been employed often in recent years. Since, however, inductors and capacitors are externally mounted, reduction in the size of the multi-channel power source IC has been limited.
FIG. 9 is a diagram showing the arrangement of an essential circuit of a DC-DC converter. An inductor L is connected to a power source IC 50, while one electrode of a capacitor C is connected to the inductor L, and the resulting connection point is connected with a VDD terminal which is the main DC terminal of the DC-DC converter. Additionally, ground (GND) of the power source IC 50 and another electrode of the capacitor C are connected, and the resulting connection point is connected with a GND terminal of the DC-DC converter. The VDD terminal and the GND terminal are connected with a load. The power source IC 50 has multiple channels and has control circuits which are respectively connected to a plurality of inductors L and are integrated.
FIG. 10 is a view showing a PCB on which are packaged a power source IC with six channels integrated, six inductors, six capacitors, and ICs as six loads.
The power source IC 50a is formed with six channels, the respective channels are connected with the six inductors L by wiring lines 61, these inductors L and the six capacitors C are respectively connected, and the individual loads 51-56 are connected to the respective connection points between the inductors L and the capacitors C. The power source IC 50a, the inductors L, the capacitors C, and the ICs as loads 51-56 are secured on PCB 100.
When the power source IC 50a in which the multiple channels are integrated is employed as shown in FIG. 10, it becomes difficult to arrange the inductors L and the capacitors C near the power source IC 50a. Besides, distances to the loads 51-56 (devices such as ICs), which are power feed destinations, become long. For this reason, wiring lines 61 which connect the power source IC 50a with the inductors L and the capacitors C become long, and noise 63 arises from the wiring lines 61. In addition, as wiring lines 62 to the loads 51-56 become long, problems occur, such as unstable operation of the power source IC 50a on account of a voltage oscillation ascribable to a wiring line inductance 64, and the ICs as loads 51-56 cannot demonstrate original performances due to voltage drops ascribable to currents which are fed to the loads 51-56, for example, when currents to be consumed in these loads 51-56 have changed abruptly.
In order to solve the problems, there has been practiced a technique wherein, as shown in FIG. 11, composite semiconductor devices 71-76, in each of which are formed a power source IC of single channel, are made unitary with an inductor and a capacitor, and the unitary composite semiconductor devices 71-76 are arranged in the vicinities of loads 51-56, thereby shortening wiring lines 77 to the loads 51-56. Additionally for this solution, the area of a PCB 101 can also be made small.
Patent Document JP-A-2002-57037 discloses a technique wherein, as shown in FIG. 12, a buffer layer 83 is formed on the rear surface of a semiconductor substrate 81 formed with an integrated circuit, a thin-type capacitor is formed by epitaxially growing a dielectric layer 85 on the buffer layer 83, and a thin-type inductor 87 is formed in the thin-type capacitor. Numeral 82 in the figure designates in phantom an element formation region in which elements constituting the integrated circuit are formed, and numerals 84 and 86 designate the electrodes of the thin-type capacitor, respectively.
Patent Document JP-A-2004-72815 discloses a technique wherein, as shown in FIG. 13, a surface on the front side of a semiconductor substrate 91 formed with a power source IC and the front surfaces of the terminals 93 of a thin-type inductor 92 are connected by bumps 94, and the rear surfaces of the terminals 93 of the thin-type inductor 92 and the electrodes 96 of a thin-type capacitor 95 are secured by a conductive adhesive (not shown).
With the technique of Patent Document JP-A-2002-57037, however, the thin-type capacitor is formed on the rear surface of the semiconductor substrate 81 by epitaxial growth, so that the manufacturing method is complicated and the cost becomes high. Moreover, the dispersion of capacitor characteristics tends to enlarge on account of the complexity of the manufacturing processes.
Besides, with the technique of Patent Document JP-A-2004-72815, the semiconductor substrate 91 and the surfaces of the terminals 93 of the thin-type inductor 92 are connected by bumps 94, and the electrodes 96 of the thin-type capacitor 95 are connected onto the rear surfaces of the terminals 93 of the thin-type inductor 92 by conductive adhesive. Therefore, the electrical connections between the semiconductor substrate 91 and the thin-type capacitor 95 are made through the bumps 94, the terminals 93 penetrating through the thin-type inductor 92, and the electrodes 96 of the thin-type capacitor 95. One of the paths of the connections is also used for grounding one electrode of the thin-type capacitor 95, but the connections need to be established more directly for the purpose of enhancing characteristics influenced by cost and noise.
Objects of this invention include solving the above problems and providing a composite semiconductor device, in which a capacitor is connected to the rear surface of a semiconductor substrate to be brought to a GND potential, at a low cost.
USPTO Backgrounds
USPTO Backgrounds