The ability for an electronic device for resetting itself in case of error or abnormal power loss can for example be observed with electronics such as a television or audio equipment or the electronics of a car or other vehicle, which are designed to function as intended again after having lost power suddenly. A sudden and strange error with a device might sometimes be fixed by removing and restoring power, making the device reset.
Processing devices, such as microcontroller units (MCU), use a reset to properly start or return to a known state in case of problems with, for example, the internal state machine. This may for example be relevant for safety critical systems, which may require that a reset can be initiated even when the system clock is not running.
A signal may be any physical quantity carrying information, for example a voltage changing over time, wherein for example one or more voltage levels may be associated with certain meanings. For example, a reset signal may comprise at least two different signal levels, wherein one level or a level change is associated with information causing the device receiving the reset signal to perform a reset. Asserting a reset may refer to changing the level of the reset signal in order to cause the receiving device to perform the reset. De-asserting the reset may refer to changing the reset signal level (back) to a level not associated with a reset command.
Reset signals for electronic systems may be issued asynchronously or synchronously with a second signal such as the system clock signal. In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that for example oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits and synchronize application of signals to synchronous or clocked circuits, such as for example flip-flop circuits, for example in a processing device, or clocked memory devices, such as random access memory (RAM) devices.
Initiating a reset even when the system clock is not running may be handled by an asynchronous reset signal independently of the current state of the system clock, routed to, for example, all flip-flop circuits, which may comprise an asynchronous reset input, for example for power-on initializing of the flip-flop. Other clocked devices, for example RAM devices, may not comprise asynchronous reset inputs and may for example be driven by flip-flop outputs.
In U.S. Pat. No. 6,237,090 a synchronous or asynchronous resetting circuit is shown, wherein a reset assertion is applied synchronously with the clock signal if a clock signal is detected within a fixed time window after the input reset signal assertion, otherwise the reset is asserted asynchronously, i.e. the asynchronous reset path is activated after a certain delay regardless of the condition of the clock.
In U.S. Pat. No. 7,449,926 a circuit for asynchronously resetting a synchronous circuit is shown, wherein separate signals for asynchronous and synchronous reset are generated, each using different routing through different wiring for applying the first and second reset signal to a receiving device.
In U.S. Pat. No. 7,626,420 a system for synchronously resetting logic circuits is shown, wherein the reset de-assertion is synchronized with a clock signal.
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