Disk Drives commonly employ one or more microprocessors or micro-controllers (the terms are used interchangeably) in an embedded control system to control operations of the drive. In order to maximize the performance of the microprocessor, a cache control system is frequently included which minimizes the access time for fetching instructions and data from memory.
As is well known in the art, a cache system depends on locality of reference to provide the expected performance improvement. This means that the memory address range for a particular segment of program code being executed tends to be co-extensive with the range of memory data being stored in the cache. Therefore, most accesses after the cache is initially loaded will be in the cache—i.e. a cache “hit”. When a memory access address falls outside the cached segment, i.e. a “cache miss” occurs, the cache control system directs the access to main memory, such as via a buffer manager circuit, and stores the new data in the cache. Generally, when a cache miss occurs, the cache control system fetches a string or burst of data sequential to the miss address, anticipating that subsequent requests will be sequential.
Unfortunately, in many instances this fetching of a string or burst of data may be delayed, thus resulting in the stalling of the microprocessor while the data request is being received. Typically, this delay or latency is introduced by the buffer manager circuit which is tasked with arbitrating access to the main memory between its various clients, such as the microprocessor, the error correction code subsystem, etc. If a client with a higher priority task is arbitrated to access the memory, then the microprocessor request for access to the memory will be delayed unit the higher priority task has accessed the memory. This delay is commonly referred to as the arbitration latency of the buffer manager. A latency-sensitive microprocessor routine, such as an interrupt service routine, can typically not tolerate the arbitration latency of the buffer manager, therefore rendering microprocessor requests to access data in main memory impractical. As a result, the latency-sensitive data will typically have to be stored in a dedicated memory, such as in a static random access memory (SRAM). The SRAM, however, is expensive to implement and is typically of a much smaller size than the main memory so that only a subset of latency-sensitive data can be stored therein.
Accordingly, what is needed is an improved disk drive cache control system which minimizes delays in providing the microprocessor with data stored in the main memory via the buffer manager, to thus offer beneficial cache performance without incurring cost penalties.
USPTO Backgrounds
USPTO Backgrounds