Recently, the large-scale integrated circuits commonly utilize multilevel metallization schemes involving two or more patterned conductive layers, wherein each of the conductive layers is separated by insulating layers. Certainly, in order to connect two different conductive layers, a plurality of via holes need to be formed therebetween so that the conductive layers can be connected by using vertically extending via structures. In the process for forming via holes, an insulating layer is often formed on the first conductive layer before another conductive layer is formed. Thereafter, the via holes are defined and formed by a photolithography and etching process. At the early stage, a general method for forming a plurality of via holes was mainly accomplished by conventional photolithographic processes. However, there are some problems encountered with conventional photolithographic processes. The actual positions of the via holes are often shifted from the predetermined positions of the via holes because the mask is not easily aligned during the photolithographic process. Therefore, a portion of the conductive layer which should not be exposed is exposed after etching process, resulting in the occurrence of a short circuit between the exposed conductive layer and the subsequently formed contact plug. This brings about a low yield rate. Certainly, the misaligned phenomenon will be worsen in the minimized semiconductor process.
In order to prevent the misaligned phenomenon, a so-called self-aligned via hole process is used to overcome this defect at the present day. In other words, it is uneasy to align the mask and the cost for the correct alignment is relatively expensive. Moreover, in order to obtain higher interconnection packing densities, a fine high-aspect-ratio via is necessary. Much effort has been dedicated to the development of advanced steppers and etchers to achieve this goal. Besides, misalignment of photolithography step would dump lots of difficulties in etching process. Hence, one method is provided for forming self-aligned via holes to improve the defects encountered by the prior art. This is why self-aligned via is crucial for advanced interconnection.
Some self-aligned contact processes have been proposed. Please refer to FIG. 1 showing a method for forming a self-aligned plug. As shown in FIG. 1(a), a conductive layer 62 is formed on the substrate 61. Thereafter, a plug 621 is formed on the conductive layer 62 by a first step of photolithography and etching process, as shown in FIG. 1(b). As shown in FIG. 1(c), the conductive layer 62 are partially removed to define a required circuit by a second photolithography and etching process. Finally, the insulating layer 65 is formed on the conductive layer 62 and then planarized to expose the top of the self-aligned plug 621 as shown in FIG. 1(d). However, the above-described process has some defects:
1. The step of forming a metal layer results in an increased manufacturing cost. PA1 2. The plurality of plugs formed previously cause a rugged surface so that the second photolithography and etching process is very hard to be executed and controlled.
Another method of providing a via structure has been disclosed. The method is to create metal pillars before a dielectric layer is deposited over a metal line and then to expose the tops of metal pillars by a proper planarization process. However, the prior methods do not provide a simple and reliable (good controllability) approach to produce via structure.
USPTO Backgrounds
USPTO Backgrounds