Microelectronic elements such as semiconductor chips typically are provided in packages which provide physical and chemical protection for the semiconductor chip or other microelectronic element. Such a package typically includes a package substrate such as a small circuit panel formed from a dielectric material and having electrically conductive terminals thereon. The chip is mounted on the panel and electrically connected to the terminals of the package substrate. Typically, the chip and portions of the substrate are covered by an encapsulant or overmolding, so that only the terminal-bearing outer surface of the substrate remains exposed. Such a package can be readily shipped, stored and handled. The package can be mounted to a larger circuit panel such as a circuit board using standard mounting techniques, most typically surface-mounting techniques. Considerable effort has been devoted in the art to making such packages smaller, so that the packaged chip occupies a smaller area on the circuit board. For example, packages referred to as chip-scale packages occupy an area of the circuit board equal to the area of the chip itself, or only slightly larger than the area of the chip itself. However, even with chip-scale packages, the aggregate area occupied by several packaged chips is greater than or equal to the aggregate area of the individual chips.
It has been proposed to provide “stacked” packages, in which a plurality of chips are mounted one above the other in a common package. This common package can be mounted on an area of the circuit panel which may be equal to or just slightly larger than the area typically required to mount a single package containing a single chip. The stacked package approach conserves space on the circuit panel. Chips or other elements which are functionally related to one another can be provided in a common stacked package. The package may incorporate interconnections between these elements. Thus, the main circuit panel to which the package is mounted need not include the conductors and other elements required for these interconnections. This, in turn, allows use of a simpler circuit panel and, in some cases, allows the use of a circuit panel having fewer layers of metallic connections, thereby materially reducing the cost of the circuit panel. Moreover, the interconnections within a stacked package often can be made with lower electrical impedance and shorter signal propagation delay times than comparable interconnections between individual packages mounted on a circuit panel. This, in turn, can increase the speed of operation of the microelectronic elements within the stacked package as, for example, by allowing the use of higher clock speeds in signal transmissions between these elements.
One form of stacked package which has been proposed heretofore is sometimes referred to as a “ball stack.” A ball stack package includes two or more individual units. Each unit incorporates a unit substrate similar to the package substrate of an individual package, and one or more microelectronic elements mounted to the unit substrate and connected to the terminals on the unit substrate. The individual units are stacked one above the other, with the terminals on each individual unit substrate being connected to terminals on another unit substrate by electrically conductive elements such as solder balls or pins. The terminals of the bottom unit substrate may constitute the terminals of the package or, alternatively, an additional substrate may be mounted at the bottom of the package and may have terminals connected to the terminals of the various unit substrates. Ball stack packages are depicted, for example, in certain preferred embodiments of U.S. Published Patent Applications 2003/0107118 and 2004/0031972, the disclosures of which are hereby incorporated by reference herein.
In another type of stack package sometimes referred to as a fold stack package, two or more chips or other microelectronic elements are mounted to a single substrate. This single substrate typically has electrical conductors extending along the substrate to connect the microelectronic elements mounted on the substrate with one another. The same substrate also has electrically conductive terminals which are connected to one or both of the microelectronic elements mounted on the substrate. The substrate is folded over on itself so that a microelectronic element on one portion lies over a microelectronic element on another portion, and so that the terminals of the package substrate are exposed at the bottom of the folded package for mounting the package to a circuit panel. In certain variants of the fold package, one or more of the microelectronic elements is attached to the substrate after the substrate has been folded to its final configuration. Examples of fold stacks are shown in certain preferred embodiments of U.S. Pat. No. 6,121,676; U.S. patent application Ser. No. 10/077,388; U.S. patent application Ser. No. 10/655,952; U.S. Provisional Patent Application No. 60/403,939; U.S. Provisional Patent Application No. 60/408,664; and U.S. Provisional Patent Application No. 60/408,644. Fold stacks have been used for a variety of purposes, but have found particular application in packaging chips which must communicate with one another as, for example, in forming assemblies incorporating a baseband signal processing chip and radiofrequency power amplifier (“RFPA”) chip in a cellular telephone, so as to form a compact, self-contained assembly.
Despite all of these efforts in the art, still further improvement would be desirable. In particular, it would be desirable to provide packages which can afford advantages similar to those achieved in a fold stack without the necessity for actually folding a substrate.
USPTO Backgrounds
USPTO Backgrounds