1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device with element isolation trenches formed to provide isolation between elements and method of manufacturing the same.
2. Description of the Related Art
Non-volatile semiconductor memory devices include electrically erasable programmable EEPROMs as known. In general, an EEPROM comprises memory cells each including a MOS transistor with a stacked-gate structure of a floating gate serving as a charge accumulation layer and a control gate stacked.
Most suitable one for achieving large capacity among the EEPROMs is an NAND-type EEPROM. The NAND-type EEPROM comprises plural memory cells serially connected such that adjacent ones share a source/drain diffused layer, thereby configuring an NAND cell unit. Plural such NAND cell units are arrayed to configure an NAND cell array. Both ends of each NAND cell unit are connected via respective selection gate transistors to a bit line and a common source line.
Floating gates are separated from each other on a memory cell basis while control gates are continuously patterned as a word line (control gate line) common to memory cells arranged in one direction. Gate electrodes on the selection gate transistors are similarly arranged as a selection gate line in parallel with the word line. The selection gate transistor on the drain side in the NAND cell unit has a diffused layer, which is connected to a bit line arranged to cross the word line. The selection gate transistor on the source side in the NAND cell unit has a diffused layer, which is connected to a common source line.
Such the EEPROM causes a problem associated with interference between floating gates due to capacitive coupling between cells as memory cells are integrated at a higher density. A technology of reducing the interference between floating gates has been known in an NAND flash memory that includes a low-permittivity oxide or an air gap formed between floating gates in plural memory cells serially connected to configure an NAND cell unit. (Daewoong Kang et al., “Improving the Cell Characteristics Using Low-k Gate Spacer in 1 Gb NAND Flash Memory”, 2006 IEDM Dig., pp. 1001-1004, December 2006.)
USPTO Backgrounds
USPTO Backgrounds