1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device whose drain-to-source breakdown voltage, VDSS, is increased and a method of manufacturing the same.
2. Description of the Related Art
By referring to FIG. 10 and FIGS. 11A to 11C, a conventional semiconductor device and a method of manufacturing the same will be described by taking a MOSFET as an example.
As shown in FIG. 10, a drain region 20 is provided, for example, by laminating an n type epitaxial layer 22 on an n+ type silicon semiconductor substrate 21, and a plurality of p type channel regions 24 are provided on a surface of the drain region 20. A gate electrode 33 is provided on a portion on the surface of the n type epitaxial layer between the two p type channel regions 24 which are adjacent to each other, with a gate insulation film 31 interposed therebetween. Peripheries of the gate electrode 33 are covered with an interlayer insulating film 36. Additionally, n+ type source regions 35, being formed in the surface of the channel regions 24, are in contact with a source electrode 38.
As a technology for the above-mentioned MOSFET of a so-called planar structure, one in which an n type impurity layer 40 having a higher impurity concentration than the epitaxial layer 22 is arranged on the surface of the n− type epitaxial layer 22 between the two adjacent p type channel regions 24 is also known. In case of a MOSFET whose breakdown voltage is 600 V, it is possible to increase the impurity concentration of the n type impurity layer 40 to approximately 1×1016 cm−3. This technology brings about an effect of reducing a drain-to-source resistance when the MOSFET is in the ON state. This technology is described, for instance, in Japanese Patent Application Publication No. 2622378.
By referring to FIGS. 11A to 11C, the method of manufacturing the above-mentioned MOSFET will be described.
A substrate, obtained, for example, by laminating the n− type epitaxial layer 22 on the n+ type silicon semiconductor substrate 21, forms the drain region 20. Ions of an n type impurity (for example, phosphor: P) are implanted into an entire surface of the n− type epitaxial layer (FIG. 11A). Thereafter, the gate oxide film 31 and the gate electrode 33 are formed. Then, ions of a p type impurity (for example, boron: B) are implanted, by using the gate electrode 33 as a mask (FIG. 11B). Subsequently, by diffusing the n type impurity and the p type impurity through a thermal treatment, the n type impurity layer 40 and the channel regions 24 are formed. On the surface of the channel regions 24, the source regions 35 are formed (FIG. 11C). Then, the gate electrode 33 is covered with the interlayer insulating film and the source electrode (not illustrated) is formed.
In the MOSFET shown in FIG. 10, when the MOSFET is in the ON state, the drain region 20 below the gate electrode 33 works as a region for causing an electric current to flow in a direction perpendicular to the substrate. That is, the n type impurity layer 40 having a high impurity concentration is arranged in a portion (hereinafter, referred to as a π portion 45) on the surface of the drain region 20 between each two adjacent ones of the channel regions 24 because it is preferable that, when the MOSFET is in the ON state, a resistance of the drain region 20 be low.
On the other hand, when the MOSFET is in the OFF state, a drain-to-source voltage is applied and a reverse bias is generated. As a result, a depletion layer 50 extends from pn junctions with the channel region 24 and generates a depletion state, whereby the breakdown voltage is increased. That is, it is preferable that the impurity concentration of the π portion 45 be higher in order to allow the drain region 20 to have a lower resistance. However, if the impurity concentration of the π portion 45 increases more than necessarily, the extension width of the depletion layer 50 becomes narrow as shown in the dotted line of FIG. 10, whereby there arises a problem that a breakdown voltage is deteriorated.
Additionally, because a curvature from a bottom to a side surface becomes large in each of the channel regions 24 formed through diffusion, the interval between the two adjacent ones of the channel regions 24 becomes wide in vicinity of the bottoms thereof. That is, the depletion layer 50 pinching off sufficiently in vicinity of the top surface of the channel regions 24 does not sufficiently pinch off in vicinity of the bottoms thereof, whereby there arises a problem that a breakdown tends to occur in corner portions (refer to a region “a” in FIG. 10) of each of the channel regions 24.
Furthermore, because the ion implantation of the n type impurity layer 40 is performed before the formation of the gate electrode (refer to FIG. 11A), the n type impurity (for example, phosphor) is diffused through a thermal treatment during the formation of the gate electrode 33. Therefore, after the formation of the channel regions 24, a depth of each of the channel regions 24 tends to be shallower than that of the π portion 45, whereby a reduced VDSS becomes a problem.
USPTO Backgrounds
USPTO Backgrounds