Some liquid crystal display devices are of an active matrix drive type. As shown in FIG. 1, in this type of liquid crystal display device, transparent plates 10 and 12 face each other with a liquid crystal layer 14 disposed between them. Transparent pixel electrodes (not shown) are arranged in matrix on a surface of the plate 10 which contacts the liquid crystal layer 14, and a transparent common electrode 16 is disposed over the entire surface of the plate 12 contacting the liquid crystal layer 14. The liquid crystal absorbs light when a voltage above a predetermined value is applied across it. Accordingly, a desired pattern can be displayed by applying a fixed voltage, e.g., ground potential, to the common electrode 16 and applying drive voltages to selected pixel electrodes. The liquid crystal layer 14 absorbs light at the portions located between the selected pixel electrodes 14 and the common electrode 16.
In order to select pixel electrodes to which a drive voltage is to be applied, a thin film transistor (TFT) is associated with each pixel electrode, and a plurality of gate conductors 18 and a plurality of source conductors 20 crossing over the respective gate conductors 18 are disposed on the surface of the plate 10 which contacts the liquid crystal layer 14. The TFT's are disposed at the respective intersections of the conductors 18 and 20 in matrix, to form a thin film transistor (TFT) array.
FIG. 2 is an equivalent circuit diagram of the TFT array shown in FIG. 1. TFT's 22 in one row have their respective gates connected to an associated gate conductor 18, and TFT's 22 in one column have their respective sources connected to an associated source conductor 20. The drain of each of the TFT's 22 is connected to the pixel electrode 24 with which that TFT 22 is associated. The capacitance of the liquid crystal layer 14 between each of the pixel electrodes 24 and the common electrode 16 is denoted by a reference numeral 26. In order to apply a drive voltage to a particular pixel electrode 24, a voltage for turning on the TFT 22 to which that pixel electrode is connected is applied to one end of the gate conductor 18 to which the gate of that TFT 22 is connected, and the drive voltage is applied to the source conductor 20 to which the source of that TFT is connected.
In the TFT array, when the TFT 22 is turned off after it has been turned on, the drive voltage is held by the liquid crystal capacitance 26. The thus held drive voltage may decrease due to discharge through the liquid crystal layer 14 or due to leakage current in the TFT 22.
An attempt to solve this problem is disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-20, No. 11, November 1973, pages 995-1001, in which a storage capacitance 28 is disposed between a pixel electrode 24 and a gate conductor 18 for the adjacent row, as shown in FIG. 3. One of the techniques for connecting the storage capacitance 28 to the adjacent row gate conductor 18 is shown in Japanese Unexamined Patent Publication No. HEI 1-197722 which was laid open to public on Aug. 9, 1989. In this Japanese publication, as shown in FIG. 4, the edge of each pixel electrode 24 adjacent to a gate conductor 18 for the next adjacent row extends to a location above that gate conductor 18 to thereby form an overlap 24a. As shown in FIG. 5, between the gate conductor 18 and the overlap 24a, there is disposed a silicon nitride layer 30 which is a dielectric for the storage capacitance 28. Although not shown in FIG. 4, the silicon nitride layer 30 is an extension of a gate insulating film which is disposed on an extension 18a of the gate conductor 18 for forming a TFT. In FIG. 4, a reference numeral 32 denotes a drain electrode.
As shown in FIGS. 3 and 4, a connection of a storage capacitor to a gate conductor 18 of an adjacent row is provided for each pixel electrode 24 by an extension 24a. Accordingly, a need for providing the metal conductor for connecting the pixel electrode 24 to the gate conductor of the adjacent row is eliminated. If such a metal conductor were used, it would overlap the pixel electrode 24 and block light at the overlap, which would reduce the aperture ratio (a ratio of an area through which light can pass) to the total area. However, the use of the extension 24a does not cause an aperture ratio reduction.
However, in order to use pixel electrode extensions 24a, it is necessary to provide the gate conductor at its edge with a slope as shown in FIG. 5 to avoid disconnection of the extension 24a at the edge of the gate conductor 18. Alternatively, the thickness of the extension 24a could be larger than that of the gate conductor 18. This impedes improvement in degree of freedom in designing TFT's.
Furthermore, with the above-described structure, if one gate conductor 18 is disconnected at some point, TFT's 22 connected to that gate conductor 18 at points beyond the disconnection point will receive no voltage for turning on them. Therefore the circuit redundancy against gate conductor disconnection of this structure is low.
Furthermore, in this structure, a voltage for turning on the TFT's 20 is applied to each gate conductor 18 at one end thereof. If the gate conductors 18 are formed of a relatively high resistance material, such as phosphorus doped polycrystalline silicon, or if the gate conductors 18 have a small cross-sectional area, the capacitance associated with the gate conductor 18 and the resistance of the gate conductor 18 will cause delay in the TFT turn-on voltage while it is transmitted through the gate conductor 18.
Therefore, an object of the present invention is to improve the degree of freedom in designing TFT's to thereby simplify the TFT array manufacturing process.
Another object of the present invention is to provide a TFT array with an improved redundancy against gate conductor disconnection.
A still further object of the present invention is to provide a TFT array with reduced TFT turn-on voltage delay.
USPTO Backgrounds
USPTO Backgrounds