This invention relates generally to DC to DC converters and more particularly to a two-switch buck-boost converter. A two-switch buck-boost converter defines a well known electrical topology used for non-isolated DC to DC power conversion in which the DC input voltage may either be "bucked" down or "boosted" up as required to produce the desired DC output voltage. A typical prior art two-switch buck-boost converter is illustrated in FIG. 1. The primary objective of this circuit, as in all power conversion topologies, is to convert the power from input to output with a minimum loss of power within the converter. This is to say that high power transfer efficiency is desired. While the most straightforward technique for controlling a buck-boost converter is by simultaneous switching of both of its switches, this control technique suffers from an unnecessary degradation in power transfer efficiency. Theoretically, it is only necessary to regulate the converter by actively switching only one of its switches at a time, depending on whether the output voltage is to be lowered or raised with respect to the input voltage of tile converter. As the process of switching a switch from one state to another causes a loss of power, this latter technique is more desirable.
In operation, the prior art buck-boost converter of FIG. 1 involves applying a uni-polar input voltage across terminals Q and R, with the polarity being positive and negative, respectively. The output voltage is developed across terminals S and T, with the polarity being positive and negative, respectively. Terminals R and T are electrically connected and described as being at zero reference potential or ground. Terminals E and F, respectively, represent the control inputs to a pair of semiconductor devices S1 and S2, known in this converter as the boost switch and buck switch, respectively. Semiconductor devices S1 and S2 may be MOSFET devices, as illustrated. If devices S1 and S2 are modulated simultaneously, it is possible to achieve any positive output voltage, within the limitations of the circuit components employed. This conventional simultaneous switching of devices S1 and S2 results in unnecessary power losses.
If device S1 is modulated while device S2 remains OFF, the output voltage can be regulated to any positive potential up to the input voltage minus voltage losses in the circuit. This is known as the buck mode of operation of the converter. If device S2 is modulated while device S1 remains ON, the output voltage can be regulated to any positive potential not less than the input voltage minus voltage losses in the circuit. This is known as the boost mode of operation of the converter. The latter two modes of operation of the prior art converter of FIG. 1 describe one-at-a-time switch control that results in a higher power conversion efficiency than does simultaneous switch modulation.
Recently, Fuji-Denki, Inc. of Japan introduced a buck-boost controller integrated circuit (Part No. FA7618) in which the one-at-a-time switch control method is successfully implemented. The relevant portion of the circuitry of this buck-boost controller is shown in FIG. 2A. One feature inherent in the buck-boost topology was foremost in allowing successful implementation of one-at-a-time switch control: that is, for a given input voltage, the output voltage of the converter is the same in buck mode running at a 100% duty ratio as is in the boost mode running at 0% duty ratio. The term duty ratio is well understood in the art to be the ratio of the ON time of a switch to the time required to complete a full cycle of ON and OFF times. Therefore, the challenge in developing this prior art control circuit was the requirement that as the signal which controls the duty ratio of the buck switch approaches 100%, the same signal must also be on the verge of modulating the boost switch starting from 0% duty ratio.
A conventional technique for accomplishing fixed-frequency pulse-width modulated control fo the switch drive duty ratio is to use a comparator to compare the control signal (error signal) against a timing ramp represented by a triangular or sawtooth waveform of fixed magnitude and frequency. The implementation employed in the prior art FA7618 controller was to use one comparator in the standard fashion just described to control one drive signal and to shift the level of one input of another comparator an amount equal to the magnitude of the timing ramp to control the other drive signal. Properly oriented, this results in the desired drive signals for both switches of the buck-boost converter. By setting the magnitude of the level shift just described equal to the ramp magnitude, the transition between the buck and boost modes can be accomplished without requiring a change in the operating point, during which time the output would be disturbed.
Operation of the prior art FA7618 controller may be understood with reference to the circuit diagram of FIG. 2A and the waveform diagram of FIG. 2B. A triangle wave oscillator ramps at a constant frequency between two potentials applied to terminals B and C to provide a timing ramp that is available at terminal G. An error signal is applied at terminal A. A comparator having an output terminal F compares the oscillator potential against the error signal potential. Its input polarities are configured such that when the error signal potential exceeds the oscillator potential the output is high, and conversely. Terminal F serves as the control terminal for the buck switch S1 of FIG. 1. Another comparator having an output terminal E compares the oscillator potential against a potential equal to the error signal potential decreased by an amount V.sub.LS. V.sub.LS is ideally equal in magnitude to the difference in the potential across terminals B and C, which is equal to the voltage excursion magnitude of the oscillator. Terminal E serves as the control terminal for the boost switch S2 of FIG. 1. A disadvantage in the design of the prior art FA7618 controller is the implementation of the level shift circuit. The key to optimal transition between buck and boost modes without overlapping lies in precisely tracking the level shift magnitude with the timing ramp magnitude. Therefore, control of the level shift and the timing ramp magnitudes are critical, the former being the more difficult to control precisely.
It is therefore an object of the present invention to provide a controller for a two-switch buck-boost converter that accomplishes one-at-a-time switch control by simultaneously employing an analog error signal to control one drive output and an analog inversion of that error signal, with respect to a voltage that is equal to the voltage excursion limit of a timing ramp signal, to control the other drive output.
It is another object of the present invention to provide an alternative controller for a two-switch buck-boost converter that accomplishes one-at-a-time switch control by employing a comparator to compare an analog error signal against a given voltage excursion limit of a timing ramp signal to perform the functions of determining which of two drive outputs is to be enabled to be modulated and of modifying the voltage excursion limits of the timing ramp signal such that the voltage excursion limit compared by the comparator is switched between two different voltage excursion limits.
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