Some conventional package substrates include at least one conductive through via for interconnecting top and bottom circuits. In the manufacturing process, the conductive through vias are formed by plating a conductive metal in through holes formed in the package substrate.
However, in the production of high aspect ratio package substrates, fully filling the substrate's high-aspect-ratio through holes by Cu-plating often leads to over-plating, which, in turn, results in over-plated Cu on a resist pattern or poor line definition in a subsequent circuit-forming step of selectively etching.
USPTO Backgrounds
USPTO Backgrounds