This application is based on Japanese Patent Application No. 10-124367, filed May 7, 1998, Japanese Patent Application No. 10-203454, filed Jul. 17, 1998, and U.S. patent application Ser. No. 09/305,752, filed May 6, 1999, now U.S. Pat. No. 5,973,991, issued Oct. 26, 1999 the contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory for configuring an SDRAM (Synchronous DRAM) which needs to operate at a high-speed, and more particularly high-speed cycle clock-synchronous memory and memory system using the same.
SDRAM has banks comprising, for example, a plurality of memory cell arrays (referred to as xe2x80x9ccell arrayxe2x80x9d below). A sense amplifier zone in each bank is shared by cell arrays adjacent thereto. Configuration of such a sense amplifier area is allowed to reduce an area occupied by the same. Also, an input/output data line may be shared by each cell array. Data is transferred to a buffer for output data burst via such shared data lines.
When data in an arbitrary cell array is accessed, all of cell arrays in the bank including the accessed cell array are controlled all at once. That is, a word line (WL) in an arbitrary cell array to be accessed is activated to be an active level, and data of each memory cell belonging to this WL is temporally stored by each sense amplifier.
Thereafter, arbitrary data is read out via an input/output data line. Data of each memory cell belonging to the above-mentioned word line WL is restored. After the WL is set at an inactive level, a bit line and the sense amplifier are equalized. Then, an arbitrary cell array in the bank can be subjected to the next activation.
FIG. 14 is a timing chart showing an example of data access design, according to the prior art described above. /RAS (Row Address Strobe) signal (the leading xe2x80x9cP, is capped with a horizontal bar in the drawings) makes a word line of a selected cell array active during xe2x80x9cLxe2x80x9d (low level). As a result, it becomes possible to access data in each memory cell belonging to the selected WL, that is, the page data.
A value of address (Add) at the time when /RAS signal falls to xe2x80x9cLxe2x80x9d designates a cell array and a word line (WL) to be selected (as denoted by (R)). Thereafter, each time /CAS (Column Address Strobe) signal (the leading xe2x80x9cP, is capped with a horizontal bar in the drawings)falls, a page address is determined (as denoted by (C1) to (C4)). Accordingly, data is output from a sense amplifier in a column corresponding to the page address.
For internal operation, during a period in which /RAS is set at xe2x80x9cLxe2x80x9d, data in each memory cell belonging to the word line WL in the activated cell array is kept in the state of sense, amplified (stored condition) and restore state (SandR). EQL is an equalizing operation of a bit line and a sense amplifier. EQL functions after /RAS becomes xe2x80x9cHxe2x80x9d (high level) and the word line WL becomes an inactive level.
Such a data access operation enables high-speed access to data in a memory cell belonging to a selected word line WL. However, such high-speed access as mentioned above cannot be maintained when selection of the WL is frequently changed. This is because access to a column cannot be performed until selection of a new word line becomes possible.
Regarding access to data in cell arrays in the same bank, attention should be paid to a time from completion of selecting one word line WL1 until it is possible to select another word line WL2.
Selection of the word line WL2 is prohibited until EQL of the internal operation in FIG. 14 is terminated, regardless of the memory cell that the WL2 belongs to. Here, EQL means equalization of the bit line and the sense amplifier based on the preceding data access to the word line WL1. Thus, it always takes a fixed and long time to access a different word line in the same bank.
In general, as well known, a DRAM senses data by using a ratio of a cell capacitance and a bit line capacitance to each other. Therefore, it should be considered that a memory is configured to ensure a cell capacitance for sensing cell data and to provide a high-speed sense operation. It is preferable to make the number of cells belonging to a bit line connected to one sense amplifier as small as possible. And it is also preferable to reduce the number of cells connected to one word line in order to decrease RC delay time needed as a rise time and a fall time of a word line.
In other words, in view of the functional improvement of a memory, the size of a cell array comprising a plurality of memory cells cannot be so large. Therefore, it is preferable to divide a memory into a number of cell arrays.
In a design of a memory, sense amplifiers are shared by adjacent cell arrays. Thus, the area occupied by the sense amplifier becomes half the area when the sense amplifier is not being shared. Such a shared sense amplifier, however, enables only one of the adjacent cell arrays to use the same at a single access.
In recent years, there has been employed a UMA (Unified memory Architecture) in which a single memory is data-accessed by many elements. By employing a UMA, access to word lines has been changed frequently. As a result, according to the prior art, an unnecessary waiting time during data transfer often occurs. Therefore, such a conventional system needs an improvement for more efficient use of memory data.
In view of the considerations described above, the present invention has been achieved. It is therefore an object of the invention to provide a high-speed cycle clock-synchronous memory and a memory system allowing effective data transfer, which realizes a word line access cycle faster than that in a conventional technique.
A first aspect of the present invention is a high-speed cycle clock-synchronous memory device comprising:
a plurality of cell arrays each including a plurality of memory cells;
a sense amplifier circuit section shared by the cell arrays;
a cell array control circuit to which row and column addresses are simultaneously inputted to designate an arbitrary memory cell in the memory cells and which independently controls an access operation to the plurality of cell arrays; and
an address structure of the plurality of cell arrays, on the basis of a change in specific bits between a first address and a second address when the first address obtained according to a first command is compared with the second address obtained according to a second command sent subsequent to the first command, by which the accesses according to the first and second commands can be judged to be accesses to the same cell array, accesses to neighboring cell arrays, or accesses to cell arrays which are far from each other can be determined.
A second aspect of the present invention is a high-speed cycle clock-synchronous memory device comprising:
a plurality of cell arrays each including a plurality of memory cells;
a sense amplifier shared by the cell arrays; and
a cell array control circuit to which row and column addresses are simultaneously inputted to designate an arbitrary memory cell in the memory cells and which independently controls an access operation to the plurality of cell arrays,
wherein the device has a burst access operating mode in which a signal for designating a cycle in which a command is obtained synchronously with a clock and instructing a timing at which a command which continuously maintains a predetermined level at least in a period before the half of the cycle of the clock is used, and
when an address of the head memory address is supplied, the subsequent addresses can be accessed.
A third aspect of the present invention is a high-speed cycle clock-synchronous memory system comprising:
a memory section having a plurality of cell arrays each including a plurality of memory cells and to which row and column addresses are simultaneously inputted to designate an arbitrary memory cell among the memory cells, wherein an access operation is independently controlled to the plurality of cell arrays; and
a memory controller portion for simultaneously supplying an address signal for selecting an arbitrary memory cell in the memory section and a command signal for controlling access to the memory part synchronously with a clock signal,
wherein the memory controller portion changes the number of clock cycles between the first and second commands on the basis of a change in a specific bit between an address signal obtained according to a first command to the memory part and the address signal obtained according to a second command subsequent to the first command.
A fourth aspect of the present invention is a high-speed cycle clock synchronous memory device comprising:
a plurality of cell arrays each including a plurality of memory cells, the plurality of cell arrays being positioned according to an address format made up of a plurality of bits;
sense amplifier circuit parts shared by neighboring cell arrays; and
a cell array control circuit which receives an address information signal for designating a desired one of the memory cells, which is constructed according to the address format and controls the sense amplifier circuits in accordance with the address information signal,
wherein when a first command and a second command subsequent to the first command are supplied to the memory,
predetermined bits in the address format provide information to identify whether a first cell array corresponding to a first address information signal and a second cell array corresponding to a second address information signal are the same cell array, neighboring cell arrays having a common sense amplifier part, or cell arrays which are far from each other having no common sense amplifier part, by comparing the first address information signal provided according to the first command with the second address information signal provided according to the second command.
A fifth aspect of the present invention is a high-speed cycle clock-synchronous memory system comprising:
at least one high-speed cycle clock-synchronous memory device; and
a memory control unit for controlling the at least one high-speed cycle clock-synchronous memory device,
wherein the memory control unit determines the number of command cycles between the first command and the second command on the basis of information provided by predetermined bits in the address format.
Without such a conventional concept of the same bank in which an access between a plurality of cell arrays having a common data transmission system is always controlled at fixed long time intervals, the present invention provides a cell array control circuit so as to control a plurality of cell arrays independently and individually. With this arrangement, it is possible to optimize an access time between different word lines into an essentially minimized time. More particularly, a mutual positional relationship between cell arrays which are accessed successively is judged so that the number of cycles between commands can be minimized.
The memory according to the present invention has another feature in that it provides an address configuration which enables the determining of a mutual positional relationship between successively accessed cell arrays by a change of addresses thereof. The memory having the address configuration is suitable for a memory system which first judges a mutual positional relationship between cell arrays which are accessed successively by a change of addresses thereof, and with this judgment, optimizes the number of cycles between commands which decides an access time between different word lines.
A memory cell array where the positional relationship is judged may be a logical cell array comprising a plurality of physical cell arrays where a defective word line can be freely replaced with a spare word line among the physical cell arrays. When the present invention is applied to a memory having such logical cell arrays, it will be possible to optimize an access time between different word lines in each memory device into an essentially minimized time while securing a proper quality necessary for a good memory device product by increasing or decreasing the number of logical cell arrays according to the number of occurrences of defective word lines.
For judging a change of addresses, a memory controller portion connected to the memory is used. Responsive to the change of addresses, the memory controller portion controls a signal indicating a timing for taking a command.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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