(1) Field of the Invention
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of uniform local oxidation using a nitrogen implant in the fabrication of integrated circuits.
(2) Description of the Prior Art
Local oxidation of silicon (LOCOS) is the conventional lateral isolation scheme. The conventional local oxidation process is described in VLSI Technology, International Edition, by S. M. Sze, McGraw-Hill Book Company, N.Y., N.Y., c. 1988 by McGraw-Hill Book Co., pp. 473-474. A layer of silicon nitride is deposited over a pad oxide overlying a silicon substrate. The pad oxide is a thin thermal oxide which allows better adhesion between the nitride and silicon and acts as a stress relaxation layer during field oxidation. The nitride and oxide layers are etched to leave openings exposing portions of the silicon substrate where the local oxidation will take place. A boron channel-stop layer is ion implanted into the isolation regions. The field oxide is grown within the openings and the nitride and pad oxide layers are removed. This completes the local oxidation.
However, as the silicon nitride opening between active device regions is reduced to the submicrometer regime, a reduction in field oxide thickness within the opening has been observed. This oxide thinning in the area where field spacing is narrow/small has caused insufficient isolation between active regions.
U.S. Pat. No. 5,061,654 to Shimizu et al and U.S. Pat. No. 5,128,274 to Yabu et al describe methods for purposefully making field oxide regions to be of different thicknesses. U.S. Pat. No. 5,173,438 to Sandhu shows a method for adjusting ion implantation to achieve different field oxide thicknesses. The purpose of the present invention is to achieve the same field oxide thicknesses for different sized openings.
In their article, "A Self-Aligned Nitrogen Implantation Process (SNIP) to Minimize Field Oxide Thinning Effect in Submicrometer LOCOS," by Somnuk Ratanaphanyarat, Jente B. Kuang, and S. Simon Wong, IEEE Transactions on Electron Devices, Vol. 37, No. 9, September 1990, pp. 1948-1958, the authors describe a method of implanting nitrogen into wide openings to slow field oxidation rates there. Nitrogen is not implanted into narrow openings which are shielded by oxide spacers so that field oxidation is not slowed in these regions.
The spin-on-glass materials have been used for planarization of integrated circuits. The material to be applied is thoroughly mixed in a suitable solvent. The spin-on-glass material suspended in the vehicle or solvent is deposited onto the semiconductor wafer surface and uniformly spread thereover by the action of spinning the wafer. The material fills the indentations in the integrated circuit wafer surface; that is planarization. Most of the vehicle or solvent is driven off by a low temperature baking step often followed by vacuum degassing. Other coatings of the spin-on-glass material are applied, baked and vacuum degassed until the desired spin-on glass layer is formed. The final step in the making of the spin-on-glass layer is curing. Curing is a high temperature heating step to cause the breakdown of the silicate or siloxane material to a silicon dioxide like cross linked material.
USPTO Backgrounds
USPTO Backgrounds