1. Field of the Invention
This invention relates to semiconductor devices and more particularly to connection of bit-lines in memory devices.
2. Description of Related Art
U.S. Pat. No. 5,204,286 of Doan for "Method of Making Self-Aligned Contacts and Vertical Interconnects to Integrated Circuits" and U.S. Pat. No. 5,231,051 of Baldi et al for "Method for Formation of Contact Plugs Utilizing Etchback" show use of deposits of tungsten which are etched back to form contacts.
In a conventional EPROM (Flash) layout, first there is a rule that there must be extra polysilicon to contact space of about 0.4 .mu.m of space required.
Secondly, a bit-line metal to contact overlap of about 0.2 .mu.m requires provision of a safe dimensional margin because of the high probability of misalignment of the bit-line with the contact. Both of these design rules will limit the ability to shrink (reduce the dimensions of) EPROM (Flash) memory devices.
USPTO Backgrounds
USPTO Backgrounds