The present invention generally relates to the manufacture of integrated circuits such as microprocessors and, more particularly, to a method of using arrays of lines and spaces for critical layers of a microdevice.
There is an ever present demand for increased resolution and uniformity when manufacturing the components of microdevices, such as microprocessors or random logic gates. Presently, device layers are patterned using optical lithography using deep ultraviolet light wavelengths of 240-248 nm, commonly referred to as DUV lithography. DUV lithography has a resolution limitation close to 1 xcexcm. This resolution limitation hampers making devices having small critical dimensions (e.g., 100 nm or less) and results in non-uniformity from gate to gate. Phase shift masks have been used with DUV lithography, but it is very difficult to achieve high uniformity among multiple gates with phase shift masks. Uniformity is important because it is a central factor in the timing of electrical signals as the signals propagate through the gates.
Next generation lithography (NGL), such as ion or electron beam projection, may increase the resolution of current lithography techniques. However, NGL technology is in a development stage and it may be years before proposals for NGL techniques become commercially viable. Therefore, there exists a need in the art for increasing resolution and generating better critical dimension uniformity of devices made with DUV lithography.
According to one aspect of the invention, the invention is a method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate layer over the first portion of the microdevice component; forming a second regular array of lines and spaces from a second layer of material deposited on the intermediate layer; patterning the second regular array of lines and spaces to form a second portion of the microdevice component; and forming contact holes in the intermediate layer to establish conductivity between the first portion of the microdevice component and the second portion of the microdevice component.
According to another aspect of the invention, the invention is a method of fabricating a microdevice, comprising the steps of providing a substrate; providing a uniform layer of material on the substrate; forming a regular array of lines and spaces from the layer of material; patterning the regular array of lines and spaces; forming a microdevice component on the substrate adjacent the patterned regular array of lines and spaces; and connecting the microdevice component to the patterned regular array of lines and spaces.
USPTO Backgrounds
USPTO Backgrounds