1. Field of the Invention
The present invention relates generally to semiconductor package devices, semiconductor package structures, and fabrication methods thereof, and more particularly to a semiconductor package device with TSVs (Through Silicon Vias), a semiconductor package structure, and fabrication methods thereof.
2. Description of Related Art
Along with the development of electronic products and the requirement for high integration of semiconductor chips, TSV technique based on deep silicon etching has been proposed and disclosed in such as U.S. Pat. No. 5,270,261 and No. 5,202,754.
Referring to FIGS. 2A to 2E, a conventional fabrication method of a semiconductor device with TSVs is shown. As shown in the drawings, a wafer 20 with a plurality of openings 201 formed on a first surface thereof is provided, wherein the openings 201 are filled with a metal material 21, and solder pads 22 are formed on the metal material 21 and adhered to a carrier 24 through an adhesive material 23. Then, the wafer 20 is thinned through a grinding process such that the metal material 21 can be exposed through a second surface of the wafer 20 opposed to the first surface with the solder pads 22. Meanwhile, the adhesive material 23 and the carrier 24 are removed. Thereafter, semiconductor chips 30 are disposed on the second surface of the wafer 20 that exposes the metal material 21 so as to electrically connect the wafer 20. Further, a plurality of solder bumps 31 is mounted on the solder pads 22 of the wafer 20 such that the semiconductor chips 30 can be electrically connected to external devices through the solder bumps 31.
During mounting of the solder bumps, the second surface of the wafer 20 with the semiconductor chips 30 faces downward and the first surface of the wafer 20 with the solder pads 22 faces upward so as to mount the solder bumps 31 on the solder pads 22. However, since the semiconductor chips 30 have different thicknesses, the wafer 20 cannot be disposed in a flat manner, which can lead to position deviation of the solder bumps 31 during the solder bump process and difficulty in cutting of the wafer during a singulation process.
Therefore, how to provide a semiconductor device with TSVs and a fabrication method thereof so as to overcome the above-described drawbacks has become urgent.
USPTO Backgrounds
USPTO Backgrounds