This section describes background subject matter related to the disclosed embodiments of the present invention. There is no intention, either express or implied, that the background information discussed in this section legally constitutes prior art.
On-chip electrical interconnections have previously been produced using “dual-damascene” fabrication techniques in which apertures are created through various layers of the device structure, and the apertures are filled with a conductive material to form the interconnects between layers and between device features located on individual layers. However, for chips which are based on 10 nm Node and smaller feature sizes, there are gap fill and resistivity constraints which make it impractical to use the “dual-damascene” fabrication techniques which have previously been relied upon.
In the time frame of 1998, the semiconductor industry saw copper metallization emerging as the next generation interconnect technology, as the feature size decreased to the deep sub-micron regime. Unlike the metallization which traditionally was aluminum at that time, copper metallization required a damascene process because copper is difficult to etch. In the damascene process, ILD (interlayer dielectric) is first deposited and patterned to define “trenches” where the metal lines will lie. Then the metal is deposited to fill the patterned oxide trenches and polished to remove excess metal outside the desired lines using chemical-mechanical polishing (CMP). (Park, T. et al. “Electrical Characterization Of Copper Chemical Mechanical Polishing”, Sematech, Austin, Tex. 1999). The article referenced describes early problems of copper dishing and oxide erosion during the polishing process. While solutions to various problems arising due to the use of CMP have been overcome during the past 14 years, the technology has progressed to a feature size of 10 nm Node or less with gap fill and resistivity increase problems which are expected to make the dual damascene process inadequate.
While the developers of the dual damascene process may have thought that feature sizes in the 10 nm range Nodes were unlikely in the near future due to patterning limitations, the development of half-pitch patterning by CVD spacer self alignment of the kind described by Christopher Bencher et al. in an article entitled: “22 nm Half-Pitch Patterning by CVD Spacer Self Alignment Double Patterning (SADP)”, Optical Microlithography XXI, edited by Harry J. Levinson, Mircea V Dusa, Proc. of SPIE Vol. 6924, 69244E-1, (2008) showed that there were techniques which could expand semiconductor feature size reduction. The fabrication of 10 nm Node feature sizes is now within reach, and a new technique for the creation of surface-available conductive interconnects for semiconductor chips is needed.
There are a number of published U.S. patents and patent applications which show structures and describe fabrication techniques which may be used to create feature sizes in the range of 22 nm and lower. For example, U.S. Pat. No. 8,232,210 B2 to Cheng et al. titled “Double Patterning Process For Integrated Circuit Device Manufacturing”, which issued on Jul. 31, 2012, from an application filed Sep. 18, 2009 describes a method of forming an integrated circuit (IC) device feature (and) includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features. (Abstract).
Additional description related to methods for multiple patterning to reduce spacing between features is provided in U.S. Published Application No. 2011/0159691 of Shih et al., entitled: “Method For Fabricating Fine Patterns Of Semiconductor Device Utilizing Self-Aligned Double Patterning”, which was published on Jun. 30, 2011. Further description related to multiple patterning to provide smaller feature sizes is provided in U.S. Pat. No. 8,431,320 B2 to Bae et al., entitled: “Self-Aligned Spacer Multiple Patterning Methods”, issued Apr. 30, 2013. Additional description related to a method of adjusting the geometry of photomask patterns is provided in U.S. Pat. No. 8,394,723 B2 to Valdivia et al., entitled: “Aspect Ration Adjustment Of Mask Pattern Using Trimming To Alter Geometry Of Photoresist Features”, issued Mar. 12, 2013. A “Double Patterning Process For Integrated Circuit Device Manufacturing” is described in U.S. Pat. No. 8,232,210 B2, issued Jul. 31, 2012.
There are a number of different techniques described for providing on-chip interconnect structures, such as in U.S. Patent Application Publication No. US 2013/0001801 A1 of Quinghuang Lin, titled: “Methods To Form Self-Aligned Permanent On-Chip Interconnect Structures”, published Jan. 3, 2013. This reference describes interconnect structures where at least one patterned dielectric layer includes differently sized conductive features embedded therein, where the differently sized conductive features are laterally adjacent to each other and are located at the same interconnect level. (Abstract) At Page 2, in Paragraph [0017], the reference teaches that the methods of the invention utilize a single exposure, double patterning technique which includes forming dielectric sidewall structures on the sidewalls of the patterned photoresist, which produce a permanently patterned dielectric material upon subsequent curing. The sidewall structures are subsequently used to narrow the width of openings in the patterned photoresist, as described in Paragraph [0018].
U.S. Pat. No. 8,354,339 B2 to Qinghuang Lin, entitled: “Methods To Form Self-Aligned Permanent On-Chip Interconnect Structures”, issued Jan. 15, 2012, describes the use of a dielectric sidewall structure over a patterned photoresist to narrow the width of openings present in the patterned photoresist. Subsequently, the patterned photoresist is removed, leaving a permanent patterned dielectric structure which is self-aligned and double patterned. An electrically conductive material is then formed within the narrowed width openings. (Abstract) U.S. Pat. No. 8,367,544 B2 to Cheung et al., entitled “Self-Aligned Patterned Etch Stop Layers For Semiconductor Devices”, issued Feb. 5, 2013, describes a method of forming a semiconductor device which includes patterning a layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogeneous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portions of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material. (Abstract).
U.S. Patent Publication No. US 2012/0280290 A1, of Khakifirooz et al., entitled: “Local Interconnect Structure Self-Aligned To Gate Structure”, published Nov. 8, 2012, describes the use of a common cut mask to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. In addition to the concern about alignment between gate structures and interconnect structures, there is a concern about electron scattering mechanisms in copper lines and the manner in which this behavior affects the extendibility of copper interconnects when line width or thickness is less than the mean free path. In an article entitled “Resistivity dominated by surface scattering in sub-50 nm cu wires” by R. L. Graham et al., published online 29 Jan. 2010 © 2010 American Institute of Physics [doi:10.1063/1.329022], the authors discuss electron scattering mechanisms in copper lines. Electron-beam lithography and a dual hard mask were used to produce interconnects with line widths between 25 and 45 nm. Electron backscatter diffraction was used to characterize grain structure. Temperature dependence of the line resistance determined resistivity which was consistent with existing models for completely diffused surface scattering and line-edge roughness, with little contribution from grain boundary scattering. As feature size shrinks, surface scattering and smaller grain size can lead to increases resistivity. The mean free path λ (MFP) of electrons in copper is said to be 39 nm, and this publication reports on copper lines of approximately this size. An analytical model was developed that describes resistivity from diffuse surface scattering and line-edge roughness. Examples of 22 nm half-pitch GDR structures were patterned into silicon. The authors concluded that with the physical limits of photolithography reached, and double patterning a certain path for device manufacturing in years to come, the spacer mask double patterning scheme clearly demonstrates the technical capabilities to meet roadmap requirements down to at least 22 nm half-pitch.
By using double patterning more than once it is possible to get pattern size down to about 10 nm half-pitch, for example. However, once the feature size is this small, it is very difficult to fill the wiring conduits with a metal. It is difficult to get a complete fill with metal through the space available for the metal to flow. In addition, it is very difficult to get alignment of connection surfaces when multiple layers are used to form metal lines and metal filled vias.
There remain a number of technical problems to be solved to enable the implementation of self-aligned interconnect structures at 22 nm half pitch and lower, and the present invention provides a fabrication technique for self-aligned interconnects which may be used for such implementation.
USPTO Backgrounds
USPTO Backgrounds