The present invention relates generally to chemical mechanical polishing of substrates.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semi-conductive or insulating layers. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar outer surface presents a problem for the integrated circuit manufacturer. If the outer surface of the substrate is non-planar, then a photo-resist layer placed thereon is also non-planar. A photo-resist layer is typically patterned by a photolithographic apparatus that focuses a light image onto the photo-resist. If the outer surface of the substrate is sufficiently non-planar, the maximum height difference between the peaks and valleys of the outer surface may exceed the depth of focus of the imaging apparatus. Then it will be impossible to properly focus the light image onto the entire outer surface. Therefore, there is a need to periodically planarize the substrate surface to provide a flat surface for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is then placed against a rotating polishing pad. A polishing slurry, including an abrasive and at least one chemically-reactive agent, may be supplied to the polishing pad to provide an abrasive chemical solution at the interface between the pad and the substrate. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. In addition, the carrier head may rotate to provide additional motion between the substrate and polishing surface. The interaction of the polishing pad and abrasive particles with the reactive sites on the substrate results in polishing.
An effective CMP process generates a substrate surface that is finished (lacks small-scale roughness) and flat (lacks large-scale profile). The polishing finish and flatness are determined in part by the force pressing the substrate against the pad and in part by the relative velocities of the substrate and the pad. However, a variety of factors, including non-uniform velocities, non-uniform slurry distribution and distortions in the polishing pad can cause the rate of polishing to vary spatially, resulting in non-uniform polishing of a semiconductor substrate surface.
USPTO Backgrounds
USPTO Backgrounds