Integrated circuit density has increased rapidly in recent years. The increase in density has been coupled with the requirement of developing test techniques that adequately test such high densities. One such technique for testing integrated circuits is called level sensitive scan design (LSSD) testing and is described by E. B. Eichelberger and T. W. Williams in an article entitled "A Logic Design Structure for LSI Testability" on pages 462-468 of the proceedings of the 14th Design Automation Conference. Basically, LSSD utilizes a plurality of control and observation points (typically implemented as a shift register string) within an integrated circuit (or board level) structure. The integrated circuit can perform self test by feeding data into a specifically configured shift register having feedback to generate data test patterns. This shift register string is referred to as a linear feedback shift register or pseudo random pattern generator. The data is allowed to shift through the Linear Feedback Shift Register (LFSR) for a defined number of scan clock cycles to generate pseudo random test data. As the pseudo random data shifts through the LFSR, pseudo random data also scans into the scan chains (storage registers) of the integrated circuit. The storage registers function as inputs into the logic of the integrated circuit to be tested. A data clock signal is issued to the logic sections, and as a result, the logic sections output test data is captured by additional storage registers. This captured data is then scanned into a Multiple Input Shift Register (MISR). The MISR stores this captured data. As the captured data is scanned into the MISR, the LFSR is generating new pseudo random data which is being scanned into the scan chains. This cycle is repeated until the test is complete with the resultant stored data forming a signature to be compared against a known signature or value. A determination of the functionality of the integrated circuit can then be made because of the comparison of the signature to a known value. This self testing technique has been described in "LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis" by Donald Komonytsky, IEEE 1982 International Test Conference, Digest of Papers, pages 414-424, and in "Self-Testing of Multiple Chip Modules" by Paul H. Bardell and William H. McAnney, 1982 International Test Conference, Digest of Papers, pages 200-204.
This technique is not, however, available to some parts of the integrated circuit structure because some logic cannot be directly stimulated by on board (or circuit) registers or the output of some logic cannot be captured by on board (or circuit) registers. This logic is typically the input/output logic associated with the drivers and receivers of the integrated circuit. This logic is generally referred to as boundary logic and typically requires a separate technique (referred to as boundary scan) to provide test coverage of the boundary logic between the primary input and the first LSSD shift register string and also between the final LSSD shift register string and the primary output.
One solution to this problem has been to place a multiplexer after the receiver of the integrated circuit but before the boundary logic in the data path. FIG. 1 illustrates this prior art approach. The integrated circuit 10 receives data through primary inputs 130 connected to a receiver 180. The output of the receiver 180 is connected to the input of a multiplexer 190. The output of a storage register 50 is also connected to the input of the multiplexer 190. The multiplexer is controlled by the self test signal 110 which switches the source of the data to the input boundary logic 20 between the receiver 180 and the storage register 50. The storage register 50 receives its input from a linear feedback shift register (LFSR) 30 which generates the test pattern for the internal logic 128 and the input boundary logic 20.
Either test or input data can then be sent to the boundary logic through the multiplexer. The multiplexer would toggle between sending test or input data to the boundary logic in response to a self test signal. The primary difficulties with this solution is that a multiplexer occupies a relatively large amount of expensive silicon area on the chip. More importantly, the multiplexer also introduces a delay of at least several nanoseconds into the data path. This delay will always exist because the multiplexer is part of the data path itself. Several nanoseconds of delay can be a very significant performance problem with many logic structure and this delay becomes increasingly more important as circuit performance increases. Finally, this solution does not address the problem of testing the output boundary logic because the multiplexer does not affect the data flow into or out of the output boundary logic.
USPTO Backgrounds
USPTO Backgrounds