The Tang System's “System-Design-On-Chip (SDOC™)” is the system on the Field-Programmable-Hybrid-Array (FPHA™) embedded in a single chip of Field Programmable System Chip(FPSC™). The unified system design environment has the System-Design-On-Chip (SDOC™) and the System-Design-On-Board (SDOB) been unified together in the same system design environment to be the unified system design platform. The Tang System's “System Design on-Chip (SDOC™)” is different from today's conventional “System Design On-Board (SDOB)”. After the schematic entry, the System Design On-Board (SDOB) needs to get the components from the different resources and have the vender to manufacture the Printed Circuit Board. After several weeks, the Printed Circuit Board comes back, the designer needs to soldier the components on the PCB, test and debug on it, etc. It takes about half year to finish one system-design-on-board iteration cycle. However, after the schematic entry, the System Design On-Chip (SDOC™) only takes five minutes to finish the download and verify the design. The System Design On-Chip (SDOC™) reduces the design iteration cycle from 6 months to be 5 minutes.
The FPHA embedded in a single chip of Field Programmable System Chip(FPSC™) has the Configurable Module Block (CMB™), Configurable Analog Block (CAB) and Configurable Logic Block (CLB). The supporting platform is constituted of the self-adaptive-Process & Temperature-compensation BandGap reference (SAPTC-BG), the frequency-programmable-Xtaless-Clock (FPXC™), PLLess™ CDR (PLL free Clock Data Recovery), Capless LDVR (Capacitor Less Low Drop Voltage Regulator), Inductorless SMPS (Inductorless Switch Mode Power Supply), etc. The flash switch for the programmable connectivity and the flash memory for the look-up-table (LUT) can reduce the FPHA chip area a lot.
The Frequency Programmable Xtaless Clock (FPXC™) has the following eight characteristics to make the Xtaless clock being implementable.    1. Self-adaptive process-temperature bandgap reference compensation    2. Gain-Boost Amplitude Control resonator    3. Active MOS Parametric Varactor Diode Compensation    4. RL=RC over Process and Temperature for frequency Compensation    5. Toroid Inductor and MIM Cap Temperature (Minor Process) Compensation    6. Double Gain-Boost/Glitch Eliminated LCO (LC Oscillator)    7. Capless LDVR/(Zero Substrat Noise)    8. Frequency Programmable Clock with capacitor arrayThe frequency can be programmed from MHz to GHz for an Frequency with COX (Oxide capacitance variance) process and temperature compensation.
The Field Programmable Radio Array FPRA is similar to the high frequency Field Programmable Analog Array FPAA. However, the FPRA has a lot of the on-chip inductors. The conventional on-chip inductor occupies a lot of chip area. It needs the miniature on-chip inductor. The miniature inductor enables the Field Programmable Radio Array (FPRA), Frequency Programmable Xtaless Clock FPXC, PLLess CDR (Clock Data recovery) and Field Programmable Switch Power Array (FPSA) being implementable on chip to have the system design on chip (SDOC) embedded in a single chip of Field Programmable System Chip(FPSC™).
For the high-speed and high frequency streaming data, the FPRA and FPAA are in the pipeline architecture. Not only the digital circuit has the pipeline architecture, to have the long connectivity, there are the pipeline analog buffer and pipeline digital buffer in the connectivity. For the analog buffer and digital buffer themselves, there are the pipeline circuit configurations, too. There are three hierarchical layers of pipeline architecture.
Furthermore, with the SDOC on FPHA embedded in a single chip of Field Programmable System Chip(FPSC™), the hot product of the Automobile Infotainment Center (AIC) is reduced to be the Mobile Infotainment Center (MIC) embedded in a single chip of Field Programmable System Chip(FPSC™).
USPTO Backgrounds
USPTO Backgrounds