1. Field of the Invention
The present invention relates generally to the field of digital phase-locked loop circuits. More particularly, the present invention relates to a digital phase locked loop utilizing a high-order sigma-delta modulator which can be used in conjunction with an analog-to-digital converter, a digital-to-analog converter, and a digital-to-digital converter.
2. Discussion of the Related Art
FIG. 1 illustrates a phase-locked loop circuit which has been used in conjunction with, for example, an analog-to-digital converter or a digital-to-analog converter to lock to an external clock signal. The phase-locked loop circuit of FIG. 1 has been used in an AD28msp01 Echo-Cancelling Modem Analog Front End circuit, made by Analog Devices, Inc., One Technology Way Norwood, Mass. U.S.A. 02062-9106. The AD28msp01 is a complete analog front end for high performance DSP-based modems. The device includes all data conversion, filtering and clock generation circuity needed to implement an echo-cancelling modem with one companion digital signal processor. Further information on the AD28msp01 can be obtained from Analog Devices, Inc. An advantage of the circuit of FIG. 1 is that, for example, an analog-to-digital converter or a digital-to-analog converter, used in conjunction with the phase-locked loop of FIG. 1, can be synchronized to an external clock signal and need not be limited to an on-chip master clock signal.
In the phase-locked loop circuit 10 of FIG. 1, an external clock signal is applied on line 12 to a phase detector 14 which produces a signal 18 proportional to a phase difference between the external clock signal on line 12 and a conversion signal (TCONV) on line 16. The conversion signal will be described in more detail hereinafter. The output signal of the phase detector, on line 18, is filtered by a loop filter 20. Typically, the loop filter has a high gain, preferably infinite, so that the phase-locked loop can always lock to the external clock signal 12 with no phase error. In addition, the loop filter acts a low-pass filter.
An output of the loop filter, on line 22, is fed to a first-order, two-bit sigma-delta modulator 24. The sigma-delta modulator 24 produces, on line 26, a two-bit digital word which is used to control a variable divider 28. As will be further explained hereinafter, the sigma-delta modulator 24 modulates the signal on line 22, which is representative of the frequency of the external clock signal on line 12. An example will serve to illustrate this function.
Assume that the data rate of the synchronization signal on line 12 is 7.2 kHz. Further assume that a frequency of a master clock signal, on line 30, fed to the variable divider 28 is 13.824 MHz. If the desired data rate of the signal on line 16 is 7.2 kHz, a signal on line 32, fed to a fixed divider 34 having a fixed dividing ratio (M) of, for example, 240, must be at a data rate of 1.728 MHz. Therefore, the two-bit code output on line 26 by the sigma-delta modulator 24 must instruct the variable divider 28 to divide the master clock signal by a factor of 8 in order to get the 1.728 MHz signal desired.
One of the limitations of this phase-locked loop circuit is that the phase-locked loop 10 is limited to a fixed operating range around a center frequency of the external clock signal, in order to keep the signal 32 at approximately 1.728 MHz. The 1.728 MHz is required by the analog-to-digital converter or the digital-to-analog converter of the Ad28msp01 analog front end chip to clock a 1-bit analog-to-digital converter for converting an analog signal to a 1-bit digital signal at an oversampled rate or to clock a 1-bit digital-to-analog converter for converting an oversampled digital signal to an analog signal. The fixed range of operation of the phase-locked loop 10 is thus a function of the dividing ratio M of the variable divider and the center frequency of the external clock signal 12. In addition, another limitation of the phase-locked loop circuit 10 is that the variable divider must be instructed what frequency the external clock signal 12 is at, in order to choose the variable dividing ratio M. Thus, the phase-locked loop circuit 10 has a limited range over which it can lock to an external clock signal, and it must be instructed as to the frequency of the external clock signal.
In addition, another limitation of the phase-locked loop circuit 10 is that a non-linear mapping results between the two-bit code, output, on line 26, by the sigma-delta modulator and the resulting conversion frequency signal TCONV. In other words, if the frequency of the conversion signal TCONV is plotted as a function of the two bit code, on line 26, as shown in FIG. 2, a non-linear relationship results. A linear relationship is ideally desired, so that the conversion signal TCONV can be changed in linear steps and so that the steps are fixed across the dynamic operating range of the phase-locked loop 10. Thus, a disadvantage of the phase-locked loop circuit 10 is that the conversion frequency signal cannot be linearly incremented by stepping through the various steps of the 2-bit code 26.
Still another limitation of the this phase-locked loop circuit 10 is that, due to the infinite gain of the loop filter 20, the circuit is characterized by undesirable phase noise. The phase noise results from the gain of the loop itself; the higher the gain, the higher the phase noise. Thus, an inherent trade off exists in responsiveness of the phase-locked loop to the external clock signal, which is a function of the loop gain, and the phase noise of the phase-locked loop. The infinite gain of the loop filter 20, of the phase-locked loop circuit 10, results in ideal responsiveness of the phase-locked loop 10 to the external clock signal, but also produces unwanted amplified phase noise.
Therefore, an object of the present invention is to provide an improved digital phase-locked loop which provides one or more of the advantages recited herein.
USPTO Backgrounds
USPTO Backgrounds