1. Field of the Invention
The present invention relates to an image pickup device having an analog-to-digital (AD) conversion circuit.
Priority is claimed on Japanese Patent Application No. 2010-268559, filed Dec. 1, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
FIG. 7 is a block diagram illustrating a partial configuration of an AD conversion circuit of the related art for measuring an amount of time called a time-to-digital converter (TDC) type AD conversion circuit. A circuit shown in FIG. 7 includes an annular delay circuit 201 in which a plurality of delay devices NAND0 and INV1 to INV8 are connected in a ring shape, a latch circuit 202, which retains an output of the annular delay circuit 201, a binarization circuit (a full-encoder circuit) 203, which binarizes a value retained in the latch circuit 202, a counter circuit 204, which counts one of outputs of the annular delay circuit 201 as a count clock, and a memory circuit 205, which retains outputs of the binarization circuit 203 and the counter circuit 204.
Next, an AD conversion operation will be described. FIG. 8 is a timing chart illustrating an operation timing of the AD conversion circuit of the related art shown in FIG. 7. A logical state of a start pulse StartP is transitioned from a low (L) state to a high (H) state, so that logical states of the delay devices constituting the annular delay circuit 201 are varied in order. Thereby, the pulse circulates within the annular delay circuit 201. After the passage of a predetermined amount of time, the latch circuit 202 retains (latches) an output of the annular delay circuit 201. As shown in FIG. 8, the output of the annular delay circuit 201 corresponds to any one of 9 states (a state 0 to a state 8). The output of the annular delay circuit 201 retained (latched) in the latch circuit 202 is fully encoded (i.e., parallelly encoded) by the binarization circuit 203, so that binary data (a lower count value) is generated. The counter circuit 204 counts an output of the delay device INV8 as a count clock, and generates a count value (a higher count value). The lower count value and the higher count value are retained in the memory circuit 205, and are output to a subsequent circuit as digital data.
The AD conversion circuit as described above may be applied to an image pickup device. Japanese Unexamined Patent Application, First Publication No. 2009-033297 discloses an example in which the AD conversion circuit is arranged inside a column unit provided in correspondence with each pixel column and a signal output from a pixel is AD-converted.
In an image pickup device using the AD conversion circuit according to the example of the related art, when subtraction (correlated double sampling (CDS) processing) is carried out between a first pixel signal corresponding to a reset level when a pixel is reset and a second pixel signal corresponding to an amount of incident light of the pixel, the first pixel signal and the second pixel signal are retained in a column unit, the pixel signals are output in parallel to a binarization circuit and a subtraction (CDS processing) circuit provided outside of the column unit, and digital data is obtained.
In the above-described image pickup device of the related art, an example in which lower phase signals, which are outputs of an annular delay circuit, (or input signals of the latch circuit) have 8-state data and a higher count value, which is an output of a counter circuit, has 9-bit data, will be described.
Naturally, it is necessary to transmit the first pixel signal and the second pixel signal outside the column unit at a high speed with an increase in the number of pixels. Furthermore, if binarization and subtraction (CDS processing) are not carried out within the column unit, it is necessary to output a total of 34 signals including a total of 17 signals including 8 lower phase signals and 9 bits of a higher count value for the first pixel signal and a total of 17 signals including 8 lower phase signals and 9 bits of a higher count value for the second pixel signal.
If the 34 signals are output in accordance with a phase (in synchronization) at a high speed and the binarization and subtraction (CDS processing) are carried out, a circuit scale becomes large and its control becomes complicated. This becomes a factor that hinders speed-up or an increase in the number of pixels in the image pickup device using the above-described configuration. If it is possible to carry out the binarization and subtraction (CDS processing) within the column unit, phase adjustment is simplified because it may be good when 12 bits, that is, 12 data signals, are only output outside the column. Thereby, it is possible to further increase speed-up or the number of pixels.
USPTO Backgrounds
USPTO Backgrounds