For forming a high-frequency local clock from a lower-frequency forwarded clock, a phase-locked loop (PLL) may provide better jitter filtering than a multiplying delay-line loop (MDLL), e.g., when there is dominant un-correlated jitter between the phase of the forwarded clock and the received data. A MDLL, however, can provide better jitter tracking for data transmission systems using a forwarded clock than a PLL. In a related art MDLL, the rising edge of the forwarded clock is fed into the delay line directly, similar to a delay line loop (DLL). This has the advantage that, because a DLL is an all-pass in jitter, the MDLL can track all correlated jitter. The related art MDLL has the disadvantage, however, that the front-end selection multiplexer may have a different propagation delay than the delay elements in the delay chain that follows it, leading to non-uniform output phases at the outputs of the front-end selection multiplexer and the subsequent delay elements. This non-uniform delay can cause errors in the output phase of a phase interpolator using the output signals of the front-end selection mux and the subsequent delay elements. Moreover, in the related art MDLL, only the rising edge is fed into delay line, causing M-cycle accumulated jitter.
Thus, there is a need for a multiplying delay-line loop design that provides uniform output phases with reduced accumulated jitter.
USPTO Backgrounds
USPTO Backgrounds