The present invention relates to a microcomputer having a central prossing unit (CPU) and an electrically erasable and programmable nonvolatile memory (caller hereinafter "EEPROM") fabricated on a single semiconductor chip.
In a microcomputer, a static type random access memory (SRAM) is employed in general as a data memory for storing data to be processed and/or processed resultant data. However, SRAM has an unavoidable problem that data stored therein are destroyed when a power voltage applied thereto is cut off. Therefore, it has been proposed to employ, as a part of the data memory, EEPROM into which data can be written and from which data can be read out, and further EEPROM holding data written therein even after a power voltage applied thereto is cut off.
A data write-processing to EEPROM consists of a data erase-operation, which is first performed to erase data already stored in an address into which new data is to be written, and a data write-operation, which is thereafter performed to write the new data into that address. It is well known in the art that such a data write-processing requires a time period of about ten msec. This time period is extremely long as compared with the instruction execution speed of CPU. If CPU manages the data write-processing to EEPROM, therefore, the program execution efficiency is deteriorated remarkably.
An automaton circuit is thus provided to perform and manage the data write-processing to EEPROM in place of CPU. When CPU encounters a data write-instruction to EEPROM, it supplies the write-processing automaton circuit only with a write-command signal, data to be written and address information for selecting a desired address of EEPROM. Thereafter, the operation of CPU is shifted to execute a next instruction. On the other hand, the write-processing automaton circuit is initiated to first erase data stored in the selected address and then write new data into that address. Thus, CPU can execute the program during the data write-processing to EEPROM.
However, since the program execution advances during the data-write processing to EEPROM, there occurs a case that CPU encounters again a data write-instruction to EEPROM before the current data write-processing to EEPROM is completed. Also in that case, CPU generates a data write-request to the automaton circuit and thereafter shifts to execute a next instruction. On the other hand, since the data write-processing responsive to the previous data write-request is still being performed in EEPROM, the new data write-request is disregarded. As a result, data to be written into EEPROM is lost to cause a misoperation.
USPTO Backgrounds
USPTO Backgrounds