The present invention relates to an engineered substrate comprising a III-V compound semiconductor material thereon and a method for manufacturing such a III-V compound semiconductor material on a semiconductor substrate.
Development of high performance III-V complementary metal-oxide-semiconductor (CMOS) devices, a type of CMOS utilizing high mobility III-V materials (such as gallium arsenide or indium gallium arsenide as channels instead of silicon, has been suffering from the difficulties of epitaxially growing defect-free III-V materials on silicon substrates.
One difficulty of epitaxially growing III-V materials on silicon substrates is that there is a large lattice-mismatch between the lattice constants of III-V materials and the lattice constant of silicon. Another such difficulty is the formation of anti-phase domain boundaries (APB) which are actually defects that act as deep level nonradiative recombination centers and consequently deteriorate the electrical performance of the device significantly.
To avoid APB, silicon (001) or germanium (001) substrates with a miscut angle larger than 2 degrees (e.g., 6 degrees) may be used. However, using miscut substrates induces additional problems in the epitaxial growth of the III-V compound materials on patterned wafers, such as surface morphology and crystal quality dependence on orientation (non-isotropy), resulting in a significant barrier for their acceptance in CMOS device fabrication. In addition, the actual impact of the miscut on carrier transport is not clear.
Yet another drawback is that miscut silicon (001) substrates are not standard in silicon CMOS industry. Consequently, it is of great interest to grow APB free III-V materials on the largely used (001) oriented silicon substrates.
USPTO Backgrounds
USPTO Backgrounds