The present invention relates to a wiring substrate and a method for manufacturing a wiring substrate.
In the prior art, in order to achieve a high density wiring pattern for a wiring substrate used in a semiconductor package or the like, a build-up wiring substrate is known in which a build-up wiring layer and an insulating layer are laminated on upper and lower surfaces of a core substrate.
The density of semiconductor chips mounted on build-up wiring substrates have become high. Thus, there is a demand for build-up wiring substrates that further increase the wiring pattern density and reduce the substrate thickness. In a build-up wiring substrate, the layered portion of a wiring layer and insulating layer can be formed thinly through a build-up process. However, the portion of a core substrate is required to have a suitable thickness in order to provide the wiring substrate with rigidity. Consequently, there have been limits on the extent to which the thickness of the entire wiring substrate can be reduced. Thus, a so-called careless substrate has been proposed, which is a wiring substrate that excludes the core substrate (support member) to further reduce the thickness of the wiring substrate (refer to, for example, Japanese Patent Application Publication No. 2000-323613).
The basic processing for a coreless substrate prepares a provisional substrate as a support body, forms a pad on the provisional substrate, laminates a desired number of build-up wiring layers and insulating layers, and finally removes the provisional substrate. In such a coreless substrate, unlike a conventional build-up wiring substrate, there is no core substrate. Thus, the thickness of the wiring substrate can be reduced.
A pad formed on the support body generally has a laminated structure including a plurality of metal layers. Such a typical laminated structure may be a two-layer structure, which includes a gold (Au) layer and a nickel (Ni) layer, or a three-layer structure, which includes an Au layer, a Pd layer, and an Ni layer. A pad having such a structure has superior wire bonding properties. However, when the pad is connected to lead (Pb)-free solder, the Ni forms a trialloy with tin (Sn) and copper (Cu). This decreases the drop impact resistance.
Another typical laminated structure is a two-layer structure formed by an Organic Solderability Preservative (OSP) process including a film (OSP film) of water-soluble preflux and a Cu layer. In a pad having such a structure, the drop impact resistance does not decrease. However, since no Ni is present, the OSP film is prone to oxidization and discoloration.
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