Current trends in integrated circuit packaging require a greater number of leads or solder bumps in a smaller and thinner form factor. To that end, the applicants have developed IC packaging technology relating to plating desired areas onto a metal substrate thereby forming several plated areas that serve as contacts, leads, die attach pads, or the like in Co Pending U.S. patent application Ser. No. 12/688,602. However, as IC developers produce ICs having a larger number of input/outputs (I/O), a greater number of contacts is required in the corresponding IC package. As the density of the contacts, or leads, are increased, what results is less robust IC packages. In some instances, the plated contacts or other structures peel away from the finished IC package. Such peeling is exacerbated by requirements of more thin packages that in turn require more thin plating.
Furthermore, in some applications, it is desirable to have a semiconductor package that stands off from the application board that it is mounted to. IC packages having standoffs can be easier to mount onto a printed circuit board (PCB) or whatever other application that the package is being mounted to. In some applications, standoffs were mounted to contact pads on IC packages to provide the gap in space between the PCB and the IC package. However, the additional step of mounting standoffs proved to be unwieldy, costly, and not robust. To that end, makers of IC package solutions have developed methods wherein a monolithic sheet of copper substrate is selectively plated on both sides to form die attach pads and contacts. When the copper is etched away, the remaining portions between the plated areas form standoffs.
U.S. Pat. No. 6,451,627 to Coffman discloses a method and eventual apparatus wherein areas corresponding to contact leads and die attach pads are plated on one side of a monolithic copper substrate. On the other side of the substrate, Coffman teaches the formation of “mold locks.” Coleman requires separate plating steps for each side of the substrate, adding process steps and cost. Coleman does not allow for routing traces under the die, thereby limiting contact density. U.S. Pat. No. 6,306,685 to Liu discloses a method and corresponding apparatus wherein both sides of a substrate are plated similarly, however Liu does not allow for routing traces under the die either, and similarly suffers from a lack of contact density. U.S. Pat. No. 7,671,452 to Bayan teaches contact traces under the die, however Bayan uses a standard pre-etched leadframe wherein the semiconductor die is placed upon the routing traces. However, the use of a pre-formed leadframe precludes plated structures that allow for the thinnest possible form factors. U.S. Pat. No. 7,095,096 to Mostafazadeh and US Pat. Publication 2010/0224971 to Li teach methods requiring multiple etching steps or other separate steps for forming routing and contact leads. As mentioned above, additional steps add unacceptable cost. It is well known that the semiconductor manufacturing industry is heavily cost driven, and semiconductor packages having fewer processing steps, thereby costing less to produce, are highly desirable.
USPTO Backgrounds
USPTO Backgrounds