Conventionally, there is known an active matrix-type display device, in which a plurality of gate bus lines (scanning signal lines) and a plurality of source bus lines (video signal lines) are provided in a grid pattern, and a plurality of pixel formation portions are provided in matrix corresponding to respective intersection points between the signal lines. Each pixel formation portion includes a thin film transistor (Thin Film Transistor: TFT) as a switching device and a pixel capacitance for holding a pixel value. A gate terminal of the thin film transistor is connected to the gate bus line that passes the corresponding intersection point, and a source terminal of the thin film transistor is connected to the source bus line that passes the same intersection point. The active matrix-type display device is further provided with a gate driver (scanning signal line drive circuit) that drives the gate bus lines and a source driver (video signal line drive circuit) that drives the source bus lines.
Video signals indicating the pixel values are transmitted through the source bus lines, but a single source bus line cannot transmit video signals indicating the pixel values of more than one row at the same time (simultaneously). Accordingly, the video signals are written to the pixel capacitances included in the pixel formation portions sequentially by row. Thus, a gate driver including a shift register having a plurality of stages is used to sequentially select the plurality of gate bus lines for a predetermined time period.
The shift register operates based on clock signals. The clock signals are supplied to each stage of the shift register from clock signal main lines provided on an outer rim of a panel. Further, the clock signals are typically supplied to a plurality of thin film transistors included in the shift register. Accordingly, an area for laying out the shift register is required between an area for providing the clock signal main lines and an area for providing the pixel formation portions. This constitutes one reason of an increase of the area for laying out the shift register. In particular, in a case of a display device having a shift register that operates based on a large number of clock signals, an increase of a picture-frame area of the panel becomes problematic. Further, in a case in which a plurality of panels cut out from a mother glass have a relatively narrow area that can be used as a picture-frame area (small or medium size panel, for example), it becomes difficult to form a shift register in a picture-frame area. This produces a useless area in a panel, and a yield ratio is markedly reduced.
It should be noted that prior art documents as listed below are known relating to the present invention. Patent Documents 1 to 7 disclose a structure of a gate driver including a shift register. According to these documents, clock signals necessary for an operation of the shift register are supplied to each stage of the shift register from clock signal main lines as shown in FIG. 26. For example, as shown in FIG. 27, Patent Document 1 discloses decreasing an interval between signal lines of agate driving unit by providing contacts (square boxes with diagonal lines) and zigzag leading lines to connect between main lines and each stage of the gate driving unit. Further, Patent Document 7 discloses connecting clock leading lines from the clock signal main lines to two adjacent stages in a single shift register, and that the clock signals are shared by the two stages (see FIGS. 4 and 6 of Patent Document 7). The same structure is also disclosed in Patent Document 6 (see FIGS. 3 and 5 of Patent Document 6). According to Patent Documents 6 and 7, the number of types of the clock signals required for the operation of the shift register is two (CK1 and CK2), and the number of clock leading lines is one for each stage of the shift register.
USPTO Backgrounds
USPTO Backgrounds