The present technique relates to an apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers.
One known technique for improving performance of a data processing apparatus is to provide circuitry to support execution of vector operations. Vector operations are performed on at least one vector operand, where each vector operand comprises a plurality of data elements. Performance of the vector operation then involves applying an operation repetitively across the various data elements within the vector operand(s).
Vector processing circuitry (often referred to as SIMD (Single Instruction Multiple Data) processing circuitry) may be used to provide multiple lanes of parallel processing in order to perform operations in parallel on the various data elements within the vector operands.
Although the use of such vector operations can result in significant performance benefits, a problem that arises is how to efficiently move the data elements required for the vector operations between memory and vector registers used to store the vector operands. In particular, the individual data elements required may be stored within a series of data structures within memory, where each data structure may include multiple related data elements, for example X, Y and Z coordinate values, red, green and blue pixel values, real and imaginary parts of complex numbers, etc. However, to enable efficient use of vector operations it is useful if a vector register stores a vector operand consisting of a series of corresponding data elements from a plurality of such data structures. Hence, using the above example of X, Y and Z coordinate values, it may be desirable for one vector register to store multiple X coordinate values, another vector register to store multiple Y coordinate values and a further vector register to store multiple Z coordinate values.
It would be desirable to provide a technique for efficiently transferring a plurality of data structures between memory and a plurality of vector registers.
USPTO Backgrounds
USPTO Backgrounds