This patent specification generally relates to semiconductor memory devices such as static RAMs (Random Access Memory), and more particularly to circuits capable of saving current, and semiconductor memory devices capable of giving operation assurance by adjusting an activation timing of a sense amplifier or a word line using a dummy memory circuit.
As a current saving system, it is known that a prescribed circuit can perform autogenous control by simulating a dummy operation in a semiconductor memory device A dummy memory circuit is a typical example of such a circuit, and changes an internal activation signal to a deactivation condition after simulating reading from an applicable (dummy) memory cell and detecting that the reading has been completed.
After a prescribed memory cell is selected and reading of data therefrom is started, the data is carried to a sense amplifier via an applicable bit line pair, and a slight potential difference existing therebetween is amplified there. An output from the sense amplifier is finally output from an output circuit. Since the output circuit generally includes a prescribed latching circuit capable of latching data, the sense amplifier need not remain activated after the output is latched.
A dummy memory circuit is frequently employed so as to monitor the output condition of a sense amplifier, and control a timing to latch the output therefrom and the sense amplifier activation.
In addition, when data is read, the potential charged to a bit line need not go to a level greater than that the sense amplifier can detect. Full swing of the change in the potential of the bit line is generally suppressed by controlling an applicable word line, again with a dummy circuit.
When performing control with a dummy memory circuit, activation of a sense amplifier and a word line should be controlled after confirming absolute output from a sense amplifier.
However, if an operation margin is excessive, a memory circuit may exhibit low performance characteristics. In contrast, if a timing of changing to a deactivation condition is too early, data output might be erroneous. Thus, a certain amount of operation margin should be generally utilized.
Further, a circuit should output correct data even under unforeseeable conditions such as variations in performance of a sense amplifier and a memory cell, variations of capacity or resistance of a bit line, etc., caused by manufacturing variations. In addition, since current is consumed in a control circuit itself, a system capable of securing an operation margin as readily as possible is generally preferable.
A dummy circuit is typically located far from a word line driver, and a prescribed system is provided so as to attempt to secure the operation margin. For example, Japanese Patent Application laid Open No. 8-273365 refers to a system in which an operation margin in operation timings for controlling activation of a sense amplifier and an output latching circuit is secured by a dummy memory cell located in the remotest end of a word line. Specifically, such an operation margin is secured by increasing a parasitic capacity (of a bit line) by increasing a line width of a dummy bit line pair and reducing its line interval. As an alternative, downsizing of a driving capability of the dummy memory cell is also proposed therein.
However, since the operation margin created by the above-described system is secured by changing the performance of the dummy cell and dummy bit line, the operation margin varies with process variations and a change in power supply voltage.
Further, an asynchronous type semiconductor memory capable of activating each section in response to an input of address data generally has no time for enabling a pre-charge circuit to pre-charge a memory cell array, unlike a synchronous type semiconductor memory capable of activating respective sections in accordance with a change in a signal level of a clock signal. Thus, the asynchronous type semiconductor memory should preserve a pre-charge time period using a pre-charge control signal xe2x80x9cPRCxe2x80x9d. In such a situation, if the pre-charge time period is too short, previous data remains in a bit line and disturbs reading of new data. In contrast, if the pre-charge time period is too long, data reading is delayed. Accordingly, optimizing the pre-charge time period can improve operational performance.
Thus, such a pre-charge time period just after data writing is an objective to be improved. Since a potential difference between a bit line pair is greatest in a data writing condition (i.e., a full-swing condition), a pre-charge time period xe2x80x9ctxe2x80x9d for the subsequent reading should be made longer. Each entire pre-charge time period is generally set on the basis of the time period xe2x80x9ctxe2x80x9d. However, there exists a problem in such a system that the pre-charge time period is too long for a data reading cycle. In addition, a pre-charge time period can not easily adapt to a change in memory size. Accordingly, a particular pre-charge time period should be designed for a particular memory size. Otherwise, the pre-charge time period should include a margin capable of accommodating a variety of memory sizes.
There exists a system having a dummy memory circuit capable of adjusting a pre-charge time period. The system employs a detection circuit capable of detecting a pre-charge condition of a bit line of the dummy memory circuit, and controls a pre-charge circuit to activate in accordance with a pre-charge condition detected by the detection circuit. Meaningless pre-charge is omitted during a data reading cycle, and a memory size change can be accommodated. However, a pre-charge condition just after data writing can not be easily followed and improved.
Since it is generally a main purpose of utilizing a dummy memory circuit to save current upon data reading, a dummy memory circuit does not include a (dummy) write buffer for data reading. Thus, upon a data writing condition, a bit line pair BL1 and BL1B exponentially is brought to a full-swing condition by a write buffer comprising a transistor having a large gate size as illustrated in FIG. 12. In contrast, a dummy bit line pair DBL and DBLB represents a small change in a potential difference as in the data reading condition.
Thus, when data writing is immediately followed by data reading from another storage location in a memory, such as in a high speed SRAM, whose data reading and writing cycles are short, there exists a difference between a first potential difference between a bit line pair, and a second potential difference between a dummy bit line pair. As a result, a pre-charge time period can not sufficiently be monitored, and data of the memory cell is sometimes destroyed or data is erroneously read.
Accordingly, an object of the system and method disclosed herein is to address and resolve the above and other problems and provide a new semiconductor memory that includes a dummy memory circuit configured to simulate dummy data reading from an applicable dummy memory cell when data reading is performed. The dummy memory circuit may include a plurality of dummy memory cells each selected together with a corresponding memory cell for reading. The dummy memory cell may include prefixed complementary data. A dummy bit line pair may be connected to each of the plurality dummy memory cells. A dummy pre-charge circuit may be provided so as to pre-charge the dummy bit line pair when data reading is performed. A dummy sense amplifier may be provided so as to amplify a potential difference between the dummy bit line pair. The dummy sense amplifier may output a control signal for controlling the semiconductor memory when the potential difference is at a prescribed level. The dummy pre-charge circuit may provide the dummy bit line pair with respective charge amounts oppositely corresponding to the complementary data when data reading is performed.
USPTO Backgrounds
USPTO Backgrounds