1. Field of the Invention
The present invention relates to a semiconductor memory having an error correction function.
2. Description of the Related Art
A semiconductor memory that can enable or disable a function that corrects an error of data that are read from a memory cell has been proposed (for example, in Japanese Unexamined Patent Application Publication No. 2004-005951). This semiconductor memory also has an output compression circuit that determines whether the number of bit errors can be corrected by the error correction circuit.
On the other hand, so-called data compression test technology that writes data received from one data terminal (test terminal) to not only a memory cell corresponding to the data terminal, but memory cells corresponding to other data terminal has been proposed (for example, in Japanese Unexamined Patent Application Publication No. 2001-210099). In the data compression test, a defect of a semiconductor memory is detected when data of a plurality of bits that are read from memory cells are not coincident. When a data compression test is performed, the number of semiconductor memories mounted on a test evaluation board increases and the test cost decreases.
A usual semiconductor memory having an error correction circuit does not have a data compression test function, which decreases the number of data terminals necessary for testing the memory. Normally, when a memory area to be tested increases in a data compression test, data terminals from and to which compression data are read and written are required. Thus, the number of terminals for data to test the semiconductor memory increases, whereas the number of semiconductor memories that can be mounted on a test evaluation board decreases. Since the number of semiconductor memories that can be tested at a time decreases, the test time per memory increases and the test cost thereof increases.
USPTO Backgrounds
USPTO Backgrounds