1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to vertical channel flash memory devices.
2. Description of Related Art
To maintain enough current through the channel of a flash memory cell more area is required for a traditional ETOX (nonvolatile memory with a metal drain line that contacts each drain region in a column of drain regions) structure since the channel is parallel to the wafer surface.
During the programming and erasing procedure, the tunneling electron always needs to pass through part of the channel area which results in charge trapping and transconductance degradation.
See as follows:
U.S. Pat. No. 5,451,538 of Fitch et al. for "Method for Forming a Vertically Integrated Dynamic Memory Cell";
U.S. Pat. No. 5,467,305 of Bertin et al. for "Three-Dimensional Direct-Write EEPROM Arrays and Fabrication Methods";
U.S. Pat. No. 5,495,441 of Hong for "Split-Gate Flash Memory Cell";
U.S. Pat. No. 5,587,949 of Bergemont et al. for "Method for Programming an ETOX EPROM or Flash Memory When Cells of the Array are Formed to Store Multiple Bits of Data"; and
U.S. Pat. No. 5,595,927 of Chen et al. for "Method for Making Self-Aligned Source/Drain Mask ROM Memory Cell Using Trench Etched Channel".
USPTO Backgrounds
USPTO Backgrounds