The preferred embodiments relate to semiconductor devices and, more particularly, to isolated III-N semiconductor devices.
Integrated circuit devices are typically formed in connection with various semiconductor materials. For some applications these materials include compound materials such as the known III-N semiconductors, which are known to include combinations of elements from group III of the periodic table. Such elements include aluminum, gallium, indium, and possibly boron, and as group III-N semiconductors they are combined with nitrogen, such that each element contributes to the overall semiconductor material. Examples of III-N semiconductor materials are gallium nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride. Moreover, III-N semiconductor devices may be included with other silicon based devices by sharing a common silicon substrate or wafer, where accommodations are made for the III-N semiconductor devices due to the differences between the compound semiconductors and the underlying silicon substrate.
The above approach has various benefits, for example in connection with gallium nitride (GaN) devices. Such devices may include, for example, light emitting diodes (LEDs), solar cells, radiation-resistant devices, and high temperature or high voltage devices, commonly including transistors. These devices, however, may suffer from certain drawbacks, including possible instabilities when mixed with different devices based on either structure or functionality.
By way of further background, FIG. 1 illustrates a schematic of a prior art half bridge 10 that may be implemented using GaN transistors, and that as implemented may suffer drawbacks as observed by the present inventors.
Specifically, half bridge 10 includes two GaN transistors T1 and T2. As is well known, the drain D(T1) of transistor T1 is connected to a first rail voltage (shown as Vline), and the source S(T2) of transistor T2 is connected to a second rail voltage (shown as ground). As such, transistor T1 is referred to as the high side, and transistor T2 is referred to as the low side. The source S(T1) of transistor T1 and the drain D(T2) of transistor T2 are connected and provide the output, Vout, for half bridge 10. The transistor gates may be connected to various signals as shown by way of illustration with a generic input block 12; the particular signals are not of particular significance for the present discussion, other than to note that they are such that the transistors T1 and T2 operate in complementary fashion, that is, one is on while the other is off, and vice versa. Lastly, as is typical in various transistor configurations, each of transistors T1 and T2 has its source connected to the substrate of the respective transistor, where such a connection is sometimes also referred to as a backgate.
In operation, transistors T1 and T2 are on one at a time and typically at a 50 percent duty cycle, so Vout tends toward Vline when the high side transistor T1 is on and toward ground when the low side transistor T2 is on. Based on the load and input voltages, such circuit may have various uses, including power electronics such as in a converter, switching, and the like. While half bridge 10 has various uses and is well-known, it is recognized in connection with the preferred embodiments that issues may arise in ideally implementing the bridge using GaN technology. Specifically, the source-to-backgate connections can cause leakage, instability, or other performance-diminishing issues due to differing voltages being connected to a same substrate. For example, consider a high-voltage application, where Vline is 400 volts. When the high side transistor T1 is on, then Vline, minus the drop across transistor T1, is connected to Vout. If, for example, that voltage drop is 1 volt, then when transistor T1 is on, Vout=399 volts. Accordingly, the source-to-backgate connection of transistor T1 couples the backgate to 399 volts, while at the same time the source-to-backgate connection of transistor T2 couples the backgate to ground, thereby creating a considerable leakage path between the two transistors. As an alternative, the backgate connections instead could be implemented by connecting each transistor drain to the backgate. While the alternative reduces the leakage issue incrementally, when the high side transistor T1 and low side transistor T2 are off, high voltage on the backgate would result in higher surface fields for a given design and lead to lower lifetimes and thereby diminish the transistor reliability. Additional issues with this approach will include added complexity in packaging technology needs like the need of insulating die attach.
Given the preceding, the present inventors seek to improve upon the prior art, as further detailed below.
USPTO Backgrounds
USPTO Backgrounds