1. Field of the Invention
The present invention relates generally to field effect transistors, and more particularly, to field effect transistors to be applied to a DRAM and a method of manufacturing the same.
2. Description of the Background Art
A DRAM using MOS transistors is known as a device for storing and writing information. FIG. 3 is a diagram showing a sectional arrangement of a memory cell of a conventional DRAM. With reference to FIG. 3, a thick field oxide film 2 for element isolation is formed on a surface of a p type silicon substrate 1. Furthermore, a transfer gate transistor 3 and a capacitor 10 are formed on the surface of p type silicon substrate between 1 field oxide films 2.
Transfer gate transistor 3 is provided with a gate electrode (word line) 4c formed on the surface of p type silicon substrate 1 with a gate oxide film 5 provided therebetween. Periphery of gate electrode 4c is covered with an isolation oxide film 44 at the both sides of gate electrode 4c. Sidewalls 44a having a sidewall structure are formed in isolation oxide film 44 at both sides of gate electrode 4c. n.sup.- impurity regions 43a, and 43b of low concentration are formed in p type silicon substrate 1 in a self-alignment manner with respect to gate electrode 4c. n.sup.+ impurity regions 53a and 53b of high concentration are formed in a self-alignment manner with respect to sidewalls 44a. n.sup.- impurity regions 43a and 43b and n.sup.+ impurity regions 53a and 53b constitute a generally called LDD (Lightly Doped Drain). Then, these impurity regions of the LDD structure serve as source/drain regions 6a and 6b. n.sup.- impurity regions 43a and 43b and n.sup.+ impurity regions 53a and 53b are formed by ion implantation.
Capacitor 10 has a multilayer structure including an impurity doped lower electrode 11, a dielectric film 12 formed of a silicon nitride film or a silicon oxide film, or a multilayer film comprising a silicon nitride film and a silicon oxide film, and an upper electrode 13 formed of impurity doped polysilicon. Capacitor 10 has lower electrode 11 formed above gate electrode 4c of transfer gate transistor 3. In addition, a part of lower electrode 11 is connected to one source/drain 6a of transfer gate transistor 3. As described in the foregoing, capacitor 10 a part of which is formed above transfer gate transistor 3 is referred to as a stacked capacitor and a DRAM including such capacitor is referred to as stacked type DRAM. A bit line 15 is connected to source/drain region 6b. A gate electrode 4d is formed on field oxide film 2.
Writing to this memory cell is performed by applying, to gate electrode 4c, a voltage corresponding to a data signal applied to bit line 15 to turn on transfer gate transistor 3, thereby storing charges corresponding to the data applied to bit line 15 in capacitor 10. Conversely, for reading the charges corresponding to the data stored in capacitor 10, a predetermined voltage is applied to gate electrode 4c to turn on transfer gate transistor 3, thereby reading the voltage corresponding to the charges stored in capacitor 10 from bit line 15.
As described above, a memory cell of a conventional DRAM comprises source/drain region 6b connected to bit line 15 and source/drain region 6a connected to capacitor 10 both formed by ion implantation.
However, with this ion implantation method, ion implantation to the surface of p type silicon substrate 1 causes imperfection in crystal on the surface of the substrate. Imperfection in crystal is also caused by etching at the time of forming sidewall 44a or impurity doping to lower electrode 11. The defect crystal on the substrate surface allows the electric charges stored in capacitor 10 to leak in p type silicon substrate 1, which results in deterioration of a refresh characteristic of the DRAM. On the other hand, source/drain region 6b connected to bit line 15 is not so largely affected by the defective crystal on the surface because the region receives an external power supply through bit line 15.
Therefore, conventionally proposed is a method of forming source/drain region 6a connected to lower electrode 11 of capacitor 10 not by ion implantation but by thermal diffusion, which method is disclosed in Japanese Patent Laying-Open No. 64-80066, for example. FIG. 4 is a diagram showing a sectional arrangement of source/drain regions formed by thermal diffusion and connected to a capacitor shown in FIG. 3 for explaining diffusion thereof. With reference to FIG. 4, n.sup.- impurity region 43a is formed by ion implantation like a conventional one because the region is scarcely damaged by ion implantation. Thereafter, impurity doped lower electrode 11 is subjected to a heat treatment to diffuse the impurities included therein into p type silicon substrate 1. This method of forming source/drain region 6a by thermal diffusion, however, requires source/drain regions of a large depth in order to keep the defective crystal in source/drain region 6a. In this thermal diffusion method, as the depth of source/drain region 6a becomes larger, the lateral diffusion is enhanced to reach the underside of gate electrode 4c. In such a case, the effective channel length of transfer gate transistor 3 is reduced to enhance a generally called short channel effect. One way of avoiding these problems is making sidewall 44a at the opposite sides of gate electrode 4c uniformly thicker. However, n.sup.- impurity region 43b constituting the LDD structure serves to weaken the field strength of the pn junction, thereby suppressing generation of hot carriers, so that its diffusion width and impurity concentration should be precisely controlled. Therefore, the width of sidewall 44a which is a factor of controlling the diffusion width of n.sup.- impurity region 43b in a self-alignment manner should be also controlled precisely. As a result, it is not possible to increase the width of sidewall 44a without considering other factors. In other words, conventionally a thermal diffusion method utilized in order to reduce defective crystal on a substrate surface results in an increase of a short channel effect. It is therefore difficult to reduce the defective crystal on the substrate surface while effectively preventing the short channel effect.
USPTO Backgrounds
USPTO Backgrounds