This invention relates to data processing.
There exists a variety of commercially available processors which are capable of providing the central processing unit of a computer. Each processor can perform arithmetic, logical and control instructions and is adapted to cooperate with a particular organisation of memory and input and output devices. To a large extent, the instructions and the manner of addressing data held in the processor or stored in memory, are characteristics of a particular processor or family of processors. As a result, computer programs written for one computer--or range of computers based on a like processor--are frequently unsuitable for use with computers based on a different processor.
It is the case that a large body of commercially available software is based on a common operating system which can run only on particular processors. Computers which are based upon an incompatible processor are not capable of using such software even though the processor may in certain technical respects be superior to the processor for which the software is written. This problem of incompatibility has been recognised and attempts have been made to deal with the problem in two different ways. First, it has been suggested to provide in a computer based on a selected first processor, a second processor serving as a co-processor to provide the necessary compatability. This obviously involves cost penalties. Second, it has been proposed to provide software by which the existing first processor is caused to emulate a different second processor. To be of practical utility, the emulation must not involve a significant drop in effective processing speed and this presents enormous difficulties, even where the processor being used is inherently faster than that being emulated so that the additional processing required by the emulation is to some extent offset by faster processing. It will be recognized that speed is important not only because a user may demand a fast response time, but also because a particular effective processing speed or minimum processing speed is essential for the correct functioning of certain programs.
This invention focuses on the software emulation approach and for clarity hereafter the term "host" will be used to mean the processor which is through software caused to emulate a different processor (the emulated processor).
In what follows, particular attention will be paid to microprocessors though it should be understood that either or both of the host and emulated processors might take other forms.
To take a specific example, consider emulation of the microprocessor manufactured by Intel Corporation and referred to as 8088. This has an instruction set whose instructions are defined by some number of 8-bit bytes the first of which is an operating code (op-code). The instruction set comprises approximately 230 op-codes (not all possible instruction labels being used). Most instructions require one or more operands and the second byte of those instructions may be regarded as defining the mode of addressing the operand. This may recite specific memories or registers and may occasionally include data. In other microprocessors, it may be a byte other than the second byte of the instruction which performs a function comparable to that of the 8088 addressing mode.
If it is desired to emulate the operation of the 8088 microprocessor, several characteristics of that processor must be emulated. Chiefly, the instruction set of the 8088 must be mapped on to that of the host microprocessor. Inevitably, there will not be a one to one mapping. In addition it will be necessary to recreate, using the facilities of the host microprocessor, the many permutations of addressing modes provided by the 8088. To interpret instructions using prior art techniques would require for each operating code (that is to say the first byte of each instruction) a routine which was capable of analysing the second and subsequent bytes of the instruction and providing an appropriate series of instructions in the instruction set of the host microprocessor. Having regard to the facts that there would inevitably be no direct mapping of operations between the emulated microprocessor and the host microprocessor and that there are likely to be differences in registers and memory addressing, the subroutine corresponding to each 8088 operating code would be complex and would typically involve a number of conditional statements serving to distinguish between different addressing modes. Running such a complex subroutine for every instruction, inevitably slows down processing. Further complications will arise in dealing with the flags (such as auxiliary carry and parity) which are provided by the 8088 but not by the host, and in handling interrupts.
USPTO Backgrounds
USPTO Backgrounds