a. Field of the Invention
This invention relates to a method and a system for assisting mending of a semiconductor integrated circuit, such as a large-scale integrated circuit (hereinafter referred to as LSI), and more particularly to a method and a system for assisting mending of an LSI such as provision of new interconnections or cutting of existing interconnections which is necessitated, for example, by modification or change of the logic thereof. This invention further relates to a wiring formation or structure and a wiring method suited for mending the LSI. According to the present invention, interconnection routes to be mended are automatically located and the yield of the mended LSIs is improved.
b. Background Art
In recent years, logic information of LSI, indicative of logic interconnection relationships between circuit elements or cells and their signal line interconnections of the LSI, has become complex and complicated and enormous more and more as the integration of LSI has become higher. In fact, it is not easy to find out defects of logic in LSI and it is difficult to locate the portions to be mended at a designing stage of LSI. Besides, the logical defects may possibly be caused in the LSI manufacturing process. By this reason, the logical defects in LSI are usually found only after LSI has been packaged and tested. To remove such logical defects, it is preferable to redesign and remake the LSI, but this takes a considerable time, causing delay in production of the device.
Various attempts have been made to remove the logic defects of LSI, modifying its logic, within a short period of time, without redesigning it, even when defects in logic are found after incorporation of LSI into the device. In these attempts, defective portions of the LSI are mended by newly providing interconnecting lines or disconnecting the lines during the development of the device.
One of the earlier attempts is disclosed in Japanese Patent Laid-Open Publication (Kokai) No. 62(1987)-229956 which teaches a technique for employing ion beam or chemical vapor deposition (CVD) for connection or disconnection of LSI wiring.
Another earlier attempt is disclosed in Japanese Patent Laid-Open Publication (Kokai) NO. 62(1987)-298134, in which a spare wiring is provided in LSI in preparation for possible modification or change in interconnections between the elements to effect desired mending easily.
Further, Japanese Patent Laid-Open Publication (Kokai) No. 59(1989)-200500 discloses still another art which relates to a method for routing wiring paths between pin and pins on a wiring board with wiring pins.
When logic defects of an LSI are found, modification of the logic is made by investigating the logic information for logics on which the wiring of LSI is based, and then by correcting defective portions of the logic and rewriting the logic information. According to the so rewritten logic information, signal interconnections to be corrected are located for mending. The rewriting of the logic information is made for reconstructing the logic in view of the changed interconnection relationship between the logic to be corrected and other relevant logic and also for analyzing the operation of LSI after correction and providing correct logic interconnections for intended mass-production of the LSI.
The mending of LSI requires extremely precise operations. By this reason, the mending is generally carried out by an automatically controlled mending device. This mending device should be instructed correctly so that wrong signal interconnections should not erroneously be subjected to mending. However, it is not easy to exactly locate portions to be mended in the LSI according to the rewritten logic information and it may possibly happen that an operator will inadvertently input wrong data for the mending device. Thus, the mending operation requires much labor and time and it still involves every possibility of mis-instruction for locations to be mended.
The above-mentioned publications, however, fail to consider those problems and give no teaching to overcome them. Accordingly, it is a task to provide an assisting method for mending LSI correctly and easily.
In the mending of the interconnections of LSI, a special attention should be paid so as not to adversely affect other irrelevant interconnections. This attention should be taken particularly for LSI with high density, which is formed in multi-layer structure and fine microstrip wiring.
However, the publications as mentioned above do not contemplate any solution for those matters. Therefore, if the mending is carried out inadvertently, short-circuiting or disconnection of the other irrelevant lines may possibly be caused, creating another defect or misoperation.
A typical example of the prior art large-scale integrated circuit is as illustrated in FIG. 16. This integrated circuit has a multi-layer structure made up of three interconnecting pattern-formed layers AL1, AL2 and AL3 formed on an insulating substrate 65. As illustrated in FIG. 16(a), interconnecting patterns 64 and 66 provided on the uppermost layer AL3 are very close to each other and, therefore, it is likely to cut inadvertently part of the adjacent interconnecting pattern 64 when the interconnecting pattern 66 is cut. FIG. 16(b) illustrates another example, in which one of closely arranged interconnecting patterns 61 and 63, for example, interconnecting pattern 61 might be partly or totally cut when an interconnecting pattern 69 on the layer AL2 is cut at 62. Thus, there is a possibility of disconnection of irrelevant interconnecting patterns and it deteriorates the reliability of the mended LSI.
For forming a new interconnecting pattern to mend the LSI, it is necessary to partly expose a surface of an interconnecting pattern 72 to which the interconnecting pattern 70 is connected. In this operation, it may possibly happen that part of an adjacent interconnecting pattern 71 is also exposed inadvertently together with the interconnecting pattern 72. In this case, the interconnecting patterns 71 and 72 are short-circuited when the interconnecting pattern 70 is provided as illustrated in FIG. 16(c). In addition, there is a possibility of cutting part of the interconnecting pattern 68 of the uppermost layer AL3 when the interconnecting pattern 69 of the intermediate layer AL2 is partly exposed for connecting a new interconnecting pattern 60 to the pattern 69 as shown in FIG. 16(d). In this case, the interconnecting patterns 68 and 69 are short-circuited when the interconnecting pattern 60 is formed, and such short-circuiting causes malfunction.
Whereas, Japanese Patent Laid-Open Publication 62-229956 as recited above only discloses a mending method of an LSI, such as connecting or disconnecting of interconnection lines of the LSI, and fails to consider any adverse effect on the other interconnection lines causable by the mending operation. More particularly, the publication has no teaching about how to determine the position to be corrected without adverse affect on other irrelevant interconnections. This prior art, after all, requires expensive, high resolution ion beam generating equipment to effect the desired mending onto the LSI without causing adverse affect on the irrelevant interconnections. In addition, the mending operation requires microscopic processing such as connection or disconnection of the minute wiring and it requires much labor Furthermore, the mending operation becomes harder and the yield of the mended LSI is lowered as the wiring further becomes minute and integration of the LSI is increased.
The second publication or Japanese Patent Laid-Open Publication No. 62-298134 merely teaches provision of spare wiring to faciliate repair or mending of the interconnections of the LSI and does not refer to the location of the disconnection or connection. This prior art also fails to suggest a solution for difficulty of the processing operation on the minute wiring of the LSI. Thus, this prior art also has such a problem that the yield of the mended LSI is still low.
The prior art as disclosed in the third publication or Japanese Patent Laid-Open Publication No. 59-200500 is directed not to LSI but to a wiring board This publication teaches how to determine a wiring path for the predetermined interconnection pins, but fails to disclose how to determine positions to be interconnected or disconnected In addition, this prior art is different, in both conditions and factors of determining wiring paths, from those required for the LSI and the disclosure of this prior art can not be applied to the LSI wiring technique.
In the mending of LSI, some areas or positions are difficult or quite impossible to be subjected to mending because of the positional relationships with the existing interconnecting lines or the density thereof. If information about such areas or positions is not given preliminarily, the mending operation shall be performed in a trial-and-error way, which is inefficient. If areas or position where the desired mending can be attained are known preliminarily, equivalent logic modification or change might be effected somewhere else. Thus, the mending operation can be carried out effectively without trying a useless operation. Even when some logical defects to be corrected are found in the LSI in the course of the development of the same and the LSI has no areas or positions which allow mending of the defects, redesigning of the LSI can be decided at once so as to promptly start remaking of the LSI, which takes a considerably long time.
However, none of the prior art as mentioned above suggest such preliminary clarification of the mending-allowable areas or positions of the LSI. Therefore, they can not provide high mending efficiency and prospect of mending chance.
USPTO Backgrounds
USPTO Backgrounds