1. Industrial Applicability
The present invention relates to a method of manufacturing a non-volatile semiconductor memory device for storing information by accumulation of an electric charge. More specifically, the present invention relates to a method of manufacturing a non-volatile semiconductor memory device in which a memory element is selectively activated by a field effect transistor, and to the non-volatile semiconductor memory device manufactured by accordance with this method.
2. Description of the Background Art
As a non-volatile semiconductor memory device having memory elements provided with floating gates and control gates, flash memory can be mentioned as an example. A variety of designs are available for flash memories, one of which is a device in which a memory element is selectively activated by a field effect transistor. A flash memory with such a configuration has been disclosed, for example, in Japanese Patent Application Laid-Open No. 6-275847/1994. In the following, a method of manufacturing the flash memory disclosed in Japanese Patent Application Laid-Open No. 6-275847/1994 is described with reference to FIGS. 44 to 52.
As shown in FIG. 44, on a principal surface of a semiconductor substrate 200, a silicon oxide layer 202 as a tunnel oxide layer is grown, and then a polysilicon layer 204 as a floating gate is formed. Part of the polysilicon layer 204 that is positioned over an access transistor formation region 232 is selectively etched as shown in FIG. 45, and remaining part of the polysilicon layer 204 positioned over a memory element formation region 234 is left. This remaining part of the polysilicon layer 204 is hereinafter referred to as a polysilicon layer 204a. As shown in FIG. 46, an ONO-layer 206 is formed on the polysilicon layer 204a, and a silicon oxide layer 208 as a gate oxide layer is formed over the access transistor formation region 232. Subsequently, a polysilicon layer 210 is formed on the ONO-layer 206 and the silicon oxide layer 208.
As shown in FIG. 47, a resist 212 is prepared on the polysilicon layer 210, which is then selectively etched by using the resist 212 as a mask, thereby forming a gate electrode 214 over the access transistor formation region 232 while leaving part of the polysilicon layer 210 that is positioned over the memory element formation region 234. The remaining part of the polysilicon layer 210 over the memory element formation region 234 is hereinafter referred to as a polysilicon layer 210a. This etching exposes the silicon oxide layer 208 on a principal surface 236 of the semiconductor substrate 200, in the area between the gate electrode 214 and a floating gate to be formed in a later step. Next, as shown in FIG. 48, the resist 212 is removed and a resist 216 is prepared over the memory element formation region 234 and the access transistor formation region 232. The resist 216 is patterned so that it provides a mask for forming a control gate.
Note that the resist 216 is patterned so that it covers the gate electrode 214, while at the same time its side surface 216a does not overlap the polysilicon layers 204a and 210a. The gate electrode 214 has to be covered because the gate electrode 214 is formed of a material identical to that of the control gate and the floating gate, i.e. polysilicon, and therefore has to be protected from being etched away during the etching step to form the control gate and the floating gate. The patterning is provided in such a way that the side surface 216a does not overlap the polysilicon layers 204a and 210a because, when the polysilicon layers 204a and 210a are etched later to form the control gate and the floating gate, unnecessary polysilicon layers 204a and 210a are left on the principal surface of the semiconductor substrate 200 if the side surface 216a overlaps the polysilicon layers 204a and 210a. Consequently, the resist 216 is patterned while maintaining the silicon oxide layer 208 exposed on a principal surface 236 of the semiconductor substrate 200, in the area between the gate electrode 214 and a floating gate to be formed in a later step.
The polysilicon layer 210a is selectively etched by using the resist 216 as a mask to form a control gate 218. The ONO-layer 206 is then selectively etched by using the resist 216 as a mask, as shown in FIG. 49. This etching removes the exposed portion of the silicon oxide layer 208 and exposes the principal surface 236 in the area between the gate electrode 214 and a floating gate to be formed in a later step.
As shown in FIG. 50, the polysilicon layer 204a is selectively etched by using the resist 216 as a mask, thereby forming a floating gate 220. Since the principal surface 236 is exposed, the principal surface 236 is also etched to unavoidably form a groove section 222 on the principal surface 236. Subsequently, an ion implantation is provided on the principal surface of the semiconductor substrate 200 using the resist 216 as a mask, thereby forming a source/drain region 224 in the memory element formation region 234 as well as an impurity region 226 electrically connected to the source/drain region 224 in the groove section 222.
A silicon oxide layer 228 is grown on the principal surface of the semiconductor substrate 200 as shown in FIG. 51, followed by the formation of a contact hole 238 on the silicon oxide layer 228 so that the source/drain region 224 is exposed. As shown in FIG. 52, an aluminum wiring layer 230 is then provided on the silicon oxide layer 228. The aluminum wiring layer 230 is also formed on the contact hole 238 and is electrically connected to the source/drain region 224. A memory element 242 is provided with the control gate 218, the floating gate 220, and the source/drain region 224, whereas an access transistor 244 is provided with the gate electrode 214 and the source/drain region 240.
Referring to FIG. 52, for selectively activating the memory element 242 with the access transistor 244, the source/drain region 240 of the access transistor 244 and the source/drain region 224 of the memory element 242 are electrically connected through the impurity region 226 formed within the groove section 222. Since the wiring region comprising the source/drain region 240, the impurity region 226, and the source/drain region 224 has an irregular shape due to the presence of the groove section 222, the diffusion resistance of the impurity region 226 significantly affects the diffusion resistance of the wiring region. In the meantime, as described with reference to FIG. 50, the source/drain region 224 and the impurity region 226 are formed simultaneously by a single ion implantation. Since this implantation is performed under the conditions for depth and concentration of impurities required for forming the source/drain region 224, the depth and concentration of impurities at the impurity region 226 are not at the adequate levels required for the region. This leads to undesirable consequences where, for example, a high diffusion resistance at the impurity region 226 slows the speed of programming, erasing, and reading of the memory element 242.
USPTO Backgrounds
USPTO Backgrounds