1. Field of the Invention
The present invention relates to an apparatus for and method of controlling a data strobe signal, and more particularly, to an apparatus for and method of controlling a data strobe signal to optimize a read margin in a memory controller as much as possible.
2. Description of the Related Art
Recently, a large percentage of digital devices use a synchronous dynamic random access memory (SDRAM) that is relatively cheap as a main data storage unit. As the storage capacity of SDRAM increases and the SDRAM performs higher speed operations, timing becomes a very important factor. In addition, as the speed of an SDRAM interface increases, it is difficult for a chip including a memory controller that uses the SDRAM as the main memory to guarantee stable read operations.
FIG. 1 is a view illustrating a general apparatus for controlling a data strobe signal to read external data.
Referring to FIG. 1, the general apparatus for controlling a data strobe signal includes a delay locked loop (DLL) 110, a controller 120, a delay line 130, and a flip-flop 140.
The general apparatus for controlling a data strobe signal may be included in a memory controller. External data (DQ) and a data strobe signal (DQS) are transmitted from the SDRAM to the memory controller generally with the same phase. Therefore, the memory controller latches the transmitted external data by using the data strobe signal. Since the data strobe signal has the same phase as that of the external data, the apparatus for controlling a data strobe signal delays the data strobe signal by a predetermined time and latches the external data by using the data strobe signal. For example, in read operations of a double data rate (DDR) SDRAM, in order to optimize a setup margin (a time interval between a time point at which a data transition occurs and a time point at which a read operation occurs) and a hold margin (a time interval between a time point at which a read operation occurs and a time point at which another data transition occurs) of data, the data strobe signal has to be shifted by 90°.
An external system clock signal or data strobe signal is applied to the DLL 110 and the DLL 110 measures and outputs a period of the applied system clock signal or data strobe signal. Outputs of the DLL 110 may be represented according to the number of delay chains included in the DLL 110.
The controller 120 receives the period of the system clock signal or data strobe signal from the DLL 110 and determines a delay length of the data strobe signal for optimizing the setup margin and the hold margin of the data. For example, the data strobe signal may be shifted by 90° in the DDR SDRAM. In this case, the DLL 110 counts the number of delay chains for a cycle of the data strobe signal, and the controller 120 multiplies the number of delay chains for the cycle by ¼ to calculate the number of delay chains required to shift the data strobe signal by 90°.
The delay line 130 delays the data strobe signal according to the delay length determined by the controller 120.
The flip-flop 140 latches and outputs external data by using the system clock signal or data strobe signal delayed and output from the delay line 130 as a trigger signal.
In this case, the general apparatus for controlling a data strobe signal cannot monitor the setup margin and the hold margin for the read operation of the data strobe signal. In addition, there is a problem in that there is no method of correcting the data strobe signal when conditions of the read operation are changed.
In addition, a margin in the read operation is smaller than that in a write operation due to input/output (I/O) power noise and jitter of the clock signal, so a method of optimizing the read margin is required.
In addition, a unit for checking the read margin between a chip including the SDRAM controller and the SDRAM is needed.
USPTO Backgrounds
USPTO Backgrounds