In order to provide greater computing power for those applications requiring significant numbers of floating- point operations, some numerical data processors implement in hardware the essential floating-point instructions, such as addition, subtraction, multiplication and division. Most commonly, these floating-point instructions are directly integrated into the data processor silicon chip. Alternatively, these floating-point instructions are provided in a separate numerical data processor, a so-called mathematical or numeric coprocessor, which cooperates with the main data processor to execute the floating-point instructions.
Numerical values or data used in scientific or technical calculations are expressed in a floating-point number configuration consisting of a sign S, an exponent E and a mantissa M, which permits the expression of a wide range of numerical values in a limited number of bits. There is a number of different standard formats to implement this configuration. In particular, a typical widely accepted floating-point format is the standard format proposed by the Institute of Electrical and Electronics Engineers (IEEE). This standard defines four floating-point formats: single, single extended, double and double extended precision.
By way of example, an 80-bit double extended precision format will be discussed below because this format is extensively used in microcomputer chips. As illustrated in FIG. 1, it consists of a 1-bit sign, a 15-bit exponent and a 64-bit significand. In this format, at location 63, an explicit 1 is stored in the significand part of the format, except for some particular values such as 0. The remaining 63-bit part of the significand comprises the mantissa M. In addition, the exponent is expressed in a biased form, i.e., a constant referred to as BIAS=16383, is added to the real value E of the exponent (true exponent). With the format of FIG. 1, 64 mantissa bits of precision are obtained representing a number within the range of -2.sup.16384 (the greatest negative number) and +2.sup.16384 (the greatest positive number). Finally, according to the IEEE standard format, the value of a real number N is given by: EQU N=(-1)**S*1.M*2**(E+BIAS)
wherein S=0 for a positive number and S=1 for a negative number.
A valid (or normalized) number N is given by 0&lt;E+BIAS&lt;32767. The case in which the value of the biased exponent is at its maximum (i.e. E+BIAS=32767) and the mantissa M.noteq.0, it is specially treated as a "non-number." The case in which the value of the biased exponent is at its maximum and the mantissa M=0, is specially treated as infinity. Finally, the case in which the value of the biased exponent E+BIAS is at its minimum, (i.e., equal to 0) is exceptionally treated as a denormalized number. Further details can be found in the document: "A Proposed Standard for Binary Floating-Point Arithmetic", Draft 8.0 of IEEE Task P754, 1981.
Whenever data processed in the 80-bit floating-point format is used by a numeric coprocessor in accordance with the IEEE standard format, addition/subtraction operations normally entail requiring a large amount of processing steps and a corresponding number of machine cycles. This point will now be illustrated for an addition by reference to Examples I and II.
USPTO Backgrounds
USPTO Backgrounds