The increasing demand for very-large-scale-integrated (VLSI) devices has made imperative the development of techniques for multilevel metallization, multilayer resist processing, and the like. These developments necessitate utilization of layers of planarizing material to smooth uneven topography on a substrate so that there will be minimal thickness variation in, e.g. a subsequently spun-on coating of resist material. In the instance of multilevel metallization, it is necessary that there be an intermediary layer of dielectric material between metal layers which smooths topography underlying the second-deposited layer of metal and which provides effective insulation between them.
The planarizing layers and, not infrequently the dielectric materials, are organic, i.e., polymeric in nature. It is frequently the case, especially with polyimide dielectrics, that such layers are etched by oxygen plasma or reactive ion etching. Since such layers are generally thick, there is a tendency for the top edge to lose edge acuity, i.e. become less vertical, during prolonged oxygen etching. This often produces a rounded top on the edge of the pattern and a sloped profile. For applications such as multilayer resist structures, liftoff structures and certain high resolution patterns where vertical and reverse-sloped wall profiles are desired, the rounding of the top edge of the patterned layer and undercutting of the masking layer can have adverse effects on dimensional control of the pattern. In accordance with this invention, an effective means of preventing the formation of rounded or sloped wall profiles has been found.
USPTO Backgrounds
USPTO Backgrounds