Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET).
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer cause the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
In conventional enhancement mode GaN transistors, the gate metal and the p-type GaN material or p-type AlGaN material are defined by using separate photo masks. For example, FIG. 1 (prior art) shows the gate metal and gate pGaN were processed with two different photo masks. FIG. 1 illustrates a conventional enhancement mode GaN transistor device 100 which includes substrate 101 which can be either sapphire or silicon, transition layers 102, un-doped GaN material 103, un-doped AlGaN material 104, source ohmic contact metal 109, drain ohmic contact metal 110, p-type AlGaN or p-type GaN material 105, heavily doped p-type GaN material 106, and gate metal 111.
As shown in FIG. 1, the gate metal, p-type GaN, or p-type AlGaN material are defined by two separate photo masks. The first mask is used to form the p-type GaN or p-type AlGaN, either by patterning a hard mask and selectively growing the p-type GaN or by patterning and etching the p-type GaN. The second mask is used to form the gate metal either by patterning and lifting off the gate metal or by patterning and etching the gate metal. The two mask process leads to wider gate length than photo/etch minimum CD. This causes high gate charge, wider cell pitch, and higher Rdson (“on resistance”). The conventional method of fabrication also increases manufacturing costs. Another disadvantage is that the highest electric field is located at the p-type GaN material or p-type AlGaN material gate corner toward the drain ohmic contact metal. This high electric field leads to high gate leakage current and a gate reliability risk.
It would be desirable to provide an enhancement mode GaN transistor structure with a self-aligned gate which avoids the above-mentioned disadvantages of the prior art. It would also be desirable to provide a feature to relieve the high electric field at the gate corner of the p-type GaN or AlGaN.
USPTO Backgrounds
USPTO Backgrounds