1. Technical Field of the Invention
The present invention relates in general to the telecommunications field and, in particular, to communications devices that utilize digital correlators to detect the presence of predetermined digital codes in noise, such as spread spectrum receivers, packet data receivers, or in frequency hopping synchronization applications.
2. Description of Related Art
FIG. 1 is a block diagram of a prior art correlator, which is used to compute correlations between the last M signal samples received and an M-bit codeword. An M-element delay line 10 stores received signal samples and sequentially shifts them through each of the M stages. Consequently, the delay line memory elements contain the last M signal sample values received. After each new sample is shifted in and one old sample is shifted out, the M sample values are read out of the delay line into M sign-changers 12, where the M sample values are multiplied by +1 or -1 according to the bits b.sub.1. . . b.sub.M of a predetermined code with which correlation is to be computed. The sign-changed values are then summed in adder 13 to produce a correlation result.
In general, the process of correlating an M-element vector A=(a1,a2. . . aM) with an M-element vector B=(b1,b2. . . bM) involves forming the inner product A.multidot.B=a1.multidot.b1+a2.multidot.b2+. . . . aM.multidot.bM. When the elements of one of the vectors (e.g., B) comprises only binary values (arithmetically +1 or -1), the products such as a1.multidot.b1 simplify to .+-.a1, but the process of adding the M values .+-.a1.+-.a2. . . .+-.aM is still a significant effort when it has to be performed for every new value of "a" received.
The prior art includes many variations of the correlator shown in FIG. 1. For example, signal samples may be single-bit or "hard-limited" quantities of only +1 or -1 instead of multi-bit quantities. The sign-changers used then are typically simple XOR gates. In that case, the adder 13 may first add pairs of single-bit values to obtain M/2 two-bit values; M/4 two-bit adders then add two-bit values to obtain M/4 three-bit values, and so on. Such a structure, known as an "adder tree", is simpler when the input values are single-bit rather than multi-bit values.
For single-bit value signal samples, the adder tree can be replaced by an up/down counter that scans the M values, and counts up when a +1 is encountered and down when a -1 is encountered. Likewise, for multi-bit value signal samples, a parallel adder tree can be replaced by a sequential adder that extracts each of the M values, in turn, from the delay line memory and adds it to an accumulator. In the latter case, the logic employed must operate M-times as fast as in the parallel adder case. Consequently, there is a trade-off between the overall speed of the correlator and the logic complexity. Nevertheless, in each of the above-described prior art correlator variations, it is necessary to combine M values anew after each new signal sample is received. However, as described below, these problems are resolved by the present invention.
USPTO Backgrounds
USPTO Backgrounds