A memory system has a memory hierarchical structure. The memory hierarchical structure includes memories having different operation speeds. More specifically, the memory hierarchical structure includes an SRAM (static random access memory), a DRAM (Dynamic Random Access Memory, a NAND flash memory and others in the order of high operation speed. These memories are different from each other in the data retention as well as the operation speed. When data transmission is carried out between memories having different data retentions, an overhead resultantly occurs. Therefore, it is desired that a wide range of the system is covered with the DRAM to simplify the memory hierarchical structure and to decrease in the overhead.
However, the use of the conventional DRAM cannot arbitrarily set the data retention and operation speed. Thus, it has been impossible to solve the problem in the memory hierarchical structure.
USPTO Backgrounds
USPTO Backgrounds