1. Field of the Invention
This invention relates generally to a method of diagnosing complex semiconductor devices utilizing logic circuits that have failed functional testing. More particularly this invention diagnoses and determines the failing locations by combining functional testing of the device circuitry with structural design and test techniques to dynamically create a new test pattern based on the functional failure and thereby determine the location of and type of error in the failing circuit.
2. Background of the Invention
Level Sensitive Scan Design (LSSD) methodology is well known to the prior art. Basically the LSSD methodology is a system design in which the device under test has a plurality of storage elements, i.e., latches or registers, that are concatenated in one or more scan chains and are externally accessible via one or more serial inputs and outputs. Storage elements that are not so concatenated are usually memory or other special macros that are isolated and can be tested independently. This LSSD methodology ensures that all logic feedback paths are gated by one or more of these concatenated storage elements, thereby simplifying a sequential design into subsets of combinational logic sections.
These basic design concepts, in conjunction with the associated system and scan clocking sequences, greatly simplify the test generation, testing, and the ability of diagnosing very complex logic structures. In such a design every latch can be used as a pseudo Primary Input (PI) and as a pseudo Primary Output (PO), in addition to the standard Primary Inputs and standard Primary Outputs, to enhance the stimulation and observability of the device being tested or diagnosed. Typically LSSD latches are implemented in a configuration having master (L1) and slave (L2) latches where each master latch (L1) has two data ports and may be updated be either a scan clock or a functional clock and each slave latch (L2) has but one clock input that is out of phase with both L1 scan and functional clocks. Scanning is done using separate A and B scan clocks.
The strategy of diagnosing these LSSD circuits has been established and evolving for many years. The primary characteristic of deterministic or pre-determined LSSD patterns is that each pattern is independent from every other pattern and each pattern consists of Primary Inputs, Clocks, a Load, and an Unload sequence. Such LSSD circuits may have thousands of patterns depending upon the size and structure of the logic. During diagnostics, one or more failing patterns are identified and fault simulation is performed on the failing pattern (Load, Primary Inputs, System Clocks, and Unload sequence). The circuit states can be quickly achieved by reviewing and simulating the falling pattern load, any Primary Inputs, System Clocks, and measures. Passing patterns may also be used to eliminate potential faults that the identified failing patterns marked as potential candidates.
However this method of diagnosing of such complex logic structures to determine the devices that have failed functional testing is very time consuming and difficult and is even more difficult when the circuit designs are sequential in nature and utilize a functional pattern test methodology as found in LSSD circuits. General Scan Designs (GSD) circuits are similar and well known to the art.
The testing and diagnosis of such complex circuits (LSSD and GSD) can be greatly simplified by adopting a design-for-test methodology that reduces the sequential circuit in partitions of combinational logic and allows access to the storage elements within the circuit during the testing process. This structural test methodology in conjunction with such scan based designs allows for effective functional and structural testing approaches.
Both, functional and structural logic test methodologies have unique advantages. Structural logic testing benefits include, ease of test pattern generation, simpler diagnostic methods, lower test pattern data volumes, specific fault targeting, high test coverage and precise test effectiveness measurement. Alternatively, functional testing can be applied at-speed, tests the actual device application functions, and closely emulates the operating environment during test. However, functional testing is sequential in nature and thus must rely on previous events or states of the logic for each subsequent pattern.
Functional fails are generally very difficult to diagnose since detail understanding of the logic circuit design and functional fail behavior is necessary and using the prior art techniques requires that test engineers and designers dedicate many hours and several diagnostic iterations to understand and diagnose the failure mechanism.
This basic problem complicates the diagnostic process by the need to track the structure's logical states for several previous events. This is required so that the failing vector can be analyzed with the proper values of each logic circuit at the time and point of failure.
Therefore, there are compelling economic reasons to electrically diagnose any fault in the circuit to within a couple of logic blocks or a dozen or so transistor devices as rapidly as possible.
It is also desirable that the diagnostic process between the electrical model and the physical location be correlated by providing conventional PFA tools with an precise physical location for the potential defect.
USPTO Backgrounds
USPTO Backgrounds