The present invention relates to the design of a semiconductor, and more particularly, to a semiconductor device which can reduce off-state leakage current due to reverse narrow width effect (RNWE) resulting from mechanical stress.
Recently, as portable information terminals are distributed, the demand for high capacity memory devices, which have small sizes and relatively superior power consumption characteristics, have been increased considerably. In order to meet the demand, it is essential to reduce semiconductor device size. However, as semiconductor devices become smaller, since leakage current proportionally increases, it has become more difficult to improve the performance of semiconductor devices.
In general, it has been known that, as size of transistors constituting a memory device becomes smaller, power consumption under an atmospheric condition increases. This results from the facts that, as the distance between a source and a drain decreases, a leakage current component flowing through a substrate between the source and drain increases and that a leakage current component generated at a zone between an active region and an isolation structure increases due to a shallow trench isolation (STI) process.
The leakage current flowing between the source and the drain is caused by narrow width effect (NWE) such as short channel effect (SCE), and the leakage current generated at the zone between the active region and the isolation structure due to the presence of defects such as divots is caused by reverse narrow width effect (RNWE). In addition, the leakage current caused by RNWE can be generated by mechanical stress from a material used to form the isolation structure when the STI process is adopted.
FIG. 1 is a plan view illustrating a conventional transistor so as to explain RNWE due to mechanical stress, and FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1. In FIG. 1, the reference symbol W designates the width of the transistor, and the reference symbol Lg designates the length of a gate.
Referring to FIGS. 1 and 2, a conventional transistor includes a source 110 and a drain 112, which are formed in a quadrangular active region and spaced apart from each other by a predetermined distance, and a gate 108, which is formed in a bar type to traverse the area between the source 110 and the drain 112. Here, the gate 108 includes a gate dielectric layer 104 and a gate electrode 106.
In the conventional transistor, as miniaturization of the transistor progresses, the length Lg of the gate 108 decreases, and the width W of the transistor also decreases. In general, as the width W of the transistor decreases, the leakage current under an atmospheric condition (hereafter referred to as “off-state leakage current”) decreases.
However, if an STI process is adopted, the off-state leakage current increases from a point of width W as shown in FIG. 3. It can be observed from FIG. 3 that the off-state leakage current increases through an RNWE range. One of the reasons why the off-state leakage current increases through a certain range of width W when the STI process is adopted is the mechanical stress of an isolation structure 105.
The isolation structure 105 includes a multi-layered insulation structure including an oxide layer 103 and a nitride layer 102. Accordingly, the mechanical stress that is induced by the respective layers 102 and 103 constituting the isolation structure 105, in particular, the nitride layer 102, exerts influences on the source 110 and the drain 112, which adjoin the isolation structure 105. Due to this fact, defects are likely to be produced in the source 110 and the drain 112, which adjoin the isolation structure 105. While a precise mechanism for these defects has not been found yet, the defects are produced in various forms and increase the off-state leakage current.
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