It is known that in continuous-time filters utilizing a transconductor and a capacitor, with a ratio between transconductance and capacitance determining a cutoff frequency of the filter. It is often desirable to have a capacitance that can control the transconductance and thus maintain a constant cutoff frequency for the filter. In various applications of continuous-time filters, it is also often desirable to be able to program the cutoff frequency of the filter.
For example, in read channels for hard disk drives, it is often necessary to equalize a signal arriving from a read head of the hard disk. Part of the equalization occurs in the analog domain by means of a filter, whose cutoff frequency should be programmable in a range between 1 and 10 and at a sufficiently high speed. Such cases usually use a transconductor filter as mentioned above, in which frequency programming occurs by controlling the transconductance of the filter. It is also important, therefore, to control the transconductance so as to allow variation of the cutoff frequency according to specific requirements.
A conventional transconductor filter is usually provided by means of a plurality of cascade-connected cells, whose number depends on the order of the filter to be provided. For example, a filter with three cells is a third-order filter. In particular, inside the filter, a so-called "master section" and a "slave section" are provided. The master section acts as a reference for the transconductance of the filter and sets a current which is then sent to the subsequent cells that belong to the slave section. All the various cells of the filter are of the same type and are similar to the master section of the filter. The transconductances of the cells of the slave section determine the cutoff frequency of the filter.
FIG. 1 is a circuit diagram of a transconductor filter comprising a master section 1 and a plurality of cells 2 and 3 (only two cascade-connected cells are shown in this case), forming the slave section of the filter. The master section 1 further comprises a transconductor 4, the input whereof receives a constant voltage V.sub.DD generated with absolute precision, so that V.sub.DD does not vary over time, and a capacitor 5 downstream of the transconductor 4. A digital-to-analog converter (DAC) 7 is connected to a node 6, is adapted to generate a reference current I.sub.R, and receives a digital word FC-WORD input. An output current from the transconductor 4 is the same that is set by the DAC 7.
The DAC 7 multiplies a fixed reference current, set by a current source 8, by the digital word FC-WORD to obtain in output a reference current I.sub.R. I.sub.R is substantially equal to the voltage input V.sub.DD to the transconductor 4 multiplied by a transconductance (defined by the expression ##EQU1## where I represents current into the transconductor 4 from a current source 12 and V represents the constant voltage provided by V.sub.DD) of the transconductor 4. The digital word FC-WORD is used to adjust the transconductance of the filter (e.g., to vary its cutoff frequency). This is done by modifying the digital word that is multiplied by the reference current set by the source 8.
A PMOS transistor 9 has a gate terminal connected to the node 6 and a drain terminal connected to a drain terminal of an NMOS transistor 10. The NMOS transistor 10 has in turn a gate terminal connected to a gate terminal of an additional NMOS transistor 11, which has a source terminal connected to a source terminal of the NMOS transistor 10. The NMOS transistor 11 is common-ground connected and has a drain terminal connected to the transconductor 4. The MOS transistors 9, 10, and 11 constitute a feedback loop which forces the transconductor 4 to have the desired transconductance.
The transconductors 15 and 16 belonging to the cells of the filter 2 and 3 are set to the same bias as the master section 1 (e.g., to the same current that is mirrored by the NMOS transistor 10). In this manner, the current set by the master section 1 is sent to all the cascade-connected cells that constitute the filter. The biasing current is varied by changing the digital word FC-WORD entered into the DAC 7. Accordingly, the transconductance of the transconductance filter shown in FIG. 1 is controlled at will, thus allowing the cutoff frequency to be varied as desired.
The above-described structure, however, entails some drawbacks. For instance, if the transconductance of the transconductance filter has to be programmed, it is necessary to be able to quickly vary the transconductances so as to reach a steady-state value and then modify the cutoff frequency of the filter. In the case of the above-described circuit of FIG. 1, a time constant set by the capacitor 5 limits the time during which the transconductance of the transconductance filter settles.
Another time constant to be taken into account is the one required to bring the gate terminals of the MOS transistor 10 and of the other transistors of the cells 2, 3 to the steady state. The higher the order of the filter (e.g., the larger the number of cells of the transconductance filter), the greater this time constant.
The large time constant is particularly troublesome if one wishes to have a widely adjustable filter, for example adjustable over a range between 1 and 10 (e.g., a filter in which the cutoff frequency can be varied by a factor of up to 10). It is desirable that the settling time of the filter is the shortest possible, but one is limited by the above-described time constants. It is in fact necessary to wait until the feedback loop provided by the MOS transistors 9, 10, and 11 enters the steady state before the transconductance of the transconductance filter can settle.
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