Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a Global Bit Line (GBL) and a method for manufacturing the same.
In recent times, technologies of 40 nm or less have been applied to semiconductor devices so that a Global Bit Line (GBL) process has been proposed. However, if misalignment between a bit line contact and a bit line occurs, the GBL process unavoidably generates a poor self-aligned contact (SAC) between a bit line contact and a storage node contact. If a thick bit line spacer is formed to solve the above-mentioned problem, a Not-Open phenomenon of a storage node contact occurs. In addition, if the bit line contact spacer is formed thick, resistance of the bit line contact is increased. In order to prevent the increasing resistance of the bit line contact, an inner GBL process has been proposed. However, the inner GBL process is disadvantageous in that it makes difficult a SAC contact process, and increases parasitic capacitance (Cb) between the bit line and a plate electrode. Increased parasitic capacitance (Cb) has a negative influence upon a sensing margin of the entire semiconductor device, resulting in deterioration of device characteristics.
USPTO Backgrounds
USPTO Backgrounds