(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of post-passivation processing for the creation of conductive interconnects.
(2) Description of the Prior Art
Improvements in semiconductor device performance are typically obtained by scaling down the geometric dimensions of the Integrated Circuits; this results in a decrease in the cost per die while at the same time some aspects of semiconductor device performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit-performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, one approach has been to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation, this approach however limits the interconnect network to fine line interconnects, associated with parasitic capacitance and high line resistivity. The latter two parameters, because of their relatively high values, degrade device performance, resulting in even more severe effects for higher frequency applications and for long interconnect lines that are, for instance, used for clock distribution lines. Also, fine line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.
It has previously been stated that it is of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity. The invention provides such a method. An analogy can be drawn in this respect whereby the currently (prior art) used fine-line interconnection schemes, which are created under a layer of passivation, are the streets in a city; in the post-passivation interconnection scheme of the present invention, the interconnections that are created above a layer of passivation can be considered the freeways between cities.
FIG. 1 shows a cross section of a silicon substrate on the surface of which has been created a conductive interconnect network. The structure that is shown in cross section in FIG. 1 addresses only and is limited to prior art power and ground distribution networks. The various features that have been highlighted in FIG. 1 are the following:
40, a silicon substrate on the surface of which has been created an interconnect network
42, a sample number of semiconductor circuits that have been created in or on the surface of the substrate 40
44, two electrostatic discharge (ESD) circuits created in or on the surface of the substrate 40; one ESD circuit is provided for each pin that is accessible for external connections (pins 52, see below)
46 is a layer in which interconnect lines are provided; these interconnect lines are above the surface of substrate 40 and under the layer 48 of passivation and represent a typical application of prior art fine-line interconnects; these fine-line interconnects in layer 46 typically have high resistivity and high parasitic capacitance
48 is a layer of passivation that is deposited over the surface of the layer 46 in which interconnect lines are provided
50 is a power or ground bus that connects to the circuits 42 via fine-line interconnect lines provided in layer 46; this power or ground bus 50 is typically of wider metal since this power or ground bus carries the accumulated current or ground connection for the devices 42
52 is a power or ground pin that passes through the layer 48 of passivation and that has been connected to the power or ground bus 50.
From the above the following can be summarized: circuits 42 and 44 are created in or on the surface of a silicon substrate 40, interconnect lines in layer 46 are created for these circuits 42 and 44 for further interconnection to external circuitry, the circuits 42 and 44 are, on a per I/O pin basis, provided with an ESD circuit 44, these circuits 42 together with the ESD circuit 44 are connected to a power or ground pin 52 that penetrates a layer 48 of passivation. The layer 48 of passivation is the final layer that overlies the created interconnect line structure, and the interconnect lines underneath the layer 48 of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.
Relating to the cross section that is shown in FIG. 1, the following comments applies: ESD circuits 44 are, as is known-in the art, provided for the protection of semiconductor circuits 42 against unexpected electrical charges. For this reason, each pin that connects to a semiconductor circuit 42 must be provided with an ESD circuit 44.
FIG. 2 shows a cross section of a prior art configuration that resembles the cross section shown in FIG. 1. The structure that is shown in cross section in FIG. 2 however addresses only and is limited to clock and signal distribution networks. FIG. 2 shows in addition (to the previously highlighted aspects of FIG. 1):
45 are two ESD circuits that are provided in or on the surface of the substrate 40; ESD circuits 45 are always required for any external connection to an input/output (I/O) pin 56
45′ which are circuits that can be receiver or driver or I/O circuits for input (receiver) or output (driver) or I/O purposes respectively
54 is a clock bus
56 is a clock or signal pin that has been extended through the layer 48 of passivation.
The same comments apply to the cross section that is shown in FIG. 2 as previously have been made with respect to FIG. 1, with as a summary statement that the layer 48 of passivation is the final layer that overlies the created structure, and the interconnect lines in layer 46 underneath the layer 48 of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.
Further applies to the cross section that is shown in FIG. 2, where pins 56 are signal or clock pins:
pins 56 must be connected to ESD circuits 45 and driver/receiver or I/O circuits 45′
for signal or clock pins 56, these pins 56 must be connected not only to ESD circuits 45 but also to driver or receiver or I/O circuits, highlighted as circuits 45′ in FIG. 2
after (clock and signal) stimuli have passed through the ESD circuits 45 and driver/receiver or I/O circuits 45′, these stimuli are further routed using, under prior art methods, fine-line interconnect wires in layer 46. A layer 48 of passivation is deposited over the dielectric layer 46 in which the interconnect network has been created.
It is therefore of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity.
USPTO Backgrounds
USPTO Backgrounds