Microprocessor-accessible memory devices have traditionally been classified as either non-volatile or volatile memory devices. Non-volatile memory devices are capable of retaining stored information even when power to the memory device is turned off. Traditionally, however, non-volatile memory devices occupy a large amount of space and consume large quantities of power, making these devices unsuitable for use in portable devices or as substitutes for frequently-accessed volatile memory devices. On the other hand, volatile memory devices tend to provide greater storage capability and programming options than non-volatile memory devices. Volatile memory devices also generally consume less power than non-volatile devices. However, volatile memory devices require a continuous power supply in order to retain stored memory content.
Research and development of commercially viable memory devices that are randomly accessed, have relatively low power consumption, and are non-volatile is ongoing. One ongoing area of research is into resistive memory cells where resistance states can be programmably changed. One avenue of research relates to devices that store data in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied programming voltages, which in turn change cell resistance. Examples of variable resistance memory devices being investigated include memories using variable resistance polymers, perovskite, doped amorphous silicon, phase-changing glasses, and doped chalcogenide glass, among others.
FIG. 1A shows a basic composition of a variable resistance memory cell 10 constructed over a substrate 11, having a variable resistance material 16 formed between a bottom electrode 14 and a top electrode 18. The bottom electrode is located within an insulating layer 12. One type of variable resistance material may be amorphous silicon doped with V, Co, Ni, Pd, Fe and Mn as disclosed in U.S. Pat. No. 5,541,869 to Rose et al. Another type of variable resistance material may include perovskite materials such as Pr(1-x)CaxMnO3 (PCMO), La(1-x)CaxMnO3 (LCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO) as disclosed in U.S. Pat. No. 6,473,332 to Ignatiev et al. Still another type of variable resistance material may be a doped chalcogenide glass of the formula AxBy, where “B” is selected from among S, Se and Te and mixtures thereof, and where “A” includes at least one element from Group III-B (B, Al, Ga, In, Tl), Group IV-B (C, Si, Ge, Sn, Pb), Group V-B (N, P, As, Sb, Bi), or Group VII-B (F, Cl, Br, I, At) of the periodic table, and with the dopant being selected from among the noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni, as disclosed in U.S. Pat. Nos. 6,881,623 and 6,888,155 to Campbell et al. and Campbell, respectively. Yet another type of variable resistance material includes a carbon-polymer film comprising carbon black particulates or graphite, for example, mixed into a plastic polymer, such as that disclosed in U.S. Pat. No. 6,072,716 to Jacobson et al. The material used to form the electrodes 14, 18 can be selected from a variety of conductive materials, such as tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among others.
Much research has focused on memory devices using memory elements composed of chalcogenides. Chalcogenides are alloys of Group VI elements of the periodic table, such as Te or Se. A specific chalcogenide currently used in rewriteable compact discs (“CD-RWs”) is Ge2Sb2Te5. In addition to having valuable optical properties that are utilized in CD-RW discs, Ge2Sb2Te5 also has desirable physical properties as a variable resistance material. Various combinations of Ge, Sb and Te may be used as variable resistance materials and which are herein collectively referred to as GST materials. Specifically, GSTs can change structural phases between an amorphous phase and two crystalline phases. The resistance of the amorphous phase (“a-GST”) and the resistances of the cubic and hexagonal crystalline phases (“c-GST” and “h-GST,” respectively) can differ significantly. The resistance of amorphous GST is greater than the resistances of either cubic GST or hexagonal GST, whose resistances are similar to each other. Thus, in comparing the resistances of the various phases of GST, GST may be considered a two-state material (amorphous GST and crystalline GST), with each state having a different resistance that can be equated with a corresponding binary state. A variable resistance material such as GST whose resistance changes according to its material phase is referred to as a phase change material.
The transition from one GST phase to another occurs in response to temperature changes of the GST material. As shown in FIG. 2, the GST material has a melting temperature Tm and a crystallization temperature Tx. The crystallization temperature Tx is lower than the melting temperature Tm. Both the crystallization temperature Tx and the melting temperature Tm are higher than room temperature. When the GST material is heated above the melting temperature Tm, the GST material loses its crystalline structure. If the GST material is then rapidly cooled to room temperature, the GST material is formed into an amorphous state—the cooling occurs too fast to allow a crystalline structure to grow. On the other hand, if the GST material is warmed to a temperature above the crystallization temperature Tx but below the melting temperature Tm, a crystalline structure is able to grow. Once converted into a crystalline structure, the GST material remains in a crystalline structure until it is again heated above the melting temperature Tm. In other words, at room temperature, the GST material is stable in either the amorphous or crystalline phases.
In a phase change memory cell, the heating and cooling can occur by causing differing strengths of current to flow through the GST material. The GST material is placed in a crystalline state by passing a crystallizing current through the GST material, thus warming the GST material to a temperature wherein a crystalline structure may grow. A stronger melting current is used to melt the GST material for subsequent cooling to an amorphous state. As the typical phase change memory cell uses the crystalline state to represent one logic value, e.g., a binary “1,” and the amorphous state to represent another logic value, e.g., a binary “0,” the crystallizing current is referred to as a set current ISET and the melting current is referred to as an erase or reset current IRST. One skilled in the art will understand, however, that the assignment of GST states to binary values may be switched if desired.
The state of the GST material is determined by applying a small read voltage Vr across the two electrodes and by measuring the resultant read current Ir. A lower read current Ir corresponds to a higher resistance. Thus, a relatively low read current Ir signifies that the GST material is in an amorphous state and a relatively high read current Ir signifies that the GST material is in a crystalline state.
The phase-changing current is applied to the GST material via electrodes that bound the GST material. In FIG. 1B, for example, the phase-changing currents are applied via the bottom electrode 14 and the top electrode 18. Because of the configurations of the bounding surface areas of the two electrodes, current densities 50 within the GST material are not equally distributed. In particular, current densities 50 near the bottom electrode 14 are greater than the densities near the top electrode 18. Furthermore, areas of the GST material that are directly in between the two electrodes 14, 18 have higher current densities 50 than areas that are not directly in between the two electrodes 14, 18, such as areas near the lower corners of the GST material.
The uneven current distribution has two significant effects. First, the area of highest current density is the area most responsive to reset currents IRST and set currents ISET. This most responsive area is near the smaller lower electrode. Second, because certain areas of the GST material have a very low current density, these areas may not be as responsive to phase-changing currents. These areas may include not only the lower corners of the GST material but also significant portions of the lower edge of the GST material. It is even possible that regions near the lower electrode and lower edge may have insufficiently high current densities to fully transform the phase of the entire region of GST material near the lower electrode. In other words, the application of a read voltage Vr could result in stray or leak currents through incompletely transformed regions of the GST material, thus resulting in erroneous GST phase state determination.
A current distribution graph 90 is illustrated in FIG. 1C. The graph 90 illustrates a cross-sectional view of the right half (which mirrors the left half) of the phase change material 16 of memory cell 10. The top edge of the phase change material 16 is identified near the top of the graph 90. The bottom edge of the phase change material 16 coincides with the bottom edge of the graph 90. The right edge of the phase change material 16 would be located just beyond the right side of graph 90. The left side of graph 90 represents the center or the horizontal midpoint of the phase change material 16. When a current is passed from the bottom electrode 14 to the top electrode 18 of memory cell 10, the current passes through the phase change material 16. The distribution of the current within the phase change material 16 is depicted in FIG. 1C. Isometric contour lines 92 represent the current density of an applied reset current IRST. The graph 90 shows that current is more broadly distributed in the vertical direction (towards the top electrode 18) than in the horizontal direction. It is desirable, however, to redistribute the current density horizontally to achieve better conversion of the phase change material to the amorphous GST state upon application of a phase changing current, thus reducing leak currents. As a result, the required programming currents to achieve the same RESET resistance may also be reduced. Such a redistribution may also assist in the operation of other resistance memory materials as well.
Accordingly, methods and structures that reduce resistive memory, e.g., phase change memory, leak currents and programming currents are desired.
USPTO Backgrounds
USPTO Backgrounds