The present disclosure relates generally to phase shifter topology. More particularly, the present application relates to a phase shifter topology that may be used in an electronically scanned array (ESA) and in other devices that require precision phase control.
In known phase shifter topology, the phase shifter divides the amplified signal from a variable amplitude controller into an in-phase (I) signal and quadrature-phase (Q) signal. The variable amplitude controller provides amplitude shaping of the signal, while the quadrature phase shifter provides for 0-180° quadrant control for the I and Q signals to achieve full 360° control. In this topology, the quadrature phase shifter has two sets of transistor pairs for the I input to create the differential in-phase signals I+ and I−, and two sets of transistor pairs for the Q input to create the differential quadrature-phase signals Q+ and Q−, for a total of eight transistors.
For the eight transistor phase shifter design, the necessity to perform the 0-180° quadrant control for the I and Q signals requires additional voltage overhead due to vertical transistor stacking. Further, the necessity to perform the outphase of the I and Q signals requires extra parasitic loading on the inputs, because only two of the four transistors in each cell are actively biased on at any point depending on the quadrant selected.
USPTO Backgrounds
USPTO Backgrounds