The present invention relates to a voltage generating circuit, and more particularly to a voltage generating circuit which divides a potential difference between a high potential power supply and a low potential power supply to generate a divided voltage and is used in a digital-to-analog (D/A) converter.
Semiconductor devices often have circuits, such as a D/A converter and a current generating circuit fabricated on a single semiconductor substrate. The D/A converter should improve the precision of linearity of its analog output signal.
FIG. 1 is a circuit diagram of a D/A converter 11 of a resistance string system mounted on a semiconductor device.
The D/A converter 11 divides a potential difference between a high potential power supply VDD and a low potential power supply VSS into 16 uniform portions and generates an analog signal Aout having a potential ((VDD-VSS).times.(n/16)+VSS) corresponding to the digital signal D2-D0. The D/A converter 11 includes a voltage dividing circuit 12 having resistors R1 to R8, where the number corresponds to the three bit digital signal D2 to D0, switches SW1 to SW6, and inverter circuits 13 to 15. The resistors R1 to R8 are connected in series between the high potential power supply VDD and the low potential power supply VSS. The value of each resistor R1 to R8 is weighted in accordance with the bit number (in this case, three bits) of the digital signal D2 to D0.
When the resistor R1 has a reference value "1", then the resistors R2 and R7 have a value of "1", the resistors R3, R6 "2", and the resistors R4, R5, R8 have a value of "4". The value of each resistor R1 to R8 is weighted by connecting a predetermined number of resistor elements in parallel each having the identical value. That is, the resistors R4, R5, R8 are each formed with single resistor element, the resistors R1, R2, R7 are each formed with four resistor elements having the same value as that of the resistors R4, R5, R8, by connecting them in parallel, and the resistors R3 and R6 are each formed with two resistor elements connected in parallel.
The resistors R2 and R3 provided near the high potential power supply VDD are connected in parallel with the switches SW3 and SW4, respectively, while the resistors R6 and R7 provided near the low potential power supply VSS are connected in parallel with the switches SWS and SW6, respectively. Each of the switches SW3 and SW4 is formed of a P-channel MOS transistor and each of the switches SW5 and SW6 is formed of an N-channel MOS transistor. Each of the switches SW3 and SW6 is supplied at its gate with an inverted digital signal D0 inverted by the inverter circuit 15, and each of the switches SW4 and SW5 is supplied at its gate with an inverted digital signal D1 inverted by the inverter circuit 14. In this way, the switches SW3 to SW6 are turned on or off in accordance with the lower 2-bits of the digital signal.
For example, if the lower 2-bits of the digital signal D1, D0 have a status of "00", then the switches SW3 and SW4 are turned off while the switches SW5 and SW6 are turned on. Thus, the resistor value between the node N2 and the low potential power supply VSS is set to "4"while the resistor value between the high potential power supply VDD and the node N1 is set to "8". If the lower 2-bits D1, D0 have a status of "01", then the switches SW4 and SW6 are turned off while the switches SW3 and SW5 are turned on. Thus, the resistor value between the node N2 and the low potential power supply VSS is set to "5" while the resistor value between the high potential power supply VDD and the node N1 is set to "7".
The resistor value between the node N1 and the node N2 is always set to "4" (the resistor value of the resistor R5). Thus, the arrangement of the D/A converter 11 controls the switches SW3 to SW6 so that the resistor value between the high potential power supply VDD and the low potential power supply VSS is always maintained to have a constant value, "16". The D/A converter 11 changes successively the resister value between the high potential power supply VDD and the node N1 and the resistor value between the node N2 and the low potential power supply VSS in accordance with the lower 2-bits of the digital signal D1, D0.
The potentials of the nodes N1 and N2 are determined by the potential difference between the high potential power supply VDD and the low potential power supply VSS, the resistor value between the high potential power supply VDD and the node N1, the resistor value between the nodes N1 and N2, and the resistor value between the node N2 and the low potential power supply VSS. Thus, the D/A converter 11 changes the potentials at the nodes N1 and N2 by a step of one-sixteenth potential difference between the high potential power supply VDD and the low potential power supply VSS in accordance with the lower 2-bits of the digital signal D1, D0.
The D/A converter 11 turns one of the switches SW1 and SW2 on in accordance with the higher bit digital signal D2. When one of the switches SW1 and SW2 is turned on, a divided voltage corresponding to the turned on switch is provided from the D/A converter 11 as an analog signal Aout.
However, even if each of the switches SW3 to SW6 is turned on, turned-on switch status does not become a conductor having no resistor value or 0 ohm (.OMEGA.). Therefore, it follows that the resistor value of the turned-on switch SW1a to SW3b is connected in parallel with the resistor R2, R3, R6, R7. Furthermore, the switches SW3 to SW6 are connected to the resistors R2, P3, R6, R7 by way of conductive wires and hence the resistor component of the wire must be counted as a resistor value of the circuit. As a result, an error is caused in the resistor value between the node N1 and the high potential power supply VDD and the resistor value between the node N2 and the low potential power supply VSS, leading to a variation in the potential difference between the node N1 and the node N2. Due to this variation of the potential difference, the voltage between the high potential power supply VDD and the low potential power supply VSS is not accurately divided into 16 portions. This results in a deterioration of the accuracy of conversion from the digital signal D2 to D0 to the analog signal Aout.
USPTO Backgrounds
USPTO Backgrounds