1. Technical Field
The present invention relates to integrated circuit device testers, and more particularly to a package test handler for supporting a number of packaged integrated circuits during testing.
2. Related Art
Integrated circuit (IC) devices typically include an IC chip that is housed in a plastic, ceramic or metal package. The IC chip typically includes a circuit fabricated by lithographically patterning conductive and insulating materials on a thin wafer of semiconductor using known fabrication techniques. The package supports and protects the IC chip and provides electrical connections between the circuit and an external circuit or system.
IC devices are tested after manufacture to assure they meet performance specifications before shipment to customers. ICs undergoing such tests include Programmable Logic Devices (PLDs) that are capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs).
Modern PLDs are highly complex and often include more than one hundred Input/Output structures and associated bonding pads that access the programmable logic circuitry therein. To support the large number of I/O structures, PLDs are typically mounted in a package including multiple external contacts (e.g., pins, solder balls/bumps, or wire leads). Several package types are used to house PLD chips, including ball grid arrays (BGAs), pin grid arrays (PGAs), plastic leaded chip carriers, and plastic quad flat packs. The package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e., the number of input/output terminals), and also in accordance with a customer's requirements.
FIG. 1 shows a side cross-sectional view of a typical IC 100 including an IC chip 110 mounted on an upper surface 122 of a package substrate 120. Electrical connections between bonding pads 115 of IC chip 110 and contact pads 125 formed on upper surface 122 of substrate 120 are provided by bond wires 130. A plurality of solder balls 126 extend from a lower surface of substrate 120 which are electrically connected to the conductive lines (not shown) and conductive vias 128 that are provided on substrate 120. Electrical signals travel between each solder ball 126 and one bonding pad 115 of IC chip 110 along an associated conductive via 128 and bond wire 130.
IC manufacturers typically use IC testing systems to test their packaged IC devices before shipping to customers. IC testing systems typically include a device tester, a device handler and an interface apparatus. A device tester is an expensive piece of computing equipment that transmits test signals to the IC device under test via tester probes and the interface apparatus. The interface apparatus is typically a printed circuit (PC) board that connects to the device tester with lines running from the tester to contacts for connecting to package connections (pins or balls). A device handler is an expensive robot that precisely supports the interface apparatus and automatically moves IC devices from a storage area to contact the interface apparatus and then puts the packages back into the storage area. Such testing systems are well known.
FIG. 2 shows a side cross-sectional view of a conventional package test interface apparatus, with supporting handler components connected to test an IC package. The interface apparatus includes a PC board 210 having mounted thereon a plurality of contact members (i.e., pogo pins) 220 and a contactor body 240. PCB 210 includes connection structures (not shown) for receiving test signals from a device tester, and conductive lines (also not shown) for transmitting signals between the connection structures and pogo pins 220. Contactor body 240 includes four walls that are formed into a generally square or rectangular frame through which pogo pins 220 extend. A non-conductive plate 250 is mounted on an upper surface of contactor body 240 for aligning pogo pins 220 such that a tip 224 of each pogo pin 220 is aligned to mate with contacts 126 on a chip package 100. Mounted on an upper surface of plate 250 is a package handler docking plate 270 with an opening area 275 that functions to align the contacts 126 of package 100 with pogo pins 220 of the interface apparatus. Alignment pins 200 are provided through holes secure the package handler to the printed circuit board 210 to provide precise alignment so that the pitch of the package contacts matches the pitch of the pogo pins 220.
During a test procedure, an IC package 100 is lowered into IC receiving area 275 of package handler docking plate 270 by a device handler arm 280 that fixedly holds the package 100. Alignment structures 270 are formed with slanted walls 277 that facilitate “rough” alignment by causing the package IC 100 to slide into IC receiving area 275. Subsequently, of each solder balls 126 become engaged to provide “fine” alignment relative to pogo pins 220.
Although the contacts are shown as pogo pins 220 with supports 240 and 250 to align the pogo pins 220 to contact the package contacts, other type connections are attachable to the PC board 210 of the interface apparatus. Instead of pogo pins 220, metal contact bumps can be used with the support structures 240 and 250 being unnecessary. Similarly, if the IC package has a lead frame instead of a ball grid array for contacts, the pogo pins 220 can be replaced by sockets to contact the leads. In either case, a docking plate 270 with slanted walls 277 and/or alignment holes for inserting pins 200, can form part of the handler to guide the IC package contacts so they align with contacts on the PC board 210.
For a typical handler, a maximum of four IC packages are typically tested at one time because of limitations of the handler allowing testing of only a limited number of ICs with a large package size and/or a large pin count, such as with FPGAs or CPLDs. The complete handler docking plate 270, thus has four openings 275 for inserting IC packages, creating a quad site docking plate 270 as part of the package test handler attachable to the PC board 210.
With multiple layered PC boards, connection lines can be distributed through the layers of the interface apparatus to enable more than four IC package connection sites to be provided on a PC board. The handler for one interface apparatus package site configuration, however will typically not fit an interface apparatus with a second package site interface configuration. Because of the high cost of the robotic handler, purchasing a new handler to accommodate more than one interface apparatus configuration is typically prohibitively expensive. Continued use of an old handler that tests only a few IC packages at a time must be weighed against the expense of purchasing a new handler to test more IC packages at one time.
It is desirable to provide a handler that can be configured to be used with more than one interface apparatus, without suffering the costs of purchasing a new handler. Further, it is desirable to make a handler adaptable so that old interface apparatuses may be continually used that test a lower number of IC packages until the interface apparatus wears out, while new interfaces that test a greater number of IC packages at one time are integrated into a test system.
USPTO Backgrounds
USPTO Backgrounds