1. Field of the Invention
The present invention relates generally to processes for semiconductor metrology and more particularly to verification of measured metrology data.
2. Description of Related Art
A typical microelectronic device or circuit may consist of twenty to thirty levels, or pattern layers. The placement of particular features on any level need to match the placement of corresponding features on other levels, i.e. there must be overlap, within an accuracy that is some fraction of the minimum feature size or a critical dimension (CD).
Overlay registration is a translational error that exists between features exposed layer to layer in the vertical manufacturing process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error. The physical sources of these errors are generally distinct; inter-field errors are generally due to imaging objective aberrations or possibly scanning dynamics while intra-field errors are usually due to the wafer alignment system and the wafer stage. Typically, in order to measure overlay error using conventional optical metrology tools, special arrays of alignment attributes or overlay targets are printed or imaged onto a properly designed recording media using a photolithographic imaging system. Recording media includes: positive or negative photoresist, optically activated liquid crystals, electronic CCD or diode imaging arrays, optically sensitive recording devices, and photographic film.
FIG. 9 is an illustration of some of the many different kinds of alignment attributes or overlay targets available, including box-in-box 902, frame-in-frame 904, segmented frame-in-frame 906, multi-segmented frame-in-frame 908, phase gratings 910, verniers, and electrical test structures. See Direct-referencing automatic two-points reticle-to-wafer alignment using a projection column servo system, M. Van den Brink, H. Linders, S. Wittekoek, SPIE Vol. 633, Optical Microlithography V, 60:71, 1986; Automated Electrical Measurements of Registration Errors in Step and Repeat Optical Lithography Systems, T. Hasan et al., IEEE Transactions on Electron Devices, Vol. ED-27, No. 12, 2304:2312, December 1980; Capacitor Circuit Structure for Determining Overlay Error, U.S. Pat. No. 6,143,621 to K. Tzeng, et al. Alignment attributes, such as the ones illustrated in FIG. 9, are used with photolithographic overlay tools. See, for example, KLA 5105 overlay brochure, KLA-Tencor; KLA 5200 overlay brochure, KLA-Tencor; Measuring system XY-5i, K. Kodama et al., SPIE Vol. 2439, 144:155, 1995; and Apparatus and Method of Measurement and Method of Data Analysis for Correction of Optical System, U.S. Pat. No. 5,828,955 to Smith et al.
FIG. 5(a) shows a typical overlay displacement vector 502 representing the x-shift and y-shift vector overlay error associated with a misaligned frame-in-frame alignment attribute. In some cases the overlay error can be measured using special in-situ exposure tool metrology See Direct-referencing automatic two-points reticle-to-wafer alignment using a projection column servo system, supra. Many commercial software packages exist (see A Computer Aided Engineering Workstation for Registration Control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266 1989; Matching of Multiple Wafer Steppers for 0.35 Micron Lithography using Advanced Optimization Schemes, M. van den Brink, et al., SPIE Vol. 1926, 189:207, 1993, (hereinafter Kiass II)) that model and statistically determine the relative magnitude of the systematic and random inter-field and intra-field error components for the purpose of process control, projection lens adjustment, wafer stage calibration, and exposure tool set-up. Other methods such as described in U.S. Pat. Nos. 5,978,085 and 5,828,455 both entitled “APPARATUS, METHOD OF MEASUREMENT, AND METHOD OF DATA ANALYSIS FOR CORRECTION OF OPTICAL SYSTEM” to Adlai Smith, Bruce McArthur, and Robert Hunter, and both incorporated in their entirety herein, use overlay techniques to determine the lens aberrations of the photolithographic exposure tool or machine.
Over the past thirty years the microelectronics industry has experienced dramatic rapid decreases in critical dimension by constantly improving photolithographic imaging systems. Today, these photolithographic systems are pushed to performance limits. As the semiconductor industry rapidly approaches limits of optical lithography new metrology techniques will be needed to measure the integrity of the photolithographic exposure machines and the devices they help produce. Specifically, metrology techniques that can accurately determine the aberrations of the projection system as well as the alignment precision of the exposure machines will be a necessity. In addition, these new metrology techniques will require advances in the methods used to guarantee the integrity of the data.
For some applications, such as very high rate overlay sampling on semiconductor production wafers, overlay registration results are not that sensitive to the exact sampling in terms of target position and other parameters. For example, a typical semiconductor manufacturing facility might, for purposes of process control, monitor the day to day alignment accuracy of an photolithographic tool by measuring a small number of overlay targets on a small group of production wafers, see for example FIGS. 14(a), 14(b), 14(c) and 15(b). See Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, J. Pellegrini, SPIE Vol. 3677, 72:82, 36220.
Typically, a sampling plan may involve measuring approximately twenty alignment attributes on each wafer and calculating the statistical distribution of overlay error associated with each group of wafers. Also, overlay variations from wafer to wafer over time can be observed to ascertain process stability. Generally, it is possible to determine significant changes in the performance of the photolithographic alignment process even when some of the overlay data is missing or parsed in the wrong order. This is mainly due to the statistical methods that are used to calculate the magnitude and direction of the spatially dependent components of overlay error See A New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March 1999; Semiconductor Pattern Overlay, supra.
However, in interferometric applications the reconstruction of the lens aberrations depends in large part on the proper reading and sequencing of large volumes of overlay data. Although in principle it should not be difficult to program an overlay tool to read alignment attributes in the correct order, there are a few programming and machine limitations that make the task difficult in practice. For example, the programming of optical overlay tools is usually sensitive to many parameters, such as desired measurement spacing, the alignment attribute size, the field point desired, and the spatial density of alignment attributes. This may be further aggravated by the fact that the reconstructed wavefront does not lend itself to an intuitive understanding of what the local overlay should look like. In addition, some overlay tools do not print or report the output using a simple coding system, making it difficult to debug the program.
In general, most overlay tools have no way of independently verifying if the overlay job deck has been programmed correctly or if the overlay tool is measuring correctly. Thus, to provide an independent verification of the program and operation of overlay tools for applications sensitive to such kinds of errors, a simple means of independently determining the programming and functioning of the overlay tool is desirable. In addition, it would be advantageous if the results of the verification are unambiguous and can be used to debug and monitor the overlay tool and/or its programming.
USPTO Backgrounds
USPTO Backgrounds