The present invention relates to the area of electronic design automation of logic design and in particular, to an aspect of optimizing a logic design known as register retiming.
Integrated circuits are important building blocks of the modern age. Technology continues to evolve and integrated circuits continue to provide improved functionality. As integrated circuits improve, so do the electronic systems that are built using integrated circuits. There are many types of integrated circuit such as memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic. Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also included embedded functionality such as user-programmable memory or RAM, digital signal processors (DSPs), and on-board microcontrollers such as ARM-based or MIPS-based controllers.
As integrated circuits become more complex and provide more functionality in a smaller die size, it also becomes increasingly difficult to ensure the logic functions are implemented properly and in an optimal way. Modern digital integrated circuits have many transistors and many logic gates, more so than can be optimized manually in a reasonable amount of time, especially when time-to-market is critical in ensuring a product's success. As a specific example, a typical programmable logic design today surpasses the multimillion-gate mark.
Computer aided design (CAD) and electronic design automation (EDA) tools are available to assist engineers with the design and verification tasks. These tools are especially helpful for complex logic designs. But even with the help of computer-aided tools, the process of optimizing an integrated circuit design can be time-consuming because of the large number of variables involved. It is desirable that the design automation task is done time efficiently even for large designs. Further, it is desirable the design automation tool maximizes performance or otherwise improve an aspect of an integrated circuit design. Some other aspects of a design that a tool may help with include improving critical path performance, removing metastability, reducing the number of logic gates used, checking or verifying functionality, removing race conditions, and others.
A specific performance measure in a design is fmax or FMAX, which is the maximum clock frequency which the integrated circuit can operate before logic errors will occur. It is desirable to optimize a logic design to provide the highest fmax frequency possible or equivalently, minimize the longest delay path. A logic design having registered or sequential logic may have logic paths where there can be increase in fmax frequency by rearranging the logic, such as register retiming. When improving the fmax, it is desirable that the equivalent or same functionality is provided as the original logic design, metastability is not introduced into the design, and the improved design is logical legal. It is important to be careful when implementing retiming because retiming can be a relatively dangerous operation in a synthesis flow due to its effects on simulation, verification and debug, and other issues such as metastability, and because a timing visibility early in a CAD flow is typically significantly less than desired.
As can be appreciated, there is a need to provide an electronic design automation system to evaluate and then improve the performance of an integrated circuit design, and in particular to provide retiming to improve the fmax frequency of a sign. This system may be specially suited to handling designs for programmable logic.
USPTO Backgrounds
USPTO Backgrounds