1. Field of the Disclosure
Generally, the present disclosure relates to semiconductor devices and respective manufacturing techniques in which ferroelectric materials may be implemented in view of extending functionality and/or enhancing performance of circuit elements of sophisticated semiconductor devices.
2. Description of the Related Art
Significant progress has been made in the field of semiconductor devices over the recent decades due to the continuous reduction of critical dimensions of field effect transistors. In recent developments, critical dimensions of transistor elements have reached 30 nm and even less in sophisticated planar device architectures, thereby achieving extremely high integration density and, therefore, providing the possibility of integrating more and more functions into a single integrated circuit. For example, the CMOS technique has proven to be a viable concept of forming powerful logic devices, such as microprocessors and the like, wherein P-type transistor elements and N-type transistor elements represent the backbone of high performance, low power semiconductor devices. Many of the advantages of sophisticated semiconductor devices have been gained by steadily reducing critical dimensions of respective circuit elements, wherein, however, a plurality of associated problems have to be addressed in order to fully exploit many of the performance advantages achieved by reduced critical dimensions. For example, dielectric materials used for isolating specific conductive regions from each other may give rise to a certain capacitance that significantly depends on the dielectric constant of the respective dielectric material. In some instances, the capacitance associated with the provision of a dielectric material between two conductive regions of a semiconductor device may be considered as an important characteristic for the correct functioning of such devices when a respective capacitive coupling is a necessity for the correction functional behavior. In other cases, a corresponding capacitance associated with a dielectric material may be considered as a parasitic capacitance and may, therefore, result in performance degradation of sophisticated circuit elements, such as field effect transistors and the like.
In many approaches, complex high-k dielectric material systems have been developed in an attempt to further improve overall transistor performance, wherein it has been recognized that some of these material systems may have ferroelectric characteristics, which may also be taken advantage of upon forming sophisticated transistor devices, capacitors and the like. Therefore, great efforts are being made in establishing material systems having ferroelectric characteristics.
In “Stabilization of metastable phases in hafnia owing to surface energy effects,” Batra et al., Applied Physics Letters, 108:172902, 2016, it is speculated that metastable polar phases of hafnium oxide may be stabilized on the basis of finite size effects due to small grain sizes and film thickness, wherein these speculations are based on first principle calculations and a very basic model of the total potential energy of hafnium oxide particles of finite dimensions.
In “Ferroelectric Si-Doped HfO2 Device Properties on Highly Doped Germanium,” Lomenzo et al., IEEE Electron Device Letters, 36:766-68, August 2015, experimental results are provided indicating that the material composition of a surface layer on which a silicon-doped hafnium oxide material is deposited may significantly influence the obtained ferroelectric characteristics, wherein, in particular, a germanium substrate may represent a promising candidate for forming thereon silicon-doped hafnium oxide material so as to exhibit superior ferroelectric characteristics.
Although promising developments may be currently seen in the field of semiconductor fabrication, it, nevertheless, appears that a reliable and flexible process strategy for implementing device characteristics on the basis of high-k dielectric materials into sophisticated semiconductor devices, including, for instance, field effect transistors and the like, may not be presently available.
In view of the situation described above, the present disclosure relates to techniques for providing device characteristics, in particular, for electrostatically influencing charge carriers in a semiconductor region of interest, while avoiding or at least reducing the effects of one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds