As known in the computing arts, an event counter is a unit that can count occurrences of a certain condition. Hardware event counters are used for statistical counts, debugging during hardware bring-up and for performance characterization. The insight attained from performance monitors is used to resolve performance bottlenecks and in fine tuning configurable parameters in the system. Event counters are also used to trigger actions. For example, when an event counter reaches certain threshold, it could be used to generate an interrupt. In applications for event counters such as these and more, there is a strong need for precise counts.
A conventional implementation of a 64 bit counter involves the use of 64 registers as storage elements and of an adder to increment the count. Hundreds of 64 bit counters can normally occupy a significant amount of silicon space on ASICs (application-specific integrated circuits). In the case of an FPGA (field programmable gate array) based implementation, where there are limited number of logic building blocks (e.g., Look-Up Tables, or LUTs), the conventional manner of implementing hundreds of counters will consume a very significant number of LUTs.
Since ASICs and FPGAs provide a dense Random Access Memory (RAM) core, this has motivated a desire to substitute RAM for registers. Some attempts have been made to address this problem by implementing a plurality of counters into RAM (e.g., “RAM based events counter apparatus and method” (U.S. Pat. No. 5,089,957) and “System for gathering data representing the number of event occurrences” (U.S. Pat. No. 4,206,346). However, these prior attempts have presented potentially lossy schemes that do not take into account the frequency of the counted events. Accordingly, a compelling need has been recognized in connection with improving upon such shortcomings and disadvantages.
USPTO Backgrounds
USPTO Backgrounds