Field of the Invention
The present invention relates to a semiconductor component which is provided on a top side with a resistive planar passivation, such as is suitable, in particular, as a top layer of constant thickness with a planar bearing surface for capacitively measuring fingerprint sensors.
When a surface of a semiconductor component is exposed to the surrounding atmosphere and, as in the case of a fingerprint sensor, is exposed to mechanical wear, it is necessary to passivate that surface so as to maintain functionality of the component. Such a passivation is particularly critical in the case of capacitively measuring micromechanical components, in which it is necessary to maintain a constant distance between an outer top side exposed to wear and conductor surfaces integrated in the component. Particularly with fingerprint sensors in which that outer top side forms a bearing surface for a fingertip, it is essential for that bearing surface to be completely planar, and in addition, even in the case of lengthy stressing, for it to ensure a fixed distance of the applied fingertip from the conductor surfaces provided for the measurement. Silicon oxide layers and silicon nitride layers are the customary passivations in the fabrication of microelectronic components, for example in the material system of silicon. The top side of the semiconductor component is usually provided with connector contacts and conductor tracks for electric wiring. It is possible for various metallization levels to be present which respectively include structured metal layers and are separated from one another by dielectric material (intermediate oxides). It is customary to apply an oxide layer to the top side of the uppermost metallization level. The oxide layer is deposited, for example, from a plasma through the use of CVD (chemical vapor deposition) from an SiH4/N2O atmosphere at approximately 400xc2x0 C., and is typically approximately 300 nm thick. A further passivating layer of silicon nitride (Si3N4) can be deposited thereon from a plasma through the use of CVD in an SiH4/NH3/N2 atmosphere, likewise at approximately 400xc2x0 C. with a typical thickness of 550 nm. Since the metallization level is structured, the passivation deposited over the entire surface cannot be given a planar top side, but is uneven at the edges of the metallization.
It has been proved, in the case of fingerprint sensors, in particular, that indiffusion of sodium can occur because of the contact of the sensors. The reason therefor can firstly be that the passivation has defects which lead to degradation through the occurrence of so-called pinholes. Secondly, even largely conformally deposited layers have growth joints in corners between vertical edges and surfaces parallel to the plane of the layer. The growth joints appear due to increased etching rates and the barrier effect of the passivation can be substantially weakened at the growth joints. The barrier effect cannot be sufficiently improved by applying thicker layers, since the sensitivity of capacitively measuring components decreases too sharply due to the increased thickness of the passivating layer.
It is accordingly an object of the invention to provide a semiconductor component with passivation, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which is passivated in such a way that a top side is planar and a constant distance from an integrated metallization layer is maintained.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising a semiconductor body and a layer structured with interspaces. The layer is carried by the semiconductor body and has a side facing away from the semiconductor body. A passivation covers the side of the structured layer facing away from the semiconductor body and fills the interspaces in the structured layer. The passivation includes at least two double passivating layers applied one above another. The at least two double passivating layers include a double passivating layer disposed furthest from the semiconductor body and a preceding double passivating layer having a planarized top side. Each of the double passivating layers is formed of two passivating layers of different dielectric materials. At least the double passivating layer disposed furthest from the semiconductor body is applied with uniform thickness to the planarized top side of the preceding double passivating layer.
In accordance with another feature of the invention, the double passivating layer contains a passivating layer of oxide and a passivating layer of nitride.
In accordance with a further feature of the invention, the structured layer is a metallization layer applied to at least one layer of a dielectric on a top side of the semiconductor body.
In accordance with a concomitant feature of the invention, the metallization layer forms conductor surfaces of a capacitively measuring fingerprint sensor, and the at least two double passivating layers include a double passivating layer disposed furthest from the metallization layer and having a surface forming a bearing surface for a fingertip.
In the case of the semiconductor component according to the invention, a multilayer passivation is present which includes at least two double passivating layers, and has an uppermost double passivating layer that is applied to a planar surface of the double passivating layer located therebelow. The double passivating layers can be formed in each case by a passivating layer of an oxide, preferably silicon oxide, and a passivating layer of a nitride, preferably silicon nitride. Two such double passivating layers are already sufficient to provide an unexpectedly substantial improvement in the passivating properties of the passivation. However, more than two double passivating layers can also be present. The double passivating layers are composed of two layers of different dielectric materials. It is possible for different double passivating layers to include different pairs of materials. The respective thicknesses of the individual passivating layers can be adapted to the respective dimensions of the component, in particular the dimensions of the structuring of the layer to which the passivation is applied.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor component with passivation, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds