A cell array of a NAND type flash memory is configured as an arrangement of NAND cell units, each NAND cell unit having a plurality of memory cells connected in series therein. The two ends of each NAND cell unit are respectively connected to a bit line and a source line via a select gate transistor.
Control gates of the memory cells in the NAND cell unit are each connected to a different word line. The NAND type flash memory has a plurality of memory cells connected in series sharing a source and a drain, moreover, has the select gate transistors and their bit line contacts and source line contacts and so on shared by the plurality of memory cells, hence a size of a unit memory cell can be reduced, and, moreover, since a shape of the word line or an element region of the memory cell is close to a simple striped shape, the NAND type flash memory is suited to miniaturization, whereby a flash memory of large capacity is achieved.
Incidentally, due to progress in miniaturization of the memory cell in the NAND type flash memory, deterioration of data holding characteristics of the memory cell has become a problem. Specifically, data holding characteristics tend to deteriorate when the cumulative number of times of executions of a write operation/erase operation to the memory cell increases causing progressive deterioration of a gate insulating film of the memory cell. Therefore, sometimes, after completion of the write operation and a write verify operation, a lower limit of the threshold voltage distribution falls to a write verify voltage or less, which leads to deterioration of data holding characteristics of the memory cell.
USPTO Backgrounds
USPTO Backgrounds