1. Field of the Invention
The invention relates to a test apparatus and a method for testing digital electronic systems.
More particularly, the present invention relates to a method and apparatus for testing assemblies forming an electronic digital system which permits testing of the integrated circuits forming each of the assemblies in the testing system to proceed even if the assemblies are misplaced in a testing facility or are missing from the test facility.
2. Description of the Prior Art
A prior art test apparatus has been described, for example, in IEEE Standard 1149.1- 1990 the entire contents of which is incorporated herein by reference. Particular reference is made to pages 1-3 through 1-5 and pages 5-1 through 5-5 of this publication. IEEE Standard 1149.1-1990 is a standard issued by the Institute of Electrical and Electronic Engineers, New York, N.Y., USA, for Test Access Ports (TAP) and Boundary-Scan Architecture, and is hereinafter referred to as "IEEE Standard". The test apparatus is used to test integrated circuits, assemblies and entire structural units of digital electronic systems for defects occurring within the integrated circuits used, as well as in the connection areas of the circuits with circuit boards as well as in the wiring of the test apparatus.
The principle of boundary scanning is employed in the IEEE Standard in which all connections of each integrated circuit are connected with the internal control of the integrated circuit via boundary scan cells integrated in the test apparatus assembly. The boundary scan cells are also controlled by an integrated control circuit which permits the parallel input of test data. The test data is serially input into the boundary scan cells, and into inputs of the integrated circuit. The integrated control circuits enable serial read out of data present at parallel outputs of the integrated circuit which are to be scanned.
The serial inputs and outputs which are connected to form assembly shift registers are switched in series for testing entire structural units, so that all integrated circuits of a structural unit, along with their connections with each other, can be tested via a single serial bus.
To shorten test operation times it is also possible to provide a plurality of serial buses, which respectively allow access to different groups of integrated circuits. The unnecessary interrogation of the boundary scan cells of integrated circuits which do not need to be tested can be avoided by providing bypass registers which are placed to bypass the control circuits of the integrated circuits and bridge the shift registers of the circuits which need not be tested.
A serial structure for a system scan bus using said IEEE Standard would be unsuitable for a higher order testing operation such as the testing of whole structural units with many assemblies, because in this case it would be necessary to pre-set the number of assembly spaces provided or to be provided with components and the positions of the assemblies using the existing test structure. Moreover, if a serial scan bus were used, a change in the number or positions of assemblies to be tested would require changes to the wiring of the scan bus and the test data generated for testing the assemblies to the adjust for the changed testing sequence. On the other hand, a parallel placement of the scan buses would also be disadvantageous, because the multiplication of the signal lines required would have to be designed for the maximum size of the system, so that too many signals would have to be provided on the plug side.
USPTO Backgrounds
USPTO Backgrounds