1. Technical Field
Embodiments of the present invention relate to a multilayered substrate and a method of manufacturing the same.
2. Description of the Related Art
In accordance with a trend toward lightness, miniaturization, an increase in a speed, multi-functionization, and improvement in performance of electronic devices, multilayered substrate technologies in which a plurality of wiring layers are formed on a printed circuit board (PCB) have been developed. Further, technologies in which electronic components such as active elements, passive elements, or the like, are embedded in a multilayered substrate have also been developed.
For example, Patent Document 1 has disclosed a printed circuit board including electronic components inserted into cavities and a plurality of layers, and a method of manufacturing the same.
Meanwhile, one of important subjects in a multilayered substrate field is to allow an embedded electronic component to efficiently transmit and receive signals including a voltage or a current to and from external circuits or other devices.
In addition, as a trend toward improvement in performance of an electronic component and miniaturization and thinness of the electronic component and an electronic component embedded substrate has been recently intensified, it should be necessary to improve a degree of integration of circuit patterns in order to embed a small electronic component in a thin and narrow substrate and connect an external electronic of the electronic component to the outside.
Meanwhile, as the electronic component embedded substrate has been thinned, a warpage phenomenon of the substrate has become a serious problem. The warpage phenomenon is also called warpage. As the electronic component embedded substrate has been made of various materials having different coefficients of thermal expansion, the warpage of the substrate has been intensified.
According to the related art, a method of forming an insulating layer using a material having high rigidity has been used in order to decrease the warpage of the substrate. However, in the case of forming the insulating layer using only the material having high rigidity, since a surface of the insulating layer is rough, there was a limitation in improving a degree of integration of wiring patterns formed on the insulating layer.
In addition, Patent Document 2 has disclosed a technology in which electronic components are embedded on one side of a core substrate and a circuit pattern layer and an insulating layer are built up only in a single direction in order to secure mechanical strength, and Patent Document 3 has disclosed a technology in which a capacitor is disposed at the center of a core substrate and a circuit pattern layer and an insulating layer are built up in both directions.
However, technologies according to the related art including the technologies disclosed in Patent Document 1 to 4, and the like, in which structures and methods that may be implemented in a technology level at that time at which the technologies were developed are universally applied to all electronic components, were not structures optimized based on a role and complexity of each of the electronic components embedded in the board. Therefore, there was a limitation to improve the degree of integration of the wiring patterns while decreasing the warpage phenomenon.
USPTO Backgrounds
USPTO Backgrounds