As semiconductor circuits such as metal-oxide-semiconductor field effect transistors (MOSFETS) are adapted for high voltage applications, problems arise with respect to the current versus voltage response of the device.
In a MOSFET device, such as lateral diffused metal-oxide semiconductor (LDMOS) structures, when a high enough voltage is applied to the gate, a channel under shallow trench isolation (STI) in the non-active region may turn on the parasitic field device. As a result, a leakage current flows through the channel and causes the device's current versus voltage response to adversely deviate from the desired current-voltage relationship.
USPTO Backgrounds
USPTO Backgrounds