1. Field of the Invention
The present invention generally relates to interface circuits, and particularly relates to an input/output interface circuit used in semiconductor devices.
2. Description of the Related Art
There is an increasing demand for semiconductor devices which achieve high-speed operations by using high-frequency signals for data input/output. When frequencies of data-input/output signals are raised with an aim of obtaining high-speed operations, however, various factors that could hamper an effort to increase signal frequencies become increasingly prominent. Such factors need to be removed to achieve high-speed operations.
One of the factors placing a cap on the signal frequencies is a signal skew, i.e., a displacement of signal timings. When an input clock signal used for signal synchronization has a skew, for example, a timing displacement may cause erroneous signal detection when other signals are detected by using this clock signal. The possibility of erroneous detection becomes greater as signal frequencies increase, so that the signal skew makes it difficult to raise signal frequencies to step up an operation speed.
There are several types of skews. A skew with regard to a rise and a fall in a signal (hereinafter referred to as a rise-and-fall skew) has not been particularly addressed in the related art. Here, a rise-and-fall skew refers to a timing displacement which diverts a signal-rise timing and a signal-fall timing from respective desired timings.
FIGS. 1A and 1B are timing charts for explaining a rise-and-fall skew of a clock signal.
FIG. 1A shows a case in which no rise-and-fall skew is present, and FIG. 1B exhibits a case in which a clock signal has a rise-and-fall skew. In FIGS. 1A and 1B, a clock signal is demonstrated along with a reference voltage Vref, which is used for voltage comparison in input buffers. A period Thigh marks an interval during which the clock signal is HIGH when the clock signal is compared with the reference voltage Vref, and a period Tlow indicates a period in which the clock signal is LOW.
In FIG. 1B, the clock signal has a skew because a transition period of signal rise is short (steep rise) and a transition period of signal fall is long (slow fall). In this case, the period Thigh and the period Tlow have different time lengths from those of FIG. 1A. This means that not only is each period elongated or shortened from a normal length thereof, but also a signal-rise timing and a signal-fall timing deviate from their expected timings.
When signal-rise and signal-fall timings are displaced in a clock signal for signal synchronization, other signals may be detected to give erroneous results. Further, if a rise-and-fall skew is in existence in signals such as data signals, a valid period in which the data is regarded as valid has a limited time span defined by the shortest one of the period Thigh and the period Tlow. Because of these, a rise-and-fall skew makes it difficult to raise input/output-signal frequencies to boost an operation speed.
Various factors contribute to generating a rise-and-fall skew. In a signal-output circuit for outputting signals, transition periods are different between a signal rise and a signal fall because of variations in circuit characteristics. That is, a rise-and-fall skew is present even at a point where signals are output from circuits. Further, if a reference voltage Vref used for comparison with input signals fluctuates in input buffers for receiving signals, the period Thigh and the period Tlow end up varying. Moreover, a transition period of signal rise and a transition period of signal fall may be different from each other in input buffers because of a variation in circuit characteristics, serving as another factor to create a rise-and-fall skew.
These factors contributing to generating a rise-and-fall skew are believed to impose the same influence on each signal. This is because output buffers and input buffers generally have the same designs, respectively, when they are used in the same semiconductor devices. Also, the reference voltage Vref is shared by each of the buffers. In consideration of this, it is fair to say that a rise-and-fall skew is a common skew shared by many signals.
Since signal frequencies used in the related art are not high in comparison to effects of skews, measures taken against the rise-and-fall skews in the related art are limited to only crude measures like designing circuits that have a small rise-and-fall skew. Such a measure is not sufficient, and a rise-and-fall skew needs to be actively reduced in order to raise signal frequencies and boost operation speeds.
Accordingly, there is a need for a circuit which can reduce a rise-and-fall skew.
Further, when there are skews between input data signals, timing displacements may cause erroneous data detection.
There are several types of skews. One of the most commonly observed skews is a timing displacement between signals which is caused by different path layouts of signal wiring lines. If each signal line has a different path length, each signal arrives at a destination at a different timing when signals are transmitted from one chip to another chip. Even if path lengths are the same, path-route differences result in capacitance, inductance, etc., varying between signal lines, thereby bringing about a variation in signal propagation speed. When this happens, signals received at the destination end up including inter-signal skews.
The inter-signal skew has been well addressed in the related art, and there are circuits which are designed to reduce inter-signal skews.
The rise-and-fall skew constitutes a problem of its own, as previously described, but also causes a problem when the rise-and-fall skew affects the extent to which inter-signal skews are reduced. When signals including a clock signal for synchronization suffer rise-and-fall skews, a circuit for reducing inter-signal skews may be used. Since each signal timing contains uncertainty owing to a rise-and-fall skew, however, alignment of signals can only be as accurate as this uncertainty. Namely, inter-signal skews can be reduced, but some inter-signal skews commensurate with this uncertainty are bound to remain.
Accordingly, there is a need for a circuit which can reduce an inter-signal skew without being affected by a common skew which is equally present in signals.
USPTO Backgrounds
USPTO Backgrounds