The present invention relates to a clock generator, a pulse generator utilizing the clock generator, and methods thereof, and particularly relates to a clock generator utilizing a delay module with suitable input signal and providing accurate delay amounts to generate an output signal, a pulse generator utilizing the clock generator, and methods thereof.
Conventionally, a delay module (e.g. a delay line) serves to delay an input clock signal in order to generate a desired clock signal, and many circuits or systems are developed utilizing this concept. However, the conventional circuits or systems have several disadvantages as described below.
FIG. 1 is a schematic diagram illustrating a related art frequency dividing operation. As known by persons skilled in the art, a frequency dividing operation is utilized to lower a frequency of a clock signal, and the resultant frequency divided clock signal is utilized as an input signal for the above mentioned delay module. For example, a frequency dividing operation is performed on the original clock signal CLK to generate a frequency divided clock signal Divided_CLK having a frequency half that of the clock signal CLK. Then the frequency divided clock signal Divided_CLK is utilized as an input signal for the above mentioned delay module. However, since the frequency divided clock signal Divided_CLK has a frequency only half or less of the original clock signal CLK, a very high frequency of the original clock signal CLK is needed if the delay module requires a high frequency divided clock signal Divided_CLK.
FIG. 2 is a schematic diagram illustrating a related art skew problem. As shown in FIG. 2, the above-mentioned delay module includes a plurality of delay units, and at least one of the delay selecting signals SEL1, SEL0 is utilized to select whether or not the input signal IN is delayed. However, the input signal IN and the delay selecting signals SEL1, SEL0 should accurately match, otherwise the output signal OUT will have errors. As shown in FIG. 2, a rising edge should be located at the location A but is located at a wrong location B, and therefore an unnecessary signal part Q appears in the output signal OUT. Such a problem is called “Skew” and will become more serious if the input signal IN and the delay selecting signals SEL1, SEL0 have high frequency. In addition, due to this skew problem, the circuits of the delay module must be well designed and the interval between two input signals cannot be too short or the skew problem will become serious.
USPTO Backgrounds
USPTO Backgrounds