Bank interleaving achieves a high-speed process by driving a plurality of memory chips in parallel, the plurality of memory chips being connected to one common IO bus. The plurality of memory chips belongs to different banks.
In an MLC (Multiple Level Cell) flash memory, the time required to write an upper page is several times longer than the time required to write a lower page.
In scheduling of bank interleaving, the order of writing between banks and the order of writing between pages are determined. An increase in the usage ratio of a plurality of banks is important to increase the write throughput. Hence, such scheduling of bank interleaving as to increase the usage ratio of the plurality of banks as high as possible is desired.
USPTO Backgrounds
USPTO Backgrounds