The present invention relates to the design of semiconductor integrated circuits, and more specifically to a design automation system and method for optimizing delay through a group of cells in the integrated circuit design prior to placement and routing.
Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library.
Each cell corresponds to a logical function unit which is implemented by one or more transistors that are optimized for the cell. The logic designer selects the cells according to the number of loads that are attached to the cell, as well as an estimated interconnection required for routing. The cells in the cell library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The cell layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell's transistors and cell routing data. The cell characteristics include a cell propagation delay and a model of the cell's function. The propagation delay is a function of the internal delay and the output loading of the cell.
A series of computer-aided design tools generate a netlist from the schematic diagram or HDL specification of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell (i.e. “fanout”), the placement of each cell and the routed interconnections.
A timing analysis tool is then used to identify timing violations within the circuit. The time it takes for a signal to travel along a particular path or “net” from one sequential element to another depends on the number of cells in the path, the internal cell delay, the number of loads attached to the cells in the path, the length of the routed interconnections in the path and the drive strengths of the transistors in the path.
A timing violation may be caused by a number of factors. For example, a particular cell may not have a large enough drive strength to drive the number of loads that are attached to that cell. Also, exceptionally long routing paths may cause timing violations. Timing violations are eliminated by making adjustments at each stage in the layout process. For example, an under-driven cell may be fixed by changing the logic diagram to include a cell having a larger drive strength. Alternatively, the logic diagram can be changed to divide the loads between one or more redundant cells or buffer cells. An exceptionally long routing path can be corrected by adjusting the placement of the cells.
Once the timing violations have been corrected, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which can be used to fabricate the integrated circuit.
Optimization algorithms are now being used to assist the logic designer in optimizing areas of the logic design that contain large, multiple-input function blocks, such as large AND, OR and XOR blocks and large buffer trees having multiple “fanouts”. These blocks can be implemented with a variety of circuit configurations. An optimization algorithm optimizes these large function blocks by expanding the blocks into smaller logical functions based on certain optimization decisions. Unfortunately, prior to placement and routing, there is little timing information on which to base the optimization decisions. Optimization decisions are based on only rough timing estimates of the delay through each logical function and typical routing path lengths. This is particularly true when the logic design is being synthesized into generic cells, as opposed to cells of a particular cell library or technology. In the typical approach, the initial placement is not timing driven since little or no timing information is available at this stage in the fabrication process.
Once the “optimized” netlist has been placed and its interconnections are routed, timing information is then fed back to the design tools as described above for further optimization. The typical approach is to carry out gate tree optimization when the information is known as to the arrival time of all input signals. Buffer trees for cells having a large-fanout are optimized when the “remaining” time for each output signal is known.
The design verification tools typically identify “critical” paths that exceed a predetermined delay criteria. Once these critical paths have been identified, expansion of multi-input logical functions, placement and routing are optimized together in an iterative fashion to reduce delay through these critical paths. However, when a change is made to one of these critical paths, such as by expanding the logical function into a different circuit configuration, by changing placement or by changing one or more routing paths to produce a local improvement in delay, these changes can affect the timing of other paths. This usually results in a very slow timing convergence and can often result in the inability to achieve a real delay minimum since each possible local optimization can improve the currently critical path only to make other paths even worse.
Improved optimization techniques are desired for optimizing a logical circuit with more accurate delay estimation prior to placement and routing.
USPTO Backgrounds
USPTO Backgrounds