Non-volatile memory has been integrated into a wide range of electronic technologies including cellular communication, digital video, digital audio, and compact data storage (i.e., flash memory cards, flash memory sticks, and USB flash drives). Silicon-oxide-nitride-oxide-silicon (SONOS) memory is a non-volatile semiconductor memory, at the heart of which is a transistor that can retain a value without a constant power supply. During operation, a conventional SONOS memory transistor stores a single charge in a nitride layer sandwiched between two thin oxide layers. The oxide layers are in turn sandwiched between two silicon layers. These two silicon layers are typically a polysilicon gate electrode (i.e., the controlling gate) and the silicon substrate.
Sidewall SONOS technology improves upon SONOS technology by storing two bits per transistor. A sidewall SONOS transistor stores two discrete bits, in contrast with the one bit stored by a conventional SONOS transistor. FIG. 1 shows the cross-section of a known sidewall SONOS transistor 10. The transistor 10 includes an oxide 16 formed around a gate electrode 12 and a gate dielectric 14. The gate dielectric 14 is directly over a silicon substrate 17. A material 18 with charge trapping properties overlies the substrate 17, and includes portions 22 that are directly adjacent the oxide 16. A silicon oxide spacer 20 is adjacent the gate electrode 12.
The sidewall SONOS transistor 10 is repeated thousands, millions, and billions of times in a memory array (not shown). Because the sidewall SONOS transistor 10 is repeated numerous times, the design of the sidewall SONOS transistor 10 is critical to the reliability and compactness of the SONOS memory as a whole.
The sidewall SONOS transistor 10 in FIG. 1 has several disadvantages. First, the sidewall SONOS transistor 10 may suffer from electron drift. During operation, an electric charge is stored in the region 22. However, the region 22 is electrically connected to larger adjacent regions of the charge storing material 18, and electrons (not shown) in the region 22 may drift, thus degrading the charge density in the region 22. Charge density in the region 22 is critical to the performance of the sidewall SONOS transistor 10. The degradation of electric charge density in the region 22 may erroneously alter the value read from the transistor 10. The flaw is compounded by the number of times the sidewall SONOS transistor 10 is repeated in the SONOS memory.
In addition to suffering from electron drift, the sidewall SONOS transistor 10 shown in FIG. 1 is poorly suited for downward scalability. For example, the transistor 10 may not be scalable to a semiconductor process technology generation below 0.130 microns (μm). The transistor 10 has a silicon oxide (SiO2) spacer 20, but technological barriers exist, which prevent the manufacturing of silicon oxide gate spacers in sub-0.130 μm semiconductor manufacturing technologies. In addition, the substantially L-shaped formation of the region 22 of the charge trapping material 18 is not reproducible in a sub-0.130 μm manufacturing technology.
FIG. 2 shows a cross-section of a conventional sidewall SONOS transistor 30 manufactured in a sub-0.130 μm technology generation. The transistor 30 includes a gate spacer 32, separated from the gate electrode 12 and gate dielectric 14, by an oxide 16. The spacer 32 has charge storing properties, and during operation, an electric charge may be formed in the spacer 32. However, the spacer 32 is sufficiently voluminous to suffer from electron drift. The dissipation of electrons in the spacer 32 reduces the charge density in the spacer 32, resulting in possible data retention and reliability issues. Hence, there is a need for a reliable sidewall SONOS transistor that is scalable to sub-0.130 μm semiconductor manufacturing technology generations.
USPTO Backgrounds
USPTO Backgrounds