The present invention relates to a voltage boosting/lowering circuit and a voltage boosting/lowering circuit control method. In particular, the present invention relates to a voltage boosting/lowering circuit and a voltage boosting/lowering circuit control method using switch control.
In recent years, as the power consumption of digital still camera sets (hereinafter, simply called “camera sets”) has been reduced in order to extend their battery life span, voltage boosting/lowering circuits have been used in power-supply circuits that supplies an electrical power to microcomputers and the likes. The reason for this trend is explained hereinafter. The power supply voltage of microcomputers installed in camera sets is 3.3 V, and lithium-ion secondary batteries are commonly used as the power supply of such camera sets. Usually, a single lithium-ion secondary battery outputs a voltage of 4.2 V at the maximum. The output voltage of a lithium-ion secondary battery decreases as its electrical power is consumed. Further, the battery life span of a lithium-ion secondary battery can be extended by using the battery until its output voltage decreases to a lower voltage (for example, 1.5 V). Therefore, in order to obtain a power supply voltage of 3.3 V for a microcomputer as the power supply of a camera set by using a single lithium-ion secondary battery, it is necessary to perform, by a power-supply circuit, a voltage boosting conversion when the output voltage of the lithium-ion secondary battery is in a range between 1.5 V and 3.3 V and perform a voltage lowering conversion when the output voltage is in a range between 3.3 V to 4.2 V. Further, for such voltage boosting/lowering circuits installed in camera sets, the demand for improving the power efficiency has been growing.
Japanese Unexamined Patent Application Publication No. 2009-296747 (Patent literature 1) discloses a technique aiming at reducing a power loss in which the reduction of the power loss is achieved by reducing the operating ratio of a voltage boosting circuit. The configuration of a power supply apparatus (voltage boosting/lowering circuit) disclosed in Patent literature 1 is explained with reference to FIG. 8. The power supply apparatus 123 shown in FIG. 8 has the following configuration. One end of a voltage source 101 is connected to one end of a first switching element 105 through an input terminal 102. The first switching element 105 is configured in such a manner that its on-off action is performed through an external signal, and uses a field-effect transistor(s) (hereinafter called “FET”). Further, a smoothing capacitor 104 is connected between the input terminal 102 and a ground terminal 103. Note that the ground terminal 103 of the power supply apparatus 123 is connected to the ground side of power system lines of the voltage source 101, a load 113, and the like.
A first rectifying element 106 is connected between the other end of the first switching element 105 and the ground terminal 103. Therefore, the first rectifying element 106 is series-connected to the first switching element 105, and thus connected between the first switching element 105 and the other end of the voltage source 101. Note that the first rectifying element 106 is composed of a diode and connected in such a manner that its anode side is connected to the ground terminal 103 side.
One end of an inductance element 107 is connected to the node between the first switching element 105 and the first rectifying element 106. A second rectifying element 109 is connected between the other end of the inductance element 107 and the output terminal 111 of the power supply apparatus 123. Note that similarly to the first rectifying element 106, the second rectifying element 109 is composed of a diode and is connected in such a manner that its anode side is connected to the inductance element 107 side. Further, the output terminal 111 is connected to one end of the load 113. Therefore, the second rectifying element 109 is series-connected to the inductance element 107, and thus connected between the inductance element 107 and the one end of the load 113.
A second switching element 108 is connected between the node between the inductance element 107 and the second rectifying element 109 and a ground terminal 112. This ground terminal 112 is also connected to the above-mentioned ground terminal 103. Further, the other end of the load 113, i.e., the ground side of the load 113 is connected to the ground terminal 112. Therefore, the second switching element 108 is connected between the node between the inductance element 107 and the second rectifying element 109 and the other end of the load 113. Note that similarly to the first switching element 105, the second switching element 108 is composed of a FET(s). Further, a smoothing capacitor 110 is connected between the output terminal 111 and the ground terminal 112. A control circuit 122, which turns on/off the first switching element 105 and the second switching element 108, is connected to these switching elements through control system lines. Further, a control system line that takes in the voltage at the output terminal 111 (hereinafter called “output voltage Vo”) is also connected to the power supply apparatus 123 so that the power supply apparatus 123 can output a stable voltage to the load 113. Furthermore, the ground side of the control circuit 122 is also connected to the ground terminal 112.
The detailed configuration and the operation of each part of the control circuit 122 are explained hereinafter. Firstly, the output voltage Vo is input to an error amplifier 120 provided inside the control circuit 122. Meanwhile, a reference voltage from a reference voltage source 121 is also input to the error amplifier 120. Therefore, the error amplifier 120 amplifies and outputs the difference of the actual output voltage Vo from the reference voltage. The output of the error amplifier 120 is input to a PWM comparator 118.
Meanwhile, a triangular wave having a predetermined cycle generated by a triangular wave generator 119 is also input to the PWM comparator 118. Note that the predetermined cycle of the triangular wave may be determined as appropriate so that the required voltage boosting/lowering characteristic is obtained. In this way, the PWM comparator 118 generates an on-off signal SW1 having an on-off cycle T and an on-time ratio D that are determined according to the output of the error amplifier 120. This on-off signal SW1 is output to the first switching element 105. Therefore, the first switching element 105 performs an on-off action with the on-time ratio D. Note that the on-time ratio D is defined to be the ratio of an on-period of the first switching element 105 to the on-off cycle T.
Further, the output of the PWM comparator 118 is input to one of the input terminals of an AND circuit 115 and also input to the other input terminal of the AND circuit 115 through a timer 117 and an inverting circuit 116. The AND circuit 115 obtains the logical product of both input signals and outputs the result to the second switching element 108. With the configuration like this, an on-off signal SW2 output to the second switching element 108 behaves in the following manner.
Firstly, the waveform that is directly input from the PWM comparator 118 to the AND circuit 115 is identical with the above-described on-off signal SW1 of the first switching element 105. Meanwhile, the timer 117 outputs an on-signal for a predetermined period tx starting at the moment when the output of the PWM comparator 118 becomes an on-state. The output signal X from the timer 117 is inverted by the inverting circuit 116 and then input to the AND circuit 115. Therefore, the output of the inverting circuit 116 is in an off-state for the predetermined period tx and becomes an on-state signal at all other times.
According to these input signals from the PWM comparator 118 and the inverting circuit 116, the AND circuit 115 outputs an on-signal only when both input signals are in an on-state. Therefore, the output of the inverting circuit 116 becomes an off-state at the moment when the PWM comparator 118 outputs an on-signal. Therefore, the output of the AND circuit 115 remains in the off-state. After that, when the predetermined period tx has elapsed, the output of the AND circuit 115 becomes an on-state. Therefore, the output of the AND circuit 115 becomes identical with the output of the PWM comparator 118 at that time. The output of the AND circuit 115 described above is used as the on-off signal SW2 of the second switching element 108.
Next, the operation of the above-described power supply apparatus 123 is explained with reference to FIG. 9. Note that FIG. 9A shows a waveform chart of the on-off signal of the first switching element 105. FIG. 9B shows a waveform chart of the output signal of the timer 117. FIG. 9C shows a waveform chart of the on-off signal of the second switching element 108. FIG. 9D shows a waveform chart of the current of the inductance element 107 when Vi>Vo. Further, FIG. 9E shows a waveform chart of the current of the inductance element 107 when Vi<Vo. Therefore, in these charts, the horizontal axis represents time t. Further, FIG. 9 shows a case where the on-time ratio D is large.
A case where the on-time ratio D is large is explained. As shown in FIG. 9A, assume that the on-off signal SW1 of the first switching element 105 becomes an on-state at a time t101. At this point, the output of the PWM comparator 118 becomes an on-signal. Therefore, in response to this, the timer 117 starts outputting an on-signal as shown in FIG. 9B. Since this output signal X is inverted by the inverting circuit 116, an off-signal is input to the AND circuit 115 at the time t101. Therefore, the output of the AND circuit 115, i.e., the on-off signal SW2 of the second switching element 108 remains in the off-state at the time t101 as shown in FIG. 9C in spite of the output of the PWM comparator 118.
Since only the first switching element 105 is in the on-state at the time t101 as described above, the voltage source 101 is connected to the load 113 through the inductance element 107 and the second rectifying element 109. At this point, when the relation between the input voltage Vi and the output voltage Vo is “Vi>Vo”, the current I flowing through the inductance element 107 increases over time as shown in FIG. 9D, whereas when the relation is “Vi<Vo”, the current I decreases over time as shown in FIG. 9E. In either case, since the current I is positive, the current I is supplied to the load 113. At this point, since the second switching element 108 is in the off-state, the loss in the power supply apparatus 123 is small.
After that, when the predetermined period tx has elapsed from the time t101, i.e., at a time t102, the timer 117 outputs an off-signal as shown in FIG. 9B. At this point, since FIG. 9 shows the case where the on-time ratio D is large, the first switching element 105 remains in the on-state as shown in FIG. 9A. Therefore, the signal input from the PWM comparator 118 to the AND circuit 115 remains in the on-state.
Meanwhile, when the output signal X of the timer 117 becomes an off-state, the output of the inverting circuit 116 becomes an on-state and this signal is input to the AND circuit 115. Therefore, since the on-signals are input to both inputs of the AND circuit 115, the output signal of the AND circuit 115 becomes an on-state. Therefore, at the time t102, the second switching element 108 is turned on as shown in FIG. 9C, and the current I of the inductance element 107 increases as shown in FIGS. 9D and 9E. As a result, the voltage boosting ratio Vo/Vi of the power supply apparatus 123 becomes larger as described later, though the internal loss in the second switching element 108 increases.
After that, at a time t103, the on-period, which is determined by the on-time ratio D of the first switching element 105, has ended, and the first switching element 105 is turned off as shown in FIG. 9A. As a result, since the AND circuit 115 outputs an off-signal, the second switching element 108 is also turned off as shown in FIG. 9C. Therefore, at the time t103, the first switching element 105 and the second switching element 108 are simultaneously turned off.
As a result, the electric power of the inductance element 107 is supplied to the load 113. Therefore, as shown in FIG. 9D, the current I of the inductance element 107 decreases over time at and after the time t103. Note that since the first switching element 105 and the second switching element 108 are both in the off-state at this point, no internal loss occurs in these switching elements. After that, at a time t104, the same action as that at the time t101 is performed, and after that, the same actions as those from the time t101 to t104 are repeated.
USPTO Backgrounds
USPTO Backgrounds