In the fabrication of microelectronic semiconductor devices on a wafer substrate, such as silicon, to form an integrated circuit (IC), various metal layers and insulation layers are deposited thereon in selective sequence. The insulation layers, e.g., of silicon dioxide, silicon oxynitride (Sio.sub.x N.sub.y), fluorinated silicate glass (FSG), also called fluorinated silicon oxide, spin-on glass (SOG), etc., serve as electrical insulation between metal layers, e.g., intermetal dielectric (IMD) layers, as protective layers, as gap filling layers to achieve planarization (layer flatness) in the wafer substrate, and the like, as the case may be. The individual layers are deposited by conventional technique such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD, etc.
Typically, a first level metal layer, e.g., disposed on a silicon substrate containing devices, is separated by one or more insulation layers from a second level metal layer thereabove. This in turn may be separated by one or more further insulation layers from a third level metal layer thereabove, etc. These metal layers are interconnected by metallization through vias or small holes or apertures etched in the intervening insulation layers.
For this purpose, the stacked layers undergo photolithographic processing to provide a pattern thereon consonant with the IC design, e.g., to form vias. The top layer on the wafer substrate is covered with a photoresist layer of photo-reactive polymeric material for patterning via a mask. Light such as visible or ultraviolet (UV) light is directed through the mask onto the photoresist layer to expose it in the mask pattern. The polymeric material of the photoresist layer is transparent to the light yet photo-reactive to change its chemical properties, i.e., by photo-initiated reaction, thereby permitting its patterning.
An antireflective coating (ARC) layer such as an organic ARC layer, e.g., of light absorbing polymer, such as polyimide, is usually provided at the top portion of the wafer substrate to minimize reflection of light back to the photoresist layer for more uniform processing.
The photoresist may be of negative or positive type. In a negative photoresist, the exposed (polymerized) areas become insoluble while the unexposed (unpolymerized) areas dissolve in a later applied developer liquid. In a positive photoresist, the exposed (degraded) soluble areas dissolve in the developer liquid while the unexposed (insoluble) areas remain. In both instances, the photoresist material remaining on the wafer substrate forms the pattern to serve as a mask for etching in turn of the pertinent layers.
Where a layer material is of different physical and chemical characteristics from that of adjacent layers, its etching process is also different therefrom, e.g., in forming vias in dielectric layers to connect neighboring level metal layers. The etching is desirably anisotropic (high rate vertical direction etching and low rate or inhibited horizontal direction etching), as distinguished from isotropic (etching the exposed surfaces equally in all directions), for providing an etched structure of uniform vertical wall geometry or profile. Etching may be effected by wet etching (solution) or dry etching (plasma etching or reactive ion etching) technique, depending on the physical and chemical characteristics of the material being etched and of the neighboring material.
For maximizing the integration (connection) of device components in the available area on the wafer substrate to fit more components in the same area, increasing miniaturization is required. As narrower metal lines and closer pitch dimensions are needed to achieve increasingly dense packing of the components, they become more vulnerable to defects at the minute tolerances involved. This has become apparent as IC miniaturization has increased to what is now called very large scale integration (VLSI) at sub-quarter micron (0.25 micron, i.e., 250 nanometer (nm) or 2,500 angstrom), or less, dimensions.
By comparison, visible light has a wavelength spectrum of 400-700 nm (4,000-7,000 angstroms), and UV light has a wavelength spectrum of 100-400 nm (1,000-4,000 angstroms). Generally, mid UV (MUV) light has a wavelength of about 365 nm, while deep UV (DUV) light has a wavelength of about 248 nm or less.
At sub-quarter micron sizes, the desired high aspect ratios (depth to width) associated with photolithographic processing to form apertures or windows, fine conductive lines, etc., in various layers of the wafer substrate, require very strict tolerances to prevent undesired defects such as touching of closely spaced apart components that can cause short circuiting, etc.
During travel of the mask patterned incident light from the radiation source through the photo-reactive polymeric material of the photoresist layer, it is progressively absorbed as it photo-initiates reaction in the exposed pattern areas. As some incident light reaching the ARC layer is not absorbed thereby, but rather is reflected and scattered back into the photoresist layer, there is interference with the incident light and formation of standing waves.
Contaminants that are incompatible with the photoreactive polymeric material can migrate into the photoresist layer from the ARC layer or other vicinal layer. These contaminants can poison the photoresist layer, e.g., undergo interfering reactions therewith, causing non-uniformity of the reaction therein by extraneous chemical interaction with the polymeric material. This is commonly called photoresist poisoning.
These influences lead to formation of a photoresist footing where a positive photoresist is used, or of a photoresist pinching where a negative photoresist is used. Specifically, upon development, the exposed pattern areas of the photoresist layer have a photoresist profile or structure with non-uniform (non-vertical) side walls. After etching, the photoresist footing or photoresist pinching problem leads to imperfect transfer of the photoresist pattern to the underlying layer or layers, and ultimately limits the minimum spatial resolution since the etched structure is imprecise compared to the desired IC design.
FSG (fluorinated silicate glass) is one of the favorable low dielectric materials used for intermetal dielectric (IMD) application in sub-half micron (0.5 micron) semiconductor fabrication technology in connection with metallization techniques before so-called back end of the line operations (between metallization and sale). To deposit FSG, for example, either high density plasma (HDP) chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) is commonly used.
The dielectric constant achievable for FSG is about 3.3 depending on the fluorine concentration in the FSG film and the precursor used to deposit the FSG film. A higher fluorine concentration usually provides a lower dielectric constant. However, a higher fluorine concentration makes the film unstable because free fluorine tends to diffuse or migrate out of the film to adjacent layers in the IC.
Out diffusion of fluorine substances (including fluorine itself and attendant self-generating contaminant compounds thereof with other contaminating precursor constituents) from FSG can create bubbles that collect at interfaces with metal layers, resulting in metal peeling problems due to corrosion or poisoning, and the like. In many cases, FSG use is combined with post plasma treatment, e.g., plasma treatment using oxygen and nitrogen or nitrous oxide (N.sub.2 O), or the inclusion of a silicon dioxide cap layer to minimize fluorine substance out diffusion. However, fluorine substances, including fluorine itself, will diffuse well into silicon dioxide films and the diffusion length (penetration depth) thereof can be in excess of several thousand angstroms.
While the matter is not fully understood at this time, it is believed that contaminants such as hydrogen and nitrogen remain as precursor constituents in silicon dioxide based layers consequent their deposition, e.g., by PECVD technique, using silane (SiH.sub.4) in the presence of oxygen, nitrogen, nitrous oxide, and the like. In the presence of fluorine, it is considered that self-generating contaminant compounds thereof are formed with attendant hydrogen and/or nitrogen and/or other species that remain as contaminating precursor constituents. It is believed that fluorine and such self-generating contaminant compounds out diffuse to collect at a vicinal metal layer interface to cause such corrosion or poisoning and metal peeling problems.
As used in the specification and claims, the term "fluorine substance" contemplates fluorine-containing substances including both free fluorine itself and attendant self-generating contaminant compounds thereof with other contaminating precursor constituents such as hydrogen and nitrogen (i.e., fluorine-containing contaminant compounds).
A typical semiconductor fabrication technique using FSG as a low dielectric material for IMD application includes the steps of:
(1) metal layer deposition and patterning on a wafer substrate; PA1 (2) silicon dioxide liner deposition on the metal layer; PA1 (3) FSG layer deposition on the silicon dioxide liner; PA1 (4) silicon dioxide cap layer deposition on the FSG layer; PA1 (5) chemical mechanical polishing (CMP) of the silicon dioxide cap layer; PA1 (6) post CMP additional silicon dioxide cap layer deposition on the polished silicon dioxide cap layer (or post plasma treatment); PA1 (7) organic ARC layer deposition on the additional silicon dioxide cap layer (or plasma treated layer); PA1 (8) photoresist layer deposition on the organic ARC layer and photolithographic exposure and development; PA1 (9) organic ARC layer open etching; and PA1 (10) dielectric layer contact etching.
It is desirable to have an arrangement of FSG as an IMD in a semiconductor device in which out diffusion of fluorine substances is prevented so as to avoid metal peeling problems, especially if this is attained essentially without increasing the manufacturing costs.
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