1. Field of the Invention
This invention relates in general to memories employed in computer systems and, more particularly, to accessing data stored in page mode memories employed in such systems.
2. Description of Related Art
The demands on computer systems to achieve ever greater operating speeds, increased effective processing power and greater overall performance continue. One trend has been to increase the clock frequency of the central processing unit (CPU) of the computer. This, of course, results in a greater number of instructions being processed per unit time. However, as clock frequency is increased, the access time associated with memory must somehow be correspondingly shortened if the full benefit of the clock frequency increase is to be realized. Otherwise, the access time associated with reading data out of memory becomes a prominent limiting factor constraining the effective performance of the CPU.
One approach to decreasing the effective access time required to read data from memory is to use page mode memory. That is, memory is divided into a plurality of pages, each page consisting of a row having a common row address for the entire row. Each row of a page includes a plurality of columns having corresponding column addresses. To access a particular piece of data stored in such a page mode memory, the row address of that data is supplied to the memory to enable selection of the page in memory where the data is located. Then, the column address associated with the data is supplied to the memory to enable selection of the particular piece of data within the addressed row or page. Typically, the addressed data is then read out to the data bus.
One example of a page mode memory is found in the IBM Personal System/2, Model 80 computer. (Personal System/2 is a trademark of the International Business Machines Corporation.) A simplified block diagram generally representative of such a page mode memory computer system is shown in FIG. 1 as system 10. System 10 includes a central processing unit (CPU) 20 or microprocessor to which an address bus 30 and a data bus 40 are coupled. System 10 further includes a memory controller 50 to which address bus 30 and data bus 40 are coupled. A control bus 60 is coupled between CPU 20 and memory controller 50 such that control signals may be passed therebetween. Memory controller 50 is coupled to at least one memory module 70 which consists of random access memory (RAM). In this example, memory module 70 is divided into pages which are 2K bytes long (512.times.32 plus parity), each page by definition having the same row address. Each page thus includes 2K column addresses. A data bus 80 is coupled between memory controller 50 and memory module 70 to permit the transfer of data therebetween.
A multiplexed MUX address bus 90 is coupled between memory controller 50 and memory module 70 so that row and column address information may be passed from memory controller 50 to memory module 70. Multiplexed address bus 90 has fewer lines than address bus 30 due to the multiplex nature of bus 90 on which a row or page address is first supplied to memory module 90 during a memory access cycle and then, second, a column address is supplied to memory module 90 later in that cycle. Memory controller 50 supplies Row Address Strobe (RAS) signals and Column Address Strobe (CAS) signals to memory module 70 as seen in FIG. 1. The nature of the RAS and CAS signals is described in the following discussion of the timing diagram of FIG. 2.
FIG. 2 shows a timing diagram of a typical memory cycle associated with computer system 10. For purposes of this example, it is assumed that CPU 20 desires to access or retrieve a first piece of data from memory 70 at a predetermined data address therein. To actually access such information, CPU 20 sends the data address to memory controller 50. Memory controller 50 effectively divides the data address into two portions, namely, the row address (also known as the page address) and the column address. The row address and the column address are multiplexed onto MUX ADDRESS bus 90. That is, the row address is first provided to such MUX ADDRESS bus at 100. The RAS signal is initially HIGH or OFF. It is noted that since negative logic is employed in the timing diagram of FIG. 2., HIGH corresponds to an OFF state and LOW corresponds to an ON state. The RAS signal goes ON at 105 to select the row address portion presently supplied to MUX ADDRESS bus 90. In this manner, memory module 70 selects the particular page (row) in which the addressed data is stored. RAS remains ON for the duration of the first memory cycle and the following second memory cycle.
After RAS goes ON and the row address is selected in the first memory cycle, the column address portion of the desired data is supplied to the MUX ADDRESS bus at 110. The CAS signal is then driven ON at 115 to select the column address portion presently supplied to MUX ADDRESS bus 90. At this point the address is complete since both the row and column address portions corresponding to the desired data have been supplied to memory module 70. Memory module 70 then accesses the data thus addressed and provides such data to memory data bus 80. The data on the memory data bus 80 becomes valid at 120 after a predetermined time delay, T.sub.D, occurs after completion and selection of the address at 115. Microprocessor 20 then picks up the addressed data from data bus 40 of FIG. 1. Those skilled in the art use the term T.sub.CAS to define the time delay between the time at which CAS becomes active to the time at which the data becomes valid on the memory data bus 80. The term T.sub.RAS refers to the time delay between the time at which RAS becomes active to the time at which the data becomes valid. More commonly, T.sub.RAS is referred to as the "access time" exhibited by a particular memory device. For example, a memory device with an 80 nanosecond access time exhibits a T.sub.RAS of 80 nanoseconds.
For purposes of this example it is assumed that a second piece of data located in the same page or row as the above first piece of data is to be accessed from memory module 70. Those skilled in the art use the term "pipelining" to describe the act of changing the address, for example the column address portion, prior to the end of the current memory cycle in preparation for the next memory cycle. Pipelining itself saves time since it permits address decoding circuitry in memory controller 50 to start processing the address earlier than would otherwise be possible. An example of such pipelining is seen in FIG. 2 where subsequent to the data becoming valid at 120 and prior to the end of the first memory cycle at 125, the column address is changed to a new column address at 130, such column address corresponding to the second piece of data. Since the second piece of data to be accessed in the second memory cycle is in the same page as the data accessed in the first memory cycle, the column address portion changes at 130 while the row address portion remains the same. This situation is referred to as a "page hit". Since it is not necessary to resend the row address portion to memory module 70 when a "page hit" occurs, valuable time can be saved in a page mode memory arrangement.
Before memory module 70 can select and actually use the column address information now present on MUX ADDRESS bus 90, it is necessary to drive the CAS signal OFF for a predetermined period of time referred to as the CAS precharge 135. Those skilled in the art refer to the CAS precharge time as T.sub.CRP. For a memory device with an 80 nanosecond access time, a typical value of T.sub.CRP would be 15 nanoseconds. Once the CAS precharge is completed, CAS is driven ON again at 140 such that the column address portion of the second piece of data is selected by memory module 70. The address of the second piece of data is thus completed and the data on memory address bus 80 becomes valid at 145 after a predetermined time delay, T.sub.D, from completion and selection of the address at 140. Microprocessor 20 then picks up the addressed data from data bus 40 of FIG. 1. The second memory cycle ends at 150.
For purposes of this example it is assumed that a third piece of data located in a different page or row than the first and second pieces of data is accessed in a third memory cycle commencing at 150, a portion of such third memory cycle being shown in FIG. 2. This situation is referred to as a "page miss". That is, a new row address portion corresponding to the location of the third piece of data must be provided to memory module 70. Such new row address portion appears on the MUX ADDRESS bus via pipelining at 155. At the beginning 150 of the third memory cycle, RAS is driven OFF in preparation for the new row address. The new row address is actually selected when RAS is driven ON at 160. The remainder of the third memory cycle is substantially similar to the first memory cycle in FIG. 2 with CAS precharge being provided at 165 near the beginning of the third memory cycle.
From the above discussion it is seen that in the situation where a "page hit" occurs in a page mode memory, a substantial amount of time is consumed (reference the second memory cycle in FIG. 2) in conducting the CAS precharge before the new column address portion can be used to complete the new address and select the corresponding data.
As mentioned above, computer systems are being designed with higher and higher clock speeds. Given that a memory cycle consists of a predetermined number of clock pulses which become correspondingly shorter as the clock speed increases, the time required for such memory set-up activities as CAS precharge tends to occupy an ever increasing proportion of the memory access cycle as the clock speed increases. One way to accommodate a microprocessor which is operating at a very fast rate with respect to the speed or access time of memory is to add wait states to the computer system to effectively slow down the microprocessor to wait for data to be accessed from memory. This course of action is generally undesirable because it negates some of the benefits of increasing the clock speed of the microprocessor.
USPTO Backgrounds
USPTO Backgrounds