This invention relates to a command generating circuit and, in particular, to a command generating circuit which is improved in setup time of a command supplied from outside and to a semiconductor memory device having the same.
Recently, an electronic system is increased in speed and a data transfer speed between semiconductor devices constructing the system is drastically increased. Therefore, the semiconductor device itself is also required to perform a high-speed data transferring operation. Inside the semiconductor device, use is made of a clock synchronization system in which the operation is synchronized with a clock. For example, as a semiconductor memory device, there is a synchronous DRAM (Synchronous Dynamic Random Access Memory, will hereinafter be abbreviated to SDRAM). The SDRAM is further improved into SDRAMs of DDR (Double Data Rate) in which the data transferring operation is synchronized with rising and falling edges of the clock, DDR2, and DDR3 types.
In the SDRAM and the DDR-SDRAM, a prefetch system using a setup time (tIS) is generally adopted for the purpose of speeding up generation of an internal command. The prefetch system using the setup time (tIS) is a system in which decoding of a command and an address is preliminarily executed by the use of the setup time to assure a timing margin of an internal circuit and to quicken the generation of the command. However, following recent increase in clock frequency, a setup time specification gradually becomes strict. For example, the setup time tIS is 1500 ps in the SDRAM of 133 MHz and 600 ps in the DDR-SDRAM of 400 MHz. In the DDR2-SDRAM of 800 MHz, the setup time tIS is 375 ps. Thus, the timing margin gained by the prefetch system is gradually decreased as the clock frequency is increased.
A command generating circuit is disclosed in the following patent documents. In Japanese Unexamined Patent Application Publication (JP-A) No. H9-139084, a write pulse is generated in response to a command and a clock supplied from outside and a write cycle time is shortened. In Japanese Unexamined Patent Application Publication (JP-A) No. 2002-025254, fetching of an address, a command, and data is performed in synchronization with both of rising and falling of a clock signal. In Japanese Unexamined Patent Application Publication (JP-A) No. H8-124380, an operation of the SDRAM is assured by confirming that a mode register is properly set. In Japanese Unexamined Patent Application Publication (JP-A) No. H11-045571, an internal clock width is adjusted to thereby set a wide internal window width.
Referring to FIGS. 1 through 5, description will be made about a typical command generating circuit by the use of a bank active command generating circuit as an example. In this example, a DDR2-SDRAM having a four-bank structure is assumed. In the SDRAM (including the DDR and the DDR2), an operation is independent in each bank. Therefore, a command is generally generated by calculating a logical product (AND) of two signals. One of the two signals is an operation mode signal (corresponding to X00 and CS_T in FIG. 2) which is determined by decoding a chip selection signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, or a write enable signal /WE (the symbol “/” means that a low state is active. The other signal is a bank select signal (BS0, BS1, BS2, or BS3) which is determined by decoding a bank address (BA0 or BA1). Thus, the command is generated by the two signals, i.e., the operation mode signal and the bank select signal.
FIG. 1 schematically shows an intermediate path from each of external terminals of the commands (/CS, /RAS, /CAS, and /WE) and the bank addresses (BA0 and BA1) to the command generating circuit. A command signal /CMD supplied to the external terminal PAD passes through an ESD protective element (ESD) (details thereof is omitted) and is converted into a converted command signal having a VDD amplitude at an input buffer (details thereof is omitted). Thereafter, the converted command signal passes through a delay (details thereof is omitted) for adjusting a timing with respect to an internal clock and is latched at a latch circuit (one example of details thereof is shown in FIG. 5) as an internal command signal CMD_T. The latched internal command signal CMD_T is supplied to the command generating circuit.
The command signal /CMD in FIG. 1 represents /CS, /RAS, /CAS, /WE, BA0, and BA1. The internal command signal CMD_T represents CS_T, RAS_T, CAS_T, WE_T, BA0_B, and BA1_B. With respect to a logic of the command signal /CMD to be supplied to a pad, logics of the internal command signals CS_T, RAS_T, CAS_T, WE_T, BA0_B, and BA1_B are inverted. Clocks ACLK_T and ACLK_B (B is an inversion signal) are the internal clocks for latching the commands, the bank address, and the like and are generated by delaying an external clocks CLK by an appropriate amount.
By setting /CS=“L”, /RAS=“L”, /CAS=“H”, and /WE=“H” at rising of the external clock CLK, a bank active command is issued. A bank to be turned active is designated by the bank address. This operation will be described with reference to FIG. 2. When the bank active command is supplied from the external terminal, CS_T=“H”, RAS_T=“H”, CAS_T=“L”, and WE_T=“L”. As RAS_T=“H”, CAS_T=“L”, and WE_T=“L”, an output X00 of a three-input NOR circuit NO30 has an “H” state. On the other hand, by setting the bank address, one of the bank select signals (BS0, BS1, BS2, and BS3) is selected and turned into an “H” state.
As mentioned above, X00=“H” and CS_T=“H”. Therefore, one of the three-input NAND circuits NA30, NA31, NA32, and NA33 is supplied with three input signals all of which have an “H” state and produces an output (an input to the latch circuit) having an “L” state (the other three three-input NAND circuits produce outputs having an “H” state). When the internal clock CCLK_T rises (CCLK_B falls), latch circuits LA00, LA01, LA02, and LA03 latch the above-mentioned data (outputs of the latch circuits are inverted with respect to input levels). Each of two-input NAND circuits NA20, NA21, NA22, and NA23 is supplied with the internal clock CCLK_T, as an enable signal, and is turned active by rising of CCLK_T. Thus, with respect to a bank selected by the bank select signal, the bank active command is issued (“H” state).
A first feature of the above-mentioned structure is that the logical product (AND) of the operation mode signal and the bank select signal is calculated at a preceding stage to the latch circuits (LA00, LA01, LA02, and LA03). Further, a second feature is that, after latching, each of the NAND circuits (NA20, NA21, NA22, and NA23) is supplied with CCLK_T as one input. The two features mentioned above provide a guard for preventing multi-issue of commands (simultaneous issue of commands to a plurality of banks). However, with this structure, the number of logic stages before latching is increased and it is difficult to assure the timing margin.
Referring to FIGS. 3 and 4, description will be made about an operation timing of the typical command generating circuit. FIG. 3 schematically shows timings from the external terminals to the generation of the commands and FIG. 4 shows details of the timings of the command generating circuit. For simplification of description, it is assumed that a delay time per each gate has a same value Δt. It is also assumed that a delay time of a transfer gate also has the same value Δt. The rising of the external clock CLK is used as a reference time t=0. A delay time from the external clock CLK to the internal clock CCLK_T is represented by ΔTc. A setup time of the command and the bank address with respect to the external clock CLK is represented by tIS.
As paths from the external terminals of the commands (/CS, /RAS, /CAS, and /WE) and bank addresses (BA0 and BA1) to the command generating circuit, the substantially same circuit (FIG. 1) is used. Therefore, although there is a slight difference depending upon a layout position, a substantially same time is required as a delay time after a signal is switched at the external terminal and before each of the internal commands CS_T, RAS_T, CAS_T, WE_T, BA0_B, and BA1_B is switched. This delay time is represented by ΔTi.
The internal commands CS_T, RAS_T, CAS_T, WE_T, BA0_B, and BA1_B are switched at a time instant t=ΔTi−tIS. The number of logic stages from RAS_T, CAS_T, and WE_T to a node X00 is two at maximum and the node X00 is determined at a time instant ΔTi−tIS+2Δt. On the other hand, the number of logic stages from BA0_B and BA1_B to the bank select signals (BS0, BS1, BS2, and BS3) is three at maximum and the bank select signals are determined at a time instant ΔTi−tIS+3Δt. Accordingly, nodes Y00, Y01, Y02, and Y03 are determined at a time instant ΔTi−tIS+4Δt and nodes ACT00, ACT01, ACT02, and ACT03 are determined at a time instant ΔTi−tIS+6Δt.
In order to issue bank active commands (ACT0, ACT1, ACT2, and ACT3) with an original proper pulse width, the internal clock CCLK_T must rise after the nodes ACT00, ACT01, ACT02, and ACT03 are determined. Therefore, it is necessary to adjust a delay amount so that CCLK_T rises at a time instant not earlier than ΔTi−tIS+6Δt. The longer becomes a time required before CCLK_T is allowed to rise, the lower becomes the upper limit of a frequency at which the circuit is operable (a cycle of operation becomes longer).
A time period from determination of outputs Y00, Y01, Y02, and Y03 of the three-input NAND circuits to the rising of CCLK_T (a setup time of the latch circuit, i.e., a setup time of the command generating circuit) is given by ΔTc−(ΔTi−tIS+4Δt). In case where data have not arrived no later than a predetermined time period prior to a time instant when a gate of the latch circuit is closed, data in the latch circuit can not be inverted and a latch failure or error is caused to occur. Let this limit time be represented by Tsl. Then, at a limit where the command generating circuit is normally operable, the following equation is given:ΔTc−(ΔTi−tIS+4Δt)=Ts1  (1)The equation (1) is rewritten into:tIS=Ts1+ΔTi+4Δt−ΔTc  (2)
This value is a minimum essential setup time (tIS) required in the circuit structure. In case where the delay time ΔTc from the external clock CLK to the internal clock CCLK_T is increased, the setup time can be reduced. However, such increase in ΔTc leads to lowering of a frequency at which the circuit is operable. At present, a higher frequency is used and the setup time specification gradually becomes strict. Therefore, an inventive circuit design is required. For this purpose, a command generating circuit is desired which is operable at a high clock frequency and is capable of assuring a sufficient setup time (tIS).
As mentioned above, in the semiconductor memory device, the clock frequency becomes higher and the timing margin gained by the prefetch system is decreased. Therefore, the command generating circuit capable of assuring a sufficient setup time (tIS) is desired.
USPTO Backgrounds
USPTO Backgrounds