1. Field of the Invention
The present invention relates to an improvement in a semiconductor device including a noise canceling circuit for removing noise of an external input signal such as a reset signal.
2. Description of Related Art
FIG. 9 is a block diagram showing a configuration of a reset signal input section and its associates of a conventional semiconductor device. In FIG. 9, the reference numerals 1 and 1 designate external clock input terminals to which a crystal oscillator not shown is connected; and 2 designates an oscillator driver for driving the crystal oscillator connected to the external clock input terminals 1 and 1. The reference numeral 3 designates an internal clock generator which is connected to the external clock input terminals 1 and 1, and outputs two internal clock signals CLK1 and CLK2 with a frequency twice that of an external clock signal Xin in synchronism with the external clock signal Xin. The reference numeral 4 designates an external input terminal to which the external reset signal Rst is applied; and 5 designates a signal synchronizing circuit 5 which latches the external reset signal Rst by the first internal clock signal CLK1, and output an internal reset signal Rint. The reference numeral 6 designates a noise canceling circuit that is connected between the external input terminal 4 and the signal synchronizing circuit 5, and passes only the external reset signal Rst with a width equal to or greater than d1.
FIG. 10 is a block diagram showing a configuration of the noise canceling circuit 6. In FIG. 6, the reference numerals 6a, 6a, . . . , 6a each designate a delay buffer consisting of a switching device in the semiconductor device; and 6b designates a two-input logical AND circuit which carries out negative OR operation of the delayed reset signal Ra passing through the delay buffers 6a, . . . 6a, and the external reset signal Rst directly supplied from the external input terminal 4, and outputs a noise canceled reset signal Rb which falls to a low level when both the input signals are at the low level. The noise canceling circuit 6 with such an arrangement outputs the reset signal Rb only when the external reset signal Rst input to the external input terminal 4 at present and a little time before are both low. In other words, the external reset signal Rst with a width of d1 and more which is low at the two timings are input to the signal synchronizing circuit 5, and noise or the like with a width less than d1 is not input to the signal synchronizing circuit 5.
FIG. 11 is a block diagram showing a configuration of the signal synchronizing circuit 5. In FIG. 11, the reference numeral 5a designates a data latch circuit for latching the external reset signal Rb output from the noise canceling circuit 6 by the first internal clock signal CLK1 output from the internal clock generator 3; and 5b designates a delay circuit which receiving the first internal clock signal CLK1 and second internal clock signal CLK2, delays the external reset signal Rc, which is latched and output by the data latch circuit 5a, by an amount of two internal clock periods 2T using the input clock signals CLK1 and CLK2. The reference numeral 5c designate a two input logical OR circuit which inputs the reset signal Rb output from the noise canceling circuit 6 at a first input, and the reset signal Rd output from the delay circuit 5b at a second input, and outputs the internal reset signal Rint of the low level when at least one of the two inputs are at the low level. Thus, the low level width of the internal reset signal Rint is equal to or greater than the two internal clock periods 2T.
Next, the operation of the conventional semiconductor device will be described.
FIG. 12 is a timing chart illustrating the timing relationships from the input of the external reset signal Rst and to the generation of the internal reset signal Rint.
As illustrated in FIG. 12, when the low level external reset signal Rst is input to the external input terminal 4 at time t0, the internal reset signal Rint falls to the low level at time t1 which is later than time t0 by a delay time d1 due to the noise canceling circuit 6. When the input of the external reset signal Rst to the external input terminal 4 returns to the high level at time t6, the output Rc of the data latch circuit 5a returns to the high level at the falling edge of the next first internal clock signal CLK1 at time t7. Then, the internal reset signal Rint returns to the high level at time t9 which is later than the rising edge of the second internal clock signal CLK2 at time t8 by an amount of the two internal clock periods 2T.
Since the conventional semiconductor device has such a configuration, if the ambient conditions like the power supply voltage and temperature of the noise canceling circuit 6 fluctuate, the timing of the noise canceled reset signal Rb output therefrom greatly varies as indicated by w1 in FIG. 12, even if the external reset signal Rst is synchronized with a particular cycle of the external clock signal.
As a result, the synchronization is lost between the timing of the reset signal Rb output from the noise canceling circuit 6 and the internal clock cycle, so that the internal reset signal Rint output from the signal synchronizing circuit 5 is shifted by an amount of at least one internal clock period T. This presents a problem in an operation test of the semiconductor device in that the operation start timing of the semiconductor device after the input of the external reset signal Rst shifts by an amount of at least one internal clock period T, thereby outputting unexpected output results at respective clock cycles in the operation test.
In particular, the synchronization loss becomes an important problem in the development of a semiconductor device which increases its operation frequency by multiplying the clock frequency in itself because of the difficulty in stable supply of an external clock signal at a high operation frequency. This is because although the clock period in such a semiconductor device becomes much shorter than that in a conventional one, the time interval from the input of the external reset signal Rst to the output of the internal reset signal Rint is kept long and fluctuates in response to the power supply voltages and temperature as in the conventional one.
Incidentally, noise canceling circuits can be interposed in signal paths other than the reset signal path to protect the internal circuit. However, since noise cancellation periods of such noise canceling circuits are much shorter than that of the noise canceling circuit described above, and their delay times little vary, this does not matter normally. Nevertheless, if they involve a time delay matching that of the noise canceling circuit 6 of the reset signal Rst, a similar problem can occur.
Besides, in the semiconductor device which increases its operation frequency by multiplying the clock frequency in itself as described above, it is common that the internal clock generator 3 is arranged such that it self-oscillates the internal clock at its unique frequency, and has its phase synchronized with an external clock signal using a phase-locked loop. In the semiconductor device with such an arrangement, the generation of the internal clock signal cannot be halted by suspending the input of the external clock signal. Therefore, the synchronization of the reset signal Rst with the clock signal cannot be established in the semiconductor device by suspending the input of the external clock signal.
For the reasons described above, it is necessary for the conventional semiconductor device to prepare test patterns as shown in FIG. 13, for example, which differs from the test pattern as shown in FIG. 12, and to carry the predetermined tests by using appropriate patterns in accordance with the ambient conditions such as the supply voltages and temperature. This presents other problems of lengthening the design term of the semiconductor device, reducing productivity in volume production, and demanding reinforcement of test facilities. Incidentally, the description of FIG. 13 will be omitted here, because the waveforms illustrated in FIG. 13 operate in the same way as those of FIG. 12, although their patterns differ from each other.
USPTO Backgrounds
USPTO Backgrounds