Modern digital systems represent digital data either in series (i.e., as a series of bits) or in parallel (i.e., as a transmitting one or more bytes simultaneously using multiple data lines). While it is generally easier to store and manipulate data in parallel, it is often beneficial to transmit data in series. Many systems therefore employ parallel-to-serial converters.
FIG. 1 (prior art) depicts a parallel-to-serial converter 100 that serializes ten-bit words presented in parallel on data lines D<9:0>. Converter 100 includes a parallel shifter 105, which in turn includes a pair of five-bit shift registers 110 and 115. Shift registers 110 and 115 each connect to one of a pair of complementary clocks CEV and COD. Designations CEV and COD stand for “clock even” and “clock odd,” respectively, because even data bits are presented on an output terminal DOUT when CEV is high and odd data bits are presented on output terminal DOD when DEV is high.
Every fifth rising edge of clock CEV, register 110 stores the even-numbered data bits D<8,6,4,2,0> presented on bus D<9:0> and register 115 stores the odd-numbered data bits D<9,7,5,3,1> presented on the same bus. Each of registers 110 and 115 then presents their respective data one bit at a time, so that both odd and even data bits are presented alternately to a data combiner 120. Data combiner 120 alternately gates the odd and even data bits presented on respective data terminals DOD and DEV to produce a serialized version of the data produced by shifter 105.
If manufactured using commonly available CMOS processes, converter 100 can perform with clock frequencies as high as about 2 Ghz. This is too slow for many modern high-speed digital communication systems, which can transmit serial data in the 10 Gb/s range. More exotic processes, such as those employing silicon germanium or gallium arsenide, provide improved high-frequency response; unfortunately, this improvement comes at considerable expense.
USPTO Backgrounds
USPTO Backgrounds