This invention relates to voltage clamping circuits, and more particularly to a circuit and method for providing symmetrical voltage clamping to an input signal to an integrated circuit (IC) without producing undesirable parasitic currents.
In the past, an IC was protected from large positive and negative voltage input signals by connecting the input of the IC in series with a limiting resistor in parallel with a zener diode. The co-inventor of the present invention, William Davis, has described significant problems associated with this technique in an article titled, "Bipolar Design Considerations for the Automotive Environment," IEEE Journal of Solid State Circuits, December, 1973, pp. 419-426. An example of such a problem occurs in response to large positive input signals which can cause significant power dissapation in the zener diode which is undesirous. An even worse condition may occur due to large negative input voltage transients.
Negative voltage transients, applied to any N-epi region with sufficient magnitude to forward bias the N-epi/P-substrate can seriously degrade functional IC performance due to the injection of electrons into the substrate (substrate injection). These minority charge carrier electrons will diffuse throughout the P-substrate region until they recombine or are collected by other reversed biased N-epi regions. As described in the above reference article, undesirous currents are established by the formation of a parasitic lateral NPN transistor which may be defined. Hence, circuit malfunction could result due to the parasitic collection of substrate injected electrons. Standard clamping techniques such as a zener diode clamp or even the conventional forward biased IC diode cannot be used as clamping devices for negative transients since substrate injection will occur as prescribed.
Thus, a need exists for symmetrically clamping the input voltage signal to the IC within a particular magnitude without producing the substrate injection of electrons.
USPTO Backgrounds
USPTO Backgrounds