1. Field of Invention
The present invention relates generally to memory technology. More generally, it relates to the use of symmetric resistive memory materials and devices for use as diodes for driving symmetric and asymmetric resistive memory elements. More specifically, the present invention is related to the use of a symmetric programmable material, such as phase change material (PCMA), as a diode for driving asymmetric programmable memory materials, such as solid electrolyte (SE) memories, or symmetric programmable memory materials, such as phase change memories (PCM), in a crosspoint array architecture. Device structures, material options, voltage sequences, etc. for symmetric programmable material (such as phase change material (PCMA)) needed for rectification of symmetric or asymmetric memory materials are described.
2. Discussion of Prior Art
The following references provide a general teaching of crosspoint arrays.
The U.S. patent to Hosotani et al. (U.S. Pat. No. 6,980,463) teaches a semiconductor memory device that has a structure using a rectifying element (e.g., a p-n junction diode) as a switching element connected to a Tunneling Magneto Resistive (TMR) element, wherein the described structure is a simple one capable of realizing a crosspoint cell.
The U.S. patent to Tsuneo Inaba (U.S. Pat. No. 7,046,546 B1) teaches a crosspoint memory cell with a memory device and a read switching element which may be a rectifying element.
The U.S. patent to Bozano et al. (U.S. Pat. No. 6,987,689 B2) teaches the possibility of achieving intrinsic rectification in a crosspoint memory element by the suitable choice of electrode materials.
The U.S. patent to Stasiak et al. (U.S. Pat. No. 7,034,332 B2) teaches a memory device including a substrate and multiple self-aligned nano-rectifying elements disposed over the substrate, wherein each nano-rectifying element has multiple first electrode lines, and multiple device structures are disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. According to Stasiak's design, the switching elements are made of phase change material.
The U.S. patent to Keiji Hosotani (U.S. Pat. No. 6,778,426 B2) teaches a magnetic random access memory (MRAM) using a phase change memory element instead of a tunneling magneto resistive (TMR) element.
The U.S. patent to Formigoni et al. (U.S. Pat. No. 4,795,657) teaches a memory cell with a rectifying element and a memory element.
The U.S. patent to Terry L. Gilton (U.S. Pat. No. 6,855,975 B2) teaches an integrated programmable conductor memory cell and diode device in an integrated circuit comprising a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment of Gilton's patent, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge2Se8 or Ge25Se75). In this embodiment of the Gilton patent, the first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type, and the memory cell comprises a chalcogenide glass element with silver ions therein.
The U.S. patent to Frederick A. Perner (U.S. Pat. No. 7,042,757) provides a 1R1D block architecture magnetic memory device. The Perner reference relates to magnetic memory devices, and in particular, relates to cross-point resistive devices such as magnetic random access memory arrays (MRAMs). By incorporating PN diodes, the effective size of the cross-point array may be increased beyond the traditional 1,000 columns by 1,000 rows.
The U.S. patent to Perner et al. (U.S. Pat. No. 7,031,185) teaches a resistive cross point memory cell array comprising a plurality of word lines, a plurality of bit lines, a plurality of cross points formed by the word lines and the bit lines, and a plurality of memory cells, each of the memory cells being located at a different one of the cross points, wherein a first bit line comprises a distributed series diode along an entire length of the bit line such that each of the associated memory cells located along the first bit line is coupled between the distributed series diode and an associated word line.
The U.S. patent to Sharma et al. (U.S. Pat. No. 6,885,573) teaches a diode for use in MRAM devices and method of manufacture of such a device. Sharma et al. teach a data storage device that has a plurality of word lines, a plurality of bit lines, and a resistive crosspoint array of memory cells. Each memory cell is connected to a bit line and connected to an isolation diode that further connects to a respective word line. The isolation diode provides a unidirectional conductive path from the bit line to the word line. Each word line provides a common metal-semiconductor contact with each diode sharing the word line such that each diode has a separate metal contact located between the semiconductor portion of the common metal-semiconductor contact and its respective memory cell. Sharma et al.'s MRAM device has improved unidirectional elements to limit leakage current within the array.
The U.S. patent to Sharma et al. (U.S. Pat. No. 6,754,097) teaches magnetoresistive devices or memory elements of a phase-change material, which are connected as a crosspoint network, wherein blocking devices such as diodes or transistors may be connected to the magnetoresistive devices.
The U.S. patent to Lung Tran (U.S. Pat. No. 6,678,189) teaches memory cell elements which may include thin film memory elements such as polymer memory elements, magnetic tunnel junctions (the SDT junction is a type of magnetic tunnel junction), or phase change devices. Each memory cell is limited in providing a conductive path in a first direction only by way of a unidirectional element, wherein such unidirectional elements could have diodes.
The U.S. patent to Goodbread et al. (U.S. Pat. No. 6,670,824) teaches an integrated polysilicon fuse and diode and methods of making the same. The integrated polysilicon fuse and diode combination may be implemented in a programmable crosspoint fuse array. The integrated polysilicon fuse and diode may be used in a random access memory (RAM) cell.
The U.S. Pre-Grant Publication to Ferrant et al. (2006/0067112 A1) teaches resistive memory cells (which can be brought into two or more states exhibiting different electrical resistance values), such as magneto-resistive memory cells including magnetic tunnel junctions as used in conventional MRAMs, phase change memory cells using some sort of a phase change material, and conductive bridging memory cells using some sort of a solid state electrolyte in combination with an ion donor electrode using a independent-gated FINFET architecture.
Whatever the precise merits, features, and advantages of the above cited references, none of them achieves or fulfills the purposes of the present invention.
USPTO Backgrounds
USPTO Backgrounds