In semiconductor wafers including microelectronic dies formed on the wafers and the like, an electrical signal can be transmitted or shared from one component part or die to another. This can be the case in testing a wafer when a test signal can be sent to multiple different dies. One problem with sharing an electrical signal from one part or die to another is that a malfunction or defect in any of the dies can adversely effect the electrical signal being shared and cause the remaining dies to malfunction or appear to fail the test when the dies may actually be good.
One example where electrical signals are shared by a plurality of different parts or dies is in a parallel test system for Wafer Level Testing (WLT). In WLT, multiple dies on a wafer can be evaluated simultaneously. Prior to WLT, each of the dies on a wafer can be individually tested by probe testing or by a similar procedure to determine if any of the dies have certain defects. After probe testing, several predetermined electrical signals can be applied to contact pads formed on the wafer to more efficiently test multiple dies simultaneously. If one or more of the dies in a group being tested together are defective, the integrity of the shared electrical signal can be impacted such that potentially all of the dies sharing the signal can fail the test. There can also be uses other than testing when electrical signals are shared and one or more defective parts or dies can adversely effect the electrical signals and consequently the performance of a device or system incorporating the dies.
Electrical signals such as the shared electrical signals can be applied to a die by a conductive pad formed on the die or wafer. For example, at least one test pad can be formed in association with each die for applying test signals during WLT. The different test pads that share the test signal can be interconnected by conductive lines or traces. During normal operation of the die, a test pad and associated interconnect lines or traces can become inadvertently coupled to an associated die or remnants of a test pad and associated interconnect lines after the dies are separated from the wafer can become inadvertently coupled to the die. The test pad and interconnecting lines can present a substantial capacitive and resistive load coupled to the die that can adversely effect performance of the die.
Accordingly, for the reasons stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for a circuit or device to isolate a defective die to prevent a shared signal from being impacted by the defective die and thereby adversely effecting the operation or testing of other dies to which the shared signal is applied. Additionally, there is a need for a circuit or device to prevent a test pad or other type pad from being coupled to an associated microelectronic die during normal operation of the die or during operation of the die other than when the pad is needed to apply a test signal or another signal. Further, there is a need for a method of testing multiple dies on a wafer where a defective die cannot adversely effect the testing of other dies sharing a common signal.
USPTO Backgrounds
USPTO Backgrounds