1. Field of the Invention
The invention relates to a chip package and a process for fabricating the same, and more particularly to a photo-sensitive chip package and a process for fabricating the same.
2. Description of the Prior Art
In the recent years, the electronic technology is advanced with each passing day and more new high-tech electronic products are presented to the public as well with more humanity, more convenience in the functions. However, all those products come into a trend toward lighter, thinner, and handier in order to provide more convenient and comfortable usage. Electronic packaging plays an important role in the fulfillment in communication industry and digital technology. Electronic consumer products such as PDA, Pocket PC, Portable PC and mobile phone accompanied with the digital image products such as digital camera and digital video cameras have become a trend.
The key component that makes a digital camera and a digital video camera capable of sensing images is a photo-sensitive device. The photo-sensitive device is able to sense the intensity of light and transfer electrical signals based on the light intensity for further processing. Furthermore, the packaging process is necessary to make the photo-sensitive chip connectable to outer electrical circuit through the substrate and protect the photo-sensitive chip from impurity and moisture contacting the sensitive area.
FIG. 1A is schematically cross-sectional view of a conventional chip package. Referring to FIG. 1A, a chip package 101 comprises a semiconductor chip 110, a circuitry board 120, a transparent substrate 130 and an adhesive material 140. The semiconductor chip 110 is formed by cutting and separating a wafer (not shown). The semiconductor chip 110 has a photo-sensitive area 112, multiple electronic components 114 and multiple connecting points. The photo-sensitive area 112 and the connecting points 116 are located on an active surface 110a of the semiconductor chip 110. The connecting points 116 are distributed around the photo-sensitive area 112. The electronic components 114, such as MOS devices or transistors, are allocated inside the semiconductor chip 110. In the photo-sensitive area 112 are an optical filter 12 and multiple micro-lenses 14 to filter and concentrate the light from the outside, respectively. The electronic components 114 in the photo-sensitive area 112 can sense the intensity of the light filtered and concentrated by the optical filter 12 and the micro-lenses 14 to generate electrical signals corresponding with the intensity of the light.
Referring to FIG. 1A, the semiconductor chip 110 is mounted on the circuitry board 120. The circuitry board 120 may comprises a hard core insulating layer, multiple polymer layers and multiple patterned metal layers. The polymer layers and patterned metal layers are formed on the top and bottom sides of the hard core insulating layer. The hard core insulating layer, such as FR-4 or FR-5, may comprise polymer and glass. The circuitry board 120 may includes multiple connecting points 122 on a top surface thereof and surrounding an area used to be joined with the semiconductor chip 110. After joining the semiconductor chip 110 and the circuitry board 120, multiple wires are formed by a wirebonding process to connect the connecting points 116 of the semiconductor chip 110 to the connecting points 122 of the circuitry board 120.
Referring to FIG. 1A, after the semiconductor chip 110 is mounted on the circuitry board 120 and multiple wires 10 are formed by a wirebonding process to connect the connecting points 116 of the semiconductor chip 110 to the connecting points 122 of the circuitry board 120, one of the transparent substrates 130 divided from a large plane piece of transparent material (not shown) is joined to the circuitry board 120 using the adhesive material 140. The material of the transparent substrate 130 is glass. The adhesive material 140 is epoxy resin. The adhesive material 140 surrounds the semiconductor chip 110 and the wires 10. The circuitry board 120, transparent substrate 130 and adhesive material 140 construct an airtight space 150 accommodating the semiconductor chip 110. Next, multiple solder balls 18 are formed on the bottom surface of the circuitry board 120 to form an electrical connection from the circuitry board 120 to a next-level printed circuit board (PCB, not shown). Thereafter, cutting the circuitry board 120 is performed and then multiple individual chip packages are completed.
FIG. 1B is a schematically cross-sectional view of another conventional chip package. Referring to FIG. 1B, the chip package 201 comprises of a semiconductor chip 201, a flexible circuitry substrate 220, multiple bumps 230, a transparent substrate 240, an adhesive material 250 and an underfill 260. The semiconductor chip 210 has a photo-sensing function and the detail structure of the semiconductor chip 210 can refer to the structure of the above-mentioned semiconductor chip 110 in FIG. 1A.
Referring to FIG. 1B, the bumps 230 are formed on multiple connecting points 216 of the semiconductor chip 210. Next, the semiconductor chip 210 is bonded to a metal layer 220a of the flexible circuitry substrate 220 through the bumps 230. The flexible circuitry substrate 220 further comprises an insulating polymer layer 220b joined to the metal layer 220a. Thereafter, the underfill 260 is provided to fill the space between the semiconductor chip 210 and the flexible circuitry substrate 220 and to cover the bumps 230. One of the transparent substrates 130 divided from a large plane piece of transparent material (not shown) is joined to the flexible circuitry substrate 120 using the adhesive material 250, wherein the transparent substrates 240 are glass, for example. At this time, the semiconductor chip 210, transparent substrate 240, flexible circuitry substrate 220, bumps 230 and underfill 260 construct an airtight space 270. Thereafter, the flexible circuitry substrate 220 is cut to form multiple individual chip packages 201.
It is worthy to notice that the fabrication of the package structures 101 and 201 as above-mentioned in FIGS. 1A and 1B is performed to attach the transparent substrate 130 or 240 onto the semiconductor chip 110 or 210 in a packaging fab. Therefore, the photo-sensitive areas of the semiconductor chips 110 and 210 will be exposed in a clean room in the packaging fab. Because the class of the clean room in the packaging fab is typically 100-100, many tiny dust particles in the air will fall on the photo-sensitive areas 112 and 212 of the chips 110 and 210. This affects their sensitivity.
Besides, in the prior art, such a process that the transparent substrate 130 or 240 after cut is joined piece by piece to the semiconductor chip 110 or 210 is joined to the transparent substrate 130 or 240 through the adhesive material 140 or 250 is not efficient.
USPTO Backgrounds
USPTO Backgrounds