1. Field of the Invention
The present invention generally relates to a semiconductor structure, and more particularly to a semiconductor structure comprising an intra-metal capacitor with an adjustable spacing between electrodes.
2. Description of the Prior Art
Passive components such as capacitors are widely used in an integrated circuit. Various types of capacitors may be formed conveniently incorporated with the process of constructing the integrated circuit by modern semiconductor manufacturing technology to fulfill different applications, such as junction capacitors, gate capacitors, and metal-to-poly or metal-to-metal capacitors. Among these various types of capacitors, metal-to-metal capacitors are known for better precision, predictable capacitance linearity and higher breakdown voltage, and therefore have been the mostly adopted type of capacitor in an integrated circuit, especially when a higher capacitance density is demanded.
A metal-to-metal capacitor may be formed by stacking the metal electrodes on top of one another to be the upper electrode and the corresponding lower electrode with an intermediate insulating layer formed therebetween. This kind of metal-to-metal capacitor is known as “an inter-metal capacitor”, wherein the metal electrodes are defined (formed) in different metal layers during the process. Extra mask layers and additional process are usually required to form an inter-metal capacitor.
Another kind of metal-to-metal capacitor is “an intra-metal capacitor”, wherein the metal electrodes are arranged side-by-side in a dielectric layer wherein the intermediate insulating layer is sandwiched between the sidewalls of adjacent metal electrodes. Please refer to FIG. 1, which is a schematic diagram exemplarily showing the structure of a conventional intra-metal capacitor 15. The electrodes 12 and 14 of the intra-metal capacitor 15 are formed side-by-side in the dielectric layer 16, and are completely separated by the intervening dielectric layer 16, wherein the electrodes 12 and 14 are arranged in such a close proximity to be capacitively coupled through the intervening dielectric layer 16 between their adjacent sidewalls. Conventionally, the electrodes 12 and 14 of the intra-metal capacitor 15 as shown in FIG. 1 are usually defined (formed) in a same metal layer of an interconnecting structure at the same time, such as a layer of metal routing or vias. The process of forming the intra-metal capacitor 15 may be completely integrated with the process of forming the layer of the interconnecting structure. Therefore, extra masks and additional process may be avoided. Furthermore, the sidewall area of the intra-metal capacitor 15 may be enlarged and consequently a larger capacitance may be achieved by, for example, forming conductive structures respectively and directly stacking on the top of the electrodes 12 and 14 in the following process of forming other layers of the interconnecting structure, and eventually building “electrode walls” which are vertically embedded through the layers of the interconnecting structure. In this way, extra layout area required for forming an inter-metal capacitor with a larger capacitance is minimized.
However, since the electrodes 12 and 14 of the intra-metal capacitor 15 are formed at the same time using a single photo mask, the distance 18 between them is constrained to the resolution limitation of the patterning process. In other words, the thickness of the intermediate insulating layer (the dielectric layer 16 between the sidewalls of the electrodes 12 and 14) is constrained to the minimum resolution (or called the minimum pitch) of the patterning process of forming the electrodes 12, 14 and the layer of interconnecting structure, resulting in a limited scalability in device shrinking or a limited capacitance of the capacitor 15. Therefore, there is still a need in the field to provide a novel intra-metal capacitor and the manufacturing process of forming the same which may be formed integrated with the process of forming a semiconductor structure and the spacing between the two electrodes is not constrained to the resolution limitation.
USPTO Backgrounds
USPTO Backgrounds