1. Field
Embodiments of the present invention generally relate to semiconductor testing.
2. Description of the Related Art
Testing is an important step in the fabrication of semiconductor devices. Typically, partially or fully completed semiconductor devices are tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. However, as the size of features formed on the DUT continue to be reduced, and/or spaced more closely together, problems arise with the scalability of the contact apparatus of the test system (for example, the resilient contact elements on the probe card). Such problems may be exacerbated by layout constraints of the testing equipment. For example, the layout of the terminals on the DUT may prevent the use of the testing apparatus for testing the DUT, or may require limiting testing of the DUT to fewer terminals at a time, thereby undesirably increasing the number of touchdowns and time to complete the testing. Moreover, many conventional designs are not scalable to smaller feature sizes due to architectures that are likely to buckle or move laterally upon shrinking the contact apparatus sufficiently to achieve the desired testing spacing.
Therefore, there is a need for an improved apparatus suitable for use in testing devices having smaller feature sizes.
USPTO Backgrounds
USPTO Backgrounds