As purchased, dual gate FETs vary in characteristics substantially unless they are purchased to an extremely tight characteristic tolerance. When solid state devices such as FETs are purchased to tight tolerances, the cost rises in accordance with the tightness of the tolerance. Thus, when less expensive FETs are purchased, the characteristics are such that the biasing points used to bias the gate on an FET must be adjusted for each individual circuit and readjusted whenever a new FET is inserted in place of a previous FET in a given circuit.
When an FET is used in a class A amplifier circuit where the objective is to have linear operation, feedback has been used from the drain to the gate to both stabilize the operating point of the FET and to linearize the output signal with respect to the input.
When an FET is used in a circuit where it is desired to mix two signals such as a local oscillator and an RF signal to obtain an intermediate frequency sum or difference signal, the basis of such mixing is in part related to the non-linear modulation of the FET channel due to the overdriving of the gate by the local oscillator signal. It is the non-linear characteristic of the FET which desirably causes the mixing action whereby the sum and difference of these two signals are created at the drain of the FET.
Since the non-linearity of the FET is a desirable characteristic when used as a mixer, one skilled in the art would assume that anything that would tend to reduce non-linearity, such as a feedback resistor, would diminish the performance of the FET in its mixing action. However, since the feedback is only applied to the gate receiving the RF input and is not applied to the gate receiving the signal which overdrives the gate, the operating point is stabilized with no measurable diminution of the mixing action as compared to prior art biasing techniques.
It is thus an object of the present invention to provide an improved mixing circuit from the standpoint of having a stable operating point while simultaneously reducing the complexity of the bias adjustment for the circuit with changes in FETs and their associated individual characteristics.
USPTO Backgrounds
USPTO Backgrounds