1. Field of the Invention
The present invention relates to a transistor assembly and to a method for manufacturing it, wherein structures in a polycrystalline semiconductor layer determine which parts of a transistor region are electrically isolated from other parts of another transistor region.
2. Description of Related Art
High-frequency transistors are usually grouped in technology families. Very flat doping profiles and minute geometries are characteristic of high-frequency transistors. Emitter and base contacts are arranged like fingers at the surface. In one prior art embodiment in a discrete high-frequency transistor type, the collector is connected from the back-side, or in another prior art embodiment and when the high-frequency transistor is arranged on an integrated circuit or IC, it is additionally supplied from the surface. In a number of prior art embodiments, the individual types within one technology family often only differ by the number of emitter and base fingers. In prior art embodiments, the low-level signal transistors typically have between 1 and about 50 emitter fingers, whereas in power transistors the number of fingers is in the order of magnitude of up to 1000.
In prior art embodiments where discrete high-frequency low-level signal transistors are employed, the transistor area actively utilized is often only a minute portion of the entire area of the chip. The boundary conditions of processability in mounting, however, require a certain minimum size for the chip.
In many prior art embodiments, the minimum chip area required today is about 0.20×0.20 mm2. Thus, a considerable portion of the chip area often remains unused, which makes the costs for manufacturing considerably higher than would be the case if the chip area corresponded to the transistor area actively utilized.
In order to make use of remaining empty chip area, a number of manufacturers producing transistors according to prior art embodiments have turned to arranging several transistor cells on a chip, which can be connected in different ways depending on the requirements in the metal level. The demand for photo masks is limited in this way.
Furthermore, in these prior art embodiments, the manufacturers of transistor assemblies can react more flexibly to changing customer requirements since it is only decided at the end of the wafer process or the manufacturing process of the wafers which one of the optional types will finally be produced.
A number of manufacturers of high-frequency transistors according to prior art embodiments employ the traditional planar process or variations or modifications thereof, wherein it is inevitable in such multiple designs for each of the transistor cells on the chip to be arranged in a way isolated from the others. FIG. 8 explains a transistor structure of a prior art embodiment.
A layer 11 positioned at the bottom of an assembly illustrated in FIG. 8 serves as a collector contact. A layer 21 arranged above it forms a collector 21. A base well 31 is arranged on a surface of the collector 21 facing away from the collector contact 11 and covers a part of this surface. The remaining part of the surface of the collector 21 facing away from the collector contact is covered by a field oxide 61.
Base contactings 41 arranged below base contacts 81 and emitter regions 51 positioned below emitter contacts 91 are introduced alternatingly into the base well 31 on the surface facing away from the collector 21. The base well 31 is covered by an oxide layer 71 serving as an isolator between the emitter contact or the base contact and the base well 31.
The field oxide 61, the oxide layer 71 and the base contact 81 and the emitter contacts 91 are coated with a passivation layer 101. In a prior art planar process illustrated here, the base well 31 into which all the emitter fingers 51 of a transistor cell are introduced is required.
In order to utilize a conventional chip area for a mass production process, which in prior art embodiments is often about 0.04 mm2, sensibly and economically, many different transistor types, quite often as many as possible, are accommodated on a single chip in prior art embodiments.
FIG. 7 explains such a prior art embodiment. There are three ways of forming a high-frequency transistor on a chip setup shown on FIG. 7. These three ways are to electrically connect either a transistor cell A 201 or a transistor cell B 211 or a transistor cell C 221 to an emitter pad 231 and a base pad 241.
In a scenario A where an activated transistor cell comprises one emitter finger, base fingers 201A are connected to the base pad 241 via a conductive track 201D, whereas an emitter finger 201B is connected to the emitter pad 231 via an emitter conductive track 201E in an electrically conducting way. It is to be pointed out here that the conductive track 201E between the emitter pad and the transistor cell A 201 and the conductive track between the base pad 241 and the transistor cell 201 are illustrated in continuous lines in FIG. 7.
In a scenario B, a transistor cell B 211 is connected, wherein a conductive track 211D is formed as a conductive track between the base pad and the transistor cell B 211 and a conductive track 211E is formed as a conductive track between the emitter pad 231 and the transistor cell B 211. The conductive tracks 211D, 211E implemented in this variation are illustrated in broken lines. The base conductive track 211 D thus connects the base pad 241 to four base fingers 211A, whereas the emitter pad 231 is connected to all three emitter fingers of the transistor cell B 211 via the emitter conductive track 211E. In scenario B, the chip of FIG. 7 is formed as a transistor assembly consisting of the transistor cell B, the transistor assembly now including three emitter fingers.
In a scenario C, the chip illustrated in FIG. 7 is formed as a transistor cell C having seven emitter fingers 221B. The base conductive track 221D and the emitter conductive track 221E are illustrated in dotted lines.
The chip illustrated in FIG. 7 can now be formed both as the transistor cell A 201 having one emitter finger 201B, as the transistor cell B 211 having three emitter fingers 211B or as the transistor cell C 221 having seven emitter fingers 221B. An electrical performance of the transistor formed on the chip depends on which transistor cell has been selected for the design. The electrical performance of the transistor is decisively determined by the number of emitter fingers.
In the sense of consistent cost optimization, the principle of multiple usage can be pushed to the limits, which means that as many different transistor types as possible may be accommodated on a single chip. It immediately becomes obvious that the area cannot be made use of optimally due to the requirement of minimum spacings between the individual transistor cells A 201, B 211, C 221. In addition, only predetermined transistor cells or combinations thereof may be manufactured as a transistor type in this method.
The limitation illustrated here is a consequence of the planar process.
USPTO Backgrounds
USPTO Backgrounds