FIG. 1 illustrates a typical hardware configuration for a computer 10 having a central processing unit (CPU) 12, a data cache memory unit 14, regular memory 18 and an input/output device 22. The CPU 12 includes a stack cache memory unit 23. The data cache memory 14 and the stack cache 23 are typically static random access memory (SRAM), whereas the regular memory 18 is dynamic random access memory (DRAM). The input/output device 22 can be any type of peripheral attached to a computer which generates or uses data, such as a data storage device or a network interface. The CPU 12, stack cache 23 and data cache 14 are generally part of a microprocessor 24. Generally, the CPU 12 includes a stack pointer 26.
Data, computer programs (applications) and/or parts of programs running on the computer 10 are stored in the regular memory 18 and in the data cache memory 14. Typically, information travels between the data cache memory 14 and the CPU 12 much faster than it travels between the regular memory 18 and the microprocessor 24. For example, information may travel between the data cache memory 14 and the CPU 12 in ten nanoseconds, whereas the same transaction between the regular memory 18 and the microprocessor 24 would take one hundred nanoseconds. Therefore, frequently used information is stored in the data cache memory 14 so that it can be accessed faster by the CPU 12.
Periodically, information stored in the data cache 14 has to be deleted. The process of deleting information from the data cache 14 is referred to as a cache flush operation. For example, a cache flush is necessary when it is desired to ensure that the same information is contained in the data cache memory 14 as in the regular memory 18. If the microprocessor 24 is a RISC based microprocessor, the cache flush operation can specify the address of each cache line and cause information at each cache line address to be deleted. However, with stack based microprocessors (e.g. a JAVA.TM. microprocessor), cost sensitivity makes it undesirable to specify the address of each cache line. Moreover, with stack based microprocessors, the bytecodes for the cache flush operation have to be small (about two bytes). Therefore, a simplified cache flush procedure is needed for use with stack based microprocessors.
USPTO Backgrounds
USPTO Backgrounds