Synthesizer circuits are common sub-blocks of many data-communication systems. A common aim is the generation of a signal that has a fixed relation to the phase of a reference signal. This aim is achieved by a phase-locked loop for example, which is found in many circuits, including integrated circuits (ICs). A synthesizer circuit like a phase-locked loop circuit may be designed based on different kinds of implementations. Generally a phase or frequency difference is converted to a signal. For convenient processing, the generated signal may be a digital signal. Thus the circuit arrangement which is to convert the phase or frequency difference to a digital signal is an important component of many such synthesizer circuits. Noise in the generated signal is problematic. Furthermore, an implementation of a phase-locked based on analog circuitry poses challenges in the design and manufacture process for digital circuits, in particular for integrated digital circuits. Another concern especially in ICs is the reduction of power consumption.
Published United States Patent Application US 2006/0171495 discloses a digital phase detector for a phase locked loop. However US 2006/0171495 lacks an implementation suitable for convenient integration into an IC and for reducing power consumption. It is an object to provide a phase frequency to digital converter architecture which can be easily integrated into the design and manufacture process for an IC and which is suitable for reducing energy consumption. It is a further object to provide a phase frequency to digital converter architecture with short reaction times and which can take advantage of future miniaturization advances in CMOS technology. An additional object is to reduce energy consumption in particular for the situation that the phase error in a phase locked loop is small. Moreover an object is to prevent an occurrence of undefined states when the phase error is below a lower threshold region.
USPTO Backgrounds
USPTO Backgrounds