High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory. In recent years, there has been an effort to increase access speed while reducing power consumption for semiconductor devices. As part of that effort to increase access speed, it may be desirable to include input signal receiver circuits having faster operation for receiving address signals, command signals, and clocks. Simultaneously, it may be desirable to accommodate a wide range of input signals at the input signal receiver circuits to meet recent semiconductor devices (e.g., low-power double data rate synchronous DRAM).
Typical signal receiver circuits include differential amplifier circuits that receive an input signal and amplify a voltage difference between the input signal and a reference voltage. The differential amplifier circuits remain active in order to be ready to receive asynchronous input signals that include information at any time during operation. Remaining active during operation, however, continually consumes power. The continual power consumption is not insignificant, and in low power systems, may be undesirable.
Therefore, it may be desirable for alternative input signal receiver circuits with reduced power consumption during operation.
USPTO Backgrounds
USPTO Backgrounds