The present invention relates to semiconductor memories. In particular, the present invention relates to semiconductor memories having redundancy thereon. In particular, the present invention relates to semiconductor memories which are organized to output more than one bit simultaneously, e.g. to a memory which is organized according to nine-bit bytes, so that each read cycle provides nine bits of information simultaneously at nine I/O pads.
As is well known in the art, there are substantial advantages to byte-wide memory organization. ("Byte-wide" is frequently used to refer only to by-8 memories, but is used in the present application to refer to any memory which is more than one bit wide.) This reduces the board-level overhead, and in general provides additional convenience to the system-level designer.
A further known desideratam in large memories is redundancy. Most bad memory chips at reasonable maturity of process have only a few bad bits. If these bad bits can be replaced by redundant elements, yield improvement can be obtained. Initially when yields with an aggressive design are small, redundancy can enhance the yield by as much as an order of magnitude. Even in a mature product the loss in yield due to increased chip area is likely to be offset by yield improvement due to repaired chips.
Memory chips which are organized as byte-wide are particularly desirable for small systems. Where the whole memory requirements of a sub-system can be satisfied with, e.g., three or four 64k memory chips, it would be exceedingly wasteful to go to a memory board using a by-one organization. A further advantage of byte-wide chips from a designer's point of view is in expandable memory configuration systems. That is, where a board can be used with various memory size options, and the smallest option is at most a small multiple of the number of bits per chip, it is much more efficient from the system designer's point of view to be able to use byte-wide memory chips.
One method of implementing redundancy in a byte-wide memory would be to have a whole redundant block, which could be substituted for one redundant bit position. That is, for example, in a 4k.times.9 half-array, one entire 16 column by 256 row block could be provided as a redundant bit position which could be substituted for any bit position which happens to contain one or more defects. However, this approach is not only tremendously wasteful of area, but also would not solve the problems of defects in more than one bit position.
It is desirable to minimize the row decode delays, which means (preferably) minimizing the length of word lines. In a large memory, this means that the memory is preferably partitioned in subarrays. This in turn means that redundancy is preferably provided separately for each subarray. The present invention could be implemented in an embodiment where a redundancy block was shared between subarrays, but this is not preferable due to the increased complexity of wiring, and at chip-level logic (i.e. subarray-select logic).
A byte-wide memory could be organized as, for example, two half-arrays each containing nine bit positions. Each "bit position" is a set of 16 columns side by side, all of these columns (with their respective 16 primary sense amplifiers) being multiplexed into a secondary sense amplifier corresponding to that bit position. Thus, where there are 256 rows, each half array contains 16.times.256 nine-bit words and each of these words can be provided from the half array as a completely parallel output.
However, there have heretofore been difficulties in combining these two improvements. That is, it has not been practical to configure a byte-wide memory having redundancy.
Thus it is an object of the present invention to provide a byte-wide semiconductor memory having redundancy.
A problem in the prior art of redundant memory circuits is the conservation of wiring space. Redundant memory designs have typically been modifications of memory designs which do not incorporate redundancy. This subsequent modification of an existing design is likely to induce great pressure on the available wiring space on the chip.
It is an object of the present invention to provide a memory, incorporating redundancy, which requires only a minimal amount of metal wiring to embody the redundancy.
In particular, it would be relatively simple to provide one redundant column for each bit position, but this approach is far from optimal, for a least two reasons. First, this occupies an excessive amount of real estate with redundancy circuits. That is, in an 8k.times.9 memory at least nine redundancy circuits would be required (or, even worse, 18, if each bit position includes columns in each half-array), rather than the 2 or 3 redundant columns per array unit which would otherwise be desirable. A second problem is that this approach would be hopeless in the case where more than one defective column is found within a single bit position. That is, in a 4k.times.9 half array, of those half arrays which have exactly two defective columns, approximately one-ninth of them will have the two defective columns located in the same bit position. Thus, a significant fraction of defect cases could not be fixed by this approach.
A further reason for using column redundancy rather than row redundancy is that upper-level metal patterning is typically a lower-yielding process than polysilicon, polycide or first-level metal patterning. That is, upper level metal patterning is not only subject to much more topographic excursion, but metal patterning in general is less intimately involved in cell area and is therefore typically not as intensively refined as polysilicon patterning processes. Thus, patterning defects which will cause a whole column of the memory array to fail are more likely than patterning defects which will cause a whole row to fail. That is, defective bits are not randomly distributed, but exhibit an anomalous correlation along the column access, and the redundancy mechanism should replicate this for optimal efficiency.
In conventional memory architecture, column redundancy is generally preferable to row redundancy. That is, metal is typically used for the bit lines, whereas the word lines are usually made of polysilicon or some other higher-resistance material. Thus, the bottleneck in access time is the row line delays. Thus a small amount of logic can be incorporated in the column-selection circuitry without increasing the total accessing delay of the memory, whereas no such additions can be made to the row-line logic. For this reason, it is preferable to incorporate both the logic for byte-wide parallel access and also the logic for redundancy in the column organization. It would obviously be easier from a design standpoint to organize these along orthogonal axes of the array, but this would increase the total delay of the memory, and is therefore not acceptable. However, it should be noted that, even if the physical organization of these elements can not be orthogonal, their functions are properly orthogonal. That is, a redundant column should preferably be capable of substitutions for any column in any bit position in the array, and multiple redundant columns should be capable of independent substitution decisions, including substitution for multiple columns at a single bit position of the array.
It is an object of the present invention to provide a semiconductor memory having byte-wide organization by columns and also having redundant columns which can each be substituted for any defective columns within any one of multiple bit positions.
It an object of the present invention to provide a semiconductor memory organized in sub-arrays each containing columns corresponding to two or more bit positions, and each subarray containing a plurality of redundant columns which can each be substituted for a defective column in any bit position of that sub array.
One important constraint on the memory system which incorporates redundant columns available to any bit position in a byte-wide memory is the relative timing between select and deselect. It is important that the defective column be deselected before it can again provide erroneous output information, when its address is accessed. That is, it is desirable that the defective column should be disabled before the row access time has elapsed. It is also preferable, to avoid excessive delay, that the redundant column should be enabled before the row access time has elapsed. Finally, it is also desirable that the defective bit position be disabled before the redundant column is enabled. This is not strictly necessary, but is a desirable precaution to avoid the possibility of the sense amplifier of the defective column fighting against the sense amplifier of the redundant column, which could lead to excessive current on the buss and possible damage to the devices.
It is an object of the present invention to provide a semiconductor memory having byte wide column organization and column redundancy, wherein a predetermined defective column position is always disabled prior to enablement of a redundant column which replaces that defective column position.
Many of the problems of redundant memories are most easily solved in laser-selected redundancy, wherein a laser (or electron beam) can destroy inter-connects or devices at essentially any position on the chip. That is, the problem of overhead circuitry is immensely simplified when the whole chip area can be spatially addressed during an independent redundancy programming process, and high-current pathways can be made or broken. However, the problem with such approaches is that they require an expensive and slow processing step which is preferably performed prior to final packaging of the device. Thus, not only is throughput greatly degraded, which sacrifices many of the advantages of redundancy programming in the first place, but since subsequent processing is required after redundancy programming, defects which first manifest themselves during the subsequent processing steps may not even be compensated for or even detected.
The alternative to such externally spatially-addressed redundancy programmation schemes is electrical redundancy programmation typically using a fuse-blowing operation. That is, after the chip has been probed, on-chip fuses using thermal-write/electrical read mechanisms (such as blowing a thin polysilicon fuse link or spiking through a junction) are used to change the static voltage on certain circuit nodes. (This can even be done after final packaging, if sufficient pin-outs are provided, but is preferably done at the multiprobe stage.) Not only are these electrically written mechanisms limited to certain circuit nodes, but also the read mechanisms thus used are typically low-current, so that amplification and buffering stages must be used to provided useful outputs. High voltage for such electrically-accessed programmation steps may be externally supplied or may be generated on chip, or (which is slightly more difficult) fusible devices which will reliably self destruct at normal power supply voltages may be used, although these must be carefully positioned.
Thus it is an object of the present invention to provide a byte-wide semiconductor memory having column redundancy, wherein the redundancy information programmation is electrically accessed.
It is an object of the present invention to provide a byte-wide semiconductor memory with column redundancy, wherein the redundancy information programmation can be performed after final packaging.
The present invention teaches a semiconductor memory including multiple bit positions in each subarray, wherein each bit position contains several columns of memory cells. When the memory is read out, one bit will be read out at each bit position, from a bit within one of the columns which are located at that bit position. Fuse information is programmed, after the memory has been probed, to indicate which columns in the subarray are defective. For each redundant column, a separate address decoder block continually tests the input column addresses received by the memory, to see if one of the column addresses received corresponds to the unique defective column in one particular bit position which that redundant column has been programmed to replace. The sense amplifier at the bit position in which the accessed column is defective is then disabled, a sense amplifier for the redundant column is enabled, and a multiplexer connects the output from the redundant column sense amplifier to the appropriate output buss so that the information read out from the redundant column is inserted at the appropriate bit position in the output word. This operation can be seen more clearly in the following specific example, although the present invention is certainly not limited to the preferred embodiment or to any of the specific features thereof.
The preferred embodiment uses a 8k.times.9 memory array which is partitioned into two 4k.times.9 sub arrrays. Each 4k.times.9 sub array contains nine bit positions, each including 16 columns, each containing 256 bits accessed by respective wordlines. Each subarray also contains two redundant columns, each with its own fuse-programmed redundancy information. One bit of the input address is used to select which half array is to be accessed, and this first one-bit decode step is preformed at higher-level array overhead. Therefore the following discussion relates to only one of the sub arrays, i.e. to a 4k by 9 subarray containing nine bit positions of 16 columns each. Suppose that, for example, a particular subarray contains a defective column (which may contain only one defective bit, or may contain many defective bit locations) in column 3 of bit position 1, and also contains another defective memory column at column 6 of bit position 2. The input address will contain four bits which specify the column position (i.e. which specify some one of the 16 columns in each bit position), and will also contain 8 bits to specify one of the 256 rows. Suppose, in this example, that column one and row one is selected by the address input. Then, in each bit position, column 1 of the 16 available columns will be activated, and the first cell in that column (selected by wordline WL1) will be selected. The information contained in the cell at row one of column one at each of the nine bit positions will be fed into the nine primary sense amplifiers which correspond to those nine columns, the output of those nine primary sense amplifiers will be connected to nine respective secondary sense amplifiers, and the output of those nine secondary sense amplifiers will be provided to output busses which lead to the I/O buffers, amplifiers, and external contact pads. There is one primary sense amplifier for each column of cells, i.e. 16 primary sense amplifiers for each of the nine bit positions, but there is only one secondary sense amplifier for each four primary sense amplifiers, i.e. a total of 36 secondary sense amplifiers. At each bit position one of the four secondary sense amplifiers is multiplexed onto the output buss. Thus, information corresponding to nine bits will simultaneously appear on the contact pads of the device.
In this same example (where the defective columns are column 3 of bit position one and column 6 of bit position 2), let us suppose that the address information externally received now corresponds to row 100 and column 3. In this case, the address decoder in the logic associated with the first redundant column will detect that a match has occurred (on column 3) but no match will be detected by the logic associated with the second redundant bit. Four fuses in the redundant column store information which indicates that column 3 is defective in one of the bit positions. Four more fuses are used to encode information which shows exactly which bit position contains the defective column. Thus, once an address match with the defective column address has been detected, the logic in the first bit position then accesses one of nine disable blocks. (The disable block is a novel circuit taught by the present invention, which will be described in more detail below.) In effect there are nine disable blocks, one for each bit position. The bit position information in the first redundant column logic is used to select which of the disable blocks a disabled signal will be provided to. In this case, a disable signal is provided to the disable block at bit position one. The disable block at bit position one is connected to the secondary sense amplifier at bit position one, and disables this sense amplifier, so that no information whatever can be placed onto the bus from the 16 columns included in bit position one.
Thus, the first operation performed in this case by the first redundant circuit logic is to disable the bit position at which a defective column was about to be addressed. A second operation was also performed to properly substitute the information stored in the memory cells of the redundant column for the information which was contained in the defective column, namely column three of byte position one. That is, redundant column one contains 256 memory cells, accessed by the same wordlines as the memory cells in the other 144 columns of the main memory of the half-array. This row of memory cells has its own primary and secondary sense amplifiers, and the secondary sense amplifier incorporates a disable circuit (as do the secondary sense amplifiers for the 144 primary columns of the half-array). When an address match to the column address stored in four of the fuses for the first redundant column is detected, the sense amplifier for this redundant column of memory cells is enabled. Thus, when the wordline for the selected row (number 100 in this example) finally goes high, the bit stored at position 100 in the redundant column will be accessed, and the primary and secondary sense amplifiers of redundant column number one will amplify the information which was stored in this memory cell. The information stored in the remaining four fuses of redundant column one now selects which of the output busses the output of a secondary sense amplifier of the redundant column will be connected to. A simple one-of-nine multiplexer accomplishes this.
All of the foregoing operations are completed before the delay normally associated with word line decoding and access has expired. That is, after an address transition (when both the row and column inputs provided from the external pins of the memory package typically change), it will typically take 2-5 NS for the address buffer to change state, and 5-6 NS thereafter until the column decoders raise lines corresponding to the selected column. In the present invention, the secondary sense amplifier of the disabled column (column 3 in the above example) will also be disabled at about this time. About 7-10 NS later, the redundant column will be enabled. Thus, all of these events have occurred in a total delay of about 15-20 NS after the address transition at the input pads. However, it will typically not be until 4-5 NS after the address buffer transition that the row decoder will change state, and, due to wordline delay, it will typically not be until an additional 4-5 NS later that the row-selected memory cell in each column is accessed. Typically another 15-20 NS will be required for the sense amplifiers to change state. It should be understood that all of these timings are approximate, contingent, and in no way essential to the present invention, but they are incorporated here to provide some understanding of the general characteristics of operation of the present invention.
It should be noted that the byte-wide redundancy implementation of the present invention is relevant to any semiconductor memory, that is to static rams, dynamic rams, nonvolatile rams, EPROMS, EEPROMS, or to other memory types. The presently preferred embodiment relates to a static ram, but the invention is also applicable to all of these other types. A further feature of the present invention, which is important in most but not all of these other memory technologies, is the write control. That is, the operation described above relates to the read operation of a memory retaining a redundant column, but the control of the write operation of a redundant-column byte-wide memory also presents significant problems. It is necessary that any write cycle which attempts to write information into a defective column should in fact write that information into the corresponding cell of the particular redundant column which has replaced that defective column. Thus, in a write cycle in the present invention the detection of the address match on the accessed column is the same as above. That is, if redundant column one replaces column three in bit position one, then whenever a write into (e.g.) cell number 100 in column three is attempted, the information of bit one of the nine bit word which is sought to be written into the memory must be written into redundant column one rather than into column three of bit position of the main array.
The write operation in this case will be described, again by way of example rather than as any necessary limitation. An address match between the column address ("3") and the information stored in the column address bits in the fuses of redundant column one will first be detected. When this match is detected, the write buffer for redundant column one will be enabled. The second four bits of redundancy information stored in fuses and in redundant column one will again be used to control a multiplexer, which is now demultiplexing the nine bits of the input buss into the write buffer. That is, in this example, the second four bits of stored fuse information say that the bit position at which column three is defective is bit position one. Therefore, the input buss which contains information being sent into the chip will provide the appropriate bits to be stored in the main array (in row 100 of column three) for each of bit positions two through nine. However, the multiplexer will connect the input buss line corresponding to bit position one into the write buffer of redundant column one. This write buffer is connected to the sense amplifiers for redundant column one, so that the externally-generated information corresponding to bit position one of the word being stored in memory is latched onto the bit lines of the first redundant column, and therefore, when word line 100 eventually goes high, the stored information in cell 100 of redundant column one will be written over by the externally received information. Thus, when a later attempt is made to read out the word stored at row 100 of column three, the correct information for the first bit of this word will be stored in redundant column one.
A further important advantage of the present invention is that the demands on metal wiring area are minimized. Only those signals which require high speed are routed through metal wiring to accomplish the redundancy function, and the other signals are routed through moat levels. That is, in effect, the bit position output from each redundancy logic block is maintained as a dc signal, which is coupled to the disable block for each bit position by conductive paths at the moat level. These dc signals are decoded to provide a dc signal which, for each redundant column, controls a pass transistor. Each pass transistor controls a connection, for only one bit position, between the output of the address-match detector in the redundant column logic and the disable logic in the sense amplifiers corresponding to that bit position. Thus, only one high-speed connection is provided from each redundant column logic to all the disable blocks, and thus only one metal wire is required. This extreme efficiency in conserving metal wiring means that redundancy according to the present invention can be retrofitted into a wide variety of prior art byte-wide memories.
Thus the present invention provides a byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the column address and the stored defective-column column address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever row line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has ever been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.
According to the present invention there is provided:
A memory comprising:
a plurality of memory cells arranged in rows and columns, said columns of memory cells being organized by bit positions, each bit position including more than one of said columns of memory cells and at least one sense amplifier;
at least one redundant column of memory cells, and a sense amplifier operatively connected thereto;
at least two output means, said output means being connected to respective ones of said array sense amplifiers to provide simultaneous data output corresponding to memory cells at different ones of said bit positions;
redundancy select logic storing defect position information, including both defective column address information and also bit position defect information indicating which of said positions includes said defective column;
and wherein said redundancy select logic connects said redundant column sense amplifier to said output means corresponding to the one of said bit positions which is encoded by said bit position defect information, wherever said externally received column address matches said stored defective column address;
and wherein said array cells, said redundant cells, said sense amplifiers, said output mens, and said redundance select logic are all integrated on a single chip.
According to the present invention there is also provided:
A memory array comprising input means, output means, and a plurality of subarrays, each memory subarray comprising:
A plurality of memory cells arranged in rows and columns, said columns of memory cells being organized by bit positions, each bit position including more than one of said columns of memory cells;
At least one sense amplifier for each of said bit positions, whereby respectively independent bits of information are selectively provided as output from more than one of said bit position simultaneously;
At least one redundant column of memory cells, and a sense amplifier connected to each said redundant column of said memory cells;
At least two output means, said output means being connected to respective ones of said array sense amplifiers to provide data outputs corresponding to different ones of said bit positions;
An address decoder, connected to receive externally generated row and column addresses, said address decoder being connected to a plurality of said bit positions sense amplifiers to access a plurality of memory cells, each corresponding to said externally received row and column addresses, at more than one of said bit positions simultaneously;
Where said redundancy select logic stores defect position information, said defect position information corresponding to the position of a defective column in said array of memory cells, said defect position information including both a column address corresponding to said defective column and also bits indicating which bit position includes said defective column;
Wherein said redundancy select logic is operatively connected to said address decoder, to monitor said externally received column addresses and to detect whenever a match occurs between one of said externally received column addresses and said stored defective column information;
And wherein, whenever said redundancy select logic has detected a match between said external column address and said stored defective column address information, said redundancy select logic connects said redundant column sense amplifier to said output means corresponding to the one of said bit positions which is encoded by said bit position defect information;
And wherein said array cells, said redundant cells, said sense amplifiers, said output means, and said redundancy select logic are all integrated on a single chip.
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USPTO Backgrounds