The present invention relates to semiconductor design technologies; and, more particularly, to an internal voltage generation circuit for generating an internal voltage used in a semiconductor device.
Generally, a cell size within a semiconductor chip is gradually becoming smaller as the chip is highly integrated. Also, an operating voltage is being lowered due to such a small-sized cell. Most of semiconductor chips incorporate therein an internal voltage generation circuit for generating an internal voltage to thereby supply voltages required for operating internal circuits of the chip themselves. The internal voltages generated by the internal voltage generation circuit include a word line rise voltage VPP, a core voltage VCORE applied to a cell and Bit Line Sense Amp (BLSA), a voltage VPERI fed to peripheral circuits, and so on.
FIG. 1 shows a block diagram for describing a conventional internal voltage generation circuit.
Referring to FIG. 1, the internal voltage generation circuit includes a high voltage generator 10 connected between an external voltage end VCC and a ground voltage end VSS, a core voltage generator 20, and a cell 30 receiving a core voltage VCORE generated by the core voltage generator 20. Here, the cell 30 illustrates a representative one of various internal circuits accepting the core voltage VCORE.
The high voltage generator 10 generates a high voltage needed for a word line WL, and the core voltage generator 20 generally serves to generate a core voltage VCORE required for the cell 30, the BLSA, and so on.
FIG. 2 is a detailed block diagram for describing the core voltage generator 20 depicted in FIG. 1.
Referring to FIG. 2, the core voltage generator 20 is provided with an active internal voltage generator 20a and a standby internal voltage generator 20b. 
The standby internal voltage generator 20b is always operated in order to maintain an electric potential of a core voltage VCORE regardless of the operation state of a semiconductor device. And, the active internal voltage generator 20a is operated for securing the core voltage VCORE with a large driving force which is a voltage generated in response to an active signal active_flag activated during an active operation.
Here, the active signal active_flag refers to a signal which becomes active when the core voltage VCORE is much used, that is, in the state that the word line WL is boosted, including both a self refresh state and an auto refresh state of the semiconductor device.
The core voltage VCORE thus generated is fed to the cell 30 and used as a power supply voltage. The cell 30 shows a representative one of various internal circuits receiving the core voltage VCORE, as in FIG. 1.
FIG. 3 is a detailed circuit diagram for explaining the core voltage generator 20 depicted in FIG. 2.
With reference to FIG. 3, the core voltage generator 20 is constituted by a reference voltage generator 20c, a standby internal voltage generator 20b, and an active internal voltage generator 20a. 
The reference voltage generator 20c is to generate a reference voltage VREF by using an external voltage VCC applied thereto. Since this is already well-known in the art, details thereof will be omitted here for simplicity.
The standby internal voltage generator 20b compares the reference voltage VREF with the core voltage VCORE to boost the core voltage VCORE when it is less than the reference voltage VREF, and is constituted by a voltage comparator 21b composed of a current mirror type differential amplifier, and a pull-up driver PM1.
The voltage comparator 21b provided in the standby internal voltage generator 20b is composed of an NMOS transistor NM1 for taking a signal v_vias for always enabling the standby internal voltage generator 20b via its gate, an NMOS transistor NM2 connected between a node N1 and the NMOS transistor NM1 for receiving the core voltage VCORE via its gate, a PMOS transistor PM2 coupled between an external voltage end VCC and the node N1 for accepting a voltage level of the node N1 via its gate, a PMOS transistor PM3 coupled between the external voltage end VCC and a node N2 for accepting the voltage level of the node N1 via its gate, and an NMOS transistor NM3 connected between the node N2 and the NMOS transistor NM1 for taking the reference voltage VREF via its gate. And, the pull-up driver PM1 is composed of a PMOS transistor connected between the external voltage end VCC and the core voltage end for receiving a voltage of an output end of the voltage comparator 21b, i.e., the node N2, via its gate.
The active internal voltage generator 20a serves to secure a greater driving force during an active operation, and is constituted by a voltage comparator 21a for comparing the reference voltage VREF with the core voltage VCORE in response to an active signal active_flag, a pull-up driver PM4, and a switch PM5 for turning off the pull-up driver PM4.
The voltage comparator 21a and the pull-up driver PM4 of the active internal voltage generator 20a are identical in constitution to the voltage comparator 21b and the pull-up driver PM1 of the standby internal voltage generator 20b except that the generator 20a employs the active signal active_flag instead of the enable signal v_vias used in the standby internal voltage generator 20b, and further has the switch PM5. The switch PM5 is coupled between the external voltage end VCC and an output end (a node N3) of the voltage comparator 21a, and composed of a PMOS transistor for receiving the active signal active_flag via its gate.
Now, an operation of the core voltage generator 20 will be described in detail. First of all, in response to the enable signal V_bias during a standby operation, the voltage comparator 21b of the standby internal voltage generator 20b generator is enabled, and compares the core voltage VCORE with the reference voltage VREF to output a logic low level if the core voltage VCORE is lower than the reference voltage VREF. Thus, the pull-up driver PM1 is turned on, so that the core voltage VCORE increases. Further, if the core voltage VCORE is higher than the reference voltage VREF, the voltage comparator 21b provides a logic high level. In response to the logic high level, the pull-up driver PM1 is turned off, which stops the increase of the core voltage VCORE.
Meanwhile, when the active signal active_flag transitions to a logic high level during an active operation, the active internal voltage generator 20a is driven. The active internal voltage generator 20a performs the same operation as the standby internal voltage generator 20b, thereby ensuring the core voltage VCORE with a greater driving force.
In conclusion, the core voltage generator 20 enables the standby internal voltage generator 20b to be driven during the standby operation, while enabling both the standby internal voltage generator 20b and the active internal voltage generator 20a to be driven during the active operation, so that a greater driving force can be secured. This prior art configuration decreases a power consumption by making the driving force different depending on the operation state of the semiconductor device.
However, power draw on the core voltage VCORE is high only during a certain time period after the active signal has transitioned from the logic low level to the logic high level, not the entire time during which the signal is at the logic high level.
Because of this, the driving of the active internal voltage generator 20a for a certain time period after the active signal has transited from the logic low level to the logic high level causes larger power consumption than needed.
USPTO Backgrounds
USPTO Backgrounds