I. Field of the Invention
This invention relates generally to high voltage semiconductor devices. More particularly the present invention relates to MOSFET type semiconductor devices having reduced cell pitch and increased electrical ruggedness against activating the inherent parasitic bipolar junctions in the device. Most particularly, this invention pertains to a double diffused metal oxide semiconductor (DMOS) and an insulated gate bipolar transistor (IGBT) having an increased ruggedness against inherent parasitic bipolar effects and having a reduced cell pitch. In addition, the present invention pertains to a method of manufacturing DMOS and IGBT devices having increased electrical ruggedness and reduced cell pitch.
II. Background Art
Several types of designs for semiconductor devices having regions of alternate conductivity, such as MOSFETs, DMOSs and IGBTs, exist. These devices, simply by their construction, possess undesirable bipolar effects which may be triggered when operated at certain conditions as a result of the parasitic NPN (or PNP) junctions of the device. Thus, when the devices are operated at high voltages, should the parasitic NPN (or PNP) junctions be activated, the devices will enter breakdown mode, thereby causing unwanted current flow and possible destruction.
Several patents exist which disclose techniques to make each semiconductor device more rugged against the activation of the parasitic NPN (or PNP) junctions. In other words, these patents discuss increasing the safe operation area of the device before the parasitic bipolar effects are triggered so that the device will remain in its off state at higher voltages. For example, U.S. Pat. No. 4,810,665 (Chang et al.) discloses a method of making a rugged MOSFET which has a deeply diffused P+ region (diffused into a major surface) located in the center of a ring shaped N+ source region (for an N-channel device). The central P+ region shorts out the emitter and base regions (the source and body, respectively) of the parasitic NPN of the device, thereby allowing the device to be operated at higher voltages. In addition, the source contact is in conductive relation with both the N+ and P+ regions on the major surface of the device so that the emitter and base regions are also shorted on the major surface.
Among the causes of absence of ruggedness in N-channel MOSFET devices is the appearance of holes in the vicinity of the lower potential source contact when the device is operated at high voltages. The Chang et al. patent, for example, makes no provision for the removal of such holes from the lower potential source contact. In addition, the need for the deeply diffused P + region limits the amount the cell pitch of the device can be reduced because the lateral diffusion resulting from the deeply diffused P+ region extends into the active area of the device, thereby degrading the device characteristics.
U.S. Pat. No. 4,587,713 (Goodman et al.) discloses a MOSFET device having improved electrical ruggedness against parasitic bipolar effects. The Goodman et al. device, like Chang et al., also incorporates a ring-shaped source region but, utilizes a supplementary region which, in effect, shorts out the base and emitter regions of the parasitic NPN (or PNP). However, the supplementary region is difficult to construct and thus makes this device impractical to manufacture. In addition, this device, like Chang et al., does not provide a way of removing generated holes from the source contact without traversing an area under the emitter which can create a sufficient voltage drop to forward bias the emitter-base junction of the parasitic NPN, thereby activating the parasitic NPN and degrading the device by causing current to flow when the device is in its off state. It is, therefore, desirable to have a semiconductor device having a reduced cell pitch while still maintaining electrical ruggedness against activating the parasitic bipolar effects.
Accordingly, it is an object of this invention to provide a semiconductor device such as a DMOS or IGBT having a reduced cell pitch without degrading the on-characteristics of the device and with increasing the electrical ruggedness against parasitic bipolar effects.
It is a further object of the present invention to provide a method for manufacturing a rugged reduced cell pitch DMOS or IGBT.
Other objects of the present invention will become apparent as the following description proceeds.
The foregoing as well as additional details of the present invention will become apparent from the following detailed description and annexed drawings of the presently preferred embodiment thereof.
USPTO Backgrounds
USPTO Backgrounds