Programmable logic devices (e.g., complex programmable logic devices or field programmable gate arrays) are well known in the art. Programmable logic devices (PLDS) can potentially handle a wide range of input/output interface standards, because of their flexible programmable circuitry.
A drawback of PLDs is that their performance is generally limited due to the nature of their flexible, programmable core logic circuitry. To support high-speed input/output interface standards that exceed the speed (e.g., clock rate) of a PLD's core logic, the PLD must have a high-speed to low-speed input/output interface. This interface, for example, may employ programmable multiplexer and/or demultiplexer circuits (also known as mux/demux circuits).
However, because typically input/output circuits on the PLD are programmable, along with clock and data paths (e.g., placement of a particular bus is done by a user resulting in a variable location and/or path for the bus), the synchronization of the distributed multiplexers/demultiplexers associated with the input/output circuits is often very difficult. As a result, there is a need to provide systems and methods for providing synchronization of multiplexers/demultiplexers across input/output circuits of programmable logic devices.
USPTO Backgrounds
USPTO Backgrounds