1. Field of the Invention
The present invention relates generally to systems for supporting VUMA devices, and, more particularly, to a system for physically mapping a Row Address Strobe (RAS) signal from a VUMA device to an appropriate memory bank of a system memory.
2. Description of the Related Art
The Video Electronics Standards Association (VESA) has been active in promulgating various standards relating to computer architectures, and in particular, has investigated a Unified Memory Architecture. The concept of a VESA Unified Memory Architecture (VUMA) is to share physical system memory, for example one or more banks of dynamic random access memory (DRAM), between the system (e.g., a CPU), and an external device--a so-called VUMA device. Such a device could be any type of controller that has a need to share physical system memory, and in the course of such sharing, directly access it. For example, one type of VUMA device may be a graphics controller, wherein such graphics controller may incorporate its graphics frame buffer in physical system memory, thus eliminating the necessity for a separate graphics memory.
Memory sharing is achieved by physically connecting a core logic chip set (hereinafter "core logic"), and the VUMA device to the same physical system memory, either directly on a motherboard, or by way of an expansion connector. Since the core logic, and the VUMA device share a common resource, arbitration is required therebetween for controlled operation. For example, in one configuration, the core logic is the default owner of the physical system memory, such ownership being transferrable to the VUMA device upon demand according to a protocol.
The physical system memory may contain a memory block allocated primarily for the VUMA device (hereinafter referred to as "main VUMA memory"). Main VUMA memory is preferably located in an uppermost block of a memory bank. The VUMA device may be connected to the physical system memory to access main VUMA memory in one of two ways. First, the VUMA device may be connected to a single memory bank of physical system memory wherein the VUMA device generates a single VUMA row address strobe signal (VRAS#), which is hardwired to the selected memory bank. Secondly, the VUMA device may be configured to access all of physical system memory wherein the VUMA device has a sufficient number of RAS# signals to access all of the memory banks in the physical system memory. Preferably, main VUMA memory needs to be mapped at the top of existing physical system memory for any particular configuration.
For the VUMA device of the type which can access only one memory bank, a problem arises when physical system memory is expanded. In particular, for example, assume that an initial system configuration includes a single bank of memory having 8 MB of memory total, wherein one MB is allocated to main VUMA memory. In such a configuration, the VUMA device is hardwired to the single memory bank. Thus, main VUMA Memory occupies physical memory from addresses 7M to 8M-1. When physical system memory is expanded to, for example, 16 MB by adding a second memory bank of 8 MB memory, a "hole" in the physical system memory, as viewed by the operating system software, is created. That is to say, under such conditions, the operating system software has access to memory from 0M, to 7M-1, and, from 8M, to 16M-1; the operating system software is not permitted to access addresses 7M to 8M-1 since this 1 MB block has been reserved for, and is accessible by, the VUMA device. Operating system software has some difficulty in dealing with this "hole" (i.e., an address space that is non-contiguous) and this fact is the reason why main VUMA memory is preferably mapped to the top of existing physical system memory (i.e., to eliminate the "hole" seen by the operating system software, since all low memory will be contiguous).
Three solutions for this problem have been proposed. One solution suggests that main VUMA memory be mapped non-contiguously with respect to the operating system memory. In particular, core logic (e.g., typically a memory controller device) maps main VUMA memory to an address beyond core logic's possible physical system memory range. Hence, even if physical system memory is expanded to the maximum possible size, there will be no "hole" in the memory as seen by the operating system software. For example, in a system where physical system memory may be expanded only to 64 MB, core logic may map main VUMA memory from 1G to 1G+1M-1. This solution, however, requires a moderate amount of hardware modification to the memory controller, as well as moderate amount of modification to the basic input/output (BIOS). In addition, the method is not independent of SIMM density.
Another solution involves mapping main VUMA memory contiguously with operating system memory. In particular, core logic maps main VUMA memory to the top of the logical address space, although, in the physical system memory space, the main VUMA memory may occupy a middle region. For example, assume that a one-bank system of 8 MB is expanded to a 16 MB two-bank system. The main VUMA memory would be mapped to addresses 15M to 16M-1; however, physically, this memory occupies a region physically between 0.S. memory spaces. This solution, however, has several disadvantages, including a moderate amount of hardware modification to the memory controller, as well as intensive BIOS modifications.
A third solution involves swapping the memory bank which contains main VUMA memory originally with the uppermost bank then-existing after expansion. That is, core logic swaps the memory bank containing main VUMA memory to the top of the memory space. Thus, although main VUMA memory is mapped "contiguously" (e.g., it is at the top of the logical address space as seen by the operating system software, and contiguous to the operating system software memory space), the solution has several disadvantages including, requiring an intensive amount of memory controller hardware modification to perform the bank switching, as well as a moderate amount of BIOS modifications.
Accordingly, there is a need to provide an improved system for defining a memory space for a VUMA device that minimizes or eliminates one or more of the problems as set forth above.
USPTO Backgrounds
USPTO Backgrounds