The present invention relates to a storage control system for a computer adopting both a virtual storage system and a buffer storage system, and to a logic-in memory device used in the storage control system.
Recent large and middle scale computers generally include both a virtual storage system and a buffer storage system. With the virtual storage system, a programmer can perform coding without considering the size of a real storage in such a manner that he or she does not use a real address of a real storage but a logical address of a virtual storage. With the buffer storage system, a memory hierarchy is employed wherein a buffer storage of high speed and small capacity is provided between a central processing unit and a main storage so as to make the main storage of large capacity and low speed compatible with the system processing speed.
With the virtual storage system, it is necessary to translate a virtual address into a real address prior to reference to a main storage. Translating a virtual address into a real address is performed by referring to an address translation table in the main storage, the table having been prepared using a program. However, if the main storage is to be referred to each time the translation is performed, an overhead of address translation becomes large. In view of this, an address translation lookaside buffer (hereinafter called TLB) is provided which stores translation pairs of a virtual address and a real address obtained by once referring to the main memory. When the main memory is referred to, it is checked if a virtual address now concerned is present in the TLB or not. If present (this probability is very high because of a localized nature of a program), a corresponding real address can be obtained at high speed.
With the buffer storage system, the buffer storage copies a fraction of data stored in the main storage. In order to store such data correspondence, there is provided a buffer address array (hereinafter called BAA). When the central processing unit activates the system to refer to the main storage using a virtual address, it is checked if a corresponding real address translated by the TLB is present in the BAA. If present (this probability is very high because of the localized nature of a program), the necessary data is read from the buffer storage at high speed and sent to the central processing unit.
The reference to the TLB and BAA has been described as performed serially. However, it is necessary for a high speed processing to perform the reference in parallel. In this case, the BAA is referred to using a virtual address, more in particular, by a real address part (intra-page address) of the virtual address. The correspondence of data of the main storage and the buffer storage is expressed by using a so-called "block" generally constructed of 32 bytes or 64 bytes, so that the number of bits necessary for the reference to the BAA is 6 to 7 bits at most.
FIG. 1 is a block diagram showing an example of a buffer storage apparatus of the type in which both the TLB and BAA systems are referred to in parallel. Upon a memory request generated by the central processing unit, a virtual address is loaded in a register 1a. Entries of a TLB 2 are identified by the lower bits of the page address of the virtual address. In this example, the TLB 2 is constructed of k columns.times.2 rows, including a first row 2-1 and a second row 2-2. Namely, each of the first and second rows has k entries. Each entry of the rows 2-1 and 2-2 of the TLB 2 is constructed of a virtual or logical address part (L), a valid flag bit part (V) and a real address part (R). The contents of the L parts and V parts read from the rows of the TLB 2 are compared with the upper bits of the page address in the register 1a at the corresponding address comparators 4-1 and 4-2.
The entries of the BAA are identified by the upper bits of the intra-page address. In this example, a BAA 3 is constructed of l columns.times.2 rows, including a first row 3-1 and a second row 3-2. Each row has l entries. In the system wherein the TLB 2 and BAA 3 are referred to in parallel, the number l of columns of the BAA is determined on the basis of the block size of the buffer storage. Namely, assuming that the page size is 4 KB and the block size is 64 bytes, the number l of columns is 64. The number of rows is based on the buffer storage capacity. Each entry of the BAA 3 is constructed of a real address part (R) and a valid flag bit part (V). Real address comparators 6-1 and 6-2 compare the contents of the R parts of the BAA 3-1 and 3-2 with a real address (page address) read from the R part of the TLB 2-1 inputted to a selector 5 or a real address (page address) directly loaded from the central processing unit into the register 1a. The selector 5 selects the content of the register 1a when the central processing unit has directly loaded a real address in the register 1a, or selects the content of the TLB 2-1 when a virtual address has been loaded in the register 1a. Other real address comparators 7-1 and 7-2 compare real addresses read from the R parts of the TLB 2-2 with real addresses read from the R parts of the BAA 3-1 and 3-2. Each of the real address comparators 6-1, 6-2, 7-1 and 7-2 outputs "1" when two inputs become coincident.
The comparison results by the real address comparators 6-1, 6-2, 7-1 and 7-2 are inputted to an encoder 8 and selected based on the results of the virtual address comparators 4-1 and 4-2 and thereafter, the encoded output (one bit in this case) is stored in a register 9 at its upper portion and the intra-page address in the register 1a at its lower portion. Thus, a buffer storage address corresponding to a virtual address or a real address loaded in the register 1a can be obtained in the register 9. Using the address in the register 9, the buffer storage is accessed and the read-out data is transferred to the central processing unit.
The TLB 2 and BAA 3 must operate at high speed and also must have a certain capacity. Accordingly, they are commonly constructed of bipolar memories. A conventional bipolar memory used for such application is shown in FIG. 2.
Referring to FIG. 2, address signals applied to input pins A0 to A2 and A3 to A5 are decoded by an X address decoder 10 and a Y address decoder 14, respectively, and supplied to drivers 11 and 13 which in turn activate a memory cell 12. In this example, the memory cell 12 is constructed of 64 bits of 8 bits.times.8 bits. One bit selected from the memory cell 12 is supplied to an output circuit 16 via a sense amplifier 15 to thereby output read-out data at an output pin DO (data out). While a WE (write enable) signal is valid, a write mode is activated. In the write mode, data at an input pin DI (data in) of a gate 17 is supplied to AND gates 18 and 19 where it is subjected to an AND operation with a WE signal so that a write "1" or "0" signal is made valid at the output of the AND gate 18 or 19. The write "1" or "0" signal is written via a driver 13 into the memory cell 12 at an address designated by address signals A0 to A5.
The bipolar memory of this type is used as the TLB or BAA by arranging it in matrix configuration realizing a desired word length and bit width.
Large scaled and high speed computers have recently been realized due to the development and improvement of super high density LSIs. This tendency is considered to be enhanced further in the future. While most of logic units such as arithmetic units are implemented in the form of LSIs with high operating speed, the logic part containing a bipolar memory is mostly occupied by gates for distribution of address to bipolar memory cells and for selection of read-out data from bipolar memory cells, thereby resulting in difficulty in implementing such units in the form of LSIs and of utilizing the advantageous features of LSIs. Therefore, there is a high possibility that such a difficulty results in a critical path in the unit which limits machine cycles of a computer. In addition, there is a tendency that the capacity of a main storage also increases so that the capacity of a buffer storage is required to be increased, i.e., the capacity of a BAA is required to be increased. In the meantime, it is now possible to realize a high speed 4K bit memory due to the advance of high integration of a bipolar memory. However, since the available number of columns of a BAA in the TLB and BAA parallel reference system is 6 to 7 bits at most as described before, it becomes necessary to increase the number of bits for high integration of a bipolar memory. However, if a BAA of large capacity is implemented using a bipolar memory having the configuration as discussed with FIG. 2, the number of package pins of the bipolar memory increases considerably so that it is hard to easily realize it.
For example, if a 4K bit memory is constructed of 64 words, it is possible to use 64 bits. However, in this case, the number of necessary pins becomes 140 for both the address and data lines. Thus, the package size of a bipolar memory is restricted by the number of input/output pins.
The Japanese Patent Publication No. JP-B-57-57784 discloses and apparatus which uses a TLB and a BAA constructed of a memory chip with a comparator included therein. The above described restriction is intended to be solved by including in a memory chip the portion encircled by a broken line in FIG. 1, for example. U.S. Pat. No. 4,332,010 also discloses a memory chip with a comparator included therein.
According to the JP-B-57-57784, a real address read from a TLB is temporarily outputted from the memory chip having the TLB and inputted to a memory chip having a BAA to be compared with a real address read by the BAA. Therefore, there is a problem that the number of pins necessary for the input/output with respect to the TLB and BAA, and a propagation delay are increased.
USPTO Backgrounds
USPTO Backgrounds