The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrinking the process node towards the sub-20 nm node). As device dimensions shrink, voltage nodes also shrink, with modern core device voltages trending toward less than 1 Volt, and input/output (I/O) device voltages under 2 Volts.
Many types of analog, digital and mixed-signal circuits rely on tuning networks to achieve fine granularity in performance metrics, such as gain, bandwidth, center frequency, oscillation frequency, and the like. The tuning networks are often designed with a view to increase resolution while maintaining or shrinking area and also guarding against process, voltage, and temperature (PVT) variation.
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USPTO Backgrounds