Heretofore, electroless plating of tin or tin-lead alloy has been practiced for the purpose of improving soldability of copper or copper alloy conductors that form circuits on electronic parts such as printed wiring boards. In order to meet the general demand on electronic equipment for size reduction, parts and circuits are reduced in size or increased in complexity, leaving some areas which are restrained from plating by electrodeposition techniques. Particular attention is paid to tin or tin-lead alloy electroless plating techniques which can provide plating on such restricted areas. For example, Japanese Patent Application Kokai No. 184279/1989 discloses a tin or tin-lead alloy electroless plating bath mainly containing an organic sulfonic acid, tin and lead salts of an organic sulfonic acid, sodium hypophosphite as a reducing agent, and thiourea as a chelating agent.
On the other hand, the electronic part packaging technology such as for IC packages is now shifting from the vertical mount technique (VMT) of DIP type packages to the surface mount technique (SMT) of flat packages. Accordingly, printed wiring boards are required to have a smooth surface which is to come in contact with products to be packaged such as IC packages, that is, to have a tin or tin-lead alloy coating of high uniformity deposited thereon.
However, prior art tin or tin-lead alloy electroless plating baths form deposits which consist of coarse grains and are less uniform and therefore, poor in reflow and solder-availability. It is thus difficult for such baths to plate fine pitch printed wiring boards intended for SMT.
USPTO Backgrounds
USPTO Backgrounds