1. Technical Field
The present invention relates to semiconductor processing and more particularly to fabrication of components with density multiplication in a single process sequence.
2. Description of the Related Art
Vertically disposed transistors formed on fins or fin field effect transistors (FinFETs) have been emerging as a promising new approach for continued scaling of complementary metal oxide semiconductor (CMOS) technology. Sidewall spacer imaging transfer (SIT) is one method for forming narrow fins beyond the printing capability of optical lithography. Conventional SIT methods result in a pattern density that is finer than conventional lithographic patterning techniques. However, as demand grows for increased semiconductor component density, improvements to conventional SIT methods are needed.
In prior art processes, pattern density can be doubled by conventional sidewall imaging transfer (SIT) as described in U.S. Pat. No. 6,391,753. Another method includes performing the SIT process multiple times. While this can further increase pattern density, multiple SIT processes adds process complexity and increases process cost. For example, pattern density can be quadrupled by performing the SIT process two times, as described, e.g., in U.S. Pat. No. 6,875,703.
USPTO Backgrounds
USPTO Backgrounds