(1) Field of the Invention
The present invention relates to solid-state imaging devices, and particularly to a solid-state imaging device including a substrate contact and to a camera including the solid-state imaging device.
(2) Description of the Related Art
Charge Coupled Device (CCD) solid-state imaging devices and Metal Oxide Silicon (MOS) solid-state imaging devices are widely available as imaging devices for a digital still camera, a digital movie camera, and the like. Among such devices, each of the MOS solid-state imaging devices includes, on a single semiconductor substrate, an imaging region made up of imaging pixels and a peripheral circuit region that obtains a signal from each of the imaging pixels included in this imaging region.
Here, a conventional solid-state imaging device is to be described with reference to FIG. 1. FIG. 1 illustrates an entire structure of the solid-state imaging device having the conventional substrate contact which is described in Japanese Unexamined Patent Application Publication No. 2001-230400. This solid-state imaging device has a p-type common well formed on an n-type semiconductor substrate, and on this common well, a pixel array area PXA including pixels PXL that are two-dimensionally arranged and a peripheral portion PP in which a circuit for driving and the like is arranged are formed.
Each of the pixels PXL includes, on the semiconductor substrate, a photodiode 1, a p+ type semiconductor region 2, a transistor, and the like, and further, a substrate contact 3. The peripheral portion PP includes a p+ type semiconductor region 2′ and a substrate contact 3′. The substrate contacts 3 and 3′ are electrically connected to the p+ semiconductor regions 2 and 2′, respectively.
Here, the reason why the substrate contact 3 is formed is to be described. Under transistors within a pixel PXL, the aforementioned p-type common well is formed so as to control a threshold of the transistors, and is connected to a base voltage (normally, 0V) so as to keep the voltage constant. However, in order to read an output signal from each of the pixels PXL, when turning amplifying transistors on and off in order, a potential of the common well varies with the capacitive coupling of the common well and a gate electrode of a selected transistor. Then, it takes finite lengths of time to reset the varying potential of the common well to the base potential. In the case where the substrate contact 3 is not formed within the pixel array area, since it is necessary to wait until the potential of the common well is reset to the base potential (0V) for operating the next-selected transistor, it becomes difficult to perform a high speed operation. In order to prevent such situation, conventionally, the substrate contact 3 is formed within the pixel array, and is connected to a wiring that connects to the base voltage. With this, it becomes possible to substantially reduce the time until the varying potential of the p-type common well is reset to the base potential.
However, there is a problem that a sensitivity difference among photodiodes each located in a different position occurs due to the pixel structure of the solid-state imaging device having the aforementioned substrate contact 3 within the pixel array area.
Using FIGS. 2 and 3A to 3C, the problem is to be described. FIG. 2 illustrates an example of a solid-state imaging device in which the sensitivity difference occurs among adjacent photodiodes.
The diagram illustrates an example of a case where a solid-state imaging device is composed of four pixels in one cell, in other words, a pair of an amplifying transistor and a reset transistor is arranged per four photodiodes 1. Furthermore, the diagram illustrates a part of the structure of the solid-state imaging device including: a photodiode 1; a gate 11 of an amplifying transistor; a source region 5 of the amplifying transistor; a gate 10 of a reset transistor; a source region 7 of the reset transistor; a drain region 6 common to the amplifying transistor and the reset transistor; a power voltage contact 17 which is connected to a power voltage wiring 12 and the drain region 6 and which supplies a power voltage to the pair of the amplifying transistor and the reset transistor; a gate 8 of a transfer transistor; a detection capacitance unit (floating diffusion layer) 9; a p+ type region 2; and a substrate contact 3.
There is a problem that the sensitivity difference occurs between the photodiode 1 that is the second (or third) one from the top and the photodiode 1 that is the fourth (or fifth) one from the top in the diagram.
This problem is described using FIGS. 3A to 3C. FIGS. 3A and 3B illustrate cross-sectional views of the photodiode 1 when an amplifying transistor or a reset transistor is adjacent to both sides of the photodiode 1. Although in FIG. 2, the power voltage contact 17 and the substrate contact 3 are not arranged on the same section including the photodiode 1, they are arranged on the same section in FIGS. 3A and 3C for the convenience of the description.
As illustrated in FIG. 3A, a collecting lens is placed above the photodiode 1. Then, incident light is collected onto the photodiode 1 through the collecting lens.
However, there are cases where incident light enters an element isolation unit 18 or the n+ type source region 7 (or 5), but does not enter the photodiode. When incident light enters the element isolation unit 18 or an n+ type source region, electrons are generated with a photoelectric conversion effect. A power voltage (normally, approximately 2 to 5 positive voltages) is applied to the n+ type source region 7 (or 5) for driving a transistor, and the generated electrons move to the power voltage side. For this reason, the electrons do not move to the photodiode side. In this case, the sensitivity of an adjacent photodiode 1 is not degraded.
As illustrated in FIG. 3C, when the photodiode 1 is adjacent to the p+ type regions 2 and incident light enters the element isolation unit 18 or the p+ type region 2, similarly, electrons are generated. The substrate contact 3 is formed on the p+ type region 2, and normally, the voltage is maintained at 0 voltage. Thus, the generated electrons move mainly to the photodiode 1, but not to the substrate contact 3. In this case, the sensitivity of the adjacent photodiode 1 is degraded.
Thus, in the conventional solid-state imaging device, a sensitivity difference (1 to 5%) occurs between a photodiode adjacent to an n-type region and a photodiode adjacent to a p-type region. In other words, sensitivity properties of photodiodes become different depending on a conductivity type in a semiconductor region adjacent to the photodiode. Accordingly, there is a problem that sensitivity inconsistency in an imaging area occurs.
The present invention has been conceived in view of the aforementioned problem, and the object is to provide the solid-state imaging device that includes a substrate contact and that reduces the sensitivity inconsistency between photodiodes and the sensitivity inconsistency in an imaging area.
USPTO Backgrounds
USPTO Backgrounds