1. Field of the Invention
The invention relates to a manufacturing method for semiconductor device having metal gate, and more particularly, to a manufacturing method for semiconductor device having metal gate integrated with the gate last process and the high-k last process.
2. Description of the Prior Art
With a trend toward scaling down the size of the semiconductor device, work function metals are used to replace the conventional polysilicon gate to be the control electrode that competent to the high dielectric constant (hereinafter abbreviated as high-K) gate dielectric layer. The conventional dual metal gate methods are categorized into the gate first process and the gate last process. Among the two main processes, the gate last process is able to avoid processes of high thermal budget and to provide wider material choices for the high-K gate dielectric layer and the metal gate, and thus gradually replaces the gate first process.
In the conventional gate last process, a dummy gate or a replacement gate is formed on a substrate and followed by steps of forming a conventional metal-oxide semiconductor (MOS) transistor device. Subsequently, the dummy/replacement gate is removed to form a gate trench. Then the gate trench is filled with work function metals required by different conductivity types. However, each layer formed in the gate trenches reduces an opening width of the gate trench by forming overhangs. The overhang problem makes it difficult to fill the gate trench with the other material. Serious overhang problem even results in a seam in the gate trench and makes the filling metal layer cannot be formed in the gate trench as desired. Eventually, the electrical performance of the transistor device having the metal gate is deteriorated.
Accordingly, though the gate last process is able to avoid processes of high thermal budget and to provide more material choices for the high-K gate dielectric layer and the metal gate, the gate last process still faces integrity requirements for the complicated processes and reliability requirement for the layers filling in the gate trench.
USPTO Backgrounds
USPTO Backgrounds