1. Field of the Invention
The present invention relates in general to a video motion compensation circuit for a high definition television (HDTV), and more particularly to a video motion compensation circuit which is capable of compensating simply for video data by a detected amount of video motion and real time-processing a large amount of video data.
2. Description of the Prior Art
A video motion compensation technique is to reduce an amount of video data using a video motion vector detected at an encoder stage, for reproduction of a video signal with a better picture quality.
A conventional video motion compensation circuit used in such a video motion compensation technique is shown in a block form in FIG. 1. As shown in this drawing, the conventional video motion compensation circuit comprises a frame memory address generator 1, an address controller 2, frame memories 3 and 3', an adder 5, a data input/output (I/O) controller 4 and a clock generator/counter 6.
In operation, the address generator 1 generates an address signal to one of the frame memories 3 and 3' to be read, in response to video motion vector X and Y signals from an encoder section (not shown) and a position signal regarding a basic block. The address controller 2 addresses one of the frame memories 3 and 3' in response to the address signal from the address generator 1. The data I/O controller 4 controls data input and output of the addressed one of the frame memories 3 and 3'. At this time, the counter 6 is controlled based on a size of the basic block to vary the address signal of the address generator 1 by an amount of video motion. The addressed one of the frame memories 3 and 3' is sequentially accessed pixel by pixel and the resultant data therefrom is added to decoded reproduction video data IT in the adder 5. Then, the added data from the adder 5 is stored in the other frame memory 3 or 3' under the control of the data input/output controller 4. An address to one of the frame memories 3 and 3' to be written can be generated on the basis of only a predetermined block position.
The above-mentioned conventional video motion compensation circuit has no problem in theory; however, it has a practical problem of requiring a system of clock of 60 MHz or more in a system hardware to real time-process a large amount of video data since the large amount of video data is processed in the unit of pixel. Namely, the use of such a high frequency system clock makes the selection of components difficult, makes the system instable and results in a limit to an availability of a clock frequency provided by an erasable programmable logic device (EPLD) being widely used now. The limit to the availability of the clock frequency restricts the use of the EPLD.
USPTO Backgrounds
USPTO Backgrounds