Testing of integrated circuits has long been known in the art. Presently, testing techniques are in widespread use for nearly all types of integrated circuits ranging from those implemented in household toys and appliances to sophisticated supercomputers. As a result, the testing of integrated circuits forms an important part of the manufacturing process for most integrated circuits in use today.
These testing techniques have been developed in a wide variety of electronic manufacturing and circuit design configurations, depending upon the intended need at the implementation site. One form of testing of integrated circuits in use today is known as Logic Built-In Self Test (LBIST). Generally, LBIST is a technique that is used to test an integrated circuit such as an Application Specific Integrated Circuit (ASIC) by a test logic sub-circuit that is built into an overall circuit design. In LBIST, test vectors are generated by a Pseudo-Random Pattern Generator (PRPG), such as the LBIST Architect tool from Mentor Graphics of Wilsonville, Oreg., on an integrated circuit and the responses from the ASIC are compressed by a Multiple Input Shift Register (MISR) to form a “signature”. The signature in the MISR will then be compared with a predetermined signature generally referred to as a “golden signature” to determine if there are any defects in the ASIC.
This technique has the benefits of: 1) improving test quality by performing at-speed testing; 2) reducing manufacturing test costs by reducing tester usage time, tester memory requirements and the required number of tester input/output connections; and 3) reducing system test, diagnosis and repair costs by performing ASIC testing on board the ASIC. The technique, however, also has several disadvantages, including: 1) design hardware overhead due to the test logic inserted into the ASIC; and 2) extra design efforts due to the design complexity introduced. While the design hardware overhead is often negligible compared to design sizes and the silicon technologies used today, the extra design effort poses a significant obstacle to the implementation and usage of LBIST techniques.
Generally, one of the most significant obstacles in LBIST design is timing closure, arising from timing violations introduced by inserting the LBIST circuitry into the ASIC. The main timing violations introduced by LBIST are due to: 1) test point insertions; 2) x-bounding logic insertions; and 3) multi-cycle paths.
The test point insertion timing violations result when test points are inserted into circuit paths, such as for control and observation purposes. Due to the use of the pseudo-random pattern generator, random resistant logic in a design can be very difficult to test, making high test coverage technically and economically impractical. As stated above, these test point insertions can introduce functional path timing violations.
The second type of timing violation in LBIST design is caused by x-bounding logic. The nature of signature compression using a MISR requires that no unknown “X” values should be propagated into the MISR, otherwise the signature will be corrupted. Generally, “X” values are introduced by floating nets in a design, latches, non scannable flip-flops, external inputs which are not controlled on a tester (such as Credence QUARTET and Credence DUO available from Credence Systems Corporation of Fremont, Calif., and Teradyne J750 and Teradyne Catalyst 400 available from Teradyne, Inc. of Boston, Mass.) or system board, memories which are treated as black boxes and buses where contentions could happen. The x-bounding logic is used to block the “X” value propagation, however, the x-bounding logic could adversely affect design timing and, in many designs, timing budgets for memory accesses and I/O are often very tight.
Another type of timing violation in LBIST design is related to design false paths and multi-cycle paths. In functional mode, the switch of timing analysis for these paths is turned off. In other words, even though there are timing violations in these paths, they are ignored during the functional mode timing analysis. In test mode, however, all paths in the design need to be tested, and therefore their timing should be considered. In normal scan design, this is generally not a significant problem because the test clock frequencies are very slow. In LBIST design however, the test clock frequencies are at or close to the functional clock frequencies of the integrated circuit and can therefor cause timing violations.
A practical issue in LBIST design is the fault coverage that can be achieved. Fault coverage is often limited due to the pseudo-random test vectors used. Currently, several approaches have been used to alleviate this situation. One approach is to insert more test points to achieve full testability. As described above, test point insertion can affect design timing. Another approach is to increase the number of pseudo-random vectors to be used. This approach, however is limited to situations when the tester cost is not an issue. In many cases, however, tester cost is of significant concern. Thus, using current techniques, a trade-off must be made in order to achieve optimal results with limited resources.
Presently, the foregoing practical issues have not been fully addressed in the existing art. One current approach is to minimize the number of test points to be inserted in order to reduce the number of timing violations caused by test points. A disadvantage of this approach is that there is no guarantee that all of the timing violations caused by test points will be resolved.
Another existing approach addresses the x-bounding timing violations by suppressing the clock to avoid capturing “X” values that will propagate into the MISR. Unfortunately, adding logic to clock trees to suppress capturing will increase clock tree skew. Yet another approach attempts to provide a solution to multi-cycle path timing problems, based on a list of multi-cycle paths and the information on the number of cycles for each multi-cycle path to disable the capturing of “X” values. Under this approach, by suppressing the capture of a transmitting flip-flop, the transmitting flip-flop holds its previous state for an extra number of cycles to allow the receiving flip-flop to capture data safely. When the transmitting flip-flop performs the capture, the capture of the receiving flip-flop will be suppressed so that there is no potential for a hold-time violation. Although this approach can achieve full coverage of a circuit, it is not without its shortcomings. First, the multiplexer added in the front of the transmitting flip-flops could cause its own timing problems. Second, as a practical matter it is very hard to obtain the multi-cycle paths and their multi-cycle number information. In many cases, ASIC designers use a very simplified approach to specify the paths that can be ignored by for example setting all paths from a clock domain A to a clock domain B to false paths. Under this approach, however, it is very hard to obtain the multi-cycle paths and their multi-cycle number information because of the generally large number of specified paths involved. In addition, prior to manufacturing a circuit, circuit layout mapping processes, such as Place and Route processes, are generally used to determine the efficient positioning and connection paths of circuit components. These processes can also introduce additional timing violations that cause an undesirable signature mismatch between the signature in the MISR and the golden signature.
The present invention introduces a technique based on timing analyses to resolve timing problems efficiently so that extra design efforts introduced by using LBIST can be reduced or eliminated.
USPTO Backgrounds
USPTO Backgrounds