Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as a layout editor, to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. The EDA layout editing tools are often performed interactively so that the designer can review and provide careful control over the details of the electronic design.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. The task of all routers is the same—routers are given some pre-existing polygons consisting of pins on cells and optionally some pre-routes from the placers to create geometries so that all pins assigned to same nets are connected by wires and vias, that all wires and vias assigned to different nets do not overlap, and that all design rules are obeyed. That is, a router fails when two pins on the same net that should be connected are open, when two pins on two different nets that should remain open are shorted, or when some design rules are violated during routing.
A layout file is created from the placement and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. The layout data set is stored, for example in GDSII (“Graphic Data System II”) or OASIS (“Open Artwork System Interchange Standard”) formats. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process.
Reducing critical areas and improving yield and performance of electronic design have been some of the ultimate goals and hence challenges in electronic designs. Traditional approaches include various or even iterative analyses (e.g., timing analysis) and repetitive applications multiple DFM (design for manufacturing) techniques at various stages of the electronic design flow. Some traditional approaches further use forward as well as backward annotation techniques to move back and forth between different domains (e.g., schematic domain and physical domain) to communicate various performance characteristics (e.g., timing characteristics) or DFM characteristics. These approaches may also invoke an iterative process to repetitively solve at least a portion of the electronic design of interest multiple times in different domains while hoping to obtain an improved yield or performance characteristics.
Some traditional approaches use a switch box by partitioning an electronic design into a fixed number of switch boxes in each routing direction. For example, these traditional design may subdivide an electronic design into 100 switch boxes in each routing direction and hence have 10,000 switch boxes (100×100) for the electronic design or even 10,000 switch boxes for each routing layer of an electronic design. These approaches may route the electronic design and perform wire spreading by individually examining and processing each switch box. Nonetheless, in these switch-box approaches, the points where interconnects cross the boundaries of switch boxes remain fixed and cannot be moved. As a result, these switch-box approaches necessitate much more jogs due to these fixed points on the boundaries of the switch boxes.
Thus, there exists a need for methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques.
USPTO Backgrounds
USPTO Backgrounds