1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device with a silicide layer in a gate electrode and a method for manufacturing the same.
2. Description of the Related Art
In recent years, with demand for high integration and miniaturization of semiconductor devices, gate electrodes are also getting smaller. In this case, a technology for silicidizing a gate electrode made of polycrystalline silicon is in wide use as a technique for decreasing the resistance value of the gate electrode to enable high-speed operation.
(Patent Document 1)
Japanese Patent Laid-open No. Hei 10-209296
(Patent Document 2)
Japanese Patent Laid-open No. Hei 7-37992
However, further progress made in miniaturization of semiconductor devices causes various problems when a gate electrode is silicidized in producing a CMOS transistor, as described below, due to a polycrystalline silicon film in which a silicide layer is to be formed.
One of the problems is that a gate electrode made of polycrystalline silicon film formed smaller in width accompanying miniaturization of the semiconductor device causes a so-called thin wire effect in which the resistance value of a high melting point metal silicide layer to be formed on the gate electrode increases. For example, FIG. 12 shows a characteristic chart of the resistance value of a cobalt silicide layer (CoSi2 layer) when formed on a gate electrode. This chart shows that when the width of the gate electrode is about 0.1 μm or less, the resistance value sharply increases, thus prominently showing the thin wire effect.
Another problem is that projections and depressions on an interface between the silicide layer formed on the gate electrode and the polycrystalline silicon film cause the silicide layer to contract upon application of a stress such as heat treatment or the like, thus increasing variations in the resistance value of the silicide layer. Still another problem is that when a silicide layer is locally excessively formed on the gate electrode, a stress is generated in polycrystal in a base film to cause deterioration of a gate insulation film.
USPTO Backgrounds
USPTO Backgrounds