As a memory device for storing data or program-configured data, attention has recently been focused on a flash EEPROM (hereinafter called a “flash memory”), which is defined as a nonvolatile memory device that is capable of electrically erasing data that is stored in predetermined units in batch form and of electrically writing data. In a flash memory, each memory cell is made up of an electrically erasable and programmable nonvolatile memory element. The flash memory is capable of erasing data that is temporarily written into a corresponding memory cell or program-configured data and of rewriting (programming) new data or program-configured data into the corresponding memory cell.
The storage of an electrical charge in a flash memory has heretofore been performed by storing or accumulating electrons in a floating gate comprising a polysilicon film and which is electrically isolated from the surroundings. Such a conventional memory cell has been called a “floating gate type flash”. The injection of hot electrons has generally been used as such an electron storage operation, i.e., a so-called write operation. The operation of discharging accumulated electrons out of the floating gate has been performed by a tunneling current which passes through a gate oxide film. When writing and erasure are repeated, a charge trap is formed inside the gate oxide film, and the surface level or state density increases at an interface between the substrate and the gate oxide film. In particular, the former has an essential problem in that the charge retention characteristic, i.e., the post-writing retention characteristic, is degraded.
As a method of resolving such a problem, a memory cell system has recently been proposed which makes use of a nonconductive charge trap film for the purpose of charge storage of the EEPROM. This has been disclosed in, for example, U.S. Pat. No. 5,768,192, U.S. Pat. No. 5,966,603, U.S. Pat. No. 6,011,725, U.S. Pat. No. 6,180,538, and B. Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cell”, International Conference on Solid State Devices and Materials, Tokyo, 1999.
U.S. Pat. No. 5,768,192 has disclosed, for example, a system wherein, as shown in FIG. 58, a silicon nitride film 183 is interposed between insulating films 182 and 184, such as a silicon oxide film, etc., whereby a so-called laminated film having an ONO (Oxide/Nitride/Oxide) structure is used as a gate insulating film. In this first conventional memory cell 0V is applied to a source 187, 5V is applied to a drain 186 and 9V is applied to a control gate 185, so as to turn on the transistor, thereby injecting hot electrons developed in the neighborhood of the drain 186 and trapping them into the silicon nitride film 183, whereby writing is performed.
As compared with a system for effecting charge storage on a polysilicon film corresponding to a continuous conductive film, a charge storage system such as provided by the conventional first memory cell is characterized in that, since the trapping of electrons into the silicon nitride film 183 is noncontiguous and discrete, all of the stored charges do not disappear, even where charge leakage passes, such as via pin holes or the like that occur in part of the oxide film 182, and the retention characteristic is essentially strong. An erase operation of such a memory cell is performed by, as shown in FIG. 59, applying 3V, 5V and −3V to the source 187, drain 186 and control gate 185, respectively, to forcibly reverse the neighborhood of the drain 186 on the silicon surface side and inject hot holes, that are generated by a band-to-band tunnel phenomenon caused by an energy band that is significantly deformed by a strong electric field, into the silicon nitride film 183, to thereby neutralize the already-trapped electrons.
U.S. Pat. No. 5,408,115 and U.S. Pat. No. 5,969,383, respectively, have disclosed a memory cell system which has a split gate using side spacers, in which charge storage is effected on an ONO film serving as a memory cell structure. A write/erase system embodying this technique is shown in FIGS. 60 and 61. In this conventional second memory cell, as shown in FIG. 60, a select gate 163 is disposed on a gate oxide film 162 which is formed on the surface of a substrate 161, and lower oxide films 165, silicon nitride films 166 and upper oxide films 167 are laminated at a peripheral portion of the select gate 163, followed by provision of side spacer-shaped control gates 168. Since the source 164 of this conventional second memory cell is formed immediately after the processing of the select gate 163, and the drain 169 is formed after the processing of the control gates 168, only the control gate 168 on the drain 169 side functions as a gate electrode.
A write operation for the conventional second memory cell, as shown in FIG. 60, is performed by applying 5V, 1V and 10V to the corresponding drain 169, select gate 163 and control gate 168, respectively, to turn on a channel and accelerate electrons travelling from the source 165 within a strong lateral electric field produced in a channel region disposed below the boundary between the select gate 163 and the control gate 168, so as to bring them to a hot electron state, and the hot electrons are caused to pass through the lower oxide film 165, from which they are injected and trapped into the silicon nitride film 167. Since the injection positions of the hot electrons are not located in the neighborhood of the drain, this operation is generally called a “source side injection (SSI) system”. An erase operation for this conventional second memory cell, as shown in FIG. 61, is performed by applying 14V to only the corresponding control gate 168, to thereby draw electrons that are trapped into the corresponding silicon nitride film 166 into the control gate 168 as a tunneling current flowing into the upper oxide film 167. Since the injection of electrons from the substrate 161 also occurs due to a tunneling current flowing via the lower oxide film 165 during the erase operation, there is a need to form the lower oxide film 165 to that it is thicker than the upper oxide film 167.
Further, in a read operation for the conventional second memory cell, as shown in FIG. 62, 2V and 5V are respectively applied to the corresponding drain 169 and select gate 163 so as to turn on the channel, and 2V is applied to the corresponding control gate 168, to thereby determine the high or low level of a threshold voltage, based on the presence or absence of the electrons trapped into the silicon nitride film, from the magnitude of the drain current. As compared with the conventional first memory cell of FIGS. 58 and 59, the conventional second memory cell of FIGS. 60-62 has the advantage of reducing the drain current necessary for the write operation and achieving a reduction in power. This is because, since the conventional second memory cell is provided with the select gate 163, the channel current at the time of writing can be controlled so that it is low. The channel current can be reduced to 1/100 or less of that for the conventional first memory cell.
Furthermore, U.S. Pat. No. 5,408,115 has disclosed a conventional third memory cell, whose structure is shown in FIG. 63. The conventional third memory cell has a structure in which the structural positions of the select and control gates employed in the conventional second memory cell are changed. In the conventional third memory cell, a control gate 175 is formed above a lamination consisting of a lower oxide film 172, a silicon nitride film 173 and an upper oxide film 174, and, thereafter, gate oxide films 177 and side spacer-shaped select gates 178 are formed. The voltages that are set to effect write, erase and read operations of the present conventional third memory cell are similar to those of the conventional second memory cell.
A conventional fourth memory cell system, whose sectional views are shown in FIGS. 64 and 65, has been disclosed in I. Fujiwara, et al., “High Speed program/erase sub 100 nm MONOS memory”, Nonvolatile Semiconductor Memory Workshop, August, 2001, p75. As shown in FIG. 64, an ONO (Oxide/Nitride/Oxide) laminated film, comprising a silicon nitride film 193 interposed between insulating films 192 and 194, such as silicon oxide films, etc., is formed as a gate insulating film, and 12V is applied to a control gate 195 to inject electrons from the semiconductor substrate 191 side by a tunneling current and trap them into the silicon nitride film 193, thereby performing an erase operation that is brought into a high threshold voltage state. 6V is applied to a source 197 and a drain 196, and −6V is applied to the control gate 195 to forcibly reverse a silicon surface near a source/drain and inject hot holes, that are developed by a band-to-band tunneling phenomenon caused by an energy band that is greatly deformed by a strong field into the silicon nitride film 193, so as to neutralize the already-trapped electrons, thereby performing a write operation that is brought into a low threshold voltage state.
USPTO Backgrounds
USPTO Backgrounds