The present invention is directed to semiconductor devices in general, and more particularly, anti-reflective coating (ARCs) used within the gate stack of modern metal oxide semiconductor (MOS) transistor structures having a metallic gate electrode.
In modern semiconductor device manufacturing, a plurality of layers are generally deposited on a semiconducting substrate, that is typically made of silicon. These layers are then patterned and etched by photolithography and etch techniques to form a gate electrode stack. Generally, the gate electrode stack includes a gate dielectric overlying a substrate channel region, a polysilicon (poly) gate layer overlying the gate dielectric, and an anti-reflective coating (ARC) layer overlying the gate layer which is typically silicon nitride. Following deposition of these three basic layers (i.e., gate dielectric, gate electrode, and ARC), a photoresist layer is spun onto the substrate over the top of the ARC layer. The photoresist is then selectively exposed to light through a lithographic mask to form exposed and unexposed regions of the photoresist. The exposed photoresist regions are then developed and removed from the substrate, thereby exposing top portions of the ARC layer. The exposed portions of the ARC layer are then exposed to an etch process which removes portions of the ARC layer, then removes portions the gate layer, and/or finally removes portions of the gate dielectric. This removal defines the gate stack structure.
The ARC layer is generally deposited to prevent unwanted reflection of radiation/energy (e.g., I-line, deep ultraviolet (DUV) radiation, and G-line radiation) from the gate stack, back into the photoresist. This undesirable reflection results in unwanted exposure of some portions of the photoresist and/or lack of proper exposure of the photoresist. Improper exposure and subsequent removal of improperly-exposed portions of the photoresist negatively impact the critical dimensions (CD) of the semiconductor devices (e.g., one important CD is the gate electrode width, which is critical to MOS device performance, and may be less controllable without an ARC layer). In addition, the reflections greatly reduce the lithographic exposure latitude which is undesirable.
In order to reduce the magnitude of these problems, anti-reflective coating (ARC) layers were developed for MOS manufacturing. Several different ARC layers have typically been used in order to prevent or largely suppress unwanted reflection of the energy during photoresist exposure. ARC layers such as silicon nitride, silicon oxynitride, silicon-rich silicon nitride, and silicon-rich silicon oxynitride, have been used as an ARC layer in connection with polysilicon MOS gate structures. While such ARC layers have been largely successful in suppressing unwanted reflection in polysilicon gate structures, problems have been encountered with the use of these known ARC materials. The problems include high stress associated with the ARC layers, poor adhesion between the ARC layer and gate electrodes, and the need for high deposition temperatures which is generally undesirable in the IC industry. The relatively high stress and low adhesion of the ARC layer results in peeling or delamination of the ARC layer from the poly gate layer, which substantially impacts device yield. In an attempt to improve device yield, it is generally desirable to put an adhesive "glue" layer between the ARC layer and the polysilicon gate layer which increases process complexity, reduces wafer throughput and IC time to market, and may adversely increase gate resistance.
As modern semiconductor manufacturing moves toward use of metal gate layers rather than polysilicon gate layers, problems with efficacy and integration of silicon nitride, silicon oxynitride, and like ARC layers become even more pronounced. Indeed, it has been found that the conventional silicon nitride and silicon oxynitride groups of materials cannot adhere properly to metal gates, such as TaN, TiN, or W.sub.2 N, and may adversely chemically interact with the underlying polysilicon material.
Accordingly, it is quite clear that a need exists in the art for ARC layers that are more compatible with metallic MOS gates. These new ARC layers should have one or more of reduced stress levels, improved adhesion, lower deposition temperatures, as well as adequate anti-reflective properties.
USPTO Backgrounds
USPTO Backgrounds