In the pursuit of low-power information processing hardware, many new post-complementary metal-oxide-semiconductor (CMOS) transistors have been created in the past few decades. One desirable property for these new devices is a large on-current to off-current ratio, which enables low-power, low-voltage operation. Initial studies and experiments on a class of emerging field effect transistor (FET) technologies that operate upon the principle of tunneling between 2-D materials have indicated their potential for low-power operation. However, current-voltage characteristics (or “I-V curves”) of these devices appear to be dissimilar to those of today's metal-oxide-semiconductor field-effect transistors (MOSFETs), and instead exhibit bell-curve characteristics. Further, double-layer graphene transistors, such as SymFETs, and bilayer pseudo-spin FETs (BiSFETs) may all possess at least some of the aforementioned characteristics. Such behavior is also observed in some molecular transistors and single-electron transistors. To date, though, little if any work has considered how such devices might be employed for the purposes of digital logic, which will ultimately help to determine the “fate” of these new device technologies. For example, scientists have not yet described how to leverage the use of SymFETs in sequential circuits. Therefore, it is both important and desirable to utilize new SymFET-based devices that are superior to CMOS designs with regards to compactness, speed, and/or energy efficiency.
Until now, little has been done in the way of designing circuits comprised of SymFETs and other devices with similar graphene-insulator-graphene structures. New topologies involving such devices can benefit from unique I-V curves. Known attempts to incorporate graphene-insulator-graphene structures to date have not proven helpful. For example, one recent gate design uses BiSFETs at a supply voltage of 25 millivolts (mV), but a 25 mV supply is likely to prove challenging when considering supply, substrate, and device noises, where, in practice, the ripple on supply rails often amounts to a few tens of mV. On the other hand, some researchers have proposed a static random-access memory (SRAM) cell without access transistors. Due to the negative differential resistance (NDR) of that device, the circuit is bistable while having only two transistors as opposed to four in a similar CMOS SRAM cell.
Therefore, a need exists for several new Boolean gates that are practical and take advantage of unique I-V curves. Even simple gates, such as an inverter, for example, exhibit new properties (i.e., hysteresis) when realized by way of SymFETs. The present disclosure concerns several new circuits with a topology different from those of popular CMOS designs. To quantify the performance of these new SymFET-based gates and determine their potential benefits, the present disclosure benchmarks these gates against existing CMOS-functional equivalents. The present disclosure also examines the relationship between SymFET and resonant tunneling diodes (RTDs) to verify the feasibility of adopting RTD-based circuits. In turn, the present disclosure will aid in developing new circuits with other SymFET-like transistors and also assist in improving future transistors.
USPTO Backgrounds
USPTO Backgrounds