1. Field of the Invention
This invention relates to distortion and smoothness of nitride semiconductor wafers which can be utilized as a substrate wafer for making blue light emitting devices (laser diodes (LDs) or light emitting diodes (LEDs)).
This application claims the priority of Japanese Patent Application No. 2003-128060 filed on May 6, 2003 and Japanese Patent Application No. 2003-281647 filed on Jul. 29, 2003, which are incorporated herein by reference.
2. Description of Related Art
Sapphire (α-Al2O3) single crystals have been exclusively utilized as substrate wafers for making InGaN-type blue light emitting diodes and InGaN-type blue light laser diodes. GaN thin films, InGaN thin films or other nitride thin films are heteroepitaxially grown on a sapphire single crystal wafer. Light emitting devices are produced by piling n-type and p-type GaN and InGaN thin layers epitaxially on the GaN thin film grown on the sapphire wafer. Sapphire wafers are sold on the market and are easily obtained. Sapphire wafers have given satisfactory achievements as an essential part of blue light sources. Sapphire wafers, however, have weak points. Sapphire, which is an insulator, cannot lead electric current. Sapphire prevents us from making n-type or p-type sapphire. A sapphire substrate forbids us to make an n-electrode on a bottom of a device chip. An n-electrode should be formed upon a conductive n-type GaN layer grown upon a sapphire substrate. Both p- and n-electrodes are formed upon a top of an LED or LD device chip.
The top n-electrode requires a wide extra surface for the device chips. Existence of the top n-electrodes inhibits device makers from reducing chip sizes of LEDs or LDs. The top electrode is one drawback of sapphire wafers. Another weak point of sapphire is non-cleavage. Sapphire (α-Al2O3) has low symmetry which deprives the crystal of natural cleavage. High mechanical rigidity is a further drawback for sapphire wafers. Without relying upon natural cleavage, a device-produced sapphire wafer is cut into individual chips by mechanical dicing, which raises manufacturing costs and lowers yields. Lattice misfitting between the sapphire wafer and GaN layers makes a lot of dislocations and degenerates a light emitting property of chips.
No GaN single crystal wafer has been available till now. Thin films of GaN are grown on a foreign material substrate. Use of sapphire substrates, silicon carbide substrates (SiC), gallium arsenide substrates (GaAs) and spinel substrates has been reported. The most prevalent foreign material substrate is a sapphire substrate as described hitherto. Since the materials of substrates and films are different, strong stress occur at an interface between films and foreign material substrates. The films grown on the foreign substrate exfoliate from the substrate due to the strong stress at an early stage. For avoiding the exfoliation, interposition of a low-temperature grown buffer layer and separation growth of individual GaN nuclei via small windows of a mask (ELO method) have been proposed. The low-temperature made GaN buffer layer has a function of alleviating inner stress at a film/substrate interface. The ELO (epitaxial lateral overgrowth) method can make thin GaN layers on a sapphire substrate by covering the sapphire substrate with a mask (e.g., SiO2 or SiN), perforating the mask into small windows regularly aligning in a hexagonal pattern composed of repetitions of many equilateral-triangles for exposing the underlying substrate via the window, growing GaN nuclei on the separated exposed windows and reducing the inner stress.
{circle around (1)} PCT-application, WO99/23693, {circle around (2)} Japanese Patent Laying Open No. 2000-22212 (Japanese Patent Application No. 10-183446), {circle around (3)} Japanese Patent Laying Open No. 2000-12900 (Japanese Patent Application No. 10-171276), {circle around (4)} Akira Usui, “Thick Layer Growth of GaN by Hydride Vapor Phase Epitaxy”, IEICE, C-II Vol. J81-C-II No. 1, pp. 58-64, January 1998, {circle around (5)} Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto, Masato Matsushima, Hiroya Kimura, Hitoshi Kasai, Kikurou Takemoto, Koji Uematsu, Tetsuya Hirano, Masahiro Nakayama, Seiji Nakahata, Masaki Ueno, Daijirou Hara, Yoshinao Kumagai, Akinori Koukitu and Hisashi Seki, “Preparation of Large Freestanding GaN Substrates by Hydride Vapor Phase Epitaxy Using GaAs as a Starting Substrate”, Jpn. J. Appl. Phys. Vol. 40 (2001) pp. L140-L143, describe the ELO of GaN films on GaAs or sapphire substrates. The ELO method, which is inherently a method of making thin films, can produce no thick layer. If a thick GaN layer piles on a substrate by the ELO method, a number of dislocations are produced and big inner stress is yielded. The large inner stress would exfoliate the GaN layer from the substrate. Thus, the ELO fails to make a freestanding GaN substrate. The ELO is insufficient to produce a thick single crystal GaN substrate wafer. Another improvement is required for making GaN freestanding single crystal bulks besides the ELO.
{circle around (6)} Japanese Patent Laying Open No. 2001-102307 (Japanese Patent Application No. 11-273882), which has the same applicant as the present invention, proposed a facet growing method of GaN. Instead of maintaining a mirror-flat c-plane on the top, the facet growth method intentionally makes facets and facet pits, maintains the facets and the facet pits on a growing surface, displaces dislocations by the facets, gathers the dislocations from neighboring regions into centers of the facet pits, reduces dislocation density in other regions, and obtains low dislocation GaN single crystals. The facet growth method of {circle around (6)} enabled us to make a large freestanding GaN wafer of good single crystal for the first time. {circle around (6)} cannot predetermine spots of the facet pits, because {circle around (6)} lacks a contrivance of determining positions of the pits and the pits are born at random spots.
{circle around (7)} Japanese Patent Laying Open No. 2003-165799 (Japanese Patent Application No. 2002-230925) gave the GaN facet growing method an improvement of predetermining the positions of facet pits by depositing seeds on an undersubstrate, making facet pits following to the seeds. The seeds initiate closed defect assembling regions (H). Positions of the closed defect assembling regions coincide with the positions of the seeds on the undersubstrate. Other parts except the closed defect assembling regions (H) are good single crystal GaN.
Polishing is another important matter for the present invention. Polishing technology has not matured for nitride semiconductors, since independent, freestanding nitride crystal bulk wafers have not been produced on a practical scale yet. Thus, current polishing technology for other materials should be considered.
In the case of silicon semiconductors, silicon wafers are mechanically polished with alumina powder. Besides the mechanical polishing, processed silicon wafers having devices are polished for flattening rugged surfaces by chemical mechanical polishing (CMP) which makes use of colloidal silica and corrosive liquid. GaAs wafers are also treated with the chemical mechanical polishing (CMP), since some corrosive liquid for GaAs is known. People have believed that the CMP is impossible for sapphire and GaN. Sapphire is a refractory oxide. GaN is a sturdy nitride. Sapphire and GaN are chemically stable materials. A corrosive liquid for sapphire and GaN has not been reported.
{circle around (8)} Japanese Patent Laying Open No. 10-166259 (166259/1998) (Japanese Patent Application No. 8-332120) declared that it proposed a chemical mechanical polishing (CMP) of sapphire for the first time by an alkali liquid. However, {circle around (8)} a makes a secret of details of the polishing liquid. {circle around (8)} disclosed no concrete components of the alkali liquid. Nobody can obtain knowledge of the detail of the alkali. What is the alkali liquid as a polishing liquid for sapphire is still outstanding in spite of {circle around (8)}.
{circle around (9)} J. L. Weyher, S. Muller, I. Grzegory and S. Porowski, “Chemical polishing of bulk and epitaxial GaN”, Journal of Crystal Growth 182 (1997), p17-22, reported that they CM-polished GaN (0001) crystal bulks with an NaOH or KOH solution. But, {circle around (9)} insisted that CMP (chemical-mechanical polishing) was still impossible for high quality GaN crystals.
{circle around (10)} J. A. Bardwell, J. B. Webb, H. Tang, J. Fraser and S. Moisa, “Ultraviolet photoenhanced wet etching of GaN in K2S2O8 solution”, J. Appl. Phys., vol. 89, No. 7, p4142-4149, (2001), disclosed that GaN was wetly etched with a K2S2O8 solution.
{circle around (11)} Japanese Patent Laying Open No. 2002-356398 (Japanese Patent Application No. 2001-166904) was contrived by the same inventor as the present invention and related to chamfering of a periphery of a GaN wafer. Freestanding circular GaN wafers had not existed, but it was possible to make them for the first time. Therefore, the inventor contrived to chamfer the periphery of the GaN wafer and to make OF for indicating a specified direction.
The technology of making a bulk GaN single crystal wafer is not fully matured yet. Technology of producing AlN and InN is far behind GaN. 50 mmφ (2-inchφ) freestanding GaN single crystal wafers are not produced on a commercial scale and do not come onto the market yet. The applicant of the present invention has a potential of making a circular 50 mmφ GaN freestanding single crystal wafer. 45 mmφ GaN wafers are also available for the applicant. Circular GaN freestanding wafers larger than 45 mmφ are suitable for substrate wafers for making light source devices (LEDs and LDs) owing to circularity and size-sufficiency. However, such large GaN wafers made by the state-of-the-art technology are annoyed by poor flatness, large distortion and bad roughness. GaN bulks made in vapor phase are annoyed by large distortion height H which randomly ranges between 200 μm and 30 μm. Thickness fluctuation exceeds 50 μm. Due to lack of a pertinent polishing method, surface roughness is over 10 μm. No circular GaN wafers prepared by the current technology satisfy the requirements of flatness, thickness uniformity and smoothness at present yet. GaN is chemically stable and physically rigid. GaN, however, is not tough and fragile. It is not easy to polish chemically-tenacious, physically-rigid but fragile GaN crystals. Slight physical shocks easily break GaN crystals. GaN, which has a hexagonal system, has asymmetric plane properties for a (0001)-plane and (000-1)-plane. The (0001)-plane is a surface consisting of Ga atoms. Thus, the (0001)-plane is sometimes called “(0001)Ga-plane”. The (000-1) plane is a surface consisting of N-atoms. The (000-1) surface is called “(0001)N-plane”. Two surfaces of the Ga-plane and N-plane are different in chemical and physical properties. Namely, the chemical and physical properties of GaN wafers have orientation dependence. The chemical obstinacy, physical rigidity, fragility and orientation dependence enhance difficulties of lapping (grinding) and polishing (whetting) of GaN bulk crystals.
GaN is transparent for visible light. A GaN wafer looks like a glass plate. Silicon (Si) wafers or gallium arsenide (GaAs) wafers are opaque. Unlike Si or GaAs, GaN wafers have difficulty of discriminating a top or bottom surface by difference of finishing for the top/bottom.
GaN has other many problems. Here, attention should be paid to distortion and roughness of GaN bulk crystals. GaN has a hexagonal system having three-fold symmetry around a c-axis. A large GaN crystal is unobtainable. A foreign material plate is employed as a starting substrate, which is called an “undersubstrate” for distinguishing the object GaN substrate wafer. For example, a GaAs (111) single crystal plate is adopted for an undersubstrate.
Collaboration of the ELO method and the facet-growth method grows a thick GaN single crystal layer on the (111) GaAs substrate in vapor phase. Then, the GaAs undersubstrate is eliminated and a GaN freestanding thick layer is obtained. GaAs and GaN have large lattice misfitting and big thermal expansion rate difference. The lattice misfit and thermal expansion difference cause large inner stress in the GaN film. The large stress is released by eliminating the GaAs undersubstrate. The released inner stress deforms the GaN film. Distortion is a serious problem for the GaN wafers.
A top convex distortion in which a top surface lifts at the center upward is defined as a positive distortion. A top concave distortion in which a top surface sinks at the center is defined as a negative distortion. Distortion is not eliminated by neither ordinary grinding nor ordinary polishing. Single surface polishing comprises the steps of sticking a wafer upon a polishing disc on a reverse side, bringing the polishing disc into contact with a whetting cloth covering a polishing turntable, pressing the polishing disc to the turntable, supplying polishing liquid, rotating the polishing disc and revolving the turntable in reverse directions. The object bottom surface of the wafer is whetted by the polishing cloth glued to the turntable. When the wafer is stuck to a flat bottom of the polishing disc before polishing, the wafer is flattened. When the wafer is removed from the flat disc after polishing, the wafer deforms back to the original distortion. Distortion of a wafer is not eliminated by polishing but survives the polishing. It is impossible to rid a wafer of distortion by the ordinary polishing. Large wafer distortion increases difficulties in wafer process and enhances probability of breaking, splitting and cracking. The wafer distortion makes it difficult to adjust a focus on the wafer in the masked exposure in photolithography and increases errors of patterning.
Simultaneous double surface polishing is composed of the steps of preparing a template having a plurality of round holes, laying the template on a lower turntable with a whetting cloth, putting object wafers on the lower turntable in the holes of the template, lowering an upper turntable onto the lower one, pressing the object wafers between the upper and lower turntables, supplying whetting liquid, rotating the upper and lower turntables in reverse directions and giving a planetary motion to the template. A top and bottom surfaces of the object wafers are polished simultaneously by the upper/lower turntables. When the wafers are picked up from the polishing machine, the wafers deform into the original distortion. Also in the double polishing, the distortion and inner stress survive the polishing. In general, lapping (grinding) and polishing (whetting) are ineffective for reducing or removing distortion from wafers. Polished or lapped wafers recover the original deformation. Annihilation of distortion is a formidable problem for GaN wafers.
Another problem is fluctuation of thicknesses of wafers. Thickness variations induce fluctuation of properties of devices produced on the wafer. Thickness should be constant in the overall area of a wafer for avoiding fluctuation of properties of devices. Suppression of the thickness fluctuation is another significant matter. There are several different kinds of estimation of the thickness fluctuation.
Here, a parameter TTV (total thickness variation) is adopted for expressing the fluctuation of thickness. The TTV is, in short, a difference between the largest thickness and the smallest thickness among defined sampling points. The TTV is obtained by mounting an object wafer on a flat stage with a vacuum chuck, pulling one surface flatly on the stage, measuring heights of the other surface at sample points two-dimensionally-aligning at a predetermined spatial sampling period, deducing the maximum thickness and minimum thickness on the whole object wafer, and subtracting the minimum from the maximum. The TTV depends upon the spatial period d of measuring spots. The spatial period d which is a distance between neighboring spots can be arbitrarily determined. For example, d=5 mm is available. Otherwise, d=1 mm or 0.5 mm is also available. A suitable spatial (sampling) period d should be defined by taking account of a texture of surfaces, size of wafers and required accuracy. The TTV is a value which is obtained by subtracting the smallest thickness from the largest thickness. The TTV is not microscopic fluctuation of thickness but macroscopic difference between the maximum and the minimum. Thus, the TTV is essentially a macroscopic value, although thickness should be measured at many spots aligning in a two-dimensional lattice at a constant interval. Actual values of the TTV may slightly differ for different spatial periods d for the same specimen. A decrement of the sampling period d increases measured TTV. But, the TTV would uniformly converge at a definite value TTV0 at an infinitesimal limit of d→0. Smaller d gives more precise value of TTV0 but takes more time to measure heights at all sampling points. Here, d=0.1 mm is adopted. Surface heights are measured at sampling spots which are two-dimensionally aligned in a lattice at the sampling period d=0.1 mm. Then, TTV is obtained by subtracting the minimum from the maximum.
Another problem is roughness of wafer surfaces. At present top surfaces of GaN wafers are mirror-polished but bottom surfaces are roughened. Difference of roughness discriminates the top from the bottom. The top surface should be mirror-smooth, because devices are fabricated upon the top by lithography. Since devices are not built upon the bottom surface, the roughened texture is allowable for the bottom surface. The inventors of the present invention are aware that a rough bottom surface incurs some problems. In the case of prevalent Si wafers, GaAs wafers and InP wafers, a final washing step eliminates fine particles adhering to top and bottom surfaces by oxidizing and reducing the surfaces of the wafers. The elimination of particles from surfaces is called “lift-off”. The oxidization/reduction treatment succeeds in removing particles from wafer surfaces of Si, GaAs and InP which are chemically active and subject to oxidization. GaN is chemically more stable and more inactive than Si, GaAs and InP. GaN prevents a final washing step from lifting-off particles by oxidizing and reducing GaN surfaces with wet etchants. Rugged surfaces are far more likely to absorb and hold particles than smooth surfaces. If fine particles once stick to rugged bottom surfaces of GaN wafers, it is very difficult to remove the particles from the rugged surfaces. Roughened bottom surfaces of current GaN wafers, in particular, are apt to wear many fine particles which are tiny fragments of polishing material, wax or others. The final washing step allows some of the particles to remove from the bottom and to adhere to the top surface. FIG. 11, which has an abscissa of bottom surface roughness and an ordinate of top surface particle numbers, denotes that an increase of bottom surface roughness invites a conspicuous rise of particle numbers on the top surface.
FIG. 11 indicates the requirement of decreasing the bottom roughness for reducing contamination of top surfaces.
GaN freestanding bulk crystals are rigid but fragile. GaN lacks toughness unlike Si or GaAs. The rigid-fragility of GaN incurs another problem deriving from distortion. If a GaN wafer is strongly distorted, polishing steps are likely to induce occurrence of cracks originating from convex/concave extremes of the distortion. FIG. 3, which has an abscissa of curvature radii and an ordinate of crack occurrence rates, shows that stronger distortion with a shorter radius yields a higher rate of occurrence of cracks. FIG. 3 requests reducing distortion of wafers for avoiding occurrence of cracks.
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