1. Field of the Invention
The present invention relates to an apparatus or carrier and a method for testing semiconductor integrated circuits, and more particularly for identifying known good dies.
2. Description of the Related Arts
A demand for a semiconductor device package with a small foot-print has given a rise to a multi-chip module (MCM) technology which includes multiple semiconductor chips within a single package outline. In order for the MCM technology to be used widely, a technology for obtaining a Known Good Die (KGD), which refers to a bare semiconductor chip that passed a burn-in test which is typically performed on a packaged semiconductor chip, must be established. The burn-in test operates semiconductor chips in accelerated conditions to identify a semiconductor chip that is likely to fail early in its life.
Two types of burn-in test are available for bare chips; a wafer-level burn-in test and a die-level (or chip-level) burn-in test. The wafer-level burn-in test simultaneously tests all semiconductor chips on a wafer and uses a probe card that contacts fine-pitched terminal pads of the semiconductor chips of a wafer. However, a thermal expansion coefficient mismatch between the wafer and the probe card or a slight warpage of the probe card can cause contact failures between the probe card and the terminal pads. Accordingly, only relatively small wafers can use the wafer-level burn-in test. Further, in the wafer-level burn-in test, it is very difficult to maintain a burn-in temperature of about 125xc2x0 C. because a different yield of the wafer produces a different amount of heat from the wafer during the burn-in test.
The die-level burn-in test does not encounter with the problems described above, but the test requires a carrier that contains a semiconductor chip during the test. Examples of such carriers are xe2x80x9cDiepakxe2x80x9d of Aehr Co. and xe2x80x9cDiematexe2x80x9d of Texas Instrument Co. However, these carriers have specific designs that require special equipment for handling the carriers during burn-in testing. This increases the manufacturing costs of known good dies.
An apparatus for manufacturing a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside of the body. The bare chip is burned-in as contained in the apparatus. After the test, the apparatus releases the stopper and unloads the bare chip.
The apparatus according to the present invention has an outer configuration of a conventional semiconductor package, such as a Small Outline Package (SOP), a Small Outline J-Leaded Package (SOJ), or a Ball Grid Array Package (BGA), so that the apparatus can be used in conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip. A top surface of the carrier has an open cavity for receiving a semiconductor chip to be tested and leads which provide inner connection terminals. Outer leads of the carrier are used as the outer connection terminals. The carrier also can have a BGA configuration. In this case, the carrier is a printed circuit board having a chip mount area, inner connection terminals on a top surface of the board, and outer connection terminals on a bottom surface of the board. The outer connection terminals are solder balls attached on solder ball pads formed on the bottom surface. The solder ball pads connect to the inner connection terminals by internal wiring of the printed circuit board.
Accordingly, the apparatus according to the present invention can use conventional handling and burn-in test equipment in manufacturing known good dies.
USPTO Backgrounds
USPTO Backgrounds