1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. More particularly, embodiments of the invention relate to a NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation.
This application claims the benefit of Korean Patent Application No. 2005-83216 filed Sep. 7, 2005, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
A broad class of semiconductor memory devices has been developed to store and subsequently provide data within various electronic and computer applications. Semiconductor memory devices may be generally classified into random access memory (RAM) devices and read only memory (ROM) devices. The data stored in a RAM device is volatile in nature, that is, it is lost when power is no longer applied to the RAM. In contrast, data stored in ROM is nonvolatile in nature. It remains stored in ROM even when power is no longer applied to the ROM.
RAM devices may be further classified as dynamic RAM (DRAM), static RAM (SRAM), etc. ROM devices may be further classified as programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory, etc. Flash memory devices include NAND flash memory devices and NOR flash memory devices.
The NAND flash memory device supports a so-called “copy back program” operation in addition to the customary program, read, and erase operations. The copy back program operation is essentially adapted to “copy back” data stored on a source page into a target page. That is, the data stored on the source page is temporarily stored on a page buffer, and then immediately programmed into the target page. Through use of the copy back program operation, the programming speed of a NAND flash memory device may be markedly improved, because the otherwise duplicate process of reading data from the source page, as well as the process of externally reloading data may be omitted.
However, a conventional NAND flash memory device may generate a 1-bit error during the process of reading data from the source page through a page buffer during a copy back program operation. Additionally, another 1-bit error may be generated during the process of reading data from the target page. That is, the conventional NAND flash memory device may generate two (2) 1-bit errors (or a cumulative 2-bit error) during a conventional copy back program operation.
Generally, a NAND flash memory device may readily correct a 1-bit error in a single page of data as it passes through an associated memory controller. This is, however, not the case for a 2-bit error.
USPTO Backgrounds
USPTO Backgrounds