In recent years, it is demanded that a comparator formed of a two-stage amplifier, which is used in an analog-to-digital converter (ADC), reduce noise and suppress inversion delay. The inversion delay is the elapsed time from a change in the magnitude relationship between two differential pair inputs to the inversion of an output.
The noise of the ADC can be reduced by reducing the noise of the comparator. Further, the time required for AD conversion can be shortened by suppressing the inversion delay in the comparator.
Comparator noise reduction can be achieved when a noise band is narrowed by increasing the capacitance value of a capacitor for band limitation (hereinafter referred to as the band-liming capacitor). In such an instance, however, the inversion delay increases.
Meanwhile, a comparator disclosed in PTL 1 is capable of changing the capacitance value of the band-limiting capacitor. The configuration described above makes it possible to minimize the inversion delay without changing the level of noise by decreasing the capacitance value of the band-limiting capacitor when a reference signal is tilted.
However, the configuration described in PTL 1 does not solve the trade-off between noise and inversion delay. That is to say, the inversion delay increases when the noise reduces.
PTL 2 proposes that a capacitor for producing the Miller effect be connected between the input and output of a second amplifier included in the comparator in order to solve the trade-off between noise and inversion delay. When the configuration described above is adopted, the capacitance value of the capacitor remains small before an inversion operation, but increases during the inversion operation due to the Miller effect. This makes it possible to minimize the inversion delay while reducing the noise.
USPTO Backgrounds
USPTO Backgrounds