The basis of all micro-fabrication techniques is the replication of a pattern in a substrate. In photolithography, a series of contact masks are used to transfer a series of patterns onto the surface of a microcircuit chip. As each pattern is formed on top of the last, individual circuit elements are built up layer by layer.
FIG. 1 is a flowchart of the steps typically employed in photolithography to transfer a pattern to a microcircuit chip or work piece. At step 1, an oxide layer is deposited onto a substrate. During step 2, the substrate, and subsequently deposited patterns, are coated with an energy sensitive layer of material called a photoresist or resist. At step 3, a contact mask is placed on the microcircuit chip or work piece. During step 4, the contact mask and the underlying resist layer are exposed to an energy source such as ultraviolet light, and portions of the resist are hardened or developed. (Both positive and negative resists are known, so either the exposed or unexposed resist advantageously may be hardened.)
During step 5, the unhardened sections of the resist layer are washed away, leaving a resist mask on the surface of the work piece surrounding exposed areas of the oxide layer. Following step 5, oxide layer etching is performed (step 6) to remove portions of the exposed oxide layer from the substrate. The resist mask is stripped from the work piece during step 7. The work piece is now ready for impurity introduction using techniques such as diffusion and ion implantation to form electrically active areas in the substrate. The steps shown in FIG. 1 can be performed several times during the fabrication process.
In order to produce microcircuit devices with smaller and smaller dimensions, e.g., smaller separations between the active areas in the substrate, the thickness of the resist must be reduced correspondingly. This in turn decreases the resist's ability to withstand subsequent oxide etching steps, e.g., removal of the substrate not covered by the resist mask. Oxide etching defects can occur which result in poorly defined oxide layer edges and, consequently, irregularly sized diffusion windows. In addition, the thinness of the resist layer can result in resolution losses during the resist development step.
Several alternative techniques have been developed to produce resist masks with more oxide etching resistance. The most commonly employed method involves a two step resist mask production process. A first, relatively thick resist layer with a thickness of about 1000 nanometers (nm) is deposited on the oxide layer. Over this thick resist layer, a second, relatively thin resist layer having a thickness of about 1 nm is deposited. A pattern is developed in the thin resist layer and then both resist layers are selectively removed by reactive ion etching (RIE). However, RIE is a complex process, requiring significant expenditures for capital equipment and operator training.
Another method for overcoming the difficulties resulting from the fabrication of smaller and smaller devices is the formation of a metal mask to replace the resist masks discussed above. U.S. Pat. No. 4,578,157 discloses a method of laser induced metal deposition onto a layer of gallium arsenide (GaAs) semiconductor substrate. Metal deposition or metallization is controlled by pulsing a laser beam through a metal bearing solution as the substrate is precisely moved by a computer controlled positioning device. This maskless process again requires substantial outlays for capital equipment.
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USPTO Backgrounds