The invention relates to a control circuit for use with a semiconductor memory device, and more particularly, to a circuit which controls a write operation.
A conventional electrically erasable programmable ROM (EEPROM) includes memory cells formed by a plurality of transistors each of a double gate construction having a floating gate and a control gate. Data is written into a memory cell transistor by accelerating hot electrons generated in a drain region of the floating gate into a source region, with part of the accelerated electrons being injected into the floating gate. Data is read by detecting a change in the operating characteristic of the memory cell transistor, which depends on the amount of charge injected into the floating gate. Thus, data is read by detecting a change in the threshold value of the memory cell transistor.
Referring to FIG. 1, a conventional semiconductor memory device 100 will now be described. The memory device 100 includes a plurality of pairs of memory cell transistors 1 arranged in a four row-one column array, and a row decoder 5 connected to the memory cell transistors 1. In FIG. 1, a column decoder is omitted from the illustration.
Each memory cell transistor 1 has an electrically isolating floating gate which stores a charge, a control gate partly overlapping with the floating gate, a source region and a drain region. The memory cell transistor 1 is turned on/off in accordance with a potential applied to the control gate. The memory cell transistor 1 has a threshold value which varies depending on the amount of charge stored on the floating gate. Two adjacent memory cell transistors 1 together form a pair.
A plurality of word lines 2 are disposed in a manner corresponding to each row of memory cell transistors 1, and connect the control gates of the memory cell transistors 1 to the row decoder 5. A bit line 3 is disposed in a manner corresponding to a column of memory cell transistors 1. The bit line 3 is connected in common to the drains of the memory cell transistors 1 and is connected to a sense amp, not shown. A plurality source lines 4 are connected in common to the sources of each of the pairs of memory cell transistors 1.
The row decoder 5 receives row address information from a control circuit, not shown, and produces row select signals LS1-LS4, each of which activates one of the four word lines 2. In response to a select clock .phi.L, the row decoder 5 activates one of the row select signals LS1-LS4 and its corresponding word line 2. In this manner, the memory cell transistor 1 connected to the activated word line 2 is turned on.
While the memory cell transistors 1 are shown as disposed in one column in FIG. 1, it should be understood that the memory cell transistors 1 may be disposed to form a plurality of columns. In this instance, a column decoder, not shown, selects one of the columns in accordance with column address information. Subsequently, one of the plurality of memory cell transistors 1 in the selected columns is selected in accordance with the row address information.
A read-out circuit 6 is connected to the bit line 3. The read-out circuit 6 produces a potential Vd1 during a read operation in response to a read-out clock .phi.R from a control circuit, not shown. A write-in circuit 7 is connected to the source line 4. The write-in circuit 7 produces a potential Vd2 during a write operation in response to a write-in clock .phi.W from a control circuit, not shown, and feeds the potential Vd2 to the source line 4. The read-out circuit 6 and the write-in circuit 7 normally provide a ground potential Vs, except for intervals during which the read-out potential Vd1 and the write-in potential Vd2 are fed to the bit line 3 and the source line 4, respectively.
An HV generator circuit 8 boosts a supply potential in response to a predetermined clock pulse from a control circuit, not shown, thereby producing a potential Vhv which is higher than the supply potential. For example, the HV generator circuit 8 produces 14 V from the supply potential of 5 V. The HV generator circuit 8 feeds the high potential Vhv to the write-in circuit 7, which in turn feeds the high potential Vhv to the source line 4 as the write-in potential Vd2. A write-in control circuit 10 is connected to the HV generator circuit 8 and the write-in circuit 7. The write-in control circuit 10 receives the high potential Vhv from the HV generator circuit 8, and feeds a control signal HE to the write-in circuit 7 to initiate the write operation when the high potential Vhv is equal to or higher than a predetermined level.
The write-in and the read operation of the semiconductor memory device 100 will now be described. During the write operation, the ground potential Vs is applied to the drain of the memory cell transistor 1 via the bit line 3, and the write-in potential Vd2, which may be 14 V, for example, is applied to the source of the memory cell transistor 1 via the source line 4. When the select signals LS1-LS4 from the row decoder 5 are applied to the control gates of the memory cell transistors 1, a particular one of the memory cell transistors 1 is selected. The write-in current flows from the source region toward the drain region in the selected memory cell transistor 1, thus injecting a charge into the floating gate.
On the other hand, during the data read operation, the read-out potential Vd1, which may be 5 V, for example, is applied to the drain of the memory cell transistor 1 via the bit line 3, and the ground potential Vs is applied to the source of the memory cell transistor 1 via the source line 4. The select signals LS1-LS4 from the row decoder 5 allow a particular one of the memory cell transistors 1 to be selected. The read-out current flows from the drain region toward the source region in the selected memory cell transistor 1. At this time, the memory cell transistor 1 has a threshold value which is determined by the amount of charge stored on the floating gate. Accordingly, a potential on the bit line 3, which depends on this threshold value, is read out to the sense amp.
Referring now to FIGS. 2 and 3, the write-in control circuit 10 will be described. As shown in FIG. 2, the write-in control circuit 10 includes N-channel transistors 11, 12 and a CMOS inverter 13. The transistor 11 has a drain connected to the supply potential, a gate which receives the high potential Vhv, and a source connected to the N-channel transistor 12. The transistor 11 has a high voltage withstanding structure in which the opposite ends of the gate are spaced from the source and the drain. The transistor 12 has a drain connected to the source of the transistor 11, a source connected to the ground potential and a gate which receives the supply potential. The inverter 13 receives an input signal or a potential Va from a node between the transistor 11 and the transistor 12 and generates a control signal HE for initiating a write operation.
The operation of the write-in control circuit 10 will now be described with reference to FIG. 3. As the HV generator circuit 8 begins its boosting operation, the output potential Vhv begins to rise. When the output potential Vhv reaches a threshold value Vh0 of the transistor 11, the transistor 11 is tuned on and, the potential Va at the node between the transistors 11 and 12 rises. The threshold value Vh0 of the transistor 11 may be suitably changed depending on the potential required for the write operation. The inverter 13 causes the control signal HE to fall in response to the rising edge of the potential Va. The write-in circuit 7 commences its write operation in response to the falling edge of the control signal HE. In other words, the write-in circuit 7 commences the write operation when the high potential Vhv from the HV generator circuit 8 reaches the level Vh0, which is required for the write operation.
If the supply potential fluctuates in the write-in control circuit 10, an on resistance of the transistor 12 will vary, even if the threshold value of the transistor 11 is maintained constant. Accordingly, the timing of the falling edge of the control signal HE. A change in this timing leads to a change in the timing when the write-in circuit 7 commences the write operation. Specifically, the write-in circuit 7 may commence the write operation before the output potential Vhv from the HV generator circuit 8 rises to the required level Vh0 or may lag in commencing the write operation. Accordingly, a fluctuation in the supply potential causes an instability in the write operation by the write-in circuit 7, causing an error in the value written to the selected memory cell transistor 1.
It is an object of the present invention to provide a semiconductor memory device which enables a stable write operation.
USPTO Backgrounds
USPTO Backgrounds