When circuit boards are inserted into live backplanes (typically at −48V), the input of a board's power module or switching power supply (or bypass capacitors if provided) can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board's components and glitches on the system power supply. By limiting inrush current caused by transient effects one protects the board from excessive current spikes. Three commercially available circuits for limiting inrush current are shown in FIGS. 1-3.
In FIG. 1, the circuit shown is commercially available from the current assignee as the Hot Swap Controller LT4250, Hot Swap being a trademark of the present assignee. The controller includes an active current limit inverting amplifier ACL that is connected to external circuitry so as to limit the inrush currents to an adjustable value by controlling the gate voltage of an external N-channel pass transistor FET. The pass transistor FET is turned off if the input voltage is less than a programmable under voltage threshold or greater than an over voltage threshold. An adjustable current limit also protects the system against shorts. After a 500 microsecond timeout the current limit circuit activates an electronic circuit breaker. By placing an external capacitor CR between the drain and the gate of the FET and using a current limited pull up in the ACL amplifier (represented by the IGATE current source), the inrush current can be set by the ratio between the load capacitance CL and CR, which is independent of the circuit breaker threshold. By setting the inrush current well below the current limit of the circuit breaker threshold, the circuit breaker can be optimized to protect the FET. A small circuit breaker time tCB reduces the power consumed by the FET upon a short-circuit event keeping it within its safe operating area. However, this technique typically requires a capacitor CG between the gate and source of the FET that is much larger than CR to avoid turning on the FET at insertion of a board equipped with the controller into a live backplane. Specifically, the capacitor CG prevents the FET from momentarily turning on when the power pins first make contact with the live backplane. Without the capacitor CG, capacitor CR would pull the gate of the FET up to a voltage roughly equal to VEE times CR/CGS (the gate-source capacitance of the FET) before the circuit can power up and actively pull the gate of the FET low. By placing the capacitor CG in parallel with the gate capacitance of FET, the problem is solved. This large CG makes the turn-off of the FET difficult in a hard short event and increases the SOA requirement. The approach also complicates the selection of the compensation network used to stabilize the active current limit.
In a second controller shown in FIG. 2, commercially available from the present assignee as the LTC4252, output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feed forward path that limits peak current under worst-case catastrophic fault conditions. Active current limit is used during the generation of inrush current in order to eliminate CR and reduce the value of CG (components used in the FIG. 1 controller). One drawback of this approach is the long circuit-breaker time tCB required to accommodate the current limit servo time to avoid timeout during startup and input step. When a short occurs, the FET experiences the full current limit through the long tCB, which results in a large SOA requirement and makes the selection of the FET difficult in a high power application. Reducing the current limit as a function of VOUT (current limit foldback) reduces the SOA requirement during startup and the input step. It also performs satisfactorily during a hard short. However, in a soft short event, the FET may still experience the full scale current limit for tCB, which in turn can result in a large stress on the FET.
A third circuit shown in FIG. 3, commercially available from Supertex of Sunnyvale Calif. as the HV301/311, also controls the output current with an active current limiting circuit. During the initial power application, the gate of the external pass device (NMOSFET) is clamped low to suppress contact bounce. Thereafter, under voltage/over voltage (UV/OV) supervisors and power-on-reset work together to suppress gate turn-on of the NMOSFET until mechanical bounce has ended. An active current limit control circuit is then activated during power-up to limit the inrush current. The capacitor C2, connected between the RAMP pin and the drain of the NMOSFET, allows the inrush current to be lower than the current limit. However, the current limit circuit is still active and there is no way to distinguish between normal inrush current and a current overload. Similar to the LTC4252, a long circuit-breaker time tCB (100 ms typical) is required to avoid circuit-breaker timeout during startup. Thus, when an output short occurs, the NMOSFET will conduct at the current limit level for the whole tCB, severely stressing the NMOSFET.
FIG. 4 illustrates a circuit, which is described in greater detail in U.S. Pat. No. 5,952,817, assigned to the present assignee. This circuit is a switching regulator that slows down both the voltage and current slew rates. However, the purpose of slowing down both the voltage and current slew rates is to reduce the high frequency noise introduced to the power supply and ground. A Miller capacitor CV, 20, and the adjustable current IVSLEW set the voltage slew rate, dV/dt, at node 22. Amplifiers 24, 26 and 28 act to control the slew rate of the transistor Q1 current.
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USPTO Backgrounds