1. Field of Invention
The present invention relates to the etching of an integrated circuit structure. More particularly, the present invention provides a method for etching a dielectric layer with a metal hard mask layer.
2. Description of Related Art
Metallic compounds and their related metals, such as Tantalum Nitride and Tantalum or Titanium Nitride and Titanium, have been used in integrated circuit (IC) fabrication. Previously, the metals and/or the metallic compounds have been used as antireflective coatings or barrier layers.
However, as device critical dimensions (CD) continue to shrink and IC manufacturing technology enters 0.10 μm and beyond technology nodes, these metals and their associated metallic compounds are used as a metal hard mask layer for a dielectric layer. Typically the dielectric layer used for manufacturing technology that enters 0.10 μm and beyond technology nodes are referred to as “low-k dielectrics”.
Low-k dielectrics can be categorized as follows: doped oxide, organic, highly fluorinated, and porous materials. Low-k materials can be deposited either by spin-on or CVD methods. Porous materials typically use spin-on methods, with controlled evaporation of the solvent providing the desired pore structure. A table of typical low-k dielectrics is provided below.
TABLE 1Illustrative Low-k Dielectric MaterialsFilm TypesSub-TypeExamplesk rangeDoped OxideF-dopedFSG3.5H-dopedHSQ2.7–3.5C (and H) dopedOSG, MSQ,2.6–2.8CVD low-kOrganicBCB, SiLK, FLARE,2.6–2.8PAE-2Highly FluorinatedParylene AF4, a-CF,2.0–2.5PTFEPorousAerogels, Xerogels,<2.2Nanogels
Low-k dielectric materials have dielectric constants of less than 4.0, and generally the dielectric constants are less than 3.0. Porous low-k dielectric materials having dielectric constants of less than 2.2 and are used in applications having CDs of 0.10 μm and beyond. The porous dielectrics have air trapped within the pore structure to generate low dielectric constants.
It was previously believed that the processes for etching porous low-k material would be the same as the processes used on the bulk materials. However, a variety of particular challenges related to the etching of an IC structure having a metal hard mask layer and a dielectric layer have been uncovered. These challenges include determining an etchant gas mixture that is selective to the dielectric layer and which provides little or no etching of the metal hard mask layer. Another challenge has been to provide a method for etching the dielectric layer and the metal hard mask layer in the same chamber, thereby improving the throughput.
Therefore it would be beneficial to provide an etchant gas mixture that is selective to the dielectric layer.
Additionally, it would be beneficial to provide an etchant gas mixture that performs little or no etching of said metal hard mask layer during the etching of the dielectric layer.
Further still it would be beneficial to provide a method for etching the dielectric layer and the metal hard mask layer in the same chamber.
USPTO Backgrounds
USPTO Backgrounds