The invention relates to an electronic circuit comprising a sample and hold circuit for sampling and holding an input data signal, comprising switching means for sampling a data voltage which corresponds to the input data signal and a capacitive element for temporarily holding the sampled voltage.
Such electronic circuits are known from the prior art and are used inter alia in various types of analog-to-digital converters. There is a general trend in the design of electronic circuits towards operation at low supply voltages. The minimum required supply voltage in known sample and hold circuits is equal to or higher than the maximum value of the sampled voltage which corresponds to a maximum voltage of the input data signal.
It is accordingly a problem f known sample and hold circuits that they do not function at supply voltages which are lower than the maximum voltage of the input data signal.
It is an object of the invention, therefore, to provide an electronic circuit with an improved sample and hold circuit which can operate at a lower supply voltage.
According to the invention, the electronic circuit mentioned in the opening paragraph is for this purpose characterized in that the electronic circuit comprises compression means for compressing the voltage range of the data voltage to be sampled.
The presence of the compression means reduces the maximum value of the sampled voltage across the capacitive element. As a result, the electronic circuit can operate at a lower supply voltage.
An embodiment of an electronic circuit according to the invention is characterized in that the electronic circuit further comprises expansion means for converting the sampled voltage into a sampled output data signal which corresponds approximately linearly to the input data signal.
The expansion means supply a current which is dependent approximately linearly on the input data signal. As a result, the output data signal is substantially undistorted, while nevertheless the electronic circuit can operate at a lower supply voltage.
An embodiment of an electronic circuit according to the invention is characterized in that the compression means comprise a first transistor with a main current path which is designed to pass a current which is substantially linearly dependent on the input data signal, a control voltage of the first transistor constituting the data voltage to be sampled in the operational state, and in that the expansion means comprise a second transistor such that the sampled voltage constitutes a control voltage for the second transistor in the operational state, while the second transistor comprises a main current path for supplying the sampled output data signal.
The first and the second transistor are mutually matched, so that they in fact form a current mirror, i.e. the output current of the current mirror is a sampled version of the input current of the current mirror. The first and the second transistor may be constructed as bipolar transistors or as field effect transistors.
USPTO Backgrounds
USPTO Backgrounds