Modern integrated circuits, such as programmable logic devices (PLDs) and other electronic devices, are often configured to begin operation shortly after being powered on. Such “instant-on” behavior, for example, may involve the loading of configuration data from non-volatile memory cells to volatile memory cells of a device.
In certain applications, configuration data may be downloaded from non-volatile memory cells of a device to volatile memory cells of the device implemented as SRAM cells. Typically, such loading is performed immediately after the device is powered on, such as in response to the release of a power-up reset signal. After a successful download of configuration data, the programmed features of the device may be utilized.
Unfortunately, such conventional approaches to the loading of the volatile memory cells can introduce errors during the programming of the configuration data in the volatile memory cells. For example, if the power supplied to the device (such as power supplied through a Vcc pin) is insufficiently high or unstable during power-up, the PLD may not be prepared to perform a reliable transfer of the configuration data. As a result, corrupt configuration data may be stored in the volatile memory cells, thereby causing unreliable operation of the PLD. Accordingly, there is a need for an improved approach to the loading of configuration data from non-volatile memory cells into volatile memory cells.
USPTO Backgrounds
USPTO Backgrounds