The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for generating a selected subset of memory addresses associated with a semiconductor memory array.
As Application Specific Integrated Circuit (ASIC) technologies expand into new markets, the need for denser embedded memory increases. For example, markets in portable and multimedia applications such as cellular phones and personal digital assistants demand increased density of embedded memory for higher function and lower power consumption. In order to accommodate this increased demand, embedded DRAM (eDRAM) macros have been offered in state-of-the-art ASIC portfolios. The integration of eDRAM into ASIC designs has intensified the focus on how best to test a high-density macro as complex as DRAM in a logic test environment. The traditional use of Direct Memory Access (DMA), however, proves to be costly in terms of silicon area, available I/O pins, wiring complexity and test time.
Accordingly, a more attractive solution to the logic test problem has been through the use of a Built-In Self Test (BIST) system that is adapted to provide all of the elements needed to provide high fault coverage on DRAM. Such elements include, for example, the calculation of a two-dimensional redundancy solution, pattern programming flexibility, at-speed testing, and test mode application for margin testing. The development of BIST has allowed the testing of large embedded memories on logic testers without added die area of performance testing inaccuracies incurred with isolation multiplexers.
A BIST unit, in response to commands from an associated test board, typically tests the entire storage cell and provides an indicia of the results of the test procedure. However, in many situations, limiting the test procedures to those involving the entire memory unit can result in an unsatisfactory test procedure. For example, in testing a prototype memory unit, the failure of the prototype memory unit may be the result of either a failure of the BIST unit itself or a design flaw in a portion of the memory unit. In either situation, the mere failure of the test procedure does not, by itself, provide enough information to localize the specific problem with sufficient accuracy so as to enable a resolution of the same.
One existing approach to limiting the portion of the memory unit to be tested by the BIST unit is to control the upper limit of the storage cell array addresses being tested. With this approach, the array address upper limit may then be varied, thereby systematically expanding the testing of the storage cell array to include the entire storage cell array. Unfortunately, this particular test procedure is not particularly useful for any address above the address including the first-identified defect. Moreover, this approach is particularly unsatisfactory when the identified defect occurs at a relatively low address.
Another existing approach has been to implement boundary registers which include preprogrammed upper and lower address limits therein. During operation of the BIST circuitry, the boundary registers determine the address at which the testing procedure begins and ends. Despite the ability to select an address subset, however, this approach still does not allow for selective skipping of any addresses falling within the upper and lower address limits.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for generating a selected subset of memory addresses associated with a semiconductor memory array. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.
In a preferred embodiment, a mask inversion signal is coupled with the series of masking bits programmed in said mask register. The mask inversion signal selectively causes any masked bits in the address counter to become unmasked, and unmasked bits in the address counter to become masked. Further, the address counter may be initialized with a starting address therein through the use of a scan chain. Preferably, the mask register is also programmed through the scan chain. The address counter further includes a binary counter which may be incremented or decremented, based upon the value of an increment/decrement signal applied thereto.
USPTO Backgrounds
USPTO Backgrounds