1. Field of the Invention
The present invention relates to a junction field effect transistor and a production method for the same.
2. Description of Related Art
As a representative example of field effect transistors (FET), a junction field effect transistor (JFET) is known well.
FIG. 6 is a sectional view schematically showing the construction of a conventional junction field effect transistor.
This junction field effect transistor 101 includes a p type substrate 102, a p type epitaxial layer 103 laminated on the p type substrate 102, and an n type epitaxial layer 104 laminated on the p type epitaxial layer 103.
In the n type epitaxial layer 104, a p+ type ring-like region 105 is formed across the entire circumference of a peripheral portion in a plan view. This p+ type ring-like region 105 extends from the surface of the n type epitaxial layer 104 toward the p type substrate 102 and its lower end reaches the p type epitaxial layer 103.
In a surface portion of the n type epitaxial layer 104, n+ type source regions 106 and drain regions 107 are alternately arranged in stripes. The source regions 106 and the drain regions 107 are formed by introducing an n type impurity from the surface of the n type epitaxial layer 104 and then diffusing the n type impurity by heat treatment.
Furthermore, between the source regions 106 and the drain regions 107, P+ type gate regions 108 are formed. Each gate region 108 extends in parallel to the source region 106 and the drain region 107, and both ends thereof are connected to the p+ type ring-like region 105. The gate regions 108 are formed by introducing a p type impurity from the surface of the n type epitaxial layer 104 and then diffusing the p type impurity by heat treatment.
A source electrode and a drain electrode are connected to the source regions 106 and the drain regions 107 respectively. A gate electrode is connected to the back surface of the p type substrate 102 (surface opposite to the side with the p type epitaxial layer 103 formed). The p+ type ring-like region 105 reaches the p type epitaxial layer 103, and the gate regions 108 are connected to the p+ type ring-like region 105, whereby the gate electrode is electrically connected to the respective gate regions 108.
In this junction field effect transistor 101, drain currents flowing between the drain regions 107 and the source regions 106 depend on the thicknesses of the n type epitaxial layer 104 (channel region thicknesses) between the gate regions 108 and the p type epitaxial layer 103. Therefore, to make uniform the drain currents of the respective devices created in a semiconductor wafer as a base material of the p type substrate 102, the thicknesses of the channel regions in the respective devices must be made uniform.
However, it is difficult to accurately control the diffusion of the p type impurity for forming the gate regions 108, so that the diffusion of the p type impurity varies, and the thicknesses of the channel regions 108 vary with in the surface of the semiconductor wafer.
USPTO Backgrounds
USPTO Backgrounds