1. Field of Invention
The present invention relates in general to the electrical connector field. More particularly, the present invention relates to a method of eliminating a via stub in printed wiring boards (PWBs) and other substrates, such as laminate subcomposites and interconnect substrates. The present invention also relates to PWBs and other substrates fabricated using the method, and a design process therefor.
2. Background Art
Electrical connectors are in widespread use in the electronics industry. In many computer and other electronic circuit structures, an electronic module such as a central processor unit (CPU), memory module, application-specific integrated circuit (ASIC) or other integrated circuit, must be connected to a printed wiring board (PWB). Printed wiring boards are also known as printed circuit boards (PCBs). When populated with one or more electronic components, a printed wiring board is often referred to as a printed wiring board assembly (PWBA) or a printed circuit board assembly (PCBA). In connecting an electronic module to a PWB, individual electrical contacts on the base of the electronic module must be connected to a plurality of corresponding individual electrical contacts on the PWB. This set of contacts on the PWB dedicated to contacting the electronic module contacts is known as a land grid array (LGA) site when a LGA connector is used to connect the electronic module to the PWB.
Typically, the PWB contains a plurality of vias, each electrically connecting a conductive trace on one layer of the PWB to one or more conductive traces on one or more other layers of the PWB. The vias may be at the LGA site, for example, or elsewhere on the PWB. FIG. 1 illustrates exemplary types of conventional vias in a cross-section of a PWB 100 having a plurality of insulator layers 102 and conductive traces 104. Typically, vias are electroplated (e.g., copper or other highly conductive metal) onto through-holes drilled into the PWB. Such a via, which extends from one surface of the PWB to the other surface of the PWB, is referred to as a plated-through-hole (PTH) via. An exemplary PTH via 110 is illustrated in FIG. 1. In addition to or in lieu of PTH vias, it is also not uncommon for high layer-count PWBs to have blind vias, which are visible only on one surface of the PWB, and/or buried vias, which are visible on neither surface of the PWB. An exemplary blind via 120 is illustrated in FIG. 1, as well as an exemplary buried via 130. Blind vias and buried vias are advantageous over PTH vias in certain respects (e.g., blind vias and buried vias are more efficient from a space utilization perspective than PTH vias, and unlike PTH vias, neither blind vias nor buried vias possess via stubs, which as discussed in more detail below, can significantly distort high speed digital signals that pass through PTH vias). However, blind vias and buried vias are significantly more expensive to fabricate than PTH vias because blind vias and buried vias are produced utilizing subcomposite fabrication steps.
As mentioned above, PTH vias possess via stubs that can significantly distort high speed digital signals that pass through PTH vias. This distortion is often severe and generally increases as the data rate increases. FIG. 2 illustrates a cross-section of a PWB 200 with an exemplary conventional PTH via 210 having a via stub 212 and an exemplary conventional backdrilled PTH via 220. The PWB 200 shown in FIG. 2 has a plurality of insulator layers 202, upper conductive traces 204, and intermediate conductive traces 206. The via stub 212 shown in FIG. 2 is the portion of the PTH via 210 that is not connected in the circuit between an upper conductive trace 204 (or contact-pad-portion of the PTH via 210) and an intermediate conductive trace 206.
A conventional technique known as backdrilling can be used to remove the via stub 212, which serves no useful function in this circuit. Backdrilling uses controlled depth drilling techniques to remove the undesired conductive plating in the via stub region. Typically, the via stub region is removed using a drill bit slightly larger in diameter than the drill bit that was used to create the original via hole. See, for example, the discussion of backdrilling via stubs in the publication of Franz Gisin & Alex Stepinski, “Overview of Backdrilling”, Sanmina-SCI Corp., San Jose, Calif., http://www.sanmina.com/Solutions/pdfs/pcbres/Backdrilling.pdf. An exemplary conventional backdrilled PTH via 220 having a backdrilled region 222 is illustrated in FIG. 2. As described in the Gisin & Stepinski publication, decreasing via stub length by backdrilling significantly reduces a particularly problematic form of signal distortion known as deterministic jitter. Because bit error rate (BER) is strongly dependent on deterministic jitter, any reduction in deterministic jitter by backdrilling will significantly reduce the overall BER of an interconnect—often by orders of magnitude. The Gisin & Stepinski publication also lists other key advantages to backdrilling PTH vias including: less signal attenuation due to improved impedance matching; increased channel bandwidth; reduced EMI/EMC radiation from the end of the via stub; reduced excitation of resonance modes, and reduced via-to-via crosstalk. Unfortunately, backdrilling is a costly, time-consuming process.
It should therefore be apparent that a need exists for an enhanced mechanism for via stub elimination in PWBs and other substrates, such as interconnect substrates.
USPTO Backgrounds
USPTO Backgrounds