This invention relates to programmable logic devices (“PLDs”), and more particularly to PLDs that include or that can include two-phase latches.
PLDs typically use single-phase, edge-triggered data storage circuitry (e.g., flip-flops) to register data signals propagating through the processing or logic circuitry of the PLD. This limits the speed at which the PLD can be made to operate (i.e., clocked) to the maximum signal propagation delay from one register to another register on the device. For example, if the maximum propagation delay between two single-phase, edge-triggered registers is 12 nanoseconds (“ns”), the period of the clock cannot be less than 12 ns. Even if the propagation delay between other registers is less than 12 ns, the slowest path controls, and it is not possible to decrease the period of the clock. Introducing another register in the path between two registers having a long inter-register propagation delay may decrease the maximum inter-register delay and thereby allow the clock period to be decreased. But this may also unacceptably or at least undesirably increase the latency of the signal(s) being propagated.
USPTO Backgrounds
USPTO Backgrounds