1. Field of Invention
The present invention relates to a semiconductor memory device and a method of operating the same. More specifically, the present invention relates to a method of programming a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device may include a memory cell array in which data is stored, and the memory cell array may include a plurality of memory cell blocks. Each of the memory cell blocks may include a plurality of cell strings disposed parallel to one another, and each of the cell strings may include a plurality of memory cells.
FIG. 1 is a circuit diagram of a conventional memory cell block.
Referring to FIG. 1, memory cells included in a memory cell array have the same configuration, and thus only one memory cell block will now be described.
The memory cell block may include a plurality of cell strings, and each of the cell strings may include a drain selection transistor, memory cells, and a source selection transistor connected in series. Drain selection transistors included in different cell strings may be connected to a drain selection line DSL, memory cells included in the different cell strings may be connected to word lines WL, and source selection transistors included in the different cell strings may be connected to a source selection line SSL. Sources of the source selection transistors may be connected to a common source line CSL, while drains of the drain selection transistors may be connected to bit lines BL.
In general, a programming operation may be performed in units of pages, which are units of memory cells connected to the same word line. For example, the programming operation may include applying a pass voltage to unselected word lines Unsel.WL and applying a program voltage to a selected word line Sel.WL with a program permission voltage applied to selected bit lines BLa and BLb and with a program prohibition voltage applied to unselected bit lines.
In recent years, a programming operation has been performed using an incremental step pulse program (ISPP) method by which a program voltage is gradually elevated to narrow a range of distribution of memory cells. Accordingly, even if a programming operation is performed on the same page, the time taken to complete a program may vary due to a difference in operating speed between memory cells. For example, when both a first memory cell Fa and a second memory cell Fb are selected memory cells, even if a program voltage is applied to a selected word line Sel.WL, the time taken to elevate threshold voltages of the first and second memory cells Fa and Fb may differ. Even if the threshold voltage of the first memory cell Fa becomes higher than a target level to complete a program operation, when the threshold voltage of the second memory cell Fb is lower than the target level the programming operation may have to be repeatedly performed by applying the program voltage to the selected word line Sel.WL until the threshold voltage of the second memory cell Fb becomes higher then the target level. In this case, while a program permission voltage is applied to a second bit line BLb associated with the second memory cell Fb, a program prohibition voltage may be applied to a first bit line BLa associated with the programmed first memory cell Fa, thus the threshold voltage of the first memory cell Fa cannot be elevated during the program operation performed on the second memory cell Fb. In general, the program permission voltage may refer to a ground voltage (e.g., 0V), while the program prohibition voltage may refer to a power supply voltage Vcc. However, the programmed first memory cell Fa may be affected by a gradually elevated program voltage until programming of the second memory cell Fb is completed, as will be described in detail with reference to the following drawings.
FIG. 2 is a graph of a threshold voltage and a bit line voltage, illustrating problems that may occur with conventional programming of a fast and slow memory cell.
Referring to FIG. 2, a fast cell may correspond to the first memory cell Fa of FIG. 1, while a slow cell may correspond to the second memory cell Fb of FIG. 1. When a program permission voltage is applied to a bit line and a gradually elevated program voltage is applied to a selected word line (T1 to T2), a threshold voltage of the fast cell rapidly increases and becomes higher than a target level at a time point T3. However, since a threshold voltage of the slow cell is lower than a target level at the time point T3, a programming operation for elevating the threshold voltage of the slow cell should continue to be performed. During programming of the slow cell, a program prohibition voltage is applied to a bit line connected to the fast cell. In this case, boosting may occur in a channel region due to an increase in capacitance between the gradually elevated program voltage and the program prohibition voltage applied to the bit line. When an electric potential of the channel region is elevated, electrons trapped in the fast cell may leak out and lower the threshold voltage of the fast cell. Since the program voltage is repeatedly elevated until the threshold voltage of the slow cell becomes higher than the target level, the threshold voltage of the fast cell is repeatedly decreased. Accordingly, after the threshold voltage of the slow cell becomes higher than the target level (T6), the threshold voltage of the fast cell may be lower than the target level.
FIG. 3 is a graph of a threshold voltage, illustrating problems that may occur with conventional programming of a fast and slow memory cell.
Referring to FIG. 3, when a programming operation of a selected page is completed, a distribution 31 of threshold voltages of selected memory cells included in the selected page should be equal to or higher than a target level. However, target voltages of some of the programmed memory cells may become lower than a target level because of the influence of a program prohibition voltage applied to a bit line and a program voltage applied to a selected word line while trying to program all unprogrammed memory cells. Accordingly, even if the programming operation of the selected page is completed, a distribution 32 of threshold voltages of selected memory cells may be lower than a target level, thereby decreasing the reliability of the programming operation.
USPTO Backgrounds
USPTO Backgrounds