Background Field
Embodiments of the subject matter described herein are related generally to overlay measurement, and more particularly to image based overlay measurement.
Relevant Background
Semiconductor processing for forming integrated circuits requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The material layers are typically patterned using a photoresist layer that is patterned over the material layer using a photomask or reticle. Typically, the photomask has alignment targets or keys that are aligned to fiduciary marks formed in the previous layer on the substrate. However, as the size of integrated circuit features continues to decrease, it becomes increasingly difficult to measure the overlay accuracy of one masking level to the previous level. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay alignment tolerances are reduced to provide reliable semiconductor devices.
Overlay measurement may be performed optically, e.g., based on an image of specially designed overlay targets or using light that is diffracted from the overlay targets. Image Based Overlay (IBO) measurements are performed using targets, such as box-in-box or bar-in-bar targets, that are imaged and the distance between target features printed on different layers is measured. Conventional IBO measurement targets are typically 20×20 μm or 25×25 μm in size. Diffracted-Based Overlay (DBO) typically uses targets having gratings that are not perfectly aligned, where a resulting diffraction pattern is used to determine the overlay error. Newer DBO targets may be 10×10 μm or larger.
There is increasing need for small overlay targets. Typically overlay targets are placed in the scribe lines between chips. Scribe lines, however, are shrinking to 50 μm, making targets of 20×20 μm or less desirable to end users who prefer to place targets side by side across the scribe line. The increase in the number of printed layers also creates pressure for targets to become smaller, as with the increase of layers, the number of targets also increases. Additionally, the newest processes benefit from more detailed knowledge of intrafield overlay variation, which can best be obtained using overlay targets that are placed within the device area, i.e., in-chip. Many end users are maintaining 10×10 μm openings within non-memory areas of their products so overlay targets may be printed and measured within these spaces.
USPTO Backgrounds
USPTO Backgrounds