(a) Field of the Invention
The present invention relates to a method for forming a silicide of a metal with a high-melting-point in a semiconductor device, and more in particular, to the method for forming suicide of a metal with a high-melting-point on the surfaces of source/drain regions of a silicon substrate.
(b) Description of the Related Art
Since a channel length is reduced with decrease of the line width of a gate electrode with the advance of the high integration of a semiconductor device, it is desired to suppress a short-channel effect in a MOSFET having shallower source/drain regions to thereby secure a desired source-drain withstand voltage.
In a MOSFET including source/drain regions having the shallower junction, the gate delay time is liable to be extended due to the increase of the sheet resistance, whereby the operational frequency of a transistor is reduced to increase the length of a response time.
In order to overcome the problem, the reduction of the resistance of the impurity-diffused region is important. A method of forming a layer of the metal-silicide layer having a lower resistance on the impurity-diffused region is conventionally developed for reducing the resistance of the surface of the diffused region.
The method for forming a metal-silicide layer in the diffused regions includes the steps of depositing a thin metal layer on the entire surface of a silicon layer, and annealing for forming the metal-silicide layer on the surface of the impurity-diffused region to proceed a reaction between cobalt and silicon at an interface between the metal layer and the silicon layer for forming a metal silicide in a self-aligned manner.
As a metal with high-melting-point for composing the metal-silicide, titanium, cobalt etc. are noticed, and a new process is developed forming a CoSix. layer on the diffused regions by reactions of cobalt and silicon.
In the process, a cobalt film is deposited on a silicon surface, and silicon substrate is annealed for forming the CoSix layer on the diffused regions.
Referring to FIGS. 1A to 1C, a conventional process for forming a CoSix. layer on the diffused regions on the gate electrode and the source/drain region of an NMOS transistor will be described,
As shown in FIG. 1A, a gate oxide film 46 and a poly-crystalline-silicon layer are formed on each isolated region of a silicon substrate 42 separated by an element-isolation region 44, and the poly-crystalline-silicon layer is patterned to form a gate electrode 48. Sidewall spacers 50 are formed along both sides of the gate electrode 48, and a masking oxide film 52 is formed on the entire surface of the wafer.
Then, impurity-implanted regions 54 to be formed as source/drain regions are under both sides of the gate electrode 48 by implanting arsenic ions thereto. A source/drain region 54 is formed by RTA(rapid thermal annealing) for diffusing the implanted arsenic ions, that is, subsequent activating.
Then, as shown in FIG. 1B, the masking oxide film 52 is removed. After the entire surface of the wafer is subjected to an O2-plasma treatment and washed, the wafer surface is subjected to a hydrogen fluoride (HF) treatment as a pretreatment of cobalt sputtering.
After the cobalt metal is deposited on the entire wafer surface by sputtering, a first annealing for reactions of cobalt and silicon is conducted. Then, after a selective wet-etching is conducted on the cobalt-silicide layer to remove the unreacted cobalt metal, a second annealing for reactions of cobalt and silicon is conducted for completing the reaction to form a CoSi2 film 56 on the gate electrode 48, and the source/drain region 54 in a self-aligned manner.
In the process described above, the following problems arise when the CoSi2 film is formed by employing the above conventional method.
Firstly, the CoSi2 film 56 may have an uneven surface or a concave-convex surface 58 having a steep slope and a sharp edge as shown in FIG. 2, which impairs reduction of resistance of the source/drain regions. If the uneven shape becomes more conspicuous, a white cloud which may be generated by peeling-off of a part of the CoSix film is formed on the substrate, or the concave-convex is formed on the entire surface. Thus, an impurity-diffused region having a desired low resistance is difficult to achieve
Secondly, the initial withstand voltage of a gate electrode (or initial gate-oxide-film breakdown voltage) is low.
Similar problems arise when another metal having a high-melting-point, for example, TiSix is formed although the CoSi2 is herein exemplified as the silicide of a metal having the high-melting-point.
In view of the foregoing, an object of the present is to provide a method for forming silicide of a high-melting-point metal in a semiconductor device without causing the above problems.
The present invention provides, in a first aspect thereof, a method for forming a silicide of a metal with high-melting-point in a semiconductor device including the steps of: implanting impurity ions into a silicon substrate to form an impurity-implanted region; heat-treating the silicon substrate in the oxidative atmosphere to form an oxide layer on top of the impurity-implanted region; etching the above-mentioned oxide layer for removal thereof by using a basic oxidant solution; heat-treating the silicon substrate to form an impurity-diffused region; depositing a metal with high-melting-point to form a metal layer on the impurity-diffused region; and heat-treating the silicon substrate to form the metal-silicide layer on the surface of the impurity-diffused region.
The present invention provides, in a second aspect thereof, a method for forming a silicide of a metal with high-melting-point in a semiconductor device including the steps of: implanting impurity ions into a silicon substrate to form an impurity-implanted region; heat-treating the impurity-implanted region to diffuse the impurity ions to form an impurity-diffused region from the impurity-implanted region; etching a top of the impurity-diffused region for removal thereof by using a basic oxidant solution; depositing a metal with high-melting-point to form a metal layer on the impurity-diffused region; and heat-treating the silicon substrate to form the metal-silicide layer on the surface of the impurity-diffused region.
In general, the top portion of the impurity-implanted region having a higher impurity concentration may act for prevention of reactions of cobalt and silicon of the impurity-diffused region after the annealing process for diffusing the implanted impurity ions. In accordance of the first and second aspects of the present invention, the top portion is removed after oxidization (first aspect) or directly after the implantation (second aspect), before forming a metal-silicide layer on the impurity-diffused region. Thus, the metal-silicification proceeds smoothly to thereby afford a higher initial gate withstand voltage and a lower sheet resistance for the gate electrode and the source/drain regions of a MOSFET.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
USPTO Backgrounds
USPTO Backgrounds