1. Technical Field
The present invention relates to a manufacturing apparatus, a test apparatus, a manufacturing method, and an integrated circuit package.
2. Related Art
A known apparatus for testing a plurality of devices formed on a semiconductor wafer uses a probe card that can contact many electrodes of the wafer at once, as shown in Patent Document 1, for example. In this apparatus, the wafer under test in contact with a probe card is placed in an examination apparatus, and examination is performed at a high temperature. Patent Document 2 describes an apparatus that stores chips in packages having the same form as a commercial package, and tests these packages.    Patent Document 1: Japanese Patent Application Publication No. 2006-173503    Patent Document 2: Japanese Patent No. 4122102
In the above apparatuses, however, a large amount of wiring must be connected to manufacture the probe card, and this incurs a high cost. Furthermore, in the above apparatuses, adjusting the relative positions of the wafer under test and the probe card is difficult. If a chip that has been cut is stored in a package having the same form as a commercial package and then tested, the packaging configuration becomes complicated and the cost of the package increases. In addition, warping occurs in the chips after cutting. In such cases, an accurate connection cannot be achieved between the electrodes of the chip and the terminals of the package.
USPTO Backgrounds
USPTO Backgrounds