The invention relates to a semiconductor memory comprising memory cells which are arranged in a matrix of rows and columns, each memory cell comprising two emitter-connected transistors whose collectors are cross-wire connected to the bases, the memory cells in a matrix row being connected parallel to one another between a first and a second power supply line, switching means being connected to the first power supply line in order to bring the first power supply line to a line selection potential or to a rest potential, and a current source being connected to the second power supply line in order to sustain data stored in each memory cell connected to said line. The switching means includes a first transistor which is connected to the first power supply line by way of its emitter and whose base receives voltage pulses in order to bring the first power supply line at the line selection potential and also includes a further transistor for discharging the first power supply line from the line selection potential to the rest potential or for discharging the second power supply line. The memory also includes detection means for detecting the end of a voltage pulse on the base of the first transistor and for controlling the further transistor, said detection means being at least indirectly connected to the base of the first transistor for this purpose.
A memory of this kind is known from Japanese Patent Application No. 54-35.915, dated Mar. 24, 1979 and published on Oct. 8, 1980 (publication No. 55-129.992); therein a static memory based on the E.C.L. technique is disclosed. Another prior-art memory circuit is shown in U.S. Pat. No. 4,156,941.
The present invention relates notably but not exclusively to RAM memories manufactured according to the E.C.L. (Emitter Coupled Logic) technique.
During normal operation, the cells of a row (the selected row) in a memory according to the present state of the art are connected to a high (selection) potential V.sub.H via a power supply line, all other cells of the other rows being at a low (rest) potential V.sub.B via a corresponding number of power supply lines. Upon a transition between two cells which belong to two different rows, the potential of the power supply line selected must be reduced as quickly as possible from V.sub.H to V.sub.B. It is known that a power supply line for a row of memory cells has a comparatively high capacitance (capacitance of the aluminum tape which interconnects the 16, 32, 64 . . . cells of the row plus the self-capacitance of each cell). This high capacitance prevents the quick discharging of a row to the rest potential. It is known to generate a special discharge current at the instant of transition; this current is sometimes referred to as "additional current" and is applied to the power supply line to be discharged.
The switching over of this "additional current" between the power supply line to be discharged and the associated discharge circuit at the appropriate instant has been described in an article in an IEEE publication of January 1981, reference CH 1626, entitled "Large E.C.L. Bipolar RAMS" (pages 120-124, FIG. 11).
The described circuit utilizes a dynamic potential difference which arises at the instant of a transition V.sub.H .fwdarw.V.sub.B between two given points which are selected on either side of the addressing circuit which is connected to the power supply line for the row of cells (which notably comprises an addressing transistor which is referred to as the "first transistor" in the above publication). At the instant of the transition V.sub.H .fwdarw.V.sub.B, the voltages on the two said points change; the voltage in the addressing circuit then immediately decreases from V.sub.H to V.sub.B because of the low-capacitance control circuit, while the voltage on the power supply line decreases comparatively slowly because its capacitance is comparatively high.
In accordance with the present state of the art said dynamic potential difference is detected by a differential amplifier which controls a second differential amplifier which applies an additional current to the power supply line to be discharged.
The use of this circuit indeed causes the quick discharging of the power supply line but also involves the drawback that the additional current source operates permanently, i.e. not only at the instants at which this additional current is acutally required. The additional current has an intensity of several mA and represents a substantial part of the quiescent current of the memory which cannot be ignored. This is a serious drawback with respect to energy consumption and, consequently, unnecessary heat is developed in the semiconductor memory. On the other hand, the proposed circuit is also complex and comprises many circuit elements so that a comparatively large amount of space is occupied on the semiconductor crystal of the memory.
USPTO Backgrounds
USPTO Backgrounds