1. Technical Field of the Invention
This invention provides a system and method for circuit simulation. More particularly, it relates to a system and method for correct manipulation of waveforms in parallel time-warp simulations.
2. Background Art
The VHDL language is described in IEEE Standard VHDL Language Reference Manual, IEEE 1987. (VHDL refers to the VHSIC Hardware Description Language of IEEE standard 1076, where VHSIC means "very high speed integrated circuit.") The concept of time warp has been described by Jefferson. See, D. R. Jefferson, "Virtual time," in ACM Transactions on Programming Languages and Systems, pp. 404-425, July 1985.
During time-warp simulation of VHDL models it is possible that a simulation of an event on any processor (sometimes referred to as dispatcher) will schedule one or more transactions with simulation time less than the simulation time of already scheduled transactions (due to a simulation of previous events on processor's inputs) on an output of the processor. Such transactions will cancel one or more of the already scheduled transactions. This may happen because (i) of non-uniform propagation delays from the inputs of a logical process (also referred to simply as process) to its outputs and (ii) of the inertial delay model for the output. However, in time-warp simulation, the event generating new transactions, which canceled already scheduled transactions on the output, can get rolled back at some later time. In such a case we need to restore all the transactions which were canceled by the simulation of the rolled back event. Briner has proposed a solution for such event cancellation due to non-uniform propagation delay in switch-level time warp simulation of digital circuits which are not modeled in VHDL. See J. V. Briner, "Parallel Mixed-Level Simulation of Digital Circuits Using Virtual Time," Ph.D. thesis, Duke University, 1990. However, Briner's solution does not deal with the complexities of multiple waveform elements for an output and/or transaction cancellation due to inertial delay model.
Consequently, it is an object of the invention to provide a system and method for handling transaction cancellation, particularly for waveform elements.
It is a further object of the invention to provide a system and method for handling transaction cancellation due to the inertial delay model in time-warp simulation of circuits modeled in VHDL or any other such HDL, e.g., Verilog.
It is a further object of the invention to provide a parallel VHDL simulation method which will run on any number of parallel platforms, including a cluster of workstations such as a cluster of IBM RS/6000 systems interconnected with a switch, such as the Allnode switch described in U.S. Pat. No. 5,404,461, the teachings of which are incorporated herein by reference.
USPTO Backgrounds
USPTO Backgrounds