The field of the invention generally relates to architected state and, more specifically to transferring architected state between processor cores.
The conventional mechanism for transferring a thread from a first processor or processing core to a second processor or processing core is to collect the architected state representing the current processing state of the thread, including intermediate data produced during execution of the thread and store the architected state to memory. A pointer to the location in memory where the architected state is stored is passed by the first processor or processing core to the second processor or processing core. The second processor or processing core then reads the architected state from the memory and processing resumes.
The thread transfer is initiated by software while the storing and reading of the architected state is performed by the processor or processor cores. After the architected state is read, the first or second processor or processing core informs the software that the transfer is complete and execution of the thread resumes. Latency is introduced during the thread transfer due to the interactions between the software and processors or processing core. Latency is also introduced by passing the architected state through the memory, especially when the available bandwidth between the processors or processor cores and memory is limited.
USPTO Backgrounds
USPTO Backgrounds