1. Field of the Invention
The present invention relates to a method of adding/subtracting floating-point representation data suitable for a computer or a digital signal processor and an apparatus therefor.
2. Description of the Related Art
Floating-point representation data is generally expressed by a format shown in FIG. 2. Referring to FIG. 2, bit 0 represents a sign of the data. That is, bit O of "0" represents the positive polarity or 0, and bit O of "1" represents the negative polarity. Bits 1 to 7 represent an exponential part of the data in units of for bits of the mantissa port, and an offset is 40H. In this case a suffix H represents hexadecimal notation. Bits 8 to 31 in the case of single precision and bits 8 to 63 in the case of double precision represent a mantissa part of the data. Since the mantissa part is normally expressed in units of four bits, i.e., in hexadecimal notation, it has six digits in the case of single precision and 14 digits in the case of double precision. Normalization is performed in units of digits assuming that a floating-point is located to the left of bit 8. That is, in data except for 0, one of bits 9 to 11 always represents 1.
An apparatus for performing addition/subtraction of the floating-point representation data having the format shown in FIG. 2 is conventionally arranged as shown in FIG. 1. Referring to FIG. 1, operation data A and B and an operation instruction M indicating which of operations (A+B) and (A-B) is to be executed are supplied to the apparatus. When data to be operated is supplied, an exponent difference detector 11 operates a difference between exponential parts of the data A and B, thereby determining which of the exponential parts of the data A and B is larger. In accordance with the determination result, a multiplexer 12 selects a mantissa part of operation data having a larger exponential part, and a multiplexer 13 selects a mantissa part of operation data having a smaller exponential part. When the exponential parts are equal to each other, selection is performed assuming that A&gt;B. A shift circuit 14 shifts the mantissa part of the operation data having the smaller exponential part selected by the multiplexer 13 to the right by the number of digits corresponding to the difference between the exponential parts operated by the detector 11. As a result, the mantissa part of the operation data having the smaller exponential part is shifted with respect to the mantissa part of the operation data having the larger exponential part.
In accordance with an operation mode, an adder/subtracter 15 performs addition or subtraction between an output from the multiplexer 12, i.e., the mantissa part of the operation data having the larger exponential part and an output from the shift circuit 14, i.e., the shifted mantissa part. The operation mode is generated from an operation mode setting section 16 on the basis of signs of the operation data A and B and the operation instruction M. In order to increase operation precision, the adder/subtracter 15 performs an operation including the digits shifted out to the right by the shift circuit 14. These extra digits in the operation are called guard digits. In addition, since a carry sometimes occurs in addition, expansion is performed to upper digits by one digit.
The operation result by the adder/subtracter 15 is supplied to the R terminal of an adder/subtracter 17 and a round controller 18. The round controller 18 controls the operation by the adder/subtracter 17 in accordance with an operation mode. That is, when the adder/subtracter 15 performs addition or when it performs subtraction and the operation result is positive, a data part corresponding to the number of digits of the mantissa part from the first digit is extracted from the output from the adder/subtracter 15, and the lowest digit is rounded. When the adder/subtracter 15 performs subtraction and the operation result is negative, the round controller 18 supplies 0 to the L terminal of the adder/subtracter 17. Under the control of the controller 18, the adder/subtracter 17 executes an operation (L-R) and returns the mantissa part to an absolute expression. An output from the adder/ subtracter 17 is supplied to a leading zero detector 19, and the number of leading zero digits is counted. A shift circuit 20 shifts the output from the adder/ subtracter 17 to the left by the number of leading zero digits. As a result, the mantissa part of the operation result is normalized.
An operation result of the exponential parts is obtained as follows. A multiplexer 21 selects a larger one of the exponential parts of the data A and B. The exponential part selected by the multiplexer 21 is supplied to a subtracter 22 for exponential part correction. The number of digits used to shift the mantissa part to the left in the shift circuit 20 is also supplied to the subtracter 22. The subtracter 22 subtracts the number of left-shifted digits from the exponential part. This subtraction result corresponds to the operation result of the exponential part.
A sign of the operation result is generated as follows. The operation mode setting section 16 outputs, in addition to the operation mode for the adder/ subtracter 15, a sign expected as the operation result. This expection sign is supplied to a sign generator 23. The sign generator 23 generates a sign of the operation result on the basis of the expection sign and the operation mode of the adder/subtracter 17 corresponding to the positive/negative polarity of the operation result of the adder/subtracter 15 detected by the round controller 18.
In the above conventional floating-point representation data adding/subtracting apparatus, an adder/subtracter (in FIG. 1, the adder/subtracter 15) performs addition/subtraction of mantissa parts. In accordance with the operation result, another adder/ subtracter (in FIG. 1, the adder/subtracter 17) performs rounding or operates an absolute value. That is, the operation is performed through the two multi-bit adder/subtracter stages and therefore requires a long period of time.
USPTO Backgrounds
USPTO Backgrounds