In power semiconductor devices, a gate may be formed in a trench that extends downward from the surface of the silicon substrate, for example, a trench MOSFET, a trench insulated gate bipolar transistor (IGBT) and the likes, which include trench gates with different functions. However, due to this structural characteristic, the electrical field intensity at the bottom of the trench reaches maximum level of the device. As the voltage climbs to the avalanche breakdown point, impact ionization, which happens during avalanche breakdown, occurs at the corner of the trench, resulting in avalanche breakdown current. In general avalanche breakdown easily lead to hot carrier effect. When the breakdown occurs close to the gate oxide layer, the hot carrier can be captured and injected into the gate oxide layers, which can damage or rupture the gate oxide layer, leading to long-term reliability problems of the power device. In addition, such trench often limits the device to achieve the high breakdown voltage.
In general, if the avalanche breakdown occurs during the low current levels, the performance of the device may not be significantly hindered when the breakdown occurs at termination region, and there is no concern about safe operating area (SOA) of the device. However if during some special operating period, such as during the unclamped inductive switching (UIS) period, since the inductive current does not change suddenly, the device often bears some relatively large voltage intensity, which is equivalent to the device being in a state of high current avalanche breakdown, the termination region with very limited surface area may not be able to handle the power loss safely and effectively, because the active area of the power device cannot be reduced to increase the termination area, the breakdown in the termination area will become a negative effect on the SOA of the device. Particularly when the trench depth in the active area and the trench depth in the termination area are not equal due to the fact that trenches in the termination area are usually made wider to provide termination functions and/or to facilitate electrical connections to the electrodes within the trenches, and that wider trenches are etched deeper in the same trench etching process, the termination area will breakdown at a low voltage level resulting in initial breakdown of device occurs in the termination area.
In view of the prior art's problems, it is necessary to keep the device in the SOA and at an optimal UIS conditions to optimize the distribution of the electric field intensity of the power semiconductor device by providing a device with substantial the same trench depth in both the active area and termination area.
It is within this context that embodiments of the present invention arise.
USPTO Backgrounds
USPTO Backgrounds