The present invention generally relates to a digital signal processing apparatus for performing digital signal processing operations on a received signal according to a digital signal processing algorithm.
Digital signal processing apparatuses find application in many different kinds of digital systems such as, for example, calculators and digital telephones. Digital signal processing operations are generally performed on multiple-bit operands and may include operand shifts, operand masks, force zero, operand addition, operand subtraction, operand multiplication and overflow detection and correction.
Digital multiplication and accumulation are often required of digital signal processors for many applications. One such application is in the implementation of Recommendation G.721 for use in cordless portable telephony. One function required in Recommendation G.721 is the performance of eight serial multiplications of eight different pairs of first and second multiple-bit binary operands and the accumulation of the multiplication products. In addition, Recommendation G.721 requires, to perform this function, one set of operands to be in floating point format, the second set of operands to be in fixed point format, and the accumulated product to be in fixed point format.
Digital signal processing apparatuses generally perform such operations under the control of operating instructions received from an instruction memory such as an instruction read only memory (IROM). Each instruction provided by the instruction memory corresponds to one operating cycle of the digital signal processing apparatus. The number of operating cycles required by a digital signal processing apparatus to perform its operations is very important and should be kept to the lowest number of operating cycles possible for high efficiency processing.
High efficiency digital signal processing apparatus performance is most desirable where operating speed is of importance, such as in portable equipment which is powered by a depletable power source such as a battery. As the number of operating cycles required by a digital signal processing apparatus to perform its operations is reduced, the power consumption of the depletable power source attributable to the digital signal processing apparatus is correspondingly reduced. This, as a result, extends the time of operation of the portable equipment before battery replacement or battery recharging is necessary.
The present invention provides an improved digital signal processing apparatus for performing a number of different digital arithmetic operations in an efficient manner thus requiring a reduced number of operating cycles. Speed of processing is further enhanced in the preferred embodiment of the present invention by connecting a multiplier and a limit and quantization circuit appropriately within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The number of instruction bits would be required to be increased by prior art digital signal processors in order to accommodate such parallel operations since additional instructional information would be required to control multiple simultaneous (i.e., parallel) operations. Such an increase in instruction bits is avoided by the preferred embodiment of the present invention by connecting the address bus system of the apparatus to the parallel-connected components and conveying instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.
USPTO Backgrounds
USPTO Backgrounds