The present invention relates to digital signal synthesis, and more particularly to a digital signal synthesis technique using a sample clock as low as twice the bandwidth of the signal being synthesized.
A digital signal synthesizer produces a signal by applying a sampled digital representation of the signal to a digital-to-analog converter under control of a sample clock. A high frequency signal F(w) to be synthesized is shown in FIG. 1 in the frequency domain. A sampled representation of the signal F(w) is stored in a data storage device as shown in FIG. 2. The samples from the data storage device are applied to a digital-to-analog converter at a regular rate indicated by the pulse period T which, to avoid aliasing distortion, has a lower limit EQU w.sub.o =2*pi/T.gtoreq.2(w.sub.c +W) (1)
where W is the bandwidth and w.sub.c is the frequency of the signal F(w). FIG. 3 illustrates the frequency domain representation of the signal at the output of the digital-to-analog converter. The desired signal F(w) is surrounded by spectral replicas that repeat in the frequency domain every w.sub.o radians. A low pass filter is used to remove the unwanted spectral replicas, producing the desired signal at the output whose frequency domain representation is equivalent to the signal in FIG. 1. As illustrated such conventional digital signal synthesis requires that the sample clock frequency be greater than twice the highest frequency of the signal in order to assure accurate reconstruction of the signal following digital-to-analog conversion. Synthesis of very high frequencies using such a traditional method uses complex digital hardware and large sample memories because of the very high sample clock rate requirement.
Therefore what is desired is a means for digitally synthesizing high frequency signals without a high sample rate clock and related complex digital hardware.
USPTO Backgrounds
USPTO Backgrounds