The present invention relates to integrated circuit Read Only Memories (ROMs) and to Programmable Logic Arrays (PLAs).
ROMs and PLAs are respectively used in electronic circuitry to store information and to execute logic functions. In particular, they are used in digital equipment, including minicomputers and microprocessor systems. In order to increase the economy of manufacturing ROMs and PLAs and to decrease the size of the overall systems which employ them, it is advantageous to have the greatest possible number of memory bits per integrated circuit chip. Accordingly, it is desirable to decrease the area used for each storage cell, a storage cell being the portion of the integrated circuit which stores a single bit of information. The storage cells are generally arranged in an x-y memory array with decoder circuitry situated along the x-axis of the memory array to select a particular column of storage memory cells and additional decoder circuitry situated along the y-axis of the array to select a particular row of memory cells, such that the intersection of the decoded row and the decoded column yields a particular bit of information to be accessed.
The size of the storage cells within the memory array determines the packing density of cells in either the x of the y direction, i.e. how closely adjacent rows and columns of memory cells can be placed. The spacing is called the "pitch" of the array. It should be noted that the "pitch" of the rows may differ from the "pitch" of the columns depending upon the manner in which the memory array is implemented and the particular design rules which are used.
As used herein, the term "design rules" refers to the rules which define the dimensions of the minimum line width and the minimum line spacing which can be reliably achieved by the technology in use.
While the present invention relates both to ROMs and to PLAs, hereafter the discussion will be substantially limited to ROMs. Those skilled in the art will recognize that the disclosure covers PLAs as well.
Heretofore, ROMs were commonly implemented by using an MOS transistor for each memory cell with the MOS transistor being biased into either a conducting or a non-conducting state. The layout of memory arrays using such prior cells required the presence of contact areas between a metal layer and an underlying epitaxial silicon line. Such metal-to-silicon contacts added to the memory array size, which directly affected the chip size. This was not previously a problem, because the ultimate limitation on the pitch of the rows and columns of cells in the memory array was not usually determined by the size of the memory cells, but by the size of the decoding circuitry located adjacent the x and y edges of the memory array.
It is desirable to maintain the decoder circuitry "on pitch" with the rows and columns of the memory array for reasons well known in the art. Accordingly, it is desirable to reduce the size of the decoder circuitry in order to have the decoders match the pitch of the cells in the memory array, thereby decreasing the ultimate size of the chip. In view of the fact that decoder circuitry requires a number of gates, and each gate requires a number of transistors, the pitch of the decoder circuitry heretofore available was much greater than the pitch in which the cells in the memory array could be arranged. Thus, much of the efforts heretofore made in ROM development involved designs for decreasing the space required by the decoder circuitry.
By way of example, a U.S. patent application entitled POWER GATED DECODING was filed as Ser. No. 044,363 on June 1, 1979 by Roger Green Stewart (RCA 73,062), one of the inventors of the present invention. That particular patent application, which is incorporated herein by reference, describes circuitry having a matrix decoder in which the size of the final stage of the decoder circuitry is reduced with respect to conventional circuitry by using the power supply to individual gates as one of the inputs to those gates. Thus, area is saved in the decoder circuitry which makes the decoder circuitry smaller than it would conventionally be. That helps in placing the decoder circuitry "on pitch" with the cells in the memory array.
The inventors have found a way to increase the effective pitch of the memory cells. In a ROM the increase would be by successive powers of two. However, in PLAs the increase could be by any arbitrary number. Their method can be employed to substantially increase the effective pitch of the memory cells in the array, i.e. for ROMs by a power of 2, a power of 4, a power of 8, etc.
In addition, the inventors have designed a new memory array in which the memory cells can occupy the minimum space allowed by the design rules in use. Thus, the combination of their new memory array with their new method of increasing the effective pitch of memory cells in the array yields a ROM in which the decoder circuitry can be built of conventional devices, yet the completed chip will have many more memory cells than a conventionally built ROM that utilized the same chip area.
USPTO Backgrounds
USPTO Backgrounds