1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of precharging a local input/output line and a semiconductor memory device using the method.
2. Description of the Related Art
A semiconductor memory device includes a plurality of cells to store data. The cells are divided into memory cell array blocks having a predetermined number of the cells. The cells that are arrayed in corresponding blocks are divided into banks to be arrayed.
In the memory cell array blocks, memory cells are arrayed in units of a matrix. A plurality of word lines and a plurality of bit lines intersect with each other. In order to access data, a bank is selected, and one of the memory cell array blocks in the selected bank is accessed. Thereafter, one of the word lines in the selected memory cell array is activated, and the data is applied to a corresponding bit line. A sense amplifier senses, amplifies, and outputs a signal applied to the bit line. In this case, the sense amplifier detects a voltage difference between the bit line and an inverted bit line applied with a reference signal. Where the bit line applied with the data and the inverted bit line applied with the reference signal are arrayed in the same memory cell array block, such a structure is referred to as a folded bit line structure. Where the bit line and the inverted bit line are arrayed in adjacent two memory cell arrays, respectively, such a structure is referred to as an open bit line structure.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device 100 having the open bit line structure. Referring to FIG. 1, the semiconductor memory device 100 includes n memory cell array blocks MCB_1 to MCB_n. Sense amplifiers SA are coupled with bit lines BL and inverted bit lines /BL between the memory cell array blocks. However, outer memory cell array blocks MCB_1 and MCB_n have dummy bit lines DBL. Cells coupled to each dummy bit line DBL do not store data during a normal operation.
For example, when data of the memory cell array block MCB_1 is accessed, data is accessed through bit lines on the right; however, data cannot be accessed through dummy bit lines on the left. Instead, half of the cells of the memory cell array block MCB_k, which is disposed at a center region, are used. Specifically, when the data of the memory cell array block MCB_1 is accessed, the data is accessed through the bit lines on the right of the memory cell array block MCB_1 and bit lines on the left of the memory cell array block MCB_k and is transmitted through corresponding local input/output lines. While data is accessed through bit lines BL on the right of the memory cell array block MCB_k, the data is not transmitted through a local input/output line LIO_kR.
Similarly, when data of the memory cell array block MCB_n is accessed, the data is accessed through bit lines BL on the left of the memory cell array block MCB_n and bit lines BL on the right of the memory cell array block MCB_k disposed at the center region.
As described above, when either of the outer memory cell array blocks MCB_1 or MCB_n is activated, the memory cell array block MCB_k disposed at the center region is also activated. In this case, conventionally, all of the local input/output lines LIO_1, LIO_2L, LIO_2R . . . , and LIO_n are continuously precharged. As a result, when a write command or a read command is continuously performed to write or read data to or from the memory cell array blocks MCB_1 and MCB_k, the local input/output lines LIO_1, LIO_2L, LIO_k−1R, LIO_kL, LIO_kR, and LIO_k+1L are continuously precharged, thereby causing unnecessary power consumption.
In addition, even if the local input/output lines for transmitting data were configured so as not to be precharged, the semiconductor memory device 100 would not operate normally. For example, suppose that data of the memory cell array blocks MCB_1 and MCB_k is read or written and the local input/output lines LIO_1, LIO_2L, LIO_k−1R, LIO_kL, LIO_kR, and LIO_k+1L are not precharged. Under these conditions, the local input/output line LIO_kR is in a floating state. As a result, the semiconductor memory device 100 can not operate normally during the read or write operation.
USPTO Backgrounds
USPTO Backgrounds