In the world of semiconductor electronics, the demand for increased device density and product performance continues to push the need for improved materials systems and the improved ability to configure those systems reliably at smaller dimensions.
With decreasing device size and/or altered device configuration, there is often a need to alter the materials used to make the devices in order to obtain the desired performance. Recently, in the area of dynamic random access memory (DRAM) and embedded DRAM design, there has been a shift to the use of vertical transistors for higher device density. See for example, U.S. Pat. Nos. 6,150,670; 6,177,698; 6,184,091; and 6,200,851, the disclosures of which are incorporated herein by reference. This design shift has resulted in DRAM device layout where the so-called support devices (e.g., transistors making up sensing and/or power supply circuitry) of the DRAM use planar transistors (channel being substantially parallel with the principal plane of the substrate) and the DRAM array cells use vertical transistors (channel being substantially perpendicular to the principal plane of the substrate).
In such configurations, the wordlines from the vertical transistors of the array reside at about the same level as the gate stacks of the support device transistors. With this configuration change, there has been a desire to manufacture the upper portion of the support device transistor gate stack from the same conductive material as is used to manufacture the wordlines. Generally, this has meant that at least the upper portion of the gate conductor (stack) should be made of a material of sufficient conductivity to act as wordline conductor. Some material such as tungsten silicide (WSix) which have been used in the upper portion of the gate stack are generally not considered adequate in such a configuration. Thus, there has been a desire to replace suicide materials with more conductive metals (e.g., to replace tungsten silicide with tungsten metal). For example, the use of tungsten metal is generally deemed necessary for gate conductors in 1 Gb DRAM applications which require lower sheet resistance.
Prior art methods for etching of gate stacks were primarily directed to tunsgten silicide-polycrystalline silicon stacks. Unfortunately, such etch methods typically provide insufficient polycrystalline silicon (polysilicon) etch selectivity for tungsten-polysilicon stacks, especially where (a) tungsten-polysilicon stacks in support devices and tungsten wordlines in the DRAM array stop on different layers (thin gate oxide in the support vs. thicker trench top oxide in the array), and/or (b) where significant topography may be present.
Thus, there is a need for improved etch protocols which perform the etch without punch-through of gate oxide and/or excess erosion of trench top oxide. There is also a need to provide such etch protocols which enable minimization of capital expenditure for additional processing equipment.
The invention encompasses new and improved methods for etching and/or over-etching tungsten stack structures, especially tungsten-polysilicon stack structures. The methods of the invention enable effective etching of tungsten stacks (especially tungsten-polysilicon stacks) even where topographic variation is present across the substrate and/or where other tungsten stacks of different structure are also being etched.
In one aspect, the invention encompasses a method of etching at least one stack structure on a substrate, the stack structure comprising at least one layer of tungsten metal over at least one layer of polycrystalline silicon, the method comprising:
a) providing a first stack of material layers in a first area of the substrate, the first stack comprising a patterned mask over at least one layer of tungsten over at least one layer of polycrystalline silicon wherein portions of the tungsten layer are exposed at first spaces in the patterned mask,
b) contacting the first stack with a first gaseous etchant composition comprising Cl2 and NF3 under reactive ion etching conditions to etch exposed portions of the tungsten layer.
Preferably, the first gaseous etchant further comprises He to improve endpoint control.
In another aspect, the invention encompasses a method of over-etching at least one stack structure on a substrate, the stack structure comprising at least one layer of tungsten metal over at least one layer of polycrystalline silicon, the method comprising:
a) providing a first stack of material layers in a first area of the substrate, the first stack comprising a patterned mask over at least one layer of tungsten over at least one layer of polycrystalline silicon wherein portions of the tungsten layer are exposed at first spaces in the patterned mask, and
b) contacting the stack with a gaseous etchant composition comprising N2, NF3 and O2 under reactive ion etching conditions to etch tungsten at the first spaces selective to the polycrystalline silicon layer.
In another aspect, the invention encompasses a multi-step method for etching a tungsten-polycrystalline silicon stack where a first etch is performed with an etchant having good tungsten etch rate and/or sidewall profile control followed by an over-etch with an etchant having a polycrystalline silicon etch selectivity. The first etchant is preferably a Cl2/NF3/O2 etchant described above. The high selectivity etchant is preferably a N2/NF3/O2 etchant described above. The over-etch may be followed by any desired etch for configuring the polysilicon in the stack (e.g., a conventional polysilicon etch and polysilicon over-etch).
The tungsten-polycrystalline silicon stack preferably further comprises an oxide layer (e.g., a gate oxide) under the polycrystalline silicon layer.
The invention further encompasses methods using etchants of the invention to simultaneously etch a second stack in a second area of the substrate, the second stack comprising a patterned mask over at least one layer of tungsten over at least one layer of oxide, the second stack being substantially free of polycrystalline silicon layers between the tungsten layer and the oxide layer of the second stack, wherein portions of the tungsten layer are exposed at spaces in the patterned mask.
These and other aspects of the invention are described in further detail below.
USPTO Backgrounds
USPTO Backgrounds