Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes, e.g., DLLs, RAMs, processors, and so forth. The various logic blocks are interconnected by a programmable interconnect structure, which typically includes a large number of interconnect lines interconnected by programmable interconnect points (PIPS) and programmable switch matrices.
The interconnect structure and logic blocks are typically programmed by loading a stream of configuration data (a configuration bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The interconnect structure of an FPGA can occupy a large proportion of the device, e.g., about fifty percent of the die area in some FPGAS. To provide flexibility for the implementation of designs, many more routing resources are typically provided than are needed for most designs. For example, a design targeted to an FPGA might use only about four percent of the available interconnect lines in the FPGA. Thus, there are typically a large number of unused interconnect lines present after loading a design into the FPGA. To prevent unwanted coupling effects and noise, the unused interconnect lines are typically pulled to a known logic level. For example, in the FPGAs provided by Xilinx, Inc., the unused interconnect lines are pulled to a logic high value.
One type of fabrication defect that can occur in integrated circuits (ICs) is a “bridging defect”. A bridging defect is an unintentional connection between two interconnect lines (a “short”). Because the dimensions of IC structures are decreasing (including the minimum distance between interconnect lines), bridging defects are becoming more common in ICs. PLDs (including FPGAS) are no exception to this trend.
Clearly, where unused interconnect lines are tied to logic high, a bridging defect between used and unused interconnect lines results in a “stuck at one” fault on the used interconnect line. However, FPGA interconnect lines are typically interconnected through a series of NMOS transistor pass gates. As is well known, NMOS transistors pass a full logic low (zero) value, but only pass a diminished logic high (one) value. If logic in the design is driving a logic low value, but the bridging defect is supplying a logic high value, the stronger logic low value dominates and is reflected in the circuit output. However, undesirable coupling effects and noise are still present, and a low signal on the interconnect line might be undesirably delayed. Therefore, it is still desirable to detect the bridging defect in these circumstances. However, the diminished logic high value makes it difficult to detect the “stuck-at-one” condition in this example by using known Boolean methods.
One method of testing for bridging defects is referred to herein as the “wired-AND” test. In the wired-AND test, all unused interconnect lines are pulled to a logic low value, instead of a logic high value. In this instance, a bridging defect behaves as a “stuck-at-zero” fault. Because a logic low value is undiminished when passing through an NMOS pass gate, a “stuck-at-zero” condition is more easily detected using well known Boolean methods. However, in many commercially available FPGAS, it is difficult to apply a logic low value to the unused interconnect lines, because unused interconnect lines are pulled high by default.
As has been demonstrated, testing for shorts (e.g., bridging defects) in PLDs can be a complicated process when known methods are used. Therefore, it is desirable to provide improved methods for testing for shorts in PLDs.
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