1. Field of the Invention
This invention relates to a data processing system in which a plurality of processors having different processing speeds are connected with a common bus so that they may respectively access the common memory connected with the common bus.
2. Description of the Prior Art
In the conventional data processing system of this kind, the respective processors share the common bus in a time sharing manner and are operated in a common machine cycle.
The transfer of data between the memory and the respective processors is performed during one machine cycle.
FIG. 1 is a time chart illustrating how a conventional synchronous common bus, which is controlled by a common clock signal, is used.
This time chart provides for a data processing system in which three processors A, B and C are connected with a common bus and in which bus occupation demands, data transfers and other operations are performed under the control of a common clock signal. In the operations of the processors A, B and C, the symbols A1, B1 and C1 respectively indicate that the corresponding processors A, B and C are delivering bus occupation demand signals. The symbols A2, B2 and C2 indicate that the processors A, B and C are performing data transfer operations. The symbols A3, B3 and C3 indicate that the processors A, B and C are performing other operations. One machine cycle covers a period from the rise of a clock pulse to the rise of the next clock pulse. Each processor executes a predetermined operation during the machine cycle. Each processor, permitted to use the common bus, occupies the bus for one machine cycle so that data may be transferred between the processor and the memory. These operations will be described below with the aid of FIG. 1. First, the processor B delivers a common bus occupation demand signal (B1) during a certain machine cycle and the use of the common bus is permitted for the processor B in the next machine cycle so that data is transferred (B2). If more than one of the processors deliver demand signals simultaneously, they are so controlled as to be sequentially selected one by one. This type of control system is disclosed in, for example, U.S. Pat. No. 4,232,366 and U.S. Pat. No. 4,229,791.
In each of the systems mentioned above, the processors and the common bus must have the same machine cycle. In the case, however, where each processor is a special-purpose processor which can be used only for its predetermined function, there occurs a difficulty. Namely, since all the processors are special-purpose apparatuses, the operation of one processor performed during its associated machine cycle is different from that of another processor performed during the corresponding machine cycle. One processor may execute a rather simple logic operation while another may perform a complicated operation. Accordingly, different operations are executed at different speeds for their respective machine cycles. If these machine cycles characteristic of the individual processors are to occur at the same period of time, the common machine cycle should be made long enough for the most complicated operation to be completed within one machine cycle. Otherwise, the complicated operations will have to be effected in two machine cycles. With the machine cycle thus determined, it becomes useless for each processor to complete an operation at its maximum speed, that is, in the shortest time possible. This is a considerable drawback of the resultant system.
On the other hand, if the common bus is permitted to be used in an asynchronous manner, that is, if each processor is operated for high speed processing, with its characteristic machine cycle independent of those of other processors, the aforementioned problem is avoided. However, because the processor accesses the common bus as frequently as once during several machine cycles, the overhead in the synchronization of the common bus occupation timing cannot be neglected, so that the performance of the system is degraded.
USPTO Backgrounds
USPTO Backgrounds