The inventive concepts relate to a method of forming a fine pattern for manufacturing a semiconductor device, and more particularly, to a method of forming a fine pattern using block copolymers.
With the increase in the integration degree of semiconductor devices, a planar area occupied by each unit cell has decreased. In response to such a decrease in the planar area, a design rule of a nano-scale critical dimension (CD) has been applied. Accordingly, a new technology for forming a fine pattern, such as a fine contact hole pattern having a nano-scale opening size or a fine line pattern having a nano-scale width, is required.
USPTO Backgrounds
USPTO Backgrounds