Image sensors find applications in a wide variety of fields, including machine vision, robotics, astronomy, navigation, and consumer products. While complementary metal-oxide-semiconductor (CMOS) technology has provided the foundation for advances in low-cost, low-power, reliable, highly integrated systems for many consumer applications, charge coupled devices (CCDs) have been, until recently, the primary technology used in electronic imaging applications. CCDs, however, are high capacitance devices that require high voltage clocks, consume large amounts of power, provide only serial output, and require specialized silicon processing that is incompatible with CMOS technology.
The availability of sub-micron CMOS technology and the advent of active pixel sensors (APS) have made CMOS technology more attractive for imaging applications. Active pixel sensors have transistors within a pixel unit cell to provide amplification and use manufacturing processes that are compatible with CMOS processes. Small pixel sizes, low noise, high speed, and high dynamic range have been demonstrated in such CMOS imagers using a variety of designs. The expected scaling of MOS devices to even smaller geometries can improve the operation and application of most CMOS-based integrated circuits, but such scaling can adversely affect the performance of imagers.
Most CMOS imagers are based on photodiode (PD) pixels because of design simplicity and conformity to conventional CMOS processes. The PD pixel is comprised of four major components. The PD region is responsible for generating and collecting signal charge. Three MOSFETs are required to measure the charge on the diode: (a) a source follower MOSFET, which converts signal charge to an output voltage, (b) a reset MOSFET, which resets the photodiode before charge is integrated on the diode, and (c) a row-select MOSFET, which selects a line for scanned readout.
CMOS image sensors benefit from technology scaling by reducing pixel size, increasing resolution, and integrating more analog and digital circuits on the same chip with the sensor. At 0.25 μm and below, however, digital CMOS technology is not directly suitable for building high quality image sensors. The use of shallow junctions and high doping results in low photoresponsivity, and the use of shallow trench isolation (STI), thin gate oxide, and salicide cause high dark current. Furthermore, signal electrons generated in the silicon should remain in the target pixel. Thermal diffusion and weak electric fields within a pixel's active volume cause signal electrons to wander into neighboring pixels, creating cross talk and related modulation-transfer-function (MTF) loss, and poor color performance. Therefore, it is important that the charge collecting electric fields within the photo region of the pixel be sufficiently deep to match the photon absorption depth. Pixel cross talk is most conspicuous for near-IR and soft x-ray photons that penetrate deep into the sensor, where weak electric fields exist. CMOS arrays show relatively poor charge collection efficiency (CCE) because standard foundry processes use low-resistivity silicon wafers (typically <10 ohm-cm) and are configured for low voltage drive (<3.3 V). Low-resistivity material is necessary to prevent cosmic-ray/radiation-event-triggered CMOS circuit latch-up and ground-bounce problems associated with support CMOS electronic circuitry. Also, low-voltage operation inherent to CMOS, reduces electric field depth. This problem is becoming severe because operating voltages decrease proportionally to feature size. For example, state-of-the-art 0.18-μm CMOS processes operate at only 1.8 V. Design rules and operating voltages will decrease as CMOS technology advances. To compound the problem, the depletion region associated with the photo region decreases as signal charge collects. This technology is discussed in, for example, Janesick., “Charge coupled CMOS and hybrid detector arrays,” SPIE Conference on Focal Plane Arrays for Space Telescopes, paper #5167-1, San Diego (August 2003). Pixel cross talk also increases dramatically as pixel size is reduced.
Pixel transistor leakage also becomes a significant source of dark current. Indeed, in a standard process, dark current due to reset transistor off-current and the follower transistor gate leakage current in a CMOS APS pixel can be orders of magnitude higher than the diode leakage itself. Furthermore, as transistor threshold voltages consume an increased fraction of the reduced operating voltages of sub-micron CMOS circuits, imager dynamic range is reduced.
Low-frequency noise in silicon MOSFETs is dominated by flicker noise. Such noise is commonly known as 1/f noise since the noise spectral density is inversely proportional to frequency. MOSFET flicker noise limits signal levels that can be processed by VLSI devices and circuits. Much effort has been directed to understanding and reducing this noise for better performance in VLSI circuits. In the carrier-density fluctuation model, the noise is explained as a fluctuation of the channel free carriers due to the random capture and emission by interface traps known as slow states. Using this model, the input referred noise is independent of gate bias voltage and the magnitude of the noise spectrum is proportional to the density of the interface trap density.
The problem of fixed pattern noise (FPN) in active pixel sensors is also well known. FPN refers to a non-temporal spatial noise and is due to device mismatches in pixels, color filters, variations in column amplifiers, and mismatches between multiple PGAs and ADCs. FPN can be either coherent or non-coherent. Dark current FPN due to mismatches in pixel photodiode leakage currents tends to dominate the non-coherent component of FPN, especially with long exposure times. Again, as with pixel dark current shot noise, low leakage photodiodes are preferable to reduce this FPN component. Dark frame subtraction is an option, but this tends to increase the read-out time of the sensor. The most problematic FPN in image sensors is associated with easily detectable (or coherent) row-wise and column-wise artifacts due to mismatches in multiple signal paths, and un-correlated, row-wise operations in the image sensor. Coherent FPN offset components can generally be eliminated by reference frame subtraction. Gain mismatches are more difficult to remove since they require time or hardware intensive gain correction. It is worthwhile to improve the circuits in order to reduce residual FPN to the lowest possible value, especially for CMOS imagers for space use when the above problems are related to radiation effects on the change in imager threshold voltages.
Two strategies can be used to address these problems. First, proper guarding can be used for transistor leakage paths that are created by positive charge build up in the oxides. Dedicated layout techniques can be used for pixels as well as for peripheral circuitry. Second, measures can be taken at the circuit level. Analog circuits can be designed to have low sensitivity to transistor parameters that are affected by radiation such as MOSFET threshold voltage.
In addition, device design must permit any FPN specification to remain valid after the device is exposed to radiation. The performance of some conventional FPN correction circuits is impaired by exposure to radiation, yielding higher residual FPN values after radiation exposure. Higher pixel readout rates are also needed. Fast column multiplexing is the readout speed bottleneck for large devices. Since many of conventional fixed pattern noise reduction circuits need signal multiplexing at double the readout rate, maximum readout speeds are limited.
In contrast to bulk CMOS technology, silicon-on-insulator (SOI) CMOS technologies use SOI wafers that include three layers: a single-crystal layer of silicon, upon which integrated circuits are fabricated; a base silicon substrate; and a thin insulator that electrically insulates the single-crystal layer and the substrate. This thin insulator reduces parasitic capacitance typically associated with circuit devices and a substrate in conventional bulk processes. Device operation in SOI-based devices is similar to that of bulk devices, except that transistors and other circuit elements do not share a common substrate. Such SOI processes can produce devices that exhibit lower power consumption and higher processing speeds than conventional bulk devices. Pain et al., U.S. Pat. No. 6,380,572, and Zhang et al., “Building Hybrid Active Pixels for CMOS Imagers in SOI Substrates,” IEEE International SOI Conference (1999), disclose active pixel sensors in which photodetectors are formed in a bulk silicon substrate and circuit elements are formed in a SOI silicon layer. The SOI silicon layer is separated from the bulk silicon by a buried oxide (BOX) layer.
Fabricating CMOS imagers on SOI wafer substrates improves performance. For example, the SOI MOSFETs are isolated from photo regions, allowing high resistivity silicon to be used. In addition, CMOS circuit ground returns for SOT are isolated, eliminating substrate bounce and transient coupling problems. This allows higher operating speeds and lower noise. SOI also makes it easier to passivate surfaces for low dark-current generation because of the planar structure of SOI devices. This advantage, in turn, makes the device more suitable for high-energy radiation environments. Lower FPN and lower power consumption have also been reported for SOI. Some improved imagers based on thinned CMOS SOI substrates and back illumination are described in Williams, U.S. Patent App. Pub. 2005/0205930 that is incorporated herein by reference.
These disclosures address methods of manufacturing sub-micron SOI CMOS imaging devices with deeply-depleted charge collection regions, but they do not address the other limitations of sub-micron CMOS scaling, such as decreased dynamic range and transistor leakage current which can degrade the performance of sub-micron CMOS imaging devices. Furthermore, while SOI-MOS devices can provide several advantages over bulk-CMOS devices, their thin silicon layers can make them unsuitable for imagers. Many semiconductor wafers and die are inefficient at absorbing longer wavelength visible and near infrared (NIR) radiation. As a result of these problems, process modifications are mandatory to obtain practical devices.
FIGS. 1-2 are schematic diagrams of conventional active pixels. With reference to FIG. 1, an active pixel 110 includes a photodiode 111 that produces a current proportional to an incident light intensity. A resulting photocurrent is integrated on a charge-sensing capacitor 113. The charge-sensing capacitor 113 is typically based on a reverse-biased PN junction capacitance associated with the photodiode 111 and other parasitic capacitance. Alternatively, for devices, such as deeply depleted SOI CMOS imagers, which are characteristically low capacitance, the capacitor can be provided as a polysilicon-oxide-polysilicon or metal-oxide-metal capacitor. A MOS transistor 115 operates as a source-follower that buffers the voltage on the capacitor 113 nondestructively to a column line 123. A row select MOS switch 117 activates the source-follower transistor 115 when the particular row is selected by connecting the column current source 125 to the source of the source-follower transistor 115.
Active pixels such as the pixel 110 must be reset in order to permit image updates. There are two conventional ways to reset an active pixel that are typically referred to as a “soft” reset and a “hard” reset. When using a “soft” reset, the voltage at a gate 121 of a reset transistor 119 is raised to a voltage that is no higher than the threshold voltage of the reset transistor (VRTTH) above the drain voltage of the reset transistor 119, typically at VDD. Generally, the voltage at the gate 121 is raised to the same potential as the drain voltage VDD. As the capacitor 113 is charged by the current from the reset transistor 119, the voltage at a sense node 127 increases, decreasing the gate-to-source voltage of the reset transistor 119. This in turn decreases the current from the reset transistor 119, and the rate of voltage rise at the sense node 127 decreases. As the gate-to-source voltage of the reset transistor 119 approaches the threshold voltage VRTTH of reset transistor 119, the current through the reset transistor 119 becomes extremely low, and the voltage at the sense node 127 rises very slowly. The voltage at the sense node 127 approaches approximately (VDD-VRTTH) but it never reaches a steady state because the rate of the voltage change slows. Then, the voltage at the gate 121 is lowered, typically to ground, completing the reset process. At this time, the voltage at the sense node 127 is approximately (VDD-VRTTH).
In hard reset, the gate voltage of the reset transistor 119 is raised to a voltage greater than the drain voltage of the reset transistor by at least VRTTH. Typically, the gate voltage of reset transistor 119 is raised to VDD while the drain voltage of the reset transistor is maintained at a reset voltage VRESET that is lower than (VDD-VRTTH). This drives the reset transistor 119 into the triode region, thereby causing the transistor 119 to behave like a resistor. The reset transistor 119 and the sense capacitor 113 behave like an RC circuit, and the sense node voltage approaches VRESET with an RC time constant τ=RONC, where RON is the ON resistance of the reset transistor 119 and C is the value of the sense capacitor 113. Since the sense capacitance is on the order of a few femtofarads and the ON resistance is a few tens of kohms, the time constant is on the order of only a nanosecond. Thus, the sense node typically reaches the full steady-state value VRESET within a few nanoseconds, which is much shorter than typical reset period of many microseconds. Then, the voltage at the gate 121 is lowered typically to ground, completing the reset process. At this time, the sense node 127 is reset to approximately VRESET.
It is well known that by using a “soft” reset, one can realize a lower reset noise than that obtained using a “hard” reset. Thus, it is desirable from signal-to-noise ratio and sensitivity point of view to use “soft” reset. However, since the sense node never reaches a steady state value using soft reset, the voltage of the sense node is actually reset to different voltages depending on the initial condition on the sense node. This leads to substantial image lag. Even with popular double sampling methods, a significant amount of image lag remains, which gives a blurry picture of moving objects. Furthermore, it is well known that by using a “hard” reset, one can substantially eliminate the image lag because the voltage to which the pixel is reset is always VRESET. However, the disadvantage of using a “hard” reset is that higher reset noise is realized. Therefore it is desirable to provide an imaging reset methodology and/or circuitry for an imager that provide a resetting capability, wherein reset noise is significantly reduced, image lag is substantially eliminated, a desirable signal-to-noise ratio is realized, and/or the imager realizes a desirable sensitivity.
Another major barrier in deep-submicron CMOS APS design is the significant reduction of available output swing with the aggressive reduction of power supply voltage. Reducing power supply voltages with APS impacts available SNR and dynamic range because of the lower allowable signal voltages and larger voltage fluctuations due to noise currents.
FIGS. 3A-3B illustrate the limited available output voltage swing VOUT for a conventional APS using NMOS transistors based on an input voltage swing VIN. Threshold voltage contributions from transistors M1 and M2 contribute VTM1 and VTM2 respectively, and at an output node the two threshold drops combined can contribute approximately 1.6 V, which for a 3.3 V process is approximately 50 percent of the output dynamic range. To increase the voltage swing and dynamic range of a conventional APS, bootstrapped reset pulses can be used. However, bootstrapping techniques result in hot-carrier reliability issues in subquarter micron technology and significantly reduce circuit lifetime.
Alternatively, PMOSFETs can be used as reset transistors. FIGS. 4A-4B illustrate APS performance using a PMOSFET as a reset transistor. By replacing the NMOS reset transistor of FIG. 3A with a PMOS transistor, output dynamic range is increased by the threshold drop associated with transistor M1. However, the use of PMOSFETs in bulk CMOS processes requires an extra well to be included in the pixel, enlarging pixel size and making the fill factor lower, both of which are undesirable. This drawback, however, can be partially compensated with more aggressively scaled technology to further reduce device size. Applying such techniques on a silicon-on-insulator (SOI) substrate allows the APS to function at lower supply voltages. However, further reduction in power supply voltage remains difficult, because the methods used only increase the input available swing of the pixel, but the output swing is still limited by the turn-on condition of the in-pixel amplifier, normally a source follower, that causes an extra voltage reduction by VT+VDsat, wherein VT is the threshold voltage and VDsat and is the saturation drain voltage.
In view of these and other shortcomings of existing imagers and imaging methods, improved active pixel sensors, manufacturing processes, and imaging methods are needed.
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