The present invention relates to a microprocessor and, more particularly, to an improvement in an interrupt vector generation unit in a microprocessor for generating an interrupt vector in response to an interrupt request.
As is well known in the art, in order for a microprocessor or central processing unit (CPU) to perform an operation requested by a peripheral unit operating in asynchronism with the CPU, the CPU handles such an operation as an interrupt operation. Specifically, the peripheral unit, when requesting a data processing operation from the CPU, supplies an interrupt request signal to the CPU. In response thereto, the CPU suspends the execution of a current program and then initiates an interrupt program routine corresponding to the requested data processing operation.
There are provided a plurality of peripheral units in general. The CPU is therefore required to distinguish which peripheral unit has issued an interrupt request. For this purpose, a plurality of interrupt vectors are provided correspondingly to the peripheral units. When one of the peripheral units issues an interrupt request, the interrupt vector associated thereto is generated and supplied to the CPU. The CPU thus distinguishes the interrupt program routine to be initiated by the associated interrupt vector.
There are two types of techniques for generating the interrupt vector, the first one of which is to generate the interrupt vector outside of the CPU and the second one of which is to generate it inside of the CPU.
Referring to FIG. 1, there is shown a microprocessor system of the first type. A CPU 1 is interconnected to an interrupt controller 3 via address and data buses 6 and 7. The controller includes an interrupt request control unit 31 supplied with interrupt request signals IQR-1 to IQR-m from peripheral units 10-1 to 10-m. When one or more peripheral units 10 issue the interrupt request, i.e., when one or more interrupt request signals IQR is changed to an active level, the interrupt request control unit 31 selects one of the active interrupt signals IRQ in accordance with the priority levels of the interrupt requests and then produces interrupt level information INTL representative of the selected interrupt request. The interrupt level information INTL is supplied to an interrupt vector generation unit 32 which, in response thereto, generates an interrupt vector IV corresponding to an interrupt operation of the selected peripheral unit 10. The interrupt vector IV is supplied to an output controller unit 34 which in turn outputs it on the data bus 7 when an enable signal supplied thereto takes an active level.
The interrupt level information INTL is further supplied to an interrupt receiving unit 11 of the CPU 1 through a level hold unit 33. The interrupt receiving unit 11 accepts the interrupt request indicated by level IV only when a mask bit of a status register (not shown) corresponding to the supplied interrupt level stores non-mask information and an execution unit 13 is performing a program operation whose level is lower than the supplied interrupt level. The interrupt receiving unit 11 produces interrupt status information AST representing whether or not the supplied interrupt request is accepted and further transfers, when accepting the interrupt request, the interrupt level IV onto the address bus 6. In the case of accepting the interrupt request, the CPU 1 initiates a bus cycle for fetching the interrupt vector.
The interrupt status information AST is decoded by a decoder 4. When the status information AST represents the acceptance of the interrupt request, the decoder 4 changes its output to an active level to activate a decoder 5. The decoder 5 thereby decodes the interrupt level INTL supplied via the address bus 6 and then changes one of interrupt acknowledge signals IACK connected respectively to the peripheral units 10 to an active level to inform the acceptance of the interrupt request. The ORed output of the acknowledge signals IACK is supplied to the output control unit 34 to allow it to output the interrupt vector IV onto the data bus 7. The CPU-1, which is in the interrupt vector fetch bus cycle, thus fetches and supplies the interrupt vector IV to an execution unit 13 through a vector input unit 14. An interrupt program operation is thus initiated.
Referring to FIG. 2, there is shown another microprocessor system of the second type in which the same constituents as those shown in FIG. 1 are denoted by the same reference numerals to omit the further description thereof. In this system, an interrupt vector generation unit is incorporated in the CPU 1. In order to synchronize the generation between the interrupt vector IV and the interrupt acknowledge signal IACK, there is provided a vector control unit 9 which is activated by the active level of at least one of the interrupt request signals IQR and produces an active level vector-enable signal AV in synchronism with the ORed acknowledge signal. The vector generation unit 12 is thereby activated to give the execution unit 13 the interrupt vector IV.
Since the CPU 1 has the interrupt vector generation unit 12, the interrupt vector fetch cycle is not required, which would be otherwise required in the system of FIG. 2. The firmware of CPU 1 of FIG. 2 is therefore simplified compared to that of FIG. 1.
Although two types of the microprocessor systems according to the prior art are described above, each of them is based on a technical concept that the execution unit 13 receives the interrupt vector IV simultaneously with the interrupt acknowledge signal IACK being returned to the peripheral unit 10. For this reason, the initiation of the interrupt program operation is delayed. Moreover, hardware such as the decoders 4 and 5 for producing the active level interrupt acknowledge signal is required and the interrupt receiving control unit 11 is required to produce the interrupt status information AST and transfer the interrupt level INTL.
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USPTO Backgrounds