1. Field of the Invention
This invention relates to a clock conditioning circuit and, more particularly, to a device and method for disconnecting initial clock pulses from a load unit and connecting subsequent clock pulses to the load unit.
2. Description of the Relevant Art
There is almost an infinite variety of load units. For operation, some load units require an input of clock pulses. The clock pulses perform many tasks, one of which is to synchronize operation of the load unit to that of possibly other connected load units. Thus, a popular load unit includes a microprocessor (or "CPU"). Current microprocessors operate at high speeds, often exceeding several hundred megahertz (MHz). Instructions, addresses and data are sent through the microprocessor at speeds synchronized with the input clock pulses.
A conventional way in which to form the clock pulses and connect those pulses to a microprocessor load is shown in the microprocessor clocking system 10 of FIG. 1. System 10 includes a high speed (e.g., several hundred MHz) crystal 12. Crystal 12 defines a relatively stable frequency of pulses sent to oscillator driver 14. Oscillator driver 14 outputs a fundamental crystal frequency, denoted as oscillator signal ("OSC"). The fundamental crystal frequency can be divided or further synchronized with a clock synchronizing signal ("CSYNC") to produce a microprocessor clocking signal denoted as CLK. Core logic 16 is used to perform all logical operations necessary to synchronize the fundamental crystal frequency of OSC signal and produce a clock signal CLK acceptable by microprocessor 20. A suitable description of conventional core logic 16 and the various logical operations contained therein, is described in Singh, et al., 16-Bit and 32-Bit Microprocessors, (Prentice-Hall, Inc., 1991), pp.120-122 (herein incorporated by reference).
As shown in FIG. 1, oscillator driver 14, core logic 16 and CPU 20 are activated upon receiving a positive voltage (i.e., power supply voltage) denoted as Vcc. The power supply voltage applied to oscillator driver 14 creates the oscillator signal and subsequently creates the clock signal input to CPU 20. Due to the somewhat large loading capacitance of oscillator driver 14, core logic 16 and especially CPU 20, the power supply voltage cannot instantly achieve full power (operational) levels. As shown in FIG. 2, power supply voltage ramps up to its operational or steady state value over a time duration from time t.sub.0 to time t.sub.1. After time t.sub.1, depending upon capacitive loading, the power supply voltage may overshoot the steady state voltage value illustrative of an underdamped condition between times t.sub.1 and t.sub.2. Most manufacturers prefer a fast ramp-up time to allow quick turn on of a load device. However, during turn on, i.e., between times t.sub.0 and t.sub.1, sporadic clocking errors can occur. Further, after time t.sub.1, as a penalty to quick turn on, underdamping often occurs. The sporadic clocking occurs as a result of noise during ramp on, and underdamping presents itself as a "ringing" of the power supply just prior to it achieving steady state value (i.e., steady state occurring after time t.sub.2).
In order to minimize cost and maximize manufacturability, most manufacturers embody as much of the clocking system as possible on a single monolithic chip. Thus, oscillator driver 14, core logic 16, CPU 20, and power supply conductors, as well as clock signal conductors, are embodied upon a single monolithic substrate. The power supply conductor carrying power supply voltage is routed throughout the monolithic chip, oftentimes proximate to core logic 16 and the clocking signal conductors. Any noise caused by ramp-up of the power supply can present itself to adjacent conductors and cause problems in the operation of CPU 20. An illustrative example of this occurrence is shown in relation to FIGS. 2 and 3.
FIG. 3 illustrates the clock signal output from core logic 16 to CPU 20. The clock signal is shown during the time of initial power supply turn on, between times t.sub.0 and t.sub.1. The clocking signal operates in the megahertz (MHz) range with a time period generally less than 100 or 200 nanoseconds (ns). Numerous clock cycles can occur during the turn on period, causing inaccurate or indeterminate clocking transistions prior to the operational power supply voltage. After time t.sub.1, the clock signals may reach operational levels, yet the high and low levels might "ring" at the transition edges as shown in FIG. 4. Indeterminate transitions and/or ringing of the clock signal during ramp-up and overshoot of the power supply prior to the supply achieving steady state causes inappropriate operation of CPU 20.
If the control clock contains transient noise spikes, those spikes can deleteriously affect initial operation of CPU 20. For example, many conventional CPUs utilize a phase-locked loop to receive the clock signal. The phase-locked loop functions to lock upon the incoming clock signal frequency using a voltage controlled oscillator and a feedback arrangement of common design. Other CPUs may use a one-shot of fixed duty cycle to receive the clock signal. The one-shot triggers upon the rising edge of the incoming clock signal and maintains an astable state for a fixed duration. In either instance, either a phase-locked loop configuration or a one-shot configuration, CPU 20 relies upon a well-defined transition edge of the incoming clock signal, and also relies on the clock signal maintaining a relatively constant or steady high and low voltage magnitude. If the transition edge or the high and low voltage magnitudes vary as a result of cross-talk between an underdamped power supply voltage and the clock signal, then the CPU internal clocking may falsely trigger and/or fail to lock upon the true clock frequency. Instead of operating at a constant, true clock-rate, CPU 20 may falsely transition to improper clock rates during initial ramp-up of the power supply voltage. It would therefore be highly desirable to ensure that CPU 20 does not experience spurious clock changes during initial ramp-up of the connected power supply. It would be further advantageous to achieve said clock conditioning without causing propagation delay of the clock signal between core logic 16 and CPU 20. Absent propagation delay, any changes at the output of core logic 16 will be immediately presented to CPU 20. It would still be further advantageous to perform clock conditioning with minimal power loss and with minimal component cost.
USPTO Backgrounds
USPTO Backgrounds