1. Field of the Invention
The present invention relates to a technology for automatically estimating a value to be assigned for automatic layout processing, which determines the arrangement of cells and the arrangement of the wiring connecting the cells constituting a logically designed electronic circuit.
2. Description of the Related Art
At present, electronic circuits are, in general, designed using CAD. In CAD, elements or components that will be functional or logical units of an electronic circuit are registered as basic elements (cells) in a library. Therefore, logical design is basically performed by selecting the necessary cells registered in the library and connecting the selected cells. Connection of the cells can be achieved by connecting pins contained in each cell.
The result of the logical design is converted into a net list (logical circuit data). The net list is written as an interconnection of the cells registered in the library. By using the net list, automatic layout processing is performed, and verification is performed after completion of the processing.
FIG. 1 is a diagram showing the flow of the automatic layout processing.
In the automatic layout processing, as shown in FIG. 1, each of the following steps is performed as a design phase in the following order: determination of cell arrangement (step S1); estimation of the delay of the electronic circuit and timing optimization in order to ensure that the delay is within a range required for normal operation of the circuit (step S2); clock tree synthesis (CTS) (step S3); timing optimization after CTS (step S4); wire routing (step S5); and timing optimization after the routing (step S6). If a point to be improved is found as a result of the timing optimizations in steps S2, S4, or S6, the operation returns to the design phase prior to the point needing improvement, and the designing in the phase is performed once again. By doing this, verification (sign-off) is conducted on electronic circuits after an operation check by the automatic layout processing. The “preCTS”, “postCTS”, and “postRoute” shown in FIG. 1 denote the design phase performed before CTS, the design phase performed after CTS, and the design phase after wire routing, respectively.
The timing optimization in step S2 is the design phase performed before CTS (preCTS). Since CTS has not been performed, the route between the cell (clock root) 21 that will be the synthesis root of the clock and the cell at which the clock ultimately will arrive (synch cell) is yet unknown in the design phase, as shown in FIG. 2. For that reason, the clock delay and the clock skew, which is the lag in the arrival time of the clock, are also unknown.
Currently, crosstalk (Xtalk) noise has been increasing due to the miniaturization of wiring lines, which influences signal delay. In the timing optimization in step S4, since it is before wire routing being performed, coupling capacity generated between adjacent wires cannot be calculated. As shown in FIG. 3, after wire routing, since wiring routes are determined, the coupling capacity present between the wire connecting cell 31 and cell 32 and the wire connecting cell 35 and cell 36, and the coupling capacity present between the wire connecting cell 32 and cell 33 and the wire connecting cell 37 and cell 38 can be calculated. However, those coupling capacities cannot be calculated before the wire routing.
As described above, in an automatic layout tool, which is application software for automatic layout processing, a designer has to manually assign (set) an estimated value for the clock skew, Xtalk delay for preCTS, and Xtalk delay for postCTS, as shown in FIG. 4. It is desirable that those estimated values (timing margins) are close to the actual values. This is because a value estimated on the basis of a harsher perspective than the actual value makes the design more difficult than necessary, and a value estimated based on a more lenient perspective than the accrual value is likely to cause iteration, i.e., performance of the previous design once again.
The current condition is such that even a designer with high skill has to conduct troublesome operations in order to assign a necessary estimated value with such automatic layout processing. Thus, it is considered to be important for a designer to be able to easily assign proper estimated values.
USPTO Backgrounds
USPTO Backgrounds