1. Field of the Invention
The present invention relates to a semiconductor circuit designing technique and a semiconductor device.
2. Description of the Related Art
In accordance with an enhancement in integration and an increase in scale of an LSI (Large Scale Integration), flat layout designing of collectively processing the entire semiconductor circuit is becoming difficult. Because of this, such a designing method has been applied that blocks are made on a lower level of hierarchy by dividing the inside of an LSI according to the function or the like, and the layout is designed for each of the blocks. This hierarchical layout has realized processing of large-scale data, whereas giving rise to the necessity of taking into account an influence given by external parts across the boundaries of the blocks.
FIG. 12 shows a wiring 1202 on an inner side of a block 1200 and a wiring 1203 on an external side thereof. A wiring 1206 is a wiring for connecting the outside and the inside of the block 1200. There is no physical pattern existing on a boundary of the block 1200. A parasitic wiring capacitance (cross coupling capacitance) 1204 exists between the internal wiring 1202 and the external wiring 1203. In designing the lower level of hierarchy, the wiring 1202 inside the block 1200 is designed. In designing an upper level of hierarchy, the wiring 1203 outside the block 1200 is designed. When the lower level of hierarchy is designed first, the calculation of the wiring capacitance 1204 is difficult since the existence of the external wiring 1203 is not known. When, on the other hand, the upper level of hierarchy is designed first, the calculation of the wiring capacitance 1204 is difficult since the existence of the internal wiring 1202 is not known. Moreover, the calculation of the influence of a crosstalk noise between the internal wiring 1202 and the external wiring 1203 is also difficult.
FIG. 13A is a top view of a semiconductor circuit showing a wiring 1302 on an internal side of a block 1300 and a wiring 1301 on an external side thereof, and FIG. 13B is a cross sectional view taken along the II—II line in FIG. 13A. The block 1300 is provided on a semiconductor substrate 1311. The external wiring 1301 passes over the block 1300. A parasitic wiring capacitance 1312 exists between the external wiring 1301 and the internal wiring 1302. In this case, too, the calculation of the wiring capacitance 1312 is difficult. The calculation of the influence of a crosstalk noise between the external wiring 1301 and the internal wiring 1302 is also difficult.
The following methods are conceivable for the layout designing in the above-described case.
(1) To prepare a region with no wiring on the internal side of the block boundary in order to make a circuit inside the block not easily susceptible to the influence of the upper level of hierarchy
(2) To extract arrangement and wiring information that a specific range on the internal side of the block boundary has, from data on the blocks of the lower level of hierarchy, and capacitance value calculation and crosstalk noise verification are carried out on the upper level of hierarchy
(3) To prohibit the use of wirings passing over the blocks by a design rule
However, the following problems arise in accordance with miniaturization of technology.
(1) an increase in regions which are not usable in arrangement and wiring processing
(2) an increase in data amount required to be extracted
FIG. 14 is a flow chart showing a hierarchical designing procedure of a semiconductor circuit according to a prior art. This designing is based on CAD (computer-aided design).
In Step S1401, a floor plan is designed, in which the position, size, external wirings, and so on of blocks are roughly determined on an upper level of hierarchy. Next, in Step S1402, power consumption of the upper level of hierarchy is estimated. Next, in Step S1403, power source wirings are laid on the upper level of hierarchy. At this time, the thickness of the power source wirings is determined depending on the aforesaid power consumption. Next, in Step S1405, it is checked whether or not there exists any unprocessed data. When there exists an unprocessed lower level hierarchical data, Step S1407 is initiated while Step S1421 is initiated when no unprocessed data exists. Step S1406, which includes Steps S1407 to S1416, is for processing the inside of blocks of the lower level of hierarchy.
In Step S1407, power consumption is estimated. Next, in Step S1408, power source wirings are laid. At this time, the thickness of the power source wirings is determined depending on the above-mentioned power consumption. Next, in Step S1409, the arrangement and wiring of cells in a block are performed. Next, in Step S1410, a resistive component and a capacitive component (RC) are extracted. At this time, the RC extraction is not accurate since it is performed assuming a certain state as boundary conditions of the block. Next, in Step S1411, delay time is calculated based on the above-mentioned resistive component and capacitive component. Next, in Step S1412, a crosstalk noise is verified. At this time, this verification is not accurate since the verification is performed assuming a certain state as the boundary conditions of the block. When the verification result indicates that the crosstalk noise gives an adverse effect, a crosstalk noise error is outputted. Next, in Step S1413, timing of a circuit inside the block is verified based on the above-mentioned delay time. When the verification result indicates that the timing is not within a prescribed value range, a timing error is outputted.
Next, in Step S1414, it is checked whether or not there exists any crosstalk noise error or timing error. When an error exists, Step S1415 is initiated while Step S1416 is initiated when no error exists. In Step S1415, the arrangement, wiring, and so on of the cells are corrected and the processing from Step S1410 is processed again. The above processing is repeated until no error is left. When no error is left, information relating to the block is extracted in Step S1416. For example, information on the arrangement, wiring, and so on that a specific range on the internal side of the boundary of the block has is extracted. Thereafter, the procedure returns to Step S1405. When there exists any other unprocessed block, the above processing in Step S1406 is repeated. When the processing for all the blocks has been completed, Step S1412 is initiated. Steps S1421 to S1430 are for design processing of the upper level of hierarchy.
In Step S1421, the information on the blocks of the lower level of hierarchy is read. Next, in Step S1422, the power source wirings are laid in detail. Next, in Step S1423, the arrangement, wiring, and so on of the blocks and the cells are performed in Step S1423. Next, in Step S1424, a resistive component and a capacitive component (RC) are extracted. At this time, the arrangement and wiring information in the specific range on the internal side of the boundaries of the blocks, which is extracted in Step S1416, is merged together to extract the RC. Next, in Step S1425, delay time is calculated based on the above-mentioned resistive component and capacitive component. Next, in Step S1426, a cross talk noise is verified. At this time, the arrangement and wiring information in the specific range on the internal side of the boundaries of the blocks, which is extracted in Step S1416, is merged together to execute the verification, and a crosstalk noise error is outputted according to the verification result. Next, in Step S1427, timing of a circuit of the upper level of hierarchy is verified based on the above-mentioned delay time, and a timing error is outputted according to the verification result.
Next, in Step S1428, it is checked whether or not there exists any crosstalk noise error or timing error. When there exists any error, Step S1429 is initiated while Step S1431 is initiated when there exists no error. In Step S1429, it is checked which of the lower level of hierarchy or the upper level of hierarchy causes the error. When the upper level of hierarchy causes the error, Step S1430 is initiated. When the lower level of hierarchy causes the error, the processing from Step S1409 is repeated to redesign the inside of the blocks. For example, when the assumption of the conditions of the block boundaries in Steps S1410 and S1412 proves to be wrong to a great degree, the inside of the blocks is redesigned.
In Step S1430, the arrangement, wiring, and so on of the blocks and the cells are corrected, and the processing from Step S1424 is repeated. In Step S1428, when it is judged there exists no error, Step S1431 is initiated to generate a mask pattern of each layer of a semiconductor device.
The above-described hierarchical designing poses the following problems.
(1) The wiring capacitance value cannot be determined accurately since the conditions of the block boundaries are not fixed until the arrangement and wiring of the inside of the blocks of the lower level of hierarchy are finished.
(2) The influence due to the wirings only passing over the blocks has to be determined after the layout of the upper level of hierarchy.
(3) Due to a trouble occurring in the block boundaries, the processing from Step S1409 sometimes has to be repeated after Step S1429 in FIG. 14 to correct the blocks of the lower level of hierarchy again and to perform the error check again on the upper level of hierarchy.
USPTO Backgrounds
USPTO Backgrounds