1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining process layer conformality.
2. Description of the Related Art
Semiconductor integrated circuit devices are employed in numerous applications, including microprocessors. Generally, the performance of a semiconductor device is dependent on both the density and the speed of the devices formed therein. A common element of a semiconductor device that has a great impact on its performance is a transistor. Design features, such as gate length and channel length, are being steadily decreased in order to achieve higher package densities and to improve device performance. The rapid advance of field effect transistor design has affected a large variety of activities in the field of electronics in which the transistors are operated in a binary switching mode. In particular, complex digital circuits, such as microprocessors and the like, demand fast-switching transistors. Accordingly, the distance between the drain region and the source region of a field effect transistor, commonly referred to as the channel length or gate length dimension, has been reduced to accelerate the formation of a conductive channel between a source and a drain electrode as soon as a switching gate voltage is applied and, moreover, to reduce the electrical resistance of the channel.
A transistor structure has been created where the longitudinal dimension of the transistor, commonly referred to as the width dimension, extends up to 20 xcexcm, whereas the distance between the drain and source regions, i.e., the channel length, may be reduced down to 0.2 xcexcm or less. As the channel length is reduced to obtain the desired switching characteristic of the source-drain line, the length of the gate electrode is also reduced.
Transistors are formed through a series of steps. An exemplary transistor structure 100 is described in reference to FIGS. 1A and 1B. Initially, shallow trench isolation regions 105 are formed in a substrate 110 by etching trenches into the substrate 110 and, thereafter, filling the trenches with an appropriate insulating material (e.g., silicon dioxide). Next, a gate insulation layer 115 is formed over the substrate 110 between the trench isolation regions 105. This gate insulation layer 115 may be comprised of a variety of materials, but it is typically comprised of a thermally grown layer of silicon dioxide. Thereafter, a gate electrode 120 for the transistor 100 is formed by forming a layer of gate electrode material, typically polysilicon, above the gate insulation layer 115, and patterning the layer of gate electrode material using known photolithography and etching techniques to thereby define the gate electrode 120. Of course, millions of such gate electrodes 120 are being formed across the entire surface of the substrate 110 during this patterning process.
To form active regions of the transistor 100 a series of implants are performed, whereby a variety of dopant atoms may be implanted into the substrate. Typically, a halo implant is performed to reduce short channel effects arising from the small dimensions of the transistor and a lightly doped drain (LDD) or extension implant is performed is performed to reduce the junction capacitance of the transistor 100. Thereafter, a relatively high concentration of dopant atoms may be implanted into the substrate to complete the formation of the source/drain regions. This latter implant is sometimes referred to as a source/drain implant. To control the location of some of the implant regions, spacers 125 are formed about the gate electrode 120. To form the spacers 125 a layer 130 of insulating material (e.g., silicon dioxide) is formed over the substrate 110 and gate electrode 120. The insulting layer 130 is anisotropically etched until the substrate 110 is exposed, leaving a portion of the insulating layer 130 adjacent the gate electrode 120 intact to form the spacers 125. Subsequently, a second set of spacers (not shown) may be formed over the spacers 125 to define the boundaries for the source/drain implant. Typically, the second set of spacers (not shown) are formed using a layer of silicon nitride in the same manner.
The eventual width of the spacers 125 is determined, at least in part, by the thickness of the portion of the insulating layer 130 disposed over the sidewalls 135 of the gate electrode 120. The time required to complete the etch process to form the spacers 125 depends on the thickness of the portion of the insulating layer 130 disposed over the substrate 10 and top surface 140 of the gate electrode.
The conformality of a layer, such as the insulating layer 130 is defined as the ratio between the sidewall deposition thickness xe2x80x9cXxe2x80x9d (ie., perpendicular to the substrate 110) to the flat area deposition thickness xe2x80x9cYxe2x80x9d (i.e., parallel to the substrate 110). The conformality of a deposited layer varies with respect to the particular material being deposited and the density of the underlying features. A process layer deposited over a low density topography typically exhibits a higher degree of conformality. The conformality of the layer ultimately affects the width of the spacers 125. Typically, conformality is studied during the process characterization phase, not during actual production runs of the device being manufactured. Commonly used examination techniques to determine deposited film confornality are destructive, cross-section techniques.
Normal variation in the deposition process during production runs can affect the conformality of the deposited layer. Because no in-line conformality monitoring is available, the variation propagates through the other processing steps. For example, a variation in the conformality of the insulating layer 130 can cause a variation in the width of the spacers 125 and a corresponding variation in the size and spacing of the implant regions. Variations in the implant regions can induce variations in the performance of the completed devices. Generally, increased variation reduces throughput, yield, and profitability.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for determining conformality of a process layer. The method includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer overlying the grating structure with a light source; measuring light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile; and determining conformality of the process layer based on the reflection profile.
Another aspect of the present invention is seen in a metrology tool adapted to receive a wafer having a grating structure and a process layer formed over the grating structure. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile. The data processing unit is adapted to determine conformality of the process layer based on the generated reflection profile.
USPTO Backgrounds
USPTO Backgrounds