Charge pumps are well known in the art. Charge pumps are electrical circuits which receive a low voltage as an input and generate a high voltage as an output. Charge pumps are used in non-volatile memory arrays to generate the necessary high voltage for erase or programming operations.
Referring to FIG. 1 there is shown a block level diagram of a charge pump 10 of the prior art. A typical charge pump 10 of the prior art comprises a first stage 12 for receiving the input voltage Vcc and for generating an output voltage which is supplied to a plurality of serially connected alternating pumps 20a and 20b. Thus, the output of the initial stage 12 is supplied as an input to a first stage 20a to which clock signal C1 and C2A are supplied. The output of the first pump stage 20a is supplied as an input to the second pump stage 20b to which clock signals C2 and C1A are supplied. The output of the second pump stage 20b is then supplied as input to yet another serially connected first pump stage 20a and so on. The last stage 16 of the charge pump 10 is either the charge pump 20a or 20b with the output as the output of charge pump 10.
Referring to FIG. 2, there is shown a detailed circuit diagram of the initial stage 12 of the charge pump 10 of the prior art. The initial stage 12 simply comprises an NMOS transistor having its gate connected to one of the terminals to the input voltage Vcc. The output of the initial stage is the second terminal of the NMOS transistor.
Referring to FIGS. 3 and 4, there is shown a detailed circuit diagram of the charge pump stages 20a and 20b. Each of the pump stages 20a and 20b are identical in circuit. The only difference between the stages 20a and 20b is the clock signals supplied thereto. Thus, as shown in FIG. 3, the charge pump stage 20a comprises an NMOS transistor 22a having a first terminal and a second terminal with a channel therebetween. A gate controls the flow of current between the first terminal and the second terminal. The first terminal of the NMOS transistor 22a is connected to the input. A second NMOS transistor 24a also comprises a first terminal and a second terminal with a channel therebetween. A gate controls the flow of current between the first terminal and the second terminal. The first terminal of the second NMOS transistor 24a is also connected to the input. The second terminal of the first NMOS transistor 22a is connected to the gate of the second NMOS transistor 24a. The second terminal of the second NMOS transistor 24a is connected to the output. The charge pump stage 20a also comprises a third NMOS transistor 26a having its first and second terminals connected together to receive the clock signal C1. The gate of the third NMOS transistor 26a is connected to the output and to the gate of the first NMOS transistor 22a. Finally, the first pump stage 20a also comprises a fourth NMOS transistor 28a. The first and second terminals of the fourth NMOS transistor 28a are connected together and receive the clock signal C2A. The gate of the fourth NMOS transistor 28a is connected to the gate of the second NMOS transistor 24a.
In like manner, the second pump stage 20b comprises a first, a second, a third, and a fourth NMOS transistors 22b, 24b, 26b, and 28b, respectively, and all as connected in the manner for the first charge pump stage 20a, shown in FIG. 3. As previously discussed, the only difference between the second charge pump stage 20b and the first charge pump stage 20a is the clock signal. In the second charge pump stage 20b, clock signal C2 is supplied to the first and second terminal of third NMOS 26b. A clock signal C1A is supplied to the first and second terminals of the fourth NMOS transistor 28b.
The charge pump 10 of the prior art receives two clock signals C1, C2, C1A, C2A whose waveforms are shown in FIG. 5.
The problem with the charge pump 10 of the prior art is that with either the first pump stage 20a or the second stage 20b as the last stage 16 of the charge pump 10, the voltage output of the charge pump 10 with a load has a swing in the voltage output, as shown in FIG. 6.
USPTO Backgrounds
USPTO Backgrounds