The present invention relates generally to the electronic arts and, more particularly, to tunnel field-effect transistors (TFETs) and their fabrication.
Tunnel field-effect transistors are similar in structure to metal oxide semiconductor field-effect transistors (MOSFETs), but require asymmetric source and drain regions that have opposite conductivity types. One conventional TFET device structure contains a P-I-N (p-type-intrinsic-n-type) junction, where the electrostatic potential of the intrinsic region is controlled by a gate terminal. By forming TFET heterojunctions using different materials, TFET performance can be improved.
TFETs have the potential to serve as a viable option for extremely low power applications. However, given the TFET requirements of different source and drain polarities, it can be challenging to form the different source and drain regions with a small gate length. The use of conventional photolithography may involve patterning one of the source and drain sides of the device and processing the other side thereof. Such an approach may create overlay/misalignment problems, particularly in devices having relatively small gate lengths. This is due at least to the presence of a reduced process window for mask placement with the small gate length.
USPTO Backgrounds
USPTO Backgrounds