The present invention relates to a jitter measuring system and a method thereof.
Measuring timing jitter is a challenge common to the design of high-speed systems. In the old days the demand is not high, since most systems are designed to transmit signals in low speed to avoid this problem. As a result, the requirement for jitter measurement is not high. For example, if the jitter ratio is 5% and the clock operation frequency is 100 MHz, jitter is 500 ps. In such a case the requirement for jitter measurement is not stringent. However, as IC technology, digital technology, computer usage, and the demand for communication bandwidth progress, all sorts of protocols now require faster speed and broader bandwidth. Under these new protocols, how to accurately measuring timing jitter becomes an important issue. For example, for a same 5% jitter ratio in 10 GHz clock signal, the jitter is required to be Sps.
Currently, jitter measurement is done using external instruments. However, measuring cost and accuracy become problems as the system operational speed increases. When measuring a high frequency signal (GHz) by oscilloscopes, in order to obtain accurate results, the sampling rate needs to be high, say often greater than 10 GS/s, and special software and hardware are needed. High speed oscilloscopes often cost tens of thousands US dollars or more. Also, using external devices to measure signals inside chips may run the risk of accuracy diminishing. For instances, interference caused by the measuring environment, limitation of the bandwidth of the I/O interface, and noise from output buffers of the chips are all causes that may reduce accuracy.
Although timing jitter is defined as the amount of phase shift, measuring definitions may vary for different applications. For example, period jitter is defined as the amount of phase shift between a real clock period and an ideal period, cycle-to-cycle jitter characterizes the time difference between two adjacent clock periods, and long-term jitter represents the accumulated period jitter after n periods. These three jitter definitions are commonly found in the system specifications regulated by the industry and are applied to specifications with different speeds. As an example, period jitter and long-term jitter are mostly applied to regulate timing margin in low speed systems. If setup-time is less than period jitter, system error may occur because there is not enough time to retrieve data; the specification sets the maximum tolerable limit for this. However, with the increase in clock speed, a system clock may be distributed to different circuits, and any tiny change in every period may affect the system. For example, delay locked loop (DLL) is often used for de-skewing clock, and if the jitter of reference clock exceeds the tracking frequency of the loop, the loop may be unlocked and system error appears. Therefore, cycle-to-cycle jitter is usually regulated in high speed clock jitter measurement. Also, period jitter and long-term jitter can be measured by using a digital story oscilloscope (DSO) to fix the rising edge and falling edge at one point and to accumulate the waves. On the other hand, due to the irregular nature of cycle-to-cycle jitter, there is no reference point for measurement. Making an effort to measure jitter between two subsequent clock cycles requires extremely fast sampling rate, and is very costly.
Currently, jitter measurement are done using time analysis method. Although there are different frameworks for doing this, these frameworks all are based on the concept of Time-to-Digital Conversion. However, there are some common problems in these frameworks, namely slow operational speed and low resolution. PC peripherals available on the market mostly are in the MHz range. As for CPUs and I/O interfaces, these are in the GHz range. Specification of jitter in high-speed systems is defined in tens of picoseconds, if the measuring devices lacked resolution and bandwidth, the measured signals cannot be verified.
Referring to FIG. 13. FIG. 13 is a diagram of a known Time-to-Digital Conversion circuit for measuring jitter. When jitter occurs in a clock signal SUT, its edge would drift away from its ideal place. The common way is to delay the SUT one period (SUTd) and measure the jitter of each period edge. This is done by sending the SUT into a delay chain as sample data, and the SUTd is the sampled clock. SUTd will generate digital information, which resembles thermal-meter codes when sampling SUT's with different delay amounts, and this digital information represents measured jitter value. For example, if the delay chain is made of 10 delay units with a delay amount of 25-ps and the clock period jitter is 10-ps, the sampling result is [Q1:Q10]=1000000000. When the jitter is 30-ps, [Q1:Q10]=110000000. Basically, when jitter increases, the 1's in the digital information increase.
As discussed above, because resolution and delay amount of the delay unit are inversely proportioned, unless the delay amount is designed to be small, errors would occur. According to the example given above, ideally, when jitter is either 0.1-ps or 24.9-ps, the digital values both are [Q1:Q10]=10000000000 and its maximum error is close to delay time of one delay buffer. This kind of error may induce quantization error especially when testing in high speed and low jitter application. One may try to shorten the delay time to reduce error by enhancing the circuit boards, but this is difficult due to manufacturing limitations and requires more hardware spaces.
USPTO Backgrounds
USPTO Backgrounds