Test costs of integrated circuits (IC) are progressively threatening to overtake all other manufacturing costs. IC makers are packing a far wider range of functions with large number of pins causing conventional IC testers that have a limited number of test channels to become obsolete. Current technology IC testers operate by classifying IC inputs into different categories, store test patterns in a tester memory buffer, and supply direct current (DC) levels for each of the IC inputs from dedicated tester channels. Appropriate sets of the DC levels are selected through board-level multiplexers for each IC pin. The levels are further controlled by a bit configuration of each test pattern.
Conventional testers become a limiting factor as complexity and pinouts (i.e., a number of pins or bonding pads) of the ICs being tested increases. The finite number of tester channels restricts the number of IC inputs that can be stimulated simultaneously. Furthermore, circuitry implemented within or on the testers on custom boards designed specifically to test a particular device increases time to set up for manufacturing test operations.
USPTO Backgrounds
USPTO Backgrounds