1. Field of Invention
The present invention relates generally to semiconductor devices and methods for fabricating the same. More particularly, at least one embodiment is directed to a flip chip semiconductor package and die bonding process.
2. Discussion of Related Art
One semiconductor packaging technique that is widely used in the radio frequency (RF) component industry is referred to as “flip chip” packaging. Flip chip describes the method of electrically connecting the die or “chip” to the package carrier. In contrast to standard chip and wire packaging that uses bond wires to connect the die to the carrier, the interconnection between the die and the carrier in flip chip packaging is made through a conductive “bump” that is placed directly on the surface the die. The bumped die is then “flipped over” and placed face down with the bumps connecting the die to the carrier directly.
The flip chip assembly process generally includes three major steps: 1) bumping of the dies; 2) “face-down” attachment of the bumped dies to the substrate or board; and 3) under-filling, which is the process of filling the open spaces between the die and the substrate or board with a non-conductive but mechanically protective material. There are several types of bumps and bumping processes that are used for flip chip devices. For example, solder bumping includes placing an underbump metallization over the bond pad (e.g., by plating, sputtering or similar techniques), and then depositing solder over the underbump metallization. Another type of flip-chip bumping is known as “plated bumping.” The bond pad is covered with a nickel layer to the desired plating thickness, forming the foundation of the bump. An immersion gold layer is then added over the nickel bump for protection. Adhesive bumping is another flip-chip bumping process that stencils electrically conductive adhesive over an underbump metallization placed over the bond pad. The stenciled adhesive serves as the bump after it has been cured.
Gold bumping is a favored bumping process, as the gold bonds provide superior bond strength because of the monolithic structure of the gold material. Gold bonds also generally have superior high frequency performance and low resistance when compared to solder or other conductive materials. Gold bumps may be formed on the flip chip die by depositing a layer of gold in the desired bump locations, or gold-plating a pad formed of another material (e.g., nickel). Flip chips with gold bumps are attached to a substrate with gold bond pads using an ultrasonic gold-to-gold interconnect (GGI) process.
GGI is a thermosonic process by which gold bumps and gold bond pads are joined together by heat and ultrasonic power under a pressure head, using a machine called a GGI bonder. The thermosonic process connection is made by solid-phase bonding between the two gold layers. Diffusion of gold (micro-welding) under load, and ultrasonic power, creates the gold-to-gold connection as a bond layer that is void-free and monolithic. The ultrasonic GGI process has a mounting accuracy of about ±10 μm and can reliably bond die with a thickness as thin as 100 μm. A disadvantage of GGI processes however, is the use of gold, an expensive material, for both the bumps and the pads.
USPTO Backgrounds
USPTO Backgrounds