1. Field of Invention
The present invention relates to memory structure and preparation method thereof. More particularly, the present invention relates to a resistive random access memory controlled by a transistor, and preparation method thereof.
2. Description of Related Art
Memory devices are distinguished into volatile memory devices and non-volatile memory devices, in which the volatile memory devices can be further categorized into DRAM (dynamic random access memory) and SRAM (static random access memory). These memory devices are widely used due to their high access speed. Besides, one of the most popular non-volatile memory devices is flash memory. However, the flash memory has shortcomings of high operating voltage, slow rewriting speed, and love durability. Further, due to the smaller size of the devices, the gate oxide layer of the flash memory devices becomes thinner and causes larger leakage current, which decrease reliability of the flash memory devices.
In recent years, the development of the resistive random access memory has considered as the key technology for low-power consumption and high-density non-volatile memory in the next generation,. The resistive random access memory includes advantages of simple structure, low operating voltage, fast rewriting speed, high applicability to multi-bit applications, good endurance of read/write, small size, non-destructive read operation and low cost. The common structure used by the resistive random access memory is metal-insulator-metal (MIM), and an external bias voltage is applied to modify the resistance to perform the read and the write operations such that the memory can switch between a high resistance state and a low resistance state corresponding to the states of “0” and “1” of the digital signal. The resistive switching layer formed by the metal oxide is the most important and the most studied part of the resistive random access memory. However, the reaction time of the measure instrument is too slow for controlling the resistive random access memory, and thus resulting in current overshoot or device crashing during switching resistance
Thus, the design of the resistive random access memory with a control unit has to be studied in order to make the device have a good endurance under the circumstances of frequent switches between different resistance states.
USPTO Backgrounds
USPTO Backgrounds