In recent years, accompanying the increase in the number of terminals and the narrowing of their pitches in the semiconductor device which result from advancements in the speed of operations, the capability of multi functions and the degree of integration thereof, there have been, more than ever, growing demands that the interconnecting substrate for packaging which carries the semiconductor device also attains a higher density in arrangement and minuter interconnections.
As the interconnecting substrate for packaging which is currently in wide use, there can be given the build-up multi-layered substrate, a sort of multi-layered interconnecting substrate.
Using a glass epoxy print substrate as the base core substrate, this build-up multi-layered substrate is fabricated in the following way. Firstly, an epoxy resin layer is each formed on both surfaces of this glass epoxy print substrate. Next, via holes are formed in these epoxy resin layers by means of photolithography or laser. After that, with a combination of the electroless or electrolytic Cu plating method and the photolithography, an interconnection layer and via conductors are formed. By repeating the above steps successively, the formation of build-up layered structure is accomplished.
However, because the glass epoxy print substrate whose heat resistance is considerably low is utilized as the base core substrate in this build-up multi-layered substrate, there arises a problem that the heat treatments performed in fabrication of the build-up multi-layered substrate may bring the glass epoxy print substrate to a poor condition, creating defects such as the shrinkage, the warp and the swell. These defects markedly lower the accuracy in the step of exposure so that it is difficult to form a densely spaced minute interconnection pattern on the glass epoxy print substrate.
Further, when the semiconductor device is loaded on such a build-up multi-layered substrate by the flip chip method, heat treatments carried out at the time of chip loading and solder reflow are liable to cause the faulty connection and the distortion, and, therefore, liable to lower the long-term reliability for the connection.
For the purpose of overcoming the above problems, there have been proposed an interconnecting substrate for packaging, wherein a build-up layered structure is formed on a base substrate made of a metal board (Japanese Patent Application Laid-open No.3980/2000).
A series of schematic views illustrating the steps of a producing method of such an interconnecting substrate for packaging are shown in FIG. 18. First, as shown in FIG. 18(a), an insulating layer 102 is formed on a metal board 101 and, then, via holes 103 are formed in this insulating layer 102. Next, as shown in FIG. 18(b), an interconnection pattern 104 is formed on the insulating layer 102 including the via holes 103. Next, as shown in FIG. 18(c), an insulating layer 106 is formed over the interconnection pattern 104, and then, in this insulating layer 106, flip chip pad sections 105 are formed to reach the interconnection pattern 104. Finally, as shown in FIG. 18(d), the metal board 101 is etched from the backside, and a substrate-reinforcing structure 107 as well as external electrode terminals 108 are formed therefrom.
In recent years, for the interconnecting substrate for packaging, it has been strongly demanded, along with attaining the afore-mentioned higher density in arrangement and minuter interconnections, that the external electrodes for making electrical connection with an external board or apparatus have narrower pitches in order to achieve a more compact and more densely spaced system.
Nevertheless, in the interconnecting substrates for packaging shown in FIG. 18, since the external electrode terminals 108 thereof are formed by etching the metal board 101, the limitation of control over the amount of side etching at the time of etching makes it extremely difficult to form the external electrode terminals 108 with narrow pitches.
Moreover, when this interconnecting substrate for packaging is mounted on an external board or apparatus, the stress is structurally centered on the interface between the external electrode terminal 108 and the insulating layer 102, which tends to give rise to opening defects so that the satisfactory mounting reliability cannot be obtained.
USPTO Backgrounds
USPTO Backgrounds