Computing and communication networks typically include devices (e.g., network devices), such as routers, firewalls, switches, servers, or gateways, which transfer or switch data, such as packets, from one or more sources to one or more destinations. Network devices may operate on the packets as the packets traverse the network, such as by forwarding or filtering the packet-based network traffic. Some computing devices (e.g., a personal computer) may not be associated with a network and thus may be referred to as standalone devices. Such network devices and computer devices include memories and interfaces for the memories, such as serial memory interfaces.
Serial memory interfaces require interoperability between different vendors and across different generations of process technologies that typically have different input/output voltages. To facilitate such interoperability, an alternating current (AC)-coupled memory interface is employed. However, unlike traditional serial interfaces between chips with on board AC capacitors for each link, memories (e.g., memory chips) and their interfaces need to be provided adjacent to a memory controller (e.g., to minimize channel loss) and therefore it is impractical to put the AC-coupled capacitors on a board (e.g., associated with the memories and the memory controller). Thus, AC-coupled capacitors are provided on chips. The small sizes of such AC-coupled capacitors (e.g., provided on chips) limit the number of consecutive identical digits (CIDs) (e.g., consecutive “0s” or “1s”) that may be provided in a data stream due to clock data recovery (CDR) and data dependent direct current (DC) baseline wander.
Thus, serial memory interfaces are faced with a DC balance problem and a CID problem. If a data stream provided to/from a serial memory interface is not DC balanced, it will lead to charge build up over the long term, which will lead to DC baseline wander. A long CID will lead to a charge storage problem on the capacitor, which may be solved by using a larger capacitor on the board. However, as described above, AC-coupled capacitors must be provided on chips (e.g., rather than on the board) and are limited in size. A long CID will also lead to clock data recovery (CDR) issues, as described above. Another problem with serial memory interfaces is that traditional asynchronous clocking is used with serial links provided between transmitters and receivers. Since a frequency offset (e.g., in parts per million (ppm)) between different clock mechanisms (e.g., crystal oscillators) leads to phase build up, additional latency and circuitry is incurred to compensate for this phase build up. Also there is a potential negative impact on a serial link's bit error rate (BER) when there is a large number of CIDs in a data stream. Furthermore, some serial memory interfaces with clock recovery typically utilize asynchronous clocking between a transmitter and a receiver, which results in latency overhead for encoding and associated logic.
USPTO Backgrounds
USPTO Backgrounds