1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device and, in particular, to a method for manufacturing a flash memory cell using a damascene working process.
2. Description of the Related Art
Because of the advantage of flash memory that it can retain data without necessitating the supply of power, the flash memory is widely employed as a storage element for multimedia cards. In recent years, there have been persistent demands for a flash memory having an increased capacity and hence it is now required to further enhance the integration degree of such a memory.
As one of the method for enhancing the integration degree of flash memory, there has been proposed a method of dividing the silicon layer of floating gate into two layers in fabricating a stacked gate structure. In this method, element isolation is performed after the formation of the first silicon layer, thereby enabling the second silicon layer to be deposited selectively and in a self-aligned manner only on the first silicon layer. According to this method, it is possible to make the floating gate larger than the width of tunnel insulating film and also to make the distance between neighboring floating gates smaller than the minimum line width.
It is however difficult to make uniform the surface area of the selectively grown silicon layer for every cells. As a result, the memories obtained tend to become non-uniform in characteristics due to the coupling ratio. Meanwhile, there has been proposed a damascene working process wherein the second silicon layer is non-selectively formed all over the surface of the first silicon layer and the surface of insulating layer for element isolation at first and then the second silicon layer is subjected to back etching or polishing so as to leave the second silicon layer only on the first silicon layer. Further, there has been proposed a slurry for polishing a polysilicon film that has been non-selectively grown by the ordinary LPCVD method. When a polysilicon film is mainly polished at a high polishing rate by this slurry, it is possible to inhibit the phenomena such as dishing and erosion that may be generated inside the pattern.
However, as the fineness of memory cells is further enhanced in future, it is feared that due to the existence of step portion between the first silicon layer and the insulating film for element isolation, a defective formation of the second silicon film may be generated to degrade the characteristics of the obtained device.
USPTO Backgrounds
USPTO Backgrounds