Memory is one of the most limiting aspects of performance of modern enterprise computing systems. One limiting aspect of memory is the fact that many types of memory exhibit a limited lifetime. For example, a lifetime of non-volatile memory such as flash is reduced each time it is erased and re-written. Over time and thousands of erasures and re-writes, such flash memory may become less and less reliable.
One common prior art technique for reducing the reduction of memory lifetime is wear leveling. Wear leveling allows for blocks within a storage device to be erased and written a roughly equal number of times. This avoids situations where one block is more frequently used, reaches an end of life, and must stop being used. This reduces the storage capacity of the entire device. Although the storage devices may have spare blocks, the spare blocks are exhausted and a memory capacity of device drops such that the storage device may not be used.
Memory vendors often guarantee a life expectancy of a certain percentage of memory. For example, a flash memory vendor may guarantee that after 100,000 program and erase cycles (i.e. endurance), less than 1% of blocks will be unusable based on exceeding error correction requirements. In this case, the error correction requirements may be set to correct a single bit error per 512 bytes for the flash device. Some recently developed devices have a much lower endurance. These devices require a much larger error correction requirement.
Furthermore, the lifetimes of memory blocks may vary. Consequently, using wear leveling, where a number of program erase cycles are leveled, a storage device may reach an end of life when only a specified percentage blocks are bad (1% for example). However, most blocks included in the storage device may still be functional.
There is thus a need for addressing these and/or other issues associated with the prior art.
USPTO Backgrounds
USPTO Backgrounds