In computer systems it is generally desirable to read and write data as quickly as possible. While advances have been made in access speeds of memory such as RAM and ROM, there remains a need in the art to accelerate read cycles from peripheral devices such as hard disk drives.
Referring now to FIG. 1, a communication bus 10 is shown for a hard disk drive controller (not shown). Communication bus 10 provides a communication link between a processor 12 and data registers 14-0 through 14-N, collectively referred to as data registers 14. Each of data registers 14 can be associated with a different module of the hard disk controller. For example, data register 14-0 can be associated with a servo control module that positions a read-write head of a hard disk drive. Data register 14-1 can be associated with a diagnostic module of the hard disk drive, and so forth.
Processor 12 executes multiple steps to read data from one of data registers 14. For example, processor 12 first designates the module that is associated with the selected data register 14 that will be read. Processor 12 then specifies an address or address offset of the selected data register 14. A snapshot register module 16 captures the data from selected data register 14. Processor 12 can then read the data from snapshot register module 16 via a multiplexer 18. This process can take several clock cycles and may prevent processor 12 from attending to other tasks while it is reading from the selected one of data registers 14.
USPTO Backgrounds
USPTO Backgrounds