The present invention relates to a system including a plurality of circuit blocks, and more particularly relates to a technique of controlling operation timing in such a manner as to suppress coincident switching noise.
In recent years, a semiconductor integrated circuit is composed of a plurality of circuit blocks in many cases. For example, a microcontroller unit (MCU) is made up of CPU, memory and other circuit blocks of numerous types.
Under the circumstances such as these, noise is more likely to be caused these days in a semiconductor integrated circuit mainly because of charging and discharging of gate and line capacitances formed by the increased number of circuit blocks included. If these circuit blocks charge and discharge simultaneously, then large noise is caused within the overall system. Such noise is generally called "coincident switching noise".
In a prior art technique for suppressing the coincident switching noise in a system including a plurality of circuit blocks, a delay circuit is provided for delaying a reference clock signal externally supplied. In this configuration, each circuit block is selectively supplied with the reference clock signal or a delayed clock signal responsive to a switching signal. This technique is disclosed in Japanese Laid-Open Publication No. 10-91274, for example.
In some of real-world circuits, a peak current state arises immediately after a clock signal has risen. In other circuits, however, the occurrence of the peak current state is delayed for some time after a clock signal has risen. For instance, if a large-scale combinatorial circuit, included in a circuit block, starts to operate later than a clock signal supplied to the circuit block, then the occurrence of a peak current state in this circuit block is delayed for a while after the clock signal has risen. Also, the delay time is variable with the internal configuration of a specific circuit block.
The prior art identified above supposes that a peak current state always arises soon after a clock signal has risen, and pays no attention to the possibilities that the peak current state may at different times in respective circuit blocks. Accordingly, in accordance with this technique, if a circuit block, where a peak current state arises later than the leading edge of a clock signal, is included in a system, then the coincident switching noise cannot always be suppressed.
USPTO Backgrounds
USPTO Backgrounds