The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly to a nonvolatile memory device and a method for fabricating the same.
Recently, demands for a nonvolatile memory device, which can be electrically programmed and erased and does not require a refresh operation for rewriting data periodically, are steadily increasing. To develop a large-capacity memory device that can store massive data, research for high integration technology of a memory device has been actively conducted. Here, ‘programming’ means writing data to a memory cell, whereas ‘erasing’ means removing data which have been written to the memory cell.
Thus, to realize a highly-integrated nonvolatile memory device, a NAND type flash memory device has been proposed in which a plurality of memory cells are connected to each other in series, that is, adjacent cells share one drain or one source, so that the plurality of memory cells constitute one string. The NAND type flash memory device, which sequentially reads data unlike a NOR type flash memory device, performs programming or erasing operations in such a manner that the threshold voltage of the memory cell is controlled by injecting electrons into a floating gate or removing electrons from the floating gate by Fowler-Nordheim (FN) tunneling.
FIG. 1 illustrates a plan view of a memory cell array of a typical NAND type flash memory device. FIG. 2 illustrates a cross-sectional view taken along the line I-I′ of FIG. 1 (a bit line direction), and FIG. 3 illustrates a cross-sectional view taken along the line II-II′ of FIG. 1 (a word line direction). Herein, a string configuration having 6 memory cells MC0˜MC5 is illustrated as an example.
Referring to FIGS. 1 to 3, a plurality of strings are arranged in the memory cell array of the typical NAND type flash memory device. Each of the strings includes a drain select transistor (not shown), a source select transistor SST, and a plurality of memory cells MC0˜MC5 connected in series between the drain select transistor and the source select transistor SST. In addition, a source of each source select transistor SST, e.g., a junction region formed by implanting impurity ions into an active region ACTIVE, is commonly connected to a common source line CSL. The common source line CSL is directly connected to a ground terminal through a contact CT and a metal interconnection M1.
However, according to the typical memory cell array structure of the NAND type flash memory device, it is often difficult to perform a post-annealing treatment such as a furnace annealing using oxygen (O2) gas, in the case that the common source line CSL is formed of a metallic material such as tungsten (W) or the like. This limitation will be more fully described below.
As illustrated in FIGS. 2 and 3, in order to directly connect the metal interconnection M1 to the common source line CSL, a portion of the common source line CSL should be exposed after the common source line CSL is formed. However, when the furnace annealing is performed using O2 gas in a state that the portion of the common source line CSL is exposed, the exposed portion of the common source line CSL is oxidized due to the O2 gas.
Accordingly, a rapid thermal annealing (RTA) treatment is employed instead of the furnace annealing to avoid the oxidation. The RTA treatment may lead to the increase of a thermionic field emission (TFE) current due to the stress generated during the RTA treatment. The increase of the TFE current causes the leakage current of the junction region to increase to thereby reduce a self-boosting level, which makes the program disturbance characteristic deteriorated.
For reference, a heat treatment such as RTA is frequently performed in fabricating a semiconductor device. For example, the RTA treatment is performed to form an ohmic contact between the active region and the metal interconnection M1 in a peripheral region after the common source line CSL is formed.
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