Manufactures, distributors, and retailers of populated circuit boards are always looking for test and measurement solutions that not only minimize cost, but also are easy to deploy. Complicating these goals is the fact that many devices that such parties desire to test require the use of a high density interconnect. In the case of a logic analysis probe, it is not unusual that an interconnect having a 49×49 array of connections is required to connect the probe to the board under test. Such interconnects have a total of 2,401 connections. Providing dedicated test pads for each of these connections would not only be expensive but would require considerable time to design.
For socketed chips, known solutions include the provision of an adapter between the socket and the chip or an external interface that fits over a chip (such as a QFP) and contacts the pins extending from the chip. Unfortunately, such probe interfaces are not suitable for use with chips using ball grid array (BGA) packaging solder attached to the board.
One of the more popular solutions for surface mount technologies is the so-called “bed of nails” probe. A bed of nails probes provides an array of pins, typically POGO-PINS, which are clamped over a matrix of connections formed on a board under test. Of course, this requires that the board be produced with such a grid. The ever-existing trend toward smaller packaging puts sever limitations on the availability of space on a PCB to accommodate test matrixes. One variation of such interfaces involves matching a bed of nails probe to a grid of conductors typically found on the opposite side of the PC board from the ball grid array. More specifically, BGA devices are typically associated with a matrix of vias, wherein the individual solder balls are attached to pads connected to vias. It is also known to attach the solder balls of the BGA directly to the vias. In any event, a probe is formed with an array of pins that match the pattern of the vias on the opposite side of the board. This is known in the art as back-side probing.
Unfortunately, current methods and apparatus for back-side probing have certain drawbacks. Most significantly, there are a number of physical parameters that are not controlled by the entity doing the actual probing, such as the size, placement and condition of the contacts to which the probe is being connected.
FIG. 1 is a conceptual sectional view of single solder ball 10 of a BGA array on a device 12 being probed from the backside of the target board 14. In this example the solder ball 10 is shown as being connected to a pad 16 formed as part of a via 18, however as noted above this need not necessarily be the case. As a result of processes and design constraints from the customer, the exposed section 20, referred to as the pad 20, of the via 18 on the backside of the target board 14 is not conducive to a reliable connection. While the ideal pad would be a smooth, flat, gold plated, dimensionally controlled surface, the pad 20 is simply bare copper left over from the formation of via 18.
Further, the pad 20 is typically surrounded by solder mask 22, a byproduct of the process used to populate the target board 14. It is typical that the solder mask 22 raises 5 to 10 thousandths of an inch above the level of the pad 20 making it quite difficult for probe to reliably contact the copper pads, especially if an elastomeric connector 23, as shown, is used. The elastomeric connector 23, in this example, is used to make contact to pad 20. The elastomeric connector 23 has conductive members running through it, perpendicular to the board. Instead of an elastomeric connector 23, contact could be attempted with pogo pins. In this case there is the possibility of the pogo pins hitting the exact center of via 18, producing minimal or no compression of the pogo-pin, or that the solder mask surrounding the via may interfere with the pogo pin. Either condition will produce an unreliable contact that can significantly deteriorate the signal.
Accordingly, the present inventors have recognized a need for new apparatus and methods to assist with back side probing that facilitate obtaining reliable connections between the probe and the pads on the device under test.
USPTO Backgrounds
USPTO Backgrounds