As integrated circuit technologies are scaled, stability in a static memory cell becomes a major concern affecting the design of reliable memory arrays, including, for example, static random access memory (SRAM) arrays. Most static memory cells employ a conventional six-transistor (6-T) architecture, as depicted in FIG. 1. While this memory cell arrangement offers a compact structure, the 6-T memory cell has many disadvantages, particularly its potential inability to scale with overall technology advancements due, at least in part, to stability problems which are often exacerbated as integrated circuit process dimensions shrink.
Stability problems generally arise whenever stored voltages on internal nodes of the memory cell are disturbed. In the case of the standard 6-T memory cell illustrated in FIG. 1, this typically occurs when an access transistor (e.g., 104) connected to an internal node (e.g., node N2) with a stored logical “0” is activated with a logical “1” on a corresponding bit line (e.g., 114). When this occurs, the internal node (e.g., node N2) is pulled above ground potential, which could unintentionally flip a logical state of the memory cell. This scenario can occur as a result of a read operation of the memory cell.
As process technologies scale, process-induced variations, as well as fundamental variation sources (e.g., dopant fluctuation effect on threshold voltage, etc.), may result in large threshold voltage variations across a given wafer. This threshold voltage scatter effect essentially magnifies the disturb voltage in 6-T memory cells, which can lead to stability failures in the SRAM array in which the 6-T memory cells are employed. The scaling of power supply voltages further degrades stability by reducing noise margins in the memory cell. Existing solutions attempting to address the stability problem typically involve subtle modifications to the 6-T memory cell itself (e.g., modifying transistor sizing, threshold voltage design, increasing cell size, etc.), or to the memory array (e.g., increasing the supply voltage, etc.), to increase the stability margin. These techniques, however, generally involve a significant tradeoff between memory cell stability and performance, and may not be sufficient for future process technologies.
There exists a need, therefore, for a static memory cell architecture having improved read stability, which does not suffer from one or more of the above-noted deficiencies associated with conventional memory cell architectures.
USPTO Backgrounds
USPTO Backgrounds