The present invention relates to interconnect structures, and more specifically, to an interconnect structure including a middle of line (MOL) metal layer local interconnect.
Integrated circuits (ICs) are typically fabricated from one or more layers of different materials. Some layers, such as polysilicon layers, are used to form semiconductor devices, while other layers, such as patterned metal layers, provide electrical connections between semiconductor devices. Referring to FIG. 1, a conventional interconnect structure 100 including a plurality of stacked dielectric layers 102a-102b is illustrated. One dielectric layer 102b includes at least one initial first layer contact element metal layer (M0) structure 104 formed directly atop one or more electrically conductive embedded vias (CA/CB) 106/108. Thus, an entire layer (e.g., dielectric layer 102b) is dedicated to supporting only the first level (M0) metal layer structures 104, which makes it difficult to reduce the size (e.g., height) of the overall structure 100. In addition, since the metal layer structures 104 require a dedicated layer (e.g., dielectric layer 102b) for local isolation, a double patterning process including multiple masks is required to achieve the proper line-to-line spacing and tip-to-tip spacing.
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