1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for a silicon oxynitride film. More specifically, the present invention relates to a semiconductor device such as a MOS transistor which is formed on a semiconductor substrate having a three dimensional structure, and a manufacturing method for a silicon oxynitride film.
2. Description of the Related Art
Semiconductor devices such as MOS transistors and memory cells have been miniaturized according to the scaling rule proposed by J. R. Brews for the purpose of implementation of high integration. However, there are great problems that occur in actual devices as miniaturization progresses, such as an increase in a leak current due to reduction in the thickness of a tunnel insulating film, an increase in a diffusion resistance due to reduction in junction depth Xj of source/drain diffusion layers, occurrence of short channel effect, and reduction in the withstand voltage against punch through between sources and drains.
In order to solve such problems, there have been proposed three dimensional semiconductor devices wherein semiconductor substrates are processed into three dimensional forms so as to secure effective dimensions of the elements while reducing the projection areas of the devices. It is explained by FIG. 32 that a technique of utilizing a structure had a trench formed in a semiconductor substrate to work as a channel of a MOS transistor and described in Japanese Unexamined Patent Publication No. HEI 5(1993)-102480 as an example of the above-described conventional art.
The MOS transistor of FIG. 32 has a gate oxide film 20 on the surface of a trench (0.4 to 0.6 μm in depth) in a first conductive type silicon substrate 1 and a gate electrode material is filled into the trench via a gate oxide film 20, whereby a trench type gate 6 is formed. Furthermore, a second conductive type source 8 and a drain 9 are formed on both sides of the trench type gate 6. At least one of the source 8 and the drain 9 is adjacent to a first conductive type impurity region 10 in the direction of the depth of the substrate. The first conductive type impurity region 10 has an impurity concentration higher than that of the silicon substrate 1. At least a part of the channel region of this MOS transistor is formed in the part other than the first conductive type impurity region 10.
With the above-described configuration, it is possible to expand the channel region in the direction of the depth of the semiconductor substrate. Furthermore, the area where the gate electrode is arranged can be reduced while preventing the reduction in a threshold voltage due to a short channel effect and deterioration of an off current. In addition, a depletion layer can be suppressed from extending from the source 8 and the drain 9 so as to increase the withstand voltage against punch through.
The sides of the trench (non-horizontal surfaces) correspond to a (110) plane of the silicon substrate, the connection regions where the sides of the trench make contact with the bottom correspond to a (111) plane, and the bottom of the trench (horizontal surface) corresponds to a (100) plane in the above-described structure. Herein, the gate oxide film is formed according to a thermal oxidation method and, in such a case, it is known that more interface levels exist between the silicon substrate and the gate oxide film in the (110) and (111) planes than in the (100) plane. Therefore, the interface levels that exist in the sides and in the connection regions significantly affect the characteristics of the semiconductor device such that they make lower mobility of carriers and they make a threshold voltage fluctuate.
In addition, it is known that the oxidation rate of the (110) plane, which is the sides of the trench, is 30 to 100% higher than that of the (100) plane on the bottom. Therefore, a problem arises wherein the inversion voltage of the channel region increases when the thickness of the gate oxide film on the sides of the trench increases, leading to the reduction of the driving performance of the MOS transistor.
Furthermore, there is a problem with the reliability of the gate oxide film in the (111) plane of the connection regions wherein an insulation breakage electrical field is lower than that in the (100) plane on the bottom.
In addition, according to the conventional thermal oxidation method, the closer to the right angle the angle (i.e., the angle between the sides and the bottom) in the crossing portion (connection region) of the surfaces of the silicon substrate having different plane directions is the more significant is the reduction in the film thickness of the gate oxide film formed in the crossing portion. Therefore, it is necessary to increase the curvature of the crossing portion and to make the angle between the sides and the horizontal surface greater than 90°. As a result, the projection area of the crossing portion increases; therefore, the dimensions of the semiconductor device increase and the integration of the devices throughout the LSI is decreased.
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