The present invention relates to a method of manufacturing highly reliable semiconductor devices based upon silicon-on-insulator (SOI) substrates. The present invention has particular applicability in manufacturing semiconductor devices with accurately formed ultra-shallow source/drain extensions which are essentially completely or substantially monocrystalline silicon and exhibit increased carrier mobility.
Conventional SOI types of substrates have evolved and basically comprise a substrate, such as a silicon-containing substrate, an insulating layer thereon, commonly referred to as a buried oxide layer, and a monocrystalline silicon layer on the insulating layer which constitutes the xe2x80x9cbodyxe2x80x9d of the transistor. In such SOI devices, the body floats in that there is no direct electrical connection thereto. As the source/drain regions are isolated from the substrate, junction capacitance is reduced, i.e., when an electrical signal changes on either or both source/drain regions, there is no capacitive coupling to the substrate. As electrical isolation is facilitated employing an SOI substrate, certain electrical elements of the circuit can be positioned closer together, thereby reducing the die size. SOI structures also offer the advantages of latch-up immunity, reduced junction leakage currents and reduced short channel effects, thereby translating to increased transistor speed.
SOI transistors can be partially depleted or fully depleted. A fully depleted SOI transistor is a transistor in which the film thickness of the monocrystalline silicon layer is thinner than the maximum depletion layer width. A partially-depleted SOI transistor is a transistor in which the film thickness of the monocrystalline silicon layer is greater than the maximum depletion layer width. Each type of SOI transistor offers advantages. For example, because it threshold voltage can be set to a high level, a partially-depleted SOI transistor can suppress the stand-by leakage current to a low level. A fully depleted SOI transistor can reduce sub-threshold swing and therefore enable high-speed operation at low voltage.
In fabricating SOI transistors with ultra shallow source/drain extensions, it is necessary to accurately define the extensions and to provide a desirable high impurity concentration therein. Accordingly, pre-amorphization techniques have been employed. However, it is desirable to recrystallize the source/drain extensions such that polycrystalline silicon is not formed, as the mobility of electrons and holes in polycrystalline silicon is lower than in monocrystalline silicon, due to scattering at the grain boundaries. However, the avoidance of polycrystalline silicon formation upon recrystallization is extremely difficult.
Accordingly, there exists a need for methodology enabling the fabrication of SOI transistors with accurately defined source/drain extensions which are essentially completely or substantially monocrystalline silicon with and attendant increase in carrier mobility.
An advantage of the present invention is a method of manufacturing a semiconductor device comprising an SOI transistor exhibiting high carrier mobility.
Another advantage of the present invention is a method of manufacturing a fully depleted or partially depleted SOI transistor with essentially completely or substantially monocrystalline silicon source/drain extensions exhibiting improved carrier mobility.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or maybe learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved by a method of manufacturing a semiconductor device, the method comprising: forming a silicon-on-insulator (SOI) substrate comprising an insulating layer on a substrate and a layer of monocrystalline silicon (Si) on the insulating layer; forming a gate electrode, having an upper surface and side surfaces, over an upper surface of the SOI substrate with a gate dielectric layer therebetween; forming dielectric sidewall spacers on the side surfaces of the gate electrode; ion implanting and annealing to form source/drain regions in the monocrystalline Si layer extending down into the insulating layer; thermally oxidizing to form a protective oxide layer on the upper surface of the gate electrode and on the upper surface of the SOI substrate over the source/drain regions; removing the dielectric sidewall spacers, thereby exposing portions of the upper surface of the SOI substrate between the protective oxide layers thereon and the side surfaces of the gate electrodes; ion implanting to form a pre-amorphized region in the monocrystalline silicon Si layer adjacent to each source/drain region to define intended source/drain extensions; ion implanting impurities into the pre-amorphized regions; and laser thermal annealing to recrystallize the pre-amorphized regions and to activate the source/drain extensions, thereby forming a field effect transistor.
Embodiments include forming additional dielectric sidewall spacers on the side surfaces of the gate electrode after laser thermal annealing and then forming a metal silicide layer on the upper surface of the gate electrode and on the upper surface of the SOI substrate over the source/drain regions. Embodiments of the present invention further comprise forming the source/drain extensions extending down to the insulating layer, wherein the field effect transistor is fully depleted or forming the source/drain extensions such that they do not extend down to the insulating layer wherein the field effect transistor is partially depleted.
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