Memory controllers are digital circuits that manage the flow of data to and from a computer's main memory. Memory controllers can be implemented as a special-purpose integrated circuit (IC), or can be integrated with a general-purpose IC, e.g. a control processing unit (CPU). Main memory, typically dynamic random-access memory (DRAM), can likewise be implemented as a special-purpose IC or integrated with other functionality.
Computer memory systems are commonly synchronous, which means that operations between the controller and the memory device or devices are synchronized to a shared timing reference. The shared timing reference is typically a clock signal external to both the controller and the memory device.
A shared timing reference may be too noisy or otherwise unsuitable for supporting internal operations in the memory device. Each controller and memory device in a given system can therefore include control circuitry that generates a stable internal timing reference signal from the relatively noisy external reference. The relatively stable internal timing references are then used to synchronize communication between devices. Unfortunately, the circuitry commonly used to generate, control and distribute an internal timing reference based on a shared external reference tends to be complex and power hungry.
USPTO Backgrounds
USPTO Backgrounds