1. Field of the Invention
The present invention is directed to a process for fabricating a vertically differentiated transistor device. more specifically, the present invention is directed to a process for protecting the gate structure of a vertically differentiated transistor structure during erosion operations.
2. Background of the Prior Art
The tremendous growth of the semiconductor industry has resulted in improved processes for fabricating vertically differentiated transistor devices. A problem associated with this fabrication has been the poor surface morphology that oftentimes results after vertically differentiated transistors are defined by reactive ion etching, typically in a halogen based plasma. A typical manifestation of this phenomenon is the "grass" which remains atop the insulating surface of a III-V compound, typically aluminum gallium arsenide, vertically differentiated semiconductor structure.
Up to now the surface of a vertically differentiated transistor device having poor surface morphology was subjected to a plasma etch in a halogen atmosphere. Although this procedure is successful in removing the grass, thus improving surface morphology, this method has been found to be unsatisfactory because while the horizontal surface subject to etching improves, the vertical surface of the gate is also etched resulting in surface damage thereto. This effect renders the transistor unusable.
The problem of undercutting in photoelectrochemical etching of transistor devices has been a problem long known in the art. Several methods have been advanced for coping with this problem. That is, several processes have been advanced for providing anisotropic etching of a vertically differentiated semiconductor structure without concurrent lateral etching which has the adverse effects discussed above.
One such method is set forth in U.S. Pat. No. 4,529,475. In that patent a dry etching apparatus and method is disclosed in which anisotropic etching is said to be achieved without causing surface damage to a workpiece subject to selective etching. This is accomplished by etching in a vacuum chamber in which two feedstock gases are introduced. One of the gases contributes to the etching effect while the other gas forms a film on the side wall of the etched portion of the workpiece protecting that wall from lateral etching. Although this method is recited to be successful, the problem of removing the film thus formed remains. The protecting film is very difficult to remove.
Another method advanced in the art is set forth in U.S. Pat. No. 4,528,066. The process of the '066 patent involves a reactive ion etching technique for etching a gate electrode comprising layers of tungsten silicide and polycrystalline silicon without etching the underlying layer of silicon dioxide which serves as the gate dielectric covering the source and drain regions. The invention of the '066 patent involves coating the gate with polytetrafluoroethylene to protect the side walls of the gate from excessive etching in the lateral direction while etching continues at the bottom on either side of the gate. Again, although this method is recited to be successful, the removal of the polytetrafluoroethylene coating is very difficult.
A third development in this art is incorporated in U.S. Pat. No. 4,482,442. The '442 patent discloses a process for photoelectrochemically etching n-type gallium arsenide and closely related gallium aluminum arsenide and gallium aluminum phosphide compound semiconductors. In this method the area to be etched is radiated while the semiconductor is in contact with an aqueous electrolyte solution containing an oxidizing and a solvating agent which dissolves the product of the oxidation process. The use of an oxidizing agent ensures oxidation in the presence of light without excessive oxidation in the absence thereof. Thus, anisotropic etching occurs with minimal etching of non-illuminated areas. The side of the semiconductor wafer is therefore non-illuminated thus minimizing lateral etching. This method requires special etching apparatus, increasing the complexity of the photoelectrochemical procedure.
Other semiconductor producing processes, which offer processes for protecting vertical faces of semiconductor structures during dry plasma etching, are set forth in Japanese Patent Publication Nos. 57-73180 and 58-132933. Suffice it to say, these methods if employed with the semiconductor structures treated in accordance with the present invention would cover horizontal surfaces and therefore would not improve the poor surface morphology of the horizontal surface of the semiconductor device. This is to be expected in that these disclosures are directed to distinguished silicon semiconductor devices rather than the III-V compound type semiconductors of the present invention.
The above remarks establish the need in the art for a new process for fabricating vertically differentiated semiconductor structures wherein lateral etching is effectively controlled without applying coatings which are difficult to remove to effectuate this desirable result. It is furthermore apparent that the process should not require modification of the apparatus usually utilized in semiconductor operations.
USPTO Backgrounds
USPTO Backgrounds