Presently in many chips, information interactions between signals often require a certain phase-delay relationship maintained between two signals. Taking a clock signal and a data signal for example, if a clock is required to sample data stably, a rising edge of the clock must be at least one setup time (the setup time of a register) later than the data. Due to the influence of Process, Voltage and Temperature (PVT), the requirement for a delay between signals may change, and a delay of a circuit for satisfying the delay requirement may also change. For example, in a NAND gate, which is the most elementary unit to form a digital circuit, the drive of a NAND gate rises as the temperature lowers or the voltage rises, and thus its delay may also be shortened. If the influence of the PVT is not compensated, the delay relationship between the signals cannot be guaranteed. One effective way to solve these problems is a Digital Phase Locking Loop (DPLL). The DPLL is used in all kinds of circuit systems to realize the delay capable of dynamically compensating the influence of the PVT, especially in high-speed circuits, such as a Double Data Rate dynamic random access memory (DDR) and a clock generation module.
The existing DPLL is usually used for the delay of the Data Strobe (DQS) in the DDR, and usually its delay function is implemented by a delay element. The structure of a delay element has many forms, one of which includes a buffer (BUF) and a multiplexer (MUX). Referring to FIG. 1, three delay elements, namely, n−1, n and n+1, are provided, and selection signals of the three delay elements are Sn−1, Sn and Sn+1 respectively. A one-hot mechanism is used for the selection signals of the delay elements. That is, a selection end S of only one MUX is set to ‘1’ at the same time, and selection ends of other MUXs are all set to ‘0’. When the DPLL performs delaying, the DPLL determines the number of the delay elements to be used by setting the selection ends of the corresponding delay elements to ‘1’. For example, at a certain time the selection end 5, of the delay element n is set to ‘1’, so that the number of the delay units selected to perform delaying is n. A delayed clock signal clk_out is obtained after a clock input signal clk_in passes n delay elements, where the clock input signal clk_in passes n BUFs. Due to the influence of the PVT, when the number of the delay elements needs to be adjusted, the selection end of the corresponding delay element of ter adjustment is set to ‘1’. For example, when the number of the delay elements changes to n+1, the selection end Sn+1 of the delay element n+1 is set to ‘1’. The objective of changing the delay time can be achieved by changing the number of the delay elements. If one delay element can produce a delay of 100 ps, twenty delay elements can produce a delay of 2 ns. Another delay structure, as shown in FIG. 2, includes BUFs and one MUX. One MUX is connected to multiple BUFs. A selection signal of the MUX is msel. The smallest value of msel is 0. When msel is 0, the clock input signal clk_in is directly output as the clk_out without passing any BUF. When msel is 1, the clock input signal clk_in is output as the clk_out after passing one BUF. Analogically, when the msel is n, the clock input signal clk_in is output as the clk_out after passing n BUFs. The value of msel represents the number of the BUFs to be passed. By changing the value of msel, the number of the BUFs that the clock input signal clk_in passes is changed accordingly, so that the objective of changing the delay time can be achieved. If one BUF produces a delay of 5 ns, passing 20 BUFs can delay the clk_in 100 ns.
Besides, another kind of delay element formed by gate circuits is provided. Because the delay of a NOR gate, an AND gate or an OR gate is longer than that of a NOT gate and a NAND gate, usually NAND gate circuits are used to form the delay element. For example, referring to FIG. 3, m delay elements, S0, . . . Sn, Sn+1, . . . and Sm (m>n) are provided, and selection signals of the delay elements are MSEL0, . . . MSELn, MSELn+1, . . . , and MSELm respectively. The delay elements use the one-hot mechanism. When the selection signal MSELn of the delay element Sn is set to ‘1’, the delayed clock signal clk_out is obtained after the clock input signal clk_in passes n delay elements (3n NAND gates). If the number of delay elements needs to be delayed is adjusted to be n+1, the selection signal MSELn+1 of the delay element Sn+1 is set to ‘1’. Different number of delay elements leads to different delay time. If one NAND gate can produce a delay of 5 ns, one delay element can produce a delay of 15 ns, and 10 delay elements can produce a delay of 150 ns and so on.
During the implementation of the present disclosure, the inventors find that the prior art has at least the following disadvantages.
When a DPLL dynamically compensates the influence of the PVT, glitches occur, so that the operation of sensitive circuits at the edge turns abnormal or even a whole system turns abnormal. For example, when a DPLL uses delay elements formed by BUFs and MUXs, during the update of the number of the delay elements, glitches are very likely to occur because of the transition of the selection ends of the MUXs. Referring to FIG. 4, the clk_in represents a clock input signal. A clock cycle is 50 ns. As shown in FIGS. 4, E, B, F, and I represent the signals at points E, B, F, and I in FIG. 1 respectively, and S represents the selection signal of a MUX. When the clock input signal runs to 50 ns, the DPLL changes the number of delay elements from n to n+1. At this moment, the selection end Sn transits from ‘1’ to ‘0’, and the selection end Sn+1 transits from ‘0’ to ‘1’. Before the transition, the signal at point I is the same as the signal at point E, and after the transition, the signal at point I is the same as the signal at point F. Because the transition happens at a rising edge of the clock input signal, point E is at a low level, and e point F is at a high level. Point I hopes to follow the low level of point E, but is increased by the signal at point F to the high level however, and then follows the signal at point F, changing to the low level. Thus, a glitch shown in FIG. 4 occurs. When the DPLL uses delay elements with a NAND gate structure, because of the delay of the NAND gates, a glitch also occurs when the number of the delay elements is updated. Referring to FIG. 5, the dashed line in FIG. 5 represents the output after the clk_in is delayed by n delay elements, and the dash-dot line represents the output after the clock input signal clk_in is delayed by n+1 delay elements. At the time of T0 when transition happens at MSEL, because the delay time represented by the thin solid line is different from the delay time represented by the heavy solid line, a glitch occurs at point c in the delay element Sn.
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