This invention relates, in general, to arrays for performing logic functions, and more particularly, to a high speed, fully precharged programmable logic array.
Arrays for performing logic functions, typically called logic arrays or programmable logic arrays, have been used to replace random logic in many digital circuits. Such programmable logic arrays are especially useful in the control section of digital systems and are frequently thought of as read only storage, read only memories, or the such. The programmable logic array is a well known convenient way of using arrays of identical circuit elements to implement arbitrary logical functions in integrated circuits. Such arrays are typically arranged in two portions or arrays. The first array generates product of sum terms and is referred to as the AND array or plane, and the second array generates sum of product terms and is referred to as the OR array or plane. Typically in NMOS technology each of the portions consists of NOR arrays which are interconnected so that the first portion performs a logical AND function and the second portion performs a logical OR function.
When a programmable logic array is implemented on an integrated circuit it becomes desirable to reduce the size of the circuit, reduce the power consumption, and speed up the operation of the circuit. One way to reduce the power consumption of the circuit is to precharge the circuit. One such dynamic programmable logic array is shown in "High-Speed Dynamic Programmable Logic Array Chip" By R. A. Wood, in IBM Journal of Research and Development, Vol. 19, No. 4, July 1975 begining at page 379. However, there are still improvements that could be made to a programmable logic array which would make the circuit smaller, and increase the operating speed which are not disclosed in Wood's article.
Accordingly, it is an object of the present invention to provide an improved programmable logic array.
Another object of the present invention is to provide a logic array having a virtual ground that can be floated, pulled high during array precharge, and then controllably coupled to ground all with a single control signal.
Yet another object of the present invention is to provide a programmable logic array which has a sense or status line through the array that asynchronously determines the end of precharge of the OR array.
A further object of the present invention is to provide a method for achieving high speed operation and low power consumption of a logic array.
USPTO Backgrounds
USPTO Backgrounds