Semiconductor processing includes many lithography steps, wherein a pattern defined on a lithographic mask (also referred to as the reticle) is illuminated by a light source, resulting in the printing of the pattern on a photoresist film deposited on a layer stack that is built up layer by layer on a semiconductor wafer.
The reduction of feature sizes in present-day integrated circuits has commanded an evolution in terms of the applied lithography. One development is the move from Deep Ultraviolet (DUV) light wavelengths towards EUV. As materials are too absorbing at the extremely small wavelengths applied in EUV lithography (typically 12-15 nm), EUV lithography relies on reflectivity rather than transparency of the mask and optics. The masks are produced from a substrate onto which a multilayer stack is deposited, thereafter referred to as an EUV blank or multilayer blank. The material (e.g., silicon and molybdenum) and the thickness of the layers are chosen so that EUV light reflected off the subsequent interfaces interferes constructively. An absorber layer is deposited on top of the blank, and subsequently patterned based on the intended mask pattern that is to be transferred onto a wafer through the lithography process. The areas where no absorber is present (referred to as the ‘clear’ areas) reflect the incoming light. The reflected light is focused through a mirror system onto a semiconductor wafer.
During manufacturing of the blank, small particles may become trapped within the layers, imperfections may occur in the layers themselves, or there may be imperfections of the substrate onto which the multilayer is deposited, all leading to microscopic bump- or pit-type defects in the multilayer. Such faults manifest themselves as blank defects, also referred to as “multilayer (ML) defects” or “phase defects”. The depth or height of these defects is in the order of nanometers, which initiates a local disturbance of the constructive interference referred to above. In this way, ML defects may cause considerable printing errors. In the lateral direction these defects are typically of the order of the critical half pitch of the pattern or larger.
Blank manufacturers have made efforts to minimize the occurrence of ML defects. Nevertheless, the appearance of a small residual number of ML defects is currently considered to be unavoidable in state-of-the-art blank manufacturing. Therefore techniques have been developed to mitigate the influence of the ML defects on the printed pattern. An ML defect avoidance approach consists of shifting the pattern on the blank, thereby covering a maximum number of defects by absorber material, so that they have no impact on the printed pattern. This technique is referred to as ‘pattern shift’.
In document “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects”, Kagalwalla et al, Journal of Micro/Nanolithography, MEMS and MOEMS, 13(4), 043005 (October-December 2014), three ways of shifting the pattern are described: shifting the entire pattern with respect to the blank (translation of the pattern), rotating the entire pattern, or in case the mask contains multiple patterns re-arranging the “floorplan”, i.e. shifting the individual patterns with respect to each other.
While such techniques allow to mitigate the influence of a number of defects, they are unable to produce a mask wherein potentially all ML defects are neutralized. Defect coverage yield is heavily dependent on a number of parameters, including the pitch of the mask pattern, the pattern density (=amount of clear), the number of blank defects, the lateral defect sizes and the amount of uncritical parts in the design. The success rate of the technique is therefore limited and the percentage covered stays relatively low.
USPTO Backgrounds
USPTO Backgrounds