Peripheral component interconnect Express™ (PCI Express or PCIe) is a high performance, generic and scalable system interconnect for a wide variety of applications ranging from personal computers to embedded applications. PCIe implements a serial, full duplex, multi-lane, point-to-point interconnect, packet-based, and switch based technology. Current versions of PCIe buses allow for a transfer rate of 2.5 Giga bit per second (Gbps) or 5 Gbps, per lane, with up to 32 lanes. The PCIe bus is fully described in the PCI Express™ base Specification reversion 1.0a published on Apr. 15, 2003, by the PCI-SIG, incorporated herein by reference in its entirety merely for the useful understanding of the background of the invention.
The roundtrip time of a PCIe bus is a major factor in degrading the performance of the bus. With reference to FIG. 1, the roundtrip is the time period elapsed from the transmission of data, for example, by a PCIe root 110 to the acknowledgment of the data reception by a PCIe endpoint 120.
The roundtrip time of the PCIe bus 100 depends on the delay of a link 130 between the PCIe root 110 and the PCIe endpoint 120. Typically, this delay is due to an acknowledged (ACK) and flow control update latencies caused by the layers of a PCIe bus. Abstractly, the PCIe is a layered protocol bus, consisting of a transaction layer, a data link layer, and a physical layer. The data link layer waits to receive an ACK signal for transaction layer packets during a predefined time window. If an ACK signal is not received during this time window, the transmitter (either at the PCIe root 110 or endpoint 120) resends the unacknowledged packets. This result in inefficient bandwidth utilization of the bus as it requires retransmission of packets with no data integrity problem. That is, high latency on the link 130 causes poor bandwidth utilization.
In addition, a typical PCIe bus includes a credit mechanism in order to avoid receiver buffer overflow. As the latency of a PCIe bus is typically low, the root 110 and endpoint 120 often implement small receiver buffers with a small number of credits. The fast PCIe link enables fast flow controls (credits) update and full bus performance. However, when the bus latency increases the small number of flow control credits is a major limitation. Even if the receiver buffer is available, the flow control packet delay causes the transmitter (either at the PCIe root 110 or endpoint 120) to be idle for a long period prior to sending data. The result is an idle PCIe bus with low bandwidth utilization.
In a typical PCIe bus architecture the PCIe root 110 is directly coupled to the PCIe endpoint 120. In fact, the root 110 and the endpoint 120 are typically connected on the same electric board. Therefore, the roundtrip time is usually very short and the PCIe is not designed to properly operate in high latency. In order to provide applications and devices in which the PCIe root and endpoints are distributed and remotely located from each other, there is a need to de-couple the link between the PCIe's bus components. For example, it would be desirable to allow PCIe connectivity over a wireless medium or over a network. However, extending the distance of the link between a PCIe root and endpoint component would significantly increase the latency of the link, and therefore degrade the performance of the bus.
Thus, it would be advantageous to provide a high performance interconnect bus that would allow distributed connectivity.
USPTO Backgrounds
USPTO Backgrounds