When an information processing device (computer), for example, executes a computer program (also referred to as a program for short), the information processing device generates a plurality of processes that are units in which the program is executed. In addition, the information processing device generates, in the process, a plurality of threads that are units in which processing is executed.
In this kind of information processing device, when processing of one thread for example within a process is delayed, this delay negatively affects processing of other threads within the same process. Thus, for example, a fault such as a process terminating in an abnormal manner is liable to occur in the information processing device.
Furthermore, the same fault of a process terminating in an abnormal manner is liable to occur in the information processing device as well when memory capacity allocated to a process is insufficient.
Reference Document 1 (Japanese Laid-open Patent Application Publication No. H10-049219) discloses a technique in which a computer detects a state where a fault is likely to occur in the computer. Reference Document 2 (Japanese Laid-open Patent Application Publication No. 2007-226399) discloses a technique in which garbage collection processing (hereinafter, also referred to as GC processing) is used for a computer to detect a state where a fault is likely to occur in the computer. GC processing is processing in which, when a memory region that is associated with processing of a program while executing the program remains associated with the processing of the program even after the program terminates, a computer cancels (releases) the association. In Reference Document 2, a computer detects a state where a fault is likely to occur in the computer by measuring a time interval in which CC processing is executed and increase in memory capacity after the GC processing, and comparing those measurement values with threshold values.
In Reference Document 3 (Japanese Laid-open Patent Application Publication No. 2008-077266) and Reference Document 4 (Japanese Laid-open Patent Application Publication No. 2008-250669), methods are disclosed in which an upper limit for the number of threads on a server is controlled based on a prediction value for a message processing time on the server. Furthermore, in Reference Documents 3 and 4, methods are also disclosed in which an upper limit for the number of terminals that respectively connect to a plurality of web servers is controlled based on processing state of requests in the plurality of web servers.
In Reference Documents 1 to 4, there is no description whatsoever of a technique that avoids a situation in which a fault occurs in a computer due to a delay in processing of a thread or a shortage of memory capacity allocated to a process.
USPTO Backgrounds
USPTO Backgrounds