Power-up refers to when power is applied to initialize the chip for operation. Initialization sets the chip's internal signals at the initial logic levels. Logic levels include logic low or 0 and logic high or 1. Generally 0 corresponds to zero volts and 1 corresponds to VDD, which is the chip's operating voltage.
In general, an IC includes different modes of operation, such as normal and test, or performs various functions. The various chip modes or functions are controlled by one or more external control signals. Activation of one or more of these control signals causes the chip to operate in certain operating modes or perform specified functions. These external control signals or system level signals are generated by other ICs within the system. Typically, certain external control signals of the chip are active low signals.
The fact that certain external control signals are active low can be problematic. For example, at least at the system level, various ICs power-up at different times. As the chip is powered-up, the chip's internal signals are initialized and set at their designated levels. A chip ready signal is issued to signify that the chip has been initialized and ready for operation. Typically, the chip ready signal is issued when the operating voltages that are supplied to the various sub-circuits of the IC reach a predetermined level.
However, different chips within the system take different amount of time to power-up. As such, there may be occasions when one (first) chip issues a chip ready signal before another (second) chip. If, for example, the second chip is the chip that generates the external control signals for the first chip, a problem arises. Since certain control signals on the first chip are active low, incomplete initialization of the second chip results in the external control signal of the first chip to be in an active and unintended state. Depending on which control signals are affected, the IC can be caused to enter into, for example, test mode unintentionally. As will be appreciated by those skilled in the art, this result is undesirable as a user may think that the chip is operating in normal mode.
Conventionally, to ensure that the IC is operating in the intended or normal mode, the control signals are cycled several additional times before the IC is accessed for normal operation. To illustrate the problem discussed above, a description of how such a problem may be encountered in a conventional dynamic random access memory (DRAM) IC is provided.
In the discussion to follow, including the detailed description of the invention, a postscript "n" or "p" may be appended to a control signal or its acronym. The "n" indicates that the signal is active when it is "low" (i.e., active low) and the "p" indicates that the signal is active when it is "high" (i.e., active high).
FIG. 1 shows a DRAM chip 7 and a memory controller 9 of, for example, a computer system. During system power-up, the operating voltages V.sub.DD and ground (GND) are supplied to various circuits including the controller and the memory chip. A boost pump 60 in the chips receives V.sub.DD and GND and generates a "boosted" voltage Vpp in response. Vpp, which generally has an amplitude greater than V.sub.DD, is distributed to various sub-circuits within the chip. Additionally, boost pump 60 provides a CHRDYp signal. When the Vpp reaches a desired level, boost pump generates an active CHRDYp signal, indicating that the respective chip is ready for operation.
The memory chip and controller communicate via RASn, CASn, and WEn signals. The signals originate at the controller and are passed to the memory chip, serving as external control signals to dictate memory chip functions. In particular, the RASn is the external master control signal of the memory chip. As such, the RASn needs to be active to initiate an operation. For example, a regular memory access cycle is initiated by RASn going low with row addresses being active. CASn then goes low with column addresses being activated. Depending on whether WEn is high or low, the access is either a read or write access.
A RAS interface 50 receives RASn and CHRDYp signals as inputs and provides an output RAS internal (RINTp) signal. The RINTp is an internal signal used to control various subcircuits, along with CAS and WEn. As shown, RINTp is active when both CHRDYp and RASn are active.
The memory chip also includes different modes of operation, such as normal and test. The test mode enables user to test the memory chip. In test mode, memory accesses such as reads and writes behave differently than in normal mode. A test mode decoder 80 is provided to control the chip's operating mode. The test mode decoder receives RINTp, CASn, and WEn signals and generates an output signal TMp. An active TMp signal causes the memory chip to operate in test mode. As RINTp is derived from RASn, it effectively plays a role in determining the chip's mode of operation.
In conventional DRAMs, a problem arises during power-up. If RASn, CASn, and WEn signals are active when CHRDYp becomes active, the memory chip enters test mode. Since RASn, CASn, and WEn are active low signals, this scenario can easily occur. For example, if the controller takes longer to initialize than the memory chip, than RASn, CASn, WEn would be low when CHRDYp is active because the controller has not completely powered up yet. This scenario causes the memory chip to enter test mode unintentionally, resulting in the chip to operate differently.
From the above discussion, it is therefore desirable to prevent an IC from inadvertently entering into an unintended mode of operation during power-up.
USPTO Backgrounds
USPTO Backgrounds