1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a memory array with improved isolation regions formed between the pin junctions underlying an array of one resistor/one diode (1R1D) bottom electrodes.
2. Description of the Related Art
Typically, an 1R1D resistor random access memory (RRAM) uses n-doped silicon (n+ Si) bit lines. An array of bottom electrodes are formed over the bit lines with intervening p-doped (p+) Si areas. The interface between the p+ Si and the n+ Si bit lines forms a p/n junction. Conventional fabrication processes permit the formation of adequate oxide isolation regions between the bit lines, as the trench and oxide isolation structures can be formed relatively early in the process, extending into the underlying silicon (Si) substrate. However, it is more difficult to isolate adjacent p/n junctions along a common (the same) bit line. The lack of proper isolation may result in crosstalk between electrodes during reading and programming operations.
FIG. 1 is a partial cross-sectional view of a trench isolated resistor memory array in two orthogonal axes (prior art). Each n+ bit line is isolated from the other bit lines by oxide trenches, as is showed in the left-hand side of FIG. 1. The right-hand side of the figure shows the cross-section along an n+ bit line. Where there are p+ areas, a p/n junction is formed overlying the n+ bit line. Although the p+ areas and the bottom electrodes are self-aligned, the p+ areas are formed by an ion implanted shallow junction. As a result, the breakdown voltage may be low and the crosstalk between adjacent bottom electrodes may be high.
It would be advantageous if adjacent p/n junctions of a 1R1D bottom electrode could be more adequately isolated along a common bit line.
USPTO Backgrounds
USPTO Backgrounds