1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to methods of forming polyconductor line ends and a memory cell including the polyconductor line ends.
2. Background Art
Memory used in integrated circuit (IC) chips can come in a variety of forms such as static random access memory (SRAM), dynamic random access memory (DRAM), Flash memory, etc. The industry has a continuing drive to shrink memory cells to remain competitive. As one attempts to shrink cells, process constraints can limit the amount of shrinkage. As isolation regions (e.g., shallow trench isolation (STI)) push closer together, the distance that a polysilicon conductor (polyconductor or PC) can extend pass the STI is decreased. The cell dimension is limited by how close one can place to PC lines end-to-end (facing each other or otherwise) on the isolation region. Thus, the performance of a memory cell is directly influenced by the end-to-end space that can be achieved between PC line-ends.
The ability to pattern a small space between PC line-ends has both lithographic and etch limitations. The etch limitations come from the fact that during the trim step (i.e., the process in which the gate critical dimension (CD) that was printed in photoresist is reduced to that which is needed in the final poly) the line-ends trim more than the gates. In particular, as shown in FIG. 1, a specific PC line-end 2 may be targeted to be, for example, 100 nm, past an active region 4 (scenario A) or contact layer 6 (scenario B) into an isolation region 8, but due to limitations of the resist, trim processing and rounding, PC line-end 2 does not end up being 100 nm past the active region 6 or contact layer 8. In some instances, PC line-end 2 is etched back over active region 4. In any event, it is common for a gate length to be incorrect because of this situation. Further scaling magnifies the situation.
There are many methods which are being pursued in the industry to enable the tighter PC line-end spacing. For example, one popular approach includes a double exposure-double etch scheme. In this case, as shown in FIG. 2A, a polyconductor (PC) 12 is exposed and etched over an active region 14 and fully across an isolation region 16 to print a gate 18 (intersection of PC 12 and active region 14), and then another exposure and etch, shown in FIG. 2B, is used to remove polyconductor 12 over the isolation region 16 to form line-ends 22 and, hence, the devices. This approach attains the necessary sizes and precision, however, the cost incurred is significant because of the need for two exposures and two etches for one level. It allows the etch step for opening line-ends 22 to be completely directional (no trim) and also creates PC tips that are relatively less rounded. The rounded line ends trim very quickly during the etch process, which makes controlling the etch difficult.
A second approach, shown in FIGS. 3A-B, attempts to decrease the trim rate of line-ends 22 (FIG. 2B) by printing a bulged region 24 (FIG. 3A) in the resist at a line-end for polyconductor 12 (single exposure, single etch) over isolation region 16. That is, line ends 22 (FIG. 2B) are printed in the resist with bulged region 24 immediately adjacent to active region 14. This approach offers smaller spacing due to the decreased trim of the line-ends, but creates bulbous line-ends 26 (FIG. 3B). Unfortunately, bulbous line-ends 26 usually land on active region 14, which causes undesirable gate 18 length variation along the device. A third approach includes using a double exposure with a single etch. While this approach does not eliminate the etch effects, it allows for a smaller line-end space to be printed in resist if the illumination is optimized for the second exposure. A fourth approach under exposes the PC using a block mask, and uses alternating phase shift masks (Alt PSM) scheme and a break through with etch.
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