1. Field of the Invention
The present invention relates to electronic imaging devices and, in particular, to CMOS imagers having a relatively small number of analog components in each pixel.
2. Description of Related Art
There presently exist many alternatives to CCD sensors for generating video or still images. The various schemes can be grouped into two basic classes, depending upon whether signal amplification is performed at each pixel site or in support circuits outside the pixel array. Passive-pixel sensors perform amplification outside the array. Passive pixel sensors exhibit pixel simplicity and maximized optical fill factor. Active-pixel sensors include an amplifier at each pixel site. Active pixel sensors optimize signal transfer and sensitivity.
The simplest passive pixel comprises a photodiode and an access transistor. The photo-generated charge is passively transferred from each pixel to downstream circuits. The integrated charge must, however, be efficiently transferred with low noise and non-uniformity. Since each column of pixels often shares a common row or column bus for reading the signal, noise and non-uniformity suppression are typically facilitated in the xe2x80x9ccolumnxe2x80x9d buffer servicing each bus. One example of a prior art passive pixel implementation is shown in FIG. 1. It uses a buffer consisting of a transimpedance amplifier with capacitive feedback to yield reasonable sensitivity considering the large bus capacitance. Such charge-amplification was not generally practical for on-chip implementation in early MOS imaging sensors. Accordingly, alternative schemes compatible with NMOS technology were used. The basic prior art scheme shown in FIG. 2 was mass-produced by Hitachi for camcorders. The key refinements over the FIG. 1 scheme include anti-blooming control and circuitry for reducing fixed pattern noise. Though these imagers were inferior to the emerging charge coupled device (CCD) imagers available at the time, similar MOS imagers are still being offered commercially today.
Subsequent efforts at improving passive-pixel imager performance have also focused on column buffer enhancements. The column buffer was improved by using an enhancement/depletion inverter amplifier to provide reasonably large amplification in a small amount of real estate. Its 40 lux sensitivity was still nearly an order of magnitude below that of competing CCD-based sensors. Others worked to enhance sensitivity and facilitate automatic gain control via charge amplification in the column buffer. More recently, the capacitive-feedback transimpedance amplifier (CTIA) concept of FIG. 1 has served as a basis for further development, as exemplified by U.S. Pat. Nos. 5,043,820 and 5,345,266. The CTIA is nearly ideal for passive-pixel readout if the problems with temporal noise pickup and fixed-pattern noise are adequately addressed.
Though much progress has been made in developing passive-pixel imagers, their temporal S/N performance is still fundamentally inferior to competing CCD imagers. Their bus capacitance translates to read noise of at least 60 e- for 352xc3x97288 formats. Since the bus capacitance increases with array size, larger formats have even higher noise. CCDs, on the other hand, typically have read noise of 20 to 40 e- at video frame rates. The allure of producing imagers with conventional MOS fabrication technologies rather than esoteric CCD processes (which usually require many implantation steps and complex interface circuitry) encouraged the development of active-pixel sensors. In order to mitigate the noise associated with the bus capacitance, amplification was added to the pixel via the phototransistor. One such approach called a Base-Stored Image Sensor (BASIS) used a bipolar transistor in emitter follower configuration with a downstream correlated double sample to suppress random and temporal noise. By storing the photogenerated-signal on the phototransistor""s base to provide charge amplification, the minimum scene illumination was reduced to 10xe2x88x923 lux in a linear sensor array. However, the minimum scene illumination was higher (10xe2x88x922 lux) in a two-dimensional BASIS imager having 310,000 pixels because the photoresponse non-uniformity was relatively high (xe2x89xa62%). These MOS imagers had adequate sensitivity, but their pixel pitch was too large at about 13 xcexcm. This left the problem of shrinking the pixel pitch while also reducing photoresponse non-uniformity.
Since the incorporation of bipolar phototransistors is not strictly compatible with mainstream CMOS processes, some approaches have segregated photodetection and signal amplification. U.S. Pat. Nos. 5,296,696 and 5,083,016, for example, describe active-pixel sensors essentially comprising a three-transistor pixel with photodiode. These implementations still exhibit inadequate performance. The ""696 patent, for example, augments the basic source-follower configuration of the ""016 patent with a column buffer that cancels fixed pattern noise, but adds a fourth transistor that creates a floating node vulnerable to generation of random offsets for charge-pumping and concomitant charge redistribution. The ""016 patent offers a method for reducing offset errors, but not with adequate accuracy and resolution to be useful for competing with CCDs. Furthermore, these and other similar approaches requires 3-4 transistors in the pixel (at least one of which is relatively large to minimize 1/f noise) in addition to the photodiode. These implementations also require off-chip signal processing for best S/N performance because none addresses the dominant source of temporal noise. In order to eliminate or greatly suppress the reset noise (kTC) generated by resetting the detector capacitance, a dedicated memory element is usually needed, either on-chip or off-chip, to store the reset voltage to apply correlated double sampling and coherently subtract the correlated reset noise while the photo-generated voltage is being read.
This basic deficiency was addressed in U.S. Pat. No. 5,471,515 by developing an active pixel sensor (APS) that uses intra-pixel charge transfer to store the reset charge at each pixel at the start of each imaging frame. The floating gate APS facilitates correlated double sampling with high efficiency by adding several transistors and relying on a photogate for signal detection. The concomitant drawbacks, however, are intractable because they increase imager cost. The former adds several transistors to each pixel and several million transistors to each imager thereby reducing production yield. The latter is not compatible with standard CMOS gate fabrication so a non-standard process must be developed. These deficiencies were tackled in U.S. Pat. Nos. 5,576,763 and 5,541,402 issued to Ackland et al. and U.S. Pat. Nos. 5,587,596 and 5,608,243 issued to Chi et al. Ackland addressed the image lag issues associated with the intra-pixel charge transfer means. But his approach still requires a nonstandard CMOS process. Chi reduced pixel complexity by using the simplest possible active pixel comprising only a phototransistor and reset MOSFET. Chi""s implementation still suffers from reset noise and compromises spectral response at longer wavelengths because the photodiode is in an n-well.
In addition to the aforementioned APS schemes that pursue charge-based signal manipulation to facilitate low temporal and fixed pattern noise in CMOS, alternative schemes use the native amplification provided by CMOS. FIG. 3, for example, is a schematic circuit diagram illustrating a transimpedance amplifier system for active-pixel imaging sensors (U.S. Pat. No. 4,794,247). This disclosure teaches a pixel-based CTIA with offset cancellation. This design provides high sensitivity if the feedback capacitance is minimized to thereby maximize transimpedance. Unfortunately, the need for both p-type and n-type transistors within the small pixel creates severe pixel real estate problems for the designer. The pixel layout is thus very inefficient in conventional LOCOS (local oxidation of silicon) processes because the p-FET must be in an n-well and the n-FET in a p-well. Ideally, only one transistor polarity should be present in the pixel to minimize circuit area and thereby maximize photodetector area.
The present invention comprises an active-pixel low-noise imaging system for implementation in CMOS or in other semiconductor fabrication technologies. The low-noise amplifier system greatly minimizes reset (kT/C) noise while simultaneously providing global reset using a minimum of active circuitry in each pixel including the photodetector and three transistors of identical polarity. The first transistor serves as a reset and a transimpedance amplifier to facilitate high impedance and suppress reset noise without needing expensive on-chip or off-chip memory. The second transistor is an access MOSFET used to read the signal from each pixel and multiplex the signal outputs from an array of pixels. The third MOSFET resets the detector after the integrated signal has been read. Since the detector sense node is xe2x80x9cpinnedxe2x80x9d by the feedback amplifier, reset noise is reduced to that generated by the much smaller feedback capacitance. Also, by using a small but well-defined feedback capacitor, an amplifier with a narrow bandwidth can be used, provided its unity-gain frequency is sufficient; this is typical of DC amplifiers operated subthreshold. Since the pixel-base amplifier""s output capacitance is far smaller than the bus capacitance, the total energy consumed during reset is very small and overall power consumption is kept at a level consistent with battery-powered operation. In addition, all the pixels may be reset simultaneously to facilitate synchronous image formation across the entire imager. In the typical two-dimensional array, the signal readout and multiplexing are performed, as in the prior art, by horizontal and vertical shift registers.
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