The present invention relates in general to semiconductor device packaging and, more particularly, to forming a semiconductor device having more than one leadframe and more than one device contained within.
In general, contemporary electronic devices are designed with critical design criteria such as size, weight and power consumption in mind. Such criteria are continuously diminished, as the designs become more complex to enable greater functionality. Demand for enhanced functionality and performance has resulted in attempts by component manufacturers to integrate devices based on different technologies in a single package.
One approach is to place two or more bare semiconductor dice on a substrate having a conductive network formed to provide electrical interconnection of the dice to form a multi-chip module, or MCM. The substrates used in MCMs are typically multi-level printed circuit boards, where some of interconnections are run external to the module for connection to the customers"" printed circuit board. The substrate of the MCM is then covered with a lid or encapsulant to form a finished packaged device.
An example of a prior art multi-chip module 500 configured as a voltage regulator is provided in FIG. 1. As shown, the MCM voltage regulator 500 includes a printed circuit board 520 that supports a plurality of dice 540 and 542, where the dice are wire bonded to the printed circuit board traces 530-532 by wires 560, 561.
Typical of many MCMs that use mixed die technology to realize device 500, die 542 is a drive transistor of power MOSFET technology, and die 540 is a voltage regulator switch of analog technology. Thus, the wire bonds required by power MOSFET die 542 to carry large currents are of large aluminum or aluminum alloy wire (for example one hundred twenty-five micrometers in diameter), and the wire bonds required by the analog die 540 for fast signal transmission and low attenuation are of small gold or gold alloy (for example fifty micrometers in diameter).
The bond head of a tool that bonds the gold wires is about two hundred fifty micrometers in diameter and for the aluminum wire it is about four thousand micrometers in diameter. The different wire bond materials used require that the traces have a compatible surface material present for best performance and reliability to attach the wire bond. In this example, trace 532 and a portion 534 of trace 531 are plated at least partially with a silver nickel alloy to facilitate the gold wire bond attach. Aluminum bond wires 561 for the power MOSFET are attached to trace 530 and a copper region 533 of trace 531. The aluminum wire bonds are made before the gold wire bonds as the high temperatures used to bond the gold wires oxidizes the copper traces which would result in the aluminum bond having poor strength and reliability.
The traces are further connected to the external leads 510 of the finished MCM to provide electrical connection to a customer printed circuit board having a connection pitch or distance 503.
A distance 501 must be provided between bond leads to allow a window frame (not shown) used to hold the substrate during the wire bonding process to clear all wires and devices. This provision of distance described above results in a long effective conductivity path 502 between die pad 871 of analog switch. 540 and die pad 872 of drive transistor 542. The long effective conductivity path degrades signal transmission especially in applications requiring fast electrical response or those carrying small electrical currents.
The module is sealed from the environment using an encapsulant 590 to form a finished multi-chip module. MCM""s thus formed, while expensive, are highly space efficient and require less printed circuit board space than individually packaged devices placed on the customer""s circuit board.
Reliability of multi-chip modules is very important to manufacturers and users. Complete functional testing of the various semiconductor dice used, particularly high speed testing and testing after burn-in are fundamental techniques to ensure reliability. A drawback of multi-chip modules is they are extremely difficult to test because only some of the contact pads of the semiconductor dice can be coupled to an external tester by way of leads that extend from the package. Testing is further problematic as it is difficult or impossible to test the semiconductor dice fully before they are mounted to the substrate. Moreover, once the various semiconductor dice are connected to each other, their characteristics are modified; parasitics created by the interconnection become difficult, if not impossible, to measure. Testing is particularly difficult at high speeds. Thus the functionality of the integrated die chips inside the multi-chip module cannot be completely tested because there is no way to couple a tester to individual contact pads on the individual semiconductor die.
Furthermore, MCM""s are very expensive to make, as the multi layer printed circuit board that acts as the substrate is complex to manufacture. In addition, different types of die within the module require different assembly equipment, materials and methods to attach them to the substrate. Attachment introduces further problems. Due to window frames that must be used during the bonding process to hold down the substrate while wire bonding and the sizes of the bond tool heads, space must be provided between leads for these items to allow wire bonding, which in turn limits the density. In general, the larger the bond wires the larger the areas around the die that need to be set aside for the window frames used to hold down the substrate.
A further problem with MCM printed circuit boards is that it is expensive and complex to make traces of varying material for wire bonding. For example, power devices are preferably wire bonded to large, thick traces to conduct large currents and heat, while analog devices are preferably wire bonded to thin and short traces for the speed needed by the analog devices. These problems with MCM""s have resulted in low yields and high costs.
Accordingly, it would be advantageous to have a structure and method of forming a semiconductor device that has the advantage of allowing integration of multiple semiconductor dice into a single packaged device while avoiding the problems of prior art.
USPTO Backgrounds
USPTO Backgrounds