1. Field of the Invention
The present invention relates to a data-rewritable non-volatile semiconductor memory device. It also relates to an electronic card with the non-volatile semiconductor memory device mounted thereon. It further relates to an electronic device that employs the electronic card. The non-volatile semiconductor memory device includes, for example, an NAND-type EEPROM.
2. Description of the Related Art
An electrically erasable programmable EEPROM has been known in the art as one of semiconductor memories. For example, an NAND-type EEPROM including NAND cells has received attention because it can be highly integrated. Each NAND cell includes a plurality of serially connected memory cells, each of which is the unit of one bit memory. The NAND-type is utilized, for example, in a memory card to store image data output from a digital still camera.
A memory cell in the NAND cell-type EEPROM has a MOSFET structure that includes a floating gate (charge storage layer) and a control gate stacked on an insulator film formed over a semiconductor substrate. A plurality of memory cells are serially connected such that adjacent ones share a source/drain to configure a NAND cell, which is connected as a unit to a bit line. Such NAND cells are arrayed in matrix to configure a memory cell array. The memory cell array is integrally formed in a p-type well (or p-type substrate).
NAND cells arranged in the column direction of the memory cell array are commonly connected at one end (drain side) to a bit line via respective selection gate transistors and connected at the other end (source side) to a common source line via respective selection gate transistors as well. Control gates of memory transistors are commonly connected as a word line (or control gate line) and gate electrodes of selection gate transistors as a selection gate line in the row direction of the memory cell.
Such the NAND cell-type EEPROM operates as follows.
Data writing is shown in FIG. 12. As shown, after write data is input, operations of write pulse applying and write-verify are repeated, and when completion of writing is detected immediately after the write-verify operation, the data writing is finished.
Data writing is performed sequentially from a memory cell located farthest from a bit line contact, that is, a memory cell located closest to a source line. In write pulse applying (see FIG. 6), a high voltage VPP (=approximately 18 V) is applied to a control gate of a selected memory cell. An intermediate potential VM (=approximately 10 V) is applied to the control gate of a memory cell located closer to the bit line contact than the selected memory cell. A voltage of 0 V or a supply voltage VCC is applied to the bit line depending on the data. In this case, the supply voltage VCC is applied to the selection gate on the bit line contact side, and 0 V to the selection gate on the source line side. When 0 V is applied to the bit line, its potential is transmitted to the channel in the selected memory cell. In this case, a difference in voltage between the selected word line and the channel in the selected memory cell is as large as VPP. Accordingly, electrons are injected from the channel of the selected memory cell into the floating gate by tunnel current to shift the threshold of the selected memory cell to a positive value. This state is regarded as “0”, for example.
When the supply voltage VCC is applied to the bit line, the voltage at the selection gate on the bit line contact side is equal to VCC. Accordingly, VCC−Vtsg is transferred to the channel in the NAND cell to bring it into a floating state (Vtsg is the threshold voltage of the selection gate transistor). Thereafter, the word line is charged up to VPP, VM. On charging up to VPP, VM, the capacitive coupling between the word line and the channel in the NAND cell boosts the voltage at the channel in the NAND cell from VCC−Vtsg to Vboost (approximately 8 V) (see FIG. 11). In this case, the difference in voltage between the selected word line and the channel in the selected memory cell is as small as VPP−Vboost. Accordingly, electron injection can not occur and thus the threshold makes no change and holds a negative value. This state is regarded as “1”.
Data erasing is performed simultaneously to all memory cells in a selected NAND cell block. Namely, all word lines (that is, control gates) in the selected NAND cell block are kept at 0 V, and a high voltage VERA (=approximately 22 V) is applied to the p-type well (or p-type substrate) to bring the bit lines, the source line, and all word lines and all selection gate lines in non-selected NAND cell blocks into a floating state. Accordingly, in every memory cell in the selected NAND cell block, electrons are released from the floating gate to the p-type well (or p-type substrate) by tunnel current to shift the threshold voltage to a negative value.
Data reading is performed by detecting whether current flows in the selected memory cell on condition that the control gate of the selected memory cell is kept at 0 V. In addition, other word lines (that is, control gates of memory cells) and selection gates are set at an intermediate voltage for reading, VREAD, slightly higher than the supply voltage. (Generally, a voltage level equal to or lower than 2-times VCC and having a value of 5 V or below is employed).
A conventional timing example of write pulse applying to the above NAND cell-type EEPROM is shown in FIG. 6. An other known conventional example of write pulse applying is described as writing operation in JP-A 10-283788.
The use of conventional data writing methods may cause no problem on the reliability of products. Recently, however, a further improvement in the reliability of data writing is desired, and the further improved reliability leads to an improved product yield.
On data writing, an erroneous write failure may occur in a memory cell to be “1”-WRITE (a failure associated with erroneous write of “0” data when VPP is applied to the selected word line during write pulse applying). In order to achieve a further improvement in the reliability against such the failure, it is effective to elevate the Vboost voltage level. The higher the Vboost voltage level, the lower the risk of the erroneous write failure can be reduced, which is caused from the electron injection into the floating gate by tunnel current. Therefore, it is desirable to employ such data writing in products that can elevate the Vboost voltage level more than the operation shown in FIG. 6 or the above JP-A 10-283788.
USPTO Backgrounds
USPTO Backgrounds