In fabricating integrated circuit components, photolithographic patterning and etch can be used to transfer a desired pattern of a masking material, such as a photoresist, to an underlying substrate material or materials. The masking material pattern can include a series of spaced projections atop the underlying substrate material such that etching can thereby produce a corresponding series of spaced features in the underlying substrate material or materials.
Advances in photolithography have enabled increasingly smaller patterns to be transferred into substrate materials, which can allow the formation of smaller integrated circuit components at lower cost. However, photolithographic methods are subject to line edge roughness (LER). LER can refer to roughness on the surface of masking material patterns and on the sidewalls of the underlying substrate features after the masking pattern is transferred.
It is desirable that the walls of masking patterns and/or features etched therefrom be smooth. However, as device dimensions and, accordingly, mask features get smaller, the walls of masks and/or features etched therefrom can become intolerably rough. The line edge roughness can result in undesirable effects in integrated circuit components, such as transistor leakage, for example. LER effects can become more of a problem as the critical dimensions of transferred patterns become increasingly smaller.
One prior approach to reducing LER of a photoresist masking feature comprises a short isotropic etch using a halogen-containing gas after mask formation. However, such approach does not adequately improve sidewall LER, reduces, or “trims,” the thickness of the photoresist mask features, and can form breaks in long-running masking features, such as in parallel lines.
Accordingly, it is desirable to identify an improved method of reducing LER of masking features and patterned features formed therefrom using photolithographic processes.
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