1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of synchronising between clock domains within data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems having multiple clock domains. As an example, one clock domain may operate at a high frequency to perform computationally intensive tasks while another clock domain operates at a lower clock frequency to perform less demanding tasks. In order that these two clock domains can communicate, it is necessary to provide synchronisation mechanisms for passing signals between the domains. One known way of doing this is to utilise a first-in-first-out memory (FIFO) between the two clock domains with data values being written into the FIFO from one clock domain and then read out of the FIFO from another clock domain. In order that the writing and reading operations can be appropriately controlled, and particularly to avoid overflow/underflow of the FIFO, it is necessary for the write pointer being used on the input side of the FIFO to be passed to the output side of the FIFO and similarly for the read pointer being used on the output side of the FIFO to be passed to the input side of the FIFO. The passage of these pointers across the clock domain boundary also requires that they be synchronised. In order to provide such synchronisation, it is known to provide a synchronisation path for the pointer signals utilising D-type latches to give glitch and meta-stability resistance at the price of increasing the latency with which a pointer can be passed across the boundary.
With the advent of more sophisticated clock control requirements, such as frequency scaling in which the clock frequencies being used can be adjusted over time to match the processing load, the nature of the synchronisation performed across a clock boundary will change with time. As an example, in one mode of a system both sides of the clock domain boundaries utilise the same clock which is synchronous across the clock boundary. In this circumstance no synchronisation is required. The system may also operate in a different mode in which the clock frequency on one side of the boundary is higher or lower than on the other side of the boundary and is asynchronous with the clock on the other side of the boundary. While it is possible to use synchronisation mechanisms which deal with these synchronisation challenges individually, it is difficult to switch between the use of these mechanisms.
One known way of switching between the synchronisation mechanism in use is to receive notification that a change of clocks requiring a change in synchronisation mechanism is required, drain all of the FIFO memories of any values that they are holding and then switch the synchronisation mechanism when there is no data in-flight. Such mechanisms may also require the master circuits transmitting data to be notified to stop transmitting further data until the change has been made. Such a change can take many hundreds of processing cycles to perform and this is a significant disadvantage.
USPTO Backgrounds
USPTO Backgrounds