1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming spacers on FinFETs and other semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
During the formation of FinFET devices, one process operation that is performed is the formation of sidewall spacers adjacent a previously formed gate structure. The sidewall spacers are formed to encapsulate or protect the gate structure. The sidewall spacers are typically comprised of silicon nitride and they are typically formed by conformably depositing a layer of spacer material across the device, including above the fins, and thereafter performing an anisotropic etching process that removes all of the spacer material except on the sidewall of the gate structure. Efforts have been made to protect the fins during this spacer etch process, but as device dimensions shrink, it is becoming more difficult to adequately protect the fins from damage during the spacer etch process.
Another import aspect of FinFET design is accurate and reliable control of the height of the fins in the finished device, which is especially important for bulk FinFET devices. The height of the fins of a FinFET device typically involves the following steps: (1) performing an etching process through a patterned mask layer to define a plurality of trenches in a semiconducting substrate which thereby defines a plurality of fin structures; (2) over-filling the trenches with an insulating material, such as silicon dioxide; (3) performing a chemical mechanical polishing (CMP) process using the hard mask layer as a polish stop to remove excess amounts of the insulating material; and (4) performing an etching process to remove a desired amount of the insulating material from within the trenches until such time as only the desired amount of the insulating material remains positioned in the bottom of the trenches (hereinafter referred to as the “CMP/etch-back” process). The height of the fins is set by the amount of the fin structure that is positioned above the remaining amount of insulating material that is positioned in the bottom of the trenches. However, in subsequent steps during the spacer and epitaxial deposition process that is performed to form source/drain regions, the height of the fins not protected by the gate structure may change due to over-etching or due to the use of HF chemistry.
The present disclosure is directed to various methods and devices that may solve or at least reduce one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds