The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device, and more precisely relates to a semiconductor device that conducts an electrical performance evaluation of a semiconductor member in the middle of the manufacture of the semiconductor device, and a method of manufacturing such a semiconductor device.
In the related art, in order to miniaturize and improve the functions of a semiconductor device, a semiconductor device is configured by laminating a plurality of semiconductor members (wiring substrates). With such a semiconductor device, a vertical hole-like wiring portion (hereinafter, also referred to as a TSV (Through Silicon Via)) that extends along the thickness direction of a silicon substrate is formed on the silicon substrate of each semiconductor member in order to obtain an electrical connection between each semiconductor member. Specifically, first, vertical holes that extend along the thickness direction of a silicon substrate is formed, and next, an electrode film composed of a metallic material such as, Cu is formed on surface of a wall portion of the silicon substrate in which the vertical hole is drawn.
With a semiconductor device that includes a TSV as described above, in general, an electrical performance evaluation (hereinafter, also referred to as a probe test) of the semiconductor members is performed in the middle of the manufacture thereof before the TSV is formed. In a probe test, an evaluation of the electrical performance of the semiconductor members is normally conducted by exposing a portion (pad portion) of the wiring and causing a probe to come into contact with the pad portion.
Therefore, when a probe test is performed, traces of the probe (hereinafter referred to as probe marks) remain on the pad portion of the wiring. In such a case, chemicals such as a plating solution, which are used in the formation process of the TSV (for example, a plating solution) after the probe test, may seep into the member from the probe marks and damage the pad portion. Further, since an opening portion for exposing the pad portion is provided, the pad portion does not obtain sufficient strength, and there may be a case when the pad portion is deformed or peeled during the formation process of the TSV. That is, due to the probe test, the yield, the reliability, and the like of the semiconductor device may decrease.
Therefore, in the related art, various techniques for decreasing the influence of the probe test described above have been proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2007-288150). Schematic cross-sectional diagrams of a wiring substrate that is proposed in Japanese Unexamined Patent Application Publication No. 2007-288150 is illustrated in FIGS. 23A and 23B. Here, the example illustrated in FIG. 23A is a first configuration example of the wiring substrate and the example illustrated in FIG. 23B is a second configuration example of the wiring substrate.
In the first configuration example as illustrated in FIG. 23A, a wiring substrate 400 includes a base material 401 and a base substrate 410 that includes a first insulating portion 402 that is formed on one face of the base material 401. Furthermore, a through hole 403 that extends in the thickness direction is formed on the inside of the base substrate 410. Further, the wiring substrate includes a first conductive layer 411 that is formed on the inside of the first insulating portion 402 to block one opening portion of the through hole 403 and a second conductive layer 412 that is formed on the surface of the first insulating portion 402. Furthermore, the wiring substrate 400 includes an island-patterned intermediate layer 413 that connects the first conductive layer 411 and the second conductive layer 412.
Further, the wiring substrate 400 includes a second insulating portion 414 that is formed on the second conductive layer 412. Furthermore, an opening portion 414a that is the contact region of the probe is formed in the region of the second insulating portion 414 that is positioned directly over the through hole 403. As described above, with the first configuration example, the conductive portion of the opening portion 414a of the second insulating portion 414 that is the contact region of the probe has a multi-layered structure, and in so doing, the influence of the probe marks described above is reduced.
On the other hand, in the second configuration example, as illustrated in FIG. 23B, a wiring substrate 420 includes a base material 421 and a base substrate 430 that includes a first insulating portion 422 that is formed on one face of the base material 421. Furthermore, a through hole 423 that extends in the thickness direction is formed on the inside of the base substrate 430. Furthermore, the wiring substrate 420 includes a conductive portion 431 that is formed on a first insulating portion 422 in order to block one opening portion of the through hole 423 and a second insulating portion 432 that is formed on the surface of the conductive portion 431.
Furthermore, in the second configuration example, an opening portion 432a is formed in the region of the second insulating portion 432 that does not overlap the opening region of the through hole 423 within the plane of the wiring substrate 420. That is, in the second configuration example, the influence of the probe test described above is reduced by placing the region of the conductive portion 431 which is the contact region of the probe within the plane of the wiring substrate 420 at a region that does not overlap the opening region of the through hole 423.
USPTO Backgrounds
USPTO Backgrounds