1. Field of the Invention
The present application relates to processor architecture, and more particularly to the execution of instructions with complex dependencies between instructions specifying different register widths.
2. Description of the Related Art
Typically, instructions are executed in their entirety in processors to maintain the speed and efficiency of execution. As instructions become more complex (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) the complexity of the processor architecture also increases accordingly. Additionally, complex data dependencies between instructions increase the complexity of the processor architecture. For example, when a first instruction produces a result that is needed as an input for execution of a second instruction, dependency logic can be used to ensure that the first instruction result is available before execution of the second instruction seeks to operate thereon. Dependencies become even more complex when lesser width (e.g. single precision) consumer instructions depend on the results of greater width (e.g. double precision) producer instructions, or conversely, when greater width consumer instructions depend on the results of one or more lesser width producer instructions.
Most current processors handle dependencies between greater width and lesser width instructions by using a rename unit to establish dependencies, and an issue unit to keep track of when dependencies have been satisfied. Tracking dependencies between lesser width instructions and greater width instructions using the rename and issue units can require tracking complex register dependencies, and may require increased complexity in rename and issue units. In some out of order processors, for example, establishing dependencies in the rename and issue unit requires that the dependent instruction be compared against all instructions in the issue queue. Additionally, forcing dependencies between instructions specifying different width registers can require a large amount of additional logic.
Complex processor architectures often consume extensive silicon area in the semiconductor integrated circuits, with more complex architectures generally requiring more silicon area than less complex architectures. Consequently, the more complex logic used by many conventional architectures to handle dependency issues between lesser width and greater width instructions can consume greater amounts of silicon area. Apparently, therefore, a method and/or system allowing processors to execute instructions having dependencies between lesser and greater width instructions, without consuming an unnecessarily large amount of silicon area, would be advantageous.
USPTO Backgrounds
USPTO Backgrounds