1. Field of the Invention
The present invention relates to a bit line pre-charge circuit for a semiconductor memory device.
2. Description of Related Art
A bit line pre-charge circuit pre-charges a pair of bit lines to a predetermined voltage level during a pre-charging operation. Generally, a pre-charge voltage is set to a half power supply voltage Vcc/2, which is a voltage halfway between a power supply voltage Vcc and a ground voltage of 0V.
When the pre-charge voltage is higher than the half power supply voltage Vcc/2, a data margin of logic “high” level data is reduced. On the contrary, when the pre-charge voltage is lower than the half power supply voltage Vcc/2, a data margin of logic “low” level data is reduced.
More particularly, in a state that a pair of bit lines is pre-charged to the half power supply voltage Vcc/2 during a pre-charging operation, a charge-sharing operation between a memory cell connected to a word line and the pair of bit lines occurs when the word line is selected during an active operation. At this time, if the bit line pair is pre-charged to a voltage that is higher than the half power supply voltage Vcc/2, a PMOS bit line sense amplifier may not be able to properly or sufficiently amplify the logic “high” level of data on the bit line pair to the power supply voltage.
In the same manner, if the bit line pair is pre-charged to a voltage level that is less than the half power supply voltage Vcc/2, an NMOS bit line sense amplifier may not be able to adequately or properly amplify the logic “low” level of data on the bit line pair to the ground voltage. Accordingly, it is necessary to maintain a pre-charge voltage level of the bit line pair at the half power supply voltage Vcc/2 during the pre-charge operation.
FIG. 1 illustrates a circuit diagram of a bit line pre-charge circuit of a conventional semiconductor memory device. This conventional bit line pre-charge circuit includes a plurality of pre-charge circuits 14-1, 14-2, 14-3 and 14-4 connected to a plurality of array bit line pairs ABL1/ABL1B, ABL2/ABL2B, ABL3/ABL3B and ABL4/ABL4B arranged at a left side of a plurality of data input/output line pairs IO1/IO1B, IO2/IO2B, IO3/IO3B and IO4/IO4B, a plurality of bit line isolation circuits 16-1, 16-2, 16-3 and 16-4, a plurality of PMOS bit line sense amplifiers 12-1, 12-2, 12-3 and 12-4, a plurality of pre-charge circuits 14-5, 14-6, 14-7 and 14-8 connected to the plurality of array bit line pairs ABL1/ABL1B, ABL2/BAL2B, ABL3/ABL3B and ABL4/ABL4B arranged at a right side of the plurality of data input/output line pairs IO1/IO1B, IO2/IO2B, IO3/IO3B and IO4/IO4B, a plurality of bit line isolation circuits 16-5, 16-6, 16-7 and 16-8, a plurality of NMOS bit line sense amplifiers 12-5, 12-6, 12-7 and 12-8, and a plurality of data input/output circuits 18-1, 18-2, 18-3 and 18-4 connected between a plurality of sense bit line pairs SBL1/SBL1B, SLB2/SBL2B, SBL3/SBL3B and SBL4/SBL4B and the plurality of data input/output line pairs IO1/IO1B, IO2/IO2B, IO3/IO3B and IO4/IO4B, respectively.
In FIG. 1, reference numerals 10-(i), 10-(i+1) and 10-(i+2) denote memory cell array blocks, and reference numerals MC1, MC2, MC3 and MC4 denote memory cells.
Operation of the pre-charge circuit of FIG. 1 will now be described.
The pre-charge circuits 14-1, 14-2, 14-3, 14-4, 14-5, 14-6, 14-7 and 14-8 each include three NMOS transistors. For example, the pre-charge circuit 14-1 includes the NMOS transistors N14, N15 and N16. The pre-charge circuits 14-2, 14-3, 14-4, 14-5, 14-6, 14-7 and 14-8 include NMOS transistors (N24, N25 and N26), . . . , (N31, N32 and N33) and (N41, N42 and N43), respectively.
The pre-charge circuits 14-1, 14-2, 14-3, 14-4, 14-5, 14-6, 14-7 and 14-8 pre-charge the array bit line pairs ABL1/ABL1B, ABL2/ABL2B, ABL3/ABL3B and ABL4/ABL4B, respectively, in response to respective pre-charge control signals PRE(i), PRE(i+1), Pre(i+2), . . . .
The bit line isolation circuits 16-1, 16-2, 16-3, 16-4, 16-5, 16-6, 16-7 and 16-8, each include two NMOS transistors N1 and N2 and isolate the array bit line pairs ABL1/ABL1B, ABL2/ABL2B, ABL3/ABL3B and ABL4/ABL4B from the sense bit line pairs SBL1/SBL1B, SBL2/SBL2B, SBL3/SBL3B and SBL4/SBL4B, respectively, in response to respective isolation control signals ISO(i), ISO(i+1), ISO(i+2), . . . .
The data input/output circuits 18-1, 18-2, 18-3 and 18-4, each include two NMOS transistors N3 and N4 and transfer data between the respective sense bit line pairs SBL1/SBL1B, SBL2/SBL2B, SBL3/SBL3B and SBL4/SBL4B and the respective data input/output line pairs IO1/IO1B, IO2/IO2B, IO3/IO3B and IO4/IO4B in response to a column selection signal CSL1.
When a short circuit occurs between a word line WLj and an array bit line ABL1, the bit line pre-charge circuit operates in a manner described below.
During the pre-charge operation, if the isolation control signals ISO(i), ISO(i+1), ISO(i+2), . . . having a power supply voltage Vcc, and the pre-charge control signals PRE (i), PRE(i+1), PRE(i+2), . . . having a power supply voltage Vcc, are generated internally, the NMOS transistors N1, N2, N11-N16, N21-N26, N31-N36 and N41-N46 are turned on. Thus, the array bit line pairs ABL1/ABL1B, ABL2/ABL2B, ABL3/ABL3B and ABL4/ABL4B and the sense bit line pairs SBL1/SBL1B, SBL2/SBL2B, SBL3/SBL3B and SBL4/SBL4B are pre-charged to a pre-charge voltage VBL. Further, since the word line WLj corresponding to the memory cell MC1 is shorted with the array bit line ABL1, current flows from the array bit line ABL1 to the word line WLj connected to a ground voltage. Accordingly, the pre-charge voltage level of the array bit line ABL1 is lowered since the word line WLj is connected to the ground voltage.
That is, current flow is generated through the NMOS transistor N12 because the NMOS transistor N12, which forms part of the pre-charge circuit 14-5, is turned on. Therefore, the pre-charge voltage VBL level of the array bit line ABL1 decreases. The decreased pre-charge voltage level of the array bit line ABL1 affects an adjacent array bit line ABL3 in a way that the pre-charge control signal PRE (i+1) having a logic “high” level is applied and then the NMOS transistor N32 in the pre-charge circuit 14-7 is turned, so that the pre-charge voltage level of the array bit line ABL3 decreases.
Accordingly, the NMOS bit line sense amplifiers 12-5 and 12-7 may not adequately or properly amplify a logic “low” level of data.
FIG. 2 illustrates a layout of a representative pre-charge circuit 14-5 of FIG. 1. Referring to FIGS. 1 and 2, reference numerals N11S, N12S and N13S denote source regions of the NMOS transistors N11, N12 and N13, respectively. Reference numerals N11D, N12D and N13D denote drain regions of the NMOS transistors N11, N12 and N13, respectively. Reference numerals N11G, NI2G and N13G denote gates of the NMOS transistors N11, N12 and N13, respectively. Reference characters l1, l2 and l3 designate channel lengths of the NMOS transistors N11, N12 and N13, respectively.
As shown in FIG. 2, an active area 30 of the NMOS transistors N11, N12 and N13 is formed in a semiconductor substrate (not shown) and has a rectangular shape. A gate body 32 having a “T” shape is formed on the active area 30 and forms gates for the NMOS transistors N11, N12 and N13. A leftward extending portion N11G of the gate body 32 forms a gate of the NMOS transistor N11, an upward extending portion N12G of the gate body 32 forms a gate of the NMOS transistor N12 and a downward extending portion N13G of the gate body 32 forms a gate of the NMOS transistor N13. Thus, the gates N11G, N12G and N13G of the NMOS transistors N11, N12 and N13 are formed in a single body 32. The source and drain regions N11S and N11D of the NMOS transistor N11 are formed at both sides of the gate N11G in the active area 30. The source and drain regions N12S and N12D of the NMOS transistor N12 are formed at both sides of the gate N12G in the active area 30. The source and drain regions N13S and N13D of the NMOS transistor N13 are formed at both sides of the gate N13G in the active area 30. Thus, a left and upper portion of the active area 30 forms a common source, N11S, N12S, for the NMOS transistors N11 and N12, and a left and lower portion of the active area 30 forms the drain N11D for the NMOS transistor N11 and the source N13S for the NMOS transistor N13. Further, a right portion of the active area 30 forms a common drain N12D and N13D for the NMOS transistors N12 and N13.
As shown in FIG. 2, the channel lengths l2 and l3 of the NMOS transistors N12 and N13 are short in comparison with the respective channel widths, so that resistances of the transistors N12 and N13 are small.
Layouts of the other pre-charge circuits of FIG. 1 are similar to that shown in FIG. 2.
Accordingly, in the conventional bit line pre-charge circuit, there is a problem in that the pre-charge voltage level of the array bit line ABL1 having a short circuit and the pre-charge voltage level of the adjacent array bit line ABL3 decrease when the short circuit is formed between the word line WLj and the array bit line ABL1. Thus, current flows from the pre-charge voltage VBL generation line to the bit line pre-charge circuits 14-5 and 14-7 through the NMOS transistors N12 and N32, each forming part of the pre-charge circuits 14-5 and 14-7, respectively, thereby causing a voltage drop in the pre-charge voltage generation line. Further, such a current flow continues during a standby operation of the semiconductor memory device, so that standby current consumption increases.
A short circuit may occur between a word line and a bit line pair due to process variations in manufacturing a semiconductor memory device. When such a short circuit occurs, the semiconductor memory device is usually repaired by replacing normal memory cells connected to the shorted word line with redundant memory cells.
In the repaired semiconductor memory device, when a pair of bit lines associated with the redundant memory cells is pre-charged to the pre-charge voltage, the pair of shorted bit lines associated with the normal memory cells is simultaneously pre-charged. Further, since a current path is formed between the shorted word line and the pair of shorted bit lines associated with the normal memory cells, the pre-charge voltage level of the pair of bit lines decreases. The decreased voltage level of the pair of bit lines affects a pre-charge circuit connected to another pair of bit lines, thereby degrading overall operation characteristics and reliability of the semiconductor memory device by lowering the pre-charge voltage level applied to the other pair of bit lines.
Further, the conventional bit line pre-charge circuit is designed in a way that transistors forming the pre-charge circuit have small resistances. Therefore, when the pre-charge voltage level of the shorted bit lines is decreased, a voltage level of a pre-charge voltage generation line is easily reduced and standby current consumption increases.
USPTO Backgrounds
USPTO Backgrounds