Semiconductor chips are integrated to more complicated functionalities and scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. The importance of wafer bonding techniques has been realized in the development of multi-layered micro/nano electromechanical systems (MEMS/NEMS) and three-dimensional integrated circuits (3D ICs) integration aiming at creating more compact and complex systems with improved functionality. This enables semiconductor devices to be fabricated separately and then bonded together, which provides more freedom in design and allows more advanced semiconductor systems to be fabricated.
But as feature sizes of the line widths approach a lower limit and the shrinkage of electromechanical systems into the nanometer range, the lack of effective techniques for achieving bonding alignment has become a critical stumbling block. There is a need for more accurate wafer deformation adjustment and bonding alignment to achieve higher device integration.
USPTO Backgrounds
USPTO Backgrounds