The present invention relates to a semiconductor device having a multilevel interconnection structure.
Interconnect layers in a semiconductor device having a multilevel interconnection structure are generally formed by using a method (a damascene process) in which a trench formed in an interlayer insulating film for each interconnect layer is filled with a metal film. The metal film deposited over the entire surface of the semiconductor substrate is subjected, for example, to a chemical mechanical polishing (CMP) process for removal of unnecessary part thereof, such that the metal film is left only in the trench. In this polishing process, in an area where the wiring pattern formed in the interlayer insulating film is sparse, the film thickness of the wiring pattern becomes smaller as compared with an area in which the wiring pattern is dense, because the polishing speed varies. To prevent such film thickness variation, a method is adopted in which a pseudo wiring pattern is provided as a dummy pattern in the area where the wiring pattern is sparse. The dummy wiring pattern thus provided prevents pattern dishing occurring in the CMP process.
For example, Japanese Laid-Open Publication No. 2004-235357 describes semiconductor devices in which a uniform dummy pattern is provided in a scribe region and in circuit regions on the semiconductor substrate for prevention of dishing in CMP process.
FIG. 10(a) shows the planar structure of a scribe region, a region which is cut when a semiconductor wafer having conventional semiconductor devices is divided into chips. FIG. 10(b) shows the structure in cross section taken along the line Xb-Xb in FIG. 10(a).
As shown in FIGS. 10(a) and 10(b), a plurality of circuit regions 2, in which function elements (not shown) are formed, are provided spaced from each other on the principal surface of a semiconductor substrate 1, and seal rings 3 made of conductive material are formed to surround the circuit regions 2. And a scribe region 4, a region which is cut to obtain the individual circuit regions 2, is formed between the circuit regions 2.
On the principal surface of the semiconductor substrate 1, first interlayer insulating films 11 and second interlayer insulating films 12 are stacked alternately. In the circuit regions 2, interconnects (not shown) made of conductive material are formed in the first interlayer insulating films 11, while vias (not shown) made of conductive material are formed in the second interlayer insulating films 12. On the other hand, in the scribe region 4, a dummy pattern 107, which is a uniformly spaced isolated pattern (an island-shaped pattern) made of conductive material, is formed in the first interlayer insulating films 11. In this way, the dummy pattern 107 is provided at uniform intervals in the scribe region 4 on the semiconductor substrate 1 so as to prevent dishing in CMP process.
However, when the scribe region 4 of the conventional semiconductor devices is cut by a dicing blade, the dicing blade cuts the conductive material of the dummy pattern 107. The cutting part of the dicing blade thus becomes clogged with the conductive material to cause the cutting ability of the dicing blade to degrade, leading to a problem in that chipping is likely to occur in the resultant semiconductor chips.
Nevertheless, if the dummy pattern 107 is not provided in the scribe region 4, the aforesaid problem, i.e., the occurrence of dishing in the CMP process, arises.
USPTO Backgrounds
USPTO Backgrounds