This invention relates generally to lithography, and more particularly relates to techniques for nanometer-scale lithography for microelectronic applications.
Many advanced microelectronic applications and much research are directed to nanotechnology and nano-scale systems. The increasing interest in the field of nanotechnology has highlighted a need for improved microelectronic material patterning capabilities at the nanometer length scale. Conventional lithographic techniques do not in general provide methods that are adequate for reliably producing sub-10 nm length-scale features; conventional optical projection lithography cannot print feature sizes less than about 60 nm, and electron beam lithography is generally highly complicated at feature sizes less than about 20 nm. Even with advances in these conventional lithographic techniques, the cost of newly developed lithographic tools is often prohibitive for research as well as commercial applications.
Nanoimprint lithography has recently emerged to address nanometer-scale lithographic requirements for microelectronic materials and semiconductor applications. In general, nanoimprint lithography employs a template or mold to stamp a pattern into a microelectronic material layer, e.g., a polymer layer, that is provided on a substrate. Conventionally, the layer is maintained in a rubbery state as the template is impressed into the layer, and then before removing the template from the layer, the layer is solidified to impose the template pattern in the layer. After removing the template, etching techniques or other processing can be carried out to transfer the pattern imposed in the layer to the underlying substrate or layers provided on the substrate.
Typically, a template to be employed for nanoimprint lithography is fabricated by, e.g., electron beam lithography. Specifically, a customized nanoimprint template is fabricated with electron beam processing to define all of the geometric features of a prespecified pattern to be transferred to, e.g., a substrate or material layer on the substrate. The thusly formed template can then be employed in a nanoimprint lithography process with the substrate, as described above, without the use of conventional lithographic techniques to pattern the substrate. Once the template is made it can be stamped many times. This process is referred to as “amplification”. But the requirement for nanometer-scale lithographic patterning of a custom nanoimprint template imposes the same challenges in difficulty, time, and expense that are imposed by electron beam lithographic patterning of a substrate itself. Nanoimprint lithography thereby shifts the difficulty of nano-scale lithography from patterning of a substrate to patterning of a nanotemplate mask. As a result, the ability of nanoimprint lithography to successfully extend beyond conventional lithography to the nanometer regime has heretofore been limited.
USPTO Backgrounds
USPTO Backgrounds