1. Field of the Invention
The present invention relates to the fabrication and structure for integrated circuits and more particularly to the fabrication of a MOSFET polysilicon self-aligned gate structure including a silicide forming metal layer between two polysilicon layers.
2. Description of the Prior Art
In integrated circuit fabrication, particularly in the fabrication process for self-aligned gates, polysilicon is used in the prior art for the gate element because the gate element is subjected to high temperatures during the diffusion step in producing the source and drain electrodes and polysilicon can withstand high temperatures similar to refractory metals. Also, in the self-aligned gate process a reoxidation step is performed to provide an oxide over the gate to separate the gate from the metal lines which are later disposed on the top of the structure and the oxide is grown better on polysilicon than on a refractory metal. A prior art structure of this type using polysilicon gate material is shown in FIG. 1 of the drawing.
A disadvantage of the polysilicon gate relative to a refractory metal gate is that it is desirable in many applications to connect the gate to the top layer of metal lines to provide a two-dimensional degree of freedom for the distribution of signals. When polysilicon is used for the gate material there is a mismatch between sheet resistance (ohms per squre cm.) of the metal and the polysilicon which causes inefficiencies such as reduced circuit speed. This disadvantage has been recognized in the prior art and attmepts have been made to avoid the resistivity mismatch. In the IBM Technical Disclosure Bulletin, Vol. 17, No. 6, November 1974, a publication entitled "Reducing the Sheet Resistance of Polysilicon Lines In Integrated Circuits" by V. L. Rideout, is directed to the use of polysilicon lines in multilayer integrated circuits because of the polysilicon's high temperature stability and the fact that silicon dioxide can be deposited or grown on it. The publication teaches that the resistance of the polysilicon lines can be decreased by forming a high-conductivity silicide layer on the exposed surface of the line. That is, the silicide is formed where the metal and the polysilicon meet. More particularly, the polysilicon lines are formed on a silicon dioxide layer over a substrate, a metal such as hafnium is deposited over the entire structure, hafnium silicide is formed over the polysilicon lines but the hafnium remains unreacted on the silicon dioxide regions and is etched away. Then an insulating layer of silicon dioxide is deposited over the structure and an aluminum metalization layer is formed over the silicon dioxide.
The present invention is distinct from the prior art in that a gate structure is formed in the self-aligned gate process wherein a first layer of polysilicon is formed, a silicide forming metal layer is then formed over the first polysilicon layer, and a second polysilicon layer is formed over the silicide forming metal layer. After masking, and during the subsequent reoxidation process, the metal layer reacts at two surfaces with the polysilicon layers and a silicide region is formed. The silicide region is available for a matched connection to the later formed upper metal layer, however the gate structure has a temperature stability property and an upper polysilicon region which provides a good oxide growth during the reoxidation process.
USPTO Backgrounds
USPTO Backgrounds