1. Field of the Invention
The present invention relates generally to integrated circuit chip package technology and, more particularly, to a semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package for enhancing heat dissipation from the die, and to allow for the stacking of one or more additional semiconductor packages upon the package while still maintaining an overall profile of reduced thickness in the resultant stack.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die attach pad or die pad of the leadframe also remains exposed within the package body. In other semiconductor packages, the metal leadframe is substituted with a laminate substrate to which the semiconductor die is mounted and which includes pads or terminals for mimicking the functionality of the leads and establishing electrical communication with another device.
As indicated above, both the semiconductor die and the bond wires used to electrically connect the semiconductor die to the leadframe or substrate of the semiconductor package are covered by the package body thereof. Typically, the encapsulant material used to form the package body is molded such that the completed package body is substantially thicker than the roof height of the conductive wires. The package body is also molded to be relatively thick at the central area of the top surface of the semiconductor die. Typically, the pads or terminals of the semiconductor die to which the conductive wires are electrically connected are located along the peripheral edge of the semiconductor die, and not within the central area thereof. Due to the aforementioned manner in which the package body is typically formed, the thickness of the semiconductor package is increased as a whole. Moreover, as the thickness of the package body is increased, heat generated from the semiconductor die is predominantly discharged to ambient air through the leadframe or substrate, rather than through the package body. As a result, the entire heat release performance of the semiconductor package is typically poor. Further, because the encapsulant material used to form the package body is molded thick on the central area of the top surface of the semiconductor die, the quantity of the encapsulant included in the semiconductor package is increased, which in turn gives rise to an increase in the overall cost thereof.
Once the semiconductor dies have been produced and encapsulated in the semiconductor packages described above, they may be used in a wide variety of electronic devices. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically includes a printed circuit board on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor dies highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
Even though semiconductor packages have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a need to find a semiconductor package design to maximize the number of semiconductor packages that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor packages. One method to minimize space needed to accommodate the semiconductor packages is to stack the semiconductor packages on top of each other, or to stack individual semiconductor device or other devices within the package body of the semiconductor package.
With regard to stacked semiconductor packages, the term PoP (package on package) is often used to describe the arrangement wherein two semiconductor packages are vertically stacked and electrically interconnected through the use of solder balls. Within the PoP arrangement, it is possible to implement various structures, such as analogue plus digital memory, logic plus flash memory, application process plus combo memory, image processor plus memory, audio/graphic processor plus memory, etc. Accordingly, it is possible not only to make a logic device with high density, but also to obtain a memory with high capacity. However, because the individual semiconductor packages in a PoP arrangement each typically include a relatively thickly molded package body, a problem that arises is that the entire thickness of the PoP is increased. With such increase in the thickness of the PoP, it is difficult to miniaturize an electronic device in which such PoP is to be integrated. Moreover, since semiconductor packages are typically stacked in the same direction, if the thickness of the package body is excessive, the number and pitch of solder balls which can be formed on one semiconductor package to facilitate the electrical interconnection of the semiconductor packages within the PoP to each other is seriously limited. That is, assuming that an upper semiconductor package is stacked on a lower semiconductor package, the number and pitch of solder balls formed on the leadframe or substrate of the upper semiconductor package is limited by the package body formed on the lower semiconductor package. As a result, it is typically not possible to form solder balls at a given area of the upper semiconductor package corresponding to the package body of the lower semiconductor package. Therefore, the number and pitch of solder balls for electrically interconnecting the upper semiconductor package and the lower semiconductor package to each other is limited, thus rendering difficulties in designing PoP's.
The present invention addresses and overcomes these problems by providing a semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package for enhancing heat dissipation from the die, and to allow for the stacking of one or more additional semiconductor packages upon the package while still maintaining an overall profile of reduced thickness in the resultant stack. These, as well as other features and attributes of the present invention will be discussed in more detail below.
USPTO Backgrounds
USPTO Backgrounds