1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to data transfer busses.
2. Description of the Related Art
The PCI Local Bus Specification Rev. 2.2 and PCI to PCI Bridge Architecture Specification Rev. 1.1, both published by the PCI Special Interest Group, proscribe a PCI (Peripheral Component Interconnect) bus protocol for integrating network controllers, mass storage controllers, display controllers, multimedia device, communication device, and other devices into a system. PCI bus protocol, which includes specifications for electrical characteristics as well as the manner in which software interacts with PCI devices, provides for the integration of peripheral devices in a manner that is generally independent from the particular protocol employed by other system components such as a host bus, processor, or memory.
PCI protocol provides xe2x80x9chooksxe2x80x9d to enable computer programs to directly access and configure PCI devices. These hooks include configuration address space for accessing 256 8-bit configuration registers associated with each PCI device to allow computer programs to optionally detect each PCI device installed in a system, identify the vendor and device type, determine each PCI device""s system resource requirements, relocate each device within the system address space, interrupt binding, install, configure, boot without user intervention and for system address map construction. Configuration registers include a predefined header region and device dependent region; however, only the necessary and relevant registers in each region need be implemented. PCI-to-PCI bridges are PCI devices with configuration registers, which are accessible to a computer program to assign a range bus number to the PCI busses behind the PCI-to-PCI bridge.
Configuration space is accessed through configuration cycles initiated by a computer program executing on a host processor. PCI protocol anticipates that the routing of configuration cycles be accomplished through either one of two distinct mechanisms in which a host-to-PCI bridge translates a software command (in the form of a sequence of processor initiated host bus accesses to I/O space) into a single configuration cycle on the targeted PCI bus involving the assertion of a particular PCI bus signal that is received by the targeted PCI device to indicate to that device that it is the target for the current configuration cycle.
Detection and initialization of PCI devices in a system can be accomplished by device independent program by utilizing configuration space. A program may poll the configuration space allocated to each slot on PCI bus 0 to detect the presence of PCI devices and PCI-to-PCI bridges that reside on bus 0. The program may assign each detected PCI-to-PCI bridge a unique bus number by writing to particular configuration registers and then poll each slot on each assigned bus to detect the presence of PCI devices and PCI-to-PCI bridges. This process may be continued until each slot on each detected PCI bus is polled and all PCI devices are detected. For each PCI device found installed in the system, the device""s configuration registers may be read to determine its resource requirements. A system address map may be built to eliminate conflicts among the system and various PCI devices and system resources may be assigned to each PCI device by writing to the appropriate configuration registers in each PCI device. Additionally, a self-test may be invoked on those devices that support self-test and any other initialization, installation, and configuration may be accomplished for each PCI device with or without user intervention.
Disadvantages imposed by strict adherence to PCI protocol include limits on data transfer speed, data path width, latency, and bandwidth, which set an upper boundary for performance of PCI devices. Performance may also be restricted by delays inherent to host-to-PCI bridges as well as the bandwidth constraints inherent to multiple PCI devices residing on a shared PCI bus. The present trend is for increasingly higher performance processors, memory, and host busses in which efficiently coupled devices can achieve performance advantages such as lower latency, higher throughput, and increased overall system performance than can be achieved through coupling to an actual PCI bus.
Plug-and-Play(trademark) resource allocation programs, as required by PCI bridge specifications, typically expect the address space allocated to a particular PCI bus to include the address space allocated to any PCI bus behind that particular PCI bus. Accordingly, full compliance with PCI protocol increases the difficulty of locating PCI devices on the host processor side of a host-to-PCI bridge, where the PCI devicesxe2x80x94possibly for compatibility reasonsxe2x80x94require an address space that may be a subset of the address space allocated to a physical PCI bus.
USPTO Backgrounds
USPTO Backgrounds