Complementary metal-oxide-semiconductor (CMOS) technology is used in microprocessors, static random access memories, and other diverse types of digital logic integrated circuits and analog integrated circuits. Conventional device structures for a planar field effect transistor (FET) fabricated using CMOS technology include a semiconductor layer, a source and a drain defined in the semiconductor layer, a channel defined in the semiconductor layer between the source and drain, and a control gate electrode. The material constituting the gate electrode in such conventional planar device structures contains polycrystalline silicon (polysilicon) or a metal applied by an additive process that involves blanket deposition of the material and patterning with a conventional lithography and etching process. When a control voltage exceeding a characteristic threshold voltage is applied to the control gate electrode, an inversion or depletion layer is formed in the channel by the resultant electric field and carrier flow occurs in the depletion layer between the source and drain (i.e., the device output current).
Non-volatile random access memory (NVRAM) refers generally any type of random access memory that retains the stored binary data even when not powered. A conventional device structure used as a memory cell in a NVRAM modifies the FET to add an electrically isolated (floating) gate electrode that affects conduction between the source and drain. In the vertical stack, a tunnel dielectric layer is interposed between the floating gate electrode and the channel. The control gate electrode, which has an overlying relationship in the vertical stack with the floating gate electrode, is separated from the floating gate electrode by an intergate dielectric layer. In such memory cells, binary data is represented by charge stored on the floating gate electrode. To provide one binary state, the floating gate electrode is charged during a write operation in which charge carriers tunnel or are injected from the biased control gate electrode through the tunnel dielectric layer to the floating gate electrode. Once the floating gate electrode has been charged, because the floating gate electrode is electrically isolated in the circuit, that charge remains intact without the requirement of being refreshed. To provide the other binary state, the charge stored by the floating gate electrode can be removed by reversing the bias on the control gate electrode, which drains charge carriers from the floating gate electrode. The memory cell is read by sensing the current flowing in the channel when the source and drain are properly biased, which is influenced by the charge stored by the floating gate electrode.
Improved device structures and fabrication methods are needed for a NVRAM that permit the use of high operating voltages for the constituent memory cells and that simplify their fabrication using CMOS technology.
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