The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to memory circuitry.
One obstacle to the advancement of silicon neural networks has been the difficulty in storing analog weight values on-chip. Prior approaches have used capacitive storage with clocked refresh, or multi-bit digital storage. Both of these approaches, however, pay a substantial penalty at least in terms of memory cell size, complexity, resolution and power consumption.
Some conventional memory cells are based on a floating gate metal-oxide-semiconductor (MOS) transistor structure which includes a control gate, an erase gate and an injection gate, each gate being distinct and separated laterally from one another. This memory cell structure consumes a substantial amount of area, resulting in reduced storage density, particularly when used in a memory array application.
USPTO Backgrounds
USPTO Backgrounds