1. Field of the Invention
The present invention relates to a pipeline AD/converter.
2. Description of the Related Art
In order to convert an analog voltage into a digital signal, a pipeline A/D converter is employed. FIGS. 1A through 1C are block diagrams showing a configuration of a typical pipeline A/D converter and a graph showing its input/output characteristics. An A/D converter 1100 includes multiple (n stages of) unit converter circuits UC1 through UCn connected to one another in a cascade manner.
The unit converter circuits UC1 through UCn sequentially execute A/D conversion in units of m bits from the most significant bit MSB to the least significant bit LSB. FIG. 1B shows a configuration of a unit converter circuit UC. Each unit converter circuit UC includes an operational amplifier OA1, a switch circuit SW, and a sub-A/D converter SADC, and is configured to alternately and repeatedly switch its state between a sampling state φ0 and a differential amplification state φ1 in a time sharing manner in synchronization with a clock signal. When a given stage of such a unit converter circuit UC is in the sampling state φ0, the adjoining stage of such a unit converter circuit is in the differential amplification state φ1.
An input voltage Vin is input to an input terminal Pi of each stage, from the immediately upstream stage. The input voltage is configured in a range between −Vref and +Vref. In the sampling stage φ0, the sub-A/D converter SADC is configured to compare the input voltage Vin with multiple reference voltages, and to generate comparison data D1 which represents the comparison result k. With such an example, the comparison data D1 has a 6-valued, i.e., approximately 2.5-bit, redundant data structure. Thus, the input voltage Vin is sampled (quantized) as follows.When −Vref<Vin<−⅝×Vref, k=−3.When −⅝×Vref<Vin<−⅜×Vref, k=−2.When −⅜×Vref<Vin<−⅛×Vref, k=−1.When −⅛×Vref<Vin<+⅛×Vref, k=0.When +⅛×Vref<Vin<+⅜×Vref, k=1.When +⅜×Vref<Vin<+⅝×Vref, k=2.When +⅝×Vref<Vin<+Vref k=3.
Furthermore, in the sampling state φ0, a switch S1 is turned on, and a switch S2 is switched to the input terminal Pi side. Moreover, the switch circuit SW selects the input voltage Vin, and applies the input voltage Vin thus selected to one terminal of each of input capacitors CS1 through CS3. As a result, a feedback capacitor Cf and the input capacitors CS1 through CS3 are each charged by the same input voltage Vin.
The next time the phase of the clock signal is switched, the state is switched to the differential amplification state φ1 in which the switch S1 is turned off, and the switch S2 is switched to the output terminal Po side of the operational amplifier OA. Furthermore, the sub-A/D converter SADC outputs the comparison result to the switch circuit SW. The switch circuit SW is configured to select one from among a set of reference voltages +Vref, −Vref, and GND, according to the comparison result, and to apply the reference voltage thus selected to one terminal of each of the input capacitors CS1 through CS3. As described above, the converted value k that represents the comparison result is switchable to any one of seven values in a range between −3 and +3. When k is positive, the switch circuit SW applies the reference voltage +Vref to each of k input capacitors CS, and applies the ground voltage GND to each of the other input capacitors CS. Conversely, when k is negative, the switch circuit SW applies the reference voltage −Vref to each of (−k) input capacitors CS, and applies the ground voltage GND to the other input capacitors. When k=0, the switch circuit SW applies the ground voltage GND to all the input capacitors C31 through CS3.
Assuming that all the capacitors Cf and CS1 through CS3 each have the same capacitance C0, the charge Q held by the inverting input terminal (−) of the operational amplifier OA is represented by the following Expression.Q=−4C0·Vin  (1)
With the electric potential of the inverting input terminal (−) of the operational amplifier OA as vi, with the output voltage thereof as vo, and with the gain thereof as G, the following Expression holds true.(vi−Vref)×k×C0+(vi−vo)C0=Q=−4C0·Vin  (2a)Vo=−G·vi  (2b)
Thus, in the differential amplification state φ1, the output voltage Vout (=vo) of each unit converter circuit UC is represented by the following Expression (3).Vout=4(Vin−k/4×Vref)/{1+(k+1)/G}  (3)
Now, assuming that G is infinite, the following Expression (3′) that represents the input/output characteristics of each unit converter circuit UC is derived.Vout=4·(Vin−k×Vref/4)  (3′)
FIG. 1C shows the input/output characteristics of the unit converter circuit UC, which is represented by Expression (3). Each open circle represents the corresponding reference voltage used by the sub-A/D converter SADC. In the drawing, each solid circle represents the corresponding offset voltage in the x-axis direction, which is represented by the second term of the right side of Expression (3′), i.e., (k×Vref). That is to say, the unit converter circuit UC is configured to amplify the difference between the input voltage Vin and the offset voltage with a gain of 4.
The output voltage Vout is supplied as the input voltage Vin to the next-stage unit converter circuit UC. As shown in FIG. 1A, the multiple unit converter circuits UC perform a pipeline operation in synchronization with the clock signal, thereby outputting, via the respective unit converter circuits UC, the data D1, D2, and so forth, each representing the corresponding converted value k. It should be noted that the final-stage unit converter circuit UC is not required to perform the differential amplification. Thus, the final stage unit converter circuit UC may be configured as a comparator array (sub-A/D converter) alone.
USPTO Backgrounds
USPTO Backgrounds