In digital and electronic systems there is often a requirement to generate an analogue waveform from a number of discrete digital samples. This is generally accomplished by using a sample generator of some description to produce a stream of discrete samples at fixed time intervals representing the desired waveform and to input the generated samples to a digital-to-analogue converter (DAC), generally referred to as Direct Digital Synthesis (DDS).
However, certain waveforms are more difficult to produce using this scheme than others. For example, it is relatively difficult to produce an accurate analogue square wave signal from a sampled system because a simple square wave requires an infinite bandwidth to be represented. If the period of the square wave required is not an integer number of samples, the sampled system must approximate the square wave by placing output edges of the waveform on the next available sample. This means that the output edge can be up to one sample time late, the net effect being that the output edge will move back and forth over one sample time. The movement of the output edge is referred to as edge jitter. Such edge jitter is usually not acceptable.
One possible solution to this problem is to use the sample generator to generate a sine wave, which when anti-alias filtered can provide accurate zero crossings. A comparator is then used to create the square wave, with the zero crossings causing an output edge to be generated. However, additional circuitry is required to provide the comparator and necessary two reference voltage generators in addition to control and calibration circuitry. This increases the complexity and expense of the required circuitry. Furthermore, in certain electronic applications the additional circuitry required cannot be physically fitted within the available space, whether this is in terms of discrete components or integrated circuit silicon wafer construction.
Another solution is to vary the frequency of the sample clock so that it is an exact multiple of the edge repetition rate. Varying the sample clock frequency is often not an option when the same clock is used to generate multiple independent sources, as is frequently the case. Another solution is to use a sample clock frequency much greater than the edge repetition rate, for instance 1000 times greater. Again, this possible solution has its own shortcomings. Using a very high sample clock frequency is generally too expensive.
USPTO Backgrounds
USPTO Backgrounds