With an apparatus for converting an analog video signal to a digital video signal and then digitally demodulating it into a baseband signal for digital processing in compliance with the digital video signal processing standards (e.g., ITU-R601), and modulating it back into a video signal, it is a common practice that a sampling clock signal of 13.5 MHz is created in synchronization with a horizontal sync signal, and in accordance with the resulting sampling clock signal, luminance and color signals are demodulated and modulated. More specifically, a horizontal sync signal is extracted from a digital video signal to detect a phase difference between the extracted horizontal sync signal and a reference horizontal sync signal per line, so that a sampling clock signal is produced according to the phase difference detected. This sampling clock generation scheme is called a "Line Locked" PLL. Because both horizontal and vertical sync signals can be extracted accurately by using this sampling clock signal to sample the analog video signal for digitization, the luminance signal can be demodulated and modulated without losing a temporal relationship between the horizontal and vertical sync signals and the luminance signal.
Besides the line locked PLL system, a burst locked PLL system is also known which produces a chrominance subcarrier signal in synchronization with a color burst signal contained in a digital video signal. With this burst locked PLL system, a color burst signal is extracted from a digital video signal to detect a phase error between the extracted color burst signal and a reference color burst signal, and, according to the resulting phase error, an oscillation signal having four times the frequency of the chrominance subcarrier signal is generated and divided by four to generate a chrominance subcarrier signal. If digital video processing is performed using the chrominance subcarrier signal obtained in the burst locked PLL system, the color signal can be demodulated and modulated stably.
If the sampling clock signal of 13.5 MHz is produced by the line locked PLL system, the luminance signal is locked to the horizontal sync signal, so that a temporal relationship between the sampled horizontal and vertical sync signals and the luminance signal is maintained normal. However, because each video apparatus, such as VCRs (video cassette recorders), has variations and errors in its sync signal, if the sampling clock signal based on that sync signal is used to process the color signal, the color signal could not be processed appropriately as the sampling clock signal varies, leading to color degradation, for example, during color demodulation. Furthermore, when the composite video signal is Y/C separated by a Y/C separation circuit, such as a comb filter, into a luminance and a color signal, degradation in separation will also result.
On the other hand, if a sampling clock signal of 13.5 MHz is produced by the burst locked PLL system, there is a problem that the clock generation circuit becomes complicated.
Accordingly, it is an object of the present invention to provide a clock generation circuit that is simple in structure and permit stable operation in both luminance and color signal processing subsystems.
USPTO Backgrounds
USPTO Backgrounds