When data is transferred between LSIs (Large Scale Integrations), a phase difference sometimes occurs between the LSI at a transmission side and the LSI at a reception side conventionally even when the frequencies of the clocks are the same.
When a difference occurs to the phases, timing for capturing data with the clock of the LSI at the reception side and a change of the data may take place at the same time. In such a case, metastable occurs, in which the data is brought into an unstable state. Therefore, the LSI at the reception side synchronizes the phase of the received data by using a synchronization circuit having FFs (Flip Flops) of multiple stages.
A synchronization circuit according to a prior art will be described with use of FIGS. 25 and 26. FIG. 25 is a diagram depicting one example of the synchronization circuit according to the prior art. As depicted in FIG. 25, the synchronization circuit according to the prior art has FFs of four stages, for example.
An FF of a first stage takes in received data and a received clock, and outputs the data to an FF of a second stage. Subsequently, the FF of the second stage takes in the data outputted by the FF of the first stage and an internal clock, and outputs the data to an FF of a third stage.
Further, the FF of the third stage takes in the data outputted by the FF of the second stage and the internal clock, and outputs the data to an FF of a fourth stage. Likewise, the FF of the fourth stage takes in the data outputted by the FF of the third stage and the internal clock, and outputs the synchronized data to a combinational circuit, a sequential circuit and the like.
When a phase difference exists between the received clock and the internal clock, the synchronization circuit synchronizes the phase as depicted in FIG. 26. FIG. 26 is a diagram depicting one example of a time chart in the case in which a phase difference exists between the received clock and the internal clock.
As depicted in FIG. 26, when only a small phase difference exists between the time of a change of the data outputted by the FF of the first stage and the time of the rising edge of the internal clock, the FF of the second stage cannot secure a sufficient SETUP time and HOLD time for stably outputting the data. As a result, the FF of the second stage outputs unstable data. Subsequently, the FF of the third stage takes in the unstable data outputted by the FF of the second stage and the internal clock, and outputs the unstable data as stable date. In this manner, the synchronization circuit according to the prior art generally takes stable data in the LSI by fixedly preparing the FFs of multiple stages.
Further, in a TDMA (Time Division Multiple Access) method, an art is also known, which captures the data with the clocks the phases of which are obtained by shifting the phase of the received clock to multiple divided degrees, and selects the clock which captures the data in the middle where the data does not change.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 8-125643
However, the aforementioned prior art has the problem of being unable to synchronize the phase with the reception side clock in a short time.
More specifically, in the prior art, the clock is synchronized each time data is transferred from the LSI at the transmission side to the LSI at the reception side. Synchronization of the clock requires time corresponding to the number of FFs which the synchronization circuit has. As a result, the latency is worsened in the LSI at the reception side. Further, the synchronization circuit in which FFs are serially provided in multiple stages is not suitable for reception of the data which toggles.
Further, in the TDMA method, the phase of the data is not synchronized with the phase of the internal clock at the reception side, but the clock which can capture the received data at stable timing is selected. Therefore, synchronization of the data cannot be performed with the reception side clock.
USPTO Backgrounds
USPTO Backgrounds