1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a process for fabricating a stacked etch, virtual ground EPROM cell without the planarization problems commonly encountered in fabricating such cells.
2. Discussion of the Prior Art
An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from the EPROM without loss of data. That is, upon reapplying power, the originally stored binary data is retained.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. Reprogramming is accomplished by first exposing the EPROM to an ultra-violet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written to the EPROM by deactivating the chip select line in order to switch the EPROM data outputs to inputs. The EPROM address inputs are then set to a starting value, the desire data is connected to the data inputs and the data is written into the data storage register identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each data storage register in the EPROM array.
In an EPROM read operation, the binary data stored in the data storage register identified at the address inputs is connected to the chip's data output buffers. If the EPROM chip select signal is activated, then the binary data from the selected storage register is provided to the databus.
An electrically erasable programmable read only memory (EEPROM) is a variation of the EPROM design wherein binary data is read, written and erased electrically. A single operation erases the selected data storage register. In the case of a so-called "flash" EPROM, all data storage registers in the memory array are electrically erased in a single operation.
FIG. 1A shows a conventional EPROM cell 10. The EPROM cell 10 includes a buried N+ source region 12 and a buried N+ drain region 14 formed in a P-type silicon substrate 16 and separated by a substrate channel region 18. Overlying the channel region 18 is a layer of insulating material 20, typically silicon dioxide. A conductive floating gate 22 is formed on the insulating material 20. Typically, floating gate 22 is formed of polycrystalline silicon (poly 1). Overlying floating gate 22 is a second layer 24 of insulating material, typically, a composite layer of oxide-nitride-oxide (ONO). A conductive control gate 26 is formed on the ONO layer 24. Typically, the control gate 26 is also formed of polycrystalline silicon (poly 2).
A plan view of this so-called "stacked gate" (or "stacked etch") EPROM cell 10 is shown in FIG. 1B. The structure of the standard "T-shaped" cell 10 shown in FIG. 1B derives its "stacked-gate" designation because of the self-aligned etching process which is utilized to form the vertically-aligned control gate 26 and floating gate 22 of the cell 10. That is the edges of the control gate 26 are used to complete the definition of the underlying floating gate 22.
The processing sequence for forming the polysilicon floating gate 22 and the polysilicon control gate line 26 of the stacked gate cell 10 is as follows. Referring to FIG. 1A, first, a layer of polysilicon (poly 1) is formed on the silicon dioxide layer 20. The poly 1 layer is then masked and etched to form the floating gate 22. Next, an ONO layer 24 is grown over the entire structure. This is followed by growth of a second polysilicon layer (poly 2) from which the control gate line 26 will be formed. The poly 2 layer is then masked and etched. The resulting poly 2 control gate line 26 is then used as a self-aligned mask to etch the interpoly ONO 24 and the underlying floating gate 22 to define the final structure of the stacked gate cell 10 shown in FIG. 1A.
Traditionally, reductions in EPROM memory array density have been accomplished by reducing the dimensions of the cell features produced by the photolithographic and etching procedures utilized in fabricating standard T-shaped EPROM cells. The shrinking cell geometries resulting from these process developments have led to corresponding requirements for new isolation schemes in order to accommodate the minimum cell pitch and to develop the sub-micron contacts which must be formed utilizing non-standard techniques.
For example, Hisamune et al, "A 3.6 nM.sup.2 Memory Cell Structure for 16MB EPROMs, IEDM 1989, page 583, disclose a process for minimizing EPROM cell pitch utilizing trench isolation of the bit lines and tungsten plugs for bit line contacts. Bergemont et al, "A High Performance CMOS Process for Submicron 16MB EPROM", IEDM 1989, page 591, also disclose techniques for reducing the size of the standard T-shaped EPROM cell.
One way to avoid the special processing requirements associated with the fabrication of high density T-shaped EPROM cell arrays is to use a different type of cell which does not require conventional LOCOS field oxide isolation and contacts in the array.
A three-dimensional schematic diagram of a portion of one such EPROM array is shown in FIG. 2. The FIG. 2 array utilizes planarized oxide over the buried N+ bit lines and bit line isolation to improve array density.
FIGS. 3A-3D show the fabrication process for the FIG. 2 array. Following formation of the poly 1 floating gates, an arsenic implant is utilized to define the buried N+ bit lines. A layer of oxide is then deposited (typically by LPCVD) and then photoresist is spun on. FIG. 3B shows the resulting structure prior to planarization. Next, as shown in FIG. 3C, the surface of the structure is etched back to planarize the oxide between the poly 1 lines. This is followed by formation and definition of an oxide-nitride-oxide (ONO) layer and an overlying second layer of control gate polysilicon (poly 2).
However, the EPROM cell array shown in FIG. 2 also suffers from process difficulties. For example, when etching the residual part of the stack, i.e. the oxides-nitride-oxide (ONO)/poly 1, that portion of the buried N+ bit line which is not covered by poly 1 must have a sufficient silicon dioxide thickness covering it to avoid digging into the bit line when etching the residual poly 1. Otherwise, the N+ bit line may be interrupted.
As stated above, the conventional solution to this bit line "digging" problem is to planarize the oxide between adjacent poly 1 lines. However, this creates three additional problems. First, the plasma etch-back planarization process is extremely complicated. Second, forming a good quality ONO layer over the poly 1 after the etch-back is difficult, since the surface of the poly 1 has been exposed to the plasma silicon dioxide etch-back process. Third, the polysilicon must be implanted at the same time as the buried N+ bit line arsenic implant, which can make it difficult to grow a good quality interpoly oxide and can also lead to problems of data retention reliability.
USPTO Backgrounds
USPTO Backgrounds