1. Field
This art is related to a method of verifying the operation of a circuit using circuit connection information about connection between logic circuits.
2. Description of the Related Art
When designing a semiconductor integrated circuit, a designer designs a circuit and performs logic synthesis in order to verify whether a problematic portion of the circuit operation is present. Recently, some highly advanced semiconductor integrated circuits have included asynchronous circuits that operate with different clocks in the transmission side and the reception side. In such asynchronous circuits, a phenomenon that is specific to asynchronous circuits occurs (e.g., a metastable state). Since this phenomenon may cause a fault, it is important to verify the asynchronous circuits in the design phase. As used herein, the term “metastable state” refers to a state in which an output level of a signal reception register becomes unstable in accordance with the reception timing of a signal reception register driven with a clock different from that of a signal transmission register.
FIG. 3 of Japanese Patent Application Laid-open No. 2000-11031 describes a method for extracting a cell for which timing verification is needed when designing a semiconductor integrated circuit. More specifically, when a clock of a signal transmission register is different from a clock of a signal reception register, the registers are extracted as cells for which timing verification is needed.
However, for example, in the existing technology described in Japanese Patent Application Laid-open No. 2000-11031, an effect of transmission and reception timing of a signal propagating in an asynchronous path on transmission and reception timing of a signal propagating in another asynchronous path may not be extracted. Accordingly, if an error is detected during circuit verification (e.g., timing verification), the designer manually needs to determine whether the cell itself is problematic, an asynchronous path between cells is problematic, or signal propagation timing between asynchronous paths is problematic.
USPTO Backgrounds
USPTO Backgrounds