Solid state image sensors are very commonly based charge coupled device (CCD) technology, and are generally classified into either interline transfer type or frame transfer type. The CCD image sensing device is typically an array of closely spaced gates composed of polycrystalline silicon (polysilicon). Polysilicon has been a material of choice due to the ease with which a reliable thin insulating layer may be produced to insulate the separate gates from one another. In operation of frame transfer type imagers, incident light must pass through the gate electrodes and be absorbed by the underlying silicon. Thus, it is desired that these gates be transparent to a broad spectrum of wavelengths of light, and in particular to be transparent to shorter wavelengths, for example, shorter than 450 nm wavelength. Polysilicon gates are not suitable for high transmission in this wavelength range. Hence, devices utilizing more transparent conducting materials, typically composed of conducting oxide materials such as indium-tin-oxide (ITO), have been proposed. For purposes of this disclosure, the term ITO is to be understood to include other conducting materials, as well.
In the prior art as taught by Losee, in U.S. Pat. No. 5,891,752, a method for constructing a CCD image sensor with all ITO gates is proposed. In that device, however, the ITO gates are subjected to chemical mechanical polishing (CMP) to achieve the required electrical isolation between adjacent gates. This CMP process can be non-uniform over widely spaced regions and, hence, devices so produced have some variation in ITO thickness from one area of the device to another. Due to the relatively high index of refraction of the ITO material, this thickness variation results in variation in the relative amount of light which reaches the silicon substrate, and hence, produces a spatial variation in the relative sensitivity of the device. For improved optical response, it is desirable to employ relatively thin ITO for the gates, for example, using thicknesses less than 100 nm. With decreasing ITO gate thickness, the variation in thickness caused by the CMP process causes stronger variation in the relative sensitivity of the device.
Another concern with the polished structure, particularly when thin ITO gates are desired, is due to fixed electrostatic charges which inevitably occur in overlying insulating layers of the device. Such fixed charge will cause small potential variations, usually as regions of increased electrostatic potential, immediately below the insulating gap between the CCD electrodes. This is illustrated in FIG. 1a. In this figure, electrostatic potential contours are indicated, and if seen that a potential well, or pocket, appears in the region beneath the electrode gap. The depth of this well depends on both the gate electrode separation and the placement and magnitude of the fixed insulator charge. Such a potential well can introduce charge transfer inefficiency, an undesirable property, in the operation of the CCD shift register.
From the foregoing it should be apparent that there remains a need in the art for a method of producing a more uniform gate thickness in frame transfer CCD images sensors, this is especially true when the gates are composed of ITO. It should also be apparent that there remains a problem of reducing the effect of fixed charges which may be present in overlaying insulating layers. Such fixed charges can result in undesirable potential wells or barriers in the underlying silicon substrate, which, in turn, can lead to charge transfer inefficiency. These and other problems within the prior art are addressed by the present invention.
USPTO Backgrounds
USPTO Backgrounds