1. Field of the Invention
The present invention relates to an improved sense amplifier.
2. Description of Related Art
Sense amplifiers are used to amplify output signals from semiconductor storage arrays, such as static random access memories (SRAMs), programmable read only memories (PROMs) and programmable logic devices (PLDs). Each of these storage arrays need to be "sensed" to read the data stored in the devices. This data is stored within semiconductor structures in the array which are generally capable of producing only very low level output signals which indicate the data. These output signals are binary, ones or zeros, and the difference between the two binary levels is very small. Accordingly, a sense amplifier is required to amplify the levels of these signals in order to further utilize them.
Most prior art sense amplifiers used in complementary MOS ("CMOS") technologies employ a CMOS clamp at the input to reduce input signal swings and, thus, the propagation delay of data through the sense amplifier. Reducing the delay through these sense amplifiers is important in order to minimize delays in accessing data stored in the device.
In the sense amplifier circuit of the present invention, the input signal appears at terminals IN and IN. The input signal can, for example, be the signal sensed from the bit line of a Programmable Logic Device (PLD) or Static Random Access Memory (SRAM). Generally, it is a small differential voltage, between about 100 mV to 200 mV.
FIG. 1a is a simplified representation of a dual differential amplifier commonly used in the prior art sense amplifier 20. As shown in FIG. 1a, differential amplifier 200 with differential inputs 205, 215 and single output 206 is controlled by transistor 207. Similarly, differential amplifier 210, which receives differential inputs 205, 215 to generate output-bar 216. The sense amplifier is turned on by an enable signal which drives the gates of transistors 207 and 217.
FIG. 1b is a schematic diagram of prior art sense amplifier 20. As shown in FIG. 1, a typical sense amplifier 30 comprises two differential amplifiers 31, 32. Input 307 and input-bar 317 are applied to the gates of the differential pair of transistors 303, 302, respectively in differential amplifier 31. Similarly input 307 and input-bar 317 apply to the gates of the differential pair of transistors 312, 313, respectively in differential amplifier 32. Tail device 304 in differential amplifier 31 is driven by the node connecting the gates of p-channel gate-coupled devices 300,301. Also, tail device 314 is driven by the node connecting the gates of p-channel gate-coupled devices 310, 311 in differential amplifier 32.
The prior art sense amplifiers have the following shortcomings. First, these sense amplifiers cannot accept input signals at the power supply voltage (e.g., V.sub.cc). Specifically, the input signals must be translated down from the power supply voltage to a lower voltage (e.g., 1 V below V.sub.cc) for the prior art circuits to work properly. Moreover, the gain of the pre-amplifier stage of these prior art circuits is high which increases the delay through the amplifier.
USPTO Backgrounds
USPTO Backgrounds