In the current systems-on-a-chip (SoC), the aging of the electronic components is anticipated during the design of the systems.
Usually, the aging is compensated by allocating an excess, or a compensation, of voltage to the power supply voltage, in order for the aged components to continue to operate in a satisfactory manner within a “worn” product. For example, an excess of 40 mV for a power supply of 150 mV is usually provided for the first uses of such a system-on-a-chip.
As a consequence, this compensation leads to an excessive energy consumption from the first use, which represents a handicap within the framework of applications in which the energy efficiency is primordial, for example in the case of a weak battery or with an objective of minimal energy dissipation.
Furthermore, these losses in performance may be even more serious when a system-on-a-chip of the same design is used for various mission profiles. A mission profile is a model of use corresponding to various stresses to which the system-on-a-chip must be subjected. By way of illustration, a system designed for industry will be subjected to a more intensive use than a system designed for motor vehicles, which itself will be subjected to a more intensive use than a system used by individuals.
The systems-on-a-chip usable for various mission profiles are consequently designed in order to withstand the model with the most severe stresses, and this represents a loss of competitiveness owing to conventional energy values (referred to Power Purchase Agreement (PPA)) that are poorly adhered to for mission profiles that are less demanding.
Thus, the optimization of the power supply in systems for managing the aging of electronic components represents a problem area in the compromise between performance characteristics and reliability, taking into account the limitations of the systems-on-a-chip comprising the components.
It would therefore be desirable to overcome this problematic feature by providing an adaptive compensation for the aging of systems-on-a-chip.
With regard to adaptive adjustment of the voltage/frequency of a system-on-a-chip, U.S. Pat. No. 8,154,335 (incorporated by reference) describes a system-on-a-chip in which a power supply voltage is reduced and/or a clock frequency is increased in order to recover conditions of use within acceptable margins, the margins being generated by a circuit for replicating a critical path. This teaching also describes an increase in the voltage and/or a decrease in the frequency for preventative purposes in the case of exceeding the acceptable margins for conditions of use.
However, the solution provided in the aforementioned U.S. Pat. No. 8,154,335 is adapted to occasional variations in the operation of the system-on-a-chip, and does not take into consideration the longer term problems of excess power supply and aging previously described.
There accordingly exists a need to estimate an operating profile of an integrated circuit of a system-on-a-chip taking into account the long-term aging of the system-on-a-chip.
USPTO Backgrounds
USPTO Backgrounds