In many of today's integrated circuits (IC's), serializer/deserializer (SerDes) circuits are implemented to enable the IC's to exchange information with each other and with other components at very high data rates. The SerDes circuits generally include a transmitter and a receiver. Typically, information is sent from a transmitter on one IC to a receiver on another IC through a series of analog pulses. Specifically, to send a digital bit of information, a transmitter determines whether the bit that it wants to send is a digital 1 or a digital 0. If the bit is a digital 1, the transmitter generates an analog signal (which may be made up of a single signal or a pair of differential signals) having a positive voltage. If the bit is a digital 0, the transmitter generates an analog signal having a negative voltage. After generating the analog signal, the transmitter sends the analog signal as a pulse having a certain duration to the receiver along a communications link. Upon receiving the analog signal, the receiver determines whether the analog signal has a positive voltage or a negative voltage. If the voltage is positive, the receiver determines that the analog signal represents a digital 1. If the voltage is negative, the receiver determines that the analog signal represents a digital 0. In this manner, the transmitter is able to provide digital information to the receiver using analog signals.
Ideally, the receiver receives analog pulses that closely resemble the analog pulses that were sent by the transmitter. Unfortunately, due to a pulse response effect that is experienced at high data rates, called intersymbol interference (ISI), this ideal cannot be achieved. Instead, neighboring pulses ‘smear’ into neighboring pulses, and it is often difficult for the receiver to determine whether the received analog signal represents a digital 1 or a digital 0.
To elaborate upon the concept of a pulse response, reference will be made to the sample pulse response shown in FIGS. 1A and 1B. FIG. 1A shows an example of what may be received by a receiver in response to a single positive-voltage pulse (representing a digital 1) sent by the transmitter. In the example shown in FIG. 1A, the pulse is sent by the transmitter in time interval t−4 and received by the receiver four time intervals later beginning with time interval t. Notice that even though the transmitter sent a pulse lasting only a single time interval, the receiver does not receive that pulse in just a single time interval. Instead, the receiver receives an analog signal that lasts for several time intervals. During time interval t, the received signal has a magnitude of h0. During the next time interval (interval t+1), the received signal magnitude drops to h1. During the next several time intervals, the received signal magnitude drops to h2, then to h3, then to h4, and so on. Thus, even though the transmitter sent a pulse lasting only one time interval, the receiver receives a signal that lasts for many time intervals.
Because of this pulse response effect, a pulse sent in one time interval has a tail that affects pulses sent in future time intervals. When pulses are sent in rapid succession, the tails of various pulses overlap and add together. Thus, the receiver rarely sees just the original pulse. Rather every pulse also arrives at the same time as the tails of various other pulses. Since each pulse is either positive or negative, and thus each tail either adds to or subtracts from the amplitude of an actual pulse, the received signals can vary greatly from the actual pulse height.
To illustrate, suppose that the transmitter sends another positive-voltage pulse in time interval t−3, and that this pulse is received by the receiver beginning in time interval t+1. During time interval t+1, the receiver would sense the h0 voltage of the pulse sent in time interval t−3. The receiver would also sense the h0 voltage of the pulse previously sent in time interval t−4. Suppose further that the transmitter sends another positive-voltage pulse in time interval t−2, and that this pulse is received by the receiver beginning in time interval t+2. During time interval t+2, the receiver would sense the h0 voltage of the pulse sent in time interval t−2. The receiver would also sense the h1 voltage of the pulse previously sent in time interval t−3. In addition, the receiver would sense the h2 voltage of the pulse previously sent in time interval t−4. Thus, the voltage sensed by the receiver at time interval x+2 is an accumulation of the effects of the pulses sent at time intervals t−4, t−3, and t−2 (and even pulses sent at time intervals before t−4). As this example shows, when the receiver senses a voltage during a time interval, it does not sense the effect of just one pulse but the accumulation of the effects of multiple pulses. This distortion may generally be referred to as “intersymbol interference” (ISI). Severe ISI may prevent receivers from distinguishing symbols (an electronic signal representing a digital bit) and consequently disrupt the integrity of received signals in a communications link.
FIG. 1A shows the pulse response for a single positive-voltage pulse. The pulse response for a single negative-voltage pulse (representing a digital 0) is shown in FIG. 1B. Notice that the pulse response of FIG. 1B is similar to the pulse response of FIG. 1A except that the voltages are negative instead of positive. Thus, as shown by FIGS. 1A and 1B, the effect that a pulse has on future pulses will depend on whether that pulse is a positive-voltage pulse (representing a digital 1) or a negative-voltage pulse (representing a digital 0). If a pulse is a positive-voltage pulse, it will add to the voltages of future pulses. Conversely, if the pulse is a negative-voltage pulse, it will subtract from the voltages of future pulses.
As can be seen from the above discussion, a pulse response can significantly affect the signals that are received by a receiver. Thus, it is highly desirable in many implementations to ascertain the pulse response effect that is experienced by a receiver. Armed with knowledge of the pulse response, it may be possible to compensate for its effects (e.g., via decision feedback equalization). It may also be possible to use the pulse response information to adjust the parameters of the transmitter and/or receiver and perhaps even other components to improve the overall performance of the transmission/reception process. These and other uses of the pulse response information are possible. A point to note is that a pulse response is a characterization of the link performance of the communications link to which a receiver is coupled. Because each receiver is coupled to a different communications link, each receiver may and most likely will experience a different pulse response effect. Thus, a pulse response is determined on a per receiver/communications link basis.
A pulse response for a particular receiver/communications link may be determined by sending a set of predetermined analog pulses (representing a predetermined bit pattern) from a transmitter to a receiver along that communications link, and capturing a waveform of the signals actually received by the receiver. Once the waveform is captured, it can be processed and compared with an ideal waveform to derive a pulse response for the receiver/communications link. The difficult part of this process, however, is capturing the waveform in a practical and feasible manner.
One possible approach to capturing the waveform is to implement sufficient sampling and storage components on each receiver to enable the receiver to capture an oversampled waveform for the signals received by the receiver. To illustrate how this may be done, suppose that a predetermined 128 bit pattern is sent by a transmitter to a receiver over 128 time intervals. Suppose further that it is desirable for the receiver to oversample the signals received by the receiver 48 times (i.e. take 48 samples of the incoming signals per time interval). To capture such a waveform, the receiver would need a sampling clock signal that is 48 times faster than the incoming data clock. During each time interval, the receiver would sample the analog signal received during that time interval 48 times. For each sample, the receiver would sense an analog signal and convert it into a corresponding x-bit (e.g. 4-bit) digital value. Each x-bit digital value would be stored in a register. At the end of the 128 time intervals, the receiver will have captured all of the sample values needed to form an oversampled waveform for the incoming signals.
A problem with this approach, however, is that it is quite resource intensive. In order to capture the entire oversampled waveform, the receiver would need 48×128 or 6,144 x-bit registers just to store all of the digital sample values. In addition, the receiver would need to have components for implementing the sampling and storage functions. These components and storage consume a significant amount of chip space. In a large scale IC (e.g. a microprocessor), which can comprise a very large number of receivers, chip space is precious, and in most implementations, it is not practical for each receiver to consume a large amount of chip space. Additionally, using excess chip space can have parasitic effects on the communications link (e.g., capacitive effects can act as a low pass filter). Because of these and other practical considerations, this approach to capturing an oversampled waveform cannot be feasibly implemented in most applications.
One technique for reducing the effect of ISI is to use an adaptive equalizer such as a decision feedback equalizer (DFE). A DFE may be operative to compensate for ISI by utilizing digital filtering techniques. For example, when a pulse response for a communication link is known, a DFE may include a plurality of taps (e.g., 2 taps, 5 taps, or the like) that are used to cancel the effects (e.g., reduce the effects from h1, h2, h3, etc.) of previously sent bits on a present bit. The taps or coefficients for a DFE may be generated using any number of adaptation processes, and may be implemented in any suitable manner.
The importance of accurate data reception motivates communication link designers to design systems that are able to tolerate ISI and other types of noise. One quality characteristic that may be used is referred to as voltage margin or simply “margin.” Voltage margin characterizes the range of voltage and timing values for which a given receiver will properly determine input signals. That is, the degree to which the voltage and time can vary without introducing error is termed the “margin” for the communications link.
USPTO Backgrounds
USPTO Backgrounds