1. Field of the Invention
The present invention relates to a silicon wafer grown by the Czochralski method and suitably used for a substrate of a semiconductor device, etc. and also to a method for producing the same.
2. Description of the Related Art
A silicon wafer used as a substrate of a semiconductor device is produced as follows: a wafer is cut out of a single crystal silicon ingot which is generally grown by the Czochralski method (hereinafter, called the “CZ method”) and subjected to the steps such as polishing. The CZ method is a method for growing a single crystal including the steps of: dipping a seed crystal in silicon melted in a quartz crucible and pulling the seed crystal. The crystal grown by this method usually includes crystal defects called grown-in defects.
FIG. 1 is a longitudinal sectional view of a pulled single crystal and also a diagram schematically showing one example of the relationship between defect distribution and V/G. V is the pulling rate of a single crystal silicon and G is the temperature gradient in the growth direction in the single crystal immediately after pulled. The above-mentioned temperature gradient G is considered to be generally constant due to a thermal characteristic of the hot zone structure of the CZ furnace, so that V/G can be controlled by adjusting the pulling rate V. The single crystal is grown while gradually lowering V/G. And the crystal is sectioned along the central axis thereof, Cu is deposited onto its section, and heat treatment is applied to the section. This drawing schematically shows the section, after above treatment, observed by X-ray topography (FIGS. 2 and 4 to be hereinafter described were also made by a similar method).
In FIG. 1, crystal originated particles (COPs) are an aggregate of vacancies (micro voids) as being devoid of atoms that make up of crystal lattices during single crystal growth, and a dislocation cluster is an aggregate of interstitial silicon excessively taken into interstices. If COPs existing in the vicinity of the wafer surface are taken into an oxide film during the thermal oxidation of the wafer surface, gate oxide integrity (GOI) characteristics of the semiconductor device are degraded. In addition, the dislocation cluster becomes causes of device characteristics defective. In other words, COPs and dislocation cluster exert an adverse influence on the device characteristics. Therefore, the research and development have been carried out for obtaining a silicon wafer free of these grown-in defects.
As shown in FIG. 1, when V/G is large (the pulling rate is fast), excessive vacancies exist and COPs are introduced into the single crystal, while when V/G is small (the pulling rate is slow), an excessive amount of interstitial silicon exist, the dislocation cluster is likely to be generated. In the growth of a single crystal silicon, since a faster pulling rate is typically employed to increase V/G for improving the productivity, etc., the wafer obtained from the pulled single crystal intrinsically contains COPs.
In order to remove such COPs introduced during growing the single crystal as described above, for example, Japanese Patent Application Publication No. 2006-344823 proposes a method of producing a silicon wafer that includes the steps of cutting wafers out of a silicon ingot as being grown by the CZ method and having a low interstitial oxygen concentration (7.0×1017 atoms/cm3 or less); and annealing the cut-out wafer in an oxidation atmosphere, thereby vanishing COPs. In this method, the resistivity is homogenized by resorting to measures such as irradiating the silicon ingot with neutrons to convert part of the silicon atoms into phosphorous atoms, so that the resulting wafer can be suitably used for a substrate of an insulated gate bipolar transistor (IGBT).
Moreover, Japanese Patent Application Publication No. 2003-297840 discloses a method of heat treatment in which a wafer having an oxygen concentration of less than 7×1017 atoms/cm3 is used, the heating temperature is selected such that the concentration of oxygen in equilibrium with the oxide film on the surface of COP exceeds the concentration of oxygen atoms dissolved in the interstices under an atmosphere containing oxygen, and the temperature of the wafer is rapidly increased to the selected temperature and kept for a specified time, followed by cooling. As a result, the oxide film on the COP surface is vanished due to the diffusion of the oxygen atoms into the crystal lattices. After the vanishment of the film, the COPs are vanished because of the diffusion of the vacancies or the interstitial silicon atoms. The outward diffusion of oxygen on the wafer surface does not count, and the diffusion of oxygen atoms at such a high temperature as causing the interstitial oxygen to be unsaturated gets the oxide film on the COP surface to be extinguished, so that COPs are vanished for a region more than at least 50% of a wafer thickness.
However, in the method of heat treatment described in Japanese Patent Application Publication No. 2003-297840, it is difficult to completely vanish the COPs existing in the inside of the wafer (bulk) by oxidation heat treatment, requiring a long period of time for the heat treatment, and consequently posing the problem of an increase in production cost. In addition, a wafer having a very low oxygen concentration has to be used, and thus the mechanical strength is low, thereby also causing the problem of generating slip dislocations in the wafer during the oxidation heat treatment at high temperature, or the like.
Along with the miniaturization and higher performance of devices in recent years, it has been clarified that even the existence of very micro COPs in active areas of the device of a wafer exerts an adverse influence on device characteristics such as lowering insulation properties of the gate oxide film (gate oxide breakdown voltage). Hence, the COPs within a wafer should be completely vanished.
In the method described in Japanese Patent Application Publication No. 2003-297840 mentioned above, in order to completely vanish the COPs, any one or the combination of measures of: (a) reducing the oxygen concentration to less than 7×1017 atoms/cm3; (b) increasing the heat treatment temperature; and (c) prolonging heat treatment time, needs to be used, however, either the pulling of a low oxygen single crystal, high temperature heat treatment, or heat treatment for a long period of time increases production cost. In the method of producing a silicon wafer described in above-mentioned Japanese Patent Application Publication No. 2006-344823 also, the production cost is also increased since a silicon ingot of an interstitial oxygen concentration of 7×1017 atoms/cm3 is used as a starting material.
This problem can be solved if a wafer is used that consists of defect-free regions that do not include COPs and dislocation clusters from the surface layer of the wafer to the entire bulk thereof. If a single crystal entirely consisting of the defect-free regions that do not include COPs or dislocation clusters is pulled up, such a wafer can be produced by cutting out of the single crystal and subjecting to necessary processing.
Such a single crystal entirely consisting of defect-free regions that do not include COPs and dislocation clusters is produced by pulling the single crystal while properly controlling the ratio (V/G) of the pulling rate V of the single crystal silicon to the temperature gradient G in the growth direction within the single crystal immediately after pulled. That is, in FIG. 1, COPs and dislocation clusters are prohibited from being introduced into the single crystal by adjusting pulling rate of the single crystal such that the V/G be controlled to be between the value corresponding to the position of symbol A and the value corresponding to the position of symbol B.
FIG. 2 is a drawing schematically showing one example of the transverse section of a pulled single crystal silicon. The drawing shows a wafer cut out of the single crystal grown such that V/G is controlled to be the value corresponding to the position of symbol C between symbol A and symbol B indicated in FIG. 1. As shown in FIG. 2, there is an OSF region at the center of the wafer, and a PV region and PI region successively exist outside the OSF region.
These regions locate between a territory including COPs as being an aggregate of vacancies and a territory including dislocation clusters as being an aggregate of interstitial silicon, and are the defect-free regions where the number of vacancies and the number of interstitial silicon are balanced to be easily united and vanished. The PV region is near the territory including COPs as being an aggregate of vacancies and is a defect-free region where vacancy-type point defects are dominant. The PI region is near the region including dislocation clusters and is a defect-free region where interstitial silicon-type point defects are dominant.
However, even such a wafer consisting of the defect-free regions that do not include COPs or dislocation clusters is not a perfect defect-free wafer. In the defect-free regions, the OSF region is adjacent to the region where COPs occur, and includes plate-like oxygen precipitates (OSF nuclei) in an as-grown condition. Hence, when the wafer is subjected to oxidation heat treatment at a high temperature (generally, from 1,000 to 1,200° C.), the OSF nuclei turn fat and overt as oxidation induced stacking faults (OSFs). Moreover, the PV region includes oxygen precipitation nuclei in the as-grown state, and if the wafer is subjected to heat treatment comprising two stages at low and high temperatures (e.g., 800° C. and 1,000° C.), oxygen precipitates are easily generated. The PI region substantially does not include oxygen precipitation nuclei in the as-grown state, and is a region in which oxygen precipitates are not easily generated even after the heat treatment.
The defects existing in the OSF region and PV region are not overt in the as-grown state, and are generated if they are subjected to the heat treatment or the like under specific conditions. However, the defects existing in the OSF region and PV region in addition to the above-described very micro COPs exert an influence on devices in terms of yield, which now cannot be ignored. For instance, it is well-known that, if the OSFs generated under the thermal oxidization at a high temperature are generated on the surface of the wafer and grown, the OSFs cause a leakage current to deteriorate the device characteristic. Additionally, the oxygen precipitate nuclei included in the PV region generate oxygen precipitates in the heat treatment in the process of device processings, and if the precipitates are left in the active layer of elements making up of the device, a leakage current might be occurred in the device.
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