1. Field of the Invention
The present invention relates to a flip chip mounting method and apparatus therefor for mounting a semiconductor element, such as LSI or so forth on a circuit board.
2. Description of the Related Art
As a method for mounting a bare chip, there has been proposed a pressure welding method. The pressure welding method does not require a supply of a bonding material, such as solder or conductive resin or the like. Electrical connection of an electrode of an LSI and a pad on a circuit board is established only by mechanical contact by shrinking force of a seal resin filled between the LSI and the circuit board.
Process steps of pressure welding are as follow. At first, a seal resin is supplied to a mounting position on the circuit board, where the LSI is to be mounted. Next, on the mounting portion, the LSI is mounted and pressurized. Subsequently, under this condition, heat or light is applied to cure the sealing resin to connect the electrode of the LSI and the pad on the circuit board.
A fabrication process of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. Showa 63-151033 is shown in FIG. 4.
At first, as shown in FIG. 4A, a thermosetting resin 13 is applied on a surface having a conductor wiring 12 of a wiring board 11.
Next, as shown in FIG. 4B, an LSI chip 14 is pressurized onto a wiring board 11 by a pulse heating tool 16 so that a projection electrode 15 on LSI chip 14 and a conductor wire 12, on wiring board 11 match with each other. Upon pressurizing the LSI chip 14, the thermosetting resin 13 on the conductive wiring 12 are pushed out to the circumference. Then, the projection electrode 15 and the conductive wire 12 are electrically contacted. In this condition, by supplying power to the pulse heating tool 16, the pulse heating tool 16 is heated to cure the thermosetting resin 13.
Subsequently, as shown in FIG. 4C, after a while upon termination of heating of the pulse heating tool 16, pressurizing force is released when the temperature is lowered to be lower than or equal to a predetermined value to fix the LSI chip 14 on the wiring board 11 and thus to establish electrical connection between the projection electrode 15 of the LSI chip 14 and the conductive wire 12.
In Japanese Unexamined Patent Publication No. Heisei 5-152359, there has been disclosed a potting apparatus which applies micro vibration to a protective resin during sealing or after sealing to get bubbles generated in the protective resin out or to prevent generation of bubbles initially and thus penetrates the protective resin into a fine gap.
In Japanese Unexamined Patent Publication No. Heisei 8-153752, there has been disclosed a following flip chip mounting method. At first, in a group of an insulation layer provided with a mounting pad of the circuit board, a sealing resin is filled. Next, in this condition, bubble in the circumference of the mounting pas is removed by heating and vacuum defoaming or application of ultrasonic vibration. Subsequently, an amount of the sealing resin is supplied in overlapping manner, and the semiconductor element is mounted.
In the pressure welding method set forth above, since the seal resin is filled between the LSI and the circuit board with flaring by the LSI, the protective resin is difficult to penetrate into the via hole or recessed portion of a solder resist formed on the circumference of the mounting pad. Namely, when flaring speed of the sealing resin is high or when the via hole or the recessed portion is small, the sealing resin flows out without filing into the via or recessed portion to permit residual air within the via or the recessed portion. In the pressure welding method, after flaring the seal resin, the seal resin is heated and cured. The residual air may expand during the process steps set forth above, a gap (hereinafter referred to as "void") is formed between the LSI and the circuit board. The void can cause lower reliability of electrical connection of the LSI and the circuit board due to lowering of fitting force of the LSi and the circuit board and lowering of shrinking force of the sealing resin and so forth. Therefore, it is required to completely avoid the void.
In the potting apparatus disclosed in Japanese Unexamined Patent Publication No. Heisei 5-152359, admixing of the bubble in the protective resin supplied from the nozzle is avoided. Avoiding the bubble residing in the fine groove of the electrode portion of the circuit board is difficult. On the other hand, upon mounting of the LSI on the circuit board, bubble penetrating into the protective resin from a bump can be avoided.
In the flip chip mounting method disclosed in Japanese Unexamined Patent Publication No. Heisei 8-153752, a vacuum drawing process is required to take a long period in operation. On the other hand, when the semiconductor element is mounted on the circuit board, penetration of bubble into the seal resin cannot be avoided.
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USPTO Backgrounds