For applications that require a printed circuit board (PCB) with a plurality of layers and a high density of interconnects, via holes have traditionally been fabricated by mechanically drilling a series of holes through the plurality of layers and then plating the holes with low resistivity metals. However, plating a long and narrow via hole has proven to be problematic. In order to have a sufficiently uninterrupted metal layer deposited within the via hole, aspect ratios (i.e., board thickness to hole diameter) have typically been limited to 15:1 for high volume, low cost PCBs and 36:1 for low volume, high cost PCBs. As packaging technology continues to advance and the pitch between electrical pads coupled to ends of the plated vias decreases, there is a need to substantially increase the aspect ratio of via holes even further.
This need is particularly true in the automated test equipment (ATE) industry for burn-in boards used for burn-in test, load boards used for package test, and probe cards used for wafer test. Probe cards, in particular, often require a 50:1 or 75:1 aspect ratio via hole for the 50 or more layers needed to internally route the PCBs. Thus, probe cards are extremely expensive owing in part to the layer and high aspect ratio requirements. In order to further reduce the cost of testing in ATE systems, more devices must be tested in parallel. As more devices are tested in parallel, more routing layers are needed to route electrical test signals to and from devices under test (DUTs). Consequently, the aspect ratio of the PCBs must be substantially increased beyond a 36:1 ratio. The increased routing layers results in an overall increase in thickness of the board.
Various methods of producing multilayered PCBs are known in the art. A commonplace production technique in the manufacture of some printed circuit boards is to form printed circuitry on both sides of a planar rigid or flexible insulating substrate. In addition, such boards also typically include several parallel and planar alternating inner layers of insulating substrate material and conductive metal. Exposed outer sides of the laminated structure are typically provided with circuit patterns and metal inner layers typically contain circuit patterns.
Conductive interconnections are provided between the various conductive layers or sides of the board in multilayered PCBs. The interconnections are commonly achieved by providing metallized conductive holes (i.e., conductive vias; also referred to in the printed circuit field as plated thru-holes or PTHs) in the board which communicate with faces and layers requiring electrical interconnection.
Typically, thru-holes are drilled (by mechanical or laser drilling means) or punched into or through the board at desired locations. Drilling or punching provides newly-exposed surfaces including via barrel surfaces and via peripheral entry surfaces. The dielectric substrate, comprising a top surface, a bottom surface, and at least one exposed via hole surface, consisting partly or entirely of insulating materials, is then metallized, generally by electroless metal depositing techniques, albeit other deposition processes are also known in the field.
When mechanically drilling a via hole through a board, care must be taken not to unintentionally drill through metallization layers that are not intended to be electrically connected to the via. Controlling the drill location within the layers of the PCB has proven to be difficult. As a result of the difficulty, large anti-pads must be created in internal and external layers of the PCB. The large anti-pads prevent inadvertent contact with particular metal layers but also limit electrical performance of the signals and create crosstalk for tight pitch devices. Further, the large anti-pads limit an overall surface density of vias.
With reference to FIG. 1, an enlarged section of a prior art PCB board 100 demonstrates difficulties encountered in contemporary via production. The prior art PCB includes a plurality of dielectric sheets 101. The dielectric sheet 101 material is usually comprised of an organic material such as fiberglass-reinforced epoxy resin (e.g., FR-4), polytetrafluoroethylene (e.g., Teflon ®, a trademark of E.I. du Point De Nemours & Co., Wilmington, Del.), Driclad (a trademark of Endicott Interconnect Technologies, Inc., Endicott, N.Y.), and similar materials known to one of skill in the art. Since the plurality of dielectric sheets 101 are nonconductive they are typically “seeded” and plated with a copper conductive layer 103. After the copper conductive layer 103 and other conductive traces or routings (not shown) are produced, each of the plurality of dielectric sheets 101 is laminated together. After lamination, a via hole 105 is mechanically drilled through the stacked plurality of dielectric sheets 101. To avoid any electrical contact between the copper conductive layers 103 and the via hole 105, large non-conductive anti-pads 107, produced on each sheet 101 prior to lamination, prevent unintended electrical communications. A conductive via plating 109 ideally is uninterrupted on sidewalls of the via hole 105 to permit electrical communications between upper and lower surfaces of the PCB 100. However, as the aspect ratio of the via 105 increases, production of an uninterrupted conductive via plating 109 becomes problematic. Therefore, as shown in FIG. 1, interrupted conductive via plating 109 may be present in via 105.
Therefore, what is needed is a simple, economical, and robust means of producing vias in PCBs which have high aspect ratio vias which are fully uninterrupted electrically, and require no large area anti-pads.
USPTO Backgrounds
USPTO Backgrounds