1. Field of the Invention
The invention relates to a method of fabricating a dual gate structure of embedded dynamic random access memory (embedded DRAM), and more particularly to a method of fabricating a dual gate structure in a logical circuitry of embedded DRAM to prevent interdiffusion from occurring in the dual gate.
2. Description of the Related Art
A logic circuitry and a DRAM cell region (memory cell region hereinafter) formed on the same semiconductor substrate define an embedded DRAM. N-type nMOSFET and pMOSFET poly gate structure usually form a CMOS structure in conventional logic circuitry. Punch through is easily induced in PMOS with an N-type poly gate, which also has lower threshold voltage and poor turnoff characteristics. NMOS and PMOS are therefore composed of N-type and P-type poly gates, respectively, to form a dual gate structure as applied in the logic circuitry to overcome the problem as described above.
In order to prevent minute current leakage and refresh sensitivity from occurring in the source/drain region of embedded DRAM, salicide can not be formed on the source/drain region of the memory cell region. On the other hand, the resistance of the poly gate has to be reduced, therefore a tungsten silicide must be formed on the poly gate to improve the conductivity of the gate. For the dual gate structure of the embedded DRAM, the resistance of the poly gate is reduced by the formation of tungsten silicide thereon; however, the tungsten silicide induces some problems that need to be overcome.
FIGS. 1A-1D are schematic, cross-sectional views illustrating fabrication of the dual gate of an embedded DRAM wherein the embedded DRAM has a logic circuitry 118a and a memory cell region 118b. Referring to FIG. 1A, a substrate 100 is provided, and a gate oxide layer 102 and a polysilicon layer 104 are respectively formed on the substrate 100. P-type and N-type ions are respectively implanted into the polysilicon layer 104 by using implanting mask to cover the polysilicon layer 104. A tungsten silicide layer 106 is formed on the polysilicon layer 104 to improve the conductivity of the gate formed in subsequent processes. The tungsten silicide layer 106, polysilicon layer 104 and gate oxide layer 102 are patterned to form a dual gate structure 108a and gate structure 108b, as shown in FIG. 1B. FIG. 2 is a perspective view of the dual gate structure 108a and gate structure 108b of FIG. 1B. The dual gate structure 108a has N-type 104a' and P-type 104b" polysilicon layer and the gate structure 108b has N-type polysilicon layer 104b. Spacers 112 are formed on the sidewalls of the dual gate structure 108a and the gate structure 108b. The substrate 100 beside the dual gate structure 108a and gate structure 108b has source/drain regions 110, 114 formed therein. The source/drain regions 110, 114 are formed by implanting ions into the substrate 100. Ions in the source/drain regions 110, 114 need to be activated thermally or by rapid thermal process (RTP).
Referring to FIG. 1C, an oxide layer is formed over the substrate 100 and the oxide layer is then defined by photolithography. The oxide layer on the logical circuitry 118a is removed to expose the dual gate structure 108a and the source/drain region 114. A titanium layer is formed on the substrate 100 and the titanium layer is then reacted with the exposed substrate 100 to form salicide 120 on the source/drain region 114 by RTP, as shown in FIG. 1D.
The formation of the tungsten silicide 106 is for increasing conductivity of the polysilicon layer 104. However, due to the high backend thermal budget and because the diffusion coefficient of impurities in the tungsten silicide layer 106 is much larger than that in the polysilicon layer 104a, 104b, N-type ions in the polysilicon layer 104a' of the dual gate 108a diffuse into the P-type polysilicon layer 104a" and P-type ions in the polysilicon layer 104a" of the dual gate 108a diffuse into the N-type polysilicon layer 104a'. Therefore, interdiffusion 122 as seen in FIG. 2 is caused between the polysilicon layer 104a', 104a" of the dual gate 108a.
USPTO Backgrounds
USPTO Backgrounds