1. Field of the Invention
The present invention relates to a method for utilizing fabrication defect of an article.
2. Description of Related Art
The fabrication process for integrated circuit dies includes film deposition, masking, photo lithography, etching, etc. During the fabrication process, the defects generated everyday in each process step and equipment are affecting the product yield. The product yield would have a direct relationship to the die cost.
However, the IC design houses have no direct knowledge or don't know how to control their own product's yield during fabricating stage. So the low yield failures will not be noticed until the design houses receive the wafer from foundry fab and finish wafer sort and package test. The design house may suffer customer delivery and quality issue if the wafer or package yield is lower than the requirement. It costs several months to make up the quantities to customer. The engineering resources in debugging low yield problem are also needed to dig out.
Some foundry fabs have considered the influence of defect to product yield. The foundry fabs used the defect area, which is generated from a defect scan and inspection tool, to determine whether the defect causes a killing failure and reduces the product yield. But the defect area represents a defect by a rectangular shape, which is usually larger than actual defect shape. This results in a wrong determination.
Therefore, there is a need for the design house or the foundry fab to accurately determine whether defects, generated during fabricating stage, cause failure or not, so as to further estimate product yield.
Consequently, because of the above limitation resulting from the technical design of prior art, the inventor strives via real world experience and academic research to develop the present invention, which can effectively improve the limitations described above.
USPTO Backgrounds
USPTO Backgrounds