The present invention is directed to automatic electronic-circuit testing and in particular to capacitive testing for open circuits.
The first step in testing electronic circuits that comprise a plurality of integrated circuits mounted on a printed-circuit board is to determine whether the board properly interconnects the integrated circuits mounted on it. In the typical case, it is only after this low-level test is complete that the more-complicated testing of the integrated-circuit and board functions can be performed.
Traditionally, the prevalent type of interconnection failure was a path-to-path short circuit caused by the soldering process between conductive paths on the printed-circuit board. As surface-mounted devices have become more popular, however, the incidence of open circuits, typically between device pins and the paths to which they are to be connected, has increased dramatically. Accordingly, whereas testing for open circuits had not previously been considered worth the effort in many cases, the ability to perform such tests has now become more important.
One type of open-circuit test, which lends itself particularly to performance by lower-cost test equipment, is the capacitive test. In this test, an AC signal is imposed on a printed-circuit path to which a device pin should be connected, and a capacitive probe placed against the device package picks up the resulting alternating electric field if the device pin is properly connected to the printed-circuit-board path. This approach can be quite effective, even in testing of surface-mount devices, whose pins typically are not readily accessible.
Although this approach does lend itself to testing of surface-mount and other types of board devices, its application presents certain difficulties. In the first place, the fixturing tends to be complex, since the capacitive probe is usually placed on the side of the circuit board under test opposite that on which the conventional, conductive probes are located. Therefore, a second fixture plate, disposed on the opposite side, must be provided.
Additionally, the capacitive signal coupling is typically low in capacitance and thus high in impedance, and steps must accordingly be taken to reduce to as great an extent as possible the resultant susceptibility to noise. For this reason, the area of a plate of the capacitive probe should be comparable in size to that of the device package's upper surface so as to maximize capacitance. The typical disposition of such large-area devices at the ends of "pogo"-type spring-loaded plungers results in a structure that not only tends to be relatively susceptible to damage but also requires a level of fixture-manufacturing sophistication that limits the tester owner's choice of fixture houses. These problems are further complicated by the fact that, in order to minimize the noise that corrupts the signal, a buffer amplifier is typically mounted right on each probe plate, at the end of the pogo probe, to buffer the signal before it has suffered much noise corruption.
USPTO Backgrounds
USPTO Backgrounds