In the manufacture of integrated circuits, there is a continuing desire to fit more semiconductor devices and circuits on semiconductor wafers. The drive for miniaturization and increasing circuit density is driven by a number of factors, including device speed, as denser circuits are closer together for fast communication, wafer utilization (more circuits per wafer) and potential semiconductor chip cost reduction as the number of semiconductor chips per wafer increase. However, as is usually the case, tradeoffs occur with increasing miniaturization and increased circuit density. As the semiconductor manufacturing processes are adjusted to enhance the performance of semiconductor devices, the thermal cycles required to create the semiconductor devices may adversely affect the performance of other nearby semiconductor devices or circuits. Additionally, as semiconductor devices are packed closer together, the heat generated by one semiconductor device may adversely affect the performance of another nearby semiconductor device.
One manufacturing method for creating wafers and semiconductor chips with improved performance, such as lower parasitic capacitance and reduced resistance to latch up, in addition to providing miniaturization capability, is the use of silicon on insulator (SOI) technology for wafer and subsequent semiconductor chip formation. SOI wafers provide layers of silicon separated by an insulation layer such as silicon dioxide. Fabricated semiconductor devices may be in the layer of silicon above an electrical insulator, improving performance capabilities. SOI wafers may be created by either an oxygen implantation using a high temperature anneal process or by bonding two wafers together with an oxide layer or dielectric material layer sandwiched between the wafers. The wafers, at least one of which is covered by an insulating or oxide layer, may be bonded by adhesive, or fusion bonded if both surfaces are covered with an oxide layer. SOI wafers provide improved performance and opportunities to utilize additional available wafer space created with an SOI structure. The processes involved in the manufacture of SOI wafers are consistent with semiconductor manufacturing tools and thus require little investment to implement.
USPTO Backgrounds
USPTO Backgrounds