1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor device, a spread spectrum clock generator and method thereof and more particularly to a semiconductor device, a spread spectrum clock generator and method of outputting signals.
2. Description of the Related Art
Increases in the operating speed of systems may cause an increase the speed at which data may be processed. Generally, to increase a data processing speed, a clock signal frequency may be increased. However, higher-frequency clock signals may contain a harmonic component. The harmonic component included in higher-frequency clock signals may cause electromagnetic waves which, in some cases, may be harmful to the human body. Conventionally, a shielding device (e.g., a capacitor) may be used to reduce the electromagnetic waves generated by the system, but such shielding devices may be limited with respect to a degree to which they may reduce the electromagnetic waves. Another conventional manner of reducing the energy of electromagnetic waves may be lowering the energy of harmonic component.
A phase-locked loop (PLL) may be used to generate a clock signal. A PLL may generate a modulated clock signal, alternatively referred to as a spread spectrum signal, to lower the energy of harmonics contained in the clock signal.
A phase modulation process and a frequency modulation process are examples of two conventional processes of generating a modulated clock signal using a PLL. The phase modulation method may use sigma-delta modulation in which the energy of an electromagnetic wave may be lowered by modulating a difference between phases of an input reference frequency and a feedback frequency with a sigma-delta modulation block of the PLL, and finely adjusting a current with a charge pump block of the PLL.
In the frequency modulation process, the energy of an electromagnetic wave may be reduced by using the phase locking range of a PLL circuit with a multi-stage counter or a read-only memory (ROM) while feeding back a frequency generated by a voltage-controlled oscillator (VCO) of a PLL.
FIG. 1 is a block diagram of a conventional spread spectrum clock generator 100. Referring to FIG. 1, the spread spectrum clock generator 100 may include a phase detector 110, a charge pump 120, a low-pass filter 130, a VCO 140, a frequency divider 150 that divides the frequency of a signal output from the VCO 140, and a sigma-delta modulator 160 that controls the operation of the frequency divider 150.
Referring to FIG. 1, the sigma-delta modulator 160 may receive a feedback signal output from the frequency divider 150 and may control a division ratio of the frequency divider 150 in response to a control signal C. For example, the sigma-delta modulator 160 may set the division ratio of the frequency divider 150 to N if a clock signal is set to a higher level (e.g., above a higher frequency threshold) and may set the division ratio to N−1 if the clock signal is to a lower level (e.g., below a lower frequency threshold).
Referring to FIG. 1, by using the sigma-delta modulator 160, the division ratio used to divide the frequency of the signal output from the VCO 140 may be adjusted to a non-integer, and a feedback signal that is phase-delayed by a cycle of the signal output from the VCO 140 may be supplied to the phase detector 110. However, if the division ratio of the VCO 140 is adjusted as described above, a signal phase-delayed by a relatively large amount (e.g., corresponding to a cycle of the signal output from the VCO 140) may be supplied to the phase detector 140, thereby increasing jitter in a spread spectrum clock signal FOUT.
FIG. 2 is a block diagram of another conventional spread spectrum clock generator 200. Referring to FIG. 2, the spread spectrum clock generator 200 may include a phase detector 210, a charge pump 220, a low-pass filter 230, a VCO 240, a selector 250 that may select one of a plurality of signals that may be output from the VCO 240, each of the plurality of signals having given phase differences, a frequency divider 260 that divides the frequency of a signal PSOUT output from the selector 250, and a sigma-delta modulator 270 that controls the operation of the selector 250.
Referring to FIG. 2, the VCO 240 may be a multi-phase VCO that generates a plurality of output signals, each having phase differences with respect to one another. One of the plurality of output signals may be selected (e.g., by the selector 250) for output as the spread spectrum clock signal FOUT.
FIG. 3 is a timing diagram for signals output from the spread spectrum clock generator 200 of FIG. 2. The sigma-delta modulator 270 of the spread spectrum clock generator 200 may receive a signal from the frequency divider 260, and may control the selector 250 to sequentially output a plurality of signals received from the VCO 240, or alternatively may continually output one of the signals received from the VCO 240 in response to a control signal C.
Referring to FIG. 3, if the selector 250 selects and outputs signals PO through P3, a signal PSOUT phase-delayed by a time period PE from each of the signals PO through P3 may be output from the selector 250.
Unlike the spread spectrum clock generator 100 of FIG. 1, the spread spectrum clock generator 200 of FIG. 2 may reduce jitter in a spread spectrum clock signal FOUT by supplying a feedback signal having different phase delays to the phase detector 210, rather than changing the division ratio of the frequency divider 260. Generally, the greater the number of signals output from the VCO 240, the smaller the difference of the phase delay of the feedback signal supplied to the phase detector 210.
Further, to reduce fabrication costs, a reference signal FIN with a lower frequency may be used, and the division ratio of the frequency divider 260 may thereby have to be increased to obtain higher-frequency clock signals. Therefore, the number of signals output from the VCO 240 to generate the spread spectrum clock signal FOUT may be increased. However, in general, a number of signals output from the VCO 240 may be relatively limited.
In order to increase a frequency offset of the spread spectrum clock signal FOUT, the sigma-delta modulator 270 may select a plurality of signals, sequentially at each clock signal, for the reference signal FIN. If the frequency of the reference signal FIN is Fr and the number of signals with a given phase difference output from the VCO 240 is N, a maximum possible frequency offset may be Fr/N.
The frequency offset may denote a frequency range within which the spread spectrum clock signal FOUT may fall. For example, if the frequency of the spread spectrum clock signal FOUT is configured for 1500 megahertz (MHz) and the frequency offset is 5%, the frequency of the spread spectrum clock signal FOUT may fluctuate between 1425 MHz (i.e., 1500 minus 5%) through 1500 MHz.
For example, in order to obtain a frequency offset ratio of 0.5%, if the frequency of the reference signal FIN is 25 MHz and the frequency of the spread spectrum clock signal FOUT is configured for 1500 MHz, N may equal 3.33 because the frequency offset may be denoted by 25/N and the frequency offset ratio may thereby be 25/N/1500=0.005. However, N may need to equal a natural number, i.e., N=3. Accordingly, if more than three signals having different phases are output from the VCO 240, it may be difficult or impossible to obtain a maximum possible frequency modulation ratio of 0.5% using the above-described conventional process.
In another conventional process, if more than three signals are generated by the VCO 240, the selector 250 may select three of the signals randomly (i.e., not sequentially) while bypassing or skipping certain signals, to reduce jitter in the spread spectrum clock signal FOUT. The selector 250 may supply the randomly selected signals to the frequency divider 260. For example, the selector 250 may not sequentially select the output signals P0 through P3 illustrated in FIG. 3, but instead may select the output signal P2 after the output signal P0. Alternatively, in another example, the selector 250 may select the output signal P3 after the output signal P1.
However, in the spread spectrum clock generator 200, the signals having a fixed phase difference may not be supplied as feedback signals to the phase detector 210. Instead, the signals having an adjusted phase difference may be supplied, thereby complicating a circuit logic and operation thereof.
USPTO Backgrounds
USPTO Backgrounds