1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) conversion method, and an A/D converter, a semiconductor device having a plurality of unit elements for detecting distribution of a physical quantity, and an electronic apparatus. More specifically, the present invention relates to a technique for converting analog output electrical signals into digital data, which is suitably used in electronic apparatuses, e.g., a semiconductor device for detecting distribution of a physical quantity, such as a solid-state imaging device, including an array of a plurality of unit elements that are sensitive to electromagnetic radiation input from the outside, such as light or rays, in which the distribution of the physical quantity that is converted into electrical signals by the unit elements is selectively read as electrical signals by address control.
2. Description of the Related Art
Semiconductor devices for detecting distribution of physical quantities are widely used in a variety of fields. In such semiconductor devices, a plurality of unit elements (such as pixels) that are sensitive to electromagnetic radiation input from the outside, such as light or rays, are arranged in a linear or matrix array.
For example, in the field of video apparatuses, charge-coupled-device (CCD), metal-oxide-semiconductor (MOS), or complementary-metal-oxide-semiconductor (CMOS) solid-state imaging devices for detecting a physical quantity, e.g., light (an example of electromagnetic radiation), are used. The distribution of the physical quantity that is converted into electrical signals by unit elements (or pixels in a solid-state imaging device) are read as the electrical signals.
One type of solid-state imaging device is an amplifier-type solid-state imaging device including pixels with active pixel sensor (APS) (also referred to as gain cell) architecture. In the APS architecture, a pixel signal generator that generates a pixel signal corresponding to a signal charge generated by a charge generator includes a driving transistor for amplification. Many CMOS solid-state imaging devices are of the type described above.
In such an amplifier-type solid-state imaging device, in order to read pixel signals to the outside, address control is performed on a pixel unit having an array of unit pixels to selectively read signals from the individual unit pixels. An amplifier-type solid-state imaging device is therefore one example of address-controlled solid-state imaging device.
For example, in an amplifier-type solid-state imaging device as one type of XY-addressed solid-state imaging device including a matrix of unit pixels, each pixel is configured using an active element of the MOS structure (MOS transistor) or the like so that the pixel itself can have the amplification capability. Signal charges (photoelectrons) accumulated in a photodiode acting as a photoelectric conversion element are amplified by the active element, and the amplified signals are read as image information.
In this type of XY-addressed solid-state imaging device, for example, a large number of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit. Accumulation of signal charges corresponding to incident light is started on a line-by-line (row-by-row) or pixel-by-pixel basis. Current or voltage signals based on the accumulated signal charges are sequentially read from the pixels by addressing. In the MOS (including CMOS) type, an exemplary address control method for simultaneously accessing pixels on one row to read pixel signals from the pixel unit on a row-by-row basis is often used.
The analog pixel signals read from the pixel unit are converted into digital data, as necessary, by an analog-to-digital (A/D) converter. Since the pixel signals are output in the form in which a signal component is added to a reset component, it is necessary to take the difference between a signal voltage corresponding to the reset component and a signal voltage corresponding to the signal component to extract a true effective signal component.
This also applies to a case where the analog pixel signals are converted into digital data. In this case, a difference signal component representing the difference between the signal voltage corresponding to the reset component and the signal voltage corresponding to the signal component is finally converted into digital data. Accordingly, a variety of arrangements for A/D conversion have been proposed in Japanese Unexamined Patent Application Publication No. 11-331883 and the following documents:
W. Yang et. al., “An Integrated 800×600 CMOS Image System”, ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 (hereinafter referred to as a first non-patent document)
Kazuya Yonemoto, “CCD/CMOS Image Sensor no Kiso to Oyo (fundamentals and applications of CCD/CMOS image sensors)”, CQ Publishing Co., Ltd., first edition, pp. 201-203, Aug. 10, 2003 (hereinafter referred to as a second non-patent document)
Toshifumi Imamura and Yoshiko Yamamoto, “3. Kosoku/kinou CMOS Image Sensor no Kenkyu (study on high-speed-and-performance CMOS image sensors)”, (which is available on-line via the Internet from <URL: http://www.sankaken.gr.jp/project/iwataPJ/report/h12/h12inde x.html>) (accessed Mar. 15, 2004) (hereinafter referred to as a third non-patent document)
Toshifumi Imamura, Yoshiko Yamamoto, and Naoya Hasegawa, “3. Kosoku/kinou CMOS Image Sensor no Kenkyu (study on high-speed-and-performance CMOS image sensors)”, (which is available on-line via the Internet from <URL: http://www.sankaken.gr.jp/project/iwataPJ/report/h14/h14inde x.html>) (accessed Mar. 15, 2004) (hereinafter referred to as a fourth non-patent document)
Imamura et. al., “3. Kosoku/kinou CMOS Image Sensor no Kenkyu (study on high-speed-and-performance CMOS image sensors)”, (which is available on-line via the Internet from <URL: http://www.sankaken.gr.jp/project/iwataPJ/report/h14/h14inde x.html>) (accessed Oct. 15, 2004) (hereinafter referred to as a fifth non-patent document)
Oh-Bong Kwon et. al., “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640×480 CMOS Imaging System”, VL3-03, IEEE, pp. 335-338, 1999 (hereinafter referred to as a sixth non-patent document)
However, the A/D conversion arrangements of the related art disclosed in the above-listed documents have difficulty in terms of the circuit size, the circuit area, the power consumption, the number of lines for interfacing with other functional units, noise and current consumption due to the lines, etc.
FIG. 9 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) of the related art in which an A/D converter and a pixel unit are mounted on the same semiconductor substrate. As shown in FIG. 9, a solid-state imaging device 1 includes a pixel unit (imaging unit) 10 having a plurality of unit pixels 3 arranged in rows and columns, a driving controller 7 provided outside the pixel unit 10, a counter (CNT) 24, a column processor 26 including column A/D circuits 25 provided for the respective columns, a reference signal generator 27 including a digital-to-analog converter (DAC) that supplies a reference voltage for A/D conversion to the column A/D circuits 25 in the column processor 26, and an output circuit 28 including a subtractor circuit 29.
The driving controller 7 includes a horizontal scanning circuit (column scanning circuit) 12 that controls column addressing or column scanning, a vertical scanning circuit (row scanning circuit) 14 that controls row addressing or row scanning, and a timing controller 21 that generates various internal clocks in response to a master clock CLK0 via a terminal 5a to control the horizontal scanning circuit 12, the vertical scanning circuit 14, and the like.
The unit pixels 3 are connected to row control lines 15 that are controlled by the vertical scanning circuit 14 and to vertical signal lines 19 that transfer pixel signals to the column processor 26.
Each of the column A/D circuits 25 includes a voltage comparator 252 and a data storage unit 255, and has a function of an n-bit A/D converter. The voltage comparator 252 compares a reference voltage RAMP generated by the reference signal generator 27 with analog pixel signals obtained for row control lines 15 (V0, V1, . . . ) from the unit pixels 3 via the vertical signal lines 19 (H0, H1, . . . ) The data storage unit 255 includes a latch (flip-flop) acting as a memory that stores a count value of the counter 24 that counts the time required by the voltage comparator 252 to finish its comparison operation. The data storage unit 255 includes n-bit latches 1 and 2 serving as internal independent storage areas.
The ramp reference voltage RAMP generated by the reference signal generator 27 is commonly fed to input terminals RAMP of the voltage comparators 252, and individual pixel signal voltages from the pixel unit 10 are fed to the other input terminals of the voltage comparators 252 that are connected to the vertical signal lines 19 of the associated columns. The signals output from the voltage comparators 252 are supplied to the data storage units 255.
The counter 24 performs counting in accordance with a count clock CK0 corresponding to the master clock CLK0 (for example, both clocks have the same clock frequency), and supplies count outputs CK1, CK2, . . . , CKn, together with the count clock CK0, commonly to the column A/D circuits 25 of the column processor 26.
Lines for the count outputs CK1, CK2, . . . , CKn from the counter 24 are routed to the latches of the data storage units 255 provided for the respective columns so that the single counter 24 can be shared by the column A/D circuits 25 for the respective columns.
The outputs of the column A/D circuits 25 are connected to horizontal signal lines 18. The horizontal signal lines 18 include signal lines for 2n bits, and are connected to the subtractor circuit 29 of the output circuit 28 via 2n sensing circuits (not shown) associated with the respective output lines. Video data D1 output from the output circuit 28 is output to the outside from the solid-state imaging device 1 via an output terminal 5c. 
FIG. 10 is a timing chart for illustrating an operation of the solid-state imaging device 1 of the related art shown in FIG. 9.
For example, for the first reading operation, the count value of the counter 24 is first reset to an initial value of 0. Then, after the first reading operation of reading pixel signals from the unit pixels 3 on an arbitrary row Hx to the vertical signal lines 19 (H0, H1, . . . ) becomes stable, the reference voltage RAMP generated by the reference signal generator 27 so as to change stepwise over time to form a substantially sawtooth (or ramp) waveform is input. The voltage comparator 252 compares the reference voltage RAMP with a pixel signal voltage on an arbitrary vertical signal line 19 (with a column number Vx).
In synchronization with the ramp-waveform voltage output from the reference signal generator 27 (at time t10), the counter 24 starts down-counting from the initial value of 0 in the first counting operation in order to measure a comparison time of the voltage comparator 252 using the counter 24 in response to the reference voltage RAMP input to the input terminal RAMP of the voltage comparator 252.
The voltage comparator 252 compares the ramped reference voltage RAMP from the reference signal generator 27 with the pixel signal voltage Vx input via the vertical signal line 19. When both voltages become equal, the voltage comparator 252 inverts its output from a high level to a low level (at time t12).
Substantially at the same time as the inversion of the output of the voltage comparator 252, the data storage unit 255 latches (holds or stores) the count outputs CK1, CK2, . . . , CKn from the counter 24 depending on the comparison period of time in the latch 1 of the data storage unit 255 in synchronization with the count clock CK0. The first iteration of A/D conversion is thus completed (at time t12).
When a predetermined down-count period elapses (at time t14), the timing controller 21 stops the supply of control data to the voltage comparator 252 and the supply of the count clock CK0 to the counter 24. The voltage comparator 252 thus stops generating the ramped reference voltage RAMP.
In the first reading operation, a reset component ΔV of each of the unit pixels 3 is read. The reset component ΔV includes noise that varies depending on the unit pixel 3 as an offset. The variations in the reset component ΔV are generally small, and the reset levels are common to all pixels. Thus, the output of an arbitrary vertical signal line 19 (Vx) is substantially known.
Thus, in the first reading operation of reading the reset component ΔV, the reference voltage RAMP is adjusted to reduce the comparison period. In this arrangement of the related art, comparison is performed on the reset component ΔV for a count period of 7 bits (128 clock cycles).
In the second reading operation, a signal component Vsig corresponding to the amount of light incident on each of the unit pixels 3 is read in addition to the reset component ΔV, and a similar operation to that of the first reading operation is performed.
More specifically, for the second reading operation, the count value of the counter 254 is first reset to an initial value of 0. Then, after the second reading operation of reading pixel signals from the unit pixels 3 on an arbitrary row Hx to the vertical signal lines 19 (H0, H1, . . . ) becomes stable, the reference voltage RAMP generated by the reference signal generator 27 so as to change stepwise over time to form a substantially ramp waveform is input. The voltage comparator 252 compares the reference voltage RAMP with a pixel signal voltage on an arbitrary vertical signal line 19 (with a column number Vx).
In synchronization with the ramp waveform voltage output from the reference signal generator 27 (at time t20), the counter 24 starts down-counting from the initial value of 0 in the second counting operation in order to measure a comparison time of the voltage comparator 252 using the counter 24 in response to the reference voltage RAMP input to the input terminal RAMP of the voltage comparator 252.
The voltage comparator 252 compares the ramp reference voltage RAMP from the reference signal generator 27 with the pixel signal voltage Vx input via the vertical signal line 19. When both voltages become equal, the voltage comparator 252 inverts its output from a high level to a low level (at time t22).
Substantially at the same time as the inversion of the output of the voltage comparator 252, the data storage unit 255 latches (holds or stores) the count outputs CK1, CK2, . . . , CKn from the counter 24 depending on the comparison period of time in synchronization with the count clock CK0. The second iteration of A/D conversion is thus completed (at time t22).
The data storage unit 255 stores the count value obtained in the first counting operation and the count value obtained in the second counting operation in different places of the data storage unit 255, namely, in the latch 2. In the second reading operation, the combination of the reset component ΔV and the signal component Vsig of each of the unit pixels 3 is read.
When a predetermined down-count period elapses (at time t24), the timing controller 21 stops the supply of control data to the voltage comparator 252 and the supply of the count clock CK0 to the counter 24. The voltage comparator 252 thus stops generating the ramp reference voltage RAMP.
At a predetermined timing (t28) after the second counting operation is completed, the timing controller 21 instructs the horizontal scanning circuit 12 to read pixel data. In response to the instruction, the horizontal scanning circuit 12 sequentially shifts a horizontal selection signal CH(i) to be supplied to the data storage unit 255 via control line 12c. 
The count values stored in the data storage unit 255, i.e., n-bit pixel data in the first iteration and n-bit pixel data in the second iteration each represented by digital data of n bits, are sequentially output to the outside of the column processor 26 via n (2n, in total) horizontal signal lines 18 and are input to the subtractor circuit 29 of the output circuit 28.
The n-bit subtractor circuit 29 subtracts, for each pixel position, the pixel data in the first iteration indicating the reset component ΔV of a unit pixel 3 from the pixel data in the second iteration indicating the combination of the reset component ΔV and the signal component Vsig of the unit pixel 3 to determine the signal component Vsig of the unit pixel 3.
A similar operation is repeatedly performed sequentially on a row-by-row basis. Therefore, video signals representing a two-dimensional image are obtained in the output circuit 28.
USPTO Backgrounds
USPTO Backgrounds