1. Field of the Present Invention
The present invention generally relates to the field of data processing systems and more particularly to systems for reliably communicating data over a transmission medium.
2. History of Related Art
The ability to reliably convert low voltage differential signals to CMOS levels has received significant attention with the increasing prevalence of networked and other types of systems in which data may reside in a permanent storage facility physically displaced from the system""s processor or processors by a significant distance (e.g., one meter or more). In such a system, information is typically communicated between the processor and storage system over a transmission medium such as copper wiring. Reliable communication of information at high speeds over a transmission medium of any considerable length is difficult to achieve. Capacitive and resistive loss characteristics inherent in any transmission medium degrade the original signal in proportion to the length of the transmission medium. If the signal attenuation due to these transmission losses exceeds roughly ⅓ of the original signal, it is generally considered advisable to utilize a differential signal to communicate the information. Transmission of information using differential signals compensates for ground level shifts between the components at either end of the transmission medium and signal attenuation along the medium. As supply voltages decrease and data rates increase however, the capabilities of conventional differential receiver circuits utilized to transform an incoming differential signal into a single ended CMOS compatible signal are reaching their limits. Minor variations or distortions introduced into even the most stringently matched transmission media and receiver circuit can affect the timing of data transitions by as much as 10% of the pulse width. Therefore, it is highly desirable to implement a differential signal receiver circuit that extends the capabilities of exiting circuits. It is further desirable if the implemented solution does not significantly increase the cost or complexity of the system and does not otherwise negatively affect the overall system performance.
The problems identified above are in large part addressed by a differential receiver circuit and an associated I/O device and data processing system for reliably producing single ended CMOS compatible signals in response to differential signals received from a transmission medium. Broadly speaking, the differential receiver circuit includes first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to and indicative of the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a single ended second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the difference in the first and second output signals. In the preferred embodiment, the first amplification stage includes an inhibit circuit suitable for receiving a inhibit control signal. The inhibit circuit is configured to drive the first amplification stage to a standby state if the control signal is in a predetermined xe2x80x9cinhibitxe2x80x9d state. In one embodiment; the first amplification stage includes first and second series circuits, first and second input circuits, and a current sinking and current sourcing device. The first series circuit includes a first pair of p-channel devices in series between a first rail voltage and a feedback node as well as a first pair of n-channel devices in series between the feedback node and a second rail voltage. The gates of the first pair of p-channel devices are connected to a first amplifier node and the gates of the first pair of n-channel devices are connected to a second amplifier node. The second series circuit includes a second pair of p-channel devices in series between the first rail voltage and the single ended output node of the amplifier circuit and a second pair of n-channel devices in series between the output node and the second rail voltage. The gates of the second pair of p-channel devices are connected to the first amplifier node and the gates of the second pair of n-channel devices are connected to the second amplifier node. The first input circuit includes a first input circuit p-channel device and a first input circuit n-channel device connected in series between a first input circuit node and a second input circuit node. The gates of the first input circuit p-channel device and the first input circuit n-channel device are coupled to receive a first input signal (V1) of the differential input signal. The second input circuit includes a second input circuit p-channel device and a second input circuit n-channel device connected in series between the first input circuit node and the second input circuit node. The gates of the second input circuit p-channel device and the second input circuit n-channel device are coupled to receive a second signal (V2) of the differential input signal. The p-channel current sourcing device is connected between the first rail voltage and the first input circuit node and the gate of the p-channel input circuit control device is connected to the first amplifier node. The n-channel current sinking device is connected between the second input circuit node and the second rail voltage, while the gate of the n-channel input circuit control device is connected to the second amplifier node. In one embodiment the differential receiver circuit further includes an inhibit circuit configured receive an inhibit control signal and to drive the p-channel devices gated to the first amplifier node and the n-channel devices gated to the second amplifier node to cutoff when the inhibit control signal is in a specified inhibit state. The inhibit circuit is preferably further configured to provide a low impedance path between the first amplifier node, the second amplifier node, and the feedback node when the inhibit control signal is in a specified functional state.
USPTO Backgrounds
USPTO Backgrounds