In the data processing art the amount of memory that is provided on a single integrated circuit chip has steadily increased with technological improvements. This increase in memory size requires more and more leads on a package for addressing and control of the memory. However, the packaging requirements for these new high density dynamic memory chips has been to stay with a standard dual-in-line eighteen pin integrated circuit chip package. This has created a need in the art for new circuits and techniques for control and access of high density memory in standard integrated circuit packages.
One technique that has been created has been the use of row address strobe (RAS) and column address strobe (CAS) addressing signals that are sequentially applied to a high density memory over the same address leads. However, these techniques are limited to use with standard addressing techniques where all memory is addressed in parallel and do not work with special memory addressing arrangements. Accordingly, there is a need in the art for a memory bank selectron arrangement that can work with a special memory addressing arrangement where different parts of a large memory are addressed differently responsive to a single input address.
USPTO Backgrounds
USPTO Backgrounds