1. Field of the Invention
The present invention relates to a multiplex circuit which generates high-speed data by multiplexing this data. In particular, the present invention relates to a multiplex circuit corresponding to an arbitrary frequency.
2. Description of Related Art
A block diagram of a conventional data multiplex circuit is shown in FIG. 4. In FIG. 4 a data generation circuit 11, multiplex circuit 4, dividing circuit 6, retiming circuit 8 and delay components 7, 15 for use in phase adjustment are provided.
Dividing circuit 6 receives a clock signal from input clock terminal 20, and generates dividing clock signal 6A. Dividing clock signal 6A is then input into data generation circuit 11. Data generation circuit 11 then generates data signal 11A which is synchronized with dividing clock signal 6A.
Delay component 15 receives the dividing clock signal 6A of dividing circuit 6, outputs and delay signal 15A. Multiplex circuit 4 receives data signal 11A and delay signal 15A, and performs multiplexing of this delay signal 15A as a synchronized clock. In other words, delay signal 15A functions as a multiplex clock signal adjusted to the phase of data signal 11A, and generates multiplex data signal 14A by means of multiplex circuit 4.
Delay component 7 delays the clock signal to be input from input clock terminal 20, and outputs delay signal 7A. Retiming circuit 8 receives as input multiplex data signal 14A and delay signal 7A. Delay signal 7A functions as a retiming clock adjusted to the phase of multiplex data signal 14A, which retimes the multiplex data signal 14A and outputs a multiplex signal from output terminal 21.
FIG. 5 shows a time chart of a conventional data multiplex circuit shown in FIG. 4. In FIG. 5, a waveform graph 20A of input clock 20 and an output waveform graph 6A of dividing circuit 6 are provided. In this figure, input clock 20 is divided by four, and then output. Output 6A of dividing circuit 6 is delayed by a delay time T1 from the input clock and then generated.
Data signal 11A to be output from data generation circuit 11, is generated after being delayed by a delay time T2 from the time when output 6A of dividing circuit 6 is input into data generation circuit 11. Output waveform 15A of delay component 15 is generated after being delayed by a delay time T7 from the waveform of output 6A. This output 15A functions as the waveform of the multiplex clock signal with a phase matching that of data 11A, and is adjusted according to an input margin of data signal 11A.
Output waveform 14A of multiplex circuit 14 is initially delayed by the operation time of multiplex circuit 14, and then generated after being delayed by a delay time T5. Output waveform 7A of delay component 7 is generated after being delayed by a delay time T8 from the waveform of clock signal 20A. This output 7A functions as the waveform of the retiming clock with a phase matching that of multiplex data signal 14A.
However, in the aforementioned structure of this conventional technology, it is necessary to delay multiplex clock 15A, bound for multiplex circuit 4, by a time T7 representing the delay T2 of data generation circuit 11 and the input margin to multiplex circuit 4 using delay component 15. In addition, it is also necessary to delay retiming clock 7A, bound for retiming circuit 8, by a time T8 corresponding to the sum of the delay T1 of dividing circuit 6, delay T7 of the dividing clock to multiplex circuit 4 and delay T5 of multiplex circuit 4, using delay component 7.
In this manner, the absolute delay time of the data generation circuit increases with increasing multiplicity, which consequently results in an increase in the absolute delay amount of multiplex clock 15A and retiming clock 7A.
USPTO Backgrounds
USPTO Backgrounds