The present invention relates to a semiconductor integrated circuit device, and to a technology effective for application to a device equipped with a memory circuit.
It has been reported that according to the known prior art search subsequent to the completion of the invention of the present application, Unexamined Patent Publication No. Hei 10(1998)-21686 (hereinafter called “a patent document 1”) and Unexamined Patent Publication No. Hei 7(1995)-37387 (hereinafter called “a patent document 2”) have been disclosed as ones wherein precharge circuits are respectively provided for signals lines for transferring read signals from memory cells as in the invention of the present application. Disclosed in the patent document 1 is that a memory circuit using capacity is provided for signals lines to properly perform a stage division of pipelines in a synchronous dynamic RAM (Random Access Memory), and a signal corresponding to an intermediate potential necessary for an amplifying operation of a main amplifier is stored in such a memory circuit to thereby provide a high-speed signal voltage. The patent document 2 discloses a circuit for supplying two types of write and read precharge voltages to signal lines according to operation modes.
As a laid-open document example related to a degradation phenomenon of a MOS device due to the bias of each gate and temperature, which is called NBTI (Negative Bias Temperature Instability), there has been known IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 5, pp. 921-926, MAY, 1999. While the precharge circuit exists in the patent documents 1 and 2, no attention is paid to the NBTI.
USPTO Backgrounds
USPTO Backgrounds