Read only memory (ROM), a kind of non-volatile memory, does not lose stored information and data even when power off. Erasable programmable ROM (EPROM) further develops ROM's application into capability of data erasable and rewriteable. However, erasing data in an EPROM requires ultraviolet rays, which raises cost of EPROM. Furthermore, all the programs or data stored in the EPROM are erased indiscriminately in an erasing process even only a portion of them are aimed to be erased. Therefore, for each data alternation, the whole flash memory needs to be reprogrammed, which is time-wasting.
Another kind of data erasable memory, electrically erasable programmable ROM (EEPROM), does not have above disadvantages, in which data can be erased and rewritten bit by bit, facilitating repeated programming, reading and erasing.
FIG. 1 is a schematic cross-sectional view of a memory cell in a conventional EEPROM.
Referring to FIG. 1, the memory cell includes a substrate 100, a storage transistor 10 and a selection transistor 20 disposed on the substrate 100. The storage transistor 10 and the selection transistor 20 are spaced apart. The storage transistor 10 includes a first gate stack on a top surface of the substrate 100, a first source region 109 and a first drain region in the substrate 100 and on opposite sides of the first gate stack. The selection transistor 20 includes a second gate stack, a second source region and a second drain region 107 in the substrate 100 and on opposite sides of the second gate stack, where the first drain region of the storage transistor 10 and the second source region of the select transistor 20 overlap with each other, forming a common doping region 108 which connects the storage transistor 10 and the selection transistor 20. The first gate stack of the storage transistor 10 includes a tunneling oxide layer 101, a floating gate 102, a control gate oxide layer 103 and a control gate 104 successively formed on the top surface of the substrate 100. The second gate stack of the select transistor 20 includes a gate oxide layer 105 and a gate electrode 106 successively formed on the top surface of the substrate 100. An N-well is formed in the substrate 100. The second drain region 107, the first source region 109 and the common doping region 108 are all P-type doped.
Erasing operation of the memory cell includes: applying positive voltages to the gate electrode 106 (coupled to a word line) of the select transistor 20 and to the first source region 109 (coupled to a source line) of the storage transistor 10, applying a negative voltage to the control gate 104 of the storage transistor 10, and configuring the second drain region 107 (coupled to a bit line) of the selection transistor 20 to open. By doing this, electrons stored in the floating gate 102 of the storage transistor 10 may pass through the tunneling oxide layer 101 and be transferred to the first source region 109, which accomplishes erasing the memory cell.
More information about manufacturing EEPROM devices may be referred to U.S. Patent Publication No. US2010/0311603A1.
However, the memory cell of the conventional EEPROM includes a storage transistor and a selection transistor which are spaced apart from each other. A common doping region is necessary to realize the connection of the two above-mentioned transistors, which increases difficulty in shrinking the memory cell. Therefore, the whole EEPROM including a plurality of memory cells may have a relatively large size and occupy a relatively large space, which increase the manufacturing costs.
Therefore, there is a need for a flash memory and a method for forming the same to reduce the size of a memory cell and decrease the manufacturing costs.
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