The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The cost of integrated circuits (ICs) may be reduced in many ways. For example, the number of functions integrated into an IC may be increased. Alternatively, the number of electrical connecting pins (referred to herein as “pins”) of an IC package may be reduced while integrating the same or more functions in an IC contained within the IC package.
A function in an IC is typically performed by one or more logic circuit elements. Examples of logic circuit elements (referred to herein as “logic”) include gates, flip-flops, memory cells, etc. Recent advances in IC manufacturing technology permit the size of logic to be reduced. Accordingly, more logic may be integrated into an IC. Adding more logic to an IC, however, may require the addition of more pins to an IC package.
The pins of an IC package are generally connected via bond wires to bond pads of an IC within the IC package. While the size of the internal logic can be reduced, the bond pads typically cannot be made correspondingly smaller. The bond pads need to have a minimum size so as to permit bond wires to be attached to the bond pads. Additionally, the size of transistors needed to drive the external logic requires larger bond pads.
Accordingly, the size and quantity of the bond pads needed for a design of an IC package may cause the design to be pad limited. That is, the size of a die used in the design is dictated by the size and quantity of the bond pads instead of being dictated by the number of logic gates used in the design. Thus, manufacturing costs cannot be reduced by using smaller internal gate geometry since smaller internal gate geometry does not decrease the size of the die. Instead, the bond pads determine the physical limits of the size of the die.
Therefore, use of the bond pads and pins of the IC package may have to be optimized if more logic is to be integrated in the IC package. Alternatively, if more logic is not to be integrated, the number of pins of the IC package may have to be reduced so that the die does not become pad limited as smaller internal gate geometry is used.
USPTO Backgrounds
USPTO Backgrounds