1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a plurality of signal lines for transmitting a signal to a plurality of memory cells formed on a chip.
2. Description of the Prior Art
In the bus line of a conventional semiconductor memory device, signal output portions are collected to one position, and signal input portions are limited to a specific position of a memory cell array or decoder layout positions.
More specifically, this bus line is recognized not as wiring lines but as a wiring group of a bundle of lines. Hence, the bus line is also laid out as a wiring group of a bundle of lines. For example, like wiring lines other than the bus line, adjacent wiring lines are laid out at an interval based on a value "S" that represents the minimum distance between signal lines, which is determined on the basis of the design rule.
A parasitic capacitance C between adjacent wiring lines is given by EQU C=2.times..epsilon..times.t(LA/S+LB/S)=2.times..epsilon..times.t(LA+LB)/S(1 )
where
.epsilon. is the permittivity between signal lines, PA1 t is the height (thickness) of the signal line, PA1 LA is the wiring length of a signal line at a portion where wiring lines are densely laid out, PA1 LB is the wiring length of a signal line at a portion where wiring lines are sparsely laid out, and PA1 S is the value representing the minimum distance between signal lines, which is determined on the basis of the design rule. PA1 a semiconductor chip having PA1 a plurality of storage regions for storing data, PA1 a circuit region where circuits for accessing the plurality of storage regions, including an address decoder, are arranged, and PA1 a wiring region having a plurality of first signal lines for transmitting signals to the plurality of storage regions, and a plurality of second signal lines for transmitting signals to the circuit region, each of the second signal lines being laid out between the first signal lines and having a wiring length shorter than that of each of the first signal lines, PA1 wherein the wiring region has a portion where wiring lines are densely laid out by laying out the plurality of first signal lines and the plurality of second signal lines, and a portion where wiring lines are sparsely laid out by laying out only the first signal lines, PA1 wherein the second signal lines laid out between the first signal lines adjacent to each other are laid out in the wiring region of the semiconductor chip while being separated from the first signal lines adjacent to the second signal lines by a distance not less than a minimum distance between signal lines, which is determined on the basis of a design rule, and PA1 wherein the plurality of first signal lines are laid out in the wiring region of the semiconductor chip at an interval (K) obtained by EQU K.gtoreq.2S+L PA1 at the portion where the wiring lines are sparsely laid out, the second signal line to be laid out is laid out in the wiring region of the semiconductor chip outside an outermost signal line of the plurality of first signal lines while being separated from a first signal line adjacent to the second signal line by the distance not less than the minimum distance (S).
FIGS. 1A to 1D show the operation of the semiconductor memory device which has the parasitic capacitance C obtained by substituting values into equation (1).
FIG. 1A shows a case wherein signals transmitted through wiring lines adjacent to each other in a wiring group A as a bus line are in phase (changes in level of signals transmitted through the wiring lines are in phase). FIG. 1B shows waveforms representing changes in level of signals.
Referring to FIG. 1B, a line segment indicated by a dotted line is a waveform representing a change in level of a signal on the circuit output side of a wiring line 1 of interest. A line segment indicated by a solid line is a waveform representing a change in level of the signal on the far-end side of the wiring line 1.
Since the wiring lines are of the same level, the parasitic capacitance between the wiring lines does not act as a capacitance. Hence, the delay time at the far-end portion when viewed from the circuit output portion is determined in accordance with the capacitance between the wiring line and the substrate.
The time until the level of the signal transmitted to the wiring line 1 of interest reaches a predetermined level Vcc, i.e., the delay time from reference time t.sub.0 will be described. At the circuit output portion, the delay time is (time t.sub.1 -time t0). At the far-end portion, the delay time is (time t2-time t0).
FIG. 1C shows a case wherein signals transmitted through wiring lines adjacent to each other in the wiring group A have opposite phases (changes in level of signals transmitted through the wiring lines have opposite phases). FIG. 1D shows waveforms representing changes in level of signals.
Referring to FIG. 1D, a line segment 120 indicated by a dotted line is a waveform representing a change in level of a signal on the circuit output side of the wiring line 1 of interest. A line segment 110 indicated by a solid line is a waveform representing a change in level of the signal on the far-end side of the wiring line 1.
The waveform whose level rises as the time elapses represents a change in level of the signal transmitted through the wiring line 1 of interest. Line segments 130 and 140 of waveforms whose level drops as the time elapses represent changes in level of the signal transmitted through a wiring line 2 adjacent to the wiring line 1.
As shown in FIG. 1C, since the signals transmitted through the wiring lines have different levels, the parasitic capacitance between the wiring lines acts as a capacitance. The capacitance of the entire wiring corresponds to the sum of the substrate capacitance and parasitic capacitance.
Hence, the delay time at the far-end portion when viewed from the circuit output portion is longer than that when the changes in level of signals transmitted through the wiring lines are in phase.
The time until the level of the signal transmitted by the wiring line 1 of interest reaches the predetermined level Vcc, i.e., the delay time from the reference time t0 will be described. At the circuit output portion, the delay time is (time t3-time t0). At the far-end portion, the delay time is (time t4-time t0).
When the delay time when the changes in level of the signals transmitted through the wiring lines are in phase is compared with that in opposite phases, time t3&gt;time t1, and time t4&gt;time t2hold.
As devices that decrease the parasitic capacitance and shorten the delay time, devices disclosed in Japanese Unexamined Patent Publication No. 3-225697 (to be referred to as prior art 1 hereinafter) and Japanese Patent No. 2776551 (to be referred to as prior art 2 hereinafter) are known.
In the circuit disclosed in prior art 1, a power supply line or ground line is divided and laid out between signal lines to separate adjacent signal lines via the power supply lines or ground lines, thereby decreasing the mutual capacitance (i.e., parasitic capacitance).
In the device disclosed in prior art 2, the first signal line group for transmitting in-phase signals and the second signal line group for transmitting signals in phase opposite to that of the in-phase signals of the first signal line group are separated by a distance longer than that between signal lines in the same signal line group. With this arrangement, the influence of coupling noise is reduced at a portion where the signal lines for transmitting signals in opposite phases are adjacent to each other.
As described above, in the conventional semiconductor memory device, since the wiring lines of the bus line are laid out at the interval based on the minimum distance (S), the parasitic capacitance C obtained by substituting values into equation (1) is generated between the wiring lines.
For this reason, when the signals transmitted through the wiring lines adjacent to each other have opposite phases, the capacitance of the entire wiring equals to the sum of the substrate capacitance and parasitic capacitance.
Hence, the delay time at the far-end portion viewed from the circuit output portion is longer than that when the signals transmitted through the wiring lines adjacent to each other are in phase.
The wiring lines are laid out in a long distance while keeping the minimum wiring interval. In a high-frequency operation, the delay time becomes long at the far-end portion when viewed from the circuit output portion. Accordingly, the time until the signal becomes active is also delayed. For this reason, the memory operation at the far-end portion cannot follow up, resulting in degradation in access characteristics and the like.
For the devices disclosed in the prior arts, nothing has been taken into consideration about a technique of improving the memory performance, i.e., shortening the signal delay time by decreasing the parasitic capacitance when the signals transmitted through the wiring lines adjacent to each other in the bus line (a plurality of wiring lines) have opposite phases.
For this reason, if the signals transmitted through the wiring lines adjacent to each other are in opposite phases, it is difficult to improve the memory characteristics.
USPTO Backgrounds
USPTO Backgrounds