A. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
B. Description of the Related Art
Conventionally, power semiconductor devices, which are represented by a FWD (free-wheeling diode), an IGBT (insulated gate bipolar transistor), and a MOSFET (insulated gate field effect transistor), have generally vertical structures in which impurity layers and electrodes are formed on a semiconductor chip not only at the front surface side but also at the back surface side. Vertical semiconductor devices are normally manufactured so that a semiconductor wafer is ground at the back surface to thin and then one impurity layer is formed as a back surface element structure on the whole back surface of the semiconductor wafer that has been ground after, or on the way of forming, a front surface element structure on the front surface side thereof.
On the other hand, a reverse conducting IGBT (RC-IGBT) integrated by including an IGBT and a FWD in the same semiconductor chip comprises two impurity layers in which the conductivity types are different to each other at the back surface side of the semiconductor chip. The two impurity layers are disposed in parallel as the back surface element structure in the horizontal direction to the principal surface of the chip. Then, the RC-IGBT requires that the back surface of a semiconductor wafer is ground to thin, and then each of ion implanting processes is performed to form the two impurity layers with different conductivity types to each other on the back surface which has been ground of the semiconductor wafer.
As a method for forming the back surface element structure of the RC-IGBT, it is known that the method includes the following processes. A resist mask covers one part corresponding to one region where one of the two impurity layers with different conductivity types to each other is formed, and then implanting ions can form the other impurity layer at the other part, where exposed at the opening of the resist mask, corresponding to the region where the other impurity layer should be formed. These processes are repeated twice by changing a part covered by the resist mask and a conductivity type of the impurity which will be implanted. This raises a problem of increase in manufacturing costs owing to patterning processes of two times for forming resist masks.
As another method for forming the back surface element structure of the RC-IGBT, it is known that the method includes the following processes. One of the two impurity layers with different conductivity types to each other is formed on the whole back surface of the semiconductor wafer. Then a resist mask covers one part of the region where one impurity layer has been formed. Implanting ions inverts one conductivity type of the other part, where exposed at the opening of the resist mask, corresponding to the region where the other impurity layer will be formed, forming the other impurity layer. This method can reduce the patterning process for forming resist mask to one time.
Japanese Unexamined Patent Application Publication No. 2005-057235, No. 2009-158922, No. 2006-019556, and No. 2011-222660, referred to herein as “Patent Documents 1 to 4,” respectively, describe two kinds of methods in which the patterning process for forming resist mask can be reduced to one time for forming the back surface element structure. The first method provides that a p-type impurity layer is formed on the whole back surface of the semiconductor wafer, and then an n-type impurity layer is selectively formed using a resist mask as a mask after patterning for forming the resist mask. The second method provides that an n-type impurity layer is formed on the whole back surface of the semiconductor wafer, and then a p-type impurity layer is selectively formed using a resist mask as a mask after patterning for forming the resist mask.
The first method provides that performing an ion implanting process of an n-type impurity inverts a part of the p-type impurity layer which has been formed earlier, forming the n-type impurity layer. FIGS. 6 to 8 are sectional views illustrating stages on the way of manufacturing a conventional semiconductor device. Specifically, the first method provides that implanting ions of boron (B) 121 can form a p+ impurity layer 111a on the whole back surface of an n− semiconductor wafer 101 (FIG. 6). Next, implanting ions of phosphorous (P) 123 on the back surface of the n− semiconductor wafer 101 using a resist mask 122 as a mask inverts a part of the p+ impurity layer 111a to that of n-type, forming an n+ impurity layer 112a (FIG. 7).
Afterward, activating the p+ impurity layer 111a and the n+ impurity layer 112a through heat treatment can form a p+ collector layer 111 and an n+ cathode layer 112, respectively (FIG. 8). The second method, in contrast to the first method, provides that, after forming an n+ impurity layer on the whole back surface of the n− semiconductor wafer, implanting ions of a p-type impurity inverts a part of the n+ impurity layer formed previously to the p-type, forming a p+ impurity layer. In both of the first and the second methods, the second ion implanting process (referred as high dose ion implantation in the following) using a resist mask is carried out with a high dose to invert the impurity layer with different conductivity type.
Then, on the ion implanting process using the resist mask as described above, loss of vacuum in a chamber of an ion implanter might occur during ion implantation. The reason is as follows. The temperature of the wafer rises owing to kinetic energy which the resist mask has received in collisions with impurity ions, and then organic solvent components constituting the resist mask are vaporized. Thus gas is emitted (so-called degassing) in the chamber. Further, so-called “sag” of a pattern, which corresponds to deformation of a resist pattern, is generated owing to the rise in temperature of the wafer. This causes the thickness of external periphery of the resist mask to become thinner partially. Thus an impurity ion implanted is liable to penetrate through a thinner part of the resist mask.
Japanese Unexamined Patent Application No. 08-031764, referred to herein as “Patent Document 5,” describes an ion implanter which can suppress degassing including an air-lock chamber with its inside state selectively switched between a vacuum state and an atmospheric state by using a vacuum exhaust measure and a ventilation measure, wherein the air-lock chamber is disposed adjacent to an implantation chamber; and a light source for irradiating the surface of processing object in the air-lock chamber. Furthermore, Japanese Unexamined Patent Application No. 07-105902, referred to herein as “Patent Document 6,” describes an ion implanter that can prevent a deformation of the resist pattern. The ion implanter includes a temperature sensor disposed on a platen which places a wafer; and a controller for scanning ion beam only when a temperature detected by the temperature sensor is within the setting condition.
Further, the temperature of the semiconductor wafer rises during ion implantation. Heating to cure the surface layer of the resist mask forms a deteriorated layer thereon. Thus a resist residue might be produced when the resist mask could not be removed perfectly. The deteriorated layer, which is formed by curing the surface layer of the resist mask, has an extremely lower ashing rate than normal resist, so this causes the resist residue to occur. As a method to remove a resist mask used for ion implantation without any residue, Japanese Unexamined Patent Application No. 2003-045858, referred to herein as “Patent Document 7,” describes a method for removing the resist mask after a process for injecting ions of a conductive type impurity element and ions of a rare gas element simultaneously.
Another method to remove a resist mask used for ion implantation without any residue is disclosed in Japanese Unexamined Patent Application No. 2010-010400, referred to herein as “Patent Document 8.” It describes a method in which, after a processing wafer is baked under normal pressure in order to remove a resist cured by ion implantation, for example, the processed wafer is subjected to plasma ashing processing in a high temperature area at about 300° C. in an oxygen single gas atmosphere composed of an oxygen gas substantially. Also, as a method to remove a resist mask without deterioration, Japanese unexamined Patent Application No. 11-162936, referred to herein as “Patent Document 9,” describes a method in which a light-ashing performed in a pre-asher room, a main ashing performed in a post-ashing room, and also an after light ashing in the pre-asher room are separately conducted each other. By the above ashing of three times, a high peeling off characteristic to the resist and a high processing ability to an apparatus are given.
However, the thinner the thickness of the semiconductor wafer becomes, the worse the radiation of heat becomes. Then a rise in temperature of a semiconductor wafer, which occurs due to the kinetic energy which a resist mask has received during ion implantation, become more remarkable. Patent Documents 5 to 9 do not refer to application for a semiconductor device having withstand voltage equal to or less than 2000 V (Withstand voltage≈Thickness of the n− semiconductor substrate×10), namely, a thin semiconductor wafer having a thickness equal to or less than 200 μm, for example. Then the temperature might rise during ion implantation for the thin semiconductor wafer equal to or less than 200 μm in thickness.
In the case of a rising in temperature of the semiconductor wafer during ion implantation, as described above, degassing occurs from the resist mask, and then a vacuum level will drop in a chamber of an ion implanter. Thus an action might be handled by the ion implanter as an emergency, requiring operator intervention such as maintenance, and then the ion implanting process might be interrupted. Further, the rise in temperature of the semiconductor wafer causes loss of vacuum in the chamber of the ion implanter. Thus a variation of dose for ion implantation might increase.
Moreover, the rise in temperature of the semiconductor wafer during ion implantation causes an organic solvent element constituting the resist mask to bump and then to scatter by spouting from the inside of the resist mask (foaming from the resist mask). Thus contaminations such as particles are liable to stick on the semiconductor wafer. Further, the rise in temperature of the semiconductor wafer during ion implantation causes the resist mask pattern to sag. Then the ion implanting process can not be performed by using desired resist pattern. Thus owing to problems encountered by the rise in temperature of the semiconductor wafer, yield may decrease.
Loss of vacuum and the sag of the resist mask pattern during ion implantation become more remarkable for the first method than for the second method as described above. The reason is that the kinetic energy which resist mask has received is larger for the first method which inverts the impurity layer from p-type to n-type by implanting ions of the n-type impurity such as phosphorus (P), arsenic (As), and antimony (Sb), which have higher mass number than the p-type impurity, in comparison with the second method which inverts the impurity layer from n-type to p-type by implanting ions of the p-type impurity such as boron (B).
Further, the higher the dose in ion implantation is, the more remarkable the loss of vacuum and the sag of the resist mask pattern become during ion implantation. Specifically, for the first method, high dose ion implantation is performed using an n-type impurity with a high dose equal to or greater than 1.0×1015 cm−2, for example. Decreased beam current during ion implantation can suppress the loss of vacuum and the sag of the resist mask pattern. However, this raises a problem of lowering throughput.
As a measure to suppress the loss of vacuum and the sag of the resist mask pattern, normally curing through ultraviolet irradiation and baking through heat treatment are conducted for the resist mask which has been patterned before implanting ions using the resist mask as a mask. However, as described above, in the case of a thin semiconductor wafer, the rise in temperature of the semiconductor wafer becomes remarkable. Then there is a risk that the loss of vacuum in the chamber and the sag of the resist mask pattern cannot be suppressed.
In the case that an impurity having higher mass number is implanted by high dose ion implantation with a higher dose, a resist residue also increases when ashing. The reason is that the higher the mass number of the impurity implanted is, the greater the damage given to the resist mask becomes, and then the greater the thickness of the deteriorated layer becomes. Moreover, when subsequent processes are continued under the state that the resist residue has been produced, the resist residue causes the semiconductor wafer to be contaminated in the subsequent processes. In addition, the resist residue is liable to cause so-called “cross-contamination” that the processing equipment is contaminated and then the other semiconductor wafer will be also contaminated. This raises a problem of lowering yields of the semiconductor wafers not only for the wafer on which the resist residue has been produced, but also for the other.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
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