Field of the Invention
The present invention relates to an image sensor, and an image capturing apparatus and a cellular phone using the image sensor.
Description of the Related Art
Conventionally, in a CMOS image sensor which is one type of solid-state image sensing elements, fusion of a CMOS logic process and image sensor process makes it possible to lay out a complicated analog circuit, digital circuit, signal processing unit, and so on, in a sensor chip. As an example, a CMOS image sensor formed with an analog digital (AD) converter laid out in an image sensor chip where pixels are two-dimensionally arranged has been already put to practical use.
In a case of forming an AD converter in an image sensor, such as a CMOS image sensor (referred to as a “CMOS sensor” hereinafter), a so-called column AD structure has been adapted. In the column AD structure, an AD converter is provided for each column of a pixel array arranged in matrix, and it is possible to reduce a conversion rate of each AD converter from a readout rate of one pixel to a readout rate of one row. Accordingly, not only overall power consumption can be reduced as the conversion rate of the AD converter decreases, but also the readout rate of the CMOS sensor can be easily increased as a consequence.
As an example of a CMOS sensor using a column AD structure, a CMOS sensor using a ramp type AD converter which uses a triangle wave has been put to practical use. In the ramp type AD converter, an analog value is input to one of the input terminals, and a reference output value that increases along with an operation of a counter is applied to the other input terminal. The AD conversion is implemented by taking a counter value at the time when the reference output value coincides with the analog value.
As the triangle wave changes the voltage in synchronization with the counter, in a case of an 8 bit AD converter, maximum of 28 steps, namely, 256 steps of processes are needed in AD conversion. In a CMOS sensor using such ramp type AD converter, if the analog signal applied to the input terminal is large, the number of steps becomes large, and AD conversion processing speed decreases. If the speed up of the AD conversion processing is attempted, then a bit accuracy of the AD conversion decreases in a case where an analog signal applied to the input terminal is small.
In consideration of above, Japanese Patent Laid-Open No. 2005-333316 suggests to switch between the configurations of an AD converter depending on whether an operation mode which gives priority to increasing the number of bits is set or an operation mode which gives priority to increasing processing speed is set, thereby realizing both an increase in the number of bits and an increase in the processing speed in AD conversion.
However, in the technique disclosed in the Japanese Patent Laid-Open NO. 2005-333316, it is not possible to increase the number of bits and the processing speed in the AD converter simultaneously. Further, since the AD converter to be used is changed in accordance with the operation mode, the accuracy of the AD conversion may fluctuate depending on the levels of pixel signals.
USPTO Backgrounds
USPTO Backgrounds