1. Field of the Invention
Generally, the present disclosure generally relates to sophisticated semiconductor devices and the manufacturing of such devices, and, more specifically, to various embodiments of novel three dimensional RRAM (Resistance Random Access Memory) devices, and various methods of making such three dimensional RRAM devices.
2. Description of the Related Art
As is well known to those skilled in the art, non-volatile memory (NVM) devices are characterized in that there is no loss of data stored in their memory cells, even when an external power supply is removed. For that reason, such non-volatile memory devices are widely employed in computers, mobile communication systems, memory cards and the like.
Flash memory structures are widely used in such non-volatile memory applications. The typical flash memory device employs memory cells having a stacked gate structure. The stacked gate structure typically includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked above a channel region. While flash memory structures have enjoyed enormous success, the continued and ever-present drive to reduce the size of integrated circuit products has created many challenges for the continued scaling of flash memory devices. Such challenges include scaling of program/erase voltages, access speed, reliability, the number of charges stored per floating gate, etc. Scaling attempts have included the fabrication of three dimensional floating gate memory devices where memory cells are stacked vertically. However, such stacking alone may not be sufficient to achieve the desired scaling of memory devices with critical dimensions less than 30 nm.
A resistance random access memory (RRAM) device is a simple two-terminal device memory device comprised of two spaced-apart electrodes with a variable resistance material layer or ion conductor layer positioned between the two electrodes. An RRAM is commonly connected in a 1T1R configuration, whereby the 1T (a transistor) is the selector and the 1R is an RRAM cell. The variable resistance material layer is typically comprised of various metal oxides, such as nickel oxide, titanium oxide, zirconium oxide, copper oxide, aluminum oxide, etc. The variable resistance material layer is used as a data storage layer. The resistance of the variable resistance material layer may be varied or changed based upon the polarity and/or amplitude of an applied electric pulse. The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material and establish a highly localized conductive filament (CF) in the variable resistance material. The pulse is of low enough energy so as to not destroy, or significantly damage, the material. Multiple pulses may be applied to the material to produce incremental changes in properties of the material. One of the properties that can be changed is the resistance of the material. The change may be at least partially reversible using pulses of opposite polarity or pulses having a different amplitude from those used to induce the initial change.
The present disclosure is directed to various embodiments of novel three dimensional RRAM devices, and various methods of making such RRAM devices that may improve bit densities and may lower the cost per bit of memory devices.
USPTO Backgrounds
USPTO Backgrounds