1. Field of the Invention
The present invention relates to a device and method for detecting path-delay faults in a sequential circuit. In particular, the invention provides a clocking scheme for use with a scan-based built-in self-test (BIST) architecture to detect path-delay faults in a sequential circuit and a technique for selecting observation points to improve fault coverage.
2. Description of the Related Art
Integrated circuits comprise one or more individual circuit elements, each of which is either combinational, e.g. a logic gate, or sequential, e.g. a flip-flop. It is beneficial to evaluate a circuit to ensure that it is fault-free. Faults may occur during manufacturing or over time as a result of wearout. Testing of the circuit results in a fault coverage ratio that represents the ratio of faults that can be detected to all faults which are taken into consideration, expressed as a percentage. Fault coverage values range between an ideal value of 100%, where all faults are detected, to 0% where no faults are detected during testing. Test patterns (test vectors) are used to stimulate the primary inputs of a circuit in order to detect the occurrence of faults at the output.
Two commonly detected types of faults are structural faults and timing faults. Structural faults represent a physical defect in the circuit. Stuck-at fault models are widely used to detect structural faults which result in very high fault coverage, e.g. greater than 99%. Stuck-at faults are tested by applying a test pattern (test vector) that, in a fault-free circuit, drives the particular node to generate an output response opposite to that which it would be if the circuit is faulty. As the complexity and size of the circuit increases, the generation of the necessary test patterns to stimulate the circuit also becomes increasingly more complex. To solve this problem random test pattern generators, as for example a linear shift feedback register (LFSR), are used to excite the circuit.
Although it is relatively simple to generate test patterns for detecting faults in a combinational circuit, significantly more complex test vectors are required to detect faults in a sequential circuit because of the need to propagate known values from element to element over time. Sequential circuits are therefore typically converted into a scan-based design. There are basically two types of scan-based designs--full-scan (completely combinational), and partial-scan (partially combinational). In the full-scan design every flip-flop in the sequential circuit is isolated and replaced by a scan flip-flop with a multiplexor at its input built-in as a cell. The scan flip-flops are linked together to form a single scan chain or multiple scan chains. A partial- scan design differs from a full-scan design in that only a select number of flip-flops are replaced by scan flip-flops.
A partial-scan BIST architecture for detecting stuck-at faults in a sequential circuit is disclosed in U.S. Pat. No. 5,329,533, which is herein incorporated by reference. That patented BIST scheme for detecting stuck-at faults is implemented with scan to ameliorate the controllability and observability of a sequential circuit. Random test vectors generated using a linear feedback shift register (LFSR) are applied to the circuit-under-test (CUT) and the corresponding output responses are compressed using a multiple-input-signature-register (MISR) to obtain a signature. The entire test functionality is monitored by a separate BIST controller which is active only in the self-test mode.
Very large scale integrated (VLSI) circuits are also generally tested to detect, in addition to structural faults, the occurrence of timing or path-delay faults. Research and development in the area of path-delay faults is gaining importance as the speed of VLSI circuits continues to increase. Path-delay faults can arise from both manufacturing process parameter variations as well as spot defects in a circuit. Unlike stuck-at faults which require only a single test pattern to stimulate an input, the detection of a path-delay fault requires a set or pair of two test patterns (test vectors) in order to propagate a signal transition through a particular path. In particular, the two test vectors must be sufficiently independent of one another and applied to the circuit at consecutive clock cycles in order to activate a signal transition at the inputs of a circuit. Thus, detection of path-delay faults requires stricter justification and propagation conditions and, as a result, such faults are more difficult to detect using the random test vectors employed for stuck-at faults. Conventional test pattern generators for stuck-at faults are thus unsuitable for path-delay faults in which a correlation exists between successively generated test vectors. As a result, the partial scan-based BIST architecture disclosed in U.S. Pat. No. 5,329,533 for detecting stuck-at faults cannot be used to test for path-delay faults.
U.S. Pat. No. 5,422,891 discloses a BIST method and apparatus for detecting path-delay faults in a combinational circuit by altering the circuit topology. In particular, that invention provides a method whereby cut points are inserted into the circuit for diverting the input of hazardous nodes to an observation point. Outputs of the integrated circuit and at the observation point in response to a hazard free input pattern are processed to generated two signatures that are compared to predetermined correct reference signatures to identify a path-delay fault. The method and apparatus described in that patent, however, is only suitable for path-delay fault testing of combinational circuits which, unlike sequential circuits, have very little practical industrial use.
It is therefore desirable to develop a scan-based BIST architecture for detecting path-delay faults as well as stuck-at faults in a sequential circuit. Moreover, it is desirable to improve the fault coverage result for path-delay fault testing by selecting and inserting observation points into the CUT. of at least one of the scan flip-flops. Observation points are selected by performing path-delay fault testing for each path in a set of paths in the sequential circuit. Those paths which are activated but not detected are then identified. An activation frequency is calculated for each scan flip-flop based on the number of paths that are activated but not detected. Thus, a predetermined number of scan flip-flops having a highest activation frequency are selected as observation points. In order to reduce processing time, the set of paths may comprise only the critical paths in the circuit.
In accordance with the invention the scan-based BIST architecture includes a test pattern generator that produces a first test pattern and a second test pattern, and a controller connected to the test pattern generator for generating a clock signal and a scan mode signal. The controller sets the scan mode signal to zero at an active edge of a first clock cycle and applies the first test pattern to a targeted path of the circuit, switches the scan mode signal to one before an active edge of a second clock cycle, holds the scan mode signal to one for two clock cycles while the second test pattern is applied to the targeted path and circuit responses of the combinational portion to the first test pattern are latched into the scan flip-flop at the active edge of the second clock cycle, and latches the second test vector into the scan flip-flop at an active edge of a third clock cycle. The first, second and third clock cycles are consecutive clock cycles. In a preferred embodiment, the test pattern generator is a multiseed linear feedback shift register.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.
USPTO Backgrounds
USPTO Backgrounds