During routine use, integrated circuits (ICs) are exposed to varying levels of radiation. However, in some applications, an IC's single crystal silicon wafer is exposed to a level of radiation sufficient to induce a single or soft error failure, i.e., a radiation event. Such failures are initiated by the introduction of excess charge carriers (i.e., electrons) in the wafer's electrical device region upon exposure to the ionizing radiation. These failures can cause electronic devices to lock-up or reset, and could potentially lead to the recall of computer workstations or large scale disruptions in chips controlling router systems. Singe crystal silicon wafers have become more susceptible to such failures as the wafers and the electrical devices thereon have decreased in size, such as in sub-100 nm device technologies. Examples of electronic device applications that are increasingly sensitive to radiation-induced failures include logic, memory, and analog applications, including microprocessors, digital signal processors, microcontrollers, logic/ASIC, DRAM, SRAM, flash memory, and mixed signal devices.
More specifically, referring to FIG. 1, a radiation event is characterized by ionizing radiation 10, e.g., alpha particles or high energy neutrons, penetrating the silicon wafer surface 11 to generate excess charge carriers throughout the structure, including the device layer 12, the near-surface region 13, and the bulk region 14. The excess charge carriers, shown as “+” and “−” in FIG. 1, are generated along the ionizing radiation 10 path through the structure to a depth proportional to the energy of the ionizing radiation. These charge carriers can then migrate into the near-surface region 13 or, more importantly, into the device region 12 within a few pico-, nano-, or microseconds, which is represented in FIG. 1 by the dashed arrows. These excess charge carriers may alter the charge state of features such as junctions in device layer 12, thereby leading to electronic device failure. The failure may be temporary and recoverable, or permanent, resulting in damage to the device itself.
Both smaller electronic device dimensions and higher density of devices on a given structure increase a silicon structure's sensitivity to radiation-induced events. At smaller dimensions, the capacitance at electrical junctions decreases, thereby reducing the critical number of excess electrons necessary to alter the junction's electrical condition.
Several approaches have been developed to protect against radiation-induced failures. Solutions involving complex error detection and correction schemes are viable, but introduce greater complexity and higher cost to the wafer's production regarding both design and chip area. Such solutions may also slow the device's operation. Alternatively, protection schemes such as adding capacitors, resistors, or additional transistors to critical nodes may also be used, but present disadvantages related to circuit speed and increased chip area. Furthermore, silicon-on-insulator (SOI) wafers can significantly reduce susceptibility to such failures based on structural aspects of the wafer design, but they represent significant additional wafer cost as well as increased design and process complexity.
Conventional silicon polished and standard epitaxial wafers lack sufficient structural protection from ionizing radiation events. In fact, the commonly employed epitaxial wafer configuration of a p-doped epitaxial layer on a more highly-doped (i.e., p+) substrate actually promotes retention of charge carriers generated in the epitaxial layer within the epitaxial layer itself. Furthermore, as suggested above, employing an SOI wafer in place of a bulk polished wafer or epitaxial wafer is not always feasible based on their significantly increased cost as well as the requisite process and design modifications for integration in the wafer processing.
USPTO Backgrounds
USPTO Backgrounds