The copending application of Jacobs et al., Ser. No. 07/981,638, filed Nov. 25, 1992 hereby incorporated herein by reference, describes a DC-DC converter which uses a pair of FET switches, interconnected by a clamping capacitor, to drive a transformer. A pulse width modulator (PWM) causes the FET switches to conduct alternately and to switch when there is a low or possibly zero voltage across the FET switches. The zero-voltage switching results in high efficiency energy conversion, and the use of the external capacitance permits the circuit designer to reduce the rate at which drain-to-source voltages of either FET changes, thereby to reduce the level of conducted or radiated high-frequency electromagnetic wave interference (EMI) which may be undesirably generated by the circuit. The application also discusses how output voltage ripple can be reduced.
Circuit analysis shows that DC-DC converters of this type, which, because of the clamping capacitor, are referred to generally as "clamped mode" circuits, may be unstable if special care is not taken. Design to avoid instability typically results in a deteriorated transient response, output impedance and audio susceptibility. Accordingly, there is still a long-felt need in the industry for reliable, stable DC-DC converters having a high conversion efficiency, and good transient response, output impedance and audio susceptibility characteristics.
USPTO Backgrounds
USPTO Backgrounds