1. Field of the Invention
The present invention relates to a semiconductor memory device such as an IC card, a memory system, etc. including a plurality of semiconductor memory chips in a package.
2. Description of the Related Art
As a semiconductor memory device, there is widely known an EEPROM (Electrically Erasable Programmable Read Only Memory) chip which enables rewriting of data. With respect to large integration, particular attention is paid to a NAND-cell type EEPROM chip which configures a NAND cell by serially connecting a plurality of memory cells.
A memory device (chip) such as NAND-cell type EEPROM is generally initialized after a power-on sequence.
A memory chip such as NAND-cell type EEPROM comprises a large number of integrated memory cells. All memory cells are not fabricated normally during chip production. There is a high possibility of manufacturing defective memory cells. If just a single defective memory cell is included, that chip is determined to be defective and must be discarded. However, this method greatly increases manufacturing costs of memory chips.
As a solution, for example, the NAND-cell type EEPROM provides a spare block as a substitute for a defective memory cell. A block containing the defective memory cell is replaced by the spare block in units of blocks to normalize the memory chip containing the defective memory cell and increase the non-defective rate.
As an example of the above-mentioned memory chip initialization, a spare block is substituted for the block containing a defective memory cell. Another example is a voltage trimming operation for optimizing various voltages used inside a memory chip.
Normally, the initialization operation is set to a given period, e.g., several hundreds of microseconds after the power supply voltage reaches a value within a specified range at the power-on time. During the initialization period, the memory chip cannot be controlled from the outside.
Conventionally, a system that uses the memory chip measures the time for the initialization, determines the end of the initialization, and then controls the memory chip.
In this case, the system using the memory chip requires an extra operation of measuring the time, complicating the memory chip control.
As a solution for this problem, the memory chip generates a busy signal at the power-on time. The busy signal indicates the busy state for a period after the power supply-voltage reaches a value in the specified range and until the memory chip becomes controllable from the outside. Regarding the busy state output, for example, the NAND-cell type EEPROM conventionally has a capability of outputting the memory chip's busy state during operations of reading, writing, or erasing data. There have been used a method of determining the busy state by (A) outputting the busy state from a pad exclusively used for the busy state output or (B) outputting the busy state from an I/O pad immediately after a busy state output command is entered, and then a data output enable state takes effect.
Normally, systems or users use different methods of detecting the busy state. Convenience is improved by allowing the use of methods (A) and (B). Namely, both methods (A) and (B) are indispensable.
Conventionally, a package product mounted with a plurality of memory chips has been used for EEPROM, IC cards or memory systems containing memory chips such as EEPROM. A widely used method allows one package to include a plurality of memory chips for increasing the memory capacity of an IC card, memory system, etc. One example is a package product including a plurality of nonvolatile memory chips.
On the package product including a plurality of memory chips, a busy state must be detected at the power-on time until the chip initialization is complete for all nonvolatile memory chips in the package.
FIG. 1 is a block diagram schematically showing a conventional packaged memory device including a plurality of memory chips. The example here shows that two memory chips MC1 and MC2 are included. The memory chips MC1 and MC2 in a memory device 10 are supplied with a power supply voltage Vcc and a ground voltage GND. Busy state output pads for the memory chips M1 and MC2 are commonly connected to a busy state output terminal 11. The output terminal 11 is connected to a node for the power supply voltage Vcc via a load resistor 12. I/O pads of the memory chips MC1 and MC2 are connected to an I/O terminal 13. The I/O terminal 13 is connected to an I/O bus 14.
The output terminal 11 generates a busy signal /BusyA causing an “L” level when at least one of memory chips MC1 and MC2 is busy. A slash (/) for /BusyA indicates an inverted signal.
When a busy state output command is entered to the memory device 10, the I/O terminal 13 outputs busy signal /Busy1 or /Busy2. This busy signal causes an “L” level when the corresponding memory chip is busy.
A package product containing a plurality of memory chips requires a busy state to be output until all memory chips in the package have been initialized after the power is turned on. Accordingly, busy states must be output from all the memory chips in the package. Each memory chip outputs a signal representing the busy state via the I/O pad and the I/O terminal 13.
Generally, an output time width for the busy signal at the power-on time depends on chips and therefore differs among chips. When one chip is busy, another may be ready, i.e., not busy.
FIG. 2 is a timing chart showing an example of operations after the power is turned on until each chip becomes ready to be controlled externally on the conventional memory device as shown in FIG. 1. When the power is turned on and the power supply voltage exceeds a specified value, an initialization operation starts in each of the memory chips MC1 and MC2. The period of this initialization is indicated with an “H” level. For example, let us assume that the memory chip. MC2 requires a longer time for initialization than the memory chip MC1.
After the initialization starts, the memory chips MC1 and MC2 output busy signals /Busy1 and /Busy2 indicative of the busy state via the I/O terminal 13. The “L” levels of the busy signal /Busy1 and /Busy2 correspond to the busy state. The busy state is released when the initialization for each chip is complete. The busy signal /Busy2 becomes ready after /Busy1. Namely, there is caused a different logical level state (TX in FIG. 2) between the busy signals /Busy1 and /Busy2. During the TX period, the busy signal /Busy1 output from the memory chip MC1 maintains the “H” level. The busy signal /Busy2 output from the memory chip MC2 maintains the “L” level. When the busy state output command is entered to the memory device 10 during the TX period, then busy signals /Busy1 and /Busy2 are output from the memory chips MC1 and MC2, a short circuit occurs between the power supply voltage Vcc and the ground voltage GND via the memory chips MC1 and MC2. This short circuit may cause the chip to malfunction due to the raised ground voltage level or lowered supply voltage level in each chip. Each chip is generally set to cause a large amount of output current to flow from the I/O pad. A large amount of current may flow between chips via the I/O bus 14, causing a possibility of destroying the device itself.
USPTO Backgrounds
USPTO Backgrounds