This application claims the priority of Korean Patent Application No. 2002-84082, filed on Dec. 26, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an apparatus and method for driving a display panel. More particularly, the present invention relates to an apparatus and method for easily generating a programmable signal to drive a digital display panel without re-designing a drive signal generating apparatus according to the specifications of the digital display panel including its size, the number of scan lines, and types of input signals.
2. Description of the Related Art
Digital display devices are classified into plasma display panels (PDPs), ferroelectric liquid crystal panels (FLCs), and the like.
In general, the PDPs are next generation flat display devices which display characters or images using plasma generated by discharging gas. Several hundreds of thousands to several millions of pixels are arranged in the PDPs in the matrix form according to their sizes.
FIG. 1 shows a PDP driving circuit to which the present invention is applied.
A drive sequence of a PDP is divided into a reset period, an address period, and a sustain period. In the reset period, display hysteresis is erased by discharging all cells and eliminating wall charges from the cells. In the address period, a discharge cell is selected by making a matrix configuration from combinations of column and row electrodes of the PDP to form an address discharge. In the sustain period, the discharge cell formed in the address period is iteratively charged and/or discharged using an energy recovery process to display an image.
The PDP driving circuit determines timings to switch various switches on and off based on an Address Display Separation (ADS) method in order to display an image. As shown in FIG. 1, Ys, Yg, Xs, and Xg denote sustain switches to apply a high-frequency alternating current (AC) pulsed-voltage to the PDP for a sustain period of the PDP. A pair of switches Ys and Xg and a pair of switches Xs and Yg are alternately switched on and/or off for the sustain period. Yr, Yf, Xr, and Xf denote switches of an energy recovery circuit which reduces power consumption by preventing fluctuations in a panel voltage and a capacitive displacement current for the sustain period. LY and LX denote inductors to recover energy. C_Yerc and C_Xerc denote capacitors, D_Yr, D_Xf, D_Xr, D_Xf, D_YvsC, and D_YGC denote diodes. The capacitors C_Yerc and C_Xerc and the diodes D_Yr, D_Xr, D_Xf, D-YvsC, and D_YGC are components necessary for the energy recovery circuit suggested by Weber et al. (U.S. Pat. No. 4,866,349). In general, sustain switches, energy recovery switches, and passive devices are incorporated into a circuit network which is called a “sustain circuit”. According to the ADS method, the sustain circuit operates for the sustain period of the PDP. Yp denotes a switch which is used to separate the address and reset circuits from the sustain circuit. Yrr, Yfr, and Xrr denote switches which are used to apply lamp type high voltages to the PDP for the reset period. That is, the switches Yrr, Yfr, and Xrr operate together with capacitors Cset and C_Xsink to apply higher voltages than a power voltage to the PDP for the reset period. Ysc and Ysp are switches which operate for the address period according to the ADS method. In particular, the switch Ysp is turned on and the switch Ysc is turned off for the address period, whereas the switch Ysp is turned off and the switch Ysc is turned on for the reset and sustain periods. A scan driver integrated circuit (IC) 100 includes a shift register and a voltage buffer, applies a horizontal synchronous signal to a screen of the PDP for the address period, and short-circuits for the reset and sustain periods. The detailed operation of an existing PDP driving circuit in compliance with a switching sequence is disclosed in U.S. Pat. No. 4,866,349.
Such a PDP driving circuit must apply X and Y drive signals suitable for types of input signals and the size of the PDP to each of the switches of FIG. 1 according to a drive sequence in order to generate X and Y electrode voltages as shown in FIG. 4 in each period.
As shown in FIG. 4, a PDP XY controller generally includes a counter 404 and a timing generating logic circuit 406. A horizontal synchronous signal H_Sync 401, a vertical synchronous signal V_sync 402, and a data enable signal Data_Enable 403 are applied to the counter 404. The time generating logic circuit 406 includes individual logic circuits and generates the X and Y drive signals so as to be suitable for the specifications of a PDP product such as its size, the number of scan lines, the number of pixels, and types of input video signals such as an NTSC video signal, a PAL video signal, etc.
Accordingly, as shown in FIG. 5, the PDP XY controller must be differently designed according to the size of the PDP. Also, as shown in FIG. 6, the PDP XY controller generates the X and Y drive signals so as to be suitable for the PDP driving circuit by selecting an NTSC XY controller 602-1 or a PAL XY controller 602-2 based on the type of an input video signal determined by a signal detector 601.
In summary, according to the related art, an XY controller must be differently designed according to the size of a PDP, the type of an input video signal, and so forth. Thus, components of the PDP are required to be re-designed whenever the specifications of the PDP are changed. As a result, developing PDPs becomes costly and time-consuming.
In addition, when a single PDP displays a plurality of types of video signals, X and Y drive signals should be changed according to the types of the video signals. Thus, the single PDP requires a plurality of XY controllers that can be appropriately switched. As a result, the volume of the single PDP increases.
USPTO Backgrounds
USPTO Backgrounds