1. Field of the Invention
Embodiments of the present invention generally relate to buffer memories. More particularly, this invention relates to shared buffer memories having hardware-based self-adjustment of the buffer regions.
2. Description of the Related Art
Transmitting data between processors and input/output devices has usually been performed by sending data in parallel according to a predetermined specification, e.g., the PCI (Peripheral Component Interconnect) bus architecture. However, because of market demands for increased data transmission rates the speed limitations of parallel data transmission have become apparent. Because of such limitations the use of serial data transmissions, e.g. the InfiniBand architecture, has begun replacing parallel data transmission architectures in applications such as high-end servers.
Conceptually, serial data transmissions send data serially, bit by bit. However, high performance serial data transmission architectures, e.g. InfiniBand, typically use multiple data virtual lanes (channels) that enable fast data transmission rates. InfiniBand virtual lanes are formed by connecting host channel adapters (HCAs), which are I/O engines within a server, and target channel adapters (TCAs), which are external I/O engines, together through InfiniBand switches. Each HCA and TCA can support up to 16 virtual lanes (VLs). The InfiniBand interconnection scheme is called a fabric. Because of its speed and multiple VLs the InfiniBand architecture can support tens of thousands of nodes in a single subnet at transmission rates of 2.5 GBps and beyond on copper wire (up to 17 meters) and on fiber optic cables (up to 10 km).
The InfiniBand specification requires sufficient buffer space for each virtual lane to store a full maximum transfer unit (MTU), with an MTU being the maximum data packet size in the InfiniBand fabric. However, that buffer space requirement represents a minimum and additional buffer space can improve system performance. Thus, large buffer spaces are beneficial.
Because large memories have performance and cost advantages over numerous smaller memories it is highly advantageous to use a reduced number, ideally one, of buffer memory devices in an InfiniBand channel adaptor (either HCA or TCA). Thus, a large, shared buffer memory dimensioned to have at least the minimum required buffer space for each virtual lane is beneficial. To improve performance, additional buffer space for the virtual lanes is desirable. Simply adding additional memory for each VL can radically increase the size and cost of the shared buffer memory. Since some virtual lanes seldom can make use of more than their minimum required buffer space, allocating such virtual lanes more buffer space is a waste. Yet other virtual lanes can dramatically benefit from increased buffer space. Therefore a method of dynamically increasing the sizes of the buffer spaces for the virtual lanes that can benefit from an increased buffer space would be useful.
Shared buffer memories are well-known. Software control of buffer space dimensions has benefited numerous applications. Unfortunately, it is difficult to design and to implement software configured buffer spaces that accommodate different and varying traffic loads as can occur in the InfiniBand fabric. Very often, even if software-configured buffer spaces are available those buffer spacers are either not configured or are poorly configured because the controlling software does not understand the nature of the system, its particular applications, and changes in buffer space demands sufficiently well to allocate appropriate buffer space sizes. This can cause performance degradation when a large part of the buffer memory is unused.
Compounding the problem of software controlling buffer space dimensions is that the same buffer memory chip can be used in very different ways in very different applications. In view of the economic and performance demands of large buffer memories and the limitations of software controlled buffer spaces, a buffer memory having hardware controlled buffer space dimensions and in which the hardware adjusts the buffer space dimensions to meet the demands of a particular system would be useful.
USPTO Backgrounds
USPTO Backgrounds