1. Technical Field of the Invention
The invention relates generally to de-serialization of serial data streams; and, more particularly, it relates to digital signal processing based de-serialization.
2. Description of Related Art
A conventional trend within communications technologies towards trying to achieve higher and higher operating rates has largely been geared towards employing wide parallel bus architectures. These implementations inherently consume a great deal of real estate. In chip-to-chip applications, one of the greatest consumers of real estate includes the wide parallel interconnections themselves that enable the communication and interconnection between the various devices. The constant increases in complexity and speed of digital hardware has turned the problems of interconnecting components increasingly difficult in contexts such as chip-to-chip, connections between multiple circuit boards across back planes, and other connections having a need for high speed communication while also being constrained by real estate and space.
Moreover, aside from the higher data rates desired in the industry, as the complexity of chips continues to increase, there is also commonly an associated requirement to provide a larger number of interconnections. Again, to ensure higher data communication rates, there is often the trend towards providing broad bus width interconnections between the devices.
One conventional approach to arrive at these high communication rates while also trying to address the design considerations of conserving space and real estate is to employ high-speed serial interconnections. A single high-speed serial interconnection may replace a large number of lower speed interconnections. As a result, a high-speed serial interconnection is largely more space and real estate conserving than parallel type interconnections. For this reason, many industries, including the computer and communications industries, have begun the use of high-speed serial transceivers for many applications including chip-to-chip and board-to-board applications. These transceivers, that may be referred to as SERDES (serializer-de-serializer) run at speeds of several hundred Mega-bits per second (Mb/s) to Giga-bits per second (Gb/s). Some products recently introduced run at data rates of 3.125 Gb/s. These SERDES interconnections are commonly implemented using analog based technology. All of the modulation/demodulation in these conventional SERDES is performed in the analog domain. A most common approach to modulation is to perform the modulation/demodulation using baseband signal processing.
However, these conventional developments fail to provide designs that operate at rates sufficiently high for many customer needs and desires. As the data rates increase, the impairments of the transmission medium become more and more important. For example, in the case of a micro-strip transmission line in a printed circuit (PC) board, dispersion (caused by the bandwidth limitations of the transmission line) causes inter-symbol interference (ISI); discontinuities in the transmission line cause reflections which also result in ISI; capacitive coupling between neighboring traces on the PC board causes crosstalk, and other deficiencies as well. Advanced signal processing techniques such as equalization and crosstalk cancellation have been applied for several decades to control similar impairments in communications systems such as voice-band modems, transceivers for the digital subscriber loop, Ethernet transceivers, and so on. However, with the only exception of the most straightforward situations, these techniques are too complex to be implemented using analog circuit design.
In addition, the analog implementation of SERDES may not be easily scaled to integrated circuit (IC) manufacturing technology of smaller dimensions. For example, a recent trend in Complementary Metal Oxide Semiconductor (CMOS) technology has been from a minimum feature size of 0.18 μm to 0.13 μm. Design engineers find the analog implementation of analog based SERDES extremely difficult. As the processing dimensions continue to decrease this situation will only get worse. The inherent non-scalability of analog based SERDES is a major limitation of the existing SERDES art.
The inability of analog based SERDES technology to enable advanced modulation, error correction and signal processing creates a situation where the fundamental limits of data rate that may be supported in backplane interconnections and other SERDES applications may never fully be realized. An analog based SERDES simply does not offer enough capabilities to enable such high data transfer rates.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the invention as set forth in the remainder of the present application with reference to the drawings.
USPTO Backgrounds
USPTO Backgrounds