Flash memory is a type of a non-volatile memory in which data can be stored even when power is turned off. Flash memory is typically made up of an array of floating gate transistors, commonly referred to as memory “cells.” One or more bits of data are stored as charge by each memory cell. The flash memory can be electrically programmed and erased and does not need a refresh function of rewriting data at regular intervals. The term “program” refers to the operation of programming data into the memory cells and the term “erase” refers to the operation of erasing data from the memory cells. The flash memory device can be mainly classified into a NOR flash memory device and a NAND flash memory device depending on the structure of the cell and operation conditions. In the NOR flash memory device, the source of each memory cell transistor is connected to the ground terminal (VSS) to enable program and erase functions for a predetermined address. Accordingly, the NOR flash memory has been mainly used for application fields requiring the high-speed operation. On the other hand, in the NAND flash memory, a plurality of memory cells are connected in series to form one string. One string is connected to the source and drain. The NAND flash memory has been mainly used for high integration data retention related fields.
In the flash memory, bit lines are typically formed in the portion of the semiconductor substrate that is below the charge trapping structure and word lines may be formed from the layer of electrically conductive material that is disposed on the charge trapping structure. This arrangement enables flash memory cells to be manufactured efficiently and economically. Various semiconductor fabrication processes use masks to help align the memory cells. Aligning the cells produces a more organized and compact design. Although masking techniques properly align the cells, scaling becomes an issue. It becomes harder to place the cells closer together. It is important to place the cells as close together without impacting their functionality because denser cells can hold more data for a given semiconductor area. In other words, tighter tolerances allow for greater memory capacity at reduced cost.
Another issue unavoidably arises as denser cells are fabricated. For example, much denser word line array with tiny pitch of the flash memory is hard to fabricate and inspect. FIG. 1 shows a schematic view of word line array of NAND flash memory. As the pitch between adjacent word lines decreases, the probability of present of short and open defects as well as the difficulty of detect the defects also increases. Therefore, there is a need for identify and detect defects present in word line array with dense pitch
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