The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Nowadays, errors occurring in a device's memory may be the biggest contributor to device crashes, hangs and/or data corruption. Memory integrity protection solutions, such as Reliability, Availability, and Serviceability (RAS) technologies have been developed to help bring the device memory vulnerability down to an almost negligible level. These measures include techniques aimed at predicting and correcting, when possible, multi-bit errors occurring in memory due to hard faults, wear-out, and the like. However, these solutions may typically require massive investments of resources necessary to provide adequate performance and power. Accordingly, such solutions may be mainly employed for mission-critical devices, e.g., high end servers for cloud computing, due to their high costs.
USPTO Backgrounds
USPTO Backgrounds