1. Field of the Invention
The invention relates to a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device in accordance with the prior art will be described with reference to FIG. 2. FIG. 2 shows a schematic partial view of a packaged semiconductor memory device.
An incoming data signal DQ is transferred via a pin 1 on the package to the pad 2 of the semiconductor memory device 3. An input receiver 4 provided on the semiconductor memory device 3 amplifies the incoming signal and outputs this to a flip-flop 5. A similar construction is provided for the data clock signals DQS in the semiconductor memory device 3. In this case, the output signal of the input receiver 4 for the data clock signal DQS serves as a clock signal for the flip-flop 5. The internal data signal DQint output by the flip-flop 5 is processed further in the semiconductor memory device 3.
Testing such a semiconductor memory device typically involves, inter alia, also checking the accuracy of the interface timing, and in particular the so-called setup time and hold time. When a semiconductor memory device is operated or tested at high frequency, e.g. with a clock frequency of more than 500 MHz, however, it becomes increasingly more difficult to check the accuracy of the interface timing since it is necessary to use test devices which can generate such high clock frequencies with a high accuracy and can also measure frequencies with a high accuracy.
Consequently, what is needed is a semiconductor memory device which enables simpler and more cost-effective testing of the semiconductor memory device in particular at high clock frequencies.
USPTO Backgrounds
USPTO Backgrounds