There continues to be a demand for more densely formed integrated circuits. One approach has been to reduce the physical scale of the circuit components so more can be formed within a given lateral area of a chip. Another approach is to vertically integrate two or more chips, each having semiconductor devices and interconnect wiring (e.g., integrated circuitry) using three-dimensional (3D) chip-to-chip stacking technology that bonds chip to chip, chip to wafer, or wafer to wafer. 3D stacking enables a greater density of integrated active circuits, enhanced performance, and improved form factors, among other gains. At present, there are many applications for 3D stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, among others.
Such 3D structures employ through-substrate vias (TSVs) to provide electrical connection to or among the devices and integrated circuitry formed on the multiple semiconductor substrate layers. For example, a 3D structure will have at least a lower chip separating the external connection (packaging) and an upper chip. Power for the devices of the upper chip can be delivered by a TSV through the lower chip.
A TSV preferably has high conductivity while consuming a minimum of area on the substrate surface, since such area could otherwise be used for additional functionality such as added logic or memory. By this measure, the area consumed by a TSV should be no more than an area sufficient to handle the design current load, that is, able to avoid electromigration effects, overheating and/or voltage drops. If such minimum area were circular, the diameter of the area could be referred to as the “current minimum dimension”. A TSV's axis is typically substantially normal to the planar orientation of the chip. By virtue of extending through the depth of a chip, a TSV's length is approximately the chip thickness, which can be orders of magnitude longer than a typical interconnect via which only extends through at most a few of the back-end-of-the-line (BEOL) interconnect layers. In other words, the TSV aspect ratio of length vs. the ‘current minimum dimension’ can be very high.
Copper's high conductivity can make it a preferable material for TSVs, but process challenges such as forming sufficiently uniform liner, barrier and/or seed layers, and/or conductively filling the TSV, effectively limit copper features to moderate aspect ratios. For a given depth through the substrate, the TSV width must generally be increased above the current minimum dimension to maintain a moderate aspect ratio. The relatively massive resulting copper TSV presents further integration and reliability challenges including CTE mismatch and wafer bowing. Higher aspect ratio features can be formed with tungsten, but tungsten has lower conductivity. For an equivalent current capacity, a tungsten TSV must have a greater cross section than a copper TSV, either as a single wider TSV, or as a set of narrow TSVs.
USPTO Backgrounds
USPTO Backgrounds