In the past, there has been known Symmetric MultiProcessor (SMP) technology, in which a plurality of arithmetic processing units share a main storage unit. As one example of an information processing system to which such SMP technology is applied, there is an information processing system in which a plurality of nodes including an arithmetic processing unit and a main storage unit are connected to the same bus, and each arithmetic processing unit shares each main storage unit through the bus.
Such an information processing system retains coherency of data cached by the arithmetic processing unit of each node by using, for example, a snoop scheme.
Also, in a system that uses a shared memory as a data communication unit between nodes, there is technology in which when an abnormality of a node is detected, data to be transmitted is converted into data representing the abnormality and the converted data is transmitted. In this technology, a node receiving the data representing the abnormality discards the received data.
Also, in a system in which a plurality of nodes are connected by a crossbar switch, there is technology in which when the retention of packet communication occurs, processing is continued by changing a communication path. In this technology, a request transmitted by a node is transmitted from the crossbar switch to its own node and other node. In this technology, the node transmitting the request measures time from the transmission of the request to reception of the request, detects a time-out, and determines that the retention of the packet communication has occurred.
Also, in a system in which a plurality of nodes are connected by a crossbar switch, there is technology in which in the case where data transmitted from a node is interrupted, when the interruption time is equal to or longer than a predetermined time, dummy data including data representing abnormality is transmitted to a node of a receiving side.    Patent Literature 1: Japanese Laid-open Patent Publication No. 2004-013723    Patent Literature 2: Japanese Laid-open Patent Publication No. 2002-366451    Patent Literature 3: Japanese Laid-open Patent Publication No. 11-168502
However, the above-described technology has a problem that does not suppress an error influence range when abnormality related to data transmission between nodes occurs.
For example, in the information processing system that retains coherency of cached data by using a snoop scheme, the following may be considered. That is, when failure occurs in a certain node (node is shut down) and communication abnormality occurs between nodes, it may be considered to bring all nodes down to retain the coherency of the cached data. In this case, an error influence range reaches all nodes.
USPTO Backgrounds
USPTO Backgrounds