The present invention relates generally to integrated circuit (IC) device testing techniques and, more particularly, to an apparatus and method for implementing improved test controllability and observability of random resistant logic.
The testing of integrated circuits has evolved into a highly developed area of technology. Generally, such testing may be implemented through the use of external equipment, Built-In Self-Test (BIST) circuitry, or a combination of the two. Typically, all test methodologies involve shifting data into scannable memory elements of an integrated circuit device (e.g., Level Sensitive Scan Design or LSSD latches), capturing the input to the memory elements, shifting the captured data out and then comparing the captured data with predetermined values to determine whether the circuit has performed according to design. Automatic test pattern generation (ATPG) systems use tools for testing digital circuits after the circuits have been manufactured. In general, an ATPG tool generates a set of test vectors that are applied to a circuit under test. The output of the circuit is analyzed to identify logic faults in the circuit design (i.e., “functional testing”), as well as detecting fabrication defects (i.e., “structural testing”).
Although it is desirable when testing the logic circuitry to use deterministic testing by checking the circuit output response to all 2n possible input permutations, this approach becomes impractical as the number of input variables n and the size of the pattern set increases. Thus, a related technique, referred to as pseudo-random testing, is employed when the number of input variables is so large that it becomes impractical to use an exhaustive testing approach. Pseudo-random testing is an alternative technique that generates test patterns in a random fashion from the 2n possible patterns. In this approach, fewer than all of the 2n patterns are tested. Because of the relatively low hardware overhead and the simplicity of test pattern generation, pseudo-random testing is a preferred technique for BIST. Practical circuits, however, often contain random pattern resistant faults which result in unacceptable low fault coverages and low circuit excitation for a reasonable test length.
Test patterns are typically graded against a fault model (e.g., the stuck-at-fault model). With pseudo-random data, certain random resistant structures are difficult to test. One example of such a “random pattern resistant” or “random resistant” logic circuit is a compare circuit that compares the contents of a first register to the contents of a second register. Because the sizes of the registers to be compared can be several bits in length (e.g., 24 bits or even 80 bits or more), it is virtually assured from a statistical standpoint that the random bits generated and loaded into the first register will not exactly match the random bits generated and loaded into the second register. Thus, the compare circuit will almost always be tested in a mismatch condition with a conventional scan chain-based BIST design, even though a test of a match condition is equally (if not more) important. In addition, a “near match” condition (e.g., where only 1 of 24 bits is mismatched) is also desired test condition. Again, however, the statistical probabilities associated with achieving such a randomly generated data type make random pattern testing of this nature problematic at best. Because compare logic is often found in the most critical of timing paths in IC designs, the quality testing of such logic structures (so as to enable the detection of small delay defects) is a significant concern.
A known technique in Design for Test (DFT) methodology is to run an analysis tool that identifies random resistant logic. In this regard, there are several commercially available products that perform this function. The output of such random resistant analysis tools is a list of recommended test points, at which a latch or other type of memory element (e.g., flip-flop) is to be added to the design in order to serve as either a control point or an observation point. Some tools may actually insert the recommended structure at the control/observation point for the user. Although the additional hardware addresses a testability problem, it also impacts the circuit design in several ways, such as with respect to timing, power consumption and device area, for example.
While other methods exist for understanding and addressing the random testability of circuit designs, in the end such solutions ultimately involve adding latches or, at a minimum, are restricted to using a latch output as a control point. It is recognized that the input and output pins of a chip may, in theory, be used as observation points, but this quickly becomes impractical given the number of test points and the limited availability of chip input/output (I/O). As a practical matter, therefore, the choice of control or observation points is essentially limited to the input or output of a latch.
Modifications to a circuit design that add control/observation latches are implemented late in the design stage such that the latches and fan-in/fan-out connections are not implement in the most efficient manner. Either more latches are added than are necessary, or a solution is implemented which adds unnecessary delay or which adversely affects the design. In certain cases, no changes are made, thereby resulting in a design with reduced random testability where the penalty for adding one or more latches is too great (e.g., unacceptable timing). Accordingly, it would be desirable to be able to improve the random testability of circuit designs, but in a manner that minimizes adverse impacts to the circuit design, such as those described above.
USPTO Backgrounds
USPTO Backgrounds