1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor integrated circuit having a stacked package structure and a semiconductor system with the same.
2. Description of the Related Art
In general, packaging technologies for semiconductor integrated circuits have continuously been advanced to meet demand for miniaturization and packaging reliability. Various technologies for stacked packages have recently been developed to meet demand for not only miniaturization but also high performance of electric/electronic products.
“Stacking” in the field of semiconductor device means piling at least two semiconductor chips or packages to be arranged in three dimensions. For example, the stacked package allows the semiconductor memory devices may to have a memory density per unit area that is twice or more than two dimensionally packaged memory devices without change of semiconductor integration processes. Advantages of the stacked package such as the density and size efficiency have triggered studies and developments of the stacked packages.
There are two types of stacked packages. First type is individual semiconductor chips to be packaged after stacking, and second type is one of individually packaged semiconductor chips. The individual semiconductor chips of the stacked package are coupled via metal wires, through-chip vias, or the like. In particular, the stacked package using a through-chip via, which will be noted as a through-silicon via (TSV) in the Figures and the specification, has a configuration in which the through-chip vias are formed in each of the semiconductor chips to couple the three-dimensionally stacked semiconductor chips physically and electrically.
FIG. 1 is an exemplary diagram illustrating the configuration of a semiconductor integrated circuit according to a related art.
Referring to FIG. 1, the semiconductor integrated circuit 100 includes first to fourth semiconductor chips 110 to 140 configured to be vertically stacked, first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33 configured to vertically penetrate the first to fourth semiconductor chips 110 to 140 respectively, first to fourth groups of bump pads BP00 to BP03, BP10 to BP13, BP20 to BP23, and BP30 to BP33 configured to be provided in lower portions of the first to the fourth semiconductor chips 110 to 140 and to couple the first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33 between the first to fourth semiconductor chips 110 to 140. The first to fourth semiconductor chips 110 to 140 include first to fourth groups of internal circuits 111 to 117, 121 to 127, 131 to 137, and 141 to 147 coupled to each of the first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33, respectively.
Here, through-chip vias in each group of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, or TSV30 to TSV33 are configured to be aligned in line and to be vertically coupled to each other between the first to fourth semiconductor chips 110 to 140. That is, the through-chip vias of the first group TSV00 to TSV03 are vertically coupled, the through-chip vias of the second group TSV10 to TSV13 are vertically coupled, the through-chip vias of the third group TSV20 to TSV23 are vertically coupled, and the through-chip vias of the fourth group TSV30 to TSV33 are vertically coupled.
The first to fourth internal circuits 111 to 117, 121 to 127, 131 to 137, and 141 to 147 may include input/output circuits.
The semiconductor integrated circuit 100 having the above-described configuration has the advantage that a total memory density increases, as the number of stacked semiconductor chips increases.
In the semiconductor integrated circuit 100 having the above-described configuration, however, through-chip vias in each group TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, or TSV30 to TSV33 share a common coupling node. Therefore, it is impossible to read the first to fourth semiconductor chips 110 to 140 simultaneously. Accordingly, it is impossible to increase bandwidth of the semiconductor integrated circuit with fixed number of through-chip vias regardless of increase of the number of stacked semiconductor chips. Increasing the number of through-chip vias for wider bandwidth of the semiconductor integrated circuit leads more space for the internal circuits for the increased number of through-chip vias, thereby increasing a size of the semiconductor chip.
FIG. 2 is an exemplary diagram illustrating the configuration of a semiconductor integrated circuit according to another related art.
Referring to FIG. 2, the semiconductor integrated circuit 200 includes first to fourth semiconductor chips 210 to 240 configured to be vertically stacked, first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33 configured to vertically penetrate the first to fourth semiconductor chips 210 to 240, respectively, first to fourth groups of bump pads BP00 to BP03, BP10 to BP13, BP20 to BP23, and BP30 to BP33 configured to be provided in lower portions of the first to the fourth semiconductor chips 210 to 240 and to couple the first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33 between the first to fourth semiconductor chips 210 to 240. The first to fourth semiconductor chips 210 to 240 include internal circuits 211, 221, 231, and 241 coupled to at least one of the first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33, respectively.
Here, through-chip vias in each group of the first to fourth groups of through-chip vias TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23, and TSV30 to TSV33 are configured to be aligned in line and to be coupled to through-chip vias in another group across the semiconductor chip. That is, the through-chip vias of the first group TSV00 to TSV02, except for the through-chip via TSV03 of the uppermost semiconductor chip 240, are coupled to the through-chip vias of the second group TSV11 to TSV13 of the above-stacked semiconductor chip, respectively. The through-chip vias of the second group TSV10 to TSV12, except for the through-chip via TSV13 of the uppermost semiconductor chip 240, are coupled to the through-chip vias of the third group TSV21 to TSV23 of the above-stacked semiconductor chip, respectively. The through-chip vias of the third group TSV20 to TSV22, except for the through-chip via TSV23 of the uppermost semiconductor chip 240, are coupled to the through-chip vias of the fourth group TSV31 to TSV33 of the above-stacked semiconductor chip, respectively. The through-chip vias of the fourth group TSV30 to TSV32, except for the through-chip via TSV33 of the uppermost semiconductor chip 240, are coupled to the through-chip vias of the first group TSV00 to TSV02 of the above-stacked semiconductor chip, respectively.
The internal circuits 211, 221, 231, and 241 may include input/output circuits.
The semiconductor integrated circuit 200 having the above-described configuration has the advantages in that the number of internal circuits 211, 221, 231, and 241 respectively included in the semiconductor chips may be minimized, and it is possible to simultaneously input to and output from the first to fourth semiconductor chips 210 to 240, and thus to widen the bandwidth of the semiconductor integrated circuit with fixed number of through-chip vias.
In the semiconductor integrated circuit 200 having the above-described configuration, however, it is only one semiconductor chip that is coupled per through-chip via, which limits increase of the memory density per through-chip via. In other words, only one through-chip via is involved in data input and output in one semiconductor chip. Therefore, it may be impossible to increase the memory density per through-chip via with fixed number of through-chip vias regardless of increase of the number of stacked semiconductor chips.
USPTO Backgrounds
USPTO Backgrounds