1. Field of the Invention
The invention relates to a passivation structure and a fabricating method thereof, and more particularly, to a method for fabricating the passivation structure and openings therein by two separate steps.
2. Description of the Prior Art
Manufacturing of integrated circuits includes a large number of precise and complicated processes such as semiconductor processes for forming devices on wafers; and metal interconnection processes for forming interconnection layers composed of metal layers and inter-metal dielectric (IMD) layers. These interconnection layers electrically connect nodes of the semiconductor devices, e.g. gate and source/drain, to pad layers that serve as I/O terminals disposed above the topmost interconnection layer. Normally, the pad layer is protected from water, scratches and other contamination by a passivation layer.
In some particular applications such as the finger printer, the passivation layer is required not only to provide effective protection against water, scratches and other contamination, but also to provide endurance for pressure from fingers, salinity from the environment, and electrostatic discharge (ESD). To satisfy those requirements, the prior art has rendered rigid dielectric material such as SiN to form the passivation layer. It is well-known that the mechanical strength of a layer is proportional to the cube of its thickness while the passivation layer is further required to sustain a test voltage of tens of thousands of Volts and ESD, thus the passivation layer is made much thicker in the prior art to improve its endurance to pressure, scratches, and ESD.
Please refer to FIGS. 1-2, which are cross-sectional views of a chip comprising a conventional thicker passivation layer. As shown in FIG. 1, a chip 100 having a main die region 102 and a scribe line region 104 defined thereon is provided; and the main die region 102 of the chip 100 includes a formed integrated circuit and a plurality of interconnection layers (both not shown). An IMD layer 110 is formed on the chip 100 and a plurality of metal pads 112 is formed on the IMD layer 110. The metal pads 112 positioned in the main die region 102 serve as I/O terminals while the metal pads 112 in the scribe line region 104 serve as test pads. A passivation layer 120 is then formed to cover the metal pads 112 on the chip 100, and followed by a photo-etching-process (PEP) for patterning the passivation layer 120, so that openings 122 respectively exposing the metal pads 112 in the main die region 102 and in the scribe line region 104 are formed.
Please refer to FIG. 2. Next, a passivation layer 130 which is thicker than conventional requirement in ordinary application is formed on the chip 100. Then another PEP utilizing the same mask used in the preceding PEP is performed to pattern the passivation layer 130, thus a plurality of openings 132 respectively corresponding to the openings 122 and consequently exposing the metal pad 112 are formed in the passivation layer 130. The exposed metal pads 112 are able to form metal wirings subsequently. However, it is observed that cracks always occur in the passivation layer 130 in the openings 132, particularly in corners of the openings 132. It is also observed that the cracks adversely influence endurance of the passivation layer 130 to the ESD.
Furthermore, please refer to FIG. 2 again. Conventionally, a deep trench is formed in the scribe line region 104 where no metal pads 112 are formed during patterning the passivation layer 120, thus the thickness in the scribe line region 104 is reduced and consequently prevents the main die region 102 from stress generated during the dicing. Nevertheless, a step height between the main die region 102 and the scribe line region 104 is unavoidably increased due to the formed thicker passivation layer 130. Therefore, alignment in the following process is deteriorated, and metal wirings 140 easily flow from the metal pad 112 in the main die region 102 to the openings 132 in the scribe line region 104 when forming gold bonds, bumps and even the wire bonding, and consequently cause short circuiting.
USPTO Backgrounds
USPTO Backgrounds