Recently, a stacked-type semiconductor memory device in which memory cells are three-dimensionally integrated has been proposed. In such a semiconductor memory device, a stacked body in which a plurality of electrode layers is stacked is provided, and a channel piercing the stacked body is provided. Further, a memory cell including a charge storage film is formed at each crossing portion between the electrode layer and the channel. For such a semiconductor memory device, an object is to improve an electrical characteristic of the memory cell.
USPTO Backgrounds
USPTO Backgrounds