1. Field of the Invention
The present invention is related to a shift register, and more particularly, to a bi-directional shift register for use in a liquid crystal display device.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, thin appearance and low power consumption, have gradually replaced traditional cathode ray tube display (CRT) devices and are widely used in electronic products such as notebook computers, personal digital assistants (PDAs), flat-panel TVs, or mobile phones. In a traditional LCD device, images are displayed by scanning the pixels of the panel using external driving chips. However, gate-on-array (GOA) technique has been developed in order to reduce the number of devices and manufacturing costs by fabricating driving circuits directly on the panel.
FIG. 1 is a simplified block diagram of a prior art LCD device 100. Partial structure of the LCD device 100 is illustrated, including a plurality of gate lines GL(1)-GL(N), a shift register 110, a clock generator 120, and a power supply 130. The clock generator 120 is configured to provide a start pulse signal VST and two clock signals CK1, CK2 for operating the shift register 110. The power supply 130 is configured to provide bias voltages VDD and VSS for operating the shift register 110.
The shift register 110 includes a plurality of shift register units SR(1)-SR(N) coupled in series and having output ends respectively coupled to the corresponding gate lines GL(1)-GL(N). According to the clock signals CK1, CK2 and the start pulse signal VST, the shift register 110 sequentially outputs gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) using the shift register units SR(1)-SR(N), respectively. In the prior art LCD device 100, each shift register unit includes an input circuit, a pull-up circuit, a first pull-down circuit, and a second pull-down circuit. The shift register 110 is a two-phase shift register in which the odd-numbered stages of the shift register units operate according to the clock signal CK1 and the even-numbered stages of the shift register units operate according to the clock signal CK2. The clock signals CK1 and CK2 periodically switch between an enable level and a disable level, and only one of the clock signals CK1 and CK2 is at enable level at the same time.
FIG. 2 is a diagram illustrating an nth stage shift register unit SR(n) among the plurality of shift register units SR(1)-SR(N) (assuming n is an odd integer between 1 and N). The prior art shift register unit SR(n) includes an output end OUT(n), a node Q(n), a pull-up circuit 15, an input circuit 25, a first pull-down circuit 35, and a second pull-down circuit 40. The shift register unit SR(n) is configured to output a gate driving signal GS(n) to a gate line GL(n).
The pull-up circuit 15 includes a transistor switch T9 having a control end coupled to the node Q(n), a first end coupled to the clock generator 120 for receiving the clock signal CK1, and a second end coupled to the output end OUT(n). The input circuit 25 includes a transistor switch T1 having a control end coupled to the output end of an (n−1)th stage shift register unit SR(n−1), a first end coupled to the power supply 130 for receiving the bias voltage VDD, and a second end coupled to the node Q(n). The first pull-down circuit 35 includes a transistor switch T5 having a control end coupled to the output end of an (n+1)th stage shift register unit SR(n+1), a first end coupled to the node Q(n), and a second end coupled to the power supply 130 for receiving the bias voltage VSS. Therefore, the input circuit 25 can maintain the level of the node Q(n) according to the (n−1)th stage gate driving signal GS(n−1), and the first pull-down circuit 35 can maintain the level of the node Q(n) according to the (n+1)th stage gate driving signal GS(n+1). When the level of the node Q(n) is higher than the turn-on voltage of the transistor switch T9, the clock signal CK1 may be transmitted to the output end OUT(n) via the conducting transistor switch T9 for supplying the gate driving signal GS(n). On the other hand, the second pull-down circuit 40 is configured to stabilize voltages at the output end OUT(n).
If the shift register 100 is configured to scan in a specific direction (such as scanning the gate lines GL(1)-GL(N) sequentially in a forward direction), the LCD device 100 fails to function normally in other driving modes (such as scanning the gate lines GL(N)-GL(1) sequentially in a reverse direction). In other words, the prior LCD device 100 only provides uni-directional scanning.
USPTO Backgrounds
USPTO Backgrounds