Fabrication of electronic circuits may be divided into two stages. In the first stage, active and passive devices are fabricated on the wafer surface. In the second stage, metal systems necessary to connect these devices are added to the chip. The various processes for connecting these component parts together are generally referred to as “metallization.”
The inventor hereof has recognized that, particularly in power and radio frequency (RF) semiconductor devices, the coefficient of thermal expansion (CTE) of the interconnect metal should closely match that of the underlying semiconductor material in order to avoid catastrophic metal failures due to the expansion from the intense heat that is generated during operation of such devices. However, the CTEs of gold (Au), aluminum (Al), Copper (Cu), Nickel (Ni), and platinum (Pt), which are commonly used as interconnect metals, do not match those of certain semiconductor materials, such as Silicon Carbide (SiC) and Gallium Nitride (GaN).
Moreover, the inventor hereof has also recognized that prior-art metallization processes frequently result in non-uniformity across the wafer and/or die, and that such processes are often subject to machine and operator errors which are inherent to prior-art etching methods.
USPTO Backgrounds
USPTO Backgrounds