This invention relates to insulated gate field effect transistor (IGFET) push-pull driver circuits and, more particularly, to an IGFET push-pull driver circuit in which the output current is accurately controlled by a current sensing feedback arrangement.
IGFET push-pull drivers are known in the art and are typically included in digital integrated circuits implemented in N-channel metal-oxide-semiconductor (NMOS), P-channel metal-oxide-semiconductor (PMOS), and complementary metal-oxide-semiconductor (CMOS) technologies. Such circuits are characterized by having a pull-up transistor connected between an output node and a VDD supply terminal and a pull-down transistor connected between the output node and a VSS supply terminal. Push-pull drivers are useful as output drivers particularly where the load to be driven is highly capacitive. The push-pull configuration allows high transconductance transistors to be used for rapid charging and discharging of the load without creating a power-consuming dc current path between the VDD and VSS power supplies. The push-pull configuration also permits operation in the so-called tri-state mode where a "third", high impedance, state can be provided at the output node by causing both the pull-up and pull-down transistors to be in their nonconducting state.
In many applications it is necessary to control the current output of a driver. One such application is where the IGFET driver circuit provides the input signal to an emitter coupled logic (ECL) gate. In order to avoid driving the input transistor of the ECL gate into saturation, the current from the output driver must be limited to some maximum value. Another application in which the output current from the IGFET driver must be limited is where several drivers provide the inputs for a current weighting network such as those found in the input stage of a digital-to-analog converter. Here, not only must the output current of each driver be limited, but the output current of each driver must be made substantially equal. However, the output current of a conventional IGFET push-pull driver is subject to large variations caused by normal processing variations of certain transistor parameters such as the threshold voltage (VT), and by variations in the device operating temperature. Therefore, conventional IGFET push-pull drivers are not suitable for many applications where the maximum output current must be accurately controlled.
One prior art technique for limiting the output current of an IGFET push-pull driver is to use a current limiting resistor between the VDD power supply terminal and the pull-up transistor. Circuit configurations using this technique have been disclosed in U.S. Pat. Nos. 3,651,340 and 3,906,255. However, such circuits have a shortcoming in that the output current, although limited by the resistor, is still dependent on the value of the current limiting resistor. Accurate control of the output current in such driver configurations would require the use of precise value resistors which would significantly increase the manufacturing cost of circuits in which they are used.
Another prior art technique for limiting the output current in an IGFET driver is to provide feedback control of the output voltage. Circuit configurations employing this technique have been disclosed in U.S. Pat. Nos. 4,065,678 and 4,096,398. Although the feedback technique would provide accurate control of the output voltage, the output current would, nevertheless, vary with variations in load impedance. Therefore, this technique is also deficient for applications where the input impedance of load circuits are subject to variations. Therefore, a need exists for an IGFET driver circuit which provides the advantages of a push-pull configuration while also providing accurate control of the maximum output current, notwithstanding variations in transistor parameters, operating temperature, and load impedance.
USPTO Backgrounds
USPTO Backgrounds