1. Field of the Invention
Embodiments of the present invention related to a semiconductor device.
2. Description of the Related Art
Silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltage and/or large current. There are several types of power semiconductor devices such as bipolar transistors, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), etc. These devices are selectively used according to an intended purpose.
For example, bipolar transistors and IGBTs have high current density compared to MOSFETs, and can be adapted for large current but cannot be switched at high speeds. In particular, the limit of switching frequency is about several kHz for bipolar transistors and about several tens of kHz for IGBTs. On the other hand, power MOSFETs have low current density compared to bipolar transistors and IGBTs, and are difficult to adapt for large current but can be switched at high speeds up to about several MHz.
However, there has been a strong demand in the market for a power semiconductor device that achieves both large current and high speed. Thus, IGBTs and power MOSFETs have been intensively developed and improved, and the performance of power devices has substantially reached the theoretical limit determined by the material. In terms of power semiconductor devices, semiconductor materials replacing silicon have been investigated and silicon carbide (SiC) has been focused on as a semiconductor material enabling production (manufacture) of a next-generation power semiconductor device having low ON voltage, high-speed characteristics, and high-temperature characteristics (see, for example, K. Shenai, et al, “Optimum Semiconductors for High-Power Electronics”, IEEE Transactions on Electron Devices, September 1989, Vol. 36, No. 9, pages 1811-1823).
Silicon carbide is chemically a very stable semiconductor material, has a wide bandgap of 3 eV, and can be used very stably as a semiconductor even at high temperatures. Silicon carbide has a critical electric field strength that is ten times that of silicon or greater, and is expected to be a semiconductor material that can sufficiently reduce ON-resistance. These merits of silicon carbide are common to all semiconductors having a wide bandgap greater than silicon (hereinafter, wide bandgap semiconductors), such as gallium nitride (GaN). Thus, a high-voltage semiconductor device can be achieved by using a wide bandgap semiconductor (see, for example, B. Jayant Baliga, “Silicon Carbide Power Devices”, U.S.A, World Scientific Publishing Co., Mar. 30, 2006, page 61).
A structure of a conventional semiconductor device will be described taking, as an example, an n-channel type MOSFET that has a planar gate structure and that is a switching device produced using silicon carbide. FIG. 9 is a perspective view of a structure of an active region of a conventional semiconductor device. As depicted in FIG. 9, in the conventional semiconductor device, on a front surface of an n+-type supporting substrate (hereinafter, n−-type SiC substrate) 101 including silicon carbide, an n−-type semiconductor layer (hereinafter, n−-type SiC layer) 102 including silicon carbide is provided. The n+-type SiC substrate 101 functions as a drain region. In a surface layer of the n−-type SiC layer 102, on a side of the n−-type SiC layer 102 opposite a side facing the n+-type SiC substrate 101, a p-type base region 103 is selectively provided. A portion of the n−-type SiC layer 102 other than the p-type base region 103 is a drift region.
On a surface of the n−-type SiC layer 102, on the side of the n−-type SiC layer 102 opposite the side facing the n+-type SiC substrate 101, a p-type semiconductor layer (hereinafter, p-type SiC layer) 104 including silicon carbide is stacked. In the p-type SiC layer 104, at a portion facing the p-type base region 103 in a depth direction, an n+-type source region 105 and a p+-type contact region 106 are each selectively provided. An n-type semiconductor region 107 is provided penetrating the p-type SiC layer 104 in the depth direction, reaching the n−-type SiC layer 102. The n-type semiconductor region 107 is arranged separate from the n+-type source region 105, on a side of the n+-type source region 105 opposite from a side facing the p+-type contact region 106.
A portion (hereinafter, second p-type base region) 104a of the p-type SiC layer 104 other than the n+-type source region 105, the p+-type contact region 106, and the n-type semiconductor region 107 functions as a base region together with a p-type base region (hereinafter, first p-type base region) 103. The n-type semiconductor region (hereinafter, n-type junction FET (JFET) region) 107 is a JFET region between adjacent base regions and functions as a drift region together with the n−-type SiC layer 102. An impurity concentration of the n-type JFET region 107 is higher than an impurity concentration of the n−-type SiC layer 102 whereby an n-type impurity concentration of a portion of the drift region between adjacent base regions is increased, facilitating reduction of JFET resistance.
On a surface of a portion of the second p-type base region 104a between the n+-type source region 105 and the n-type JFET region 107, a gate electrode 109 is provided from the n+-type source region 105 to the n-type JFET region 107 via a gate insulating film 108. The source electrode 110 is in contact with the n+-type source region 105 and the p+-type contact region 106, and is electrically insulated from the gate electrode 109 by an interlayer insulating film 111. In FIG. 9, to clearly depict the arrangement of the n+-type source region 105, the p+-type contact region 106, and the gate electrode 109, a portion of the source electrode 110 in the front in the drawing is not depicted. On the source electrode 110, a source electrode pad 112 is provided. On a rear surface of the n+-type SiC substrate 101, a drain electrode 113 is provided.
In the MOSFET of the configuration depicted in FIG. 9, when positive voltage with respect to the source electrode 110 is applied to the drain electrode 113 and voltage lower than a threshold voltage is applied to the gate electrode 109, a pn junction between the second p-type base region 104a and the n-type JFET region 107 becomes reversed biased, reverse breakdown voltage of the active region is established, and current does not flow. In contrast, when current equal to or greater than the threshold voltage is applied to the gate electrode 109, an n-type inversion layer (channel) is formed at a surface layer of a portion of the second p-type base region 104a directly beneath the gate electrode 109 (drain side). As a result of this, current flows through a path of the n+-type SiC substrate 101, the n−-type SiC layer 102, the n-type JFET region 107, the surface inversion layer of the second p-type base region 104, and the n+-type source region 105. In this manner, by controlling gate voltage, the widely known MOSFET switching operation may be performed.
Nonetheless, to take advantage of the characteristics of silicon carbide, even when silicon carbide is used and a MOS gate (insulated gate of a metal oxide film semiconductor) structure is formed as described above (refer to FIG. 9), channel mobility and the resistance of the n-type JFET region 107 (JFET resistance) cannot be increased and the ON resistance cannot be decreased. Therefore, to reduce the ON resistance, the channel resistance has to be reduced. As a semiconductor device for which the ON resistance has been reduced, a device has been proposed in which a width of the JFET region is set to be 0.8 μm to 3 μm and an impurity density of the JFET region is equal to or greater than an impurity density of the drift layer and set to be 1×1016/cm3 or greater (for example, refer to Japanese Laid-Open Patent Publication No. 2011-159797). In Japanese Laid-Open Patent Publication No. 2011-159797, the ON resistance is reduced by a structure that lowers channel resistance and JFET resistance.
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