1. Field of the Invention
The invention relates to mask read-only memory, and more particularly to mask read-only memory having flat-type bank select.
2. Description of the Prior Art
There are several read-only memory (ROM) cell structures are well known in application. One approach is referred to as the flat-type ROM design. With the requirement of better memory cell efficiency, the cell pitch and bank height become the key factor to be considered. While the memory cell is shrinking down, the contact size and metal pitch become the limit of it. On the other hand, memory array used to use LOCOS-type MOS for the bank selection transistors, which causes difficulties in the reduction of the layout area.
Memory devices with flat-type ROM design are well documented. For example, a prior technique is illustrated in U.S. Pat. No. 5,117,389 of Yiu, entitled “Flat-Cell Read-Only-Memory Integrated Circuit”. Shown in FIG. 1, the number of bank selection transistors utilized is reduced in a memory array, and the metal lines are shared between even and odd banks. Access to the metal lines is made through a plurality of LOCOS bank selection transistors connected to every other buried diffusion. By using this architecture, the metal lines are running parallel to the buried diffusion lines. A block select transistor (BWLN), word select transistor (SWLN), bank left select transistor (SBLN) and a bank right select transistor (SBRN) are required to access a ROM cell. Contacts are made for connecting them by using isolated bank selection transistors. The alternate buried diffusion bit lines are connected through either a buried diffusion region to its left or a buried diffusion region to its right to the metal lines, by means of left-right bit selection transistors. One disadvantage of the ROM design of Yiu is the number of transistor required to access the ROM cell, which affects the overall size of the array. Other peripheral circuits also contribute to the overall array size.
Another design is U.S. Pat. No. 5,621,697 of Weng et al., entitled in “High Density Integrated Circuit with Bank Select Structure”. In this design, the bank selection structure includes bank selection transistors which are located and oriented adjacent diffusion bit lines and intrabank diffusion bit lines. Each intrabank bit lines of a bank extends into neighboring banks either above or below the bank. Interbank bit lines provide reducing the number of bank selection transistors. To improve the vertical pitch, the bank selection transistors are coupled to the metal lines by metal-to-diffusion region contacts.
Therefore, it is desirable to design a high performance ROM that can be manufactured with high yield. It is also desirable to utilize straight metal bit lines to simplify manufacture and increase circuit efficiency. It is also desirable to minimize the number of transistors in an array in order to optimize speed, size, power consumption and ease of fabrication parameters. Furthermore, for reduction of layout area and flexible fabrication, the contact number should be reduced and the metal pitch should be released.
USPTO Backgrounds
USPTO Backgrounds