This specification relates to storage devices with soft processing.
Memory devices are widely used for storage of information. There are two main categories of memory devices: volatile memories, which generally need electrical power to maintain their stored information, and non-volatile memories, which can retain the stored information even when not powered. Common examples of volatile memories include dynamic random access memory (DRAM) and static random access memory (SRAM). Common examples of non-volatile memories include read-only memory (ROM) and flash memory.
In many semiconductor-based memory devices, data is stored in an array of memory cells. FIG. 1 shows one example of a two-dimensional memory array 110 in which cells 112 are arranged into columns and rows. Each cell 112 is connected to its neighboring cells via a pair of word line Wi and bit line Bi that together defines a unique physical address for the cell. Based on its address, each cell can be accessed (e.g., written, read, and/or erased) individually or in groups (e.g., words, pages) depending on the architecture of the memory device.
In an example of a flash memory, a cell 112 can be made from a floating-gate transistor that has a source (S), a drain (D), a control gate (CG), and a floating gate (FG). During a “write” (also known as “program”) operation, data is written to the cell 112 by injecting a certain amount of electrical charge onto the FG to alter the threshold voltage (VT) of the cell. Here, the threshold voltage VT refers to the lowest voltage applied to the CG of the cell that is sufficiently high to induce a source-drain current.
The VT of a flash memory cell is usually in a physical range, known as the “voltage window,” defined by a minimum voltage value Vmin and a maximum voltage value Vmax. The voltage window can be partitioned into two or more threshold voltage domains to define a set of different logic states (e.g., “0,” “1,” “2,” . . . ) to which a cell can be written. For example, for a memory that stores a single bit per cell (also referred to as a memory of binary cells), the voltage window is divided into two threshold voltage domains that respectively represent state “0” and “1.” For a memory that stores a string of 3 bits per cell, the voltage window is divided into 8 (i.e., 23) domains, each of which represents a different one of the 8 logic states of the cell.
In some examples of flash memory, to read a memory cell, the threshold voltage of the cell is compared with a set of reference voltages representative of the threshold voltage domains defining the logic states. A signal is generated by sensing the source-drain current of the cell to determine whether the cell's threshold voltage is higher or lower than the reference voltage with which it is compared, and consequently, to which logic state the cell was last written.
As with most devices, memory devices are susceptible to errors. There are various factors that may affect the reliability of the write and read results of a memory device. One example is the aging of certain types of memory cells that causes a gradual shift in the voltage window and the threshold voltage domains that define the logic states of the cells. Due to aging, the number of times for which these types of memory cells can be re-programmed is generally limited. Another example is the variations in the fabrication process that may cause certain cells to behave differently than others when read or programmed. A further example is the random noise that limits the precision of the read and/or program circuitry.
Some memory designs make use of error reduction and/or error correction schemes to improve the reliability (e.g., read/write accuracy) of memory devices. FIG. 2 shows one example of a flash memory device 200 with error correction functionality. In this example, a memory array 210 resides together with a set of one or more reference cells 220 on a memory chip 250. Each reference cell carries a reference voltage that may be applied in a pre-defined order to the control gate of a selected memory cell for generating a signal representing the source-drain current i of this cell. (In some other examples, references voltages may be swept to control the gate of selected memory cells to generate signals.) This current i is then compared in a comparator 230 or a thresholding device (e.g., a sense amplifier) against a threshold current ith to produce a “hard” (digital) bit, i.e., “0” or “1,” representing the result of comparison. Subsequently, the output of the comparator 230 is translated in a translation unit 232, for example, according to a control signal provided by a controller 231 that also controls the sequential application of reference voltages, to generate a bit string representing the data stored in the cell. As a group of memory cells are read, a digital bit stream is produced representing the stored data in those cells. Note that this bit stream is likely to include errors for reasons described above. In this example, to improve the data reliability and reduce the bit error rate (BER) of the memory device, error correction codes (ECC) may be used in write operations to introduce carefully designed redundancy to generate a coded bit string (codewords) representing the original information to be stored. To recover the original information in a read operation, the stream of the sensed (observed) coded bit strings may be sent to an external controller chip 260 to be decoded in an ECC decoder module 240.
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