1. Field of the Invention
The present invention relates to a repair control circuit, and in particular to an improved repair control circuit which is capable of reducing a fuse cutting time and a chip size by reducing the number of fuses when a sense amplifier having a repair function is operated.
2. Description of the Background Art
As shown in FIG. 1, a known repair control circuit includes a block repair controller 1 for outputting a block repair control signal RB, a column coding controller 2 for outputting a column coding signal RECOL, an input/output repair controller 3 for receiving the column coding signal RECOL and outputting an input/output enable signals IOEN.sub.j, where j=0 to 3, main sense amplifier controllers 40-i, where i=1 to 4, for outputting main sense amplifier disable signals MSADIS.sub.j, where j=0 to 3, main sense amplifiers 5-i, where i=1 to 4, for receiving data from a data bus and amplifying the same in accordance with a main sense amplifier disable signal and a sense amplifier enable signal SAEN, a repair sense amplifier 6 for receiving data from the data bus and amplifying the same in accordance with a block repair control signal RB and a sense amplifier enable signal SAEN, and a multiplexer 7 for selectively outputting data from the main sense amplifiers 5-i and the repair sense amplifier 6.
Here, as shown in FIG. 2, the input/output repair controller 3 includes an inverter INV21 for inverting a column coding signal RECOL, a plurality of input/output fuses IOF21 through IOF24 for blocking the output signal from the inverter INV21, and a plurality of ground voltage fuses VSF21.about.VSF24 connected with a ground voltage VSS and the input/output fuses IOF21.about.IOF24.
As shown in FIG. 3, an example main sense amplifier controller 4 includes: a resistor R31 and a main sense amplifier fuse MF31 connected in series between an external voltage VCC and a ground voltage VSS; an inverter INV31, one input terminal of which is commonly connected with the resistor R31 and the main sense amplifier fuse MF31 for outputting a main sense amplifier disable signal MSADIS0; a PMOS transistor PM31, the drain and source of which receive an external voltage VCC, and the gate of which is commonly connected with the resistor R31 and the main sense amplifier fuse MF; and a PMOS transistor PM32, the source of which receives an external voltage VCC, the gate of which receives an output signal from the inverter INV31, and the drain of which is commonly connected with the resistor R31 and the main sense amplifier fuse MF31.
As shown in FIG. 4, an example main sense amplifier 5-L includes: a NAND-gate ND41 for receiving the main sense amplifier disable signal MSADIS0 and the sense amplifier enable signal SAEN; an inverter INV41 for inverting the output signal from the NAND-gate ND41; NMOS transistors NM41 and NM42, the gates of which receive the output signal from the inverter INV41, and the sources of which are connected with the ground voltage VSS; and main sense amplifiers MSA41 and MSA42 for receiving data DI0, DIB0, DI1 and DIB1 from the data bus in accordance with the control of the drains of the NMOS transistors NM41 and NM42 and amplifying the thusly received data and outputting main sense amplifier output data DO0 and DO1.
As shown in FIG. 5, the repair sense amplifier 6 includes: a NAND-gate ND51 for receiving a block repair control signal RB and a sense amplifier enable signal SAEN; an inverter INV51 for inverting an output signal from the NAND-gate ND51; NMOS transistors NM51 and NM52, the gates of which receive an output signal from the inverter INV51 and the source of which is connected with a ground voltage VSS; and main sense amplifiers RSA0 and RSA1 controlled by the drains of the NMOS transistors NM51 and NM52 for amplifying the data RDI0, RDIB0, RDI1 and RDIB1 inputted through the data bus and amplifying the same and outputting main sense amplifiers RSA51 and RSA52.
As shown in FIG. 6, an example output multiplexer 7 includes: inverters INV61 and INV62 for inverting the input/output repair control signal IOEN0; and transmission gates TG61 and TG62 controlled in accordance with the input/output repair control signal IOEN0 and the inverter signal for transmitting the main sense amplifier output data DO0 and DO1 and the repair sense amplifier output data RDO0 and RDO1 and selectively outputting the output data DOUT0 and DOUT1.
The operation of the known input/output repair control circuit will now be explained with reference to the accompanying drawings.
First, the block repair controller 1 cuts the block fuse with respect to the cell to be repaired and outputs a low output signal. As a result of the block coding, as shown in FIG. 7A, a high level enable signal is outputted to the block repair signal RB.
At this time, the input/output repair controller 3 cuts the input/output fuse with respect to the cell to be repaired, and the repair column signal RECOL which is a column signal of the cell to be repaired (as shown in FIG. 7B) is outputted as a high level input/output enable signal IOEN as shown in FIG. 7C. If there is not cell to be repaired, the input/output repair control signal IOEN cuts the ground voltage fuse VSF, and a low level input/output enable signal IOEN is outputted.
In addition, the main sense amplifier controller 4 cuts a main sense amplifier fuse MF neighboring with the main sense amplifier with respect to the input/output corresponding with the cell to be repaired, and the main sense amplifier disable signal MSADIS as shown in FIG. 7E becomes a low level, so that the main sense amplifiers MSA41 and MSA42 of the main sense amplifier 5 is disabled.
If there is a cell to be repaired, the main sense amplifier disable signal MSADIS becomes a low level, and the NMOS transistors NM41 and NM42 are turned off, so that the main sense amplifiers MSA41 and MSA42 are disabled. In addition, the repair sense amplifiers RSA51 and RSA52 of the repair sense amplifier 6 are enabled by the repair block signal RB and the sense amplifier enable signal SAEN as shown in FIG. 7D.
Therefore, if there is a cell to be repaired, the input/output repair control signal, e.g., IOEN0 which is an output signal from the input/output repair controller 3 becomes a high level, and the transmission gates TG61 and TG63 of the multiplxer 7-1 transmitting the output signals DO0 and DO1 from the main sense amplifiers MSA41 and MSA42 are turned off, and the output signals DO0 and DO1 from the main sense amplifiers MSA41 and MSA42 are not outputted. The transmission gates TG62 and TG64 of the multiplxer 7-1 transmitting the output signals RDO0 and RDO1 from the repair sense amplifiers RSA0 and RSA1 are turned on. As shown in FIGS. 7F and 7G, the output signals RDO0 and RDO1 from the repair sense amplifiers RSA51 and RSA52 are outputted as output data DOUT0 and DOUT1.
Generally, when the repair sense amplifier is operated in order to output the input/output data repaired by the repaired chip, the repair sense amplifier and the main sense amplifier are all operated, so that the driving current of the chip is increased.
Therefore, in order to reduce the above-described driving current, since the fuses disabling the main sense amplifier should be used for every main sense amplifiers, the number of the fuses is increased, so that the size of the main chip is increased, and the repairing time is increased.
USPTO Backgrounds
USPTO Backgrounds