Various kinds of packages for LSI chips are known. Recently, a chip size package (CSP) having almost the same size as the LSI chip, has been put under development in order to reduce the size of the package.
FIG. 1 shows packaging processes for various kinds of conventional chip size packages. Reference numeral 101 shown in FIG. 1 shows a packaging process for a lead frame package, reference numeral 102 shown in FIG. 1 shows a packaging process for a Fine-pitch Ball Grid Array (FBGA) and reference numeral 103 shown in FIG. 1 shows a packaging process for a wafer-level CSP.
The packaging process 101 for the Lead frame package and the packaging process 102 for the FBGA shown in FIG. 1 are conventional packaging processes (a dicing process A1, a die bonding process A2, a wire bonding process A3, an encapsulation process A4, a lead forming process A5/a lead surface finishing process and a cutting process for singularization (dicing a wafer into single chips) A6 or a terminal finishing process and a cutting process for singularization A7). In these packaging processes, each chip processed by a front-end process 104 is cut by the dicing process and the chip is assembled by an assembly process. However, in a packaging process 103 in the wafer level CSP of the present invention as shown in FIG. 1, a wafer processed by the front-end process is directly processed by the packaging process 103 (a Pi film forming process A11, a reroute tracing process A12, a post forming process A13, an encapsulation process A14, and a terminal grinding process A15). Then, the wafer is cut to singularize each chip (a dicing process A16).
FIG. 2 shows a sectional view of the chip manufactured by the wafer level CSP technology. In FIG. 2, reference numeral B1 shows an IC chip (a silicon chip), reference numeral B2 shows an aluminum electrode placed on a pad of the IC chip B1, reference numeral B3 shows a barrier metal layer, reference numeral B4 shows a reroute trace layer (Cu) placed on the barrier metal layer B3, reference numeral B5 shows a copper post, reference numeral B6 shows a solder bump (a solder ball), reference numeral B7 shows a passivation layer, reference numeral B8 shows a mold layer(for example, a resin encapsulation layer) and reference numeral B9 shows a protection film.
In the conventional wafer level CSP, it is assumed that the aluminum electrode B2 placed on the pad of the IC chip B1 is connected to the copper post B5 and the solder bump (the solder ball) B6 only through the reroute trace B4 having a resistance as low as possible.
However, there is a problem that specifications and performance of the CSP are limited by the structure of the IC chip, if it is assumed that the aluminum electrode placed on the pad of the IC chip B1 is connected to the copper post B5 and the solder bump (the solder ball) B6 only through the reroute trace B4 having a resistance as low as possible.
USPTO Backgrounds
USPTO Backgrounds