The present invention relates to chip-type composite electronic parts such as a network resistor and a hybrid IC.
In general, a chip-type network resistor is produced as follows. First, as shown in FIG. 1, common electrodes 4, individual electrodes 5 and resistor films 6 are formed, by printing and baking, on a substrate 1 in which breaking slits 2 and holes 3 have been formed. Then, the respective resistor elements are trimmed with each unit of eight resistor elements employed as a composite part 7. Then, breaking is performed to divide the substrate 1 into rows of composite parts, and side-face electrodes are formed.
FIG. 2 is a circuit diagram of the chip-type network resistor 7 of FIG. 1. For example, an element R.sub.8 in FIG. 2 is trimmed while applying a measurement probe is applied to terminals P.sub.1 and P.sub.10 or to terminals P.sub.6 and P.sub.10. However, if the FIG. 2 circuit itself is subjected to the trimming of the element R.sub.8, a current flows between the terminals P.sub.6 and P.sub.10 via an element R.sub.A, which means a resistance of a parallel circuit of the elements R.sub.8 and R.sub.A is measured. Therefore, the trimming of the element R.sub.8 cannot be performed. As a countermeasure, the trimming is conventionally performed in a state that the electrode located between the elements of the adjacent parts is opened.
However, this trimming method may cause a conduction defect in forming a side-face electrode 8 because the electrode conductor 5 on the substrate 1 does not reach the end face of the substrate 1 (see FIG. 3). On the other hand, the elimination of the adjacent element will reduce the number of produced parts per substrate, which causes a cost increase. Further, the opening of the electrode will halve a pad area for connection of the measurement probe, which will increase defects.
USPTO Backgrounds
USPTO Backgrounds