1. Field of the Invention
The invention generally relates to differential circuits using metal-oxide semiconductor (MOS) field effect transistors (FETs). In particular, embodiments are applicable to the biasing of any MOS transistor differential pair configuration for which the gate voltage can be adjusted and biasing in the saturation region is desirable.
2. Description of the Related Art
Differential signaling is often used in high-speed data transmission systems in a variety of applications including in printed-circuit boards, cables and backplanes. When compared to single-ended signaling, it provides a higher signal integrity because of its superior common-mode noise immunity and of the threshold level that is unaffected by differences in ground or supply levels.
High-speed transmission of electrical signals requires that the output impedance of the driver and the input impedance of the receiver be relatively well matched to that of the transmission medium. When this is not the case, the impedance mismatches will typically create reflections that will affect the integrity of the received signal. In typical systems, the impedance of the medium varies between 50Ω and 75Ω, with the driver and the receiver being terminated having 50Ω to 75Ω single-ended terminations or 100Ω to 150Ω differential terminations. FIG. 1 illustrates an example of a link with a driver and a receiver and terminations at both ends.
In many circuits using complementary MOS (CMOS) technology, differential output drivers are commonly implemented as a differential open-drain driver with resistive loads. FIG. 2 illustrates an example such a driver using a differential pair of N-channel or N-type of MOS transistors in the driver. Of course, P-channel or P-type devices can also be used. In such a driver, the resistive loads R1, R2 are generally set to approximately 50Ω or 75Ω to ensure a proper near-end termination. With this approach, it is desirable to maintain relatively high output impedance in the transistors of the differential pair so that the output impedance is mainly determined by the resistive loads R1, R2. Providing a termination that matches well with the transmission line ensures a high return loss for the driver at low frequencies.
To maintain a relatively good return loss for an open-drain differential driver at high frequencies, the drain capacitance of the differential pair transistors is preferably kept relatively low. One way to achieve relatively low capacitance is to bias the transistors in the saturation region when “on,” rather than in the triode or linear region. It will be understood that when a differential pair is used for data transmission, one of the transistors will typically be biased “on” and the other transistor will typically be biased “off” (except during transitions). In other applications, both transistors of the differential pair can be “on.” FIG. 3 illustrates a family of curves for an N-channel device and graphically indicates the triode or linear region and the saturation region. FIG. 3 also illustrates a sub-threshold region. These regions will also be described in greater detail with equations. In the saturation region, the transistor's channel is pinched off near the drain, which advantageously reduces the drain-gate capacitance. This reduction in capacitance also has the added benefit of improving the edge rates at the driver output, which permits relatively higher transmission rates.
In addition to obtaining relatively high return loss, it can be useful to maintain a well-controlled output swing. In data communication applications, the transistors of a differential pair typically switch between active (on) and inactive states (off). When the transistors are biased to the saturation region when “on” rather than to the linear region, the transistors are more readily transitioned to an inactive state, which reduces the leakage current of the inactive branch of a differential pair for a given input voltage swing. With relatively small leakage current, the current IOUT and the value of the load resistors R1, R2 define the output swing. This can be a significant benefit when the pre-driver (driver of the differential driver) has a relatively limited output swing with a low level that is not guaranteed to fully turn off the transistor of the inactive branch in the output driver. For example, this can occur when the pre-driver is implemented with a differential circuit similar to that of the output driver.
FIG. 4 illustrates a conventional differential open-drain driver with generic blocks for the loads L1, L2. The skilled artisan will appreciate that a wide variety of loads L1, L2 can be used, including, but not limited to, transistor loads or external resistive loads, without a loss in generality. While N-type MOS transistors (NMOS) are illustrated, the skilled artisan will also appreciate that the driver can also be made with P-type of MOS transistors (PMOS).
In the differential output driver illustrated in FIG. 4, the output voltage (VOP−VON) is created by switching the current IOUT to the loads L1 and L2 through the differential pair transistors M1 and M2. This switching is enacted by applying a differential input voltage (VIP−VIN) to the differential pair transistors. Depending on the values of VDD, VSS, IOUT, VIP, VIN, VOP and VON, the differential pair transistors can operate either in the triode region or the saturation region when active. As described earlier, in differential open-drain drivers, there are significant benefits to maintaining driver transistors M1, M2 in their saturation region (VDS>VDSAT) when active.
When driver transistors M1, M2 are biased in the saturation region when active, their output impedance is relatively high, and their output current is relatively independent of their drain-source voltage (VDS). This reduces the sensitivity of the output swing to supply variations. When the loads L1, L2 are used as termination resistors, the relatively high output impedance of the driver transistors M1, M2 ensures that the output impedance of the driver is mainly determined by the loads L1, L2. This allows for relatively accurate termination impedance across process variations and improves the low frequency return loss at the driver output. Maintaining a relatively high output impedance for driver transistors M1, M2 also reduces the output capacitance of the current source I1 seen at the output nodes, which has a relatively large benefit on return loss and edge rates.
In the saturation region, the drain-gate capacitance (CGD) of driver transistors M1, M2 is relatively small due to the narrow channel at the drain. The reduction of CGD increases the bandwidth, reduces the rise times and improves high frequency return loss at the driver output (VOP, VON). It allows for a reduction in the size and power consumption of the pre-driver circuit and minimizes feedthrough from the driver input to the driver output.
Equation 1 illustrates conditions for a transistor in the differential pair to be in the saturation region. It will be understood that while illustrated in the context of NMOS, the principles also apply to PMOS.VDS≧VGS−VT  Equation 1
In Equation 1, VT is the threshold voltage of the differential pair transistors (M1, M2). In the literature, the threshold voltage is also written VTH.
From Equation 1, it can be observed that the output differential pair can be kept in saturation either by reducing the output swing to increase VDS or by making the devices relatively larger to reduce VGS−VT for a given output swing. Neither option is desirable in a high-speed differential open drain driver for which a common design goal is to make an efficient use of dissipated power by achieving a relatively high output swing with relatively low input and output capacitance to ensure relatively fast edge rates.
Also, maintaining the transistors of the differential pair in the saturation region when active can reduce the pre-driver swing used for ensuring that there is no significant leakage in the inactive branch. A transistor should be “off” when the gate-to-source voltage VGS of the transistor is less than the threshold voltage VT of the transistor. In practice, it will be understood that a gate-to-source voltage VGS that is lower than the threshold voltage VT by a small amount ΔV is typically used to compensate for second-order effects that can result in sub-threshold currents. These sub-threshold currents are typically reduced exponentially in proportion to the small amount ΔV so that ΔV is typically relatively small. The reduction in swing can be a significant benefit when the pre-driver has a relatively limited output swing with a low level that is not guaranteed to fully turn off the transistor of the inactive branch in the output driver for all pre-driver common-mode levels.
One conventional approach to the design of open-drain differential drivers is to select the minimum-size differential pair that allows the IOUT current to be switched completely through the active transistor of the differential pair, while leaving enough headroom for the precise operation of the current source I1. To keep the differential pair transistors in saturation when a large output swing is used, it is often necessary to lower the high output voltage of the pre-driver circuit (denoted VGHIGH). FIG. 5 illustrates high and low pre-driver output voltages that are applied as inputs to gates of the differential pair (N-channels illustrated). This level shifting of the input voltage of the differential pair transistors effectively lowers their source voltage (VS) and increases their drain-to-source voltage VDS for a relatively constant gate-to-source voltage VGS.
However, the use of deep-sub-micron technologies using low supply voltages, for example, on the order of 1V and less, renders this traditional approach impractical. Accordingly, the objectives of relatively large output swings while keeping the output transistors in saturation, as required to achieve fast output transitions and good return loss, are difficult to achieve.
For large output swings in these technologies, or very large swings in higher voltage technologies, it is difficult to determine a static pre-driver high output voltage level that will guarantee the saturation of the differential pair transistors across process, voltage and temperature variations (PVT).
This can be readily illustrated with a simple example. Consider the basic equation for the drain current (ID) of the MOS transistor operating in the saturation region (N-channel):ID=K*(VGS−VT)2  Equation 2
From Equation 2, it can be seen that process variations in the threshold voltage VT require a similar variation of the gate-source voltage VGS to maintain a constant drain current ID. It should also be noted that for the differential pair of the open-drain driver, the minimum source voltage is fixed by the headroom required for the precise operation of the current source I1 and that the minimum drain voltage is set by VDD minus the output swing.
From these observations and Equation 1, it is apparent that the designer of a relatively high swing open-drain differential driver faces two conflicting constraints with respect to gate voltage. For process variations characterized by relatively high threshold voltage VT, the gate voltage of the active transistor in the differential pair should be increased to maintain a VGS−VT large enough to fully commutate IOUT while maintaining sufficient headroom for the current source I1. For process variations characterized by relatively low threshold voltage VT, the source voltage of the active transistor is naturally higher and pushes the transistor out of saturation since its drain voltage is fixed by VDD and the output swing. In this low threshold voltage VT process corner, the gate voltage of the active transistor should thus be lowered to similarly lower the active transistor's source voltage and increase its VDS so that the transistor can operate in the saturation region while active.
Note that this example is illustrative of only one of the many possible impacts of process, voltage and temperature (PVT) variations. It will be understood that other process variations will introduce other compromises and that these variations can also be combined.
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