The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The circuit components are interconnected, enabling the ICs to perform the desired functions.
FIG. 1 shows an interconnection used in ICs 100. The interconnection is formed in an interlevel dielectric (ILD) layer 110 disposed on a substrate 105. A copper line 140 is disposed on an upper part of the ILD layer. Coupled to the metal line is a contact 130, interconnecting the metal line to the substrate below. The contact can be coupled to another copper line or device feature 120. Typically, an IC includes a plurality of metal levels.
To form the interconnection, the ILD layer is patterned to create a via and trench. The via and trench are filled with copper. The copper includes an overburden to ensure filling of the trench and via. The overburden or excess copper is then removed by chemical mechanical polishing (CMP) to form a planar top surface with the metal line 170 and ILD layer. In conventional interconnection processes, a pre-CMP low temperature anneal, for example, less than 150° C. is performed on the copper.
However, conventional interconnection processes induces tensile stress 173 on the metal line which can cause a void 135 (“via pull-out”) between the contact and, for example, metal line below. This can cause contact failure in the IC.
From the foregoing discussion, it is desirable to provide interconnections without void in the contacts.
USPTO Backgrounds
USPTO Backgrounds