1. Field of the Invention
The invention relates to a digital integrating circuit device (hereinafter referred to as "digital integrating circuit"), and, more specifically, to a digital integrating circuit for accumulating data at a high speed in camcorders and the like.
2. Description of the Prior Art
FIG. 8 is a structural diagram of a prior art digital integrating circuit. In the figure, designated at 10 to 1n are n+1 (n: an integer of 1 or more) one-bit full adders (FA) corresponding to bits 0 to n of input data. A0 to An and B0 to Bn represent add inputs of the full adders, C0 to Cn carry inputs, S0 to Sn sum outputs, and CY0 to CYn carry outputs. The carry outputs are connected to higher-order carry inputs. Designated at 20 to 2n are D type flip-flops (FF) corresponding to the above-described full adders. I indicates the data input of each of the flip-flops, O data output, C clock input and R reset input. The sum outputs S0 to Sn of the above-described full adders 10 to 1n are input into the data input I of the flip-flops upon a fall in clock signal U and data are output from the data output O of the flip-flops to the add inputs B0 to Bn of the full adders 10 to 1n upon a rise in clock signal U. In the initial state, the data output O of each of the flip-flops 20 to 2n is set at "0" by a reset signal RESET from the outside of the device. Designated at 30 to 3n are latch circuits corresponding to the full adders 10 to 1n. I represents the data input of each of the latch circuits, O data output, and C clock input. During the period when the clock signal U is at high ("H"), the latch circuits supply data input through external input terminals P0 to Pn from the outside of the device directly to the add inputs A0 to An of the full adders 10 to 1n, and, during the period when the clock signal U is at low ("L") , they maintain the previous state.
A description is subsequently given of the operation of the digital integrating circuit. At the start of the operation, data from the data output O of each of the flip-flops 20 to 2n is set at an initial value of "0" by the reset signal RESET. FIG. 9 is a timing chart showing the timing of the digital integrating circuit shown in FIG. 8. Upon a rise in clock signal U, n+1 pieces of data from the respective input terminals P0 to Pn are input into the respective add inputs A0 to An of the full adders 10 to 1n through the respective latch circuits 30 to 3n. Values of the flip-flops 20 to 2n (initially set at "0") are input into the other respective add inputs B0 to Bn of the full adders. At this time, since the carry input C0 of the full adder 10 corresponding to the least significant bit (LSB) is fixed at "0", the sum output S0 and the carry output CY0 of the full adder 10 become definite after a unit delay time .DELTA.t. This unit delay time At is required for the input, addition and output of data A0 and B0. The add inputs A1 and B1 of the following full adder 11 are supplied simultaneously with the add inputs A0 and B0 of the above-described full adder 10. However, since the carry input C1 of the full adder 11 also becomes definite after a delay time of .DELTA.t, the outputs S1 and CY1 of the full adder 11 become definite after a delay time of 2.DELTA.t. In consequence, the outputs Sn and SYn of the full adder in corresponding to the most significant bit (MSB) of the digital integrating circuit shown in FIG. 8 are delayed by (n+1).times..DELTA.t.
It is necessary to divide the screen into some sections and to obtain an integral value of a luminance signal for each section of an image obtained from each scanning in order to effect auto-focusing and auto-exposure in an imaging device such as a camcorder. FIG. 10 shows the scanning of the sectioned screen, and solid lines indicate scanning lines and broken lines indicate horizontal retrace lines. In FIG. 10, the screen to be scanned is divided into three sections I, II and III to obtain an integral value between the vertical retrace lines of each section (for one frame). The actual state of the signal is such as shown in FIG. 11 (since waveforms corresponding to scanning lines between scanning lines 2 and 3 and between scanning lines 3 and 4 are the same as the previous ones, they are omitted). To integrate the signal, it is necessary to perform the following. The scanning line 3 of FIG. 10 has virtually the waveform 3 in FIG. 11 and consists of five parts corresponding to sections I, II, III, II and I. FIG. 12 is an enlarged diagram of this waveform. As shown in FIG. 13, actual integration is effected by sampling waveforms at time intervals of .DELTA.T, carrying out A/D conversion at time intervals of .DELTA.T, and inputting the thus obtained digital values to the external input terminals P0 to Pn of the digital integrating circuit shown in FIG. 8. FIG. 12 and FIG. 13 indicate the following. Analog values obtained at time intervals of .DELTA.T, that is, values in the direction of height (the direction h of the vertical axis), are converted into (n+1)-bit binaries which are then input into the external input terminals P0 to Pn. In other words, this A/D conversion is performed at time intervals of .DELTA.T in the direction t of the horizontal axis, heights obtained at time intervals of .DELTA.T are converted into (n+1)-bit binaries, and the binaries are then input into P0 to Pn at time intervals of .DELTA.T. Data to be converted is (n+1)-bit data and digital values obtained by A/D conversion at time intervals of .DELTA.T are binaries whose least significant bit (LSB) is input into the external input terminal PO and whose most significant bit (MSB) is input into the external input terminal Pn. In this manner, values obtained by A/D conversion at time intervals of .DELTA.T are input into the external input terminals P0 to Pn, and their accumulated values are stored in the flip-flops 20 to 2n by the above-described operation principle. However, since it is necessary to obtain an accumulated value for each of the sections I, II and III, three integrating circuits shown in FIG. 8 must be prepared to calculate and accumulate values for these sections. This process is performed for each scanning line to obtain accumulated values for the sections I, II and III between vertical retrace lines. Upon completion of accumulation, that is, within the vertical retrace line section, a value of the output O of each of the flip-flops 20 to 2n shown in FIG. 8, that is, a (n+1) -bit binary, is used as the final data to be displayed externally. Values at time intervals of .DELTA.T shown in FIG. 13 are obtained by sampling the waveform shown in FIG. 12 at time intervals of .DELTA.T. Input digital data shown in FIG. 8 are (n+1)-bit binaries obtained by converting the analog data sampled at time intervals of .DELTA.T in FIG. 13. Conventionally, digital integrating circuits are provided for each of the sections I, II and III and used by switching. In FIG. 11, the digital integrating circuits are not reset after the accumulation of a waveform 1. Accumulation is continued for waveforms 1 to 5 and the digital integrating circuits are then reset in vertical retrace line sections. The integrating circuits corresponding to the sections I, II and III are only active for their respective sections I, II and III, and reset only in the vertical retrace line sections. Therefore, immediately before the digital integrating circuits are reset in the vertical retrace line sections, the sum of the waveforms 1 to 5 for the section I, for example, is accumulated in the integrating circuit corresponding to the section I. If the sampling cycle of .DELTA.T is shortened by raising the sampling frequency, higher-precision auto-focusing and auto-exposure can be achieved.
Since the prior art digital integrating circuit is structured as described above, higher-order adders are delayed more, and the adder corresponding to the most significant bit (MSB) is delayed by (n+1).times..DELTA.t. In this way, after the carry output of the preceding adder becomes definite, the next adder can perform an add operation. Therefore, the larger the bit width of the adders, the more the adders are delayed, which hinders operation speed. Therefore, when accumulation is performed for each section in camcorders and the like, it is impossible with the prior art digital integrating circuit to raise the sampling frequency because of a carry propagation delay.
USPTO Backgrounds
USPTO Backgrounds