1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device such as an erasable programmable read-only memory (hereinafter referred to as an "EPROM") in which ultraviolet light is used for erasing data and an electrically erasable programmable read-only memory (hereinafter referred to as an "EEPROM") in which the data erasing is effected electrically.
2. Description of the Related Art
A conventional non-volatile semiconductor memory device is shown in FIGS. 1A and 1B which are a longitudinal cross-sectional view and a transverse cross-sectional view of the device, respectively. As shown therein, the device includes a semiconductor substrate 1; a drain region 2c and a source region 2d constituted by n-type impurity diffusion layers, respectively; a floating gate electrode 4; a gate insulating film 3 (hereinafter referred to as "C-FG gate insulating film") disposed between a channel region and the floating gate electrode 4; a control gate electrode 6; a gate insulating film 5 (hereinafter referred to as "FG-CG gate insulating film") disposed between the floating gate electrode 4 and the control gate electrode 6; an interlayer insulating film 7; and a field insulating film 8. Under the field insulating film 8, there is a channel stopper (now shown in the drawings) constituted by a highly doped diffusion layer.
In the conventional memory transistor described above, the changes in threshold values depend on the electric charge accumulated in the floating gate 4. The storing of data is effected by the electric charge and the reading of the data is effected by the conversion of the changes in the threshold values into channel currents.
The data writing or programming is effected mainly through the injection of hot electrons from the channel region, the Fowler-Nordheim tunneling phenomena which takes place in the C-FG gate insulating film 3, and the avalanche breakdown caused by the injection of hot holes.
An equivalent circuit diagram of an ordinary memory array which is used in an EPROM or a flash EEPROM (hereinafter referred to as "FEPROM") is shown in FIG. 2. Here, Q.sub.Mi,j (i=1,2, j=1,2) are memory transistors; X.sub.1, X.sub.2 are word lines connecting the control gate electrodes 6 shown in FIGS. 1A and 1B in a row direction; Y.sub.1, Y.sub.2 are bit lines connecting the drain regions 2c in a column direction; and S is a source line commonly connecting the source regions 2d.
Now, the operation of the above described conventional device is explained.
(1) READING: The word line selected is biased to a high voltage, for example, 5 V and the other word line is biased to a low voltage, for example, 0 V. Also, the bit line selected is put to 1 V and the other bit line is put to an open state. This selected bit line is connected to a sense amplifier. Consequently, the current that corresponds to the threshold value of the memory transistor at an intersection point of the selected word line and the selected bit line flows in the selected bit line. That is, if the threshold value of the transistor is lower than 5 V, the channel current flows and, if the same is higher than 5 V, no current flows. The sense amplifier detects the potential changes taking place at the node (intersection) due to the presence or absence of the current.
(2) WRITING: The word line selected is biased to a high voltage, for example, 13 V and the other word line is biased to a low voltage, for example, 0 V. Also, the bit line selected is put to 7 V and the other bit line is made open. Consequently, the channel current flows only to the transistor at the intersection of the selected word line and the selected bit line with the hot electrons being produced and the electrons being injected to the floating gate electrode 4. In the same manner, the memory transistors to be written-in are consecutively selected.
(3) ERASING: In the case of EPROM, the entire surface is subjected to irradiation by ultraviolet light. In the case of FEPROM, all the word lines are put to a low voltage, for example, 0 V and all the bit lines are made open, with a high voltage, for example, 12 V being applied to the source line. Consequently, the electric field between the source and the floating gate electrode becomes strong thereby causing the discharge of electrons from the floating gate electrode to the source electrode, which results in the data erasing.
The conventional device described above has the following structural characteristics which result in the problems also explained below.
1) The source/drain regions are formed within the surface region of the semiconductor substrate.
2) The channel region is formed using the surface of the semiconductor substrate.
3) Device isolation is effected by means of a thick insulating film formed on the surface of the substrate and an impurity diffusion layer formed under the insulating film.
The problems resulting from the above are:
I) The substrate has a fixed constant potential but, in view of 1) above, there is produced a depletion layer between the drain electrode and the substrate, causing the generation of a diffusion layer capacitance, the value of which is dependent on the total area of the drain region and the amount of impurity concentration of the substrate. Under the condition of the substrate concentration being 7.times.10.sup.16 cm.sup.-3, V.sub.D =1 V, the capacitance per .mu.m.sup.2 is about 1.times.10.sup.-3 pF. In the actual fabricated device, since many memory transistors are connected to the bit line, the bit line capacitance becomes several pF. However, when the device capacity is increased, since the charging-up of the drain voltage is delayed in proportion to a time-constant given by the product of the bit line capacitance and the resistance of the bias transistor and the discharging is delayed in proportion to a time-constant given by the product of the bit line capacitance and the resistance of the cell transistor, so that this structure suffers from the problem of a slower reading speed.
II) Since the drain region is formed in the surface region of the substrate as described in 1) above, junction leakage occurs where there is a defect in the drain depletion layer. Unless this leakage current is negligibly small when compared with the current for reading the cells, it becomes impossible to read the data from the written-in cell. Especially, this structure is susceptible to crystallization defects in the region adjacent to the thick insulating film for device isolation, and such phenomena result in the lowering of the production yield.
III) Since the source region is formed in the surface region of the substrate as described in 1) above, where a high voltage is to be applied to the source electrode for effecting the data erasing, an avalanche breakdown current or a leakage current in addition to the Fowler-Nordheim tunneling current is produced and is caused to flow into the substrate. Consequently, if the source voltage is applied by means such as a charge pump power source in which the voltage is raised from a low power source voltage, voltage drop occurs due to a power supply shortage and this results in the inability to maintain the voltage required for the data erasing operation.
IV) In view of 2) above, the threshold value V.sub.TM of the memory transistor changes depending on the substrate potential V.sub.SUB according to the following equation: ##EQU1## Here, V.sub.TMO is V.sub.TM when V.sub.SUB =0 V, .epsilon..sub.Si is the dielectric constant of Si (silicon), .epsilon..sub.O is the dielectric constant for vacuum, q is the amount of electron charge, N.sub.A is the amount of impurity concentration of the substrate, of is the Fermi energy level, and C.sub.OX is a gate oxide film capacitance.
Thus, when the substrate potential is applied, the threshold value V.sub.TM of the memory transistor rises. On the other hand, the diffusion layer capacitance lowers when the substrate potential is applied and this is an advantage to the high speed operation of peripheral transistors. For this reason, the substrate biasing method is generally used for memories such as a dynamic random access memory (DRAM). However, in the EPROM or FEPROM, the impurity concentration of the channel section is high and the rise of the threshold value V.sub.TM due to the substrate biasing is large resulting in a large trade-off with respect to the speeding up of peripheral circuit sections, and thus the substrate biasing method cannot be employed.
V) Generally, the formation of the thick insulating film referred to under 3) above employs a selective oxidation method which is called "LOCOS (Local Oxidation of Silicon)". However, when this method is used, erosion resulting in "bird's beaks" occurs in the isolation insulating film toward the channel region, which may also spread to the impurity channel region formed under the insulating film. Consequently, the problem presented is that the narrow channel effect markedly increases with the effective channel width becoming smaller than the initial patterning channel width.
USPTO Backgrounds
USPTO Backgrounds