The use of dynamic logic is an efficient way of increasing circuit speed and reducing die area of integrated circuitry. The basic dynamic gate, shown in FIG. 1, includes a logic structure whose output node is precharged to VDD by a P-type transistor (the "precharge" transistor) and conditionally discharged to ground by an N-type transistor (the "evaluate" transistor). The precharge and evaluate transistors are typically connected to a single phase clock. During the precharge phase, the clock is low and the output node is precharged to VDD. At the completion of the precharge phase, the clock goes high and the path to VDD is turned off while the path to ground is conditionally turned on. In this evaluate phase, depending on the state of the data inputs, the output will either be at a high level or will be pulled down.
This dynamic logic is advantageous in that it generally requires fewer transistors than static logic. These circuits are often cascaded as shown in FIG. 2. However, when many of these circuits are cascaded, delays in propagating the signal through the cascaded blocks can mount.
Referring next to FIG. 3, there is illustrated a sea of logic circuitry having an input and an output, which may be implemented within a portion of a data processing system. Such logic circuitry can be represented by a sea of Boolean equations. Within the sea of logic circuitry, there is a critical path, which for a particular set of designated criteria results in the highest cost for that designated criteria. Quite typically, the primary criteria with which a designer is concerned is the amount of time it takes for a signal to travel from the input to the output. The critical path within the logic circuitry is the path requiring the longest amount of time for the traveling of such a signal. Naturally, other criteria may be utilized such as circuit costs or area.
Nevertheless, it is often desired to minimize the timing required for such a sea of logic circuitry. One of the most fruitful techniques for doing so is to redesign the circuitry along the critical path in order to shorten the amount of time it takes for a signal to travel from the input to the output over such a critical path. Of course, once an identified critical path has been redesigned, another critical path within the sea of logic circuitry may be established.
What is needed in the art is an efficient and flexible system and method for restructuring logic circuitry in order to minimize a particular cost criteria, such as the amount of time it takes for a signal to travel through a particular path within the logic circuitry.
USPTO Backgrounds
USPTO Backgrounds