The present invention relates to voltage regulators, and more particularly to a voltage regulator capable of quickly restoring the normal functioning mode after an abrupt load variation during a stand-by state.
Switching regulators include one or more power switches, components capable of storing energy (inductor and capacitor) and a control circuit, generally including both analog and digital circuits, for driving the power switch(es) to nullify or reduce the error between the output voltage of the regulator and a reference voltage. In certain applications (e.g. in battery powered devices) a high efficiency of the regulator even under low load conditions is important. At low loads the power consumption of the regulator is substantially due to the control circuit, both by the digital and analog stages, because power dissipation in the power switch(es) is negligible. The current absorbed by the logic driving circuit, for loading the capacitance(s) of the control input of the switch(es), is proportional to the switching frequency, while the consumption of the analog portion of the control circuit is substantially independent from the frequency.
To improve the efficiency under low load conditions, it would be necessary to reduce the switching frequency and the power dissipation of the analog stages. Constraints on the size of inductors and capacitors impose the choice of a relatively high switching frequency and the dissipation of the analog blocks cannot be reduced beyond a certain limit, otherwise performance would be excessively penalized. Many architectures of controllers implementing a specific low load functioning mode, different from that used at high load conditions, have been proposed, for modifying the operating parameters. The known approaches that are discussed hereinbelow refer to a current-mode regulator such as that depicted in FIG. 1. The converter may be, for instance, a buck converter, comprising a HS switch and eventually a second LS switch, working as a synchronous rectifier, with a dedicated comparator ZERO_CROSSING COMP for detecting and signaling the zero crossing of the current in the inductor of the control circuit, to make the latter prevent the current in the coil from inverting its direction.
The current mode controller comprises a first feedback loop that makes the current in the inductor equal to a certain programmed value. A second feedback loop (voltage loop) determines the programmed current in function of the integral of the error voltage, to which an eventual proportional contribution is added. Typically, the voltage loop is composed of an error amplifier GM (commonly a transconductance amplifier) and an integration capacitance CCOMP, defining an integrator, optionally with a compensation resistance RCOMP in series thereto when a proportional contribution is required. Usually, the transconductance amplifier is capable of outputting a relatively low maximum current (in terms of absolute value) and proportional to the absorbed current, which on its turn does not depend on the voltage error (because the amplifier is a class A amplifier).
The current loop includes current sensing means/unit, represented by a circular dial on a terminal of the inductor, and by a comparator CURRENT COMPARATOR that compares a voltage proportional to the current in the inductor (for example, the voltage drop on a sensing resistor connected in series with the inductor or alternatively on the HS switch when it is on), with the output voltage of the transconductance amplifier that may be attenuated if needed. A clock signal, generated by an oscillator OSCILLATOR, switches on the switch HS while the comparator switches it off when the current flowing in the coil reaches the programmed value. A further ramp signal generated by the circuit SLOPE GEN is input to the comparator for ensuring the stability of the current loop when the duty-cycle is greater than 0.5.
The voltage loop is stable when the overall transfer function GLOOP(s) between the current in the inductor and the programmed current has a certain shape (appropriate cross frequency and phase margin) independently from the capacitance and the parasitic series resistance ESR of the output capacitor COUT. This implies an appropriate choice of the capacitance CCOMP and of the compensation resistance RCOMP. In general, a compensation resistance is required when the zero frequency of the output capacitance                               f          OUT                =                  1                      2            ⁢                          π              ·                              C                OUT                            ·              ESR                                                          (        1        )            
is very high.
A known technique for improving efficiency at low load includes making the regulator function in burst mode when the load current drops below a certain burst threshold. Each burst may be constituted by a plurality of pulses of the same frequency at which the regulator would be functioning with a load greater than the threshold, or, even, by a single pulse. In case there are more pulses, their number may be fixed or variable with the load.
In the interval between a burst and the successive one, the current in the inductor becomes null. The (average) current in the inductor during a burst must be at least equal to the current delivered to the load. Between a burst and the successive one, some of the analog circuits may be turned off, so that the effective average consumption of the controller diminishes when the load decreases. At null load conditions, only the analog blocks that cannot be turned off absorb a current, such as the reference voltage generator, and the components necessary to restore the switching activity.
When the burst is constituted by a single pulse, that is the current in the coil has a triangular waveform, the current peak must be at least twice the burst threshold IBURST. When there are more pulses in a burst, the greater the number of pulses, the smaller each current peak may be than twice the burst threshold IBURST. If each current peak is made equal to the burst threshold IBURST, the system must be capable of varying the number of pulses of the burst in function of the load. At low load conditions there will be few pulses, while when the load increases and approaches the threshold there will be longer lasting bursts. This second mode is less noisy than the approach contemplating a single pulse because of the smaller peak current and for this reason it is often preferred.
A way for implementing a variable duration burst mode under low load conditions is depicted in FIG. 2. A hysteresis comparator SLEEP COMPARATOR compares the output of the integrator that is proportional to the programmed current, with a threshold corresponding to the load current below which the burst mode functioning starts. The stand-by signal SLEEP generated by the comparator SLEEP COMPARATOR sets (when active) the regulator in stand-by, whereby the power switch HS and various analog circuits are turned off, among which the oscillator, the current comparator and the slope compensation circuit SLOPE GEN. If a second switch LS is present, this is turned on and remains on as long as the current in the inductor is positive, and it is turned off when the current becomes null. The integrating circuit and the reference voltage generator must remain on, instead.
As shown in FIG. 3, during each burst, the current in the coil is close to the burst current and the peak of each pulse varies in the range comprised between the upper IMAX and lower threshold IMIN of the comparator. Between a burst and the successive one, the current becomes null. The voltage of the integrator oscillates about the two thresholds of the sleep comparator and the output voltage oscillates about the reference voltage. The amplitude of the positive and negative over-elongations of the output voltage depends on the separation between the two thresholds, on the output capacitance and on its time constant ESR*COUT and on the capacitive branch RCOMPxe2x88x92CCOMP of the integrator.
The drawback of this known approach is the delay of response to a load transient. When the stand-by interval is long (very small load), the output of the integrator decreases below the lower threshold of the sleep comparator, to the negative saturation point of the integrator. If a load transient takes place during the stand-by, it is necessary to wait for the output of the integrator to reach the upper threshold before the switching be resumed. This lag time may be even longer because of the transconductance amplifier inability to deliver a large output current because of design restrictions for limiting power consumption. As a consequence, there may be the risk of a large under-elongation of the output voltage.
Another known type of regulator, depicted in FIG. 4, contemplates the use of a clamp on the output of the transconductance amplifier GM for preventing the output voltage of the integrator, and as a consequence the programmed current, to drop below the burst current IBURST. If the load current is smaller than the burst current, the clamp turns on. The current in the inductor thus remains equal to the burst current, so the output voltage tends to increase. A comparator forces the stand-by state when the output exceeds by a certain quantity the reference voltage. The stand-by state is abandoned when a second comparator, or the comparator SLEEP COMPARATOR that forced the stand-by state itself, if it is a comparator with hysteresis, detects if the output voltage has become lower than the reference. During the stand-by state, it is possible to turn off also the transconductance amplifier GM.
According to this approach, the entering in and the exiting from stand-by (that is the duration of the burst and of the stand-by) are tied to the crossing of appropriately set thresholds by the output voltage, as depicted in FIG. 5, by contrast, according to the previous approach, the thresholds are placed on the programmed current (that is on the integral-proportional error). As a consequence, resumption of the switching caused by load transients occurring during a stand-by is almost instantaneous. However a drawback of this approach is that the duration of the burst may be hardly controlled as a function of the distance of the thresholds (amplitude of the hysteresis) of the sleep comparator SLEEP COMPARATOR when the parasitic resistance ESR of the output capacitor COUT is relatively high.
The duration of the burst TBURST is approximately given by                               T          BURST                =                              C            OUT                    ·                                                    Δ                ⁢                                  xe2x80x83                                ⁢                                  V                  OUT                                            -                              ESR                ·                                  I                  BURST                                                                                    I                BURST                            -                              I                OUT                                                                        (        2        )            
wherein IOUT is the load current and the variation of the output voltage xcex94VOUT is supposed to be greater than ESR*IBURST. By contrast, in the regulator of FIG. 2 the dependence on the resistance ESR is far less marked. This is due to the fact that, given that the regulator is properly compensated, the transfer function GLOOP(s) between the current in the inductor and the programmed current does not depend on the value of the resistance ESR.
A further drawback is represented by the high accuracy that the integrator and the comparator for determining the output voltage must have. To make the system work correctly, the separation between the thresholds must be greater than the difference between the offsets of the integrator and of the comparator. To not excessively separate the two thresholds, which would cause an excessive output ripple, it is necessary to determine with high precision both the offset of the comparator and the offset of the integrator. Even in this respect the previous approach is preferable because the offset of the comparator determines in that case only the accuracy of the burst threshold.
A third known regulator, shown in FIG. 6, responds more promptly (than the regulator of FIG. 2) to load variations during the stand-by state because it disconnects the integration capacitance (and its parasitic series resistance) from the output of the transconductance amplifier during the stand-by state and charges it with a voltage PARKING VOLTAGE greater than the stand-by threshold voltage. In this way, during the stand-by state, the transconductance amplifier GM is loaded only by its parasitic output capacitance toward ground and behaves practically as a comparator of the output voltage with the reference voltage. The stand-by state finishes practically when the output voltage becomes smaller than the reference voltage.
An object of this invention is to provide a burst controlled voltage regulator wherein the duration of each single burst does not depend sensibly on the time constant and on the capacitance of the output capacitor and that ensures a fast response to load variations.
The invention stems from the recognition that a reason for the poor precision with which the duration of the burst is determined in a known regulator of the type depicted in FIG. 4, is that the sleep comparator is connected to the output node. Because of this, the burst period depends on the parasitic series resistance ESR of the output capacitor. It has been found that, if a minimum current clamp is connected in parallel to the capacitive branch, the current circulating in the clamp is a function of the difference between the output voltage and the reference voltage. Therefore, it is not necessary to connect the sleep comparator to the output node, but it is possible to input to it a signal representative of the current circulating in the clamp to resume from a stand-by state when the voltage decreases below a certain value, or to enter a stand-by state when the output voltage exceeds a certain value.
More precisely, the present invention is directed to a regulator of the supply voltage of a load comprising an inductor driven by a power stage, connected between a node at a non regulated supply voltage and a ground node, including at least a power switch for connecting the inductor to the node at a non regulated supply voltage, an output capacitor having a certain parasitic series resistance connected between the output node of the regulator and ground, an integrator of the error voltage, a clamp connected to the output of said integrator, a comparator with hysteresis of the current circulating in said clamp producing a stand-by signal when the current exceeds a certain threshold. The integrator, the consumption of which may be reduced by the stand-by signal, has a capacitive integration branch and generates a feedback signal proportional to the integral of the difference between the reference voltage and the output voltage. Dedicated circuit means generate a signal proportional to the current circulating in the inductor and a current comparator, which is disabled by the stand-by signal, is input with the feedback signal and with the signal proportional to the current circulating in the inductor and generates a logic comparison signal. A control logic, input with the logic comparison signal and the stand-by signal, drives the switch or the switches of the power stage. A clamp, connected in parallel to the capacitive branch, makes the feedback signal greater than a certain minimum threshold, to make the current that is delivered to the load, when the regulator is not in the stand-by state, greater than a certain minimum current.
The regulator of this invention is not affected by the above discussed drawbacks of the known regulators because it comprises circuit means for detecting the current circulating in the clamp and generating a signal representative of the sensed current, and the comparator with hysteresis has an input coupled to the signal representative of the current circulating in the clamp for activating the stand-by signal when the current circulating in the clamp exceeds an upper threshold and disabling it when this current diminishes below a lower threshold.
Optionally, the integrator comprises a transconductance amplifier input with the difference between the regulated supply voltage and the reference voltage, and a capacitive integrating branch connected between the output of the transconductance amplifier and the ground node of the regulator.
USPTO Backgrounds
USPTO Backgrounds