Chemical-mechanical polishing (CMP) is widely employed to planarize ILD layers used to isolate metal connections formed from patterned metal layers deposited on semiconductor wafers. Planarization of ILD layers by CMP is a technique that relies on the removal of oxide from the wafer surface at locally different rates. The local rate of removal of oxide depends on the pattern density of the patterned metal layer and/or underlayer. In this context, the underlayer corresponds to the surface on which the patterned metal layer and the ILD layer are formed. With the proper amount of polishing under well-controlled pad, slurry, and surface speed conditions, all local steps are removed from the surface of the ILD layer. Local planarity is essentially 100%.
The long-range behavior with CMP is also significantly improved over competing smoothing techniques such as resist/spin-on-glass etchback or deposit-etch-deposit, i.e., dep-etch-dep, processes. CMP, however, offers less than perfect planarity. Global planarity ranging from 60% to. 80% is typical for CMP of surface features present in ILD layers in logic/memory devices. In this context, global refers to the area defined by repeating die or reticle patterns and global planarity of 60% to 80% corresponds to a planarized surface being 60% to 80% more planar than the surface topography measured across a reticle pattern or stepper field before polishing.
Nevertheless, as a means of ILD planarization, chemical-mechanical polish offers significant processing advantages. The combination of local planarity and low-defect processing improves metal yields by reducing shorts from tungsten stringers and nodules. Furthermore, the much-improved planarity over the range of the stepper field assists in printing deep-submicrometer geometries where depth-of-focus limitations become important.
The issues that must be understood, characterized, and controlled with ILD polish planarization fall into two categories: (a) a process must always achieve local planarity while maximizing global planarity; and (b) a process must result in a controlled, uniform, and reproducible ILD thickness.
What is needed is a method for characterizing and developing polish processes for specific semiconductor product wafers that achieves local planarity while maximizing global planarity and results in a controlled, uniform, and reproducible ILD thickness.
USPTO Backgrounds
USPTO Backgrounds