1. Field of Invention
This invention is generally related to a process for fabricating a Thin Film Transistor (TFT) in a Liquid Crystal Display (LCD). Especially, this invention is related to a TFT composed of polycrystalline silicon and having an off-set area or a lightly doped drain (LDD) structure.
2. Description of Related Art
An LCD is comprised of two substrates with liquid crystals interjected therebetween. An LCD is controlled by applying voltages to electrodes formed on the inside surface of substrates. It displays images by controlling the transmission and interception of lights, taking advantage of the relationship between the alignment of the liquid crystal layer and a polarizor. The liquid crystal layer's alignment is controlled by the electric field applied through the TFT. An LCD employs a retardation film, a reflecting plate and color filters for its image display. A lot of efforts are devoted for a better LCD in improving a polarizer, an alignment layer, an electrode composition, a glass substrate and a rubbing technique.
A pixel circuit, a display unit of LCD, is controlled by a transistor made of a semiconductor thin film on a glass substrate. TFT LCDs can be categorized into two types by characteristics of the semiconductor thin film. One type is an amorphous Si type TFT and the other is a polycrystalline Si type TFT. Amorphous Si type TFT has advantages that it can be formed at a low temperature, while having disadvantages that it has a lower carrier mobility. Usually, an amorphous Si type TFT is used for a switch transistor of a pixel circuit. This means that a driver circuit, which needs a higher carrier mobility, should be fabricated in a separate polycrystalline silicon process, resulting in a cost increase.
Polycrystalline Si has a high carrier mobility necessary for a driver circuit, so it can be used for both a driver circuit and a pixel circuit if a high temperature in fabricating a polycrystalline Si layer is not a problem. A polycrystalline Si structure would decrease the power consumption and the manufacturing costs. However, polycrystalline Si layer requires an additional step of the laser annealing of an amorphous Si layer and may not maintain a sufficient electric field in the pixel region because the high carrier mobility renders an excessive off current flow when the TFT is turned off.
FIG. 1 shows a vertical section of a conventional thin film transistor. An insulation layer (100) as a buffer layer lies on the substrate (10). An active area (200) formed of a semiconductor film lies on the insulation layer and a gate insulation layer (300) lies on the active area. Gate (410) lies on the gate isolation layer over the center of the active area. Source area and drain area (211, 213) are formed in an active area using the gate as implantation mask.
Current flows from source to drain when the transistor is turned on, and the display signal is applied to a pixel circuit connected to the drain. However, in a polycrystalline Si TFT, once the transistor is turned off, display signals can not be maintained in the pixel because a lot of off-currents are flowing when the transistor is turned off due to the high carrier mobility of polycrystalline Si. Usually an LDD (Lightly Doped Drain) or an off-set area that is not doped are used as a barrier structure between channel and source (or drain) to suppress the off-current.
The challenges in manufacturing a polycrystalline Si type LCD having a driver circuit and a pixel circuit on the same glass substrate are how to form a barrier structure in an N-channel TFT; how to mask the P,N ion implantation; and how to minimize the process steps.
In order to form a barrier structure, a conventionally used ion implantation mask is a photo resist pattern, a spacer around the gate, or an oxidized gate metal edge. However, a photoresist pattern as an ion implantation mask renders aligning difficulties, and is not cost effective. Also a photo resist pattern may not stand out the heat generated during the high energy ion implantation. A spacer requires an extra deposition and an etch-back of CVD (Chemical Vapor Deposition) layer. Using an oxidized gate metal edge requires an additional mask in order to prevent other areas from oxidation. Also, the device may be partially damaged during the anisotropic dry etching and extra oxidation process.
USPTO Backgrounds
USPTO Backgrounds