Phase-locked loop (PLL) integrated circuits produce an oscillator frequency output which matches an input frequency signal or matches multiple times of input frequency. A typical PLL may include a phase-frequency detector, a charge pump, and a voltage-controlled oscillator.
FIG. 1 is a block diagram of a typical phase-locked loop (PLL) circuit. PLL 100 includes phase-frequency detector (PFD) 112. PFD 112 detects the difference in phases and frequencies of two input signals, Ref_CLK and FB_CLK. From the difference detected, PFD 112 generates difference signals. Difference signals generated include positive current source, UP, and negative current source, DN (or ‘DOWN’). Current sources UP and DN provide input to charge pump 114. Using current sources UP and DN, charge pump 114 generates a proportional charge. Thus, charge pump 114 provides a voltage to voltage-controlled oscillator (VCO) 116. VCO 116 generates a periodic signal according to input voltage at Node_N. This periodic signal may be referred to as PLL_Out.
This periodic signal generated by VCO 116, PLL_Out, is input to configurable frequency divider 118. For example, if given Ref_clk is 500 MHz when the frequency desired at PLL_Out is 1.0 GHz, a dividing ratio of ‘2’ may be selected. Alternately, when PLL Out is desired to be 2.0 GHz, a dividing ratio ‘4’ may be selected. As other examples, configurable frequency divider 118 may be configured with a dividing ratio of 1, 2, or 3. The output of VCO 116 is provided to frequency divider 118 en route to the feedback input to PFD 112. Thus, PLL_Out is input to feedback divider 118, and FB_CLK is output from feedback divider 118.
Phase-locked loops of the type depicted above are widely used in digital electronics, signal telemetry, and communications applications. Many applications require phase-locked loop (PLL) circuits which will work with high frequencies. In particular, PLL circuits are often utilized with semiconductor devices. More specifically, PLL circuits may be utilized in what is commonly referred to a system on a chip (SOC).
A system on a chip may be a chip, semiconductor or integrated circuit that holds substantially all of the necessary hardware and electronic circuitry for a particular system. Depending on the system desired, SOCs may include on-chip memory (RAM and ROM), processor logic, peripheral interfaces, I/O logic control, data converters, and other components that substantially comprise a particular system.
FIG. 2 depicts one embodiment of a system on a chip. Semiconductor 200 may be a microprocessor, as is known in the art. This microprocessor may include various areas of logic utilized in conjunction with various tasks, such as level two cache logic, level three cache logic, load/store units, execution units, instruction issue unit, etc. Additionally, semiconductor 200 may utilize a PLL to provide a clock signal to one or more areas of circuitry or logic on semiconductor 200.
The benefits of implementing a microprocessor as a system on a chip like the one depicted above may include conservation of space as overall chip count is reduced, resulting in system cost reduction and improved performance. These benefits, however, do not come unencumbered. Namely, the close proximity of the components in a system on a chip may sometimes cause problems. More specifically, in the case of system on a chip such as that depicted in FIG. 2, the proximity of circuitry may cause problems with the PLL used to provide the clock signal to circuitry or logic on semiconductor 200.
In some cases, noise from outside the PLL circuit can cause PLL jitter. This noise may be the result of utilization of circuitry or logic in proximity to the PLL circuit. For example, if PLL is placed in proximity to an execution unit, during a particular instruction that execution unit may be relatively heavily utilized. This greater degree of utilization in turn results in relatively more noise being generated by the execution unit and, as PLL may be in proximity to the execution unit, this noise may cause jitter in the PLL circuit.
Additionally, in some cases, because of the placement of logic within semiconductor 200, during relatively heavy utilization of a particular area of logic on semiconductor 200, the PLL on semiconductor 200 may suffer from a power level drop, as these areas are consuming relatively more power during this period of heavy utilization. This power level drop may also induce jitter in the PLL on semiconductor 200 especially if the PLL is connected to the same power line as the logic in use. The PLL on semiconductor 200 typically must compensate for this jitter in order to once again achieve a locked state.
A typical PLL control loop for compensating for these conditions and achieving lock in such situations is depicted in FIG. 3. An instruction is issued at step 300. This instruction may utilize or affect logic on the semiconductor. The issue of this instruction (step 300) results, at step 310, in relatively larger power consumption by the logic and a commensurate increase in the noise produced by the logic, at step 320. This noise or power drop may result, at step 330, in a decrease in the output frequency of VCO 116 of PLL 100. The output of VCO 116 is provided to the feedback input of PFD 112, which at step 340 detects the decrease in frequency by detecting the difference in phases or frequency between the Ref_CLK and FB_CLK inputs. From the difference detected, PFD 112 generates difference signals, resulting, at step 350 in charge pump 114 outputting more voltage. The output of the extra voltage results, at step 360, in an increase of the voltage level at Node N, in turn resulting in PLL 100 once again locking at step 370.
As can be seen, there is a delay between the issue of an instruction which will affect the PLL circuit (by causing a power drop at the PLL or noise in circuitry or logic in proximity to the PLL) and the PLL being able to compensate for the effects of the instruction.
Thus, a need exists for systems or methods which can substantially reduce the effects of the operation of logic on a PLL circuit.
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