Leadframes are commonly incorporated into different types of microelectronic packages including, for example, leaded packages (e.g., Dual Flat Packages/“DFPs” and Quad Flat Packages/“QFPs”) and no-lead packages (e.g., Dual-Flat No-Lead/“DFN” packages and Quad-Flat No-Lead/“QFN” packages). In the case of leaded packages, the leadframe typically includes elongated leads, such as gullwing leads, projecting outwardly and downwardly from the package sidewalls to permit surface mounting to an electronic device or substrate, such as a Printed Circuit Board (“PCB”). Conversely, in the case of no-lead packages, portions of the leadframe may be exposed through the package bottomside to permit surface mounting to a PCB. During manufacture of the microelectronic package, the semiconductor die can be placed onto the leadframe die flags utilizing a pick-and-place tool; the bond pads of the die can be electrically interconnected with the leadframe by, for example, wire bonding; and the die, the body of the leadframe, and the wire bonds can then be overmolded with an encapsulant to complete fabrication of the microelectronic package.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques can be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures can be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.
USPTO Backgrounds
USPTO Backgrounds