1. Field of the Invention
This invention teaches control of doping of the vertical edge transistor of CMOS/SOS to increase the edge NFET threshold voltage to total dose radiation to preclude radiation induced leakage.
2. Prior Art
It is known that the SOS N-channel silicon gate transistor is actually three transistors in parallel. The primary top channel transistor is the intentional transistor and the two parasitic transistors comprise a back channel transistor at the epitaxial silicon-sapphire interface and edge transistor along the edge of the silicon islands -- each of these transistors contributes to the radiation induced leakage.
It is well known to minimize the radiation degradation due to the primary top channel transistor and the back channel transistor. But control of the leakage from these transistors is not adequate because total dose radiation results have consistently shown that edge leakage can often be the dominant source of leakage induced radiation failures.
Conventional implant techniques are used to control the surface doping and thus, the threshold voltage of the top channel transistor. However, it is extremely difficult to control doping of the vertical edge transistor. A direct implant is obviously not possible along the 0.6 micron or so thick edge. But it is known that radiation induced edge leakage currents could be reduced if a technique could be defined for doping the island edges to increase the edge NFET threshold voltage.
SUMMARY OF THE INVENTION
Two techniques have been defined for selectively doping only the vertical NFET transistor surface on vertically edge structures. Boron edge doping is used indirectly as derived from multiple implants into the silicon and laterally diffused prior to island etching. The silicon islands are formed and their edges are verticalized by reactive ion etching. The active regions of the NFETs are shielded by silicon nitride, and boron ions are implanted along the edges thereof with energies ranging between approximately 20 Kev and 50 Kev using a dose of 10.sup.14 -10.sup.17 ions per cm.sup.2. Two or more implants are established at different energy levels within the, e.g., 20 to 50 Kev in order that a more uniform rather than a peaked distribution will be available. The doping is driven in an inert atmosphere to attain approximately 0.10 micron penetration from each side.
In contrast, a direct boron edge doping is available using high temperature boron nitride processing (wherein photoresist won't take the high temperature and cannot act as a shield to block the PFET leaving only the NFET exposed). Here again, the boron is placed in the edges of the silicon island to adjust the voltage threshold to a high enough value to avoid leakage.
These principles are different from the top surface which has an orientation of &lt;100&gt; because the leakage sides are oriented at &lt;110&gt; or &lt;111&gt; and there is a difference of thickness of oxide and the Q.sub.ss has a different effect on the threshold voltage, but the principles herein teach the use of these two doping methods to produce an edge hardened device.
USPTO Backgrounds
USPTO Backgrounds