This invention relates generally to the field of data communications, and more particularly, is directed to a system for recovering encoded data from a transmitted signal.
Many data encoding and recovering systems known in the prior art utilize a single data encoding scheme such as Split Phase (SPL). Where there are many systems using the same encoding scheme, however, the likelihood of interference is great. Data communications systems known in the prior art address this problem by utilizing an encoding scheme with a start code comprised of None Return to Zero (NRZ) signals of M bits/sec and a data or information code comprised of SPL signals of M/2 bits/sec where M is a predetermined number of bits. The block diagram of a conventional system for recovering such encoded data is shown in FIG. 1, with associated waveforms shown in FIG. 2. In this conventional system, signal AS (see FIG. 2) represents the encoded data signal and is supplied to clock regenerating circuit 1 and sampling circuit 3. Circuit 1 generates clock signal BS which ideally is an exact replica of the clock signal encoded in the data signal but is delayed by 1/2 bit time. Regenerated clock signal BS (hereinafter "clock signal BS") is supplied to selecting circuit 2 and frequency divider 5. Frequency divider 5 divides clock signal BS by two (BS/2) and also supplies it to selecting circuit 2. Selecting circuit 2 provides signal CS to sampling circuit 3. Signal CS is either clock signal BS or BS/2, depending on the status of signal ES which is coupled from start code detector 4 to selecting circuit 2. During the start code portion of data signal AS, signal ES disables frequency divider 5 and conditions selecting circuit 2 to output signal CS equal to clock signal BS. See FIG. 2 where the start code portion of data signal AS is represented by time T1 and signal CS is shown as being the same frequency as clock signal BS. The purpose of sampling circuit 3 is to sample the logic state of data signal AS on the rising edge of signal CS. Because clock signal BS, and thus signal CS, is delayed 1/2 bit time, sampling occurs at the center of each bit in data signal AS. During time T1 (the start code portion of data signal AS as shown in FIG. 2), sampling circuit 3 produces signal DS which is a replica of data signal AS delayed by 1/2 bit time. The end of the start code portion of data signal AS (end of time T1) is detected by start code detector 4 which changes the logic level of output signal ES. Signal ES thus enables frequency divider 5 and conditions selecting circuit 2 to provide signal CS equal to BS/2 as shown during time T2 in FIG. 2. Time T2 is the actual information or data portion of data signal AS. Clock signal CS is thus equal to clock signal BS during time T1 and clock signal BS/2 during time T2. Signal AS is sampled by sampling circuit 3 using clock signal BS/2 during the time T2 (see FIG. 2). Thus the sampling rate is delayed by 3/4 bit time during T2.
As mentioned above, in systems known in the prior art, reproduction of a data signal is done by using a reproduced clock signal whose phase is adequately delayed. The start code part of the signal is sampled at the 1/2 bit time and the information code portion is sampled at the 3/4 bit time. The purpose of sampling at the 1/2 and 3/4 bit time is to improve the signal to noise ratio (S/N) of the system. However, sampling at a single point in each bit does not provide a reliably reproduced signal even though sampled at a delayed bit time. This is especially true for weak signals or signals that are severely interferred with.
USPTO Backgrounds
USPTO Backgrounds