The disclosed subject matter relates generally to manufacturing and, more particularly, to the identification of illegal devices using contact mapping.
In the semiconductor industry many device designers outsource the actual device fabrication process. These designers are referred to as fab-less companies. In some cases, the designer may bid the fabrication process to multiple fabrication foundries. A common problem faced by foundries that manufacture the semiconductor devices is to ensure that the device structures contained in a layout database sent by a customer are actually supported by the current process used by the foundry. Due to late process changes, support for certain device structures might have ended, while the customer layout was not updated accordingly to account for this fact. Also, in the case where a customer is dealing with more than one foundry, the device structures supported by the processes of the different foundries may differ.
If such a layout were to be fabricated, a non-functional device may result from the non-supported device structures. Standard methodology to detect illegal device structures is to use Layout-vs-Schematic (LVS) software to compare the logic design to the layout data. The LVS review compares the schematic netlist and the layout file to determine whether the integrated circuit layout corresponds to the original schematic of the design. In general, LVS employs equivalence checking, which checks whether two circuits perform the exact same function without demanding exact equivalency. The LVS verification process recognizes the drawn shapes in the layout that represent the electrical components of the circuit, as well as the connections between them. The derived electrical components are compared to the schematic netlist to identify errors.
However, because customers do not reveal the schematic to the foundry, the foundry is not able to run LVS on customer designs. Moreover, if the customer uses a foundry as a second source supplier, the customer is usually not willing to rerun physical verification for the second source foundry, as it is expected that the second source foundry matches the process with the first source foundry.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
USPTO Backgrounds
USPTO Backgrounds