1. Field of the Invention
This invention is related to the field of processors and caching, and more particularly to cache management instructions.
2. Description of the Related Art
The rapid increase in operating frequency and performance of general purpose processors has been at the heart of increased computer system performance. At the same time, the amount of system memory (e.g. in the form of dynamic random access memory, or DRAM, of various types) has been increasing in size. However, the memory latency has not decreased to match the increases in processor performance. The latency of memory access is often a performance limiter.
To reduce the average memory latency, caches have been implemented within processors and/or in other locations that are logically between the processors and the system memory. Generally, the caches are small, low latency memories. Recently accessed data is typically stored in the cache, available for low latency access (as compared to system memory latency) by the processors.
While caches were originally designed to be transparent to the software executed by the processors, providing some cache management instructions has become common. The cache management instructions generally permit software to force data from main memory into the cache, or to force data stored in the cache out of the cache (either by invalidating the data in the cache, or writing the data back to the main memory).
USPTO Backgrounds
USPTO Backgrounds