1. Field of the Invention
Embodiments of the present invention generally relate to synthesized frequency generators, and more specifically to charge pump current compensation for phase-locked loop (PLL) frequency synthesizer systems.
2. Description of the Related Art
Many conventional electronic systems require a plurality of signal sources, each with specific frequency characteristics. In certain systems, at least one signal source may need to generate arbitrary frequencies over a relatively wide range. For example, many radio-frequency (RF) transmission systems are required to operate over the full specified range of a given service band. A specific service band may span tens or even hundreds of megahertz (MHz). Such wide operating frequency ranges typically complicate the design of RF circuits used to construct RF transmission systems. A frequency synthesizer is one common RF circuit that is particularly challenging to construct using monolithic manufacturing processes, such as complementary-symmetry metal-oxide semiconductor (CMOS) fabrication. CMOS circuits are typically subject to relatively wide process variation that impacts important circuit parameters, thereby precluding CMOS frequency synthesizer designs that rely on highly precise or tuned circuit elements.
FIG. 1 is a block diagram of a conventional frequency synthesizer 100. The frequency synthesizer 100 typically incorporates a variable frequency oscillator, such as a voltage controlled oscillator (VCO) 116, and control circuitry configured to form a closed-loop feedback control system, such as a PLL, for controlling the frequency of the VCO 116. The control circuitry conventionally includes a phase-frequency detector (PFD) 110, a charge pump 112, a loop filter 114, a feedback divider 120, and a feedback divider control module 122. The PFD 110 continuously generates an error signal that is proportional to detected phase error between two input signals, such as a feedback clock 132 and a reference clock 130. The charge pump 112 operates on the error signal to generate error pulses, which are transmitted to the loop filter 114. The loop filter 114 integrates the error pulses over time, using a low-pass filter, to generate a VCO control voltage 136. The VCO operates in response to the VCO control voltage 136 to generate an oscillating VCO output signal 134 (the primary output signal of the frequency synthesizer 100) with a frequency that is a function of the VCO control voltage 136. The VCO output signal 134 is transmitted to the feedback divider 120, which generates the feedback clock 132. The feedback clock 132 is transmitted to one input of the PFD 110 for comparison with the reference clock 130, which is coupled to the second input of the PFD 110. Using this architecture, the VCO 116 may be controlled in a closed-loop regime to generate an arbitrary multiple of the reference clock 130.
The VCO 116 is typically required to generate a sine wave with relatively high spectral purity. An inductor-capacitor (LC) resonant tank structure may be used within the VCO 116 to establish the output frequency of the VCO 116. A varactor, or any other appropriate voltage-variable capacitor structure, may be used to tune the resonant frequency of the LC tank structure. The useful capacitance range of a varactor is limited and does not typically provide a sufficient operating frequency range for the VCO 116. To extend the operating range of the VCO 116 to meet the frequency range requirements of a given service band, a digitally controlled variable capacitor structure may be added to the LC tank.
Persons skilled in the art will recognize that as the VCO 116 frequency changes, the loop bandwidth also changes, thereby potentially degrading the overall performance of the frequency synthesizer 100. In other words, the overall performance of the frequency synthesizer 100 may be optimized when the effective loop bandwidth is held to an appropriate constant over the full frequency range of the VCO 116. However, process variation in the circuit elements within the frequency synthesizer 100 introduces sufficiently wide component tolerance values that optimal performance over a wide frequency range is not possible by simply picking optimal component values. Instead, component values are typically selected that attempt to generally satisfy operating requirements over a full operating range. As a result, sub-optimal performance is generally attained within the frequency synthesizer at any specific operating frequency.
As the foregoing illustrates, what is needed in the art is a technique for optimizing performance in frequency synthesizers over both process variation and wide VCO frequency ranges.
USPTO Backgrounds
USPTO Backgrounds