1. Field of the Invention
The present invention relates to a voltage generating circuit for a computer, and more particularly to a memory voltage generating circuit for a computer.
2. General Background
In general, a user can make a computer enter various sleeping modes through a user setting in Advanced Configuration and Power Interface (ACPI), in order to protect the computer and save energy.
Typically, an ACPI has various modes as follows: S0, S1, S2, S3, S4, and S5. While a system is in the S0 state, it is in the system working state. That is, all devices, such as processors, dynamic random access memory (DRAM), power resources and etc., are all maintained. The S0 state is further divided into two sub-states, a before (Advanced Technology Extend Power OK) ATXPOK S0 state and an after ATXPOK S0 state. The conversion of the before and after ATXPOK S0 states is instantaneous. While the system is in the S1 sleeping state, which is also called Power on Suspend (POS), processors of the system are not executing instructions. However, the processor-complex context is maintained. The S2 sleeping state is logically lower than the S1 state. And it is assumed to conserve more power. In the S2 sleeping state, the processors are not executing instructions. Meanwhile, the processor-complex context is not maintained. The S3 state, which is familiar to us, is also called Suspend to RAM (STR). It is logically lower than the S2 state. And it is assumed to conserve more power. In the S3 state, all the devices except DRAM are not maintained. Contents of the DRAM can be maintained by hardware. The S3 state is a commonly used power saving state. Then there is the S4 state, which is also called Suspend to Disk (STD), it is logically lower than the S3 state and is assumed to conserve more power. In the S4 state, a system main power is turned off. A copy of memory is saved to a disk. All the devices stop working while the disk has a power supply. The disk is wakened when needed. The S5 state is in the soft off state and requires a complete boot when awakened. In the S5 state, all the devices including the power supply is turned off.
Functions of the commonly used STR state are to save executing information of the system to a memory. In the STR state, a power supply is needed for main devices such as the memory to insure no loss of important data. However, other devices are turned off to save energy. The system is awakened when a power button is pressed, and a previous working state before STR is resumed by the memory.
A memory voltage generating circuit is needed to output a memory voltage in order to obtain the STR state. The memory voltage is 2.6V.
Referring to FIG. 2, a typical memory voltage generating circuit for a motherboard of the computer includes a control module 10, a first voltage generating circuit 12, and a second voltage generating circuit 14. The control module 10 is used to control working states of the first voltage generating circuit 12 as well as the second voltage generating circuit 14. The memory voltage 2.6V is generated by one of the first and second voltage generating circuits under various working states.
The control module 10 includes a bipolar junction transistor (BJT) Q11′ and a BJT Q12′. A base of the BJT Q11′ is coupled to a 3.3V standby voltage (3.3V Vsb) via a resistor R5′. An emitter of the BJT Q11′ is coupled to a terminal 1′ via a resistor R6′ for receiving a first voltage control signal (SLP4_L) from a south bridge chip of the computer. A collector of the BJT Q11′ is coupled to a 5V standby voltage (5V Vsb) via a resistor R7′. A base of the BJT Q12′ is connected to the collector of the BJT Q11′. An emitter of the BJT Q12′ is connected to a terminal 2′ for receiving a second voltage control signal (ATXPOK) from the motherboard power supply of the computer. A collector of the BJT Q12′ is coupled to the 5V Vsb via a resistor R8′. According to power specification of computers, the SLP4_L is a high level voltage when the computer works in the S0, S1, S2, and S3 state. And the SLP4_L is a low level voltage when the computer works either in the S4 or in the S5 state. The ATXPOK is a low level voltage in all the states except the after ATXPOK S0 state. That is, only in the after ATXPOK S0 state the ATXPOK is a high level voltage. In the memory voltage generating circuit, scheduling of working is controlled by voltage control signals of the SLP4_L and ATXPOK.
The first voltage generating circuit 12 includes an integrated circuit (IC) (not shown). The IC outputs a 2.6V standby voltage (2.6V Vsb) as shown in FIG. 2. The first voltage generating circuit 12 further includes a metal-oxide-semiconductor field-effect transistor (MOSFET) Q3′. The MOSFET Q3′ is P-channel-strengthen MOSFET. A drain of the MOSFET Q3′ is a terminal 3′ which outputs the memory voltage 2.6V. The 2.6V Vsb from the IC is input to a source of the MOSFET Q3′. A gate of the MOSFET Q3′ is connected to the collector of the BJT Q12′. Then a reference point A′ is formed between the control module 10 and the first voltage generating circuit 12.
The second voltage generating circuit 14 includes an operation amplifier U′, an N-channel-strengthen MOSFET Q1′, an N-channel-strengthen MOSFET Q5′, a BJT Q13′, and a BJT Q14′. A system voltage 12V Vcc from the motherboard power supply of the computer is provided as a working voltage of the operation amplifier U′. A non-inverting input terminal of the operation amplifier U′ is connected to the 2.6V Vsb as a reference voltage via a resistor R1′. An inverting input terminal of the operation amplifier U′ is coupled to a source of the MOSFET Q1′. An output terminal of the operation amplifier U′ is connected to the source of the MOSFET Q1′ via a resistor R2′. A drain of the MOSFET Q1′ is coupled to the drain of the MOSFET Q3′. A negative-feedback loop is formed between the operation amplifier U′ and the output memory voltage 2.6V via the MOSFET Q1′ to ensure a steady output memory voltage 2.6V. A drain of the MOSFET Q5′ is coupled to a system voltage 3V Vcc. A gate of the MOSFET Q5′ is connected to the output terminal of the operation amplifier U′. A source of the MOSFET Q5′ is connected to the source of the MOSFET Q1′. The second voltage generating circuit 14 works when the MOSFET Q1′ and the MOSFET Q5′ are turned on simultaneously. A base of the BJT Q13′ is connected to the reference point A′ via a resistor R9′. An emitter of the BJT Q13′ is grounded. A collector of the BJT Q13′ is coupled to the 5V Vsb via a resistor R10′. A gate of the BJT Q14′ is connected to the collector of the BJT Q13′. An emitter of the BJT Q14′ is grounded. A collector of the BJT Q14′ is connected to a gate of the MOSFET Q1′. The gate of the MOSFET Q1′ is coupled to the ground via a resistor R4′. The gate of the MOSFET Q1′ is connected to the 12V Vcc via a resistor R3′. The MOSFET Q1′ is turned on when the reference point A′ is a high level voltage.
The 5V Vsb, 3.3V Vsb, and 2.6V Vsb are high level voltages at any state. The 12V Vcc and 3V Vcc are at high level only when the computer is in after ATXPOK S0 state. The 12V Vcc and 3V Vcc are at high levels on condition that the ATXPOK is a high level voltage.
A working process of the typical memory voltage generating circuit is as follows: the memory voltage is not used in the S1, S2, and S4 states. In the S5 state, the 12V Vcc, 3V Vcc, SLP4_L, and ATXPOK are low level voltages. The BJT Q11′ of the control module 10 is turned on. A low level voltage is input to the base of the BJT Q12′. The BJT Q12′ is turned off. Therefore, the reference point A′ is at a high level. The 5V Vsb is input to the gate of the MOSFET Q3′. Because the MOSFET Q3′ is a P-channel-strengthen MOSFET, the MOSFET Q3′ is turned off. Therefore, the first voltage generating circuit 12 does not generate the memory voltage 2.6V. As the 12V Vcc and 3V Vcc are at low level, the operation amplifier U′ can not get the working voltage, so the low level voltage is input to the gate of the MOSFET Q5′. Because the MOSFET Q5′ is an N-channel-strengthen MOSFET, the MOSFET Q5′ is turned off. Therefore, the second voltage generating circuit 14 does not work. That is, in the S5 state, there is no need for the memory voltage 2.6V.
In the before ATXPOK S0 state and the S3 state, the ATXPOK, 12V Vcc, and 3V Vcc are at low levels, however, the SLP4_L is a high level voltage, and the voltage of the SLP4_L is higher than 3.3V Vsb when it is in the high level. Therefore, the second voltage generating circuit 14 does not work. The BJT Q11′ is turned off. The 5V Vsb is inputted to the base of the BJT Q12′. The BJT Q12′ is turned on and the reference point A′ is at a low level. Thus, the first voltage generating circuit 12 outputs the memory voltage 2.6V to the terminal 3′.
In the after ATXPOK S0 state, the 12V Vcc, 3V Vcc, SLP4_L, and ATXPOK are all at high levels, and the voltage of the ATXPOK is higher than 5V Vsb. Therefore, the BJT Q11′ and BJT Q12′ are turned off. Thus, the reference point A′ is at a high level. The MOSFET Q3′ is turned off. The first voltage generating circuit 12 does not output the memory voltage 2.6V. The BJT Q13′ is turned on, and the BJT Q14′ is turned off. So the MOSFET Q1′ is turned on. Meanwhile, the MOSFET Q5′ is turned on because of the high level voltages 12V Vcc and 3V Vcc. So the second voltage generating circuit 14 outputs the memory voltage 2.6V to the terminal 3′.
However, the typical memory voltage generating circuit has some disadvantages. That is, there are so many components in the typical memory voltage generating circuit that connections between them are complex. Thus, cost of the typical memory voltage generating circuit is high.
What is needed is a less complex and less expensive memory voltage generating circuit for a computer.
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