A conventional memory device includes a memory cell, complementary first and second lines, a pre-charging circuit, and a sensing circuit. Prior to a read operation of the memory device, the pre-charging circuit pre-charges the first and second lines to a high voltage level. Thereafter, the first and second lines are left floating at the high voltage level.
During a read operation of the memory device, bits ‘0’ and ‘1’ of data stored in the memory cell are respectively transferred to the first and second lines. This pulls the first line towards a low voltage level and keeps the second line at the high voltage level. When the sensing circuit senses a difference between levels of voltages on the first and second lines exceeds a threshold level, the sensing circuit pulls the first line to the low voltage level, whereby complementary bits of the data are read from the memory cell. Such a read operation is relatively slow.
USPTO Backgrounds
USPTO Backgrounds