Protection from electrostatic discharges is almost indispensable for modern integrated circuits. For this purpose, such ICs include special protective circuits, which conduct electrostatic discharges which occur at an input of the circuit, for instance because of touching by a person, away to a supply voltage, for instance earth.
Such an arrangement is shown schematically in FIG. 6. The intention is to protect the circuit part 2 of an integrated circuit from ESD pulses or EOS events which are present at a connection 1, for instance an I/O pad. For this purpose, an ESD protective element 33 is connected between the connection 1 and an earth line (GND) 5. Instead of the earth line 5, another supply voltage line, for instance a positive supply voltage VDD, can be chosen, and moreover a protective path between a positive supply voltage and earth can be considered by analogy. Below, only a protective path between an input or output and earth is considered explicitly. For the other stated possibilities, the following applies by analogy. The ESD protective element is a component which in normal operation of the circuit has blocking behaviour, but if a critical voltage Uc such as occurs, for instance, in the case of ESD or EOS events is exceeded, has low resistance. The corresponding ESD/EOS pulses are thus diverted to earth, as indicated by the arrow 12. Examples of such components are Zener diodes or correspondingly wired MOS components.
In normal operation of the component, i.e. in the non-conducting state, such an ESD protective element 33 is usually only permitted for a specified voltage range. Operation outside this voltage range over a relatively long period is not allowed, for reliability reasons. For the arrangement shown in FIG. 6, this means a restriction of the permitted signal voltage range at the connection 1, and thus a restriction of the functionality of the circuit to be protected.
Furthermore, the permitted operating voltage of the components and thus also of the ESD protective elements falls with each new technology generation. On the other hand, the signal ranges of standard I/O interfaces such as PCI or USB are maintained over several generations. Thus, for instance, even in a 1.5 V CMOS technology, 3.3 V interfaces must be made available.
One possibility for solving this problem is to connect multiple protective elements in series, to achieve a lower voltage drop at the individual element. Examples of this are shown in FIG. 7. FIG. 7A shows a series circuit of two ESD protective elements 33a and 33b, so that the voltage drop at each individual ESD protective element is reduced compared with the circuit shown in FIG. 6. In FIG. 7B, the intention is to achieve a reduction of the dropping voltage at the ESD protective element 33 through one or more diode cutoff voltages of diodes 32. The diodes which are used can be bipolar pn or CMOS diodes. Additionally, the concept which is presented below can be transferred to a series circuit with CMOS or bipolar transistors.
In the case of such approaches with individual elements connected in series, there is the problem that an effective division of the total voltage drop to the individual elements of the protective circuit can be guaranteed only with a defined current flow, for instance to set an operating point of the diodes 32 in the series circuit. For instance, in the case of the series circuit of diodes 32 with an NMOS-based protective element 33, the “natural” leakage current is typically only between 1 nA and 1 μA, resulting in a voltage drop of only a few 10 mV or 100 mV per diode threshold. Thus the voltage drop at the protective element 33 is only insignificantly reduced, so that there is a danger of damage or degradation of the protective element in normal operation of the circuit, i.e. in blocking mode of the ESD elements, for instance in the case of an NMOS-based protective element by endangering the gate oxide.
Another ESD protective arrangement, which can tolerate different operating voltages, for integrated circuits is known from U.S. Pat. No. 5,719,737. This protective arrangement is specially designed for protection of a power supply of the integrated circuit. The circuit arrangement which is disclosed there uses a voltage divider to reduce the voltage which drops at one ESD protective element.
USPTO Backgrounds
USPTO Backgrounds