The present invention relates to hierarchical memory systems, and, in particular, to systems and methods for performing built-in self test (BIST) of hierarchical memory systems.
Hierarchical memory systems include multiple memory blocks arranged in a hierarchical topology. Hierarchical memory systems are used in devices, such as search accelerators, in which large amounts of data are to be searched quickly and efficiently. That is, data structures can be stored in hierarchical memories in a manner that enables fast and efficient searching. For example, a b-tree data structure can be efficiently searched when stored in a hierarchical memory, as described in U.S. patent application Ser. No. 11/934,240 filed Nov. 5, 2007 entitled “Integrated Search Engine Devices That Support Efficient Default Route Match Detection And Handle Management In Multi-Way Trees,” which is assigned to the assignee of the present invention.
Hierarchical structures are commonly used in content addressable memory (CAM) devices. In many memory devices, such as random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in CAM devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition: In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry.
An exemplary CAM device that utilizes a priority encoder to identify a highest priority matching entry is disclosed in commonly assigned U.S. Pat. No. 6,370,613 to Diede et al., entitled “Content Addressable Memory with Longest Match Detect.” Additional CAM devices are described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and in U.S. Pat. Nos. 6,101,116, 6,256,216, 6,128,207 and 6,262,907 to Lien et al., assigned to the present assignee.
In order to verify that the logic circuits of an electronic device, such as the memory blocks of a hierarchical memory, are operating properly, it is desirable to provide test circuitry in the devices. The test circuitry can be used for performing Built-In Self Test (BIST) of the memory devices. In addition, the test circuitry may be designed to permit external testing, such as field testing of an installed memory by a customer.
A standard interface for production and field testing of electronic devices has been defined in Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1: Standard Test Access Port and Boundary Scan Architecture. This standard was developed based on recommendations by the Joint Test Action Group (JTAG), a group of silicon device manufacturers, and is commonly known as the JTAG Boundary Scan Architecture.
The JTAG architecture was designed to provide pin-level access to a logic circuit, providing test circuitry virtual control over the operation of the circuit. In this manner, faults, such as logic faults, memory cell faults, and even fabrication faults, such as cold solder joints and improper wire bond connections, could be discovered and isolated.
Although initially designed for printed circuit boards, the JTAG architecture can be used for accessing sub-blocks of integrated circuits. Moreover, as mentioned above, the JTAG interface can be used as a production testing/debugging tool as well as a field testing tool. When used as a debugging tool, an in-circuit emulator can use the JTAG interface as a transport mechanism, enabling access to an on-chip debug module.
The internal registers of an integrated circuit (IC), such as a memory cell, may be placed on a JTAG boundary scan chain, which allows the combinational logic of the circuit to be field tested after the IC is installed in a production system. When combined with BIST circuitry, the JTAG boundary scan interface enables low overhead, embedded testing of an IC for static faults.
A conventional JTAG-enabled device 10 is illustrated in FIG. 1. As shown therein, the device 10 includes a core logic block 12 that is accessed through a plurality of input/output (I/O) pads or lines 14. A Boundary Scan Register (BSR) including a plurality of boundary scan cells 16 is provided between the core logic block 12 and the I/O pads or lines 14. The boundary scan cells 16 provide pin-level access to the core logic block 12, which permits the test circuitry to read and write data to/from the core logic block 12 at pin level.
That is, the BSR provides a serial scan path that intercepts signals between the core logic block 12 and the I/O pads or lines 14. In normal operation the boundary scan cells 16 are invisible. However, in test mode the boundary scan cells 16 can be used to set and/or read values of the core logic block 12.
The JTAG interface, collectively known as a Test Access Port, or TAP, uses a number of defined signals and registers to support the boundary scan operation. Boundary scan operations are generally controlled by a TAP controller 18, which is a state machine whose transitions are controlled by the TMS (“test mode select”) signal. The TCK (“test clock”) signal carries the test clock, which synchronizes the internal state machine operations.
The TDI (“test data in”) signal represents the test data shifted into the test or programming logic of the device 10. The TDI signal is sampled when the internal state machine is in the correct state. The TDO (“test data out”) signal represents the data shifted out of the test or programming logic of the device 10. The TRST (“test reset”) signal is an optional signal that is used to reset the state machine of the TAP controller 18.
There are two types of registers associated with boundary scan—instruction registers and data registers. A JTAG-compliant device has one instruction register and two or more data registers.
The instruction register 20 holds the current instruction, which is used by the TAP controller 18 to decide what to do with test signals that are received. Typically, the content of the instruction register 20 identifies the data registers signals to which test signals should be passed.
There are three primary data registers in a JTAG interface: the Boundary Scan Register (BSR), composed of the boundary scan cells 16, a BYPASS register 22 and an IDCODES register 24. Other data registers 26 may be present.
The BSR is the main testing data register, and is used to read/write data to/from the core logic block 12.
The BYPASS register 22 is a single-bit register that causes information to be passed directly from TDI to TDO, allowing other devices/blocks in a circuit to be tested with minimal overhead.
The IDCODES register 24 contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file, which contains details of the Boundary Scan configuration for the device.
The IEEE 1149.1 standard further defines a set of instructions for operating the interface. The BYPASS instruction causes the TDI and TDO lines to be connected via a single-bit pass-through register (the BYPASS register 22).
The EXTEST instruction causes the TDI and TDO to be connected to the Boundary Scan Register (BSR). The device's pin states are sampled and new values are shifted into the BSR. These values are then applied to the pins 14.
The SAMPLE/PRELOAD instruction causes the TDI and TDO to be connected to the BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be accessed by a data scan operation to take a sample of the functional data entering and leaving the device. The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction.
The INTEST instruction causes the TDI and TDO lines to be connected to the Boundary Scan Register (BSR). While the EXTEST instruction allows the user to set and read pin states, the INTEST instruction relates to the core-logic signals of a device 10.
Multiple devices can be connected in a daisy-chain fashion, permitting testing of multiple logic blocks through a single JTAG interface. Referring to FIG. 2, three devices (Device 1, Device 2 and Device N) are connected in a daisy-chain configuration. The devices Device 1 to Device N may represent separate IC chips and/or separate logic blocks of a single IC chip. The TMS and TCK signals are applied in parallel to each of the connected devices. The TDI signal is applied to Device 1, while the TDO signal output by Device 1 is supplied as the TDI signal of Device 2, and so on. While three devices are illustrated in FIG. 2, it will be understood that many more devices may be connected in the chain. In this manner, efficient testing of multiple devices may be accomplished through a single interface, which may be externally accessible to permit field testing of devices.
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