The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to solder bump connections and methods for fabricating solder bump connections during back-end-of-line (BEOL) processing of semiconductor chips.
A chip or die includes integrated circuits formed by front-end-of-line (FEOL) processing and metallization levels of an interconnect structure formed by back-end-of line (BEOL) processing. Chips are then packaged and mounted on a circuit board. Solder bumps are commonly utilized to provide mechanical and electrical connections between the last or top metallization level and the circuit board. A common type of solder bump is the controlled collapse chip connection (C4) solder bump. Controlled collapse chip connection (C4) processes are well known in forming solder bumps in semiconductor fabrication. During assembly of the chip and circuit board, C4 solder bumps establish physical attachment and electrical contact between an array of C4 pads on the chip and a complementary array of C4 pads on the circuit board.
Conventional solder bump connections employ a technique called ball limiting metallurgy (BLM) in which layers of a particular group of metals can promote the attachment of the C4 solder bump to the chip. These “BLM layers” can promote adhesion between an underlying dielectric passivation layer and a metal pad, promote solder wetting, and act as a solder diffusion barrier. A variant of the C4 process, such as disclosed, for example, in U.S. Pat. No. 7,825,511 and/or U.S. Patent Application Publication No. 2012/0146212, the disclosures of which are incorporated by reference, eliminates the use of an aluminum (Al) pad structure as a cost-saving measure in chip fabrication. Instead, the aluminum (Al) pad structure is replaced with a process and structure that makes use of a thick layer of Cu to completely fill the final polyimide via opening to comprise the chip side interface structure for the C4 chip-to-package interconnect. This “plug via” formation process can employ a relatively thick Cu layer deposited directly on a cured, final level polyimide (PI) layer, which can then be planarized using chemical mechanical polishing (CMP) to leave a plug of copper within the final PI structure. The final via plug can be used in conventional under bump metallurgy (UBM) and/or C4 processes and can make an electrical connection between a resulting solder bump and the final copper metallization level in the BEOL without an aluminum pad. The plug via process offers significant advantages over other techniques, including allowing fabrication of structures on a smaller level than previously achieved, but efforts continue to improve plug via processes and semiconductor device manufacture as a whole.
USPTO Backgrounds
USPTO Backgrounds