The present invention generally relates to so-called charge-coupled devices and more particularly to a process and circuit for eliminating noise from the output of a charge coupled device.
FIG. 1 shows a typical conventional charge-coupled device (CCD) 10 and an output circuit cooperating therewith. Referring to FIG. 1, there is provided a CCD transfer channel 1 for transferring electric charges formed by individual CCD active elements not illustrated, a buffer circuit 2 for detecting the transfer of electric charges and for producing an output voltage in response thereto, and a reset transistor for resetting the buffer circuit 2. The buffer circuit 2 detects the transferred electric charges by detecting the voltage appearing at a diode 5 that is provided at an end of the channel 1 for collecting the transferred electric charges. More specifically, in correspondence to the transfer channel 1, there are provided a number of transfer electrodes 4 of the CCD active elements, and the electric charges produced by the CCD active elements are transferred from one element to another in response to application of transfer clocks .phi.1 and .phi.2 that have respective phases shifted from each other. Thus, in response to every one period of the transfer clock .phi.1, the electric charges flow into the diode 5 and causes a change in the voltage at the diode 5 that in turn is detected by the buffer circuit 2.
In the circuit of FIG. 1, there is provided a reset transistor 6 between the diode 5 and the buffer circuit 2 for resetting the voltage produced at the diode 5. The transistor 6 has a gate electrode 6 that is supplied with a reset pulse .phi.r with a period identical to the period of the transfer clocks .phi.1 and .phi.2. Thus, when the transistor 6 is turned on in response to the reset pulse .phi.r, the output voltage of the diode 5, i.e., the input signal to the buffer circuit 2 is reset.
FIGS. 2(A)-(C) are waveform diagrams for explaining the operation of the circuit of FIG. 1, wherein FIG. 2(A) shows the reset pulse .phi.r, FIG. 2(B) shows the transfer clock .phi.1, and FIG. 2(C) shows the waveform of output of the diode 5.
Referring to the drawings, the voltage appearing at the diode 5 is forcedly increased to the level of +V volt that is the drain voltage of the reset transistor 6 in an interval between a time t0 and a time t1 during which the transistor 3 is turned on. In this interval, it should be noted that the reset pulse .phi.r is set to have a high level state. Next, the transistor 3 is turned off at the time t1, and in response thereto, the voltage appearing at the diode 5 is set at a predetermined, reference voltage level Vo that is determined by a capacitance 7 and a gate-source capacitance of the reset transistor 3. Here, the capacitance 7 is formed by the capacitance of the diode 5 and the gate-source capacitance of the buffer circuit 2. Next, at a time t3, the electric charges are caused to flow into the diode 5 and the voltage at the diode 5 is changed from the foregoing level Vo to an output voltage level Vs. This voltage level Vs represents the output of the CCD active element and is outputted after amplification in the buffer circuit 2 as an output voltage of the CCD device 10. Thus, in response to the repetition of the transfer clocks .phi.1 and .phi.2, the output voltage Vs corresponding to the electric charges produced by the CCD elements are outputted one after another with the reset interval interposed therebetween.
In this conventional construction, there is a problem in that the transistor 3 generates a noise En during the interval in which it is turned on. Thereby, there arises a chance that the noise En modifies the voltage level Vo in a magnitude of .+-.Vn, where Vn represents the reset noise caused by the noise En. When such a modulation or fluctuation of the reference voltage level Vo occurs, the signal-to-noise ratio of the output signal Vs is inevitably deteriorated.
Further, such a source of the noise is not limited to the reset transistor. The buffer circuit 2 also contributes to the formation of the noise that causes the fluctuation of the reference voltage level Vo. The noise that is produced by the buffer circuit 2 has an amplitude generally proportional to the inverse frequency and is known as the 1/f noise.
In order to eliminate or minimize such reset noise and 1/f noise signals, a technique of so-called "double cross-correlational sampling" is proposed according to the Japanese laid-open patent application No. 56-116374, wherein the reference voltage level Vo is clamped, at a time t2 that is later than the time t1 but earlier than the time t3, and the output voltage Vs is obtained by sampling at a time t4 that is later than the time t3. Further, there is a proposal according to the Japanese laid-open patent application No. 62-208375 wherein the output signal of the CCD device is passed through a bandpass filter having a central frequency that coincides to the transfer clock frequency and apply a synchronous demodulation thereto in synchronization with the transfer clocks. According to this latter approach, the noise is reduced in the frequency range that corresponds to the pass-band of the bandpass filter, and thereby an improvement of the signal-to-noise ratio is achieved.
However, the double cross-correlational sampling is effective only for the reset noise signals and the low frequency component of the 1/f noise signals. Further, this approach cannot prevent the reference voltage level Vo that is clamped during the interval between t0 and t1 or the signal voltage Vs from being affected by the random noise that has no correlation. Such random noise signals are formed from the high frequency components of the 1/f noise signals. Further, there occurs other high frequency noise such as ringing noise that is produced when the CCD device is driven at a high speed. Thus, the approach of the double cross-correlational sampling cannot provide a satisfactory solution to the problem of the noise in the output of the CCD devices.
On the other hand, in the case of the synchronous demodulation, there is a problem in that the precise synchronous demodulation is difficult to achieve when the signal waveform of the output of the CCD device is deviated from the sine function significantly. Such a deviation makes it difficult to achieve synchronization. Further, this approach suppresses the low frequency component of the output signal of the CCD device that changes gradually with correlation between picture elements. This problem becomes particularly acute when image signals having gradation is processed. Because of the cut off of the low frequency component, the gradation of the original image cannot be reproduced satisfactorily.
Further, in the case where a sample and hold circuit is employed for processing the output of the CCD device, there arises a problem that a very stringent response is requested for the processing circuit because of the steep leading edge nature of the output waveform of the CCD devices.
USPTO Backgrounds
USPTO Backgrounds