The present invention relates to a semiconductor memory device, a semiconductor device, and a method of manufacturing a semiconductor memory device. In particular, it relates to a semiconductor memory device on which a ReRAM and a DRAM are mounted, a semiconductor device, and a method of manufacturing a semiconductor memory device.
For the purpose of saving data, a technology for mounting a volatile memory and a non-volatile memory on a single conductor chip has been expected. There is a method, for example, in which, using a DRAM (Dynamic Random Access Memory) as a cache, data is written to a NAND flash memory. While the transfer speed of DRAM has been accelerated, the transfer speed of the NAND flash memory is decreasing as its capacity increases. Therefore, in a method where data is written to the NAND flash memory using the DRAM as a cache, there occur problems as follows. That is, the number of the NAND flash memories to which data are written in parallel increases. Also, more electricity is consumed when data are written.
As a non-volatile memory for reducing the difference in speed, a ReRAM (Resistance Random Access Memory), whose writing speed is faster than that of the NAND flash memory, is receiving attention. For example, Non-Patent Document 1 discloses that when a ReRAM is used as a cache memory and a method of sequentially wiring data temporarily stored in the ReRAM to the NAND flash memory sequentially is adopted, power consumption at the time of data writing is reduced by 97% and an acceptable raw bit error rate becomes 3.6 times higher.
The DRAM and the ReRAM have the same MIM (Metal-Insulator-Metal) structures. Therefore, they can be manufactured simultaneously by using the same material. For example, Patent Document 1 (Japanese Patent Laid-open No. 2008-282918 (Corresponding US Application: U.S. 2008280415 A1)) discloses a structure where, between a capacitance element and a variable resistance element, materials of at least one of an upper electrode and a lower electrode are different but the remaining materials are the same and are manufactured in the same manufacturing process. Moreover, Patent Document 2 (Japanese Patent Laid-open No. 2010-55731 (Corresponding US Patent: U.S. Pat. No. 7,995,373 B2)) discloses a technique in which the forming is performed, in a memory cell array of a DRAM, for memory cells in a selected area, and thereby the memory cells are changed to non-volatile memory cells.
[Patent Document 1]
Japanese Patent Laid-open No. 2008-282918
[Patent Document 2]
Japanese Patent Laid-open No. 2010-55731
[Non-patent Document 1]
M. Fukuda, et al., “3.6-Times Higher Acceptable Raw Bit Error Rate, 97% Lower-Power, NV-RAM & NAND-Integrated Solid-State Drives (SSDs) with Adaptive Codeword ECC”, Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp 1166-1167
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