This invention relates in general to the testing and diagnostics of devices, and in particular to systems for testing of the internal nodes of devices.
A semiconductor integrated circuit (IC) is a very complex device. The circuit comprises a multitude of electronic components in a silicon chip. A microprocessor-based IC is frequently a Very Large Scale Integration (VLSI) component, with the number of internal logical components, typically transistors, ranging to more than 100,000. From the design of the IC to its final fabrication, a significant amount of time and effort is used for debugging the device. Testing and diagnostics are needed for design verification, for the checking of timing properties and for quality control in the fabrication process. In addition, testing and diagnostics allow more accurate information to be obtained about the actual performance of a device. Among other things, they allow easier design upgrades to be made to a device.
The IC is usually packaged with a limited number of external pins which are connected internally to the inputs or outputs of the IC chip in order to perform a variety and sometimes large number of functions. Because of the limited number of pins, often it is difficult to exhaustively test nodes buried within a circuit, particularly in the case of embedded state machines. Several methods are commonly used. One way is to use an IC tester for inputting special input sequences that must be followed in order to get certain designated internal nodes into specific test states, and to observe the effect as they propagate to the output pins. These test sequences are typically very different for different ICs and in some cases the IC cannot be driven to the state necessary for some types of tests. In the cases where the IC can be driven to the proper state, the input sequence necessary cannot be generated without using expensive and dedicated IC test equipment. Also the process is very time consuming when checking critical timing of the circuit, since the test sequences must be finely divided (micro-sliced) in order to resolve the timing difference.
Certain components in an integrated circuit are particularly difficult to test. Thus, typically the only way to write test data to a FIFO embedded within the receiver to a serial communications device is via a serial bit pattern which must be encoded in one of the established protocols recognized by the device. The data is then internally decoded and shifted onto a parallel bus before being loaded into the FIFO. Similarly, reading from the FIFO of a transmitter usually involves loading data into a shifter, serializing it, and encoding it into recognized data protocol. The output is a serial bit pattern. Designing a serial pattern for a tester, decoding and encoding, and shifting the data through the FIFO are all time consuming during testing of the device. The encoding and decoding make preparing the test patterns a long process.
One way of testing the internal nodes in a device is to use microprobing techniques which are slow, piecemeal and require expensive equipment.
Another common method of testing the internal nodes related to such embedded state machines is disclosed in U.S. Pat. No. 4,441,075 issued to M. T. McMahon, U.S. Pat. No. 4,494,066 issued to P. Goel et al. and U.S. Pat. No. 4,504,784 issued to P. Goel et al. The method is to include extra logic at the inputs of all flip-flops in the IC that, in test mode, forms a long shift register out of these flip-flops. Data is then shifted serially through this shifter to exercise the random logic between the flip-flops. This obviously takes a significant amount of time and does not make use of existing hardware such as the parallel bus interface on a bus oriented device.
U.S. Pat. No. 4,677,586 issued to Magar et al. discloses various test modes for a microprocessor IC chip. In one example, the internal problem in the ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes. The test mode is triggered by an abnormally high voltage forced onto one of the input pins of the device. This disables normal functions and allows a dump of the contents in the normally inaccessible ROM onto the data bus.
Accordingly, it is a primary object of the invention to provide improved accessibility to the internal nodes via the bus of an IC device under test mode.
It is another object of the invention to provide addressibility to certain sets of internal nodes which are to be accessed.
It is yet another object of the invention to provide a test mode which selects alternative paths for reading data from an addressed set of internal nodes while allowing for the normal functioning of the device.
It is yet another object of the invention to provide a test mode which selects alternative paths for writing test data to an addressed set of internal nodes while allowing for the normal functioning of the device.
USPTO Backgrounds
USPTO Backgrounds