1. Technical Field
The present application relates generally to an improved package design configuration. More specifically, the present application is directed to a method and apparatus for continuously referencing signals over multiple layers in laminate packages.
2. Description of Related Art
A die is an unpackaged piece of silicon containing the functional components of a device. “Die,” also referred to as a “chip” herein, is the formal term for the piece of silicon containing an integrated circuit. A package is a housing that chips come in for plugging into or soldering onto printed circuit boards. The package provides electrical wiring and connections to pins. A lid covers the chip and bonds with the package.
The exemplary aspects of the present invention concern an improved package design configuration with continuous voltage reference for signals transmitted through layers of a laminate package. A discussion of laminate packages follows to provide a context for the exemplary aspects of the present invention; however, the illustrative embodiments described herein should not be limited to any particular package type.
The chip is bonded to the package using, for example, solder, controlled collapse chip connection (C4), or wire bond. Other package configurations are known in the art, such as flip-chip, for example. Creating a mounting for a chip might seem trivial to the uninitiated, but the ability to provide more and more input/output (I/O) interconnections to chips that are shrinking in size and growing in complexity is an ever-present problem.
A common chip package is the dual in-line package (DIP). A DIP is a rectangular chip housing with leads (pins) on both long sides. Tiny wires bond the chip to metal leads that wind their way into spider-like feet that are inserted into a socket or soldered onto a circuit board. A ceramic dual in-line package (CDIP) is a type of ceramic DIP made of ceramic materials. A CDIP package is made of ceramic materials and often uses gold-plated leads attached to two sides by brazing and a metal lid bonded to the package with a metal seal. A CERDIP uses a ceramic lid that is bonded to the package with a glass seal. A plastic leaded chip carrier (PLCC) package is a plastic, often square, surface-mount chip package that contains leads on all four sides. The leads (pins) extend down and back under and into tiny indentations in the housing. A ceramic quad (CERQUAD) package is a substantially square, ceramic, surface-mount chip package. A CERQUAD package uses a ceramic lid that is bonded to the package with a glass seal. A CERQUAD package has pins on all four sides that wrap under like those of a PLCC package.
Flip chip plastic ball grid arrays (FlxI/OTM or FCPBGA) utilize multi-layer organic substrate solutions. The advent of FCPBGA allows a circuit designer to place signal I/O anywhere on the chip. This approach is also known as Area Array I/O or Core I/O. Solder bumps on the active surface of the chip are used to connect to the substrate. The chip is flipped, facedown, and the bumps are soldered to the surface of the package. An array of solder balls on the package fastens to the host circuit board while providing a low inductance electrical path to the board. “FlxI/OTM” is a trademark of LSI Logic Corporation in the United States, other countries, or both.
Land grid array (LGA) is a package that contains terminations on the bottom of the package. The exposed package must be mounted onto a printed circuit board, and proper connections must be made in order for the device to function correctly. One of the main reasons for using land grid array packages and other surface mount connectors is to increase the number of pins that connect within an area of a printed circuit board. With more pins in a small amount of space, one can increase the number of electrical connections between the chip and the printed circuit board. In addition, LGA provides for a shorter distance from the pin to the connection point on the board. This helps to ensure the clarity and quality of the signal by reducing lead inductance and capacitance. With ball grid array (BGA) technology, balls of solder are used to make the package area distributed connections from the chips to the board. BGA provides increased levels of electrical performance. In addition, these products are known to withstand heat better than pins and socket adapters. Other package types are known to those skilled in the art.
A package consists of a plurality of conductive layers separated by insulator layers. The conductive layers may carry a source voltage reference, a ground voltage, or signals provided by chips. It is desirable to situate signal planes in the package between a source voltage (VDD) plane and a ground (GND) plane in the package to provide a voltage reference and shield for signals that come from the chip and travel through the package. Every signal path is part of a closed circuit. If the signal is high, then it is brought up to the source voltage and current must travel to ground. If the signal is low, then it is brought down to ground and current must travel from the source to the ground potential. In either case, the signal must have a return path.
When a signal is transmitted on a signal plane, it is ideal to have a return path, a voltage reference, nearby. Without a voltage reference nearby, the signal will seek out some other return path. That other return path may have different impedance, which will distort the signal, because the difference in impedance changes the amount of signal that gets reflected at the end.
An entire signal path, which must form a closed circuit, can be viewed as a transmission line, such as a pair of conductors. As a signal propagates down the pair of conductors, each new section acts electrically as a small lumped circuit element. In its simplest form, called the lossless model, the equivalent circuit of a transmission line has just inductance and capacitance. These elements are distributed uniformly down the length of the transmission line.
Without a voltage reference nearby, a signal path, which must form a closed circuit, resembles a lossy transmission line model where the sections of the circuit are not uniform. Some sections of the closed circuit may have added impedance. With a lossy transmission line model, there may be reflections from characteristic impedance changes, which degrade the signal being transmitted.
Due to differences in chip design, one chip may be better suited for having the ground plane on top and another chip may be better suited for having the voltage source plane on top. In addition, even though having the source voltage plane on top may provide ideal voltage referencing in an area under a particular chip, having the source voltage plane on top may cause reliability issues in areas away from the chip.
As a particular example, providing vias to lower layers in the package requires breaks in the top layer. For instance, the package design may call for the ground plane to be on top; however, a particular chip may require a high concentration of vias to lower layers, to the source voltage plane or signal planes, in a particular area of a package design. This would result in a break in the voltage reference. That is, due to the chip design and the chosen top layer, the signal layer may pass under holes in the top layer, and in these areas the signal path may not have ideal transmission line characteristics.
A mixed plane design uses one voltage plane on top for certain areas of the package and another voltage plane on top for other areas. For example, one may determine that having the source voltage plane on top is ideal under a particular chip to avoid excess holes in the top layer due to the number of vias necessary to connect to lower layers, while having the ground plane on top is ideal for areas that are not under the chip. In fact, one may determine that one voltage plane is preferred under one chip while another voltage plane is preferred under a second chip on the same package.
The signal plane may have a voltage reference by virtue of being positioned below the source voltage plane and above the ground plane under the area of the chip, for example. In an area that is not under the chip, the signal plane may have a voltage reference by virtue of being positioned below the ground plane and above the source voltage plane in another area of the package. This design may attempt to provide an ideal voltage reference for all areas of the package; however, the signal plane may cross a void where the voltage reference switches or breaks, which causes distortion and degrades the quality of the signal at the receiving end.
USPTO Backgrounds
USPTO Backgrounds