1. Field of the Invention
This invention relates to the field of filters having tunable pole frequencies.
2. Background Art
Many signal processing applications require filters that can operate at high signal rates with a minimum of delay variation. For example, certain disk drive applications, such as constant density recording disk drive schemes, require Bessel-type low pass filters to handle data rates up to 24 megabits per second. These applications generally use continuously tunable pole frequencies (F.sub.0) of up to 13 megahertz. The applications often require less than one nanosecond group delay deviation between DC and F.sub.0. Such applications often also require programmable high frequency boost (commonly known as pulse slimming).
In the prior art, high order filters are realized by cascading second order building blocks (biquads). Pulse slimming can then be theoretically realized by subtracting the output of a variable gain, high pass biquad from its matched low pass counterpart. To accomplish this, the filters must have identical poles in the S plane. One prior art filter is illustrated in FIG. 1. An input voltage, V.sub.I 10 is provided to a low pass filter 11 and to a variable gain amplifier 15. The output 12 of low pass filter 11 is voltage V.sub.LP and is coupled to summing node 13. The output 16 of variable gain amplifier 15 is provided to high pass filter 17. The output 18 of high pass filter 17, V.sub.HP, is provided to an inverting node of summing node 13 so that the output of the high pass filter is subtracted from the output of the low pass filter. The output 14 of node 13 is the output voltage V.sub.0.
Using standard equations for second order filters, phase and group delay can be calculated for the circuit of FIG. 1 as follows: ##EQU1## with s=j.omega., phase and group delay, respectively, given by: ##EQU2## one finds from Equation 1: ##EQU3##
Monolithic high frequency biquads are typically based on transconductances and capacitors. An ideal transconductance is a circuit element that converts an input voltage (or voltage difference) into an output current. FIG. 2 illustrates an ideal transconductance element. A positive voltage V.sup.+ and a negative voltage V.sup.- are provided at the positive and negative inputs of a transconductance element 19. The transconductance element 19 provides an output current 20, I.sub.0. The circuit of FIG. 2 is described by the equation I.sub.0 =GM (V.sup.+ -V.sup.-).
Ideal transconductances are assumed to have infinite input and output impedances (zero admittances). A typical state variable transconductance-C Biquad is illustrated in FIGS. 3a and 3b.
Referring to FIG. 3a, a first transconductance element 21 receives input voltage 10 V.sub.i at its positive input. The output of transconductance 21 at node 22 is coupled through capacitor C1 to ground. Node 22 is also coupled to buffer 23. Buffer 23 may be a level shifter. The output 24 of buffer 23 is provided to the positive input of a second transconductance element 25. The output of the transconductance element 25 at node 26 is coupled through capacitor C2 to ground and to the input of buffer 27. The output of buffer 27 at node 28 is voltage V.sub.LP. This voltage V.sub.LP is coupled in a feedback loop to the negative input terminal of transconductance element 25 and the negative input terminal of transconductance element 21.
Analysis of the circuit in FIG. 3a results in: ##EQU4##
The circuit of FIG. 3a can be implemented in an integrated circuit. However, there may be matching problems when implementing separate low pass and high pass functions. Matching problems can be eliminated by combining the low pass and high pass functions as in the circuit of FIG. 3b. This is accomplished by removing capacitor C2 from ground and feeding the input signal forward through an internal circuit node. The input voltage 10 V.sub.i is provided to the positive input of transconductance element 21 and to variable gain amplifier 29. The output 30 of variable gain amplifier 29 is provided to one terminal of capacitor C2. The other terminal of capacitor C2 is coupled to node 26 (the output of transconductance element 25). The circuit of FIG. 3b can be described as follows: ##EQU5##
The circuits of FIGS. 3a and 3b are accurate models when dealing with ideal transconductances. However, physical transconductance elements are not ideal and have non-zero input and output admittances, creating a parasitic conductance and parasitic capacitance in parallel with each load capacitor as shown in FIG. 4. The circuit of FIG. 4 is substantially the same as the circuit of FIG. 3b with the addition of a parasitic conductance 31 coupled to node 22 and a parasitic capacitance C.sub.P1 coupled in parallel to node 22. In addition, the second transconductance 25 has an associated parasitic conductance 32 and parasitic capacitance C.sub.P2 coupled in parallel to node 26. Transconductance element 21 has an associated output admittance represented by g.sub.01 and C.sub.01 and the second transconductance element 25 has an associated output admittance g.sub.02 and C.sub.02. The buffers 23 and 27 have input admittances represented by g.sub.IB and C.sub.IB.
The parasitic conductance and capacitance at nodes 22 and 26 are given by the following: ##EQU6## or, in case the stages are directly coupled without buffer, ##EQU7##
It should be mentioned that in nearly all practical situations, g.sub.o and C.sub.o dominate.
When these parasitics are included, the transfer function for FIG. 4 is: ##EQU8##
Due to the s-term introduced in the numerator, the biquad's group delay is no longer independent of K. By rewriting the previous equation in its standard form, ##EQU9## the section's group delay can now be expressed as: ##EQU10## A numerical example, representative for an actual design, shows that the error is often unacceptably high. ##EQU11##
Filter implementations are further limited by the large dynamic range requirement of the variable gain amplifier. Typically, input signals are on the order of 1 V.sub.pp and desired gain factors of up to K=5 or more are desired. This requirement is hard to meet in 5 V only designs. Furthermore, gain amplifiers must be kept simple to avoid excess phase that can affect the filter's group delay and degrade performance.
Therefore, it is an object of the present invention to provide a filter and pulse slimmer that compensates for transconductance element non-idealities.
It is another object of the present invention to provide a filter with adequate dynamic range and minimum group delay variation due to variable pulse slimming.
USPTO Backgrounds
USPTO Backgrounds