Today's integrated circuit and computer system designers must carefully weigh tradeoffs between functionality, space and performance in their designs. For example, computer memory subsystem designers have many variables to consider when designing the cache memory architecture of the memory subsystem. Each decision regarding the cache memory architecture will have an impact on overall memory subsystem performance. Generally, the designer's goal is to design a high performance memory subsystem using as little space (e.g. silicon) as possible.
Cache memories are very fast local storage memory arrays used by the central processing unit (CPU). Cache memories are usually significantly faster than main system memory based on their access time and close proximity to the CPU and are, therefore, useful in increasing overall system performance. Recently and/or frequently accessed instructions or data are stored in cache memory on the assumption that they will be used soon. By storing this information in a cache memory, it can be accessed more quickly than going to slower system memory or disk.
Cache memories generally comprise data cache memory, tag memory and cache management logic. Data cache memory is a block of fast memory (usually static random access memory or SRAM) for storage of data and/or instructions and is usually referred to as the "data cache RAM". It should be noted that the word "information" in reference to the contents of a cache memory is used herein to indicate either data or instructions stored in the cache memory. Also, the word "shared" in reference to a cache memory is used herein to indicate that information from two memories, a RAM and an alternative memory in one embodiment, is stored in the same cache memory.
Tag memory comprises a cache tag for each line of cache memory. Tag memory usually comprises a block of SRAM for storing the original logical address of the information stored in the corresponding area of the data cache RAM. In other words, the address stored in the tag memory indicates where the corresponding information in the cache memory originated from in the case of information written to the cache memory from another memory. When the information is written to the cache memory from the CPU, the tag indicates the address in memory that the information is destined for. In many cases, tag memory stores only part of the address. The remainder of the address is indicated by the location in cache memory where the information is stored. For example, a cache memory with cache lines 0-FF may be used to store information from logical address FFFF in main system memory in cache line FF. The cache tag corresponding to that particular location in cache memory would contain the address FF. Thus, the original logical address of information stored in a cache memory can be determined from the cache tag and the location of the information in cache memory in many cache configurations.
Tag memory may also include additional status bits for use by the cache management logic. Examples of status bits used may include a "least recently used" or "LRU" bit to indicate the information that was accessed last in the case of a set associative cache memory. A "valid" bit may be used to indicate whether the corresponding information is valid or a "modify" bit may be used to indicate whether the corresponding information in cache memory has been modified so that it is no longer consistent with the information in system memory or an alternative memory.
Tag memory is often referred to as "tag RAM" or simply the "cache tag". The address portion of the tag RAM is frequently 14 or more bits wide and may include one or more status bits. Generally, there is a cache tag for each line in the corresponding cache memory. Today's cache memories frequently comprise 4000 or more lines. Thus, the tag RAM can be a very sizable portion of the overall cache memory.
Cache management logic performs many functions related to the reading and writing of cache memory. For example, the cache management logic reads the cache tag including both the address and the status bits to determine whether an item in memory requested by the CPU is present in the cache memory. The general architecture and operation of data cache RAM, tag RAM, and cache management logic are well known to those of ordinary skill in the art.
Cache memory is used to store frequently used data and/or instructions for the computer system processor. The information in cache memory is associated with (either is stored from or will be written to) an external memory in the computer system often referred to as main or system memory. Some computer systems, however, are designed with both system memory (usually dynamic random access memory or DRAM) and an alternative memory (usually also DRAM). This alternative memory may be accessible only in a particular mode of the computer system during operation. It is desirable to have a cache memory available to cache both system memory information and alternative memory information to improve system performance.
Prior art systems have approached this design issue in various ways. One method is to use two separate cache memories: one for the system memory and one for the alternative memory. This design is costly in terms of efficiency, space and memory as it requires not only two data cache RAMs, but also two cache tag RAMs and potentially, separate cache control logic.
Another approach shares one cache memory between two memories with non-overlapping logical addresses. In other words, all logical addresses of one memory are different from all logical addresses of the second memory. The cache control logic is able to distinguish between information related to the system memory and information related to the alternative memory based on the address of the information alone. This approach does not work, however, where the logical addresses of the two memories are the same or overlap. General cache control logic only provides for interpretation of address and status fields in the cache tag to manage information reads and writes. Where the logical addresses of two separate memories are the same and they share one cache memory, another method must be used to distinguish between information related to the system memory and information related to the alternative memory.
Where the logical addresses of the system memory and an alternative memory are the same, some prior art designs have added an extra bit to the cache tag to indicate whether the cache information associated with that specific tag corresponds to system memory or to the alternative memory. This method requires an increase in the size of the tag RAM by at least one bit per cache memory line. Cache memories are frequently 256 Kbytes, 512 Kbytes or larger and can contain 4096 or more cache memory lines. Even with an increase of only one bit per cache tag per line, this method can be costly in terms of silicon space.
Another prior art approach uses one of the existing address bits in the cache tag to indicate whether the corresponding cache information is associated with the system memory or the alternative memory. This method is similar in operation to the method described above, but instead of adding an extra bit, this method effectively reduces the cacheable memory. For example, a cache memory with a cache tag providing for 32 bit addresses is capable of addressing 4 gigabytes of memory. When one of the cache tag bits is used to indicate the memory with which the information is associated, the cache memory and the information in the cache tag are only able to indicate 31 bits of address information. 31 bits of address information is capable of addressing only 2 gigabytes of memory thereby effectively cutting the memory addressability of the cache memory in half.
Still another approach is to use one cache memory to cache both memories in a mutually exclusive manner. In other words, the cache memory is used only for system memory when the computer system is in one mode and only for alternative memory when the computer system is in another mode. Using this method, there is no concern for overlapping information that has the same logical address, but there is still a penalty. This method requires that the cache memory is flushed and any inconsistent information is written to the appropriate memory each time the system changes modes. Flushing the cache memory and writing any changed information to memory may require many computer execution cycles and have a measurable impact on overall system performance. This is especially true if the computer system switches between modes frequently.
As will be shown, the present invention provides a method and apparatus for caching two memories that may have the same or overlapping logical addresses in the same cache memory. The present invention provides the advantage of maintaining the size of the address portion of the cache tag, and thus, the amount of cacheable memory, without increasing the overall cache memory size. Additionally, the present invention does not require flushing of the cache memory when switching between modes that utilize the two memories.
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