Integrated circuits (ICs) comprise many transistors and the electrical interconnections between them. Depending upon the interconnection topology, transistors perform Boolean logic functions like AND, OR, NOT, NOR.
ICs and chips have become increasingly complex, with the speed and capacity of chips doubling about every eighteen months. This increase has resulted from advances in design software, fabrication technology, semiconductor materials, and chip design. An increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to specify and design a chip that performs as actually specified. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application.
The challenge of complexity has been met by introducing specialized software tools intended to design chips correctly and efficiently. The software tools have become complex, resulting in “higher levels of abstraction,” which simply means that the logical entities with which designers work are standardized, encapsulated, and bundled together so they can be treated like black box functions.
FIG. 1 is a block diagram illustrating a conventional IC 10 made up of package 12 and die 14. Die 14 is typically a thin silicon-based wafer that is attached to package 12 through various techniques, for example wirebonding and flip-chip, each technique used with different types of packages. Different dies are typically different devices with different functionality, for example an analog-to-digital converter or a memory device.
Die 14 includes rcell fabric 16 that is a medium that contains circuit elements (not shown) and the I/O interface. In IC design, circuit elements bundled together and treated like black box functions may be called hard macros, or “hardmacs.” Hardmac is a generally rectangular cell that may be a complex hierarchical module containing several smaller modules. Hardmac 18 is part of the I/O interface and is intended to control signal transmission between the circuit elements of die 14 and package 12, or, more broadly, to the printed circuit board (PCB) (not shown) to which package 12 is attached. Hardmacs 18 are difficult to design and therefore expensive.
Hardmacs 18 typically align with and connect to bit slices 20 in a 1-to-1 ratio. For example, four adjacent bit slices 20 align with one hardmac 18 that has four attachment points 22.
Bit slices 20 align with and connect to I/O slots 22 in a 1-to-1 ratio, which typically map internal and external signaling levels between IC 10 and the PCB.
Each die 14 or device may have a different size and a different number of I/O slots 22. Correspondingly, each package 12 has a different size and therefore a different “footprint,” or amount of space it will take up on a printed circuit board. Package 12 connects to die 14 through array 24 of either bumps (for flip-chip packaging) or wires (for wirebond packaging). Through array 24, I/O slots 22 connect to package balls 26, which connect to the pins (not shown) exiting most ICs. Not all package balls 26 are useable, so I/O slots 22 connect only to useable package balls 26.
A desirable feature in IC design is scalability. Different packages 12 have different sizes, with a different number of useable package balls 26 for each size, able to support die 14 with a different number of I/O slots 22. Scalability in IC design means that different packages may integrate the same die, or different dies may be integrated into the same package. One impediment to this scalability is the I/O interface between die 14 and package 12 (or the PCB). One solution is to redesign hardmacs 18 for each die/package combination. However, this is expensive due to the time involved in designing hardmacs 18.
FIG. 2 is a block diagram illustrating a second solution with IC 30 made up of package 32 and die 34. In this example, die 34 is the same device as die 14 but integrated into smaller package 32, hence implementing scalability. Rcell fabric 36 supports hardmacs 38 with attachment points 42. Hardmacs 38 may be hardmacs 18 designed for the die/package interface of FIG. 1. Hardmacs 38 connect to some of bit slices 40, however, unused bit slices 41 are not connected to hardmacs 38. Hardmacs 38 may connect to bit slices 40 in groups of 8, 15, or 24, for example, depending of the particular design of hardmac 38. Bit slices 40 that are connected to hardmac 38 then connect to I/O slots 42. Unused I/O slots 43 are not connected to bit slices 40. Finally, I/O slots 42 that are connected to hardmacs 38 through bit slices 40 are connected to the useable portion of package balls 46 through array 44. Fewer I/O slots 42 and bit slices 40 may be used because there are fewer package balls 46 in package 32. Package 32 is smaller than package 12, for which die 34 and hardmacs 38 were designed.
One problem with this solution is that smaller packages may not be able to handle the congestion of I/O slots 42 required by hardmac 38, or IC 30 may be difficult to manufacture as result of I/O slot congestion in a smaller package. Another problem with this solution is a potential impact on line speed signal integrity. Also, in wirebonding, the gaps between used I/O slots (e.g. unused I/O slots) may be susceptible to uneven flow of the package material during assembly, resulting in a phenomenon known as “wire sweep” where used I/O slots short with each other.
Accordingly, what is needed is a system and method for providing scalability in an integrated circuit in a cost effective manner and avoiding the above-stated problems. The present invention addresses such a need.
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