1. Field of the Invention
This invention relates to an input protection circuit for protecting the gate of a MOS (insulated gate type) transistor provided at the input stage of a semiconductor integrated circuit from electrostatic discharge (ESD) breakdown, and more particularly to the element structure of an input protection resistor constituting the input protection circuit.
2. Description of the Related Art
In a semiconductor integrated circuit device, ESD breakdown of an internal element caused by input of a surge voltage during the mounting operation by a user is a serious problem. The ESD breakdown is caused when an excessively high voltage is applied to an external pin of the semiconductor integrated circuit device.
In order to prevent occurrence of the ESD breakdown, an input protection circuit is provided in the conventional MOS LSI (large scale integrated circuit). The input protection circuit is provided in a signal path extending from an input pad which is supplied with an input signal from the exterior of the LSI to the gate of a MOS transistor at the input stage of an internal circuit. That is, the drain of an N-channel MOS transistor (input protection transistor) serving as an input protection element is connected to the gate of the input-stage MOS transistor and the gate and source of the input protection transistor are connected to a ground terminal. FIG. 1 shows an example of the cross sectional structure of the input protection transistor. An element isolation region (field insulation film) 61 is selectively formed on the main surface of a P-type semiconductor substrate 60. A drain region (N.sup.+ -type impurity diffused layer) 62 and a source region (N.sup.+ -type impurity diffused layer) 63 are separately formed in the main surface area of the substrate 60 corresponding to an element region separated by the element isolation region 61. A gate insulation film 64 is formed on that portion of the substrate 60 which lies between the drain and source regions 62 and 63 and a gate electrode 65 is formed on the insulation film 64. An inter-level insulation film 66 is formed on the element isolation region 61 and the gate electrode 65. Contact holes 66a and 66b are formed in those portions of the inter-level insulation film 66 which lie on the drain and source regions 62 and 63. A drain electrode 67 is formed on the inter-level insulation film 66 and made in contact with the drain region 62 via the contact hole 66a. Likewise, a source electrode 68 is formed on the inter-level insulation film 66 and made in contact with the source region 63 via the contact hole 66b.
When an excessively high voltage is applied to the input pad and a potential applied to the drain of the input protection transistor with the construction shown in FIG. 1 becomes higher than the surface breakdown voltage of the junction plane between the drain region 62 and the substrate 60, breakdown occurs in the PN junction plane between the drain region (N.sup.+ -type impurity diffused layer) 62 and the P-type substrate 60, causing a large number of holes 69 to be discharged from the drain region 62 into the P-type substrate 60. The holes 69 raise the potential of the P-type substrate 60, and when the potential thereof becomes higher than the ground potential Vss by the forward voltage drop across the PN junction between the P-type substrate 60 and the source region (N.sup.+ -type impurity diffused layer) 63, the holes 69 flow into the source region 63. As a result, the input protection transistor acts as an NPN bipolar transistor and an excessively high voltage input from the exterior is discharged by the bipolar action.
FIG. 2 shows the input voltage-output current characteristic obtained by the bipolar action of the input protection transistor. When the input voltage V.sub.IN is raised, the input protection transistor operates as an NPN bipolar transistor and is turned on so as to permit current to flow. If the bipolar transistor is once turned on, it maintains the ON-state even if the input voltage V.sub.IN is set lower than the turn-ON voltage.
Therefore, the gate voltage of the MOS transistor at the input stage (first stage) of the internal circuit is kept lower than the surface breakdown voltage of the junction plane between the substrate and the drain region of the input protection transistor so that an excessively high voltage can be prevented from being applied to the gate of the input-stage MOS transistor.
However, in recent years, in order to form the semiconductor integrated circuit device at a high integration density, elements constituting the internal circuit are formed in a fine pattern and the input protection elements are formed in a fine pattern. With the even greater miniaturization of the elements, the PN junction of the input protection transistor tends to be broken down by heat generated at the time of breakdown of the input protection transistor. The above problem occurs because heat generated in the junction plane is transmitted to aluminum forming the drain electrode 67 when the breakdown occurs at the PN junction plane between the P-type substrate 60 and the drain region 62 of the input protection transistor. When the temperature of aluminum is raised to the melting point of aluminum by the thus generated heat, aluminum at the contact portion with the drain region 62 melts and flows on the surface of the drain region 62 in a current flow direction. When the melted aluminum has reached the substrate 60, the drain region 62 is short-circuited to the substrate 60 and a state equivalent to a state in which the PN junction is broken down is set up.
The junction breakdown due to the melting of aluminum occurs before occurrence of the PN junction break-down due to concentration of electric field since the melting point of aluminum is low. For this reason, it is difficult to attain the greater miniaturization of elements and the high breakdown voltage of the PN junction at the same time.
There is a semiconductor integrated circuit device in which an input to an address input pin is required to be subjected to three-valued control, for example, in the electric signature test in an EPROM (ultraviolet erasable and programmable read only memory). The three-valued control is effected by controlling an input voltage by use of an ordinary high level (substantially the power source voltage level), low level (ground potential level) and a voltage level which is higher than the high level. In the case of the electric signature test, the high level is set at 5 V, the low level is set at 0 V and the voltage level higher than the high level is set at 12.5 V.
Assume now that noise is mixed into the input voltage in the electric signature test with the input voltage V.sub.IN set at a voltage of 12.5 V which is higher than the high level. For example, if the breakdown voltage of the NPN transistor is 14 V, the input voltage V.sub.IN becomes 14.5 V (12.5 V+2 V) when noise of approximately 2 V is superposed on the input voltage, thereby turning on the input protection transistor (NPN transistor). Noise is superposed instantaneously and then the input voltage is returned to 12.5 V, but the NPN transistor which is once turned on permits current to continuously flow if the input voltage V.sub.IN is kept at 12.5 V as shown in FIG. 2. Current flowing in the NPN transistor which is set in the ON-state is large and heat generated at this time may cause the NPN transistor to be broken down. Further, a latch-up phenomenon may occur by a substrate current flowing at the time of turn-on of the NPN transistor.
The above explanation is made by taking an example of a case wherein a voltage higher than the high level is input in the electric signature test for EPROMs, but the above phenomenon may occur when an ordinary address is input if the surface breakdown voltage is lowered with the even greater miniaturization of elements. Particularly, the NPN transistor is turned on immediately after noise is superposed on the address input and overshooting of the address input has occurred, and the ON-state is maintained so that the NPN transistor may be damaged.
As described above, the conventional input protection circuit permits current to continuously flow at the time of breakdown of the input protection transistor by reduction in the surface breakdown voltage due to the even greater miniaturization of elements and the PN junction of the input protection transistor tends to be broken down by heat caused by the current. Further, a latch-up phenomenon tends to occur by the substrate current flowing when the input protection transistor is turned on.
USPTO Backgrounds
USPTO Backgrounds