Recently, as a design rule of a semiconductor device becomes smaller, the integration degree of a semiconductor device is largely increased.
As the design rule of the semiconductor device becomes smaller, the chip size and the circuit line width of the semiconductor device become gradually smaller and various problems occur.
As one of the problems, the gap between gate structures included in the semiconductor device become narrow so that the aspect ratio of the gap formed between the gate structures is increased, thereby frequently generating a void between the gate structures when forming an interlayer dielectric layer covering the gate structures.
The problem where a void is generated between gate structures frequently occurs in a NOR-type flash memory device having a cell array area where a plurality of memory cells are connected to one bit line in parallel.
Since the bit line is arranged between a pair of neighboring gate structures, the NOR-type flash memory device frequently generates the void at a position where the bit line is formed.
USPTO Backgrounds
USPTO Backgrounds