Clock transmission in an integrated circuit and systems implementing an integrated circuit is an important aspect of implementing the integrated circuit, such as a programmable logic device (PLD) or an application specific integrated circuit (ASIC). Accurate clock transmission not only affects the functionality of an integrated circuit or system, but also the speed of the integrated circuit or system.
Complementary metal oxide semiconductor (CMOS) clocking has been traditionally used for clock signaling. However, with the push for higher data rates, and particularly higher data rates in high speed serializer-deserializer (SERDES) designs, current-mode logic (CML) clocking is more widely used. That is, it is not power efficient to route clock signals using high rates and or to drive long routes using CMOS clocking circuits. In the CML clock source stage of conventional devices, the current sources and impedances can be programmable to vary the output swing of the clock signal, and can be adjusted for a given data rate for example. However, a conventional CML clock source stage is in open-loop. Therefore, variations, such as process, voltage and temperature (PVT) variations will cause the output amplitude, and therefore the clock signal received at the destination, to vary.
Accordingly, improved circuits for transmitting a signal in a CML circuit would be beneficial.
USPTO Backgrounds
USPTO Backgrounds