The present invention relates to an analog-to-digital converter and, more particularly, an analog-to-digital converter of the integrating type.
A conventional integrating analog-to-digital converter is described in U.S. Pat. No. 3,316,547 to Stephan K. Ammann. This converting system is known as the so-called dual slope integrating analog-to-digital converter. The system will be described with reference to FIGS. 1 and 2.
As shown in FIG. 1, the prior art converter comprises an integrator 1 composed of an input resistor R, an integrating capacitor C, a reset switch 11 and an operational amplifier 4. A voltage -V.sub.1 of an analog signal source 2 or a reference voltage V.sub.2 of a reference voltage source 3 is selectively applied to an input terminal 12 of the integrator 1, through operation of a switch 18. The output signal 14 is the integrator 1 and a threshold voltage V.sub.T are applied to a comparator 5 where the output signal 14 is compared with the threshold voltage V.sub.T. The output 15 of the comparator 5 is applied to one of two input terminals of an AND gate 13 whose other input terminal receives a pulse signal from a pulse generator 6. The output 17 of the AND gate 13 is transmitted to a counter 7. A control circuit 8 controls on-off operation of the switch 11 through a flip-flop 9, resets the counter 7 to its initial state and controls the on-off operation of the switch 18 through a flip-flop 10.
For an explanation of the operation, reference is also made to FIG. 2 illustrating waveforms at respective points in the circuit shown in FIG. 1. At time t.sub.R the control circuit 8, produces a signal which in turn resets the flip-flops 9 and 10. A signal so produced at this time from the flip-flop 9 closes the switch 11 so that the integrator 1 is reset to be at zero level at the output. Also in response to a signal S.sub.1 of the flip-flop 10, the switch 18 couples the analog signal source 2 with the input 12 of the integrator 1. Then, at time t.sub.0 the reset state of the flip-flop 9 is released by a signal from the circuit 8 to open the switch 11. From this time t.sub.0, the integrator 1 integrates the voltage -V.sub.1 of the analog signal source 2 to be converted, and its integration output 14 is compared wih the threshold level V.sub.T. When the integration output exceeds the threshold level V.sub.T at time t.sub.1 1 the comparator 5 produces the output 15 which in turn enables the AND gate 13 to transmit the pulses from the pulse generator 6 to the counter 7. Thus the integrator 1 continues its integration, and thus the counter 7 also continues its counting operation. At time t.sub.2 when the counter 7 reaches its full scale count, the counter 7 produces a full scale output 16' which in turn sets the flip-flop 10 to turn the switch 18 to the reference voltage source 3 by the signal S1, and at the same time the count of the counter 7 returns to zero. The period of time from the initiation (t.sub.1) of counting by the counter 7 when the integration output 14 exceeds the reference value V.sub.T of the reach of the full scale count (t.sub.2) is expressed by T.sub.1. Upon the switching of the switch 18, the integrator 1 initiates the integration of the voltage V.sub.2 of the reference voltage source 3. Since the polarity of the voltage V.sub.2 is set to be opposite to that of the voltage V.sub.1 of the analog signal source 2, the integrator 1 initiates an inverse integration from this time, that is to say, it initiates a subtraction from an absolute value of the integration value at time t.sub.2. Thus, the output of the integrator 1 gradually decreases. At time t.sub.3 the integration value returns to the reference value V.sub.T and the comparator output 15 stops. As a result, the gate 13 closes to inhibit transferring the pulses 17 to the counter 7, resulting in the interruption of the counting operation of the counter 7. The count output 16 of the counter 7 at this time represents the number of pulse counts N in the time interval T.sub.2 from time instant t.sub.2 to the time point t.sub.3 that the output 14 of the integrator 1 reaches again the threshold voltage V.sub.T of the comparator 5. The voltage -V.sub.1 of the analog signal source 2 is integrated over the period of time T1 so that the output 14 of the integrator 1 changes by .DELTA.V, and the difference .DELTA.V between level Vx at time t2 and level V.sub.T is given as follows: EQU .DELTA.V=V.sub.1 .times.T1/RC.
The pulse repetition frequency f.sub.0 of the pulse generator 6, the full scale count F of the pulse counter durig the period T1 and the period T1 are related by T.sub.1 =F/fo. Upon substituting for T.sub.1, the following equation is obtained: EQU .DELTA.V=V.sub.1 .times.F/RC f.sub.0.
Similarly, the output change of the integrator 1 during the period T2 is .DELTA.V and the number of pulse counts N during the period T2 has a relation of T2=N/fo. Therefore, we have the following relation of the difference .DELTA.V: EQU .DELTA.V=V2.times.T2/RC=V2N/RC f.sub.0.
Rearranging the equations .DELTA.V=V.sub.1 .times.F/RC f.sub.0 and .DELTA.V=V2.times.N/RC f.sub.0, there is obtained the following equation (1): PS EQU N=V1/V2.times.F or T2=V1/V2.times.T1. (1)
Therefore, if F/V2 is selected to be 10 n (n=0, 1, 2 . . . ), the input analog voltage V1 may be expressed in digital form by the output count N from the counter 7.
Thus, the conventional integrating A/D converter requires a conversion time period of at least T1+T2. The maximum value T2 max of the period T2 is determined by the maximum value V1 max. of the analog input voltage and is given by: EQU T2max=(V1max/V2).times.T1.
If V1max=V2 and T2max=T1, the converting time period s 2T1. The maximum value .DELTA.V(max) of the amplitude of the output signal of the integrator is expressed as follows: EQU .DELTA.V(max)=(V1max F)/(RC fo)=(V1max)/(RC)T1.
Thus, in order to improve the converting precision, .DELTA.V(max) must be relatively large, and therefore the circuit components used in the integrator must have withstand high voltage.
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