Miniaturization of wireless products such as cellular phones and handheld computers such as personal digital assistants (PDA), has driven the increased demand for smaller component footprints, which in turn increases the popularity of multi-chip stack BGA packaging. Most multi-chip packages involve stacking dies on top of each other by means of adhesive elements. However, to achieve a low package height for multi-chip stacked die packages, a significantly reduced die thickness is needed together with the use of special wire bond techniques to reduce the height of the wire bond loop height.
Thin die handling and the required special bonding techniques poses many challenges to the assembly process. FIGS. 1-3 depict conventional ways of packaging a multi-chip stacked die package. As shown in FIG. 1, one prior art package 10 includes two conventional stacked dies, the first (bottom) die 12 being surface mounted by means of an adhesive element 14 to a substrate 16, and a smaller second (top) die 18 being mounted by a second adhesive element 20 onto the active surface 22 of the bottom die 12, each of the dies being wire bonded 24 to the substrate 16. FIG. 2 illustrates a prior art stack die package 10a in which the first (bottom) die 12a is mounted to a substrate 16a in a flip chip attachment, and the second (top) die 18a is surface mounted to the inactive surface 26a of the first die 12a by means of an adhesive element 20a and wire bonded 24a to the substrate 16a. FIG. 3 shows a prior art three-die stack BGA package 10b in which the first bottom die 12b is mounted to a substrate 16b by an adhesive element 14b, a second (middle) die 18b is mounted on the active surface 22b of the bottom die 12b by a second adhesive element 20b, and a third (top) die 28b is mounted on a spacer 30b mounted on the active surface 32b of the second (middle) die 18b, with each of the dies being wire bonded 24b to the substrate 16b. 
In stacked die assemblies in which the bottom die is a flip chip, there is a limit on the minimum overall thickness of the package that can be achieved. If a solder-bumped wafer having a 150 μm bump height were to be ground to a total thickness of 150 μm to 200 μm, there would be a high occurrence of broken wafers due to the stress induced on the wafers from the bumps. Furthermore, even if the wafer does not crack, the die strength will drop significantly due to the presence of “dimples” on the backside of the wafer. Such dimples are typical defects observed on bump wafers that are ground too thin or an inappropriate backgrinding tape is used in the process.
In addition, as depicted in FIG. 3, with multiple stacked dies, a spacer 30b is required to create the minimal clearance for the wire loop height between the second (middle) die 18b and the third (top) die 28b. This results in a higher package height, or requires ultrathin dies in order to meet the package height requirement. Thinner dies translate into a higher possibility of cracked dies during the assembly process.
In view of these and other deficiencies, improvements in stacked die modules are desirable.
USPTO Backgrounds
USPTO Backgrounds