1. Field of the Invention
This invention relates to semiconductor technologies, and more particularly, to a circuit for use on a wafer formed with multiple discrete semiconductor devices, such as DRAM (dynamic random access memory) devices, to perform a burn-in operation on the semiconductor devices so as to test the reliability thereof.
2. Description of Related Art
Burn-in is the operation of a new integrated circuit (IC) product for a specified time under accelerated aging conditions prior to the shipment so as to sort out premature failures. The burn-in operation is an essential step for testing the reliability of the IC products. Most IC products, such as DRAMs, undergo the burn-in operation after they have been cut apart from the wafer and then packaged in holders. One drawback to this practice is that, in the event that any failures are found in the addresses, including row or column addresses, or memory cells in the DRAM package during the burn-in operation, the IC chip is not repairable since it is already sealed in the package. As a consequence, the whole IC package may have to be discarded or sold at a significantly reduced price.
A solution to the forgoing problem has been disclosed and published in IEEE, IEDM 93-639 by Tohru Furuyama et al. of Toshiba Corporation of Japan. This paper teaches an improved method for the burn-in operation on the DRAM devices formed on a wafer. This method, however, still has the following drawbacks. First, for each DRAM device, the burn-in for the memory cells thereof and the burn-in for the periphery circuitry thereof should be separately performed (i.e., a concurrent burn-in operation to these two parts of each DRAM device is impossible). The overall burn-in is therefore quite time-consuming. Second, since the burn-in is carried out by using a number of probes to poke on the pads formed on each die in the wafer, additional work time may be required if the number of probes is insufficient. Third, it requires the provision of a number of test pads on each die in the wafer for the burn-in operation, which causes each die to be take additional real estate of the wafer in order to incorporate these test pads thereon. The die is therefore large in size.
USPTO Backgrounds
USPTO Backgrounds