1. Field of the Invention
The present invention relates to a device for controlling a gate of a three-level inverter using a self-arc extinction type power semiconductor element (hereinafter referred to simply as xe2x80x9cself-arc extinction elementxe2x80x9d) and a method of controlling the gate, and more particularly to a device and a method of controlling the gate of the three-level inverter that prevents the self-arc extinction element from being damaged by forming the shortest commutation loop at the time of switching operation.
2. Description of the Related Art
As a general three-level inverter, there is, for example, xe2x80x9cLoss balancing in three-level voltage source inverters applying active NPC switchesxe2x80x9d disclosed in PESC (2001), pp. 1135 to 1140.
Referring to FIGS. 3 to 5 and Table III of the above document, self-arc extinction elements T5 and T6 are added as active NPC switches.
Also, in the case where neutral point potential of a d.c. power source is outputted to the three-level inverter, there is disclosed four kinds of gate control methods.
An object of the above-mentioned document is to average the losses generated in the self-arc extinction elements T5 and T6 that constitute the three-level inverters by appropriately selecting the four kinds of gate control methods.
Therefore, the commutation operation taking the inductance of the wiring structure within the three-level inverter into consideration is not particularly limited.
Since in the conventional device and method of controlling the gate of the three-level inverter, the commutation operation taking the inductance of the wiring structure within the three-level inverter into consideration is not devised as described, there arises such a problem that the reliability of the three-level inverter is lowered.
In particular, there arises such a problem that the self-arc extinction elements are damaged at the time of switching operation when the inductance (corresponding to the number of wiring elements) of the wiring structure that forms the commutation loop becomes large at the time of commutation between the respective self-arc extinction elements that constitute the three-level inverters.
The present invention has been made to solve the above-mentioned problems with the conventional device, and therefore an object of the present invention is to provide a device and a method of controlling a gate of a three-level inverter which reduces the inductance of a commutation loop to prevent self-arc extinction elements from being damaged by forming the shortest commutation loop at the time of commutation between the self-arc extinction elements.
A gate control device for a three-level inverter according to the present invention includes: first to third d.c. terminals having first to third potential levels; first to fourth self-arc extinction elements connected in series between the first and third d.c. terminals; first and second clamp diodes connected in reverse parallel between a node of the first and second self-arc extinction elements and a node of the third and fourth self-arc extinction elements; fifth and sixth self-arc extinction elements connected in reverse parallel between the respective both terminals of the first and second clamp diodes, individually, in which a node of the first and second clamp diodes is connected to the second d.c. terminal; a PWM circuit that generates a first conduction control command with respect to the first and third self-arc extinction elements and a second conduction control command with respect to the second and fourth self-arc extinction elements; and a gate control circuit that generates gate signals with respect to the gates of the first to sixth self-arc extinction elements on the basis of the first and second conduction control commands, wherein the gate control circuit includes: first and second inversion circuits that invert the first and second conduction control commands, individually; and a delay circuit group that generates the gate signals on the basis of the first and second conduction control commands and the inverted first and second conduction control commands, and wherein the third and fifth self-arc extinction elements are rendered conductive at the same time, and the second and sixth self-arc extinction elements are rendered conductive at the same time.
Further, a gate control device for a three-level inverter according to the present invention includes: first to fourth on-delay circuits that generate first to fourth gate signals with respect to the first to fourth self-arc extinction elements; a first series circuit including a fifth on-delay circuit that generates a fifth gate signal with respect to the fifth self-arc extinction element and a first off-delay circuit; and a second series circuit including a sixth on-delay circuit that generates a sixth gate signal with respect to the sixth self-arc extinction element and a second off-delay circuit, wherein a first dead time of the first and second off-delay circuits is set to be shorter than the dead time of the fifth and sixth on-delay circuits, wherein second dead time of the first to fourth on-delay circuit is set to be longer than the dead time of the fifth and sixth on-delay circuits, wherein the fifth self-arc extinction element starts conduction precedent to a time point at which the conduction of the third self-arc extinction element starts and ends the conduction with a delay from a time point at which the conduction of the third self-arc extinction element ends; and that the sixth self-arc extinction element starts conduction precedent to a time point at which the conduction of the second self-arc extinction element starts and ends the conduction with a delay from a time point at which the conduction of the second self-arc extinction element ends.
Further, a gate control device for a three-level inverter according to the present invention includes: a positive polarity comparator and a negative polarity comparator that generate a current polarity signal corresponding to the polarity of the output current of the three-level inverter; and third and fourth inversion circuits that invert the respective current polarity signals from the positive polarity comparator and the negative polarity comparator, individually, wherein the gate control circuit includes first to sixth selection circuits that switchingly select the gate signals in accordance with the respective current polarity signals and the respective output signals of the third and fourth inversion circuits, wherein in the case where the output current is positive, the third and fifth self-arc extinction elements are rendered conductive at the same time under control, and wherein in the case where the output current is negative, the second and sixth self-arc extinction elements are rendered conductive at the same time under control.
Further, according to a gate control device for a three-level inverter of the present invention, the gate control circuit includes: a first exclusive OR circuit that takes an exclusive logical addition of the output signal of the third on-delay circuit and the output signal of the first series circuit to generate the gate signal with respect to the gate of the fifth self-arc extinction element; and a second exclusive OR circuit that takes an exclusive logical addition of the output signal of the second on-delay circuit and the output signal of the second series circuit to generate the gate signal with respect to the gate of the sixth self-arc extinction element, wherein the fifth self-arc extinction element starts to be rendered conductive precedent to a time point at which the conduction of the third self-arc extinction element starts, holds a non-conductive state during the conduction period of the third self-arc extinction element, and is rendered conductive by the first dead time from the time point at which the conduction of the third self-arc extinction element ends, and wherein the sixth self-arc extinction element starts to be rendered conductive precedent to a time point at which the conduction of the second self-arc extinction element starts, holds a non-conductive state during the conduction period of the second self-arc extinction element, and is rendered conductive by the first dead time from the time point at which the conduction of the second self-arc extinction element ends.
Further, according to a gate control device for a three-level inverter of the present invention, the gate control circuit includes: fifth and sixth inversion circuits that invert the output signals of the second and third on-delay circuits, individually; a first AND circuit that takes the logical product of the output signal of the first series circuit and the output signal of the fifth inversion circuit; a first OR circuit that takes the logical addition of the output signal of the first exclusive OR circuit and the output signal of the first AND circuit to generate the gate signal with respect to the gate of the fifth self-arc extinction element; a second AND circuit that takes the logical product of the output of the second series circuit and the output signal of the sixth inversion circuit; and a second OR circuit that takes the logical addition of the output signal of the second exclusive OR circuit and the output signal of the second AND circuit to generate the gate signal with respect to the gate of the sixth self-arc extinction element, wherein the fifth self-arc extinction element starts to be rendered conductive precedent to a time point at which the conduction of the third self-arc extinction element starts, holds a non-conductive state except for a period of time during which the first and second self-arc extinction elements are rendered nonconductive at the same time, and is rendered conductive by the first dead time from the time point at which the conduction of the third self-arc extinction element ends, and wherein in the sixth self-arc extinction element starts to be rendered conductive precedent to a time point at which the conduction of the second self-arc extinction element starts, holds a non-conductive state except for a period of time during which the third and fourth self-arc extinction elements are rendered nonconductive at the same time, and is rendered conductive by the first dead time from the time point at which the conduction of the second self-arc extinction element ends.
Further, according to a gate control method for a three-level inverter, the device includes: first to third d.c. terminals having first to third potential levels; first to fourth self-arc extinction elements connected in series between the first and third d.c. terminals; first and second clamp diodes connected in reverse parallel between a node of the first and second self-arc extinction elements and a node of the third and fourth self-arc extinction elements; and fifth and sixth self-arc extinction elements connected in reverse parallel between the respective both terminals of the first and second clamp diodes, individually, in which a node of the first and second clamp diodes is connected to the second d.c. terminal, the method comprising the step of rendering the third and fifth self-arc extinction elements conductive at the same time, and rendering the second and sixth self-arc extinction elements conductive at the same time.
Further, a gate control method for the three-level inverter according to the present invention comprises the steps of: starting the conduction of the fifth self-arc extinction element precedent to a time point at which the conduction of the third self-arc extinction element starts and ending the conduction of the fifth self-arc extinction element with a delay from a time point at which the conduction of the third self-arc extinction element ends; and starting the conduction of the sixth self-arc extinction element precedent to a time point at which the conduction of the second self-arc extinction element starts and ending the conduction of the sixth self-arc extinction element with a delay from a time point at which the conduction of the second self-arc extinction element ends.
Further, according to a gate control method for the three-level inverter of the present invention, in the case where the output current of the three-level inverter is positive, the third and fifth self-arc extinction elements are rendered conductive at the same time under control, and wherein in the case where the output current is negative, the second and sixth self-arc extinction elements are rendered conductive at the same time under control.
Further, a gate control method for the three-level inverter according to the present invention comprises the steps of: starting the conduction of the fifth self-arc extinction element precedent to a time point at which the conduction of the third self-arc extinction element starts; holding a non-conductive state thereof during the conduction period of the third self-arc extinction element; and rendering the fifth self-arc extinction element conductive by a predetermined period of time from the time point at which the conduction of the third self-arc extinction element ends; and starting the conduction of the sixth self-arc extinction element precedent to a time point at which the conduction of the second self-arc extinction element starts; holding a non-conductive state thereof during the conduction period of the second self-arc extinction element; and rendering the sixth self-arc extinction element conductive by the predetermined period of time from the time point at which the conduction of the second self-arc extinction element ends.
Further, a gate control method for the three-level inverter according to the present invention comprises the steps of: starting the conduction of the fifth self-arc extinction element precedent to a time point at which the conduction of the third self-arc extinction element starts; holding a non-conductive state thereof except for a period of time during which the third and fourth self-arc extinction elements are rendered non-conductive at the same time; and rendering the fifth self-arc extinction element conductive by a predetermine period of time from the time point at which the conduction of the third self-arc extinction element ends; and starting the conduction of the sixth self-arc extinction element precedent to a time point at which the conduction of the second self-arc extinction elements starts; holding a non-conductive state thereof during the conduction period of the second self-arc extinction element; and rendering the sixth self-arc extinction element conductive by the predetermined period of time from the time point at which the conduction of the second self-arc extinction element ends.
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