1. Field of the Invention
The present invention relates to a signal transmission technology for enabling high-speed signal transmission between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or cabinets, and more particularly to an output circuit device to be used for clock signal distribution in high-speed signal transmission, and a system constructed with such output circuit devices.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, etc. have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed gap between a memory such as a SRAM or DRAM and a processor (i.e., between LSIS), for example, has been widening, and in recent years, this speed gap has been becoming a bottleneck in a computer's performance. Further, not only the speed of signal transmission between such chips, but because of increasing integration and increasing size of chips, decreasing supply voltage levels (decreasing signal amplitude levels), etc. the speed of signal transmission between elements or circuit blocks within a single chip is also becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset also is becoming a major factor limiting the overall performance of the system.
Here, a technique for distributing a clock for accurate timing becomes important when it comes to increasing the speed of signal transmission within a cabinet or between circuit blocks or chips. That is, as the timing accuracy of the distributed clock directly affects the accuracy of receive timing and also the timing accuracy of a signal to be generated, a buffer that can minimize the occurrence of jitter must be used as a clock buffer for clock distribution. This applies not only to the clock distribution buffer, but also to various other output circuit devices that are required to operate at high speed with accurate timing.
In the prior art, it was difficult to provide an output circuit device that can operate at high speed with accurate timing by minimizing the occurrence of jitter.
The prior art and its associated problem will be described in detail later with reference to relevant drawings.
USPTO Backgrounds
USPTO Backgrounds