1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to an analog IC in which the development time can be shortened, the reliability can be improved, and the degree of freedom in design can be enhanced.
2. Description of the Related Art
Conventionally, ASICs are mainly configured by MOS devices, and realized in the form of a gate array, a master slice, or the like. Since a MOS device is mainly used in a digital circuit and such a circuit is formed by turning on/off a transistor, elements such as transistors and resistors are formed so as to have a substantially same size. Therefore, transistors, resistors, and other elements are repeatedly formed, and these elements are selected through interconnections to constitute a circuit, thereby realizing an IC.
A linear circuit, particularly, a BIP linear circuit consists of a plurality of electronic circuit blocks, and elements constituting the blocks have various characteristics and sizes. Even when semiconductor elements such as transistors, diodes, resistors, and capacitors are configured by selecting repeatedly formed elements as in the case of a gate array or a master slice, therefore, satisfactory characteristics cannot be obtained. Consequently, a countermeasure is taken as described below.
For example, JP-A-2-3952 (FIG. 9) discloses a technique as an example of such a countermeasure. The disclosed technique is a so-called building block layout in which a layout region for elements is formed into a rectangular shape, and a power source line and a ground line are disposed on both sides of each block. In the technique, all building blocks have the same size.
When an AM circuit is to be configured, the number of elements is first determined, and all the elements are distributed over layout regions of the same size.
Referring to FIG. 9, for example, two rows in each of which eight layout regions of the same size are laterally arranged are formed in an area of a semiconductor chip 30 surrounded by bonding pads 31. Among the layout regions, three layout regions constitute an electronic circuit block (for example, an AM circuit) indicated by A, three layout regions constitute an electronic circuit block indicated by B, two layout regions constitute an electronic circuit block indicated by C, five layout regions constitute an electronic circuit block indicated by D, and three layout regions constitute an electronic circuit block indicated by E.
In other words, the layout regions of the same size correspond to bricks, respectively, and the bricks are freely arranged in a rectangular IC, so that the layout regions are regularly placed.
When the electronic circuit block C is not necessary, the corresponding two layout regions are deleted, and the remaining layout regions are rearranged, so that another IC chip can be realized. When another electronic circuit block F is to be added, the layout regions including those constituting the new circuit block are rearranged in a similar manner as bricks.
A design technique for the layout will be described. In the case of an IC of an AM/FM circuit, for example, a necessary circuit library is first selected, and rectangular pattern libraries are formed in order to construct the selected circuit library in an IC chip by he building block layout, and then arranged in the IC chip. Thereafter, metal interconnects are formed so as to select all the pattern libraries, thereby configuring a first generation of an AM/FM IC serving as a parent production type.
When such a first generation IC is to be remodeled into another IC, an efficient layout of an IC chip must be considered. Therefore, it is required that an unnecessary circuit block is deleted or a necessary circuit block is added and blocks are efficiently rearranged on the IC chip.
Consequently, the user requesting such remodeling to be realized in a shorter design time is not satisfied with the proposed technique.
With respect to a necessary circuit block, the circuit design and the pattern design must be performed from the beginning, and hence a long design time is required. Such a newly developed circuit block involves at first various problems such as a parasitic effect, oscillation, and invasion of noises, and does not has guaranteed reliability. Improvements for solving the problems are required, and the pattern design must be repeated many times.
In the case where the user requests a short delivery time of a product, a master slice is employed. In a master slice also, however, the whole configuration is realized by selection of elements, and hence there is a problem in that the reliability is low.
According to the invention, first, the problems are solved by a configuration in which one region is formed as a region where a master slice is enabled, so as to facilitate the pattern design of an electronic circuit that is to be newly developed, and fundamental blocks that are frequently used are placed in another region.
Namely a first aspect of the present invention is a semiconductor integrated circuit device in which a semiconductor layer formed in a surface of a semiconductor chip is divided into a plurality of block regions serving as a layout region for an electronic circuit,
a plurality of semiconductor elements constituting said electronic circuit mounted in said block regions, and interconnects are formed in an upper layer of and/or
a periphery of said block regions in which said electronic circuit is formed, wherein
said block regions are divided into a master slice region which is configured by selecting or unselecting elements, and a fixed region in which substantially all of elements are selected to configure one circuit.
When a part of the above-mentioned electronic circuit is configured by using the fundamental blocks, it is possible to improve the reliability. The use of the fundamental blocks facilitates improvement of the electronic circuit, and expansion of product types.
Second, in a building block layout in which the longitudinal length is standardized and the lateral length is flexibly set, circuits of different sizes are configured in each block region, and hence block regions have different sizes. In a semiconductor chip, consequently, a vacant region is inevitably produced. Fundamental blocks are positively accommodated in such a vacant region, so that modification of a circuit and expansion of product types are facilitated.
Third, in a building block layout in which both the longitudinal and lateral lengths are standardized, fundamental blocks are positively accommodated in a vacant region in the same manner as described above, so that modification of a circuit and expansion of product types are facilitated.
Each fundamental block may be configured by a differential circuit, an op-amp, a comparator, a frequency converter, a multiplier, a reference voltage source, an analog switch, or the like.
Fifth, the problems can be solved by a configuration in which a first block region where an electronic circuit block and/or a semiconductor element that is particularly accurate in an electronic circuit is placed is formed in a substantial center of a semiconductor chip.
In order to improve the design speed, a master slice layout is employed. At present, the position where a resistor which defines the oscillation frequency is to be placed depends largely on a design software. Therefore, such a resistor or an electronic circuit block is determined so as to be placed in the center of a semiconductor chip, whereby resin distortion after packaging, and wafer distortion due to the resin distortion are eliminated as far as possible.
When a region other than the first block region is used as that where the master slice layout is employed, therefore, the configuration except an important circuit (a circuit in which variations of characteristics are not desired) can be realized by selection and unselection of elements. As a result, shortening of the design time, and prevention of variations of circuit characteristics can be realized.
When an oscillation circuit which is to be fixed to a specific frequency is placed in the first block region, particularly, it is possible to prevent the fixed frequency from fluctuating.
When the semiconductor element formed in the first block region is a resistor, variations of the resistance can be suppressed.
USPTO Backgrounds
USPTO Backgrounds