The increasing density of integrated circuits (e.g., DRAMs) is increasing the need for materials with high dielectric constants to be used in electrical devices such as capacitors. Generally, capacitance is directly related to the surface area of the electrode in contact with the capacitor dielectric, but it is not significantly affected by the electrode volume. The current method generally used to achieve higher capacitance per unit area is to increase the surface area/unit area by increasing the topography in trench and stack capacitors using silicon dioxide or silicon dioxide/silicon nitride as the dielectric. This approach becomes very difficult in terms of manufacturability for devices such as the 256 Mbit and 1 Gbit DRAMs.
An alternative approach is to use a high permitivity dielectric material. Many high dielectric constant (HDC) materials including perovskites, ferroelectrics and others, such as (Ba, Sr)TiO3 (BST), usually have much larger capacitance densities than standard SiO2-Si3N4-SiO2 capacitors. The deposition process for HDC materials such as BST usually occurs at high temperature (generally greater than 500.degree. C.) in an oxygen containing atmosphere. Therefore, the lower electrode structure formed prior to the HDC deposition should be stable in an oxygen atmosphere and at these temperatures.
Various metals and metallic compounds, and typically noble metals such as Pt and conductive oxides such as RuO2, have been proposed as the electrodes for the HDC materials. However, there are several problems with the materials thus far chosen for the lower electrode in thin-film applications. Many of these problems are related to semiconductor process integration. For example, it has been found to be difficult to use Pt alone as the lower electrode. While Pt is stable in oxygen, it generally allows oxygen to diffuse through it allowing neighboring materials to oxidize. Pt. does not normally stick very well to traditional dielectrics such as silicon dioxide and silicon nitride and Pt can rapidly form a silicide at low temperatures. Therefore, prior art methods have used lower electrodes comprising multiple layers to separate the Pt from the underlying silicon. However, even when multiple layers are used for the lower electrode, a problem remains in that Pt is very difficult to etch when using a pattern. The principle problem is the difficulty in forming volatile halides. For example, etching Pt in fluorine and chlorine gas mixtures is almost a completely physical process until very high temperatures (&gt;300.degree. C.) are reached. Physical etching typically results in redeposition on the sidewalls of photoresist or other pattern definers unless a very sloped sidewall (&lt;65 degrees) is used. If the goal is to etch 1 G-like structures (F-0.18 .mu.m) with reasonable aspect ratios (&gt;1), then sloped sidewalls are a serious problem.
USPTO Backgrounds
USPTO Backgrounds