1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to an electrically reprogrammable memory consisting of a single stacked-gate type storage MOS transistor where each cell is composed of a floating gate and a control gate stacked via an insulator film.
The present invention relates also to a stacked-gate type nonvolatile semiconductor memory where data is written in its cell by injecting electrons into a floating gate.
The present invention relates further to an address decoding circuit adapted for use as a row decoder of a control gate in the above nonvolatile semiconductor memory.
2. Description of the Prior Art
Of the conventional nonvolatile memories, there is known an electrically reprogrammable nonvolatile memory which, as disclosed in Japanese Patent Laid-open No. Hei 1 (1989)-158777 for example, consists of a single stacked-gate type memory MOS transistor where each cell is composed of a floating gate and a control gate stacked via an insulator film.
It has been generally customary heretofore that such a nonvolatile memory is used as shown in FIGS. 1(A) to 1(D) . First in FIG. 1(A), a source S of each memory MOS transistor is connected to a common line COM, a drain D thereof to a bit line BL, and a control gate thereof to a word line WL, respectively.
A writing operation is performed, as shown in FIG. 1(B), by applying voltages of 0 V and 5 V respectively to the source S and the drain D, a positive high voltage of +10 V to 12 V to the control gate, and injecting channel hot electrons from the drain D into the floating gate.
A reading operation is performed, as shown in FIG. 1(C), by applying a voltage of +5 V to the control gate (for turning the word line WL to 5 V), 0 V to the source (common line), a positive voltage of +1 V to the drain (bit line BL), and detecting a current flow in the memory MOS transistor.
Further an erasing operation is performed, as shown in FIG. 1(D), by applying a positive voltage of, e.g., +5 V to the source S, a negative high voltage of, e.g., -9 V to the control gate, and tunneling the electrons from the floating gate to the source S.
In the conventional nonvolatile memory, as shown in FIG. 2(A), a written bit (cell) has a high threshold voltage, while a nonwritten bit has a low threshold voltage. An erasing operation is performed by injecting the electrons, which are in the floating gate of the written bit having a high threshold voltage, into the source S by Fowler-Nordheim tunneling.
However, there may occur a situation where, during an erasing operation, the amount of injected electrons becomes excessive so as to consequently lower the threshold voltage beyond 0 V. In such a condition, the cell to be in a normally off-state during a reading operation is turned to a normally on-state. This situation may naturally cause an erroneous reading. Such excessive injection of electrons is termed over-erasing.
Such over-erasing is derived from delicate variations in the characteristics of the stacked-gate type MOS transistors constituting the cells. It has been extremely difficult in the prior art heretofore to eliminate the characteristic variations.
Consequently, it is necessary to execute bit-by-bit erasing while verifying the level of each bit, and therefore a batch erasing operation is impossible.
It has also been necessary heretofore to once write data in the entire bits on the premise of erasing. Because, in any nonvolatile memory where there exist written cells and nonwritten ones prior to erasing, the threshold voltages are mutually different in the individual cells as shown in FIG. 2(A), and if batch erasing is performed in this condition, all the nonwritten cells are over-erased.
In the prior art, therefore, the entire bits are written once before being erased so that the threshold voltage levels of the cells are equalized, and upon completion of the writing, the bits are erased one by one while being verified as to whether the individual erasing level is proper or not.
Thus, a specific algorithm is needed for reprogramming the data in the conventional memory, and the time required for such operation is extremely long.
It is a matter of course that, in a reading mode, V.sub.CC (e.g., 5 V) is applied to a word line (control gate) at the time of selection, but the voltage needs to be 0 V at the time of nonselection.
Meanwhile in a writing mode, 0 V is applied to the source (common line) and 5 V to the drain (bit line), and a high positive voltage V.sub.PP (+10 to 12 V, e.g. +12 V) is applied to the control gate or word line, whereby a considerably large channel current is caused to flow to inject electrons from the drain into the floating gate by tunnel effect. In this case also, the voltage to the word line needs to be 0 V at the time of nonselection as in a reading mode.
In an erasing mode, the operation is performed by opening the drain (bit line), applying 5 V to the source (common line), and applying a negative high voltage V.sub.PP (e.g., -10 V) to the floating gate or word line, hence transferring the electrons from the floating gate to the source to thereby erase the written data.
Thus, in the conventional memory, as mentioned above, a nonselected word line is turned to 0 V in a reading mode, while a selected word line is driven at 5 V.
In the known memory where a nonselected word line is at 0 V during a reading operation, the voltage applied to a selected word line is 5 V when a supply voltage from a power source is 5 V, and therefore the amplitude of the voltage at the word line is merely 5 V during the reading operation.
In such electrically erasable nonvolatile semiconductor memory, the problem that has been existent heretofore is over-erasing. FIG. 3 is an exemplary diagram of such over-erasing.
A nonwritten bit (cell) has a low threshold voltage, while a written bit has a high threshold voltage. Although the threshold voltage of the written bit is lowered by the erasing, voltage variations are induced in the individual cells so that the distribution width of the threshold voltage is prone to be widened, and there may be a possibility that the threshold voltages of some bits become lower than 0 V. With regard to any bit having a threshold voltage below 0 V, the voltage of the nonselected word line is 0 V in a reading mode so as to consequently bring about a disadvantage that a current flows even in a nonselected state. This phenomenon is derived from over-erasing.
If, in an erasing mode, electrons are transferred from the floating gate to the source even with regard to any nonwritten bit, its threshold voltage is rendered considerably lower than 0 V so as to consequently induce over-erasing with certainty. Therefore, when an erasing operation is performed, it is necessary to execute a procedure of first reading out the data from the entire bits to thereby detect the nonwritten bits, then writing the nonwritten bits by injecting electrons therein to place the entire bits in a written state, and transferring the electrons from the floating gates to thereby achieve the desired erasing.
It is absolutely necessary to avert such over-erasing since a current flow may be caused even in a nonselected state as mentioned above, and therefore the control action by the application of a control voltage fails to be performed properly. For this purpose, it has been customary in the prior art to raise the initial erasing threshold voltage to 1.5-2 V which is sufficiently higher than 0 V, thereby eliminating an undesired condition where some bits (cells) have lower threshold voltages below 0 V due to threshold voltage variations.
In this case, the erasing decision level is raised to or beyond 3-3.5 V or so to consequently reduce the reading speed.
Thus, in the prior art where f the supply voltage from a power source is as low as 5 V, it is required to raise the erasing decision level for avertion of over-erasing as mentioned, hence lowering the reading speed as a result.
In view of the general trend that the rated supply voltage is lowered in design, there is a requirement of setting the supply voltage to 3 V also in an electrically erasable nonvolatile semiconductor memory, and technical development to meet such requirement is presently needed. If the conventional technical concept is adopted in a nonvolatile semiconductor memory where the supply voltage is set to 3 V, it is necessary to supply 0 V to a nonselected word line and 5 V to a selected word line. Because, considering the margin between the threshold voltage of a written cell and that of an erased cell, an amplitude of 3 V is not sufficient at the time of reading the word line, at least 5 V is needed (or even 5 V is still insufficient as described).
In the above case where the supply voltage of 3 V needs to be raised to, e.g., 5 V in a reading mode, such procedure is not desired since it increases the possibility of soft writing in the reading mode. Soft writing identifies a phenomenon where hot electrons, even if few, are generated in the reading mode and are injected into the floating gate by Fowler-Nordheim tunneling since a voltage of 5 V or so is applied to the control gate (1 V to the drain) in the reading mode though not so high as the voltage applied in the writing mode. As the dependency of such soft writing on the gate voltage is extremely great, the voltage applied to a selected word line in the reading mode needs to be minimized. Therefore it is foolish, with respect to the soft writing, to apply a voltage of 5 V or so to the selected word line by boosting the supply voltage of 3 V.
According to the technique of using a stacked-gate cell type nonvolatile memory, it is necessary to change the output of a row decoder, i.e., the voltage of a word line as shown in Table 1 below.
TABLE 1 ______________________________________ Mode Selection state Reading Writing Erasing ______________________________________ Selected V.sub.CC (5V) V.sub.PP (12V) V.sub.BB (-10V) Nonselected 0V 0V V.sub.CC (5V) ______________________________________
A reading operation is performed by applying a voltage of, e.g., 1 V to a drain of a cell (bit line) 0 V to a source thereof (common line), V.sub.CC of, e.g., 5 V to a control gate (word line), and detecting a channel current flow to thereby decide whether any written data is existent or not in the cell. Namely, no current flows if any data is written by injection of electrons into the floating gate, or a current flows in an inverse condition, whereby the writing can be detected in accordance with the presence or absence of the current. It is a matter of course that V.sub.CC (e.g., 5 V,) applied to a selected word line (floating gate) in a reading mode, needs to be 0 V when the word line is not selected.
A writing operation is performed by applying 0 V to the source (common line), 5 V to the drain (bit line), and a positive high voltage V.sub.PP (+10 to 12 V, e.g. 12 V) to the control gate or the word line, thereby causing a considerably large channel current flow to inject electrons from the drain into the floating gate by tunnel effect. In this case also, the voltage to the word line needs to be 0 V at the time of nonselection as in the reading operation.
In an erasing mode, the operation is performed by opening the drain (bit line), applying 5 V to the source (common line), and a negative high voltage V.sub.PP of, e.g., -10 V to the floating gate or the word line, thereby transferring the injected electrons from the floating gate to the source to erase the written data. The above procedure is executed at the time of selecting the word line, whereas V.sub.CC (5 V) is applied to any nonselected word line.
Table 1 is a list showing how the voltage applied to the word line is changed depending on the reading, writing or erasing mode, and also on whether the word line is selected or not.
In Table 1, there are identified two important conditions. The first is that, in the erasing mode, a high negative voltage (e.g., -10 V) needs to be applied to a selected word line. The second is that, in the reading/writing mode, 0 V needs to be applied to a nonselected word line, and V.sub.CC (5 V) or V.sub.PP (12 V) to a selected word line; whereas in the erasing mode, V.sub.CC needs to be applied to a nonselected word line, and a negative voltage V.sub.BB to a selected word line. Thus, the logical level needs to be inverted in accordance with the reading/writing mode and the erasing mode.
Therefore, in the prior art, a p-channel MOS transistor is provided between a word line and a row decoder, and a negative power source consisting of a charge pump and so forth is connected to the word line via another p-channel MOS transistor so that a negative voltage is applicable to the word line in the erasing mode.
Furthermore, the voltage at a nonselected word line is reduced to 0 V in the reading mode by employing a depletion type p-channel MOS transistor or by applying a negative voltage to the gate of the p-channel MOS transistor.
For the purpose of inverting the logical level in accordance with the reading/writing mode and the erasing mode, complicated circuits are provided as disclosed in Japanese Patent Laid-open No. Hei 1 (1989)-158777 and shown in FIGS. 3, 5 and 6 thereof, wherein there are included an inverter for inverting the output of an address decoder, and a switching transistor controlled by an erasing command signal for switching the output of the inverter (inverted one of the address decoder output) and the output of the address decoder.
In the conventional memory where a p-channel MOS transistor is disposed between the address decoder and the word line as mentioned, the word signal transmission speed is lowered by the resistance existing in the p-channel MOS transistor, to consequently raise a problem that an attempt of realizing a faster access fails to be accomplished. Although a reduction of the transmission speed can be decreased by employing a greater p-channel MOS transistor, such means is not desirable since it causes impediment to high density integration of nonvolatile memories.
In addition to the above, a circuit for a negative power source is also required in the prior art, and there exists the further necessity of providing a charge pump circuit and a function for decoding the p-channel MOS transistor disposed between the charge pump and the word line, hence bringing about extreme difficulties in realizing high density integration.
USPTO Backgrounds
USPTO Backgrounds