1. Field
Example embodiments relate to memory devices, and more particularly, to memory devices using a spin hall effect and/or methods of manufacturing and operating the memory device.
2. Description of the Related Art
In general spin transfer torque magnetic random access memories (STT-MRAMs), a transistor is formed in each cell in order to minimize interference between the cell and a peripheral cell. Thus, each cell has a structure in which one transistor and one capacitor are formed, that is, a 1T-1C structure. Accordingly, the size of each cell is 6 F2 or more.
As the need for high integration of semiconductor devices increases, research into further reduction in the size of a unit cell has been actively conducted. As a result, memory cells including only a storage node have been introduced.
Memory cells, that is, cross point devices including only a storage node and not including a cell transistor have been often studied in resistive RAMs (RRAMs).
In RRAMs, current flows through a cell, and thus multiple writing does not occur. For example, when data is simultaneously written in three unit cells, current flows through each unit cell, and thus the magnitude of current applied through a word line (W/L) becomes three times in order to write data in the three unit cells. In other words, the magnitude of current needed for multiple writing in the RRAM changes frequently according to a number of unit cells which are objects of the multiple writing. Thus, an operation is performed through single writing in which data is written in a single unit cell at a time, instead of multiple writing. A memory operation speed is reduced due to the operation through the single writing.
In addition, when the unit cell is a cross point device, leakage current flows to an adjacent cell during a read operation. Thus, because a resistance value of a unit cell to be actually read cannot be accurately measured, errors may occur during the read operation.
USPTO Backgrounds
USPTO Backgrounds