1. Field of the Invention
The present invention relates to control of the power supply voltage and substrate voltage supplied to a transistor and to control of the relationships of a plurality of power supply voltages.
2. Description of the Prior Art
In recent years, in semiconductor integrated circuit devices, control of the power supply voltage and substrate voltage has been implemented for the purpose of smaller power consumption and faster operations. In the power supply level control and substrate level control, however, there is a probability that independently controlling respective ones of the power supply voltage and substrate voltage leads to occurrence of latch-up and occurrence of breakdown voltage degradation due to exceeded transistor breakdown voltage. A conventional solution to such problems is to carry out a substrate level control process not during but after transition of the power supply voltage (see Japanese Laid-Open Patent Publication No. 2000-138348).
In the case of controlling the substrate voltage to a desired level relative to the power supply voltage after a power supply level control process, elongation of the transfer time for the substrate voltage to transfer to a desired level adversely affects the mode transition time of the system. In addition, performing power supply level control and substrate level control processes independent of the respective voltages leads to occurrence of latch-up and occurrence of breakdown voltage degradation due to exceeded transistor breakdown voltage.
USPTO Backgrounds
USPTO Backgrounds