Asynchronous transfer mode (ATM) data transfer is a communication technology in which fixed-size packets of data, known as xe2x80x9ccells,xe2x80x9d are transferred between ATM switching devices (xe2x80x9cswitchesxe2x80x9d). ATM switches may be thought of as circuit oriented, low-overhead packet switches providing virtual circuits. The virtual circuits provide the basis for both switching and multiplexed transmission. Asynchronous time division (ATD) and fast packet switching are alternate terms which have been employed to describe similar transfer technology.
ATM networks transfer information using a cell format that typically conforms to formats adopted by the International Telecommunications Union (ITU). ITU-standard ATM cells have a 5-byte header field and a 48-byte payload field. The header field carries information pertaining to the transport and routing of an ATM cell through switching equipment in a communications network. The payload field is available to transfer user-data. User-data may be digitized video or audio, data from a computer application, or information provided by a higher layer communication protocol.
ATM cells are sent from originating network access equipment, typically located at a customer""s premises, to an ATM network and from the ATM network to destination network access equipment, typically located at a second customer""s premises. The ATM network provides end-to-end routing of the ATM cells.
In general, in one aspect, the invention features an information cell transmission method. The method includes receiving flow control cells at a switch from a collection of multicast virtual circuits and aggregating the flow control cells to form an aggregate flow control cell.
Implementations may include one or more of the following features. Resource management data, such as BRM cell explicit rate data, may be calculated by processing rate control data in each flow control cell using a traffic rate control algorithm. The calculated resource management data may then be stored in a database record associated with the virtual circuit on which the flow control cell was received. Each of the virtual circuits may operatively couple the switch to a destination node. A flow control cell traveling in a forward direction may be received from a source virtual circuit and sent over each virtual circuit in the collection toward a destination node, and the aggregate flow control cell may be sent in a backward direction from the switch over the source virtual circuit toward a source node. The aggregate flow control cell may be sent when a cell counter is above a threshold value. The counter may be incremented when a flow control cell is received at the switch in a forward direction and decremented when the aggregate flow control cell is sent from the switch in a backward direction.
In general, in another aspect, the invention features a network switch. The network switch includes first and second port circuitry and control circuitry. The first port circuitry is operative to exchange flow control cells on a collection of virtual circuits coupling the switch to destination nodes. The second port circuitry is operative to exchange flow control cells on another virtual circuit that couples the switch to a source node. The control circuitry is operatively coupled to the first and second port circuitry. The control circuitry includes circuitry to receive the flow control cells from the first port circuitry, circuitry to aggregate the first flow control cell data to form an aggregate flow control cell, and circuitry to send the aggregate flow control cell to the second port circuitry for transmission toward the source node.
Implementations may include one or more of the following features. The control and/or aggregation circuitry may include a memory having locations to store data received in flow control cells. Each of the memory locations in the aggregation circuitry may be associated with a predetermined one of the virtual circuits served by the first port circuitry. The switch may include multicasting circuitry coupling the first and second port circuitry to each other and configured to receive a cell from the second port circuitry and to send the cell over each of the collection of virtual circuits. The first port circuitry may include circuitry to transmit and receive data cells over multiple physical links. Virtual circuits served by both the first and second port circuitry may share a single physical link or may be on different physical links. The control circuitry may include counter circuitry configured to increment a count when a flow control cell is received in a forward direction from a virtual circuit and to decrement the count when the aggregate flow control cell is transmitted in a backward direction on that virtual circuit. The control circuitry may include circuitry to transmit an aggregate flow control cell only when the count is above a threshold value.
In general, in another aspect, the invention features a network switch including port circuitry, switching circuitry, and control circuitry. The port circuitry is configured to exchange cells on a collection of virtual circuits. The switching circuitry is operatively coupled to the port circuitry to receive cells from a first one of the virtual circuits and to transmit the cells from the first virtual circuit on a group of second virtual circuits. The control circuitry is operatively coupled to the switching circuitry to receive flow control cells from the second virtual circuits, to aggregate data in the flow control cells, and to send the aggregated data over the first virtual circuit in an lo aggregate flow control cell.
USPTO Backgrounds
USPTO Backgrounds