Many types of electronic equipment, to which a commercial AC power supply (AC 100 V) is fed, use a switching power supply circuit to obtain a DC power supply for driving the internal electronic circuits of the electronic equipment. Therefore, it is necessary for the switching power supply circuit to provide a rectifier circuit for converting the commercial AC power supply to a DC power supply. If power factor improvement is not conducted, a high frequency current component and a high frequency voltage component will be caused in the rectifier circuit, and the power factor will be impaired, since a current flows only at the peak of the input voltage to a smoothing capacitor connected to the rectifier circuit.
The power factor is obtained by dividing the input effective power Pi(W) (that is, the product of the same phase components of an input voltage and an input current in an AC circuit), by the apparent power (that is, the product of the effective value of the input voltage and the effective value of the input current). In other words, the effective power is obtained by multiplying the apparent power by a factor (e.g., power factor) determined by a load. When a resistance load is connected to an AC 100 V source, the voltage waveform and the current waveform are in-phase, resulting in a power factor of 1. Due to a load factor other than the resistance, the current phase may sometimes be delayed from the voltage phase. Since the effective power lacks a component corresponding to the delay, it can be necessary to prevent the power factor from being lowered, using a power factor improving circuit, and to suppress the power consumption.
FIG. 6 is a block circuit diagram showing a switching power supply circuit that employs a conventional power factor improving circuit.
The power factor improving circuit is a circuit that sets an AC input voltage and an AC input current to be in phase to improve the power factor, prevents harmful electromagnetic interference (hereinafter referred to as “EMI”), and prevents a high-frequency current and a high-frequency voltage that may break down the equipment.
In the switching power supply circuit shown in FIG. 6, full-wave rectifier 1 performs full-wave rectification of an AC input voltage. The output terminal of full-wave rectifier 1 is connected to the first end of capacitor 2 and a boost circuit. Capacitor 2 removes the high frequency current and the high-frequency voltage caused by the switching operation of output transistor 4, described later. The boost circuit includes boost inductor 3 on the primary side of transformer T, having a first end connected to the output terminal of full-wave rectifier 1, a metal-oxide-semiconductor field-effect transistor (a MOSFET that will be referred to hereinafter as an “output transistor”) 4 connected between the second end of inductor 3 and a reference potential, diode 5, and capacitor 6 connected to the second end of inductor 3 via diode 5. A synchronous rectifying transistor may readily be used in substitution for diode 5. The boost circuit boosts and rectifies the rectified voltage fed from full-wave rectifier 1 and feeds a DC output voltage, e.g. about 400 V, to a load (not shown) connected between output terminal 7 and the ground.
Power factor controller (hereinafter referred to as “PFC”) circuit 10 may be implemented by an integrated circuit that integrates various functions into a unit. PFC circuit 10 includes FB terminal FB for receiving a feedback signal, IS terminal IS for detecting the current flowing through output transistor 4, OUT terminal OUT for providing an output, ZCD terminal ZCD for receiving a zero-cross signal, RT terminal RT for connecting a resistor for determining the oscillation waveform of oscillator 13, and COMP terminal COMP for connecting a phase compensation element. The integrated circuit may include error amplifier 11, formed by a trans-conductance amplifier, PWM comparator 12, oscillator 13, OR-circuits 14a and 14b, RS flip-flop 15, ZCD comparator 16, timer 17, OVP comparator 18 for over-voltage protection, and comparator 19 for detecting an overcurrent.
RT terminal RT of PFC circuit 10 is connected to timing resistor R1, the first end of which is grounded. ZCD terminal ZCD is connected to the first end of inductor 8 on the secondary side of transformer T via resistor R2. The second end of inductor 8 on the secondary side is grounded. OUT terminal OUT is connected to the gate of output transistor 4. The source terminal of output transistor 4 is connected to the second end of current detecting resistor R3, the first end of which is grounded. The connection point of the source terminal of output transistor 4 and the second end of current detecting resistor R3 is connected to IS terminal IS. Output terminal 7 is grounded via dividing resistors R4 and R5 connected in series to each other. The connection point of dividing resistors R4 and R5 is connected to FB terminal FB. COMP terminal COMP is grounded via capacitor C1. A series circuit of resistor R6 and capacitor C2 are connected in parallel to capacitor C1. PFC circuit 10 also includes a VCC terminal for receiving the power supply voltage and a GND terminal for grounding, although these terminals are not illustrated in FIG. 6.
PFC circuit 10 sets the inductor current in the boost circuit and the output voltage to the load to be in phase.
Error amplifier 11 in PFC circuit 10 receives reference voltage Vref via the non-inverting input terminal of error amplifier 11. The inverting input terminal of error amplifier 11 is connected to FB terminal FB. The output from error amplifier 11 is connected to COMP terminal COMP and the inverting input terminal of PWM comparator 12. The output from PWM comparator 12 is connected to the reset terminal of RS flip-flop 15 via OR-circuit 14a. Oscillator 13 is connected to timing resistor R1 via RT terminal RT. Oscillator 13 generates an oscillating output having a saw-tooth-waveform and a gradient corresponding to the resistance value of timing resistor R1. The oscillating output is fed to the non-inverting input terminal of PWM comparator 12.
ZCD comparator 16 receives reference voltage Vzcd via the non-inverting input terminal of ZCD comparator 16. The inverting input terminal of ZCD comparator 16 is connected to ZCD terminal ZCD. The output from ZCD comparator 16 is connected, together with the output from timer 17, to the set terminal of RS flip-flop 15 via OR-circuit 14b. The Q output Q from RS flip-flop 15 is fed to the gate terminal of transistor 4 via OUT terminal OUT. OVP comparator 18 receives reference voltage Vovp on the inverting input terminal of OVP comparator 18. The non-inverting input terminal of OVP comparator 18 is connected to FB terminal FB. The output from OVP comparator 18 is connected to the reset terminal of RS flip-flop 15 via OR-circuit 14a. Comparator 19 receives reference voltage Vovc on the inverting input terminal of comparator 19. The non-inverting input terminal of comparator 19 is connected to IS terminal IS. The output from comparator 19 is connected to the reset terminal of RS flip-flop 15 via OR-circuit 14a. 
The power factor control performed in the switching power supply circuit shown in FIG. 6 is called a “fixed-ON-period control method.” The fixed-ON-period control method is applied to electronic equipment, and consumes a small amount of power, e.g. around 250 W or lower.
The control methods used in power factor improving circuits include a peak current mode control (hereinafter referred to a “PCMC”), an average current mode control (hereinafter referred to an “ACMC”), and the like.
Next, fixed-ON-period control by PFC circuit 10 as shown in FIG. 6 will be described.
ZCD comparator 16 detects the voltage value at which the current flowing through inductor 3 on the primary side of transformer T in the boost circuit becomes zero. ZCD comparator 16 detects the zero inductor current, sets the output of ZCD comparator 16 at a high level (H-level), and feeds the set signal at the H-level to RS flip-flop 15. As the set signal at the H-level is fed to RS flip-flop 15, RS flip-flop 15 sets its Q output Q at the H-level. Q output Q from RS flip-flop 15 is outputted from OUT terminal OUT, bringing output transistor 4 into the ON-state. The output from ZCD comparator 16 is also fed to oscillator 13. Oscillator 13, triggered by the output from ZCD comparator 16, starts generating a saw-tooth oscillation output (saw-tooth-wave signal) at the time at which output transistor 4 becomes ON. As the saw-tooth-wave signal reaches a predetermined value, oscillator 13 stops generating the oscillation output, and rests the oscillation output at an initial value to wait for a next trigger input.
The divided voltage obtained by dividing the DC voltage fed to output terminal 7 with resistors R4 and R5 is fed back to FB terminal FB. Error amplifier 11 generates an error signal obtained by amplifying the difference between the feedback voltage and reference voltage Vref. PWM comparator 12 compares the error signal with the saw-tooth-wave signal from oscillator 13. As PWM comparator 12 detects that a value of the saw-tooth-wave signal has reached a value of the error signal, PWM comparator 12 feeds a reset signal to RS flip-flop 15. As the reset signal is fed to RS flip-flop 15, Q output Q from RS flip-flop 15 is set at a low-level (hereinafter referred to as an “L-level”). As Q output Q set at the L-level is outputted from OUT terminal OUT of PFC circuit 10, output transistor 4 is brought into the OFF-state.
If the weight of the load connected to output terminal 7 of the switching power supply circuit is constant, the error signal will be constant. The ON-period of output transistor 4 is a period of time from the time at which the saw-tooth-wave signal starts from the reference value to the time at which the value of the saw-tooth-wave signal reaches the value of the error signal. Therefore, the ON-period of output transistor 4 is controlled to be constant. However, since the input to the switching power supply circuit is an AC voltage, the voltage across inductor 3 changes depending on the phase angle of the AC voltage. Therefore, the gradient of the inductor current flowing through inductor 3 on the primary side of transformer T changes depending on the input voltage. The peak values of the inductor current that are the current values at the times at which output transistor 4 is brought into the OFF-state cause an AC waveform.
By the operation described above, zero-current switching is performed by the zero-cross switching control in PFC circuit 10 using the fixed-ON-period control method. By the zero-current switching, a low-loss and low-noise operation is realized. However, since the inductor current is reset in association with every ON and OFF of output transistor 4, the peak of the inductor current becomes high. (The peak current is twice as high as the effective current.) Therefore, the inductance becomes too large in the switching power. supply circuit, which can feed a high wattage of DC power. To avoid the latter problem, a continuous control method is usually employed.
In the power factor improving circuit described above, which includes the described boost circuit, PFC circuit 10 incorporates an over-voltage-protection function for preventing the voltage boosted by the boost circuit from rising limitlessly when an anomaly is caused. In more detail, OVP comparator 18 connected to FB terminal FB monitors the rise of the feedback voltage. When the feedback voltage rises to reference voltage Vovp, which is higher than reference voltage Vref by a certain percentage, a reset signal is fed to RS flip-flop 15 for stopping the switching operation of output transistor 4.
FIG. 7 shows wave charts describing a voltage waveform and a current waveform at the start of the power supply operation and at the transient response in the conventional power factor improving circuit.
Since no soft-start circuit is employed in operations as described above, an over voltage is caused at the start of the power supply operation and at the transient response. The wave chart (a) in FIG. 7 describes the output voltage fed to the load connected to output terminal 7. The wave chart (b) in FIG. 7 describes the gate signal that controls the ON and OFF of output transistor 4. The wave chart (c) in FIG. 7 describes the envelope connecting the peak values of the inductor current. When reference voltage Vovp for over-voltage protection is set, for example, at 400 V, output transistor 4 is turned OFF as shown in the wave chart (b) in FIG. 7, as the voltage fed to the load exceeds the set value of 400 V even if only a little, as described in the wave chart (a) in FIG. 7. As output transistor 4 is turned OFF and the switching operation is stopped, the current flowing through inductor 3 on the primary side of transformer T becomes zero. (If diode 5 is not present, the current flowing through inductor 3 on the primary side of transformer T will keep decreasing to the negative side.) FIG. 7 also describes the steady-state operations of a conventional power factor improving circuit, e.g., when an overshoot is caused on the output voltage in the steady state operation of the conventional power factor improving circuit, similarly resulting in an abrupt stopping of the switching operation.
In the state in which a current is flowing through inductor 3 on the primary side of transformer T, a magnetic field is generated around inductor 3. Due to the magnetic field, magneto striction (mechanical deformation) is caused in the core of transformer T. When the inductor current becomes zero due to the zero-current switching, the magnetic field that causes magneto striction in the core vanishes, as output transistor 4 is made to stop switching in the usual switching operation. However, the deformation due to the magneto striction has not been completely removed yet. As a next switching period starts as described in the wave chart (b) in FIG. 7 before the deformation is removed from the core and the core is restored to its original shape, an inductor current flows through inductor 3 on the primary side of transformer T, causing magneto striction again in the core of transformer T.
While the operation described above is repeated, inductors 3 and 8 in transformer T are forced to vibrate mechanically at the switching frequency. When the core is vibrating at the switching frequency and the switching frequency is not in the audible range, buzzing of transformer T is not caused (although an ultrasonic wave may be generated). On the other hand, if the switching operation is stopped suddenly, a vibration that releases the magneto striction energy at the mechanical and natural vibration frequency of the core is caused. If the natural vibration frequency is in the audible range, a single shot of sound will be caused at the time at which the switching operation is stopped. Therefore, when a sudden change is caused in the input current, buzzing is caused in transformer T (core buzzing is caused).
At the time at which the starting operation of the power factor improving circuit is completed, a single shot of buzzing is caused as described above, without exception. For preventing a single shot of buzzing, in conventional circuits a soft-start circuit is added to prevent overshooting at the start of the operation of the power factor improving circuit. See Japanese Unexamined Patent Application Publication No. 2007-295800, in particular paragraphs [0042] through [0049] and FIG. 7.
The buzzing caused by the stopping of a switching operation further causes a troublesome noise from household equipment (such as a TV set) used in a living room or a similar quiet environment.
The method disclosed in Japanese Unexamined Patent Application Publication No. 2007-295800, that adds a soft-start circuit to prevent overshooting at the start of the power supply operation, exhibits some effectiveness toward preventing the buzzing caused at the start of the power supply operation. However, when PFC circuit 10 is implemented by an integrated circuit, pins used solely for the soft start are needed. It is possible for a semiconductor device (IC) having many pins (16 pins or 20 pins) to provide pins solely for the soft start. However, it is difficult for a semiconductor device (IC) having few pins (8 pins for example) to provide pins solely for the soft start. The soft-start circuit is provided so as not to generate any over voltage at the start of the power supply operation. Since the soft-start circuit stops the switching operation as soon as an over voltage is detected in the steady state of operation after the starting operation is over, it is impossible for the soft-start circuit, in the steady state, to prevent the buzzing caused by an over voltage from occurring.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a switching power supply circuit that prevents the buzzing caused by the stopping of a switching operation with an integrated circuit that has a small number of pins.
USPTO Backgrounds
USPTO Backgrounds