Flash memory is composed of flash memory cells that store bits, with a flash memory Single Level Cell (SLC) storing a single bit and a flash memory Multi-Level Cell (MLC) storing multiple bits. When reading the stored bits from the flash memory cells, the bits may toggle from one read to the next. These bits are termed toggle bits. The toggle bits are information that are stored on the tail of a particular state of a flash memory cell, and are intrinsically invalid as the toggle bits are in-between normal states.
One solution to the problem of toggling bits is to iteratively test each of the possible values of the toggling bits. For example, a page in flash memory may have N toggling bits. This solution iteratively flips through the N toggling bits (potentially through each of the 2N possibilities), testing the possibilities using an error correction algorithm until the error correction algorithm indicates that one of the possibilities is valid. However, this solution is time-intensive (potentially requiring testing of 2N possibilities) and may not yield the correct result (since the error correction algorithm may indicate that multiple of the 2N possibilities are “valid”).
Another solution is to read the flash memory cell several times and use the majority count to decide if the toggling bit should be a one or zero. Then, the data pattern is again fed into a decoding algorithm or other error correction algorithm in order to determine if a valid code word results. However, the values of the toggling bits are often erratic, so that a majority count may not yield the correct result.
Still another solution is to add more parity bytes and use a more complex error correction decoder. Parity bytes and error correction coding are typically used to correct for errors in reading the flash memory cells. The additional parity bytes and more complex decoder, while potentially correcting for the toggling bits, may overly complicate the operation of the flash memory.
USPTO Backgrounds
USPTO Backgrounds