1. Field of the Invention
The present invention relates to memory devices to be placed in the memory address space of a computer using a microprocessor.
2. Description of the Prior Art
FIGS. 2A and 2B show in block diagrams a memory device using 64 kilobit DRAM (hereinafter "64 KDRAM") according to the prior art and the essential part thereof, respectively. FIGS. 3A and 3B illustrate in block diagrams a memory device using 256 KDRAM according to the prior art and the essential part thereof, respectively. In the figures there is shown a microprocessor or system bus 1 of a computer using a microprocessor. A number, n, of memory arrays 2 are placed in the memory address space of, for example, one megabyte of the system bus 1. Each memory array 2 is composed of eight 64-KDRAMs (in FIG. 2) or eight 256-KDRAMs (in FIG. 3).
Denoted at 3 is an address decoding circuit 3 for selecting one memory array from the n memory arrays 2. Denoted at 4 is a memory timing circuit for the memory arrays 2, and at 5 an address multiplexer for generating a memory address for each memory array. Denoted at 6, 7, and 8 are row address strobe (RAS), column address strobe (CAS), and write enable (WE) driver circuits, respectively, for each memory array 2 selected by the address decoding circuit 3. Denoted at 9 is a refresh controller for determining the refreshing timing of the memory array 2, at 10 a refresh address counter counted up or down on demand by the refresh controller 9, and at 11 an arbiter for performing arbitration between the demand from the refresh controller 9 and the demand for access to the memory from the microprocessor or system buss 1. The address decoding circuit 3 and the address multiplexer 5 constitute memory array selecting means and address generating means, respectively, of this memory device.
In operation, on access to a memory array 2, the microprocessor or system bus 1 outputs address information (a) corresponding to the address space, command information (b) for read or write control and its timing, and bit parallel data (c). The address decoding circuit 3 then tries to determine which memory array 2 has been selected by decoding with the aid of a few upper bits of the address information (a) and the command information (b). If any memory array 2 has been selected, it feeds the arbiter 11 with a RAM demand signal (d). It also outputs a memory bank selecting signal (e) for the selected memory array 2.
The RAS, CAS, and WE driver circuits 6, 7, and 8 then feed the selected memory array 2 with strobe signals (f), (g), and (h) according to the timing signals generated by the memory timing circuit 4. The address multiplexer signal (i) from the memory timing circuit 4 allows the address multiplexer 5 to switch between the row and column addresses for allocating the row or column of the memory array 2 from the lowest bit of the address information so as to access a given address of the memory array 2 selected by the address decoding circuit 3. At this point, the data are transferred through the data bus (c). The refresh demand signal (j) from the refresh controller 9 allows refresh of all the memory arrays 2. In the devices of FIGS. 2 and 3, only the RAS is refreshed. The address for this is output from the the refresh address counter 10, and a READY signal (k) is fed to the microprocessor or system bus 1. The arbiter 11 makes a decision on the dispute between the memory access and refresh demands.
If the microprocessor or system bus 1 has a capacity of 20 bits of the address information (a) and 8 bits of the data (c), the lower 16 bits (A0-A15) and the upper 4 bits (A16-A19) are used for a memory address and address decoding, respectively, in the system using 64 KDRAM of FIG. 2, and each memory array 2 has 64 kilobytes of address space. The lower 18 bits (A0-A17) and the upper 2 bits (A18-A19) are used for a memory address and address decode, respectively, in the system using 256 KDRAM, and each memory array 2 has 256 kilobytes of address space.
However, the capacity of the aforementioned prior memory devices can be expanded by units of only 64 kilobytes in the memory device using 64 KDRAMs or only 256 kilobytes in the memory device using 256 KDRAMs. If the capacity of the latter memory device is desired to be expanded by 64 kilobytes, it is necessary to change the address decoding conditions and to use an entire memory array of 256 KDRAMs.
USPTO Backgrounds
USPTO Backgrounds