Effective communications between processors are important to the performance or the capabilities of architectures and elements that employ processors. One area of processor communications that generally inhibits system performance is the timing of communications between processors. Communications protocols that delay in transmitting or receiving messages may have a negative impact on the system. This may be due, in part, to the substantive nature of the messages being communicated between processors. In some cases, the message that is being communicated may trigger an action to be performed before the destination processor proceeds to a next task. When communications between processors are delayed, the receiving processor may act inappropriately in executing functions that disregard the incoming message. In certain scenarios, after the message has been properly received by the destination processor, conditions in the corresponding system or environment may have changed, thereby making the message irrelevant or moot. In other scenarios, multiple reads for an entity that received the interrupt or multiple writes for a broadcast message to elements within a system may result in redundancy or increased traffic, which may in turn inhibit processing speeds. Accordingly, messages between processors need to be communicated quickly and accurately to intended targets such that a processor receiving the message may act properly in response to receipt of the message.
USPTO Backgrounds
USPTO Backgrounds