OTP (One-Time Programmable) read only memory is used in integrated circuits for a variety of applications including nonvolatile memory applications. They may be used as a single memory cell, or in arrays of memory cells to provide unique chip identifications and to set operating parameters such as clock multipliers and voltage levels for devices such as microcontrollers and microprocessors, and also high-density memory applications for various applications. They may also be used to configure, customize, and repair a chip after testing, in order to repair a controller's cache memory array. One-time programmable memories are typically implemented using charge storage, fuse, or anti-fuse approaches. Charge storage approaches have typically involved defining a bit value based on charge stored on an insulated metal-oxide semiconductor (MOS) type gate structure. Such charge storage approaches, however, are not practicable with current and deep sub-micron technologies that feature very thin gate oxide because of the high gate leakage current that prevents a long retention time of the information. And other type of OTP memory is capacitor type, wherein oxide breakdown is used to program the capacitor type memory cells, as published, U.S. Pat. No. 7,102,951 and U.S. Pat. No. 6,700,151.
In FIG. 1A, a memory cell 100 comprises an NMOS transistor 102, a high voltage device 104, and a sense circuit 105 (depicted by broken line) formed from a program/sense NMOS transistor 106 and a sense amplifier 108. The MOS memory cell device 102 has two terminals, one coupled to VSENSE/VPROG terminal 112, and the other coupled to the high voltage device 104. The memory cell 100 is used in a MOS logic circuit operating with a VDD (supply) voltage of about 1.2 V. Accordingly, the voltage supply terminal 112 (VSENSE/VPROG) is set at about 1.2 V during sensing (reading) and in excess of about 3 V during programming. The high voltage device 104 is positioned between the memory cell 102 and the sense amplifier 105 to protectively shield it from the high programming voltage. The program/sense transistor 106 is an NMOS transistor with the sense amplifier 108 coupled at its drain.
When programming the memory cell, a PROG/SENSE control signal 116 is input at the gate of the program/sense transistor 106 to turn it on. And when the memory cell is to be sensed, the PROG/SENSE control signal 116 is turned off. During programming when the high VPROG voltage 112 is applied at the voltage supply terminal, both the high voltage device and program/sense transistor 106 are “on” thereby causing the high program voltage to be applied across the memory cell 102, which is initially open. A current path is provided from the memory cell 102 to ground through the high voltage device 104 and program/sense transistor 106. Thus, as the memory cell breaks down, current is tunneled through it until its resistance is sufficiently reduced (i.e., until it is “blown”). During sensing, on the other hand, the lower VDD voltage is applied at the memory cell voltage supply terminal 112, and the program/sense transistor 106 is turned off, which forces current passing through the memory cell (if it has been blown) to flow substantially into the sense amplifier 108.
However, the VSENSE/VPROG terminal 112 as a common electrode is heavily loaded, when the memory array is increased. Hence, the common electrode 112 should flow very high current when the memory array is big, which causes a data pattern sensitivity. For example, maximum current should be flown through the common node, when all the memory cells are programmed to “1” (blown), while no current should be flown when programming all “0” (not blown). This means that the common electrode 112 may be dropped by high current when programming all “1”, which may increase programming time to break down the oxide, because programming voltage has been changed with all “1” programming when the memory array is increased. Furthermore, a resistance after blowing may be different depending on data pattern. In order to increase density with OTP memory, pattern sensitivity should be reduced.
And in FIG. 1B, another prior art is illustrated as published, U.S. Pat. No. 5,675,547, wherein memory cells are connected to multiple word lines 153, 173, 174 and 175, and multiple bit lines 154 and 156, and a common plate line 155 is connected to multiple memory cells as well. The OTP (one time programmable) memory circuit 150 includes a sense amp 176 for programming and reading data which is stored in the memory cell including a capacitor 152 as a one-time programmable storage element and a pass transistor 151 as an access device. The capacitor 152 is destroyed or not for storing a data. However, the common plate line may cause data pattern sensitivity when programming all “1” (blown) or all “0” (not blown). Furthermore, the common plate line 155 is raised to high voltage for programming a selected row 153, but other rows 173, 174 and 175 are not selected, such that gate oxide of unselected pass transistors are overstressed after the selected capacitor is destroyed, because unselected word lines 173, 174 and 175 keep low while the common plate line 155 is asserted to high voltage 3V, for instance. Hence, gate oxide of unselected memory cell may be destroyed during programming. In order to avoid overstress, additional biased transistor is added, as published, U.S. Pat. No. 6,927,997, but additional transistor increases cell area. Furthermore, the local bit line 154 is heavily loaded with conventional sensing scheme which includes differential amplifier, so that charging time of the local bit line is slow, which is one of obstacles for achieving fast read operation.
In this respect, there is still a need for improving the read only memory, which realizes fast random access. In the present invention, bit line is multi-divided for reducing parasitic capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for reading the divided bit lines. When programming the OTP memory, in particular, the multi-stage sense amps serve as a detector circuit, such that the detector circuit detects whether the capacitor is blown or not, and generates a feedback signal after the capacitor is blown. Thus, the feedback signal is used to cut off a current path from the capacitor to the bit line. Thereby voltage drop of a plate of the capacitor is reduced during program, which realizes more uniform programming with less voltage drop of the plate.
The memory cell can be formed on the surface of the wafer. And the steps in the process flow should be compatible within the current CMOS manufacturing environment. Alternatively, the memory cell can be formed from thin film polysilicon layer, because the lightly loaded bit line can be quickly discharged by the memory cell even though the thin film pass transistor can flow relatively low current. In doing so, multi-stacked memory is realized with thin film transistor, which can increase the density within the conventional CMOS process with additional process steps, because the conventional CMOS process is reached to a scaling limit for fabricating transistors on a surface of a wafer. In addition, a body-tied TFT (Thin Film Transistor) transistor can be used as the thin film transistor for alleviating self heating problem of short channel TFT.
USPTO Backgrounds
USPTO Backgrounds