The inventive concepts relate to a delay locked loop and a memory device including the same, and more particularly, to a delay locked loop to cancel an offset and a memory device including the same.
When a clock applied from the outside is used inside an electronic device, a clock skew may occur in internal circuits. To compensate the clock skew, a delay locked loop (DLL) may be used. A delay locked loop (DLL) may be used for an electronic device to be synchronized with an external clock.
A general delay locked loop may include replica circuits that replicate internal circuits to synchronize an electronic device with an external clock. However, the internal circuits and the replica circuits may become different from one another due to process voltage temperature (PVT) variations. Because of this, there is a problem that an electronic device is not synchronized with a clock applied from the outside.
USPTO Backgrounds
USPTO Backgrounds