1. Field of the Invention
The present invention relates to a clock signal amplifier circuit, a control method thereof, and a clock signal distribution circuit, and more particularly, to a clock signal amplifier circuit capable of performing a high-speed operation, a control method thereof, and a clock signal distribution circuit capable of performing a high-speed operation.
2. Description of Related Art
A clock signal distribution circuit which incorporates a CML (Current Mode Logic) driver (for example, disclosed in Japanese Unexamined Patent Application Publication No. 2008-227696) is used as a high-speed clock signal distribution means in an electric circuit such as an LSI (Large Scale Integration). FIG. 5 is a block diagram showing a configuration of a common clock signal distribution circuit 400. First, the configuration of the clock signal distribution circuit 400 will be described with reference to FIG. 5. As shown in FIG. 5, the clock signal distribution circuit 400 includes a PLL (Phase Locked Loop) 41, a test clock generator 42, a CML driver 43, a CML driver 44, and a selector 45.
The PLL 41 serves as a clock generator and outputs a clock signal CLK and a clock signal CLKB to the selector 45. The clock signal CLKB is an inverted signal of the clock signal CLK. The test clock generator 42 outputs a test clock signal TST and a test clock signal TSTB to the selector 45.
The selector 45 operates according to a select signal SEL. For example, when the select signal SEL is a HIGH signal, the selector 45 performs a normal operation. In this case, the selector 45 outputs the clock signal CLK and the clock signal CLKB to the CML driver 43. On the other hand, when the select signal SEL is a LOW signal, the selector 45 performs a test mode operation. In this case, the selector 45 outputs the test clock signal TST and the test clock signal TSTB to the CML driver 43. Note that the test clock signal TSTB is an inverted signal of the test clock signal TST.
The CML driver 43 amplifies the clock signals CLK and CLKB or the test clock, signals TST and TSTB, and outputs the amplified signals to the CML driver 44. The CML driver 44 amplifies the signals output from the CML driver 43, and outputs the amplified signals from output terminals OUT and OUTB as output signals.
In other words, the clock signal distribution circuit 400 can be switched between a normal operation state and a test mode operation state by changing the select signal SEL supplied to the selector 45.
Next, the CML drivers 43 and 44 will be described. FIG. 6 is a block diagram showing a configuration of the CML driver 43 serving as a common CML driver. FIG. 7 is a circuit diagram of the CML driver 43. As shown in FIG. 6, input signals IN and INB are supplied to the CML driver 43. The CML driver 43 amplifies the input signals IN and INB, and outputs the amplified signals from output terminals OUT and OUTB as output signals.
Subsequently, the configuration of the CML driver 43 will be specifically described with reference to FIG. 7. As shown in FIG. 7, the CML driver 43 includes a constant current source 46, Nch (N-channel) transistors 47a and 47b, and pull-up resistors 48a and 48b. 
One end of the constant current source 46 is connected to a ground voltage. The other end of the constant current source 46 is connected to the sources of the Nch transistors 47a and 47b. The drain of the Nch transistor 47a is connected to a supply voltage through the pull-up resistor 48a. The gate of the Nch transistor 47a receives the input signal INB. The drain of the Nch transistor 47b is connected to the supply voltage through the pull-up resistor 48b. The gate of Nch transistor 47b receives the input signal IN. The output terminal OUT is connected to a node between the Nch transistor 47a and the pull-up resistor 48a. The output terminal OUTB is connected to a node between the Nch transistor 47b and the pull-up resistor 48b. 
Next, an operation of the CML driver 43 will be described. The CML driver 43 is a differential amplifier circuit. Thus, the CML driver 43 amplifies the input signals IN and INB, and outputs the amplified signals from the output terminals OUT and OUTB as output signals. Here, the CML driver 44 has the same configuration as the CML driver 43, and thus description thereof will be omitted.
However, the present inventor has found a problem described below. A selector circuit is used so as to select the clock signal or the test clock signal in the clock signal distribution circuit 400. Generally, the selector circuit has a low frequency limit. This inhibits a high-speed operation of the clock signal distribution circuit. Further, the number of circuit stages increases because of the inserted selector circuit, thereby failing to suppress jitter.
USPTO Backgrounds
USPTO Backgrounds