1. Field of the Invention
The present disclosure generally relates to the field of fabricating semiconductor devices, and, more particularly, to metallization systems including low-k dielectric materials.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of semiconductor fabrication, since, here, it is essential to combine cutting-edge technology with volume production techniques. One important aspect in realizing the above strategy is seen in continuously improving device quality with respect to performance and reliability, while also enhancing the diversity of functions of semiconductor devices. These advances are typically associated with a reduction of the dimensions of the individual circuit elements, such as transistors and the like. Due to the continuous shrinkage of critical feature sizes, at least in some stages of the overall manufacturing process, frequently, new materials may have to be introduced to adapt device characteristics to the reduced feature sizes. One prominent example in this respect is the fabrication of sophisticated metallization systems of semiconductor devices in which advanced metal materials, such as copper, copper alloys and the like, are used in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 and significantly less, in which case these materials may also be referred to as ultra low-k dielectrics (ULK). By using highly conductive metals, such as copper, the reduced cross-sectional area of metal lines and vias may at least be partially compensated for by the increased conductivity of copper compared to, for instance, aluminum, which has been the metal of choice over the last decades, even for sophisticated integrated devices.
On the other hand, the introduction of copper into semiconductor manufacturing strategies may be associated with a plurality of problems, such as sensitivity of exposed copper surfaces with respect to reactive components, such as oxygen, fluorine and the like, the increased diffusion activity of copper in a plurality of materials typically used in semi-conductor devices, such as silicon, silicon dioxide, a plurality of low-k dielectric materials and the like, copper's characteristic of generating substantially no volatile byproducts on the basis of typically used plasma enhanced etch processes, and the like. For these reasons, sophisticated inlaid or damascene process techniques have been developed in which typically the dielectric material may have to be patterned first in order to create trenches and via openings, which may then be coated by an appropriate barrier material, followed by the deposition of the copper material. Consequently, a plurality of highly complex processes, such as the deposition of sophisticated material stacks for forming the interlayer dielectric material including low-k dielectrics, patterning the dielectric material, providing appropriate barrier and seed materials, filling in the copper material, removing any excess material and the like, may be required for forming sophisticated metallization systems, wherein the mutual interactions of these processes may be difficult to assess, in particular, as material compositions and process strategies may frequently change in view of further enhancing overall performance of the semiconductor devices.
For example, the continuous shrinkage of the critical dimensions may also require reduced dimensions of metal lines and vias formed in the metallization system of sophisticated semiconductor devices which may lead to closely spaced metal lines, which in turn may result in increased RC (resistive capacitive) time constants. These parasitic RC time constants may result in significant signal propagation delay, thereby limiting overall performance of the semiconductor device, although highly scaled transistor elements may be used in the device level. For this reason, the parasitic RC time constants may be reduced by using highly conductive metals, such as copper, in combination with dielectric materials of very reduced permittivity, also referred to as ULK materials, as previously discussed. On the other hand, these materials may exhibit significant reduced mechanical and chemical stability, for instance when exposed to the various reactive etch atmospheres and mechanical stress, for instance during etch processes, resist removal, the removal of excess metal by chemical mechanical polishing (CMP) and the like.
For example, the reduced mechanical stability of the low-k dielectric material, in particular when ULK materials are considered, may result in increased damage during the CMP process, which may typically require the provision of an additional cap layer, which may be removed during the chemical mechanical polishing process. However, in sophisticated applications, a high degree of damaging may still be observed, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 at a manufacturing stage in which a metallization system is to be formed on the basis of sensitive dielectric materials in combination with highly conductive metals. As illustrated, the semiconductor device 100 comprises a substrate 101 above which may be formed a plurality of device levels, i.e., various levels in which circuit elements and other device features may be formed. For example, the substrate 101 may have incorporated therein an appropriate semiconductor layer in and above which circuit elements, such as transistors and the like, may be formed in accordance with design rules of the device 100. For instance, in complex semiconductor devices formed on the basis of CMOS technology, transistors having a gate length of 50 nm and less may be provided in the device level. Furthermore, any appropriate contact structure connecting to the circuit elements may be provided so as to act as an interface between the circuit elements and a metallization system 120 of the semiconductor device 100. For convenience, any such contact structures are not shown in FIG. 1a. The metallization system 120 may comprise a plurality of metallization layers 110 and 130, wherein the number of metallization layers in the system 120 may depend on the overall complexity of the semiconductor device 100. For example, the metallization layer 110 comprises an appropriate dielectric material 111, such as a low-k dielectric material, whose dielectric constant may be 3.0 or significantly less, such as 2.0, when ULK materials are considered. It should be appreciated that the dielectric material 111 may comprise different material compositions, depending on the overall device requirements. Furthermore, one or more metal lines 112 may be formed in the dielectric material 111 and may represent respective metal lines or any other metal regions as required according to the overall circuit layout of the device 100. The metal line 112 may comprise a conductive barrier material 112A, which may act as an interface between a highly conductive metal 112B, such as copper, copper alloy and the like, and the dielectric material 111. Hence, the conductive barrier material 112A may suppress any diffusion of reactive components, such as oxygen, fluorine and the like, to the copper-based metal 112B in order to suppress any unwanted chemical reaction, while on the other hand out-diffusion of copper atoms into the surrounding dielectric material 111 may also be suppressed by the barrier material 112A. For example, tantalum nitride, tantalum and the like are well-established barrier materials used in view of maintaining a desired chemical and mechanical integrity of the metal 112B. Moreover, an etch stop layer 113 may be formed on the dielectric material 111 and on the metal line 112, wherein the etch stop layer 113 may, in some approaches, also act as a cap material for confining the metal 112B.
Similarly, the metallization layer 130 may comprise a low-k dielectric material 131, such as a ULK material, when the metallization layer 130 may represent a critical metallization level with respect to parasitic RC time constants. That is, in complex metallization systems, such as the system 120, at least some metallization levels may require a reduced parasitic capacitance between neighboring metal lines, thereby demanding a very low dielectric constant of the dielectric material 131. On the other hand, the reduction of the dielectric constant is typically associated with a reduced density and thus mechanical stability of the dielectric material 131, which may affect the further processing of the device 100. For example, exposure to reactive atmospheres during process steps, such as etching, resist stripping and the like, may cause the creation of a damaged surface area which may result in reliability concerns and non-uniformities during the further processing. Furthermore, the reduced mechanical stability may also lead to increased yield loss during planarization processes, such as CMP, which is conventionally addressed by providing an additional dielectric cap layer 135 which is comprised of a dielectric material of increased stability, such as silicon dioxide and the like, thereby reducing degradation of severe defects during the CMP process to be applied in a later manufacturing stage. Moreover, in the manufacturing stage shown, the metallization layer 130 may further comprise an interconnect structure 132 including a metal line 132L and a via 132V that connects to the metal line 112 of the metallization layer 110. The interconnect structure 132 may also comprise a barrier layer 132A which may have a similar composition to the barrier layer 112A. In the manufacturing stage shown, the interconnect structure 132 may be filled with a conductive metal, such as copper, which may be provided in an amount so as to reliably fill the metal line 132L. Hence, a certain amount of excess material may have to be provided, which may be removed by a CMP process.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of well-established process techniques including the formation of any circuit elements, such as transistors and the like, in and above the substrate 101. Thereafter, an appropriate contact structure may be formed using well-established techniques and thereafter the metallization layer 110 may be formed by depositing the dielectric material 111 and patterning the same using well-established lithography and etch techniques. Next, the barrier layer 112A may be formed, followed by the electrochemical deposition of the copper material, an excess material of which may be removed by CMP. It should be appreciated that a corresponding cap material may also be used for forming the metallization layer 110 when the dielectric material 111 may suffer from a reduced mechanical stability. In this case, similar techniques may be used as will be described when referring to the metallization layer 130. Thus, after planarizing the surface topography, the etch stop layer 113 may be formed, for instance comprised of silicon carbide, nitrogen-containing silicon carbide and the like, followed by the deposition of the dielectric material 131 which may include, at least partially, a highly sensitive portion having a reduced dielectric constant. Next, the cap layer 135 may be formed, for instance in the form of silicon dioxide and the like, using well-established thermally activated chemical vapor deposition (CVD), plasma assisted CVD and the like. Next, an appropriate patterning regime may be used, such as a dual damascene or dual inlaid technique, in which a via opening and a trench opening may be formed in the dielectric material 131 and the cap layer 135 followed by the deposition of the barrier material 132A and the filling in of the copper material. Next, a CMP process 102 may be performed to remove excess material of the copper and the barrier layer 132A. During a CMP process, typically, an appropriate slurry material may be applied to the surface to be polished, which is selected such that a desired chemical reaction may be induced. At the same time, a physical polishing component may be created by relatively moving the surface to be polished with respect to a polishing pad, thereby obtaining a total removal rate that is determined by the characteristics of the slurry material and the parameters of the polishing process, such as down force, speed of the relative motion and the like. Due to the physical component, therefore, certain mechanical stress is exerted to the surface to be polished and thus to the dielectric material 131, wherein the cap layer 135 is provided to provide enhanced mechanical strength.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced phase of the CMP process 102. As illustrated, during the removal of the excess copper material and also during the polishing of the cap layer 135, the mechanical stress of the polishing process 102 may result in the creation of micro cracks 135C, which may form in the surface that is in immediate contact with the polishing pad of the corresponding CMP tool. The size and the number of micro cracks 135C may significantly depend on process parameters, such as down force and relative speed, and may therefore require a corresponding adaptation of these CMP parameters, thereby resulting in an overall reduced removal rate. On the other hand, with respect to overall process throughput, a minimum removal rate may be required, thereby also producing a certain degree of defects in the form of the micro cracks 135C. It has been recognized, however, that, due to the provision of the cap layer 135, the micro cracks 135C may frequently be increased during the polishing process 102, thereby deepening the cracks 135C, which may thus extend into the dielectric material 131 (see FIG. 1c) and which may result in reduced reliability during the further processing after the removal of the cap layer 135. For instance, the micro cracks 135C may further propagate into the dielectric material 131 during further manufacturing processes, such as the formation of further metallization layers, which may finally result in an overall reduced mechanical stability, which in turn may result in significant yield losses in a very advanced manufacturing stage due to delamination of metallization layers and the like, or which may result in reduced reliability of the metallization system during operation of the device 100.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.
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USPTO Backgrounds