In an internal circuit of conventional semiconductor equipment, internal elements repeat high-speed switching in synchronization with a signal called a system clock. As a result, harmonic current passes through the internal circuit and flows to the outside, resulting in electromagnetic interference and so on (Japanese Patent Laid-Open No. 5-152908).
FIG. 10 shows such conventional semiconductor equipment.
A semiconductor chip 101 serving as semiconductor equipment comprises an oscillator circuit 2 to which an oscillator or a radiator is connected and an internal circuit 4 which operates in synchronization with a system clock S191 outputted from the oscillator circuit 2. FIG. 11 shows the system clock S191 and the current waveform of the internal circuit 4 of the semiconductor equipment shown in FIG. 10.
To be specific, circuit elements constituting the internal circuit 4 start signal changes simultaneously at the rising edge of the system clock S191 having been generated in the oscillator circuit 2. In a CMOS circuit constituting the internal circuit 4, through current and charge/discharge current required for a voltage change of a signal line are generated during the transition of a signal, and the current is consumed at the rising edge of the system clock. FIG. 12 shows the existing state of the generation of high-order harmonics. The first spectrum indicates the second-order harmonics of the system clock, and the subsequent spectrum indicates fourth-order harmonics.
Under present circumstances, in semiconductor equipment where internal elements repeat high-speed switching in synchronization of a system clock, high-order harmonics are generated and result in electromagnetic interference.
It is an object of the present invention to provide semiconductor equipment which hardly causes electromagnetic interference.
USPTO Backgrounds
USPTO Backgrounds