Improvements in chip fabrication process technologies enable fabrication of integrated circuits (or circuits) with millions of components. Design of these circuits is complex and time-consuming. Various tools have been developed to automate the circuit design process. The purpose of these tools is to generate a convergent circuit design, which is a circuit design that meets the specified design constraints (e.g., power, area, timing, functionality, etc.).
Typically, the circuit design process is initiated by creation of the functional description of the desired circuit in a high-level language. This functional description is translated or converted to a gate-level implementation using cells (e.g., standard cells) from a given process technology library. This translation process is referred to as synthesis. The gates from synthesis are then placed and routed with the intent to create a physical design layout that meets specified design constraints. Further, the physical design layout is utilized to fabricate the desired circuit.
Although generation of a convergent circuit design is the goal, the gate-level implementation may lead to a non-convergent circuit design despite much effort to generate the convergent circuit design. Typical corrective action by the design team focuses on changing the functional description and performing synthesis again to generate a new gate-level implementation. However, there is no guarantee that the change in the functional description will lead to the convergent circuit design. Multiple iterations of this corrective action are typically required, increasing costs and causing major delays.
Further exacerbating this problem is that the capacity of the circuit design automation tools is being overwhelmed by the growing complexity of and the growing number of components in desired circuits fabricated on semiconductor chips. This has lead to dividing the circuit design into logical blocks that the circuit design automation tools can handle and to budgeting the design constraints among the logical blocks. Each logical block is designed independently. When the logical blocks are brought back together as a circuit on a chip, design constraints met at the logical block level may no longer be met at the global or chip level.
Many prior art tools and approaches to synthesizing a gate-level implementation using statistical wireload models and then placing and routing the gate-level implementation in two separate steps is no longer adequate with the newer process technologies due to the inaccuracy of the wireload models used during synthesis. This is the reason for the non-convergence described above. More recent prior art tools and approaches attempt to solve this problem by performing some gate-level optimization during place and route. This approach is typically referred to as physical synthesis. However, the ability of physical synthesis to drastically alter the gate-level implementation is fairly limited because it manipulates detailed gates without knowledge of design functionality.
Another approach to achieving a convergent circuit design has focused on creating a prototype physical design implementation using a library of predefined and precharacterized blocks before synthesizing the gate-level implementation. This library is created without any design-specific information. The functional description of a design is mapped into these predefined and precharacterized blocks. A prototype physical design implementation is created using the predefined and precharacterized blocks to meet various design constraints. Since these predefined and precharacterized blocks did not use any design-specific information and their characteristics can vary greatly from the gates eventually synthesized to implement the design, the prototype physical design implementation often does not correlate well with the final physical design implementation and thus, may not lead to a convergent circuit design.
USPTO Backgrounds
USPTO Backgrounds