1. Field of the Invention
The present invention relates to a semiconductor device and a method for making the same, and more particularly, to a semiconductor device including a channel region having a strained silicon epitaxial layer, and a method for making the same.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology such as multiple gate Field effect transistor (multiple gate FET) technology has been developed to replace the planar MOS transistor. The three-dimensional structure of a multiple gate FET increases the overlapping area between the gate and the fin structure of the silicon substrate, and accordingly, the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect is therefore reduced. In addition, the channel region is longer under the same gate length, and thus the current between the source and the drain is increased.
To meet the design trends with respect to high integration, high performance, low power consumption, and the demand of products, fabricating a novel multiple gate FET to improve the reliability of semiconductor device performance is an important issue in the field.
USPTO Backgrounds
USPTO Backgrounds