Static electricity exists everywhere during manufacturing, packaging, testing and using an array substrate including thin film transistors, accumulated electrostatic charges are released within nanoseconds to microseconds in the current of several amperes or tens of amperes, the instantaneous power is up to hundreds of kilowatts, and the discharge energy can reach millijoule, so that the destruction strength on the thin film transistors is very large.
Therefore, an electrostatic protection design in the thin film transistor design directly relates to the stability of the function of a chip and is very important. With the development of the process, the feature size of a device has gradually become smaller, and the thickness of an insulation layer (located between a gate electrode and an active layer and is also called a gate oxide or a gate insulation layer) in the thin film transistor has reduced proportionally. The gate insulation layer is usually made from silicon dioxide, the dielectric strength of which is approximately 8×106 V/cm, thus the breakdown voltage of the gate insulation layer with a thickness of 10 nm is about 8 V. Although such breakdown voltage is more than twice of 3.3 V supply voltage, the peak voltage of static electricity caused by all kinds of factors can be far higher than 8V, so that the insulation layer may be broken down. Moreover, with the use of new processes, such as polysilicon metallization, diffusion region metallization, polysilicon and diffusion region metallization and the like, the parasitic resistance of the device is reduced, so that the protection capacity of preventing electrostatic discharge is greatly weakened. In order to adapt to the continuous improvement of the integration density and the working speed of a super-large-scale integrated circuit, the electrostatic protection for the thin film transistor needs to be improved.
As shown in FIG. 1, an array substrate includes a display area for displaying and a driving area located around the display area. In this case, thin film transistors located on a base substrate 1 are provided in both the display area and the driving area of the array substrate, each thin film transistor is provided with an insulation layer 3 between a gate electrode 2 and an active layer 5, an etching stop layer 4 is further arranged on the active layer 5, source/drain electrodes 6 are arranged on the etching stop layer 4, and the source/drain electrodes 6 are electrically connected with the active layer 5 through vias 7, respectively.
An electrostatic protection structure is arranged in the driving area of the array substrate to release the electrostatic charges, but when too many charges are accumulated, the electrostatic discharge current is quite large and cause electrostatic discharge at the vias 7 of the thin film transistor in the driving area, so that the gate electrode and the source/drain electrodes 6 may be short circuited due to the breakdown of the insulation layer 3. Therefore, increasing the thickness of the insulation layer 3 of the thin film transistor in the driving area becomes an important measure for preventing electrostatic discharge, but in the thin film transistor in the display area of the array substrate, adverse effects such as a reduced migration rate and threshold voltage drift will be caused due to the increased thickness of the insulation layer 3, so the thickness of the insulation layer 3 of the thin film transistor in the display area cannot be too large.
In the prior art, when the insulation layer 3 (including the insulation layers in the display area and the driving area) of the array substrate as shown in FIG. 1 is formed by a patterning process, a used mask is shown in FIG. 2, and the mask includes a display area mask 9 corresponding to the display area and four driving area masks 8 corresponding to the surrounding driving areas respectively. During exposure, the above-mentioned masks are spliced and exposure is carried out, and then development and etching are performed to simultaneously obtain patterns of the insulation layers in the display area and the driving areas.
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