This invention relates to comparator circuitry, and in particular, to comparator circuitry for sensing and storing signals representative of input signals.
It is known to sense and compare input signals using differential amplifiers and to produce amplified signals at the output of the differential amplifiers. It is also known to couple the amplified output to a latch or flip-flop circuit to store the amplified differential signals. By way of example, refer to FIG. 1 which shows a prior art circuit described in FIG. 13 of an article titled, "A 10 bit 15 MHZ CMOS Recycling Two-Step A/D Converter", authored by Bang-Sup Song et al. and published in the IEEE Journal of Solid State Circuits Vol. 25, No. Dec. 6, 1990. The prior art circuit of FIG. 1, includes an amplifier comprised of transistors M1, M2, M3, M4, and M11. The outputs of the amplifier are coupled via transistors M5 and M6 to a latching circuit comprised of transistors M7, M8, and M12 which is selectively reset to a neutral state by means of shunting circuitry comprised of transistors M9, M10 and M13. When signals to be compared are applied to the inputs of M1 and M2 (i.e., during a data acquisition phase), the amplified signals are translated via M5 and M6 into nodes Q and Q(not). Concurrently, M9 and M10, whose conduction paths are returned to ground via M13, shunt the latch keeping Q and Q(not) at a low level which also maintains the latch at a low gain level and in a non-regenerative state. When the data acquistion phase ends and the data storage (or latching) phase begins, M9 and M10 are turned-off while Q and Q(not) are still being precharged by the amplifier. As M9 and M10 are being turned-off, the latch is set to the condition reflective of the value of Q and Q(not).
A problem with the prior art circuit is that the latch will draw current in the steady state even when it has reached its fully latched condition because one of M5 and M6 will be trying to force current into a node that is held "low" by M7 or M8. Another problem with the prior art circuit is that, at the onset of the latching phase, the amount of regeneration and thus, its speed, is limited to that supplied by the "one sided latch" made up of M7 and M8. Furthermore, the circuit is susceptible to switching noise when the shunting transistors are turned off which may mask the signal being coupled into the latch.
The problems discussed above are either eliminated or significantly reduced in circuits embodying the invention.
USPTO Backgrounds
USPTO Backgrounds