Many integrated circuit architectures employ one or more buried regions or layers, typically located along an interface between an upper (epitaxially formed) semiconductor layer in which a variety of device regions are formed. For example, in the case of a junction isolation architecture, such as that diagrammatically illustrated in FIG. 1, an N type epitaxial layer 11 may be formed atop an underlying P type semiconductor substrate 13. Prior to formation of the epitaxial layer 11, respective N+ and P+ type (high impurity concentration) regions 15 and 17 are formed in spaced apart surface portions of the top surface 19 of the P type substrate 13. In such an architecture, the N+ buried region 15 is usually employed as a low resistance path to a bottom, N type terminal (not shown) of a vertical device, such as the collector of a vertical NPN bipolar transistor, or the drain of a vertical DMOSFET device. The P+ buried region 17 is customarily used to provide lateral isolation, by extending the substrate doping type up into the epitaxial layer 11. In some processes, the P+ buried region 17 may also provide the same buried region functionality as the N+ buried region 15, for example, serving as the collector of a vertical PNP bipolar transistor.
In processes that are intended to provide very low buried N+ region resistance over a large area, while also maintaining a high breakdown voltage, the use of an epitaxial process to form the topside layer 11 may constitute a severe restraint due to autodoping from the underlying N+ region 15 into the epitaxial layer 11, as the epitaxial layer is being formed. This undesirable autodoping phenomenon is illustrated in FIG. 2, which illustrates the impurity concentration profile of the resulting device along section line 18 in FIG. 1 of the dual buried region architecture of FIG. 1 resulting from autodoping. During the initial phase of the epitaxial process, N type impurities outdope from the N+ buried region 15 and are incorporated ubiquitously into the growing epitaxial layer 11. This intrusion of N type dopant can create a large, unwanted N-type doping contaminant throughout the bottom or substrate-interface portion of the epitaxial layer, so that the N-type autodoped material forms a junction with the P+ buried region 17. This junction will necessarily have the lowest breakdown voltage, and can limit the intended performance of the device.
One way to mitigate the effects of such autodoping is to provide a source of P type doping to compensate for the N type outdoping. Unfortunately, the large difference in diffusion coefficients between a typical P type dopant, such as boron, and an N type dopant, such as arsenic or antimony (preferred species for the formation of an N+ buried region), can mean that such a compensation approach is ineffective as an unmasked layer.
More particularly, if the P type dopant (boron) is able to successfully compensate the peak of the N type autodoping, it is likely to extend well beyond the autodoped N profile in the vertical direction, thereby producing an unwanted P type peak, both above and below the autodoping, as diagrammatically illustrated in FIG. 3. This P type peak will interact with the N+ buried region 15 in the same way that the N type autodoping does with the P+ buried region 17. It will be readily appreciated, therefore, that using unpatterned P type compensation does not solve the problem; it merely moves it from the P+ buried region 17 to the N+ buried region 15.
One solution would be to add a masking level and make the P type compensation material a P type buried region, with the mask placing the P type compensation only around the P+ buried region 17 and preventing it from reaching the N+ buried region 15. It goes without saying, however, that the addition of a masking level undesirably increases processing complexity and cost.
USPTO Backgrounds
USPTO Backgrounds