1. Field of the Invention
This invention relates to computer systems and more particularly to computer systems having system control adapters and still more particularly to computer systems having functional units constructed from LSI circuitry and organized so as to be responsive to signals from a system control adapter via a common RAS bus to go thru an operation.
2. Description of the Prior Art
Prior art arrangements for testing functional units within a computer system such as described in the IBM Technical Disclosure Bulletin Volume 12, No. 12, March 1970, page 1614 do not have direct addressing of the individual units to be tested and require simulation hardware. Some prior art arrangements such as in U.S. Pat. No. 3,806,878 dated Apr. 23, 1974, for Concurrent Subsystem Diagnostics and I/O Controller require use of a diagnostic instruction and do not have a separate RAS bus.
Other prior art such as in U.S. Pat. No. 3,825,901 dated July 23, 1974, for Integrated Diagnostic Tool does not have direct access to all triggers, registers and other elements of the computer system. Also, these prior art systems are unable to test the failing unit by means of a test pattern capable of testing the operation of individual logic elements. Rather, they use a functional test pattern and exercise the functional unit being tested, such as as ALU, to see if it operates in its intended manner. For example, a functional test pattern would be sent to the ALU to determine if it operates properly in the add mode, etc. There is no capability to test the operation of the individual logic elements irrespective of the operational mode of the unit being tested.
Additionally, these prior art systems are not capable of concurrent operation because they do not degate the failing functional unit and do not provide special system clocks to the failing functional unit. In the present invention each I/O type of functional unit can be degated from the remainder of the system. If the CPU is failing, it is not degated from the rest of the system. The degated functional unit can be separately addressed and furnished with system clocks for effecting one clock cycle, one shift cycle, one machine cycle or one instruction cycle, while the remainder of the system is operating with system clocks occurring in the normal system operation mode. Thus, the present invention is particularly suitable for computer systems operating with work stations. A failing work station can be tested while the remainder of the system continues to run in its normal mode. This is particularly advantageous over prior approaches where the entire system is dedicated to the test mode.
USPTO Backgrounds
USPTO Backgrounds