1. Field of the Invention
The present invention relates to semiconductor devices, particularly a semiconductor device including an internal voltage generation circuit.
2. Description of the Background Art
In a general DRAM (Dynamic Random Access Memory), an N channel MOS transistor is used as a transfer gate of a memory cell. A positive voltage is employed as the voltage for selection, applied to a word line, when a memory cell is rendered active. A negative voltage generation circuit generating a negative voltage lower than the ground voltage is incorporated in this DRAM. The negative voltage is used as a substrate bias voltage to control the substrate effect of a transistor.
In this context, variation in the level of the negative voltage is suppressed due to the large capacitance of the substrate. Further, high-speed response at the negative voltage generation circuit formed of a negative voltage detection circuit and a negative charge supply circuit is not required. Since high-speed response at the negative voltage generation circuit is not required even for a chip that incorporates a plurality of memories, only one negative voltage generation circuit having a performance level just required to charge the substrate when the external power supply is turned on is disposed at one site.
In a DRAM using a P channel MOS transistor as the transfer gate of a memory cell, a negative voltage is used as the voltage for selection, applied to a word line, when a memory cell is rendered active. In this type of DRAM, it is required to write a signal of ground level into a memory cell in a write operation mode, and output a signal voltage of sufficient amplitude from a memory cell in a readout operation mode. Therefore, the voltage to select a word line must be set sufficiently low.
In this context, high-speed response at the negative voltage generation circuit is required since the substrate capacitance is not large as in a conventional DRAM and the current consumption related to negative voltage is increased. Thus, there is a problem that variation in the negative voltage becomes great in a chip that has one negative voltage generation circuit incorporated for a plurality of memories.
A possible consideration is to increase the through current (standby current) flowing to the negative voltage detection circuit in the negative voltage generation circuit to allow higher speed in response. However, the standby current cannot be increased in the field of battery-driven portable equipment in which this type of DRAM is incorporated, since there is a demand for lower power consumption by reduction in operating voltage and consumed current.
This type of DRAM also poses the problem of increase in circuit failure caused by excessive stress applied to the transistor during a burn-in test mode.
Further, this type of DRAM poses the problem that the operation speed is reduced due to the reduction in power supply voltage and/or increase in ground voltage in a circuit operation mode.
In addition, this type of DRAM is easily affected by noise.
Moreover, there was a problem that a semiconductor integrated circuit device including a plurality of such DRAMs exhibited unstable circuit operation due to the reduction in power supply voltage and/or increase in ground voltage.
USPTO Backgrounds
USPTO Backgrounds