Patent Literature 1 (Japanese Patent Application Publication No. 2002-305305) describes an insulating gate bipolar transistor (IGBT). The IGBT in Patent Literature 1 includes a semiconductor substrate, an upper surface electrode disposed on an upper surface of the semiconductor substrate, and a lower surface electrode disposed on a lower surface of the semiconductor substrate. The IGBT in Patent Literature 1 also includes an n-type emitter region provided in a portion disposed at the upper surface of the semiconductor substrate, a p-type collector region provided in a portion disposed at the lower surface of the semiconductor substrate, an n-type drift region provided between the emitter region and the collector region, a p-type body region provided between the emitter region and the drift region, and a gate trench extending from the upper surface of the semiconductor substrate to a depth reaching the drift region through the emitter region and the body region. A gate electrode is disposed in the gate trench. The IGBT in Patent Literature 1 also includes an n-type buffer region provided between the drift region and the collector region, and a p-type low concentration region provided between the buffer region and the collector region. The buffer region has an impurity concentration higher than an impurity concentration of the drift region. The low concentration region has an impurity concentration lower than an impurity concentration of the collector region.
In the technology in Patent Literature 1, carriers are accumulated in the low concentration region when the IGBT is in an on-state. This mitigates a sharp current decrease at turn-off of the IGBT. The carriers, which have been accumulated in the low concentration region move to the collector region, thereby leading to a gentle current decrease. Moreover, the mitigation of the sharp current decrease suppresses an oscillation (a noise) of a voltage between the upper and lower surface electrodes.
USPTO Backgrounds
USPTO Backgrounds