1. Field of the Invention
The present invention relates to package on package (PoP) structures and fabrication methods thereof, and more particularly, to a PoP structure and a fabrication method thereof for improving the product yield.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. To improve electrical performances and save spaces, a plurality of packages can be vertically stacked on one another to form a package on package (PoP) structure. Such a packaging method allows merging of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic elements having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
FIG. 1 is a schematic cross-sectional view of a conventional PoP structure 1. Referring to FIG. 1, the PoP structure 1 has a first packaging substrate 11 and a second packaging substrate 12 stacked on the first packaging substrate 11. The first packaging substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. A first semiconductor element 10 is disposed on the first surface 11a of the first packaging substrate 11 and electrically connected to the first packaging substrate 11, and a plurality of solder balls 17 are formed on conductive pads 112 of the second surface 11b of the first packaging substrate 11. The second packaging substrate 12 has a third surface 12a with a plurality of conductive pads 120 and a fourth surface 12b opposite to the third surface 12a. Further, a solder mask layer 123 is formed on the third and fourth surfaces 12a, 12b and has a plurality of openings for exposing the conductive pads 120.
To fabricate the PoP structure, the first semiconductor element 10 is flip-chip electrically connected to the first packaging substrate 11, an underfill 16 is formed between the first semiconductor element 10 and the first packaging substrate 11, and a plurality of solder posts 13 are formed on the first surface 11a of the first packaging substrate 11. Then, the second packaging substrate 12 is stacked on the solder posts 13 via the fourth surface 12b thereof and electrically connected to the first packaging substrate 11 through the solder posts 13. Thereafter, an encapsulant 14 is formed between the first surface 11a of the first packaging substrate 11 and the fourth surface 12b of the second package substrate 12 for encapsulating the first semiconductor element 10. Subsequently, a plurality of second semiconductor elements 15 are disposed on the third surface 12a of the packaging substrate 12 and electrically connected to the conductive pads 120, and an underfill 16 is formed between the second semiconductor element 15 and the second packaging substrate 12.
In the PoP structure 1, the solder posts 13 are used for mechanical support and electrical connection between the first packaging substrate 11 and the second packaging substrate 12. However, as I/O counts of electronic products increase, if the package size does not change, the pitch between the solder posts 13 must be reduced. As such, solder bridging easily occurs between the solder posts 13, thus reducing the product yield and reliability.
Therefore, how to overcome the above-described drawbacks has become critical.
USPTO Backgrounds
USPTO Backgrounds