1. Field of the Invention
This invention relates to a microinstruction processing unit for use in a data processing system.
2. Description of the Prior Art
Generally, in a microprogram-controlled data processing system, a microinstruction which has requested an interruption in response to an interrupt request (an interrupting microinstruction) is processed when said interrupting microinstruction is ranked higher in the priority order than the currently executed microinstruction (the present microinstruction). To enable the processing of the interrupted microprogram to be resumed after completion of the interruption processing, information needed for the resumption of said interrupted processing (including arithmetic data and results) is stored in a sheltering register at the time of interruption.
Stated in greater detail, resumption after interrupt has been achieved in the prior art using an arithmetic register which stores arithmetic data, an arithmetic circuit which operates on the data from the arithmetic register and a microinstruction processing unit (MP unit) provided with a sheltering register into which the contents of said arithmetic register can be transferred and sheltered. This MP unit is installed in the central processor unit (CPU) and performs the transfer of the contents of the arithmetic register to the sheltering register when interruption occurs.
Because the foregoing interruption processing procedure requires a considerable number of microinstruction process steps, however, some prior art systems have used an MP unit that employs a register file instead of a sheltering register. This register file functions as a storage device having a plurality of storage positions whose respective addresses correspond to the priority levels assigned to various microprograms. More specifically, the MP unit in such prior systems comprises a priority order-indicating (PO) register for storing data to assign the priority order of consecutive processing in response to a series of microinstructions; a register file for storing information (including arithmetic data and results) to be used for subsequent reprocessing of the interrupted microprogram in the assigned address based on the contents of the PO register; and an arithmetic circuit for processing information given from the register file. In an MP unit of this type, however, when the interrupting microinstruction issued in response to an interrupt request has a higher priority level than the present microinstruction, information needed to operate the contents of the PO register, depending on the priority order of the interrupting microinstruction, must be taken out of the register file. This is very time-consuming.
Moreover, it is frequently necessary to check the processing results of the interrupted microprogram obtained immediately before the interruption. However, all that can be read out of the register files of such MP unit systems is address information for reprocessing corresponding to the priority order of the present microinstruction. Consequently, in order to achieve the required error checking, the contents of the PO register must be rewritten and the addresses of the register file must be converted into addresses useful for taking error checking information out of the register file. This results in a substantial increase in the number of microinstruction steps. An MP unit of this type is described by International Business Machine Corporation in "A Guide to the IBM System/7", 1970, pp. 24-25.
It is therefore an object of the present invention to provide a microinstruction processing unit responsive to interruption priority order which is free from the above-described and other disadvantages of conventional units.
USPTO Backgrounds
USPTO Backgrounds