The present invention relates to techniques for manufacturing semiconductor devices, and relates to a technique effectively applied to the technique for manufacturing resin-sealed semiconductor devices, for example.
Japanese Patent Laid-Open No. 2001-257291 describes a technique, in which a brazing material, such as solder, is used for coupling between one conductive path and one circuit element, while a conductive paste, such as an Ag paste, is used for coupling between the other conductive path and the other circuit element.
In Japanese Patent Laid-Open No. 2010-114454, one semiconductor chip is mounted over a wiring substrate, and the wiring substrate and one semiconductor chip are coupled to each other using a first solder. This first solder is formed by a high melting point solder (e.g., a Pb(lead)-Sn(tin) solder containing Pb(lead)) that is in a liquid state at temperatures equal to or greater than 280° C., for example. Furthermore, the other semiconductor chip is also mounted over the wiring substrate, and the wiring substrate and the other semiconductor chip are coupled to each other using a second solder. This second solder is formed, for example, by a Pb free solder (e.g., a Sn (tin)-silver (Ag)-copper (Cu) solder) which does not contain Pb(lead) that is in a liquid state at temperatures equal to or greater than 200° C.
Japanese Patent Laid-Open No. 2008-53748 describes a technique, in which a control power MOSFET chip and a synchronous power MOSFET chip are provided. Then, drain terminals on the respective rear surfaces of the control power MOSFET chip and the synchronous power MOSFET chip are bonded to an input side plate-like lead portion and an output side plate-like lead portion, respectively, via a die bonding material, such as a silver paste, for example.
USPTO Backgrounds
USPTO Backgrounds