The concept of microbranching, that is, branching within the microcode level of microinstructions in a central processing unit of data processing systems is well known in the art. It is known to perform microbranching upon selected results of selected test conditions in the central processing units of data processing systems. Within data processing systems which employ pipelined architectures, it is known to perform microbranching as the result of tests which are performed during the execution of different ranks of the microcode field for a single microinstruction. Some prior art systems have the capability to only do "fast" branches, that is, to branch on the result of test conditions which are sensed during the execution of the rank one microcode bit field in any given microinstruction. Other systems have had the capability to branch only in a "slow" manner, that is, upon the results of test conditions which occur during execution of the second rank of microcode for any given microinstruction. Some of the systems known in the prior art which are capable of performing microbranching have the capability to inhibit lines of microcode which enter the pipeline after the line which causes the branch to occur. The necessity to inhibit the execution of such later lines of microcode is dependent on the function that the microcode performs and whether it is compatible with the branch which is taken by the CPU under the direction of the microcode as the result of the test conditions.
While these prior art microbranching architecture schemes have provided flexibility to system designers and have made possible the design of systems which are capable of making more decisions and thus functioning on higher levels of abstraction, there is still room for improvement in the design and execution of such system hardware.
For example, systems which are not capable of performing both fast and slow branches are not as flexible as systems which are so designed. Such systems do not generally have the capability of performing more than one test at any one particular time or even the capability of performing more than one test during the execution of any one microinstruction. Some such systems have the capability of only performing fast microbranches and some systems only perform slow microbranches. The systems which are capable of only performing fast microbranches cannot branch on conditions generated by the rank two execution of the current microinstruction. The obvious reason for this shortcoming is that the condition which invokes the decision to branch occurs during a later period in time than is capable of being sensed by the branching hardware.
On the other hand, systems which only perform slow branches must always wait an extra clock cycle for the conditions which invoke the branch to occur under the direction of rank two microcode and thus lose a clock cycle before execution of microcode at the branch target can begin.
Another drawback of the prior art systems which are capable of performing slow microcode branching is that they lack the flexibility to selectively inhibit either one or both extra lines of microcode which enter the pipeline before the branch decision is made. Likewise, prior art systems which are capable of performing fast microbranching typically lack the flexibility to selectively inhibit either one or both of the current or next lines which enter the pipeline before the branch decision can be made.
Furthermore, prior art systems which allow extra lines to execute after the decision to microbranch as the result of a test condition has been made generally do not have the capability of calling a subroutine and then returning to a line of microcode other than the line of microcode following the line of microcode which invoked the branch.
Another drawback of currently-employed microbranching hardware is that the hardware employed by the prior art for performing both fast and slow microbranching cannot be checked against one another without the need to employ additional checking hardware.
Finally, a return address stack is commonly employed by systems which perform any type of microbranching. This return address stack is used as a vector by the system to point to an address to which the processor should return to resume executing the microcode it was executing prior to the branch being taken. Prior art return address architectures known to the inventors of the present invention share the common architectural feature that the loading of the return address is coupled to the rotation of the stack. This tends to reduce flexibility or increase the hardware cost of prior CPU's.
Therefore, it is an object of the present invention to provide an architecture for use in central processing units for performing microbranching which is capable of performing both fast and slow microbranching.
It is a further object of the present invention to provide a microbranching architecture which is capable of performing more than one test during the execution of any single microinstruction.
It is a further object of the present invention to provide a microbranching architecture which is capable of inhibiting either or both of the extra lines which enter the pipeline during a slow microcode branch.
It is yet another object of the present invention to provide a microbranching architecture which is capable of inhibiting either or both of the current and the following line which enter the pipeline during a fast microbranch.
Yet another object of the present invention is to provide a microbranching architecture which allows extra lines in the pipeline to be executed and has the capability of calling a subroutine and then executing any line in the control store upon returning from the subroutine.
A further object of the present invention is to provide for a microbranching architecture capable of performing both fast and slow microcode jumps and having the further capability of allowing the operations of both the fast and slow microcode jumping hardware to be checked against one another.
It is also an object of the present invention to provide a return address stack for use in performing microbranching in which the return address loading is decoupled from the rotating of the stack.
These and other objects of the present invention will become apparent to those of ordinary skill in the art from an examination of the specification, accompanying drawings, and appended claims.
USPTO Backgrounds
USPTO Backgrounds