1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, which forms a resist pattern corresponding to a gate electrode on a semiconductor device in such a way that only a fine resist pattern is formed on a resist member by an electron beam lithography and other resist patterns are formed on the same resist member by an optical lithography.
2. Description of the Related Art
Recent high integration and high speed of an LSI are accomplished by the miniaturization of device elements.
Conventionally, at the time of forming an nMOSFET as a device element, for example, a resist pattern is formed by patterning a resist member, thereby forming one gate electrode layer 10 as shown in FIG. 1. This gate electrode layer 10 comprises an n type polycrystalline silicon (polysilicon) layer 10a, which becomes a gate electrode of the operational area of the MOSFET, and an n type polysilicon layer 10b, which is a contact portion to other interconnections and where a contact hole 11 is formed. The gate electrode layer 10 has different sizes at the individual portions.
In forming the resist pattern, lithographies are selected in accordance with the sizes of the individual portions. An electron beam lithography may be used for the n type polysilicon layer 10a which is a fine portion, while using an optical lithography for the n type polysilicon layer 10b.
According to the optical lithography technique, normally, a mask for pattern transfer is prepared and is transferred on a resist by a reduced exposure projection scheme, thus forming a desired pattern. The pattern transfer can be accomplished in a short period of time; the transfer time is normally about several hundreds of milliseconds.
The resolution of the optical lithography is limited by the wavelength of light used in the lithography, and this resolution limit is improved by shortening the wavelength of the light in use. Even the lithography technique using a KrF (excimer) laser, which is presently prior art, can form a pattern of as small as about 0.3 .mu.m.
As the electron beam lithography directly forms a resist pattern using an electron beam, a fine pattern of about 0.1 .mu.m can be formed.
The electron beam lithography directly forms every pattern in an LSI with an electron beam. For an LSI which has several tens of millions of transistors and has a gate length of about 0.1 .mu.m, therefore, processing a single wafer takes several hours and the increased processing considerably increases the LSI manufacturing cost.
It is apparent from the above that the optical lithography and the electron beam lithography have merits and demerits. A positive resist member suitable for the wavelength of the light is used in the optical lithography, while a negative resist member is used in the electron beam lithography.
At the time of forming an nMOSFET as a device element, for example, even if there are a fine gate length portion and another gate length portion involved in forming one gate electrode after forming a resist pattern by patterning a resist member, it is troublesome to provide different resist members suitable for the different gate length portions. When a plurality of device elements are provided side by side, in particular, the fabrication becomes complicated. Conventionally, therefore, the optical lithography and the electron beam lithography were not selectively used for one device element using the same resist member in accordance with the different gate lengths of the gate electrode.
If the electron beam lithography is used entirely for the gate electrode, while this lithography technique is suitable for forming a fine gate length portion, it is not suitable for another gate length portion because the processing inevitably takes time and increases the LSI fabrication cost. If the optical lithography is used entirely for the gate electrode, this lithography technique is not suitable for forming a fine gate length portion from the viewpoint of the limited resolution.
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