Amorphous silicon (a-Si:H) thin film transistors (TFTs) are critical devices for high performance liquid crystal display (LCD) products. TFTs can also be applied to other two-dimensional imagers, sensors, and electronic equipment. Therefore, TFT development is a fundamental technology for present and future electronics. Currently, a serious problem for the production of a-Si:H TFTs is low yield due to shorts between conducting layers, specifically between the gate metal and the source/drain metals, as detailed below with reference to FIG. 1. Due to the requirement that each layer be as thin as possible, poor step coverage of dielectric layers over the metal steps can cause discontinuities of the metal layers or shorts between top and bottom metals. This results in unworkable products.
A common profile for a-Si:H TFTs is the inverted, staggered structure illustrated in FIG. 1. A metal gate 11 is formed on a substrate 10 which is a glass or silicon wafer, and coated with a thin layer of gate dielectric 12. Over the gate dielectric, an active amorphous silicon layer 16 and a dielectric layer 15 are deposited, followed by patterning the dielectric layer 15, and depositing and patterning source and drain metal, 13 and 14. A thin n+ layer (not shown in this figure) is usually deposited before deposition of the source and drain metal. Variations on the illustrated TFT include multichannel TFTs, of the type described in the article entitled "Single-gate multichannel amorphous silicon thin-film transistors," authored by the present inventor, Applied Physics Letters, Vol. 67, No. 21, pages 3174-3176, (November 1995), and split-gate TFTs, of the type described in "Horizontally Redundant, Split-Gate a-Si:H Thin Film Transistors," authored by the present inventor, Journal of the Electrochemical Society, Vol. 143, No. 8, pages 2680-2682, (August 1996). All of the known TFTs are prone to experiencing metal-to-metal shorts occurring between the gate and the source and/or drain regions, because the gate dielectric step coverage to the metal line is poor, or because the gate dielectric film at the bottom corner of the gate line is easily attacked by etchants during subsequent processing.
Prior art solutions which have been proposed to overcome the problems associated with shorts between the metal of the transistor gate and source/drain regions include providing redundant gate dielectric layers to improve gate metal coverage. In providing redundant gate dielectric layers, it is common to utilize two different gate dielectric materials, thereby decreasing the likelihood of duplicating or propagating any pinholes or weak areas in the first-deposited layer. Combinations of gate dielectric layers which have been taught in the literature include SiN.sub.x /SiO.sub.2, SiN.sub.x /Ta.sub.2 O.sub.5, and SiN.sub.x /Al.sub.2 O.sub.3. In each instance, the SiN.sub.x layer is preferably deposited adjacent to the a-Si:H layer, due to the low interface density of states encountered between the two materials. If SiO.sub.2 is used, the gate dielectric is necessarily blanket-deposited on the substrate and gate structure. As a result, the gate dielectric is not self-aligned to the gate metal. For LCD applications, if the ITO is deposited before the preparation of the TFT, the SiO.sub.2 layer must be etched off with the gate SiN.sub.x layer to make contact vias, which adds an extra processing step. An additional disadvantage to usage of SiO.sub.2 is that it is etchable by the hydrofluoric acid solution which is required to etch the subsequently-deposited SiN.sub.x. What occurs, therefore, is unintended etching of the redundant layer leaving discontinuities in the SiO.sub.2 layer which may result in the metal-to-metal shorts that the layer was supposed to prevent.
Both of the known redundant metal oxide gate dielectric materials, Ta.sub.2 O.sub.5 and A1.sub.2 O.sub.3, are deposited in a manner to provide a self-aligned gate dielectric immediately adjacent the gate metal. In addition, each of the alternative materials exhibits greater etch resistance to hydrofluoric acid than does SiO.sub.2. However, anodization is required to grow the self-aligned metal oxides on the gates. Anodization is carried out in aqueous solutions, thereby introducing a significant source of contaminants such as sodium and potassium which can become trapped in the porous metal oxide film. In addition, the metal oxide layers are difficult to etch with either a wet or a dry process, and etching of the metal oxide layers is necessary in the via areas for connecting the driving integrated circuits to the gate and to the data lines.
It is also to be noted that Ta.sub.2 O.sub.5 requires that the gate metal includes tantalum which has a high resistivity and is therefore generally considered unsuitable for use as a gate material for large area applications. Similarly, Al.sub.2 O.sub.3 requires that the gate metal include aluminum. While an aluminum or aluminum alloy gate would have favorable electrical properties, it is not preferred due to the aforementioned shortcomings of porosity and ready contamination.
It is therefore an objective of the present invention to provide a thin film transistor structure having a self-aligned dielectric layer which has minimal contaminations and provides non-porous gate coverage.
It is additionally an objective of the present invention to provide a gate dielectric which is easily deposited and etched with minimal impact on the adjacent materials.
USPTO Backgrounds
USPTO Backgrounds