A prior art high frequency signal receiving apparatus is described in the following with reference to drawing. A prior art high frequency signal receiving apparatus shown in FIG. 4 comprises an input terminal 1 for receiving digital modulated high frequency signal, a high frequency amplifier 2 coupled to the input terminal 1 a mixer 4 one input of which being coupled to output of the high frequency amplifier 2 while other input being coupled to output of a local oscillator 3, an I/Q detector 6 one input of which being coupled to output of the mixer 4 while other input being coupled to output of a local oscillator 5, an A/D converter 7 coupled to output of the I/Q detector 6, a demodulator 8a which being part of a digital signal demodulating section 8 and coupled to output of the A/D converter 7, a frequency error detector 8b provided within the demodulating section 8, a D/A converter 8d provided between the frequency error detector 8b and said local oscillator 5, a digital signal decoding section 9 coupled to output of said demodulator 8, an output terminal 10 coupled to output of the decoding section 9, a PLL circuit 11 coupled to said local oscillator 3, a PLL circuit control terminal 12 coupled to control input of the PLL (phase locked loop) circuit 11, a demodulating section control terminal 13 coupled to an interface circuit 8e which circuit being control input of said demodulating section 8, and a decoding section control terminal 14 coupled to control input of said decoding section 9.
The operation of the above high frequency signal receiving apparatus is described in the following. A digital modulated high frequency signal inputted to input terminal 1 is amplified at high frequency amplifier 2, mixed at the mixer 4 with an output frequency from the local oscillator 3, and a desired high frequency signal is tuned. This is converted at A/D converter 7 into digital value after quadrature detection by I/Q detector 6, and delivered to demodulator 8a. In the demodulator 8a, digital signal is demodulated. An oscillation frequency of around 479.5 MHz for the I/Q detection is obtained at local oscillator 5 by inputting the output of frequency error detector 8b to the local oscillator 5 after D/A conversion at D/A converter 8d. Thus the demodulating section 8 reduces the frequency error by the feedback, also reproduces clock in a clock recovery circuit 8c. The digital demodulation is performed accurately using the reproduced clock. Output of the demodulator 8a is delivered to output terminal 10 after undergoing error correction, etc. at decoding section 9.
In the above described conventional structure, however, the PLL circuit control terminal 12, demodulating section control terminal 13 and decoding section control terminal 14 are connected respectively direct to outside or external equipments. For example, the PLL circuit control terminal 12 of PLL circuit 11 receives signal for tuning clock signal, data signal, enable signal, etc. direct from outside equipment. The PLL circuit 11 need to be provided with a one which is different depending on destination market. Demodulating section 8 needs to be provided with roll-off factor, data for specifying difference of tuner specification, frequency dividing rate, transmission rate, etc. through the demodulating section control terminal 13 in a format specific to the demodulating section 8. Decoding section 9 needs to be provided with specific information for error correction represented by, for example, Reed-Solomon, Viterbi decode, etc. through decoding section control terminal 14.
As described above, the prior art constitution requires specific control for each of the terminals, such a control in an outside equipment is quite complicated, which may lead to a delayed processing in the main function of the outside equipment, posing a heavy burden on the outside equipment.
USPTO Backgrounds
USPTO Backgrounds