1. Field of the Invention
The present invention relates generally to a serializer/de-serializer (SerDes) and, more particularly, to a dual purpose SerDes for point-to-point and point-to-multipoint communication.
2. Introduction
A SerDes is an integrated circuit (IC or chip) transceiver that converts parallel data to serial data and vice-versa. The transmitter section has parallel data lines coming in and a serial output data stream. The transmitter section can also have a phase-locked loop (PLL) that multiplies the incoming parallel clock up to the serial frequency. For example, a SerDes in a gigabit Ethernet system would include 10 parallel data lines that can be clocked at 125 Mhz, with the resulting serial output clocked at 1.25 Ghz. The gigabit Ethernet SerDes would commonly use an 8B/10B coding scheme that maps 8-bit symbols to 10-bit symbols to achieve DC-balance on the line. As would be appreciated, the receiver section is the reverse of the transmitter section and would have a serial data stream coming in with parallel data lines coming out.
FIG. 1A illustrates the implementation of a SerDes component within a gigabit Ethernet physical layer device (PHY). As illustrated, the gigabit Ethernet PHY includes a physical coding sublayer (PCS), a physical medium attachment (PMA), and physical media dependent (PMD). The PCS is generally responsible for encoding/decoding gigabit media independent interface (GMII) octets to/from ten-bit code-groups (8B/10B) for communication with the underlying PMA. Similarly, FIG. 1B illustrates the implementation of a SerDes component within a 10 G PHY. As illustrated, the 10 G Ethernet PHY's PCS is generally responsible for encoding/decoding 10 gigabit media independent interface (XGMII) 64-bit data to/from 66-bit code-groups (64B/66B) for communication with the underlying PMA.
In general, the PMA abstracts the PCS from the physical medium. Accordingly, the PCS can be unaware of whether the medium is copper or fiber. The primary functions of the PMA include mapping of transmit and receive code-groups between the PCS and PMA, serialization/de-serialization of code-groups for transmission/reception on the underlying serial PMD, recovery of clock from the coded data (e.g., 8B/10B, 64B/66B, etc.) supplied by the PMD, and mapping of transmit and receive bits between the PMA and PMD.
The PMD is generally responsible for generating electrical or optical signals depending on the nature of the physical medium connected. PMD signals are sent to the medium dependent interface (MDI), which is the actual medium connected, including connectors, for the various media supported.
As noted above, the PMA is responsible for the recovery of the received clock, which is used by the PCS to sample the data presented to it by the PMA. Conventional clock recovery mechanisms use delay locked loops (DLLs) or phase locked loops (PLLs) that align a local clock's phase to the phase of the recovered clock.
For point-to-point systems, the locking to an incoming embedded clock is a one-time event prior to the communication of data across the link. For this reason, the process of locking to an incoming embedded clock need not be bounded by a particular locking time requirement. As would be appreciated, the relaxed timing requirement for locking to an incoming embedded clock can relax the design requirements of the SerDes.
In a point-to-multipoint system such as an Ethernet passive optical network (EPON), a single optical line terminal (OLT) at a head end can be designed to communicate with a plurality of optical network units (ONTs) at various end nodes. This arrangement leverages a shared fiber optic plant by multiple networking nodes. Typically, the OLT broadcasts its transmissions in the downstream direction to all the ONTs. Each of the ONTs, on the other hand, transmit in the upstream direction to the OLT. It should be noted that the OLT and ONTs need not transmit at the same signaling rate or bandwidth. It should also be noted that the ONTs can be designed to share bandwidth or use a different wavelength in the upstream direction to eliminate overlap.
In receiving a plurality of individual communications from the various connected ONTs, the SerDes in the OLT is required to acquire phase and frequency for each of the individual ONT communications. The locking to an incoming embedded clock is therefore not a one-time event. With a stricter timing requirement to achieve a lock, the SerDes in the OLT faces tighter design constraints.
In the SerDes market, point-to-point and point-to-multipoint solutions will continue to exist as the markets expand. What is needed therefore is a SerDes design that can leverage increased volumes while meeting the needs of various point-to-point and point-to-multipoint applications.
USPTO Backgrounds
USPTO Backgrounds