In the semiconductor-processing industry there is an increasing need for integrated circuits to be arranged three-dimensionally, that is to say stacked one above another within a chip arrangement. This need results, on the one hand, from the general desire to increase the packing density of electronic components and functions. In addition, there are also situations in which semiconductor chips interact functionally, for example, when a first semiconductor chip is driven by a second semiconductor chip, and, to shorten the signal paths between the connection contacts of the two semiconductor chips, it is beneficial to arrange the two semiconductor chips one above another.
In producing arrangements of stacked semiconductor chips, it is possible to use connecting wires for connecting the chips to the other circuitry. One disadvantage of this production method, however, is that welding or soldering the connecting wires requires precision work and, thus, results in a comparatively high expense. A further possibility for producing chip arrangements of stacked semiconductor chips uses flip-chip technology. Besides the relatively complicated process of forming contacts, which is usually effected by means of a ball grid array (BGA), a further disadvantage of the flip-chip method is that it is not readily possible to stack a plurality of chips one above another.
Consequently, there is a need to reduce the complexity and cost in the production of chip arrangements of stacked chips and at the same time also to provide a possibility of enabling larger numbers of semiconductor chips to be stacked one above another.
USPTO Backgrounds
USPTO Backgrounds