1. Field of the Invention
The present invention relates to a digital data code conversion circuit for a variable-word-length data code. More particularly, the present invention relates to a digital data code conversion circuit for a variable-word-length data code wherein a preparation circuit is provided for dividing a parallel input variable-word-length data code into data codes having word lengths less than or equal to a predetermined length.
2. Description of the Prior Art
Generally, in digital data transmission, two types of data coding systems are used. One type is a variable-word-length data coding system wherein the number of bits contained in one word is varied in accordance with the content of the data. The other type is a fixed-word-length data coding system wherein the number of bits contained in one word is always constant. The variable-word-length data coding system has the advantage that the total number of bits required for the same amount of information is smaller than the fixed-word-length data coding system. Accordingly, the variable-word-length data coding system is widely used in the transmission of a video signal, a voice signal, etc. However, in the variable-word-length data coding system, the number of bits contained in one word can be different for each word. It is inconvenient processing data words having different word lengths without any conversion, and the circuit construction for processing the data words can become complicated. The disadvantage of the variable-word-length data coding system can be eliminated by dividing and combining a series of data codes having different lengths to convert them into a series of parallel data codes having fixed lengths. To accomplish this, a conversion circuit for converting a variable-word-length data code into a fixed-word-length data code is required.
A prior art digital data code conversion circuit for a variable-word-length data code is disclosed in Japanese Patent Application No. 55-017,259. In this digital data code conversion circuit, code pattern information for a variable-word-length data code having a word length of up to n bits is input in parallel through data input terminals, and word-length information representing the number of bits of the input variable-word-length data code is input through word-length input terminals. The input variable-word-length data code is converted in the conversion circuit, and a fixed-word-length data code with n-bits is output.
In the above-mentioned digital data code conversion circuit, since the word lengths of data codes processed by the conversion circuit are required to be less than or equal to n-bits, it is necessary to make the bit number n processed in parallel larger if the maximum bit number of the input variable-word-length data code becomes larger. This means that the circuit structure becomes more complicated and the scale of the device becomes larger.
USPTO Backgrounds
USPTO Backgrounds