A conventional semiconductor memory device comprises a plurality of output circuits which supply read data to an external circuit in accordance with a chip selecting signal, an address change detecting signal and an output controlling signal, an output controlling circuit which controls output operations of the output circuits by supplying the output controlling signal to the output circuits, and an address change detecting circuit which detects an address change to supply information of the address change to the output controlling circuit and the output circuits.
In operation, the semiconductor memory device is selected to operate, when the low-active chip selecting signal turns to a low level. When the address change is detected in this state, the address change detecting circuit supplies an address change detecting signal to the output controlling circuit, which in turn supplies an output controlling signal to the output circuits. Thus, discharge of the output terminals is carried out in the output circuits, simultaneously. After that, the read data are supplied through the the output circuits to the external circuit.
However, the conventional apparatus for controlling outputs of read data in a semiconductor memory device has a disadvantage in that noise may be produced when a large amount of current flows in the simultaneous discharge of the output circuits, if many of the output terminals thereof are in a high level state.
USPTO Backgrounds
USPTO Backgrounds