The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a transistor containing a gate structure located atop a carbon nanostructure and positioned between metal semiconductor alloy portions and a method of forming the same.
The integration of carbon nanostructures as channel materials in the next generation of electronic devices offers many advantages over the continued scaling of silicon (Si). Carbon nanotubes and graphene are two nanoscale forms of carbon that exhibit extremely high current carrying capacity and mobilities which are several orders of magnitude beyond the theoretical limit for silicon. Additionally, carbon nanotubes (one-dimensional carbon nanostructures) and graphene (two-dimensional carbon nanostructure) are low-dimensional (ultra thin-body) materials, allowing them to be aggressively scaled in field-effect transistors without incurring deleterious short-channel effects that hinder modern scaled devices.
One of the foremost challenges to scaling carbon nanostructures such as, for example, carbon nanotubes and graphene, is the difficulty of establishing thin, uniform and high-quality dielectrics on their surfaces. The surface of both materials consists of strong sp2 carbon bonds with nominally no surface states. The absence of open surface bonds makes it nearly impossible to nucleate or deposit insulators, especially with the monolayer accuracy that is needed for scaled gate dielectrics.
Additionally, it is desirable to have a self-aligned carbon nanostructure contact process for lowering parasitic resistance. Unfortunately, at the time of filing this application, there is no such process that is presently available.
USPTO Backgrounds
USPTO Backgrounds