1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM) cell.
2. Description of Related Art
Dynamic random access memory (DRAM) is a type of volatile memory. Although reading from and writing to a DRAM cell is quite complicated and the design of peripheral circuits is quite intricate, each DRAM cell consists only of a transistor and capacitor. Hence, an array of the device can be put together on a silicon chip to produce a highly integrated memory circuit at a low cost. Nowadays, DRAM is one of the most widely adopted memory components.
A capacitor is a critical device in the storage of data in each DRAM cell. A DRAM capacitor capable of storing a larger number of electric charges is less vulnerable to noise corruption when stored data within the DRAM is read out. There are a number of means to increase the storage capacity of a capacitor. For example, the effective surface area of a capacitor can be increased to provide more space for accumulating electric charges. However, as the level of integration continues to increase, new methods and structures must be sought to obtain a relatively constant capacitance.
FIGS. 1A through 1E are schematic cross-sectional views showing the progression of steps for manufacturing a conventional DRAM cell.
As shown in FIG. 1A, a substrate 100 having a transistor therein is provided. A first dielectric layer 101 is formed over the substrate 100 and then a bit line 103 is formed over the first dielectric layer 101. A second dielectric layer 102 is formed over the bit line 103 and the first dielectric layer 101. Using photolithographic technique, a patterned first photoresist layer 104 is formed over the second dielectric layer 102.
As shown in FIG. 1B, a node contact opening 106 is formed in the second dielectric layer 102 using the first photoresist layer 104 as an etching mask. The first photoresist layer 104 is removed. Polysilicon material is deposited into the node contact opening 106 to form a polysilicon layer 108. A silicon nitride layer 110 is formed over the second dielectric layer 102 and then a third dielectric layer 112 is formed over the silicon nitride layer 110. A second patterned photoresist layer 114 is formed over the third dielectric layer 112.
As shown in FIG. 1C, the second dielectric layer 112 and the silicon nitride layer 110 are sequentially etched using the second patterned photoresist layer 114 as a mask to form an opening 116. The second photoresist layer 114 is removed. Polysilicon material is deposited into the opening 116 and over the second dielectric layer 112 to form a polysilicon layer 118. A silicon oxide layer 120 that fills the opening 116 is formed over the polysilicon layer 118.
As shown in FIG. 1D, the silicon oxide layer 120 is etched back until the polysilicon layer 118 is exposed. The polysilicon layer 118 is etched until the third dielectric layer 112 is exposed.
As shown in FIG. 1E, the third dielectric layer 112 and the silicon oxide layer 120 are removed using the silicon nitride layer 110 as an etching stop layer. Ultimately, the polysilicon layer 108 at the bottom section of the opening 116 is exposed to serve as the lower electrode of a capacitor.
In a conventional method, the process of forming the node contact and the lower electrode opening requires two masking steps. The additional process not only increases production cost, the chance of contaminating the silicon chip increases as well. Moreover, the process of forming the node contact opening requires proper alignment. Any misalignment may lead to circuit connection errors.
USPTO Backgrounds
USPTO Backgrounds