As is known in the art, recent advances in monolithic heterogeneous integration of compound semiconductor (CS) devices (including Group III-V devices composed of InP, GaAs, GaN, or AlN containing materials)with elemental semiconductor devices, such as Si based CMOS, have enabled compound semiconductor devices to be grown in etched windows on modified silicon on insulator (SOI) substrates and fabricated within a few microns of neighboring CMOS devices. Ideally, the resulting CS devices are co-planar or nearly co-planar with the CMOS in order to enable the use of standard back-end CMOS processing techniques to complete process integration. In this approach, compound semiconductor devices are grown on modified Silicon-On-Insulator (SOI) variants with compound semiconductor growth supports that are one of the following:                the SOI handle substrate (which may be Si, SiC, Sapphire or other elemental or compound semiconductor)        a template layer that has been grown directly on the SOI handle substrate        a template layer that was layer transferred to the handle substrate        a template layer that has been layered transferred and ends up sandwiched (i.e., buried) between two oxide layers in the SOI.        
Generalized outlines of two of these modified SOI variants are shown in FIGS. 1A-1F and 2A-2F, for gallium nitride (GaN) and gallium arsenide (GaAs) or gallium nitride (GaN), respectively, integrated with CMOS. In FIGS. 1A-1F, the GaN/CMOS integration is accomplished by growing the GaN device in a window directly on the window exposed portion of the handle wafer, e.g., Si, SiC, or Sapphire. On the other hand, for the GaAs (or InP)/CMOS integration of FIGS. 2A-2F, the GaAs devices are grown on a window exposed portion of the template layer that is otherwise buried between two oxide layers in the SOI structure. It should be noted that the buried template layer could be any compound or elemental semiconductor such as Si, Ge, InP, GaAs, GaN, or AlN. Alternately, the figures could have been drawn with the GaN devices grown on an exposed portion of the buried template layer, and the GaAs (or InP) devices grown directly on the handle substrate.
More particularly, it is noted that for both SOI variants, a substrate (or handle) of, for example, silicon, SiC or sapphire is provided with a buried oxide (BOX) layer of silicon dioxide on the surface of the substrate. In the case the GaN structure, a top layer of silicon (Top Si) is formed on the BOX layer and then the CMOS devices are formed in the top silicon layer as shown in FIG. 1F; and in the case of the GaAs or InP structure, a buried CS template layer is sandwiched between a pair of BOX layers (i.e., a lower BOX layer 2 (BOX2) and an upper BOX layer 1 (BOX1) and then the CMOS devices are formed in the top silicon layer, as shown in FIG. 2.
The monolithic approach to heterogeneous integration that is outlined in FIGS. 1A-1F and 2A-2F face many challenges including:
1. vertical and lateral windows etch repeatability
2. the impact of CS growth temperatures on CMOS device parameters
3. impact of growing CS devices on non-native substrates and templates on CS device reliability
4. layer cross contamination during SOI wafer manufacture, III-V growth, and process anneal steps
5. CS to CMOS heterogeneous interconnect fabrication
As mentioned above, heterogeneous integration on modified SOI wafers (as shown in FIGS. 1A-1F and 2A-2F) suffers from limited process control/repeatability related to etching windows into the SOI so that CS devices can be grown. The limited process control/repeatability of the windows etching process impacts two areas that are the following:
1. the quality of the CS devices grown
2. the minimum possible spacing between CMOS and CS devices
The process shown in FIG. 2B above is shown in more detail in FIGS. 2B-1 through 2B-3. Thus, as shown in FIG. 2B-1, the top oxide layer is first etched with a fluoride containing plasma. The etch is a non-selective etch and penetrates into the Top Si. Next, a fluoride-oxide containing plasma is used to selectively remove the remaining Top Si and selectively expose the BOX layer, as shown in FIG. 2B-2. Next, the upper portion of the exposed BOX layer is dry etched with fluoride containing plasma (as shown FIG. 2B-3); it being noted that a thin portion of the BOX layer remains. This thin BOX layer is then removed with a final wet HF etch.
The inventors have recognized that both of these issues stem from the fact that in order to achieve the minimum spacing between CMOS and CS devices, one must dry etch most of the Top oxide/Top Si/BOX stack and leave a minimal amount of BOX (above the CS template surface).
The final wet etch removal of a thin residual BOX layer is necessary because in most cases complete dry etch removal of the buried oxide would result in a damaged template surface for CS growth. This in turn would result in higher defects in the CS devices that may suffer from performance and reliability issues (impacting area 1 above). On the other hand, the hydrofluoric acid solutions used for final BOX removal will substantially laterally etch both the top oxide layers (above the CMOS) and BOX if wet etch times are long (impacting area 2 above). As a result, the amount of BOX left after the dry etch process should be as thin as possible, so as to minimize wet etch times.
A poorly controlled dry etch of the BOX could result in either an over etch of the BOX resulting in a complete dry etch process (impacting area 1 above), or in an under etch of the BOX that would leave more oxide than expected for wet etch removal (impact areas 1 or 2 above). If the wet etch time of the under dry etched case is not adjusted, and residual oxide is present in the windows, then the CS devices will fail to nucleate properly during growth (impacting area l above) in windows. If the wet etch time is adjusted to remove the oxide, but it is lengthened too much, than the lateral etching of the oxide may be excessive (impacting area 2 above)
In accordance with the present disclosure, a layer having an elemental semiconductor device is disposed over aburied oxide (BOX) layer. A selective etch layer is disposed between the elemental semiconductor device layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in the etched window.
In one embodiment, a semiconductor structure is provided having CMOS transistor and a compound semiconductor device. The structure includes: a compound semiconductor growth support for the compound semiconductor having the compound semiconductor device therein; a selective etch layer on the compound semiconductor growth support; and a silicon layer disposed over the selective etch layer, the silicon layer having disposed in portions thereof the CMOS transistors. A window formed through other portions of the silicon layer and underlying portions of the selective etch layer exposes a portion of the compound semiconductor growth support. The compound semiconductor is disposed over the exposed portion of the compound semiconductor growth support.
In one embodiment, the selective etch layer is aluminum oxide (Al2O3), silicon nitride (SiNx), aluminum nitride (AlN), hafnium oxide, or zirconium oxide or a plurality of layers having combinations of aluminum oxide (Al2O3), silicon nitride (SiNx), aluminum nitride (AlN), hafnium oxide, or zirconium oxide.
In one embodiment, the compound semiconductor growth support is silicon (Si), SiC or sapphire.
In one embodiment, the compound semiconductor growth support is a compound or elemental semiconductor.
In one embodiment, the compound semiconductor growth support is Ge, InP, GaAs, GaN, or AlN.
The overall thickness of the selective etch layer or layers and the remaining buried oxide are selected to minimize or eliminate any additional buried oxide thickness relative to typical SOI buried oxide thicknesses, which, in turn, widens the process windows available during modified SOI manufacture, CS/CMOS process integration, and CS growth processes.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
USPTO Backgrounds
USPTO Backgrounds