The present invention relates to a circuit to disconnect a load and to preserve charge on a capacitor under emergency conditions and, more particularly, to a circuit to provide power during head retract and spindle motor brake in a hard disk drive memory system.
Moving media hard disk drive (HDD) memories are commonly used in computers and portable electronic systems whenever substantial amounts of memory storage are required. In moving media hard disk drive memories, the motion of the spinning disks suspends a magnetic read/write head above the media to facilitate the motion of the head across the disk. A voice coil motor or head actuator is then used to position the head above a particular data sector and track. When the battery or power supply fails or is unexpectedly disconnected, an emergency condition or a power-down procedure including retracting the read/write head to areas free from encoded data and/or braking of the spindle motor must be performed. The positioning of the head into a safe area is known as a head retract. The braking of a spindle motor is known as a spindle brake.
If the head retract is not completed before the head crashes onto the disk, permanent loss of data and damage to the disk may result. In order to prevent such damaging head crash, the head retract circuit must be able to provide reliably an auxiliary gate drive to the power transistor devices during retract even if the power supplies are failing completely.
FIG. 1 illustrates one such circuit to maintain a voltage on a capacitor in the event of an emergency condition to be used to retract the arm and/or to brake the motor. The maintained capacitor voltage is used for providing gate drive to the power transistor devices during retract and/or brake. In FIG. 1, the voltage on capacitor 114 decays such as illustrated in FIG. 2 as a result of a noisy switching on and off of the regulator 104 and the activation and deactivation of the sleep circuit 106 which turns on and off the load. As illustrated in FIG. 1, the ENABLE input to the regulator 104 is illustrated as the output voltage VFAULTZ of a power supply monitoring comparator 102, where Z at the end of a signal name by the convention used in this description means the logical complement, i.e., VFAULTZ is the complement of VFAULT. This voltage is a series of pulses which activate and deactivate regulator 104 and load 106 under a noisy situation. Normally, once a regulator is disabled completely, it takes time to recover. It can be seen from a linear regulator schematic shown in FIG. 8 that the base node 802 of the output stage NPN transistor in the regulator takes time to slew up to a certain voltage level to turn on the NPN after the node 802 has been pulled low completely. In the meantime, the load would be turned on relatively quickly. If the VFAULTZ pulses are short, then the consequence is that each turn on is not long enough for the regulator to recover, and thus the load would drain a certain amount of charge from the capacitor 114 each time. So the voltage at node V10 (and VPUMP) would droop, as shown in FIG. 2. But this drooping of the voltage at V10 and VPUMP is not desirable, because the voltage at the capacitor is needed for driving the gates of the power transistor devices for head retract and spindle brake. FIG. 3 is an oscilloscope picture with implementation as shown in FIG. 1 showing the drooping of V10 voltage occurring under a fault on the power supply VCC5. Glitches are noise pulses which are unexpected and of short duration.
The present invention provides a method and apparatus for maintaining the voltage on a capacitor. The voltage is maintained during an emergency condition for example a voltage loss or voltage reduction. Additionally, the present invention maintains this voltage on the capacitor if there are glitches in the voltage. The present invention employs a one-shot circuit to prevent these glitches from reaching the regulator circuit and consequently from preventing the capacitor from discharging due to excess on and off operation of the regulator circuit. Thus, the present invention uses a one-shot device to prevent capacitor droop when the voltage as a result the emergency condition causes multiple trips due to circuit and system noise.
USPTO Backgrounds
USPTO Backgrounds