The present invention relates to a semiconductor device and, more particularly, to a resin sealed package structure that is effectively adopted in such a case where a copper (alloy) type frame is used for a lead on chip (LOC) structure of an LSI circuit.
An example of the basic structure of a LOC package is shown in FIG. 16. The basic structure of the LOC package is disclosed in JP-A-61-241959. A plurality of inner leads 3, which are extended onto a surface of a chip with a circuit formed thereon, are fixed with an adhesive agent on the chip 5 through an insulating film. The inner leads 3 and the chip 5 are electrically connected by bonding wires (thin metallic wires) 4 In order to reduce the number of pins and to ensure stable supply of line voltage, a common inner lead 1 is provided in parallel to the arranging direction of the electrodes of the chip 5 and electrically connected, as a power lead that permits multi-point connection, by means of the chip 5 and the bonding wires 4. Lastly, the entire assembly is sealed with a molding resin 7. In comparison with a conventional package design wherein a chip is mounted on a die pad, the LOC design has advantages such that it permits a larger chip to be mounted, accommodates larger current to achieve higher speed, and allows higher flexibility of chip layout design.
USPTO Backgrounds
USPTO Backgrounds