The availability of unlicensed mm-wave RF bands is spurring the development of main stream applications that use mm-wave wireless technologies. For example, the Institute of Electrical and Electronics Engineers (IEEE) 802.11ad standard—also known as WiGig to consumers—promises up to 7 Gigabits per second data rate over the 60 GHz frequency band for consumer applications such as wireless transmission of high-definition video.
Communication over mm-wave frequency bands can be implemented in wireless communications devices by a “Wi-Fi” module soldered to a printed circuit board of the device. The Wi-Fi module is typically connected on the printed circuit board to an applications processor (CPU) through a host interface (e.g., Peripheral Component Interconnect Express). Within the Wi-Fi module, there is typically a MAC-PHY integrated circuit that implements the physical networking layer (e.g., the 802.11ad/WiGig physical layer) and the media access control networking layer (e.g., the 802.11ad/WiGig media access control layer). There is also a radio frequency integrated circuit (also referred to as a “RFIC”) for controlling an antenna or an array of antennas in wireless communications with one or more other wireless communications devices. The MAC-PHY circuit and the RFIC may be connected by a bi-directional analog signal path and a RFIC control path.
The MAC-PHY circuit may use the RFIC control path to send signals to the RFIC for, among other things, gain and antenna control for real-time beamforming. For example, the RFIC control path may be implemented as a high-speed serial bus. Unfortunately, implementing the RFIC control path as a high-speed serial bus presents a number of potential issues. First, a high-speed serial bus may increase power requirements, which is a drawback for battery-operated wireless communications devices. Second, a high-speed serial bus may require specialized circuity that increases per-unit cost. Third, using a high-speed serial bus may result in a higher latency implementation due to protocol and packet structure requirements. Fourth, a high-speed serial bus may require high speed clocking using phase locked loops (PLLs) which can have adverse effects on the radio frequency circuitry.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
USPTO Backgrounds
USPTO Backgrounds