1. Technical Field
The present invention relates to a timer circuit, and particularly relates to a timer circuit that utilizes charging and discharging of a capacitance element.
2. Related Art
Timer circuits that measure time by charging capacitors (hereinafter referred to as capacitance elements) external to the circuits (for example, see Japanese Patent Application Laid-Open (JP-A) No. 2000-241565) are commonly known as timer circuits that are used in semiconductor integrated circuits and the like.
FIG. 9 illustrates an example of a circuit diagram of a related art timer circuit that uses charging of a capacitance element C. As illustrated in FIG. 9, this configuration is provided with a comparator CMP, a reference voltage source that generates a reference voltage VREF, a charging circuit A for putting the capacitance element C into a charged state and a discharging circuit B for putting the capacitance element C into a discharged state. The capacitance element C is connected to the circuit by a capacitive element connection terminal.
The charging circuit A is provided with a resistance element R1 and a switch 51, and the discharging circuit B is provided with a resistance element R2 and a switch S2. A timer operation allowance signal is input to the switch 51 without being inverted, and the timer operation allowance signal is inverted by a NOT circuit and input to the switch S2. Thus, the charging circuit A and the discharging circuit B are connected to the capacitance element C exclusively.
FIG. 10 illustrates an operation timing chart of this related art timer circuit.
When the timer stops, the timer operation allowance signal is put to low level, the discharging circuit B is connected to the capacitance element C, and a state in which the capacitance element C is discharged is continued. When the timer starts, the timer operation allowance signal is put to high level, the charging circuit A is connected to the capacitance element C, and charging of the capacitance element C begins. Then, when the capacitance element C is charged up to the reference voltage VREF, a time-up signal is output from the comparator CMP.
Thus, the duration, from when charging of the capacitance element C is started until the time-up signal that is the output signal of the comparator CMP is output, is utilized as a timer duration. By the capacitance of the capacitance element C being changed, the timer duration may be set to an arbitrary timer duration. Therefore, this circuit may be utilized as a timer circuit in many semiconductor integrated circuits.
However, in the related art timer circuit described above, if a problem occurs in the external capacitance C, or foreign bodies or the like adhere to a circuit substrate and the capacitance element C is short-circuited, the timer does not get to time-up. Even if a spare timer circuit is provided, the spare timer circuit may not be switched to unless it can be detected that the capacitance element C is in the short-circuit state.
USPTO Backgrounds
USPTO Backgrounds