(1) Field of the Invention
The present invention relates to integrated circuits on semiconductor substrates, and more particularly to the fabrication metal contacts to thin amorphous or polysilicon layers having low resistance ohmic characteristics.
(2) Description of the Prior Art
Down scaling and increased packing densities of semiconductor devices on substrates have greatly increased the circuit density on the semiconductor substrate. This increased circuit density has significantly improved the circuit performance and has reduced the cost of todays electronic products.
However, as efforts are made in the semiconductor industry to further down scale the devices, process problems on the substrate and electrical limitations on the devices have made it difficult to manufacture integrated circuits with improved performance. One of the process limitations is the ability to accurately and repeatedly control the etching of contact openings in relatively thick insulating layers to the surface of relatively thin amorphous or polysilicon layers (e.g. &lt;500 Angstroms) that make up part of todays semiconductor devices and the electrical interconnections.
This etch control problem is particularly acute on SRAM circuits having thin film transistors (TFT) as part of the latch circuit on the memory cell. The thin film transistor is usually composed in part of a patterned continuous thin amorphous silicon layer, for example, between about 50 to 700 Angstroms in thickness. This patterned amorphous or polysilicon layer serves as the TFT channel layer, the P.sup.+ source/drain areas and the P.sup.+ doped stripe that form the interconnect to the power supply voltage, usually designated V.sub.cc. The metal contact for the power supply voltage is made through an opening in an insulating layer to the P.sup.+ stripe. Unfortunately, it is difficult to accurately control the etch stop to the thin silicon layer (&lt;700 Angstroms), and therefore unreliable contacts can result. To circumvent this problem, it is common practice in the, prior art, to form an underlying thicker pad polysilicon layer patterned from a previously deposited polysilicon layer. This patterning polysilicon layer functions as a buffer layer to which both the thin P.sup.+ stripe and metal contacts are made.
This prior art method and its limitations are best understood by referring to the FIGS. 1 and 2 for forming the contact to the TFT channel layer on the SRAM cell. An elevational schematic view is shown in FIG. 1 for the completed contact structure and a cross sectional schematic view is shown in FIG. 2 for the region 2--2' in FIG. 1. Referring now to FIG. 2 the prior art contact structure is shown with the various parts also labeled the same as in FIG. 1. A portion of the substrate 10 is shown after completing the P-channel thin film transistor and other circuit elements on the SRAM device. The patterned buffer polysilicon layer 14 is shown formed on a previously deposited first insulating layer 12. The patterned layer 14 is usually formed at an earlier process step, such as when the N+ bit lines are formed for the SRAM device. A second insulating layer 16, also deposited during an earlier processing step is shown deposited over the buffer polysilicon layer 14. After forming the gate electrode (not shown) for the thin film transistor (TFT) a thin gate oxide is formed on the gate electrode, and this oxide also extends over the contact area and is shown as insulating layer 18. A first contact opening 2 is then etched in the gate oxide 18 and the second insulating layer 16 to the surface of the buffer polysilicon layer 14. Now when the thin channel layer polysilicon 20 is deposited to form the channel for the TFT gate electrode, it also extends over and in the contact opening 2. Layer 20 is then implanted to form the source/drain of the TFT (not shown), and also implanted over the opening 2 to make a P.sup.+ /N.sup.+ junction to the buffer layer 14. After patterning the channel layer 20 to define the channel width and interconnect to the opening 2, a thick third insulating layer 22 is then deposited and a second contact opening 4 is etched adjacent to the first contact opening 2 through layers 22, 18 and 16 to the buffer layer surface 14. A metal layer 30 is deposited and patterned to form the contact in opening 4 that is used to apply a voltage V.sub.cc to the source of the TFT.
Unfortunately, the buffer pad polysilicon layer requires additional space on the chip and therefore limits the packing density of devices. And secondly, the P.sup.+ /N.sup.+ contact results in a contact with diode characteristics that degrade the SRAM electrical performance. Therefore there is still a strong need in the semiconductor industry for making a small low resistance ohmic contact.
USPTO Backgrounds
USPTO Backgrounds