Delay lock loop (DLL) circuits are used to generate a periodic signal such as a clock signal based on a periodic reference signal from, for example, an oscillator. The generated clock signal should maintain a specific phase relationship with the reference signal to be synchronized. A DLL circuit will adjust the phase of the generated clock signal to maintain the desired phase relationship. DLL circuits are used, for example, in high-speed clocked memories such as synchronous dynamic random access memory (SDRAM) devices.
USPTO Backgrounds
USPTO Backgrounds