1. Field of the Invention
This invention relates in general to PCI-to-PCI bridges, and more particularly to a method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0.
2. Description of Related Art
Personal computers (PC) transfer data from disk to CPU, from CPU to memory, or from memory to the display adapter. A PC cannot afford to have separate circuits between every pair of devices. A mechanical switch, like the old phone systems used, would be too slow. The solution is a bus. A bus is simply a common set of wires that connect all the computer devices and chips together. Some of these wires are used to transmit data. Some send housekeeping signals, like the clock pulse. Some transmit a number (the “address”) that identifies a particular device or memory location. The computer chips watch the address wires and respond when their identifying number is transmitted. They then transfer data on the other wires.
Buses come in different widths, which are determined by the number of bits that can travel on the bus at one time. The rate at which a bus transfers data, so many bits per second, is referred to as bandwidth. A bus with a higher bandwidth carries more bits per second, so it transfers more information at once. That means the computer operates faster. Buses also have different speeds. Speed is measured in megahertz (MHz), or millions of cycles per second.
The local bus provides a direct path between peripheral devices (graphics boards, memory, the monitor, or programs) and the CPU. This improves both speed and performance. The local bus usually transfers data at the rate of the computer's system clock. Like other computer technologies, the local bus has industry standards to establish compatibility. Local bus architectures started to appear in the late 1980s when the standard I/O busses such as ISA, EISA, and MCA could not provide the level of video performance that graphics-oriented operating systems and environments such as OS/2 and Microsoft® Windows demanded. The two main local bus standards are Peripheral Component Interconnect (PCI) and the VESA Local-Bus (VL-Bus), standardized by the Video Electronics Standards Association (VESA). Both provide a uniform hardware interface for local bus peripherals. Let's take a closer look at each.
The Video Electronics Standards Association (VESA) version of the local bus, the VL-bus, was developed to be a fast-time-to-market solution. It is primarily an extension of the processor bus to allow video to be connected directly to the CPU, bypassing the slow I/O bus bottleneck. As a result, some major limitations, especially compatibility related ones, currently plague the standard, i.e., not every VL-bus card is compatible with every VL-bus based system.
PCI, on the other hand, is an open, non-proprietary local bus standard that was originally proposed by Intel in late 1991 and later embraced by other leading companies in the computer industry. A PCI special interest group (SIG) was formed in June 1992 to promote, oversee, and enhance the development of PCI as an open standard. By late 1993, there were 160 active members of PCI SIG-including computer manufacturers, semiconductor suppliers, add-in board manufacturers, and BIOS vendors. Version 2.0 of the PCI Local Bus was released in April 1993.
PCI provides a processor-independent data path (a bridge) between the CPU and the system's peripherals. It ensures compatibility between PCI add-in boards and PCI systems. This bridge, or buffer, isolates the CPU and peripherals. More than one peripheral can be attached to the same PCI local bus. With PCI, peripherals can be added directly to the motherboard without extra support and circuitry. And the PCI interface is designed to remain compatible with future generations of microprocessors.
PCI devices also have low access latency, which reduces the amount of time a peripheral has to wait for a bus once it has been requested. In a PCI system, the microprocessor operates simultaneously with bus masters instead of waiting for them.
Bus mastering takes advantage of having a separate bus from the processor bus. By having a separate bus, operations on the PCI bus can occur while there is activity on the processor bus. The processor does not need to control the bus. The bus master grabs hold of the bus and sends data over it while the processor is doing something else.
The PCI bus improved the speed and scalability of client/server networks and became an industry standard just a few years after its introduction. The efficient design, Plug and Play capability, high performance and compatibility of the PCI bus with existing standards offers significant advantages over all other expansion and local buses in use today.
In a system where transactions are required to pass between two separate PCI buses, a traditional PCI-to-PCI bridge device is used to handle this task. A peripheral component interconnect (PCI) bridge provides a connection path between two independent PCI buses. The primary function of a PCI-to-PCI bridge is to allow transactions to occur between a device on one PCI bus and a device on the other PCI bus. System and option card designers can use multiple PCI-to-PCI bridges to create an hierarchy of PCI buses. This allows system and option card designers to overcome electrical loading limits.
In a transaction between two PCI devices, the PCI device that initiates the transaction is called the master and the other PCI device is called the target. If the master and target are on different PCI buses, the bus that the master resides on is the initiating bus. The bus that the target resides on is the target bus.
A PCI-to-PCI bridge has two PCI interfaces, each connected to a PCI bus. The PCI interface of the PCI-to-PCI bridge that is connected to the PCI bus that is closest to the CPU is the primary interface. The PCI interface of the PCI-to-PCI bridge that is connected to the PCI bus that is farthest from the CPU is the secondary interface. Similarly, the PCI bus that is connected to the primary interface of the PCI-to-PCI bridge is called the primary PCI bus. The PCI bus that is connected to the secondary interface of the PCI-to-PCI bridge is called the secondary bus.
A PCI-to-PCI bridge acts essentially as an intermediary between devices located on the secondary bus and devices that are located on the primary bus. The two interfaces of the PCI-to-PCI bridge bus are capable of both master and target operations. The PCI-to-PCI bridge acts as a target on the initiating bus on behalf of the target that actually resides on the target bus. Similarly, the PCI-to-PCI bridge functions as a master on the target bus on behalf of the master that actually resides on the initiating bus. To devices located on the primary bus, the PCI-to-PCI bridge appears as one device where it actually represents several PCI devices that are located on the secondary bus. A detailed specification for PCI-to-PCI bridges is set forth in “PCI-to-PCI Bridge Architecture Specification”, Revision 1.0, Apr. 5, 1994, PCI Special Interest Group, Hillsboro, Oreg.
However, a PCI-to-PCI bridge device requires extra card real estate and increases overall power dissipation. With the increase in circuit density of ASIC (Application Specific Integrated Circuit) technology, there is a strong desire for system developers to integrate or embed the PCI-to-PCI bridge function with other PCI high-function devices that are attached to the same primary PCI bus.
One problem with this integration is that the PCI-to-PCI bridge function requires a Type 1 PCI Configuration Header that allows only two Base Address Registers for internal registers or memory devices. A PCI device that requires more than two PCI Base Address Registers will not be able to embed the PCI-to-PCI bridge function into a single ASIC.
It can be seen then that there is a need for a method and apparatus that implements the PCI-to-PCI bridge function in PCI devices in a manner that supports a greater number of Base Address Registers.
USPTO Backgrounds
USPTO Backgrounds