1. Technical Field
Various aspects of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a technology which reduces a skew between internal signals.
2. Related Art
A semiconductor memory apparatus has an internal memory area divided into multiple memory banks. Each of the multiple memory banks may be selectively enabled by a bank address signal. Generally, the arrangement structure in multiple memory banks and internal circuits is determined by the operational performance and spatial efficiency.
FIG. 1 illustrates an internal structure in a typical semiconductor memory apparatus.
Referring to FIG. 1, a typical semiconductor memory apparatus 1 comprises first memory banks BANK0_0 and BANK0_1 110 and 120, second memory banks BANK1_0 and BANK1_1 210 and 220, first to fourth column selection control units 111, 121, 211 and 221, first to fourth data write units 112, 122, 212 and 222, and first to fourth data read units 113, 123, 213 and 223.
For reference, the first memory banks BANK0_0 and BANK0_1 110 and 120 may be divided into a first sub bank 110 and a second sub bank 120, and the second memory banks BANK1_0 and BANK1_1 210 and 220 may be divided into a third sub bank 210 and a fourth sub bank 220. The memory banks which may be each selectively enabled by a bank address signal may be arranged to be physically divided into multiple sub banks.
Circuits configured to control access to row areas in the memory banks may be provided in row control areas XLOGIC 311 and 312, and drivers and repeaters for various internal signals may be provided in a cross area XY CROSS 320.
The first data write unit 112 is configured to transfer write data to the first sub bank 110, and the first data read unit 113 is configured to sense and amplify read data transferred from the first sub bank 110. The second data write unit 122 is configured to transfer write data to the second sub bank 120, and the second data read unit 123 is configured to sense and amplify read data transferred from the second sub bank 120. The third data write unit 212 is configured to transfer write data to the third sub bank 210, and the third data read unit 213 is configured to sense and amplify read data transferred from the third sub bank 210. The fourth data write unit 222 is configured to transfer write data to the fourth sub bank 220, and the fourth data read unit 223 is configured to sense and amplify read data transferred from the fourth sub bank 220.
Meanwhile, each in the first to fourth column selection control units 111, 121, 211 and 221 is configured to control access to each column area in the first memory banks BANK0_0 and BANK0_1 110 and 120 and the second memory banks BANK1_0 and BANK1_1 210 and 220, respectively. The basic operations in the first to fourth column selection control units 111, 121, 211 and 221 may be identical to one another. Therefore, the internal operation in the first column selection control unit 111 and the related internal circuits therein will be described in detail as a representative example.
Column selection signals YI<0> to YI<i> generated by the first column selection control unit 111 control data access to the corresponding memory cell in the first sub bank 110 located within the first memory bank. The column selection signals YI<0> to YI<i> may be transferred through transmission lines to the first sub bank 110. For example, when a specific column selection signal YI<k> is activated, data access to the corresponding memory cell is performed. Thus, in the data read mode, the first data read unit 113 senses and amplifies read data which is transferred from the corresponding memory cell. In the data write mode, the first data write unit 112 transfers write data to the corresponding memory cell.
As described above, the typical semiconductor memory apparatus 1 comprises the column selection control unit provided in each memory bank. In the above example, the column selection control unit is in each sub bank in the memory bank. Such a structure needs a large chip area when the column selection control units may be arranged. Therefore, there is a need for technology which solves the above-described problems, without degrading the performance in the access to the column area.
USPTO Backgrounds
USPTO Backgrounds