1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit capable of reducing current leakage and mitigating voltage stress.
2. Description of the Prior Art
Along with the advantages of thin appearance, low power consumption and low radiation, liquid crystal displays (LCDs) have been widely applied in various electronic products for panel displaying. The operation of a liquid crystal display is featured by varying voltage drops between opposite sides of a liquid crystal layer for twisting the angles of the liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module. In general, the liquid crystal display comprises plural pixel units, a shift register circuit, and a source driver. The source driver is utilized for providing plural data signals to be written into the pixel units. The shift register circuit comprises a plurality of shift register stages which are employed to generate plural gate signals for controlling the operations of writing the data signals into the pixel units. That is, the shift register circuit is a crucial device for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior-art shift register circuit. As shown in FIG. 1, the shift register circuit 100 comprises a plurality of shift register stages and, for ease of explanation, illustrates an (N−1)th shift register stage 111, an Nth shift register stage 112 and an (N+1)th shift register stage 113. Each shift register stage is employed to generate one corresponding gate signal furnished to one corresponding gate line based on a first clock CK1 or a second clock CK2 having a phase opposite to the first clock CK1. For instance, the (N−1)th shift register stage 111 is employed to generate a gate signal SGn−1 furnished to a gate line GLn−1 based on the second clock CK2, the Nth shift register stage 112 is employed to generate a gate signal SGn furnished to a gate line GLn based on the first clock CK1, and the (N+1)th shift register stage 113 is employed to generate a gate signal SGn+1 furnished to a gate line GLn+1 based on the second clock CK2. The Nth shift register stage 112 comprises a pull-up unit 120, an input unit 130, an energy-store unit 125, a discharging unit 140, a pull-down unit 150, and a control unit 160. The pull-up unit 120 pulls up the gate signal SGn according to a driving control voltage VQn. The discharging unit 140 and the pull-down unit 150 are utilized for pulling down the driving control voltage VQn and the gate signal SGn respectively according to a pull-down control voltage Vdn generated by the control unit 160.
In the operation of the Nth shift register circuit 112, when the driving control voltage VQn is not pulled up to high-level voltage, since both the low-level voltages of the driving control voltage VQn and the gate signal SGn are the low power voltage Vss, the current leakage event of the pull-up unit 120 may occur due to the ripple of the driving control voltage VQn which is caused by the rising and falling edges of the first clock CK1 via a capacitive coupling effect based on the device capacitor of the pull-up unit 120. Accordingly, the voltage level of the gate signal SGn is likely to drift significantly, which degrades the image quality of the liquid crystal display. In another aspect, when the driving control voltage VQn is not pulled up to high-level voltage, the pull-down control voltage Vdn is retained to around the high power voltage Vdd so as to continue turning on the transistors of the discharging unit 140 and the pull-down unit 150 for continuously pulling down the driving control voltage VQn and the gate signal SGn. That is, the transistors of the discharging unit 140 and the pull-down unit 150 suffer high voltage stress in most of operating time, which is likely to incur an occurrence of threshold voltage shift. Besides, when the pull-down control voltage Vdn is pulled down to the low power voltage Vss, the two transistors of the control unit 160 are both turned on, which causes high power consumption and in turn raises working temperature. In view of that, the reliability and life-time of the shift register circuit 100 are then downgraded.
USPTO Backgrounds
USPTO Backgrounds