1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more particularly, to a method for manufacturing a semiconductor memory device having a contact.
2. Description of the Related Art
In general, as the dynamic random access memory (DRAM) becomes more highly integrated, the size of a cell gradually decreases, thereby decreasing the process margin in manufacturing a semiconductor device. Thus, precision in the alignment in forming a contact in the cell becomes more important.
In a DRAM, a contact in a cell array portion, particularly, a contact for connecting a storage electrode of a capacitor to a semiconductor substrate is usually formed between a bit line and a gate electrode line. Thus, securing an alignment margin to form a contact in such condition directly affects the performance therefor of the device.
Also, a semiconductor memory device of 64M DRAM or more adopts a capacitor on bit-line (COB) structure, which results in an increase of a step difference between a cell array region and a peripheral circuit region. Accordingly, it is very difficult to secure an appropriate focus margin and form a fine pattern.
USPTO Backgrounds
USPTO Backgrounds