1. Field of the Invention
The present invention relates to a thin film transistor (TFT) process, and more particularly, to a method of forming a top gate thin film transistor.
2. Description of the Related Art
Thin film transistors (TFTs) are utilized in various fields. For example, a TFT can be used in a liquid crystal display device (LCD) to drive liquid crystals, as a sensor for reading images and the like. Hereinafter, a traditional top gate TFT process will be described, with reference to FIGS. 1A˜1D.
In FIG. 1, a transparent substrate 100, such as a glass substrate, is provided. The substrate 100 has a predetermined channel area 105 thereon. By performing a first photolithography procedure using a first reticle, a silicon island 110 is formed on part of the substrate 100.
In FIG. 2, by performing a second photolithography procedure using a second reticle, a photoresist layer 120 is formed on the substrate 100 and part of the silicon island 110. The photoresist layer 110 has an opening 125 exposing the surface of the silicon island 110 in the channel area 105. An ion implantation 130 is performed to implant impurities into the silicon island 110 in the channel area 105, thus a channel layer (also referred to as an active layer) 111 is formed in the silicon island 110. This step functions as a threshold voltage adjustment (Vt adjustment).
In FIG. 1C, an insulating layer 140 is formed on the substrate 100 and the silicon island 110. By performing a third photolithography procedure using a third reticle, a gate 150 is then formed on part of the insulating film 140. Using the gate 150 as a mask, a low-dose ion implantation 160 is performed to form lightly doped drain (LDD) regions 165 in part of the silicon island 110.
In FIG. 1D, by performing a fourth photolithography procedure using a fourth reticle, a photoresist layer 170 is formed on part of the insulating layer 140 and over the gate 150. A high-dose ion implantation 180 is performed to form heavily doped regions 185 in part of the silicon island 110. The heavily doped regions 185 serve as source/drain regions.
Accordingly, the traditional top gate TFT process requires four reticles for patterning the silicon island 110, the photoresist layer 120, the gate 150 and the photoresist layer 170. Thus, the traditional process is complicated and expensive.
USPTO Backgrounds
USPTO Backgrounds