1. Field of the Invention
The disclosed methods and systems relate to a phase-change memory device, and more particularly, to a phase-change memory device with improved current driving capacity and a method of fabricating the same.
This application claims priority from Korean Patent Application No. 10-2006-0001011 filed on Jan. 4, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Phase-change random access memories (PRAMs) store data using a phase-change material, such as any number of chalcogenide alloys that can take either a crystalline state or an amorphous state based on a particular heating and cooling process applied to the material. The resistance of a phase-change material in its crystalline form is relatively low compared to the resistance of the phase-change material in it amorphous form. Generally, the crystalline state is referred to as a set (or “0”) state and the amorphous state is referred to as a reset (or “1”) state.
A phase-change memory is a device that includes a plurality of phase-change memory (PCM) cells disposed at positions where a plurality of bit lines and a plurality of word lines intersect. Each PCM cell has a device composed of a phase-change material whose resistance varies depending on its state (crystalline or amorphous) and an access device (e.g., a cell diode) controlling the current flowing through the phase-change material.
FIG. 1 is a circuit diagram of a conventional phase-change memory device 1. As shown in FIG. 1, the conventional phase-change memory device 1 includes a phase-change memory (PCM) cell array 2 and a row driver 6. The PCM cell array 2 includes a plurality of PCM cells 3 connected between each of a plurality of bit lines BL0˜BLn and of both word lines WL0 and WL1. The row driver 6 includes an inverter consisting of a pull-up transistor 7 and a pull-down transistor 8, and operates to adjust the voltage levels of the word lines WL0 and WL1 in response to row address signals XS0 and XS1.
To read or write data stored in the PCM cells 3, one of the bit lines BL0˜BLn and one of the word lines WL0 and WL1 must be selected. For example, when the PCM cell 3 (which is connected between bit line BLn and word line WL1) is selected, a current (shown passing through current path 5) will pass through the PCM cell 3 as a result, thus enabling a data read or write operation.
Since each of the word lines WL0 and WL1 may have a large intrinsic resistance (shown as resistors R_WL0, R_WL1) only a limited number of PCM cells can be connected with a given word line. Further, in order to properly operate such a high-resistance word line, the row driver 6 must have a high current driving capacity.
USPTO Backgrounds
USPTO Backgrounds