1. Technical Field
This invention generally relates to semiconductor devices, and more specifically relates to timing circuits in semiconductor memory systems.
2. Background Art
Many modem semiconductor devices use timing signals that require accurate pulse widths. Unfortunately, as the operating speed of modem devices increases, the required pulse width often narrows and the task of maintaining an accurate pulse width becomes more difficult. This is especially true where temperature, voltage and process variations potentially affect the signal pulse width.
Most modem memory systems use an address transistor detector (ATD) to control the memory circuits such that their evaluation efficiency is maximized. On detecting an address transition, the ATD provides an ATD signal that comprises a pulse or set of pulses. This ATD signal is used to equalize, preset and/or recover the timing critical circuits of the semiconductor memory system, resulting in faster access times. The pulse width of these ATD signals is critical. If the pulse width is too short, it can lead to incorrect data. If the pulse width is too long, the access time may be pushed out (i.e., increased).
Turning now to FIG. 1, FIG. 1 is a portion of a prior art ATD pulse generator 100. ATD pulse generator 100 comprises a plurality of delay elements, including delay elements 102 and 104, a plurality of logic circuits, including logic circuit 106, and an ATD sum 108. The ATD pulse generator receives a plurality of address signals ADDR(i) (e.g., ADDR(1)) and plurality of address signal complements ADDRbar(i) (e.g., ADDRbar(1)) and uses these address signals to create an ATD pulse signal. Typically, the ATD pulse generator 100 receives each address signal in the memory system. For simplicity, FIG. 1 illustrates only the ADDR(1) inputs, with the ADDR(2) to ADDR(i) inputs not shown. The address signals and address signal complements are each split and sent through an ADDR(1) delay element 102 and an ADDRbar(1) delay element 104 resulting in ADDR(1)DLY an ADDRbar(1)DLY signals. The resulting four signals are inputted to an logic circuit 106. The logic circuit 106 performs an exclusive OR operation on each set of two signals and then performs an OR operation on the results. This results in an ATD(1) signal that is outputted to ATD sum 108.
Similar elements create ATD(2) through ATD(i) and these signals are all inputted to ATD sum 108. ATD sum 108 is preferably a full CMOS or ratioed NOR device. Thus, ATD sum 108 "ORs" the ATD(i) signals, creating the final ATD signal.
Turning now to FIG. 3, FIG. 3 is a waveform diagram of various signals in ATD pulse generator 100. The waveforms include two address signals (ADDR(1) and ADDR(2)) and their complements. Also shown are two delayed address signals (ADDR(1)DLY and ADDR(2)DLY) and their complements. Of course, in an actual ATD device, many more address signals (ADDR(3)-ADDR(i)) would be used to create the ATD signal.
ADDR(1), ADDR(1)DLY and their complements are inputted into a logic circuit 106 which outputs an ATD(1) signal. Likewise, ADDR(2), ADDR(2)DLY and their complements are inputted into a logic circuit (not shown in FIG. 1) which outputs an ATD(2) signal. As shown in FIG. 3, the ATD(i) signals have a pulse width that is a function of the delay through the various delay elements (e.g., 102, 104). These ATD(i) signals, are summed together by ATD sum 108.
Thus, the ATD pulse width is determined by the amount of delay through the delay elements. The accuracy of the pulse width is then a function of the accuracy of the delay elements.
Turning now to FIG. 2, FIG. 2 is a schematic view of delay element 200. The delay element 200 is a typical prior art delay that is used in ADDR delay 102 and ADDRbar delay 104 of FIG. 1. Delay element 200 comprises strings of inverters 202 with capacitors 204 in between. The delay through the inverters 202 determines the width of the ATD pulse. Unfortunately, the use of inverters 202 to determine the ATD pulse width has the disadvantage of creating pulse widths that can vary with process and environmental changes. Specifically, because the delay through inverters is a function of process variations, temperature and power supply voltage, the final pulse width of the ATD signal will also fluctuate with those parameters. Without the ability to control the effects of this variation, the ATD pulse width cannot be accurately provided, especially where a short ATD pulse width is required. Thus, this variation can limit the performance of the memory system.
To try and compensate for this problem, some prior art approaches for optimizing ATD pulse width includes trimming the ATD pulse width during fabrication to compensate for process variations. This solution however, does not compensate for variations in the power supply voltage and operating temperature of the memory system. Other solutions have used longer pulse widths to compensate for variations. Unfortunately, this approach comes at the expense of access time and is not an optimal solution.
Therefore, there existed a need to provide an improved mechanism for providing an accurate ATD signal having an optimized pulse width that avoids the limitations and problems of the prior art.
USPTO Backgrounds
USPTO Backgrounds