1. Field of the Invention
The present invention relates to a process for forming a thin film by using plasma CVD for use in the production of a semiconductor device. More particularly, it relates to a process for forming a thin film by using plasma CVD for use in the production of a semiconductor device including the step of covering minute drop portions, which are formed on multi-layered wirings according to the miniaturized shape of elements with an insulating film having a flatness and a reliability. Further, it relates to a semiconductor device including multi-layered insulating films formed by the step for forming the insulating film.
2. Related Prior Art
In relation to a semiconductor integrated circuit device (LSI), circuit elements, such as active elements or passive elements and so on are formed on a semiconductor substrate, and the circuit elements are inter-connected by a wiring layer formed on an insulating film deposited on those elements.
However, in recent years, LSI has become highly-integrated, and the size of circuit elements has been miniaturized, so that the drop of the foundation forming the insulating film becomes steeper.
Further, highly-integrated LSI requires the use of multi-layered wirings in order to connect between structural elements. As the multi-layered wirings are formed via an insulating film on the drop portion, the lower wiring and the upper wiring can cause short-circuits via a defective portion of an inter-insulating film when the inter-insulating film is not perfectly formed.
Furthermore, the upper wiring portion becomes thinner at the steep drop portion and results in a high resistance, and is cut down when the drop portion remains without forming it flat, so that there is the possibility of lowering the reliability of LSIs.
In conventional processes, the insulating film is formed by a process such as the CVD (Chemical Vapor Deposition) process. However, it is impossible to perfectly cover the steeply dropped portions of the surface of a substrate. This is because the quality of covering of the insulating film is not good. For example, as described in Japanese unexamined patent application No. 4-111424, the covering is currently improved by coating SOG (Spin On Glass) using a spinner process or using an organic gas, for example, TEOS [Tetraethoxy silane : Si (OC.sub.2 H.sub.5).sub.4 ] and the like, as a feed gas. The resulting insulating film, however, is not significantly improved over conventional processes.
Further, a process was also employed in which the film was reflowed by annealing after deposition for flattening the surface thereof, and the insulating film having relatively low-melting point, such as PSG (Phospho-silicate Glass), and BPSG (Boron-doped Phospho-silicate Glass) had to be used in such a conventional process. It was required to subject the insulating film, such as PSG and BPSG to reflow-treatment at a high temperature of about 900.degree. C. or above as the above-described, so that there was a limit as to the feasibility of this process.
Further, in the above-case, it was known that the anneal temperature could be lowered when annealing with water vapor. However, it has not been put to practical use because of a significant reduction in the quality of the insulating film when annealing in the water vapor in this way.
USPTO Backgrounds
USPTO Backgrounds