1. Field of the Invention
The present invention relates to a semiconductor device having a trench-type isolation structure and a method of manufacturing the same.
2. Description of the Background Art
In a semiconductor integrated circuit, in order to completely independently control elements in its operation, it is necessary to eliminate electrical interference between the elements. For this reason, an isolation structure having an isolation region is adopted in the semiconductor integrated circuit. As one of the isolation structures, a trench isolation method is widely known and various improvements thereof are proposed.
The trench isolation method is a method to electrically insulate the elements by forming a trench which extends from a surface of a substrate towards the inside thereof and filling the inside of the trench with a dielectric substance. In this method, there is little bird's beak, which is found in the isolation structure formed by the LOCOS method. For this reason, the isolation structure by the trench isolation method needs a smaller area on the surface of the substrate to form than that by the LOCOS method, and therefore the trench isolation method is a preferable method to promote size reduction of the semiconductor integrated circuit. Accordingly, the trench isolation method is an essential isolation method in the semiconductor integrated circuit whose size is to be further reduced in the future.
FIG. 23 is a schematic plan (top) view showing a semiconductor device 101P in the background art. FIGS. 24 and 25 are (vertical) cross sections taken along the line AP—AP and the line BP—BP in FIG. 23, respectively. FIG. 26 is an enlarged cross section showing part of FIG. 25. In FIG. 23, part of the elements shown in FIGS. 24 to 26 are omitted.
As shown in FIGS. 23 to 26, the semiconductor device 101P comprises a P-type silicon single crystal substrate (hereinafter, referred to simply as “substrate”) 1P. A trench 2P is formed, extending from a main surface 1SP of the substrate 1P towards the inside of the substrate 1P, and the trench 2P forms an isolation region AR2P.
A silicon oxide film 9AP is formed on an inner surface 2SP of the trench 2P and a silicon oxide film 9BP is formed on the silicon oxide film 9AP. In this case, the inside of the trench 2P is filled with the silicon oxide films 9AP and 9BP (also generally referred to as “silicon oxide film 9P”). The silicon oxide film 9P is a so-called trench isolation.
In the background-art semiconductor device 101P, the silicon oxide film 9P which serves as the trench isolation has a shape sagging from the main surface 1SP of the substrate 1P along an opening edge of the trench 2P (hereinafter, also referred to as “sag or depression”) 9RP.
An N channel-type field effect transistor (NMOSFET) is formed in an active region AR1P of the semiconductor device 101P. In more detail, a gate insulating film 4P extends on the main surface 1SP of the substrate 1P across the active region AR1P (see FIG. 23). A polysilicon film 5AP and a tungsten silicide film 5BP are layered on the gate insulating film 4P in this order, and the polysilicon film 5AP and the tungsten silicide film 5BP form a gate electrode 5P. Further, as shown in FIGS. 25 and 26, the gate electrode 5P extends also on the silicon oxide film 9P across the silicon oxide film 9P and is also arranged in the sag 9RP of the silicon oxide film 9P. A sidewall oxide film 41P is formed on the gate insulating film 4P, being in contact with a side surface of the gate electrode 5P.
Further, two source/drain layers 6P are formed in the main surface 1SP of the substrate 1P with a channel region of the MOSFET below the gate electrode 5P interposed therebetween. The source/drain layers 6P consists of an N+-type layer 6BP and an N−-type layer 6AP, and the N−-type layer 6AP has an impurity concentration lower than that of the N+-type layer 6BP and is formed closer to the channel region.
Furthermore, a channel impurity layer 10P to control a threshold voltage of the MOSFET is formed in the main surface 1SP of the substrate 1P. The channel impurity layer 10P is formed of a P-type layer like the substrate 1P and has an impurity concentration higher than that of the substrate 1P. The channel impurity layer 10P is provided in a region deeper than the channel region and the whole of it is formed in a plane substantially parallel to the main surface 1SP of the substrate 1P. Part of the channel impurity layer 10P and part of the source/drain layers 6P share a formation region (overlap one another) in the substrate 1P, and more specifically, the channel impurity layer 10P is formed across bottom portions of the source/drain layers 6P.
Next, a method of manufacturing the semiconductor device 101P will be discussed, referring to FIGS. 27 to 31 along with FIGS. 23 to 26. Further, FIGS. 27 to 31 are vertical cross sections taken along the line AP—AP of FIG. 23, like FIG. 24.
First, the substrate 1P is prepared, and the main surface 1SP of the substrate 1P is thermally oxidized to form a silicon oxide film 7P (see FIG. 27). Subsequently, a silicon nitride film 8P (see FIG. 27) is formed on the silicon oxide film 7P.
Next, a resist (not shown) to cover a region other than the region which is to be the isolation region is formed on the silicon nitride film 8P by photolithography technique. Then, by anisotropic etching with the resist used as a mask, the silicon nitride film 8P, the silicon oxide film 7P and the sub 1P is partially etched in this order. With this etching, a trench 2aP is formed, extending from an exposed surface of the silicon nitride film 8P to the inside of the substrate 1P as shown in FIG. 27. After that, the inner surface 2SP of the trench 2aP is thermally oxidized to form a silicon oxide film 9AaP as shown in FIG. 28, and subsequently a silicon oxide film 9BaF is so deposited as to cover the whole surface of the substrate 1P on the side of the main surface 1SP to fill the inside of the trench 2aP by the HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) method.
The silicon oxide film 9BaP is polished until the silicon nitride film 8P is exposed by the CMP (Chemical Mechanical Polishing) method with the silicon nitride film 8P used as a stopper (see FIG. 29). With this polishing, the portion of the silicon oxide film 9BaP existing in the trench 2aP remains as the silicon oxide film 9BbP.
Then, the silicon nitride film 8P is removed with thermal phosphoric acid and subsequently the silicon oxide film 7P is removed with hydrofluoric acid (see FIG. 30). With these removing processes, the trench 2P which is part of the trench 2aP existing in the substrate 1P remains. Further, as shown in FIG. 30, in the process using the hydrofluoric acid, the sag 9RP is formed in the silicon oxide films 9AaP and 9BbP along an opening edge of the trench 2P.
Next, the main surface 1SP of the substrate 1P is thermally oxidized to form a silicon oxide film again. Then, the channel impurity layer 10P is formed by ion implantation as shown in FIG. 31. Subsequently, the silicon oxide film is removed with the hydrofluoric acid. At this time, the silicon oxide films 9AaP and 9BbP is partially etched to form the silicon oxide film 9P consisting of the silicon oxide films 9AP and 9BP, but the sag 9RP is formed or enlarged in this process using the hydrofluoric acid.
After that, the silicon oxide film, the polysilicon film and the tungsten silicide film are sequentially formed and patterned to form the gate insulating film 4P and the gate electrode 5P (see FIGS. 24 and 25). The ion implantation to form the N−-type layer 6AP, formation of the sidewall oxide film 41P and the ion implantation to form the N+-type layer 6BP are sequentially performed to complete the semiconductor device 101P shown in FIGS. 23 to 25.
As discussed above, the semiconductor device 101P has the sag 9RP in the opening edge of the silicon oxide film 9P serving as the trench isolation. Specifically, in the background-art method of manufacturing the semiconductor device 101P, the silicon oxide films 9AaP and 9BbP is also partially etched and the sag 9RP is formed in the silicon oxide film 9P when the silicon oxide film 7P and the silicon oxide film which is formed again after removing the silicon oxide film 7P are removed with hydrofluoric acid (see FIGS. 29 to 31).
As shown in FIG. 26, since the sag 9RP is formed lower than the main surface 1SP of the substrate 1P, a portion of the gate electrode 5P which is formed in the sag 9RP is closer to the side surface of the trench 2P as compared with a case where no sag 9RP is formed. For this reason, an electric field E on the side surface of the trench 2P or the active region AR1P among the electric field caused by a voltage applied to the gate electrode 5 becomes strong. In other words, the electric field E is concentrated on an edge of the active region.
Since such an electric field concentration deteriorates the potential at the edge of the active region, the threshold voltage at the edge of the active region of the MOSFET is lower than that in the channel region (central portion). Specifically, a parasitic MOSFET (or parasitic element) having a threshold voltage lower than a desired (designed) voltage is formed at the edge of the active region. For this reason, the parasitic MOSFET turns on first in the operation, and then portions other than the parasitic MOSFET turn on. As a result, as indicated by the characteristic line β in the view of FIG. 32 showing the characteristics of the MOSFET, a drain current of the MOSFET starts to flow at a voltage lower the desired threshold voltage. In other words, a hump is observed in the characteristic view.
Further, when the channel width decreases as the size of the device is reduced, the presence of the parasitic MOSFET causes an inverse-narrow channel effect where the threshold voltage decreases as the channel width decreases. In other words, a current starts to flow at a voltage lower than the desired threshold voltage in the MOSFET due to the inverse-narrow channel effect.
Furthermore, even in a case of no sag 9RP, the electric field from various wires and the like formed in the isolation region AR2P or on the silicon oxide film 9P affects the potential at the edge of the active region through the silicon oxide film 9P or through the side surface of the trench 2P, to possibly form the parasitic MOSFET.
Since the hump and the inverse-narrow channel effect due to the presence of the parasitic MOSFET causes an increase in off current or leak current of the MOSFET, the yield of the semiconductor device 101P is disadvantageously lowered.
Further, though no sag is formed in the LOCOS because of difference in the method of forming the isolation structure, the trench isolation structure is essential for further size reduction of the semiconductor device, as discussed earlier.
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