The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). An MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions. There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry, the size of each individual device in the circuit and the size and spacing between device elements (the feature size) must decrease.
To achieve scaling of semiconductor devices, a variety of unconventional, sensitive, and/or “exotic” materials are being contemplated. High dielectric constant materials, also referred to as “high-k dielectrics,” such as hafnium dioxide (HfO2), hafnium silicon oxynitride (HfSiON), or zirconium dioxide (ZrO2), are considered for the 45 nm node technology and beyond to allow scaling of gate insulators. To prevent Fermi-level pinning, metal gates (MG) with the proper work function are used as gate electrodes on the high-k gate dielectrics. Such metal gate electrodes typically are formed of a metal gate-forming material such as lanthanum (La), aluminum (Al), magnesium (Mg), ruthenium (Ru), titanium-based materials such as titanium (Ti) and titanium nitride (TiN), tantalum-based materials such as tantalum (Ta) and tantalum nitride (TaN) or tantalum carbide (Ta2C), or the like.
Typically during fabrication of a semiconductor device, the gate stack, comprising a gate insulator and a gate electrode, is exposed to liquid chemistries, such as solvents and/or aqueous solutions, used to remove disposable materials. For example, sulfur peroxide is commonly used during photolithography to strip photoresist from semiconductor substrates, ammonium peroxide is commonly used to clean materials of a semiconductor device, and hydrofluoric acid is commonly used as a pre-clean for metal silicide and to remove low temperature and other oxides. To protect the gate stack, particularly a gate stack comprising sensitive materials such as high-k dielectrics and metal gate-forming materials, a silicon nitride spacer is formed about sidewalls of the gate stack. However, depending on non-uniformities of the gate stack fabrication process or non-uniformities created during preparation of the semiconductor substrate prior to fabrication of the gate stacks, the silicon nitride spacer may not be adequate to protect the gate stack. For example, FIG. 1 is a cross-sectional view of gate stacks 10 overlying a semiconductor substrate 12. Each of the gate stacks comprises a first gate stack-forming layer 14. The first gate stack-forming layer 14 may comprise a high-k dielectric, a metal gate-forming material, or a combination thereof. The gate stacks 10 further comprise a second gate stack-forming layer, such as, for example, another metal gate-forming material or polycrystalline or amorphous silicon. Prior to fabrication of the gate stacks 10, shallow trench isolation (STI) regions 18 are formed within the semiconductor substrate 12 to electrically isolate other regions of the semiconductor substrate. Typically, the STI regions are fabricated by forming a patterned hard mask, usually silicon nitride, over the semiconductor substrate 12, etching exposed regions of the substrate to form trenches, and depositing an insulating material such as silicon oxide in the trenches. The silicon oxide is subjected to planarization to expose the hard mask and the hard mask then is removed by exposure to a wet etch chemistry, such as a subsequent phosphoric acid and hydrofluoric acid glaze. During exposure to the wet etch chemistry, the silicon oxide also is slightly etched laterally. This etching causes a “divot” or void 20 to be formed at the edge of the STI region 18 and the semiconductor substrate 12. Accordingly, during fabrication of the gate stacks 10, the first gate stack-forming layer 14 can be formed, not only overlying semiconductor substrate 12, but also in the divots 20.
In efforts to protect the gate stacks 10 from subsequent wet etch chemistries, a silicon nitride spacer 22 typically is formed about sidewalls of the gate stack. However, while the silicon nitride spacers protect the sidewalls of the gate stacks 10, portions 24 of the first gate stack-forming layer in the divots can still be exposed. During subsequent processing, when exposed to one or more wet etch chemistries that can etch the high-k dielectric, the metal gate-forming material, or both, such as, for example, sulfur peroxide, aluminum peroxide, or hydrofluoric acid, the exposed portions 24 of the gate stack-forming layer 14 in the divots are etched and provide a pathway for the etchant to attack the gate stack-forming layer 14 underlying the second gate stack-forming layer 16, as illustrated in FIG. 2. This etching can create a void 26 underlying the second gate stack-forming layer 16 of the gate stacks 10 and thus lead to catastrophic failure of subsequently-formed transistors comprising such void-containing gate stacks.
This phenomenon also may arise in other situations when divots are not created in the semiconductor substrate. FIG. 3 is a cross-sectional view of a gate stack 10 of a semiconductor device having “footings” 30 of first gate stack-forming layer 14. Footings can result from the non-uniformity of reactive ion etching processes, the non-uniformity of photolithography processes used to form the gate stacks, and the like. Footings also can result when first gate stack-forming layer 14 is deposited in scratches that are formed during polishing of the semiconductor substrate. These footings are exposed even though a protective spacer 22 may be disposed adjacent sidewalls of the gate stack 10. In this regard, the footings provide a pathway for wet etch chemistries used in subsequent processing to attack the first gate stack-forming layer 14 underlying the second gate stack-forming layer 16 of the gate stacks 10, thus forming voids (not shown) that result in catastrophic failure of a subsequently-formed transistor.
Accordingly, it is desirable to provide methods for fabricating semiconductor devices, which methods protect gate stacks comprising high-k dielectrics and/or metal gate-forming materials during subsequent wet etch processing. In addition, it is desirable to provide semiconductor devices fabricated from such methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
USPTO Backgrounds
USPTO Backgrounds