The present invention relates to a data output circuit with a nibble mode function for use in a dynamic memory.
A typical example of the conventional data output circuit is schematically illustrated in FIG. 1. As shown in FIG. 1, the data output circuit comprises data latch circuits L1 to L4, a data output control circuit D, and a couple of output transistors 01 and 02. The latch circuits L1 to L4 are respectively coupled with memory arrays C1 to C4, each including a number of matrix arrayed memory cells, through pairs of data transfer nodes I/01 and I/01 to I/04 and I/04. The latch circuits L1 to L4 are coupled for reception with switch signals R1 to R4. For selecting one of the latch circuits, the switch signal R associated with the desired latch circuit is selected. The output terminal pairs of these latch circuits L1 to L4 are connected to a pair of intermediate nodes Do and Do, as shown. The data output control circuit D is connected to the latch circuits L1 to L4 through the paired nodes Do and Do. For data outputting, the control circuit D allows a data output drive signal .phi.OUT to pass and go to either of the output transistors 01 and 02, through nodes N01 and N02.
In the read mode of the dynamic memory, data are concurrently read out from the memory cells in the memory arrays C1 to C4 at the address (x, y), as specified by an address signal. The data read out are transferred, in the form of a potential difference, to the four pairs of data transfer nodes I/01 and I/01 to I/04 and I/04, and then latched in the latch circuits L1 to L4. One of switch signals R1 to R4 is specified to drive its associated latch circuit. The latch circuit driven by the specified switch signal provides the data stored therein onto the paired intermediate nodes Do and Do in the form of a potential difference. The data is applied to the data output control circuit D which is coupled for reception with the data output drive signal .phi.OUT. The control circuit D outputs the drive signal .phi.OUT onto one of the nodes N01 and N02. The node to which the drive signal .phi.OUT is applied is selected according to the contents of the data applied to the control circuit D. The drive signal .phi.OUT on the node drives the transistor 01 or 02 connected thereto. Then, the data is output at the output node DOUT. When the transistor 01 is driven, the data of a power source (VDD) level, i.e., a high(H) level, is output. When the transistor 02 is driven, the output data is at a reference or ground potential (VSS) level, i.e. a low (L) level.
In the subsequent active modes, the switch signals R2 to R4 are selected, and the data stored in the latch circuits L2 to L4 are output to the output node DOUT in the above mentioned manner.
FIGS. 2A and 2B illustrate a detailed circuit arrangement of the conventional data output circuit of FIG. 1. All the transistors are of N channel MOS type in the output circuit. As shown in FIGS. 2A and 2B the latch circuit L1 comprises a flip-flop made up of transistors 0102 and 0103, and switching transistors 0101, and 0104 to 0109. The transistor 0101 receives, at its gate, a signal .phi.A. One end of the current flow path of the transistor 0101 is connected, through a node N0101, to the junction between the current flow path of the transistors 0102 and 0104 and the current flow path of the transistors 0103 and 0105. The other end of the current flow path of the transistor 0101 is connected to VSS. The transistors 0102, 0104, 0106, 0108 are series connected. Similarly, the transistors 0103, 0105, 0107, and 0109 are series connected. The drain of the transistor 0102 is connected to the data transfer node I/01 and the gates of the transistors 0103 and 0105. The drain of the transistor 0103 is connected to the node I/01 and the gates of the transistor 0102 and 0104. A read/write signal .phi.w is coupled with the gates of the transistors 0106 and 0107. The switch signal R1 is connected to the gates of the transistors 0108 and 0109.
The circuit arrangement of the latch circuit L1 is similarly applied to the remaining latch circuits L2 to L4.
The source of the transistor 0108 in the latch circuit L1 is connected to those of the corresponding transistors 0208, 0308 and 0408 in the other latch circuits L2, L3 and L4. Similarly, the source of the transistor 0109 in thel atch circuit L1 is connected to those of 0209, 0309 and 0409 in the other latch circuits L2, L3 and L4. The interconnection of the sources of the transistors 0108, 0208, 0308 and 0408 in the latch circuits L1 to L4 is connected to the intermediate node Do. The interconnection of the source of the transistors 0109, 0209, 0309 and 0409 is connected to the intermediate node Do.
The intermediate nodes Do and Do are coupled with transistors 011 to 013 which are series connected to VDD. The transistor 012 is inserted between the paired nodes Do and Do. The gates of these transistors 011 to 013 are coupled with a signal .phi.p.
The data output control circuit D comprises the transistors 014 to 023. The data output drive signal .phi.OUT is coupled with the transistors 014 and 015. The signal .phi.p is also applied to the gate of the transistors 020 and 021. The transistors 014 and 020 are connected in series between the signal .phi.OUT and VSS. Similarly, the transistors 015 and 021 are connected in series between .phi.OUT and VSS. The gates of the transistors 016 and 017 are coupled with VDD. The current path of the transistors 016 and 019 is connected between the gate of the transistor 014 and VSS. Similarly, the current paths of the transistors 017 and 018 is connected between the gate of the transistor 015 and VSS. The node Do is connected to the junction between the current paths of the transistors 016 and 019. The other node Do is connected to the junction between the current paths of the transistors 017 and 018. The gate of the transistor 018 is connected to the junction between the current paths of the transistors 014 and 020. The gate of the transistor 019 is connected to the junction between the current paths of the transistors 015 and 021. The drain of the transistor 022 is connected to the drain of the transistors 020 and the gate of the transistor 023. The source of the transistor 022 is connected to VSS. The drain of the transistor 023 is connected to the drain of the transistor 021 and the gate of the transistor 022. The source of the transistor 023 is connected to VSS.
The gate of the output transistor 01 is connected, through a node N01, to the gate of the transistor 023. The gate of the output transistor 02 is connected, through a node N02, to the gate of the transistor 022. The transistors 01 and 02 are connected in series between VDD and VSS. The output node DOUT is connected to the junction between the current paths of these transistors 01 and 02.
The operation of the data output circuit will be described referring to FIGS. 3A to 3L.
In the precharge mode, a row address select signal RAS and a column address select signal CAS are both high (FIGS. 3A and 3B), and the pairs of data transfer nodes I/01 and I/01 to I/04 and I/04 are charged up to VDD, viz. the potential at these nodes is high in level (FIG. 3D). The signal .phi..rho. is also high (FIG. 3E). Accordingly, the transistors 011 to 013, coupled with the intermediate nodes Do and Do, are turned on to charge these nodes to VDD level (FIG. 3J). Further, by the signal .phi.p in H level, the transistors 020 and 021 are turned on to place the nodes N01 and N02 at VSS level.
The address signal applied when the signal RAS is low is used as the row address signal, while the address signal applied when the signal CAS is low is used as the column address signal. The row and column address signals are applied to the memory arrays C1 to C4 for specifying the memory cells from which data are to be read out. When the signal CAS goes low, the signal .phi.p becomes VSS in potential level. The data are read out from the specified memory cells and transferred onto the node pairs I/O and I/O to I/04 and I/04. Then, the signal .phi.A goes high (FIG. 3C). With the H level of the signal .phi.A, the transistors 0101, 0201, 0301 and 0401 are turned on to place the related nodes N0101, N0201, N0301 and N0401 at VSS level. At this time, one of each pair of transistors 0102 and 0103, 0202 and 0203, 0302 and 0303, and 0402 and 0403 is turned on, so that one of each of node pairs I/01 and I/01 to I/04 and I/04 drops to VSS in potential level. In this way, the data are stored and latched in the latch circuits L1 to L4.
One of the switch signals R1 to R4, which are coupled with the paired transistors 0108 and 0109, 0208 and 0209, 0308 and 0309, and 0408 and 0409, is selected by an address designation, and set at high level. It is assumed here that the node I/01 is high in level and the node I/01 is low. (The write signal .phi.w is high in the read mode.) Under this condition, the transistors 0103, 0105, 0107, and 0109 are all turned on. The node Do is set at VSS and the node N04 falls to VSS through the transistor 017. At this time, the switch signals R2 to R4 are at VSS. The data read out onto the paired nodes I/02 and I/02 to I/04 and I/04 are latched in the latch circuits L2 to L4. Then, the drive signal .phi.OUT goes high (FIG. 3K) and, in the control circuit D, the node N01 goes high through the transistor 014. Then, the output transistor 01 is turned on to provide a high level signal at the output node DOUT (FIG. 3L).
If the node I/01 is low and the node I/01 is high, the transistor 02 is turned on and a low data signal appears at the output DOUT.
The column address signal goes high again and the read operation enters the precharge mode. The switch signal R1 becomes VSS in potential level to electrically disconnect the latch circuit L1 from the paired nodes Do and Do. The signal .phi.p goes high to charge the nodes Do and Do up to VDD again. The nodes N01 and N02 drop to VSS in potential. The drive signal .phi.OUT also drops to VSS. The signal .phi.A remains high in level. The data read out onto the node pairs I/01 and I/01 are latched in the latch circuits L1 and L4.
The signal CAS goes low and the active mode is attained. The switch signal succeeding to the signal R2 goes high. The data on the nodes I/02 and I/02 is transferred to the intermediate nodes Do and Do. The control circuit D applies the drive signal .phi.OUT to the node N01 or N02, which is selected according to the contents of that data. Finally, the data is ouput to the node DOUT. The switch signals R3 and R4 are subsequently selected and a similar operation is carried out.
As described above, in the prior art circuit of FIGS. 2A and 2B, the output terminal pairs of the latch circuit L1 to L4 are connected to a single pair of intermediate nodes Do and Do. Of those paired output terminals of the latch circuit L1 to L4, the first output terminals are connected to one of the paired intermediate nodes, and the second output terminals are connected to the other. With this connection, when one active mode is being executed and the column address signal CAS goes high, the potential states on the nodes Do and Do are cleared. For this reason, the paired nodes Do and Do must be charged up to VDD by making the signal .phi.p high. Then, the signal CAS is set low to set up the succeeding active mode. In this active mode one of the signals R1 to R4 is set high, and after one of the nodes Do and Do goes low, the drive signal .phi.OUT must be set high. In other words, the setting high operation of the drive signal .phi.OUT must wait until one of the nodes Do and Do goes low. This is a problem in improving the data read operation.
USPTO Backgrounds
USPTO Backgrounds