1. Field of the Invention
The present invention relates to an arithmetic unit and a data processing unit mounted in a digital signal processor and the like.
2. Description of the Prior Art
A prior art data processing unit for performing data comparison will be described below. The prior art data processing unit hereinafter described is primarily used as a special-purpose circuit when performing variable length encoding of image information, etc. after a discrete cosine transform. The prior art data processing unit has the circuitry shown, for example, in FIG. 16, in which reference character 1x is a memory (8-bit-data memory with addresses 0 to 63), 2x is a read control circuit, 3x is a zero run counter, 4x is a zero decoder, 5x is memory data, 6x is a memory read control signal, 7x is an enable signal, 8x is a zero decode signal, and 9x is a zero run count signal. Further, reference character 10x is a variable length encoder for performing variable length encoding.
Operation of the thus configured data processing unit will be described below with reference to the waveform diagram of FIG. 17 (reference characters shown correspond to those in FIG. 16). In FIG. 17, a typical memory readout address signal is depicted as the memory readout control signal 6x. 
Waveform 1w in FIG. 17 is used as the operating clock (CLK) of the data processing unit of FIG. 16. The read control circuit 2x in FIG. 16 reads out the memory data 5x at the address specified by the memory readout control signal 6x when the enable signal 7x is at a high level (hereinafter referred to as H level) (in the illustrated example, addresses are generated in the order of 0, 1, 2, . . . , 63).
The zero decoder 4x decodes the memory data 5x and, when the memory data shows a value 0, sets the zero decode signal 8x to the H level. At this time, the zero run counter 3x counts up, thus counting the number of 0s occurring consecutively. When the zero decode signal 8x is at a Low level (hereinafter referred to as the L level), the zero run counter 3x shows a value 0.
The thus generated zero run count signal 9x and the zero decode signal 8x are output together with the memory data 5x; the variable length encoder circuit 10x at the following stage performs data processing using the zero run count signal 9x and memory data 5x at the time that the zero decode signal 8x is at the L level. Variable length encoding is a process in which data is compressed by treating the number of consecutive data zeros and the nonzero data following the data zeros as one set of data. Strictly speaking, quantization is performed before the variable length encoding. In the illustrated example, the zero run count signal 9x indicates the number of consecutive data zeros and the memory data 5x the nonzero data.
Since specialized circuitry, such as the zero run counter 3x and the zero decoder 4x, is used to sequentially detect and output the number of consecutive zeros and the nonzero data following the data zeros, the prior art data processing unit lacks versatility and cannot, for example, detect the number of consecutive data values other than zeros; further, when, for example, it becomes necessary to perform an addition or comparison in addition to sequentially detecting and outputting the number of consecutive data zeros and the nonzero data following the data zeros, extra circuitry for performing the addition or comparison has to be added.
Furthermore, the prior art data processing unit, when mounted as a special-purpose circuit in a digital signal processor or the like, is not able to continuously perform the data processing using the zero run count signal 9x and memory data 5x if zeros continue to appear in the memory data. The reason is that, since data compression is performed using both the number of consecutive zeros and the nonzero data, it is not possible to produce the output of the zero run counter 3x and the output of the nonzero data in every cycle.
The prior art data processing unit has also had the problems that it lacks versatility because it is designed for performing data processing on fixed data (in the above example, data zeros), and that the processing time increases since data retrieval is performed through the entire memory even in the case of data that may be all zeros beyond a certain memory range.
It is an object of the present invention to provide an arithmetic unit with sufficient versatility to be able to not only perform the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros but also perform other processing.
It is another object of the present invention to provide an arithmetic unit with sufficient versatility to be able to not only perform the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros but also perform similar processing on data of values other than zero.
It is a further object of the present invention to provide a data processing unit that can continuously perform data processing.
It is still another object of the present invention to provide a data processing unit that can shorten the processing time required to process data.
It is yet another object of the present invention to provide a data processing unit that can increase the degree of freedom of data processing programs.
A first arithmetic unit of the present invention comprises a comparator circuit, a shifter, an adder circuit, a register, and a selection circuit. The comparator circuit takes as inputs first data as comparison reference data and second data as data to be compared with the first data, and performs a comparison between the first and the second data; when the first and the second data match as the result of the comparison, the comparator circuit outputs a value 1 and sets a match signal active, while, when the first and the second data do not match, the comparator circuit outputs the second data and sets the match signal inactive. The shifter accepts an output of the comparator circuit at its input, and shifts, or does not shift, the output of the comparator circuit, depending on the state of the match signal supplied from the comparator circuit. The adder circuit accepts an output of the shifter at one input thereof. The register accepts an output of the adder circuit at its input. The selection circuit accepts a value 0 at one input thereof and an output of the register at the other input, and couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal.
With the selection circuit selecting either the value 0 or the output of the register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data.
According to the above configuration, with the provision of the comparator circuit for performing a comparison between the first and second data, the shifter for accepting the output of the comparator circuit at its input, and for shifting or not shifting the output of the comparator circuit depending on the state of the match signal supplied from the comparator circuit, the adder circuit for cumulatively adding the output of the shifter, and the selection circuit, not only can the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros be performed, but similar processing can also be performed on data of values other than zero. This provides great versatility.
It is also possible to use only the function of the comparator circuit by controlling the shifter, adder circuit, and selection circuit, only the function of the shifter by controlling the comparator circuit, adder circuit, and selection circuit, or only the function of the adder circuit by controlling the comparator circuit, shifter, and selection circuit. This adds great versatility to the arithmetic unit.
A second arithmetic unit of the present invention comprises a comparator circuit, a flag register, a first register, a shifter, a second register, a third register, and a selection circuit. The comparator circuit takes as inputs first data as comparison reference data and second data as data to be compared with the first data, and performs a comparison between the first and the second data; when the first and the second data match as the result of the comparison, the comparator circuit outputs a value 1 and sets a match signal active, while, when the first and the second data do not match, the comparator circuit outputs the second data and sets the match signal inactive. The flag register accepts the match signal at its input. The first register accepts an output of the comparator circuit at its input. The shifter accepts an output of the first register at its input, and shifts, or does not shift, the output of the first register, depending on the state of the match signal supplied from the flag register. The second register accepts an output of the shifter at its input. The adder circuit accepts an output of the second register at one input thereof. The third register accepts an output of the adder circuit at its input. The selection circuit accepts a value 0 at one input thereof and an output of the third register at the other input, and couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal.
With the selection circuit selecting either the value 0 or the output of the third register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data.
According to the above configuration, in addition to the same effects as achieved with the first arithmetic unit, the interposition of the first and second registers and the flag register between the comparator circuit, the shifter, and the adder circuit offers an additional effect; that is, with this arrangement, if the comparator circuit, the shifter, and the adder circuit are not fast in operation, not only can the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros be performed, but similar processing can also be performed on data of values other than zero.
A first data processing unit according to the present invention comprises: a control unit which, when executing an instruction, outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison reference data setting signal, and an end flag signal; a first memory to which the memory read control signal is input; a first data register to which the comparison reference data setting signal is input to set comparison reference data therein; a second data register which stores data from the first memory; a number-of-retrievals counter to which the instruction execution signal is input, and which outputs to the control unit a count of the number of data retrievals so far performed on the first memory; an execution unit to which the instruction execution signal and output data from the first data register and the second data register are input, and which outputs a comparison signal and an execution data signal; and a second memory to which the memory write control signal, the execution data signal from the execution unit, and the end flag signal are input.
In the above configuration, when executing a comparison instruction, the output data from the first data register and the second data register are loaded by the instruction execution signal into the execution unit for data comparison and, at the same time, the number-of-retrievals counter is made to count up, wherein the end flag signal is held inactive until the output of the number-of-retrievals counter reaches a predetermined value and, upon the output of the number-of-retrievals counter reaching the predetermined value, the control unit terminates the comparison instruction and sets the end flag signal active, while the comparison signal from the execution unit is output to the control unit to control writing to the second memory so that the end flag signal and the execution data signal, indicating the number of times that the output data matched and data from the first memory that did not match the comparison reference data, are written to the second memory when the end flag signal is held inactive and also when the end flag signal is set active.
According to the above configuration, the comparison instruction can be executed for any given value by setting desired comparison reference data in the first data register, and can be terminated by the action of the number-of-retrievals counter counting the number of retrievals performed within the comparison range, and the end flag signal can thus be written to the second memory, so that the last written data can be detected by just reading the data written in the second memory.
As described above, since the number of times the comparison data matched, the data that did not match, and the end flag signal are written to the second memory, and since the data in the second memory can be read out (in the order in which the data were written) in each cycle at any later time, subsequent data processing such as variable length encoding can be performed without interruption. Furthermore, any data can be handled by setting any given value in the first data register, and the versatility is thus increased.
Further, by writing the number of times the comparison data matched, the data that did not match, and the end flag signal to the second memory, a variable length encoding instruction can be executed any time without having to be limited to the time at which a count of the number of times the comparison data matched and the data that did not match, based on which variable length encoding is performed, are latched.
Furthermore, when the execution unit is configured to have other functions than the detection of the number of values 0, since it has a path via which to store data in the second memory, the execution unit of such a configuration can also be used without losing its versatility.
When generating data for variable length encoding using specialized circuitry, as in the prior art example, it is not possible to perform arithmetic operations other than those for the generation of data for variable length encoding; if other operations such as additions and comparisons in addition to the generation of data for variable length encoding are to be performed, it will become necessary to provide general-purpose circuitry such as an adder and comparator in addition to the specialized circuitry designed for the generation of data for variable length encoding, and the chip area of the integrated circuit will increase. On the other hand, in the present invention, since the circuitry provided for the generation of data for variable length encoding can be designed with versatility, other operations such as additions and comparisons can also be performed using the same circuitry. Accordingly, not only the processing for the generation of data for variable length encoding but also other processing can be performed without requiring increasing the chip area of the integrated circuit compared with the configuration designed exclusively for the generation of data for variable length encoding.
Furthermore, since the data before variable length encoding is held in the second memory, it is possible to verify whether or not the variable length encoded data has been correctly converted by comparing the variable length encoded data with the data held in the second memory, and the variable length encoded data can thus be debugged.
The last written data earlier mentioned refers to the data that was written at the last address when comparing data in the first memory, for example, from a certain address to a certain address. Upon detecting the last written data, the execution of the comparison instruction is terminated, and the end flag signal is written to the second memory.
When performing processing for variable length encoding or the like, data written by the comparison instruction is read out, and by reading the last written data containing the end flag signal, the end of the data can be detected, thus making it possible to perform variable length encoding without any problem.
A second data processing unit of the present invention comprises: a control unit which, when executing an instruction, outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison reference data setting signal, and an end flag signal; a first memory to which the memory read control signal is input; a first data register to which the comparison reference data setting signal is input to set comparison reference data therein; a second data register which stores data from the first memory; a number-of-retrievals counter to which the instruction execution signal is input, and which outputs to the control unit a count of the number of data retrievals so far performed on the first memory; an execution unit to which the instruction execution signal and output data from the first data register and the second data register are input, and which outputs a comparison signal and an execution data signal; a second memory to which the memory write control signal and the execution data signal from the execution unit are input; and a third data register to which the end flag signal is input, and which stores the address of data stored in the second memory.
In the above configuration, when executing a comparison instruction, the output data from the first data register and the second data register are loaded by the instruction execution signal into the execution unit for data comparison and, at the same time, the number-of-retrievals counter is made to count up, wherein the end flag signal is held inactive until the output of the number-of-retrievals counter reaches a predetermined value and, upon the output of the number-of-retrievals counter reaching the predetermined value, the control unit terminates the comparison instruction and sets the end flag signal active, while the comparison signal from the execution unit is output to the control unit to control writing to the second memory so that the end flag signal and the execution data signal, indicating the number of times that the output data matched and data from the first memory that did not match the comparison reference data, are written to the second memory when the end flag signal is held inactive and also when the end flag signal is set active, and so that the address last written to the second memory is stored in the third data register when the end flag signal is set active.
According to the above configuration, the comparison instruction can be executed for any given value by setting desired comparison reference data in the first data register, and can be terminated by the action of the number-of-retrievals counter counting the number of retrievals performed within the comparison range, and the end flag signal can thus be generated and the memory address be stored in the third data register functioning as a memory address setting register; accordingly, the memory address where the last written data is stored can be detected by just reading the data from the third data register.
As described above, since the number of times the comparison data matched and the data that did not match are written to the second memory, and since the data in the second memory can be read out in each cycle at any later time, data processing such as variable length encoding can be performed without interruption. Further, since the memory address where the last written data is stored is held in the third register instead of writing the end flag signal to the second memory, the bit count of the second memory can be reduced. In the case of the first data processing unit, an extra bit is required for the end flag. In the second data processing unit, on the other hand, the address where the last written data is stored can be found by reading the third register.
Furthermore, any data can be handled by setting any given value in the first data register, and the versatility is thus increased.
The other effects are the same as those obtained with the first data processing unit.
A third data processing unit of the present invention comprises: a control unit which, when executing an instruction, outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison reference data setting signal, an end flag signal, and a number-of-retrievals setting signal; a first memory to which the memory read control signal is input; a first data register to which the comparison reference data setting signal is input to set comparison reference data therein; a second data register which stores data from the first memory; a number-of-retrievals counter to which the instruction execution signal is input, and which outputs a count of the number of data retrievals so far performed on the first memory; a third data register to which the number-of-retrievals setting signal is input to set therein an end value for the number of retrievals; an execution unit to which the instruction execution signal and output data from the first data register and the second data register are input, and which outputs a comparison signal and an execution data signal; a second memory to which the memory write control signal, the execution data signal from the execution unit, and the end flag signal are input; and a match detection circuit to which the output of the number-of-retrievals counter and the value set in the third register are input, and which outputs a match signal to the control unit.
In the above configuration, when executing a comparison instruction, the output data from the first data register and the second data register are loaded by the instruction execution signal into the execution unit for data comparison and, at the same time, the number-of-retrievals counter is made to count up, wherein the end flag signal is held inactive until the match signal is output from the match detection circuit and, in response to the match signal output from the match detection circuit, the control unit terminates the comparison instruction and sets the end flag signal active, while the comparison signal from the execution unit is output to the control unit to control writing to the second memory so that the end flag signal and the execution data signal, indicating the number of times that the output data matched and data from the first memory that did not match the comparison reference data, are written to the second memory when the end flag signal is held inactive and also when the end flag signal is set active.
According to the above configuration, the third data processing unit is capable of executing the comparison instruction for any given value by setting desired comparison reference data in the first data register, and can arbitrarily set the number of retrievals, to be performed within the comparison range, in the third data register, so that the comparison instruction can be terminated after performing an arbitrary number of retrievals. Since the end flag signal can thus be written to the second memory, the last written data can be detected by just reading out the data written to the second memory.
As described above, since the number of times the comparison data matched, the data that did not match, and the end flag signal are written to the second memory, and since the data in the second memory can be read out (in the order in which the data were written) in each cycle at any later time, data processing such as variable length encoding can be performed without interruption. Furthermore, any data can be handled by setting desired values in the third data register and the first data register, and the versatility is thus increased.
The other effects are the same as those obtained with the first data processing unit.
A fourth data processing unit of the present invention comprises: a control unit which, when executing an instruction, outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison reference data setting signal, an end flag signal, a number-of-retrievals setting signal, and a selection signal; a first memory to which the memory read control signal is input; a first data register to which the comparison reference data setting signal is input to set comparison reference data therein; a second data register which stores data from the first memory; a third data register to which the number-of-retrievals setting signal is input to set therein an initial value for the number of retrievals; a number-of-retrievals counter to which the instruction execution signal and output data from the third data register are input, and which outputs a count of the remaining number of retrievals to be performed on the first memory; an execution unit to which the instruction execution signal and output data from the first data register and the second data register are input, and which outputs a comparison signal and an execution data signal; an adder to which the output of the number-of-retrievals counter and a number-of-matches data signal carried in the execution data signal are input; a selector which selects either an output of the adder or the number-of-matches data signal by the selection signal generated by the control unit in accordance with the number-of-matches data signal carried in the execution data signal; and a second memory to which the memory write control signal, data from the first memory that did not match the comparison reference data and that is carried in the execution data signal, an output of the selector, and the end flag signal are input.
In the above configuration, when executing a comparison instruction, the output data from the first data register and the second data register are loaded by the instruction execution signal into the execution unit for data comparison and, at the same time, the number-of-retrievals counter is made to count down, wherein the end flag signal is held inactive until the output of the number-of-retrievals counter reaches a first predetermined value or until the number-of-matches data signal carried in the execution data signal reaches a second predetermined value and, upon the output of the number-of-retrievals counter reaching the first predetermined value or upon the number-of-matches data signal carried in the execution data signal reaching the second predetermined value, the control unit terminates the comparison instruction and sets the end flag signal active, while the comparison signal from the execution unit is output to the control unit to control writing to the second memory so that the end flag signal and the execution data signal, indicating the number of times that the output data matched and data from the first memory that did not match the comparison reference data, are written to the second memory when the end flag signal is held inactive and also when the end flag signal is set active, and so that, when the number-of-matches data signal carried in the execution data signal reaches the predetermined value, all data remaining to be compared are assumed to match the comparison reference data, and the output of the adder, the data from the first memory that matched, and the end flag signal are written to the second memory.
According to the above configuration, the fourth data processing unit is capable of executing the comparison instruction for any given value by setting desired comparison reference data in the first data register, and can arbitrarily set the number of retrievals, to be performed within the comparison range, in the third data register, so that the comparison instruction can be terminated after performing an arbitrary number of retrievals. Furthermore, when data matches occur consecutively, the comparison instruction can be terminated by assuming that the remaining data also match the comparison reference data, thus shortening the entire retrieval time. Since the end flag signal is thus written to the second memory, the last written data can be detected by just reading out the data written to the second memory.
As described above, since the number of times the comparison data matched, the data that did not match, and the end flag signal are written to the second memory, and since the data in the second memory can be read out (in the order in which the data were written) in each cycle at any later time, data processing such as variable length encoding can be performed without interruption. Furthermore, when data matches occur consecutively, the comparison instruction can be terminated by assuming that the remaining data also match the comparison reference data; this serves to shorten the entire retrieval time, hence shortening the processing time. Moreover, any data can be handled by setting desired values in the number-of-retrievals counter and the first data register, and the versatility is thus increased.
The other effects are the same as those obtained with the first data processing unit.
A fifth data processing unit of the present invention comprises: a control unit which, when executing an instruction, outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison reference data setting signal, an end flag signal, a number-of-retrievals setting signal, a number-of-consecutive-matches setting signal, and a selection signal; a first memory to which the memory read control signal is input; a first data register to which the comparison reference data setting signal is input to set comparison reference data therein; a second data register which stores data from the first memory; a third data register to which the number-of-retrievals setting signal is input to set therein an initial value for the number of retrievals; a fourth data register to which the number-of-consecutive-matches setting signal is input to set the number of times that data matches may occur consecutively; a number-of-retrievals counter to which the instruction execution signal and output data from the third data register are input, and which outputs a count of the remaining number of retrievals to be performed on the first memory; an execution unit to which the instruction execution signal and output data from the first data register and the second data register are input, and which outputs a comparison signal and an execution data signal; an adder to which the output of the number-of-retrievals counter and a number-of-matches data signal carried in the execution data signal are input; a match detection circuit to which the number-of-matches data signal and an output of the fourth data register are input for detection of a data match therebetween; a selector which selects either an output of the adder or the number-of-matches data signal by the selection signal generated by the control unit in accordance with an output from the match detection circuit; and a second memory to which the memory write control signal, data from the first memory that did not match the comparison reference data and that is carried in the execution data signal, an output of the selector, and the end flag signal are input.
In the above configuration, when executing a comparison instruction, the output data from the first data register and the second data register are loaded by the instruction execution signal into the execution unit for data comparison and, at the same time, the number-of-retrievals counter is made to count down, wherein the end flag signal is held inactive until the output of the number-of-retrievals counter reaches a predetermined value or until the output of the match detection circuit indicates a match and, upon the output of the number-of-retrievals counter reaching the predetermined value or in response to the output of the match detection circuit indicating a match, the control unit terminates the comparison instruction and sets the end flag signal active, while the comparison signal from the execution unit is output to the control unit to control writing to the second memory so that the end flag signal and the execution data signal, indicating the number of times that the output data matched and data from the first memory that did not match the comparison reference data, are written to the second memory when the end flag signal is held inactive and also when the end flag signal is set active, and so that, when the output of the match detection circuit indicates a match, all data remaining to be compared are assumed to match the comparison reference data, and the output of the adder, the data from the first memory that matched, and the end flag signal are written to the second memory.
According to the above configuration, the fifth data processing unit is capable of executing the comparison instruction for any given value by setting desired comparison reference data in the first data register, and can arbitrarily set the number of retrievals, to be performed within the comparison range, in the third data register, so that the comparison instruction can be terminated after performing an arbitrary number of retrievals. Furthermore, by presetting the desired number of matches in the fourth data register, when data matches occur consecutively the preset number of times, the comparison instruction can be terminated by assuming that the remaining data also match the comparison reference data, thus shortening the entire retrieval time. Since the end flag signal is thus written to the second memory, the last written data can be detected by just reading out the data written to the second memory.
As described above, since the number of times the comparison data matched, the data that did not match, and the end flag signal are written to the second memory, and since the data in the second memory can be read out (in the order in which the data were written) in each cycle at any later time, data processing such as variable length encoding can be performed without interruption. Furthermore, by presetting the desired number of matches in the fourth data register, when data matches occur consecutively the preset number of times, the comparison instruction can be terminated by assuming that the remaining data also match the comparison reference data, thus making it possible to shorten the entire retrieval time and hence the processing time. Moreover, any data can be handled by setting desired values in the search count counter and the first data register, and the versatility is thus increased.
The other effects are the same as those obtained with the first data processing unit.
A sixth data processing unit of the present invention is the same as the first, second, third, fourth, of fifth data processing unit of the present invention, wherein the execution unit comprises: a comparator circuit which takes as inputs the output of the first data register as first data to serve as comparison reference data and the output of the second data register as second data to be compared with the first data, and performs a comparison between the first and the second data, and which, when the first and the second data match as the result of the comparison, outputs a value 1 and sets a match signal active, and when the first and the second data do not match, outputs the second data and sets the match signal inactive; a shifter to which an output of the comparator circuit is input, and which shifts, or does not shift, the output of the comparator circuit, depending on the state of the match signal supplied from the comparator circuit; an adder circuit which accepts an output of the shifter at one input thereof; a register to which an output of the adder circuit is input; and a selection circuit which accepts a value 0 at one input thereof and an output of the register at the other input, and which couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal.
With the selection circuit selecting either the value 0 or the output of the register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output as the execution data signal by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data.
According to the above configuration, the same effects as obtained with the first arithmetic unit of the present invention can be achieved in addition to the effects obtained with the first, second, third, fourth, or fifth data processing unit of the present invention.
A seventh data processing unit of the present invention is the same as the first, second, third, fourth, or fifth data processing unit of the present invention, wherein the execution unit comprises: a comparator circuit which takes as inputs the output of the first data register as first data to serve as comparison reference data and the output of the second data register as second data to be compared with the first data, and performs a comparison between the first and the second data, and which, when the first and the second data match as the result of the comparison, outputs a value 1 and sets a match signal active, and when the first and the second data do not match, outputs the second data and sets the match signal inactive; a flag register to which the match signal is input; a first register to which an output of the comparator circuit is input; a shifter to which an output of the first register is input, and which shifts, or does not shift, the output of the first register, depending on the state of the match signal supplied from the flag register; a second register to which an output of the shifter is input; an adder circuit which accepts an output of the second register at one input thereof; a third register to which an output of the adder circuit is input; and a selection circuit which accepts a value 0 at one input thereof and an output of the third register at the other input, and which couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal.
With the selection circuit selecting either the value 0 or the output of the third register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output as the execution data signal by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data.
According to the above configuration, the same effects as obtained with the second arithmetic unit of the present invention can be achieved in addition to the effects obtained with the first, second, third, fourth, or fifth data processing unit of the present invention.
USPTO Backgrounds
USPTO Backgrounds