The inventive concept relates to dynamic random access memory (DRAM) devices and, more particularly, to capacitor-less DRAM (dynamic random access memory) devices.
In general, a unit memory cell of a DRAM device includes a field effect transistor (hereinafter referred to as a ‘transistor’) and a capacitor that stores charges. The transistor may be a metal-oxide-semiconductor (MOS) transistor that controls reproduction and recording of data. The integration degree of the DRAM device has been continuously increased by reducing the size of the transistor. Also, the integration degree of the DRAM device has been continuously increased by using a capacitor formation process for providing an effective capacity of a capacitor such as techniques of forming a stack capacitor or a deep trench capacitor, techniques of using a capacitor dielectric layer as a high-k dielectric layer, techniques of increasing a surface area of a dielectric layer in a lower portion of a capacitor, and so forth.
However, a short channel effect due to size reduction of the transistor and the complexity of the capacitor formation techniques hinder the further increase of the integration degree of DRAM devices. Accordingly, attempts have been made to modify the structure of the DRAM devices.
USPTO Backgrounds
USPTO Backgrounds