The present invention relates to the field of integrated circuit manufacturing, and, more particularly, to testing of Complementary Metal Oxide Silicon (CMOS) integrated circuits.
At the end of the manufacturing process of a plurality of basically identical integrated circuits formed on a wafer of semiconductor material, a final wafer test is carried out on each device using suitable automatic equipment before the devices are separated from each other. Testing includes various electrical measurements intended to ascertain that each device complies with certain functional requirements defined in the design phase. Devices that do not comply with all these requirements are identified so that they can be rejected once the wafer has been divided, whereas the devices that have passed the test are forwarded to the subsequent assembly and encapsulation phases.
When testing large size CMOS digital integrated circuits or mixed digital/analog integrated circuits, one of the parameters on which one of the most significant electrical measurements is made is the idle current in static conditions, i.e. the current that the integrated circuit absorbs when it is connected to the power source but is functionally inactive and in stand-by or power-down mode. This parameter is usually indicated as IDDQ where I indicates the current, DD indicates the D.C. power supply and Q xe2x80x9cquiescentxe2x80x9d or idle status.
The IDDQ current measured includes the sum of the so-called sub-threshold currents of the MOS transistors, including those that form the memory cells, and of the leakage currents due to manufacturing defects or faulty materials. Further junction leakage currents are at least two orders of size lower and are therefore negligible. If the test specimen is faulty, as will be explained in more detail below, the current measured also includes a contribution provided directly by the fault.
For each integrated circuit under test, the current IDDQ measured is compared in a comparator with a threshold value Ith established previously by examining test specimens of the same device and taking into account suitable margins of tolerance. If the comparison reveals that IDDQ is equal to or higher than Ith, the device tested is identified for subsequent rejection.
The IDDQ test method, i.e. the method based on measurement and comparison of the IDDQ current, is acknowledged as highly significant in CMOS integrated circuit test schedules but is becoming ever more difficult to apply as integrated circuits become increasingly complex, i.e. as integration density and the number of logic gates, which usually indicate the level of complexity of a digital integrated circuit, increase. This is easier to understand considering that, as integration techniques have gradually improved, IDDQ currents have risen in just a short time from the 1 xcexcA to 10 xcexcA of integrated circuits containing 1,000-10,000 logic gates based on 1.5-1.0 xcexcm technology to IDDQ currents of between 100 and 10,000 xcexcA of integrated circuits containing 100,000-10 million logic gates in 0.5-0.2 xcexcm technology.
It is known that the contribution of the sub-threshold currents to the IDDQ current increases in proportion to the number of transistors. On the other hand, the threshold current Ith must be established so as to permit identification of a faulty device. In other words, it must be equal to the sum of the IDDQ current measured for a non-faulty device and of a current below the If current due to the presence of even just one electrical defect such as a short-circuit or a floating node in the integrated circuit. As this If current depends basically on the complexity of the integrated circuit, the difference between the IDDQ current measured for a non-faulty device and the Ith current is percentagewise lower the higher the number of transistors of the integrated circuit. For example, if the IDDQ current for a device without electrical defects is 10 xcexcA and if the If current due to a defect is at least 50 xcexcA, the threshold current Ith can be set to 60 xcexcA, i.e. six times the IDDQ of a non-faulty device. If, on the other hand, the IDDQ of a non-faulty device is 1 mA, the threshold voltage Ith must be set to 1.05 mA, i.e. to a value that differs from the IDDQ of a non-faulty device only for a fraction of this ({fraction (1/20)}th in this example) to avoid the risk of accepting devices with even only one defect that contributes with 50 xcexcA to the measurement of the IDDQ. In conclusion, in the first case, the difference between IDDQ and Ith is 50 xcexcA which is 500% of the IDDQ current to be compared and, in the second case, the difference is still 50 xcexcA, which is however only 5% of the IDDQ current to be compared. Therefore, to ensure that the measurements are reliable also for devices with high integration density, ever more sensitive and therefore complex comparators and increasingly critical measurement procedures must be used.
The inevitable differences between different samples of the same device belonging to different manufacturing lots due to variations in the manufacturing parameters represent a further complication.
In particular, the sub-threshold currents of the MOS transistors which, as already mentioned, represent the highest contribution to the IDDQ current, vary considerably in devices of different lots and also in devices belonging to wafers of the same lot. For example, the IDDQ current measurement in non-faulty devices (which will be indicated below as IDDQN) belonging to different lots may be between 5 and 35 xcexcA. When the minimum current increase xcex94If due to a defect is within the variability range of the IDDQN current, it is difficult to establish a threshold value Ith that allows the comparator to distinguish between acceptable and non-acceptable devices.
In the example given above, the variability range is 30 xcexcA. If a defect involves an increase xcex94If, for example, of 20 xcexcA, it is impossible to establish a threshold value Ith that makes it possible to reject all the devices with this defect only. The devices with IDDQN=5 xcexcA, may include one that, with a defect xcex94If=20 xcexcA, returns an IDDQ measurement of IDDQ=30 xcexcA, so that a threshold Ith even only slightly above the maximum limit of IDDQN current for non-faulty devices (35 xcexcA), would not permit identification of the faulty device.
An object of this invention is to establish a high component density CMOS integrated circuit test method that improves discrimination between non-faulty devices and faulty devices and thus guarantees higher production throughput.
This and other objects are provided by a method fo testing a CMOS integrated circuit including establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents. Also, the method includes calculating the sub-threshold currents by channel unit of area of the transistors of the integrated circuit using the sub-threshold currents measured and the channel areas of the measurement transistors, obtaining the sum of the channel areas of the transistors that are cut off when the integrated circuit is idle in static conditions, and calculating the current absorbed by the integrated circuit when idle in static conditions using the result of the two operations described above and adding a pre-established current increase to the current absorbed to obtain the threshold value.
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