Integrated circuit fabrication techniques vary greatly depending on the specific chip structure being made, the exact processes being used, and/or the available equipment. However, almost all fabrication methods include a lithography process during which certain portions of a wafer (i.e., a silicon slice coated with a photoresist material) are exposed to radiation to delineate a latent image corresponding to the desired circuit pattern. Specifically, radiation is passed through a reticle having clear portions and opaque portions corresponding to the desired pattern and the radiation passing through the reticle's clear portions passes to the wafer. If reduction optics are employed, the imaging portions of the reticle reflect an enlarged version of the desired pattern, such as four times (4.times.) the desired pattern, onto an exposure site on the wafer.
A lithography process may be performed by one of several available lithography systems. Of particular relevance to the present invention is a scanning lithography system, such as a step-and-scan lithography system. A scanning lithography system typically includes an illumination source and a projection assembly. The illumination source provides a narrow slit of light corresponding to that section of the light beam having minimal aberrations. In a reflective scanning system, the slit of light is in the form of a narrow ring concentric with the optical axis of the system's reflecting mirrors. In a purely refractive scanning system, the slit of light is the form a linear band. In a catadioptric scanning system, the slit of light may be in the form of either a ring or a band.
The slit of light illuminates a certain slit-shaped region of the reticle. Radiation passing through the clear portions of the reticle are projected by the projection assembly onto the wafer to delineate a slit-shaped region of the wafer. If reduction optics are employed, the projection assembly includes a reduction lens and the slit-shaped region of the wafer is a demagnified version of the reticle region. For example, if the projection assembly introduces a 4:1 demagnification factor, the reticle region will be four times larger than the wafer region.
The illumination slit extends entirely across the imaging surface of the reticle in one direction and is scanned across the imaging surface of the wafer in a transverse direction. For the purposes of the present discussion, the direction the slit extends will be called the "slit direction" and the direction of scanning will be called the "scan direction."
Scanning is accomplished by relative movement between the optical elements (i.e., the illumination source and the projection assembly) and the imaging elements (i.e., the wafer and the reticle). For example, the illumination source and the projection assembly may remain stationary and the wafer and the reticle may be moved relative thereto. To this end, the lithography system could include stages that support the wafer and the reticle, respectively, and a scanning assembly which moves the stages in the scan direction. If the system employs reduction optics, the wafer must move at a slower rate than the reticle. Thus, if the projection assembly introduces a 4:1 demagnification factor, the scanning assembly must move the reticle stage four times faster than the wafer stage.
A lithography system must have the consistent ability to print features having a certain minimum size. This feature size is measured in terms of "linewidth." Typically, during the set-up of the lithography system, an actual linewidth is measured and compared to a target value to obtain an error factor. If the error factor is within an acceptable tolerance, the lithography process may proceed. If the error factor is too great, adjustments are made to the lithography components to obtain acceptable linewidth tolerances before proceeding with the lithography process.
In a reduction scanning lithography system, linewidth errors may be caused by optical aberrations and/or other non-optical factors. As such, the absolute value of a linewidth error itself does not provide any insight as to whether the errors are caused by the system's optical components, its scanning components, or both. While adjustments may be made to, for example, the system's scanning assembly, to reduce linewidth errors to an acceptable tolerance, these adjustments will not cure the contribution of the error caused by optical aberrations.
Accordingly, the inventor appreciated that a need remains for a method of characterizing the contributions to linewidth errors.
USPTO Backgrounds
USPTO Backgrounds