This invention relates generally to the field of semiconductor devices and more specifically to a method for constructing a metal oxide semiconductor field effect transistor.
Metal oxide semiconductor field effect transistors (MOSFETs) often experience parasitic capacitance that may degrade the performance of the transistor. The source and drain of a transistor are typically adjacent to the transistor substrate. The interface between the source and drain regions and the substrate, however, often form depletion zones that result in parasitic capacitance. Known methods of reducing this form of parasitic capacitance call for using an implantation process to widen the transistor channel or for reducing the size of the source and/or drain regions. These known methods, however, do not satisfactorily reduce parasitic capacitance.
While known approaches have provided improvements over prior approaches, the challenges in the field of semiconductor devices have continued to increase with demands for more and better techniques having greater effectiveness. Therefore, a need has arisen for a new method for constructing a metal oxide semiconductor field effect transistor.
In accordance with the present invention, a method for constructing a metal oxide semiconductor field effect transistor is provided that substantially eliminates or reduces the disadvantages and problems associated with previously developed methods.
According to one embodiment of the present invention, a semiconductor device and a method for constructing a semiconductor device are disclosed. A trench isolation structure and an active region are formed proximate an outer surface of a semiconductor layer. An epitaxial layer is deposited outwardly from the trench isolation structure. A first insulator layer is grown outwardly from the epitaxial layer. A second insulator layer is grown outwardly from the first insulator layer. A gate stack is formed outwardly from the epitaxial layer. The gate stack comprises a portion of the first insulator layer, a portion of the second insulator layer, and a gate formed proximate the second insulator layer, where the gate has a narrow region and a wide region. The epitaxial layer is heated to a temperature sufficient to allow for the epitaxial layer to form a source/drain implant region in the active region.
Embodiments of the invention may provide numerous technical advantages. A technical advantage of one embodiment is that trench isolation regions comprising an insulative material isolate epitaxial source/drain regions of a transistor from the substrate of the transistor. This configuration reduces parasitic capacitance from the epitaxial source/drain regions to the substrate, thus improving the performance of the transistor. A technical advantage of another embodiment is that the trench isolation regions may prevent cosmic or ionizing high energy particles from penetrating the source/drain active regions to the substrate, thus making the semiconductor device less susceptible to single event upsets.
A technical advantage of another embodiment is that formation of source/drain implant regions may be performed at the same time as the formation of the transistor gate. A technical advantage of another embodiment is that a gate stack has a first insulator layer comprising silicon dioxide and a second insulator layer comprising silicon nitride, which allows for controlled formation of a gate region for the transistor gate. A technical advantage of another embodiment is that a gate has a wide region and a narrow region. The narrow region may provide for a better channel between epitaxial source/drain regions, whereas the wide region may reduce the resistance of the gate.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
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