1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and process of manufacturing the same, and more particularly to a structure of a device isolation insulator film for defining device formation regions.
2. Description of the Related Art
An electrically erasable programmable non-volatile semiconductor memory device (EEPROM) of the so-called floating gate type causes a problem associated with an increase in capacitive coupling between floating gates. For the purpose of solution of this problem, a known technology is employed to etch a device-isolation insulator film formed between the floating gates to form a recess therein so that a control gate can be buried deeply in between the floating gates. Such the technology is disclosed, for example, in JP-A 2001-168306 (paragraphs from [0032] through [0041] and FIG. 17).
This technology is described with reference to FIG. 30, in which a semiconductor substrate 11 has a plurality of device formation regions 12. Adjacent device formation regions 12 are defined by a device isolation trench 13. Buried in the device isolation trench 13 is a device-isolation insulator film 14 for electrically isolating memory cells from each other, which are formed in the device formation regions 12. On the device formation region 12, in turn from below, a lower gate insulator film (tunnel insulator film) 21, a floating gate 22, a second gate insulator film (ONO film) 23, and a control gate 26 composed of a polysilicon film 26a and a tungsten suicide film (WSi film) 26b are formed to configure a single memory cell. At the center of the device-isolation insulator film 14, a recess 14v is formed by etching to fill the control gate 26 also in the recess 14v. Thus, capacitive coupling between the floating gates 22 can be reduced.
The technology disclosed in JP-A 2001-168306 requires etching of the device-isolation insulator film 14 with a spacer mask formed on the sidewall of the floating gate 22 to form the recess 14v in the device-isolation insulator film 14. Accordingly, there is a problem because process steps are increased by the step of forming the spacer mask. In particular, with the progress of fine patterning, the device-isolation insulator film 14 may have a narrow width. In such the case, there is another problem because the control gate 26 is hardly buried in the recess 14v and the capacitive coupling between the floating gates 22 cannot be reduced easily.
USPTO Backgrounds
USPTO Backgrounds