Timely and accurate identification of root causes for a faulty chip is important in yield improvement, debug of new device silicon, and failure analysis of customer returns. Traditional failure analysis of faulty chips comprises two processes, electrical failure analysis and physical failure analysis. Electrical failure analysis localizes and examines the faulty electrical behavior by varying test conditions such as supply voltage, frequency, temperature etc. Physical failure analysis acquires physical defect images and/or measures physical dimensions such as gate lengths, metal pitches, etc through instruments such as a Transmission Electronic Microscope (TEM) and a Scanning Electronic Microscope (SEM). As silicon technology advances the silicon dimension becomes smaller and smaller resulting in more difficult defect searching during physical failure analysis. Small defects that previously were not harmful to device operations become deadly defects. Searching such smaller defects in physical failure analysis requires the electrical failure analysis provide better fault diagnostic resolution.
The present invention comprises a method for performing failure diagnostics of a circuit which overcomes the foregoing difficulties which have long since characterized the prior art. In accordance with the broader aspects of the invention a method for testing VLSI circuits comprises a two-pass diagnostic method for testing a VLSI circuit wherein a first pass comprises a conventional test flow in which an ATPG tool generates a set or test patterns and identifies possible faulty nets within the circuit and a second pass comprises extracting one or more critical subsets from the original circuit utilizing an extraction algorithm in order to obtain more accurate failure diagnosis than has been previously available using other testing methods known in the art.
In accordance with more specific aspects of the invention, an Automatic Test Pattern Generation (ATPG) tool first generates test patterns for an original circuit. The original circuit is tested according to the generated test patterns and output data is collected. Once the output data is collected fault diagnosis is performed by using fault diagnosis capability of an ATPG tool. The fault diagnosis generates a list of likely faulty nets. The likely faulty nets are then used as the interested nets for extraction of the critical circuit subset. Once the critical circuit subset is extracted, the ATPG tool can generate more thorough test patterns on the much smaller extracted subset. The test patterns are mapped back to the original circuit for testing by the ATPG. Output data from the ATPG test can be collected and a more accurate fault diagnosis can be performed. If the fault diagnostic resolution is not satisfied, the process can be repeated until the desired resolution is reached. The likely faulty nets generated in previous runs can be used as the interested nets for the circuit subset extraction in subsequent runs.
The extracted critical subset contains all nets of interest which include all possible faulty nets. The subset maintains accessibility to the interested nets thereby maintaining the capability of asserting and observing the logic states of the interested nets. The critical subset significantly reduces the circuit size comparing to the original circuit. There are several advantages to working on a smaller circuit subset than on the original circuit. First, the ATPG tool generates test patterns for a small circuit much faster than for a larger circuit. Second, the test patterns for the small circuit can be much more thorough thereby improving the fault coverage and the fault diagnostic resolution. Finally, the test time is much faster relative to a test time for a larger circuit, enabling re-testing of the critical subset as needed to vary parameters such as supply voltages, frequency, temperature, etc.
The extraction algorithm comprises an extensive set of rules by which unnecessary circuit elements can be systematically eliminated from the “subset” circuit. For each possible input and output of a likely faulty net the algorithm selects an optimal path within a critical “subset circuit” of the circuit and passivates all other possible paths such that the inputs and outputs of the pacified paths are insensitive to inputs. As used herein the term “passivate” means to make a component neutral to inputs or outputs and to neighboring components. If any path cannot be passivated then that path is also included in the subset circuit for testing. The subset circuit focuses on specific local areas where the most probable faults lie. The subset includes all faulty candidate nets and all possible surrounding circuitry traced up to primary inputs (PI), primary outputs (PO), & scan cells. The subset therefore significantly reduces size of circuit to be scanned. The subset circuit is extracted from the original circuit, so no changes are required to existing ATPG tools or diagnosis flows.
USPTO Backgrounds
USPTO Backgrounds