This invention relates to a technology for evaluating the quality of test sequences, which represents the performance in testing faults, for semiconductor integrated circuits. The technology is used in testing delay faults on the semiconductor integrated circuits.
A recent fast-paced advancement in a miniaturization technology for semiconductor process is rapidly leading to the semiconductor integrated circuits in a larger size and more complex configuration, which is making it even more difficult for the semiconductor integrated circuits to be tested. In order to deal with the problem, the design for testability method, such as scan testing, has been in use as a measure to facilitate the tests for the semiconductor integrated circuits. Faults presented in a stuck-at fault model can be now efficiently tested. When the faults according to the stuck-at fault model are detected, the performance of the detection does not depend on a clock frequency. Therefore, the scan test is generally implemented with a slower clock frequency than an actual operation speed.
As a result of more and more apparent variability in the semiconductor process along with the advancing miniaturization thereof, however, it is becoming too difficult for the use of the lower clock frequency to guarantee an expected quality of the tests. There is now a call for a delay fault test such as a technology to enable a test using a clock frequency same as in the actual operation.
A fault coverage representing the quality of the delay fault test sequences is calculated according to the following formula.
                              Formula          ⁢                                          ⁢          1                ⁢                                  ⁢                              fault            ⁢                                                  ⁢            coverage                    =                                                    number                ⁢                                                                  ⁢                of                ⁢                                                                  ⁢                detected                ⁢                                                                  ⁢                faults                                            number                ⁢                                                                  ⁢                of                ⁢                                                                  ⁢                all                ⁢                                                                  ⁢                defined                ⁢                                                                  ⁢                faults                                      ×            100            ⁢            %                                      1      
In the fault coverage 1, an equal importance is placed on all the delay faults, which arises a problem that the fault coverage does not quite reflect the quality of the test sequences in real fault detection. The problem is described below referring to the drawing.
FIG. 14 illustrates the characteristics of delay faults defined on a semiconductor integrated circuit. The lengths of respective arrows extending from signal paths b1-b6 denote “design delay values on the respective signal paths”. A “design delay value” means a delay value when the semiconductor integrated circuit is designed. The vertical dotted line on the right side of FIG. 14 denotes a value of one clock rate on the semiconductor integrated circuit. In general, the larger the “design delay value on the signal path” is (the closer to one clock rate), the more likely the signal path induces a delay fault. From this aspect, it is obvious that, in FIG. 14, the signal path b3 is more likely than b6 to induce a delay fault. Therefore, it can be said that a test for detecting the delay fault defined on the signal path b3 has a higher quality than a test for detecting the delay fault defined on the signal path b6.
According to the fault coverage obtained by the formula 1, it is interpreted that the delay fault detections for the signal path b3 and signal path b6 are equivalent in that a delay fault is found therein and therefore share the same quality. For example, assuming that a delay fault is defined on each of the signal paths b1-b6, the fault coverage in the case of detecting the delay faults on the signal paths b1-b3 having more likelihood of failure is:( 3/6)×100(%)=50%
The fault coverage, on the other hand, in the case of detecting the delay faults on the signal paths b4-b6 having less likelihood of failure is also:( 3/6)×100(%)=50%
The signal paths b1-b3 and b4-b6 are different in likelihood of actual failure, however share the same fault coverage.
Having the fault detection tests for the signal paths b1-b3 having the larger delay values and for the signal paths b4-b6 having the smaller delay values compared to each other, the former obviously has a higher quality. Thus, the formula 1 to provide the fault coverage does not correctly reflect the test quality. As a result, the test sequences used for fault detection are wrongly evaluated.
USPTO Backgrounds
USPTO Backgrounds