Turbo-code is employed as one of the encoding schemes for the next-generation mobile communication systems and widely applied in communication field, as it has a decoding capability close to Shannon limit by using an iterative decoding method.
For example, a rate 1/3 Turbo-code is taken as a channel encoding scheme in the physical layer of the LTE (Long Term Evolution) standard. The Turbo-code employs two component encoders, input with a code block S appended with a checksum of CRC (Cyclic Redundancy Check), at a sending terminal. For the first component encoder, the input may be the code block S in the original order and the output may be a check sequence P0. For the second component encoder, the input may be the code block S interleaved by QPP (Quadratic Permutation Polynomial) and the output may be a check sequence P1. The sequences S, P0 and P1 may be sent to a transmission channel after rate matching and modulation.
At a receiving terminal, Turbo-code may be decoded by employing iterative decoding. FIG. 1 schematically illustrates a decoding process of Turbo decoder. As shown in FIG. 1, the input of a component decoder 1 may be soft-information corresponding to S and P0, and extrinsic information output from a component decoder 2, where the extrinsic information is de-interleaved before sending to the component decoder 1. The output of the component decoder 1 may be extrinsic information to be sent to the component decoder 2 and decoded bits. Similarly, the input of the component decoder 2 may be soft-information corresponding to P1 and interleaved S, and extrinsic information output from the component decoder 1, where the extrinsic information is interleaved before sending to the component decoder 2. The output of the component decoder 2 may be extrinsic information to be sent to the component decoder 1 and decoded bits. The two component decoders may perform alternate and iterative decoding by interchanging extrinsic information, thereby improving the reliability of the decoded bits constantly. In the LTE standard, as each Turbo-code block has a checksum of CRC, CRC check may be performed on decoded bits output from each component decoder. If passing the CRC check, the Turbo-code decoding may be terminated in advance to save power consumption. Since the output of the component decoder 2 includes an interleaved sequence, de-interleaving need to be performed on the interleaved sequence before CRC check. During the decoding process, the two component decoders may not operate at the same time and computations thereof may be basically the same. Therefore, only one component decoder may be employed in practical hardware implementation to save chip area.
Since a conflict free QPP interleaver is employed in the LTE standard, a Turbo-code block may be divided into multiple data sections and each section may be decoded independently. Thus, multiple sections may be decoded in parallel, thereby improving throughput of the Turbo decoder.
FIG. 2 schematically illustrates a conventional Turbo decoder structure and FIG. 3 schematically illustrates a flow chart of a conventional method for decoding. Referring to FIG. 2 and FIG. 3, a Turbo-code block may be divided into K sections. K independent decoders may be employed to perform decoding in parallel, where the number K is generally called decoding parallelism. The K independent decoders read data from a memory array through a switching network, where the memory array includes K memory banks in which K sections are stored separately. The component decoders 1 and 2 may perform decoding alternately and iteratively. During the stage of outputting decoded bits of the component decoder 1, 2-bit data may be output from each of the K independent decoders in every clock cycle, so totally 2K-bit data for the K independent decoders. The 2K-bit data belongs to different K sections of the code block prior to being interleaved, so they need to be written to a sorting memory, in order to recover the code block's original order. Then the recovered data are read out from the sorting memory for CRC check. Similarly, during the stage of outputting decoded bits of the component decoder 2, 2-bit data may be output from each of the K independent decoders in every clock cycle, so totally 2K-bit data for the K independent decoders. The 2K-bit data belongs to different K sections of the interleaved code block, so they need to be de-interleaved and then written to a sorting memory, in order to recover the code block's original order. Then the recovered data are read out from the sorting memory for CRC check. If the decoded bits of the component decoder 1 or the component decoder 2 pass the CRC check or the number of iteration times reaches a maximum value, the decoding process may be terminated.
In conventional LTE Turbo decoders, the CRC check is performed on the data read from the sorting memory after component decoding, which may result in additional access to the sorting memory and extra decoding computations, which thereby decreases the throughput of the decoder and increases the hardware power consumption.
USPTO Backgrounds
USPTO Backgrounds