1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
A DRAM whose memory cell includes one transistor (cell transistor) and one capacitor can be highly integrated, has no limit on the number of times of writing in principle, and can perform writing and reading at relatively high speed; thus, such a DRAM is used in many kinds of electronic appliances. Various efforts have been made to further increase the degree of integration of a DRAM (see Patent Document 1).
A DRAM stores data by accumulating electric charge in a capacitor of each memory cell, and reads the data by releasing the electric charge to a bit line.
The amount of change in the potential of the bit line due to the release of the electric charge is determined by the ratio between the capacitance of the capacitor and the parasitic capacitance of the bit line. The parasitic capacitance of the bit line is substantially proportional to the length of the bit line. Accordingly, the capacitance of the capacitor should be constant when the length of the bit line is not changed. In a DRAM widely used at present, a capacitor is required to have a capacitance of about 30 fF.
Although the size of a memory cell tends to be reduced as miniaturization proceeds, while an area in which a capacitor is formed is reduced, the capacitor has been required to have the same capacitance as a conventional capacitor because the capacitance of the capacitor needs to be kept at a certain value or more as described above.
At present, a capacitor is formed to have a trench structure in which a deep hole is formed in a silicon wafer or a stack structure in which a chimney-like projection is provided (see Non Patent Documents 1 and 2). Both the hole and the projection are required to have an aspect ratio of 50 or more. That is, an extremely long and narrow structure body whose depth or height is 2 μm or more needs to be formed in a limited area, which is difficult to realize with high yield.
In order to overcome such a difficulty, a method is disclosed in which sub bit lines branched from a bit line are provided and a sense amplifier of a flip-flop circuit type is connected to each of the sub bit lines so that the capacitance of a capacitor is reduced (see Patent Document 2).
However, in a DRAM having a conventional structure, a bit line and a sub bit line are required to overlap with each other over a word line. When a stacked capacitor is employed, thus many structure bodies are provided over a word line, which results in difficulty in circuit design and manufacture.
It is also a problem that when the capacitance of a capacitor is reduced, an interval between refresh operations is correspondingly shortened. For example, when the capacitance is reduced to one tenth, the time during which electric charge is held in the capacitor also becomes one tenth, assuming that the off resistance of a cell transistor is constant; thus, refresh operation needs to be performed at an interval of one tenth as compared with using a conventional capacitor (i.e., at a frequency ten times as high as). Although many proposals related to a divided bit line structure have been made, including Patent Document 2, there seems to be no example which bring a breakthrough in this respect.
USPTO Backgrounds
USPTO Backgrounds