Cache memory systems may be used to generally improve memory access speeds in computer or other electronic systems. Increasing cache size and speed may tend to improve system performance. However, increased cache size and speed may be costly and/or limited by advancements in cache size and speed. Additionally, there may be a desire to balance overall system performance gains with overall system costs.
Different types of mapping methods may be used in a cache memory system, such as direct mapping, fully associative mapping, and set-associative mapping. For a set-associative mapping system, the cache memory is divided into a number of “sets” where each set contains number of “ways” or cache lines. Within each set, searching for an address is fully associative. There may be n locations or ways in each set. For example, in a 4-way, set-associative cache memory, an address at the data source may be mapped to any one of 4 ways 0, 1, 2, or 3 of a given set, depending on availability. For an 8-way set-associative cache memory, the address at the data source may be mapped to one of 8 ways or locations within a given set.
Memory management is crucial to graphics processing and manipulating the large amounts of data encountered therewith. As processing requirements increase for graphics, including 3-D (three dimensional) texturing, various aspects of memory allocation and mapping have been considered for improvement to increase graphics processing. In some instances, a memory for graphics data may be organized in tiles. Tile organized memory may allow faster access of graphics data as compared to linearly organized memory.
In some instances, the systems and methods for tile organized memory mapping may be directed to optimizing processing of “y-major” or “tiled-Y” read request operations. In a tiled-Y tiling scheme, two contiguous data structures in the Y-direction are consecutive in memory. Also, Y-major tiling may be an efficient method of organizing memory for graphics texture applications. Some graphics engines and graphics systems load texture data from a processor into cache memory in the Y-direction. Accordingly, a graphics engine or system may be configured or optimized to read graphics data (e.g., texture data) in the Y-direction. Such optimization may allow be tiled-Y read requests to be processed in one clock cycle. However, optimization for one type of operation may have undesired results regarding other operations.
USPTO Backgrounds
USPTO Backgrounds