1. Field
Exemplary embodiments of the present invention relate to an image sensor (IS), and more particularly, to a successive approximation analog-to-digital converting apparatus having a high definition property while occupying a small area, an operating method thereof, and a Complementary Metal-Oxide Semiconductor (CMOS) image sensor including the same.
2. Description of the Related Art
A conventional single-slop analog-to-digital convertor (ADC) has low definition properties and long analog-to-digital conversion time when used in a Complementary Metal-Oxide Semiconductor (CMOS) image sensor of a column parallel readout scheme Therefore, a Successive Approximation Register (SAR) analog-to-digital converting apparatus is being researched and developed.
The SAR analog-to-digital converting apparatus has a simple circuit configuration including a capacitor digital-to-analog converter (DAC), a comparator, and an SAR logic unit, and thus it consumes less power. The SAR logic unit may include a Successive Approximation Register (SAM.
In the SA analog-to-digital converting apparatus, however, the area of the capacitor DAC is doubled, as the number of bits to be converted is increased by one bit. To reduce the area of the capacitor DAC when the high-definition SAR analog-to-digital converting apparatus is designed, a method of controlling the level of a reference voltage is suggested.
In the method of controlling the level of the reference voltage, a high level of accuracy for the reference voltage is required to protect an output signal of the SAR analog-to-digital converting apparatus from a nonlinear error.
USPTO Backgrounds
USPTO Backgrounds