1. Field of the Invention
The present invention relates to a burn-in test circuit for screening a chip having a potential defect leading to an initial defect, by applying a voltage higher than that in a normal operation mode to a memory cell in a semiconductor memory circuit, especially, a DRAM chip.
2. Description of the Prior Art
FIG. 4 shows a configuration of a conventional semiconductor memory circuit. The conventional semiconductor memory circuit includes a memory cell array having a plurality of memory cells MC arranged in a matrix. Bit line pair BL1 and /BL1 and bit line pair BL2 and /BL2 are provided in rows of the matrix, while a plurality of word lines WL are provided in columns of the matrix. The memory cells MC are disposed at points of intersection of the bit lines and the word line WL. Each of the memory cells MC is a DRAM memory cell including one transistor and one capacitor.
A sense amplifier circuit 2 including a plurality of sense amplifiers SA is provided at each of opposite sides of the memory cell array 1. The sense amplifiers SA disposed at the right side of the memory cell array 1 are connected to the bit line pair BL1 and /BL1 so as to amplify a minute potential difference between the bit line pair BL1 and /BL1, while the sense amplifiers SA disposed at the left side of the memory cell array 1 are connected to the bit line pair BL2 and /BL2 so as to amplify a minute potential difference between the bit line pair BL2 and /BL2.
As described in, for example, Japanese Patent Laid-Open Publication No. 10-340598 (1998), the memory cell array 1 of the conventional semiconductor memory circuit in FIG. 4 has a so-called quarter pitch cell arrangement in which the bit line pair BL1 and /BL1 and the bit line pair BL2 and /BL2 are combined with each other telescopically in a direction of the word lines WL such that a plurality of sets each having the bit lines BL1, BL2, /BL1 and /BL2 arranged sequentially are repeated.
A bit line equalizing circuit BLEQ and a bit line and sense amplifier interconnecting circuit BLI are provided between the sense amplifier circuit 2 and the memory cell array 1. The bit line equalizing circuit BLEQ functions to set the bit line pair to an identical potential during standby. In FIG. 4, two potentials VBL1 and VBL2 are provided as described in, for example, Japanese Patent Laid-Open Publication No. 2001-243794 (2001).
In a normal operation mode, the potentials VBL1 and VBL2 are set to be equal to each other. Each sense amplifier circuit 2 is shared by a pair of the bit line and sense amplifier interconnecting circuits BLI provided on its both sides and this is referred to as a xe2x80x9cshared sense amplifier configurationxe2x80x9d. At the time of activation of the word lines WL, the bit line and sense amplifier interconnecting circuit BLI is used for isolating one of the opposite bit line pairs of the respective sense amplifier circuits 2 from the corresponding sense amplifier circuit 2 so as to reduce stray capacity of the bit lines.
In order to secure reliability of the memory cells, a burn-in test in which a chip having a potential defect leading to an initial defect is screened by applying a voltage higher than that in the normal operation mode to the memory cells is performed prior to the shipment. The chip found to be defective by the burn-in test is replaced by an accepted chip and is discarded as a defective product so as to be rejected before the shipment. Rate for detecting the potential defect by the burn-in test is referred to as xe2x80x9cburn-in accelerationxe2x80x9d. The burn-in acceleration depends on a voltage applied in the burn-in test. Naturally, as the burn-in voltage is higher, the burn-in acceleration is higher. Meanwhile, as the burn-in period is longer, detection of the potential defect progresses further. Therefore, in order to heighten the burn-in effect, it is desirable that the burn-in test is performed at as high a voltage as possible for as long a time as possible. However, if the burn-in period is long, productivity deteriorates, so that the burn-in test is economically performed at such a high voltage as not to bring about breakdown of a transistor or the like.
The bit line equalizing circuits BLEQ are employed for applying a voltage stress among the neighboring bit lines BL1, BL2, /BL1 and /BL2 in the memory cell array 1 in the quarter pitch cell arrangement of FIG. 4 so as to perform the burn-in test. Namely, if the potentials VBL1 and VBL2 are, respectively, set to high level and low level by setting a signal of the bit line equalizing Circuits BLEQ to high level, the bit line pair BL1 and /BL1 are set to high level. On the other hand, since the bit line pair BL2 and /BL2 are set to low level, the voltage stress can be applied among the neighboring bit lines BL1, BL2, /BL1 and /BL2.
On the contrary, if the potentials VBL1 and VBL2 are, respectively, set to low level and high level, the bit line pair BL1 and /BL1 are set to low level and the bit line pair BL2 and /BL2 are set to high level. Therefore, by setting to different values the potentials VBL1 and VBL2 equal to each other in the normal operation mode, the voltage stress can be applied among the neighboring bit lines BL1, BL2, /BL1 and /BL2.
FIG. 5 shows a configuration of another known semiconductor memory circuit. As described in, for example, Japanese Patent Laid-Open Publication No. 10-340598 (1998) referred to above, the memory cell array 1 of FIG. 5 has a so-called half pitch cell arrangement in which the bit line pair BL1 and /BL1 and the bit line pair BL2 and /BL2 are provided alternately in the direction of the word lines WL such that a plurality of sets each having the bit lines BL1, /BL1, BL2 and /BL2 arranged sequentially are repeated. A decision as to which one of the memory cell array 1 of the quarter pitch cell arrangement in FIG. 4 and the memory cell array 1 of the half pitch cell arrangement in FIG. 5 should be selected is made based on various factors, mainly, feasibility of microfabrication of the memory cells and feasibility for optimizing current driving force of a transistor in the memory cell.
Also in the known semiconductor memory circuit of FIG. 5, a voltage stress can be applied among the neighboring bit lines by using the bit line equalizing circuits BLEQ in the same manner as the conventional semiconductor memory circuit of FIG. 4. Namely, if the potentials VBL1 and VBL2 are, respectively, set to high level and low level by setting a signal of the bit line equalizing circuits BLEQ to high level, the bit line pair BL1 and /BL1 are set to high level and the bit line pair BL2 and /BL2 are set to low level. Therefore, the voltage stress can be applied between the bit lines /BL1 and BL2 and between the bit lines /BL2 and BL1.
On the contrary, if the potentials VBL1 and VBL2 are, respectively, set to low level and high level, the bit line pair BL1 and /BL1 are set to low level and the bit line pair BL2 and /BL2 are set to high level. Therefore, the voltage stress can be applied between the bit lines /BL1 and BL2 and between the bit lines /BL2 and BL1. In the example shown in FIG. 5, the voltage stress cannot be applied between the neighboring bit lines BL1 and /BL1 and between the neighboring bit lines BL2 and /BL2. Hence, also in the memory cell array 1 of the half pitch cell arrangement in FIG. 5, it is necessary to apply the voltage stress between the neighboring bit lines BL1 and /BL1 and between the neighboring bit lines BL2 and /BL2. To this end, the sense amplifier SA should be activated at a potential corresponding to the voltage stress to be applied. FIG. 6 is a circuit diagram of the sense amplifier SA. By setting sense amplifier activating signals SAP and SAN to low level and high level, respectively, the bit line pair BL and /BL are, respectively, set to high level and low level or low level and high level, so that the voltage stress can be applied between the bit line pair BL and /BL. If a supply potential fed to the sense amplifier SA is raised as high as in the burn-in test, a potential between the bit line pair BL and /BL also increases, so that the burn-in test can be performed.
In recent years, operating voltages of DRAMs are on the downward trend. For example, a former standard synchronous DRAM (SDRAM) has an operating voltage of 3.3 V. However, a double data rate (DDR) type DRAM in current use predominantly has an operating voltage of 2.5 V. In addition, a double data rate-II (DDR-II) type DRAM considered to be used predominantly in future has an operating voltage of 1.8 V. A purpose for lowering the operating voltage of the DRAM year by year is to lower an operating current of the DRAM and to reduce electromagnetic noises in high-speed operation.
However, the DDR-II type DRAM has an operating frequency of not less than 400 MHz. Therefore, in case the DDR-II type DRAM is operated at such a high speed by a supply voltage of 1.8 V, it is essential to upgrade driving capability of transistors used in the circuit. Actually, in the DDR-II type DRAM, transistors having a dielectric film thinner than those of the memory cells are used for a control circuit or a data processing circuit in the chip so as to obtain a high driving force at the low voltage.
Thus, in the prior art semiconductor memory circuits, the transistors of the sense amplifier are formed by thin film transistors, while the transistors of the DDR-II type DRAM memory cells, the transistors of the bit line equalizing circuits and the bit line and sense amplifier interconnecting circuit are formed by thick film transistors, so that the thin film transistors and the thick film transistors are provided mixedly. In this case, when the burn-in test is performed by raising as high as in the burn-in test the supply potential fed to the sense amplifier SA of FIG. 6, a problem arises.
Namely, in the sense amplifier SA, a threshold voltage is set to be low so as to detect at a low voltage a minute potential difference between the bit line pair. However, in order to restrict cut-off leakage current to a small value at the low threshold voltage, the transistors of the sense amplifier SA are desirably formed by the thin film transistors. Thus, if the transistors of the sense amplifier SA are formed by the thin film transistors, breakdown of the sense amplifier SA happens when the voltage of the sense amplifier SA is raised. Therefore, it is impossible to raise the voltage of the sense amplifier SA.
For example, supposing that thickness of an oxide film of the thick film transistor is set to 6.5 nm, thickness of an oxide film of the thin film transistor is set to 3.5 nm and an electric field stress applied to the oxide film in the burn-in test is 8 MV/cm, a potential difference of 5.2 V can be applied to the thick film transistor but merely a potential difference of 2.8 V can be applied between the bit line pair connected to the sense amplifier, so that burn-in acceleration is low.
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art a semiconductor memory circuit which is capable of performing a burn-in test by applying a high potential difference between bit line pair even in case a thin film transistor is used for a sense amplifier.
In order to accomplish this object of the present invention, a semiconductor memory circuit having a normal operation mode and a burn-in test mode, according to the present invention includes a memory cell array which includes a plurality of memory cells arranged in a matrix, a plurality of bit lines provided in rows of the matrix and a plurality of word lines provided in columns of the matrix. First and second sense amplifier circuits are, respectively, provided at opposite sides of the memory cell array in a direction of the bit lines and include a plurality of first sense amplifiers each connected to first bit line pair in the bit lines and a plurality of second sense amplifiers each connected to second bit line pair in the bit lines, respectively. First and second bit line and sense amplifier interconnecting circuits couple the first and second bit line pairs to the first and second sense amplifier circuits, respectively. First and second bit line equalizing circuits set the first and second bit line pairs to first and second identical potentials, respectively during standby. A first short-circuiting transistor circuit couples first and second potentials to the first bit line pair, while a second short-circuiting transistor circuit couples third and fourth potentials to the second bit line pair. The first bit line and sense amplifier interconnecting circuit, the first bit line equalizing circuit and the first short-circuiting transistor circuit are provided between the memory cell array and the first sense amplifier circuit, while the second bit line and sense amplifier interconnecting circuit, the second bit line equalizing circuit and the second short-circuiting transistor circuit are provided between the memory cell array and the second sense amplifier circuit such that the first and second short-circuiting transistor circuits are, respectively, disposed more adjacent to the memory cell array than the first and second bit line and sense amplifier interconnecting circuits are. Each of the first and second sense amplifiers is formed by a first transistor having a first gate insulation film, while each of the first and second bit line and sense amplifier interconnecting circuits, the first and second bit line equalizing circuits and the first and second short-circuiting transistor circuits is formed by a second transistor having a second gate insulation film thicker than the first gate insulation film.
USPTO Backgrounds
USPTO Backgrounds