1. Technical Field
This invention relates to delayed-locked loops.
2. Description of the Related Art
Skew reduction techniques using a phase-locked loop (PLL) or delay-locked loop (DLL) have become increasingly important as the required system bandwidth increases. Especially, the DLL has become more popular as a zero delay buffer because of its better stability and better jitter characteristics than the PLL. However, the conventional DLL does not offer a frequency range as wide as the PLL does because of its inherent limitation on the frequency range and the problem of false locking. PLLs and DLLs are typically used in synchronous systems wherein the integrated circuits in the system are synchronized to a common reference clock.
In the phase-locked loop, a voltage-controlled oscillator produces a local clock. The phases of the local clock and a reference clock are compared by a phase-frequency detector, with the resulting error signal used to drive the voltage-controlled oscillator via a loop filter. The feedback via the loop filter phase locks the local clock to the reference clock. Stability of the feedback loop, however, depends in part on the loop filter. The electronic characteristics of the loop filter, in turn, often depend significantly on manufacturing parameters. As a result, the same loop filter design may result in a stable feedback loop when manufactured with one process but an unstable loop when manufactured by another. It is difficult to produce a single loop filter design for use with all manufacturing processes, and the design of the loop filter typically must be optimized on a process by process basis.
The delay-locked loop generates a synchronized local clock by delaying the incoming reference clock by an integer number of periods. This approach avoids the stability problem inherent in the phase-locked loop approach. Delay-locked loops, however, have a disadvantage of narrow frequency range. The delay-locked loop adjusts the amount of additional delay in order to achieve the desired synchronization, but this adjustment is essentially a phase adjustment. The conventional delay-locked loop lacks any significant frequency adjustment, thus limiting the overall frequency range of conventional delay-locked loops. Furthermore, delay-locked loops may falsely lock on a frequency.
Accordingly, it is desirable to achieve a delay-locked loop that can operate over a wide frequency range and which can provide protection against false locking.
USPTO Backgrounds
USPTO Backgrounds