Known methods enable multiple gate MOS devices to be manufactured. The gates of these devices may, for example, be produced by etching, such as a junction etching or an isotropic etching.
Concerns with multiple gate architecture include the difficulty of production due to their three dimensional architecture. However, the production of doubles gates by etching poses difficulties, especially with regard to the alignment and the dimensional control of the gates, and due to the fact that the etching applies to the mask used. Certain difficulties also appear due to the reduction in the technological dimensions produced.
Optical lithography is also widely used in the production of semiconductor devices. But this technique may not be used in the production of self-aligned double gate devices because it may not enable patterns in depth in a material to be produced.
Lithography by electron beam, known as “E-Beam” lithography, represents an interesting technological alternative. Indeed, it enables the formation of patterns in depth in a material thanks to the depth of penetration of the electrons projected during the lithography.
Patent FR-A-2 858 876 proposes a self-aligned device produced by E-Beam lithography, represented in FIG. 1. In this solution, a localised zone is reproduced from an E-Beam lithography with a high voltage in order to be able to dissipate the electrons in the lower layers. In FIG. 1, an MOS transistor 1 is produced by E-Beam lithography. This transistor 1 comprises a source zone 2 and a drain zone 3. These two zones 2 and 3 are linked by a conducting bridge 4. The transistor 1 also comprises a double gate 5, 6, surrounding the conducting bridge 4. The two gates 5, 6 are self-aligned. Indeed, the two gates 5, 6 are produced during a single lithography step, by a same beam of electrons. Nevertheless, this may not enable a dimensional control in 3 dimensions since the two gates have the same CD (Critical Dimension), in other words the same width.
Recent studies have shown by simulations that dissymmetric gates can increase the performance levels of a transistor. FIG. 2 represents two MOS architectures 7a, 7b each comprising a source zone 10a, 10b and a drain zone 11a, 11b linked by a conducting bridge 12a, 12b. Each architecture 7a, 7b comprises a self-centred double gate 8a, 9a and 8b, 9b. In the first architecture 7a, the lower gate 9a is wider than the upper gate 8a, these two gates being centred with the middle of the conducting bridge 12a. In the second architecture 7b, the widths of the gates 8b, 9b are identical to those of the gates 8a, 9a. In this second architecture 7b, the upper gate 8b is not centred with the middle of the conducting bridge 12b but is offset from the side of the drain 11b or source 10b zone, the gates 8b and 9b in this example being self-centred towards the drain 11b. Simulations have made it possible to show that such structures enable saturation current, transconductance and gate capacity values, greater than the values obtained with, for example, a device such a that described in patent FR-A-2 858 876, to be obtained.
Thus there is a need to propose a method of producing an asymmetric, 3D architecture, semiconductor device enabling the three dimensions of the exposed zones to be controlled, and especially to command independently the widths of the exposed zones in several levels of the device. Also, there is a need to propose a production method that is rapid and compatible with the production constraints, particularly of a symmetric and/or asymmetric self-aligned double gate semiconductor device.
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