1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly to a semiconductor apparatus with through vias.
2. Related Art
With increasing capacities and speeds of semiconductor memories used in various electronic systems, various attempts have been made to mount many semiconductor memories within a narrow area and drive efficiently the memory.
In order to highly integrate semiconductor memories, a three-dimensional (3D) layout, in which a plurality of memory chips is stacked, may be substituted for a two-dimensional (2D) layout.
A through via may be used in such a 3D layout structure. The through via has been adopted as an alternative for overcoming degradation of a transmission speed due to a distance to a controller on a module, poor data bandwidth, and degradation of a transmission speed due to variables in a package. In the through via, paths are formed to pass through a plurality of memory chips, and electrodes are formed in the paths so that respective memory chips and a controller can communicate with each other. In a stacked semiconductor memory apparatus to which the through via is applied, wires, sub packages and package balls, which are used in an SIP type and a POP type, are not needed, and electrodes are connected directly over a controller in such a way as to have paths passing through a plurality of memory chips. Bumps are formed between the paths passing through the plurality of memory chips, to electrically connect the plurality of memory chips with the controller.
Since a semiconductor memory apparatus is generally formed of silicon, the through via used in the semiconductor memory apparatus is also referred to as a through-silicon via (TSV).
FIG. 1 is a schematic cross-sectional view explaining processing errors that may occur when forming through vias in a semiconductor apparatus.
FIG. 1 shows a metal layer 10 for forming a through via, a dielectric layer 20 and a substrate 30.
While not shown in FIG. 1, connection layers (not shown) may be electrically connected to the upper and lower ends of the metal layer 10.
The connection layers are formed of a conductive substance for connecting the through via with another through via or a controller. In general, the connection layers are constituted by bumps.
(a) of FIG. 1 shows the case in which the through via is normally formed in a semiconductor chip.
Referring to (a) of FIG. 1, a path passing through the substrate 30 is formed, and the metal layer 10 formed of a metallic substance is normally formed in the path.
In the through via, in order to isolate the metal layer 10 and the wafer layer 30 from each other, the dielectric layer 20 such as an oxide is formed between the metal layer 10 and the substrate 30.
(b) and (c) of FIG. 1 show the cases in which the metal layer 10 is abnormally formed in the path surrounded by the dielectric layer 20.
If a variation occurs in process conditions while forming the through via, the metal layer 10 may be abnormally formed in the course of filling the path surrounded by the dielectric layer 20 with the metal layer 10.
If the metal layer 10 is formed with an open type gap as shown in (b) of FIG. 1, a current path is not created between an electrode e1 and an electrode e2. Therefore, the through via formed as in (b) of FIG. 1 cannot transfer a signal.
If the metal layer 10 is formed with a void type gap as shown in (c) of FIG. 1, although a current path is created between an electrode e3 and an electrode e4, the current path has a large resistance value due to the presence of the void type gap. Therefore, the through via formed as in (c) of FIG. 1 cannot stably transfer a signal.
If a subsequent process is continuously performed for a product in which the processing error is caused in the course of forming through vias in semiconductor chips, the manufacturing yield decreases, the productivity deteriorates, and additional costs are incurred.
USPTO Backgrounds
USPTO Backgrounds