In the integrated circuit (IC) manufacturing technology, a semiconductor device is typically formed by providing semiconductor, conductor and dielectric on a silicon wafer. Then, the deposited materials are patterned by etching to exhibit circuit features. After the materials are deposited and patterned by etching in sequence, the semiconductor device exhibits poor planarity on the surface thereof, which may cause problems during manufacturing processes, especially during the photolithography process. Therefore, surface planarization of a semiconductor device has become very important.
The chemical mechanical polishing (CMP) is the most widely used planarization technique. However, the CMP technique encounters many challenges. For example, CMP with different pattern densities may result in over-polishing to cause dishing in the trench in the low pattern density region. As a result, open circuits occur due to collapse or breaks in the metal interconnects.
To overcome the problems due to dishing caused by the CMP process, U.S. Pat. No. 6,372,605 provides a method using an additional oxide-reduction etching step performed prior to chemical-mechanical processing so as to reduce the polishing time to prevent dishing for shallow trench isolation processing.
In the present invention, a method for planarizing a semiconductor device is provided by depositing two semiconductor films with different CMP removal rates prior to the CMP process to improve the surface planarity of the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds