1. Technical Field
The present disclosure relates to a micro-electro-mechanical (MEMS) device with buried conductive regions and to the manufacturing process thereof.
2. Description of the Related Art
As is known, MEMS devices comprise a structural layer having regions that extend over a cavity or air gap and define suspended structures mobile in a direction parallel or transverse with respect to the top surface of a support, for example a substrate of semiconductor material, extending underneath the structural layer.
The suspended structures may be obtained with various machining techniques, such as surface micromachining, including defining the structures in the structural layer and removing a sacrificial layer formed on top of the substrate.
Frequently, the suspended structures, as other fixed structures facing the suspended structures, are anchored to the substrate via anchoring and support regions. These anchoring and support regions also enable electrical connection of the suspended or fixed structures to other parts of the device or to the outside world, for their electrical biasing and reading variable electrical quantities generated by the movement of the mobile structures.
In this case, the electrical-connection structures are formed by buried regions including conductive interconnection lines, which extend underneath the cavity, are supported by the substrate, and are typically electrically insulated from the latter by an insulating layer, when the substrate is of semiconductor material.
The conductive interconnection lines may be advantageously made of semiconductor material, typically doped polysilicon.
For example, a process used by the applicant for producing silicon inertial sensors and actuators includes providing buried interconnection lines of polycrystalline silicon (also referred to as polysilicon) arranged on a substrate, doped in situ, forming a sacrificial oxide layer, typically by plasma-enhanced chemical-vapor deposition (PECVD), and forming the structural layer by growth, using an epitaxial technique, of a thick polysilicon layer.
This technology enables forming suspended structures of a large thickness, which are able to move in a plane parallel to the surface of the substrate and/or in a direction transverse to the plane. The achievable large thickness enables extensive vertical surfaces to be obtained and thus high total capacitances, and high robustness, sensitivity and reliability.
In these types of devices, the final resistivity of the interconnections strictly depends upon the layout, the thickness, the process deposition parameters, and the sequence of the thermal-process steps and has a marked impact on the electrical behavior of the finished MEMS device in terms of signal-to-noise ratio.
In particular, to obtain a high signal-to-noise ratio, it is expedient to provide buried interconnection lines having a low resistance. To this end, it is known to dope the deposited polycrystalline material. For example, a thermal-doping step with POCl3 or an ion implantation may be carried out. In this way, resistivities on the order of 0.4-1.5 mΩ·cm are obtained. The ion-implantation technique is, however, relatively costly and does not enable sufficiently low resistivities to be achieved. The doping with POCl3, on the other hand, enables resistivities to be achieved that are lower as compared to the implantation technique but are still not sufficient. In addition, the technique is relatively far from uniform and less commonly used in processes on substrates with a diameter greater than 150 mm.
In order to obtain a high conductivity of the buried interconnection lines, it has also already been proposed to use a silicidation technique, including forming a metal silicon layer on top of the interconnection lines, a technique already known and applied in integrated circuits and in memory systems.
For example, Zhihong L. et al. “Study on the application of silicide in surface micromachining”, J. Micromech. Microeng. 12 (2002), pp. 162-167 describes a technique for forming silicidized interconnection lines in MEMS devices. In particular, this article describes a self-aligned technique, whereby a polysilicon layer is provided, is implanted and subjected to annealing, a metal layer, typically cobalt, is deposited, and the resulting wafer is subject to rapid thermal annealing (RTA) so that silicide forms where the polysilicon interconnection lines are present. The metal that has not reacted is removed via a hydrochloric acid solution, and the process proceeds with the steps for forming the fixed and mobile structures of the device.
The above known solution may, however, be improved since cobalt silicide does not have a sufficient resistance to the hydrofluoric acid used for releasing the mobile structures and degrades at the high temperatures that are typically utilized for the growth of the structural layer, thus nullifying the advantages that may be achieved. In addition, this solution cannot be integrated easily with current manufacturing processes.
USPTO Backgrounds
USPTO Backgrounds