The present invention relates to a computer with a cache function and to a cache memory control method.
In the field of computers, a cache function means a technique for storing data whose reading is requested by a processor (e.g. a CPU) of the computer, and data which is expected to be read next to the first-mentioned data, in a cache memory (which may consist of a SRAM expensive but capable of high speed operation) located near the CPU, and then reading target data first from the cache memory (if it is stored in the cache memory), not from its original memory area. This cache function can reduce the time required to read data and increase the total processing speed of the computer.
Since the memory capacity of the cache memory must be set much smaller than that of a main memory, an auxiliary storage device (e.g., a hard disk drive (HDD)), or a floppy disk drive (FDD), from which data is read, it is necessary to erase old data stored in the cache memory, in order to store new data read from such a storage device.
In the conventional cache memory control method, to erase data stored in the cache memory and store new data therein, the data to be erased is unconditionally erased.
It is evident that the higher the frequency of access for reading data, the greater the advantage of a high-speed operation realized by the cache memory, if the data is stored therein. Accordingly, the advantage of the cache memory which has a small memory capacity can be made the most of by storing therein, for as long time as possible, data to be read at high frequency.
In the conventional cache memory, however, old data stored therein is necessarily erased each time new data is written. In other words, there are many cases where new data to be read at low frequency is replaced, in the cache memory, with data to be read at high frequency. This being so, the advantage of the high-speed operation realized by the cache memory cannot be made the most of.
USPTO Backgrounds
USPTO Backgrounds