1. Technical Field
The present invention relates to a system and method that uses translation table attributes for replacement class identifier determination in locking a cache. More particularly, the present invention relates to a system and method that selects a “way” (or “set”) of a cache based on data stored in a Memory Management Unit's Translation LookAside Buffer (TLB).
2. Description of the Related Art
A cache often has a number of “ways” or “sets.” In one implementation, a cache with four “sets” is implemented using a cache with four columns for storing data, with each of the columns (“sets”) corresponding to a particular class identifier. Application developers often use the sets in order to store similar information. For example, in a four set cache, one set can be designated to store “streaming” data, two sets can designated to store “locking” data, and the fourth set can be designated to store general data. In this example, all streaming data (e.g., video, multimedia, etc.) is sent to the streaming set of the cache in order to prevent “polluting” the cache. Likewise, the locking sets of the cache are ideally used to store data in order to ensure real-time functionality. One challenge of the prior art is that the cache set that is used is often pre-determined during compilation. If the compiler makes a mistake, data may be sent to the wrong cache set which may, as described above, impact performance if the cache is polluted or data used for real-time functionality is not readily available.
Traditional Real Memory Translation (RMT) implementations use range registers that are based on effective address ranges and are associated with specific class identifiers that identify the cache set. The range registers are typically hardware-based registers. One challenge of the traditional approach is the hardware overhead used to dedicate range registers that are used for RMT management. Another challenge facing this traditional approach is that the number of active RMT classes is limited to the number of Effective Address Range (EAR) registers that have been architected into the hardware design.
Another challenge facing the traditional approach is the difficulty in changing the RMT configuration of a system. Using the traditional approach, multiple software load and store operations are needed in order to set up, or configure, the fields used in RMT management.
The traditional approach's use of pre-architected EAR registers limits a system's flexibility of the RMT and relies upon the course compile-time allocation of EAR registers described above. This inflexibility limits the Memory Management Unit's (MMU's) control over various memory units. In addition, the traditional implementation imposes compile-time constraints on cache-locking. Imposing such compile-time constraints on cache-locking restricts the Virtual Memory Manager (VMM) from providing fine-grain control over the cache and, thus, may result in poorer performance.
USPTO Backgrounds
USPTO Backgrounds