(1) Field of the Invention
The present invention relates to a photolithographic process, and more particularly to a method for forming submicrometer patterns of photoresist using a silylation process and anti-reflective coating techniques that provide high-fidelity, distortion-free photoresist patterns. The method is used to make submicrometer gate electrodes for field effect transistors (FETs).
(2) Description of the Prior Art
Today's Ultra Large Scale Integration (ULSI) on semiconductor substrates requires the patterning of closely spaced submicrometer lines in semiconductor materials such as polysilicon, metals, and insulators, and more specifically for making FET gate electrodes. Advances in photolithographic techniques and in anisotropic (directional) etching have substantially decreased the line widths and spacings between lines. For example, improvements in optical exposures and photoresist materials have lead to submicrometer resolution in photoresist image sizes. Directional plasma etching has resulted in submicrometer patterns being replicated in the underlying semiconductor layers using these photoresist images as an etch mask. Unfortunately, high resolution submicrometer images in photoresist require shallow depth of focus during exposure, but thick photoresist patterns are required because of the poor etch rate between the photoresist layer and underlying semiconductor layer.
Typically these submicrometer closely spaced lines are formed on substrates having non-planar surfaces and other irregular structures. These rough or irregular topographies make it difficult to use a single layer of photoresist without having distorted images. These distorted images can result from the scattered radiation from the underlying structures during the exposure of the photoresist layer. One prior method of minimizing these distorted images is to use a multilayer photoresist technique. For example, a three-layer process consisting of a bottom photoresist, an intermediate spin-on glass (SOG), and an upper high-resolution photoresist layer is deposited by spin coating. Optical exposure methods are used to pattern the upper photoresist layer, and then anisotropic plasma etching is used to replicate the pattern in the underlying SOG and bottom photoresist layers. This involves a complicated process in which two reactive ion etching (RIE) steps are used: one to etch the SOG, and then using the SOG as a mask to pattern the underlying photoresist layer using a second RIE step. The relatively thick bottom photoresist layer forms an essentially flat surface over the underlying structure. This photoresist absorbs the reflected light scattered from the underlying rough topography during exposure.
To simplify this process, an alternate technique using a silylation process can be used. In this method a single layer of photoresist is used and exposed using a mask to form latent images in the photoresist. Silicon compounds are then applied to the photoresist surface. These compounds, which are selectively absorbed on the exposed portions of the photoresist having the latent images, form a patterned silylated layer. The photoresist is then patterned by an etching process, such as RIE in oxygen (O.sub.2), to remove the non-exposed portions of the photoresist layer, while the silylated portions form an effective mask to the oxygen etching. One method of forming improved silylated images is described by S. Ito et al. in U.S. Pat. No. 5,407,786. In this method ammonia is used before or after the photoresist layer is exposed, then the photoresist layer is treated with hexamethyldisilazane (HMDS) to provide an improved silylation layer on the exposed portions of the photoresist. The silylated patterned portions provide a good etch mask in oxygen plasma etching for replicating the underlying photoresist layer. Another method, similar to Ito's, of forming submicrometer resist patterns using a silylation process is described by J. S. Lee in U.S. Pat. No. 5,525,192 in which the photoresist layer is treated with an alkali solution to form an insoluble layer, and then latent images are formed by optical exposure using a mask. Selective etching is used to remove portions of the exposed photoresist layer to about the thickness of the insoluble layer and the portions of the exposed photoresist layer are then silylated. The silylated portions are used as an O.sub.2 RIE mask.
Unfortunately, the scattered radiation from the rough underlying topography during exposure of the single layer of photoresist can still result in distorted latent images which are silylated. These silylated patterns are then replicated by plasma etching in oxygen in the underlying resist, still resulting in distorted patterns. Therefore there is still a need in the semiconductor industry to improve on the silylation process that also minimizes or eliminates the distorted images that can occur from the reflected light while providing a cost-effective manufacturing process.
USPTO Backgrounds
USPTO Backgrounds