1. Field of the Invention
The present invention relates to a lead frame which is used in a semiconductor device assembly process, and more particularly, to a method of etching the lead frame.
2. Description of the Related Art
A typical lead frame, which is used in a semiconductor device assembly process, is one of the core component materials for a semiconductor package. The lead frame serves as a lead for connecting the interior and exterior of the semiconductor package to one another, and as a supporting member for a semiconductor chip. The lead frame is comprised of a chip pad for loading a chip thereon, an inner lead, and an outer lead. A lead frame fabricating method is largely divided into a stamping process and an etching process. The stamping process fabricates a lead frame having a predetermined pattern by pressing a substrate and forming a certain shape while sequentially transferring the substrate using a sequential transfer press molding device. This method is advantageous for mass production, but requires a large initial investment on the mold fabrication and it takes as long as about six to ten months to make a mold. Therefore, the etching process has been adopted for multi-species production in small quantities. The etching process fabricates a lead frame of a desired pattern by exposure to light, development, and etching after forming a photoresist layer on either surface of a substrate. The etching process is suitable for the formation of a fine pattern, and does not take long to process. However, the etching process has drawbacks in terms of high cost and suitability for mass production.
A lead frame fabricating method using a typical etching process includes the steps of pretreating a lead frame material after completing the design of a lead frame, coating a photoresist, exposing to light, developing, etching, peeling, plating, and taping as post-processing steps.
FIG. 1 illustrates a conventional method of etching a lead frame. Referring to FIG. 1, a photoresist pattern 3 is formed on both surfaces of a lead frame material 1, and the lead frame material 1 is etched using the photoresist pattern 3 as an etching mask. In fabricating a lead frame having a minute pattern, the lateral ends of the lead frame material are overetched during the etching process, thereby generating an undercut nonlinear portion 5. The nonlinear portion 5 has been a serious obstacle in fabricating a lead frame requiring an accurate size.
Also, the nonlinear portion 5 impedes a subsequent silver plating on the tip of the inner lead or chip pad, or plating of an alloy of tin (Sn) and lead (Pb) on the external lead in a packaging process. That is, the conventional method has a drawback in that the thickness of a material plated on the surface of the lead frame is not uniform.
USPTO Backgrounds
USPTO Backgrounds