This invention relates to a method of manufacturing semiconductor devices, and more particularly to an improved method of forming multi-layered conductive structure semiconductor devices.
In semiconductor memory devices, attempts have been made to reduce the pattern size. This is due to the requirement of improving integration density to improve the operating speed of the integrated circuit. Particularly, in a semiconductor device of the multi-layered conductive structure type, further reduction has been made to the width of each conductive layer and to the interval between adjacent conductive layers. This trend has tended to reduce through hole sizes. It is for this reason that the RIE (reactive ion etching) process has been employed for forming through-holes. The RIE process is characterized by a small amount of side etching and also high etching controllability.
The conventional method of manufacturing a double conductive layer structure semiconductor device will be described by referring to FIGS. 1A through 1D. The following manufacturing method includes the step of forming through-holes.
USPTO Backgrounds
USPTO Backgrounds