1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device such as a NAND type flash memory suitable for operation by a single power supply at a low voltage and a method of data programming of the same.
2. Description of the Related Art
Conventionally, in semiconductor nonvolatile memory devices such as EPROM's or flash memories, the mainstream was a NOR type semiconductor nonvolatile memory device for performing the programming of data by injecting electrons into a floating gate by injection of channel hot electrons (hereinafter referred to as "CHE's").
In a NOR type semiconductor nonvolatile memory device, however, two memory transistors share one bit contact and source line, therefore there is a problem in that higher integration is difficult and an increase of capacity cannot be achieved.
From the above viewpoint, a NAND type flash memory realizing higher integration by connecting a plurality of memory transistors in series to constitute a NAND string and having two NAND strings share one bit contact and source line has been proposed.
In a general NAND type flash memory, in an erasing operation, 0 V is supplied to all word lines of a selected NAND string block, and a high voltage (for example 20 V) is supplied to all word lines of non-selected NAND string blocks and a substrate of a memory array.
As a result, electrons are pulled out of the floating gates of only the memory transistors of the selected NAND string block to the substrate. The threshold voltage of the memory transistors shifts in a negative direction and becomes for example about -3 V.
On the other hand, the operation for programming data is carried out together for memory transistors connected to the selected word lines in so-called page units. A high voltage (for example, 18 V) is supplied to the selected word lines, 0 V is supplied to the bit lines to which the ("1" data) memory transistors which are to be programmed are connected, and an intermediate voltage (for example, 9 V) is supplied to the bit lines to which the ("0" data) memory transistors which are prohibited from being programmed are connected.
As a result, electrons are injected into the floating gates of only the selected memory transistors which are to be programmed. The threshold voltage of the selected memory transistors shifts in a positive direction and becomes for example about 2 V.
In such a NAND type flash memory, both the programming and erasing of the data are carried out by an FN (Fowler-Nordheim) tunnel current. Therefore, there are the advantages that it is relatively easy to supply an operating current from a booster circuit inside the chip and that operation by a single power source is easy.
Further, since the data is programmed in units of pages, that is, all together for memory transistors connected to the selected word line, as a natural result, this memory is superior in the point of the programming speed.
Nevertheless, the above NAND type flash memory has the following disadvantage.
Namely, since the data programming operation of the NAND type flash memory is carried out in units of pages, it is necessary to supply an intermediate voltage (for example 9 V) to all bit lines to which memory transistors for which programming is prohibited are connected.
The number of bit lines in a page unit usually is as much as that for 512 bytes, that is, about 4000, therefore the load an the booster circuit for generating the intermediate voltage is large.
Further, in the above data programming operation, due to the necessity of controlling the threshold voltage of the programmed memory transistors, the programming/verifying operation is repeatedly carried out a number of times, therefore it is necessary to charge the bit lines for which programming is prohibited to the intermediate voltage at every programming operation.
For this reason, when the programming/verifying operation has been performed a large number of times, the time required for switching of the bit line voltage in the programming/verifying operation becomes greater than the substantive programming time. The programming speed is therefore restricted and high speed programming becomes difficult.
Further, the data latch circuits provided for every bit line for latching the page data must be made so durable against high voltages in specifications so as to handle the intermediate voltage. The size inevitably becomes large, and accordingly it becomes difficult to lay out the data latch circuits for every bit line.
A new method of programming of a NAND type flash memory which solves the above problems, which is suited for operation by a single power supply at a low voltage, which is able to be processed at a high speed, and in addition which enables easy layout of the data latch circuits for the bit lines is disclosed from p. 1152 to p. 1153 and FIG. 5 to FIG. 6 of the "IEEE Journal of Solid-State Circuits", vol. 30, No. 11, November 1995.
In the data programming operation disclosed in the above document, NAND strings to which memory transistors for which programming is prohibited are placed in a floating state and the channel portion voltage of the NAND strings is automatically boosted mainly by capacity-coupling with a pass voltage(for example, 10 V) supplied to the non-selected word lines.
This automatic boosting operation is referred to as a "self-boost" operation.
FIG. 28 is a view explaining an operation where the data programming of a NAND type flash memory is carried out by a self-boost operation.
The NAND type flash memory of FIG. 28 is for convenience shown as a memory array where four memory transistors are connected in series to one NAND string connected to two bit lines, but in an actual memory array, the number of the memory transistors connected in series to one NAND string is generally as high as 16.
In FIG. 28, BLa and BLb denote bit lines. The bit line BLa has connected to it a NAND string comprised of two selection transistors ST1a and ST2a and four memory transistors MT1a to MT4a connected in series.
Further, the bit line BLb has connected to it a NAND string comprised of two selection transistors ST1b and ST2b and four memory transistors MT1b to MT4b connected in series.
The selection transistors ST1a and ST1b are controlled by a selection gate line SL1, while the selection transistor ST2a and ST2b are controlled by a selection gate line SL2. Further, the memory transistors MT1a to MT4a and MT1b to MT4b are controlled by word lines WL1 to WL4, respectively.
Next, an explanation will be made of an operation where MT2a is a memory transistor for which programming is prohibited and MT2b is a memory transistor which is to be programmed when the word line WL2 is selected and page programming is carried out in the NAND type flash memory of FIG. 28.
First, a power supply voltage VCC (3.3 V) is supplied to the selection gate line SL1, a ground voltage GND (0 V) is supplied to the selection gate line SL2, the power supply voltage VCC (3.3 V) is supplied to the bit line BLa to which the memory transistor MT2a for which programming is prohibited is connected, and the ground voltage GND (0 V) is supplied to the bit line BLb to which the memory transistor MT2b which is to be programmed is connected.
Next, a program voltage Vpgm (for example, 18 V) is supplied to the selection word line WL2, and the pass voltage Vpass (for example, 10 V) is supplied to the non-selected word lines WL1 and WL3 to WL4.
As a result, the channel portion of the NAND string to which the memory transistor MT2a for which programming is prohibited is connected achieves a floating state, the potential of the channel portion is mainly boosted by capacitor-coupling with the pass voltage Vpass supplied to the non-selected word lines (three in FIG. 28, but generally 15) and rises up to the programming prohibit voltage, and data programming to the memory transistor MT2a is prohibited.
On the other hand, the channel portion of the NAND string to which the memory transistor MT1b which is to be programmed is set to the ground voltage GND (0 V), data is programmed to the memory transistor MT2b by the potential difference with the program voltage Vpgm supplied to the selected word line, and the threshold voltage shifts in the positive direction and becomes for example -3 V to about 2 V of the erasing state.
FIGS. 29A and 29B are views explaining the self-boost operation. FIG. 29A illustrates one memory transistor in the program prohibit NAND string at the time of a self-boost operation; and FIG. 29B is an equivalent circuit diagram thereof.
In FIG. 29A, VC is a voltage supplied to the word line WL (control gate CG), VF is a potential of the floating gate FG, Vch is a boosted NAND string channel potential, C-ono is an inter-layer capacitor comprised by a three-layer insulation film between a control gate and a floating gate, C-tox is a tunnel oxide film capacity, and C-ch is a channel portion capacitor of a memory transistor including a source/drain diffusion layer region. Further, L-dep is the length of spread of a depletion layer in the source/drain diffusion layer.
Further, in FIG. 29B, C-ins is a combined capacitor comprised by a serial connection of the inter-layer capacitor C-ono and the tunnel oxide film capacitor C-tox.
By the equivalent circuit of FIG. 29B, the NAND string channel potential Vch at the time of a self-boost operation is represented by equation (1): EQU Vch=Vr*VC (1)
Here, Br is a self-boost efficiency represented by the following equation (2) and usually is set at around 0.8 according to the optimum design of the device structure. EQU Br=C-ins/(C-ins+C-ch) (2)
In the self-boost operation at the time of programming, VC of equation (1) becomes the weighted average of all voltages supplied to the word lines, but in a general NAND type flash memory, there are about 16 word lines constituting a NAND string, therefore the pass voltage supplied to the non-selected word lines becomes greater.
Accordingly, equation (1) may be represented as in equation (3). EQU Vch=Br*Vpass (3)
Accordingly, if Br=0.8 and Vpass=10 V, Vch becomes almost equal to 8 V and can sufficiently become the programming prohibit voltage.
The data programming operation of the NAND type flash memory using the above self-boost operation is suited to operation by a single power supply at a low voltage since it is not necessary to supply a high intermediate voltage to the non-selected bit lines, it enables high speed programming, and in addition enables easy layout of the data latch circuits for every bit line.
However, in order to realize a self-boost operation, it is necessary to make the self-boost efficiency Br large, i.e., 0.6 to 0.8 at the lowest.
When the self-boost efficiency Br cannot be sufficiently obtained, the NAND string channel potential Vch does not sufficiently rise, therefore, in the example of FIG. 28, there is a possibility that the non-selected memory transistor MT2a will be erroneously programmed.
Further, when it is intended to increase the channel potential Vch by raising the pass voltage Vpass, in the example of FIG. 28, there is a possibility that the memory transistors MT1b and MT3b to MT4b will be erroneously programmed.
Further, the self-boost efficiency Br cannot become about 1 in principle, therefore even in a case where the non-selected memory transistors are not erroneously programmed, degradation of the disturb tolerance cannot be avoided.
In the device structure of a NAND type flash memory, in order to set the self-boost efficiency Br as large as possible for avoiding the above problem, it is necessary to make the channel portion capacitor C-ch of a memory transistor including a source/drain diffusion layer region smaller than that of equation (2). The P-type impurity concentration of the P-type well region in which the NAND type memory array is formed must be set low for this purpose.
If the P-type impurity concentration is set low as described above, however, the length of spread of the depletion layer L-dep illustrated in FIG. 29A becomes large, the punch through tolerance is lowered, the channels of the memory transistors and selection transistors can no longer be shortened, and consequently higher integration can no longer be realized.
That is, in the device structure of the NAND type flash memory of the related art, there is a tradeoff between securing the self-boost efficiency Br and shortening the channels of the memory transistors and the selection transistors, therefore it is difficult to both secure a disturb tolerance and a higher integration.
FIGS. 30A and 30B are graphs showing the tradeoff explained above.
In FIG. 30A, the abscissa indicates the concentration Ndope of the memory array PWELL, while the ordinate indicates the self-boost efficiency Br.
Further, in FIG. 30B, the abscissa indicates the concentration Ndope of the memory array PWELL, while the ordinate indicates the channel shortening limit Lmin of the memory transistors and selection transistor (TR).
It is understood from FIG. 30A that, in order to secure a sufficient self-boost efficiency Br, it is necessary to set the PWELL concentration Ndope low. On the other hand, it is understood from FIG. 30B that shortening of the channels of the memory transistors and selection transistors becomes difficult if the PWELL concentration Ndope is set low.
In the NAND type flash memory of the related art, aluminum is used for each of the bit lines arranged in the column direction.
In this case, due to the restriction of the pitch in the column direction, it becomes difficult to arrange bit contacts between the aluminum interconnections, diffusion layer and the data latch circuits for every bit line.
A structure of a NAND type flash memory which solves the above problems, eases the restriction of the pitch in the column direction, and eases the arrangement of the bit contacts between the aluminum interconnections and the diffusion layer and the data latch circuits for every bit line is disclosed in the diagram of the memory array of FIG. 2 and the diagram of the pattern layout of FIG. 3 in U.S. Pat. No. 4,962,481.
In the NAND type flash memory disclosed in the above patent, the restriction of the pitch in the column direction is eased by having a pair of two NAND strings share one bit line.
FIG. 31 is a view of the memory array of the NAND type flash memory disclosed in the above patent.
The NAND type flash memory of FIG. 31 is for convenience shown as a memory array comprised of a pair of two NAND strings connected to one bit line and four memory transistors connected in series to each NAND string, but in an actual memory array, there are generally about 16 memory transistors connected in series to one NAND string.
In FIG. 31, BL denotes a bit line. The bit line has connected to it a pair of two NAND strings NANDa and NANDb.
The NAND string NANDa is comprised of two selection transistors ST1a, ST2a, four memory transistors MT1a to MT4a, and a pass transistor Pass-TR connected in series.
The NAND string NANDb is comprised of two selection transistors ST1b, ST2b, four memory transistors MT1b to MT4b, and a pass transistor Pass-TR connected in series.
The selection transistors ST1a and ST1b are respectively controlled by selection gate lines SL1a and SL1b, the selection transistors ST2a and ST2b are controlled by the selection gate line SL2, and the memory transistors MT1a to MT4a and MT1b to MT4b are respectively controlled by the word lines WL1 to WL4.
Here, the pass transistor Pass-TR of the NAND string NANDa is controlled by the selection gate line SL1b, while the pass transistor Pass-TR of the NAND string NANDb is controlled by the selection gate line SL1a. In these pass transistors pass-TR, N-type impurity layers such as phosphorus (P) are formed. The transistors are in the ON state irrespective of the voltage supplied to the selection gate lines.
Accordingly, in the memory array of FIG. 31, when the selection gate line SL1a is at a high level, and the selection gate line SL1b is at a low level, the NAND string NANDa is connected to the bit line BL. When the selection gate line SL1b is at a high level, and the selection gate line SL1a is at a low level, the NAND string NANDb is connected to the bit line BL.
FIG. 32 is a view of the pattern layout of the NAND type flash memory of FIG. 31.
Further, FIGS. 33A and 33B are sectional views of the device structure of the pattern layout of FIG. 32, in which FIG. 33A is a sectional view in the direction A-A'; and FIG. 33B is a sectional view in the direction B-B'.
In FIG. 32 and FIGS. 33A and 33B, 100 denotes a semiconductor substrate, 101 a P-type well region in which a memory array region is formed, 102 a source and drain N-type diffusion layer of a memory transistor, 103 a VSS interconnection and an N-type diffusion layer of a bit contact portion, 103a an N-type diffusion layer formed in the channel portion of the pass transistor, 104 a tunnel oxide film, 105 a gate oxide film of the selection transistor portion, 105a a LOCOS element isolation oxide film, 106 a first layer polycrystalline silicon gate electrode forming a floating gate electrode, 107 an ONO-3 layer insulation film, 108 second layer polycrystalline silicon interconnections forming control gate electrodes of the memory transistors and selection transistors, 112a an inter-layer insulation film under the aluminum interconnections, 113a a contact hole under the aluminum interconnections, and 114 aluminum interconnections.
In the memory array of the NAND type flash memory mentioned above, the pitch of the bit line layout in the column direction is increased to two times the usual pitch, therefore the layout of the bit contacts between the aluminum interconnections and diffusion layer and data latch circuits for every bit line is easy.
However, in the memory array described above, it is necessary to connect one extra pass transistor in series for every NAND string, therefore there is a disadvantage that the memory size becomes larger by about 6 to 7 percent and the cost becomes high.
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