1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention teaches a novel method for etching semiconductor devices incorporating low dielectric constant organic films, such as SiLK(copyright), while maintaining one or more desirable feature attributes, including feature critical dimension.
2. Description of Related Art
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, K, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as xe2x80x9clow-K materialsxe2x80x9d, have been developed. Many of these new dielectrics are organic compounds.
Low-K materials include, but are specifically not limited to: benzocyclobutene or BCB; Flare(trademark) manufactured by Allied Signal(copyright) of Morristown, N.J.; one or more of the Parylene dimers available from Union Carbide(copyright) Corporation, Danbury Conn.; polytetrafluoroethylene or PTFE; and SiLK(copyright). One PTFE suitable for IC dielectric application is SPEEDFILM(trademark), available from W. L. Gore and Associates, Inc, Newark, Del. SiLK(copyright), available from the Dow(copyright) Chemical Company, Midland, Mich., is a silicon-free BCB.
SiLK(copyright) has a dielectric constant of 2.65, can be processed at temperatures up to 490xc2x0 C., and is compatible with metals such as aluminum Al, copper Cu, and the barrier materials titanium Ti, and tantalum Ta. These properties make this material suitable for all existing complementary metal oxide semiconductor, or CMOS, interconnect technologies which implement aluminum lines and tungsten vias, as well as copper/damascene technologies.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes a photo resist material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that blocked light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials the exposed regions are removed, and in the case of negative photoresist materials the unexposed regions are removed. Thereafter the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer.
The development of an effective etching process for an organic low-K film such as SiLK(copyright) must take into account several criteria including etch rate, profile control, selectivity to underlying materials as well as hardmask and critical dimension (CD) control. The etching of low-K dielectric materials was at first approached as if a silicon-based dielectric were being etched. In the case of organic low-K films however, other chemistries and processes are often needed to effectively etch the material.
Etching may be accomplished in a dual-frequency capacitively-coupled, (DFC) dielectric etch system. One such is Lam Research(trademark) model 4520 XLE(trademark), available from Lam Research(trademark) Corporation, Fremont Calif. A simplified view of this system is shown at FIG. 1. Having reference to that figure, the system, 1, operates with two different frequencies coupled to the top and bottom electrodes respectively, 5 and 7. The frequencies used in this system are 27 MHz and 2 MHz, respectively, but alternate frequencies may also be implemented. The dual frequencies implemented in the system are provided by frequency drives 17 and 19. This system provides total etching power of up to 3000 watts. This system utilizes rings, for instance 13, at the wafer edge to keep the etching plasma confined. Processes are typically run at pressures of 100-300 mT, which are maintained within chamber 15. The gap between the electrodes can be adjusted as required for the process, by means of a gap drive, 3. Finally, the wafer is held for processing by means of an electrostatic chuck, 9, formed in conjunction with the lower electrode 7. Not shown in this diagram is the system for maintaining pressures within chamber 15. Study of the principles hereinafter enumerated will render evident to those having skill in the art that these principals are applicable to a wide variety of semiconductor etching systems. Such systems incorporate a broad range of operating features and parameters, and the principles later detailed specifically contemplate their implementation in all such etching systems, within the range of operating parameters defined herein.
Low-K organic polymers, such as SiLK(copyright) can be etched via an oxidation (e.g. oxygen-based) or a reduction (e.g. hydrogen-based) chemical process. Because of the strong chemical nature of an oxygen-based etch an isotropic profile will result, unless a passivant such as a fluorocarbon or a hydrocarbon is added to protect the sidewalls during the etch. Although chemistries that use fluorocarbons as passivants give reasonable etch rates and profile control, the free fluorine from the fluorocarbon causes poor selectivity to the oxide hardmask. This particularly affects corner selectivity where the oxide hardmask is first exposed, and as a result CDs are degraded. At least two different oxygen-based chemistries have been utilized to etch low-K materials: N2/O2/H2 and N2/O2/hydrocarbon, especially CH4 and C2H4.
To facilitate discussion, FIG. 2 illustrates a representative layer stack 100 during the etch process, including a photoresist layer 102, a hard mask layer 104, a low capacitance dielectric layer 106 and an etch stop layer 108. Stack 100 is disposed on a substrate, for instance a wafer, not shown in this view. Etch stop layer 108 may represent, for example, an etch stop layer for a dual damascene process and is typically formed of a suitable etch stop material such as TiN, SiN, tetraethylorthosilicate or TEOS, or the like. Low capacitance dielectric layer 106 represents a layer of one of the organic low-K materials previously discussed.
Above low capacitance dielectric layer 106 there is shown disposed a hard mask layer 104, which is typically formed of a material including but not limited to SiN, silicon oxynitride or SiON, and TEOS. Hard mask layer 104 represents the masking layer that is employed to etch the via/trench in low capacitance dielectric layer 106. Each of the layers in the stack are ultimately disposed on the surface of a wafer, not shown in this view. The hard mask layer is employed since photoresist is typically ineffective as a masking material when etching the organic low-K material of low capacitance dielectric layer 106. This is because the photoresist material and the organic low-K material tend to have similar chemical characteristics, tend to require a similar etch chemistry, and/or tend to have a similar etch rate. To pattern the hard mask out of hard mask layer 104, photoresist layer 102 is provided. Photoresist layer 102 may represent, for example, a layer of deep UV or conventional photoresist material.
Photoresist layer 102 has been patterned using a conventional photoresist patterning process. The patterning of photoresist layer 102 creates an opening through which hard mask layer 104 was etched in a subsequent hard mask etch process. In one example, hard mask layer 104 represents a TEOS layer, and the hard mask etch process may take place in a plasma processing reactor using a suitable TEOS etch chemistry such as Ar/C4F8/C2F6/O2 or a conventional TEOS etchant.
In FIGS. 2 and 3, the low capacitance dielectric layer 106 is being etched. The etching of low capacitance dielectric layer 106 typically takes place in a plasma processing reactor. Low capacitance dielectric layer 106 is typically etched using an oxygen-radical containing gas, including but not limited to O2, CO, CO2, or the like. A diluent such as N2 is typically added to the etchant gas employed to etch through the low capacitance dielectric material. A passivating agent such as a fluorocarbon gas is also typically added to the etch chemistry.
Fluorocarbons which have been found to be useful as passivants include, but are not limited to C4F8, C2HF5, CH2F2. However, as shown at FIG. 4 and later discussed, while the addition of the fluorocarbon passivating agent helps preserve the vertical sidewall profile, it tends to facet first the photoresist and subsequently the hard mask, which in turn enlarges opening 202 as the etch proceeds through low capacitance dielectric layer 106. Since the fluorine in etch processes utilized hydrofluorocarbons enhance hardmask loss, and since some low-K material, including SiLK(copyright) do not contain silicon, there is no need to include fluorine in the etch gases.
As the low-K material is often a similar chemical composition to the photoresist, the etching of the low-K material causes a concomitant etching of the photoresist, as is later explained. The photoresist layer survives for a period of time during the low-K etch step, and after the photoresist has been consumed, the hard mask remains during the remainder of the low-K etch, as shown at FIG. 3. Following completion of the etch step, further fabrication steps are employed. By way of example but not limitation, the trench or via formed at 202 may be filled with a metal, which is deposited by any known means. Thereafter the deposited metal layer may be polished, for instance by means of a chemical mechanical polish or CMP, to remove the metal layer down to the hard layer, thus leaving the via, or trench filled with metal interconnects. These latter fabrication steps are not shown in this figure.
As is well known, the oxygen species employed to etch through low capacitance dielectric layer 106 tends to etch isotropically, causing the sidewalls in opening 202 to bow instead of maintaining the desired vertical sidewall profile. The bowing effect is exacerbated if over-etching is required to compensate for etch nonuniformity across the wafer. This bowing effect degrades profile control, for example, causing the formation of re-entrant profiles, which are profiles that have angles greater than 90 degrees, and cause difficulties in subsequent processing steps such as metal fill.
The oxygen species that is employed to etch through the low capacitance dielectric layer 106 also attacks the overlying photoresist material in layer 102. Consequently, the thickness of photoresist layer 102 is reduced as the etch proceeds through low capacitance dielectric layer 106.
As shown at FIG. 4, because the oxygen species attacks the photoresist material 102 isotropically, the photoresist mask often pulls back in certain regions of the via/trench, for instance as shown at 401 and 401xe2x80x2. As the photoresist material is worn away by the oxygen species and the photoresist material is pulled back, the TEOS hard mask material of hard mask layer 104 is exposed to the fluorocarbon that is added for passivation purposes. Since fluorocarbon is also an etchant of TEOS, the exposed hard mask material is also etched away during the low-K etch process, for instance at 403 and 403xe2x80x2, causing the opening in hard mask layer 104 to enlarge. This faceting of the opening in hard mask layer 104 in turn enlarges the via/trench to be etched through low capacitance dielectric layer 106. With this enlargement, the critical dimension of the via/trench may be lost.
The use of a fluorocarbon additive also narrows the process window of the low capacitance dielectric layer etch. If too much fluorocarbon is added to the etch chemistry, the etch rate of the low capacitance dielectric layer will be reduced dramatically, until etch stoppage eventually occurs. If too little fluorocarbon is added, there may be insufficient passivation to maintain the desired vertical sidewall profile.
Even where appropriate etchant/diluent/passivant combinations are employed, uniformity of the etch process across the surface of the wafer is often a problem. In one instance, it was observed that in the manufacture of semiconductors, including at least one layer of low-K material, an oxide hard mask and a layer of organic photoresist, the etching process employed to form the device proceeded at different rates across the surface of the wafer. What is needed is the determination of the causation of the uneven etching of low-K materials in combination with photoresist and oxide hard masks.
Upon the determination of one or more causes of uneven etching, what accordingly is necessary is a methodology which improves the uniformity of the etch process in fabricating a semiconductor device which include one or more layers of low-K material, photoresist and hard mask.
Finally, what is needed is at least one etch chemistry which will operate with the method to maintain critical dimension, minimize isotropicity and hard mask faceting while providing for an acceptable etch rate for the fabrication of the device.
These and other features of the present invention will be described in more detail in the section entitled detailed description of the invention and in conjunction with the following figures.
The present invention teaches a two-step process to improve low-K dielectric etch uniformity on a wafer bearing a low-K layer, a hard mask layer, and a photoresist layer. The etching process takes place in a reactor vessel. According to a first aspect of the present invention, in a first etching step while photoresist is present the low-K material is etched using a first etchant including an oxygen-bearing compound and a hydrocarbon passivant in the presence of a radio-frequency insulative edge ring. When the photoresist is determined to be substantially cleared from the wafer, for instance by means of a clearing signal generated by detectors and end-point software, a second etching step is performed. In the second etching step, the low-K material is etched using a second etchant including an oxygen-bearing compound and a hydrocarbon passivant in the presence of a radio-frequency conductive edge ring. Hydrocarbons may, in accordance with another aspect of the present invention, further include hydrofluorocarbons.
According to one aspect of the present invention, in some cases the first and second etchants may be identical. According to another aspect of the present invention, the first and second etchants may be different, either by virtue of different oxygen-bearing compounds or different hydrocarbons, or by different concentrations of at least one of the oxygen-bearing compound and the hydrocarbon.
According to yet another aspect of this invention, a diluent may be added to at least one of the first and second etchants. Where diluents are included in both etchants, they may be identically composed and concentrated in both etchants, or they may differ by virtue of chemical composition or concentration within their respective etchants.
Different combinations of low-K materials, hard mask materials and photoresists may require different etchant/passivant/diluent combinations, and examples of these are chemistries are presented in the section entitled xe2x80x9cDetailed Description of the Inventionxe2x80x9d.
According to yet another aspect of this invention an insulative cover is provided over a radio-frequency conductive edge ring to provide the radio-frequency insulative edge ring. The insulating cover is moved aside to expose the conductive edge ring for the second etching step. The present invention contemplates a number of physical configurations whereby the insulator ring is urged into, and away from, its masking of the radio-frequency conductive edge ring.
Alternatively, still another aspect of the present invention contemplates the etching of the wafer may be conducted in two locales, where the first etch step is conducted using an insulating hot edge ring at a first locale in a reactor vessel. The wafer is then moved to a second locale and a second etch step is conducted using a conductive hot edge ring. These two steps may be performed in a series of reactor vessels, or in one reactor vessel having a plurality of processing stations.
These and other advantages of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the Drawing.
USPTO Backgrounds
USPTO Backgrounds