Chemical mechanical polishing (CMP) used to fabricate a semiconductor device is a technology that forms a planarized layer on a semiconductor device by polishing a target layer formed on the substrate, or that forms patterns by a damascene technique using different polishing rates of two or more materials.
In a CMP process, a suitable slurry for a material to be polished is supplied to polish a layer to be polished. A polishing aspect varies depending on an area occupied by the layer to be polished and on pattern density in a region where a layer to be polished remains.
As illustrated in FIG. 1, a semiconductor substrate includes thereon first patterns 12 formed at high density, each with small widths, and a second pattern 14 formed at low density with a layer width. The CMP process may be performed on such a semiconductor substrate to form the resulting patterns filling the first patterns 12 and the second pattern 14 with their top surfaces planarized. In order to form the resulting patterns, a layer 16 to be polished is formed on the semiconductor substrate having the first patterns 12 and the second pattern 14.
As illustrated in FIG. 2, the layer 16 to be polished is polished using a slurry that polishes it more quickly than the semiconductor substrate 10 is polished, to thereby form third patterns 16a and a fourth pattern 16b respectively filled in the first patterns 12 and the second pattern 14. Considering the purpose of the CMP process, top surfaces of the third patterns 16a and the fourth pattern 16b should be planarized and aligned with a top surface of the semiconductor substrate 10. However, as illustrated, the layer to be polished is over-polished in a region where pattern density of the resulting patterns is high or the pattern area is large. This causes dishing in the top surface of the fourth pattern 16b which causes the top surface to be lower than other regions, as illustrated.
Referring to FIG. 3, in subsequent processes, when portions of the third patterns 16a and the fourth pattern 16b are removed to expose the substrate 10, the substrate 18 under the fourth pattern 16b may become over-etched and damaged due to the dishing in the region where the pattern density is low or the pattern area is large. On the other hand, when the third patterns 16a and the fourth pattern 16b are etched until the substrate 18 under the fourth pattern 16b is exposed, the third patterns 16a may not become completely etched, and thus the substrate thereunder may not be exposed.
For example, when a large region is a monitoring pattern that monitors a process on a small device region, the dishing of the large monitoring pattern may interfere with an accurate determination of a process result in the small device region. Also, when both large and small regions are included within the device region, the process results of both regions may differ from each other, which may cause a material in any one of the regions to remain or become over-etched.
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