1. Field of the Invention
This invention relates to chip sets for use on computer mother boards, and more particularly, to a computer chip set which is specifically devised for use on a computer mother board with various clock rates, so as to allow the computer mother board to utilize various clock rates to drive various data processing devices, such as a CPU and a memory unit, with high performance.
2. Description of Related Art
The central processing unit (CPU) is the heart of a personal computer. As a general rule, the performance of a CPU is largely dependent on the rate of the clock signal used to drive the CPU. In the old days, the clock rate for a CPU was only several megahertz, however, with advances in the semiconductor technology, the clock rate for a CPU nowadays has advanced to several hundred of megahertz. An old CPU with a low clock rate on a computer mother board can be upgraded to a new one with a higher clock rate simply by replacing the old CPU with the new one. However, one problem arises in that the associated devices working in conjunction with the CPU, such as DRAM (dynamic random access memory), may not be able to catch up with the faster speed provided by the new CPU. Therefore, the chip set for the computer mother board needs to be able to provide various clock rates that can be selected for use by the CPU. For instance, on a high-end computer mother board, either 100 MHz, 83 MHz or 66 MHz can be selected as the clock rate for the CPU. Either 100 MHz, 83 MHz, 66 MHz or 50 MHz can be selected as the clock rate for the DRAM. Either 66 MHz or 33 MHz can be selected as the clock rate for the PCI (Peripheral Component Interconnect) controller. Finally, either 133 MHz or 66 MHz can be selected as the clock rate for the AGP (Accelerated Graphics Port) controller.
When these devices are set to different clock rates, the transfer of data and signals among these devices can be a problem that can even cause the computer system to come to a dead halt. Therefore, a suitable interface means needs to be provided among these devices to handle the different clock rates.
A conventional solution to the foregoing problem is to let the CPU and the DRAM, regardless of the ratio between their clock rates, carry out one action at the appearance of each pulse until the action of the current pulse is completed. This causes a waiting state in the processing of the data and thus considerably degrades the performance.
Another conventional solution is to drive the CPU and the DRAM at the same clock rate. However, DRAMs that can be driven by as high a clock rate as the high-end CPUs are usually much more expensive to purchase. Since new CPUs are typically provided with cache memories, the use of a low-speed DRAM does not considerably affect the overall system performance. Hoverer, the use of a low-speed DRAM in conjunction with a high-speed CPU causes the computer system to be extremely unstable in operation. A system crash or dead halt can therefore occur.
Moreover, since electromagnetic radiation from electric appliances can be hazardous to health, a personal computer must pass the EMI (electromagnetic interference) test before it can be put on the market. The electromagnetic radiation emanating from a high-speed CPU is even higher in frequency and can cause an increased level of interference. To reduce the EMI effect, several solutions have been proposed, such as lowering the clock rate for the CPU and shortening the signal transmission path between the CPU and the DRAM. For high-speed CPUs, signal transmission paths can easily be shortened to reduce the EMI effect; however, for DRAMs, signal transmission paths can hardly be shortened since DRAMs are typically provided in modules that are mounted in dedicated slots on the mother board. Therefore, if the DRAM shares the same high clock rate for the CPU, the EMI problem will be quite serious.
In summary, conventional computer mother boards with various clock rates have the following drawbacks.
(1) First, the conventional method of letting the CPU and the DRAM carry out one action at the appearance of each pulse until the action of the current pulse is completed cause the computer to be very low in performance since a waiting state is required and wastes time.
(2) Second, since all sequence control situations need to be well considered in the design, a very broad boundary condition would cause the circuit to be highly complex in structure, difficult to debug, large in layout space and less cost-effective to manufacture.
(3) Third, if the DRAM shares the same high clock rate of the CPU, the EMI effect will be quite serious since the signal transmission paths for the DRAM can not be further shortened.
USPTO Backgrounds
USPTO Backgrounds