This application is based upon and claims the benefit of priority from each of the prior Japanese Patent Application No. 2002-28469 filed on Feb. 5, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to cancellation of DC offset component that is likely to be included in an output signal, more particularly to a receiver used for mobile communication such as cellular phones.
2. Description of Related Art
Mobile communication appliances such as cellular phones rapidly prevailing in recent years need to meet demands on miniaturization, weight saving, and multi-function design. To meet such demands, in place of superheterodyne system conventionally used for a radio processing section, there has been widely employed direct conversion system that does not require an intermediate frequency signal (IF signal) and directly converts a radio frequency signal (RF) into a baseband signal. Since this system does not require a section for processing an IF signal, circuit scale of it can be compressed more than that of the superheterodyne system, which contributes to miniaturization, weight saving, and multi-function design of mobile communication appliance kind.
However, since the direct conversion system directly converts an RF signal into a baseband signal, this system cannot remove unnecessary DC offset components whereas DC offset components in an IF signal were removed by a band-pass filter or the like in the superheterodyne system. Accordingly, the direct conversion system requires a particular circuit for canceling DC offset.
FIG. 5 through FIG. 8 show examples of DC offset cancel circuits conventionally used. Out of those, examples of circuit structure shown in FIG. 5 through FIG. 7 are suitable for communication system such as called FDMA (frequency division multiple access), CDMA (code-division multiple access) or the like. FDMA and CDMA are communication system for receiving RF signals that succeed in terms of time. On the other hand, circuit structure shown in FIG. 8 is suitable for communication system such as called TDMA (time division multiple access) or the like. TDMA is communication system for receiving RF signals that do not succeed in terms of time. In the following descriptions, against TDMA system, communication system for receiving RF signals that succeed in terms of time will be mentioned as non-TDMA system.
It should be noted that FDMA (frequency division multiple access) is communication system that different frequencies are allocated to respective channels and CDMA (code-division multiple access) is communication system that different codes are allocated to respective channels. In both FDMA and CDMA, receiving signals succeed in terms of time. On the other hand, TDMA (time division multiple access) is communication system that channels are allocated to time slots each of which has its predetermined time length and RF signals circulate in each channel. Accordingly, receive operation is conducted in predetermined time slots only.
FIG. 5 shows circuit structure 110 directed to first prior art. In the circuit structure 110, there are provided highpass filters (HPF) 101, and 102 in signal paths that lead to differential output signals OUT, XOUT from differential input signals IN, XIN, respectively, through an amplifier (AMP) 10, whereby DC offset is cancelled. In FIG. 5, the highpass filters (HPF) 101, and 102 are provided at input side and output side of the amplifier (AMP) 10, respectively, whereby DC offset components are cut out in double. Other than this manner of DC offset cancellation, the first prior art can be structured with either one of the highpass filters (HPF). There are structured the highpass filters (HPF) 101, and 102 including capacitor elements in the signal paths, and, on demand, further including resistance elements between output side of the capacitor elements and reference voltage. In the circuit structure 110, DC offset is filtered in a form of analog signal and finally cancelled. Circuit structure as such is suitable for non-TDMA system where signals that succeed in terms of time are dealt.
FIG. 6 shows circuit structure 120 directed to second prior art. In the circuit structure 120, differential output signals OUT, XOUT are integrated by an integration circuit 103 and fedback to differential input signals IN, XIN, whereby DC offset is cancelled. The integration circuit 103 is constituted by a comparator 15 and a time constant circuit that is constituted by connecting two couples of a resistance element and a capacitor element (R101 and C101, R102 and C102) between differential input side and differential output side of the comparator 15. Differential output signals OUT, XOUT inputted through the resistance elements R101 and R102 include AC signal components as AC component and DC offset component as DC component. However, the integration circuit 103 integrates the differential output signals OUT, XOUT depending on time constant determined by the two couples of resistance element and capacitor element (R101 and C101, R102 and C102) and only predetermined DC offset components of those signals are feedback to an amplifier (AMP) 10. Although FIG. 6 shows structure that a feedback signal is directly fedback to differential input signals IN, XIN, it is possible to feedback a feedback signal to a point other than the input signals IN, XIN if it is a point capable of adjusting DC offset components of the amplifier (AMP) 10. For example, a feedback signal can be feedback to a bias current source to an input-stage differential pair of the amplifier (AMP) 10. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
It should be noted that the comparator 15 is a circuit that has a predetermined gain and outputs a signal depending on differential signals of differential output signals OUT, XOUT.
FIG. 7 shows circuit structure 130 directed to third prior art. In the circuit structure 130, differential output signals OUT, XOUT are compared at a comparator 15 and differential output signals as comparison result are fedback to an amplifier (AMP) 10 through a lowpass filter constituted by two couples of a resistance element and a capacitor element (R103 and C103, R104 and C104), whereby DC offset is cancelled. The differential output signals OUT, XOUT and the comparison result include AC signal components as AC component and DC offset components as DC components. However, only predetermined DC offset components are extracted by the lowpass filter 104 and fedback to the amplifier (AMP) 10. Different from the case of FIG. 6, FIG. 7 is structured such that a feedback signal is feedback to an internal circuit such as bias current source to an input-stage differential pair of the amplifier (AMP) 10. The circuit structure 130 filters analog signals through the lowpass filter 104 and calculates a correction value of DC offset components. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
FIG. 8 shows circuit structure 140 directed to fourth prior art. In the circuit structure 140, differential output signals OUT, XOUT are compared at a comparator 15 and then, converted into digital signals by an AD converter 107. To these digital signals, digital processing is applied by a digital signal processing circuit (DSP) 108 so as to output correction signals against DC offset components. Since the correction signal is a digital signal, the signal is converted into an analog signal by a DA converter 109 and fedback to an amplifier (AMP) 10. In case a predetermined time slot in a predetermined communication time cycle is set as offset-quantity detecting time like TDMA system, a correction value obtained by signal processing and calculation is stored in the digital signal processing circuit (DSP) 108 or the DA converter 109, whereby DC offset is cancelled. In the circuit structure 140, an analog signal is converted into a digital signal through signal processing and a correction value and then, a correction value of DC offset component is calculated. Circuit structure as such is suitable for TDMA system where a predetermined time slot in a predetermined communication time cycle is provided as offset-quantity detecting time and a correction value of DC offset components in the next communication time cycle is determined during this predetermined time slot.
Furthermore, as communication system of mobile radio communication appliances, different communication systems actually diversify region by region: PDC, a kind of FDMA, is prevailed in Japan whereas GSM, a kind of TDMA, is prevailed in Europe. Furthermore, there has been raised and considered W-CDMA system as the next generation communication system. Therefore, there is possibility that another different communication system will coexist with the W-CDMA system while a transitional period to the next generation communication system. So, it is considered convenient that a single communication appliance is compatible with pluralities of communication system. Due to demand as such, there have been proposed dual-mode-structured receivers capable of coping with both communication system, namely, TDMA system and non-TDMA system. FIG. 9 specifically shows circuit structure capable of changing over switches of a DC offset cancel circuit. In FIG. 9, selection circuits 105 and 106 change over switches like that in case of TDMA system, the DC offset cancel circuit uses the circuit structure 140, whereas in case of non-TDMA system, the DC offset cancel circuit uses the circuit structures 110 and 120 or 130.
However, as for the circuit structure 110, 120 and 130 directed to the first through third prior art, suitable to non-TDMA system, it is necessary to set frequency band of offset components that are to be cancelled to a sufficiently low frequency so that effective signal components in a low frequency band may not be cut out. Therefore, regarding the first prior art, capacity of capacitor elements that constitute the highpass filters (HPF) need to be set to large values so that effective signal components can surely pass there. Furthermore, regarding the second and third prior art, capacity of capacitor elements that constitute the integration circuit 103 or the lowpass filter 104 need to be set to large values so that only offset components can be feedback as correction values. Any of the circuit structure 110 through 130 is likely to need capacitor elements with large capacity. Therefore, there is a fear that a DC offset cancel circuit cannot be structured with compact circuit scale. In other words, this is an obstacle to miniaturization, weight saving, and multi-function design of receivers.
Furthermore, regarding the circuit structure 140 suitable to TDMA system, directed to the fourth prior art, a predetermined time slot in a predetermined communication time cycle is allocated as offset-quantity detecting time where offset quantity is detected without communication. Based on offset quantity detected during this offset-quantity detecting time, offset is cancelled. Accordingly, both communication operation and offset detection operation cannot be conducted successively. That is, there is a fear that the system cannot keep up with transitional fluctuation of offset quantity until the next offset-quantity detecting time.
Furthermore, in case it is intended to provide a dual-mode-structured receiver, as shown in FIG. 9, such a structured receiver must include both DC offset cancel circuit 140 suitable for TDMA system and DC offset cancel circuits 110, 120 or 130 suitable for non-TDMA system so as to switch between those circuits depending on communication system. Therefore, the receiver needs selection circuit 105, 105, 106, 106 for controlling selection of DC offset cancel circuits and control circuit (not shown) for outputting control signals. Addition of such items makes circuit scale large nevertheless miniaturization and weight saving design is nowadays demanded for mobile radio communication appliances such as cellular phone. It is problematic.
Furthermore, in case it is a dual-mode-structured receiver, it is conceivable to use the circuit structure 110, 120, and 130, directed to the first, second, and third prior art, respectively, for TDMA system. However, as described in advance, the circuit structure 110, 120 and 130 need large capacity of capacitor elements. Therefore, in case the circuit structure 110, 120 and 130 are used in TDMA system where a predetermined time slot in a predetermined communication time cycle is allocated to each channel and a signal is received during only this predetermined time slot, rising time of a reception signal takes long in a predetermined time slot. As a result, there arises a fear that the system cannot keep up with high-speed operation.
Furthermore, for a dual-mode-structured receiver, the circuit structure 140 suitable to TDMA, directed to the fourth prior art, cannot cope with non-TDMA system. Since the circuit structure 140 is structured for detecting offset quantity in a predetermined time slot allocated as offset-quantity detecting time, it is impossible to stop communication for offset quantity detection and to secure particular time. Thus, the circuit structure 140 cannot cope with non-TDMA system that requires successive communications.
Accordingly, it is an object of the present invention to provide a DC offset cancel circuit capable of canceling DC offset regardless TDMA system and non-TDMA system, with simple circuit structure, and applicable to dual-mode-structured receivers.
To achieve the object, according to one aspect of the present invention, there is provided a DC offset cancel circuit for canceling DC offset components between signals that constitute output signals having at least two phases different to each other when the output signals are outputted from a signal processing section, the DC offset cancel circuit comprising: a phase conversion section for converting at least any one of the output signals into at least any one of phase-converted signals phase of which is same as a phase of at least any one of other output signals; and a comparator section for comparing one of the other output signals and the phase-converted signal and for feeding-back a comparison result to the signal processing section.
In the DC offset cancel circuit directed to one aspect of the present invention, at least any one of the output signals is converted into at least any one of phase-converted signals phase of which is same as phase of at least any one of other output signals. Since one of the phase-converted signals and one of the other output signals are in same phase, DC components of these signals are compared and a comparison result is fedback to the signal processing section.
Thereby, even if DC offset components are included between two output signals phases of which are different from each other, a phase of one of the output signals is converted to same as that of other output signal to be compared, and phase components between these two signals are cancelled out each other. Thereby, DC offset components as DC components between the two signals can be compared. In the DC offset cancel circuit directed to one aspect of the present invention, DC offset can be cancelled as follows: (1) signal components of two signals phases of which are different from each other are cancelled out each other; (2) DC offset components as DC components are extracted; (3) the DC offset components are compared; and (4) a comparison result is fedback to the signal processing section for canceling DC offset. DC offset cancel operation such as above can be done without conducting filtering integration operation using a capacitor element, or without setting a predetermined time slot as offset-quantity detection time using a predetermined signal processing circuit.
According to another aspect of the present invention, there is provided a DC offset cancel circuit for canceling DC offset components between two differential output signals when the differential output signals are outputted from a signal processing section, the DC offset cancel circuit comprising: a first differential amplifier to which one of the differential output signals is inputted; a second differential amplifier to which other one of the differential output signals is inputted; a reference voltage generating section that inputs reference voltage to the first differential amplifier and the second differential amplifier; and a comparator that compares a first output signal and a second output signal outputted from the fist differential amplifier and outputted the second differential amplifier, respectively.
In the DC offset cancel circuit directed to another aspect of the present invention, one of the differential output signals outputted from the signal processing section and the reference voltage outputted from the reference voltage generating section are inputted to the first differential amplifier. One of the differential output signals is differentially amplified with reference to a reference voltage through the first differential amplifier and this differentially amplified signal is outputted from the first differential amplifier as a first output signal. Furthermore, other one of the differential output signals outputted from the signal processing section and the reference voltage outputted from the reference voltage generating section are inputted to the second differential amplifier. Other one of the differential output signals is differentially amplified with reference to a reference voltage through the second differential amplifier and this differentially amplified signal is outputted from the second differential amplifier as a second output signal. The comparator compares the first output signal and the second output signal and then, a comparison result is fedback to the signal processing section.
Thereby, the first differential amplifier and the second differential amplifier can inverse phase of differential output signals in same phase or opposite phase with reference to the reference voltage. Therefore, with respect to either one of the first output signal and the second output signal, phase of one of them is inverted with reference to the reference voltage so that the first output signal and the second output signal can be set in same phase in case there is a 180-degree phase difference between differential output signals. Without capacitor element and a predetermined signal processing circuit, employment of the first and second differential amplifiers works out as DC offset canceller such that phase components between the first output signal and the second output signal are cancelled out each other, DC offset components equivalent to DC components are extracted, the extracted DC offset components are compared, and the comparison result is feedback to the signal processing section so as to cancel DC offset.
The DC offset cancel circuit directed to another aspect of the present invention thus can be constituted by the first and second differential amplifiers without employing a capacitor element. Accordingly, DC offset cancel circuits employing a capacitor element sometimes require large-volume capacitor elements so as to set frequency band of offset components to sufficiently low frequency band, which is to prevent effective signal components from being cut out. On the other hand, the DC offset cancel circuit directed to another aspect of the present invention can be structured with compact circuit scale, whereby such a compact scaled DC offset cancel circuit can realize miniaturization, weight saving, and multi-function design of receivers.
Furthermore, in case a predetermined time slot is set as offset-quantity detection time, the DC offset cancel circuit directed to another aspect of the present invention can always detect offset quantity, different from a case of using a signal processing circuit that detects offset quantity during the predetermined time slot only. Thereby, offset quantity can be detected continuously even while intermittence periods between predetermined time slots, which are not set as offset-quantity detection time. This is preferable because the DC offset cancel circuit can keep up with transitional fluctuation of offset quantity.
Furthermore, since no capacitor element is employed, the DC offset cancel circuit directed to another aspect of the present invention can keep up with high-speed signals even if offset quantity is detected during the predetermined time slot only. Still further, since no signal processing circuit is employed, the DC offset cancel circuit can cope with offset-quantity detection operation that is conducted continuously in terms of time. Accordingly, this DC offset cancel circuit can be applied to both communication systems, namely, TDMA and non-TDMA. It is applicable to dual-mode-structured receivers that are compatible with the both communication systems and such receivers can be realized with compact circuit scale.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.
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USPTO Backgrounds