1. Technical Field
The present invention relates to a semiconductor device having a spiral inductor and a method for manufacturing thereof.
2. Related Art
In a radio frequency large scale integrated circuit (LSI), a spiral inductor may be mounted on the LSI, in order to employ thereof for a high frequency circuit such as LC voltage controlled oscillator (LCVCO). In semiconductor devices having a spiral inductor mounted thereon, a generation of a noise due to a coupling of the spiral inductor formed of metallic interconnects with a silicon substrate may be a problem, and a countermeasure thereof may be a provision of a shielding between the inductor and the silicon substrate.
Typical technologies for such semiconductor device include a technology described in Japanese Patent Laid-Open No. 2001-230,375. FIGS. 7 to 10 are schematic diagrams, illustrating a spiral inductor in a semiconductor device described in Japanese Patent Laid-Open No. 2001-230,375. FIG. 7 is a plan view, showing a configuration of the semiconductor device including the spiral inductor. FIG. 8 is a cross-sectional view of the semiconductor device shown in FIG. 7 along line A-A′. FIG. 9 is a schematic diagram, selectively showing layers of a polysilicon 205, a side wall 206 and a metal silicide 208, which are also shown in FIG. 7. Further, FIG. 10 is a schematic diagram, selectively showing a first layer metallic interconnect 211, a second layer metallic interconnect 214, a contact plug 210 and a via plug 213, which are also shown in FIG. 7.
This semiconductor device has a configuration including a spiral inductor composed of the first layer metallic interconnect 211, the second layer metallic interconnect 214 and the via plug 213 formed on the p-conductivity type silicon substrate 201. The first layer metallic interconnect 211 is coupled to a source/drain region 207 of a metal oxide semiconductor field effect transistor (MOSFET) via a contact plug 210 embedded in a contact hole that extends through the first insulating interlayer 209. The conductivity type of the source/drain region 207 is n-type.
Further, in order to shield the coupling of the spiral inductor with the silicon substrate 201 to provide a inhibition in the generation of noise, a polysilicon 205 is provided between the spiral inductor and the silicon substrate 201. A metal silicide 208 is provided on the upper portion of the polysilicon 205. A cut 215 for suppressing a generation of eddy current due to an influence of the inductor is provided in the polysilicon 205 and the metal silicide 208 disposed on the upper portion thereof. Further, the layout of the device is presented, such that a reduced shielding ability between the inductor and the silicon substrate 201 caused by the presence of the cut 215 is compensated by silicidizing the surface of the silicon substrate 201 so as to conform the cutout region to provide a metal silicide 208. In this configuration, an element isolating oxide film 202 is employed for an insulating film between the polysilicon 205 and the silicon substrate 201. Shallow trench isolation (STI) technology is generally employed for forming the element isolating oxide film 202.
FIG. 11 and FIG. 12 are schematic diagrams for describing another example of a spiral inductor disclosed in Japanese Patent Laid-Open No. 2001-230,375. FIG. 11 is the plan view, selectively showing layers of a polysilicon 205, a side wall 206 and a metal silicide 208 in the another example. Further, FIG. 12 is a cross-sectional view of the spiral inductor region shown in FIG. 11 along line A-A′. This configuration is distinctive from the device shown in FIGS. 7 to 10, in terms of employing a gate oxide film 204, which is provided as an insulating film between the polysilicon 205 and the silicon substrate 201 so as to contact with the upper portion of the p-type well 203.
In the meantime, Japanese Patent Laid-Open No. 2002-110,908 describes a spiral inductor having a configuration of providing a dummy element region in an inductor-forming region.
USPTO Backgrounds
USPTO Backgrounds