1. Field of the Invention
The present invention generally relates to memory cells for high integration density integrated circuits such as dynamic random access memories (DRAM) cells and integrated circuits which combine such cells with high performance logic circuit transistors on the same semiconductor chip.
2. Description of the Prior Art
Both improved performance and increased manufacturing economy can potentially be achieved by increasing integration density of elements (e.g. transistors, capacitors and the like) of integrated circuits as well as, in most cases, reduction of the size of those elements and the circuits they comprise. Therefore, there are currently substantial pressures to decrease both size and spacing of integrated circuit structures.
At least one lithographic process is generally required to establish the size and location of some of the elements on an integrated circuit chip and at any given time, several lithographic feature size regimes are in use or under development to establish processes which will provide economically acceptable manufacturing yields for a given application or market. For example, a half-micron minimum lithographic feature size may be the standard for products intended for the general public while a quarter-micron regime may be the standard for high-performance products which command a premium price and a sub-one-tenth-micron minimum feature size regime, sometimes referred to as a sub-100 nm regime may be under development to increase manufacturing yield while producing some amount of product for extremely demanding state-of-the-art applications where the need for performance that can not be otherwise obtained can offset costs of a relatively low manufacturing yield.
It should be understood that some designs for elements and circuits can be scaled from a given feature size regime to a smaller feature size regime while others cannot. For those that can be scaled in such a manner, it is customary to refer to the area of a given type of circuit or design by the number of minimum feature size areas, F2 (F being the effective resolution of the system or the minimum feature dimension that can be resolved in a lithographic exposure), it requires. For example, modern DRAM cell designs generally require a minimum area of 6 to 12 F2 on a chip, assuming that processes exist to carry out the fabrication of the design for a given F. At the same time, it should be recognized as a goal for a given F to be able to design and economically fabricate a given type of circuit in the same minimum number of F2 areas required for a circuit having the same function at a larger minimum feature size or value of F, particularly where a given circuit design cannot be directly scaled.
At the same time, however, new structures are being developed to reduce the minimum area required for a given type of circuit. For example, to reduce a DRAM cell area from about 12F2 to 6F2, the transistor gates (there being one transistor and one capacitor per cell in current designs and DRAM cells generally being produced at extremely high density) must be spaced apart by less than 2F and generally by only 1F. Due to such short distances, mask alignment cannot be used to form a contact between gates. Therefore, recently developed so-called borderless contacts are generally employed to make a contact between the gates. In general, borderless contacts exploit differential etch rate techniques in an area that overlaps two materials (often SiO2 and SiN) in order to form a sub-lithographic size structure extending orthogonally to the chip surface.
Another new structure that enables a small DRAM cell size is a non-planar (vertical) access transistor. In this structure, the access transistor is formed on the walls of a trench or pillar. Such a transistor can have a gate length larger than 1F while maintaining a small wafer surface footprint. Therefore, the cell size scaling is effectively decoupled from the transistor channel length. This feature is important because of the existence of a lower channel length limit imposed by the charge retention requirement of memory cells in the array.
In DRAM circuits the retention of the stored charge can be affected by transistor leakage and capacitor size. That is, as capacitor size is reduced, the amount of stored charge representing stored data is correspondingly reduced and leakage through the transistor when the off-resistance is reduced may corrupt data unless refresh rates are increased; increasing, for example, the power consumption.
Non-planar transistors and borderless contacts are often combined in the same cell for greater density and charge retention characteristics in memory designs currently of interest. However, developing transistors at such small sizes and spacings and the use of techniques and structures such as borderless contacts and non-planar transistors generally precludes the development of other structures that may be important to transistor switching performance even though reduced transistor performance may be tolerable in some applications.
High performance logic transistors exhibit very high switching speed. Several techniques have been developed for increasing their performance but many be incompatible with high density memory structures described above. In order to achieve a very fast switching speed, logic transistors (e.g. transistors used in logic switching applications, as distinguished from isolation-type access transistors such as is employed in DRAM arrays) have a very thin gate dielectric, a heavily doped dual work function gate, carefully engineered source and drain impurity implantation profiles and a sub-lithographic (typically about 0.7-0.5F) trimmed gate.
Even with currently known designs which can be fabricated at sub-100 nm feature sizes, array transistors and logic transistors have much different fabrication requirements which have been considered as incompatible at least to the extent of requiring compromise of performance and/or operating margins to form both types of transistors on a single chip, if possible at all. Specifically, borderless contacts of array transistors require a thick insulator (generally nitride) while similar insulating materials are used as sidewalls only for controlling extension and possibly halo implants and the like. Similarly, array transistors and logic transistors require different sheet resistance of their gates. In the array, where there are long word lines, the gate sheet resistances should be minimized by creating a highly conductive metal layer on top of the gate electrode. On the other hand, relatively short logic gates use a silicide layer as their gate conductors. Further, the silicidation process results in a low source and drain contact resistance which is necessary in logic transistors to increase their switching speed.
Another area of incompatibility between array and logic transistor designs is spacer geometry even though spacers for array and logic transistors may be of the same material. Logic transistors imply spacers at the sides of the gates to control the location of implant and/or halo implants which control short channel effects and to separate the extension/halo implants from the source/drain implants (which are generally of different energy, energy spread and concentration). A single spacer thickness may suffice for NMOS transistors which use an impurity with relatively low diffusivity at high temperatures (e.g. arsenic) which limits the diffusion rate during subsequent heat treatment. However, to obtain desired dopant concentration profiles in PMOS transistors which employ an impurity with relatively high diffusivity at high temperatures (e.g. boron) and higher diffusion rates, at least two spacers, often of differing thickness, are generally required. Even more spacers may be necessary for both NMOS and PMOS transistors, depending upon desired electrical chartacteristics. On the other hand, as alluded to above, for array transistors located with a 1F separation, a total sidewall spacer thickness well below 0.5F is required in order to form a borderless contact therebetween.
Moreover, the silicidation alluded to above and required by the logic transistors for high performance requires metal deposition at a late stage in the fabrication process while the metal is already in place for the array transistors. Heat treatment after metal deposition which is necessary to the silicidation process can also destroy array transistors which are spaced from each other by a distance comparable the the silicidation depth (e.g. where metal diffuses into silicon and alloys therewith).
In yet another area of incompatibility is the electrical thickness (physical thickness multiplied by the ratio of the dielectric constant of silicon oxide to that of the gate dielectric) of the gate dielectric. High speed logic transistors have an extremely thin gate dielectric which is often made from a high dielectric constant (high-k) material as compared with thermal silicon oxide. Such high-k material can be a nitrided silicon oxide, silicon nitride, various metal oxides (e.g. aluminum oxide, hafnium oxide, zirconium oxide, and the like), certain insulating metal nitrides (e.g. aluminum nitride) and their various combinations (e.g. laminates and composites). On the other hand, memory access transistors have a relatively thick gate dielectric/insulator (typically a thermal silicon oxide) in order to minimize leakage in the xe2x80x9coffxe2x80x9d state.
Furthermore, the gate depletion effect in polycrystalline silicon gates becomes very important for ultra-thin gate insulators of logic transistors. Indeed, if the gate electrode doping level is around 1020/cm3, the depletion layer in a doped gate electrode is approximately 10-11 Angstroms. This would effectively thicken the ultra-this gate dielectric by 3-4 Angstroms of equivalent oxide thickness (EOT). With the state of the art gate insulators of 12-15 Angstroms, the depletion layer can degrade the performance by 20%-30%. Therefore, it is highly desirable to increase the gate electrode doping of logic transistors to the range of 5xc3x971020/cm3 to 2xc3x971021/cm3. Such high doping levels are not required (and, hence, not used) in the memory access transistors.
In summary, there are numerous points of incompatibility between array transistor structures and logic transistors which prevent or greatly complicate the development of high performance of logic transistors and extremely close spacing between array transistors on the same chip. At the present state of the art where sub-100 nm feature size regimes are being developed, the trade-off is so severe that one or the other must be substantially sacrificed; limiting the memory capacity of a chip or severely reducing performance of logic switching transistors. Additionally, the process complexity must not be increased to the point of compromising manufacturing yield or economy in order to produce such effects while supporting relatively high volume production.
It is therefore an object of the present invention to provide a high capacity, high performance memory array which may be embedded in a circuit including very high performance logic transistors consistent with limited process complexity and high manufacturing yield.
It is a further object of the invention to provide a manufacturing technique which decouples the production of desirable design features of array transistors and high performance logic transistors formed on a common chip or wafer.
It is yet another object of the invention to provide a manufacturing technique by which silicidation can be masked and thus controlled in array transistors of a memory array when integrated with other structures requiring late-process formation of silicide.
In order to accomplish these and other objects of the invention, a semiconductor integrated circuit having array transistors in memory cells and logic transistors is provided wherein the array transistors have a spacing of the minimum feature size, F, the memory cells having an area of 12F2 or less and the logic transistors have an effective channel length of 0.7F or less, an effective gate dielectric thickness of twenty Angstroms or less, a dual work function semiconductor gate with maximum depletion thickness of 1.5 Angstroms of equivalent oxide thickness in the inversion mode and a source drain contact resistance of 3xc3x9710xe2x88x928 or less.
In accordance with another aspect of the invention, a semiconductor integrated circuit is provided including array transistors having metal gate conductors encapsulated by a diffusion barrier including a thick cap insulator and a borderless source/drain contact at a spacer adjacent said thick cap insulator, and logic transistors having silicided contacts, extension implants and a dual work function semiconductor gate having an impurity concentration of greater than 4xc3x971020.
In accordance with a further object of the invention, a method of making an integrated circuit is provided including steps of forming a dielectric layer on a semiconductor substrate wherein the dielectric layer includes a gate dielectric region, forming a polysilicon layer on the dielectric layer and the gate dielectric region, removing the polysilicon layer in an array area of the integrated circuit, forming a plurality of layers including an insulator material layer on a remaining portion of the polysilicon layer and on portions of the gate dielectric such that recesses remain where polysilicon has been removed, forming a mask in the recesses, removing the plurality of layers and the mask to a surface of said polysilicon, patterning the polysilicon and a remaining portion of the plurality of layers, and completing the integrated circuit whereby thick layers and, later, tall structures of differing materials are formed.
USPTO Backgrounds
USPTO Backgrounds