As the semiconductor industry introduces new generations of integrated circuits (IC's) having better performance and more functionality, the density of the circuit elements that form the integrated circuits is increased, and the dimensions, sizes, and spacing between the individual components or elements are reduced. While in the past such reductions were limited mainly by the ability to define the structures photo-lithographically, device geometries having smaller dimensions created new limiting factors. For example, for any two adjacent conductive paths, as the distance between the conductors decreases, the resulting capacitance (a function of the dielectric constant (k) of the insulating material divided by the distance between conductive paths) increases. The increased capacitance results in increased capacitive coupling between the conductors, increased power consumption, and an increase in the resistive-capacitive (RC) time constant. Therefore, continual improvement in semiconductor IC performance and functionality is dependent upon the using of low-k dielectric materials.
The using of low-k dielectric materials introduces the requirement of diffusion barriers, which have the function of preventing copper from diffusing into the low-k dielectric layers. Tantalum nitride (TaN) has a good diffusion-retarding ability, and was commonly used to form barrier layers. The resistivity of TaN, however, is about one order higher than that of tantalum (Ta). Accordingly, Ta on TaN (or titanium (Ti) on titanium nitride (TiN) was typically used to form barrier layers. TaN/Ta and TiN/Ti barrier layers suffer from drawbacks. The metallic Ta and Ti do not bond well to the non-metallic silicon or silicon oxide substrate, and TaN and TiN do not bond well with copper. As a result, delamination, peeling, and void may occur during the chemical mechanical polish step, which is used for forming copper interconnect structures that are located on the TaN/Ta or TiN/Ti barrier layers.
USPTO Backgrounds
USPTO Backgrounds