This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-005561, filed Jan. 12, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to, for example, a semiconductor device and more specifically to an electric fuse circuit that is used for setting an operation of the semiconductor device, setting an address of a redundancy circuit, and the like.
2. Description of the Related Art
A fuse circuit is used for setting an operation of a semiconductor device, an address of a redundancy circuit, and the like. A laser fuse that is blown by a laser beam has been used as the fuse circuit; however, its programming is complicated. When a defective memory cell is detected in a process of testing a semiconductor device, it cannot be replaced with a spare cell at once. After the testing, a wafer is carried to another device and in this device a fuse is blown by a laser beam, thereby replacing the defective memory cell with a spare cell. Thus, it takes time to program the laser fuse.
An electrically programmable electric fuse that is easily programmed is developed.
FIG. 11 shows an example of a general electric fuse circuit.
The electric fuse circuit comprises a voltage generation circuit 101, a plurality of fuse circuits 1021 and 1022 to 102n, a first switch circuit 103, a second switch circuit 104, a detection circuit 105, a first common wire 106, a second common wire 107, and a pad 108. The fuse circuits 1021 and 1022 to 102n and the first and second switch circuits 103 and 104 are provided for each bank of a semiconductor device and used for setting an address of a redundancy circuit.
The voltage generation circuit 101 generates a high voltage VBP of about 9V in response to a program signal PRGM when a fuse element is programmed. The circuit 101 is connected to the first switch circuit 103 through the first common wire 106.
The first switch circuit 103 includes N-channel MOS transistors N10 and N11, P-channel MOS transistors P10 and P11, a NAND circuit ND1, and an inverter circuit IV1 supplied with an output signal of the NAND circuit ND1. The input terminal of the NAND circuit ND1 is supplied with the program signal PRGM and bank select signal BSS. A connection node between the transistors P10 and N10 of the first switch circuit 103 is connected to one end portion of each of the fuse circuits 1021 and 1022 to 102n.
The fuse circuits 1022 to 102n each have the same arrangement as that of the fuse circuit 1021. The fuse circuit 1021 includes a fuse element FS, N-channel MOS transistors N1 and N2, and a latch circuit LT. The fuse element FS includes, for example, a trench capacitor that is applied to, e.g., a dynamic RAM. The fuse element FS increases in resistance before programming and decreases in resistance after programming. The transistor N1 is a barrier transistor for protecting the latch circuit LT and its gate is always supplied with a high voltage VPP. The transistor N2 selects a fuse circuit in response to an address signal ADDi. The latch circuit LT holds data that is read out of the fuse element in read mode.
The second switch circuit 104 includes N-channel MOS transistors N20 and N21, a NAND circuit ND2, and an inverter circuit IV2 supplied with an output signal of the NAND circuit ND2. The input terminal of the NAND circuit ND2 is supplied with a verify signal VRFY generated in verify mode and the bank select signal BSS. A connection node between the transistors N20 and N21 is connected to the other end portion of each of the fuse circuits 1021 and 1022 to 102n.
One end portion of the detection circuit 105 is connected to a pad 108 and the other end portion thereof is connected to the second switch circuit 104 through the second common wire 107. The detection circuit 105 detects a current flowing through the fuse element FS in verify mode.
When a defective memory cell is found in a bank (not shown) in a manufacturing process of a semiconductor device, the fuse element FS is programmed in order to replace the defective memory cell with a spare memory cell.
When the fuse element FS is programmed, the program signal PRGM is activated to a high level. Then, the voltage generation circuit 101 generates a high voltage VBP.
In the first switch circuit 103, the program signal PRGM and bank select signal BSS are set at a high level. The level of the output signal of the NAND circuit ND1 is therefore low. The transistor N11 that is supplied with the output signal through the inverter circuit IV1 turns on, and the transistor N10 that is supplied with the output signal turns off. Accordingly, the transistor P10 turns on, while the transistor P11 turns off.
In the second switch circuit 104, the verify signal VRFY is set at a low level and the bank select signal BSS is set at a high level. The level of the output signal of the NAND circuit ND2 is therefore high. The transistor N20 that is supplied with the output signal via the inverter circuit IV2 turns off, while the transistor N21 that is supplied with the output signal turns on.
When the fuse circuit 1021 is selected in response to the address signal ADDi in the state as described above, the high voltage VBP generated from the voltage generation circuit 101 is supplied through a path including the first common wire 106, the transistor P10 of the first switch circuit 103, the fuse element FS, the transistors N1 and N2, the transistor N21 of the second switch circuit 104, and the ground, as indicated by a broken line A. Thus, a high voltage is applied to the fuse element FS, and the fuse element is programmed to low resistance.
Then, the state of the programmed fuse element is verified. In the verify operation, the program signal PRGM is set to a low level and the verify signal VRFY is set to a high level. The bank select signal BSS is also set to a high level.
When the program signal PRGM is at a low level, the level of the output signal of the NAND circuit ND1 of the first switch circuit 103 becomes high. The transistor N10 that is supplied with the output signal turns on, while the transistor N11 that is supplied with the output signal through the inverter circuit IV1 turns off. Accordingly, the transistor P11 turns on and the transistor P10 turns off.
The level of the output signal of the NAND circuit ND2 of the second switch circuit 104 becomes low in response to the verify signal VRFY and bank select signal BSS. Thus, the transistor N21 that is supplied with the output signal turns off, while the transistor N20 that is supplied with the output signal through the inverter circuit IV2 turns on.
In this state, a voltage for verification, which is lower than the program voltage, is applied to the pad 108. Thus, a current flows through a path including the detection circuit 105, the transistor N20 of the second switch circuit 104, the transistors N2 and N1, the fuse element FS, the transistor N10 of the second switch circuit 103, and the ground, as indicated by a thick broken line B. The detection circuit 105 detects a value of the current and accordingly the state of the fuse element FS is verified.
In order to program the fuse element FS with reliability, it is necessary to apply a high voltage of about 9V to the fuse element FS and pass a current of several milliamperes therethrough. To achieve this, the size of the transistors P10 and N21 composing the first and second switch circuits 103 and 104, respectively, e.g., the channel width thereof is set larger than that of another transistor. Further, the size of the transistors N1 and N2 in each fuse circuit needs to increase.
In verify mode, a current flows through the transistor N20 of the second switch circuit 104 and the transistor N10 of the first switch circuit 103. It is desirable that these transistors increase in size in order to improve the operating margin of verification.
The foregoing the general electric fuse circuit requires a plurality of large-sized transistors in order to program and verify the fuse element. The area of the transistors occupied in the chip becomes large and the size of the chip is difficult to reduce. Consequently, a semiconductor device that is capable of programming and verifying a fuse element with reliability without using any large-sized transistors, is desired.
According to an aspect of the invention, there is provided a semiconductor device comprising: a fuse circuit having a first end portion and a second end portion, the fuse circuit being programmed electrically; a voltage generation circuit connected to the first end portion of the fuse circuit, the voltage generation circuit generating a first voltage in program mode to write data to the fuse circuit, a second voltage in verify mode to verify the data written to the fuse circuit, and a third voltage in read mode to read the data from the fuse circuit; and a first transistor connected to the second end portion of the fuse circuit, the first transistor turning on in the program mode.
USPTO Backgrounds
USPTO Backgrounds