Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include, but are not limited to, these exemplary devices and further can include devices that are only partially programmable.
Any IC, whether or not a PLD, is affected by jitter. Jitter refers to the deviation in, or displacement of, some aspect of the pulses in a digital signal. There are a variety of different types of jitter. For example, one type is peak-to-peak jitter. Typically, peak-to-peak jitter is defined as the difference between the earliest edge of a pulse and the latest edge of a pulse. This technique for measuring jitter is generally accepted and provides what is usually considered the “worst case” jitter. Measuring jitter in this manner, however, may lead to situations in which jitter is overstated. Overstating jitter can influence many aspects of timing analysis and design of ICs. This may lead to situations in which implementation tools are overly-constrained, or overly safe, in terms of delay estimation to overcome the effects of jitter.
USPTO Backgrounds
USPTO Backgrounds