The present invention relates generally to the field of the fabrication of semiconductor devices, and more particularly to the fabrication of bulk fins with vertical sidewall profiles.
Field-effect transistors (FETs) can be semiconductor devices fabricated on a bulk semiconductor substrate or on a silicon on insulator (SOI) substrate. FET devices generally consist of a source, a drain, a gate, and a channel between the source and drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the field or gate oxide. A voltage drop generated by the gate across the oxide layer induces a conducting channel between the source and drain, thereby controlling the current flow between the source and the drain. Integrated circuit designs use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) for logic functions.
A FinFET is a non-planar FET. The “fin” is a narrow, vertical base channel between the source and the drain. The fin is covered by a thin gate oxide and surrounded on two or three sides by an overlying gate structure.
USPTO Backgrounds
USPTO Backgrounds