The present invention relates generally to magnetic memory circuits, and more particularly relates to an improved architecture for cross point magnetic random access memory (MRAM).
In conventional magneto-resistive memory architectures, writing individual memory cells without also writing adjacent or other non-intended cells, referred to as write selectivity, remains a problem. Typically, writing a magnetic tunnel junction (MTJ) memory cell, an exemplary magneto-resistive memory cell, involves passing electrical currents simultaneously through a bit line (generally defined along a y axis) and a word line (generally defined along an x axis) at the intersection of which the intended MTJ cell resides. Thus, selected memory cells in an MRAM are written by the coincidence of x-oriented and y-oriented magnetic fields. The selected MTJ cell will experience a magnetic field which is the vector sum of the magnetic fields created by the word and bit line currents. All other MTJ cells that share the same bit line or word line as the selected MTJ cell will be half-selected and will thus be subjected to either bit line or word line magnetic fields, respectively. An MTJ cell receiving no bit line or word line magnetic field will be unselected.
Variations in the geometry (e.g., shape or size) of an MTJ memory cell can give rise to variations in magnetic thresholds of the MTJ cells which are so large that it is virtually impossible to write a selected cell without also arbitrarily switching some of the half-selected cells, thus placing the reliability and validity of the stored data in question. There may also be other factors, for example, related to manufacturing uncertainties and intrinsic magnetic material variability (e.g., temperature and processing variations) such that cell to cell magnetic response variations can be significantly large. This magnetic response variability from cell to cell adversely impacts the write select margin of the MRAM device. Additionally, the spontaneous switching of an MTJ cell when it is subjected to repeated magnetic field excursions much smaller than its nominal switching field, either by an effect known as xe2x80x9ccreepxe2x80x9d or by thermal-activated switching, narrows the acceptable write select margin even further thereby making the need for greater write selectivity of individual MTJ memory cells even more imperative.
A write disturb is generally defined as an unintended change in the logical state of an unselected memory cell while a selected cell, which is targeted for a write operation, is written to a new logical state. The avoidance of write disturbs is a critical issue for MRAM devices. In conventional MRAM, selected memory cells are written by the coincidence of x-oriented and y-oriented magnetic fields, as stated above. Ideally, half-selected memory cells receive only one of the two fields. The force of only one field on a magnetic memory cell is typically not enough to change the polarity, and therefore the state, of the cell. In practice, however, stray magnetic fields (e.g., emanating from adjacent word lines, etc.) may combine to make a half-selected memory cell susceptible to write disturbs. This is an undesirable characteristic which is inherent in a conventional cross-point write scheme.
A major hurdle to the realization of practical MRAM architectures has been the problem of write selectivity. The avoidance of write disturbs in cross point MRAM has, thus far, only been addressed by Reohr, et al., in U.S. Pat. No. 6,335,890. However, the prior art does not provide a means to minimize the stray magnetic fields generated as a byproduct of delivering the hard axis field to the selected memory cells. Moreover, since the prior art only addresses a write operation, it does not provide an adequate circuit structure for maintaining an equipotential voltage, necessary for subsequent read operations, on all word lines except those required to carry current to the word line corresponding to the selected memory cells.
There exists a need, therefore, in the field of magnetic memory devices for improved write selection techniques which can be readily adapted to a cross point MRAM architecture as well as other alternative magnetic memory architectures.
The present invention provides techniques for effectively writing memory cells in an MRAM. By selectively controlling the path of the write current flowing in the cross point MRAM so that the write current traverses a subset of word lines in the MRAM, stray magnetic field interaction with unselected memory cells in the array is substantially reduced. In this manner, a write selectivity of the cross point MRAM is advantageously improved. Moreover, the write current only affects the voltage on a subset of word lines involved in the write operation, leaving the bulk of the word lines at an equipotential voltage as is necessary for a read operation.
In accordance with one embodiment of the invention, a write circuit for selectively writing one or more magnetic memory cells in an MRAM includes at least one programmable current source couplable to one or more global word lines in the MRAM, the programmable current source including an input for receiving a first control signal and an output, the programmable current source generating at least a portion of a write current at the output having a magnitude which varies in response to the first control signal. The write circuit further includes a plurality of current sinks, each current sink being couplable to one or more global word lines in the MRAM, each current sink including an input for receiving a second control signal, each current sink returning at least a portion of the write current in response to the second control signal. A controller operatively coupled to the at least one programmable current source and the plurality of current sinks is operative to generate the first and second control signals and to selectively distribute the write current across a plurality of global word lines in the MRAM so that stray magnetic field interaction between selected memory cells and half-selected and/or unselected memory cells in the MRAM is minimized.
USPTO Backgrounds
USPTO Backgrounds