There is currently demand for high speed, high capacitance capacitors for use in integrated circuit semiconductor devices. The speed of a capacitor can be increased by reducing the resistance of the capacitor electrodes thereby decreasing the frequency dependency thereof. The capacitance of a capacitor can be increased by reducing the thickness of the dielectric layer between the capacitor electrodes and/or increasing the dielectric constant of the dielectric layer. The capacitance of a capacitor can also be increased by increasing the surface area of the capacitor electrodes.
Integrated circuit capacitor structures include metal oxide semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulatorpolysilicon (PIP) capacitors, metal-insulator-metal (MIM) capacitors. In MOS, PN, and PIP capacitors, single crystal silicon and/or polycrystalline silicon are used to provide at least one of the capacitor electrodes. The use of silicon as a capacitor electrode, however, may make significant reductions in electrode resistance difficult to obtain thus making higher speed capacitors difficult to obtain. Accordingly, thin film metal-insulator-metal (MIM) capacitors have been used to provide which speed capacitors because the MlM structure can provide relatively low resistance capacitor electrodes. Metal-insulator-metal capacitors are also frequently used in accurate analog semiconductor devices because MIM capacitors have a relatively low capacitance variation as well as desirable electrical characteristics over a broad range of voltages and temperatures.
In addition, multi-level wiring processes have been developed to provide high levels of integration in integrated circuit devices. Accordingly, the metal electrodes of a MIM capacitor can be formed during the formation of multiple wiring layers.
FIGS. 1A-1E are cross-sectional views illustrating steps of a method of making a thin film capacitor according to the prior art. As shown in FIG. 1A, a field oxide layer 12 defines active and isolation regions of the silicon substrate 10. A first insulating layer 14 is formed on the silicon substrate 10 and the field oxide layer 12. The insulating layer 14 insulates structures previously formed on the substrate 10 and selectively provides contact to these lower structures through contact holes. An aluminum layer is deposited on the first insulating layer 14 and photolithographically patterned to provide the lower capacitor electrode 16. Wiring structures can also be provided on the insulating layer 14 simultaneously with the steps of forming and patterning the lower capacitor electrode 16.
A second insulating layer 18 is formed on the lower capacitor electrode 16 and on the first insulating layer 14 as shown in FIG. 1B. The photoresist layer is deposited on the insulating layer 18 and exposed and developed to provide the photoresist mask 19 having the window 20 therein. The window 20 exposes a portion of the insulating layer 18 opposite the lower capacitor electrode 16.
The exposed portion of the insulating layer 18 is selectively etched using a dry etch step wherein the patterned photoresist mask 19 acts as an etch mask. A contact hole 21 is thus formed in the insulating layer 18, and the photoresist mask 19 is removed as shown in FIG. 1C. A surface portion of the lower capacitor electrode 16 is thus exposed through the contact hole 21.
An oxide layer is then grown on the exposed surface of the lower capacitor electrode 16 and on the exposed surfaces of the insulating layer 18 as shown in FIG. 1D. This oxide layer thus provides a capacitor dielectric layer 22 on the exposed portion of the lower capacitor electrode 16. If the lower capacitor electrode 16 is over etched during the dry etch step used to form the contact hole 21, however, the exposed surface of the lower capacitor electrode may become uneven as shown in FIG. 1D. In particular, uneven portions of the lower capacitor electrode 16 may not be completely covered by the capacitor dielectric layer 22 as indicated by reference number 23. Accordingly, a short circuit may result between the lower capacitor electrode 16 and an upper capacitor electrode formed on the capacitor dielectric layer 22. As shown in FIG. 1E, a metal layer is formed on the capacitor dielectric layer 22 and patterned to provide the upper capacitor electrode 24. Incomplete coverage of the exposed surface of the lower capacitor electrode 16 by the capacitor dielectric layer 22 may result in a short circuit between the two capacitor electrodes as indicated by reference numeral 23.
In other words, the step coverage of the capacitor dielectric layer 22 may not be sufficient to cover unevenness in the exposed surface of the lower capacitor electrode 16 resulting from an over etch during the step of forming the contact hole. In particular, the combination of the relatively steep sidewalls of the insulating layer 18 on the lower capacitor electrode 16 and the unevenness of the surface of the lower capacitor electrode 16 may make it difficult to cover the exposed surface of the lower capacitor electrode with a thin dielectric layer. The resulting risk of short circuiting between the upper and lower capacitor electrodes may reduce manufacturing yield and reliability of the capacitor structure.
Accordingly, thin film capacitors of the prior art have been fabricated with dielectric layers having thicknesses greater than 1,000 Angstroms. For example, delayed open Japanese Patent Application No. 5-299582 discusses the use of a dielectric oxide layer having a thickness of about 1,300 Angstroms. This dielectric thickness, however, may result in an undesirable reduction in the capacitance per unit area.
Accordingly, there continues to exist a need in the art for capacitor electrodes and structures which allow the fabrication of thin and reliable capacitor dielectric layers.
USPTO Backgrounds
USPTO Backgrounds