1. Field of the Invention
The present invention relates generally to electronic packaging technology and, more particularly, to solder bump structures that may be used for flip chip packages or wafer level packages, for example.
2. Description of the Related Art
As integrated circuits (IC) advance toward higher speeds and larger pin counts, first-level interconnection techniques employing wire bonding technologies may have approached or even reached their limits. For example, technologies for achieving fine-pitch wire bonding structures may not keep pace with the demand resulting from increased IC chip processing speeds and higher IC chip pin counts. As such, a current trend may involve replacing wire bonding structures with other package structures, such as flip chip packages or wafer level packages (for example).
Flip chip packages and wafer level packages may employ solder bumps, which connect to interconnection terminals of the IC chips. A conventional solder bump structure is shown in FIGS. 1A and 1B, where like elements are designated by the same reference numbers. FIG. 1A shows the solder bump structure prior to being mounted on a circuit substrate, and FIG. 1B shows the solder bump structure after being mounted on the circuit substrate.
Referring to FIGS. 1A and 1B, an IC chip 1 may be equipped with a plurality of chip pads 2. Only one chip pad 2 is shown in FIGS. 1A and 1B. The chip pad 2 may be typically formed of aluminum (Al). Openings may be defined in one or more passivation layers 3 and 4 to expose surfaces of the chip pads 2. One or more under bump metal (UBM) layers 6 and 7 may be interposed between a solder bump 5 and the chip pad 2.
The UBM layers 6 and 7 may function to reliably secure the solder bump 5 to the chip pad 2, and to prevent moisture absorption into the chip pad 2 and the IC chip 1. Typically, the first UBM layer 6 may function as an adhesion layer and may be deposited by sputtering of Cr, Ti, or TiW. Also typically, the second UBM layer 7 may function as a solder wetting layer and may be deposited by sputtering of Cu, Ni, or NiV. The UBM layer 6 or 7, or an intermediate layer therebetween, may function as a solder diffusion barrier. Further, another layer may be optionally deposited on the UBM layers 6 or 7 or the intermediate layer for oxidation prevention purposes.
As shown in FIG. 1B, the flip chip package or the wafer level package may be mounted on a circuit substrate 9 via the solder bumps 5. The circuit substrate 9 may have a plurality of substrate pads 8 corresponding to the chip pads 2 of the IC chip 1. The respective solder bumps 5 may provide solder joints between both pads 2 and 8.
The solder bumps 5 may be subjected to thermal and/or mechanical stresses due to a difference in the coefficient of thermal expansion (CTE) between the IC chip 1 and the circuit substrate 9. Thermal and/or mechanical stresses on the solder bump 5 may cause a crack or fissure, which may propagate completely through the solder bump structure.
An attempt to solve the above-discussed problem has been disclosed in Japanese Patent Publication No. 2000-91371. According to this disclosure, a pillar-shaped metal bump may be embedded within a solder bump to absorb stresses applied to the solder bump. However, a solder layer for the solder bump may be formed on the pillar-shaped metal bump filled in an aperture part of a photoresist film. Thus, the solder layer may be shaped into a mushroom over the photoresist film so that the finished solder bump meets the desired size requirements. Due to the mushroom-shaped solder layer, this conventional, solder bump forming technique may not be suitable for preparing a fine-pitch configuration. For example, the mushroom-shaped solder layer may inadvertently overlap with an adjacent solder layer.
Applicant has introduced a solder bump structure having metal projections, which may reduce cracks and also facilitate the preparation of a fine-pitch configuration. An example of this solder bump structure is depicted in FIGS. 2A and 2B.
Referring to FIGS. 2A and 2B, the solder bump structure may include a plurality of metal projections 511 extending upwardly from a surface of a UBM layer 507. The metal projections 511 may be embedded within a solder bump 505. The metal projections 511 may be arranged in a regular mesh pattern as shown in FIG. 2B. The regular mesh pattern of the projections 511 may act as obstacles to crack propagation, and further lengthens the propagation path of any crack as it travels through the solder bump 505, thus decreasing the likelihood of device failure.
FIGS. 3A though 3I show an exemplary method for manufacturing the solder bump structure shown in FIGS. 2A and 2B. As shown in FIG. 3A, the UBM layers 506 and 507 may be formed over chip pads 502 and passivation layers 503 and 504 on an IC chip 501. As shown in FIG. 3B, a photoresist 515 may be coated over the UBM layer 507, and as shown in FIG. 3C, the photoresist 515 may be patterned through exposure and development processes so as to form a plurality of openings 516 selectively exposing the UBM layer 507. As shown in FIG. 3D, a metal 511 may be deposited in the openings 516, and as shown in FIG. 3E, the photoresist 515 may be removed, with the resultant structure having the metal projections 511.
As shown in FIG. 3F, another photoresist 517 may be coated over the structure having the projections 511. As shown in FIG. 3G, the photoresist 517 may be patterned through exposure and development processes so as to form a single opening 518 exposing the metal projections 511, and as shown in FIG. 3H, a solder material 505 may deposited in the opening 518. As shown in FIG. 31, the photoresist 517 may be removed and the UBM layers 506 and 507 may be etched using the solder material 505 as a mask. The solder material 505 may be reflowed into a globe-shape configuration.
In the solder bump forming technique depicted in FIGS. 3A through 3I, separate openings 516 (see FIG. 3C) and 518 (see FIG. 3G) may be respectively used to form the metal projections 511 and the solder bump 505. This technique makes it possible to deposit the solder material just within the opening 518, thereby avoiding the formation of the mushroom-shaped solder layer associated with the technique disclosed in Japanese Patent Publication No. 2000-91371. Thus, the forming technique depicted in FIGS. 3A through 3I may be used to prepare a fine-pitch configuration.
USPTO Backgrounds
USPTO Backgrounds