Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
In a multi-core processing system comprising a plurality of processing cores, in various conventional systems each processing core is associated with a corresponding cache. For example, a first processing core is associated with a first cache. The first processing core enters a dormant mode, based on, for example, a processing load of the system.
In a first example, while the first processing core is in the dormant mode, the first processing core receives a cache command associated with, for example, invalidating a cache line of the first cache, and such a cache command needs to be executed to maintain cache coherency among the caches of the system. The first processing core has to wake up from the dormant mode to execute such a cache command. Thus, the first processing core has to wake up frequently from the dormant mode, namely each time the first processing core receives such cache commands.
In a second example, prior to the first processing core entering the dormant mode, the first processing core flushes all the cache lines of the associated first cache (i.e., the first cache is emptied). Flushing the cache lines of the first cache ensures, for example, that while the first processing core is in the dormant mode, no cache command associated with invalidating a cache line of the first cache is received (as all the cache lines of the first cache is already flushed). However, as all the cache lines of the first cache are flushed, the hit ratio in the first cache is relatively low subsequent to the first processing core waking up from the dormant mode, thus adversely affecting the performance of the first cache.
USPTO Backgrounds
USPTO Backgrounds