Field
The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same.
Description of the Related Technology
Advances in semiconductor fabrication technology continue to enable physical scaling of semiconductor integrated circuit devices. One of the technological advances in new generations of semiconductor devices, e.g., memory device technologies at advanced technology nodes (e.g., nodes below 10 nm), includes three dimensional (3D) memory devices or vertical non-volatile memory devices, such as, for example, 3D NAND flash memory devices. However, some 3D NAND flash memory technologies can have a number of disadvantages, such as: limited scalability (scaling the plug diameter is difficult), a need for high voltages (typically higher than 10V, even higher than 15V) and/or electrical nonuniformities associated with tapering of the vertical channel resulting from vertically nonuniform etch profiles.
Another type of non-volatile memory device is the ferroelectric field effect transistor (FeFET) which can also be built in a vertical configuration. US patent application US2014/0070290 A1 discloses a ferroelectric memory having a 3D structure type NAND memory cell. The memory comprises cell gate electrodes and interlayer insulating films which are alternately stacked, and a trench which passes through this stack structure. A gate insulating film and an interfacial insulating film are stacked on the inner wall of the trench, and the core of the trench is filled with an n-type semiconductor layer. A cell gate region, an inter-adjacent-cell-gate region, and a select gate region are defined. The vertical gate insulating film is tuned to be ferroelectric in the cell gate region and insulating in the inter-adjacent-cell-gate region and the select gate region. The vertical gate insulating film includes a metal that is hafnium (Hf) or zirconium (Zr) and oxygen as the main components and to which an element selected from the group consisting of silicon (Si), magnesium (Mg), aluminum (Al), and yttrium (Y) is added. Along the inter-adjacent-cell-gate region additionally Nitrogen and Carbon elements are added which act as fixed charge impurities, thereby suppressing polarization in this region. As such any wrong memory operation can be avoided.
Regardless of whether the FeFETs are integarated as planar two-dimensional or vertical three-dimensional memory transistors, many technological challenges of FeFET memory devices continue to remain. For example, some FeFET memory devices have been known to suffer from limited data retention times (i.e., times associated with change in a polarization state without external power), whose effects have been associated with the presence of a depolarization field. The problem of retention loss and the depolarization field is for example also explained in an article of Ma T. P. et al. titled “Why is nonvolatile ferroelectric memory field-effect transistor still elusive?” from IEEE Electron Device Letters, Vol. 23(7) p. 386 (2002). Thus, there is a need for FeFET devices memory devices with improved data retention and scalability.
USPTO Backgrounds
USPTO Backgrounds