As high degree of integration becomes more and more demanding for integrated circuit (IC) devices, the reliability requirement of transistors is also increased. In CMOS process, negative bias temperature instability (NBTI) is a key factor when evaluating the reliability of PMOS transistors. NBTI occurs, when a PMOS transistor is under negative gate bias voltages and high temperatures. In this case, silicon-hydrogen bond at the interface between the gate oxide and the substrate of the PMOS transistor breaks and thereby forms interface defect charges, which may cause threshold voltage drift and saturation current drift of the PMOS transistor to occur.
FIG. 1 is a schematic diagram illustrating a circuit to test NBTI effect in a PMOS transistor. When testing NBTI effect in PMOS transistor (P10), at a high ambient temperature (typically 125° C.), a negative stress voltage Vstress is applied to the gate of PMOS transistor P10, and a 0V voltage is applied to the source, the drain and the substrate of PMOS transistor P10, i.e., to ground the source, the drain and the substrate of PMOS transistor P10. Testing the NBTI effect in PMOS transistor P10 reduces the absolute values of linear region drain current (Idlin), saturation drain current (Idsat), and low frequency trans-conductance (gm). In the meantime, testing the NBTI effect in PMOS transistor P10 increases the absolute values of drain-source cutoff current (Ioff), threshold voltage (Vt), and gate-induced drain leakage (GIDL) current.
Specifically, FIG. 2 is a diagram illustrating how drain current changes with gate-source voltage in the PMOS transistor P10 shown in FIG. 1. The horizontal axis represents gate-source voltage (Volt) in the PMOS transistor P10 and the vertical axis represents drain current (Ampere) in the PMOS transistor P10. The solid curve L21 in FIG. 2 shows the relationship between drain current and gate-source voltage in PMOS transistor P10 before NBTI test, while the dotted curve L22 shows the relationship between drain current and gate-source voltage in the PMOS transistor P10 after NBTI test. As shown, the NBTI test reduces drain current in PMOS transistor P10.
FIG. 3 is a diagram illustrating how low frequency trans-conductance changes with gate-source voltage in PMOS transistor P10 shown in FIG. 1. The horizontal axis represents gate-source voltage (Volt) in PMOS transistor P10 and the vertical axis represents low frequency trans-conductance (Siemens) in PMOS transistor P10. The solid curve L31 shows the relationship between low frequency trans-conductance and gate-source voltage in PMOS transistor P10 before NBTI test, while the dotted curve L32 shows the relationship between low frequency trans-conductance and gate-source voltage in PMOS transistor P10 after NBTI test. As shown, NBTI test reduces the maximum value of low frequency trans-conductance in PMOS transistor P10.
As the critical dimension (CD) of semiconductor devices shrinks, the NBTI effect in PMOS transistors has become increasingly evident and adversely affects the lifespan of PMOS transistors. Therefore, it is desirable to mitigate the NBTI effect in PMOS transistor.
USPTO Backgrounds
USPTO Backgrounds