1. Technical Field
The present invention relates to a field effect transistor (FET), and more particularly, to a GaN-based FET having a channel layer constituted by a GaN-based semiconductor and a manufacturing method therefor.
2. Related Art
GaN-based FETs and metal-insulator semiconductor FETs (MISFETs) using a wide bandgap semiconductor such as GaN, AlGaN have received much attention as a power device for high power application since they are one order of magnitude or more smaller in on-resistance than FETs using Si, GaAs or the like, and are hence operable at higher temperature with higher current and can withstand high voltage application.
In conventional GaN-based FETs, however, since a lift-off method is adopted for electrode formation, it is difficult to form electrodes with a sufficient thickness so as to make electrode resistance sufficiently small. FETs have their on-resistance determined by electrode resistance as well as contact resistance between electrodes and corresponding respective regions of the FETs, and therefore, the on-resistance cannot be made sufficiently small, if the electrode resistance is not small.
As for conventional MISFETs, source and drain regions are formed on a surface of a channel layer by using as a mask a resist pattern formed by photolithography, thereby forming the channel layer between the source and drain regions. Since the dimensional accuracy of resist-pattern formation is not so high as to permit the distance between the source and drain regions (i.e., the length of the channel layer) to be small to the extent that the on-resistance of the MISFETs becomes sufficiently small.
With reference to FIGS. 12-22, an example of a manufacturing method of a conventional GaN-based FET will be explained and drawbacks of the method will be mentioned.
First, an undoped GaN layer 52, an n-type GaN channel layer 54 doped with Si impurity, and an n-type GaN contact region 56 highly doped with Si impurity are crystal-grown on a sapphire substrate 50 in this order. Then, patterning of an SiO2 film 58 formed on the contact region 56 is conducted by the lithography and etching method, thereby forming the SiO2 film 58 into the desired pattern (refer to FIG. 12).
Next, using the patterned SiO2 film 58 as a mask, the contact region 56, the channel layer 54 and the undoped GaN layer 52 are selectively removed by etching, whereby they are formed into a mesa structure for the interelement separation, with a surface of the undoped GaN layer 52 partly exposed (see FIG. 13).
After the SiO2 film 58 is removed by etching, an SiO2 film 60 is formed on the entire surfaces of the exposed undoped GaN layer 52, the contact region 56 and the like. Then, the SiO2 film 60 is selectively removed by the lithography and etching method, to make the contact region 56 exposed (FIG. 14).
Next, using the SiO2 film 60 as a mask, the exposed contact region 56 is removed by etching, to thereby cause the surface of the channel layer 54 to be exposed and separate the contact region 56 into two contact regions 56a and 56b (FIG. 15).
After the SiO2 film 60 is removed by etching, an SiO2 film 62 is formed on the entire surfaces of the exposed undoped GaN layer 52, the exposed channel layer 54, and the contact regions 56a, 56b (FIG. 16).
Next, patterning of a resist film applied to the SiO2 film 62 is conducted by lithography to form the desired resist pattern 64. Using the resist pattern 64 as a mask, the SiO2 film 62 is selectively removed by etching, to thereby form contact holes 66a, 66b in the SiO2 film 62, through which the contact regions 56a, 56b are partly exposed (FIG. 17).
Then, TaSi and Au are sequentially vapor-deposited in layer on the entire faces of the resist pattern 64 and the exposed contact regions 56a, 56b, whereby a TaSi/Au layer 68 is formed with which the contact holes 66a, 66b are filled (see FIG. 18).
Next, using a lift-off method, the resist pattern 64 and most parts of the TaSi/Au layer 68 formed thereon are removed, whereas those parts of the TaSi/Au layer 68 which are filled in and vertically project from the contact holes 66a, 66b are kept remained. As a result, source and drain electrodes 68a, 68b are formed that are constituted by the TaSi/Au layers 68 and in ohmic contact with those parts of the contact regions 56a, 56b which are located beneath the contact holes 66a, 66b (see FIG. 19).
Next, patterning of a resist film applied to the entire surfaces of the SiO2 film 62 and the source and drain electrodes 68a, 68b is made by the lithography method, thereby forming a resist pattern 70 through which a central part of the SiO2 film 62 is exposed. Whereupon, using the resist pattern 70 as a mask, the exposed central part of the SiO2 film 62 is removed by etching, whereby the SiO2 film 62 is formed with a contact hole 72 through which the channel layer 54 located between the contact regions 56a, 56b is exposed (FIG. 20).
Next, Pt and Au are sequentially vapor-deposited in layer on the resist pattern 70 and part of channel layer 54 exposed through the contact hole 72, thereby forming an Au/Pt layer 74 with which the contact hole 72 is filled (see FIG. 21).
Then, using the lift-off method, the resist pattern 70 and the Au/Pt layer 74 are removed, with the Au/Pt layer 74 in the contact hole 72 kept remained. As a result, a gate electrode 74a is formed, which is constituted by the Au/Pt layer 74 filled in the contact hole 72 and Schottky-contacted to the channel layer 54 (FIG. 22). The FET fabrication is thus completed.
As explained above, in the conventional GaN-based FET, the lift-off method is adopted for the formation of source, drain and gate electrodes 68a, 68b and 74a, and therefore, it is difficult to make the thicknesses of these electrodes greater than about 2-3 μm. Thus, the electrode resistance cannot be made sufficiently small, especially for a large-area device, posing a problem that it is difficult to attain satisfactory power characteristics.
The source and drain electrodes 68a, 68b must be formed separately from the gate electrode 74a, using an electrode material different from that for the gate electrode 74a. Accordingly, photolithography, etching and vapor-depositing processes for the lift-off method must be repeated, causing a problem of increased costs due to complicated fabrication processes.
In addition, usage of highly hard sapphire substrate 50 poses a further problem that a difficult is encountered in properly cutting a wafer-into chips in the dicing process which is the final wafer process.
Moreover, the sapphire substrate 50 is extremely poor in heat dissipation, making it difficult for a power device to dissipate heat generated therein. This causes problems of deterioration of electrodes and of badly affecting on characteristics such as drain withstand voltage, on-resistance and the like. To cope with these problems, there is the idea of using a silicon substrate instead of the sapphire substrate 50. However, a method for epitaxial growth of a GaN layer on a silicon substrate has not been established as yet.
In the following, an example of a conventional GaN-based MISFET will be explained with reference to FIG. 37, and drawbacks of the MISFET will be pointed out.
There is shown a sapphire substrate 150 on which sequentially formed in layer are a GaN buffer layer (not shown), an undoped GaN layer (not shown), and a p-type GaN channel layer 152 doped with Mg impurity. By adding n-type impurity such as Si to the channel layer 152 with use of, as a mask, a resist pattern formed on the channel layer 152 by lithography, a central region without n-type impurity being added is formed on a surface of the channel layer 152, and n-type GaN source and drain regions 154, 156 are formed thereon on both sides of the central region, respectively.
On the source and drain regions 154 and 156, source and drain electrodes 158, 160 are formed, each electrode being constituted by an Al/Ti layered structure formed by sequentially vapor-depositing Al and Ti in layer, whereas a gate electrode 164 of an Al/Ti layered structure is formed on a central portion of a gate insulating film 162 constituted by an SiO2 film or the like, which portion is located directly above the central region of the channel layer 152.
The MISFET has a channel region thereof constituted by the central portion of the channel layer 152 between the source and drain regions 154, 156, and has a channel length represented by the length of the channel region.
As understood from the foregoing explanation, the conventional GaN-based MISFET is fabricated in the form of a planar structure as in the case of MISFETs using Si or GaAs.
Instead of using the aforementioned method, the source and drain regions may be formed by making embedding-growth of n-type GaN layers in two recesses that are formed by etching in the p-type GaN channel layer 152, using as a mask a resist pattern formed on the channel layer 152 by photolithography.
At any rate, the channel length L, i.e., the length of the channel layer 152 between the source and drain regions 154, 156 is restricted by the dimensional accuracy of the resist pattern formed on the channel layer 152 and hence cannot be sufficiently shortened. The channel length L of an ordinary GaN-based MISFET is about 6 μm.
Due to the difficulty in sufficiently decreasing the channel length, the conventional GaN-based MISFET entails a drawback that the on-resistance cannot be made sufficiently small despite that the bandgap of p-type GaN constituting the channel layer 152 is wider than those of Si and GaAs.
A further problem is posed that the contact resistance between the source and drain electrodes 158, 160 and n-type GaN source and drain regions 154, 156 is extremely large, on the average, in the order of 2×10−4 Ωcm2.
Theoretically, the on-resistance of MISFETs having a channel layer constituted by a wide bandgap semiconductor such as GaN, AlGaN is one order of magnitude or more smaller than that of MISFETs using Si or GaAs. Nevertheless, a suitable device structure that effectively utilizes such an advantage of wide bandgap semiconductors has not been proposed as yet.
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