Narrowband applications like telemetry in the Medical Implant Communication Service (MICS) band require a power efficient, relatively high data rate transmitter for short range communication. Low-power transceivers capable of delivering reasonably high communication data rate 1 Mbps are often required for short range communication of 1 m to 5 m. In battery-less remote control applications, where energy is harvested from a push button piezoelectric or other mechanical means, more stringent requirements on power consumption is imposed. While frequency shift keying (FSK), where binary bits are represented by 2 different frequencies, is often adopted as the signaling scheme for short range communication for its robustness and ease in performing modulation and demodulation operations, power efficiency still poses a great challenge in the transmitter design, especially for the above-mentioned applications.
A frequency shift keying (FSK) transmitter is often based on the fractional-N PLL (phase-locked loop) [M. Perrott, T et al., “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, December 1997]. This architecture consumes few to tens of mW as it involves dividing down from a high frequency domain that is often tens of times of the desired frequency to minimize quantization noise for good phase noise performance. The architecture includes a power hungry modulus divider circuit which often consists of flip-flops and logic counters to obtain the required division ratio. The transmitter is energy-inefficient due to complexity and higher operation frequency. The PLL is not inherently stable, so design effort to ensure loop stability has to be enforced. However, high data-rate is often achievable with these designs. The control word, K, determines the fractional division ratio between N and N+1, so that the output frequency of the VCO will be a N+fraction multiple of the reference frequency.
Another FSK architecture is the open-loop voltage or digitally controlled oscillator (VCO/DCO) based transmitter having only a voltage or digitally controlled oscillator (VCO/DCO) directly driving the inductive antenna [J. L. Bohorquez, et al., “A 350 μW CMOS MSK transmitter and 400 μW OOK super-regenerative receiver for medical implant communications,” IEEE J. of Solid-State Circuits, vol. 44, no. 4, pp. 1248-1259, April 2009; J. Bae, et al., “A 490 μW fully MICS compatible FSK transceiver for implantable devices,” IEEE Proc. of Symp. on VLSI Circuits, pp. 36-37, June 2009]. This involves changing the free-running frequency of the oscillator through some passive element like a varactor or capacitor bank. While this method seems attractive since the design consists of only a single oscillator block, the output signal suffers from frequency drift or instability which is a major drawback. Performance burden is hence shifted to the receiver side. The transmitter also has poor phase noise.
A further FSK transmitter has an injection locked ring oscillator (RO) with hybrid edge combiner/power amplifier (EC/PA) architecture [J. Pandey and B. Otis, “A 90 μW MICS/ISM band transmitter with 22%global efficiency,” IEEE Proc. of Radio Frequency Integrated Circuits (RFIC) Symp., May 2010, pp. 285-288]. The transmitter uses crystal frequency pulling for frequency modulation and employs injection locking twice, serially to 2 ring oscillators (RO) to stabilize the generated signal. The signal is then multiplied up 9 times to its desired frequency via an edge combiner (EC) before transmission through a power amplifier (PA) driven antenna. Through the use of a hybrid EC/PA circuit and keeping the operation of its frequency generating circuit 9 times below the desired frequency, the power consumption is in the sub-100 μW range. However, the system is very rigid as the frequency generating circuit only produces 2 fixed frequencies depending on the physical properties of the crystal, making frequency selection very limited, which inhibits frequency hopping. The frequency range crystal pulling can achieve is typically in the range of 10 s to 100 s of kHz. In order to obtain a wide tuning range, a high factor frequency multiplier is required. A data rate of 200 kbps for the transmitter is reported.
Another FSK transmitter is the delta-sigma modulator (ΔΣM) phase interpolator based transmitter, providing phase interpolation [Y.-H. Liu and T.-H. Lin, “A wideband PLL-based G/FSK transmitter in 0.18 μm CMOS,” IEEE J. of Solid-State Circuits, vol. 44, no. 9, pp. 2452-2462, September 2009]. An integer-N PLL generates 4 equally spaced clock edges and through a ΔΣM controlled phase rotator (PR), it is able to generate fractional delays by performing a dithered selection among the 4 clock phases. Although it can cover a wide frequency range due to π/2 separation of each clock phase, it suffers from larger quantization noise, resulting in higher in-band noise. Moreover, it is not fully efficient as a divide-by-two block is used to generate the different clock phases, implying that the VCO has to operate at twice the desired frequency rather than directly at the operating frequency. The transmitter is energy-inefficient due to complexity and higher operation frequency. The in-band noise can be reduced if the quantization step is made smaller than π/2. However, this will result in a more sophisticated design to generate smaller and equal phase separated clock edges.
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