The present invention relates to a dynamic semiconductor memory device to which a power supply voltage of e.g., 1V or less can be applied, and more particularly, to a sense system of the dynamic semiconductor memory device.
In a dynamic random access memory device (DRAM), as miniaturization of the device is accelerated, an amount of charge accumulated in a cell capacitor is reduced. Since the charge accumulated in the cell capacitor is released during a read-out operation in the DRAM, the reduction of capacitance in the cell capacitor has a direct effect upon charge storage characteristics, in particular, holding time in the DRAM. Besides this, with a recent tendency of lowering the power supply voltage, the amount of charge accumulated in the cell capacitor has been reduced. Therefore, the holding time will be further reduced.
The read-out operation in the DRAM is performed by releasing the charge of a memory cell to a bit line and detecting a slight potential change of the bit line by a sense amplifier. In the read out operation, the change in potential of the sense amplifier right after the charge of the memory cell is released is smaller than the voltage virtually written in the memory cell. A potential change in the sense amplifier section after a word line is activated and charge of the cell is released to a bit line, is expressed by Equation (1): EQU Vsense=(Vcell-VBL).times.Cs/(Cb+Cs) (1)
where Vsense is an amount of a signal voltage output to a bit line, Vcell is a potential of a storage node right before a word line is activated, VBL is a precharge potential of a bit line, Cs is a cell capacitance, and Cb is a capacitance of a bit line. PA1 Cb is about 20 times as large as Cs. Vsense decreases up to about 1/20 of cell write voltage Vcell-VBL. If the Vsense is reduced equal to and less than the read-out sensitivity of the sense amplifier, incorrect data comes to be read out. To prevent this, it is required to increase a voltage to be applied in order to release charge of a memory cell to a bit line. As such a technique, a charge transfer type sense amplifier has been developed. PA1 where .DELTA.V BLS/A is a potential change of the bit line BLS/A, .DELTA.V BLcell is a potential change of the bit line BLcell, Cb is a capacitance of a bit line BLcell, and Csa is a capacitance of a bit line BLS/A. PA1 Cb is about 20 times as large as Csa. Therefore, if .DELTA.VBLcell has a voltage of, e.g., -0.02V, .DELTA.VBLS/A is amplified up to about -0.4V. However, if the memory cell MC stores data "1", the transistor Q2 remains in an OFF state and VBLS/A remains at "1", since .DELTA.VBLcell is not negative. To sense "1", a dummy cell is additionally required. PA1 where Cs is a capacitance of a memory cell, Cb is a capacitance of a bit line on the memory cell side, and Csa is a capacitance of a bit line on a sense amplifier side. PA1 a bit line pair including two complementary bit lines to each of which a memory cell is connected; PA1 a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair; PA1 charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof; PA1 a gate potential generator connected to the charge control terminal, controlling ON/OFF of each of the charge transfer gates; PA1 a precharging/equalizing circuit connected to the bit line pair located on a sense amplifier side of the charge transfer gate; and PA1 a bit line potential generator connected to the precharging/equalizing circuit, generating a potential precharging and equalizing the bit line pair. PA1 a bit line pair including two complementary bit lines to each of which a memory cell is connected; PA1 a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair; PA1 charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof; PA1 a gate potential generator connected to the control terminal, controlling ON/OFF of each of the charge transfer gates; PA1 a precharging circuit connected to the bit line pair of a sense amplifier side of the charge transfer gates, precharging the bit line pair; PA1 a first signal line connected to the precharging circuit, transmitting a precharge startup signal; PA1 an equalizing circuit connected to the bit line pair located on the sense amplifier side of the charge transfer gates, equalizing the bit line pair; PA1 a second signal line connected to the equalizing circuit, transmitting an equalizing startup signal; and PA1 a bit line potential generator connected to the precharge circuit, generating a potential precharging the bit line pair. PA1 the potential being higher than a value in a case where each of the charge transfer gates is an n-channel MIS transistor and lower in a case where each of the charge transfer gates is a p-channel MIS transistor, PA1 the value being obtained by adding a threshold voltage of the charge transfer gates to a potential which is to be transferred to a corresponding one of the two complementary bit lines on the sense amplifier side, after a potential of the memory cell is output to the corresponding one of the two complementary bit lines on a memory cell side, PA1 so that a potential of a corresponding one of the two complementary bit lines located on the memory cell side is transferred to the sense amplifier.
Now, the charge transfer type sense amplifier will be explained.
FIG. 1 shows a schematic circuit diagram of a charge transfer type sense amplifier. The memory cell MC is constituted of a transistor Q3 and a capacitor C1. The gate of the transistor Q3 is connected to a word line WL. An end of the current path of the transistor Q3 is connected to a bit line BL. A transistor Q2 is inserted in the bit line BL. A voltage VR is supplied to the gate of the transistor Q2. An end of the current path of a transistor Q1 is connected to a bit line BLS/A, which is interposed between the transistor Q2 and a sense amplifier (not shown). A voltage VH is supplied to the other end of the current path of a transistor Q1. A capacitor Cb is a parasitic capacitor of a bit line BL cell located on a memory cell side of the transistor Q2. A capacitor Cs a is a parasitic capacitor of a bit line BLS/A located on a sense amplifier side of the transistor Q2. The transistor Q2 is a charge transfer gate.
In this circuit arrangement, when a signal .phi.1 to be supplied to the gate of the transistor Q1 goes to a high level during a bit line precharge period, as shown in FIG. 2, the transistor Q1 is turned on, whereby the bit line BLS/A on the sense amplifier side is charged to a voltage VH by way of the transistor Q1. At this time, since the gate of the transistor Q2 is set at a voltage VR (&lt;VH), if the bit line BLcell on the memory cell side is charged up to VR-Vth, the transistor Q2 is turned off. The Vth used herein is a threshold voltage of the transistor Q2. When the charge operation is completed and thereafter the word line WL is activated, the potential of the bit line BL varies depending upon the amount of charge accumulated in the storage node of the capacitor C1. More specifically, in the case where the memory cell MC stores data "0" (ground potential Vss), the potential of the bit line BL cell decreases lower than the voltage VR-Vth. As a result, the transistor Q2 is turned on.
After the transistor Q2 is turned on, the potential of the bit line BLS/A on the sense amplifier side changes as indicated by Equation (2): EQU .DELTA.VBLS/A=.DELTA.VBLcell.times.Cb/Csa (2)
When the charge transfer type sense amplifier is used, it is impossible to use half of the power source voltage Vcc (1/2 Vcc) as a precharge voltage to be applied to the bit line, although 1/2 Vcc is preferable since power consumption is reduced. In addition, the dummy cell is required.
FIG. 3 shows a circuit arrangement of a conventional charge transfer type sense amplifier to which 1/2 Vcc can be applied as the precharge voltage for the bit line (Masaki Tsukude et al., "A 1.2V to 3.3V Wide-Range DRAM with 0.8V Array Operation", IEEE International Solid-State Circuit Conference Digest of Technical Papers, pp 66-67, 1997).
In FIG. 3, a selection gate SG1 (serving as a charge transfer gate) is inserted in the midway of each extension line of a bit line pair BL, /BL. To one side (upper side of the figure) of the selection gate SG1, not only an equalizing circuit EQL for equalizing the bit line pair but also a first sense amplifier p-SA formed of p-channel transistors are connected. To the other side (lower side of the figure) of the selection gate SG1, not only a precharge circuit PRC for precharging the bit line pair but also a second sense amplifier n-SA formed of N-channel transistors, are connected.
In the aforementioned circuit arrangement, the precharge circuit PRC is activated during the precharge period, whereby the bit line pair on the side of the second sense amplifier n-SA are charged up to a sense amplifier precharge level Vcc[1+.gamma.] (e.g., 1.6V) and the bit line pair on the bit line side are precharged to 1/2 Vcc (e.g., 0.4V). After the word line WL is activated, the gate voltage SGL of the selection gate SG is increased from a ground potential Vss to .beta.+Vth. For example, if .beta.+Vth is increased to 0.9V, (.beta.: 0.5V, Vth: 0.4V, for example), the charges of the bit line on the side of the second sense amplifier n-SA are transferred to the bit line on the side of the first sense amplifier p-SA. As a result, both bit lines BL, /BL are charged to a potential of SGL-Vth=.beta.(for example, 0.5V). More specifically, the bit lines BL, /BL to which the memory cell MCs are connected, are charged at the same potential by the transfer of charges from the side of the second sense amplifier n-SA. In this way, the circuit of the charge transfer type sense amplifier functions.
In the meantime, to obtain a maximum potential difference in the sense amplifier, a value of .beta. is larger than the potential when data 1 is read out to a bit line and is a potential inevitably supplied by transferring charges from a sense amplifier side during the data "0". More specifically, the value of .beta. must satisfy the relationship expressed by Equation (3): EQU 1/2Vcc.times.[1+Cs/(Cb+Cs)]&lt;.beta.&lt;(Vcc[1+.gamma.].times.Csa+1/2Vcc.times.C b)/(Cb+Csa+Cs) (3)
Furthermore, it is necessary to add 0.05V to a right hand side of the equation as an operational margin. For example, assuming that Cb=20.times.Cs, Csa=Cs, Vcc[1+.gamma.]=1.6V, 1/2 Vcc=0.4V, .beta. is controlled to satisfy the following equation: 0.42V&lt;.beta.&lt;0.44V.
The charge transfer type sense amplifier shown in FIG. 3 employs 1/2 Vcc as the bit line precharge voltage. However, in this circuit, the precharge circuit PRC for the sense amplifier and the equalizing circuit EQL for the bit line must be arranged at both sides of the selection gate SG.sub.1 (charge transfer gate), respectively. Furthermore, it is impossible to share a p-channel type sense amplifier between a memory cell (not shown) connected to one of sides (the lower portion of FIG. 3) of a selection gate SG.sub.2 and a memory cell connected to a selection gate SG.sub.1. For these reasons, the scale of the circuit is enlarged, so that a chip size and a manufacturing cost are increased.
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