Flat panel displays have recently been developed for visually displaying information generated by computers and other electronic devices. These displays can be made lighter and require less power than conventional cathode ray tube displays. One type of flat panel display is known as a cold cathode field emission display (FED).
A field emission display uses electron emissions to illuminate a cathodoluminescent display screen (termed herein a "faceplate") and generate a visual image. An individual field emission pixel typically includes emitter sites formed on a baseplate. The baseplate includes the circuitry and devices that control electron emission from the emitter sites. A gate electrode structure, or grid, is associated with the emitter sites. The emitter sites and grid are electrically connected to a voltage source. The voltage source establishes a voltage differential between the emitter sites and grid and controls electron emission from the emitter sites. The emitted electrons pass through a vacuum space and strike phosphors contained on the display screen. The phosphors are excited to a higher energy level and release photons to form an image. In this system the display screen is the anode and the emitter sites are the cathode. The emitter sites and faceplate are spaced apart by a small distance to stand off the voltage difference between these components and to provide a gap for gas flow. In order to provide a uniform resolution, focus and brightness at the faceplate, it is important that this distance be uniform across the total surface of the faceplate. In addition, in order to achieve reliable display operation during electron emission from the emitter sites, a vacuum on the order of 10.sup.-6 Torr or less is required. The vacuum is formed in a sealed space contained within the field emission display.
Field emission displays are typically constructed as a package having a seal for sealing the space between the baseplate and faceplate. However, prior to sealing of the package it is necessary to align the baseplate with the faceplate. This is required so that elements on the baseplate (e.g., emitter sites) are in alignment with corresponding elements on the faceplate.
One difficulty with the process for aligning the baseplate and faceplate is that because these components are ultimately assembled in a spaced or offset configuration, alignment errors introduced during the alignment process are magnified by the spacing of the assembled components. These errors are termed herein as "parallax" errors because they are caused by a different viewpoint during the alignment and bonding steps. As an example, the baseplate and faceplate can be initially spaced apart, optically aligned, and then brought into a final spaced configuration during assembly. However, misalignment during the initial alignment procedure can introduce parallax errors in the assembled components that cannot be tolerated in a field emission display.
In view of the foregoing, it is an object of the present invention to provide an improved method for aligning and assembling spaced components such as the baseplate and faceplate of a field emission display.
It is a further object of the present invention to provide an improved method for aligning and assembling spaced components using an optical alignment tool calibrated to reduce parallax alignment errors.
It is yet another object of the present invention to provide an improved method for calibrating conventional alignment tools to eliminate parallax errors to permit their use in aligning and assembling spaced components.
Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
USPTO Backgrounds
USPTO Backgrounds