Magnetic random access memory (MRAM), particularly MRAM using an array of magnetic tunnel junction (MTJ) devices as storage elements, is employed in a wide variety of circuits and applications. As storage density requirements continue to increase, the design of MRAM circuit architectures to meet such requirements becomes significantly more challenging. Furthermore, with greater storage density comes a higher likelihood that one or more memory cells (i.e., bits) in the MRAM will be defective (e.g., shorted). Thus, although it would be desirable to achieve one hundred percent yield of working devices, such a yield is generally not attainable in a high-density memory device within a reasonable cost.
Conventionally, MRAM is often designed with a certain amount of built-in redundancy, so that defective memory cells, at final test, can be identified, readdressed and essentially replaced by memory cells residing in a redundancy area of the device. While this approach has had some success at increasing yield, the additional chip area required in order to incorporate such redundancy in the MRAM device comes at the price of significantly lower storage density in the device and is therefore undesirable. Moreover, due to the ever-increasing storage capacity of MRAM, the number of defects is becoming so large that the redundancy methodology is no longer a viable solution.
Accordingly, there exists a need for techniques capable of providing enhanced yield in a memory circuit that do not suffer from one or more of the problems exhibited by conventional memory architectures and methodologies.
USPTO Backgrounds
USPTO Backgrounds