Semiconductor devices, such as memory devices, image sensors, and the like, may be obtained by highly integrating a plurality of unit elements on a semiconductor substrate.
To highly integrate a plurality of unit elements on a semiconductor substrate, the respective unit elements may be stacked. Alternatively, metal interconnections may be required through which driving signals may be applied to drive the respective unit elements. Such metal interconnections may also be stacked as multiple layers by interlayer dielectric layers.
If unit elements are formed in the above manner and metal interconnections to drive the unit elements are arranged, the metal interconnections may be disconnected if a prescribed portion of an interlayer dielectric layer, in which the metal interconnections are stacked later, is not planarized.
For this reason, a CMP (Chemical Mechanical Polishing) process may be used to planarize the interlayer dielectric layer. The CMP process may not be able to completely planarize the interlayer dielectric layer. Accordingly, a defect may occur in the interconnection process.
FIG. 1 is an example sectional view showing a structure of a related art MOS transistor.
According to the related art MOS transistor, as shown in FIG. 1, active and field regions may be defined in semiconductor substrate 1 such that isolation layers 2 may be formed in the field region.
A gate, which may have gate insulating layer 3, gate electrode 4, and cap insulating layer 5 sequentially formed therein, may be formed on semiconductor device 1 in the active region.
Lowly concentrated n-type impurity regions (-n) 8a and 8b may be formed in semiconductor substrate 1 at both sides of the gate, for example by implanting impurities using the gate as a mask. Sidewall insulating layers 6 may be formed on both side surfaces of gate, respectively.
Source/drain regions 9, which may be highly concentrated n-type impurity regions, may be formed in semiconductor substrate 1 at both sides of the gate, for example by implanting impurities using the sidewall insulating layers and the gate as a mask.
The related art semiconductor device may have various problems. For example, since an interlayer dielectric layer may convexly protrude along a gate in a case where it may be formed on a top surface of a MOS transistor formed as described above, it may be difficult to planarize the interlayer dielectric layer.
Since an interlayer dielectric layer may not be planarized, a failure of a metal interconnection may be caused in a case where a metal interconnection is formed on the interlayer dielectric layer.
USPTO Backgrounds
USPTO Backgrounds