A very large scale integrated (VLSI) complementary metal oxide semiconductor (CMOS) chip is typically manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.) and material modifications (i.e., oxidations, ion implants, etc.). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations must be confined to small, well-defined regions.
Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending with the removal of the expended photoresist to allow new resist to be applied for further iterations of the process sequence.
A conventional lithography system consists of a light source, a stencil or photomask containing the pattern to be transferred to the wafer, a collection of lenses, and mechanism for aligning existing patterns on the wafer with patterns on the mask. Because a wafer (typically containing from fifty to one hundred chips) is patterned in steps of one to four chips at a time, these lithography tools are commonly called steppers. The resolution, R, of an optical projection system such as a lithography stepper is limited by parameters described in Raleigh's equation: ##EQU1## where .lambda. is the wavelength of the light source used in the projection system, NA is the numerical aperture of the projection optics used, and k is a factor describing how well a combined lithography system can use the theoretical resolution limit in practice. The factor k can range from 0.8 down to 0.5 for standard exposure systems.
The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at a wavelength of 248 nm. Alternately, mid ultra violet (MUV) steppers with a wavelength of 356 nm are also available.
FIG. 1A shows a side view of a conventional photomask 100. Referring to FIG. 1A, photomask 100 consists of chromium patterns 102 on quartz plate 104, allowing light to pass wherever the chromium has been removed from photomask 100, such as area 106. Light of a specific wavelength is projected through the mask on the photoresist coated wafer (not shown), exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to light of the appropriate wavelength causes modifications in the molecular structure of the resist polymers which allows developer to dissolve and remove the resist in the exposed areas. (Negative resist systems allow only unexposed resist to be developed away.) The photomask, when illuminated, can be pictured as an array of individual, infinitely small light sources which can be turned on (clear areas 106) or off (chrome areas 102). As shown in FIG. 1B, if the amplitude of the electric field vector, which describes the light radiated by these individual light sources, is mapped across a cross section of the photomask 100, a step function 110 will be plotted reflecting the two possible states that each point on the mask can be found (light on, light off).
These conventional photomasks are commonly called chrome-on-glass (COG) binary masks, due to the binary nature of the image amplitude. The perfectly square step function 110 exists only in the theoretical limit of the exact mask plane. As shown in FIG. 1C, at any distance away from the mask, such as at the wafer plane 120, diffraction effects will cause images to exhibit a finite image slope 122. At small dimensions, such as when the size and spacing of the images to be printed are small relative to the .lambda./NA, electric field vectors of adjacent images 124, 126, 128 interact and add constructively. As shown in FIG. 1D, the resulting light intensity curve 130 between the features is not completely dark, but exhibits a significant amount of light intensity, created by the interaction of adjacent features. This results in minimal definition 132 between adjacent features. The resolution of an exposure system is limited by the contrast of the projected image, that is, the intensity difference between adjacent light and dark features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than as discrete images.
The quality with which small images can be replicated in lithography depends largely on the available process latitude: the amount of allowable dose and focus variation that still results in correct image size. Phase-shift mask (PSM) lithography improves the lithographic process latitude or allows operation of a lower k value (see Equation 1) by introducing a third parameter on the mask. The electric field vector, like any vector quantity, has a magnitude and direction, so in addition to turning the electric field amplitude on and off, it can be turned on with a 0 degree phase or turned on with a 180 degree phase, for example.
Referring to FIG. 2A, this phase variation is achieved in PSMs by modifying the length 202, 204 that light beam 206, 208 travels through the mask material 200, in areas 205, 207, respectively. By recessing the mask to an appropriate depth 210, light 208 traversing the thinner area 207 of the mask and light 206 traversing the thicker area 205 of the mask will be 180 degrees out of phase: their electric vectors will be of equal magnitude but point in exactly opposite directions so that any interaction between these light beams results in perfect cancellation. This result is shown in FIG. 2B, where the summation of light beams 206 and 208 before and after passing through mask 200 are indicated as light beams 212 and 214, respectively. Marc D. Levenson, in "Phase-Shifting Mask Strategies: Isolated Dark Lines", Microlithography World, pp. 6-12 March/April 1992, provides additional information on PSMs.
Phase-edge PSM lithography uses contrast enhancement caused by phase transition across an opaque feature on a mask. This phase transition is achieved by creating an appropriate (0.5+.lambda.)/(1-refractive index) pathlength difference between light traversing the mask on opposite sides of a critical dimension feature. The pathlength difference can be accomplished by selectively subtracting or depositing material on either or both sides of the critical dimension feature.
Referring to FIGS. 3A-3D, a typical PSM photomask is shown. In FIG. 3A, photomask 300 has chromium deposits 302 on a surface of quartz plate 304. Clear areas 306 are of varying depth to create an out of phase condition. FIG. 3B shows the resulting step function 310. FIG. 3C shows that, although the electric fields have defined slopes 322, 324, 326 for each section of photomask 300, adjacent slopes such as 322, 324, and 326 are out of phase. As shown in FIG. 3D, the resulting light intensity curve 330 has increased definition 332 between adjacent features.
FIGS. 4A-4D show two types of PSM photomasks. FIGS. 4A and 4B show a 0.degree./180.degree. process PSM photomask and FIGS. 4C and 4D show a 90.degree./270.degree. process PSM photomask.
In FIG. 4A photomask 400 has chromium deposits 402 on a surface of quartz plate 404. Clear areas 406 and 408 are phased at 0.degree. and 180.degree., respectively. This results in a phase shift on only one side of a feature. FIG. 4B is a cross-section of photomask 400 taken along section line 4B--4B.
In FIG. 4C, photomask 400 also has chromium deposits 402 on a surface of quartz plate 404. Clear areas 410 and 412 are phased at 90.degree. and 270.degree., respectively. In addition, clear area 414 is phased at 0.degree.. This results in a phase shift on both sides of a feature. FIG. 4D is a cross-section of photomask 400 taken along section line 4D--4D.
Independent of the specific implementation of the phase-edge PSM technique, existing circuit designs must be modified to provide design shapes reflecting the desired topography modifications on the mask. This design modification process depends on automated computer-aided design (CAD) tools to efficiently and accurately convert large hierarchical data sets to include the phase-edge PSM topography designs. It is well known to those skilled in the art that, independent of the specific PSM implementation and the specific CAD tool, it is not possible to convert all circuit designs to PSM layout data.
Such a CAD-based PSM design tool is disclosed in U.S. Pat. No. 5,537,648 issued on Jul. 16, 1996 to Liebmann et al. This tool is unable to guarantee that any arbitrary chip design can be converted to a PSM design without violations between phases.
Another approach for converting conventional VLSI designs to phase-shift compliant designs is illustrated by Kazuko Ooi et al., in "Method of Designing Phase-Shifting Masks Utilizing a Compactor", Jpn. J. Appl. Phys., Vol. 33, pp. 6774-6778 (1994). This approach assigns colors to neighboring shapes and uses a layout modification system to place shapes based on a simple, single-spacing rule for shapes of opposite color. The drawback of this approach is that it is restricted to one type of PSM design.
Design conflicts also arise from shapes that cannot be consistently converted to a PSM design. A typical example of such a shape is a "T". Furthermore, layouts that are driven by physical size requirements for the individual phase regions may violate spacing requirements.
Extensive and complex design rules need to be imposed on circuit designers to ensure that a resulting design can be converted to a PSM layout. Several problems arise from these PSM specific design rules:
1. Designs cannot be migrated from a technology generic layout to a process specific design without major manual intervention. PA1 2. The design rules targeting the prevention of specific PSM conflicts are complex and difficult to communicate to designers. PA1 3. Generic extractions of the PSM-specific rules that are easier to communicate, have a prohibitively large layout density impact on chip designs PA1 4. Without appropriate CAD tools it is difficult to quantify the density impact of certain design rules without actually implementing the design changes.
In many cases, a single design conflict can be resolved in multiple fashions, such as either separating two features to accommodate the phase shapes or expanding (widening) one or both conflicting features to eliminate the need for phase shifting. Any manipulation to the design level targeted for the phase-shift conversion has potential impacts on designs on a large number of other design levels. Although the layout modification system-based design manipulation approach correctly manipulates all affected design shapes, it is further necessary to select the best solution to the design conflict.
Constraint-based layout compaction techniques have been used to legalize conventional VLSI designs. Y. Z. Liao and C. K. Wong, An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints", Proc. 20th Design Automation Conference, June 1983, pp. 107-112. This approach translates separation required by design ground rules between two layout elements, such as edges of shapes, vias, transistors, etc., into a linear constraint. The system of linear constraints is then solved by using an objective function such as a minimum design area.
More recently, a more general constraint-based layout modification technique using minimum perturbation criteria has been proposed for the purpose of design migration. Fook-Luen Heng et al., "A VLSI Artwork Legalization Technique Based on a New Criterion of Minimum Layout Perturbation", ISPD, 1997, pgs. 116-121. This approach uses the same system of linear constraints to represent the separation between layout elements in order to represent the layout but uses the minimum perturbation criteria in its objective function. These constraint-based layout modification systems can be used to convert conventional migration VLSI designs from one process technology to another. These constraint-based layout modification systems cannot be used, however, to migrate conventional VLSI designs to PSM complaint designs due to the complex shape interactions in a PSM photomask.
PSM conflicts cannot be detected easily using current constraint generation techniques. These techniques only create constraints for simple interaction between layout elements. For example, generating constraints which represent a "T" junction in a PSM photomask is not done in the constraint generation phase of the current constraint-based layout modification system. This implies a method to recognize the "T" junction which is not present in the constraint generation process of conventional constraint-based systems. In addition, the objective functions of the conventional constraint-based systems do not provide fine cost controls to resolve PSM conflicts.
FIGS. 5A-5H illustrate a simple layout that can not be converted to a phase shifted design and various corrective approaches. Referring to FIG. 5A, a portion of an integrated circuit layout 500 to be converted to a PSM-compliant layout is shown. Layout 500 consists of gate levels 502, 504, 506, for example.
Referring to FIG. 5B, an exemplary phase-shift design solution is shown. The photomask 510 used to create gate levels 502, 504, 506 may be initially designed by assigning phases to areas 512, 514, 516 adjacent to each gate level area 502, 504, 506. For example, the phase of area 512 may be 90.degree.. This results in area 514, which is opposite area 512 and adjacent gate level 502, having an opposite phase assigned. Because the phase of area 512 is 90.degree., the phase of area 514 is 270.degree.. Following this approach, area 516 is then assigned a 90.degree. phase. This results in a conflict in area 514 where area 514 is adjacent to both sides of gate level 504.
FIG. 5C illustrates an exemplary approach to correct the design conflict. In FIG. 5C, the distance 520 between gate level 502 and 504 is increased. As shown in FIG. 5D, this eliminates the conflict by creating areas 514A, 514B, and 514C from area 514. Areas 514A and 514B are on opposite sides of gate level 504 and may now be assigned opposite phases, such as 270.degree. and 90.degree., respectively. Area 514C is opposite area 512 and as such is assigned a phase opposite to the phase of area 512. As a result, each gate level 502, 504, 506 is defined by areas 512, 514A, 514B, 514C, 516 where a 180.degree. phase shift is realized across each gate level.
Referring to FIG. 5E, a second exemplary approach to the conflict of FIG. 5B is illustrated. In FIG. 5E, a width 525 of a portion of gate level 506 is increased. The mask features which accomplish this solution are shown in FIG. 5F. In FIG. 5F, area 514 of FIG. 5B is divided into areas 514D and 514E each having opposite phases to one another. In addition, area 516 of FIG. 5B is divided into areas 516A and 516B each having opposite phases to one another and to areas 514E and 514D, respectively. This results in a proper phase-shift compliant photomask design.
Referring to FIG. 5G, a third exemplary approach to the conflict of FIG. 5B is illustrated. In FIG. 5, a width 530 of a portion of gate level 502 is increased. The mask features which accomplish this solution are shown in FIG. 5H. In FIG. 5H, area 514 of FIG. 5B is divided into areas 514A and 514B, as shown in FIG. 5D, each having opposite phases. In addition, area 512 of FIG. 5B is divided into areas 512A and 512B each having phases opposite to one another and to areas 514B and 514A, respectively. This results in a proper phase-shift compliant photomask design.
Identifying the best solution out of this multitude of possibilities by manually manipulating the design is virtually impossible for complex IC layouts. In view of the shortcomings of the prior art, it is an object of the present invention to provide a method for design migration to phase-shift compliant integrated circuit designs.
It is a further object of the invention to provide a method for automatically finding the best design solution.
It is another object of the invention to provide a method in which complex PSM conflicts are provided to the constraint-based layout modification system and the conflicts are resolved by a controlled modification using a cost-assignment sequence. Marker shapes may be used to communicate PSM conflicts to the layout modification system in the description of the invention. Other means to communicate the PSM conflicts may include a more sophisticated constraint generation process.
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