The present invention relates to a semiconductor integrated circuit device and the art of manufacturing the same; and, more specifically, the invention relates to improvements applicable to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
The memory cells of a DRAM are arranged at the cross points of a plurality of word lines and a plurality of bit lines all of which are arranged in a matrix over the principal surface of the semiconductor substrate, and each of the memory cells includes one memory cell selecting MISFET and one information storing capacitive element (capacitor) which is connected in series with the memory cell selecting MISFET. The memory cell selecting MISFET mainly includes a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions which constitute a source and a drain. The bit line is arranged above the memory cell selecting MISFET, and is electrically connected to either one of the source and the drain. The information storing capacitive element is similarly arranged above the memory cell selecting MISFET, and is electrically connected to the other of the source and the drain.
As described above, recent types of DRAMs have adopted a so-called stacked capacitor structure in which information storing capacitive elements are arranged above memory cell selecting MISFETs to compensate for a decrease in the charge storage quantity per information storing capacitive element due to the scaling of memory cells. DRAMs which adopt this stacked capacitor structure are divided into two kinds, a capacitor under bitline (CUB) structure in which information storing capacitive elements are arranged below bit lines and a capacitor over bitline (COB) structure in which information storing capacitive elements are arranged above bit lines.
In the above-described two kinds of stacked capacitor structures, as compared with the CUB structure, the COB structure in which information storing capacitive elements are arranged above bit lines is suited to scaling of memory cells. This is because if the charge storage quantity of a scaled information storing capacitive element is to be increased, it is necessary to three-dimensionally design the structure of the information storing capacitive element and increase the surface area thereof, but in the case of the CUB structure in which bit lines are arranged above information storing capacitive elements, contact holes for connecting the bit lines and the memory cell selecting MISFETs become extremely large in aspect ratio and the contact holes become difficult to open.
In the case of recent large-capacity DRAMs such as 64- or 256-Mbit DRAMs, it has become difficult to ensure the required charge storage quantity merely by three-dimensionally forming information storing capacitive elements and increasing the surface areas thereof, and in addition to the three-dimensional formation of the capacitive elements, consideration has been given to the use of a capacitive insulating film formed of a high dielectric material such as Ta2O5 (tantalum oxide), (Ba, Sr)TiO3 (barium strontium titanate; hereinafter referred to as BST) or SrTiO3 (strontium titanate; hereinafter referred to as STO). DRAMs using a capacitive insulating film formed of such a high dielectric material are described in, for example, Japanese Patent Laid-Open No. 222469/1989 and U.S. Pat. No. 5,383,088.
Furthermore, in the field of the above-noted 64- to -256-Mbit DRAMs, it is considered that it becomes inevitable to use a metal material which is lower in resistance than polycrystalline silicon film, for the material of word lines and bit lines as a countermeasure for signal delay due to an increase in chip size or to use the silicidation technique of forming a high melting-point metal silicide layer such as TiSi2 (titanium silicide) or CoSi2 (cobalt silicide) over the surfaces of the sources and drains of MISFETs which constitute peripheral circuits such as sense amplifiers and word drivers which are required to perform high-speed operation, as a countermeasure for avoiding an increase in resistance due to the scaling of contact holes for connecting interconnect lines and the sources and drains of the MISFETs. This silicidation technique is described in, for example, Japanese Patent Laid-Open Nos. 29240/1994 and 181212/1996.
In DRAMs which belong to a 256-Mbit or later generation, as a countermeasure for signal delay due to an increase in chip size, the gate electrodes (word lines) of memory cell selecting MISFETs and the gate electrodes of MISFETs of peripheral circuits are formed of a low-resistance material mainly made of a high melting-point metal such as W (tungsten), and as a countermeasure for decreasing the contact resistance between diffusion layers and interconnect lines, a high melting-point silicide layer is formed over the surfaces of the sources and drains of the MISFETs which constitute the peripheral circuits.
In such DRAMs, as a countermeasure for the signal delay of bit lines, the bit lines are formed of a low-resistance material mainly made of a high melting-point metal such as W, and as a countermeasure for reducing the number of process steps for forming the interconnect lines, the bit lines and first-layer interconnect lines of the peripheral circuits are formed at the same time in one process step. Moreover, in the DRAMs, as a countermeasure for ensuring the charge storage quantities of the information storing capacitive elements, a COB structure in which information storing capacitive elements are arranged above bit line is adopted to facilitate the three-dimensional formation of the capacitive elements, and capacitive insulating films are formed of a high dielectric material such as Ta2O5 (tantalum oxide).
However, the present inventor examined the above-described DRAM manufacturing process, and found out a phenomenon in which the bit lines formed above the MISFETs and the first-layer interconnect lines of the peripheral circuits peeled off the surfaces of the insulating films during high-temperature heat treatment which was performed in a subsequent process step for forming the information storing capacitive elements.
The outline of a process for manufacturing the above-described type of DRAM will be described in brief below. First of all, a low-resistance material which is mainly made of a high melting-point metal deposited over a principal surface of a semiconductor substrate is patterned to form gate electrodes (word lines) of memory cell selecting MISFETs and gate electrodes of MISFETs of a peripheral circuit, and then an impurity is ion-implanted into the semiconductor substrate to form the sources and drains of these MISFETs.
Then, after these MISFETs are covered with an insulating film, contact holes are formed in the insulating film above the respective sources and drains of the memory cell selecting MISFETs, and polycrystalline silicon plugs are buried into the respective contact holes. Then, after contact holes are formed in the insulating film above the respective gate electrodes, sources and drains of the MISFETs of the peripheral circuit, a high melting-point metal film such as a Ti film or a Co film is thinly deposited over the insulating film as well as the interiors of these contact holes. Then, the semiconductor substrate is heat-treated to cause the substrate (Si) and the high melting-point metal to react with each other at the bottoms of the contact holes, thereby forming a high melting-point metal silicide layer at the bottoms of the contact holes.
Then, after an interconnect-line material which mainly contains a high melting-point metal such as W is deposited over the insulating film as well as the interiors of the contact holes of the peripheral circuit, the interconnect-line material and an unreacted Ti film remaining on the surface of the insulating film are patterned to form bit lines and first-layer interconnect lines of the peripheral circuit over the insulating film. The bit lines are electrically connected to either the sources or the drains of the memory cell selecting MISFETs through the contact holes in which the polycrystalline silicon plugs are buried. The first-layer interconnect lines of the peripheral circuit are electrically connected to any of the gate electrodes, sources and drains of the MISFETs of the peripheral circuit through the contact holes of the peripheral circuit.
Then, the bit lines and the first-layer interconnect lines of the peripheral circuit are covered with an interlayer insulating film, and through holes for connecting the sources or the drains of the memory cell selecting MISFETs and information storing capacitive elements are formed in the interlayer insulating film. After that, a conducting film such as polycrystalline silicon which is deposited above the through-holes is patterned to form lower electrodes for the information storing capacitive elements each having a three-dimensional structure.
Then, after a high dielectric material such as Ta2O5 (tantalum oxide) is deposited over the surfaces of the lower electrodes, high-temperature heat treatment is performed. Any high dielectric material made of a metal oxide such as Ta2O5, BST or STO has a common nature which needs high-temperature heat treatment of approximately 800xc2x0 C. after film formation in order to reduce leak current. In addition, it is necessary to take care not to expose the degradation of the film quality to a high temperature of not less than approximately 450xc2x0 C., after such high-temperature heat treatment is performed.
Then, after a conducting film such as a TiN film is deposited over the high dielectric film, this conducting film and the underlying high dielectric material are patterned to form upper electrodes of the information storing capacitive elements and a capacitive insulating film.
However, the present inventor examined the above-described DRAM manufacturing process and found out a phenomenon in which the bit lines and the first-layer interconnect lines of the peripheral circuit peeled off the surface of the insulating film during the high-temperature heat treatment for improving the film quality of the Ta2O5 film. This is because if the Ti film used to form the Ti silicide layer at the bottoms of the contact holes remains on the insulating film formed of silicon oxide, peeling occurs at the interface between the Ti film and silicon oxide, and the reason for this is considered to be that Ti easily forms an oxide compared to Si.
As a countermeasure for preventing the peeling of the Ti film and the silicon oxide film due to high-temperature heat treatment, there is a method of removing with an acid etchant an unreacted Ti film which remains on the surface of the insulating film after the Ti film is heat-treated to form the Ti silicide layer at the bottoms of the contact holes. However, in the process step of forming the contact holes in the insulating film above the sources and drains of the MISFETs of the peripheral circuit, since contact holes are also formed above the gate electrodes of the MISFETs at the same time, if the unreacted Ti film is removed by the etchant after the formation of the Ti silicide film, the etchant also enters the contact holes formed above the gate electrodes and the metal film which constitutes the gate electrodes is etched. Accordingly, the above-described countermeasure is useful in a case where the gate electrodes are formed of a polycrystalline silicon film or a polycide film (a stacked layer made of polycrystalline silicon and high melting-point metal silicide) which has resistance to acid etchants, but cannot be applied to a case where the gate electrodes are formed of a material which mainly contains metal.
As a countermeasure for preventing peeling from occurring at the interface between the Ti film and the silicon oxide film, there is a method of replacing the Ti film with a TiN (titanium nitride) film having good adhesion to the silicon oxide film by performing heat treatment in a nitrogen atmosphere after a Ti silicide layer is formed by heat-treating the Ti film (or while the Ti silicide is being formed). However, it is difficult to completely replace the Ti film on the silicon oxide film with the TiN film by the heat treatment in the nitrogen atmosphere, so that although the surface of the film may be nitrified, the interface between the film and the silicon oxide film is not completely nitrified. In addition, if this high-temperature heat treatment is continued for a long time, the diffusion of impurities implanted in the sources and drains of the MISFETs is promoted to hinder formation of shallow junctions.
An object of the present invention is to provide the art of preventing a failure in which an underlying interconnect line peels off the surface of an insulating film during high-temperature heat treatment to be performed for improving the film quality of a high dielectric material in a DRAM in which the capacitive insulating film of an information storing capacitive element is formed of the high dielectric material.
The above and other objects and novel features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
Representative aspects of the invention disclosed herein will be described below in brief.
(1) In a semiconductor integrated circuit device according to the present invention, an interconnect line which extends with at least a portion of the interconnect line being in contact with a silicon oxide-based first insulating film is formed over the first insulating film which is formed over a principal surface of a semiconductor substrate, and a capacitive element having a capacitive insulating film at least a portion of which is formed of a high dielectric film is formed over a second insulating film formed over the interconnect line, and a portion of a conducting film which constitutes the interconnect line, which portion is in contact with the first insulating film over the first insulating film, is formed of a high melting-point metal excluding titanium or a nitride of a high melting-point metal.
(2) A semiconductor integrated circuit device according to the present invention, comprises a DRAM in which a memory cell selecting MISFET provided with a gate electrode formed integrally with a word line is formed in a first area over a principal surface of a semiconductor substrate, a bit line is formed over a silicon oxide-based first insulating film which covers the memory cell selecting MISFET, the bit line being electrically connected to either one of a source and a drain of the memory cell selecting MISFET and extending in contact with the first insulating film, and an information storing capacitive element is formed over a second insulating film formed over the bit line, the information storing capacitive element being electrically connected to the other of the source and drain of the memory cell selecting MISFET and having a capacitive insulating film at least a portion of which is formed of a high dielectric film, wherein a portion of a conducting film which constitutes the bit line, which portion is in contact with the first insulating film over the first insulating film, is formed of a high melting-point metal excluding titanium or a nitride of a high melting-point metal.
(3) In the semiconductor integrated circuit device according to the present invention described in the above paragraph (2), the high dielectric film is a tantalum oxide which is subjected to heat treatment for crystallization.
(4) In the semiconductor integrated circuit device according to the present invention described in the above paragraph (2), a conducting film which constitutes a gate electrode of the memory cell selecting MISFET is at least partly formed of a metal film.
(5) In the semiconductor integrated circuit device according to the present invention described in the above paragraph (2), a MISFET of a peripheral circuit of the DRAM is formed in a second area over the principal area of the semiconductor substrate, a first-layer interconnect line is formed over the silicon oxide-based first insulating film which covers the MISFET of the peripheral circuit, the first-layer interconnect line being electrically connected to any one of a gate electrode, a source and a drain of the MISFET of the peripheral circuit and extending in contact with the first insulating film, and a portion of a conducting film which constitutes the first-layer interconnect line, which portion is in contact with the first insulating film over the first insulating film, is formed of a high melting-point metal excluding titanium or a nitride of a high melting-point metal.
(6) In a semiconductor integrated circuit device according to the present invention described in the above paragraph (5), a titanium silicide layer is formed at a bottom of a contact hole which is opened in the first insulating film and electrically connects the first-layer interconnect line and the source or drain of the MISFET of the peripheral circuit.
(7) In a semiconductor integrated circuit device according to the present invention described in the above paragraph (5), each of the conducting films which respectively constitute the bit line and the first-layer interconnect line is a tungsten film.
(8) In a semiconductor integrated circuit device according to the present invention described in the above paragraph (5), the first-layer interconnect line is electrically connected to the source or drain of the MISFET of the peripheral circuit via a plug which is formed in the contact hole and is formed of a stacked film made of a titanium film and a barrier metal film or a stacked film made of a titanium film, a barrier metal film and a tungsten film.
(9) In a semiconductor integrated circuit device according to the present invention described in the above paragraph (5), the gate electrode of the MISFET of the peripheral circuit is formed of a metal film.
(10) In a semiconductor integrated circuit device according to the present invention described in the above paragraph (5), the first insulating film is a spin-on-glass film or a silicon oxide film deposited by a CVD method.
(11) In a semiconductor integrated circuit device according to the present invention described in the above paragraph (5), a second-layer interconnect line which is electrically connected to the first insulating film is formed over a silicon oxide-based third insulating film formed over the information storing capacitive element, and a portion of a conducting film which constitutes the second-layer interconnect line is a titanium film, the portion being in contact with the first insulating film
(12) A method of manufacturing a semiconductor integrated circuit device, comprises:
(a) forming a silicon oxide-based first insulating film over a principal surface of a semiconductor substrate and then depositing a conducting film a portion of which is in contact with the first insulating film, over the first insulating film, the portion being made of a high melting-point metal excluding titanium or a nitride of a high melting-point metal including titanium;
(b) patterning the conducting line to form an interconnect line which extends with at least a portion of the interconnect line being in contact with the first insulating film, and then forming a second insulating film over the interconnect line; and
(c) forming a capacitive element made of a first electrode, a dielectric film and a second electrode, over the second insulating film,
the capacitive-element forming step including heat treatment for improving a film quality of the dielectric film.
(13) A method of manufacturing a semiconductor integrated circuit device, comprises:
(a) forming a memory cell selecting MISFET which constitutes a memory cell of a DRAM, in a first area over a principal surface of a semiconductor substrate, and forming a MISFET which constitutes a peripheral circuit of the DRAM, in a second area over the principal surface of the semiconductor substrate;
(b) forming a silicon oxide-based first insulating film over each of the memory cell selecting MISFET and the MISFET of the peripheral circuit;
(c) forming a first contact hole in the first insulating film over at least one of a source and a drain of the memory cell selecting MISFET, forming second contact holes in the first insulating film over the respective source and drain of the MISFET of the peripheral circuit, and forming a third contact hole in the first insulating film over a gate electrode of the MISFET of the peripheral circuit;
(d) depositing a titanium film over the first insulating film as well as interiors of the respective second and third contact holes, and forming titanium silicide layers over surfaces of a source and a drain of the MISFET of the peripheral circuit which are respectively exposed at bottoms of the second contact holes, by heat-treating the semiconductor substrate;
(e) depositing a barrier metal film or a stacked film made of the barrier metal and a high melting-point metal film excluding titanium over the titanium film as well as interiors of the second and third contact holes and then forming plugs in the respective second and third contact holes by removing the barrier metal film or the stacked film over the first insulating film together with the titanium film;
(f) depositing a conducting film over the first insulating film, at least a portion of the conducting film which is in contact with the first insulating film being made of a high melting-point metal excluding titanium or a nitride of a high melting-point metal;
(g) patterning the conducting film to form a bit line to be electrically connected to one of the source and the drain of the memory cell selecting MISFET through the first contact hole, and forming a first-layer interconnect line of the peripheral circuit to be electrically connected to the MISFET of the peripheral circuit through the second contact holes or the third contact hole; and
(h) forming an information storing capacitive element made of a first electrode, a high dielectric film and a second electrode, over the second insulating film,
the capacitive-element forming step including heat treatment for improving a film quality of the dielectric film.
(14) In a method of manufacturing a semiconductor integrated circuit device according to the present invention described in the above paragraph (13), a conducting film which constitutes a gate electrode of the memory cell selecting MISFET and a gate electrode of the MISFET of the peripheral circuit is a stacked film made of a low-resistance polycrystalline silicon film doped with an impurity, a barrier metal film and a tungsten film.
(15) In a method of manufacturing a semiconductor integrated circuit device according to the present invention described in the above paragraph (13), the bit line and the first-layer interconnect line of the peripheral circuit are made of a tungsten film.
(16) In a method of manufacturing a semiconductor integrated circuit device according to the present invention described in the above paragraph (13), the dielectric film is made of a metal oxide.
(17) In a method of manufacturing a semiconductor integrated circuit device according to the present invention described in the above paragraph (16), the metal oxide is tantalum oxide.
(18) In a method of manufacturing a semiconductor integrated circuit device according to the present invention described in the above paragraph (13), heat treatment temperature for improving the film quality of the dielectric film is 750xc2x0 C. or more.
(19) A method of manufacturing a semiconductor integrated circuit device, comprises:
(a) forming a memory cell selecting MISFET which constitutes a memory cell of a DRAM, in a first area over a principal surface of a semiconductor substrate, and forming a MISFET which constitutes a peripheral circuit of the DRAM, in a second area over the principal surface of the semiconductor substrate;
(b) forming a silicon oxide-based first insulating film over each of the memory cell selecting MISFET and the MISFET of the peripheral circuit;
(c) forming a first contact hole in the first insulating film over at least one of a source and a drain of the memory cell selecting MISFET, forming second contact holes in the first insulating film over the respective source and drain of the MISFET of the peripheral circuit, and forming a third contact hole in the first insulating film over a gate electrode of the MISFET of the peripheral circuit;
(d) depositing a cobalt film over the first insulating film as well as interiors of the respective second and third contact holes, and forming cobalt silicide layers over surfaces of a source and a drain of the MISFET of the peripheral circuit which are respectively exposed at bottoms of the second contact holes, by heat-treating the semiconductor substrate;
(e) depositing a barrier metal film or a stacked film made of the barrier metal and a high melting-point metal film excluding cobalt over the cobalt film as well as interiors of the second and third contact holes and then forming plugs in the respective second and third contact holes by removing the barrier metal film or the stacked film over the first insulating film together with the cobalt film;
(f) depositing a conducting film over the first insulating film, at least a portion of the conducting film which is in contact with the first insulating film being made of a high melting-point metal excluding cobalt or a nitride of a high melting-point metal;
(g) patterning the conducting film to form a bit line to be electrically connected to one of the source and the drain of the memory cell selecting MISFET through the first contact hole, and forming a first-layer interconnect line of the peripheral circuit to be electrically connected to the MISFET of the peripheral circuit through the second contact holes or the third contact hole; and
(h) forming an information storing capacitive element made of a first electrode, a high dielectric film and a second electrode, over the second insulating film,
the capacitive-element forming step including heat treatment for improving a film quality of the dielectric film.
USPTO Backgrounds
USPTO Backgrounds