1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly to an internal voltage generating circuit within a semiconductor device.
2. Description of the Related Art
An internal voltage generating circuit regulates internal voltage at a constant predetermined value within a highly integrated semiconductor device. Generally, the internal voltage is obtained by reducing an external voltage down to the predetermined voltage level. The internal voltage generating circuit operates in either a standard mode for normal operation or a test mode for chip reliability testing depending on the externally supplied voltage. Ordinarily, a normal mode test and a stress mode test are available in the test mode.
The normal mode test uses an internal voltage regulator that lowers the external voltage to an internal reference voltage. The voltage regulator typically supplies an internal reference voltage of about +5V.
In the stress test mode, the internal voltage must be higher than the reference voltage. However, raising the internal voltage cannot be accomplished since the voltage regulator generates the predetermined reference voltage. Therefore, an output terminal of the voltage regulator circuitry has a voltage boosting circuit to execute the test. In this mode, the boosting circuit generates a boosted voltage of about 6-7 volts.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generating circuit of a semiconductor device. A voltage regulator 10 is connected between voltage supply terminals V.sub.ext and V.sub.ss and supplies a reference voltage V.sub.ref on internal voltage terminal V.sub.int. A boosting circuit 11 is connected between the voltage supply terminal V.sub.ext and the internal voltage terminal V.sub.int. Boosting circuit 11 has a plurality of serially connected PMOS transistors M.sub.1 -M.sub.n. In each of the PMOS transistors, their source electrode is connected with their substrate and their gate electrode is commonly connected with their drain electrode. The reference voltage V.sub.ref is used to perform the normal mode test. The boosting circuit 11 boosts the voltage supplied on the internal voltage terminal V.sub.int above the reference voltage V.sub.ref.
FIG. 2 is a graph showing the relationship between the internal supply voltage V.sub.int and an external supply voltage V.sub.ext of the circuit shown in FIG. 1. A low range of the external supply voltage is the range below V.sub.3. In the low range, the internal supply voltage V.sub.int generated by the voltage regulator 10 increases linearly to the value V.sub.ref. A middle range of the external supply voltage is the range between V.sub.3 and V.sub.4. In the middle range, the internal supply voltage V.sub.int remains at the reference voltage V.sub.ref. A high range of the external supply voltage is the range above V.sub.4. In the high range, the internal supply voltage V.sub.int increases linearly again. That is, the internal supply voltage V.sub.int increases proportionally to the external supply voltage V.sub.ext (after being held constant at the reference voltage V.sub.ref), when the voltage difference between the external supply voltage V.sub.ext and the reference voltage V.sub.ref exceeds a threshold voltage n.cndot.V.sub.th (the sum of the transistor thresholds) of the n PMOS transistors in the boosting circuit 11.
In other words, when the conventional internal voltage generating circuit uses the boosting circuit 11, the internal supply voltage V.sub.int is Vext-(n.cndot.V.sub.th) obtained by subtracting the summed threshold voltages across boosting circuit 11 from the external supply voltage V.sub.ext. If a plurality of PMOS transistors constituting boosting circuit 11 are used, so that the threshold voltage (n.cndot.V.sub.th) circuit 11 across boosting is large, external supply voltage V.sub.ext applied during the reliability test should be very high. In this case, the reliability of the transistors to which external supply voltage V.sub.ext is directly applied can be greatly eroded. Conversely, if the number of the PMOS transistors in the boosting circuit 11 is reduced to the minimum, the threshold voltage, (n.cndot.V.sub.th) is reduced. Therefore, the internal supply voltage V.sub.int increases at low external supply voltage V.sub.ext. Accordingly, the reliability test is not as effective.
USPTO Backgrounds
USPTO Backgrounds