1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which operates in synchronism with an external clock.
A non-volatile semiconductor memory device such as a flash ROM is widely used together with an MPU (MicroProcessor Unit) and a peripheral circuit. As the MPU and the peripheral circuit speed up, it is required that the non-volatile semiconductor memory device performs the read operation at a higher speed.
Nowadays, a synchronous-type MPU and a synchronous-type peripheral circuit are widely used, and the non-volatile semiconductor memory device is thus required to operate in a synchronous fashion.
2. Description of the Related Art
FIG. 1 illustrates a conventional non-volatile semiconductor memory device. The device includes an address buffer 401, a memory cell array 402, a word line select circuit 403, a bit line select circuit 404, a sense amplifier group 405, a sense amplifier select circuit 406, an output buffer 407. The sense amplifier unit 405 includes sense amplifier units 405a, 405b, 405c and 405d, each of which units includes 16 sense amplifiers. Thus, the sense amplifier unit 405 includes 64 sense amplifiers.
An address is applied to the address buffer 401 from the outside of the device. Then, upper and lower addresses of the external address are separated into each other and are output from the address buffer 401. The upper address is used to read data from the memory cell array 402, and the lower address is used to further select data from among the read data. The upper address is used to specify one word line WL and bit lines BL so that data stored in all memory cells connected to the selected bit lines BL are read thereto. The lower address is used to control the sense amplifier select circuit 406 so that it selects one of the sense amplifier units 405a-405d in order to latch the read data.
The non-volatile semiconductor memory device thus configured has a performance such that the time necessary to latch data in the sense amplifier group 405 responsive to the upper address is longer than the time necessary to perform the read operation of the sense amplifier group 405 responsive to the lower address. As shown in FIG. 2, the above performance results from the time it takes to read data from the selected memory cells and latch the read data in the sense amplifier group 405. Particularly, at the time of latching data in the sense amplifier group 405, there is a sense waiting time during which the potentials are not settled after the sense amplifier group 405 is activated. After the sense waiting time, the data are latched in the sense amplifier group 405. Hence, it takes a long time to latch the data in the sense amplifier group 405.
Further, referring to FIG. 2, there is illustrated a read operation performed when the burst length is equal to 4. A symbol "X" denotes a latency time starting from the time when the address is applied. The latency time X is the sum of the time necessary to read data from the memory cells and the above-mentioned sense waiting time. When the read operation with the burst length equal to 4 is repeatedly performed, data stored in the sense amplifier units 405a-405d can successively be read therefrom. However, if the address changes and a different word line WL is selected, the latency time X is needed again. Hence, the read operation cannot be performed at a high speed.
If the burst length is increased to, for example, 8, 16 or 32, an increased number of sense amplifiers such as 128, 256 or 512 is needed to realize the continuous read operation. That is, an increased number of sense amplifiers needs an increased number of sense amplifiers. However, an increased number of sense amplifiers occupies an increased chip area and causes an increased amount of current consumed in the chip.
USPTO Backgrounds
USPTO Backgrounds