1. Field of the Invention
One embodiment relates to an arithmetic processing unit.
2. Description of the Related Art
For arithmetic processing units (e.g., central processing units (CPUs)), an architecture called a stored-program system is employed in many cases. In an arithmetic processing unit using a stored-program system, an instruction and data needed for performing the instruction are stored in a memory device (e.g., a semiconductor memory device), and an instruction and data are sequentially read from the memory device and the instruction is performed.
The memory device includes a main memory device for storing data and instructions and a cache memory which can perform data writing and data reading at high speed. In order to reduce access to a low-speed main memory device and speed up the arithmetic processing, a cache memory is provided in an arithmetic processing unit, between an arithmetic unit (also referred to as an operation part) or a control unit (also referred to as a control part) of the arithmetic processing unit and the main memory unit. In general, a static random access memory (SRAM) or the like is used as a cache memory.
The capacitance of a cache memory provided in an arithmetic processing unit increases year after year. Accordingly, the proportion of power consumption of a cache memory to the total consumption of an arithmetic processing unit remarkably increases; thus, various methods have been suggested in order to reduce power consumption of the cache memory.
For example, a method in which a cache memory is divided into several blocks and the less frequently used blocks (also referred to as lines) acquired by historical information are operated with a low voltage has been suggested. Furthermore, a method for stopping power supply to a cache line which is less likely to be accessed has also been suggested.
Standby of data or the like is required for a cache memory when arithmetic operation is rarely performed. In such a case, power consumption can be reduced by saving data to a memory device with less power consumption and stopping power supply to the cache memory. Data is preferably saved to a device inside the arithmetic processing unit to ensure high-speed response.
For example, Patent Document 1 discloses a structure in which in a cache memory using a volatile memory such as an SRAM and a backup memory with excellent data retention characteristics as compared with a volatile memory, data of the volatile memory is saved (backed up) to the backup memory before power supply is stopped and the data is returned to the volatile memory (recovered) after the power supply is restarted.
USPTO Backgrounds
USPTO Backgrounds