This application relates in general to buffer circuits and more particularly to high speed low power buffer circuits useful, for example, in integrated circuit logic devices.
As the technology for producing large scale integrated deviced advances, an increasing number of devices are now fabricated on a single integrated circuit chip. To be economical and useful, large scale logic circuits must operate at relatively high speed. High speed operation usually, however, implies relatively high power consumption. It is therefore desirable to provide a buffer circuit used in integrated circuits which is capable of fast response and high speed operation and yet consumes a low amount of power.
One type of conventional buffer circuit is illustrated in the schematic diagram of FIG. 1. The conventional buffer circuit 10 comprises an inverter 12 to which the input signal Vin is applied. The output of the inverter is connected to the gate of FET 14 through the main current path of FET 16. A constant DC voltage VDD is applied to the gate of FET 16. The main current path of FET 14 connects a clock and the output of the buffer circuit. The output of the buffer circuit is also connected to ground through the main current path of an FET 18. The input voltage Vin is applied to the gate of FET 18. When Vin is high it turns on FET 18 causing the output Vout to be pulled low. When the input voltage Vin is low, FET 18 is turned off and the output of inverter 12 is high. Since FET 16 is turned on at all times by DC voltage VDD this causes the gate of FET 14 to also go high. If the clock goes high when Vin is low the gate-drain parasitic capacitance of FET 14 forces the gate voltage of FET 14 to exceed VDD. FET 16 is thereby turned off allowing the gate voltage of FET 14 to be forced even higher in a process known as bootstrapping. This causes FET 14 to be turned on even harder which reduces the delay between Vout and the clock. If the clock goes low when Vin is low, output Vout is pulled low. Thus, the output Vout follows the clock when Vin is low.
In certain integrated circuit logic applications it may be desirable to provide a buffer circuit whose output does not follow the clock exactly as in the above described conventional buffer circuit. Instead, longer duration output pulses may be desirable. For example, instead of following the clock exactly, it may be desirable for the output to change logic state at a lower frequency than the clock frequency but where the changes are synchronized with the clock. It may also be desirable for a change in the logic state of the input signal to cause a corresponding change in the output state.
USPTO Backgrounds
USPTO Backgrounds