In the semiconductor industry, many replicate components, or die, are created on a single silicon wafer. In order to eliminate faulty die prior to the cost intensive step of packaging, semiconductor fabricators typically perform wafer testing or sorting. The performance characteristics of the die are evaluated in a wafer test cell or test station by establishing electrical connectivity between the bonding pads or bumps present on each individual die and external test equipment.
A variety of wafer test cells components and configurations are possible and FIG. 1 illustrates one wafer test cell configuration. Test cell 10 may incorporate: a probe card or probe array 50 comprising an array of fine wires, formed springs or similar conductive elements known as probe pins; a test head or interface unit 30 upon which a probe array may be structurally coupled or mounted; a signal delivery system 40 which establishes electrical contact between probe array 50 and tester 80; manipulator 20 which functions to support and move test head 30, signal delivery system 40, and probe array 50; a test machine or tester 80 which is electrically coupled to probe array 50 and able to generate, detect and measure electrical signals in a manner suitable to determine the performance of the individual die on the wafer or device under test (DUT); a prober 70 which aligns the wafer to probe array 50 such that the probe pins make accurate contact with the wafer bonding pads; and a head plate 60 which facilitates docking or mating between prober 70 and the other test cell components.
In practice, wafer test cell 10 may utilize one tester controlling one or more probers with each prober contacting one or multiple DUTs of one wafer at a time. A wafer is loaded and positioned horizontally with bonding pads facing up in prober 70. Probe array 50 is loaded or secured to test head 30 such that it can be positioned horizontally with probe pins facing down. Manipulator 20 may be used to position test head 30, signal delivery system 40, and probe array 50 to head plate 60 of prober 70. A prober provides alignment functionality by developing a positional relationship between the probe array and the bonding pads of the DUT. For example, a prober may incorporate two cameras, one operable to image the probe array and one operable to image the bonding pads of the DUT. Based on the image data collected, prober will align the probe array to the corresponding bonding pads. Once a first wafer has been aligned, probers usually have a step and repeat subsystem, which permits this process to be repeated for each DUT or group of DUTs. Exemplary prober systems and functionalities are described in U.S. Pat. Nos. 6,096,567 and 6,111,421, hereby incorporated by reference in their entirety.
In other wafer test cell configurations, the various wafer test cell components described above may be integrated into one another. FIG. 1 shows some of the components, or component functionalities, that may be integrated with one another as shaded. For example, some or all of the tester, test head, signal delivery system, and probe array functionality may be integrated into a single head complex 90. In practice, head complex 90 may be coupled to head plate 80 which may in turn be mounted on to prober 70. The V5400 system, designed and manufactured by Verigy Ltd., is an example of one such an integrated wafer test cell system although other wafer test cell components and configurations may be employed for testing wafers. Generally, wafer test cells may be viewed as incorporating (1) a prober, (2) probe array, and (3) tester electronics.
Also relevant is the inspection and testing of the equipment employed in the wafer test cell. Of particular interest is the inspection and analysis of probe array 50. Wafer test probe card inspection and analysis has conventionally been performed by one of several varieties of stand-alone wafer test probe card analysis systems. Examples of probe card inspection and analysis systems are embodied in the probeWoRx® 300/200 and PrecisionPoint VX probe card analysis systems, designed and manufactured by Applied Precision LLC, of Issaquah Wash.
FIG. 2 is a block illustration of an exemplary wafer test probe card inspection and analysis system. The generalized probe card inspection and analysis system 100 comprises a probe array analyzer module 110; a motherboard 120; and the probe array 50 to be tested. Motherboard 120 is a specialized system component that adopts or docks a specific purpose probe array 50 to the general-purpose probe array analyzer module 110. Motherboard 120 provides electrical contact between probe array 50 and the measurement electronics of probe card inspection and analysis system 100. The design of the motherboard is constrained by (1) the electrical and mechanical characteristics of conventional stand alone probe card inspection and analysis system and (2) the mechanical and electrical characteristics of the specific probe card being tested. In practice, motherboard 120 functions similarly to the signal delivery system 40 and/or test head 30 of wafer test cell 10, described above and illustrated in FIG. 1.
Probe array analyzer module 110 comprises a transposable stage or fiducial plate such as a planar conductive surface which may or may not be transparent or bare fiducial marks; a mechanical positioning components such as precision actuators; imaging components such as optical lenses and an illumination sources; imaging sensors such as a CCD or CMOS, electrical probe array test components, and a computer. The probe array analysis module 110 computer may operate through hardware and software components, such as drivers, frame grabbers, and image acquisition, analysis, and pattern matching software well known in the field. Generally speaking, the computer controls the overall operation of probe card inspection and analysis system 100. The computer may be viewed as functioning, in part, analogously to tester 80 of wafer test cell 10, described above and illustrated in FIG. 1.
Conventional probe card inspection and analysis systems determine probe needle locations in three-dimensional space and analyze the movement of needles under a programmable range of loaded and unloaded conditions. Several techniques known in the art such as, traditional lead screw or optical comparative metrology may be employed to determine probe pin locations. For example, probe pin locations may be determined by scanning the pins across a conductive and/or nonconductive transition on a stage as disclosed in U.S. Pat. Nos. 4,918,374, 5,508,629, and 5,831,443, which are hereby incorporated by reference in their entirety. Probe pin locations may also be determined by a combination of a precision motion stage and a video camera as described in U.S. Pat. No. 5,657,394, which is hereby incorporated by reference in its entirety. Alternatively, probe pin positions may be determined by utilizing a fiduciary plate having a plurality of fiduciary marks and a digital imaging device, as disclosed and claimed in U.S. Pat. No. 6,710,798, which is hereby incorporated by reference in its entirety.
Probe card inspection and analysis systems may also be operable to evaluate other probe card characteristics including, for example, probe card planarity, probe array planarity, probe card alignment, probe card pin alignment, electrical planarity, optical planarity, no-load planarity, loaded planarity, probe card/fixture deflection, leakage, wirechecker, probe force, and contact resistance. Probe card inspection and analysis systems may also be equipped with electrical signal generation and detection capabilities suitable to determine the functionality or characterize the performance of certain electronic components that may be incorporated into probe card circuit designs. Such components include voltage sources, voltage meters, current sources, current meters, multiplex electronics, relays, electronic buffers, MUX switches, electronic memory devices, communication circuitry and the like. Some probe card inspection and analysis systems may also incorporate probe card rework functionality.
Over the last decade, there has been a trend to increase the parallelism of wafer testing, particularly, for dynamic and flash memory testing. This allows devices with long test times to be processed more efficiently and thereby reduce cost. The current trend is to design and manufacture wafer test cell components such that a wafer is tested in a minimum number of touches, i.e. a probe array is brought into contact with a single wafer one time in order to facilitate testing of each DUT on the wafer.
As parallelism in wafer testing increases so does the complexity, size and weight of the previously described wafer test head components. For example, as parallelism increases so does the number of probe pins in the probe array. The increased number of pins necessitates the application of higher forces in order to contact the pins to the pads or bumps of the DUT. The use of higher forces in turn requires the implementation of more structurally rigid components, components with increased sizes and/or weights. These components generate interactions between the test head, probe card, and prober unique to a specific test cell. The conventional probe card inspection and analysis system is structurally limited in its ability to mimic or otherwise simulate these unique characteristics of a wafer test cell. As a result, the results obtained from a conventional probe card inspection and analysis system may be of increasingly limited value when used to troubleshoot problems in the increasingly complex probing process. What is needed in the field is an apparatus and method for the inspection and analysis of probe arrays under conditions that more closely correlate with the real-world conditions of the wafer test cell.
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