1. Field of the Invention
The present invention generally relates to a microcomputer which includes a processor and a memory integrated on the same substrate, and more particularly to a circuit configuration between the processor and the memory, and a layout of buses for connecting the processor and the memory.
2. Description of the Related Art
When a processor and a memory are not integrated on the same chip, and a bus between the processor and the memory is wide enough not to decrease a processing function of the processor, it is necessary to provide respective chips loading the processor and loading the memory with pins for the connection therebetween. This unavoidably increases power consumption and production costs. To solve these problems and to improve a processing efficiency of the processor, there are arts of active interest for integrating the processor and the memory on the same chip of one body. However, general use processors are usually different in the manufacturing process and design from general-use large-capacity memories, which makes it considerably difficult to simply apply the existing technique to the processors and memories for the above purpose.
First, the manufacturing process will be explained. Although general memories use two layers of wirings at most, many steps are carried out to make each cell of the memory fine. On the other hand, a multi-layer wiring is often employed in the processor to improve a degree of integration.
Next, the concept of design will be explained. The memory is designed in such a layout as to optimize analog characteristics, e.g., a cell capacity and a wiring delay, and therefore changing the layout requires a lot of time and costs. FIG. 1 shows an example of the layout of a 16-Mbit DRAM. A common 16-Mbit DRAM has 4-Nbit cell regions arranged in the form of arrays. On the other hand, for the processor, particularly a control logic unit, a CAD tool (automatic arranging/wiring tool) is utilized which allows an automatic layout in a given region. In other words, the processor is allowed a high degree of freedom for changing the layout.
The following method may be proposed to integrate general-purpose processors and large-capacity memories in one chip under the aforementioned conditions. That is, a manufacturing process is based on that for the memory, while the conventional layout for the memory is also shared without being changed for the memory cell regions. The processor is made as small as possible so as to eliminate influences of degrading characteristics due to the fact that the manufacturing process is a memory basis. With the degree of freedom for changing the layout utilized, the processor is arranged in a gap in the memory.
For example, in "Proposal of New General-purpose Functional Part PPRAM toward 21st Century, by Mlurakami et al., Computer Architecture Research Report No. 108, 94-ARC-108, pp. 49-56, The Information Processing Society, Research Report Vol. 94, No. 91, ISSN 0919-6072", there is proposed a PPRAM (Parallel Processing Random Access Memory, Practical Parallel Random Access Machine) in which four general purpose processors 11 are arranged in parallel on one side of the chip, and arranged in the remaining region are a plurality of memory cell regions 12a of a general-purpose memory 12 in the form of arrays.
In the layout shown in FIG. 2, the memory cell regions 12a are located at different distances from the general-purpose processors 11 depending on their positions. The longer the distance, the longer the bus is, with the result that a delay in data transmission is increased. The difference in length of buses causes a difference in the data transmission time, necessitating an adaption in data transmitted from faster to slower. Further, when the length of the bus is lengthy, an area on the layout required for the bus is larger.
Also, in the Japanese Patent Application Laid-Open No. 5-94366(1993), there is disclosed a microcomputer in which a CPU 14 is installed in a gap between two memory spaces 13, and arranged at one side in parallel to the row of the CPU 14 and memory spaces 13 are an address bus 15 and a data bus 16 as shown in FIG. 3.
In this microcomputer, the address bus 15 and the data bus 16 provided at one side of the row of the memory spaces 13 and the CPU 14 are required to be the same length as the row, and therefore the length is undesirably elongated if the memory spaces 13 are large.
Further, in the Japanese Patent Application Laid-Open No. 63-81569(1988), there is disclosed a microcomputer in which a plurality of modules 31, 32 and 33 having respective functions as memories and peripheral circuits, and a CPU 34 are set in a manner to be generally of the same width, with a bus 35 arranged at one side in parallel with the row of the modules 31, 32 and 33 and the CPU 34, as shown in FIG. 4. In the disclosed microcomputer, when the modules 31, 32, and the CPU 34 are arranged in two rows, the bus 35 is provided between the rows (FIG. 5). If the modules 31, 32, . . . and the CPU 34 each having a different width are used, the bus 35 is disposed in the perimeter of the modules, that is, in the periphery of the chip (FIG. 6). In any of FIGS. 5 and 6, the CPU 34 is located generally at the center of the modules 31, 32, . . . In addition, the modules 31, 32 . . . , and the CPU 34 face straight to the bus 35.
In this art, however, the same problem as discussed above remains. That is, when the bus 3D is arranged in parallel with the row of the modules 31, 32, 33 and the CPU 34, and when the bus 35 is arranged in the perimeter of the modules 31, 32. . . and the CPU 34, namely, in the periphery of the chip, the larger module elongates the bus.
Also, in the configuration in which the bus (15, 16 or 35) is provided at the lateral side of the memory spaces 13 (or the modules 31, 32, . . .) and the CPU 14 (or 34), such a disadvantage arises in to that the area required for forming the bus is increased in proportion to a count of bits.
FIG. 7 is a schematic plan view showing a connecting part between a processor and a memory in a conventional microcomputer. Buses B.sub.a, B.sub.b, and B.sub.c connects a CPU 3 and a memory cell region 2 as shown in FIG. 7. In general, the buses B.sub.a, B.sub.b, and B.sub.c have the same width. This structure where the buses for connecting the processor and the memory have the same width is usually employed both when the CPU and the memory cell regions are integrated in one chip and when the CPU and the memory cell regions are provided on separate chips.
However, when an operation speed in the memory cell region 2 is lower than that in the CPU 3, the operation speed in the CPU 3 is matched to the operation speed in the memory cell region 2. Consequently, the CPU 3 does not fully exert its processing efficiency at present.
Still further, in the Japanese Patent Application Laid-Open No. 2-87283 (1990), there is disclosed a semiconductor integrated circuit device including a serial/parallel converter for converting a bus connection between a CPU and a peripheral circuit to a serial connection, and a clock multiplying circuit, whereby a count of bus wirings is decreased.
Still further, in the Japanese Patent Application Laid-Open No. 7-153257 (1995), there is disclosed a semiconductor memory comprising a DRAM and an SRAM mounted on the same chip, wherein the DRAM is accessed from outside via the SRAM.
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