1. Field of the Invention
The present invention relates to an integrated circuit design method and a related system, and more particularly, to an integrated circuit design method for improving placement and routing (P&R) by rotating a metal track direction of metal layers of ultra high speed cells.
2. Description of the Prior Art
With the development of semiconductor technology, conventional electronic elements (such as capacitors and resistors) can be integrated into a chip. Hence, during a semiconductor manufacturing process, an integrated circuit (IC) can be produced by connecting metals on the chip. Due to ICs being widely applied to miscellaneous electronic products, planning a floor plan, power plans, placements of the IC, and routing between elements have become an important topic of this field.
IC design methods are divided into several kinds: full-custom design, gate array design, and standard cell design, wherein the standard cell design brings designed element modules together to form a large-scale circuit by utilizing a cell library. Pluralities of library cells are usually built in the cell library, wherein a normal cell and an ultra high speed cell are the most common library cells. Please refer to FIG. 1 and FIG. 2. FIG. 1 (including 1A and 1B) is a diagram showing metal layers of a conventional normal cell and a conventional ultra high speed cell according to the prior art. FIG. 2 (including 2A and 2B) is a diagram showing the power rails of the normal cell and the ultra high speed cell shown in FIG. 1. As shown in FIG. 1, the normal cell and the ultra high speed cell respectively consist of a plurality of metal layers. The normal cell consists of six metal layers M11-M16, as is shown in 1A. The ultra high speed cell consists of six metal layers M21-M26, as is shown in 1B. A metal track direction of the odd metal layers M11, M13, and M15 of the normal cell is perpendicular to that of the odd metal layers M21, M23, and M25 of the ultra high speed cell. A metal track direction of the even metal layers M12, M14, and M16 of the normal cell is perpendicular to that of the even metal layers M22, M22, and M26 of the ultra high speed cell. As shown in 2A, the power rail of the normal cell uses the first metal layer M11 as its power mesh and has a height of 3.2 μm. As shown in 2B, the power rail of the ultra high speed cell uses the second metal layer M22 as its power mesh and has a height of 4 μm.
However, if the conventional normal cell and the conventional ultra high speed cell are desired to be placed in the same IC design, extra wirings and extra vias are required to complete the power plans and the placement and routing (P&R) of the IC design due to the metal track directions of the normal cell being different from that of the ultra high speed cell. As a result, the cost is raised.
USPTO Backgrounds
USPTO Backgrounds