The present invention relates in general to BiCMOS output buffers and, more particularly, to a 3-state BiCMOS output buffer that can be placed in a power-down mode and remain impervious to voltage supply and external interface bus conditions.
It is known in the art that output buffers, hereinafter referred to as buffers, are used in large scale integrated circuits and in electronic systems to drive bus lines. These buffers may be located on the same integrated circuit die or on different die, depending upon the system configuration. A multiple of buffers may also be connected to a common bus line that in turn is connected to the addressing inputs of such devices as microprocessors, memories and registers. These buffers typically incorporate 3-state features to remove output buffer signals that are not required on the output bus for given signal conditions.
In order to reduce power consumption, it is desirable to inactivate circuitry that is not in use, such as the output buffer. It is also advantageous to incorporate circuits powered by one power supply voltage but able to interface to devices powered by different power supply voltages within the bussed system.
However, when utilizing reduced power technology, undesirable conditions can develop between the bus line and the power supply line of the inactive powered down buffer. For example, in a typical BICMOS output buffer, a PMOS transistor is used as an upper driving transistor. It is desired that a bus line, that is driven by an active buffer, maintain the voltage level and current drive capability that is presented by the active buffer even when a co-existing bus buffer is powered down and rendered inactive. Typically, a bus line, at some point in time, will receive an output from an active buffer whose output is in a high state while the commonly bussed buffer will be in a powered down state. When this occurs, the upper PMOS driving transistor of the powered-down buffer will experience abnormal biasing conditions. The drain of the transistor, p-type semiconductor material, will continue to be biased at the voltage level of the bus line. However, this voltage can be near the higher power supply voltage rail. Since the power supply voltage of the powered down buffer has collapsed; the source of the PMOS transistor will reside at zero volts. The backgate of the PMOS transistor, which is n-type material and typically biased to the same potential as the source of the transistor, also resides at zero volts. Thus, a parasitic pn diode is formed from the drain of the transistor to the collapsed supply voltage, producing an undesirable path for current to be displaced from the bus line.
To combat this condition, a diode is sometimes placed between the power supply and the backgate of the PMOS transistor to establish a blocking structure to the current. However, the diode solves only a portion of the problem. If the inactive circuit was placed in a 3-state mode prior to powering down, a second current robbing mechanism is activated. In this case, the drain, source, and backgate of the PMOS structure remain as described above, but the gate is now biased at or near zero volts. In this situation, the PMOS transistor is now made active in an inverse mode and again conducts current away from the bus line thereby negating the positive effect of the diode.
Hence, a need exists for an efficient power down circuit that is capable of inactivating a given buffer circuit on a bus line while maintaining the integrity of the required voltage level and the required current driving conditions of the bus line.
USPTO Backgrounds
USPTO Backgrounds