1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and, more particularly, to a TFT, a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same.
2. Description of the Related Art
Television products are the major application targets in the remarkably growing flat panel display market. Currently, a liquid crystal display (LCD) is a mainstream as a TV panel, and research into an application of an organic light emitting display device to TVs has been actively ongoing.
Current TV display techniques are focused on major items required in the market, and the requirements in the market include a large-scale TV or digital information display (DID), low cost, high picture quality (video representation performance, high resolution, brightness, contrast ratio, color gamut, and the like).
In order to meet the requirements, a thin film transistor (TFT) that may be applied as a switching and driving element of a display having excellent performance without increasing cost, together with an increase in the size of a substrate such as glass, or the like, is required.
Thus, development of techniques in the future is expected to be focused on securing a TFT fabrication technique capable of fabricating a display panel having excellent performance at low cost according to such tendency.
An amorphous silicon TFT (a-Si TFT) as a typical driving and switching element of a display is a currently commonly used element that may be uniformly formed on a large substrate having a size exceeding 2 m at low cost.
However, as displays tend to have a large size and high picture quality, high device performance is required, and thus, it is determined that an existing a-Si TFT having mobility of 0.5 cm2/Vs has reached a limitation.
Thus, a high performance TFT having mobility higher than that of a-Si TFT and a fabrication technique thereof are required. Also, a-Si TFT has a problem of reliability in that as it continues to operate, device characteristics continue to be degraded to result in a failure of maintaining initial performance.
This is the reason why the a-Si TFT is hardly applied to an organic luminescence emitted diode (OLED) that operates while a current is continuously applied, in comparison to an LCD driven by an AC.
A polycrystalline silicon TFT having remarkably high performance relative to an a-Si TFT has high mobility ranging from tens to hundreds of cm2/Vs, so it has performance applicable to a display having high picture quality hardly realized by the existing a-Si TFT and rarely degrades device characteristics according to an operation in comparison to the a-Si TFT. However, a fabrication of a poly-Si TFT requires a large number of processes in comparison to the a-Si TFT and investment in additional equipment should be made first.
Thus, p-Si TFT may be appropriately applied to make a display have high picture quality or applied to a product such as an OLED, or the like, but it is inferior to the existing a-Si TFT in terms of cost, so an application thereof is limited.
In particular, in the case of a p-Si TFT, due to a technical issue such as a limitation in fabrication equipment or a defect in uniformity, a fabrication process using a large substrate having a size of 1 m has not been realized so far, so the difficulty of the p-Si TFT in its application to a TV product is a factor making it difficult for high performance p-Si TFT to be easily settled down in the market.
Thus, demand for a new TFT technique that may support the advantages (large size, low cost, and uniformity) of the a-Si TFT and the advantages (high performance and reliability) is highly on the rise, and research into the new TFT technique has been actively ongoing. An oxide semiconductor is a typical one thereof.
An oxide semiconductor has advantages in that it has high mobility in comparison to an a-Si TFT and simpler fabrication process and lower fabrication cost in comparison to a polycrystalline silicon (p-Si) TFT, and thus, it is of a high utility value in an LCD or an OLED.
In this point of view, a structure of an oxide TFT according to the related art using an oxide semiconductor will be described with reference to FIGS. 1 to 3.
FIG. 1 is a plan view of an oxide TFT structure according to the related art.
FIG. 2 is a schematic sectional view of the oxide TFT according to the related art, taken along line II-II in FIG. 1.
FIG. 3 is an enlarged sectional view of a portion ‘A’ in FIG. 2, illustrating a distance between an etch stop layer pattern and source electrode and drain electrode.
As illustrated in FIGS. 1 to 3, the oxide TFT 10 according to the related art includes a patterned gate electrode 13 formed on a substrate 11 and having a certain width and length, a gate insulating layer 15 formed on the entire surface of the substrate 11 including the gate electrode, an active layer 17 formed on an upper portion of the gate insulating layer 15 including an upper side of the gate electrode 13 and made of an oxide semiconductor patterned to have a certain shape, an etch stop layer 19 formed on the active layer 17 and patterned to have a certain shape, and a source electrode 21 and a drain electrode 23 spaced apart from one another on an upper portion of the etch stop layer 19 and formed on upper portions of the active layer 17 and the gate insulating layer 15.
Here, the etch stop layer 19 overlaps with the gate electrode 13 and the active layer 17, and is formed on an upper portion of a channel region of the active layer 17.
Also, the source electrode 21 and the drain electrode 23 are formed to be spaced apart on an upper portion of the etch stop layer 19 and formed on the etch stop layer 19, the active layer 17, and the gate insulating layer 15.
In this case, a first width W1 in which the source electrode 21 and one side of the etch stop layer 19 overlaps is different from a second width W2 in which the drain electrode 23 and the other side the etch stop layer 19 overlaps.
Namely, as shown in FIGS. 1 and 3, the first width W1 in which the source electrode 21 and one side of the etch stop layer 19 overlaps and the second width W2 in which the drain electrode 23 and the other side the etch stop layer 19 overlaps are different due to misalignment of a mask during a process of fabricating the source electrode and the drain electrode of the oxide TFT. Here, the first width W1 is longer than the second width W2. This is caused as the mask (not shown) is shifted to the other side of the etch stop layer 19 when the source electrode and the drain electrode are formed.
In particular, when the oxide TFT is fabricated, a process of forming the etch stop layer 19 and a process forming the source electrode 21 and the drain electrode 23 are performed through different masking processes, so there is a possibility in which the source electrode 21 and the drain electrode 23 and the etch stop layer 19 are misaligned.
Thus, in the case of the oxide TFT according to the related art, an ON current of the oxide TFT or a threshold voltage Vth is shifted due to the misalignment caused between the source electrode 21 and the drain electrode 23 and the etch stop layer 19.
In addition, in the oxide TFT according to the related art, since the process of forming the etch stop layer 19 and the process of forming the source electrode 21 and the drain electrode 23 are performed in different masking processes, the number of masking processes is increased to increase fabrication costs.
USPTO Backgrounds
USPTO Backgrounds