1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit and a fabrication process thereof, and more particularly, to a layout structure of an electrostatic discharge protection circuit applicable in an integrated circuit, and a fabrication process thereof.
2. Description of Related Art
The main architecture of an electrostatic discharge protection circuit includes a protection element and a resistor, wherein the resistor is a current-limiting resistor. This architecture effectively enhances the capability for electrostatic discharge (ESD) protection. As shown in FIG. 11, in the layout design of a conventional electrostatic discharge protection circuit, the resistor 30 is disposed outside the protection element 40, and thus occupies an additional area. Moreover, this layout causes the overlapped area between the drain D of the protection element 40 and the substrate to be relatively large, so that a relatively large parasitic capacitance will be formed, which influences the operating performance of the chip, and causes the problem of crosstalk.
As the transmission speed in telecommunications is increasingly enhanced and the frequency of operating interface circuits is increasingly high, a signal transmission interface circuit with higher quality and higher speed is required. To solve the above problems, a conventional solution is to add protection circuits around signal lines with excessive large capacitance, and the protection circuits are connected to a stable signal source (normally the ground or a power source), so as to form a masking effect to isolate the signal lines. Another solution is to prevent the aforementioned effect by increasing the distance between two signal lines. However, although the problems are solved, the conventional solutions both require additional space.
USPTO Backgrounds
USPTO Backgrounds