1. Field of the Invention
The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same and, more particularly, to an apparatus for generating a clock signal with jitter, which can output clock jitter by applying the sum of a signal having a specific waveform, which is generated from a waveform generator, and a power source signal to a phase-locked loop (PLL) circuit unit as a power source, and a test apparatus including the same.
The present invention has been induced from researches made as a part of IT Growth Power Technology Development by Ministry of Information and Communication and Institute for Information Technology Advancement, Republic of Korea, [Project Management No.: 2006-S-001-02, Project Name: Development of Adaptive Wireless Access and Transmission Technology for Fourth-Generation Mobile Communication].
2. Discussion of Related Art
Clock jitter is a distorted clock signal, which appears as an ideal clock signal transits fast or slowly from a reference point as much as a specific time. Clock jitter can be generated due to a system-inherent problems, such as crosstalk and impedance mismatch, data-inherent characteristics such as inter-symbol interference and cyclic distortion, and/or random noise such as heat noise.
In a reliability test of a specific device, a test on a case where clock jitter is applied is indispensable. Jitter can be generated by a variety of factors, such as system problems, applied data problems, and/or noise. In the case in which clock jitter is applied, clock jitter must be applied to a device using an artificial apparatus for generating a clock signal with jitter so as to test the stability of an output signal of the device.
A general apparatus for generating a clock signal with jitter is configured to separate low frequency components and high frequency components from predetermined jitter data, control an oscillation frequency of an oscillation circuit unit according to the jitter data of the low frequency components, and control the delay amount of an oscillation signal according to the jitter data of the high frequency components. However, if the above method is used, the device must include a digital-to-analog converter (DAC) for converting jitter data into analog data, and a filter for filtering low frequency components and high frequency components from jitter data. Accordingly, the complexity of the device can be increased.
USPTO Backgrounds
USPTO Backgrounds