The very small and very large numbers of circuits on the integrated circuit die, generally require some housing and protection from the system or product environment. This housing and protection often takes the form of an integrated circuit package that provides a mechanism for making electrical interconnection between the circuits on the integrated circuit die and the leads that are utilized to make electrical interconnections to circuits, power, and ground external to the integrated circuit die. For early types of integrated circuits, the packaging of the integrated circuits was relatively straightforward and generally involved an array of leads arranged around a die cavity to be electrically connected to associated die pads. There were also relatively few circuits on each integrated circuit die, and the circuit operational rates were by modern day standards relatively slow.
Across virtually all applications, there continues to be growing demand for reducing size and increasing performance of integrated circuits. The seemingly endless restrictions and requirements are no more visible than with products in our daily lives. Smaller and denser integrated circuits are required in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc. As the demand grows for smaller electronic products with more features, manufacturers are seeking ways to include more features as well as reduce the size of the integrated circuit packages. To meet these needs, packaging technologies are increasingly using smaller form factors with more circuits.
Wafer manufacturers strive to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality. Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices. Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future. However, significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to integrated circuit packaging as a means to fulfill the relentless demands for enhanced system performance.
Drawbacks of conventional designs include a relatively large footprint of the package on the mounting surface of motherboard. The footprint typically reflects the maximum planar dimension of the package, namely, the x-y dimension of the package. In applications where mounting space is at a premium, such as pagers, portable telephones, and personal computers, among others, a large footprint is undesirable at best. With the goal of increasing the amount of circuitry in a package without increasing the area of the package, so that the package does not take up any more space on the circuit board, manufacturers have been stacking two or more die within a single package. Unfortunately, sufficient overlap for electrical interconnect and large footprint top packages have plagued previous stacked package or package on package designs.
Thus, a need still remains for an integrated circuit package system to provide improved function, area, volume, and manufacturing yield. In view of the increasing demand for improved integrated circuits and particularly more functions in smaller products at lower costs, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
USPTO Backgrounds
USPTO Backgrounds