1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to a circuit for driving a ferroelectric memory.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has a data processing speed as fast as a DRAM and conserves data even after the power is turned off. The FRAM includes capacitors similar to the 45 DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not lost even after eliminating an electric field applied thereto.
FIG. 1A illustrates a general hysteresis loop of a ferroelectric substance, and FIG. 1B illustrates a construction of a unit capacitor in a background art ferroelectric memory. As shown in the hysteresis loop in FIG. 1A, a polarization induced by an electric field does not vanish, but remains at a certain portion ("d" or "a" state) even after the electric field is cleared due to an existence of a spontaneous polarization. These "d" and "a" states may be matched to binary values of "1" and "0" for use as a memory cell. Referring to FIG. 1B, the state in which a positive voltage is applied to a node 1 is a "c" state in FIG. 1A, the state in which no voltage is applied thereafter to the node 1 is a "d" state. Opposite to this, if a negative voltage is applied to the node 1, the state moves from the "d" to an "f" state. If no voltage is applied to the node 1, thereafter the state moves to an "a" state. If a positive voltage is applied again, the states moves to the "c" state via the "b" state. At the end, even if there is no voltage applied on both ends of a capacitor, a data can be stored in stable states of "a" and "d". On the hysteresis loop, "c" and "d" states correspond to a binary logic value of "1", and "a" and "f" states correspond to a binary logic value "0".
In reading a data from the capacitor, the "d" state is destroyed to read the data stored in the capacitor. In a background art, a sense amplifier is used for reading a data using a voltage generated in a reference voltage generator and a voltage generated in a main cell array. In a ferroelectric reference cell, two modes of "1" polarity and "0" polarity are used for generating a reference voltage on a reference bit line. Accordingly, the sense amplifier compares a bit line voltage on a main cell and a reference bit line voltage on a reference cell, to read information in the main cell. By rewriting the read data within the same cycle, the destroyed data can be recovered.
Referring to FIG. 2, the array of the background art ferroelectric memory cells, each unit memory cell having two transistors and two capacitors (2T/2C) is provided with a plurality of wordlines W/L arranged in one direction and spaced at fixed intervals. A plurality of platelines P/L are arranged parallel to the wordlines and between each of the wordlines W/L. A plurality of bitlines B.sub.-- n, B.sub.-- n+1 and bitbarlines BB.sub.-- n, BB.sub.-- n+1 are arranged alternatively and in a direction vertical to the wordlines W/L and the platelines P/L.
The gate electrodes of the two transistors T1 and T2 in a unit memory cell 21 are connected to an adjacent wordline W/L in common, and the source electrodes of the transistors T1 and T2 are connected to an adjacent bitline B.sub.-- n and bitbarline BB.sub.-- n, respectively. The drain electrodes of the transistors T1 and T2 are connected to the first electrodes of two capacitors, respectively, while the second electrodes of the capacitors are connected in common to an adjacent plateline P/L.
The array of the background art 2T/2C FRAM cells writes and reads a logic value "1" or "0" as follows. Referring to FIG. 3A, in a writing mode, when a chip enable signal CSBpad transits from a "high" to a "low" externally, the array is enabled, and simultaneously, a writing mode enable signal WEBpad also transits from a "high" to a "low" to provide "high" and "low" or "low" and "high" signals to the bitline and the bitbarline according to a logic value intended to be written. An address is decoded to transit a wordline signal of a selected cell from a "low" to a "high" for selecting the cell.
During an interval in which the wordline is held at a "high", a "high" signal of a fixed interval and a "low" signal of fixed interval in succession are applied to a corresponding plateline P/L. For writing a binary logic value "1", a "high" signal is applied to a bitline B.sub.-- n and a "low" signal is applied to a bitbarline BB.sub.-- n. For writing a binary logic value "0", a "low" signal is applied to a bitline B.sub.-- n and "high" signal is applied to a bitbarline BB.sub.-- n. Thus, either a logic value "1" or a logic value "0" can be written into the capacitor C1 or C2.
Referring to FIG. 3B, when a chip enable signal CSBpad transits from a "high" to a "low" and a write mode enable signal WEBpad transits from a "low" to a "high", the write mode is deactivated and a read mode is enabled. Before selection of a required wordline, all bitlines are equalized to a "low" level by an equalization signal. After completion of the equalizing to the "low" level, an address is decoded to transit a signal on the required wordline from a "low" to a "high" for selecting a corresponding unit cell. A "high" signal is applied to a plateline of the selected cell to cancel a data on the bitline or the bitbarline.
In other words, if a logic value "1" is written, a data in a capacitor connected to the bitline will be destroyed, and if a logic value "0" is written, a data in a capacitor connected to the bitbarline will be destroyed. Thus, depending on the data destroyed on the bitline or on the bitbarline, a value different from each other is provided according to the hysteresis loop characteristics. When the data provided through either the bitline or the bitbarline is sensed by the sense amplifier, the data value will be either logic "1" or logic "0". After the sense amplifier amplifies and provides the data, since the cell should have the data recovered, during the required wordline is applied of "high", the plateline is disabled from a "high" to a "low".
The background art ferroelectric memory has various problems and/or disadvantages. Despite the advantage of data conservation even after the power is turned off, the cell plate line separately required in the FRAM which causes a complicated layout as well as a complicated fabrication process such separate platelines are a disadvantage for mass production. Further, the provision of a control signal to the plateline for data reading and writing degrades efficiency as a memory device.
The background art FRAM also can not solve a problem of integration if a new electrode material and a new barrier material are not provided. In view of the integration, there is another problem in that the incapability of formation of a capacitor directly on a silicon substrate or a polysilicon caused by an inadequate development of the technology of forming a ferroelectric film directly on a silicon surface leads to fabricate a FRAM having an area greater than a DRAM. Moreover, the different transmission paths of control signals through the wordlines and the cell platelines individually result in an inaccurate control.
USPTO Backgrounds
USPTO Backgrounds