The present invention relates to a cache memory and a control method thereof, and specifically, to a cache memory employing a set associative system and a control method thereof.
Conventionally, a cache memory is arranged especially between a processor and a high-capacity and low-speed main memory, and stores commands, data and so forth which are frequently accessed, and thereby, shortens access time of an entire system. For such a cache memory that shortens the access time of the entire system, a set associative system is widely being used, in which a plurality of places where each block is allocatable exist in order to improve a hit rate of the data.
In the cache memory employing this set associative system, a storage region of the memory is divided into a plurality of sets, and an address tag of a data is stored for each set in a tag memory. And, the address tag read from the tag memory is compared with an access address, and a hit/miss-hit signal is generated from a comparison result, and the data memory in which the data is stored is accessed.
Usually, in each block of the tag memory, together with the tag address, a valid bit (a valid bit) for showing whether the contents of the data memory corresponding to the address is valid or invalid is stored. When the tag address read from the tag memory is compared with the access address, the valid bit is read for every way of each set. And, in case that, as a result of the comparison, both addresses coincide with each other, and a way for which the valid bit shows “validity” exists, access to the data memory becomes possible.
The cache memory employing such a set associative system is widely being used for generally making a function of a processor higher. And, in recent years, it is required that flash of the cache memory employing the set associative system is performed one clock.
As a technology for performing the flash of the cache memory employing the set associative system one clock, JP-P1990-90348A is disclosed. In a cache memory employing the set associative system of JP-P1990-90348A, the tag address is divided from a valid bit register for storing a valid bit therein, and by means of memory means for memorizing the valid bit, all clear operation at one cycle is conducted.
However, in case of employing the set associative system having an n-way/k-set arrangement in the cache memory of JP-P1990-90348A, the number of the valid bit registers becomes n×2k, and a circuit scale of the cache memory increases. And, in association with the increase of the circuit scale of the cache memory, electric power consumption consumed in the cache memory increases. Specifically, in association with the increase of a way number, the circuit scale infinitely increases, and in association therewith, the electric power consumption infinitely increases.
Further, if the number of the valid bit registers becomes greater, in performing write into the cache memory and read from the cache memory, a control circuit for selecting the valid bit registers becomes complicated. Accordingly, there is a task that a time period necessary for the writing into and reading from the valid bit increases, and the speed of the cache memory becomes lower.
As described, in the conventional cache memory, there is a task that, even though clear operation can be performed, the circuit scale of the cache memory itself is enlarged.
USPTO Backgrounds
USPTO Backgrounds