1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having an error correcting function that employs an error correcting code (hereinafter referred to as "ECC").
2. Description of the Art
With the achievement of high integration of semiconductor memories, the size of memory cells has been reduced and, as a result, so-called soft errors, that is, the phenomena that information stored in memory cells are destroyed by alpha particles or the like, have become a serious problem. To cope with this problem, it is an effective practice to employ an error correcting method such as that discussed, for example, in ISSCC Digest of Technical Papers, pp. 22-23, February, 1987. Error correction will be briefly explained hereinunder.
Error correction is a procedure wherein redundant bits (i.e., test bits) are added to bits carrying information which is to be stored (i.e., information bits) according to a certain rule to impart redundancy to the data, thereby detecting and correcting an error occurring in a part of the data in the light of the certain rule. Error correcting codes constitute a system, which provides a rule according to which check bits are added to give information bits so that error correction is available. Such error correcting codes include two dimensional codes and multi-dimensional codes, and two dimensional codes include Hamming codes, horizontal and vertical parity, BCH codes, etc.
The procedure of error correction is carried out in two steps, that is, the step of calculating a syndrome and the step of correcting an erroneous bit by the use of the syndrome. Syndrome is an extract from information concerning errors in data and it is arithmetically obtained by selecting some bits from data according to a certain rule and making a check for the parity (even or odd error correcting code) of the selected bits. It should be noted that error correcting codes and error correcting methods that employ the same are described in detail, for example, in Miyagawa et al. "Code Theory", Shokodo.
As described above, to cope with soft errors, it is an effective practice to employ a method whereby errors are corrected. This error correcting method suffers, however, from the following problems.
It is necessary, in order to effect error correction, to add check bits to bits carrying information which is to be stored. Since extra memory cells are needed to store the check bits, it is preferable to minimize the number of check bits employed. It is, however, known from the code theory that there is a lower limit to the number of check bits needed for error correction. According to the code theory, it is necessary, in order to enable correction of a single erroneous bit among a total of (k+m) bits, to satisfy the following condition: EQU k.ltoreq.2.sup.m -1-m (1)
where
k: the number of information bits employed to effect a single error correction PA1 m: the number of check bits employed to effect a single error correction
It will be understood from the above expression that, the larger the value of m, the smaller the redundancy m/k of the code. For example, EQU if k=32, then m.gtoreq.6 and therefore m/k.gtoreq.0.19; EQU if k=64, then m.gtoreq.7 and therefore m/k.gtoreq.0.11; and EQU if k=128, then m.gtoreq.8 and therefore m/k.gtoreq.0.06.
Accordingly, it is only necessary in order to decrease the redundancy to increase the number k of information bits which are employed to effect a single error correction.
On the other hand, the error correction circuit that is used to effect error correction needs (k+m)-bit inputs. More specifically, (k+m) wirings are needed between a memory array and the error correction circuit. Accordingly, it is preferable to reduce the value of k from the viewpoint of the number of wirings required.
One method which is contrived to satisfy the above-described requirements which are contrary to each other is presented in Japanese Patent Laid-Open No. 62-119800 (1987). FIG. 7 is a block diagram of a semiconductor memory which is shown in the specification of the above-described Japanese Patent Laid-Open No. 62-119800 (1987). In the figure, the reference numeral 11 denotes a memory array, 12 memory blocks for storing information bits, 13 a memory block for storing check bits, 17 multiplexers, 18 output buffers, 19 sense amplifiers, 20 parity check circuits, 21 error correction circuits, and 22 a bus for connecting together the memory blocks to carry out syndrome calculation (the bus 22 being hereinafter referred to as "syndrome bus"). It should be noted that the syndrome bus 22 has in-bus parity check circuits 22a disposed thereon. In this semiconductor memory, the memory array 11 is divided into a plurality (b; b=4 in this arrangement) of memory blocks 12 for storing information bits and one memory block 13 for storing check bits. A combination of a parity check circuit 20 and an error correction circuit 21 is provided in close proximity to each memory block 12 for storing information bits. Each parity check circuit 20 effects a pre-stage processing for syndrome calculation that is, a parity check for each memory block. The parity check circuits 20 and the memory block 13 for storing check bits are connected together through the syndrome bus 22 where the post-stage processing for syndrome calculation is carried out. More specifically, the parity check results are integrated to generate a syndrome. Each error correction circuit 21 effects error correction using the thus generated syndrome. Pieces of the information thus corrected are output from output terminal Q.sub.0 to Q.sub.3 through the multiplexers 17 and the output buffers 18, respectively.
With this method, the number of relatively long wirings for connection between the memory blocks is one, i.e., only the syndrome bus 22. Since the number of wirings that connect together the memory blocks in this arrangement is m (2 m for the total number of outgoing and incoming wirings), the number of required wirings is much smaller than the aforementioned number, i.e., (k+m).
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