This invention relates to analog to digital converters in general and more particularly to an improved synchro to digital converter with inherent quantization error centering.
In order to convert synchro or resolver voltages into a digital signal it is conventional to utilize successive approximation sampling synchro to digital converters. In the case of a resolver input the sine and cosine outputs generated thereby are fed directly, through appropriate buffering amplifiers, to the converter. In the case of a synchro, the synchro outputs are first fed through the well-known Scott-T transformer to convert them into sine and cosine outputs. Generally, demodulation is carried out to convert the AC synchro or resolver signal into a DC signal having magnitude proportional to the magnitude of the respective sine or cosine and a sign which is positive if the AC voltage is in phase and negative if out of phase.
Such converters are well-known and described for example in the DDC Synchro Conversion Handbook by ILC Data Devices Corporation (1975) at pp. 27 et seq. In the device disclosed therein, DC voltages are obtained by peak detecting and sampling of the sine and cosine voltages at the peak. The two voltages are supplied as inputs to a quadrant selector which selects which of the sine and cosine are to be provided to a sine multiplier and cosine multiplier respectively. The quadrant selector also is used to control the sign of the cosine. In the sine and cosine multipliers the outputs of the quadrant selectors are multiplied by the digital angle and the results of the multiplications summed in appropriate summing means to develop a steering voltage. The steering voltage is used to control a means for example, which provides input to a counter, the outputs of which are coupled into a register which stores the digital angle. The value in the counter is changed until the digital output angle corresponds to the angle represented by the analog inputs. At this point, the multiplication and summing results in a zero error signal. The steering voltage generated is a voltage proportional to sine (.theta.-.beta.) where .theta. is the analog input angle and .beta. the digital output angle. The following trigonometric identity and nonlinear approximations are used: EQU SIN (.theta.-.beta.)=SIN (.theta.) COS .beta.-COS (.theta.) SIN .beta.
where SIN .theta., COS .theta. are analog input signals and: ##EQU1## and whose intrinsic accuracy is .+-.1.9 arc minutes.
For carrying out the necessary quadrant selection the two most significant bits are used. Although these can be generated in the same manner as the rest of the bits, some prior art systems utilize a two segment conversion in which the two most significant bits are determined by a standard decoding of sine and cosine voltage polarities. When using such circuitry it must incorporate an offset of one-half of the least significant bit (LSB) in order to center the information such that the minimum inherent quantization error of one-half least significant bit is approached. Most typically, in the prior art, this centering has been accomplished using offsets generated from the DC voltages used in the system. The technique is sensitive to errors caused by maximum tolerances of both the DC voltages and the nominal line-to-line voltage of the interrogated synchro or resolver. Thus this prior art system cannot be easily adapted to synchros or resolvers having different output voltages.
USPTO Backgrounds
USPTO Backgrounds