1. Field
Exemplary embodiments of the present invention relate to a semiconductor, and more particularly, to a method for fabricating a semiconductor having a buried bit line included in a channel area of a vertical channel transistor.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, a memory cell of a memory device such as DRAM, includes a cell transistor such as a metal oxide semiconductor field-effect transistor (MOSFET). In general, the MOSFET forms a source/drain area in a semiconductor substrate, and a planar channel is formed between the source area and the drain area. Such a MOSFET is referred to as a planar channel transistor.
As the degree of integration and performance of semiconductor devices has continuously evolved, the fabrication technology of the MOSFET is approaching its physical limit. For example, with the decrease in the size of memory cells, the size of the MOSFET is reduced. Thus, the channel length of the MOSFET is also reduced. When the channel length of the MOSFET is reduced, the characteristics of the memory device may be degraded due to various problems. For example, data maintenance characteristics may be degraded.
In order to overcome the above-described problem, a vertical channel transistor has been proposed. The vertical channel transistor has a source area and a drain area that are formed over and under a pillar. Either one of the source area or the drain area is connected to a bit line. The bit line has a structure buried in the lower part of the vertical channel transistor. Such a bit line is referred to as a buried bit line.
The buried bit line is formed by a one-side-contact (OSC) process, in which a plurality of bodies, isolated by trenches, are formed in a substrate, air opening is formed to open one sidewall of each body, a bit line is formed to fill a part of the trench, and the body and the bit line are connected through the opening.
However, with a high degree of integration, a parasitic capacitance CB between adjacent buried bit lines may increase. The parasitic capacitance between buried bit lines substantially corresponds to capacitance between a body and a buried bit line, because the buried bit line is contacted with the body. Therefore, since the distance between adjacent buried bit lines is small, the parasitic capacitance becomes very high.
Thus, when the parasitic capacitance between the buried bit lines increases, the semiconductor device may not be operated. Therefore, the parasitic capacitance needs to be minimized by increasing the distance between buried bit lines.
USPTO Backgrounds
USPTO Backgrounds