In a typical computer system, a processor interfaces with a memory device over a bus. When a processor submits a request to a memory device, the response from the memory device can be read by the processor from the bus after a delay of time, referred to as a "latency." For example, a processor may issue a read request to a cache memory system. After a period of time, the cache memory system will respond by placing the requested data on the bus. The processor can then receive the data from the bus after the latency has expired. If the processor attempts to receive the data from the bus before the latency has expired, the processor will likely receive inaccurate and invalid data.
The amount of latency can vary depending on the type of request. The amount of latency can also vary among the same type of requests. For example, a memory device may require 100-150 microseconds to respond to a read request, but only 50-100 microseconds to respond to a write request.
A processor, in advance of issuing a memory request, typically stores a latency value for each type of request. Therefore, when issuing a request, the processor can determine the period of time that it must wait until valid data in response to the request can be received from the bus.
In most prior art processors, such as the Pentium.RTM. processor from Intel Corp., the latency values are fixed within the processor. In the Pentium.RTM. processor, the latency values are in terms of a number of processor clock cycles. Therefore, a read operation of a cache memory system may be assigned a fixed latency value of 20 clock cycles for the cache to respond. The processor will then always wait 20 clock cycles after issuing a cache read instruction before it receives the response from the bus.
However, having fixed latency values based on clock cycles can cause inefficiencies when a processor is operated at less than its intended speed. For example, a processor intended to operated at 100 MHz may have a fixed latency value for a cache read operation of 20 clock cycles. If this 100 MHz processor is instead operated at only 50 MHz, each clock cycle will take twice as long than at 100 MHz. Therefore, the fixed latency value of 20 clock cycles causes the processor at 50 MHz to wait twice as long as necessary before receiving information from a cache read request. In other words, when operated at 50 MHz, valid data from a cache read request will be available to the processor after 10 clock cycles. However, because of the fixed latency value, the processor will wait for 20 cycles before receiving the data from the bus. This unnecessary delay causes the computer system to operate inefficiently.
Based on the foregoing, there is a need for a processor that allows memory access latency values to be dynamically set and modified.
USPTO Backgrounds
USPTO Backgrounds