1. Field of the Invention
This invention relates to means for testing integrated circuits in semiconductor fabrications, and more particularly, to a test connecting device including testkey and probe card for use in the testing of integrated circuits, which can prevent a low-pass filter (LPF) effect to the probe card that would otherwise result from parasite capacitances between the probe pins on the probe card, so that the frequency response of the output signal from the integrated circuit being tested can be increased to high-frequency band.
2. Description of Related Art
Integrated circuits are key elements in computers and various other intelligent electronic devices which are now indispensable tools in the information age. In the semiconductor fabrication processes, one important procedure is to test the fabricated IC chips so as to verify their reliability and performance before shipping to the customers.
FIG. 1 shows a conventional test connecting device including a testkey (which is enclosed in a dashed box indicated by the reference numeral 70) and a probe card (which is enclosed in another dashed box indicated by the reference numeral 100) for use in the testing of integrated circuits. In this particular example, the probe card 100 is of the type that comes with the HP4062 semiconductor test instrument from Hewlett Packard Corporation. This test connecting device is used to electrically connect an IC chip (not shown) being tested to the test instrument (not shown) for the test instrument to measure various electrical characteristics of the IC chip being tested.
As shown, the testkey 70 includes at least one device unit 250 and six test pads 10, 20, 30, 40, 50, 60. The device unit 250 has a V.sub.OUT port connected to the third test pad 30, a V.sub.CC1 port connected to the first test pad 10, a V.sub.CC2 port connected to the second test pad 20, and a GND port connected to the fourth test pad 40. In the case of FIG. 1, for example, the fifth and sixth test pads 50, 60 are floating. The device unit 250 is used to hold an integrated circuit (not shown) being tested.
The probe card 100 includes a row of at least six probe pins 110, 120, 130, 140, 150,160. During testing, the probe card 100 is coupled to the testkey 70 in such a manner that the first probe pin 110 comes into electrical contact with the first test pad 10 to be electrically connected to the V.sub.CC1 port of the device unit 250; the second probe pin 120 comes into electrical contact with the second test pad 20 to be electrically connected to the V.sub.CC2 port; the third probe pin 130 comes into electrical contact with the third test pad 30 to be electrically connected to the V.sub.OUT port; and the fourth probe pin 140 comes into electrical contact with the fourth test pad 40 to be electrically connected to the GND port. In the case of FIG. 1, for example, the fifth and sixth probe pins 150, 160 are not in use since they come into electrical contact with the fifth and sixth test pads 50, 60 which are floating. During the testing, a first voltage V.sub.CC1 is supplied via the first probe pin 110 and first test pad 10 to the V.sub.CC1 port of the device unit 250, and a second voltage V.sub.CC2 is supplied via the second probe pin 120 and second test pad 20 to the V.sub.CC2 port, while the GND port of the device unit 250 is connected via the fourth test pad 40 and fourth probe pin 140 to the ground. With this power connection, the device unit 250 generates an output signal which is sent out from the V.sub.OUT port thereof and then transferred via the third test pad 30 and the third probe pin 130 to a test instrument (not shown) used to measure the electrical characteristics of the device unit 250 from this output signal. The device unit 250 include ring oscillators or frequency dividers that can be used to test integrated circuits fabricated under the same environmental conditions.
The use of the foregoing HP4062 probe card 100, however, has one drawback during testing, in that the spacings between the probe pins 110, 120, 130, 140, 150, 160 are small enough to cause parasite capacitances to appear therebetween. That is, according to basic electrical principles, the parasite capacitance C between one neighboring pair of the probe pins 110, 120, 130, 140, 150, 160 can be expressed as follows: EQU C=(.epsilon..multidot.A)/d
where .epsilon. is the permitivity of air;
A is the lateral area of each probe pin; and
d is the length of spacing between the neighboring pair of probe pins. Therefore, if d is very small, the parasite capacitance C will be large enough to cause the undesired effect of virtual short circuit between the probe pins when the output signal from the V.sub.OUT port is in the high-frequency band. In the case of FIG. 1, one parasite capacitance C.sub.P23 will exist between the second probe pin 120 and the third probe pin 130, and another parasite capacitance C.sub.P34 will exist between the third probe pin 130 and the fourth probe pin 140.
When a high-frequency output signal from the V.sub.OUT port of the device unit 250 passes through third probe pin 130, the parasite capacitance C.sub.P23 between the second probe pin 120 and the third probe pin 130 and the parasite capacitance C.sub.P34 between the third probe pin 130 and the fourth probe pin 140 would become virtual short circuits between the same. These virtual short circuits would then cause the high-frequency output signal in the third probe pin 130 to be partly bypassed to the fourth probe pin 140 which is connected to the ground, thus causing the signal received by the test instrument (not shown) to have an attenuated magnitude. Moreover, since the second probe pin 120 is connected to a voltage source of V.sub.CC2, a current would flow via the virtual short circuit to the third probe pin 130, which is then mixed to the output signal in the third probe pin 130 such that the signal received by the test instrument (not shown) would contain a DC component.
Therefore, the existence of the parasite capacitances C.sub.P23 and C.sub.P34 in the probe card 100 would cause the probe card 100 to act like a low-pass filter that would reject high-frequency components in the output signal from the V.sub.OUT port. The measurements of electrical characteristics from the test instrument are thus unreliable.
To solve the foregoing problem, one solution is to lower the frequency of the output signal through the use of frequency dividers or ring oscillators with increased number of stages, so that the signal passing through the probe pin to the test instrument has a low frequency that can pass through the probe card. However, in the case of the HP4062 semiconductor test instrument, since it has a bandwidth below 6 MHz, the use of frequency dividers or ring oscillators with increased number of stages requires additional hardware components that will take up space in the integrated circuits, and may cause deviations to the actual frequency of the output signal.
USPTO Backgrounds
USPTO Backgrounds