The inventive concepts herein generally relate to semiconductor devices, and more particularly, the inventive concepts relate to substrate structures which include buried wiring, to semiconductor devices containing substrate structures including buried wiring, and to methods of fabricating the same.
As semiconductor devices are becoming highly integrated, sizes of source/drain regions and width of gate electrodes and metal wiring in semiconductor devices are being rapidly decreased. Thus, multi-layered wirings have been widely used as a wiring structure of the semiconductor device in which a number of wiring layers are sequentially stacked in a vertical direction and each of the wiring layers are electrically connected to each other by interconnections such as a contact plug.
In general, the wirings in a semiconductor device are electrically connected to underlying conductive structures such as transistors and are separated from each other by a number of insulation inter-layers. Then, the insulated upper and lower wirings are electrically connected to each other by the interconnections penetrating through the insulation interlayer.
These types of multi-layered wiring structures are becoming increasingly difficult to implement as design rules continue to decrease, particular in memory cell regions of semiconductor memory devices. For example, it may be difficult to overcome limitations of photolithography processes and ensure sufficient process margins because of resolution limits. Further, parasitic capacitances and the like can adversely impact electrical characteristics as wiring structures become increasingly integrated.
USPTO Backgrounds
USPTO Backgrounds