Integrated circuits comprise electronic devices such as transistors formed in a semiconductor substrate. The interconnection of these electronic devices to form the completed circuit is accomplished by forming metal interconnect lines in dielectric layers above the semiconductor. The metal lines are patterned to produce the required circuit interconnection. In forming the metal interconnects, a dielectric layer is first formed above the semiconductor containing the electronic devices. A first layer of patterned metal interconnect lines is then formed in the dielectric layer. The first layer of patterned metal interconnect lines is connect to the electronic devices by contacts formed in the dielectric layer. The contacts typically comprise columns of metal formed in the dielectric layer. The contacts are typically less than 1 um square. Following the formation of the first layer of patterned metal interconnect lines, additional layers of dielectric layers and patterned metal interconnect lines are formed over the first layer of patterned metal interconnect lines. The additional layers of patterned metal lines are interconnected to each other by vias that are formed in the additional dielectric layers that separate the patterned metal layers. Vias are typically on the order of less than 1 um square.
In addition to the electronic devices formed in the semiconductor additional components such as inductors are often required in integrated circuits that require filters and oscillators. Typical integrated circuit inductors comprise metal windings formed in dielectric layers above the semiconductor. The metal windings of integrated circuit inductors are formed using the same layers of patterned metal interconnect lines. Inductor performance is characterized by a quality (Q) factor with a larger Q factor being more desirable. The Q factor is a function of the operating frequency of the circuit: it increases with increasing frequency in the metal resistance limited regime, then it falls with increasing frequency in the substrate capacitance limited regime. The peak frequency depends on the geometry of the inductor and is chosen near the operating frequency of the circuit. For a given inductor geometry, since the substrate effects are typically fixed by the CMOS requirements, the only way to increase the Q factor is by reducing the metal resistance.
One method of reducing the resistance of the inductor metal lines comprises forming the inductor using multiple layers of metal lines. This method of using multiple lines is effective in obtaining the necessary Q factor for older technologies that used thicker metal lines, since each additional metal line greatly reduced the overall resistance. However with newer technologies, the metal lines are made thinner to reduce the minimum metal pitch, so even stacking all the available metal lines does not provide low enough metal resistance for high Q. Integrated circuits require operating frequencies on the order of tens of gigahertz and the present method of forming integrated circuit inductors is no longer able to achieve the required Q factor of the inductor without the addition of additional metal layers at great cost. For example, with the five metal layers required for integrated circuit operation, a 1.5 nH inductor operating at about 4 GHz requires a quality factor of about 10. Using the five available levels of metal the maximum Q factor obtainable was about 6. Adding an additional level of metal (i.e. a sixth metal level) increased the Q factor to about 13 but required the use of two additional photo-reticles which added great cost to the process. This is therefore a need for an integrated circuit inductor and method for making the same that achieves the required Q factor for a given operating frequency and inductance without the use of additional metal layers and without changing the thickness or process of the existing metal levels. The instant invention addresses this need.
USPTO Backgrounds
USPTO Backgrounds