1. Field of the Invention
The present invention relates to a testing technique for testing a signal transmission system that carries out transmission and reception of signals at high speed between LSI circuits (large-scale integrated circuits) or between devices. More particularly, the present invention relates to a test circuit that carries out a verification of a connection of nodes, and a semiconductor integrated circuit device to which the test circuit is applied.
2. Description of the Related Art
In recent years, there has been a remarkable improvement in the performance of parts that constitute computers and other information processing units. Along with this improvement, it has become necessary to carry out transmission and reception of signals at high speed between LSIs (LSI chips) and between devices consisting of a plurality of LSIs. In other words, it has become necessary to carry out a high-speed transmission of large-capacity signals between LSIs and between devices consisting of a plurality of LSIs. For example, in the solution service for network infrastructures, a high-speed transmission in the order of giga bits has become necessary, and a device called a “giga bit SERDES (Serializer and Deserializer)” has come to attract attention.
For a relatively low-speed data transmission in the order of dozens of MHz, a single end transmission system (a system for transmitting data using one signal line) like a TTL system has conventionally been used. However, the single end transmission system has drawbacks in that the system easily receives external noise, and that the transmission distance is short. Further, EMI (electromagnetic interface: electromagnetic radiation noise) occurs easily.
As the single end transmission system has the above problems, systems like the PCML (pseudo-current mode logic) system and the LVDS (low-voltage differential signaling) system that use differential signals (complementary signals) have come to be used for transmission/reception terminals for high-speed data transmission. These systems use two signal lines to transmit data using differential signals of small amplitudes. It is possible to reduce EMI to about one fifth of that of the single end transmission system, and it is also possible to cancel noise between the two differential signal lines. Therefore, it is possible to transmit data over a distance of dozens of meters. Further, as the differential signals have small amplitudes, it is possible to restrict crosstalk.
When a system including a transmitting/receiving circuit (an output circuit and an input circuit) for realizing a high-speed transmission is considered, it is also necessary to pay attention to a method of testing this system. In general, in order to confirm a connection status of signals within a printed substrate, a JTAG (joint-test action group) test (a boundary scan test) is carried out. In other words, in line with reduction in weight and sizes of electronic parts and progress of package techniques, an in-circuit test based on the JTAG has been established as a standard technique.
The boundary scan is architecture for exchanging data with a target semiconductor integrated circuit device (LSI). A mechanism for boundary scanning is built into the LSI. In other words, boundary scan cells that perform operations equivalent to that of a test robe are provided between the core and pins inside the LSI. These boundary scan cells are connected to structure a shift register. A test (a keyboard test or the like) is carried out based on the control of this shift register.
However, at present, there is no example of a JTAG test that takes into account the differential terminals of the PCML system or the LVDS system, in the system built in with the transmitting/receiving circuit. There has not yet been an established technique for inserting a BSR (boundary scan register) and a testing method. A test circuit like a BSR at a transmitter side is connected to an input stage of a transmitting circuit (output circuit), and test data is transmitted from the test circuit through the output circuit. In the mean time, a test circuit at a receiver side is connected to an output stage of a receiving circuit (input circuit), and the test data is received through the input circuit.
As explained above, in order to carry out an operation test of an LSI chip or a test of connection between a package and a board on which the package is mounted (board test), it is necessary to carry out a test based on a boundary scan. For confirming a connection between a system including a transmitting/receiving circuit and an external circuit, it is inefficient to test a single end terminal and differential terminals separately.
When it is possible to carry out a JTAG test for differential terminals in a similar manner to that for a single end terminal, it becomes possible to perform the test in one pass. This can reduce test time and improve the test efficiency. In this case, it is necessary that test data is output from the output circuit to the transmitter terminal. On the other hand, it is necessary that the input circuit receives the test data that is input from the receiving terminal.
However, when a signal processing circuit for carrying out a high-speed serial-to-parallel conversion, a transmitting circuit (output circuit) and a receiving circuit (input circuit) are connected together, the insertion of a test circuit like a BSR (boundary scan register) into between the transmitting circuit or the input circuit (receiving circuit) and the signal processing circuit lowers the transmission performance. Further, in the case of a differential output and a differential input, it is not possible to install a conventional BSR on the terminal.
USPTO Backgrounds
USPTO Backgrounds