1. Field of Invention
This invention relates to testing of integrated circuits and in particular to testing embedded DRAM""s
2. Description of Related Art
There has long been a desire to integrate a computer onto a single chip, and the progress in device geometries is making it possible to consider a processor and memory integrated together on the same semiconductor chip. Putting together these two functions on a single chip puts a demand on testing and how to insure that each function is working correctly. Providing a built in self test, otherwise known as a BIST, is a way of allowing an embedded memory function to be tested separate from the processor function and to provide an assurance the memory will operate properly.
In U.S. Pat. No. 5,825,785 (Barry et al.) a built in self test capability is described for embedded macros using a state machine based controller. A built in self test circuit receives a scan vector that describes the parameters of the embedded macro that is to be tested. In U.S. Pat. No. 5,764,655 (Kirihata et al.) an integrated circuit chip is described that contains a built in self test and a nonvolatile RAM and includes an RF circuit for transmitting test results to a detector external to the chip. The present invention is described in C. Huang et al., xe2x80x9cA Programmable BIST CORE for Embedded DRAMxe2x80x9d, IEEE Design and Test of Computers, January-March 1999, pp 2-13. In J. Dreibelbis, xe2x80x9cProcessor-Based Built-In Self-Test for Embedded DRAMxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 33, No. 11, November 1998, pp 1731-1740, a built-in self-test engine and test methodology was developed for testing a family of high bandwidth and high density DRAM macros. The processor based test engine has two separate instruction storage memories and combines with address, data and clock generators to provide high performance ac testing of a DRAM. In S. Tanoi et al., xe2x80x9cOn-Wafer BIST of a 200-Gb/s Failed-Bit Search for 1-Gb DRAMxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 32, No. 11, November 1997, pp 1735-1742, an on-wafer built-in self-test (BIST) test technique is discussed. The technique was developed to implement a 200-Gb/s failed-bit search for a 1-Gb DRAM. The BIST circuits include a very long word bus and test management circuit to probe DRAM arrays and compress test results. Read/compare circuits are embedded in sense amplifiers to identify failed bit column address.
In P. Camurati et al., xe2x80x9cIndustrial BIST of Embedded RAMsxe2x80x9d, IEEE Design and Test of Computers, Fall 1995, pp 86-95, a built-in self-test scheme is discussed for deeply embedded memories. A test pattern generation algorithm is implemented in hardware and extending to word based memories. In R. Treuler et al., xe2x80x9cBuilt-In Self-Diagnosis for Repairable Embedded RAMsxe2x80x9d, IEEE Design and Test, June 1993, pp 24-32, a method of built-in self-diagnosis (BISD) is presented. The test circuit contains a small reduced instruction set processor which executes diagnostic algorithms stored in a ROM. The algorithms employ hybrid serial/parallel and modular operations depending whether external or self repair is required. In B. Nadeau-Dostie et al., xe2x80x9cSerial Interfacing for Embedded-Memory Testingxe2x80x9d, IEEE Design and Test of Computers, April 1990, pp 52-63, a serial interfacing scheme is presented where several embedded memories share the same built in self test circuit. The approach requires only two serial pins to access the data path. A test pattern is applied every clock cycle as a result of the memory shifting the test data. In R. Dekker et al., xe2x80x9cA Realistic Self-Test Machine for Static Random Access Memoriesxe2x80x9d, 1988 International Test Conference, Paper 20.2, pp 353-361, a specification and implementation is described for a self test machine for static random access memories. There were several improvements over then existing self test machines, including improved test algorithms, machine structure independent of address and data scrambling, data backgrounds generated on chip, include a data retention test, suitable for both embedded and stand alone SRAM""s, and small silicon overhead due to the symmetric structure.
Testing embedded memories, such as DRAM""s, is more difficult than testing commodity memory chips because of the accessibility of the embedded memory. The surrounding logic must be isolated and a design for testability can result in extra hardware overhead. In addition, there can be performance penalties along with noise and parasitic effects. An external memory tester is expensive, and considering the increased speed and bandwidth associated with embedded memories, it is difficult to produce an adequate test capability. Trying to maintain an adequate test capability in an environment of engineering change only adds to the difficulties of an external tester.
Providing a built in self test capability allows a much simpler and less costly tester to be used in testing a chip containing an embedded memory. With built in self test the embedded memory can be more easily isolated and can be tested at operating speeds. Testing at higher levels of assembly to can provide diagnostics in situ. By providing a capability to introduce different test sequences, a built in self test can test for critical timing during wafer test, pre-burn-in test, burn-in test and final test. Providing the user the capability to program different test algorithms and optimize the tests for a specific embedded memory adds important flexibility to built in self test.
In this invention is described a built in self test (BIST) for embedded DRAM""s. Although the concentration is on an embedded DRAM, the method and techniques disclosed herein are applicable to other types of embedded memories, such as SRAM""s and Flash memories, and can also be used on commodity memories as well. The BIST is constructed of a controller circuit and a sequencer circuit. The controller circuit provides test sequences to the sequencer circuit that generates test data and timing sequences to be applied to the embedded DRAM. A comparator located in the sequencer is used to compare the output data to the input data of the DRAM and produces a go/no go signal which is connected to an external tester.
The controller circuit includes a BIST controller which is a finite state machine, multiple scan chains used to provide test commands, diagnostic information, and a BIST scan path for testing the BIST logic except the finite state machine. The BIST controller controls the scan chains, shifting in test patterns and commands, and shifting out results. The finite state machine controls the BIST scan operation which is done first to insure that the built in self test circuitry is operating properly.
The sequencer circuit accepts commands and diagnostic information from the controller circuit and turns the commands into timing sequences and data to be connected to the embedded DRAM. The comparator contained within the sequencer circuit compares data outputted from the DRAM to the original input data and creates an error signal when a discrepancy is found. Timing sequences are created with the use of counters and a timing generator contained within the sequencer circuit. DRAM interface buffers contained within the sequencer circuit provide for address data, row and column access signals, write enable and data input and data output to be connected to the embedded DRAM. The sequencer output signals to the embedded DRAM are glitch free resulting from the state transition of the finite state machine being on the rising edge of the BIST clock and the control signals for the DRAM being on the falling transition.
The BIST controller finite state machine is configured to control the operations of the BIST by selecting a test mode, decoding the commands of the test mode, scanning in test patterns, executing the tests and pausing for observations or a retention test. The length of the pause for retention test is a user determined length of time, and the finite state machine can be reset to an initial state by the application of four consecutive logical zeros from any operational state. The BIST supports several test modes including a scan test, a memory test, a burn-in test and a timing fault test. The scan test is used to test the BIST except the controller finite state machine to insure correct functionality before testing of the embedded DRAM takes place. The BIST functionally tests the DRAM using march algorithms which exercises the DRAM in page and non-page modes. During march testing of the DRAM, read-write sequences are moved from cell to cell across the rows and columns of the embedded DRAM.
The BIST also tests refresh and memory retention. The burn-in test exercises the entire embedded memory and can use a march algorithm supported in the memory test mode. Timing fault testing is accomplished by running the BIST clock at an appropriate speed and determining whether various memory operations were performed within the clock period. These timed memory operations include setup time, hold time, and data arrival time for various controls and data signals.
The sequencer is designed for flexibility and can be used with a wide range of embedded memories of different dimensions and timing requirements. The sequence controller finite state machine generates timing sequences for single read/write commands as well as for page mode read/write commands for march elements defined in the controller. The page mode access cycle comprises a row access followed by a sequence of column access. The DRAM under test first latches the row address and then latches, one by one, the column address for the whole page. The sequencer also tests a DRAM refresh mechanism for a variety of refresh states, including self refresh, hidden refresh and RAS only refresh state. The sequencer outputs are implemented such as to be glitch free when the BIST is in use and in a high state when the BIST is not in use. The state transitions are timed to be on the rising edge of the BIST clock and the control timing signals for the DRAM are on the falling edge of the clock producing glitch free sequencer outputs. If test time is important, testing multiple memory banks and multiple words simultaneously with multiple built in self test sequences can be used to reduce test time.
USPTO Backgrounds
USPTO Backgrounds