1. Field of the Invention
The present invention relates in general to electrostatic discharge (ESD) protection circuits. In particular, the present invention relates to ESD protection circuits for sub-micron complementary metal-oxide semiconductor integrated circuits (CMOS IC's). More particularly, the present invention relates to ESD protection circuits for sub-micron CMOS IC's capable of triggering SCRs (SCR) thereof to activate the protection by lowering the trigger voltage thereof.
2. Description of Related Art
ESD, electrostatic discharge, is a common phenomenon found that occurs during handling of semiconductor IC devices. Electrostatic charges may accumulate for various reasons and cause damage to an IC device. Damage typically can occur during a testing phase of its fabrication, during assembly of the IC to a circuit board, as well as during the use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic equipment can hamper its designed functions partially, sometimes completely. Research in the ESD protection for semiconductor IC's is, therefore, an important issue.
Those skilled in the IC art know that the cause of ESD is explained by four different models. The first such model is the human-body model. It is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. This Military Standard models the electrostatic stress produced on an IC device when a human carrying electrostatic charges touches the lead pins of the IC device. The second is a machine model. This model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying electrostatic charges contacts the lead pins of the IC device. The third model is the charged device model. This model describes the ESD current pulse generated when an IC device already carrying electro-static charges is grounded in the process of its handling. The fourth model is the field induced model, which describes the electric potential field induced in an IC device when it is placed in an electrostatic field. The electric potential field may produce ESD in the IC device when the device is later grounded during handling.
As the IC fabrication arts advance, there is more and more device miniaturization. Semiconductor devices having reduced-size now being fabricated employ photomasking procedures having patterns in resolutions in the range of less than 1-millionth of a meter, or, 1 micron. In this sub-micron size range, ESD protection circuits in semiconductor IC devices must be reduced in size as well. The design of the ESD circuits must be modified to accommodate the overall miniaturization. Lightly-doped drains (LDD), as well as the utilization of metal-silicide diffusion procedure in the fabrication, require the use of lateral SCRs (SCR) as the main components in the ESD circuits for facilitating the protection, while allowing the sub-micron semiconductor devices to function acceptably.
One constraining design factor of the lateral SCR's used in ESD protection circuits for sub-micron semiconductor devices is, however, inherent. Trigger voltage for lateral SCR's in sub-micron CMOS devices is in the range of 30 to 50 volts. The typical thickness of gate oxide layers in CMOS fabrication processes employing a resolution of 0.6-0.8 microns is about 150-200 angstrom. Considering a dielectric breakdown strength of 10 MV/cm for typical SiO.sub.2 material, the gate oxide layers in these sub-micron CMOS devices would be destroyed by a voltage of 15-20 volts. Therefore, lateral SCR's with a trigger voltage in the range of 30-50 volts must be fitted with other protection components so that they can provide protection for gate oxide layers in the sub-micron CMOS IC devices.
Efforts have been made to lower the trigger voltage of the lateral SCR's in the ESD protection circuits for the sub-micron CMOS device. The trigger voltage is reduced to below the dielectric breakdown voltage of the gate oxide layers of the CMOS device, so that the ESD protection circuits can provide the protection for the CMOS device before being damaged themselves. Several ways to lower the trigger voltage of lateral SCR have been proposed.
For example, A. Chatterjee and T. Polgreen proposed a low-voltage trigger SCR (LVTSCR) configuration in "A low-voltage trigger SCR for on-chip ESD protection at outputs and input pads," Proc. 1990 Symposium on VLSI Technology, pp 75-86. In their disclosure, Chatterjee and Polgreen employed a short-channel NMOS transistor coupled to an SCR to form the low-voltage trigger SCR, hereafter referred to as LVTSCR, having a trigger voltage that is about equal to the breakdown voltage (BV.sub.dss) of the short-channel NMOS transistor.
However, polarity characteristics arise in the stresses produced by these ESD discharges toward each of the two voltage planes VDD and VSS in the semiconductor power system caused by electrostatic charge build-up. There are four ESD stress patterns that can occur in an input or output buffering pad of the semiconductor IC device. They are, namely, the discharges of positive and negative currents at the input and output respectively. Each of these ESD patterns causes their respective pattern of damage to the NMOS and/or PMOS components of the input stage and output driver of the semiconductor device.
Conventional semiconductor IC devices employing these Low Voltage Trigger Silicon Controlled Rectifier (LVTSCR) components for ESD protection have their LVTSCR's arranged only in circuit locations between the input/output buffering pads and the VSS terminal of the entire IC device. No ESD protection was provided between the I/O buffering pads and the VDD terminal of an IC. Thus, when the VSS terminal of a CMOS semiconductor IC device is left floating, while an ESD stress arises between one of the I/O buffering pads and the device VDD terminal, the typical ESD current would flow in a path starting from the particular buffering pad, passing first through the LVTSCR, then to the VSS power terminal of the CMOS IC device, then penetrates through the ESD protection circuitry between the VDD and VSS terminals of the device, and finally discharges out of the IC device via the VDD lead pin.
As a result of the influences of parasitic resistance and capacitance that are inherent in the VSS and VDD lines of the CMOS IC device, the above-described ESD current flow path would induce unpredictable damages to the internal circuits of the IC device, as were indicated by C. Duvvury, R. N. Rountree and O. Adams in "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. on Electron Devices, Vol. 35, No. 12, pp 2133-2139, December 1988.
An effective and complete ESD protection device should, therefore, include direct protection measures between the I/O buffering pads of the IC device and both the VDD and VSS planes of the entire IC device.
USPTO Backgrounds
USPTO Backgrounds