Conventional semiconductor package frames (“lead frames”) have a plurality of openings for wires to pass through and an area for mounting the die (or chip) which is know as a paddle. FIG. 1 shows a conventional semiconductor frame 100. Semiconductor frame 100 includes plurality of holes 102 and paddle area 104. Plurality of holes 102 provide spacing for wires to pass through semiconductor frame 100. Paddle area 104 provides a surface for mounting of the die or chip. The wires that pass through plurality of holes 102 connect the die to pins which are attached during subsequent stages of the semiconductor packaging process and facilitate the semiconductor package to be connected and mounted to a printed circuit board.
Semiconductor frames are often made initially from a single piece of material in large quantity and then individually cut into strips (“lead frame strips”) or rows and then cut into individual semiconductor frames. During manufacturing, there are often controllable and uncontrollable variances which may result in defective elements or components in semiconductor packages. In order eliminate and track down these variances, there is a need to identify and track the conditions under which a semiconductor package was manufactured. In the device 100, the strip form is often marked uniquely identifying the parts. Individual frame are not marked. Therefore, once the strip is separated into the component frames, the identifiers are no longer associated with the individual frames.
FIG. 2 shows another conventional semiconductor frame design 200. Semiconductor frame 200 includes plurality of openings 202, paddle area 204, and identification area 206. Similar to design 100, plurality of openings 202 allows for wires to pass through semiconductor frame 200. The wires that pass through plurality of openings 202 to connect the die to pins which are attached during subsequent steps of the semiconductor packaging process and allow the semiconductor package to be connected and/or mounted to a printed circuit board. Paddle area 204 provides a surface for mounting the die. Paddle area 204 is substantially smaller than paddle area 104 to make room for identification areas 206. Identification areas 206 provide an area for printing tracking information such as letters or numbers to identify the unique semiconductor package. This allows tracking of a particular semiconductor frame, not just the strip from which it originated. Design 200 is problematic because the reduced paddle size of 204 means that dies must be redesigned to fit within the smaller non-standard area and also associated equipment may need to be reconfigured or retooled.
USPTO Backgrounds
USPTO Backgrounds