1. Field of the Invention
The present invention relates to a technique for designing a semiconductor device comprising at least one semiconductor element having at least two electrodes, particularly to a simulation model for designing a semiconductor device in which reproducibility of a behavior in a transition state of a carrier in each electrode and between the electrodes during a high-speed operation of a semiconductor element, an apparatus for simulating the designing of a semiconductor device, a method of simulating the designing of a semiconductor device, a computer-readable recording medium in which a program for simulating the designing of a semiconductor device, a semiconductor device designed using them, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
When a semiconductor device is manufactured, in general, an operation of a designed semiconductor device is usually predicted beforehand by simulation prior to actual manufacturing of the semiconductor device. In general, the operation of the semiconductor device is reproduced by the simulation to thereby confirm and inspect whether or not an actually manufactured semiconductor device exerts its performance as desired.
Here, a case where the high-speed operation of a metal-oxide-semiconductor field-effect transistor (MOSFET) is reproduced by simulation will be described with respect to a semiconductor device comprising, for example, a MOSFET which is one type of an semiconductor element. In this case, a simulation model capable of analyzing and reproducing a behavior of a carrier in a source/drain and channel of the MOSFET with high precision is required in order to raise the precision of the simulation. A passage time (passage delay) of the carrier which runs to the drain from the source via the channel needs to be considered in order to obtain the simulation model. As the simulation model for designing the semiconductor device in consideration of the passage delay of the carrier passed through the channel, a large number of simulation models, so-called non-quasi-static models (NQS models), have heretofore been proposed. The NQS simulation model has been described, for example, in Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 2132-2136 Part 1, No. 4B, April 2003.
For example, as a first non-quasi-static model, there is a model in which an actual transistor (MOSFET) is virtually divided into a plurality of small transistors, and resistance is held between the transistors to thereby represent delay of carrier running. As a second non-quasi-static model, there is a model in which resistances having different values are virtually arranged between source and gate and between gate and drain to thereby represent the delay in carrier running. Furthermore, as a third non-quasi-static model, there is a model in which a relaxing time is introduced in forming a charge in the channel, and the time is solved using a virtual equivalent apparatus. As a typical example of the third non-quasi-static model, there is a model called the Berkeley short-channel IGFET model (BSIM) which has been most frequently used in the world.
As described above, various non-quasi-static models have been proposed in order to predict or reproduce the high-speed operation of the MOSFET by the simulation with a high precision. However, a satisfactory result is not practically obtained in most of the models. For example, in the first non-quasi-static model, since the number of the transistors to be considered increases, a calculation time becomes enormous. Moreover, since a channel length changes with the number of divided channels in the first non-quasi-static model, it is not clear whether or not all the divided and integrated transistors have the same characteristics as those of the whole transistor before divided. In the second non-quasi-static model, estimation of each resistance value is not clear. Further in the third non-quasi-static model, it is difficult to converge the device. Moreover, in the third non-quasi-static model, a charge loss in a channel region generated by an NQS effect in consideration of the delay in the carrier running in the channel region cannot be described.
Moreover, this problem does not necessarily occur only in the MOSFET. The above-described problem could be caused generally in the semiconductor element having at least two electrodes concerned with transmission/reception of the carrier, for example, in a bipolar transistor or the like.
As described above, in the conventional non-quasi-static simulation model, it has heretofore been difficult to predict or reproduce the behavior of the carrier in the semiconductor device including the semiconductor element within a practically allowable time and with a high precision regardless of a stationary or transient state. It is substantially impossible to especially predict or reproduce the behavior of the carrier in the semiconductor element or the semiconductor device which operates at a high speed using the simulation model with the high precision. Moreover, needless to say, it is clearly difficult to simulate the operations of the semiconductor element and the semiconductor device within the practically allowable time and with high precision by a simulation apparatus, simulation method, or simulation program using the above-described simulation model. Additionally, there is a possibility that performances of the semiconductor element and the semiconductor device designed or manufactured using the simulation model, simulation apparatus, simulation method, and simulation program are largely inferior to desired performances.
USPTO Backgrounds
USPTO Backgrounds