1. Field of the Invention
The present invention relates to signal processing and more particularly relates to sample rate conversion systems having an independent internal oscillator to generate an operating clock signal.
2. Description of the Related Art
Digital electronics occupy a significant portion of the electronics market. Users or manufacturers often desire to combine multiple discrete digital electronic systems into a consolidated system. This modularity provides desirable system flexibility and expandability.
When combining discrete systems into a consolidated system, various compatibility issues arise such as disparate data sampling frequencies. For example, a user may desire to use a digital versatile disk (DVD) audio playback system to listen to audio sourced from a compact disk (CD) player. DVD audio playback systems generally have an input signal sample frequency of 96 kHz, and CD players generally have an output signal sample frequency of 44.1 kHz. Directly providing a 44.1 kHz sampled audio input signal to a DVD audio playback system that expects a 96 kHz sampled audio input signal would result in significant distortion of the audio signal. Sample rate conversion (SRC) circuits solve the sampling frequency incompatibility problem by converting the sampling frequency of data from a first sampling frequency used by a data source into a second sampling frequency used by a data sink. Thus, the SRC circuit facilitates interconnectivity and interoperability of multiple discrete signal processing systems.
FIG. 1 depicts a digital signal processing system 100 that includes an SRC circuit 102 to convert input data from data source 104 sampled at the sampling frequency of the input frame clock signal, fsi, into output data for data sink 106 sampled at the sampling frequency of the output frame clock signal, fso. The input and output frame clocks can be internal or external to the respective data source 104 and data sink 106. Clock source 108 depicts an external output frame clock signal source that provides the output frame clock signal to SRC circuit 102 and data sink 106. The SRC circuit 102 attempts to preserve the content of the input data while adding a minimal amount of noise. Many SRC circuits designs exist, and SRC circuits are often implemented as independently packaged integrated circuits (IC).
Data source 104 represents any data source, such as a CD player, that produces input data sampled at frequency fsi. Data sink 106 represents the intended recipient of the input data. Data sink 106 processes output data from SRC circuit 102. Two clocks separately generate the input frame clock signal and the output frame clock signal. The SRC circuit 102 includes two inputs to respectively receive an input frame clock signal having a frequency of fsi and an output frame clock signal having a frequency of fso. The SRC circuit 102 uses the input and output frame clocks to convert the sampling frequency of the input data to a sampling frequency compatible with the data sink 106.
The SRC circuit 102 is generally designed to provide compatibility with different input frame clocks and output frame clocks. Thus, SRC circuit 102 includes logic that automatically processes the input data at the correct sampling frequencies. For example, some embodiments of SRC circuit 102 automatically track arbitrary irrational and rational ratios of the output frame clock signal fso to the input frame clock signal fsi (i.e. fso/fsi). The ratio may be static or dynamic and may not be known exactly in advance of receiving the clock signals. In other embodiments, SRC circuit 102 directly uses the input frame clock and output frame clock to convert the input data into output data using the correct sampling frequencies. Phase lock loops can be used to lock on to the input and output frame clock signals to convert the data from the correct input data sampling frequency to the correct output data sampling frequency. If the input data frame clock frequency is known, at a minimum, a clock signal synchronized to a desired output data frame rate is provided to SRC circuit 102 to convey information about the output sample frequency fso.
The conversion logic of SRC circuit 102 can be implemented in any of a number of ways. In one embodiment, the SRC circuit 102 uses a digital to analog converter to convert the input data into an analog signal. The SRC circuit 102 also includes sampling circuitry to sample the analog signal at a sampling frequency of fso and convert the analog input data into digital data using a digital to analog converter. Some embodiments of SRC circuit 102 are configured in a “slave-slave” configuration. A “slave-slave” configuration refers to a configuration when the input data port 112 and output data port 110 are respective slaves to the input frame clock and the output frame clock. When an output data port 110 providing the output data is configured as a slave, the output frame clock provides the synchronized clock since the output frame clock is already provided as an input to SRC 102.
In addition to relying upon the input and output frame clocks, SRC circuit 102 uses an operating clock 114 to provide an operating clock signal to operate the internal digital logic hardware of SRC circuit 102. Operating clock 114 must have a high enough frequency to allow the SRC circuit 102 to compute the next demanded output data in time to begin processing the next input data. The operating clock signal may be synchronous or asynchronous to the input frame clock and the output frame clock signals and is usually higher in frequency than both frame clocks. Operating clock 114 is shown in dashed lines because it may be supplied internally to SRC circuit 102 or supplied from an external source.
Conventional SRC circuits, such as SRC circuit 102, use a high precision operating clock 114 to provide precise clock pulses. A high precision clock, by definition, generates a clock signal with a small amount of jitter. “Clock jitter” refers to any variation of a clock period from the clock's nominal period. For audio applications, a “small amount of clock jitter” can be defined as approximately less than 0.2 nanosecond root mean square (RMS) variation of a clock signal's period.
FIGS. 2, 3, and 4 depict various embodiments of operating clock 114. SRC circuits 200, 300, and 400 represent embodiments of SRC circuit 102 and differ only in the embodiment of operating clock 114. SRC circuit 200 includes an external pin 202 to receive a high precision operating clock signal from clock generator 204. Clock generator 204 can be any clock signal source, such as a crystal oscillator based circuit or a high quality phase-locked-loop, that generates a high precision operating clock signal. Generally SRC circuit 200 is disposed on a larger system board and clock generator 204 is also located on the same system board.
SRC circuit 300 generates a high precision operating clock signal using internal and external circuitry. SRC circuit 300 includes two external pins 302 and 304 to receive a resonating signal from an external resonator crystal circuit. SRC circuit 300 includes an internal amplifier 308 to amplify the resonating signal into an operating clock signal.
SRC circuit 400 generates a high precision operating clock signal using internal circuitry. SRC circuit 400 includes a high precision analog phase locked loop (PLL) circuit (PLL) 402 that provides the operating clock signal to the SRC core logic 404. In accordance with a select signal (not shown), multiplexer (MUX) 406 alternately selects the input frame clock signal and the output frame clock signal for processing PLL 402. PLL 402 generates a high precision multiple of the input and output frame clock signals. Alternatively, SRC circuit 400 could include two analog PLLs to respectively derive multiples of the input frame clock signal and output frame clock signal. Additionally, SRC circuit 400 may require an optional extra pin 408 (shown in dotted lines) to connect to an optional large, external filter 410 since the relatively low frequencies of the input and output frame clocks usually imply a low PLL bandwidth and, thus, large filter value components.
Because of the straightforward function of an SRC circuit, customers expect SRC circuit 102 (including embodiments SRC circuits 200, 300, and 400) to possess a low pin count (i.e. has few external pins). Customers also expect SRC circuit 102 to be sold at a low cost including the cost of necessary external components such as components used to generate an operating clock signal.
Generating the high precision operating clock signal for SRC circuit 102 including the SRC circuit 200, 300, and 400 embodiments adds a nontrivial amount of cost to the SRC circuits. To provide SRC circuit 200 with a high precision operating clock, SRC circuit 200 requires an extra pin 202, an external clock generator 204, and off-chip signal routing. To provide SRC circuit 300 with a high precision operating clock, SRC circuit 300 requires two extra pins 302 and 304, an external crystal resonator circuit 306, an amplifier 308, and off-chip signal routing. To provide SRC circuit 400 with a high precision operation clock, SRC circuit 400 requires an internal, precision PLL and MUX that occupy a significant amount of relatively expensive die area. Additionally, SRC circuit 400 often requires an external pin, an external filter circuit, and off-chip signal routing. Thus, the conventional approach of providing a high precision operating clock for SRC circuits adds a nontrivial amount of cost to the SRC circuits.
USPTO Backgrounds
USPTO Backgrounds