A power MOSFET or power FET is designed to handle significantly higher power levels than other semiconductor devices. However, such applications, for example, motor driver applications and DC/DC regulators, also demand a control scheme that provides information about the current flowing through the load.
Existing solutions for lossless current sensing of power FETs use either a single sense FET, or a direct measurement of the drain-source voltage VDS of the power FET. However, a direct measurement of the drain-source voltage VDS may not be accurate, particularly when the “on” channel resistance RDSON of the power FET is low. Further, using a single sense FET permits measuring current flow in only one direction (sink or source).
For example, FIG. 1 shows a circuit 55 having a power FET 60 with its drain coupled to the load, its source coupled to ground, and its gate coupled to a gate voltage Vgate. A sense FET 61 has its drain coupled to the inverting input of amplifier 70 and to the source of sense FET 62, its source connected to ground, and its gate coupled to the gate voltage Vgate. The load is also connected to the non-inverting input of amplifier 70, thus creating a feedback loop that maintains a stable current through sense FET 62. The gate of sense FET 62 is coupled to the output of amplifier 70, which drives the sense FET 62 to deliver a one-way current Isns through the channel of the sense FET 62 when current is flowing out of the load.
Therefore, it would be desirable to provide a way of detecting both amplitude and direction of the load current, as well as providing a voltage representation of the load current for processing.
USPTO Backgrounds
USPTO Backgrounds