Recent innovations in three-dimensional (3D) chip, die and wafer integration (hereinafter, collectively, stacked structures) have enabled a greater miniaturization of devices as well as technological advancements in increased speed and density, with reduced power consumption and cost. However, further cost-effective miniaturization is presently hindered by bonding related issues affecting the manufacturability and mass production of 3D integrated circuits (IC) stacked structures. Current bonding processes, e.g., copper-to-copper (Cu—Cu) bonding, oxide bonding, soldering bonding, or other polymer bonding processes, fail to adequately address the industry's increasing requirements for precision alignment, bonding strength, electrical interconnection, and manufacturability. For instance, wafer bonding involving complementary metal-oxide-semiconductor (CMOS) wafers would require the bonding temperature to be limited to about 400° C. Additionally, a high force needs to be applied to the wafers in order to achieve a reasonable bonding strength. However, the application of high bonding force for wafer-to-wafer level bonding may result in increased wafer breakages.
A need, therefore, exists for a bonding methodology enabling the fabrication of 3D IC stacked structures with improved alignment, bonding strength, electrical interconnection, and manufacturability at lower bonding forces and lower temperatures.
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