1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including highly scaled transistor elements comprising highly capacitive gate structures including a high-k gate dielectric of increased permittivity compared to gate dielectrics, such as silicon dioxide and silicon nitride.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine the performance of integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon, due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage, without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, silicon dioxide is preferably used as a gate insulation layer in field effect transistors that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although generally high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for performance driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3) having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since, typically, a low threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, is desired to obtain the high drive currents, commonly the controllability of the respective channel requires pronounced lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region to “reinforce” the resulting PN junction dopant gradient after the formation of respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing an appropriate halo implantation region, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll off, and also reducing significant variations of transistor performance with a variation in gate length. Since the threshold voltage of the transistors is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
After forming sophisticated gate structures including a high-k dielectric and a metal-based gate material, however, high temperature treatments may be required, which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, as will be explained in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 having formed thereon a silicon layer 102, in which a first active region 102A and a second active region 102B are formed. The active regions 102A, 102B are to be understood as appropriately doped semiconductor regions for forming therein and thereon respective transistor elements having drain and source regions and a channel region. In the example shown in FIG. 1a, the first active region 102A may represent a lightly P-doped region so as to form therein one or more N-channel transistor elements. Similarly, the second active region 102B may represent a lightly N-doped region so as to receive one or more P-channel transistors. The first and second active regions 102A, 102B are laterally isolated from each other by a trench isolation structure 103, which may be comprised of an insulating material including a significant portion of silicon dioxide material. Furthermore, in the manufacturing stage shown, the device 100 further comprises a gate layer stack configured to provide enhanced capacitive coupling and conductivity, as previously explained. That is, the gate layer stack 110 comprises a high-k dielectric insulating material 111, which may be provided in the form of a hafnium-based or zirconium-based dielectric material, as previously explained, in order to obtain a significantly increased capacitance for a similar layer thickness compared to conventionally used silicon dioxide gate dielectrics. For example, in this manufacturing stage, the high-k dielectric layer 111 may be provided with a thickness of approximately 15-25 Å for highly sophisticated applications.
The layer stack 110 further comprises a metal-containing conductive material 112, such as a titanium-based material and the like, which may exhibit a significantly higher electrical conductivity compared to conventionally used polycrystalline silicon, also referred to as polysilicon. The metal-containing material layer 112 comprises a first portion 112A that is formed above the first active region 102A and has a first work function adjusted such that the Fermi level is appropriately located with respect to the band gap of the doped silicon material in the first active region 102A. Hence, for an N-channel transistor, the first portion 112A may have a Fermi level in the vicinity of the upper band gap edge, which may, for instance, be accomplished by providing the first portion 112A in the form of an alloy of a metal substantially comprising a second portion 112B, the characteristics of which are selected such that the work function of the second portion 112B is appropriate for the P-channel transistors to be formed in the second active region 102B. By appropriately selecting the respective work functions, the threshold voltage of the transistors to be formed in the first and second active regions 102A, 102B may be maintained at a low level, thereby providing the potential for enhancing the channel control on the basis of halo implantation processes, as previously explained.
Furthermore, the gate layer stack 110 further comprises a polysilicon layer 113 which may have any appropriate thickness in accordance with device requirements.
The semiconductor device 100 may be formed according to the following conventional process strategies. First, the trench isolation structures 103 may be formed on the basis of well-established techniques, including lithography, etch and deposition processes for forming a trench in the semiconductor layer 102 and subsequently filling the trench with a silicon dioxide-based material. Thereafter, appropriate implantation processes may be performed to define the first and second active regions 102A, 102B configured to enable the formation of N-channel transistors and P-channel transistors, respectively. Next, the high-k dielectric material may be formed on the basis of appropriate deposition techniques, wherein a layer thickness may be maintained within the above-specified range for sophisticated devices. Thereafter, the metal-containing layer 112 may be deposited, for instance, on the basis of chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like. For example, in a first step, the layer 112 may be deposited as the first portion comprised of the material 112A, which may represent any appropriate metal alloy of a desired refractory metal and the like. Thereafter, the layer may be patterned to form the first portion 112A. Subsequently, the second portion 112B may be deposited and may be planarized, if required, to reduce the surface non-uniformity. Thereafter, the polysilicon layer 113 may be deposited as a final layer of the gate layer stack 110 in order to provide a highly stable surface of the gate layer stack 110 and also provide a high degree of compatibility with well-established gate patterning strategies, which are performed on the basis of polysilicon materials.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage wherein one or more gate electrode structures 120A, 120B, 120C are formed above the first and second active regions 102A, 102B, wherein at least one gate electrode structure 120B is provided as a common conductive line connecting a transistor element still to be formed in the first active region 102A with a transistor element still to be formed in the second active region 102B so that the gate electrode structure 120B extends across the trench isolation structure 103.
The gate electrode structures 120A, 120B, 120C may be formed on the basis of well-established lithography and sophisticated etch techniques, wherein appropriate etch chemistries may be used to efficiently etch through the polysilicon material of the layer 113 and the metal-containing portions 112A, 112B, as well as the high-k dielectric layer 111. Thereafter, any further processes may be performed to complete the respective transistor elements, such as forming drain and source regions on the basis of ion implantation and the like.
FIG. 1c schematically illustrates the device 100 during a high temperature treatment 131, which may be required during the process of forming respective transistor elements 130A, 130B, 130C and 130D. During the high temperature treatment 131, a significant oxygen diffusion may take place within the high-k dielectric material 111, wherein the oxygen diffusion may be fed by oxygen contained in the trench isolation structure 103 and in the metal-containing materials 112A, 112B, in particular in the alloy of the portion 112A. Since, for instance, hafnium- and zirconium-based oxides grow very fast due to the high affinity to oxygen diffusion even at moderately high temperatures, such as 700-800° C., a significant modification of the characteristics of the high-k dielectric material may be observed, for instance an increased layer thickness and thus a reduced dielectric constant, which may even further be pronounced at moderately high temperatures of approximately 950-1300° C., as may typically be used during activation treatments and the like.
In addition to a significant modification of the high-k dielectric material in the layer 111, also the work function of the metal-containing layer 112, in particular the alloy of the first portion 112A, may be shifted towards the center of the band gap thereby modifying the threshold voltage of the respective transistors 130A, 130B. Due to the high oxygen affinity of the high-k dielectric material of the layer 112, the trench isolation structure 103 may act as a source of oxygen, as indicated by arrows 132, which may then be redistributed via the high-k dielectric material into the alloy of the portion 112A, thereby shifting the work function and also providing additional oxygen at a corner 103A of the trench isolation structure 103. Consequently, additional insulating material may be grown within the active region 102A, that is, in the channel region of the transistor 130B at the corner 103A, thereby reducing the width thereof and therefore decreasing the drive current capability of this device, in particular if narrow channel transistors are considered. Thus, an increase of threshold voltage due to the metal work function shift, in combination with a loss of drive current owing to the increased thickness of the insulating material at the corner 103A, may render the conventional approach for integrating a high-k metal gate prior to transistor formation as described with reference to FIGS. 1a-1c less than desirable. However, a strategy in which the high-k dielectric material may be removed from the top of the trench isolation structure 103 may require a respective patterning regime including a highly complex lithography process followed by a respective etch process. During a respective lithography process, very strict overlay tolerances may have to be respected so as to align a respective etch mask precisely to the trench isolation structure 103. For sophisticated devices, corresponding overlay tolerances may be difficult to meet.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
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USPTO Backgrounds