Voice and data switches are known in the prior art. Packet switching is also known. In the past, however, synchronization for the control of the devices sending and receiving information packets in a voice/data packet switch has been a problem. This problem has been related to the problem of dynamically allocating the packet bandwidth between the various peripheral devices attached to the switch for voice information and data information. Another related factor has been the network interface architecture for the switch. The network interface architectures of past switches have used the same bus for both data and control. When coupled with the problem of dynamically allocating bandwidth on the bus, this network interface architecture has resulted in the switch having a low switching capacity and throughput. These performance problems become even more significant in the context of modern fast packet protocols. It would be desirable, therefore, to provide a voice/data packet switch with an improved network interface architecture.
In a synchronous system a clock signal corresponding to intervals of data transmission is either made directly available to terminals within the network or it is derived from signals sent by the transmitting terminal. In such a system, a master terminal defines the clock information which is derived by slave terminals. Mainframe computer networks which maintain constant communication with slave devices are an example of such networks.
Asynchronous communications differ in that clock information is not provided. Another mechanism must be utilized in order to define the beginning and end of each character or period. In modem networks start and stop bits are utilized by the transmitting modem so that the receiving modem can identify the beginning and end of a transmitted character.
In a TDMA packet network in which each frame contains a plurality of time slots allocated for different users or purposes, it is critical that the receiving terminal be able to properly correlate the beginning of each frame and of each time slot in order to properly decode the transmitted information. It is known in packet systems to utilize a time stamp which is transmitted as part of the packet. For example, see U.S. Pat. No. 4,530,091 and U.S. Pat. No. 4,894,823.
In a wireless packet TDMA system, two types of synchronization is required. First, the beginning of each frame and each time slot (packet) within each frame must be identified. Such identification can be accomplished by transmitting a known data pattern for a predetermined number of bits. This pattern is recognized by the receiving terminal and the beginning of the frame or packet is determined. In a TDMA network in which a master node defines the frame and packet timing for remote terminals, each terminal must be aligned in time relative to the start of the node frame in order to properly receive and transmit information at a predefined time slot within the-frame. Problems in acquiring and maintaining this type of synchronization exist especially in a wireless TDMA packet network in which different directional antennas are used for communications. Thus there exists a need for an improved method for maintaining time synchronization in a wireless TDMA packet network in which multiple antennas are utilized.
Packet data networks convey information from an originator to a specified addressee by incorporating the information into packets. Each packet contains a preamble (control data) and information (message data). The preamble typically includes packet network control data, synchronization information, and addressee destination information. The information portion contains part of the total originator's message.
The packet originated by the addressor is typically not directly received by the addressee. The packet may be relayed by several intermediate stations before reaching the final addressee destination. As the transmission speeds of packet networks increase, it becomes increasingly important for relay stations to be able to efficiently handle and process packets.
In a direct method for handling packets, received packets are stored in a memory location. The destination of the packet contained at the preamble is checked as well as other packet network control information. Correct receipt or validation of the control information and the packet data information is checked. Assuming no errors are detected, a new packet corresponding to the received packet is created and stored in a different memory location for transmission. At the appropriate time, the reconstituted packet is retransmitted by the relay station towards its final destination.
Packets are handled in a different manner in an Ethernet local area network. A buffer ring structure comprised of a series of contiguous fixed length byte buffers are utilized for storage of received packets. The beginning and end location of the stored packet is identified by addresses held in a page start and a page stop register. Successive buffers in the ring are utilized to store the packet. Multiple packets can be consecutively stored in the ring structure. The packets are normally removed from the receive buffer ring in FIFO order and are reconstituted for retransmission in memory separate from this ring.
There exists a need for an improved method for organizing and handling packets that minimizes intermediate data transfer to additional memory locations prior to retransmission of the packet.
Packet protocols become increasingly inefficient as the amount of data to be transmitted per packet decreases because of the required packet overhead required for each packet. Although short commands can be transmitted from one point to another using packets, a substantial delay exists before the receiving device can act upon the command due to the time requirements of packet transmission and packet disassembly before the command can be forwarded to the destination device.
In a conventional direct control systems each function to be controlled is assigned a separate wire or communication channel which carries a predetermined command from a controller to the device implementing the function. Such systems exist for a variety of applications and are efficient where a limited number of commands are to be transmitted to specific devices. These systems become increasingly complex as the number of commands and devices to be controlled increase. No addressing is required in these systems since each dedicated path has a preassigned single function to control.
There exists a need for a system and method which can carry information utilizing packets while minimizing the inefficiencies related to the transmission of commands to associated devices.
USPTO Backgrounds
USPTO Backgrounds