High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory. In recent years, there has been an effort to further increase the speed of memory access.
In conventional peripheral circuitries for a semiconductor memory device, for example, pads and data input/output circuits are arranged in a corresponding manner across layers. For example, a semiconductor memory device may include a data input/output circuit. To achieve high speed transmission, the impedance of the data input/output circuit should be controlled. To control the impedance, an external resistance, such as ZQ resistor may be coupled, and a driver impedance may be adjusted based on a comparison with an impedance of the ZQ resistor. However, in some instances, the impedance curve of a driver to be adjusted may be non-linear such that adjustments in one part of the curve may have a smaller impact on impedance of the driver than adjustments in other parts of the curve.
USPTO Backgrounds
USPTO Backgrounds