In a photolithographic process, a semiconductor device results from a mask based on a corresponding layout diagram. In some approaches, a layout diagram is pre-distorted in a manner which mitigates optical proximity effects (OPEs) that otherwise result in shape distortions in the semiconductor device based on the corresponding layout diagram. In some approaches, OPEs are mitigated after the uncorrected layout diagram has been generated, such as during tape out, using optical proximity correction (OPC).
USPTO Backgrounds
USPTO Backgrounds