1. Field of Invention
Embodiments of the invention relate generally to electronic devices and, more specifically, in certain embodiments, to fin transistors.
2. Description of Related Art
Fin field-effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member) rising generally perpendicularly from a substrate. Typically, a gate traverses the fin by conformally running up one side of the fin, over the top, and down the other side of the fin. In some instances, the gate is disposed against the sides of the fin and does not extend over the top. Generally, a source and a drain are located on opposite sides of the gate, near the ends of the fin. In operation, a current through the fin between the source and drain is controlled by selectively energizing the gate.
Some finFETs include gates formed with a sidewall-spacer process. In some versions of this process, the gates are formed by covering a fin with a conformal, conductive film and, then, anisotropically etching the conductive film. During the etch, the conductive material is removed faster from the horizontal surfaces than from the vertical surfaces. As a result, a portion of the conductive material remains against the vertical sidewalls of the fins, thereby forming the gate. An advantage of this process is that relatively narrow gates can be formed relative to gates patterned with photolithography, which is often subject to alignment and resolution constraints.
Although forming gates with a sidewall-spacer process avoids some process issues, it can introduce other failure mechanisms. Often the sidewalls of the fins are angled rather than vertical because the fins were formed with an etch that is less than perfectly anisotropic. These angled sidewalls can narrow, and in some cases close, the process window for the sidewall spacer. The angles place the bases of adjacent fins closer to one another, and when the conformal film is deposited in this narrower gap, the portions of the film covering the adjacent sidewalls can join, creating a film with a larger vertical thickness in the gap. The film can become so thick in the gap that the sidewall-spacer etch does not remove all of the conductive film between adjacent gates. The resulting conductive residue may form stringers that short adjacent finFETs and lower yields.
USPTO Backgrounds
USPTO Backgrounds