1. Field of the Invention
The present invention relates to a low voltage differential signal driver circuit and a method for controlling the same, and more particularly, to a low voltage differential signal driver circuit which outputs differential amplification signals having constant DC offset voltages and is capable of operating at a high speed at a low voltage, and a method for controlling the same.
2. Discussion of Related Art
In general, a low voltage differential signal driver circuit is being used to match information data between electronic devices at a high speed (for example, more than 200 MHz), in a high capacity information storage device, a high performance computer system, information telecommunication home appliances, a high-speed wire information telecommunication system, and so on.
FIG. 1 is a circuit diagram of a conventional low voltage differential signal driver circuit.
Referring to FIG. 1, the low voltage differential signal driver circuit includes a current source IS defining the magnitude of a driving current; current switches SW1 to SW4 for switching the flow of the driving current in response to a differential digital input signal; and a common-mode feedback block (CMFB) for sensing output matching impedance RO and DC offset voltages of differential output signals VON and VOP to control the magnitude of a variable load RL.
In the case where the low voltage differential signal driver circuit of FIG. 1 is manufactured using a complementary metal oxide semiconductor (CMOS) manufacturing process, the current source IS is comprised of an n-channel metal-oxide-semiconductor field effect transistor (nMOSFET) element, the current switches SW1 to SW4 are comprised of nMOSFET elements or pMOSFET elements, and the variable load RL is comprised of a p-channel metal-oxide-semiconductor field effect transistor (pMOSFET) element. As shown in FIG. 1, the conventional low voltage differential signal driver circuit having a general structure where four MOSFETs are series connected, has disadvantages in that the phase noise characteristics are bad due to unbalance of a switching gain and a switching noise that generates when the driving current is switched, and a power supply is low and a high speed operation is limited due to a four-stage series structure and a four-switch structure.
USPTO Backgrounds
USPTO Backgrounds