1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to devices having an SOI (Semiconductor On Insulator) structure and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a DRAM (Dynamic Random Access Memory) is well known in the art as a semiconductor memory device capable of random input/output of memory information. In general, the DRAM includes a memory cell array portion serving as a memory region for storing a large amount of information and a peripheral circuit portion for controlling an operation of the memory cell array portion.
FIG. 50 is a block diagram showing a structure of an ordinary DRAM. With reference to FIG. 50, a DRAM 150 includes: a memory cell array 151 for storing data signals of memory information; a row and column address buffer 152 which receives externally an address signal for selecting a memory cell constituting a unit memory information; a row decoder 153 and a column decoder 154 for specifying a memory cell by decoding the address signal; a sense refresh amplifier 155 for amplifying and reading a signal stored in the specified memory cell; a data in buffer 156 and a data out buffer 157 for data input/output; and a clock generator 158 for generating a clock signal.
In memory cell array 151 which occupies a large area on a semiconductor chip, a plurality of memory cells for storing unit memory information are arranged in a matrix. Generally, one memory cell is formed by a MOS (Metal Oxide Semiconductor) transistor and a capacitor connected thereto. Such a memory cell is called a one-transistor one-capacitor type memory cell. Since this type of memory cell has a simple structure, integration of a memory cell can be improved easily. Therefore, such a memory cell has been widely used in a DRAM having a large capacitance.
Memory cells in the DRAM can be divided into several types depending on a structure of a capacitor. One type is called a stacked type capacitor. In the stacked type capacitor, a major portion of a capacitor is extended onto as far as a gate electrode and a field oxide film so as to increase an opposing area between electrodes of the capacitor.
Accordingly, capacitance of the capacitor can be increased. Having this characteristic, the stacked type capacitor can secure the capacitance of the capacitor even if elements are miniaturized in accordance with high integration of a semiconductor memory device. As a result, such a stacked type capacitor has become widely used as integration of semiconductor memory devices is further developed
However, if elements are further miniaturized in the future, it is likely that securing a certain capacitance of the capacitor will be no longer possible even though the previously described stacked type capacitor is used. Therefore, in order to secure the certain capacitance of the capacitor and to improve a characteristic of a transfer gate transistor used in the DRAM regardless of further miniaturization of elements and high integration of memory cells, a technique using an SOI structure in the DRAM has been disclosed in Japanese Patent Laying-Open No. 60-250665.
FIG. 51 is a partial sectional view showing a DRAM disclosed in Japanese Patent Laying-Open No. 60-250665. An example of a conventional DRAM having an SOI structure will be described below with reference to FIG. 51.
As can be seen from FIG. 51, a thin insulating oxide film 102 and a thick oxide film 103 are formed on a main surface of p type silicon substrate 101. A conductive layer 104 formed of polycrystalline silicon is formed on thin insulating oxide film 102. A capacitor 120 is formed by silicon substrate 101, thin insulating oxide film 102 and conductive layer 104.
An insulating layer 105 having a contact hole at a predetermined position is formed on conductive layer 104. Within the contact hole is provided a plug 106 formed of a high melting point metal silicide or the like. AMOS transistor 107 is formed on insulating layer 105 and plug 106. MOS transistor 107 include impurity regions 121 and 122 serving as source/drain regions formed in a silicon layer and a gate electrode 109.
Impurity region 12 is connected electrically to conductive layer 104 via plug 106. Also, impurity region 122 is connected electrically to a bit line 108. Insulating layers 133 and 134 are formed to cover MOS transistor 107. On insulating layer 133 is provided a word line 110 connected electrically to gate electrode 109.
In such a DRAM having an SOI structure, MOS transistor 107 is formed on capacitor 120 with insulating layer 105 interposed therebetween, whereby a large planar area of capacitor 120 can be secured. This leads to securing of the certain capacitance of the capacitor even in high integration of elements. Also, MOS transistor 107 is provided with a characteristic specific to the SOI structure.
However, even in the DRAM having the SOI structure, there are three problems as will be described below. Now, the first problem will be described. In the DRAM having the SOI structure, a silicon layer in which MOS transistor 107 is formed and conductive layer 104 are formed in separate layers. Therefore, formations of, for example, plug 106 for electrically connecting impurity region 121 in the MOS transistor and conductive layer 104, and insulating layer 105 for isolating MOS transistor 107 from conductive layer 104 in a portion other than plug 106 are required. More particularly, formation of conductive layer 104, insulating layer 105, plug 106, the silicon layer in which the MOS transistor is formed, and the like, has to be formed respectively in separate steps. This results in the complex process and the high manufacturing cost.
Next, the second problem will be described. In the DRAM having the SOI structure, MOS transistor 107 is formed on capacitor 120 with insulating layer 105 interposed therebetween in order to increase the capacitance of the capacitor. This incurs the problem such as the increased height of the DRAM.
Next, the third problem will be described. As can be seen from FIG. 51, impurity region 121 in the DRAM is electrically connected to conductive layer 104 serving as a storage node electrode via plug 106. Accordingly, both a contact portion between impurity region 121 and plug 106 and a contact portion between plug 106 and conductive layer 104 are provided between impurity region 121 and conductive layer 104. Thus, a resistance value between impurity region 121 and conductive layer 104 is increased due to these two contact portions. This results in reduction of an operating speed of the DRAM.
USPTO Backgrounds
USPTO Backgrounds