This invention relates generally to test sockets and more specifically to test sockets for Very Large Scale Integrated (VLSI) circuits. As it is known in the art, once a wafer of semiconductor devices has been manufactured it is generally desirable to test individual die before dicing and sawing. In this manner the failing die can be identified and discarded while the passing die are packaged then subjected to more stringent testing. One technique used to test the die at the wafer level is to use either wire probe cards or a polyimid based membrane attached to an aluminum substrate to interconnect the I/O pads of the die to a device tester so that the die can be exercised to determine if the die are functional.
Typical semiconductor manufacturing processes call for the die to undergo a low level functional test while still at the wafer level. The wafer is cut to produce the individual (singulated) die, with the failures from the low level functional test discarded. The die which have passed the low level functional test are packaged and subjected to vigorous functionality and burn-in testing to insure the die are fully functional across their operating temperature and voltage range. This process suffers from several drawbacks among them being the amount of time consumed, failing to provide for the most efficient use of very expensive tester resources, lost value by the packaging of some die which pass the first limited functionality test but fail the more vigorous testing, and delays in the transmission of test results to the wafer fabrication process which serves to impede yield improvement efforts.
Additionally as the circuitry of the die becomes more complex and more dense the number of I/O pads on the die also increases. In order to minimize die size and maximize the number of I/O pads the distance between the I/O pads (pitch) must shrink and the peripheral array I/O pads are supplemented by I/O pads distributed within the central portion of the die (area array). Techniques for testing and burning-in of finer pitch and area array I/O's need be developed.
One approach to reducing the drawbacks of the typical manufacturing process has been to increase the scope of the wafer level test to include the more vigorous functional and burn-in tests as are done on the singulated packaged die. In order to facilitate the fully functional and burn-in testing, it is necessary to interconnect all or almost all of the I/O pads of the die to the device tester. Wire probe cards are used to access all the I/O pads of the die at the singulated die level but are limited by the pitch between the I/O pads as well as being limited to peripheral pads. These constraints eliminate the use of wire probe cards from contacting more than one die at a time, thus all the die of an entire wafer cannot be fully tested and burn-in tested at the same time.
Another approach has been to use a polyimid based membrane to access the I/O pads of the die. The polyimid based cards suffer from a wasting of tester resources unless wafer yields are close to 100%. Since the die are being tested before being separated from the wafer some faulty die take up a portion of the tester time. For example if a wafer contained one hundred die, all one hundred would be interconnected to the device tester and tested at the same time. If twenty of the die were defective, the failing die could not be removed from the testing procedure until the entire wafer had completed it's testing. In this manner one fifth of the available tester time is wasted on defective die.
USPTO Backgrounds
USPTO Backgrounds