1. Field of the Invention
The present invention relates in general to clock generation, and more particularly to generating clock signals with reduced jitter using a low bandwidth phase-locked loop with a matched clock delay path, and using at least one high bandwidth phase-locked loop with local feedback paths to minimize jitter.
2. Description of the Related Art
A conventional clock generation system typically includes at least one phase-locked loop (PLL) that multiplies the frequency of a reference clock to generate one or more higher frequency clock signals. The clock signals are used for synchronization or other timing purposes and are provided to functional circuitry on an integrated circuit (IC) or semiconductor chip or the like. Each clock signal generated by a corresponding PLL is routed back to a feedback input of that PLL, which attempts to align phase and frequency of the reference and feedback clock signals. Although the reference and output clock signals may have the same frequency, a frequency divider (fixed or programmable) in the feedback path may be used to increase the frequency of the output clock relative to the frequency of the reference clock. Thus, each PLL may be used to multiply frequency to provide a high frequency clock signal.
The functional circuitry depends upon the type of chip or system. A microprocessor chip, for example, typically includes one or more processing cores, one or more memory arrays (e.g., L1 and L1 cache memories), various processor support circuitry and functions, various input/output (I/O) functions, etc. Each clock signal developed by a PLL are distributed throughout the chip via a clock distribution system including conductive traces or the like.
The reference clock may be provided from an external source and typically includes a certain level of input noise contributing to a first type of jitter, referred to herein as input jitter. Jitter is an undesired deviation or variation of clock edges from cycle to cycle. Input jitter is also jitter developed along feedback clock paths and provided to the feedback inputs of each PLL. Input jitter may be caused by thermal noise generated on the chip or temperature gradients across the chip. The clock distribution system may incorporate conductive traces, buffers, inverters, and/or clock repeaters or the like that are used to distribute the clock across the system, such as a semiconductor die. These clock tree devices introduce delays that vary over time, voltage and temperature gradients in which the variations contribute to clock jitter. The supply voltages (e.g., VDD and VSS) may have significant variations across the chip or clock system causing clock edge timing variations thereby contributing to clock jitter from cycle to cycle. Also, temperature gradients across the chip contribute to input jitter. The input jitter (or feedback input jitter) is transferred to the output of the PLL and fed back in the PLL control loop.
A second type of jitter is referred to herein as “internal” jitter, which is jitter generated by or otherwise within the PLL itself. The internally generated noise is caused by a variety of sources, including, for example, circuit components, such as the charge pump, the voltage-controlled oscillator (VCO), etc., as well as external sources, such as the power supply. The internal noise is also caused by thermal noise within the PLL or supply voltage variations applied to components of the PLL. It is undesirable for this internal jitter to be propagated to the output of the PLL.
The overall jitter is the sum of the first (input) and second (internal) types of jitter. In a conventional configuration, the designer attempted to reduce the jitter by adjusting the bandwidth of the PLL. The bandwidth of the PLL may be set or otherwise adjusted by the designer and is largely independent of the frequency. A low bandwidth PLL filters or otherwise attenuates the input jitter, but generally passes the internal jitter. A high bandwidth PLL filters the internal jitter but generally passes the input jitter. Thus, the designer of the PLL was forced to compromise on the bandwidth and was unable to reduce both types of jitter at the same time. Although both input jitter and internal jitter may have been attenuated to some degree with bandwidth adjustment, the sum of the two types of jitter was often still significant. Consequently, the system had to be designed to operate at a higher frequency with the appropriate frequency margin to tolerate the worst case jitter to ensure proper operation.
It is desired to improve the spectral integrity of distributed clock signals by reducing jitter. Reducing jitter relaxes the frequency design constraint and allows for improved efficiency and performance.
USPTO Backgrounds
USPTO Backgrounds