1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a semiconductor device of small package structure that has a large number of external connection terminals.
2. Description of the Related Art
With enhancement in function of semiconductor devices, there has been a great increase in circuit scale and the number of terminals for connection with an outside. While the number of terminals for connecting with the outside has increased greatly, a goal set for semiconductor devices is size reduction. To achieve this goal, various small-sized packages have been developed. An example of inexpensive small-sized packages is window ball grid array (wBGA) packages.
FIGS. 1A and 1B illustrate a sectional structure of a semiconductor device having a wBGA package structure and a wiring layout plan view of its package substrate, respectively. A semiconductor device 10 includes a chip 11, which is bonded facedown to a surface of a package substrate 13 via an adhesive 12. The chip 11 includes die pads 14 for bonding in the middle. The package substrate 13 includes solder balls 15 as external connection terminals, and has a slot 16 formed by cutting out a part of the substrate such that the die pads 14 of the chip 11 are exposed in the middle of the substrate. The slot 16 is a space where the package substrate 13 is cut out, and lines along which the substrate is cut out are referred to as the four sides of the slot 16.
On the bottom surface of the package substrate 13, bonding fingers 17 for bonding are provided in an area adjoining the longitudinal sides of the slot 16 and arranged along those sides. The die pads 14 of the chip 11 and the bonding fingers 17 of the package substrate 13 are connected to each other through the slot 16 by bonding wires 18. Further, the package substrate 13 includes on its bottom surface a plurality of the solder balls 15 as external connection terminals. The solder balls 15 and the bonding fingers 17 are connected to each other by wiring patterns 19. Of the wiring patterns 19, ones related to power sources such as a high-power source (VDD) and a grounded power source (VSS) employ wide wiring lines in order to reduce impedance and control noise. The wiring patterns related to power sources are therefore grouped together and illustrated in FIG. 1B as hatched, or vertically striped, wide wiring patterns 19 along with the solder balls 15. The semiconductor device 10 also includes molds 20, which respectively protect the rear side of the chip 11 and the slot portion.
The chip 11 is bonded to a surface of the package substrate 13 that is opposite from the surface where the solder balls 15 are provided (attached to the top surface of the substrate) with the use of the adhesive 12. The chip 11 is bonded such that the die pads 14 of the chip 11 are disposed in the middle of the slot 16 of the package substrate 13. The slot 16 is created by cutting out the middle part of the package substrate 13, and the die pads 14 on the chip 11 and the bonding fingers 17 on the substrate are arranged along the longitudinal sides of the slot 16 on a one-on-one basis. The die pads 14 and the bonding fingers 17 are connected by bonding with the use of the bonding wires 18.
In this manner, in a wBGA package, external connection terminals (solder ball terminals) and bonding fingers are disposed on the same surface of a package substrate and connected to each other by substrate wiring patterns. The opposite surface of the package substrate is a chip mount surface on which a chip is mounted. The chip is mounted such that die pads provided in the middle of the chip are disposed in the middle of a slot cut in the substrate. The die pads of the chip and the bonding fingers are connected by wire bonding through this slot.
A wBGA package is a low-cost package and is designed based on design standards, an example of which is illustrated in FIG. 2. For example, an angle θ of the bonding wires 18 is prescribed in order to avoid interference with the die pads 14 adjacent to the wires. As illustrated in FIG. 2, the angle θ is an angle that each bonding wire 18 forms with each straight line (dotted line of FIG. 2) which runs through the center of each die pad and intersects vertically a straight line (not shown) on which respective pads are aligned. The bonding wire angle θ is within 45° in an example of the design standards. A pitch A which defines the interval between bonding fingers is derived from the size of a capillary employed (tool used in bonding), and is prescribed in order to prevent the capillary from coming into contact with the wires. The bonding finger pitch A is 150 μm at minimum in an example of the design standards.
Japanese Unexamined Patent Application Publication (JP-A) No. 2001-298039 (Patent Document 1) discloses a chip-size semiconductor device which makes high-density packaging possible. The semiconductor device has a structure in which external electrode terminals are provided on the bottom surface of a semiconductor carrier, a plurality of electrodes arranged in a staggered pattern and electrically connected to the external electrode terminals are disposed on the top surface of the semiconductor carrier along with a semiconductor element, and the staggered electrodes and electrodes on the semiconductor element are connected by wires. With the staggered arrangement of electrodes, the area that the wiring takes up is prevented from expanding beyond the extent of the semiconductor element, thereby reducing the semiconductor device in size.
USPTO Backgrounds
USPTO Backgrounds