1. Field of the Invention
The present invention relates in general to a manufacturing process of a thin film transistor liquid crystal display (TFT-LCD). In particular, the present invention relates to a TFT-LCD manufacturing process using three photolithography process masks.
2. Description of the Related Art
A liquid crystal display (LCD) employing a thin film transistor (TFT) as an active device provides advantages of low power consumption, thin profile, light weight and low driving voltage. However, the TFT process consists of multiple masks in multiple photolithography processes, usually more than seven masks, thereby encountering the problems of poor yield and high cost. In order to improve the problems, reducing the steps of the photolithography process becomes an important issue.
U.S. Pat. No. 5,478,766 discloses a process for forming of a TFT-LCD by multiple photolithography processes using three masks. FIGS. 1A to 1C show top views of the masks used in the TFT-LCD manufacturing process according to the prior art, and FIGS. 2A to 2E are cross-sectional views along the line 1A-1Axe2x80x2 in FIGS. 1A to 1C of the prior art. First, as shown in FIG. 1A and FIG. 2A, a first metal layer is deposited on a substrate 21, and patterned by a first photolithography process to form a gate electrode 22 and a gate line (not shown) connected to the gate electrode 22. Usually, the metal layer is further oxidized to form a protecting layer 23 covering the gate electrode 22. Then, as shown in FIG. 2B, an insulating layer 24, an amorphous silicon layer 25 and a doped silicon layer 26 are deposited on the substrate 21. Next, as shown in FIGS. 1B and 2C, a second metal layer is deposited on the doped silicon layer 26. The second metal layer is then patterned as a signal line 27 and a source/drain metal layer 28 by a second photolithography process. As shown in FIGS. 1C and 2D, an indium tin oxide (ITO) layer is deposited on the substrate 21. A photo resist layer (not shown) is then formed above the ITO layer, then the ITO layer is patterned to form a pixel electrode 29 by a third photolithography process. Finally, as shown in FIG. 2E, the same photo resist layer is used to define the patterns of the source/drain metal layer 28 and the doped silicon layer 26. A source electrode 31 and a drain electrode 32 are finally formed.
According to the above process, the masks used in the photolithography process are reduced to three masks; however, an insulating layer 24 is formed between the pixel electrode 29 and the substrate 21, and the transmission of the display is decreased. Further, the first metal layer and the second metal layer cannot electrically connect for avoiding the damage of electrostatic discharge (ESD) because the insulating layer 24 is remained on the substrate 21. The reliability of the LCD may be poor because of the damage of electrostatic discharge (ESD).
An object of the present invention is to provide a process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) by three masks, providing a protective circuit to avoid ESD effect, increasing the transmission of the TFT-LCD, and forming a capacitor in the TFT-LCD to solve the above problems.
Another object of the present invention is to provide a process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) with a protective structure to avoid capacitor shorts and shorts between the gate line and the signal line.
In achieving the above objects, the process for manufacturing the thin film transistor liquid crystal display comprises the steps of:
(a) providing a substrate having a transistor area, a capacitor area, a pixel area, and a gate pad area;
(b) depositing and patterning a first metal layer on the substrate to form a gate electrode, a capacitor upper electrode, and a pad electrode respectively in the transistor area, the capacitor area, and the gate pad area;
(c) depositing and patterning an insulating layer, a semiconductor layer, a doped silicon layer and a second metal layer to (1) form an TFT island structure in the transistor area and a capacitor in the capacitor area, and (2) remove the second metal layer, the doped silicon layer, the semiconductor layer and the insulating layer in the pixel area and the gate pad area to expose the substrate in the pixel area and expose the pad electrode in the gate pad area; and
(d) depositing a transparent conducting layer, and (1) patterning the transparent conducting layer by defining a channel area in the transistor area, and removing the transparent conducting layer within the channel area, and (2) removing parts of the second metal layer and the doped silicon layer uncovered by the transparent conducting layer so as to define a source electrode and a drain electrode in the transistor area, therefore, the source electrode and the drain electrode being separated by the channel area to expose the semiconductor layer in the channel area.
USPTO Backgrounds
USPTO Backgrounds