A data generator stores arbitrary data patterns in a memory and reads the data patterns out to generate output data. To generate high speed data patterns, the pattern data is read out of the memory in parallel and then converted to serial data. The generated data may be directly used as digital data. Alternatively, multiple serial data outputs may be combined as fast parallel data that are converted to an analog signal by digital to analog conversion. Such an apparatus is called a signal generator. The AWG series of Arbitrary Waveform Generators, manufactured by Tektronix, Inc., U.S.A., are an example of these types of signal generators.
One of usages of the signal generator is to provides signals that represent signals of an unfinished circuit block under development. The signal generator provides a finished circuit block with a signal that the unfinished circuit block will provide in response to a given signal from the finished circuit block. This allows a user to check operations of the finished circuit blocks even if other circuit blocks have not been finished. As described, the signal generator provide an output signal in response to the given signal. The given signal triggers the signal generator to output its signal so that the given signal is called a trigger signal hereinafter. The signal generator includes a data generator having circuitry for implementing the data generation in response to the trigger signal, which has been realized in two types as described below.
FIG. 1 is a block diagram of an example of a conventional data generator. A clock generator 12 provides a continuous clock CLK to a clock gate circuit 14. The clock gate circuit 14 enables the clock CLK in response to a trigger signal. A parallel to serial converter 16 operates according to the gated clock. The parallel to serial converter 16 provides a divided clock by dividing the clock CLK. The division ratio of the parallel to serial converter 16 is based on the bit number of the parallel data. For example, if the parallel data has 16 bits the division ratio may be 16. A data pattern generator 10 operates according to the divided clock. The divided clock is enabled by the trigger signal and then the data pattern generator 10 provides the parallel data in response to the trigger signal.
FIG. 2 is a block diagram of another example of a conventional data generator wherein blocks corresponding to those of FIG. 1 have the same numbers. The clock generator 12 provides a continuous clock CLK to a parallel to serial converter 16. The parallel to serial converter 16 continuously provides a divided clock by dividing the clock CLK. The data pattern generator 10 has a trigger input and starts to provide parallel data for generating serial data when it receives the trigger signal. The parallel to serial converter 16 converts the parallel data to the serial data.
In the circuit of FIG. 1, the clock CLK (or divided clock) is provided after the trigger signal input and, as a result, the phase of the clock CLK is delayed relative to the trigger signal input. As a method of removing a delay, a DLL (Delay Locked Loop) may be used for intentionally delaying the phase of the clock CLK up to the start phase of the next cycle as if there is no delay. It, however, requires that the clock should be continuously provided so that A DLL cannot be applicable to the case of FIG. 1 because the clock CLK or divided clock is gated by the trigger signal.
On the other hand, the clock CLK or divided clock is continuously provided in the case of FIG. 2 and then the DLL is applicable to speed up a logic circuit operation as described above. It, however, starts to output the serial data according to the divided clock, with the duration from the trigger arrival to the serial data output fluctuating because the period of the divided clock is long. FIG. 3 is a timing chart showing a relationship between trigger arrival and the divided clock. For example, if the parallel to serial converter 16 has a 16 to 1 conversion ratio the divided clock has a period 16 times longer period than the clock CLK. This means that the serial data output time point relative to the trigger signal has uncertainty that is 16 times longer than the period of the clock CLK.
Japanese patent application No. 2005-49069 corresponding to US2006/0202875 discloses a circuit that reduces the uncertainty of the serial data output time point to the trigger signal while having the advantage using the logic circuit speed-up by DLL. FIG. 4 is a functional block diagram disclosed in the above Japanese patent application and FIG. 5 is a functional block diagram of a trigger detector 8. In this invention, a phase shifter 20 produces four divided clocks that are shifted in phase relative to each other and a trigger arrival time is detected using them. Parallel data is rearranged based on the detected phase information and then converted to serial data.
It is desirable that duration from the trigger arrival to the data output start is constant. Further, it is necessary that the circuit continuously operates even before the trigger signal arrival because of increased clock speeds. The present invention provides an alternative solution to the invention disclosed in the above Japanese patent application.
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