Traditionally, integrated circuit (IC) chips are connected to external circuits by metal wires (e.g., wire bonding). However, as critical dimension of the IC chips reduces and as scale of the ICs increases, such wire bonding technique is no longer applicable.
Chip scale package (CSP) is considered as the latest generation of chip packaging technology. CSP packaging products have small size, good electrical properties, and good thermal properties. Wafer-chip-scale package (WCSP) is one of the chip scale packages and includes a process of first packaging the whole wafer and then, after testing, dicing the wafer into individual CSP circuits.
FIG. 1 depicts a conventional semiconductor device including a wafer level CSP structure. As shown, the semiconductor device can include a semiconductor substrate 11 having a solder pad 12 and a passivation layer 14 on surface of the semiconductor substrate 11. The passivation layer 14 has an opening exposing the surface of the solder pad 12. A re-wiring layer 16 is on a surface portion of the passivation layer 14 and includes an opening in the passivation layer 14, such that the re-wiring layer 16 is connected to the solder pad 12. A columnar electrode 17 is on surface of the re-wiring layer 16 outside of the opening. An insulating layer 20 covers the re-wiring layer 16 and a portion of the passivation layer 14. The insulating layer 20 has a top surface flushed with a top surface of the columnar electrode 17. A solder ball 21 is disposed on the columnar electrode 17.
The solder ball in conventional semiconductor devices, however, may be easily detached from the columnar electrode. The disclosed methods and devices are directed to solve one or more problems set forth above and/or other problems.
USPTO Backgrounds
USPTO Backgrounds