1. Field of the Invention
The present invention relates to an arithmetic unit which performs arithmetic operations on data and, more particularly, to a multiplier which performs multiplication on data.
2. Description of the Related Art
In computers, floating point numbers and fixed point numbers are handled. Arithmetic units for performing operations on floating point numbers and fixed point numbers are known. An arithmetic unit for performing multiplication among such arithmetic units is called a multiplier. Conventional arts described below are known as arts relating to arithmetic units and multipliers.
Japanese Patent Laid-Open No. 61-49234 discloses a floating-point multiplication circuit designed to efficiently execute multiplication of integers as well as multiplication of floating point numbers. According to the technique disclosed in Japanese Patent Laid-Open No. 61-49234, integer data is expressed in floating-point form such that the most significant bit of a mantissa part is 0. This technique eliminates any special discrimination between integer data and floating point number data and enables these two kinds of data to be handled in a unifying manner.
Japanese Patent Laid-Open No. 5-40605 discloses a floating-point multiplier which performs multiplication of fixed point numbers and non-normalized floating point numbers as well as normalized floating point numbers. For example, a fixed point number is shifted by the number of successive 0s from the most significant bit by a left shifter and thereafter provided to a multiplication circuit for performing multiplication of normalized floating point numbers. Also, the sum of the amount of shift of a multiplier and the amount of shift of a multiplicand is computed by an adder. The multiplication result output from the multiplication circuit is shifted by the amount corresponding to the sum of the amounts of shift by a right shifter.
Japanese Patent Laid-Open No. 10-333886 discloses a technique with the objective to reduce the scale of a floating-point multiplication circuit. The floating-point multiplication circuit has a multiplier for performing multiplication between a mantissa part of a first value and a second mantissa part of a second value. The multiplier obtains partial products by means of a second-order booth decoder and a selector. The obtained partial products are added in an array manner.
Japanese Patent Laid-Open No. 5-150870 discloses a technique with the objective to reduce the power consumption of an arithmetic circuit in a digital signal processor (DSP) The arithmetic circuit has a plurality of functional blocks, a plurality of switches and a control block. The plurality of switches turn on/off clock signals supplied to the plurality of functional blocks. The control block controls each switch to control the supply of the clock signal to the corresponding functional block.
Japanese Patent Laid-Open No. 9-114639 discloses a bit field operation circuit in a microprocessor. The bit field operation circuit has a mask data generation circuit and performs a bit field operation by using mask data output from the mask data generation circuit. The mask data generation circuit has a mask bit generation circuit and a shifter. The shifter shifts a mask bit output from the mask bit generation circuit by an amount corresponding to predetermined bits, and outputs the mask bit as mask data to an arithmetic unit.
USPTO Backgrounds
USPTO Backgrounds