A typical PLD uses a memory to program the logic circuitry within the PLD. The memory typically resides on the same silicon die and in the same silicon substrate as do the logic circuitry and other circuitry within the PLD. For a PLD with a relatively large number of programmable elements, the memory may store a large number of bits. Consequently, the memory typically consumes a relatively large and substantial area of the silicon die. For a given die size with a total die area, the area that the memory consumes reduces the area available to the other circuitry within the PLD, such as the logic circuitry. Thus, the overall capacity of the PLD in (terms of equivalent gates or other measure) decreases.
Furthermore, building interconnects between the memory and the logic circuitry typically uses a relatively large number of metal layers, contacts, and a correspondingly substantial number of vias. Fabricating the memory in the same substrate as the logic circuitry leads to using interconnect resources that the logic circuitry would otherwise use, in turn resulting in use of additional interconnect resources. A need therefore exists for PLDs with increased circuit density and efficient use of equivalent gate-count and interconnect resources.
USPTO Backgrounds
USPTO Backgrounds