(1) Field of the Invention
This invention relates to methods and systems for controlling a semiconductor manufacturing line. In particular, the invention relates to method and systems determining the optimal queue time based on utilization loss and rework percentage being dependent upon wafer lot order.
(2) Description of the Prior Art
In semiconductor manufacturing, cycle-time is a most critical factor. Cycle-time can be defined as the sum of processing time and queue time. The queue time represents the time difference between the time when a wafer or lot leaves a process step and the time when it enters the next process step. While the processing time is defined by the type of process tools used in a manufacturing line the queue time can be influenced by manufacturing line control methods as e.g. managing the order of wafer lots.
In semiconductor manufacturing, queue time (or time window) control is commonly implemented between processes. The selected queue time may affect the materials applied to a semiconductor substrate, as well as electrical properties of a device being formed. The control of queue time is implemented for known time-sensitive process steps that are commonly discovered by experimentation or general knowledge of the manufacturer (e.g. through experience). Such approach is highly dependent on the human judgment and does not take into consideration utilization loss and rework percentage. In view of this, there is a need for a wafer lot order method that takes into consideration utilization loss and rework percentage for time window control.
Prior art patent documents, U.S. Patent (U.S. Pat. No. 6,470,231 to Yang et al.), U.S. Patent (U.S. Pat. No. 7,027,885 to Barto et al.), and U.S. Patent Publication (US 2005/0234578 to Liu et al.) disclose queue time control. U.S. Patent (U.S. Pat. No. 6,470,231 to Yang et al.) teaches a dispatching system and method. In the lot order algorithm of this prior art, each wafer is dispatched to an available tool in accordance to scheduled output, wherein the output of each tool must be maximized and wafer with higher priority have to be processed first. Although queue time was mentioned in the ranking algorithm in this prior art, an approach of determining the optimum allowable queue time based on utilization and rework percentage is not disclosed in this prior art. U.S. Patent (U.S. Pat. No. 7,027,885 to Barto et al.) relates to a technique by which a manufacturing process flow determines when to begin processing a batch of lots. U.S. Patent Publication (US 2005/0234578 to Liu et al.) discloses a method and system for identifying process steps for queue-time control and abnormality detection.
Furthermore there are more patents in the field of dispatching wafer lots of a semiconductor manufacturing lines:
U.S. Patent (U.S. Pat. No. 7,020,594 to Chacon) proposes an integrated wafer fab production characterization and scheduling system incorporating a manufacturing execution system with a scheduling system based on simulation. The integrated characterization/scheduling system provides manufacturing with a simulation tool integrated with the manufacturing execution system to evaluate proposed production control logic as a practical alternative to expensive experimentation on actual production system. Furthermore, simulation models are used to create short-term dispatch schedules to steer daily manufacturing operations towards planned performance goals. Innovative features include integration of preventive maintenance scheduling, Kanban based WIP control, an integrated time standard database, a, and real time lot move updates.
U.S. Patent (U.S. Pat. No. 6,763,277 to Allen, Jr. et al.) discloses a method, apparatus, and system provided for a proactive dispatch system to improve line balancing. At least one request for processing a semiconductor wafer is received. A line-balancing analysis based upon the request is performed. At least one semiconductor wafer based upon the line-balancing analysis is processed.
U.S. Patent (U.S. Pat. No. 5,818,716 to Chin et al.) discloses a semiconductor manufacturing fabrication plant with production to-order type operation having hundreds of devices and various processes to be managed. To provide short cycle time and precise delivery to satisfy customer expectations is a major task. A dispatching algorithm named “Required Turn Rate (RTR)” functions according to the level of current wafers in process (WIP) algorithm revising the due date for every lot to satisfy the demand from Master Production Scheduling (MPS). Further the RTR algorithm calculates the RTR of each lot based on process flow to fulfill the delivery requirement. The RTR algorithm determines not only due date and production priority of each lot, but also provides RTR for local dispatching. The local dispatching systems of each working area dispatch the lots by using required turn rate to maximize output and machines utilization.
USPTO Backgrounds
USPTO Backgrounds