1. Field of the Invention
The present invention generally relates to the field of memory systems and in particular to the field of means for generating memory-internal command signals for memory systems.
2. Description of the Related Art
In memory systems, like for example a DRAM memory (DRAM=dynamic random access memory) typically several subprocesses have to be carried out in the memory system for performing a memory operation, as for example a read operation, a write operation or an update operation. Such subprocesses for example include an activation of a memory bank, an activation of row address lines, an activation of a read process or a write process or a precharging, in order to bring the memory system for the next memory operation into an available state.
These processes need to be performed with delays time matched to each other, in order to avoid conflicts resulting from a too early or too late triggering of the processes.
Typically, a command decoder is used for controlling these time matched storage processes, which is connected to a command line, like for example a command bus line, on the input side for receiving memory operation commands and connected to internal command signal lines of the memory system on the output side for outputting commands associated with the respective subprocesses.
The command for performing a memory operation is thereby applied to the input of the command decoder via the command line, wherein the command decoder thereupon creates one or several memory-internal command signals which are applied to internal command signal lines of the memory system.
FIG. 1 shows a known command decoder, wherein one command input 110 is connected to several delay units 112a, 112b, 112c. Each of the delay units 112a, 112b and 112c is connected to a first input of the AND logic elements 116a, 116b, 116c, respectively, via the signal lines 114a, 114b, 114c, respectively.
Second inputs of the AND logic elements 116a-116c are further connected to a clock signal input 120 via a signal line 118. Furthermore, the outputs of the AND logic elements 116a-116c are connected to memory-internal command signal lines 122a, 122b, 122c, respectively. In the known command decoder according to FIG. 1 a memory-internal ACTIVATE command signal is transmitted via the command signal line 122a, a memory-internal WRITE command signal is transmitted via the command signal line 122b and a memory-internal PRECHARGE command signal is transmitted via the command signal line 122c. 
A command is input to the command input 110 via a command line, wherein the command causes the delay units 112a-112c to be activated. The delay units 112a-112c thereby are implemented such that a respective delay unit generates an output signal at the outputs 114a-114c after a respective time period T1, T2 and Tn associated with it, with respect to the time or points of time of applying the command to the command input 110. This is performed in that a delay unit, for example delay unit 112a pulls or sets the output line associated with it, i.e. line 114a in the above example, from a logical low state to a logical high state.
The output signals are applied to the first inputs of the AND logic elements 116a-116c via the signal lines 114a-114c. Thereafter, AND-operations with an external clock signal, i.e. more precisely with a state of the line 118 which is determined by the external clock signal, are performed in the AND logic elements 116a-116c. The clock signal is thereby applied to the line 118 connected to the respective second inputs of the logic elements 116a-116c via the clock signal input 120.
The AND-operation to the external clock signal causes that the time-delayed output signals of the delay units 112a-112c are time-synchronized with the external clock signal, so that time-delayed memory-internal command signals are generated at the outputs of the AND logic elements 116a -116c which are time-matched to one of the signal edges of the external clock signal, i.e. either to the rising edge of the external clock signal or the falling edge of same.
The delay values T1, T2, Tn, respectively, of the time delay units 112a-112c are each determined according to the command signals generated by same. By the delay unit 112, for example, a time delay for an activate command signal is determined, wherein the time delay T1 is selected depending on the time at which the memory-internal ACTIVATE command signal is to be applied via the command signal line 122a of the memory system. Accordingly, the delay value T2 of the delay unit 112b is determined such that between the memory-internal WRITE command signal output at the command signal line 122 and the ACTIVATE command signal output at the command signal line 122a such a time delay results, which securely allows the memory system to be able to carry out a write action to the same after activating one or several memory cells of the memory system.
Consequently, the delay time values T1, T2, Tn need to be preset considering the type and the way of functioning of the memory system to which the known command decoder is connected, so that the processes triggered by the command signals are performed in the memory system without conflicts.
The selection of the delay values T1, T2, Tn, respectively, thereby needs to ensure, that at the time at which the command signal is applied to the memory system via the command signal lines 122a-122c, the memory system is ready to properly perform the process caused by the command signal at the memory system.
It is thereby disadvantageous that the performance of the memory systems may be slightly different from memory chip to memory chip. These fluctuations of the performance are caused by fluctuations of parameters in the manufacturing process and include, for example, fluctuations of the width of metallic conductor tracks, different dopant concentrations, etc. This results in different optimum times for generating a respective memory-internal command signal for each memory system.
It is therefore desirable for a certain memory system to generate the command signals close to the optimum time for each respective memory system in order to prevent excessive delays between successive command signals which might result in a bad performance and excessive operation times for performing the memory operation.
The known command decoder according to FIG. 1 thereby has the disadvantage that the delay units 112a-112c generate the respective delays asynchronous with the external clock signal. This means, that the time at which a respective line 114a-114c is set to a logical high state by the delay unit 112a-112c associated with it is not time-matched to the time, at which the clock signal line 118 is set to a logical high state by the external clock signal.
If, for example, the line 114a is pulled to a logical high state at a time shortly after the clock signal line 118 has been pulled to a logical low state, then the memory-internal command signal is only generated to a logical high state with the next transition of the clock signal line 118, i.e. about one clock period later. Consequently, it is not possible with the known command decoder to achieve a high time accuracy of generating the memory-internal clock signals.
Furthermore, it is not possible with the known command decoder to set and/or program the time of generating the memory-internal command signals. A settable delay is desirable, as the performance of the memory system may differentiate from chip to chip, as was mentioned above.
Additionally, with the known command decoder it is difficult to carry out a characterization, i.e. to determine which delays are optimum for the present memory chip. In order to carry out such a characterization of memory timing parameters, like for example a writeback, in the known command decoder, test methods need to be used in which the memory-internal command signals are shifted using more or less delays. These test methods are expensive and further not very accurate.
Therefore it is desirable to have a command decoder for a memory system in which the memory-internal command signals are generated close to the time which is optimum for the memory system and wherein further a simple characterization of decisive memory timing parameters is possible.
It is the object of the present invention to provide a concept which enables an improved and more flexible generation of memory-internal command signals.
The invention is a device for generating memory-internal command signals from a memory operation command, having:
a command input for receiving a memory operation command for performing a memory operation at a memory system;
a clock signal input for receiving an external clock signal;
an output for applying a memory-internal command signal to a command signal line of the memory system; and
a command signal generating means implemented to generate the command signal using the memory operation command at a time depending on the command signal and is selectively settable synchronous with the rising or synchronous with the falling edge of the external clock signal.
The invention is based on the findings that an improved and more flexible generation of memory-internal command signals in a command decoder is achievable by generating memory-internal command signals, which are generated using an applied memory operation command, synchronous with the rising or synchronous with the falling edge of an external clock signal.
It is an advantage of the present invention that a simple and time accurate characterization of memory timing parameters is performable.
In a preferred embodiment a coarse setting of the time of generating the memory-internal command signal is performed by a shift register which is connected to a multiplexer. At the input of the shift register, a command is input via the command line which causes that the first memory unit and/or the first flip-flop of the shift register is set to a high logical state. The shift register further receives an external clock signal which controls a shifting of the shift register. The inputs of the multiplexer are connected to predetermined data outputs of the memory units, wherein it is determined by applying a selection value to the multiplexer which of the memory units is switched to be active. Consequently, a first signal is output at an output of the multiplexer after a predetermined time delay, i.e. at a time at which the input memory value at a logical high state reaches the activated memory cell.
In the preferred embodiment the delay time is further fine-set by a clock signal selection means by generating the memory-internal command signal from the first signal of the multiplexer selectively with a rising edge or a falling edge of the external clock signal in response to a fine-setting selection signal.
It is an advantage of the preferred embodiment that the time of generating is settable or programmable.
USPTO Backgrounds
USPTO Backgrounds