1. Field of Invention
This invention is related to a method and apparatus for manufacturing semiconductor devices including Si devices, GaAs devices and TFT (thin film transistor). More particularly, the present invention relates to a technique which enables, by use of an electric vertical furnace, rapid thermal treatment. More specifically the present invention is related to a heating technique using a heating apparatus having simultaneous different temperature in the different sections along the axis of the electric vertical furnace and shortening the intermediate region between the high and low temperature regions by making the temperature gradient between these regions steep.
2. Description of Related Arts
In accordance with the development of semiconductor devices in recent years various heat-treatment techniques have been developed. These include such heat treatments as oxidation, diffusion, annealing, CVD and the like in the case of manufacturing ultra LSIs.
A vertical or horizontal hot-wall type electric furnace has been used for the heat-treatments as described above. Meanwhile, along with larger scale integration and fine patterning of semiconductor devices, it is necessary to form a shallow junction and to suppress the re-distribution of impurities. In order to decrease the sum of total heat mass of the Si devices, rapid thermal treatment has been employed.
The first described method using a hot-wall type electric furnace enables a batch treatment and has excellent temperature stability but involves difficulty in temperature-control. The second described method using a lamp-annealing furnace has advantages that a plurality of wafers can be treated, and, further the process-temperature can be controlled. This is therefore allegedly one of the most attractive methods in recent use.
Regarding 64M-DRAMs, the pattern rule for manufacturing semiconductor devices is 0.35 .mu.m rule. In the manufacturing of such devices, a CVD oxide layer is formed as an inter-layer insulating beneath a B-PSG layer and the B-PSG layer is subjected to reflowing to flatten its surface. Total quantity of heat imparted to semiconductor devices is important for manufacturing 64M-DRAMs.
Specifically, in the case of transistors produced by a conventional process, the sources and drains formed by the ion-implantation undergo a shape change when heat is imparted thereto at 850.degree. C. for 70 minutes or longer, so that characteristics of the transistors are impaired. Furthermore, monosilane could be used in the growth of CVD oxide film in the case of 16M-DRAM, whose pattern rule is 0.6-0.4 .mu.m, but could no more be used for 64M-DRAMs because a CVD oxide film is formed at 800.degree.-850.degree. C., if retained for 60-120 minutes.
In the manufacturing of 64M-DRAMs, a process frequently used comprises covering a polysilicon layer with a CVD oxide layer and forming a continuous B-PSG layer to be used as a flattening layer. The CVD oxide layer, which covers the polysilicon layer, prevents boron or phosphorous in the B-PSG layer from diffusing into the polysilicon layer. Thickness of the CVD-oxide layer required to attain this diffusion-preventing function is from 500 to 1000 angstroms.
When an aluminum conductor layer is to be formed on the B-PSG layer, it is necessary to form a CVD oxide layer on the B-PSG layer after its reflowing.
As is described hereinabove, a rapid thermal annealing method is appropriate for manufacturing semiconductor devices having a shallow junction. However, the lamp annealing method does not yet attain a temperature distribution on the wafer surface as uniform as that attained by an electric furnace. Therefore, when a wafer is subjected to the rapid thermal annealing method, thermal stress is caused under the temperature distribution provided by such a method and hence slip lines generate from the peripheral part of the wafer.
Allegedly, the rapid thermal annealing method experimentally achieved success in the heat treatment of 6 inch wafers. However, even in experiments, the slip lines are inevitably formed on the wafers, when the scale of experiments is enlarged such that the number of wafers treated is comparable to that of mass production. In order to avoid the slip lines in mass production, the temperature elevating speed in a lamp-annealing furnace must be lowered to a significantly low level.
Rapid-thermal processing of an 8-inch wafer, which must be used for the 16M or more DRAMs, is more difficult than that for 6-inch wafer. The rapid-thermal processing of an 8-inch wafer is hence not applied to an industrial production. A report is made in J. Vac. Sci, Technol. B. 8(6), Nov/Dec 1990, pp 1249-1259 (American Vacuum Society) that the rapid-heating annealing is tried by using a hot-wall type electric furnace including a silicon-carbide reaction tube. However, in the furnace reported in this journal a mere annealing is carried out.
It is known that a high-temperature region and a low-temperature region are formed in a horizontal furnace, in which a number of wafers are subjected to diffusion sequentially in the above order. A number of wafers are carried on wafer holders successively connected with one another and are conveyed from one end to the other end of the furnace during diffusion. This diffusion method is in principle inappropriate for the formation of a CVD layer and rapid thermal annealing.
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