As microelectronic device dimensions continue to shrink, patterning problems increasingly hinder integrated circuit and semiconductor device fabrication. Semiconductor device fabrication often requires extremely planar surfaces and thin films of precise thickness. The surfaces requiring planarization and thickness control in semiconductor devices include areas or layers of dielectric material (such as SiO.sub.2) on the surface of semiconducting materials and other device pattern layers. The insulating dielectric layers and other device layers need to be extremely planar because irregularities and rough topography lead to fabrication problems, including Depth of Focus budget (hereafter DOF) problems. Since an irregularity in the surface can cause part of the surface to be out of focus at a particular distance between the optical system and the wafer, errors in pattern formations can occur. Also, the thickness of layers needs to be precisely controlled because variations in thickness may affect the electrical properties of the layers and adjacent device patterns, particularly in the interconnections between the different layers of microelectronic devices.
The precise control of layer thickness is also crucial in semiconductor device fabrication. In VLSI technology, for instance, certain layers of multi-layer devices are generally electrically interconnected. These layers are also typically insulated from various levels by thin layers of insulating material (such as SiO.sub.2). In order to interconnect the device layers, contact holes are often formed in the insulating layers to provide electrical access therebetween. If the insulating layer is too thick, the layers may not connect, if the layer is too thin, the hole formation process may damage the underlying device layer.
For normal semiconductor device fabrication, the device layer comprises of a conductor such as aluminum. This conductive material layer is then patterned so that the portions of the device layer that remain are individual conductors that are separated by voids. The individual conductors are subsequently isolated from each other and from a subsequent metal level by deposition of a dielectric layer that fills the voids or spaces between adjacent metal lines, and leaves an insulating layer on top of the conductors. The conductors and voids that underlie the inter-level dielectric layer affect the leveling of the inter-level dielectric layer. Planarization systems are then needed to level the inter-level dielectric layer so that a stack of conductive layers and dielectric layers may be fabricated without DOF and other problems.
Chemical-mechanical polishing (CMP) is an often employed planarization technique for limiting variations of layer thickness in integrated circuit and semiconductor device fabrication. These variations in layer thickness are often induced by the underlying topography of a patterned device layer which creates peaks and valleys in layers that are deposited above it. Generally, CMP is a technique of planarizing wafers through the use of a polishing pad attached to a rotating table. The wafer is held by a chuck above a polishing pad which rotates on a spindle. The wafer is pressed downward against the polishing pad. The nap of the rotating pad removes bits of the film layer, thereby planarizing the surface. A solution of pH controlled fluid and colloidal silica particles called slurry flows between the pad and the wafer to remove material from the polishing area and to enhance the planarization of the wafer surface.
To ensure that an employed planarization system, such as CMP, is continuing to produce acceptable planarization results, periodic tests are conducted on layers that have been subjected to the polishing step. Planarity tests may also be conducted when establishing new fabrication processes or when comparing the planarization ability of different planarization systems or when evaluating maintenance needs of an existing planarization system (for instance, the effectiveness of a CMP system may decrease when the polishing pad needs to be replaced).
Currently, techniques for testing a planarization system examine a layer in a semiconductor wafer (which may or may not include circuit elements, such as an integrated circuit) that has been subjected to the planarization system. One technique uses a scanning electron microscope (SEM) on cross-sections of the semiconductor wafer to take thickness measurements of the layers. Another technique uses an optical metrology tool that emits an incident light beam and measures the reflected light from the top surface of the inter-level dielectric layer and from the interface of the inter-level dielectric layer and an underlying layer to take thickness measurements of the inter-level dielectric layer. Unfortunately, these testing techniques have limitations that reduce their desirability.
The SEM technique is very time consuming, highly localized, and does not allow rapid characterization of a planarization system because of the time required to prepare the semiconductor wafer for scanning. The optical metrology technique's accuracy is effected by the location on the semiconductor device where the measurement is taken. Most optical probes have a spot size, smallest zone of focus, of about five to ten micrometers while the patterned device features fabricated on the underlying layer (e.g., substrate) may have dimensions on the order of one micrometer or less. For example, the conductors of a metal layer in a semiconductor device may be around one micrometer in size. Because of the small size of the conductors, multiple conductors may exist in any five to ten micrometers zone of focus. Therefore, a portion of the incident light is reflected by the features at a first depth and a portion of the incident light is reflected by the substrate at a second depth different form the first depth. This difference in the depth of the surfaces reflecting the light has dramatic effects on the accuracy of the measurement taken by the probe. Further, typical VLSI devices have very few suitable areas where the underlying metal pad is larger than the optical tool's spot size, and measurements can be taken. This reduces significantly the ability to obtain dielectric layer thickness information across a whole die and/or wafer.
While some optical metrology tools may have smaller spot size, they are typically much more expensive than those with larger spot size. In addition, even if optical probes with very small spot sizes are used, efforts still must be expended to ensure that the optical probe is positioned over a location on the semiconductor device or integrated circuit that is desired to be measured, for example, where there is no underlying feature that would deteriorate the optical measurement of thickness.
Therefore, an unsatisfied need still exists for systems and methods to test the planarity of layers of semiconductor devices and integrated circuits, that are less time consuming, less laborious, and more accurate.
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