1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to techniques for the reduction of leakage current within integrated circuits.
2. Description of the Prior Art
As process geometries have become smaller, a growing problem is that of leakage current. Leakage current occurs when a transistor is notionally in its switched off state, but nevertheless some current does pass through the transistor. These leakage currents become higher as the transistor becomes smaller in size.
One known technique for the reduction of leakage currents is to use header and footer transistors around the functional circuitry. The header and/or footer transistors supply power to a virtual power rail and then the functional circuits, such as the normal processing circuits required to do the desired processing operations of an integrated circuit, draw their electrical power from the virtual power rails. When it is desired to power down the integrated circuit, then the header and/or footers can be used to isolate the virtual power rails from the power supplies to which they are connected during functional operation. It may also be desired to hold the integrated circuit in a retention mode in which state data is retained within the integrated circuit and the clock is stopped. The integrated circuit may be then resume processing rapidly by restarting the clock and the retained state data will be immediately available. In order to reduce power consumption during such a retention mode of operation, it is known to utilise header and/or footer transistors to at least partially isolate the virtual power rails from the power supplies such that the voltage difference supplied to the functional circuits is reduced and the leakage currents through those functional circuits are reduced. One problem is that if the voltage difference between the virtual rails becomes too low during the retention mode then it is more difficult to rapidly restart processing, e.g. either a long time is taken to bring the virtual power rails back to an operational voltage or there is a risk of the voltage across the functional circuits dipping too low resulting in data loss if the functional circuits resume processing operations and drawing power too soon.
USPTO Backgrounds
USPTO Backgrounds