A flash memory generally comprises a floating gate and a control gate. A dielectric layer such as an oxide-nitride-oxide (hereinafter referred to as “ONO”) layer is positioned between the floating gate and the control gate. A tunneling oxide layer is positioned between the floating gate and a silicon substrate. Flash memory usually stores or removes data by placing or removing electrons or holes in or from the floating gate. Because the floating gate is completely isolated by the tunneling oxide layer and the dielectric layer, once electrons or holes enter the floating gate, they cannot escape from the floating gate even though no power is supplied. Therefore, data can be stored in the flash memory for long time periods without using power.
In order to write or erase data into or from the flash memory, a bias voltage is applied to terminals accessible from outside the memory. That is, a sufficiently strong voltage must be applied to the control gate and to a junction or substrate to generate a strong electric field at both ends of the tunneling oxide. The coupling ratio (hereinafter referred to as “CR”) is a ratio of the voltage applied to the control gate and the junction or substrate, and the voltage induced in the floating gate. As the coupling ratio CR increases, the efficiency of programming and erase operations of a memory cell improves such that the voltage which must be applied from outside to effect such operations decreases.
The CR is defined by the ratio between the capacitance of the tunneling oxide layer and the capacitance of the ONO layer. When the tunneling oxide capacitance is represented as CTUN and the ONO capacitance is represented as CONO, the coupling ratio CR may be expressed as follows:
  CR  =            C      ONO              (                        C          TUN                +                  C          ONO                    )      
For a high CR, the CONO must be relatively high compared to the CTUN. Capacitance is determined by several factors such as the dielectric constant, the thickness of a dielectric layer, and the area of a capacitor.
In a known flash memory, the thickness of the tunneling oxide layer is about 80 Å to 120 Å, and the thickness of the dielectric layer is about 150 Å to 300 Å. As a result, for corresponding areas of the tunneling oxide layer and dielectric layer, the CONO is smaller than the CTUN and, therefore, it is difficult to obtain a CR required for acceptable operation of the flash memory. Accordingly, in order to ensure a high CR, methods for increasing the surface area of the floating gate have been suggested.
Kim et al., Korean Patent Publication No. 2003-29203, describes a semiconductor device fabricating method to prevent leakage of current through a multiple tunnel junction layer by reducing the width of the multiple tunnel junction layer.
Shin et al., Korean Patent No. 375231, describes a method for fabricating a non-volatile memory device to maximize an area in which a floating gate and a control gate electrode overlap by forming a U-type floating gate without increasing a cell area so that a low operating voltage and a fast operating characteristic are realized.
Shin et al., U.S. Pat. No. 6,482,728, describes a method for fabricating a floating gate in a non-volatile memory device to reduce a bridge between floating gates and a field loss during processes such as an ONO etching process. In the above-mentioned U.S. Patent, a conductive layer with upper and lower portions is formed over a substrate with field regions formed therein, and the upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact. The slope-etched upper portion of the conductive layer is again vertically etched and the lower portion of the conductive layer is concurrently slope-etched.
FIGS. 1a through 1g are cross-sectional views illustrating a conventional flash memory fabricating process to increase the surface area of a floating gate. Referring to FIG. 1a, a tunneling oxide layer 2 is deposited on a silicon substrate 1. A first polysilicon layer 3 to form a first floating gate is deposited on the tunneling oxide 2. Then, a first mask layer 4 is deposited on the first polysilicon layer 3. The first mask layer 4 is generally nitride.
Referring to FIG. 1b, some parts of the first mask layer 4, the first polysilicon layer 3, the tunneling oxide 2, and the silicon substrate 1 are removed by a photolithography process and an etching process to form shallow trench isolation (hereinafter referred to as “STI”) within field oxide areas 5 to be formed in a subsequent process.
Referring to FIG. 1c, a field oxide is deposited on the first mask layer 4 and the STI. A chemical mechanical polishing (hereinafter referred to as “CMP”) process is then performed so that the field oxide remains only within the STI areas 6.
Referring to FIG. 1d, the STI field oxide is etched until its height reaches the height of the floating gate 3 and the first mask layer 4 is also removed. Then, a second polysilicon layer 7 is deposited over the whole surface of the resulting substrate to form a second floating gate so that the first floating gate 3 is in contact with the second floating gate. A second mask layer is deposited on the second polysilicon layer 7 and selectively etched to form a second mask pattern 8.
Referring to FIG. 1e, a third mask layer is deposited on the second polysilicon layer 7 and the second mask pattern 8. The third mask layer is then anisotropically etched to form spacers 9 on the side-walls of the second mask pattern 8.
Referring to FIG. 1f, the second polysilicon layer 7 is etched using the second mask pattern 8 and the spacers 9 as a hard mask to form the second floating gate 7. The second mask pattern 8 and the spacers 9 are then removed.
Finally, referring to FIG. 1g, a dielectric layer 10 and a third polysilicon layer 11 are sequentially deposited over the whole surface of the resulting structure to form a control gate.
In the above-described prior art process, the length of the floating gate 7 is extended over the field oxide area(s) 6 to increase the surface area of the floating gate 7. In addition, in order to minimize an increase in memory cell size due to the lengthened floating gate 7, the space between adjacent floating gates is minimized by a hard mask process. Thus, as shown in FIG. 1g, the surface area of the floating gate 7 becomes larger because the height and length of the floating gate 7 increase by h and 2 L, respectively, compared to the surface area of the tunneling oxide.
Moreover, the conventional flash memory fabricating method described above necessarily includes several processes such as photolithography, etching, and hard mask layer deposition to increase the length of the floating gate 7 to extend over the field oxide area(s) 6, thereby increasing process costs.
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