The present invention relates to a code error monitor apparatus for monitoring a code error generated in data transmitted through a transmission line (for example, data bus) More specifically, this invention relates to a code error monitor apparatus which can be suitably used for a transmission line that adopts two different types of systems for detecting a code error.
In recent years, with an increase in the data processing speed in an information processing apparatus an amount of data in a transmission line such as a data bus is also increasing remarkably. When the amount of data to be transmitted increases a code error becomes a problem. Accordingly, in a conventional manner, in order to detect a code error, an error correcting code (a redundant bit) is added to the data to be transmitted so that the code error is detected by the code error detecting systems such as a known odd parity check system and even parity check system, and thus the code error is corrected.
In addition, in a computer system, a CPU (Central Processing Unit) is connected with a apparatus (memory, display, etc.) to be controlled by a system bus composed of a plurality of buses, and occasionally different code error detecting systems are adopted for each bus. In such a system also it is required to suppress a rate of generation of malfunction due to a code error as low as possible.
FIG. 28 is a block diagram showing a structure of the main sections of a conventional code error monitor apparatus. The code error monitor apparatus shown in FIG. 28 detects a code error in data to be transmitted through a data bus according to two different code error detecting systems, and corrects the code error based on the detected results. In FIG. 28, a data bus 1A on the CPU side transmits bit data DATA_A[0] through bit data DATA_A[n] of (n+1) bits, and its one end is connected with a not shown CPU.
In addition, the data bus 1A on the CPU side is provided with a data line for transmitting A-system error correcting code DP_A. The A-system error correcting code DP_A is a redundant bit for detecting a code error in bit data DATA_A[0] through bit data DATA_A[n] according to a system A (for example, odd parity check system). In this odd parity check system, A-system error correcting code DP_A of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is added as a redundant bit to a bit string of (n+1) bits composed of the bit data DATA_A[0] through bit data DATA_A[n] so that a number of xe2x80x9c1xe2x80x9d becomes an odd number in the bit data DATA_A[0] through bit data DATA_A[n] and in A-system error correcting code DP_A.
That is, in the odd parity check system, when the number of xe2x80x9c1xe2x80x9d in the bit string of (n+1) bits is an even number, the A-system error correcting code DP_A of xe2x80x9c1xe2x80x9d is added to the bit string. On the other hand, when the number of xe2x80x9c1xe2x80x9d in the bit string of (n+1) bits is an odd number, A-system error correcting code DP_A of xe2x80x9c0xe2x80x9d is added to the bit string. The bit string composed of ((n+1)+1) bits where the A-system error correcting code DP_A is added to the bit data DATA_A[0] through bit data DATA_A[n] is referred to as an A-system bit string in the following description.
One end of an internal data bus 1B is connected with the data bus 1A on the CPU side, and the other end is connected with a not shown apparatus (for example, memory) to be controlled. That is, the data bus 1A on the CPU side and the internal data bus 1B form a data bus which connects the CPU and the apparatus to be controlled. The internal data bus 1B transmits the bit data DATA_A[0] through bit data DATA_A[n] transmitted on the data bus 1A on the CPU side as bit data DATA_B[0] through bit data DATA_B[n] to the apparatus to be controlled.
That is, similarly to the data bus 1A on the CPU side, the internal data bus 1B transmits bit data DATA_B[0] through bit data DATA_B[n] of (n+1) bits. Moreover, the internal data bus 1B is provided with a data line for transmitting a B-system error correcting code DP_B. The B-system error correcting code DP_B is a redundant bit for detecting a code error in the bit data DATA_B[0]) through bit data DATA_B[n] according to a system B (for example, even parity check system).
In this even parity check system, the B-system error correcting code DP_B of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is added as a redundant code to the bit string of (n+1) bits composed of the bit data DATA_B[0] through bit data DATA_B[n] so that a number of xe2x80x9c1xe2x80x9d in the bit data DATA_B[0] through bit data DATA_B[n] and in the B-system error correcting code DP_B becomes an even number.
That is, in the even parity check system, when xe2x80x9c1xe2x80x9d in the bit string of (n+1) bits is an odd number, the B-system error correcting code DP_B of xe2x80x9c1xe2x80x9d is added to the bit string. On the other hand, when a number of xe2x80x9c1xe2x80x9d in the bit string of (n+1) bits is an even number, the B-system error correcting code DP_B of xe2x80x9c0xe2x80x9d is added to the bit string. The bit string composed of ((n+1)+1) bits where the B-system error correcting code DP_B is added to the bit data DATA_B[0] through bit data DATA_B[n] is referred to as a B-system bit string in the following description.
Thus, in the data bus composed of the data bus 1A on the CPU side and the internal data bus 1B, two different types of code error detecting systems: the system A (odd parity check system) and the system B (even parity check system) are adopted. A A-system code error detecting circuit 2 detects a code error based on the number of xe2x80x9c1xe2x80x9d in the A-system bit string (bit data DATA_A[0] through bit data DATA_A[n] and A-system error correcting code DP_A) according to the system A (odd parity check system).
More specifically, when the number of xe2x80x9c1xe2x80x9d in the A-system bit string is an even number then the A-system code error detecting circuit 2 judges that a code error has occurred in the data bus 1A on the CPU side and outputs an A-system code error detecting signal ERROR_A of xe2x80x9c1xe2x80x9d to the CPU. On the other hand, when the number of xe2x80x9c1xe2x80x9d in the A-system bit string is an odd number then the A-system code error detecting circuit 2 judges that a code error has not occurred in the data bus 1A on the CPU side and outputs an A-system code error detecting signal ERROR A of xe2x80x9c0xe2x80x9d to the CPU.
A B-system error correcting code generating circuit 3 is provided on a downstream side of the A-system code error detecting circuit 2, and generates a B-system error correcting code DP_B of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d so that the number of xe2x80x9c1xe2x80x9d in the bit string of (n+2) bits composed of the bit data DATA_A[0] through bit data DATA_A[n] and the B-system error correcting code DP_B becomes an even number. A B-system code error detecting circuit 4 is provided on a downstream side of the B-system error correcting code generating circuit 3. This B-system code error detecting circuit 4 detects a code error based on the number of xe2x80x9c1xe2x80x9d in the B-system bit string (bit data DATA_B[0] through bit data DATA_B[n] and B-system error correcting code DP_B) according to the system B.
More specifically, when the number of xe2x80x9c1xe2x80x9d in the B-system bit string is an odd number then the B-system code error detecting circuit 4 judges that a code error has occurred in the internal data bus 1B and outputs a B-system code error detecting signal ERROR_B of xe2x80x9c1xe2x80x9d to the CPU. On the other hand, when the number of xe2x80x9c1xe2x80x9d in the B-system bit string is an even number then the B-system code error detecting circuit 4 judges that a code error has not occurred in the internal data bus 1B and outputs a B-system code error detecting signal ERROR_B of xe2x80x9c0xe2x80x9d to the CPU.
In addition, in the conventional code error monitor apparatus, a code error is detected according to the system A on an upstream side of a point xe2x80x98axe2x80x99 on the data bus composed of the data bus 1A on the CPU side and the internal data bus 1B, whereas a code error is detected according to the system B on a downstream side of a point xe2x80x98bxe2x80x99.
In the above constitution, when the A-system bit string is driven to the data bus 1A on the CPU side by the CPU (not shown), the A-system bit string is input into the A-system code error detecting circuit 2 positioned on the point xe2x80x98axe2x80x99. Here, if a code error does not occur in the data bus 1A on the CPU side, the A-system code error detecting circuit 2 outputs an A-system code error detecting signal ERROR_A of xe2x80x9c0xe2x80x9d to the CPU. Then, the B-system error correcting code generating circuit 3 positioned on the point xe2x80x98bxe2x80x99 generates a B-system error correcting code DP_B based on normal bit data DATA_A[0] through bit data DATA_A[n], and outputs the B-system error correcting code DP_B to the B-system code error detecting circuit 4.
If a code error does not occur in the bit data DATA_B[0] through bit data DATA_B[n] transmitted in the internal data bus 1B then the B-system code error detecting circuit 4 outputs a B-system code error detecting signal ERROR_B of xe2x80x9c0xe2x80x9d to the CPU. Normal bit data DATA_B[O] through bit data DATA_B[n] are then input into the apparatus to be controlled. Thus, when a code error does not occur in both the data bus 1A on the CPU side and the internal data bus 1B then the bit data DATA_A[0] through bit data DATA_A[n] driven by the CPU are input as bit data DATA_B[0] through bit data DATA_B[n] to the apparatus to be controlled.
On the other hand, when a code error occurs in the data bus 1A on the CPU side then the A-system code error detecting circuit 2 outputs a A-system code error detecting signal ERROR_A of xe2x80x9c1xe2x80x9d to the CPU. As a result, the CPU executes error correction such as retransmission of the bit data DATA_A[0] through bit data DATA_A[n] where a code error occurred.
Similarly, when a code error occurs in the internal data bus 1B then the B-system code error detecting circuit 4 outputs B-system code error detecting signal ERROR_B of xe2x80x9c1xe2x80x9d to the CPU. As a result, the CPU executes error correction such as retransmission of the bit data DATA_A[0] through bit data DATA_A[n] which are original data corresponding to the bit data DATA_B[0] through bit data DATA_B[n] where the code error has occurred.
As mentioned above, in the conventional code error monitor apparatus, a code error is detected according to the system A on the upstream side of the point xe2x80x98axe2x80x99 in the data bus composed of the data bus 1A on the CPU side and the internal bus 1B shown in FIG. 28, and a code error is detected according to the system B on the downstream side of the point xe2x80x98bxe2x80x99. The portion Z between the points xe2x80x98axe2x80x99 and xe2x80x98bxe2x80x99 is positioned between a portion (portion on the upstream side of the point xe2x80x98axe2x80x99) where the code error is detected according to the system A and a portion (portion on the downstream side of the point xe2x80x98bxe2x80x99) where a code error is detected according to the system B. Thus, this Z is a portion where a code error is not detected at all.
When a code error occurs in the portion Z then the B-system error correcting code generating circuit 3 generates an incorrect B-system error correcting code DP_B based on incorrect bit data DATA_A[0] through bit data DATA_A[n]. However, in the conventional code error monitor apparatus there is no provision to check whether or not the B-system error correcting code DP_B is a correct code. Therefore, even if the B-system error correcting code DP_B is incorrect it is treated as a correct code.
Further, the B-system code error detecting circuit 4 treats the B-system bit string including the incorrect B-system error correcting code DP_B as a correct data so that the code error cannot be detected accurately. The bit data DATA_B[0] through bit data DATA_B[n] where a code error has occurred are input as they are into the apparatus to be controlled so that a malfunction occur.
Thus, in the conventional code error monitor apparatus, malfunction due to a code error is caused by existence of a portion where a code error cannot be detected, and hence reliability and quality of the apparatus is deteriorated.
The present invention has been made in light of the above problems. It is an object of the present invention to provide a code error monitor apparatus which is capable of preventing malfunction due to a code error even if different code detecting systems are adopted and capable of improving reliability and quality.
According to the first aspect of the invention, a A-system code error detecting unit is provided on the downstream side of the B-system error correcting code generating unit, so that even if a code error occurs in the data used in the B-system error correcting code generating unit, the A-system code error detecting unit detects the code error. Thus, according to the first aspect of the invention, even when different code error detecting systems, i.e., the system A and system B are adopted in the data transmission line, the A-system code error detecting unit can detect a code error of the data used in the B-system error correcting code generating unit. As a result, malfunction due to the code error can be prevented based on the detected result, and reliability and quality can be improved.
According to the second aspect of the invention, a code error which occurred on the downstream side of the A-system code error detecting unit on upstream side is detected by a A-system code error detecting unit so that reliability of the data used in the B-system error correcting code generating unit can be verified. Therefore, according to the second aspect of the invention, malfunction due to the code error can be prevented based on the detected result of the A-system code error detecting unit, and reliability and quality can be improved.
According to the third aspect of the invention, a A-system code error detecting unit is provided on the downstream side of the B-system error correcting code generating unit so that even if a code error occurs in the data used in a B-system error correcting code generating unit, the code error is detected by the A-system code error detecting unit. The correcting unit corrects the code error of the data based on the detected result of the A-system code error detecting unit. Thus, according to the third aspect of the invention, even if different code error detecting systems, i.e., the system A and system B are adopted in the data transmission line, after the A-system code error detecting unit detects a code error of the data used in the B-system error correcting code generating unit, the correcting unit corrects the code error. As a result, malfunction due to the code error can be prevented, and reliability and quality can be improved.
According to the fourth aspect of the invention, a correcting unit corrects a code error of the data based on the detected results of a plurality of A-system code error detecting units. Thus, according to the fourth aspect of the invention, since the plural detected results are used, code error detecting accuracy can be improved further than the case where a code error is detected by using one detected result, and a code error can be corrected accurately.
According to the fifth aspect of the invention, on the data transmission line and branch data transmission lines, a code error is detected by a A-system code error detecting unit and A-system code error detecting unit on branch side. Then, a selection circuit selects data on the data transmission line or data on the branch data transmission line based on the detected results of the A-system code error detecting unit and the A-system code error detecting unit on branch side, and the selected data are transmitted to the downstream side. In the case where the A-system code error detecting unit detects a code error, for example, the selection unit transmits the data on the branch data transmission lines where the code error does not occur to the down stream side. According to the fifth aspect of the invention, when the normal data are transmitted to the downstream side by the selection unit, the process for correcting a code error is not required, and thus the data transmission efficiency can be improved.
According to the sixth aspect of the invention, normal data are held previously in a holding unit, and when a A-system code error detecting unit detects a code error of the data on the data transmission line, the normal data are transmitted to the data transmission line by a switching unit. According to the sixth aspect of the invention, the normal data are held in the holding unit, and when a code error occurs, the normal data are transmitted to the data transmission line, that is, recovery function is provided. As a result, it is not necessary to execute the process for correcting a code error, and thus the data transmission efficiency can be improved.
According to the seventh aspect of the invention, a comparison unit compares the normal data with the data where a code error occurred so that a portion where the code error occurred can be specified easily based on the comparison result.
USPTO Backgrounds
USPTO Backgrounds