1. Field of the Invention
The present invention is related to a lateral-diffused metal oxide semiconductor device and fabrication method thereof, and more specifically, to a lateral-diffused metal oxide semiconductor device and fabrication method thereof having a low On-state resistance/breakdown voltage (R/B) ratio.
2. Description of the Prior Art
As manufacturing techniques for semiconductor integrated circuits progress, it is preferable to have controllers, memories and devices for low-voltage operation and power devices for high-voltage operation integrated in one single-chip system. Prior art devices employ an insulated gate bipolar transistor (IGBT) and double-diffused metal oxide semiconductor (DMOS) transistor devices as the power devices of high-voltage operation in the single-chip system.
The DMOS transistor device can be categorized into lateral DMOS (LDMOS) and vertical DMOS (VDMOS) devices. Due to their advantages of higher operational bandwidth, higher operational efficiency, and convenience of integration with other devices such as CMOS devices due to their planar structure, LDMOS devices are more widely used.
FIG. 1 schematically depicts a cross-sectional view of a conventional lateral-diffused metal oxide semiconductor device. As shown in FIG. 1, a lateral-diffused metal oxide semiconductor device 100 includes a P-type substrate 110, an N-type well 120 disposed in the substrate 110, a field oxide layer 130 disposed on the substrate 110, a gate 140 disposed on a portion of the field oxide layer 130, and a spacer 150 disposed beside the gate 140. A P-type dopant region 160 is located in the N-type well 120. The source 170 is located in the P-type dopant region 160 at one side of the spacer 150 and the drain 180 is disposed in the N-type well 120 at the other side of the spacer 150.
As the voltage forced onto the gate 140 of the lateral-diffused metal oxide semiconductor device 100 is higher than the threshold voltage, the lateral-diffused metal oxide semiconductor device 100 turns on. At this time, the high voltage signal inputted to the drain 180 transfers to the source 170 by passing through the N-type well 120. The N-type well 120 is used as a resistance to make the high voltage signal passing through the N-type well 120 drop to a low voltage signal for use in the internal circuits. However, the concentration of the electrical field caused by the sharp doping profile of the interface between the P-type dopant region 160 and the N-type well 120 will lead to low breakdown voltage and high on-state resistance of the lateral-diffused metal oxide semiconductor device 100. As a result, the R/B ratio (On-state resistance/breakdown voltage) of the lateral-diffused metal oxide semiconductor device of the prior art remains at a high level.
Therefore, a lateral-diffused metal oxide semiconductor device is needed for solving the problem of reducing the R/B ratio.
USPTO Backgrounds
USPTO Backgrounds