1. Technical Field
This disclosure relates to a method for eliminating parasitic corner devices which form at corners of active areas in semiconductor devices and more particularly, to a method for forming an isolation spacer for increasing a threshold voltage for the parasitic corner devices.
2. Description of the Related Art
Field effect transistors (FET) for semiconductor devices typically include a doped active area 10 where a channel 14 forms between a source 8 and a drain 12 of the FET as shown in FIGS. 1A and 1B. When a gate electrode 12 is activated under proper conditions, conduction of current between source and drain occurs through a channel 14 (shown in phantom lines) below the gate electrode 12. Many transistor designs include an active area which is at a different height relative to isolation regions 16 adjacent to the active area 10. Due to process control, these isolation regions 16 may be lower or higher than active area 10.
Due to the height difference between the active areas 10 and the adjacent isolation regions 12, parasitic corner devices 18 are formed between the corners of the active areas and a portion of the gate conductor formed in a divot 20 adjacent to the corners. The divot 20 is created during the formation removal of a silicon nitride liner 22 formed in shallow trenches adjacent to the active areas 10. When a gate oxide 24 is formed the divot 20 remains and fills with polysilicon of the gate electrode 12. This parasitic leakage due to the corner device reduces FET performance and leads to errors in data or malfunctions in the FET.
Therefore, a need exists for a spacer which fills the divot to prevent the gate conductor from entering the divot. A further need exists for such a spacer to be formed after implantation of active areas to further reduce a threshold voltage of parasitic corner devices.
USPTO Backgrounds
USPTO Backgrounds