Flash memories have been widely used as digital storage media in digital cell phones, digital cameras, MP3 players etc. Flash memories are devices for which the contents can be erased or programmed by a block or page unit.
FIG. 1 illustrates an architecture of a conventional flash memory device. As shown in FIG. 1, a flash memory includes a memory cell array for storing data information. The cell array includes a plurality of NAND or cell strings, which are connected to bit lines, respectively. As is well known, a NAND string comprises a string select transistor connected to a bit line, a ground select transistor connected to a common source line, and memory cell transistors connected in series between select transistors. Each of the memory cell transistors is controlled by corresponding word lines.
The flash memory further includes a control circuit, an address buffer, a data input/output buffer, a column decoder, a row decoder and a page buffer circuit. The control circuit controls various operations of the memory cell array. The data buffer circuit temporarily stores data input from the outside or output through the memory cell array and the page buffer.
The address buffer circuit latches column and row addresses provided to input/output pins depending on a control of the control circuit. The latched row and column addresses are respectively transferred to the column and row decoder circuits.
The column decoder circuit selects one of bit lines in response to an input address. The row decoder circuit selects one of word lines in response to the input address and provides word line power to selected and non-selected word lines, respectively.
As is generally known, page buffer circuits perform various functions according to an operation mode. For example, page buffer circuits read output data from memory cells of a selected word line during a read operation. Page buffer circuits provide a program voltage or a program inhibit voltage to bit lines according to the states of data to be programmed during a program operation.
However, a verification check is typically performed to determine whether the program operation was successfully performed. If data to be programmed is successfully stored in the memory cell array, this means that the program operation “passed.” If data to be programmed is not successfully stored in the memory cell array, this means that the program operation “failed.”
A semiconductor memory device capable of checking pass/fail status is disclosed in Korean Laid-Open publication No. 10-2003-0061877. FIG. 2 illustrates the architecture of the semiconductor memory device disclosed in the Korean Laid-Open Publication. Referring now to FIG. 2, a conventional semiconductor memory device capable of checking pass/fail status comprises a cell array 10, a page buffer circuit 20, and a pass/fail check circuit 30 for outputting a verification result of a program operation with respect to page data using a signal output from the page buffer circuit 20.
The semiconductor memory device shown in FIG. 2 has a pass/fail check function. According to this function, in advance, a verify read operation is performed by means of the page buffer. Data nWD0 read out by the page buffer is transferred to the pass/fail check circuit 30 so as to check whether a program operation has been successfully performed.
The pass/fail check circuit 30 includes a latch LAT1 comprising a NMOS transistor M1, an inverter INV1, and two inverters INV2 and INV3. The pass/fail check circuit 30 checks whether the data nWD0 has the same values (e.g., a pass data value) or not. If the data has the same values, for example, the present program operation is considered to be successfully performed.
The above-mentioned nonvolatile memory device only checks the pass/fail status of a programming page. Accordingly, when two or more pages are successively programmed, then the pass/fail status with respect to pages other than the programming page may not be checked.
USPTO Backgrounds
USPTO Backgrounds