1. The Field of the Invention
The present invention relates to methods of patterning a volume of silicon-containing material on a semiconductor substrate. More particularly, the present invention relates to methods of forming shaped structures from a volume of silicon-containing material on a semiconductor substrate using ion implantation and an etching process which is selective to either implanted silicon-containing material or to unimplanted silicon-containing material. The present invention is particularly useful for forming shaped silicon-containing material structures such as polysilicon plugs, interconnect lines, transistor gates, trenches, and capacitor storage nodes in an efficient manner and with a high degree of control over the resulting profile of the shaped structure.
2. The Relevant Technology
In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above.
Integrated circuits on electronic chips provide the logic and memory of computers and other intelligent electronic devices. These integrated circuits have advanced to a highly functional level to the benefit of the computers and other intelligent electronic devices. The vast functionality of integrated circuits is also being provided at a cost that is economical, allowing the computers and intelligent electronic devices to be provided to consumers at affordable prices. Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor wafer.
The computer and electronics industry is constantly under market demand to increase the speed and functionality and to reduce the cost of integrated circuits. One manner of accomplishing this task is by increasing the density with which the semiconductor devices can be formed on a given surface area of a semiconductor wafer. In order to do so, the semiconductor devices must be decreased in dimension in a process known as miniaturization. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured.
Accordingly, one aspect of integrated circuit manufacturing that is in need of improvement is the complexity of the processes by which integrated circuits are manufactured. As integrated circuits have become increasingly complex, processing steps for forming the integrated circuits have multiplied in length. The number of fabrication process steps has also increased in proportion to the increased complexity of the integrated circuits. It is axiomatic that, as integrated circuit manufacturing processes increase in complexity, the cost of production of the integrated circuits correspondingly increases. Accordingly, in order to maintain an affordable cost of production of the improved and more functional computers and other intelligent electronic devices, new methods for manufacturing integrated circuits are needed which are simpler and more efficient, which assist in the miniaturization process, and which do not compromise integrated circuit quality or performance.
One necessary stage of conventional integrated circuit manufacturing processes is the formation of shaped structures which are used to form the semiconductor devices or discrete features of the semiconductor devices, such as MOS transistor gate regions and capacitor storage nodes. These shaped structures are generally formed by the patterning of structural layers on the semiconductor wafer. The structural layers are typically patterned with a process which includes depositing the structural layer, covering the structural layer with a photoresist mask, and etching away portions of the structural layer that are not covered by the photoresist mask. The portion or portions of the structural layer that are covered by the photoresist mask form the shaped structure.
The photoresist mask through which the structural layer is etched is conventionally formed by a process known as photolithography. Photolithography generally utilizes a beam of light, such as ultraviolet (UV) light, to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than the section of the semiconductor wafer on which the photoresist coating is to be exposed. Light is passed through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the required size on the wafer. For positive photoresist the portions of the photoresist coating that are unmasked are developed away.
The resolution with which a pattern can be transferred to the photoresist coating from the photolithographic template place limits upon feature sizes that can be created. The dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming shaped structures having feature sizes smaller than 0.2 microns.
As an example of one such shaped structure which is in need of being formed with reduced size is an ovonic cell of a programmable resistor. An ovonic cell is a region of chalcogenide material that has a resistance which is programmable by an electrical charge passed through the ovonic cell. Generally, the ovonic cell is formed by etching out an opening from a volume of material, and thereafter depositing the chalcogenide material into the opening. As a high charge density is most suitable for programming the ovonic cell, it is desirable that the opening be formed with a small cross-sectional area, which serves to increase the density of a charge applied thereto. The opening is conventionally patterned with photolithography. It would be desirable to find a commercially feasible method of forming the opening with a width narrower than about 0.2 microns.
Certain alternative methods to photolithography for forming shaped structures of semiconductor devices with higher resolution than is possible with photolithography do currently exist, but these alternative methods have certain drawbacks and limitations which keep them from being widely employed. For example, one such alternative method is referred to as a disposable spacer flow process. The disposable spacer flow process involves initially forming a sacrificial block of material and then forming spacers at the edges of the sacrificial block of material. The sacrificial block of material is situated such that the spacers are formed in the locations where resulting high resolution shaped structures are to be located. Once the spacers are formed, the sacrificial block of material is removed and the spacers remain to form the shaped structures. As photolithography is not used in forming the spacers, the spacers are not restricted by current photolithography resolution limitations, and can be formed with dimensions less than or equal to 0.2 microns.
One problem with the disposable spacer flow process, however, is that it is limited in the types of shaped structures that can be formed thereby. Generally, such shaped structures must be of a single width. That is, when a sub-photolithography feature, such as an interconnect line, is formed with the disposable spacer flow process at a sub-photolithographic resolution width, the entire interconnect line must be of sub-photolithographic resolution width. The interconnect line cannot then be connected with structures of greater size without further deposition and masking steps to form wider portions of the interconnect lines to which the wider structures can be connected.
There is a need currently existing in the art for a method whereby a shaped structure, such as a semiconductor device feature, can be formed in a manner which is simpler and more efficient than current existing process flows. From the prior discussion, it is apparent that such a method would be additionally beneficial if it could be used to form the shaped structure with reduced dimensions from those that can be achieved with conventional photolithography and in a manner that is more flexible than photolithography-alternatives such as the disposable spacer flow.
Etching processes that selectively etch insulating surfaces efficiently are common. Less common are etching processes that etch conducting layers efficiently and with flexibility. One type of structural layer that is frequently used in forming shaped structures, and particularly shaped structures that are conductive to electricity, is polysilicon. Polysilicon is frequently used in integrated circuit formation and is preferred, in part, because it is easily deposited. Deposition of polysilicon is typically conducted with the use of chemical vapor deposition (CVD) which is typically conducted in a deposition chamber with a chemical reaction involving the pyrolitic decomposition of a precursor material such as silane, disilane, or dichlorosilane.
In order to form a shaped structure from polysilicon, the polysilicon is deposited as a structural layer and is then patterned. Patterning of a layer of polysilicon is conventionally accomplished with a process that involves photoresist patterning and thus the above-discussed shortcomings attendant thereto. Conventional processes for patterning polysilicon also generally involve dry etching with a plasma etching process, which also has certain shortcomings that will be discussed below.
Generally, when etching to form a shaped structure, it is desirable to be able to etch orthogonally into the material being etched. Such an etching process is referred to as an anisotropic etching process. Anisotropic dry etching is a form of etching in which the semiconductor wafer is bombarded with ions generated by a plasma that is formed in a flow of one or more etchant gases. Typically, one or more halocarbons and/or one or more other halogenated compounds are used as the etchant gas. For example, CF.sub.4, CHF.sub.3 (Freon 23), SF.sub.6, NF.sub.3, and other gases are conventionally used as the etchant gas. Additionally, gases such as O.sub.2, Ar, N.sub.2, and others are also added to the gas flow. The particular gas mixture used depends on, for example, the characteristics of the material being etched, the stage of processing, the type of etching system being used, and the desired etch characteristics, such as etch rate and degree of anisotropy.
The anisotropic nature of dry etching is desirable, but it has the drawback of not being highly selective to different types of layers. Because of this drawback, it is difficult to precisely terminate a dry etching process at a desired depth to form a shaped structure with a sharp profile. Also, the patterns that can be formed with a single photoresist masking and dry etching step are limited to a single depth, and to the patterns that can be formed with photoresist. Consequently, forming a shaped structure having a complicated profile requires multiple repeated masking and dry etching steps, which drives up cost. Therefore, it is desirable to design a more controllable etching process, capable of patterning a structural layer such as a polysilicon layer anisotropically, yet with greater control of feature size and profile, and at a low cost.
Such an improved method would also provide numerous collateral advantages in addition to those discussed above. For instance, in order to increase the functionality of the integrated circuit, it would be beneficial if an improved method could be provided that imparts a flexibility to the types of profiles of the shaped structures that can be formed thereby. It would also be beneficial if the improved method simplified the process flows of certain semiconductor device formation processes in order to meet the demand for reduced cost discussed above. In order to further illustrate these and other needs of integrated circuit manufacturing processes, several representative conventional process flows and their limitations will be discussed herein.
A first representative example of a process flow in need of improvement is discussed below. In particular, it is necessary at several stages during an integrated circuit manufacturing process to form openings in an insulative layer of material. Conductive material is deposited into the openings in order to make electrical contact to underlying semiconductor devices or discrete features of semiconductor devices. Generally, an opening through an insulating layer exposing an active region is referred to as a contact opening, while an opening through an interlevel dielectric layer is referred to as a via opening. The term interconnect structure opening will be used herein to collectively refer to such openings through an insulative layer. Contact openings and via openings are filled with a conductive material to form a contact or via. A contact or via opening filled with polysilicon is generally preferred to as a polysilicon plug. As used herein, the term interconnect structure will be used to collectively refer to conductive structures such as contacts, vias, and plugs that electrically connect discrete semiconductor device features located on differing levels of a semiconductor wafer.
To form an interconnect structure opening or another such opening through an insulating layer under conventional process flows, a photoresist mask is formed over the insulating layer and is patterned to leave exposed the area above the location of the insulating layer where the interconnect structure opening is intended to be formed. Material is then removed from the insulative layer to form the opening with an etching process which, in current conventional process flows, is typically the dry etching process discussed above.
The dry etching process has proven problematic, as discussed above, due to its lack of selectivity to different types of materials. In forming interconnect structures with a high density, high aspect ratio interconnect structure openings are required. The aspect ratio of an opening, as used herein, refers to the ratio of the primary vertical dimension of the opening divided by the primary horizontal dimension of the opening. Forming interconnect structures with a high aspect ratio requires a high selectivity of the etching process so that the etching process does not over etch, such as into an underlying silicon substrate. A measure of selectivity is typically achieved with the use of a silicon nitride etch barrier layer. Nevertheless, as aspect ratios increase, it is increasingly difficult to consistently form interconnect structure openings with high aspect ratios using conventional dry etching processes.
Conventional dry etching processes also exhibit poor uniformity, as it is difficult to uniformly etch the entire wafer surface with conventional dry etching processes. Yet another problem associated with dry etching is that it is difficult to dry etch surfaces which are not smooth and have a nonuniform topography. When dry etching such interconnect structure openings, uniformity problems occur in which open surfaces are etched faster than recessed surfaces, and in which the selectivity of the dry etching process varies for the depth of the feature being etched. Thus, a high selectivity is difficult to maintain in surfaces with a nonuniform topography.
A further limiting factor in interconnect structure opening formation is the difficulty involved in masking prior to etching interconnect structure openings. The mask is formed with openings for the interconnect structures that are extremely small when forming high density contact openings, which makes it difficult to correctly align the mask openings to the proper locations on the semiconductor substrate.
To complete an interconnect structure once the interconnect structure opening is formed, the interconnect structure opening is filled with a metal such as aluminum or tungsten. Filling the interconnect structure opening with metal causes additional problems, however, in that aluminum and tungsten do not form a highly conductive interface with an underlying epitaxial silicon of an active region. Aluminum diffuses into the active region and can form conductive spikes that short out the active region. Tungsten tends to chemically react and leave voids at the active region that reduce the conductivity of the interconnect structure. Consequently, when using the aluminum or tungsten as filler materials, elaborate steps of forming a liner layer must be conducted. Formation of the liner layer also poses difficulty, however, as the deposition of the liner layer tends to narrow the contact opening, making it difficult to effectively deposit the filler material.
One type of interconnect structure used to overcome the problems associated with filling the interconnect structure opening is the polysilicon plug. To form a polysilicon plug, an insulating layer is first formed over a semiconductor device feature which is to be provided with electrical communication by the polysilicon plug. The semiconductor device feature typically comprises an active region of a transistor. In MOS transistors, the active region is a source/drain region. Once the active region is formed, an insulating layer such as borophosphosilicate glass (BPSG) is subsequently formed, and is then reflowed. A contact opening is then etched through the insulating layer using photolithography and dry etching. The contact opening is subsequently filled with polysilicon. The polysilicon is typically deposited by chemical vapor deposition as a blanket layer of polysilicon over the entire insulating layer. The portion of the blanket polysilicon layer extending above the insulating layer is then removed using a planarization process such as CMP or a dry etch. Alternatively, the portion of the polysilicon layer situated above the polysilicon plug can be removed by masking the polysilicon and etching the remainder of the polysilicon layer away.
Polysilicon plugs are advantageous in that they form a highly conductive interface to the underlying crystalline silicon of the active region, which thereby overcomes the diffusion problems of interconnect structure formation processes that use metals for the conductive filing material. On the other hand, polysilicon plugs are problematic in that the dry etching process discussed above must still be conducted in the formation of the interconnect structure opening in which the polysilicon plug is formed. Conventional polysilicon plug formation processes are complex. Such complexity restricts throughput and increases the opportunity for error, thereby driving up integrated circuit fabrication costs. Consequently, a need also exists for a method whereby interconnect structures, and especially polysilicon plugs for high aspect ratio interconnect openings, can be formed efficiently and simply and without the need for dry etching to form a high aspect ratio interconnect structure opening.
A further shaped structure which is frequently formed in integrated circuit manufacturing is the capacitor. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. The storage node and cell plate are frequently formed from polysilicon. The polysilicon of the storage node and the cell plate are generally deposited separately and are patterned by conventional photolithography and dry etching. An intervening dielectric layer is formed between the formation of the storage node and the cell plate, typically by growth of silicon dioxide through exposure to oxygen.
An important consideration of forming capacitors in integrated circuits is surface area. A larger surface area of the storage node and upper capacitor cell plate provides greater capacitance. Balanced against this need is the competing requirement that the capacitor occupy a minimum of space on the silicon substrate of the semiconductor wafer. One manner in which the prior art has approached capacitor formation in order to obtain a greater surface area without increasing the space occupied on the silicon substrate is to form the capacitor at a distance above the silicon substrate. When so doing, one of the storage node and the cell plate are typically wrapped around the other in a compact area, forming what is known as a stacked capacitor. One problem common with the various configurations of stacked capacitors and the processes used to form them is that the processes are generally complicated and lengthy, increasing the opportunities for defect conditions to occur and driving up cost. Consequently, a method is needed for forming a stacked capacitor with a large surface area yet occupying a minimum of space on the silicon substrate in a simple and efficient manner. It is also desirable to gain greater charge storage area by integrally forming the stacked capacitor storage node and the underlying interconnect structure.
An additional problem attendant to forming a stacked capacitor is that the stacked capacitor must be linked in electrical communication to an active region on the silicon substrate underlying the capacitor storage node. It is critical in maintaining a high speed of the integrated circuit that the stacked capacitor maintain a high rate of charge retention. This is particularly so in forming integrated circuits that provide memory functions, such as dynamically refreshable random access memory (DRAM) integrated circuits. In order to maintain a high charge retention in the storage node, the stacked capacitor is generally separated from the silicon substrate.
Forming an interconnect structure from an active region on a silicon substrate to a stacked capacitor, however, poses certain difficulties. For instance, conventional methods of forming interconnect structures electrically connecting the storage node with the underlying active region typically involve forming an interconnect structure opening of an extended depth and then filling the interconnect structure opening, typically with polysilicon. The processes which do so, however, are difficult to conduct, as they have narrow process windows for correctly controlling all process parameters such that a defect condition does not occur. For instance, an interconnect structure opening with an aspect ratio of over two to one may be difficult to accomplish with standard dry etching processes.
A further semiconductor device for which an improved manufacturing process is needed is the MOS transistor. The transistor is the mainstay of modem integrated circuit fabrication, and integrated circuits such as microprocessors often utilize millions of transistors in a single chip. Currently, the MOS transistor is the most common type of transistor in integrated circuit formation. Greater functionality is obtained from an integrated circuit by forming a greater number of transistors in the same amount of space on an integrated circuit. Thus, a method is needed that forms a transistor which occupies less surface area of the silicon substrate of the semiconductor wafer.
It is also desired that transistors operate at lower voltage levels. One barrier to the formation of MOS transistors that operate at lower voltage levels is the channel length of MOS transistors. The channel length is generally determined by the width of a gate region of the MOS transistor being formed. The width of the gate region is, in turn, limited in conventional manufacturing processes by photolithography resolution limits as discussed above. The dimensions of the gate region also determines, to an extent, the amount of surface area that the transistor occupies. Accordingly, an improved process is needed which can manufacture transistors on integrated circuits with reduced gate length and with lower operational voltage levels.
The formation of transistors is also a complicated process, requiring numerous steps. The high number of steps required increases integrated circuit manufacturing process costs, reduces throughput, and presents more opportunities for error to occur. Therefore, a method for streamlining the transistor formation process is also needed.
Another shaped structure for which an improved method of formation is needed is a shallow trench that is often etched into a silicon substrate and which is used for forming semiconductor devices such as a trench isolation region and a trench capacitor. A method is needed of forming a trench capacitor that has an adequate volume and yet which does not occupy a large amount of surface area of the silicon substrate in order to provide high capacitance of the trench capacitor. A method of forming a trench with adequate volume would also improve a trench isolation region and help to prevent cross-talk current leakage between source/drain regions of MOS transistors that are typically formed on either side of the trench isolation region.
A further shaped structure that is frequently used in the construction of integrated circuits is the interconnect line. The term interconnect line, as used herein, refers to shaped structures that electrically connect semiconductor devices or features of semiconductor devices located on the same level, or that make electrical interconnections between interconnect structures formed on a single level of the semiconductor wafer, yet which are physically separated from each other. When formed on the top surface of the semiconductor wafer, this structure is referred to simply as a surface interconnect line. When formed beneath the surface of the semiconductor wafer, the interconnect line is referred to as a local interconnect.
One consideration in miniaturizing the integrated circuit is obtaining a more dense packing of the interconnect lines within the integrated circuit. One manner of more densely packing interconnect lines is to form the interconnect lines with a narrower width. Interconnect line widths are currently restricted by the resolution limits of conventional photolithography processes. One manner in which the prior art has attempted to overcome these limitations is with the disposable spacer flow process discussed above. As discussed therein, the thickness of the conducting lines formed with the disposable spacer flow cannot be varied. Consequently, when it becomes necessary to connect the conducting spacers to wider interconnect lines or to devices with larger feature sizes, no extra material is provided for doing so. Thus, a more flexible process for providing narrow interconnect lines is needed.
Other shaped structures are also frequently used in forming integrated circuits and would also benefit from an improved etching process whereby shaped structures could be formed with a more flexible, simple, and efficient process. One application for such shaped structures is in forming micro-machine parts as are commonly used in miniature sensors and actuators. A method is needed for forming such structures with a minimum of material deposition, masking, and etching steps.
A further shaped structure used in integrated circuit formation is a free-standing wall that is used to form capacitor storage nodes and other conducting devices. A method that provides flexibility as to the thickness of the resulting free-standing wall, and as to the shape with which the free-standing wall can be formed is needed. Such a method that can form the free-standing wall efficiently and with sub-photolithographic resolution is also needed.
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