Operational and differential amplifiers typically have an error voltage coupled to the circuit output resulting from noise and other variations existent in the power supply voltage. The error voltage is commonly associated with output gain stages which utilize a frequency compensation capacitor commonly referred to as "Miller" compensation. At sufficiently high frequency, the frequency compensation capacitor effectively becomes a short circuit connecting the gate and drain of an output transistor having a source thereof connected to a power supply voltage. In this diode configured arrangement, the output transistor has a substantially constant gate-to-source voltage. Therefore, any voltage variations in the power supply voltage are directly coupled to the drain of the output transistor which functions as the output of the amplifier. Others have proposed a variety of techniques to minimize the amount of error voltage from a power supply which is coupled to the output of an amplifier and thus improve the amplifier's power supply noise rejection. A cascoded operational amplifier with high power supply rejection is illustrated by David Ribner and Miles Copeland in "Design Techniques for Cascoded CMOS Op Amps with Improved PSRR and Common-Mode Input Range" in the IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, pgs. 919-925, Dec. 1984 at page 919. However, as noted by Ribner and Copeland at page 923, there exists potential frequency stability problems when the cascode compensation is used. Another circuit for improving power supply rejection in an operational amplifier is taught by Roger Whatley in U.S. Pat. No. 4,713,625, assigned to the assignee hereof, wherein charge compensation in a non-signal path of the amplifier is utilized. In some applications, less circuitry than that used in the amplifier taught by Whatley is desired and less circuitry may also have additional benefits as additional circuitry can itself introduce errors into the signal path.
USPTO Backgrounds
USPTO Backgrounds