A Hash memory device is a nonvolatile memory device, which can store data for a long period without the supply of power. In the flash memory device, the data is stored in cells having floating gate transistors, and the data can be written and erased by an electrical programming and erasing operation.
FIG. 1 is a sectional diagram showing a stack-gale type flash memory cell known in the art. In a stack-gate type flash memory cell 100 shown in FIG. 1, a source region 3 and a drain region 4 are formed on a semiconductor substrate 1 with a channel region 2 interposed therebetween, and a tunnel oxide layer 5, a floating gate 6, a dielectric thin film 7, and a control gale 8 are stacked on the channel region 2 in this order. The dielectric thin film 7 is formed of an oxide-nitride-oxide (ONO) film. The source and drain regions 3 and 4 form a junction stricture of an N+ region and an N− region by using a spacer 9. The drain region 4 is connected to a bit-line 11 through a bit-line contact region 10.
FIG. 2 is a diagram showing a memory array constituting an NOR type flash memory cell. When the electrical programming operation is performed on an NOR type flash memory cell, a high voltage of 9V or more is supplied to word lines WL0 to W13 and a voltage of 4V or more is supplied to bit-lines BL0 to BL3. Accordingly, electrical current flows to the channel region 2 and hot-electrons generated in this process are injected to the floating gate 6, thereby increasing a threshold voltage of the flash memory cell. When the electrical erasing operation is performed on the NOR type flash memory cell, a negative voltage is supplied to the word lines WL0 to WL3 and a positive high voltage is supplied to the substrate 1 (or ‘bulk’ in FIG. 1). Accordingly, excess electrons accumulated in the floating gate 6 are discharged toward the channel region 2 through the tunnel oxide layer 5, thereby decreasing the threshold voltage of the cell.
Examples of external interfacing methods of addresses and commands to write and read data to and from the flash memory cell include a parallel interfacing method and a serial interfacing method.
A parallel interlace refers to an interface in which addresses, commands, and data are concurrently input and the data stored in the same address are also concurrently output. More specifically, in the case of an ‘×16’ operation for outputting sixteen data, addresses are concurrently input and sixteen data from DQ0 to DQ15 are concurrently output at a time within a predetermined period of time, i.e., tACC (Address to Output Delay).
On the other hand, a serial interlace refers to an interface in which addresses, commands, and data are sequentially input through a single pin and the data is sequentially output through the single pin.
FIG. 3 is a timing diagram of a serial peripheral interface (SPI) as an example of the serial interlace.
Referring to FIG. 3, an SPI interface uses only four pins that are CS#, SCK, SI and SO. The CS# pin receives a chip select signal for enabling or disabling a chip. The SCK pin receives a data clock signal for synchronizing input or output of data. The SI pin is a serial input pin for inputting addresses, commands or data. The SO pin is a serial output pin for outputting the data stored in the chip. The SPI interface includes one SI pin and one SO pin and therefore all the data are input and output through the SI and SO pins.
The basic principle of operation of the SPI interface is that after the CS# signal is changed to a logic low state, the SCK clock signal is activated and a command signal is input to the SI pin. The command signal is generally one byte signal. The input data to the SI pin is synchronized with a rising edge of the clock signal input to the SCK pin and the output data to the SO pin is synchronized with a falling edge of the clock signal input to the SCK pin.
FIG. 4 is a timing diagram showing a read operation of an SPI interface flash memory cell.
Referring to FIG. 4, a chip is selected when the CS# signal transits from a logic high state to a logic low state. A read instruction is input within the first eight (8) SCK clocks with the command value synchronized with the SCK clock. Thereafter, twenty-four address values are sequentially input in synchronization with the SCK clock. The first eight of the first twenty-four address values are usually used as a sector address for selecting a sector. The next eight addresses are used as an X address for selecting a word line WL and the last eight address are used as a Y address for selecting a bit-line B/L. After the twenty-fourth address is input, read data is output through the SO pin in synchronization with the falling edge of die SCK clock and the output data is sequentially output from MSB to LSB.
FIG. 5 is a circuit diagram showing an exemplary bit-line architecture and a sensing scheme for a flash memory cell.
FIG. 5 illustrates a hierarchical bit-line structure including a global bit-line G_B/L and a local bit-line L_B/L. One bit-line is selected by switching transistors 501, 502, and 503 which are turned on by column select signals YC, YB, and YA generated from a Y decoder (not shown). The YC signal and YB signal are signals for selecting the global bit-line G_B/L and the YA signal is a signal for selecting one of a plurality of local bit-lines L_P/L connected to one global bit-line G_B/L.
In the flash memory cell, the threshold voltage of the cell is varied by the number of electrons stored in the floating gate 6 in FIG. 6 and data is sensed depending on the amount of current flowing in the cell. In order to sense the data, an operation of precharging the bit-line WL to a predetermined voltage level needs to be performed in advance. When a precharge signal PCHARGE is enabled, a transistor 504 connected to a main cell Main Cell and a transistor 514 connected to a reference cell Ref Cell are turned on. Thereafter, the global bit-lines G_B/L and the local bit-lines L_B/L connected to the main cell and the reference cell are precharged to the predetermined voltage level by the switching transistors 501, 502, and 503 selected by the column select, signals YC, YB, and YA and switching transistors 511, 51.2, and 513 selected by a reference column select signal YR.
After completing the precharging operation, the precharge mode is disabled and a sensing operation is initiated. In an erased cell, since the threshold voltage of the cell is lower than the word line WL voltage, the cell is tinned on and a current flows in the cell, thereby decreasing the voltage level of a VM node to a level lower than the precharge level. On the other hand, in a programmed cell, since the threshold voltage of the cell is higher than the word line WL voltage, the cell is turned off and no current flows in the cell, thereby increasing the voltage level of the VM node to a level higher than the precharge level. A sense amplifier S/A senses and amplifies the VM node and the VR node when the voltage level of the VM node is increased (developed) to a suitable level.
FIG. 6 is a block diagram showing a data output path of a serial interface flash memory cell.
In an exemplary architecture shown in FIG. 6, one sector is formed of 2048 columns and 256 rows. The 2048 columns are divided into sixteen (16) I/O groups. When address signals are input, data is sensed by sixteen sense amplifiers S/A0 to S/A15. The high half bytes DO15 to DO8 or the low half bytes DO7 to DO0 of sixteen output signals from the sense amplifiers S/A0 to S/A15 is selected by an address signal Yadd<0>. The selected eight data is input to a shift register and then sequentially output from MSB to LSB in synchronization with the falling edge of the SCK clock.
FIG. 7 is schematic diagram showing a bit-line precharging scheme known in the art.
Referring to FIG. 7, after the entire Y addresses YA<3:0>, YB<7:0>, and YC<3:0> for selecting the bit-line WL are input, one local bit-line L_B/L and one global bit-line G_B/L connected to the switching transistors are precharged.
FIG. 8 is a timing diagram showing a word line enabling operation of an SP1 interface flash memory cell.
Referring to FIG. 8, a read operation instruction is followed by a sector address <23:16> constituting a first byte, an X address <15:8> constituting a second byte, and a Y address <7:0> constituting a third byte. The word line can be enabled after the entire X addresses are input.
FIG. 9 is a timing diagram showing respective timings for precharging, sensing, and latching in a serial interface flash memory cell.
Referring to FIG. 9, the Y addresses are selectively assigned for predecoding of the column select signals YA, YB, and YC. More specifically, the Yadd<7:6> addresses are assigned for YC predecoding, the Yadd<5:3> addresses are assigned for YB predecoding, and the Yadd<2:1> addresses are assigned for YA predecoding. The Yadd<0> address is assigned for selecting one byte of 16 output signals from the sense amplifiers S/A0 to S/A15.
In the prior scheme where only one bit-line B/L selected by the Y addresses is precharged and sensed, the entire address signals, i.e., Yadd<7:1>, need to be input before the one bit-line WL selected from the 128 bit-lines is precharged. In other words, the precharging operation is not performed until the seventh bit of the Y address is input. After completing the precharging operation, precharged transistors are turned off and thereafter a sensing operation and a latching operation are performed on the data.
After the eighth bit of the Y address is input, it is possible to select the high half bytes or the low half bytes of the sixteen sensed data. Using the eighth Y address signal, the data output are multiplexed and only the last eight data are output to the shift register, thereby outputting the data in synchronization with the falling edge of the SCK clock.
Therefore, in the prior precharging method in which one bit-line is precharged, the operations of precharging, sensing and data output multiplexing need to be completed in 1.5 clocks after the seventh Y address is input. In general, since the precharging time ranges from about 15 ns to about 30 ns and the sensing lime ranges from about 10 ns to about 20 ns, the precharging operation and the sensing operation require a total operation time ranging from about 25 ns to about 50 ns.
However, when a frequency of the SCK clock is increased for a high-speed operation, for example, when the frequency of the SCK clock is increased to 40 MHz or more, one clock period of the SCK clock is decreased to 25 ns or less. Accordingly, the time for performing the precharging operation and the sensing operation is insufficient, and it is impossible to complete the operations.
USPTO Backgrounds
USPTO Backgrounds