The present invention relates to a TLB control system in a computer of virtual memory control scheme having a translation lookaside buffer (TLB).
In a computer of virtual memory control scheme, an address translation buffer called a TLB is used to perform high-speed address translation of virtual addresses into real addresses. Each TLB entry has a field of address translation data, including a real page number and a valid bit field indicating validity (or invalidity) of the entry.
When a memory access is performed, the TLB is referred to using a predetermined field of the virtual address as an address. Validity of memory access is checked in accordance with the contents of the predetermined field of the virtual address and the corresponding TLB entry. When the memory access is determined to be valid, it is performed using the real address obtained by the real page number of the corresponding entry and the offset data of the virtual address. Conversely, when the memory access is determined to be invalid, TLB entry replace is performed, and, thereafter, the memory access is performed.
In a computer of virtual memory control scheme using the TLB as described above, processing speed is slow in the case of a fullword access of a halfword boundary, involving a page boundary. When a memory access involves a boundary between two pages, the TLB entries corresponding to the two pages must be checked to determine validity of the memory access, all of which delays processing.
USPTO Backgrounds
USPTO Backgrounds