1. Field
The present disclosure generally relates to the design of a chip package. More specifically, the present disclosure relates to the design of a chip package that includes a high-signal-density bus that results in a distribution of impedance values and in which reflections reach a substantial fraction of a steady-state value within a symbol time.
2. Related Art
In order to achieve high performance in computer systems, the inter-chip communication channels on chip packages need to provide high-bandwidth and low-latency communication between computer system components. However, the technology used in existing inter-chip communication channels is beginning to approach its limits. For example, many existing inter-chip communication channels include signal lines that are paired with corresponding reference-to-ground or return paths. Hence, as the number of signal lines increases, the number of return paths also increases. Unfortunately, there are limits on the number of such interconnections within a chip package. Consequently, as the number of signal lines and corresponding return paths increases, the required number of inter-chip communication channels is beginning to approach these limits, which will constrain communication bandwidth, increase latency and, thus, decrease performance.
Hence, what is needed is a chip package that does not suffer from the above-described problems.
USPTO Backgrounds
USPTO Backgrounds