Historically, integrated circuits (“ICs”) which are configurable post-fabrication have been dominated by field programmable gate arrays (“FPGAs”), which provide an array of identical logic gates or other elements. In some integrated circuit embodiments, the gate array is also coupled to one or more microprocessor cores, for the FPGA components to provide configurable, application-specific acceleration of selected computations. The logic elements in an FPGA are typically very “fine-grained”, as gate arrays which can be connected through data inputs and outputs (“I/O”) to provide a more advanced function such as addition, subtraction or comparison, without separate hard-wired, application-specific components directly providing such advanced functions. The process for configuring the gate arrays of FPGAs is comparatively slow, typically through a serial configuration bus, so that FPGAs generally have not been capable of real-time re-configuration for immediate changes in functionality.
In other circumstances, configurable ICs have involved large-scale (or “coarse-grained” configurable logic elements which are capable of significant functionality, such as multimedia processing, arithmetic processing, and communication functionality. While these large-scale configurable logic elements provide extremely capable acceleration, each group of configurable logic elements is typically different and requires separate programming to carry out its functions. In addition, such large-scale configurable logic elements are not translatable to other functions, exhibiting similar constraints of application-specific ICs (“ASICs”).
Configurable capabilities have also been added to microprocessor, ASIC and memory ICs. For example, in memory ICs, extra or redundant rows and columns are fabricated; when subsequent testing may reveal that selected rows and columns have defects, those affected IC regions are disabled, with the balance of the memory IC being useable potentially and, with the redundancy, may still meet the memory capacity specification. In other circumstances, some amount of configurability may be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths.
In addition, after configuration and during operation, such FPGAs, ASICs, processors, and other configurable logic do not exhibit resiliency. For example, if a portion of the IC becomes defective during operation, the entire IC fails instantly, losing all functionality. While the IC may be taken off line or removed, diagnosed, and depending upon the damage, possibly reconfigured, such ICs are not capable of real-time reconfiguration and transferring of functionality to unaffected portions of the IC.
Another technology created by IBM and referred to as “eFuse” utilizes electromigration to create microscopic electrical fuses which disable selected or defective portions of the IC, with software utilized to open or close gates to re-route chip logic to the remaining good portions of the IC, such as to correct design flaws, fabrication defects, and manage power consumption. For example, the eFuse technology can disable defective memory rows and columns, and eFuse software can change memory addresses so that data will be stored in the non-defective portions of the memory.
None of these technologies, however, addresses the increasing number of defects which are now arising in sub-100 nm IC fabrication. More particularly, as IC feature size continues to decrease below 90 nm, there are increasing levels of defects and decreased IC yields. In addition, while an IC initially may be sufficiently free of defects to operate for its intended use, the smaller feature size also increases the probability of IC failure during operation, such as due to tunneling and electromigration effects.
In addition, while each of these prior art technologies have their own advantages, such as an ability to correct design flaws and to work-around minor fabrication defects, none of these prior art technologies provide sustainable resiliency over time, during IC operation. Whether defects were created during fabrication or much later, during IC usage, these known technologies simply cannot accommodate both certain kinds of defects and certain levels of defects, and the entire IC fails completely. Such failure is often catastrophic, such that the entire IC fails instantly and without warning. For example, if a region of a microprocessor fails, the entire microprocessor becomes instantly useless.
To attempt to provide some level of resiliency, these various technologies have simply added some redundancy. For example, multiple processors will be placed on the same IC, such that if a defect causes one processor to fail, a redundant processor is available to take over. In these circumstances, however, either the redundant processor was previously completely idle and unused, or its prior functioning has been superseded and completely lost. In either event, this resiliency is at the expense of approximately twice the IC area and significantly increased manufacturing costs. In addition, such basic redundancy efforts do not account for defects which may occur within all redundant components, as even small defects may cause such components to fail.
As a consequence, a need remains for an integrated circuit architecture which is significantly resilient and robust despite fabrication or usage defects which can affect any components, without the expense of otherwise unused redundancy. Such an IC should provide for ongoing adaptation, such that when a defect arises, functionality may be transferred to an unaffected region in real-time or near-real time. Such technology should provide for configuration (programming or other software) for the IC which allows such transferable functionality, without requiring the entire program to be transferred to a completely redundant processor. In addition, such an IC should provide for a graceful degradation with increasing defects or problems, rather than a catastrophic failure.
USPTO Backgrounds
USPTO Backgrounds