The present invention relates to a modular multiprocessor system of advanced multiple-hierarchical-level architecture, consisting of a number of elementary processing units varying (from a few to a few thousand) according to the application involved, and each cooperating with the others in high-efficiency manner, with common bus connections between the various processors and the memory.
A need is generally acknowledged for combining high computing power with the ability to handle large streams of in-coming and out-going data, particularly in applications involving complex real-time processing (e.g. image processing, pattern and voice recognition, artificial intelligence and scientific computation in general). The formation of high-computing-power multiprocessor systems poses various problems, including task division, processor communication, process cooperation and theoretical-versus-practical application feasibility, mainly due to conflicting access to common resources (communication lines and memories) due to simultaneous operation of a large number of processors. Known proposed solutions (many no more than theoretical) involve extremely high-cost systems (processor arrays and matrix-connected memories) which, in addition to being difficult to control, are unacceptable in terms of performance-cost ratios. Furthermore, when exchanging messages between various sections at a fairly high data rate, known systems have as yet failed to solve the problem of fully independent, transparent operation of communicating multiprocessor sections.
USPTO Backgrounds
USPTO Backgrounds