1. Field of the Invention
The present invention relates to a MOS (Metal-Oxide Semiconductor) type, thin-film transistor and a semiconductor device, active matrix board and liquid-crystal display device, into which the thin-film transistor is implemented.
2. Related Background Art
In the manufacturing process of the thin-film transistor (TFT), two types of processes are mainly available for isolating one element from another: mesa and LOCOS (localized oxidation of silicon) processes. In the mesa isolation process, a semiconductor layer is formed entirely on an insulating substrate and unwanted regions of the semiconductor layer are then removed by etching or other techniques. In the LOCOS process, isolation is assured by selectively oxidizing the semiconductor layer. FIGS. 7A and 7B show a prior art thin-film transistor that is manufactured using the mesa isolation process. FIG. 7A is a plan view of the thin-film transistor and FIG. 7B is a cross-sectional view taken along the line 7B--7B in FIG. 7A. Shown in the figures are an insulating substrate 1, a semiconductor region 2, a gate insulating layer 3, a gate electrode 4, a source region 5, and a drain region 6.
The prior art thin-film transistor has the following disadvantage.
In the prior art thin-film transistor, because of the effect of the geometry, a lower threshold value results in regions 76 where the side wall portions (peripheral portions) of the semiconductor region 2 are close to the gate electrode 4 via the gate insulating layer 3, compared to the remaining plane region on which the gate insulating layer 3 and the gate electrode 4 are laminated in plane. The side wall portions of the semiconductor region 2 is subject to the following phenomena: a leak current takes place because of the effect of an interface region that is generated in the isolation process; and the threshold value drops because an impurity concentration is varied due to the effect of segregated areas of impurities and the like. Although FIGS. 7A and 7B show the example of the mesa device, the same problems are encountered in the LOCOS isolation process.
The transistor structure shown in FIGS. 8A and 8B has been proposed to prevent leak currents in the thin-film transistor substrate (U.S. Pat. No. 4,809,056). In FIGS. 8A and 8B, those portions equivalent to those described with reference to FIGS. 7A and 7B are designated with the same reference numerals. In this transistor as shown, the width W.sub.1 of the source region 5 and the drain region 6, both being heavily doped n-type regions, is set be narrower than the width W.sub.2 of the semiconductor region 2. Designated 81 is a heavily doped p-type region which is provided to keep fixed the potential of the well. The region 81 is more heavily doped than the well and is wired to keep fixed the well potential.
In FIGS. 8A and 8B, although current leakage is less likely to take place by keeping fixed the potential of the well, a leakage path 82 still remains. It is therefore difficult to manufacture at a high yield a semiconductor device which is made up of a large number of transistors. Forming a contact to fix the well potential lowers substantially the level of integration of the semiconductor device.
When the thin-film transistor is applied in the field of the LCD device, as a switching element, current leakage in the thin-film transistor adversely affects the display screen of the LCD device.
FIG. 5 is a schematic diagram showing the circuit of a typical active matrix LCD device. The LCD device is driven by a horizontal shift register 51 and a vertical shift register 52. Fed to the horizontal shift register 51 are a clock pulse 53, a start pulse 54, and a video signal 55. For color display, color video signals may be separately supplied.
The horizontal shift register 51 operates to write a signal on a signal line 56 on the display to drive pixels. A clock pulse 57 and a start pulse 58 are supplied to the vertical shift register 52, which in turn feeds a voltage to gate lines 59 to sequentially turn on the transistors. The signal written on the signal lines is fed to the liquid crystal 61 of each pixel via each pixel transistor 60.
Storage capacitors, though not shown in FIG. 5, may be formed in parallel with the liquid crystals 61 to prevent voltage variations in the pixels arising from current leaks in the pixel transistors and liquid crystals and voltage fluctuations. An attempt to resolve the degradation of image quality arising from the leaks in the transistors by increasing storage capacitance, however, decreases the aperture ratio of the device, and prolongs writing time thereby making it difficult to drive fast the device. This problem is expected to be even more serious in the design of a large-scale or high-resolution display screen panel. In view of the above, it is important to control current leaks in the pixel transistors even with the storage capacitors incorporated.
It is also important to control current leaks in the transistors that constitute the horizontal and vertical shift registers, as the driving circuits. The shift register transfers its input signal to a succeeding stage, one stage by one stage, in synchronism with the clock pulse. The input signal must be held at each stage until a next clock comes in. If current leaks take place in the reset switch that resets the voltage at each stage, the voltage varies to its reset value with time. This leads to the circuit failure in which the function of shift register stops, with the input signal unable to transfer from one stage to the next. Current leaks in the transistors in the peripheral circuits thus should be controlled.
USPTO Backgrounds
USPTO Backgrounds