Technical Field
The present invention relates to extra gate (EG) device integration into nanosheet fin complementary metal oxide semiconductor (CMOS) devices, and more particularly to devices and methods for making the same.
Description of the Related Art
In nanometer scale devices, gate structures are often disposed between fin structures or other conducting structures, such as nanosheets. In many instances, the conducting or semiconducting structures are formed closer together due to scaling to smaller node technology sizes. This can be a limiting factor in the reduction of the device size scaling.
While finFETs and/or nanosheets can benefit from tight device-device spacing, these dimensions may limit scaling of these devices. Further, devices requiring thicker dielectric for higher voltage operation are even more severely limited in the allowable dimensions. Higher voltage devices for input/output circuits require thicker gate dielectrics as compared to standard gate devices, which have a lower voltage and may be employed, e.g., in logic devices. However, spacing between sheets needs to be small to realize capacitance benefits.
The increased gate dielectric thickness needed for high voltage devices is thicker than the optimal space between sheets. Thus, there is a need for a new device structure and method to build the structure to enable the integration of high voltage or extra gate devices with standard nanosheet devices.
USPTO Backgrounds
USPTO Backgrounds