In a field effect transistor (xe2x80x9cFETxe2x80x9d), a capacitance is associated with a gate dielectric layer, which insulates a gate electrode from a channel disposed within a semiconductor substrate. As semiconductor devices continue to be scaled down to reduce power consumption, the demand for higher input FET capacitances has increased. The input capacitance of a FET may be increased by either reducing the thickness of the gate dielectric layer or increasing its dielectric constant.
Gate dielectric layers have historically been realized by bulk silicon dioxide, SiO2. To date, industry has been reducing the thickness of bulk silicon dioxide-based gate dielectric layers to increase input FET capacitances. However, at thicknesses of less than about 15 xc3x85, bulk silicon dioxide becomes exceedingly susceptible to leakage currents tunneling through the gate dielectric layer. Thus, the leakage current problem is now becoming a practical concern.
To overcome this leakage current problem, industry has begun to explore various alternatives materials. These alternative materials have a dielectric constant greater than that of bulk silicon dioxide. As input FET capacitance is directly proportional to the dielectric constant of the gate dielectric layer and inversely proportional to the gate dielectric layer""s thickness, it is believed that one of these alternative materials may enable the formation of a gate dielectric layer of a sufficient thickness to ameliorate the leakage current problem, while also increasing the input FET capacitance. Typical materials being investigated include metal-silicon-oxynitride and metal silicate, for example.
The use of such alternative materials as gate dielectric layers gives rise to other problems, however. The interface between the alternative materials under consideration and the underlying silicon substrate is of a poorer quality than the interface between bulk silicon dioxide and the silicon substrate. This poorer interface quality, attributable to several factors including an increased number of defects (e.g., dangling bonds) at the silicon interface, as well as the numbers of charges to become trapped by these defects. The trapped charges degrade device performance, reduce the reliability of the gate dielectric layer, and, therefore, reduce the FETs"" so-called xe2x80x9cmean time between failure.xe2x80x9d
In accordance with our invention, we have recognized that the search for gate dielectric materials other than silicon dioxide is somewhat misplaced. Our invention takes advantage of the silicon dioxide/silicon interface study by two of us, as reported in xe2x80x9cThe Electronic Structure at the Atomic Scale Of Ultrathin Gate Oxides,xe2x80x9d Nature, Vol. 399, June 1999, which theorizes that a layer of silicon oxide (SiOX less than 2) of a sufficient thickness may exhibit a dielectric constant greater than that of bulk silicon dioxide (i.e., about 3.9). In particular, we have now recognized that at least one layer of silicon oxide (SiOXxe2x89xa62), in contrast with bulk silicon dioxide (SiO2), may be advantageously employed as a gate dielectric layer. It appears to us now that a layer of silicon oxide at thickness of about 5 xc3x85 or less exhibits a dielectric constant greater than about 3.9. More particularly, a layer of silicon oxide apparently exhibits a dielectric constant of about 12 at thickness of about 3 xc3x85. Consequently, it appears that a gate dielectric layer formed from a layer of silicon oxide, SiOXxe2x89xa62, will increase the input FET capacitance, while also providing a desirable interface with a silicon substrate. To further ameliorate leakage current problemsxe2x80x94albeit with a somewhat reduced input capacitancexe2x80x94the gate dielectric layer may also comprise a second layer of silicon oxide, SiOXxe2x89xa62, formed upon the first layer of silicon oxide.
We have also recognized that a gate dielectric layer formed from one or two layers of silicon oxide, SiOXxe2x89xa62, each having a thickness of about 5 xc3x85 or less, may, however, still be insufficient to withstand damaging leakage current. Consequently, we have also invented a composite gate dielectric layer having a complementary dielectric layer formed upon a layer of silicon oxide, SiOXxe2x89xa62, in accordance with our co-pending, commonly assigned, U.S. Patent application, entitled xe2x80x9cA COMPOSITE GATE DIELECTRIC LAYER,xe2x80x9d Ser. No. 09/773,442, filed concurrently with the present application. The complementary dielectric layer is of a sufficient thickness to substantially inhibit the flow of leakage current through the gate dielectric layer.
The addition of the complementary dielectric layer will likely reduce the input FET capacitance. As such, the complementary dielectric layer has a dielectric constant greater than that of the layer of silicon oxide. For example, the complementary dielectric layer may be formed from at least one of aluminate, silicate, ZrO2, HfO2, TiO2, Gd2O3, Y2O3, Si3N4, Ta2O5 and Al2O3. Nonetheless, by judiciously choosing an alternative material for the complementary dielectric layer, and an appropriate thickness, a gate dielectric layer may be provided which exhibits an advantageous combination of properties (i.e., increased capacitance and reduced leakage current, for example) not achieved by the prior art approaches of fabricating a gate dielectric layer.
USPTO Backgrounds
USPTO Backgrounds