A conventional power semiconductor device generally includes an active portion including a plurality of transistors that are electrically connected in parallel and an edge termination portion surrounding the active portion. The edge termination portion contributes to the removal of undesired leakage current or accumulated electrostatic charges in the active portion.
The transistors of the active portion are formed with a plurality of alternately arranged n-type and p-type semiconductor pillars. The edge termination portion typically includes an n-type semiconductor layer and a p-type semiconductor layer to form a junction. When a depletion area of the junction is increased by decreasing an n-type doping concentration of the n-type semiconductor layer and a p-type doping concentration of the p-type semiconductor layer, an accordingly decreased electric field intensity of the junction will lead to uneven electric field lines, and thus the power semiconductor device has a relatively low breakdown voltage. When the electric field intensity of the junction is increased by increasing the n-type doping concentration of the n-type semiconductor layer and the p-type doping concentration of the p-type semiconductor layer, the breakdown voltage of the power semiconductor device will still be low because of the decreased depletion area of the junction.
Besides, for forming the plurality of alternately arranged n-type and p-type semiconductor pillars of the active portion, a thermal budget of a thermal process for forming the p-type semiconductor pillars that can be connected among the n-type semiconductor pillars of the conventional power semiconductor device, is relatively large.
USPTO Backgrounds
USPTO Backgrounds