1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more specifically to a method of fabricating an n-MOSFET (metal-oxide-semiconductor field-effect-transistor) which features an effective suppression of reverse short-channel effects.
2. Description of the Related Art
As is known in the art, one of the most important subjects for MOS devices is a short-channel effect. A threshold voltage is determined by the space charge in a depletion layer formed under a gate electrode. However, in a short channel MOSFET, the charge is reduced because of a charge sharing with the drain field. For this reason, the threshold voltage of a short channel MOSFET is undesirably reduced.
In addition to the above mentioned short-channel effect, as the MOSFET channel length becomes smaller, another undesirable effect which is reverse to the short-channel effect, called a reverse short-channel effect. That is, as the channel length is reduced, the threshold level increases. This reverse short-channel effect will be described later.
Before turning to the present invention, a conventional method of fabricating an n-MOSFET is briefly described with reference to FIGS. 1A-1E, 2A-2B, 3A-F, and 4A-4E.
Referring to FIGS. 1A-1E, processes of fabricating a MOSFET are shown.
As shown in FIG. 1A, a plurality of element isolating regions 61 are formed at predetermined portions of a p-type semiconductor substrate 60. Thereafter, a suitable resist 62 covers a region to which an n-MOSFET is to be formed. Following this, an n-type impurity is ion implanted to the region thereby to form an n-well 64. At the same time, n-type impurities are also ion implanted to the same region to adjust a threshold voltage of. p-MOSFET.
Further, as shown in FIG. 1B, a p-MOSFET forming region is masked using a resist 65, after which a p-type impurity is ion implanted to the region in order to form a p-well 67. At the same time, the p-type impurity is also ion implanted to the p-MOSFET forming region to adjust a threshold voltage of the n-MOSFET.
Subsequently, as shown in FIG. 1C, a gate oxide 68 and a polycrystalline silicon 69 are deposited in this order on the p-type substrate 60, after which gate electrodes 70 are formed using photolithography and etching techniques.
Then, as shown in FIG. 1D, after the n-well 64 is masked with a resist 71, an n-type impurity is ion implanted to the p-type well 67 thereby to form a n-type source-drain region 73. On the contrary, as shown in FIG. 1E, after the p-well 67 is masked with a resist 74, a p-type impurity is ion implanted to the n-type well 64 thereby to form a p-type source-drain region 76. Following this, after the resist 74 is removed, the substrate is annealed in an atmosphere of nitrogen for activating the source-drain regions 73 and 76. The annealing is to repair lattice damage and put dopant atoms on substitutional sites where they will be electrically active.
However, in the processes shown in FIGS. 1A-1E, while the source-drain regions 73 and 76 are subject to heat treatments (viz, annealing) for being activated, point defects in interstitial sites in the source and drain regions are liable to combine with boron ions and diffused in an accelerated manner along the direction of channel. Thus, as the channel length becomes shorter, the concentration of boron immediately below the channel becomes higher. As a result, threshold voltages of MOSFETs become higher. This phenomenon is called a reverse "short-channel" effect.
On the contrary, with MOSFETs, as the channel length is reduced, the depletion layer widths of the source and drain junction become comparable to the channel length, whereby the threshold voltage of the MOS device is lowered (short-channel effect).
In the case where the above mentioned two effects occur at the same time, it is extremely difficult to control the threshold voltage. Therefore, it is highly desirable to effectively suppress the anti-short-channel effect.
One known approach to suppressing the reverse short-channel effect is to implement ion implantation for forming the source-drain regions, which follows the annealing for activation of the source-drain regions. Subsequently, the ion implantation for adjusting the threshold voltage is carried out. Such a known technique is described with reference to FIGS. 2A and 2B.
As shown in FIG. 2A, a gate oxide layer 81 and a gate polysilicon electrode 82 are formed onto a p-type substrate 80 using known techniques. Subsequently, an n-type impurity such as As.sup.30 is implanted into the substrate 80 thereby to form a source-drain region 84. Thereafter, the substrate 80 undergoes annealing at 1000.degree. C. for 10 seconds. Following this, as shown in FIG. 2B, an p-type impurity such as B.sup.30 is implanted, via the gate polysilicon electrode 82 and the gate oxide layer 81, into the substrate 80 thereby to adjust a threshold voltage.
With the conventional technique shown in FIGS. 2A and 2B, the ion implantation for adjusting the threshold voltage is implemented after annealing the source-drain region 84 and thus, the reverse short-channel effect is able to be suppressed. However, in order to adjust the threshold voltage, the dopant is implanted through the gate oxide 81 into the substrate. Therefore, this prior technique suffers from the problem that the reliability of the gate oxide 81 is undesirably degraded.
In order to overcome the difficulty inherent in the second prior technique, it is necessary to form the gate oxide layer after the processes of the annealing and the ion implantation for adjusting the threshold voltage. Such a known technique, disclosed in Japanese Laid-open patent application No. 4123439. This third prior art however suffers from the problem in that when an oxide is formed on source and drain regions, the substrate is exposed to aluminum. Therefore, the aluminum forms an energy level which deteriorates the characteristics of the device. Further, an SiO.sub.2 film of this prior art is grown in a liquid phase and thus the quality of the film is degraded. As a result, in order to solve the above mentioned problems, it is necessary to use using a CVD technique for forming an oxide film on a source and drain region. A prior method using the CVD technique is disclosed in Japanese Laid-open Patent Application No. 4123439. However, this prior art is encountered the difficulty of a large number of fabrication processes.
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