Recent semiconductor devices have not only been scaled up and speeded up, but also been systematized by incorporating many functions. In order to scale up and speed up semiconductor devices, transistors have been made finer, and operating speeds have been improved while power source voltages have been reduced. Various types of function blocks including CPUs and various types of memory devices are combined with each other for systematization. Those memory devices jointly mounted on system LSIs are similarly required to operate at a high speed and a low power source voltage. For example, a static random access memory (hereinafter abbreviated as an SRAM), which is jointly mounted for applications of a cache memory and the like, is similarly required to operate at a high speed and a low power source voltage.
A conventional SRAM will be described with reference to FIGS. 1 to 4. FIG. 1 shows a conventional SRAM memory cell (hereinafter referred to as an SRAM cell) formed by six transistors. When a word line WL has a low potential, data can be held stably by forming a loop with two CMOS (Complementary Metal Oxide Semiconductor) inverters. Specifically, one of the CMOS inverters uses a storage node V1 as an input and outputs inverse data of data stored in the storage node V1 to a storage node V2. The other of the CMOS inverters uses the storage node V2 as an input and outputs inverse data of data stored in the storage node V2 to the storage node V1.
When the word line WL is accessed and brought into a high potential, access transistors N3 and N4 are brought into conduction so as to read data stored in the storage nodes V1 and V2 into bit lines BLT and BLN, thereby performing a reading operation of the memory. Conversely, data from the bit lines BLT and BLN are written into the storage nodes V1 and V2, thereby performing a writing operation of the memory.
However, in a conventional SRAM cell, a problem of corruption of stored data also arises when a reading operation is performed at a low power source voltage. The corruption of stored data in the reading operation will be described below.
When the word line WL is brought into a high level, the access transistors N3 and N4 are brought into conduction. Accordingly, the storage nodes V1 and V2 are connected to the bit lines BLT and BLN, respectively, and are to be changed into a bit line level. For example, when a low level is stored on the storage node V1, the potential of the storage node V1 is slightly increased by the bit line BLT. However, because a drive transistor N1 is in an on state, it lowers the potential of the storage node V1. If the increased potential of the storage node V1 exceeds a threshold level of a drive transistor N2 on an opposite side, the drive transistor N2 is turned on, thereby lowering a level of the storage node V2. Thus, an on-state current of the drive transistor N1 is reduced so that the potential of the storage node V1 is further increased. As a result, corruption of the stored data is caused.
Generally, a static noise margin (hereinafter abbreviated as an SNM) is used as an index for measuring the stability of holding accessed data in an SRAM cell.
As shown in FIG. 2, an SRAM cell is separated into two inverters, and DC (direct current) characteristics are calculated for each inverter. When those two DC characteristics are superimposed so that a DC characteristic output of one of the inverters serves as a DC characteristic input of the other inverter, a butterfly curve is drawn. An SNM is defined as one side of a maximum square inscribed in this butterfly curve. When an SNM exceeds 0 mV, a normal reading operation is performed. When an SNM is 0 mV or less, stored data are overwritten with inverse data and thus corrupted in a reading operation.
Predictions for the future of the SNM have been made in A. J. Bhavnagarwala's “The impact of intrinsic device fluctuations on CMOS SRAM cell stability”, IEEE Journal of Solid State Circuit, Vol. 36, No. 4, April 2001 (FIGS. 5 and 10) (Non-patent Document 1). Specifically, when channel lengths of transistors used are made shorter so that they are shifted from 250 nm to 50 nm as shown in FIG. 3, an average of the SNMs is decreased, and a deviation of the SNMs is simultaneously increased. Accordingly, the worst value of the SNMs is considerably lowered. The worst value of the SNMs becomes below “0” in the illustrated example of 50 nm. Accordingly, stored data are corrupted when the word line WL is brought into a high potential in a reading operation.
Meanwhile, H. Sakakibara's “A 750 MHz 144 Mb cache DRAM LSI with speed scalable design and programmable at speed function-array BIST”, IEEE International Solid State Circuit Conference, 2003 (FIG. 1) (Non-patent Document 2) discloses an SRAM cell formed by eight transistors as shown in FIG. 4 in which a read-only port is added to an SRAM cell formed by six transistors. With this configuration, corruption of stored data is not caused in a reading operation. However, this SRAM cell has problems in that the number of the transistors becomes eight and that a cell area is increased because of an increased number of signal lines.
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USPTO Backgrounds