Technical Field
The present invention relates to integrated circuit, and more particularly to an integrated circuit chip and its impedance calibration method.
Related Art
In designing an integrated circuit chip, the output impedance of the chip is required to be in match with specific impedance such as that of receiving circuit or transmission line of cable so as to correctly transmit signals by preventing reflection of output signal and loss thereof. In addition, rise time and fall time (slew time) of waveform of the output signal shall be adjusted to fall into appropriate range. If it is too short, noise may be generated. If it is too long, the waveform may be deteriorated.
In order to solve the above problems, functions for adjusting and controlling terminating resistance of an interface circuit have been provided within some prior art internal integrated circuit chips. For example, as far as an ODT (on-die termination) circuit configured for DDR2 standard memory is concerned, it has terminal resistance value that can be adjusted to 75 ohms or 150 ohms. In other words, multiple PMOS tubes and NMOS tubes are connected in parallel in the ODT circuit, thus forming the terminal resistance. In fact, the number of the transistors connected in parallel is adjusted by supplying control signal(s) to gates of the transistors so that the value of the transistor resistance in sum is controlled to be equal to the resistance value of external standard resistance.
FIG. 1 shows a structural schematic view of an impedance calibration circuit in the integrated circuit chip of the prior art. As shown in FIG. 1, when the circuit is conducted impedance calibration, a standard impedance Rref is connected to node A, a comparator 710 compares the voltage value of node A with that of the reference voltage configured to ½ or ⅓ times of supply voltage, and outputs the comparison signal; a control module that is not shown in FIG. 1 outputs an impedance calibration code P-CODE[0 . . . N] according to the comparison signal, so as to turn the multiple parallel PMOS tubes on and off, respectively. When the value of node A is equal to that of the reference voltage, the control module keep outputting the current calibration code P-CODE[0 . . . N], the calibration code P-CODE[0 . . . N] being used as reference calibration code for other interface driver circuit.
The foregoing prior art integrated circuit chips have the following defects: on one hand, it cannot be adapted simultaneously to both single-ended signal output and differential signal output; On the other hand, the configuration of the reference voltage cannot be suitable for wide range of power supply voltage. As shown in FIG. 2, when the supply voltage is in the range of 1.8V˜3.3V, the reference voltage is configured to ½ or ⅓ times of supply voltage according to the impedance calibration circuit of the prior art, resulting in a narrow linear range of output characteristic curve.
USPTO Backgrounds
USPTO Backgrounds