The production of integrated circuits (IC) requires many different skills using knowledge from various disciplines. This process generally starts with the design of an IC chip, including the various circuit elements, their electrical interconnects, and their physical layout across the chip. The IC design typically describes each layer required to fabricate the IC in a FAB using a photolithographic process. There are generally many layers to an IC chip.
The design is analyzed with respect to its physical layout. For example, wire width may be determined and efficient routing and placement of components may occur. Process model may also be used in analyzing the design. This information usually is obtained from a library provided by the manufacturers.
After an integrated circuit is designed, a photomask is created. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. There are different types of masks, including binary chrome-on-glass, attenuated phase-shifting masks (attPSM) and alternating phase-shifting masks (altPSM). Before being used in a photolithography system to replicate the mask image in reduced size onto a wafer when building the IC, the mask is inspected for defects. Defects found in the mask will often be repaired so that they will not be replicated on or introduce harmful distortions to the chips created from that mask.
The demand to meet shrinking feature size is a challenge faced by the IC industry. Resolution Enhancement Techniques (RET) are applied to masks to meet some photolithographic results due to several factors including 1) mask features being smaller than the wavelength of the stepper, 2) object placement, and 3) shapes in combinations with diffraction limited issues. As more RET is required, manufacturing costs and cycle time increase exponentially.
Up until tapeout, a vast amount of information is available, including, for example, the relation of the physical layout to the design schematic or netlist; individual circuit element models and properties; circuit criticalities; and manufacturing assumptions which were used in the IC design. Furthermore, the information is typically in a design hierarchy of fundamental library base cells, or ‘hard IP,’ of redesigned and characterized blocks, or ‘cores.’ Circuit elements at this level may include, for example, transistors, power buses, resistors, capacitors, and interconnects. Logos and manufacturing elements, such as area fill cells, may also be included.
Tapeout is typically the last step in the IC design flow and is the ‘handoff’ mechanism to manufacturing. Typically, tapeout produces a geometries-only design hierarchical data file in GDS-II stream format. However, a wealth of design knowledge is stripped out into this geometry-only format, and therefore is unavailable to any data file derived from it or any design or manufacturing integration process occurring thereafter.
Yield loss during the semiconductor manufacturing process is very problematic. Linking design knowledge to predict real-world manufacturing processes has not been resolved. There are various approaches to identifying lithography critical areas to monitor on the wafer after printing, but no solution has been suggested to correlate the electrical and physical attributes as a basis for enhancing parametric and functional yields.
Traditionally, enlarging the process yield window has been the goal of DFM, while manufacturing Advanced Process Control (APC) aims to keep the manufacturing process in the process yield window. A current approach utilizes RET Process Window Optimization (PWO) using brightfield imaging wafer defect inspection techniques. RET PWO does not account for parametrically sensitive areas but only focuses on functional areas that are deemed difficult to lithographically print on the wafer surface.
Manufacturers, receiving the mask, manufacture and package the ICs on wafers. The current choice of inline metrology/inspection points on wafer is based on in-house knowledge. Traditionally during full volume manufacturing, ten to twenty sites are selected on the wafer to be inspected. Dimensional excursions outside the control limits of these sites are what triggers a manufacturing process adjustment.
As process nodes shrink to sub 65 nm, the driver for yield loss has shifted from random defects to systematic defects. Systematic defects typically account for more than 80% of yield loss; moreover, parametric defects account for more than 50% of yield loss. The current choice of inline metrology/inspection points on the wafer is based on in-house knowledge. Traditionally during full volume manufacturing, ten to twenty sites are selected on the wafer to be inspected. These ten to twenty sites typically are not adjusted wafer to wafer or lot to lot, and are design independent. Wafer fabrication manufacturers use historical inspection data to determine areas that are presumed to be representative structures for wafer yield.
In house knowledge does not account for parametrically sensitive areas but only focuses on functional areas that are deemed difficult to manufacture. Furthermore, any parametric yield loss is only detected at the end of manufacturing during wafer electrical test.
Therefore, there is a need to allow for more cooperation and sharing of information between the designers and manufacturers. Also, there is a need to improve the accuracy of hot spot determination and selection of inline metrology/inspection points.
USPTO Backgrounds
USPTO Backgrounds