1. Technical Field
Embodiments of the present disclosure generally relate to electronic device packages and, more particularly, to electronic device packages including bump buffer spring pads and methods of manufacturing the same.
2. Related Art
Electronic devices employed in electronic systems may include various circuit elements such as active elements and/or passive elements. The circuit elements may be integrated in and/or on a semiconductor substrate, thereby constituting the electronic device (also, referred to as a semiconductor chip or a semiconductor die). The electronic device may be mounted on a printed circuit board (PCB) or a package substrate to produce an electronic device package. The package substrate may include circuit interconnections such as silicon interposers. The electronic device package may be mounted on a main board to constitute the electronic systems, for example, computers, mobile systems or data storage media.
Bumps are widely used in fabrication of the electronic device packages. The bumps may electrically connect the semiconductor chips to the package substrates or may electrically connect the semiconductor chips to each other. For example, the bumps may be employed in flip chip packages to realize diverse stack structures of the semiconductor chips and/or to increase the number of input/output terminals. In the fabrication of the flip chip packages, the bumps may be surrounded by an under fill material to electrically insulate the bumps after the semiconductor chips are electrically connected to the package substrates through the bumps.
As the mobile systems become more widely used and the semiconductor chips become more highly integrated, the electronic device packages such as the flip chip packages have been continuously scaled down. This may lead to reduction of the height or the size of the bumps used in the electronic device packages. As the size of the bumps is reduced, high reliability of the bumps may be more required. That is, if the size of the bumps is reduced, a physical stress and/or an impact may be more readily generated when the bumps are combined with landing pads of the package substrates or the semiconductor chips using an adhesion layer. The physical stress and/or the impact may remain in the package substrates or the semiconductor chips and may cause process failures such as cracks or delamination of metal pads (or metal interconnection lines). In addition, the physical stress and/or the impact may cause crystalline defects such as dislocations in active regions of semiconductor substrates acting as base material layers of the semiconductor chips. Accordingly, theses process failures may degrade the reliability of the electronic device packages.
USPTO Backgrounds
USPTO Backgrounds