1. Field of the Invention
The embodiments of the invention generally relate to planar field effect transistors (FETs), and, more particularly, to a planar field effect transistor structure and method of forming the structure with epitaxially deposited source/drain regions.
2. Description of the Related Art
Charge carrier mobility affects current flowing through the channel region of field effect transistors. That is, in n-type field effect transistors (NFETS) current flow is proportional to the mobility of electrons in the channel region, whereas in p-type field effect transistors (PFETs) current flow is proportional to the mobility of holes in that channel region. Stress can be imposed upon on the channel region in order to adjust carrier mobility and, thereby, adjust current flow. Specifically, compressive stress on the channel region of a PFET can enhance hole mobility, whereas tensile stress on the channel region of an NFET can enhance electron mobility. Various stress engineering techniques are known for imparting the desired stress on NFET and PFET channel regions.
For example, as discussed in U.S. Pat. No. 6,885,084 of Murthy et al. issued on Apr. 26, 2005 and incorporated herein by reference, a compressive stress (i.e., a uni-axial compressive strain parallel to the direction of the current) can be created in the channel region of a PFET by forming the source/drain regions with an epitaxially deposited alloy of silicon and germanium. Unfortunately, when formed according to the technique described by Murphy et al., the resulting PFET structure is prone to junction leakage problems. Therefore, there is a need in the art for an improved transistor structure and method of forming the structure that incorporates epitaxially deposited source/drain semiconductor films.
USPTO Backgrounds
USPTO Backgrounds