1. Field of the Invention
This invention relates generally to fabrication of planar surfaces for integrated circuits and, more particularly, to a high density interconnect (HDI) fixture and process for fabricating HDI circuits with planar surfaces.
2. Description of the Related Art
Conventional high density interconnect (HDI) processes often use cavities formed into a substrate base for the placement of chips so that the top surfaces of the chips are essentially planar with the surface of the substrate. The substrate is generally a ceramic or a composite structure. The conventional HDI technique for fabricating cavities in the substrate is to mechanically machine or mill out the cavity material with a computer-controlled diamond tooled bit. This time consuming process does not always provide the desired chip cavity depth and can result in cracks which render the substrate unusable, and chips placed with this process often are displaced during further processing because there are non-uniform surface tension forces at the chip-to-die attach adhesive inter-face.
In conventional HDI techniques, an adhesive-coated polymer film overlay covers a plurality of integrated circuit chips in chip wells on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips. Methods for performing a HDI process using overlays are described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. Additionally, it is desirable to provide via openings or apertures in the polymer film overlay so as to be able to provide electrical connection between various parts of a chip or between several chips. Eichelberger et al., U.S. Pat. No. 4,894,115, issued Jan. 16, 1990, describes embodiments for providing such apertures.
Fillion et al., "Embedded Substrate For Integrated Circuit Modules," Ser. No. 08/087,434, filed Jul. 9, 1993, which is a continuation-in-part of application Ser. No. 08/014,481, filed Feb. 8, 1993, and is herein incorporated by reference, describes a method of fabricating an HDI substrate by molding plastic around chips placed on a film, thus eliminating the milling process and providing a planar surface without moats between chips and the substrate. Briefly, the technique includes applying an insulative base sheet over a base. At least one chip having contact pads is placed face down on the base sheet. A mold form is positioned around a desired perimeter and surrounds at least one chip. Substrate molding material is added and then hardened within the mold form. Then the mold form and base are removed, the substrate is inverted, and the chips are interconnected. Removal of the mold form can be facilitated if a release agent, such as Teflon polytetrafluoroethylene or vegetable oil, has been applied to the mold form prior to the addition of the substrate molding material. It can be difficult to obtain a planar base sheet surface because, as the molding material cures and/or cools, the base sheet can be lifted off the base and wrinkled.
Flat, void-free laminations of different types of materials such as epoxy and polyimides are thus not easy to achieve when the materials must withstand the environmental stresses of electronic fabrication. Furthermore, in conventional patterning techniques of multi-layer modules, solvent crazing of polymer films or poor adhesion of subsequent layers occurs due to dissolved solvents or residues of mold release agents present in the preceding layers.
USPTO Backgrounds
USPTO Backgrounds