1. Field of the Invention
The present invention relates to a Phase-Locked Loop (PLL) circuit.
2. Description of the Related Art
A PLL is a fundamental component of many electronic systems (for example, in telecommunication applications). The PLL consists of a negative feedback circuit that allows multiplication of the frequency of a reference signal by a selected conversion factor; this results in the generation of a tunable and stable output signal with the desired frequency.
Typically, the PLL includes a frequency divider that scales the frequency of the output signal by the conversion factor. The resulting signal is fed back to a phase comparator, which detects a phase difference between the feedback signal and the reference signal; the phase comparator outputs a control current indicative of the phase difference. A loop-filter integrates the control current into a corresponding voltage, which controls the frequency of the output signal accordingly. In a lock condition, the frequency of the feedback signal matches the frequency of the reference signal; therefore, the frequency of the output signal will be equal to the reference frequency multiplied by the conversion factor.
A problem of the structure described above is that different spurious signals (or spurs) can be generated during operation of the PLL. This problem is particularly acute in PLLs with a fractional architecture, wherein a dividing ratio of the frequency divider changes dynamically in the lock condition (so as to provide an average conversion factor equal to a fractional number); the fractional PLL allows finer resolution of the output frequency, and it exhibits improved performance in terms of both settling time and phase noise. However, the change in the dividing ratio causes fractional spurs at low-frequency offsets from a carrier that are multiple of the periodicity in the division pattern.
In order to remove the spurs generated during operation of the PLL, different techniques for conditioning the control current have been proposed in the last years.
For example, a solution known in the art for reducing the effects of the non-linearity of the phase comparator consists of sinking a direct current (DC) from an output node of the phase comparator. In this way, the PLL locks when the control current that is injected into the loop-filter during every cycle (consisting of a series of width-modulated pulses, indicative of the phase difference between the feedback signal and the reference signal) matches the current that is sunk, so that the average current provided to the loop-filter is zero. As a consequence, in the lock condition the reference signal and the feedback signal have the same frequency, but a pre-defined phase difference (thereby forcing the phase comparator to work in a part of its I/O characteristic that is more linear).
Another conditioning technique is routinely used in fractional PLLs for compensating a phase error, which is caused by the fact that in the lock condition the feedback signal and the reference signal are not instantaneously at the same frequency. For this purpose, a compensation current (consisting of a series of amplitude-modulated pulses) is sunk from the output node of the phase comparator. Each pulse of the compensation current has the same area as the corresponding pulse of the control current, so that in the lock condition the average current provided to the loop-filter during every cycle is zero.
A drawback of the solutions described above is that they increase the level of reference spurs at an offset around the carrier that is equal to the reference frequency. This is due to the fact that, although zero on the average, the current injected into the loop filter in the lock condition has an instantaneous value that is different from zero. As a consequence, the control voltage output by the loop filter exhibits a ripple at the operative frequency of the phase comparator.
USPTO Backgrounds
USPTO Backgrounds