1. Field of the Invention
This invention relates generally to a semiconductor device, and more particularly to a flash memory cell array and manufacturing method thereof.
2. Background of the Related Art
Flash memory is a non-volatile solid state memory that maintains data even after all power sources have been disconnected. Flash memory has been widely used in personal computers and other electronic equipment because of its programmable features allowing writing, erasing and reading data a number of times.
A conventional flash memory cell is a transistor comprising a control gate, a doped polysilicon floating gate and an oxide layer separating these two gates from each other. A tunnel oxide layer separates the floating gate and the substrate. Because the floating gate is insulated by oxide, any negative charge on a floating gate does not leak, even if the power is off.
To write/erase the data in the cell, a bias voltage is applied to the drain in order to push electrons into the floating gate or pull electrons out of the floating gate by Fowler-Nordhem tunneling. To read the data in the cell, a working voltage is applied to the control gate to determine whether the channel is on or off. The value of the data (“0” or “1”) depends on the amounts of electrons trapped in the floating gate, which affect the status of the channel.
During data erase operation, however, it is very difficult to control the amount of the electrons flowing out of the floating gate and may make the floating gate positively charged due to over-pulling the trapped electrons. This effect is so call “over-erase”. If the over-erase effect is too severe, the channel will be always on, even without applying the working voltage to the control gate. It causes to mis-read the value in the cell.
To prevent the over-erase effect, some flash memory devices have used split gate design. It has an additional “select gate” on the side wall of the control gate and the floating gate and uses an oxide layer separating the select gate from the control gate, the floating gate, and the substrate. Hence, even if the over-erase effect occurred, the channel below the erase gate would still be off to avoid mis-reading the data. However, the size of the split-gate flash memory cell becomes larger than that of conventional flash memory cell because it requires a larger area for the split gate structure. This would cause the concern in high integration density issue.
One may use NAND gate array, instead of NOR gate array, for split gate flash memory in order to increase its integration density because NAND gate array allows serial connection of the memory cells. However, the write/read operations are much more complicated for NAND gate array. Furthermore, the current is smaller due to the serial connection, which seriously affects the performance of the memory cells because of a longer write/erase cycles.
USPTO Backgrounds
USPTO Backgrounds