1. Field of the Invention
The present invention relates to package on package (PoP) structures, and more particularly, to a PoP structure and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of portable electronic products, various package types such as PoP structures have been developed to meet high density, high performance and miniaturization requirements.
FIG. 1 is a schematic cross-sectional view of a conventional PoP structure 1. Referring to FIG. 1, the PoP structure 1 has a first package structure 1a and a second package structure 1b stacked on the first package structure 1a. 
The first package structure 1a has a first substrate 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a. The first surface 11a of the first substrate 11 has a plurality of conductive pads 111 and the second surface 11b of the first substrate 11 has a plurality of conductive pads 112. A first electronic element 10 is flip-chip bonded to the first substrate 11. A first encapsulant 13 is formed on the first substrate 11 for encapsulating the first electronic element 10 and has a plurality of openings 130 for exposing the conductive pads 111. A solder bump 114 is formed on each of the conductive pads 111 in the openings 130 of the first encapsulant 13. A plurality of solder balls 14 are formed on the conductive pads 112 of the second surface 11b of the first substrate 11.
The second package structure 1b has a second substrate 12, a plurality of second electronic elements 15a, 15b bonded to the second substrate 12 through wire bonding, and a second encapsulant 16 formed on the second substrate 12 for encapsulating the second electronic elements 15a, 15b. The second substrate 12 is stacked on the solder bumps 114 of the first package structure 1a so as to be electrically connected to the conductive pads 111 of the first substrate 11 through the solder bumps 114.
Therefore, in the PoP structure 1, the solder bumps 114 are used for mechanical support and electrical connection between the first substrate 11 and the second substrate 12. However, as I/O count increases, if the package size does not change, the pitch between the solder bumps 114 must be reduced. As such, solder bridging easily occurs between the solder bumps 114, thereby reducing the product yield and reliability and hindering fabrication of fine-pitch products.
Further, after a reflow process, the solder bumps 114 can have large differences in volume and height from one another. That is, size variation of the solder bumps 114 is not easy to control. As such, defects may occur to solder joints and result in a poor electrical connection quality. For example, during the reflow process, the solder bumps 114 easily collapse and deform under pressure of the second substrate 12. Therefore, solder bridging easily occurs between adjacent solder bumps 114, thereby reducing the electrical connection quality. Furthermore, the solder bumps 114 arranged in a grid array may have a poor coplanarity. Consequently, uneven stresses can be applied on the solder joints, thus easily leading to a tilted bonding between the two package structures 1a, 1b and even causing an offset of the solder joints.
Moreover, since only the solder bumps 114 provide mechanical support between the first and second package structures 1a, 1b and a large gap d is formed between the first and second package structures 1a, 1b, warpage easily occurs to the first and second substrates 11, 12.
Therefore, how to overcome the above-described drawbacks has become critical.
USPTO Backgrounds
USPTO Backgrounds