1. Field of the Invention
The present invention relates to a method for forming a semiconductor device and more particularly, to a method for forming a semiconductor device including a bit line contact.
2. Background of the Invention
Recently, most electronic appliances include semiconductor devices. Semiconductor devices include electronic elements, such as transistors, resistors, capacitors, and the like. These electronic elements are designed to perform functions of the electronic appliances and are integrated on a semiconductor substrate. For example, electronic appliances, such as computers, digital cameras, and the like, include semiconductor devices, such as memory chips for storage of information, processing chips for control of information, and the like. Memory chips and processing chips include electronic elements integrated on a semiconductor substrate.
There is a need for increasing the integration degree of these types of semiconductor devices in order to satisfy consumer demands for superior performances and lower prices. Such increases in the integration degree of a semiconductor device entails a reduction brought about by the design rule which causes patterns of a semiconductor device to be increasing reduced. Although an entire chip area is increased with respect to the memory capacity, the semiconductor device is becoming super miniaturized and highly integrated. As a result, the area of a cell region where patterns of a semiconductor device are actually formed decreases. Accordingly, since a greater number of patterns should be formed in a more limited cell region in order to achieve a desired memory capacity, there is a need for forming microscopic patterns that have reduced critical dimensions.
Nowadays, various method for forming microscopic patterns have been developed, including, e.g., a method that uses a phase shift mask as a photo mask, a Contrast Enhancement Layer (CEL) method that uses a separate thin film capable of enhancing image contrast when formed on a wafer, a Tri Layer Resist (TLR) method that uses an intermediate layer, such as, e.g., a Spin On Glass (SOG) intermediate layer film, when interposed between two photo-resist films, or a silylation method that selectively implants silicon into upper portions of a photoresist film. All of the above described methods aim principally at decreasing the achievable resolution limit.
Meanwhile, a contact for connecting upper and lower conductive lines to each other can be significantly adversely affected by a design rule, as compared to line and space patterns. In more detail, an increase in the integration degree of a semiconductor device causes a reduction in a size of a contact and an interval between the contact and the neighboring conductive line and consequently, causes an increase in an aspect ratio of the contact, that is, a ratio of a diameter to a depth of the contact. Therefore, a contact forming process is important in forming a highly integrated semiconductor devices. Accordingly, in highly integrated semiconductor devices that have multilayered conductive lines, a contact forming process may require an extremely precise and strict mask alignment, may require entailing a reduction in process margin, or may be difficult in progressing a process without a margin.
In the case where a semiconductor device that is 30 nm thick which has buried gates, to substantially prevent a bridge phenomenon between a previously formed hole type bit line contact and a subsequently formed storage node contact, then the hole type bit line contact should have at least a dimension of less than 30 nm. Although various methods for realizing a hole type bit line contact having a dimension of less than 30 nm, for example, a method of performing a reflow process on a photo-resist pattern, or a method using patterning of a spacer, have been proposed, these conventional methods suffer in that it is difficult to form uniform contacts.
USPTO Backgrounds
USPTO Backgrounds