As is known in this specific technical field, IGBT power devices and MOS devices are widely and specifically applied in fields with high voltage and current, for example in the field of control circuits and power switches.
These power devices are generally expected to provide good performance at high switching speeds. The typical parameters to reduce switching times in these devices are a low gate charge Qg, and thus a lower gate capacitance, and a reduced and uniform gate resistance Rg.
Such good performance is expected even as the sizes of power devices continue to decrease.
IGBT and MOS power devices, being integrated on a semiconductor substrate, comprise a plurality of elementary cells, each having a gate region, interposed to the source and body region.
Elementary cells may be made in two alternative embodiments: one with a planar gate and the other with a trench gate.
In the method for manufacturing a trench-gate power device, and particularly with a trench of the Metal Insulator Semiconductor (MIS) type, for each elementary cell the gate is realized by making a trench, on the semiconductor substrate, whose walls and bottom are covered by a thin oxide layer and then filled in with a polysilicon layer.
These power devices with a trench gate of the MIS type may have several advantages, in particular they may allow the integration scale to be increased, with a subsequent increase in the current density and a JFET resistance drop as well, considerably improving the device conductance.
Nevertheless, power devices with a trench gate of the MIS type may have some drawbacks. In fact, the trench bottom may cause a thickening of the electric field with a subsequent worsening, for the same drift-layer thickness, of the break-down voltage of the device. A solution to this drawback is to make the trench bottom with a “U” shape, which may allow the breakdown voltage to be improved.
Nevertheless, these trench-gate devices may have another drawback if compared with a planar-gate device, for each elementary cell there is an increase in the area being occupied by the gate oxide in correspondence with the trench, involving an increase in parasitic capacitances linked to the gate terminal of the device.
A known solution to solve these drawbacks is described, for example, in U.S. Pat. No. 7,205,607, which is incorporated by reference. As shown in FIG. 1, this solution provides the reduction in the overlapping area between the trench gate oxide and the gate electrode by limiting in particular the gate electrode extension only to trench vertical walls. In this way, a reduction in gate-drain capacitance, and consequently, in gate charge, may be obtained.
Another known solution is described in US Patent Application No. 2007/0063272, which is incorporated by reference, as shown in FIG. 2. This solution provides an oxide thickening in the trench bottom and in the walls below the body region. Moreover, in correspondence with the thick oxide, there is a conductive layer being independent from the gate electrode and electrically insulated therefrom. According to this solution, the thin gate electrode is present only in the trench sidewalls, thus allowing a reduction in the gate-drain capacitances and thus also in the gate charge to be obtained.
A similar solution is also described in U.S. Pat. No. 7,005,351, which is incorporated by reference and which corresponds to a method for manufacturing a transistor configuration comprising at least a trench transistor cell, shown in FIG. 3. This solution too provides a thick oxide in the trench bottom and a thin gate oxide only in the trench sidewalls.
Further known solutions are shown in the following four documents per FIGS. 4-7, respectively, of the present application: U.S. Pat. No. 6,528,355; US Patent Application No. 2003/0235958; US Patent Application No. 2001/0026989; European Patent Application No. EP1742257 all of which are incorporated by reference.
The solutions being indicated in these four documents generally provide a thickening of the gate oxide in the trench bottom with a single conductive layer making the gate electrode. A thin gate oxide is present, on the contrary, in the trench walls, near the body regions, allowing a reduction in the gate-drain capacitances and thus also in the gate charge to be obtained.
Moreover, referring to FIG. 8, the solution being described in the U.S. Pat. No. 7,045,858, which is incorporated by reference, provides the presence of a metal silicide layer on trench walls contacting the polysilicon so as to reduce the gate electrode resistance, thus improving the switching rate.
It is noted that in general in these power devices the signal transmission line or conductive mesh is implemented by means of the same gate electrode.
USPTO Backgrounds
USPTO Backgrounds