A waveform map (ROM) having addressing inputs connected to receive signals developed by a counter and data outputs connected to drive a digital-to-analog converter (DAC or D/A) is shown in the U.S. Pat. No. 4,039,806 of O. Fredriksson and E. Thomas, the U.S. Pat. No. 4,192,007 of D. Becker, the U.S. Pat. No. 4,283,768 of R. Scott, and the U.S. Pat. No. 4,301,415 of D. McFayden. The ROM (22) (waveform map) shown in the O. Fredriksson and E. Thomas patent stores a number of binary words, each of which represents a discrete amplitude or argument of a sinusoid to be generated as a function of time. In FIG. 3 of the O. Fredriksson and E. Thomas patent, a circle is shown to illustrate addressing operations for various phase values. The text of the O. Fredriksson and E. Thomas patent (column 3, lines 11-32) directs "(1)et X(t) represent a continuous sinusoid of frequency f.sub.o. Then, ##EQU1## where f.sub.o is frequency and T is the period. When (1) is expressed discretely, it becomes X(n): ##EQU2## Of course, X(n) is the value of the function throughout the nth interval; in the case of interest each n interval is preferably made one degree long.
Each separate arc of phase circle (16 of FIG. 3) defines a selected sinusoid argument. The argument is generated as a function of discrete time intervals, T/360. However, its exact digital representation, say as set forth in equation (2), is also a function of storage available within the sin wave generator (14 of FIG. 2).
A (phase) accumulator is disclosed in the U.S. Pat. No. 3,689,914 which issued to J. Butler. In FIG. 1 of the J. Butler patent, the (phase) accumulator is shown as a block (16) driven both by a digital generator (12) and a clock (20) and driving a digital-to-analog converter (18) to generate, at the output of the converter, a signal having either a triangular or sawtooth shape.
In FIG. 2 of the J. Butler patent, a four stage (phase) accumulator is shown to include four full adders (32-38) and five J-K flip-flops (40-48). The adders are connected in cascade with the carry output of one adder connected to the carry input of the next adder. One of the two addend inputs of each of the adders is connected to the digital generator; and, the two, complementary, outputs of each of the adders are connected to the J and K inputs, respectively, of the corresponding one of four of the flip-flops. The fifth flip-flop is configured with the J input directly connected to the carry output of the fourth adder and the K input coupled thereto by an inverter (60). The T input of each of the flip-flops is connected to the corresponding one of five outputs of a time patch (58) which is driven by the clock. The output of each of the flip-flops is connected to the other one of the addend inputs of the corresponding adder to provide feedback. It is indicated that at each clock pulse of the clock, the accumulator adds the value of the binary number applied thereto to a number already stored therein and replaces the stored number with the sum (column 2 lines 20-24).
Additionally, the J. Butler (phase) accumulator is shown to include four exclusive OR gates (50-56) (forming a 1's complement circuit). Specifically, one of the two inputs of each of the exclusive OR gates is connected to the output of the corresponding one of the four flip-flops; and, the output of each of the flip-flops is connected to the digital-to-analog converter. The other input of each of the exclusive OR gates is connected to a line which is selectively coupled by a switch (22) either to the output of the fifth flip-flop or to circuit ground to select either the triangular or sawtooth signal shape.
The J. Butler (phase) accumulator (arithmetic synthesizer) is included (as a pair of blocks 16 and 20) in the U.S. Pat. Nos. 4,021,757 and 4,114,110, both of E. Nossen. In FIG. 3 of the U.S. Pat. No. 4,114,110, a frequency register (20) of the arithmetic synthesizer (phase accumulator) is shown as a block being driven both by fine frequency selecting signal(s) and by signal(s) developed by an analog-to-digital converter (19) (block) from an analog signal(s).
A numerically controlled oscillator (NCO) (phase accumulator) is shown in FIG. 1 of the U.S. Pat. No. 4,514,696 of T. Genrich to include a parallel digital adder (12) and a register (14). The adder is shown to have a first set of addend inputs connected to a set of input terminals (10), a second set of addend inputs, and a set of outputs. The register is shown to have a set of inputs connected to the set of outputs of the adder, an input connected to a terminal (16), and a set of outputs connected both to a set of output terminals (18) and to the second set of adder addend inputs.
It is indicated in the T. Genrich patent that the adder and register are each N bits wide. Further, it is indicated (column 3, lines 32-64) that "(o)ne input word to the adder is an N bit word indicative of a desired frequency called FREQ. The register is used to hold the result of the last addition. It is updated at a rate determined by pulses applied to terminal 16. Thus, the NCO is an accumulator that is incremented at a rate determined by the frequency of the clock input and the magnitude of the FREQ digital word. These values are related by the equation, ##EQU3## where: F.sub.OUTPUT =the toggle rate of the most significant output bit at terminals 18,
F.sub.CK =the frequency of the input clock applied to terminal 16, PA1 N=the bit capacity of adder 12, and PA1 FREQ=the numerical value of the input word FREQ, where EQU 0.ltoreq.FREQ.ltoreq.2.sup.N-1. (2)
Therefore, ##EQU4##
In the article by D. Sunderland, R. Strauch, S. Wharfield, H. Peterson, and C. Cole which appeared on pages 497-506 of the August 1984 edition (Volume SC-19, Number 4) of the "IEEE Journal of Solid-State Circuits," there is shown (in FIG. 2) a number of blocks. Shown are a pair of adders driving a pair of registers (to form a phase accumulator) driving a 1's complement circuit driving a pair of ROMs driving another pair of registers driving another adder driving another 1's complement circuit driving still another register.
The reader may also find of interest the U.S. Pat. No. 4,388,597 of R. Bickley and A. Hunt and the U.S. Pat. No. 4,516,084 of A. Crowley.
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