1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for using spacers to constrain epitaxial growth on fins of a finFET device and for providing a cap layer to protect the epitaxial material during removal of the spacers.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fin is vertically spaced apart from and above the substrate with an isolation material positioned between the fin and the substrate. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, an isolation material 130, a gate structure 115, sidewall spacers 120 and a gate cap layer 125. The gate structure 115 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 100. The fins 110 have a three-dimensional configuration: a height, a width, and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition. Forming the additional epi material on the fins 110 in the source/drain regions of the device reduces the resistance of source/drain regions and/or makes it easier to establish electrical contact to the source/drain regions.
FIG. 1B illustrates a cross-sectional view depicting the formation of epitaxial semiconductor material on various fins across the substrate 105, including fins for various finFET devices 100. The epitaxial material is formed in the source/drain regions of the finFET devices. The fins 110 shown in FIG. 1B are so-called densely-spaced fins. Additional so-called isolated fins 135 are illustrated representing a different region of the substrate 105 where the spacing between adjacent fins is larger. For example, the densely-spaced fins 110 may be part of a logic device or SRAM NFET, while the isolated fins 135 may be part of an SRAM PFET. During an epitaxial material growth process, the growth starts in the direction of a (111) crystallographic plane of the substrate 105. In the case of the densely spaced fins 110, the epitaxial material can grow between the fins 110 and merge to form a substantially horizontal surface. Further growth from the horizontal surface occurs in a direction corresponding to a (100) plane of the substrate. Growth occurs much faster in a (100) plane as compared to a (111) plane, thus resulting in a merged epitaxial material structure 140 above the densely-spaced fins 110 and discrete unmerged epitaxial material structures 145 above the isolated fins 135.
A device with the merged epitaxial material structure 140 can have different device characteristics as compared to a device with the discrete unmerged epitaxial material structures 145. For example, the resistance of the device may be higher for the device with the merged epitaxial material structure 140. Conductive contact structures will eventually be formed to the source/drain regions of the device. Due to the relatively higher position of the upper surface and the more planar-like surface topology of the merged epitaxial material structure 140, the contact etches terminate differently, and the contact structures have different sizes, as compared to contact structures formed on the discrete unmerged epitaxial material structures 145 above the isolated fins 135. This size difference results in a difference in resistance. In addition, the densely-spaced fins 110 may be associated with separate devices (e.g., an N-channel device and a P-channel device), and the merged epitaxial material structure 140 may cause a short circuit between the densely-spaced fins 110 of the separate devices, which may destroy their functionality.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds