1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which memories and logic circuits, analog circuits, etc. are included.
2. Description of the Related Art
In an application specification integrated circuit (ASIC), memories and logic circuits, analog circuits, etc. are often included (see Japanese Laid-Open Publication No. 11-214649, for example).
FIG. 3 is a block diagram illustrating an example of a conventional semiconductor integrated circuit. This semiconductor integrated circuit includes memory macros, a logic circuit block, power circuit macros for the memory macros, power terminals, power wires, etc.
The semiconductor integrated circuit shown in FIG. 3 has a structure in which a logic circuit block 32, memory macros 33, logic circuit power terminals 35, memory power terminals 36, logic circuit power wires 37, memory power wires 38, power circuit macros 39, internal power wires 40, memory high-voltage power terminals 41, and memory high-voltage power wires 42 are provided on a semiconductor chip 31.
Power for operating the logic circuit block 32 is supplied to the logic circuit block 32 from the logic circuit power terminals 35 through the logic circuit power wires 37. Power for operating the memory macros 33 is supplied to the memory macros 33 from the memory power terminals 36 through the memory power wires 38, while power generated by the power circuit macros 39 is supplied to the memory macros 33 through the internal power wires 40. The power circuit macros 39 generate the power from power supplied thereto from the memory high-voltage power terminals 41 through the memory high-voltage power wires 42.
Of the two power supply voltages supplied to each memory macro 33, the voltage supplied through the memory power wire 38 is used for operation of a logic circuit section provided in the memory macro 33. On the other hand, the power supply voltage supplied through the memory high-voltage power wire 42 is used as power for a memory core portion in the memory macro 33, to be specific, as word line power and memory cell substrate power. The power supply voltage supplied through the memory power wire 38 is about 1.2 V, and the power supply voltage supplied through the memory high-voltage power wire 42 is about 3.3 V, for example.
In this semiconductor integrated circuit, the logic circuit block 32 and the memory macros 33 having the different power sources are provided on the semiconductor chip 31 in a mixed manner. The logic circuit power terminals 35 and the memory power terminals 36 for supplying power to the logic circuit block 32 and the memory macros 33, respectively, are provided around the peripheries of the logic circuit block 32 and memory macros 33 at irregularly spaced intervals.
For example, as shown in FIG. 3, in the case where the memory macros 33 are disposed on the right and left sides of the semiconductor chip 31, the memory power terminals 36 for supplying power to the respective memory macros 33 are provided at the right and left sides of the semiconductor chip 31. This is because it is preferable that the lengths of the memory power wires 38 be minimized in order to reduce voltage drops, wire delays and so on in the memory power wires 38 that connect the memory macros 33 and the memory power terminals 36 which supply power to the memory macros 33.
The power circuit macros 39 are in a one-to-one correspondence with the memory macros 33 and are provided in or adjacent to the respective memory macros 33.
However, the above-described conventional semiconductor integrated circuit has a problem in that the wire efficiency therein declines as the power wire resistance increases.
Specifically, in the conventional semiconductor integrated circuit, since the logic circuit block and the memory macros are disposed on the semiconductor chip at irregularly spaced intervals, the logic circuit power terminals and the memory power terminals are also placed on the semiconductor chip at irregularly spaced intervals. This causes the logic circuit power wires 37 and the memory power wires 38 to be present in a complicated manner on the semiconductor chip. As a result, the logic circuit power wires 37 and the memory power wires 38 may not be able to be collectively disposed around the logic circuit block 32 and the memory macros 33, respectively, in which case the power wire resistance will be increased and the wire efficiency will thus decline.
Furthermore, since the memory power terminals are placed on the semiconductor chip at irregularly spaced intervals, it is also necessary to route wires for supplying the memory power, outside the semiconductor chip. That is, in the above-described conventional semiconductor integrated circuit, the wiring outside the periphery of the semiconductor chip may also be adversely affected.
Moreover, since each memory macro is provided with the corresponding power circuit macro, the total area occupied by those power circuit macros is increased. That is, the area of the memory-related block is increased, resulting in an increase in the area of the entire semiconductor chip.
USPTO Backgrounds
USPTO Backgrounds