1. Field of the Invention
This invention relates to computer systems and more particularly to peripheral resource controllers that include a DMA transfer mechanism for transferring data between a host computer and a peripheral resource. The invention further relates to high performance adapter cards including disk controllers.
2. Description of the Relevant Art
High performance adapter cards such as disk controllers and network controllers coordinate the transfer of data between a host computer and a peripheral resource. A typical adapter card includes a DMA controller which provides a hardware mechanism for transferring large sequential groups of data between a host system memory and a local memory of the adapter card. The adapter card's local memory typically includes a RAM buffer, often in the form of a cache memory, which temporarily holds data prior to sending it to the host computer or to the peripheral resource.
The DMA controller associated with a peripheral resource controller must be programmed with the host and local addresses for a desired sequential transfer request along with the length of the transfer. The length of the transfer is typically specified as a number of "blocks", wherein each block consists of a predetermined amount of data. The local processor typically loads the address and block length information in a memory table or list. This list is then read by the DMA controller to set-up each block transfer for execution.
Further details regarding the operation of a typical peripheral resource controller will be better understood with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a computer system 100 including an exemplary adapter card illustratively embodied as peripheral controller 104. A host processor 102 and a system memory 103 are coupled to peripheral controller 104 via a host bus 106. A plurality of SCSI devices 106A-106D are further shown coupled to peripheral controller 104 via SCSI buses 108 and 110. The peripheral controller 104 includes a bus interface controller 120 coupled to a local processor 122 and to a local memory 124 via a local bus 126. A pair of SCSI processors 128 and 130 as well as a DMA transfer list memory 132 are finally shown coupled to local bus 126.
FIG. 2 is a block diagram of the bus interface controller 120 incorporated within the peripheral controller 104 of FIG. 1. The bus interface controller 120 includes a host interface 202 coupled to host bus 106, and a local interface coupled to local bus 126. A DMA controller 208 is coupled between local interface 204 and host interface 202.
Peripheral controller 104 is illustrative of a caching disk array controller. As such, SCSI devices 106A-106D are representative of a set of SCSI hard drives. Referring collectively to FIGS. 1 and 2, if it is desired to transfer data stored within one or more sectors of the hard drives into system memory 103, host processor 102 must first provide a data request command, which may be in the form of a data request structure stored within local memory 124, to peripheral controller 104 to thereby cause local processor 122 to determine the particular sectors of the hard drives at which the requested data resides. If the data is not already present within a cached portion of the local memory 124, the local processor 122 causes the requested data to be transferred from the appropriate hard drive(s) into local memory 124 under control of the respective SCSI processor 128 or 130.
In addition to determining the particular hard drives and corresponding sectors in which the requested data resides and causing the transfer of those sectors into local memory 124, local processor 122 also loads into the DMA transfer list memory 132 the host and local addresses for a sequential transfer along with the number of blocks forming each sequential transfer. Once the requested data (or portions thereof) is stored within the local memory 124 and the corresponding address and block length information has been stored within DMA transfer list memory 132, local processor 132 invokes DMA controller 208 to begin a direct memory access transfer operation wherein DMA controller 208 reads the sequential transfer information from DMA transfer list memory 132 and responsively effectuates a transfer of the data from local memory 124 to system memory 103 without the supervisory control of either the host processor 102 or the local processor 122.
Since the DMA transfer list memory 132 resides on local bus 126, DMA controller 208 must arbitrate for local bus 126 to retrieve the transfer list address and block length information from the DMA transfer list memory 132. This reduces the DMA performance as well as limits the ability of local processor 322 to perform concurrent bus operations. Although the DMA transfer list memory 132 could be decoupled from local bus 126 by integrating it internally within bus interface controller 120, such a solution is typically not cost effective, particularly where the bus interface controller 120 is fabricated using FPGA or gate array implementations.
USPTO Backgrounds
USPTO Backgrounds