1. Field of the Invention
The present invention relates to a processor capable of switching/reconstituting its architecture, comprising a processor architecture conversion unit for executing a plurality of types of processor instruction sets of different architecture with one and the same hardware, by which the processor architecture can easily be switched or reconstituted because the processor architecture constitution information in the processor architecture conversion unit is concentratedly stored in several means for memorizing.
2. Description of the Related Art
Conventionally, all processors have been provided with a single instruction set appropriate to its hardware architecture that can be directly executed (hereinafter referred to as a “native instruction set”), and have been unable to directly execute any software program designed for an instruction set of a different architecture (hereinafter referred to as a “non-native architecture”). Items to be considered when executing a software program for a non-native architecture include, in addition to the difference of instruction sets, difference of formality processing appropriate to the processor hardware architecture, such as typically an exception processing. Since such processing is in general automatically executed according to the processor hardware, an instruction for the required formality is not introduced from outside. Accordingly, by a simple instruction conversion it is impossible to execute a software program designed for a non-native architecture with respect to exception processing. From such a viewpoint, in order to execute a software program designed for a non-native architecture by a processor, it has been necessary to provide means for virtually achieving a function that is appropriate to the processor hardware in addition to instruction conversion processing for converting a non-native instruction into a native one.
The virtual achievement of instruction conversion and a function appropriate to hardware can be broadly classified into the achievement by software and that by hardware.
One of the easiest ways to convert an instruction by hardware is to adopt a lookup table. A prescribed lookup table in which correspondence of non-native instructions with native instructions is prepared in advance, so that an arbitrary instruction binary value of a non-native instruction set can be referred as a reference address according to the lookup table, to read out not less than one corresponding native instruction. By this method, an instruction conversion can be executed much more quickly than a conversion by software, and a non-native instruction set application program can be executed no less quickly than executing a native instruction set program in terms of execution speed of an application program, though there may be a slight time-lag because of the conversion.
However, this method has the following disadvantage. When converting according to a lookup table, a one-on-one instruction conversion is basically assumed. Generally, a CISC (Complex Instruction Set Computer) type instruction set sometimes includes a case where an extremely complicated processing is executed through a single instruction, such as a singular, combined and/or repeated processing of functions like memory address calculation, memory access, computation etc. for which complicated operations are required, however in order to convert such a complicated instruction into an RISC (Reduced Instruction Set Computer) type instruction set, since a one-on-multiple instruction conversion is indispensable, a simple one-on-one lookup table method cannot be employed in such a case. In case where a one-on-multiple conversion is to be executed at all by lookup table method, a lookup table of an extremely large capacity (memory capacity in general) would be required, which would cause a prohibitive cost increase.
In order to restrict the increase of a lookup table capacity, a proposition has been made that while separately extracting only field information that has a particular meaning in a certain portion of an instruction word (such information as computation register designation, memory access addressing mode designation, etc.) through an exclusive combinational logic circuit, reference is made with the lookup table based on instruction binary information of the remaining portion of the original instruction word length except the above field portion, and the converted instruction word and the extracted field information are merged so as to convert into a native instruction word. However in many of the CISC type instruction sets especially those with a short instruction bit length, position or length of field information that has a particular meaning in a portion of the instruction word is not constant but different depending on instructions, therefore it is difficult to apply the above-proposed method. Accordingly in such a case the only possible way is to refer to the lookup table using all binary values of the instruction word as reference address, and consequently a large lookup table capacity is required. For instance, for executing a one-on-one conversion of a CISC type instruction set having a basic length of 16 bits into a VLIW type instruction set of 128 bits by a simple lookup table, a lookup table of a capacity of as large as 1 MB (Megabyte) is required, which makes it impossible to employ this system from a view point of cost. Further, in case of converting a CISC type instruction set of a basic length of 32 bits, the required lookup table capacity reaches as great as 64 GB (Gigabyte), which is impossible to integrate in one chip with the currently available semiconductor technology.
Another major problem with the lookup table method is that formality processing cannot be handled.
In view of the foregoing problems, instruction set architecture conversion by an exclusive combinational logic circuit that does not include a lookup table is popularly employed, especially for converting a CISC type instruction set into an RISC type instruction set. By such method, a formality processing, which is unsolvable with the lookup table method, can also be handled through establishing an exclusive state machine. However even in this case, since the combinational logic is fixed, when executing different non-native instruction set architectures on one and the same processor, exclusive instruction conversion circuits for the respective non-native instruction set architectures to be converted have to be provided, which significantly increases the cost. In addition, it is also impossible to freely modify the non-native instruction set architecture to be executed at an operation site of the processor.
It is an object of the invention to provide solutions for the foregoing various problems related to conversion of instruction and architecture by hardware that is prominently superior in execution speed performance among those processor systems capable of executing non-native instruction sets, specifically the problems with the lookup table method that besides requiring a large table (memory) capacity it is impossible to completely reproduce formality processing functions appropriate to the processor architecture such as external interrupt exception processing; with the combinational logic circuit that since the logic is fixed it is difficult to reconstitute the logic, moreover for conversion of a plurality of non-native instruction set architectures a large circuit scale is needed since the same number of combinational logic circuits as the non-native instruction set architectures are required, which results in a disadvantage in cost, etc.
By totally resolving these problems, it becomes possible to convert a plurality of different non-native instruction set programs on one and the same processor at a low cost, maintaining a high execution speed performance and dynamically switching the non-native instruction sets without depending on a native instruction set architecture of an execution unit, and further it will be possible to even select or modify whenever necessary the non-native instruction sets to be converted in operation sites of the processor systems in which the invention is incorporated.
USPTO Backgrounds
USPTO Backgrounds