1. Field of the Invention
The present invention is related to a method for fabricating Thin Film Transistor (TFT), and more particularly, to a method for fabricating TFT, of which an active layer is formed by crystallizing a silicon thin film, using Sequential Lateral Solidification (SLS).
2. Description of Related Art
In order to fabricate TFTs on a low heat-resistant substrate, such as a glass substrate, an amorphous silicon layer or a polycrystalline silicon layer is deposited on the substrate and is etched by photolithography to form active layers for TFTs.
The mobility of a carrier is low in the amorphous silicon layer. Accordingly, amorphous silicon TFT is difficult to be used as a device for driving circuits of a liquid crystal display (LCD). However, the mobility of a carrier is high in the polycrystalline layer. Accordingly, polycrystalline TFT could be used as a device for driving circuits of a liquid crystal display (LCD), in which devices for pixel array and a device for driving circuits are formed simultaneously.
There are two techniques to form polycrystalline silicon film on a glass substrate. In the first technique, an amorphous silicon film is deposited on the substrate and is crystallized under a temperature of 600 C by Solid Phase Crystallization (SPC). The first technique needs a high temperature process. Therefore, it is difficult to form the polycrystalline silicon film layer on the glass substrate by the first technique.
In the second technique, an amorphous silicon film is deposited on the substrate and is crystallized by thermal treatment using a laser. The second technique does not require a high temperature process. Therefore, the second technique is applied to form a polycrystalline silicon film on the glass substrate.
FIG. 1A to FIG. 1E are schematic drawings for explaining a method for fabricating a TFT according to the prior art.
Referring to FIG. 1A, a source electrode 11S and a drain electrode 11D are formed on an insulating substrate 100. And an amorphous silicon layer 12 is deposited on the exposed surface of the substrate comprising the source electrode 11S and the drain electrode 11D. The amorphous silicon layer 12 has steps and sloping surfaces, since the amorphous silicon layer 12 covers the protruding source and drain electrodes 11S and 11D.
Referring to FIG. 1B, the amorphous silicon layer is crystallized into a polycrystalline silicon layer 13 by carrying out a crystallization procedure using laser annealing. The method for crystallizing the amorphous silicon layer into the polycrystalline silicon layer 13 by applying a laser beam to the amorphous silicon layer is described as follows.
An active layer of the TFT is formed by the polycrystalline silicon layer having large silicon grains to decrease the effect of the grain boundary which prevents carriers from passing through the channel.
A selected region of the amorphous silicon layer is first irradiated with an energy density to induce separated islands of amorphous silicon, remaining. The other regions undergo complete melting. The amorphous film is translated or moved relative to the laser beam over a distance less than a predetermined distance for a second irradiation. While the film is translating, the separated islands of amorphous silicon are used as seeds and grow into the molten silicon region, to form a first polycrystalline silicon region. Herein, grain growth occurs from the interface between the liquid silicon region and the solid state amorphous silicon region into the liquid silicon region. This grain growth stops by making grain boundary when each grain collides. The above-described process of irradiating and crystallizing is repeated over a total translation distance to crystallize the majority of the film.
Referring to FIG. 1C, the polycrystalline silicon layer is etched by photolithography to form an active layer 14. Referring to FIG. 1D, a gate insulating interlayer 15 and a gate electrode 16 are formed on the active layer 14. Source and drain regions 14S and 14D are then formed in the active layer 14 by doping impurities in the exposed portions of the active layer 14. The channel region 14C is formed between the source and the drain regions 14S and 14D.
Referring to FIG. 1E, a passivation layer 17 is deposited on the exposed surface of the substrate and is etched selectively to expose a portion of the drain electrode 11D. And a pixel electrode 18 is formed connecting the exposed portion of the drain electrode 14D on the passivation layer 17.
However, since the size of each silicon grain is non-uniform and the location of grain boundary is random in the active layer, device-to-device uniformity is low in TFTs fabricated according to the prior art. Therefore, the polycrystalline silicon layer connot be applied to form devices having complicated circuits, while a single crystal silicon film could be applied to form such device.
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