(1) Field of the Invention
The present invention relates to manufacturing of semiconductor devices in general, and in particular, to a method of improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m.
(2) Description of the Related Art
Electrostatic discharge (ESD) occurs when a relatively large amount of voltage usually generated by tribo(rubbing) electricity is released suddenly. For example, a person taking an integrated circuit from its plastic wrapping materials or walking across a room can generate up to 20,000 V. Such an unintended discharge into a metal oxide semiconductor field effect transistor (MOSFET) can cause immediate damage to the circuit or subsequent early life failure.
The elements that initially encounter an ESD pulse in an integrated circuit are typically input and/or output buffers that are directly connected to bond pads or terminals on a chip which are exposed to the external environment. The discharge can find its way to the gate, drain or the source, although the source is typically connected to a power supply and is unlikely to supply an ESD pulse. Whether the ESD pulse traverses the gate or the drain, it can ultimately cause a breakdown of the dielectric gate oxide barrier between the gate and the channel in an FET device by leaving a conductive path of ionized dielectric or trapped electrons, or by burning a hole in the gate oxide. Even if the ESD pulse does not flow directly between the gate and the drain, an electronic ripple from this pulse may destroy the gate oxide layer, which breaks down at 20 volts or less. The destruction of the gate oxide renders the circuit, chip, and often the device containing the chip nonfunctional.
The function of a prior art ESD device in protecting an internal FET device in an integrated circuit is depicted in the circuit diagram of FIG. 1a which is also described in U.S. Pat. No. 5,559,352. ESD protection device (50) is connected to input or output (I/O) pad (51), and consists of two NMOS devices (53) and (55). It is through pad (51) that electrostatic charges may enter the integrated circuit from an exterior source such as a person handling the device. The NMOS transistor (53) has its source connected to Vcc, a voltage source. At the same time, its (53) drain is connected to the drain of NMOS (55), and to the I/O pad (51), as well as to the internal circuit (60) the ESD is designed to protect. The gates of transistors (53) and (55) as well as the source of (55) are connected to ground.
The internal device that is to be protected on the same IC chip is shown to be a CMOS inverter (60) in FIGS. 1a and 1b, though other circuits could be protected by the same ESD device. This inverter has its input (63) connected to the gates of P-channel transistor (67) and N-channel transistor (69). The P-channel source is connected to Vcc, while the N-channel source is connected to ground. The drains of the two transistors are connected together and provide the output terminal of the inverter. A cross-sectional representation of the circuit diagram in FIG. 1a, and connections, is shown in FIG. 1b where drain, source and gate are schematically labeled as (30), (35) and (37), respectively on substrate (10) and isolated with field oxide (20).
There are several methods available in prior art to mitigate the occurrence of ESD. The simplest method is to increase the thickness of the gate oxide material, SiO.sub.2. However, this would be contrary to the trend in technology where the gate oxide thickness is being reduced continuously because the speed of the devices is inversely proportional to that thickness. The gate oxide in present circuits is approximately 100 angstroms, .ANG., thick or less and will be thinner in future circuits. Normally, the dielectric breakdown strength of silicon dioxide (SiO.sub.2) is 8 MV/cm. Therefore, a 100 .ANG. thick gate oxide will not sustain voltages more than about 8 volts. In actual practice, gate oxides are thinner than 100 .ANG. and process variables make the gate oxides thinner in spots causing the actual sustainable voltage to be well below 8 V. Furthermore, this 8 V breakdown is less than the junction breakdown voltages. Thus, gate oxide will breakdown before the junction does. This is especially a problem with ESD protection devices because ESD transient operating voltages are higher than the gate oxide breakdown voltage. When the gate oxide in the protection circuit breaks down, the ESD protection circuit does not function to protect the device circuit. It is conceivable to have thicker gate oxide thickness for ESD protective devices while keeping the thinner thickness for input product devices, the conventional one step gate oxidation process does not permit variable thicknesses on the same wafer. Therefore, other methods must be sought to provide electrical strength for the relatively thin gate oxides of the more recent ultra high speed circuits of today.
In U.S. Pat. No. 5,532,178, Liaw, et al, propose a method that will provide a higher gate oxide breakdown voltage than the drain junction breakdown voltage on ESD circuit transistors while maintaining thin gate oxide thickness for product CMOS device circuits. The improvement consists of fabricating an NMOS ESD circuit with an undoped polysilicon gate electrode combined with CMOS devices which may have doped gate electrode. The undoped polysilicon gate electrode of the ESD transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.
The approach taken by Hsue of U.S. Pat. No. 5,559,352 is the opposite of the previous approach in that rather than increasing the breakdown voltage of the gate oxide, the junction breakdown voltage of the ESD protection device is reduced. Thus, it is again the junction that is made to fail before the breakdown of the gate oxide. This is accomplished by forming a deeper and lighter ion implanted region of opposite conductivity centered under the source and drain regions of the ESD device, thereby lowering the level of drain junction breakdown.
Instead of adding protective circuits, which occupy valuable chip area, a still another approach protects an integrated circuit chip from ESD events by adding a series resistance between a source and drain of input or output transistors connected to bond pads of the chip. As described by Randazzo, et al, in U.S. Pat. No. 5,493,142, the series resistance is designed to raise the voltage of localized current path between the source and drain above a trigger voltage at which ESD conduction across the channel initiates. By raising the voltage of this path above the trigger voltage, ESD conduction is induced in adjacent paths. Thus, instead of ESD conduction being concentrated along a localized path between the source and drain, which typically burns a hole along the path that destroys the transistor and renders the chip nonfunctional, ESD conduction is encouraged to spread across the channel width, which is designed to be large enough to absorb and ESD pulse without damage. According to the same patent, the actual forming of the series resistance is accomplished by doping a substrate masked by a gate and then forming and selectively etching an oxide layer covering the gate, source and drain of the transistor during manufacturing such that a sidewall oxide spacers is extended outward from the gate toward the drains a measured amount. The selective etching of that oxide layer exposes the surface of the substrate at ends of the sidewall oxides proximal to the gate, allowing the formation of source and drain regions and contacts thereto. A lightly doped region of the substrate is left under the extended sidewall oxide, providing a resistance in series between the drain and the channel. It is taught by Randazzo that this added series resistance mitigates ESD damage.
Yet another prior art approach provides the forming of transistor devices in electrically and physically isolated islands. This technique is especially amenable to silicon-on-insulator (SOI) technology where silicon film on an insulator can be delineated easily to form the desired islands as described in U.S. Pat. No. 5,489,792. Each island then has at least one conducting path which is capable of absorbing some amount of ESD energy. The total ESD energy is thus spread among the isolated regions, whereas in a contiguous bulk transistor, the ESD current tends to concentrate in few paths which can lead to device failure.
Each one of these methods of forming ESD protective devices has the advantages cited above, but applicable only to semiconductor lithographic technologies of 1-micron (.mu.m) or greater where the gate oxide thicknesses are 100 .ANG. or more. However, for advanced sub-micron technologies of today where speed and packing density are critical, the gate oxide thicknesses are becoming much less than 100 .ANG.. It is disclosed in the present invention an ion implanting method of forming ESD devices for technologies supporting feature sizes under 1/2-micron. It is also disclosed that by this method, junction areas of high leakage current and high capacitance are advantageously avoided. Furthermore, the method disclosed here prevents the formation of contacts of higher contact resistances that are usually experienced with prior art methods.
USPTO Backgrounds
USPTO Backgrounds