1. Field of the Invention
The present invention relates to a driving circuit for a shared sense amplifier, and more particularly, it relates to a circuit for driving a sense amplifier shared by two pairs of bit lines at a high speed.
2. Description of the Prior Art
FIG. 1 shows an example of a shared sense amplifier to which the present invention can be applied. In FIG. 1, a clock .phi..sub.3 is supplied to respective sources of transistors 1 and 2. The drain of the transistor 1 is connected to a sense node 9 while the gate thereof is connected to a sense node 10. On the other hand, the drain of the transistor 2 is connected to the sense node 10 while the gate thereof is connected to the sense node 9. These transistors 1 and 2 form a flip-flop type sense amplifier.
One end of the sense node 9 is connected to a bit line 3.sub.R through a transfer transistor 7.sub.R while the other end thereof is connected to a bit line 3.sub.L through a transfer transistor 7.sub.L. One end of the sense node 10 is connected to a bit line 4.sub.R through a transfer transistor 8.sub.R while the other end thereof is connected to a bit line 4.sub.L through a transfer transistor 8.sub.L. The transfer transistors 7.sub.R and 8.sub.R are adapted to connect and cut off the bit lines 3.sub.R and 4.sub.R on the right side with and from the sense amplifier, and are on-off controlled by a control clock .phi..sub.2R. Similarly, the transfer transistors 7.sub.L and 8.sub.L are adapted to connect and cut off the bit lines 3.sub.L and 4.sub.L on the left side with and from the sense amplifier, and are on-off controlled by a control clock .phi..sub.2L. The bit lines 3.sub.R and 4.sub.R form a pair of folded bit lines while the bit lines 3.sub.L and 4.sub.L similarly form another pair of folded bit lines. In the shared sense amplifier circuit as shown in FIG. 1, the sense amplifier, which is formed by the transistors 1 and 2, is shared by the two pairs of folded bit lines.
The bit lines 3.sub.R and 4.sub.R on the right side of FIG. 1 are respectively connected with sources of transistors 5.sub.R and 6.sub.R. Precharge voltage V.sub.R is applied to respective drains of the transistors 5.sub.R and 6.sub.R while a precharge clock .phi..sub.1R is supplied to respective gates thereof. These transistors 5.sub.R and 6.sub.R are adapted to charge the bit lines 3.sub.R and 4.sub.R at the precharge voltage V.sub.R in response to the precharge clock .phi..sub.1R respectively. The bit lines 3.sub.R and 4.sub.R are further connected with memory cells MC.sub.1R and MC.sub.NR respectively. The storage content of the memory cell MC.sub.1R is read on the bit line 3.sub.R when a word line WL.sub.1R is selected while the storage content of the memory cell MC.sub.NR is read on the bit line 4.sub.R when a word line WL.sub.NR is selected. The bit lines 3.sub.R and 4.sub.R are further connected with dummy memory cells DC.sub.1R and DC.sub.2R. With respect to the dummy memory cell DC.sub.1R, intermediate potential between read out potential of information "0" and that of information "1" is read on the bit line 3.sub.R when a dummy word line DWL.sub.1R is selected, while the said intermediate potential is read on the bit line 4.sub.R when a dummy word line DWL.sub.2R is selected with respect to the dummy memory cell DC.sub.2R.
Elements similar to those connected with the bit lines 3.sub.R and 4.sub.R are connected with the bit lines 3.sub.L and 4.sub.L on the left side. The elements corresponding to the aforementioned ones are indicated by the same reference numerals, except for that the subscripts "R" are replaced by "L", and detailed description thereof is herein omitted.
The bit lines 3.sub.L and 4.sub.L on the left side are connected with read/write lines I/O.sub.1 and I/O.sub.2 respectively through transfer transistors 11 and 12. A clock .phi..sub.4 is supplied to respective gates of the transfer transistors 11 and 12.
Although merely four word lines WL.sub.1R, WL.sub.NR, WL.sub.1L and WL.sub.NL are shown in FIG. 1, a number N (arbitrarily selected even number) of word lines are present on each side in practice while the number N of memory cells MC.sub.1R (MC.sub.1L) to MC.sub.NR are connected with the bit lines 3.sub.R (3.sub.L) and 4.sub.R (4.sub.L) by N/2 respectively.
Although the circuit as shown in FIG. 1 employs only one sense amplifier, a practical memory is generally formed by a plurality of sense amplifiers which are vertically aligned to form arrays of memory cells.
Description is now made on a circuit having one sense amplifier and two word lines, for easy understanding of the present invention.
FIG. 2 is a timing chart of an NMOS employed for illustrating the operation of the circuit as shown in FIG. 1.
In a standby state to a time T.sub.1, the precharge clock .phi..sub.1L is at a high level, whereby the transistors 5.sub.L and 6.sub.L are in ON states and the bit lines 3.sub.L and 4.sub.L are charged at the precharge voltage V.sub.L. The precharge clock .phi..sub.1R is also at a high level, whereby the bit lines 3.sub.R and 4.sub.R are charged at the precharge voltage V.sub.R through the transistors 5.sub.R and 6.sub.R. During this period, the clock .phi..sub.3 for inactivating the sense amplifier is at a high level, whereby the sense amplifier is retained in the standby state. Assuming here that either of the memory cells MC.sub.1R and MC.sub.NR on the right side of the sense amplifier is addressed by address data (not shown), the potential of either word line WL.sub.1R or WL.sub.NR and that of either dummy word line DWL.sub.1R or DWL.sub.2R are increased, while the non-selected word line WL.sub.1L or WL.sub.NL and dummy word line DWL.sub.1L or DWL.sub.2L remain at low levels.
The potential levels at the selected word line and dummy word line are not immediately increased upon the addressing performed by the address data. This is because the address data are supplied to a decoder (not shown), which increases the potential levels at the selected word line and dummy word line, whereby the increase in the potential levels of the word line and dummy word line is delayed from the addressing by the time required for processing in the decoder.
Description is now made on the case where, for example, the word line WL.sub.1R and dummy word line DWL.sub.2R are selected.
Upon input of the address data, the control clock .phi..sub.2L is turned to a low level at a time T.sub.2 before increase of the potential levels at the word line WL.sub.1R and dummy word line DWL.sub.2R, whereby the transfer transistors 7.sub.L and 8.sub.L are both made nonconductive. Thus, the sense nodes 9 and 10 are electrically cut off from the bit lines 3.sub.L and 4.sub.L, and the potential levels at the word line WL.sub.1R and dummy word line DWL.sub.2R are increased at a time T.sub.3. Then, information stored in the memory cell MC.sub.1R is read on the bit line 3.sub.R and the charge stored in the dummy memory cell DC.sub.2R is read on the bit line 4.sub.R respectively. The read information is transferred to the sense nodes 9 and 10 through the transfer transistors 7.sub.R and 8.sub.R during the period when the control clock .phi..sub.2R is at a high level to a time T.sub.4. The level of the control clock .phi..sub.2R slightly drops at the time T.sub.4 while impedance levels of the transfer transistors 7.sub.R and 8.sub.R are increased. When the clock .phi..sub.3 is turned to a low level at a time T.sub.5, the sense amplifier formed by the transistors 1 and 2 is activated and the information transferred to the sense nodes 9 and 10 is amplified. The amplified information is returned to the bit lines 3.sub.R and 4.sub.R respectively through the transfer transistors 7.sub.R and 8.sub.R, to be re-written in the memory cell being selected. The control clock .phi..sub.2L is again turned to a high level at a time T.sub.6, whereby the amplified information is transferred to the bit lines 3.sub.L and 4.sub.L through the transfer transistors 7.sub.L and 8.sub.L.
The clock .phi..sub.4 is turned to a high level at a time T.sub.7, and the amplified information is transferred to the read/write lines I/O.sub.1 and I/O.sub.2 through the transfer transistors 11 and 12. The word line WL.sub.1R, dummy word line DWL.sub.2R and clock .phi..sub.4 return to low levels at a time T.sub.8 and the clocks .phi..sub.1R, .phi..sub.1L, .phi..sub.3 and .phi..sub.2R are turned to high levels at a time T.sub.9, whereby the folded bit lines on both sides are charged at V.sub.R and V.sub.L respectively, and the sense amplifier returns to a standby state.
The sequential read/write operation is performed in the aforementioned manner. The impedance levels of the transfer transistors 7.sub.R and 8.sub.R are so increased in amplification of the sense amplifier as to reduce capacitive loads at the sense nodes 9 and 10 thereby to increase amplification sensitivity.
When the memory cells MC.sub.1L and MC.sub.NL on the left side are selected, the waveforms of the control clocks .phi..sub.2L and .phi..sub.2R change places with each other.
As hereinabove described, the sense amplifier as shown in FIG. 1 is driven to be shared by two pairs of folded bit lines.
As obvious from the foregoing description, the waveforms of the control clocks .phi..sub.2R and .phi..sub.2L have important functions for driving the shared sense amplifier. Particularly the control clock on the non-selected side (.phi..sub.2L in the above case) must be immediately turned to a low level before the potential levels at the selected word lines rise upon the addressing of the memory cells by the address data, i.e., before read-out of the memory cells, to cut off the non-selected bit lines from the sense amplifier. Slow fall of the control clock on the non-selected side delays the read-out from the memory cells, whereby high-speed read-out is disabled. Thus, awaited is implementation of a driving circuit for a shared sense amplifier which can attain high-speed readout operation by quickly connecting and cutting off bit lines with and from the sense amplifier.
USPTO Backgrounds
USPTO Backgrounds