1. Field of the Invention
The present invention relates to integrated circuit power dissipation. More specifically, the present invention relates to a lower power dissipation bus structure within an integrated circuit or a circuit board.
2. Description of the Background Art
Integrated circuits operate by charging and discharging internal components in order to switch between logic states. The frequency at which an integrated circuit switches between logic states is referred to as its switching frequency. Each switching cycle dissipates power in charging and discharging components and in passing the power through busses to and from the logical components. The faster the switching frequency, the greater the power dissipation in a given period of time.
The dissipation of power generates heat. The quantity of heat generated in a given area of an integrated circuit is directly proportional to the density of the logic elements and circuitry on the integrated circuit chip. The heat generated should be removed from the chip to maintain the chip within its proper operating temperature. The rate of heat removal is proportional to its surface area, including any surface area of a heat sink attached to the chip and the rate of air flow over the chip. A densely packed chip with a high switching frequency must dissipate significantly more heat with a smaller surface area than a larger chip with a slower switching frequency and less dense packing.
The increase in switching frequencies and chip densities of current integrated circuit chips requires additional techniques for reducing power dissipation to maintain acceptable operational temperatures. Some integrated circuit chips have incorporated a reduction in operational voltage to compensate for increased power dissipation requirements. By decreasing the operational voltage of a chip, the quantity of power dissipated during logic level switching is reduced.
The technique of reducing the operational voltage to reduce power dissipation is approaching its physical limitations due to a variety of reasons, including the minimal necessary voltage for the logic elements. Current integrated circuits, such as DSP""s, RISC processors and the like typically operate between 2 volts and 9 volts. Operating voltages of current integrated circuits are approaching 1.0 volt. The operational voltage of an integrated circuit cannot be reduced significantly below 0.9 volts otherwise differentiation of logic states will be lost due to noise margins associated with resistive losses, switching noise and thermal noise.
This present invention address a new method of reducing power dissipation within an integrated circuit. Power dissipation within a CMOS circuit is a result of either charging a node from a low voltage to a higher voltage or from discharging a node from a high voltage to a lower voltage. Typically, the lower voltage state is referred to as Vss and the higher voltage is referred to as Vdd. The two voltages are derived from two power supply voltages to the integrated circuit.
The present invention reduces the significant portion of the IC""s power dissipation consumed by the act of charging and discharging data and address busses within the IC because theses busses possess the highest capacitances of any of the nodes within the part. The present invention provides a multi-level bus circuit, with a plurality of input voltages; a bus connected at a first end to said plurality of input voltages and assuming a bus voltage corresponding to a selected one of said input voltages; and a logic circuit for sensing said bus voltage and for producing a binary output corresponding to said sensed voltage.
Presently, a data or address bus consists of xe2x80x9cnxe2x80x9d parallel lines where each line switches between Vdd and Vss in order to transfer information. The information on each of these lines is represented by two unique states, where a state is defied by the voltage on the line with respect to predefined voltage thresholds. For example, most binary systems define a logic xe2x80x9c0xe2x80x9d to be any voltage below 0.8 V and a logic xe2x80x9c1xe2x80x9d to be any voltage above 2.0 V, thus a voltage difference of 1.2 V. The region between 0.8 V and 2.0 V is the logic threshold. Since there is one threshold, there are two logic states: xe2x80x9c0xe2x80x9d below the threshold and xe2x80x9c1xe2x80x9d above the threshold.
The present invention defines a series of n+1 logic states by setting a series of thresholds from a minimum voltage to a maximum voltage. Below the minimum threshold voltage Vref1, the logic state would be xe2x80x9c0xe2x80x9d. Above the maximum threshold voltage Vrefn, the logic state would be xe2x80x9cnxe2x80x9d. A series of defined thresholds, Vref1, Vref2, . . . Vrefn, between the minimum and maximum voltages define a series of logic states 0, 1, 2 . . . n+1 between 0 and n+1. A multi-level line is used to carry the voltage signal. A voltage on the line is detected to indicate the logic state of the line.
USPTO Backgrounds
USPTO Backgrounds