1. Field of the Invention
This invention generally relates to semiconductor memory devices, and more particularly to a nonvolatile semiconductor memory device such as erasable and programmable read only memory (EPROM).
2. Description of the Prior Art
EPROMs as the nonvolatile semiconductor memory device are well known, and the structure of the EPROM cell, the arrangement of EPROM cells into a memory array and other related basic concepts are described, for example, in an article entitled "E-PROMs graduate to 256-K density with scaled n channel process" by M. Van Buskirk et al (Electronics, Feb. 24, 1983). FIG. 1 shows in block diagram the general arrangement of a typical prior art EPROM. As shown, the EPROM includes a memory array formed of a plurality of memory cells for storing data, an address buffer for selecting input addresses, X and Y decoders connected to the address buffer. The EPROM also includes an interface section having a sense amplifier and a program circuit connected to input and output buffers.
FIG. 2 shows an arrangement of the memory array of FIG. 1. A plurality of data storing memory cells are provided at the intersections or junctions of word lines WL.sub.1 -WL.sub.n and bit lines BL.sub.1 -BL.sub.m. As can be seen in FIG. 2, the word lines WL.sub.1 -WL.sub.n are connected to the X decoder, while the bit lines BL.sub.1 -BL.sub.m are connected to the Y-Gate transistors. Y-Gate transistors are connected to the Y decoder. The memory cells thus provided at the intersections of the word lines and bit lines form the memory array.
Now to briefly describe the operation, input address signals comprising row address signals and column address signals are fed through the address buffer to the X and Y decoders where the address signals are decoded to provide appropriate word line selection signals and bit line selection signals. The word line selection signal defines a word line to be selected, while the bit line selection signal defines a bit line to be selected. When one of the word lines and one of the bit lines are selected, data that has been stored in the memory cell at the intersection of the selected word line and the selected bit line is sensed or read out and it is amplified by the sense amplifier, after which the read out data is retrieved through the buffer.
FIG. 3 is a fragmentary plan view showing the construction of a typical prior art EPROM cell array. FIG. 4 is a cross-section taken along the line IV--IV of FIG. 3, and FIG. 5 is a cross-section taken along the line V--V of FIG. 3. Referring to these figures, there are formed on a semiconductor substrate 1 a plurality of field oxide layers 2 spaced away from one another. There are also formed gate oxide layers 3 to extend in a direction along the line IV--IV. Floating gates 4 are provided spaced apart from one another on the gate oxide layer 3. Another set of gate oxide layers 6 cover the floating gates 4 over the semiconductor substrate 1. On each of the gate oxide layers 6, a control gate strip 5 extends in the row direction of the memory array, that is, in a direction along the line IV--IV. Each control gate strip 5 includes a plurality of control gates and interconnects them to one another. An insulating layer 7 disposed on the semiconductor substrate 1 covers the elongated control gate strips 5. A plurality of metal conductor strips or lines 11 are formed spaced apart from one another along the line V--V on the insulating layer 7. As can be seen in FIG. 5, drain region 8 and source region 9 of the memory cell are alternately formed in the surface areas of the semiconductor substrate 1 between adjacent floating gates 4. The drain region 8 is electrically connected to the metal conductor strip 11 at a contact hole 10. As shown in FIG. 3, the drain region 8 is produced in the surface area surrounded by the field oxide layers 2 and the control gate strips 5. On the other hand, the source region 9 is formed to extend between adjacent control gate strips 5 along the line IV--IV. A coating 12 of glass (oxide layer) covers the metal conductor strips 11.
FIGS. 6A-6D and FIGS. 7A-7D illustrate in partial cross-section successive stages in the process for manufacturing the prior art EPROM shown in FIGS. 3, 4 and 5. FIGS. 6A-6D are cross-sectional views taken along the line IV--IV of FIG. 3, and FIGS. 7A-7D are cross-sectional views taken along the line V--V of FIG. 3.
Referring now to FIGS. 6A and 7A, field oxide layers are first formed on a P-type semiconductor substrate 1 to line up along the line IV--IV of FIG. 3 and are spaced FIG. 3 by using selective thermal oxidation techniques. Then gate oxide layer 3 is applied to cover the entire surface of the semiconductor substrate 1 including the field oxide layers 2. A layer of polycrystalline silicon (not shown) is deposited over the gate oxide layer 3 by, for example, chemical vapor deposition (CVD), and the polysilicon layer is selectively removed by dry etching in the areas over the field oxide layers 2 to leave portions 4 which will be formed into floating gates in the subsequent step.
In the step of FIGS. 6B and 7B, a second gate oxide layer 6 is first grown by CVD, and then a polysilicon layer (not shown) is deposited on this gate oxide layer. A layer 13 of photoresist having a predetermined pattern layout is applied over the polysilicon layer, and using the photoresist layer as a mask, selective etching is performed to form control gate strips 5. At the same time, separate floating gates 4 are formed in self-alignment manner (as can be more clearly seen in FIG. 7C).
Now in FIGS. 6C and 7C, after stripping the photoresist layer 13, arsenic ions are implanted in the direction indicated by the arrows with control gate strips 5 masking the implant, thereby forming N-type drain region 8 and N-type source regions 9 in the surface of the semiconductor substrate 1.
In FIGS. 6D and 7D, an insulating layer 7 is grown by chemical vapor deposition and contact holes 10 are made in the insulating layer at locations above drain regions 8 by dry etching. A metal conductor layer 11 is formed and patterned on the insulating layer 7 and it connects to drain regions 8 through contact holes 10. Finally, the substrate structure is covered by the glass coating 12 to produce an EPROM cell shown in FIGS. 3-5.
With the EPROM cell thus manufactured, when drain regions 8 and control gate strips 5 are kept at a high potential level, and the source region 9 is kept at a ground potential level, hot electrons produced in the channel region between the drain regions 8 and the source region 9 are injected into the floating gate 4. As a result, a data "0" is written and stored in the cell. When the memory cell is exposed to UV light, the electrons accumulated in the floating gate 4 are excited and discharged. As a result, the stored data "0" is erased (a data "1" is stored).
As shown in the graphic representation of FIG. 8, the threshold voltage V.sub.TH of the memory transistor in the EPROM cell during the data writing cycle differs from the threshold voltage during the erasure circle. By setting the control gate voltage V.sub.R for the data read out at a value midway between the threshold voltage during the writing cycle and the threshold voltage during the erasure circle, a nonvolatile read-out of data can be done. In FIG. 8, I.sub.D indicates a drain current, and V.sub.G indicates a control gate voltage.
As discussed hereinabove, in the prior art EPROM, the floating gates 4 are formed to lie side by side directly under the control gate strip 5 by selectively etching away the polysilicon layer. In this connection, it should be noted that the adjacent floating gates 4 must be horizontally and laterally spaced away from one another over the field oxide layer 2 in order to electrically isolate them. This has been done by using photoresist masking and etching. A layer of photoresist is coated over the polysilicon layer, leaving areas between adjacent floating gates exposed. Then the exposed areas of the polysilicon are etched away, thus providing an appropriate horizontal spacing or gap between the adjacent floating gates. The length or size of this horizontal inter-gate spacing depends on the resolution of both the photoresist and etching, and spacing can not be made smaller than this resolution. In memory devices currently manufactured on the mass production basis, the inter-gate spacing is in the order of 1.5 .mu.m. It has been necessary to provide this inter-gate spacing in order to electrically isolate adjacent floating gates, but the presence of such an inter-gate spacing is not desirable in terms of the existing need for a high density, high integrity memory device. Therefore, it is preferable if inter-gate spacing can be successfully eliminated without impairing the performance of the memory device.
USPTO Backgrounds
USPTO Backgrounds