This invention relates to a semiconductor integrated circuit device and also to a method for manufacturing the same. More particularly, the invention relates to a technique which is suitably applicable to semiconductor integrated circuit devices which include a DRAM (dynamic random access memory) provided with a memory cell having a stacked capacitor structure wherein an information storage capacitor is arranged above a MISFET for memory cell selection.
The recent DRAM with a great capacity usually has a stacked capacitor structure, wherein an information storage capacitor is arranged above a memory cell selection MISFET, in order to compensate for a storage charge reduction of an information storage capacitor as will be caused by the miniaturization of the memory cells.
The information storage capacitor having the stacked capacitor structure is formed by successively superposing a storage electrode (lower electrode), a capacity insulating film(dielectric film), and a plate electrode (upper electrode). The storage electrode of the information storage capacitor is connected with one of the semiconductor regions (source region, drain region) of a memory selection MISFET of the n channel type. The plate electrode is constituted as a common electrode for a plurality of memory cells and is supplied with a given fixed potential (plate potential).
The other semiconductor region (source region, drain region) of the memory cell selection MISFET is, in turn, connected to a bit line in order to permit data to be written in and read out. The bit line is provided between the MISFET for memory cell selection and the information storage capacitor or above the information storage capacitor. The structure wherein the information storage capacitor is provided above the bit lines is called a "capacitor over bitline" (COB) structure.
A DRAM having such a COB structure is described, for example, in Japanese Laid-open Patent Application No. 7-122654 (corresponding to a U. S. patent application Ser. No. 08/297,039, assigned to Hitachi Ltd.), and Japanese Laid-open Patent Application No. 7-106437.
The DRAM disclosed in the Japanese Laid-open Patent Application No. 7-122654 includes bit lines which are formed of a polysilicon film (or polycide film) formed above the MISFET for memory cell selection wherein a gate electrode (word line) is formed of a built-up film (polycide film) of a polysilicon film and a tungsten silicide (WSix) film. An information storage capacitor which includes a storage electrode formed of a polysilicon, a capacitance insulating film constituted of a built-up film of a silicon oxide film and a silicon nitride film, and a plate electrode formed of a polysilicon film are provided above the bit lines. In addition, a common source line made of a first layer made of an Al (aluminium) film and a word line for a shunt are formed over the information storage capacitor.
The DRAM set out in the Japanese Laid-open Patent Application No. 7-106437 includes bit lines made of a polysilicide film and formed on the MISFET for memory cell selection whose gate electrode (word line) is made of a polysilicon film. The storage electrode or plate electrode of the information storage capacitor disposed above the bit lines and the first interconnection layer of a peripheral circuit are both formed of a metal material (e.g. Pt). Thus, the step of forming the electrode of the information storage capacitor and the step of forming the metallic interconnection of the peripheral circuit are performed commonly to simplify the manufacturing process.
USPTO Backgrounds
USPTO Backgrounds