In the semiconductor industry, capacitors having linear capabilities are of critical importance for both digital and analog devices. Presently, two capacitors designs are commonly employed in CMOS technology.
Referring to FIG. 1, a first capacitor 10 known for its linear capabilities is shown. Capacitor 10 comprises a polysilicon top plate 12 and a heavily doped diffusion region forming a bottom plate 14 on a substrate 18. Both top and bottom plates are separated by a dielectric layer 16 comprising a gate oxide.
By the arrangement of the structure of FIG. 1, a capacitor having linear capabilities is formed. However, this configuration is substantially limited. First, capacitor 10 comprises a parasitic capacitance between the heavily doped diffusion region forming a bottom plate 14 and the substrate 18. This parasitic capacitance varies over the voltage applied. As such, the overall capacitance comprises a voltage dependent characteristic.
Referring to FIG. 2, a second capacitor 20 known for its linear capabilities is shown. Second capacitor 20 comprises a first and second conductive plate, 22 and 24, both formed superjacent a field oxide region 26. First and second conductive plate, 22 and 24, both preferably comprise polysilicon and are separated by a dielectric layer 28.
The structure of FIG. 2 overcomes some of the disadvantages of the device illustrated in FIG. 1. The impact of the parasitic effects of the configuration of capacitor 20 of FIG. 2 is diminished by positioning the bottom plate 24 over field oxide region 26, as opposed to substrate 18 of FIG. 1. By doing so, capacitor 20 comprises substantially reduced voltage dependent parasitic capacitance characteristics.
However, the capacitor structure of FIG. 2 is also limited. First, in order to fabricate capacitor 20, a double polysilicon process is needed to form both upper and lower plates 22 and 24. Second, the dielectric layer 28 is formed by depositing a thin silicon-dioxide layer. This also requires several additional steps beyond those required in the typical single polysilicon process.
Given the limitations of these known structures, there remains a need for a linear capable capacitor having substantially reduced voltage dependent parasitic capacitance characteristics. Further, a demand remains for a linear capable capacitor requiring few additional processing steps to achieve this reduction in voltage dependent parasitic capacitance.
USPTO Backgrounds
USPTO Backgrounds