Digitally controlled clock signal synthesizers are known. Systems known as arbitrary waveform generators include a source of a series of digital control signals representing the value of an output clock signal at that time. The rate at which the digital control signals are supplied is controlled by a system clock, which has a frequency generally substantially higher than that of the synthesized clock signal. These digital control signals are supplied to a digital-to-analog converter (DAC). The analog output signal from the DAC is low pass filtered and threshold detected. The output signal from the threshold detector is the synthesized clock signal.
For system clock periods when the synthesized clock signal is high, the digital signals have a maximum value, and for system clock periods when the synthesized clock signal is low, the digital signals have a minimum value. For system clock periods during which leading and trailing edges occur, the digital signals have intermediate values. The DAC generates an analog signal having levels corresponding to the values of the digital signals. For example, at a leading edge, the clock signal transitions from the minimum value of the preceding system clock cycle to the maximum value of the following system clock cycle. At the system clock period of a leading edge, a digital control signal having an intermediate value near the minimum value causes the low pass filtered analog signal to rise relatively slowly, so that signal crosses the threshold level relatively late. The leading edge, consequently, occurs relatively late in that system clock period. Conversely, a digital signal at an intermediate value near the maximum value causes the low pass filtered analog signal to rise relatively quickly, so that signal crosses the threshold level relatively early. In this case, the leading edge occurs relatively early in that system clock period. Trailing edges are placed in a similar manner. In this manner, a digital clock signal may be synthesized with leading and trailing edges placed at fractional locations within a system clock period.
Such a system can generate a synthesized clock signal having edges placed accurately with relatively high resolution. However, such a system requires a system clock frequency which is substantially higher than the frequency of the synthesized clock signal. Should a synthesized clock be required at a relatively high frequency, then such a system would require an extremely high frequency system clock signal, and a correspondingly high speed source of digital control signals, DAC, low pass filter, and threshold detector. Such high frequency components would be very expensive, or even technologically impossible.
Other techniques for providing synthesized clock signals having accurately placed edges with relatively high resolution, but not requiring high speed components have been developed. For example, U.S. Pat. No. 5,394,106, entitled APPARATUS AND METHOD FOR SYNTHESIS OF SIGNALS WITH PROGRAMMABLE PERIODS, issued Feb. 28, 1995 to Black et al., discloses such a system. The system disclosed in this patent includes a source of a series of digital control signals, a counter clocked by a system clock, a magnitude comparator, and a variable delay circuit. The digital control signals represent the time from the last generated edge to the next desired edge. One portion of each digital control signal represents the integer number of system clock cycles from the preceding edge to the desired time location of the next edge of the synthesized clock signal. A second portion of each digital control signal represents a fractional portion of a system clock cycle from the preceding edge to the desired time location of the next edge. The digital control signals are coupled through an accumulator to one input terminal of the magnitude comparator and the value from the counter is applied to the second input terminal of the magnitude comparator. The counter counts system clock cycles, and when the required number of clock cycles have been counted (i.e. when the desired count has been reached), the magnitude comparator produces a logical `1` signal to indicate a match. The fractional portion of the digital control signal, then, conditions the variable delay circuit to delay the logical `1` output signal from the magnitude comparator for the required portion of a system clock cycle. The delayed output signal from the variable delay circuit places an edge in the synthesize clock signal.
The system of U.S. Pat. No. 5,394,106 can place edges in a synthesized clock signal at a fractional resolution of the system clock cycle, without requiring the frequency of the system clock signal to be substantially higher than that of the synthesized clock signal. Instead, the frequency of the system clock signal need only be of the same order as the highest frequency desired in the synthesized clock signal. However, in systems such as the system of U.S. Pat. No. 5,394,106, a new digital control signal is requested from the digital control signal source in response to the `match` signal from the magnitude comparator, that is when the edge corresponding to the last digital control signal has been generated. Because such a system can be used, and is intended to be used, to generate a phase modulated synthesized clock signal (as for jitter response measurement), the requests for new digital control values occur at varying time periods. In other words, input digital control values are received asynchronously with respect to the system clock.
One skilled in the art will understand, however, first that synchronous digital systems are easier to design, implement, and integrate into other digital systems. The asynchronicity of the U.S. Pat. No. 5,394,106 system makes integrating such a system into a digital system difficult. Second, asynchronous systems make accurate filtering difficult to design and implement. Thus, a clock signal synthesizer which permits accurate and high resolution edge placement, without requiring a system clock having a frequency substantially higher than that of the synthesized clock signal, and which operates in a synchronous manner (i.e. receiving digital control signals synchronously with the system clock) is desirable.
Clock signal analyzers are also known. Such analyzers generate data representing the phase of the input clock signal. In a corresponding manner to the clock signal generator described above, one clock signal analyzer includes a counter which is started at one edge of the input clock signal, and stopped at the next edge. The counter is clocked by a system clock, and the count at the end of the counting period gives an indication of the time between the two edges.
The above method has the resolution of the system clock period. A method for achieving finer resolution includes two ramp generators for the purpose of achieving finer resolution than the system clock. Pulses are used to indicate the locations of edges in the clock signal being analyzed. A start pulse triggers a ramp generator which is constructed to traverse from a minimum voltage to a maximum voltage during a system clock period. This ramp generator continues until the beginning of the next system clock cycle. The value of the ramp signal at the start of the next system clock cycle is converted to a digital signal, and is an indication of the fraction of a clock cycle from the start pulse to the start of the next system clock cycle: a low value indicates that the start pulse occurred near the end of the system clock cycle and a high value indicates that the start pulse occurred just after the start of the system clock cycle. The start pulse also enables a counter which begins to count system clock cycles. A stop pulse disables the counter and triggers a second ramp generator. The second ramp generator operates in a similar manner to the first ramp generator and generates a digital value indicating the fraction of a system clock cycle from the stop pulse to the start of the next system clock cycle. The value of the second ramp generator is also converted to a digital value. The time duration between the start pulse and the stop pulse, thus, can be determined as the number of system clock cycles in the counter, plus the fraction of a clock cycle between the start pulse and the first full system clock cycle represented by the digital value of the first ramp generator, minus the fraction of the clock cycle between the stop pulse and the next full system clock cycle represented by the digital value of the second ramp generator.
It is not always necessary that each edge of a synthesized clock signal be specified, nor that the time of each edge of an input clock signal be analyzed. In some cases, it is sufficient that edge data be supplied, and edge timing data be received, at a lower rate than the rate of the edges in the synthesized or analyzed data signal.
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