Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, placement, and routing. When designing large systems to be implemented on large target devices, EDA tools may require a large amount of time to perform these compilation procedures.
When making changes to large systems, it is typically more common for designers to modify localized portions of a design rather than making radical changes to large portions of the system. When making such localized changes, it is undesirable to have to invest a large amount of time to re-compile the entire system which would include the unmodified portions of the design. It is also undesirable to have the EDA tool process the entire system from scratch because the designer may be satisfied with the results of unmodified portions of the system and re-processing the unmodified portions may change achieved timing results unfavorably due to the heuristic nature of CAD algorithms. This may result in requiring additional design iterations to be performed to achieve timing closure which could be costly.
USPTO Backgrounds
USPTO Backgrounds